drivers/net/mlx5/mlx5_flow_dv.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2018 Mellanox Technologies, Ltd
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdalign.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10
  11 #include <rte_common.h>
  12 #include <rte_ether.h>
  13 #include <rte_ethdev_driver.h>
  14 #include <rte_flow.h>
  15 #include <rte_flow_driver.h>
  16 #include <rte_malloc.h>
  17 #include <rte_cycles.h>
  18 #include <rte_ip.h>
  19 #include <rte_gre.h>
  20 #include <rte_vxlan.h>
  21 #include <rte_gtp.h>
  22 #include <rte_eal_paging.h>
  23 #include <rte_mpls.h>
  24
  25 #include <mlx5_glue.h>
  26 #include <mlx5_devx_cmds.h>
  27 #include <mlx5_prm.h>
  28 #include <mlx5_malloc.h>
  29
  30 #include "mlx5_defs.h"
  31 #include "mlx5.h"
  32 #include "mlx5_common_os.h"
  33 #include "mlx5_flow.h"
  34 #include "mlx5_flow_os.h"
  35 #include "mlx5_rxtx.h"
  36 #include "rte_pmd_mlx5.h"
  37
  38 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
  39
  40 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
  41 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
  42 #endif
  43
  44 #ifndef HAVE_MLX5DV_DR_ESWITCH
  45 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
  46 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
  47 #endif
  48 #endif
  49
  50 #ifndef HAVE_MLX5DV_DR
  51 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
  52 #endif
  53
  54 /* VLAN header definitions */
  55 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
  56 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
  57 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
  58 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
  59 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
  60
  61 union flow_dv_attr {
  62         struct {
  63                 uint32_t valid:1;
  64                 uint32_t ipv4:1;
  65                 uint32_t ipv6:1;
  66                 uint32_t tcp:1;
  67                 uint32_t udp:1;
  68                 uint32_t reserved:27;
  69         };
  70         uint32_t attr;
  71 };
  72
  73 static int
  74 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
  75                              struct mlx5_flow_tbl_resource *tbl);
  76
  77 static int
  78 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
  79                                       uint32_t encap_decap_idx);
  80
  81 static int
  82 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
  83                                         uint32_t port_id);
  84 static void
  85 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss);
  86
  87 /**
  88  * Initialize flow attributes structure according to flow items' types.
  89  *
  90  * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
  91  * mode. For tunnel mode, the items to be modified are the outermost ones.
  92  *
  93  * @param[in] item
  94  *   Pointer to item specification.
  95  * @param[out] attr
  96  *   Pointer to flow attributes structure.
  97  * @param[in] dev_flow
  98  *   Pointer to the sub flow.
  99  * @param[in] tunnel_decap
 100  *   Whether action is after tunnel decapsulation.
 101  */
 102 static void
 103 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
 104                   struct mlx5_flow *dev_flow, bool tunnel_decap)
 105 {
 106         uint64_t layers = dev_flow->handle->layers;
 107
 108         /*
 109          * If layers is already initialized, it means this dev_flow is the
 110          * suffix flow, the layers flags is set by the prefix flow. Need to
 111          * use the layer flags from prefix flow as the suffix flow may not
 112          * have the user defined items as the flow is split.
 113          */
 114         if (layers) {
 115                 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
 116                         attr->ipv4 = 1;
 117                 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
 118                         attr->ipv6 = 1;
 119                 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
 120                         attr->tcp = 1;
 121                 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
 122                         attr->udp = 1;
 123                 attr->valid = 1;
 124                 return;
 125         }
 126         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
 127                 uint8_t next_protocol = 0xff;
 128                 switch (item->type) {
 129                 case RTE_FLOW_ITEM_TYPE_GRE:
 130                 case RTE_FLOW_ITEM_TYPE_NVGRE:
 131                 case RTE_FLOW_ITEM_TYPE_VXLAN:
 132                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
 133                 case RTE_FLOW_ITEM_TYPE_GENEVE:
 134                 case RTE_FLOW_ITEM_TYPE_MPLS:
 135                         if (tunnel_decap)
 136                                 attr->attr = 0;
 137                         break;
 138                 case RTE_FLOW_ITEM_TYPE_IPV4:
 139                         if (!attr->ipv6)
 140                                 attr->ipv4 = 1;
 141                         if (item->mask != NULL &&
 142                             ((const struct rte_flow_item_ipv4 *)
 143                             item->mask)->hdr.next_proto_id)
 144                                 next_protocol =
 145                                     ((const struct rte_flow_item_ipv4 *)
 146                                       (item->spec))->hdr.next_proto_id &
 147                                     ((const struct rte_flow_item_ipv4 *)
 148                                       (item->mask))->hdr.next_proto_id;
 149                         if ((next_protocol == IPPROTO_IPIP ||
 150                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 151                                 attr->attr = 0;
 152                         break;
 153                 case RTE_FLOW_ITEM_TYPE_IPV6:
 154                         if (!attr->ipv4)
 155                                 attr->ipv6 = 1;
 156                         if (item->mask != NULL &&
 157                             ((const struct rte_flow_item_ipv6 *)
 158                             item->mask)->hdr.proto)
 159                                 next_protocol =
 160                                     ((const struct rte_flow_item_ipv6 *)
 161                                       (item->spec))->hdr.proto &
 162                                     ((const struct rte_flow_item_ipv6 *)
 163                                       (item->mask))->hdr.proto;
 164                         if ((next_protocol == IPPROTO_IPIP ||
 165                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 166                                 attr->attr = 0;
 167                         break;
 168                 case RTE_FLOW_ITEM_TYPE_UDP:
 169                         if (!attr->tcp)
 170                                 attr->udp = 1;
 171                         break;
 172                 case RTE_FLOW_ITEM_TYPE_TCP:
 173                         if (!attr->udp)
 174                                 attr->tcp = 1;
 175                         break;
 176                 default:
 177                         break;
 178                 }
 179         }
 180         attr->valid = 1;
 181 }
 182
 183 /**
 184  * Convert rte_mtr_color to mlx5 color.
 185  *
 186  * @param[in] rcol
 187  *   rte_mtr_color.
 188  *
 189  * @return
 190  *   mlx5 color.
 191  */
 192 static int
 193 rte_col_2_mlx5_col(enum rte_color rcol)
 194 {
 195         switch (rcol) {
 196         case RTE_COLOR_GREEN:
 197                 return MLX5_FLOW_COLOR_GREEN;
 198         case RTE_COLOR_YELLOW:
 199                 return MLX5_FLOW_COLOR_YELLOW;
 200         case RTE_COLOR_RED:
 201                 return MLX5_FLOW_COLOR_RED;
 202         default:
 203                 break;
 204         }
 205         return MLX5_FLOW_COLOR_UNDEFINED;
 206 }
 207
 208 struct field_modify_info {
 209         uint32_t size; /* Size of field in protocol header, in bytes. */
 210         uint32_t offset; /* Offset of field in protocol header, in bytes. */
 211         enum mlx5_modification_field id;
 212 };
 213
 214 struct field_modify_info modify_eth[] = {
 215         {4,  0, MLX5_MODI_OUT_DMAC_47_16},
 216         {2,  4, MLX5_MODI_OUT_DMAC_15_0},
 217         {4,  6, MLX5_MODI_OUT_SMAC_47_16},
 218         {2, 10, MLX5_MODI_OUT_SMAC_15_0},
 219         {0, 0, 0},
 220 };
 221
 222 struct field_modify_info modify_vlan_out_first_vid[] = {
 223         /* Size in bits !!! */
 224         {12, 0, MLX5_MODI_OUT_FIRST_VID},
 225         {0, 0, 0},
 226 };
 227
 228 struct field_modify_info modify_ipv4[] = {
 229         {1,  1, MLX5_MODI_OUT_IP_DSCP},
 230         {1,  8, MLX5_MODI_OUT_IPV4_TTL},
 231         {4, 12, MLX5_MODI_OUT_SIPV4},
 232         {4, 16, MLX5_MODI_OUT_DIPV4},
 233         {0, 0, 0},
 234 };
 235
 236 struct field_modify_info modify_ipv6[] = {
 237         {1,  0, MLX5_MODI_OUT_IP_DSCP},
 238         {1,  7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
 239         {4,  8, MLX5_MODI_OUT_SIPV6_127_96},
 240         {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
 241         {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
 242         {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
 243         {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
 244         {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
 245         {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
 246         {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
 247         {0, 0, 0},
 248 };
 249
 250 struct field_modify_info modify_udp[] = {
 251         {2, 0, MLX5_MODI_OUT_UDP_SPORT},
 252         {2, 2, MLX5_MODI_OUT_UDP_DPORT},
 253         {0, 0, 0},
 254 };
 255
 256 struct field_modify_info modify_tcp[] = {
 257         {2, 0, MLX5_MODI_OUT_TCP_SPORT},
 258         {2, 2, MLX5_MODI_OUT_TCP_DPORT},
 259         {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
 260         {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
 261         {0, 0, 0},
 262 };
 263
 264 static void
 265 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
 266                           uint8_t next_protocol, uint64_t *item_flags,
 267                           int *tunnel)
 268 {
 269         MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
 270                     item->type == RTE_FLOW_ITEM_TYPE_IPV6);
 271         if (next_protocol == IPPROTO_IPIP) {
 272                 *item_flags |= MLX5_FLOW_LAYER_IPIP;
 273                 *tunnel = 1;
 274         }
 275         if (next_protocol == IPPROTO_IPV6) {
 276                 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
 277                 *tunnel = 1;
 278         }
 279 }
 280
 281 /* Update VLAN's VID/PCP based on input rte_flow_action.
 282  *
 283  * @param[in] action
 284  *   Pointer to struct rte_flow_action.
 285  * @param[out] vlan
 286  *   Pointer to struct rte_vlan_hdr.
 287  */
 288 static void
 289 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
 290                          struct rte_vlan_hdr *vlan)
 291 {
 292         uint16_t vlan_tci;
 293         if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
 294                 vlan_tci =
 295                     ((const struct rte_flow_action_of_set_vlan_pcp *)
 296                                                action->conf)->vlan_pcp;
 297                 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
 298                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
 299                 vlan->vlan_tci |= vlan_tci;
 300         } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
 301                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
 302                 vlan->vlan_tci |= rte_be_to_cpu_16
 303                     (((const struct rte_flow_action_of_set_vlan_vid *)
 304                                              action->conf)->vlan_vid);
 305         }
 306 }
 307
 308 /**
 309  * Fetch 1, 2, 3 or 4 byte field from the byte array
 310  * and return as unsigned integer in host-endian format.
 311  *
 312  * @param[in] data
 313  *   Pointer to data array.
 314  * @param[in] size
 315  *   Size of field to extract.
 316  *
 317  * @return
 318  *   converted field in host endian format.
 319  */
 320 static inline uint32_t
 321 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
 322 {
 323         uint32_t ret;
 324
 325         switch (size) {
 326         case 1:
 327                 ret = *data;
 328                 break;
 329         case 2:
 330                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 331                 break;
 332         case 3:
 333                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 334                 ret = (ret << 8) | *(data + sizeof(uint16_t));
 335                 break;
 336         case 4:
 337                 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
 338                 break;
 339         default:
 340                 MLX5_ASSERT(false);
 341                 ret = 0;
 342                 break;
 343         }
 344         return ret;
 345 }
 346
 347 /**
 348  * Convert modify-header action to DV specification.
 349  *
 350  * Data length of each action is determined by provided field description
 351  * and the item mask. Data bit offset and width of each action is determined
 352  * by provided item mask.
 353  *
 354  * @param[in] item
 355  *   Pointer to item specification.
 356  * @param[in] field
 357  *   Pointer to field modification information.
 358  *     For MLX5_MODIFICATION_TYPE_SET specifies destination field.
 359  *     For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
 360  *     For MLX5_MODIFICATION_TYPE_COPY specifies source field.
 361  * @param[in] dcopy
 362  *   Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
 363  *   Negative offset value sets the same offset as source offset.
 364  *   size field is ignored, value is taken from source field.
 365  * @param[in,out] resource
 366  *   Pointer to the modify-header resource.
 367  * @param[in] type
 368  *   Type of modification.
 369  * @param[out] error
 370  *   Pointer to the error structure.
 371  *
 372  * @return
 373  *   0 on success, a negative errno value otherwise and rte_errno is set.
 374  */
 375 static int
 376 flow_dv_convert_modify_action(struct rte_flow_item *item,
 377                               struct field_modify_info *field,
 378                               struct field_modify_info *dcopy,
 379                               struct mlx5_flow_dv_modify_hdr_resource *resource,
 380                               uint32_t type, struct rte_flow_error *error)
 381 {
 382         uint32_t i = resource->actions_num;
 383         struct mlx5_modification_cmd *actions = resource->actions;
 384
 385         /*
 386          * The item and mask are provided in big-endian format.
 387          * The fields should be presented as in big-endian format either.
 388          * Mask must be always present, it defines the actual field width.
 389          */
 390         MLX5_ASSERT(item->mask);
 391         MLX5_ASSERT(field->size);
 392         do {
 393                 unsigned int size_b;
 394                 unsigned int off_b;
 395                 uint32_t mask;
 396                 uint32_t data;
 397
 398                 if (i >= MLX5_MAX_MODIFY_NUM)
 399                         return rte_flow_error_set(error, EINVAL,
 400                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 401                                  "too many items to modify");
 402                 /* Fetch variable byte size mask from the array. */
 403                 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
 404                                            field->offset, field->size);
 405                 if (!mask) {
 406                         ++field;
 407                         continue;
 408                 }
 409                 /* Deduce actual data width in bits from mask value. */
 410                 off_b = rte_bsf32(mask);
 411                 size_b = sizeof(uint32_t) * CHAR_BIT -
 412                          off_b - __builtin_clz(mask);
 413                 MLX5_ASSERT(size_b);
 414                 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
 415                 actions[i] = (struct mlx5_modification_cmd) {
 416                         .action_type = type,
 417                         .field = field->id,
 418                         .offset = off_b,
 419                         .length = size_b,
 420                 };
 421                 /* Convert entire record to expected big-endian format. */
 422                 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 423                 if (type == MLX5_MODIFICATION_TYPE_COPY) {
 424                         MLX5_ASSERT(dcopy);
 425                         actions[i].dst_field = dcopy->id;
 426                         actions[i].dst_offset =
 427                                 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
 428                         /* Convert entire record to big-endian format. */
 429                         actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
 430                 } else {
 431                         MLX5_ASSERT(item->spec);
 432                         data = flow_dv_fetch_field((const uint8_t *)item->spec +
 433                                                    field->offset, field->size);
 434                         /* Shift out the trailing masked bits from data. */
 435                         data = (data & mask) >> off_b;
 436                         actions[i].data1 = rte_cpu_to_be_32(data);
 437                 }
 438                 ++i;
 439                 ++field;
 440         } while (field->size);
 441         if (resource->actions_num == i)
 442                 return rte_flow_error_set(error, EINVAL,
 443                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 444                                           "invalid modification flow item");
 445         resource->actions_num = i;
 446         return 0;
 447 }
 448
 449 /**
 450  * Convert modify-header set IPv4 address action to DV specification.
 451  *
 452  * @param[in,out] resource
 453  *   Pointer to the modify-header resource.
 454  * @param[in] action
 455  *   Pointer to action specification.
 456  * @param[out] error
 457  *   Pointer to the error structure.
 458  *
 459  * @return
 460  *   0 on success, a negative errno value otherwise and rte_errno is set.
 461  */
 462 static int
 463 flow_dv_convert_action_modify_ipv4
 464                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 465                          const struct rte_flow_action *action,
 466                          struct rte_flow_error *error)
 467 {
 468         const struct rte_flow_action_set_ipv4 *conf =
 469                 (const struct rte_flow_action_set_ipv4 *)(action->conf);
 470         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
 471         struct rte_flow_item_ipv4 ipv4;
 472         struct rte_flow_item_ipv4 ipv4_mask;
 473
 474         memset(&ipv4, 0, sizeof(ipv4));
 475         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 476         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
 477                 ipv4.hdr.src_addr = conf->ipv4_addr;
 478                 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
 479         } else {
 480                 ipv4.hdr.dst_addr = conf->ipv4_addr;
 481                 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
 482         }
 483         item.spec = &ipv4;
 484         item.mask = &ipv4_mask;
 485         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
 486                                              MLX5_MODIFICATION_TYPE_SET, error);
 487 }
 488
 489 /**
 490  * Convert modify-header set IPv6 address action to DV specification.
 491  *
 492  * @param[in,out] resource
 493  *   Pointer to the modify-header resource.
 494  * @param[in] action
 495  *   Pointer to action specification.
 496  * @param[out] error
 497  *   Pointer to the error structure.
 498  *
 499  * @return
 500  *   0 on success, a negative errno value otherwise and rte_errno is set.
 501  */
 502 static int
 503 flow_dv_convert_action_modify_ipv6
 504                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 505                          const struct rte_flow_action *action,
 506                          struct rte_flow_error *error)
 507 {
 508         const struct rte_flow_action_set_ipv6 *conf =
 509                 (const struct rte_flow_action_set_ipv6 *)(action->conf);
 510         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
 511         struct rte_flow_item_ipv6 ipv6;
 512         struct rte_flow_item_ipv6 ipv6_mask;
 513
 514         memset(&ipv6, 0, sizeof(ipv6));
 515         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 516         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
 517                 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
 518                        sizeof(ipv6.hdr.src_addr));
 519                 memcpy(&ipv6_mask.hdr.src_addr,
 520                        &rte_flow_item_ipv6_mask.hdr.src_addr,
 521                        sizeof(ipv6.hdr.src_addr));
 522         } else {
 523                 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
 524                        sizeof(ipv6.hdr.dst_addr));
 525                 memcpy(&ipv6_mask.hdr.dst_addr,
 526                        &rte_flow_item_ipv6_mask.hdr.dst_addr,
 527                        sizeof(ipv6.hdr.dst_addr));
 528         }
 529         item.spec = &ipv6;
 530         item.mask = &ipv6_mask;
 531         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
 532                                              MLX5_MODIFICATION_TYPE_SET, error);
 533 }
 534
 535 /**
 536  * Convert modify-header set MAC address action to DV specification.
 537  *
 538  * @param[in,out] resource
 539  *   Pointer to the modify-header resource.
 540  * @param[in] action
 541  *   Pointer to action specification.
 542  * @param[out] error
 543  *   Pointer to the error structure.
 544  *
 545  * @return
 546  *   0 on success, a negative errno value otherwise and rte_errno is set.
 547  */
 548 static int
 549 flow_dv_convert_action_modify_mac
 550                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 551                          const struct rte_flow_action *action,
 552                          struct rte_flow_error *error)
 553 {
 554         const struct rte_flow_action_set_mac *conf =
 555                 (const struct rte_flow_action_set_mac *)(action->conf);
 556         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
 557         struct rte_flow_item_eth eth;
 558         struct rte_flow_item_eth eth_mask;
 559
 560         memset(&eth, 0, sizeof(eth));
 561         memset(&eth_mask, 0, sizeof(eth_mask));
 562         if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
 563                 memcpy(&eth.src.addr_bytes, &conf->mac_addr,
 564                        sizeof(eth.src.addr_bytes));
 565                 memcpy(&eth_mask.src.addr_bytes,
 566                        &rte_flow_item_eth_mask.src.addr_bytes,
 567                        sizeof(eth_mask.src.addr_bytes));
 568         } else {
 569                 memcpy(&eth.dst.addr_bytes, &conf->mac_addr,
 570                        sizeof(eth.dst.addr_bytes));
 571                 memcpy(&eth_mask.dst.addr_bytes,
 572                        &rte_flow_item_eth_mask.dst.addr_bytes,
 573                        sizeof(eth_mask.dst.addr_bytes));
 574         }
 575         item.spec = &eth;
 576         item.mask = &eth_mask;
 577         return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
 578                                              MLX5_MODIFICATION_TYPE_SET, error);
 579 }
 580
 581 /**
 582  * Convert modify-header set VLAN VID action to DV specification.
 583  *
 584  * @param[in,out] resource
 585  *   Pointer to the modify-header resource.
 586  * @param[in] action
 587  *   Pointer to action specification.
 588  * @param[out] error
 589  *   Pointer to the error structure.
 590  *
 591  * @return
 592  *   0 on success, a negative errno value otherwise and rte_errno is set.
 593  */
 594 static int
 595 flow_dv_convert_action_modify_vlan_vid
 596                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 597                          const struct rte_flow_action *action,
 598                          struct rte_flow_error *error)
 599 {
 600         const struct rte_flow_action_of_set_vlan_vid *conf =
 601                 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
 602         int i = resource->actions_num;
 603         struct mlx5_modification_cmd *actions = resource->actions;
 604         struct field_modify_info *field = modify_vlan_out_first_vid;
 605
 606         if (i >= MLX5_MAX_MODIFY_NUM)
 607                 return rte_flow_error_set(error, EINVAL,
 608                          RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 609                          "too many items to modify");
 610         actions[i] = (struct mlx5_modification_cmd) {
 611                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 612                 .field = field->id,
 613                 .length = field->size,
 614                 .offset = field->offset,
 615         };
 616         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 617         actions[i].data1 = conf->vlan_vid;
 618         actions[i].data1 = actions[i].data1 << 16;
 619         resource->actions_num = ++i;
 620         return 0;
 621 }
 622
 623 /**
 624  * Convert modify-header set TP action to DV specification.
 625  *
 626  * @param[in,out] resource
 627  *   Pointer to the modify-header resource.
 628  * @param[in] action
 629  *   Pointer to action specification.
 630  * @param[in] items
 631  *   Pointer to rte_flow_item objects list.
 632  * @param[in] attr
 633  *   Pointer to flow attributes structure.
 634  * @param[in] dev_flow
 635  *   Pointer to the sub flow.
 636  * @param[in] tunnel_decap
 637  *   Whether action is after tunnel decapsulation.
 638  * @param[out] error
 639  *   Pointer to the error structure.
 640  *
 641  * @return
 642  *   0 on success, a negative errno value otherwise and rte_errno is set.
 643  */
 644 static int
 645 flow_dv_convert_action_modify_tp
 646                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 647                          const struct rte_flow_action *action,
 648                          const struct rte_flow_item *items,
 649                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 650                          bool tunnel_decap, struct rte_flow_error *error)
 651 {
 652         const struct rte_flow_action_set_tp *conf =
 653                 (const struct rte_flow_action_set_tp *)(action->conf);
 654         struct rte_flow_item item;
 655         struct rte_flow_item_udp udp;
 656         struct rte_flow_item_udp udp_mask;
 657         struct rte_flow_item_tcp tcp;
 658         struct rte_flow_item_tcp tcp_mask;
 659         struct field_modify_info *field;
 660
 661         if (!attr->valid)
 662                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 663         if (attr->udp) {
 664                 memset(&udp, 0, sizeof(udp));
 665                 memset(&udp_mask, 0, sizeof(udp_mask));
 666                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 667                         udp.hdr.src_port = conf->port;
 668                         udp_mask.hdr.src_port =
 669                                         rte_flow_item_udp_mask.hdr.src_port;
 670                 } else {
 671                         udp.hdr.dst_port = conf->port;
 672                         udp_mask.hdr.dst_port =
 673                                         rte_flow_item_udp_mask.hdr.dst_port;
 674                 }
 675                 item.type = RTE_FLOW_ITEM_TYPE_UDP;
 676                 item.spec = &udp;
 677                 item.mask = &udp_mask;
 678                 field = modify_udp;
 679         } else {
 680                 MLX5_ASSERT(attr->tcp);
 681                 memset(&tcp, 0, sizeof(tcp));
 682                 memset(&tcp_mask, 0, sizeof(tcp_mask));
 683                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 684                         tcp.hdr.src_port = conf->port;
 685                         tcp_mask.hdr.src_port =
 686                                         rte_flow_item_tcp_mask.hdr.src_port;
 687                 } else {
 688                         tcp.hdr.dst_port = conf->port;
 689                         tcp_mask.hdr.dst_port =
 690                                         rte_flow_item_tcp_mask.hdr.dst_port;
 691                 }
 692                 item.type = RTE_FLOW_ITEM_TYPE_TCP;
 693                 item.spec = &tcp;
 694                 item.mask = &tcp_mask;
 695                 field = modify_tcp;
 696         }
 697         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 698                                              MLX5_MODIFICATION_TYPE_SET, error);
 699 }
 700
 701 /**
 702  * Convert modify-header set TTL action to DV specification.
 703  *
 704  * @param[in,out] resource
 705  *   Pointer to the modify-header resource.
 706  * @param[in] action
 707  *   Pointer to action specification.
 708  * @param[in] items
 709  *   Pointer to rte_flow_item objects list.
 710  * @param[in] attr
 711  *   Pointer to flow attributes structure.
 712  * @param[in] dev_flow
 713  *   Pointer to the sub flow.
 714  * @param[in] tunnel_decap
 715  *   Whether action is after tunnel decapsulation.
 716  * @param[out] error
 717  *   Pointer to the error structure.
 718  *
 719  * @return
 720  *   0 on success, a negative errno value otherwise and rte_errno is set.
 721  */
 722 static int
 723 flow_dv_convert_action_modify_ttl
 724                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 725                          const struct rte_flow_action *action,
 726                          const struct rte_flow_item *items,
 727                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 728                          bool tunnel_decap, struct rte_flow_error *error)
 729 {
 730         const struct rte_flow_action_set_ttl *conf =
 731                 (const struct rte_flow_action_set_ttl *)(action->conf);
 732         struct rte_flow_item item;
 733         struct rte_flow_item_ipv4 ipv4;
 734         struct rte_flow_item_ipv4 ipv4_mask;
 735         struct rte_flow_item_ipv6 ipv6;
 736         struct rte_flow_item_ipv6 ipv6_mask;
 737         struct field_modify_info *field;
 738
 739         if (!attr->valid)
 740                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 741         if (attr->ipv4) {
 742                 memset(&ipv4, 0, sizeof(ipv4));
 743                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 744                 ipv4.hdr.time_to_live = conf->ttl_value;
 745                 ipv4_mask.hdr.time_to_live = 0xFF;
 746                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 747                 item.spec = &ipv4;
 748                 item.mask = &ipv4_mask;
 749                 field = modify_ipv4;
 750         } else {
 751                 MLX5_ASSERT(attr->ipv6);
 752                 memset(&ipv6, 0, sizeof(ipv6));
 753                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 754                 ipv6.hdr.hop_limits = conf->ttl_value;
 755                 ipv6_mask.hdr.hop_limits = 0xFF;
 756                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 757                 item.spec = &ipv6;
 758                 item.mask = &ipv6_mask;
 759                 field = modify_ipv6;
 760         }
 761         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 762                                              MLX5_MODIFICATION_TYPE_SET, error);
 763 }
 764
 765 /**
 766  * Convert modify-header decrement TTL action to DV specification.
 767  *
 768  * @param[in,out] resource
 769  *   Pointer to the modify-header resource.
 770  * @param[in] action
 771  *   Pointer to action specification.
 772  * @param[in] items
 773  *   Pointer to rte_flow_item objects list.
 774  * @param[in] attr
 775  *   Pointer to flow attributes structure.
 776  * @param[in] dev_flow
 777  *   Pointer to the sub flow.
 778  * @param[in] tunnel_decap
 779  *   Whether action is after tunnel decapsulation.
 780  * @param[out] error
 781  *   Pointer to the error structure.
 782  *
 783  * @return
 784  *   0 on success, a negative errno value otherwise and rte_errno is set.
 785  */
 786 static int
 787 flow_dv_convert_action_modify_dec_ttl
 788                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 789                          const struct rte_flow_item *items,
 790                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 791                          bool tunnel_decap, struct rte_flow_error *error)
 792 {
 793         struct rte_flow_item item;
 794         struct rte_flow_item_ipv4 ipv4;
 795         struct rte_flow_item_ipv4 ipv4_mask;
 796         struct rte_flow_item_ipv6 ipv6;
 797         struct rte_flow_item_ipv6 ipv6_mask;
 798         struct field_modify_info *field;
 799
 800         if (!attr->valid)
 801                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 802         if (attr->ipv4) {
 803                 memset(&ipv4, 0, sizeof(ipv4));
 804                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 805                 ipv4.hdr.time_to_live = 0xFF;
 806                 ipv4_mask.hdr.time_to_live = 0xFF;
 807                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 808                 item.spec = &ipv4;
 809                 item.mask = &ipv4_mask;
 810                 field = modify_ipv4;
 811         } else {
 812                 MLX5_ASSERT(attr->ipv6);
 813                 memset(&ipv6, 0, sizeof(ipv6));
 814                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 815                 ipv6.hdr.hop_limits = 0xFF;
 816                 ipv6_mask.hdr.hop_limits = 0xFF;
 817                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 818                 item.spec = &ipv6;
 819                 item.mask = &ipv6_mask;
 820                 field = modify_ipv6;
 821         }
 822         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 823                                              MLX5_MODIFICATION_TYPE_ADD, error);
 824 }
 825
 826 /**
 827  * Convert modify-header increment/decrement TCP Sequence number
 828  * to DV specification.
 829  *
 830  * @param[in,out] resource
 831  *   Pointer to the modify-header resource.
 832  * @param[in] action
 833  *   Pointer to action specification.
 834  * @param[out] error
 835  *   Pointer to the error structure.
 836  *
 837  * @return
 838  *   0 on success, a negative errno value otherwise and rte_errno is set.
 839  */
 840 static int
 841 flow_dv_convert_action_modify_tcp_seq
 842                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 843                          const struct rte_flow_action *action,
 844                          struct rte_flow_error *error)
 845 {
 846         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 847         uint64_t value = rte_be_to_cpu_32(*conf);
 848         struct rte_flow_item item;
 849         struct rte_flow_item_tcp tcp;
 850         struct rte_flow_item_tcp tcp_mask;
 851
 852         memset(&tcp, 0, sizeof(tcp));
 853         memset(&tcp_mask, 0, sizeof(tcp_mask));
 854         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
 855                 /*
 856                  * The HW has no decrement operation, only increment operation.
 857                  * To simulate decrement X from Y using increment operation
 858                  * we need to add UINT32_MAX X times to Y.
 859                  * Each adding of UINT32_MAX decrements Y by 1.
 860                  */
 861                 value *= UINT32_MAX;
 862         tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
 863         tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
 864         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 865         item.spec = &tcp;
 866         item.mask = &tcp_mask;
 867         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 868                                              MLX5_MODIFICATION_TYPE_ADD, error);
 869 }
 870
 871 /**
 872  * Convert modify-header increment/decrement TCP Acknowledgment number
 873  * to DV specification.
 874  *
 875  * @param[in,out] resource
 876  *   Pointer to the modify-header resource.
 877  * @param[in] action
 878  *   Pointer to action specification.
 879  * @param[out] error
 880  *   Pointer to the error structure.
 881  *
 882  * @return
 883  *   0 on success, a negative errno value otherwise and rte_errno is set.
 884  */
 885 static int
 886 flow_dv_convert_action_modify_tcp_ack
 887                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 888                          const struct rte_flow_action *action,
 889                          struct rte_flow_error *error)
 890 {
 891         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 892         uint64_t value = rte_be_to_cpu_32(*conf);
 893         struct rte_flow_item item;
 894         struct rte_flow_item_tcp tcp;
 895         struct rte_flow_item_tcp tcp_mask;
 896
 897         memset(&tcp, 0, sizeof(tcp));
 898         memset(&tcp_mask, 0, sizeof(tcp_mask));
 899         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
 900                 /*
 901                  * The HW has no decrement operation, only increment operation.
 902                  * To simulate decrement X from Y using increment operation
 903                  * we need to add UINT32_MAX X times to Y.
 904                  * Each adding of UINT32_MAX decrements Y by 1.
 905                  */
 906                 value *= UINT32_MAX;
 907         tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
 908         tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
 909         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 910         item.spec = &tcp;
 911         item.mask = &tcp_mask;
 912         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 913                                              MLX5_MODIFICATION_TYPE_ADD, error);
 914 }
 915
 916 static enum mlx5_modification_field reg_to_field[] = {
 917         [REG_NON] = MLX5_MODI_OUT_NONE,
 918         [REG_A] = MLX5_MODI_META_DATA_REG_A,
 919         [REG_B] = MLX5_MODI_META_DATA_REG_B,
 920         [REG_C_0] = MLX5_MODI_META_REG_C_0,
 921         [REG_C_1] = MLX5_MODI_META_REG_C_1,
 922         [REG_C_2] = MLX5_MODI_META_REG_C_2,
 923         [REG_C_3] = MLX5_MODI_META_REG_C_3,
 924         [REG_C_4] = MLX5_MODI_META_REG_C_4,
 925         [REG_C_5] = MLX5_MODI_META_REG_C_5,
 926         [REG_C_6] = MLX5_MODI_META_REG_C_6,
 927         [REG_C_7] = MLX5_MODI_META_REG_C_7,
 928 };
 929
 930 /**
 931  * Convert register set to DV specification.
 932  *
 933  * @param[in,out] resource
 934  *   Pointer to the modify-header resource.
 935  * @param[in] action
 936  *   Pointer to action specification.
 937  * @param[out] error
 938  *   Pointer to the error structure.
 939  *
 940  * @return
 941  *   0 on success, a negative errno value otherwise and rte_errno is set.
 942  */
 943 static int
 944 flow_dv_convert_action_set_reg
 945                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 946                          const struct rte_flow_action *action,
 947                          struct rte_flow_error *error)
 948 {
 949         const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
 950         struct mlx5_modification_cmd *actions = resource->actions;
 951         uint32_t i = resource->actions_num;
 952
 953         if (i >= MLX5_MAX_MODIFY_NUM)
 954                 return rte_flow_error_set(error, EINVAL,
 955                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 956                                           "too many items to modify");
 957         MLX5_ASSERT(conf->id != REG_NON);
 958         MLX5_ASSERT(conf->id < RTE_DIM(reg_to_field));
 959         actions[i] = (struct mlx5_modification_cmd) {
 960                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 961                 .field = reg_to_field[conf->id],
 962         };
 963         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 964         actions[i].data1 = rte_cpu_to_be_32(conf->data);
 965         ++i;
 966         resource->actions_num = i;
 967         return 0;
 968 }
 969
 970 /**
 971  * Convert SET_TAG action to DV specification.
 972  *
 973  * @param[in] dev
 974  *   Pointer to the rte_eth_dev structure.
 975  * @param[in,out] resource
 976  *   Pointer to the modify-header resource.
 977  * @param[in] conf
 978  *   Pointer to action specification.
 979  * @param[out] error
 980  *   Pointer to the error structure.
 981  *
 982  * @return
 983  *   0 on success, a negative errno value otherwise and rte_errno is set.
 984  */
 985 static int
 986 flow_dv_convert_action_set_tag
 987                         (struct rte_eth_dev *dev,
 988                          struct mlx5_flow_dv_modify_hdr_resource *resource,
 989                          const struct rte_flow_action_set_tag *conf,
 990                          struct rte_flow_error *error)
 991 {
 992         rte_be32_t data = rte_cpu_to_be_32(conf->data);
 993         rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
 994         struct rte_flow_item item = {
 995                 .spec = &data,
 996                 .mask = &mask,
 997         };
 998         struct field_modify_info reg_c_x[] = {
 999                 [1] = {0, 0, 0},
1000         };
1001         enum mlx5_modification_field reg_type;
1002         int ret;
1003
1004         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1005         if (ret < 0)
1006                 return ret;
1007         MLX5_ASSERT(ret != REG_NON);
1008         MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1009         reg_type = reg_to_field[ret];
1010         MLX5_ASSERT(reg_type > 0);
1011         reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1012         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1013                                              MLX5_MODIFICATION_TYPE_SET, error);
1014 }
1015
1016 /**
1017  * Convert internal COPY_REG action to DV specification.
1018  *
1019  * @param[in] dev
1020  *   Pointer to the rte_eth_dev structure.
1021  * @param[in,out] res
1022  *   Pointer to the modify-header resource.
1023  * @param[in] action
1024  *   Pointer to action specification.
1025  * @param[out] error
1026  *   Pointer to the error structure.
1027  *
1028  * @return
1029  *   0 on success, a negative errno value otherwise and rte_errno is set.
1030  */
1031 static int
1032 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1033                                  struct mlx5_flow_dv_modify_hdr_resource *res,
1034                                  const struct rte_flow_action *action,
1035                                  struct rte_flow_error *error)
1036 {
1037         const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1038         rte_be32_t mask = RTE_BE32(UINT32_MAX);
1039         struct rte_flow_item item = {
1040                 .spec = NULL,
1041                 .mask = &mask,
1042         };
1043         struct field_modify_info reg_src[] = {
1044                 {4, 0, reg_to_field[conf->src]},
1045                 {0, 0, 0},
1046         };
1047         struct field_modify_info reg_dst = {
1048                 .offset = 0,
1049                 .id = reg_to_field[conf->dst],
1050         };
1051         /* Adjust reg_c[0] usage according to reported mask. */
1052         if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1053                 struct mlx5_priv *priv = dev->data->dev_private;
1054                 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1055
1056                 MLX5_ASSERT(reg_c0);
1057                 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1058                 if (conf->dst == REG_C_0) {
1059                         /* Copy to reg_c[0], within mask only. */
1060                         reg_dst.offset = rte_bsf32(reg_c0);
1061                         /*
1062                          * Mask is ignoring the enianness, because
1063                          * there is no conversion in datapath.
1064                          */
1065 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1066                         /* Copy from destination lower bits to reg_c[0]. */
1067                         mask = reg_c0 >> reg_dst.offset;
1068 #else
1069                         /* Copy from destination upper bits to reg_c[0]. */
1070                         mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1071                                           rte_fls_u32(reg_c0));
1072 #endif
1073                 } else {
1074                         mask = rte_cpu_to_be_32(reg_c0);
1075 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1076                         /* Copy from reg_c[0] to destination lower bits. */
1077                         reg_dst.offset = 0;
1078 #else
1079                         /* Copy from reg_c[0] to destination upper bits. */
1080                         reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1081                                          (rte_fls_u32(reg_c0) -
1082                                           rte_bsf32(reg_c0));
1083 #endif
1084                 }
1085         }
1086         return flow_dv_convert_modify_action(&item,
1087                                              reg_src, &reg_dst, res,
1088                                              MLX5_MODIFICATION_TYPE_COPY,
1089                                              error);
1090 }
1091
1092 /**
1093  * Convert MARK action to DV specification. This routine is used
1094  * in extensive metadata only and requires metadata register to be
1095  * handled. In legacy mode hardware tag resource is engaged.
1096  *
1097  * @param[in] dev
1098  *   Pointer to the rte_eth_dev structure.
1099  * @param[in] conf
1100  *   Pointer to MARK action specification.
1101  * @param[in,out] resource
1102  *   Pointer to the modify-header resource.
1103  * @param[out] error
1104  *   Pointer to the error structure.
1105  *
1106  * @return
1107  *   0 on success, a negative errno value otherwise and rte_errno is set.
1108  */
1109 static int
1110 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1111                             const struct rte_flow_action_mark *conf,
1112                             struct mlx5_flow_dv_modify_hdr_resource *resource,
1113                             struct rte_flow_error *error)
1114 {
1115         struct mlx5_priv *priv = dev->data->dev_private;
1116         rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1117                                            priv->sh->dv_mark_mask);
1118         rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1119         struct rte_flow_item item = {
1120                 .spec = &data,
1121                 .mask = &mask,
1122         };
1123         struct field_modify_info reg_c_x[] = {
1124                 [1] = {0, 0, 0},
1125         };
1126         int reg;
1127
1128         if (!mask)
1129                 return rte_flow_error_set(error, EINVAL,
1130                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1131                                           NULL, "zero mark action mask");
1132         reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1133         if (reg < 0)
1134                 return reg;
1135         MLX5_ASSERT(reg > 0);
1136         if (reg == REG_C_0) {
1137                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1138                 uint32_t shl_c0 = rte_bsf32(msk_c0);
1139
1140                 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1141                 mask = rte_cpu_to_be_32(mask) & msk_c0;
1142                 mask = rte_cpu_to_be_32(mask << shl_c0);
1143         }
1144         reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1145         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1146                                              MLX5_MODIFICATION_TYPE_SET, error);
1147 }
1148
1149 /**
1150  * Get metadata register index for specified steering domain.
1151  *
1152  * @param[in] dev
1153  *   Pointer to the rte_eth_dev structure.
1154  * @param[in] attr
1155  *   Attributes of flow to determine steering domain.
1156  * @param[out] error
1157  *   Pointer to the error structure.
1158  *
1159  * @return
1160  *   positive index on success, a negative errno value otherwise
1161  *   and rte_errno is set.
1162  */
1163 static enum modify_reg
1164 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1165                          const struct rte_flow_attr *attr,
1166                          struct rte_flow_error *error)
1167 {
1168         int reg =
1169                 mlx5_flow_get_reg_id(dev, attr->transfer ?
1170                                           MLX5_METADATA_FDB :
1171                                             attr->egress ?
1172                                             MLX5_METADATA_TX :
1173                                             MLX5_METADATA_RX, 0, error);
1174         if (reg < 0)
1175                 return rte_flow_error_set(error,
1176                                           ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1177                                           NULL, "unavailable "
1178                                           "metadata register");
1179         return reg;
1180 }
1181
1182 /**
1183  * Convert SET_META action to DV specification.
1184  *
1185  * @param[in] dev
1186  *   Pointer to the rte_eth_dev structure.
1187  * @param[in,out] resource
1188  *   Pointer to the modify-header resource.
1189  * @param[in] attr
1190  *   Attributes of flow that includes this item.
1191  * @param[in] conf
1192  *   Pointer to action specification.
1193  * @param[out] error
1194  *   Pointer to the error structure.
1195  *
1196  * @return
1197  *   0 on success, a negative errno value otherwise and rte_errno is set.
1198  */
1199 static int
1200 flow_dv_convert_action_set_meta
1201                         (struct rte_eth_dev *dev,
1202                          struct mlx5_flow_dv_modify_hdr_resource *resource,
1203                          const struct rte_flow_attr *attr,
1204                          const struct rte_flow_action_set_meta *conf,
1205                          struct rte_flow_error *error)
1206 {
1207         uint32_t data = conf->data;
1208         uint32_t mask = conf->mask;
1209         struct rte_flow_item item = {
1210                 .spec = &data,
1211                 .mask = &mask,
1212         };
1213         struct field_modify_info reg_c_x[] = {
1214                 [1] = {0, 0, 0},
1215         };
1216         int reg = flow_dv_get_metadata_reg(dev, attr, error);
1217
1218         if (reg < 0)
1219                 return reg;
1220         /*
1221          * In datapath code there is no endianness
1222          * coversions for perfromance reasons, all
1223          * pattern conversions are done in rte_flow.
1224          */
1225         if (reg == REG_C_0) {
1226                 struct mlx5_priv *priv = dev->data->dev_private;
1227                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1228                 uint32_t shl_c0;
1229
1230                 MLX5_ASSERT(msk_c0);
1231 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1232                 shl_c0 = rte_bsf32(msk_c0);
1233 #else
1234                 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1235 #endif
1236                 mask <<= shl_c0;
1237                 data <<= shl_c0;
1238                 MLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1239         }
1240         reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1241         /* The routine expects parameters in memory as big-endian ones. */
1242         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1243                                              MLX5_MODIFICATION_TYPE_SET, error);
1244 }
1245
1246 /**
1247  * Convert modify-header set IPv4 DSCP action to DV specification.
1248  *
1249  * @param[in,out] resource
1250  *   Pointer to the modify-header resource.
1251  * @param[in] action
1252  *   Pointer to action specification.
1253  * @param[out] error
1254  *   Pointer to the error structure.
1255  *
1256  * @return
1257  *   0 on success, a negative errno value otherwise and rte_errno is set.
1258  */
1259 static int
1260 flow_dv_convert_action_modify_ipv4_dscp
1261                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1262                          const struct rte_flow_action *action,
1263                          struct rte_flow_error *error)
1264 {
1265         const struct rte_flow_action_set_dscp *conf =
1266                 (const struct rte_flow_action_set_dscp *)(action->conf);
1267         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1268         struct rte_flow_item_ipv4 ipv4;
1269         struct rte_flow_item_ipv4 ipv4_mask;
1270
1271         memset(&ipv4, 0, sizeof(ipv4));
1272         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1273         ipv4.hdr.type_of_service = conf->dscp;
1274         ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1275         item.spec = &ipv4;
1276         item.mask = &ipv4_mask;
1277         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1278                                              MLX5_MODIFICATION_TYPE_SET, error);
1279 }
1280
1281 /**
1282  * Convert modify-header set IPv6 DSCP action to DV specification.
1283  *
1284  * @param[in,out] resource
1285  *   Pointer to the modify-header resource.
1286  * @param[in] action
1287  *   Pointer to action specification.
1288  * @param[out] error
1289  *   Pointer to the error structure.
1290  *
1291  * @return
1292  *   0 on success, a negative errno value otherwise and rte_errno is set.
1293  */
1294 static int
1295 flow_dv_convert_action_modify_ipv6_dscp
1296                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1297                          const struct rte_flow_action *action,
1298                          struct rte_flow_error *error)
1299 {
1300         const struct rte_flow_action_set_dscp *conf =
1301                 (const struct rte_flow_action_set_dscp *)(action->conf);
1302         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1303         struct rte_flow_item_ipv6 ipv6;
1304         struct rte_flow_item_ipv6 ipv6_mask;
1305
1306         memset(&ipv6, 0, sizeof(ipv6));
1307         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1308         /*
1309          * Even though the DSCP bits offset of IPv6 is not byte aligned,
1310          * rdma-core only accept the DSCP bits byte aligned start from
1311          * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1312          * bits in IPv6 case as rdma-core requires byte aligned value.
1313          */
1314         ipv6.hdr.vtc_flow = conf->dscp;
1315         ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1316         item.spec = &ipv6;
1317         item.mask = &ipv6_mask;
1318         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1319                                              MLX5_MODIFICATION_TYPE_SET, error);
1320 }
1321
1322 /**
1323  * Validate MARK item.
1324  *
1325  * @param[in] dev
1326  *   Pointer to the rte_eth_dev structure.
1327  * @param[in] item
1328  *   Item specification.
1329  * @param[in] attr
1330  *   Attributes of flow that includes this item.
1331  * @param[out] error
1332  *   Pointer to error structure.
1333  *
1334  * @return
1335  *   0 on success, a negative errno value otherwise and rte_errno is set.
1336  */
1337 static int
1338 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1339                            const struct rte_flow_item *item,
1340                            const struct rte_flow_attr *attr __rte_unused,
1341                            struct rte_flow_error *error)
1342 {
1343         struct mlx5_priv *priv = dev->data->dev_private;
1344         struct mlx5_dev_config *config = &priv->config;
1345         const struct rte_flow_item_mark *spec = item->spec;
1346         const struct rte_flow_item_mark *mask = item->mask;
1347         const struct rte_flow_item_mark nic_mask = {
1348                 .id = priv->sh->dv_mark_mask,
1349         };
1350         int ret;
1351
1352         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1353                 return rte_flow_error_set(error, ENOTSUP,
1354                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1355                                           "extended metadata feature"
1356                                           " isn't enabled");
1357         if (!mlx5_flow_ext_mreg_supported(dev))
1358                 return rte_flow_error_set(error, ENOTSUP,
1359                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1360                                           "extended metadata register"
1361                                           " isn't supported");
1362         if (!nic_mask.id)
1363                 return rte_flow_error_set(error, ENOTSUP,
1364                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1365                                           "extended metadata register"
1366                                           " isn't available");
1367         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1368         if (ret < 0)
1369                 return ret;
1370         if (!spec)
1371                 return rte_flow_error_set(error, EINVAL,
1372                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1373                                           item->spec,
1374                                           "data cannot be empty");
1375         if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1376                 return rte_flow_error_set(error, EINVAL,
1377                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1378                                           &spec->id,
1379                                           "mark id exceeds the limit");
1380         if (!mask)
1381                 mask = &nic_mask;
1382         if (!mask->id)
1383                 return rte_flow_error_set(error, EINVAL,
1384                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1385                                         "mask cannot be zero");
1386
1387         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1388                                         (const uint8_t *)&nic_mask,
1389                                         sizeof(struct rte_flow_item_mark),
1390                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1391         if (ret < 0)
1392                 return ret;
1393         return 0;
1394 }
1395
1396 /**
1397  * Validate META item.
1398  *
1399  * @param[in] dev
1400  *   Pointer to the rte_eth_dev structure.
1401  * @param[in] item
1402  *   Item specification.
1403  * @param[in] attr
1404  *   Attributes of flow that includes this item.
1405  * @param[out] error
1406  *   Pointer to error structure.
1407  *
1408  * @return
1409  *   0 on success, a negative errno value otherwise and rte_errno is set.
1410  */
1411 static int
1412 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1413                            const struct rte_flow_item *item,
1414                            const struct rte_flow_attr *attr,
1415                            struct rte_flow_error *error)
1416 {
1417         struct mlx5_priv *priv = dev->data->dev_private;
1418         struct mlx5_dev_config *config = &priv->config;
1419         const struct rte_flow_item_meta *spec = item->spec;
1420         const struct rte_flow_item_meta *mask = item->mask;
1421         struct rte_flow_item_meta nic_mask = {
1422                 .data = UINT32_MAX
1423         };
1424         int reg;
1425         int ret;
1426
1427         if (!spec)
1428                 return rte_flow_error_set(error, EINVAL,
1429                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1430                                           item->spec,
1431                                           "data cannot be empty");
1432         if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1433                 if (!mlx5_flow_ext_mreg_supported(dev))
1434                         return rte_flow_error_set(error, ENOTSUP,
1435                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1436                                           "extended metadata register"
1437                                           " isn't supported");
1438                 reg = flow_dv_get_metadata_reg(dev, attr, error);
1439                 if (reg < 0)
1440                         return reg;
1441                 if (reg == REG_B)
1442                         return rte_flow_error_set(error, ENOTSUP,
1443                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1444                                           "match on reg_b "
1445                                           "isn't supported");
1446                 if (reg != REG_A)
1447                         nic_mask.data = priv->sh->dv_meta_mask;
1448         } else if (attr->transfer) {
1449                 return rte_flow_error_set(error, ENOTSUP,
1450                                         RTE_FLOW_ERROR_TYPE_ITEM, item,
1451                                         "extended metadata feature "
1452                                         "should be enabled when "
1453                                         "meta item is requested "
1454                                         "with e-switch mode ");
1455         }
1456         if (!mask)
1457                 mask = &rte_flow_item_meta_mask;
1458         if (!mask->data)
1459                 return rte_flow_error_set(error, EINVAL,
1460                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1461                                         "mask cannot be zero");
1462
1463         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1464                                         (const uint8_t *)&nic_mask,
1465                                         sizeof(struct rte_flow_item_meta),
1466                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1467         return ret;
1468 }
1469
1470 /**
1471  * Validate TAG item.
1472  *
1473  * @param[in] dev
1474  *   Pointer to the rte_eth_dev structure.
1475  * @param[in] item
1476  *   Item specification.
1477  * @param[in] attr
1478  *   Attributes of flow that includes this item.
1479  * @param[out] error
1480  *   Pointer to error structure.
1481  *
1482  * @return
1483  *   0 on success, a negative errno value otherwise and rte_errno is set.
1484  */
1485 static int
1486 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
1487                           const struct rte_flow_item *item,
1488                           const struct rte_flow_attr *attr __rte_unused,
1489                           struct rte_flow_error *error)
1490 {
1491         const struct rte_flow_item_tag *spec = item->spec;
1492         const struct rte_flow_item_tag *mask = item->mask;
1493         const struct rte_flow_item_tag nic_mask = {
1494                 .data = RTE_BE32(UINT32_MAX),
1495                 .index = 0xff,
1496         };
1497         int ret;
1498
1499         if (!mlx5_flow_ext_mreg_supported(dev))
1500                 return rte_flow_error_set(error, ENOTSUP,
1501                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1502                                           "extensive metadata register"
1503                                           " isn't supported");
1504         if (!spec)
1505                 return rte_flow_error_set(error, EINVAL,
1506                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1507                                           item->spec,
1508                                           "data cannot be empty");
1509         if (!mask)
1510                 mask = &rte_flow_item_tag_mask;
1511         if (!mask->data)
1512                 return rte_flow_error_set(error, EINVAL,
1513                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1514                                         "mask cannot be zero");
1515
1516         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1517                                         (const uint8_t *)&nic_mask,
1518                                         sizeof(struct rte_flow_item_tag),
1519                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1520         if (ret < 0)
1521                 return ret;
1522         if (mask->index != 0xff)
1523                 return rte_flow_error_set(error, EINVAL,
1524                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1525                                           "partial mask for tag index"
1526                                           " is not supported");
1527         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
1528         if (ret < 0)
1529                 return ret;
1530         MLX5_ASSERT(ret != REG_NON);
1531         return 0;
1532 }
1533
1534 /**
1535  * Validate vport item.
1536  *
1537  * @param[in] dev
1538  *   Pointer to the rte_eth_dev structure.
1539  * @param[in] item
1540  *   Item specification.
1541  * @param[in] attr
1542  *   Attributes of flow that includes this item.
1543  * @param[in] item_flags
1544  *   Bit-fields that holds the items detected until now.
1545  * @param[out] error
1546  *   Pointer to error structure.
1547  *
1548  * @return
1549  *   0 on success, a negative errno value otherwise and rte_errno is set.
1550  */
1551 static int
1552 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
1553                               const struct rte_flow_item *item,
1554                               const struct rte_flow_attr *attr,
1555                               uint64_t item_flags,
1556                               struct rte_flow_error *error)
1557 {
1558         const struct rte_flow_item_port_id *spec = item->spec;
1559         const struct rte_flow_item_port_id *mask = item->mask;
1560         const struct rte_flow_item_port_id switch_mask = {
1561                         .id = 0xffffffff,
1562         };
1563         struct mlx5_priv *esw_priv;
1564         struct mlx5_priv *dev_priv;
1565         int ret;
1566
1567         if (!attr->transfer)
1568                 return rte_flow_error_set(error, EINVAL,
1569                                           RTE_FLOW_ERROR_TYPE_ITEM,
1570                                           NULL,
1571                                           "match on port id is valid only"
1572                                           " when transfer flag is enabled");
1573         if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
1574                 return rte_flow_error_set(error, ENOTSUP,
1575                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1576                                           "multiple source ports are not"
1577                                           " supported");
1578         if (!mask)
1579                 mask = &switch_mask;
1580         if (mask->id != 0xffffffff)
1581                 return rte_flow_error_set(error, ENOTSUP,
1582                                            RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1583                                            mask,
1584                                            "no support for partial mask on"
1585                                            " \"id\" field");
1586         ret = mlx5_flow_item_acceptable
1587                                 (item, (const uint8_t *)mask,
1588                                  (const uint8_t *)&rte_flow_item_port_id_mask,
1589                                  sizeof(struct rte_flow_item_port_id),
1590                                  MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1591         if (ret)
1592                 return ret;
1593         if (!spec)
1594                 return 0;
1595         esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
1596         if (!esw_priv)
1597                 return rte_flow_error_set(error, rte_errno,
1598                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1599                                           "failed to obtain E-Switch info for"
1600                                           " port");
1601         dev_priv = mlx5_dev_to_eswitch_info(dev);
1602         if (!dev_priv)
1603                 return rte_flow_error_set(error, rte_errno,
1604                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1605                                           NULL,
1606                                           "failed to obtain E-Switch info");
1607         if (esw_priv->domain_id != dev_priv->domain_id)
1608                 return rte_flow_error_set(error, EINVAL,
1609                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1610                                           "cannot match on a port from a"
1611                                           " different E-Switch");
1612         return 0;
1613 }
1614
1615 /**
1616  * Validate VLAN item.
1617  *
1618  * @param[in] item
1619  *   Item specification.
1620  * @param[in] item_flags
1621  *   Bit-fields that holds the items detected until now.
1622  * @param[in] dev
1623  *   Ethernet device flow is being created on.
1624  * @param[out] error
1625  *   Pointer to error structure.
1626  *
1627  * @return
1628  *   0 on success, a negative errno value otherwise and rte_errno is set.
1629  */
1630 static int
1631 flow_dv_validate_item_vlan(const struct rte_flow_item *item,
1632                            uint64_t item_flags,
1633                            struct rte_eth_dev *dev,
1634                            struct rte_flow_error *error)
1635 {
1636         const struct rte_flow_item_vlan *mask = item->mask;
1637         const struct rte_flow_item_vlan nic_mask = {
1638                 .tci = RTE_BE16(UINT16_MAX),
1639                 .inner_type = RTE_BE16(UINT16_MAX),
1640                 .has_more_vlan = 1,
1641         };
1642         const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
1643         int ret;
1644         const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 |
1645                                         MLX5_FLOW_LAYER_INNER_L4) :
1646                                        (MLX5_FLOW_LAYER_OUTER_L3 |
1647                                         MLX5_FLOW_LAYER_OUTER_L4);
1648         const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
1649                                         MLX5_FLOW_LAYER_OUTER_VLAN;
1650
1651         if (item_flags & vlanm)
1652                 return rte_flow_error_set(error, EINVAL,
1653                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1654                                           "multiple VLAN layers not supported");
1655         else if ((item_flags & l34m) != 0)
1656                 return rte_flow_error_set(error, EINVAL,
1657                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1658                                           "VLAN cannot follow L3/L4 layer");
1659         if (!mask)
1660                 mask = &rte_flow_item_vlan_mask;
1661         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1662                                         (const uint8_t *)&nic_mask,
1663                                         sizeof(struct rte_flow_item_vlan),
1664                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1665         if (ret)
1666                 return ret;
1667         if (!tunnel && mask->tci != RTE_BE16(0x0fff)) {
1668                 struct mlx5_priv *priv = dev->data->dev_private;
1669
1670                 if (priv->vmwa_context) {
1671                         /*
1672                          * Non-NULL context means we have a virtual machine
1673                          * and SR-IOV enabled, we have to create VLAN interface
1674                          * to make hypervisor to setup E-Switch vport
1675                          * context correctly. We avoid creating the multiple
1676                          * VLAN interfaces, so we cannot support VLAN tag mask.
1677                          */
1678                         return rte_flow_error_set(error, EINVAL,
1679                                                   RTE_FLOW_ERROR_TYPE_ITEM,
1680                                                   item,
1681                                                   "VLAN tag mask is not"
1682                                                   " supported in virtual"
1683                                                   " environment");
1684                 }
1685         }
1686         return 0;
1687 }
1688
1689 /*
1690  * GTP flags are contained in 1 byte of the format:
1691  * -------------------------------------------
1692  * | bit   | 0 - 2   | 3  | 4   | 5 | 6 | 7  |
1693  * |-----------------------------------------|
1694  * | value | Version | PT | Res | E | S | PN |
1695  * -------------------------------------------
1696  *
1697  * Matching is supported only for GTP flags E, S, PN.
1698  */
1699 #define MLX5_GTP_FLAGS_MASK     0x07
1700
1701 /**
1702  * Validate GTP item.
1703  *
1704  * @param[in] dev
1705  *   Pointer to the rte_eth_dev structure.
1706  * @param[in] item
1707  *   Item specification.
1708  * @param[in] item_flags
1709  *   Bit-fields that holds the items detected until now.
1710  * @param[out] error
1711  *   Pointer to error structure.
1712  *
1713  * @return
1714  *   0 on success, a negative errno value otherwise and rte_errno is set.
1715  */
1716 static int
1717 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
1718                           const struct rte_flow_item *item,
1719                           uint64_t item_flags,
1720                           struct rte_flow_error *error)
1721 {
1722         struct mlx5_priv *priv = dev->data->dev_private;
1723         const struct rte_flow_item_gtp *spec = item->spec;
1724         const struct rte_flow_item_gtp *mask = item->mask;
1725         const struct rte_flow_item_gtp nic_mask = {
1726                 .v_pt_rsv_flags = MLX5_GTP_FLAGS_MASK,
1727                 .msg_type = 0xff,
1728                 .teid = RTE_BE32(0xffffffff),
1729         };
1730
1731         if (!priv->config.hca_attr.tunnel_stateless_gtp)
1732                 return rte_flow_error_set(error, ENOTSUP,
1733                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1734                                           "GTP support is not enabled");
1735         if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
1736                 return rte_flow_error_set(error, ENOTSUP,
1737                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1738                                           "multiple tunnel layers not"
1739                                           " supported");
1740         if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
1741                 return rte_flow_error_set(error, EINVAL,
1742                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1743                                           "no outer UDP layer found");
1744         if (!mask)
1745                 mask = &rte_flow_item_gtp_mask;
1746         if (spec && spec->v_pt_rsv_flags & ~MLX5_GTP_FLAGS_MASK)
1747                 return rte_flow_error_set(error, ENOTSUP,
1748                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1749                                           "Match is supported for GTP"
1750                                           " flags only");
1751         return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1752                                          (const uint8_t *)&nic_mask,
1753                                          sizeof(struct rte_flow_item_gtp),
1754                                          MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1755 }
1756
1757 /**
1758  * Validate IPV4 item.
1759  * Use existing validation function mlx5_flow_validate_item_ipv4(), and
1760  * add specific validation of fragment_offset field,
1761  *
1762  * @param[in] item
1763  *   Item specification.
1764  * @param[in] item_flags
1765  *   Bit-fields that holds the items detected until now.
1766  * @param[out] error
1767  *   Pointer to error structure.
1768  *
1769  * @return
1770  *   0 on success, a negative errno value otherwise and rte_errno is set.
1771  */
1772 static int
1773 flow_dv_validate_item_ipv4(const struct rte_flow_item *item,
1774                            uint64_t item_flags,
1775                            uint64_t last_item,
1776                            uint16_t ether_type,
1777                            struct rte_flow_error *error)
1778 {
1779         int ret;
1780         const struct rte_flow_item_ipv4 *spec = item->spec;
1781         const struct rte_flow_item_ipv4 *last = item->last;
1782         const struct rte_flow_item_ipv4 *mask = item->mask;
1783         rte_be16_t fragment_offset_spec = 0;
1784         rte_be16_t fragment_offset_last = 0;
1785         const struct rte_flow_item_ipv4 nic_ipv4_mask = {
1786                 .hdr = {
1787                         .src_addr = RTE_BE32(0xffffffff),
1788                         .dst_addr = RTE_BE32(0xffffffff),
1789                         .type_of_service = 0xff,
1790                         .fragment_offset = RTE_BE16(0xffff),
1791                         .next_proto_id = 0xff,
1792                         .time_to_live = 0xff,
1793                 },
1794         };
1795
1796         ret = mlx5_flow_validate_item_ipv4(item, item_flags, last_item,
1797                                            ether_type, &nic_ipv4_mask,
1798                                            MLX5_ITEM_RANGE_ACCEPTED, error);
1799         if (ret < 0)
1800                 return ret;
1801         if (spec && mask)
1802                 fragment_offset_spec = spec->hdr.fragment_offset &
1803                                        mask->hdr.fragment_offset;
1804         if (!fragment_offset_spec)
1805                 return 0;
1806         /*
1807          * spec and mask are valid, enforce using full mask to make sure the
1808          * complete value is used correctly.
1809          */
1810         if ((mask->hdr.fragment_offset & RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
1811                         != RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
1812                 return rte_flow_error_set(error, EINVAL,
1813                                           RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1814                                           item, "must use full mask for"
1815                                           " fragment_offset");
1816         /*
1817          * Match on fragment_offset 0x2000 means MF is 1 and frag-offset is 0,
1818          * indicating this is 1st fragment of fragmented packet.
1819          * This is not yet supported in MLX5, return appropriate error message.
1820          */
1821         if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG))
1822                 return rte_flow_error_set(error, ENOTSUP,
1823                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1824                                           "match on first fragment not "
1825                                           "supported");
1826         if (fragment_offset_spec && !last)
1827                 return rte_flow_error_set(error, ENOTSUP,
1828                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1829                                           "specified value not supported");
1830         /* spec and last are valid, validate the specified range. */
1831         fragment_offset_last = last->hdr.fragment_offset &
1832                                mask->hdr.fragment_offset;
1833         /*
1834          * Match on fragment_offset spec 0x2001 and last 0x3fff
1835          * means MF is 1 and frag-offset is > 0.
1836          * This packet is fragment 2nd and onward, excluding last.
1837          * This is not yet supported in MLX5, return appropriate
1838          * error message.
1839          */
1840         if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG + 1) &&
1841             fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
1842                 return rte_flow_error_set(error, ENOTSUP,
1843                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
1844                                           last, "match on following "
1845                                           "fragments not supported");
1846         /*
1847          * Match on fragment_offset spec 0x0001 and last 0x1fff
1848          * means MF is 0 and frag-offset is > 0.
1849          * This packet is last fragment of fragmented packet.
1850          * This is not yet supported in MLX5, return appropriate
1851          * error message.
1852          */
1853         if (fragment_offset_spec == RTE_BE16(1) &&
1854             fragment_offset_last == RTE_BE16(RTE_IPV4_HDR_OFFSET_MASK))
1855                 return rte_flow_error_set(error, ENOTSUP,
1856                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
1857                                           last, "match on last "
1858                                           "fragment not supported");
1859         /*
1860          * Match on fragment_offset spec 0x0001 and last 0x3fff
1861          * means MF and/or frag-offset is not 0.
1862          * This is a fragmented packet.
1863          * Other range values are invalid and rejected.
1864          */
1865         if (!(fragment_offset_spec == RTE_BE16(1) &&
1866               fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK)))
1867                 return rte_flow_error_set(error, ENOTSUP,
1868                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
1869                                           "specified range not supported");
1870         return 0;
1871 }
1872
1873 /**
1874  * Validate IPV6 fragment extension item.
1875  *
1876  * @param[in] item
1877  *   Item specification.
1878  * @param[in] item_flags
1879  *   Bit-fields that holds the items detected until now.
1880  * @param[out] error
1881  *   Pointer to error structure.
1882  *
1883  * @return
1884  *   0 on success, a negative errno value otherwise and rte_errno is set.
1885  */
1886 static int
1887 flow_dv_validate_item_ipv6_frag_ext(const struct rte_flow_item *item,
1888                                     uint64_t item_flags,
1889                                     struct rte_flow_error *error)
1890 {
1891         const struct rte_flow_item_ipv6_frag_ext *spec = item->spec;
1892         const struct rte_flow_item_ipv6_frag_ext *last = item->last;
1893         const struct rte_flow_item_ipv6_frag_ext *mask = item->mask;
1894         rte_be16_t frag_data_spec = 0;
1895         rte_be16_t frag_data_last = 0;
1896         const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
1897         const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 :
1898                                       MLX5_FLOW_LAYER_OUTER_L4;
1899         int ret = 0;
1900         struct rte_flow_item_ipv6_frag_ext nic_mask = {
1901                 .hdr = {
1902                         .next_header = 0xff,
1903                         .frag_data = RTE_BE16(0xffff),
1904                 },
1905         };
1906
1907         if (item_flags & l4m)
1908                 return rte_flow_error_set(error, EINVAL,
1909                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1910                                           "ipv6 fragment extension item cannot "
1911                                           "follow L4 item.");
1912         if ((tunnel && !(item_flags & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
1913             (!tunnel && !(item_flags & MLX5_FLOW_LAYER_OUTER_L3_IPV6)))
1914                 return rte_flow_error_set(error, EINVAL,
1915                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1916                                           "ipv6 fragment extension item must "
1917                                           "follow ipv6 item");
1918         if (spec && mask)
1919                 frag_data_spec = spec->hdr.frag_data & mask->hdr.frag_data;
1920         if (!frag_data_spec)
1921                 return 0;
1922         /*
1923          * spec and mask are valid, enforce using full mask to make sure the
1924          * complete value is used correctly.
1925          */
1926         if ((mask->hdr.frag_data & RTE_BE16(RTE_IPV6_FRAG_USED_MASK)) !=
1927                                 RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
1928                 return rte_flow_error_set(error, EINVAL,
1929                                           RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1930                                           item, "must use full mask for"
1931                                           " frag_data");
1932         /*
1933          * Match on frag_data 0x00001 means M is 1 and frag-offset is 0.
1934          * This is 1st fragment of fragmented packet.
1935          */
1936         if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_MF_MASK))
1937                 return rte_flow_error_set(error, ENOTSUP,
1938                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1939                                           "match on first fragment not "
1940                                           "supported");
1941         if (frag_data_spec && !last)
1942                 return rte_flow_error_set(error, EINVAL,
1943                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1944                                           "specified value not supported");
1945         ret = mlx5_flow_item_acceptable
1946                                 (item, (const uint8_t *)mask,
1947                                  (const uint8_t *)&nic_mask,
1948                                  sizeof(struct rte_flow_item_ipv6_frag_ext),
1949                                  MLX5_ITEM_RANGE_ACCEPTED, error);
1950         if (ret)
1951                 return ret;
1952         /* spec and last are valid, validate the specified range. */
1953         frag_data_last = last->hdr.frag_data & mask->hdr.frag_data;
1954         /*
1955          * Match on frag_data spec 0x0009 and last 0xfff9
1956          * means M is 1 and frag-offset is > 0.
1957          * This packet is fragment 2nd and onward, excluding last.
1958          * This is not yet supported in MLX5, return appropriate
1959          * error message.
1960          */
1961         if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN |
1962                                        RTE_IPV6_EHDR_MF_MASK) &&
1963             frag_data_last == RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
1964                 return rte_flow_error_set(error, ENOTSUP,
1965                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
1966                                           last, "match on following "
1967                                           "fragments not supported");
1968         /*
1969          * Match on frag_data spec 0x0008 and last 0xfff8
1970          * means M is 0 and frag-offset is > 0.
1971          * This packet is last fragment of fragmented packet.
1972          * This is not yet supported in MLX5, return appropriate
1973          * error message.
1974          */
1975         if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN) &&
1976             frag_data_last == RTE_BE16(RTE_IPV6_EHDR_FO_MASK))
1977                 return rte_flow_error_set(error, ENOTSUP,
1978                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
1979                                           last, "match on last "
1980                                           "fragment not supported");
1981         /* Other range values are invalid and rejected. */
1982         return rte_flow_error_set(error, EINVAL,
1983                                   RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
1984                                   "specified range not supported");
1985 }
1986
1987 /**
1988  * Validate the pop VLAN action.
1989  *
1990  * @param[in] dev
1991  *   Pointer to the rte_eth_dev structure.
1992  * @param[in] action_flags
1993  *   Holds the actions detected until now.
1994  * @param[in] action
1995  *   Pointer to the pop vlan action.
1996  * @param[in] item_flags
1997  *   The items found in this flow rule.
1998  * @param[in] attr
1999  *   Pointer to flow attributes.
2000  * @param[out] error
2001  *   Pointer to error structure.
2002  *
2003  * @return
2004  *   0 on success, a negative errno value otherwise and rte_errno is set.
2005  */
2006 static int
2007 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
2008                                  uint64_t action_flags,
2009                                  const struct rte_flow_action *action,
2010                                  uint64_t item_flags,
2011                                  const struct rte_flow_attr *attr,
2012                                  struct rte_flow_error *error)
2013 {
2014         const struct mlx5_priv *priv = dev->data->dev_private;
2015
2016         (void)action;
2017         (void)attr;
2018         if (!priv->sh->pop_vlan_action)
2019                 return rte_flow_error_set(error, ENOTSUP,
2020                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2021                                           NULL,
2022                                           "pop vlan action is not supported");
2023         if (attr->egress)
2024                 return rte_flow_error_set(error, ENOTSUP,
2025                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2026                                           NULL,
2027                                           "pop vlan action not supported for "
2028                                           "egress");
2029         if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
2030                 return rte_flow_error_set(error, ENOTSUP,
2031                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2032                                           "no support for multiple VLAN "
2033                                           "actions");
2034         /* Pop VLAN with preceding Decap requires inner header with VLAN. */
2035         if ((action_flags & MLX5_FLOW_ACTION_DECAP) &&
2036             !(item_flags & MLX5_FLOW_LAYER_INNER_VLAN))
2037                 return rte_flow_error_set(error, ENOTSUP,
2038                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2039                                           NULL,
2040                                           "cannot pop vlan after decap without "
2041                                           "match on inner vlan in the flow");
2042         /* Pop VLAN without preceding Decap requires outer header with VLAN. */
2043         if (!(action_flags & MLX5_FLOW_ACTION_DECAP) &&
2044             !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2045                 return rte_flow_error_set(error, ENOTSUP,
2046                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2047                                           NULL,
2048                                           "cannot pop vlan without a "
2049                                           "match on (outer) vlan in the flow");
2050         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2051                 return rte_flow_error_set(error, EINVAL,
2052                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2053                                           "wrong action order, port_id should "
2054                                           "be after pop VLAN action");
2055         if (!attr->transfer && priv->representor)
2056                 return rte_flow_error_set(error, ENOTSUP,
2057                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2058                                           "pop vlan action for VF representor "
2059                                           "not supported on NIC table");
2060         return 0;
2061 }
2062
2063 /**
2064  * Get VLAN default info from vlan match info.
2065  *
2066  * @param[in] items
2067  *   the list of item specifications.
2068  * @param[out] vlan
2069  *   pointer VLAN info to fill to.
2070  *
2071  * @return
2072  *   0 on success, a negative errno value otherwise and rte_errno is set.
2073  */
2074 static void
2075 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
2076                                   struct rte_vlan_hdr *vlan)
2077 {
2078         const struct rte_flow_item_vlan nic_mask = {
2079                 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
2080                                 MLX5DV_FLOW_VLAN_VID_MASK),
2081                 .inner_type = RTE_BE16(0xffff),
2082         };
2083
2084         if (items == NULL)
2085                 return;
2086         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2087                 int type = items->type;
2088
2089                 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
2090                     type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
2091                         break;
2092         }
2093         if (items->type != RTE_FLOW_ITEM_TYPE_END) {
2094                 const struct rte_flow_item_vlan *vlan_m = items->mask;
2095                 const struct rte_flow_item_vlan *vlan_v = items->spec;
2096
2097                 /* If VLAN item in pattern doesn't contain data, return here. */
2098                 if (!vlan_v)
2099                         return;
2100                 if (!vlan_m)
2101                         vlan_m = &nic_mask;
2102                 /* Only full match values are accepted */
2103                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
2104                      MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
2105                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
2106                         vlan->vlan_tci |=
2107                                 rte_be_to_cpu_16(vlan_v->tci &
2108                                                  MLX5DV_FLOW_VLAN_PCP_MASK_BE);
2109                 }
2110                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
2111                      MLX5DV_FLOW_VLAN_VID_MASK_BE) {
2112                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
2113                         vlan->vlan_tci |=
2114                                 rte_be_to_cpu_16(vlan_v->tci &
2115                                                  MLX5DV_FLOW_VLAN_VID_MASK_BE);
2116                 }
2117                 if (vlan_m->inner_type == nic_mask.inner_type)
2118                         vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
2119                                                            vlan_m->inner_type);
2120         }
2121 }
2122
2123 /**
2124  * Validate the push VLAN action.
2125  *
2126  * @param[in] dev
2127  *   Pointer to the rte_eth_dev structure.
2128  * @param[in] action_flags
2129  *   Holds the actions detected until now.
2130  * @param[in] item_flags
2131  *   The items found in this flow rule.
2132  * @param[in] action
2133  *   Pointer to the action structure.
2134  * @param[in] attr
2135  *   Pointer to flow attributes
2136  * @param[out] error
2137  *   Pointer to error structure.
2138  *
2139  * @return
2140  *   0 on success, a negative errno value otherwise and rte_errno is set.
2141  */
2142 static int
2143 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
2144                                   uint64_t action_flags,
2145                                   const struct rte_flow_item_vlan *vlan_m,
2146                                   const struct rte_flow_action *action,
2147                                   const struct rte_flow_attr *attr,
2148                                   struct rte_flow_error *error)
2149 {
2150         const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
2151         const struct mlx5_priv *priv = dev->data->dev_private;
2152
2153         if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
2154             push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
2155                 return rte_flow_error_set(error, EINVAL,
2156                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2157                                           "invalid vlan ethertype");
2158         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2159                 return rte_flow_error_set(error, EINVAL,
2160                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2161                                           "wrong action order, port_id should "
2162                                           "be after push VLAN");
2163         if (!attr->transfer && priv->representor)
2164                 return rte_flow_error_set(error, ENOTSUP,
2165                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2166                                           "push vlan action for VF representor "
2167                                           "not supported on NIC table");
2168         if (vlan_m &&
2169             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
2170             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
2171                 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
2172             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
2173             !(mlx5_flow_find_action
2174                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
2175                 return rte_flow_error_set(error, EINVAL,
2176                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2177                                           "not full match mask on VLAN PCP and "
2178                                           "there is no of_set_vlan_pcp action, "
2179                                           "push VLAN action cannot figure out "
2180                                           "PCP value");
2181         if (vlan_m &&
2182             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
2183             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
2184                 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
2185             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
2186             !(mlx5_flow_find_action
2187                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
2188                 return rte_flow_error_set(error, EINVAL,
2189                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2190                                           "not full match mask on VLAN VID and "
2191                                           "there is no of_set_vlan_vid action, "
2192                                           "push VLAN action cannot figure out "
2193                                           "VID value");
2194         (void)attr;
2195         return 0;
2196 }
2197
2198 /**
2199  * Validate the set VLAN PCP.
2200  *
2201  * @param[in] action_flags
2202  *   Holds the actions detected until now.
2203  * @param[in] actions
2204  *   Pointer to the list of actions remaining in the flow rule.
2205  * @param[out] error
2206  *   Pointer to error structure.
2207  *
2208  * @return
2209  *   0 on success, a negative errno value otherwise and rte_errno is set.
2210  */
2211 static int
2212 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
2213                                      const struct rte_flow_action actions[],
2214                                      struct rte_flow_error *error)
2215 {
2216         const struct rte_flow_action *action = actions;
2217         const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
2218
2219         if (conf->vlan_pcp > 7)
2220                 return rte_flow_error_set(error, EINVAL,
2221                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2222                                           "VLAN PCP value is too big");
2223         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
2224                 return rte_flow_error_set(error, ENOTSUP,
2225                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2226                                           "set VLAN PCP action must follow "
2227                                           "the push VLAN action");
2228         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
2229                 return rte_flow_error_set(error, ENOTSUP,
2230                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2231                                           "Multiple VLAN PCP modification are "
2232                                           "not supported");
2233         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2234                 return rte_flow_error_set(error, EINVAL,
2235                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2236                                           "wrong action order, port_id should "
2237                                           "be after set VLAN PCP");
2238         return 0;
2239 }
2240
2241 /**
2242  * Validate the set VLAN VID.
2243  *
2244  * @param[in] item_flags
2245  *   Holds the items detected in this rule.
2246  * @param[in] action_flags
2247  *   Holds the actions detected until now.
2248  * @param[in] actions
2249  *   Pointer to the list of actions remaining in the flow rule.
2250  * @param[out] error
2251  *   Pointer to error structure.
2252  *
2253  * @return
2254  *   0 on success, a negative errno value otherwise and rte_errno is set.
2255  */
2256 static int
2257 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
2258                                      uint64_t action_flags,
2259                                      const struct rte_flow_action actions[],
2260                                      struct rte_flow_error *error)
2261 {
2262         const struct rte_flow_action *action = actions;
2263         const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
2264
2265         if (rte_be_to_cpu_16(conf->vlan_vid) > 0xFFE)
2266                 return rte_flow_error_set(error, EINVAL,
2267                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2268                                           "VLAN VID value is too big");
2269         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
2270             !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2271                 return rte_flow_error_set(error, ENOTSUP,
2272                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2273                                           "set VLAN VID action must follow push"
2274                                           " VLAN action or match on VLAN item");
2275         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
2276                 return rte_flow_error_set(error, ENOTSUP,
2277                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2278                                           "Multiple VLAN VID modifications are "
2279                                           "not supported");
2280         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2281                 return rte_flow_error_set(error, EINVAL,
2282                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2283                                           "wrong action order, port_id should "
2284                                           "be after set VLAN VID");
2285         return 0;
2286 }
2287
2288 /*
2289  * Validate the FLAG action.
2290  *
2291  * @param[in] dev
2292  *   Pointer to the rte_eth_dev structure.
2293  * @param[in] action_flags
2294  *   Holds the actions detected until now.
2295  * @param[in] attr
2296  *   Pointer to flow attributes
2297  * @param[out] error
2298  *   Pointer to error structure.
2299  *
2300  * @return
2301  *   0 on success, a negative errno value otherwise and rte_errno is set.
2302  */
2303 static int
2304 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
2305                              uint64_t action_flags,
2306                              const struct rte_flow_attr *attr,
2307                              struct rte_flow_error *error)
2308 {
2309         struct mlx5_priv *priv = dev->data->dev_private;
2310         struct mlx5_dev_config *config = &priv->config;
2311         int ret;
2312
2313         /* Fall back if no extended metadata register support. */
2314         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2315                 return mlx5_flow_validate_action_flag(action_flags, attr,
2316                                                       error);
2317         /* Extensive metadata mode requires registers. */
2318         if (!mlx5_flow_ext_mreg_supported(dev))
2319                 return rte_flow_error_set(error, ENOTSUP,
2320                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2321                                           "no metadata registers "
2322                                           "to support flag action");
2323         if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
2324                 return rte_flow_error_set(error, ENOTSUP,
2325                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2326                                           "extended metadata register"
2327                                           " isn't available");
2328         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2329         if (ret < 0)
2330                 return ret;
2331         MLX5_ASSERT(ret > 0);
2332         if (action_flags & MLX5_FLOW_ACTION_MARK)
2333                 return rte_flow_error_set(error, EINVAL,
2334                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2335                                           "can't mark and flag in same flow");
2336         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2337                 return rte_flow_error_set(error, EINVAL,
2338                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2339                                           "can't have 2 flag"
2340                                           " actions in same flow");
2341         return 0;
2342 }
2343
2344 /**
2345  * Validate MARK action.
2346  *
2347  * @param[in] dev
2348  *   Pointer to the rte_eth_dev structure.
2349  * @param[in] action
2350  *   Pointer to action.
2351  * @param[in] action_flags
2352  *   Holds the actions detected until now.
2353  * @param[in] attr
2354  *   Pointer to flow attributes
2355  * @param[out] error
2356  *   Pointer to error structure.
2357  *
2358  * @return
2359  *   0 on success, a negative errno value otherwise and rte_errno is set.
2360  */
2361 static int
2362 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
2363                              const struct rte_flow_action *action,
2364                              uint64_t action_flags,
2365                              const struct rte_flow_attr *attr,
2366                              struct rte_flow_error *error)
2367 {
2368         struct mlx5_priv *priv = dev->data->dev_private;
2369         struct mlx5_dev_config *config = &priv->config;
2370         const struct rte_flow_action_mark *mark = action->conf;
2371         int ret;
2372
2373         /* Fall back if no extended metadata register support. */
2374         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2375                 return mlx5_flow_validate_action_mark(action, action_flags,
2376                                                       attr, error);
2377         /* Extensive metadata mode requires registers. */
2378         if (!mlx5_flow_ext_mreg_supported(dev))
2379                 return rte_flow_error_set(error, ENOTSUP,
2380                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2381                                           "no metadata registers "
2382                                           "to support mark action");
2383         if (!priv->sh->dv_mark_mask)
2384                 return rte_flow_error_set(error, ENOTSUP,
2385                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2386                                           "extended metadata register"
2387                                           " isn't available");
2388         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2389         if (ret < 0)
2390                 return ret;
2391         MLX5_ASSERT(ret > 0);
2392         if (!mark)
2393                 return rte_flow_error_set(error, EINVAL,
2394                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2395                                           "configuration cannot be null");
2396         if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
2397                 return rte_flow_error_set(error, EINVAL,
2398                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2399                                           &mark->id,
2400                                           "mark id exceeds the limit");
2401         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2402                 return rte_flow_error_set(error, EINVAL,
2403                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2404                                           "can't flag and mark in same flow");
2405         if (action_flags & MLX5_FLOW_ACTION_MARK)
2406                 return rte_flow_error_set(error, EINVAL,
2407                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2408                                           "can't have 2 mark actions in same"
2409                                           " flow");
2410         return 0;
2411 }
2412
2413 /**
2414  * Validate SET_META action.
2415  *
2416  * @param[in] dev
2417  *   Pointer to the rte_eth_dev structure.
2418  * @param[in] action
2419  *   Pointer to the action structure.
2420  * @param[in] action_flags
2421  *   Holds the actions detected until now.
2422  * @param[in] attr
2423  *   Pointer to flow attributes
2424  * @param[out] error
2425  *   Pointer to error structure.
2426  *
2427  * @return
2428  *   0 on success, a negative errno value otherwise and rte_errno is set.
2429  */
2430 static int
2431 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
2432                                  const struct rte_flow_action *action,
2433                                  uint64_t action_flags __rte_unused,
2434                                  const struct rte_flow_attr *attr,
2435                                  struct rte_flow_error *error)
2436 {
2437         const struct rte_flow_action_set_meta *conf;
2438         uint32_t nic_mask = UINT32_MAX;
2439         int reg;
2440
2441         if (!mlx5_flow_ext_mreg_supported(dev))
2442                 return rte_flow_error_set(error, ENOTSUP,
2443                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2444                                           "extended metadata register"
2445                                           " isn't supported");
2446         reg = flow_dv_get_metadata_reg(dev, attr, error);
2447         if (reg < 0)
2448                 return reg;
2449         if (reg != REG_A && reg != REG_B) {
2450                 struct mlx5_priv *priv = dev->data->dev_private;
2451
2452                 nic_mask = priv->sh->dv_meta_mask;
2453         }
2454         if (!(action->conf))
2455                 return rte_flow_error_set(error, EINVAL,
2456                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2457                                           "configuration cannot be null");
2458         conf = (const struct rte_flow_action_set_meta *)action->conf;
2459         if (!conf->mask)
2460                 return rte_flow_error_set(error, EINVAL,
2461                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2462                                           "zero mask doesn't have any effect");
2463         if (conf->mask & ~nic_mask)
2464                 return rte_flow_error_set(error, EINVAL,
2465                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2466                                           "meta data must be within reg C0");
2467         return 0;
2468 }
2469
2470 /**
2471  * Validate SET_TAG action.
2472  *
2473  * @param[in] dev
2474  *   Pointer to the rte_eth_dev structure.
2475  * @param[in] action
2476  *   Pointer to the action structure.
2477  * @param[in] action_flags
2478  *   Holds the actions detected until now.
2479  * @param[in] attr
2480  *   Pointer to flow attributes
2481  * @param[out] error
2482  *   Pointer to error structure.
2483  *
2484  * @return
2485  *   0 on success, a negative errno value otherwise and rte_errno is set.
2486  */
2487 static int
2488 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
2489                                 const struct rte_flow_action *action,
2490                                 uint64_t action_flags,
2491                                 const struct rte_flow_attr *attr,
2492                                 struct rte_flow_error *error)
2493 {
2494         const struct rte_flow_action_set_tag *conf;
2495         const uint64_t terminal_action_flags =
2496                 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
2497                 MLX5_FLOW_ACTION_RSS;
2498         int ret;
2499
2500         if (!mlx5_flow_ext_mreg_supported(dev))
2501                 return rte_flow_error_set(error, ENOTSUP,
2502                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2503                                           "extensive metadata register"
2504                                           " isn't supported");
2505         if (!(action->conf))
2506                 return rte_flow_error_set(error, EINVAL,
2507                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2508                                           "configuration cannot be null");
2509         conf = (const struct rte_flow_action_set_tag *)action->conf;
2510         if (!conf->mask)
2511                 return rte_flow_error_set(error, EINVAL,
2512                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2513                                           "zero mask doesn't have any effect");
2514         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
2515         if (ret < 0)
2516                 return ret;
2517         if (!attr->transfer && attr->ingress &&
2518             (action_flags & terminal_action_flags))
2519                 return rte_flow_error_set(error, EINVAL,
2520                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2521                                           "set_tag has no effect"
2522                                           " with terminal actions");
2523         return 0;
2524 }
2525
2526 /**
2527  * Validate count action.
2528  *
2529  * @param[in] dev
2530  *   Pointer to rte_eth_dev structure.
2531  * @param[out] error
2532  *   Pointer to error structure.
2533  *
2534  * @return
2535  *   0 on success, a negative errno value otherwise and rte_errno is set.
2536  */
2537 static int
2538 flow_dv_validate_action_count(struct rte_eth_dev *dev,
2539                               struct rte_flow_error *error)
2540 {
2541         struct mlx5_priv *priv = dev->data->dev_private;
2542
2543         if (!priv->config.devx)
2544                 goto notsup_err;
2545 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
2546         return 0;
2547 #endif
2548 notsup_err:
2549         return rte_flow_error_set
2550                       (error, ENOTSUP,
2551                        RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2552                        NULL,
2553                        "count action not supported");
2554 }
2555
2556 /**
2557  * Validate the L2 encap action.
2558  *
2559  * @param[in] dev
2560  *   Pointer to the rte_eth_dev structure.
2561  * @param[in] action_flags
2562  *   Holds the actions detected until now.
2563  * @param[in] action
2564  *   Pointer to the action structure.
2565  * @param[in] attr
2566  *   Pointer to flow attributes.
2567  * @param[out] error
2568  *   Pointer to error structure.
2569  *
2570  * @return
2571  *   0 on success, a negative errno value otherwise and rte_errno is set.
2572  */
2573 static int
2574 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
2575                                  uint64_t action_flags,
2576                                  const struct rte_flow_action *action,
2577                                  const struct rte_flow_attr *attr,
2578                                  struct rte_flow_error *error)
2579 {
2580         const struct mlx5_priv *priv = dev->data->dev_private;
2581
2582         if (!(action->conf))
2583                 return rte_flow_error_set(error, EINVAL,
2584                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2585                                           "configuration cannot be null");
2586         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
2587                 return rte_flow_error_set(error, EINVAL,
2588                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2589                                           "can only have a single encap action "
2590                                           "in a flow");
2591         if (!attr->transfer && priv->representor)
2592                 return rte_flow_error_set(error, ENOTSUP,
2593                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2594                                           "encap action for VF representor "
2595                                           "not supported on NIC table");
2596         return 0;
2597 }
2598
2599 /**
2600  * Validate a decap action.
2601  *
2602  * @param[in] dev
2603  *   Pointer to the rte_eth_dev structure.
2604  * @param[in] action_flags
2605  *   Holds the actions detected until now.
2606  * @param[in] attr
2607  *   Pointer to flow attributes
2608  * @param[out] error
2609  *   Pointer to error structure.
2610  *
2611  * @return
2612  *   0 on success, a negative errno value otherwise and rte_errno is set.
2613  */
2614 static int
2615 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
2616                               uint64_t action_flags,
2617                               const struct rte_flow_attr *attr,
2618                               struct rte_flow_error *error)
2619 {
2620         const struct mlx5_priv *priv = dev->data->dev_private;
2621
2622         if (priv->config.hca_attr.scatter_fcs_w_decap_disable &&
2623             !priv->config.decap_en)
2624                 return rte_flow_error_set(error, ENOTSUP,
2625                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2626                                           "decap is not enabled");
2627         if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
2628                 return rte_flow_error_set(error, ENOTSUP,
2629                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2630                                           action_flags &
2631                                           MLX5_FLOW_ACTION_DECAP ? "can only "
2632                                           "have a single decap action" : "decap "
2633                                           "after encap is not supported");
2634         if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
2635                 return rte_flow_error_set(error, EINVAL,
2636                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2637                                           "can't have decap action after"
2638                                           " modify action");
2639         if (attr->egress)
2640                 return rte_flow_error_set(error, ENOTSUP,
2641                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2642                                           NULL,
2643                                           "decap action not supported for "
2644                                           "egress");
2645         if (!attr->transfer && priv->representor)
2646                 return rte_flow_error_set(error, ENOTSUP,
2647                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2648                                           "decap action for VF representor "
2649                                           "not supported on NIC table");
2650         return 0;
2651 }
2652
2653 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
2654
2655 /**
2656  * Validate the raw encap and decap actions.
2657  *
2658  * @param[in] dev
2659  *   Pointer to the rte_eth_dev structure.
2660  * @param[in] decap
2661  *   Pointer to the decap action.
2662  * @param[in] encap
2663  *   Pointer to the encap action.
2664  * @param[in] attr
2665  *   Pointer to flow attributes
2666  * @param[in/out] action_flags
2667  *   Holds the actions detected until now.
2668  * @param[out] actions_n
2669  *   pointer to the number of actions counter.
2670  * @param[out] error
2671  *   Pointer to error structure.
2672  *
2673  * @return
2674  *   0 on success, a negative errno value otherwise and rte_errno is set.
2675  */
2676 static int
2677 flow_dv_validate_action_raw_encap_decap
2678         (struct rte_eth_dev *dev,
2679          const struct rte_flow_action_raw_decap *decap,
2680          const struct rte_flow_action_raw_encap *encap,
2681          const struct rte_flow_attr *attr, uint64_t *action_flags,
2682          int *actions_n, struct rte_flow_error *error)
2683 {
2684         const struct mlx5_priv *priv = dev->data->dev_private;
2685         int ret;
2686
2687         if (encap && (!encap->size || !encap->data))
2688                 return rte_flow_error_set(error, EINVAL,
2689                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2690                                           "raw encap data cannot be empty");
2691         if (decap && encap) {
2692                 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
2693                     encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
2694                         /* L3 encap. */
2695                         decap = NULL;
2696                 else if (encap->size <=
2697                            MLX5_ENCAPSULATION_DECISION_SIZE &&
2698                            decap->size >
2699                            MLX5_ENCAPSULATION_DECISION_SIZE)
2700                         /* L3 decap. */
2701                         encap = NULL;
2702                 else if (encap->size >
2703                            MLX5_ENCAPSULATION_DECISION_SIZE &&
2704                            decap->size >
2705                            MLX5_ENCAPSULATION_DECISION_SIZE)
2706                         /* 2 L2 actions: encap and decap. */
2707                         ;
2708                 else
2709                         return rte_flow_error_set(error,
2710                                 ENOTSUP,
2711                                 RTE_FLOW_ERROR_TYPE_ACTION,
2712                                 NULL, "unsupported too small "
2713                                 "raw decap and too small raw "
2714                                 "encap combination");
2715         }
2716         if (decap) {
2717                 ret = flow_dv_validate_action_decap(dev, *action_flags, attr,
2718                                                     error);
2719                 if (ret < 0)
2720                         return ret;
2721                 *action_flags |= MLX5_FLOW_ACTION_DECAP;
2722                 ++(*actions_n);
2723         }
2724         if (encap) {
2725                 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
2726                         return rte_flow_error_set(error, ENOTSUP,
2727                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2728                                                   NULL,
2729                                                   "small raw encap size");
2730                 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
2731                         return rte_flow_error_set(error, EINVAL,
2732                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2733                                                   NULL,
2734                                                   "more than one encap action");
2735                 if (!attr->transfer && priv->representor)
2736                         return rte_flow_error_set
2737                                         (error, ENOTSUP,
2738                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2739                                          "encap action for VF representor "
2740                                          "not supported on NIC table");
2741                 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
2742                 ++(*actions_n);
2743         }
2744         return 0;
2745 }
2746
2747 /**
2748  * Match encap_decap resource.
2749  *
2750  * @param list
2751  *   Pointer to the hash list.
2752  * @param entry
2753  *   Pointer to exist resource entry object.
2754  * @param key
2755  *   Key of the new entry.
2756  * @param ctx_cb
2757  *   Pointer to new encap_decap resource.
2758  *
2759  * @return
2760  *   0 on matching, none-zero otherwise.
2761  */
2762 int
2763 flow_dv_encap_decap_match_cb(struct mlx5_hlist *list __rte_unused,
2764                              struct mlx5_hlist_entry *entry,
2765                              uint64_t key __rte_unused, void *cb_ctx)
2766 {
2767         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
2768         struct mlx5_flow_dv_encap_decap_resource *resource = ctx->data;
2769         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2770
2771         cache_resource = container_of(entry,
2772                                       struct mlx5_flow_dv_encap_decap_resource,
2773                                       entry);
2774         if (resource->entry.key == cache_resource->entry.key &&
2775             resource->reformat_type == cache_resource->reformat_type &&
2776             resource->ft_type == cache_resource->ft_type &&
2777             resource->flags == cache_resource->flags &&
2778             resource->size == cache_resource->size &&
2779             !memcmp((const void *)resource->buf,
2780                     (const void *)cache_resource->buf,
2781                     resource->size))
2782                 return 0;
2783         return -1;
2784 }
2785
2786 /**
2787  * Allocate encap_decap resource.
2788  *
2789  * @param list
2790  *   Pointer to the hash list.
2791  * @param entry
2792  *   Pointer to exist resource entry object.
2793  * @param ctx_cb
2794  *   Pointer to new encap_decap resource.
2795  *
2796  * @return
2797  *   0 on matching, none-zero otherwise.
2798  */
2799 struct mlx5_hlist_entry *
2800 flow_dv_encap_decap_create_cb(struct mlx5_hlist *list,
2801                               uint64_t key __rte_unused,
2802                               void *cb_ctx)
2803 {
2804         struct mlx5_dev_ctx_shared *sh = list->ctx;
2805         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
2806         struct mlx5dv_dr_domain *domain;
2807         struct mlx5_flow_dv_encap_decap_resource *resource = ctx->data;
2808         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2809         uint32_t idx;
2810         int ret;
2811
2812         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2813                 domain = sh->fdb_domain;
2814         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2815                 domain = sh->rx_domain;
2816         else
2817                 domain = sh->tx_domain;
2818         /* Register new encap/decap resource. */
2819         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
2820                                        &idx);
2821         if (!cache_resource) {
2822                 rte_flow_error_set(ctx->error, ENOMEM,
2823                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2824                                    "cannot allocate resource memory");
2825                 return NULL;
2826         }
2827         *cache_resource = *resource;
2828         cache_resource->idx = idx;
2829         ret = mlx5_flow_os_create_flow_action_packet_reformat
2830                                         (sh->ctx, domain, cache_resource,
2831                                          &cache_resource->action);
2832         if (ret) {
2833                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);
2834                 rte_flow_error_set(ctx->error, ENOMEM,
2835                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2836                                    NULL, "cannot create action");
2837                 return NULL;
2838         }
2839
2840         return &cache_resource->entry;
2841 }
2842
2843 /**
2844  * Find existing encap/decap resource or create and register a new one.
2845  *
2846  * @param[in, out] dev
2847  *   Pointer to rte_eth_dev structure.
2848  * @param[in, out] resource
2849  *   Pointer to encap/decap resource.
2850  * @parm[in, out] dev_flow
2851  *   Pointer to the dev_flow.
2852  * @param[out] error
2853  *   pointer to error structure.
2854  *
2855  * @return
2856  *   0 on success otherwise -errno and errno is set.
2857  */
2858 static int
2859 flow_dv_encap_decap_resource_register
2860                         (struct rte_eth_dev *dev,
2861                          struct mlx5_flow_dv_encap_decap_resource *resource,
2862                          struct mlx5_flow *dev_flow,
2863                          struct rte_flow_error *error)
2864 {
2865         struct mlx5_priv *priv = dev->data->dev_private;
2866         struct mlx5_dev_ctx_shared *sh = priv->sh;
2867         struct mlx5_hlist_entry *entry;
2868         union {
2869                 struct {
2870                         uint32_t ft_type:8;
2871                         uint32_t refmt_type:8;
2872                         /*
2873                          * Header reformat actions can be shared between
2874                          * non-root tables. One bit to indicate non-root
2875                          * table or not.
2876                          */
2877                         uint32_t is_root:1;
2878                         uint32_t reserve:15;
2879                 };
2880                 uint32_t v32;
2881         } encap_decap_key = {
2882                 {
2883                         .ft_type = resource->ft_type,
2884                         .refmt_type = resource->reformat_type,
2885                         .is_root = !!dev_flow->dv.group,
2886                         .reserve = 0,
2887                 }
2888         };
2889         struct mlx5_flow_cb_ctx ctx = {
2890                 .error = error,
2891                 .data = resource,
2892         };
2893
2894         resource->flags = dev_flow->dv.group ? 0 : 1;
2895         resource->entry.key =  __rte_raw_cksum(&encap_decap_key.v32,
2896                                                sizeof(encap_decap_key.v32), 0);
2897         if (resource->reformat_type !=
2898             MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2 &&
2899             resource->size)
2900                 resource->entry.key = __rte_raw_cksum(resource->buf,
2901                                                       resource->size,
2902                                                       resource->entry.key);
2903         entry = mlx5_hlist_register(sh->encaps_decaps, resource->entry.key,
2904                                     &ctx);
2905         if (!entry)
2906                 return -rte_errno;
2907         resource = container_of(entry, typeof(*resource), entry);
2908         dev_flow->dv.encap_decap = resource;
2909         dev_flow->handle->dvh.rix_encap_decap = resource->idx;
2910         return 0;
2911 }
2912
2913 /**
2914  * Find existing table jump resource or create and register a new one.
2915  *
2916  * @param[in, out] dev
2917  *   Pointer to rte_eth_dev structure.
2918  * @param[in, out] tbl
2919  *   Pointer to flow table resource.
2920  * @parm[in, out] dev_flow
2921  *   Pointer to the dev_flow.
2922  * @param[out] error
2923  *   pointer to error structure.
2924  *
2925  * @return
2926  *   0 on success otherwise -errno and errno is set.
2927  */
2928 static int
2929 flow_dv_jump_tbl_resource_register
2930                         (struct rte_eth_dev *dev __rte_unused,
2931                          struct mlx5_flow_tbl_resource *tbl,
2932                          struct mlx5_flow *dev_flow,
2933                          struct rte_flow_error *error __rte_unused)
2934 {
2935         struct mlx5_flow_tbl_data_entry *tbl_data =
2936                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
2937
2938         MLX5_ASSERT(tbl);
2939         MLX5_ASSERT(tbl_data->jump.action);
2940         dev_flow->handle->rix_jump = tbl_data->idx;
2941         dev_flow->dv.jump = &tbl_data->jump;
2942         return 0;
2943 }
2944
2945 int
2946 flow_dv_port_id_match_cb(struct mlx5_cache_list *list __rte_unused,
2947                          struct mlx5_cache_entry *entry, void *cb_ctx)
2948 {
2949         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
2950         struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
2951         struct mlx5_flow_dv_port_id_action_resource *res =
2952                         container_of(entry, typeof(*res), entry);
2953
2954         return ref->port_id != res->port_id;
2955 }
2956
2957 struct mlx5_cache_entry *
2958 flow_dv_port_id_create_cb(struct mlx5_cache_list *list,
2959                           struct mlx5_cache_entry *entry __rte_unused,
2960                           void *cb_ctx)
2961 {
2962         struct mlx5_dev_ctx_shared *sh = list->ctx;
2963         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
2964         struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
2965         struct mlx5_flow_dv_port_id_action_resource *cache;
2966         uint32_t idx;
2967         int ret;
2968
2969         /* Register new port id action resource. */
2970         cache = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID], &idx);
2971         if (!cache) {
2972                 rte_flow_error_set(ctx->error, ENOMEM,
2973                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2974                                    "cannot allocate port_id action cache memory");
2975                 return NULL;
2976         }
2977         *cache = *ref;
2978         ret = mlx5_flow_os_create_flow_action_dest_port(sh->fdb_domain,
2979                                                         ref->port_id,
2980                                                         &cache->action);
2981         if (ret) {
2982                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], idx);
2983                 rte_flow_error_set(ctx->error, ENOMEM,
2984                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2985                                    "cannot create action");
2986                 return NULL;
2987         }
2988         return &cache->entry;
2989 }
2990
2991 /**
2992  * Find existing table port ID resource or create and register a new one.
2993  *
2994  * @param[in, out] dev
2995  *   Pointer to rte_eth_dev structure.
2996  * @param[in, out] resource
2997  *   Pointer to port ID action resource.
2998  * @parm[in, out] dev_flow
2999  *   Pointer to the dev_flow.
3000  * @param[out] error
3001  *   pointer to error structure.
3002  *
3003  * @return
3004  *   0 on success otherwise -errno and errno is set.
3005  */
3006 static int
3007 flow_dv_port_id_action_resource_register
3008                         (struct rte_eth_dev *dev,
3009                          struct mlx5_flow_dv_port_id_action_resource *resource,
3010                          struct mlx5_flow *dev_flow,
3011                          struct rte_flow_error *error)
3012 {
3013         struct mlx5_priv *priv = dev->data->dev_private;
3014         struct mlx5_cache_entry *entry;
3015         struct mlx5_flow_dv_port_id_action_resource *cache;
3016         struct mlx5_flow_cb_ctx ctx = {
3017                 .error = error,
3018                 .data = resource,
3019         };
3020
3021         entry = mlx5_cache_register(&priv->sh->port_id_action_list, &ctx);
3022         if (!entry)
3023                 return -rte_errno;
3024         cache = container_of(entry, typeof(*cache), entry);
3025         dev_flow->dv.port_id_action = cache;
3026         dev_flow->handle->rix_port_id_action = cache->idx;
3027         return 0;
3028 }
3029
3030 int
3031 flow_dv_push_vlan_match_cb(struct mlx5_cache_list *list __rte_unused,
3032                          struct mlx5_cache_entry *entry, void *cb_ctx)
3033 {
3034         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3035         struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3036         struct mlx5_flow_dv_push_vlan_action_resource *res =
3037                         container_of(entry, typeof(*res), entry);
3038
3039         return ref->vlan_tag != res->vlan_tag || ref->ft_type != res->ft_type;
3040 }
3041
3042 struct mlx5_cache_entry *
3043 flow_dv_push_vlan_create_cb(struct mlx5_cache_list *list,
3044                           struct mlx5_cache_entry *entry __rte_unused,
3045                           void *cb_ctx)
3046 {
3047         struct mlx5_dev_ctx_shared *sh = list->ctx;
3048         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3049         struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3050         struct mlx5_flow_dv_push_vlan_action_resource *cache;
3051         struct mlx5dv_dr_domain *domain;
3052         uint32_t idx;
3053         int ret;
3054
3055         /* Register new port id action resource. */
3056         cache = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN], &idx);
3057         if (!cache) {
3058                 rte_flow_error_set(ctx->error, ENOMEM,
3059                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3060                                    "cannot allocate push_vlan action cache memory");
3061                 return NULL;
3062         }
3063         *cache = *ref;
3064         if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3065                 domain = sh->fdb_domain;
3066         else if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3067                 domain = sh->rx_domain;
3068         else
3069                 domain = sh->tx_domain;
3070         ret = mlx5_flow_os_create_flow_action_push_vlan(domain, ref->vlan_tag,
3071                                                         &cache->action);
3072         if (ret) {
3073                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
3074                 rte_flow_error_set(ctx->error, ENOMEM,
3075                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3076                                    "cannot create push vlan action");
3077                 return NULL;
3078         }
3079         return &cache->entry;
3080 }
3081
3082 /**
3083  * Find existing push vlan resource or create and register a new one.
3084  *
3085  * @param [in, out] dev
3086  *   Pointer to rte_eth_dev structure.
3087  * @param[in, out] resource
3088  *   Pointer to port ID action resource.
3089  * @parm[in, out] dev_flow
3090  *   Pointer to the dev_flow.
3091  * @param[out] error
3092  *   pointer to error structure.
3093  *
3094  * @return
3095  *   0 on success otherwise -errno and errno is set.
3096  */
3097 static int
3098 flow_dv_push_vlan_action_resource_register
3099                        (struct rte_eth_dev *dev,
3100                         struct mlx5_flow_dv_push_vlan_action_resource *resource,
3101                         struct mlx5_flow *dev_flow,
3102                         struct rte_flow_error *error)
3103 {
3104         struct mlx5_priv *priv = dev->data->dev_private;
3105         struct mlx5_flow_dv_push_vlan_action_resource *cache;
3106         struct mlx5_cache_entry *entry;
3107         struct mlx5_flow_cb_ctx ctx = {
3108                 .error = error,
3109                 .data = resource,
3110         };
3111
3112         entry = mlx5_cache_register(&priv->sh->push_vlan_action_list, &ctx);
3113         if (!entry)
3114                 return -rte_errno;
3115         cache = container_of(entry, typeof(*cache), entry);
3116
3117         dev_flow->handle->dvh.rix_push_vlan = cache->idx;
3118         dev_flow->dv.push_vlan_res = cache;
3119         return 0;
3120 }
3121
3122 /**
3123  * Get the size of specific rte_flow_item_type hdr size
3124  *
3125  * @param[in] item_type
3126  *   Tested rte_flow_item_type.
3127  *
3128  * @return
3129  *   sizeof struct item_type, 0 if void or irrelevant.
3130  */
3131 static size_t
3132 flow_dv_get_item_hdr_len(const enum rte_flow_item_type item_type)
3133 {
3134         size_t retval;
3135
3136         switch (item_type) {
3137         case RTE_FLOW_ITEM_TYPE_ETH:
3138                 retval = sizeof(struct rte_ether_hdr);
3139                 break;
3140         case RTE_FLOW_ITEM_TYPE_VLAN:
3141                 retval = sizeof(struct rte_vlan_hdr);
3142                 break;
3143         case RTE_FLOW_ITEM_TYPE_IPV4:
3144                 retval = sizeof(struct rte_ipv4_hdr);
3145                 break;
3146         case RTE_FLOW_ITEM_TYPE_IPV6:
3147                 retval = sizeof(struct rte_ipv6_hdr);
3148                 break;
3149         case RTE_FLOW_ITEM_TYPE_UDP:
3150                 retval = sizeof(struct rte_udp_hdr);
3151                 break;
3152         case RTE_FLOW_ITEM_TYPE_TCP:
3153                 retval = sizeof(struct rte_tcp_hdr);
3154                 break;
3155         case RTE_FLOW_ITEM_TYPE_VXLAN:
3156         case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3157                 retval = sizeof(struct rte_vxlan_hdr);
3158                 break;
3159         case RTE_FLOW_ITEM_TYPE_GRE:
3160         case RTE_FLOW_ITEM_TYPE_NVGRE:
3161                 retval = sizeof(struct rte_gre_hdr);
3162                 break;
3163         case RTE_FLOW_ITEM_TYPE_MPLS:
3164                 retval = sizeof(struct rte_mpls_hdr);
3165                 break;
3166         case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
3167         default:
3168                 retval = 0;
3169                 break;
3170         }
3171         return retval;
3172 }
3173
3174 #define MLX5_ENCAP_IPV4_VERSION         0x40
3175 #define MLX5_ENCAP_IPV4_IHL_MIN         0x05
3176 #define MLX5_ENCAP_IPV4_TTL_DEF         0x40
3177 #define MLX5_ENCAP_IPV6_VTC_FLOW        0x60000000
3178 #define MLX5_ENCAP_IPV6_HOP_LIMIT       0xff
3179 #define MLX5_ENCAP_VXLAN_FLAGS          0x08000000
3180 #define MLX5_ENCAP_VXLAN_GPE_FLAGS      0x04
3181
3182 /**
3183  * Convert the encap action data from list of rte_flow_item to raw buffer
3184  *
3185  * @param[in] items
3186  *   Pointer to rte_flow_item objects list.
3187  * @param[out] buf
3188  *   Pointer to the output buffer.
3189  * @param[out] size
3190  *   Pointer to the output buffer size.
3191  * @param[out] error
3192  *   Pointer to the error structure.
3193  *
3194  * @return
3195  *   0 on success, a negative errno value otherwise and rte_errno is set.
3196  */
3197 static int
3198 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
3199                            size_t *size, struct rte_flow_error *error)
3200 {
3201         struct rte_ether_hdr *eth = NULL;
3202         struct rte_vlan_hdr *vlan = NULL;
3203         struct rte_ipv4_hdr *ipv4 = NULL;
3204         struct rte_ipv6_hdr *ipv6 = NULL;
3205         struct rte_udp_hdr *udp = NULL;
3206         struct rte_vxlan_hdr *vxlan = NULL;
3207         struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
3208         struct rte_gre_hdr *gre = NULL;
3209         size_t len;
3210         size_t temp_size = 0;
3211
3212         if (!items)
3213                 return rte_flow_error_set(error, EINVAL,
3214                                           RTE_FLOW_ERROR_TYPE_ACTION,
3215                                           NULL, "invalid empty data");
3216         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
3217                 len = flow_dv_get_item_hdr_len(items->type);
3218                 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
3219                         return rte_flow_error_set(error, EINVAL,
3220                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3221                                                   (void *)items->type,
3222                                                   "items total size is too big"
3223                                                   " for encap action");
3224                 rte_memcpy((void *)&buf[temp_size], items->spec, len);
3225                 switch (items->type) {
3226                 case RTE_FLOW_ITEM_TYPE_ETH:
3227                         eth = (struct rte_ether_hdr *)&buf[temp_size];
3228                         break;
3229                 case RTE_FLOW_ITEM_TYPE_VLAN:
3230                         vlan = (struct rte_vlan_hdr *)&buf[temp_size];
3231                         if (!eth)
3232                                 return rte_flow_error_set(error, EINVAL,
3233                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3234                                                 (void *)items->type,
3235                                                 "eth header not found");
3236                         if (!eth->ether_type)
3237                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
3238                         break;
3239                 case RTE_FLOW_ITEM_TYPE_IPV4:
3240                         ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
3241                         if (!vlan && !eth)
3242                                 return rte_flow_error_set(error, EINVAL,
3243                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3244                                                 (void *)items->type,
3245                                                 "neither eth nor vlan"
3246                                                 " header found");
3247                         if (vlan && !vlan->eth_proto)
3248                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3249                         else if (eth && !eth->ether_type)
3250                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3251                         if (!ipv4->version_ihl)
3252                                 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
3253                                                     MLX5_ENCAP_IPV4_IHL_MIN;
3254                         if (!ipv4->time_to_live)
3255                                 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
3256                         break;
3257                 case RTE_FLOW_ITEM_TYPE_IPV6:
3258                         ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
3259                         if (!vlan && !eth)
3260                                 return rte_flow_error_set(error, EINVAL,
3261                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3262                                                 (void *)items->type,
3263                                                 "neither eth nor vlan"
3264                                                 " header found");
3265                         if (vlan && !vlan->eth_proto)
3266                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3267                         else if (eth && !eth->ether_type)
3268                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3269                         if (!ipv6->vtc_flow)
3270                                 ipv6->vtc_flow =
3271                                         RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
3272                         if (!ipv6->hop_limits)
3273                                 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
3274                         break;
3275                 case RTE_FLOW_ITEM_TYPE_UDP:
3276                         udp = (struct rte_udp_hdr *)&buf[temp_size];
3277                         if (!ipv4 && !ipv6)
3278                                 return rte_flow_error_set(error, EINVAL,
3279                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3280                                                 (void *)items->type,
3281                                                 "ip header not found");
3282                         if (ipv4 && !ipv4->next_proto_id)
3283                                 ipv4->next_proto_id = IPPROTO_UDP;
3284                         else if (ipv6 && !ipv6->proto)
3285                                 ipv6->proto = IPPROTO_UDP;
3286                         break;
3287                 case RTE_FLOW_ITEM_TYPE_VXLAN:
3288                         vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
3289                         if (!udp)
3290                                 return rte_flow_error_set(error, EINVAL,
3291                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3292                                                 (void *)items->type,
3293                                                 "udp header not found");
3294                         if (!udp->dst_port)
3295                                 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
3296                         if (!vxlan->vx_flags)
3297                                 vxlan->vx_flags =
3298                                         RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
3299                         break;
3300                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3301                         vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
3302                         if (!udp)
3303                                 return rte_flow_error_set(error, EINVAL,
3304                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3305                                                 (void *)items->type,
3306                                                 "udp header not found");
3307                         if (!vxlan_gpe->proto)
3308                                 return rte_flow_error_set(error, EINVAL,
3309                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3310                                                 (void *)items->type,
3311                                                 "next protocol not found");
3312                         if (!udp->dst_port)
3313                                 udp->dst_port =
3314                                         RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
3315                         if (!vxlan_gpe->vx_flags)
3316                                 vxlan_gpe->vx_flags =
3317                                                 MLX5_ENCAP_VXLAN_GPE_FLAGS;
3318                         break;
3319                 case RTE_FLOW_ITEM_TYPE_GRE:
3320                 case RTE_FLOW_ITEM_TYPE_NVGRE:
3321                         gre = (struct rte_gre_hdr *)&buf[temp_size];
3322                         if (!gre->proto)
3323                                 return rte_flow_error_set(error, EINVAL,
3324                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3325                                                 (void *)items->type,
3326                                                 "next protocol not found");
3327                         if (!ipv4 && !ipv6)
3328                                 return rte_flow_error_set(error, EINVAL,
3329                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3330                                                 (void *)items->type,
3331                                                 "ip header not found");
3332                         if (ipv4 && !ipv4->next_proto_id)
3333                                 ipv4->next_proto_id = IPPROTO_GRE;
3334                         else if (ipv6 && !ipv6->proto)
3335                                 ipv6->proto = IPPROTO_GRE;
3336                         break;
3337                 case RTE_FLOW_ITEM_TYPE_VOID:
3338                         break;
3339                 default:
3340                         return rte_flow_error_set(error, EINVAL,
3341                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3342                                                   (void *)items->type,
3343                                                   "unsupported item type");
3344                         break;
3345                 }
3346                 temp_size += len;
3347         }
3348         *size = temp_size;
3349         return 0;
3350 }
3351
3352 static int
3353 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
3354 {
3355         struct rte_ether_hdr *eth = NULL;
3356         struct rte_vlan_hdr *vlan = NULL;
3357         struct rte_ipv6_hdr *ipv6 = NULL;
3358         struct rte_udp_hdr *udp = NULL;
3359         char *next_hdr;
3360         uint16_t proto;
3361
3362         eth = (struct rte_ether_hdr *)data;
3363         next_hdr = (char *)(eth + 1);
3364         proto = RTE_BE16(eth->ether_type);
3365
3366         /* VLAN skipping */
3367         while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
3368                 vlan = (struct rte_vlan_hdr *)next_hdr;
3369                 proto = RTE_BE16(vlan->eth_proto);
3370                 next_hdr += sizeof(struct rte_vlan_hdr);
3371         }
3372
3373         /* HW calculates IPv4 csum. no need to proceed */
3374         if (proto == RTE_ETHER_TYPE_IPV4)
3375                 return 0;
3376
3377         /* non IPv4/IPv6 header. not supported */
3378         if (proto != RTE_ETHER_TYPE_IPV6) {
3379                 return rte_flow_error_set(error, ENOTSUP,
3380                                           RTE_FLOW_ERROR_TYPE_ACTION,
3381                                           NULL, "Cannot offload non IPv4/IPv6");
3382         }
3383
3384         ipv6 = (struct rte_ipv6_hdr *)next_hdr;
3385
3386         /* ignore non UDP */
3387         if (ipv6->proto != IPPROTO_UDP)
3388                 return 0;
3389
3390         udp = (struct rte_udp_hdr *)(ipv6 + 1);
3391         udp->dgram_cksum = 0;
3392
3393         return 0;
3394 }
3395
3396 /**
3397  * Convert L2 encap action to DV specification.
3398  *
3399  * @param[in] dev
3400  *   Pointer to rte_eth_dev structure.
3401  * @param[in] action
3402  *   Pointer to action structure.
3403  * @param[in, out] dev_flow
3404  *   Pointer to the mlx5_flow.
3405  * @param[in] transfer
3406  *   Mark if the flow is E-Switch flow.
3407  * @param[out] error
3408  *   Pointer to the error structure.
3409  *
3410  * @return
3411  *   0 on success, a negative errno value otherwise and rte_errno is set.
3412  */
3413 static int
3414 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
3415                                const struct rte_flow_action *action,
3416                                struct mlx5_flow *dev_flow,
3417                                uint8_t transfer,
3418                                struct rte_flow_error *error)
3419 {
3420         const struct rte_flow_item *encap_data;
3421         const struct rte_flow_action_raw_encap *raw_encap_data;
3422         struct mlx5_flow_dv_encap_decap_resource res = {
3423                 .reformat_type =
3424                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
3425                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3426                                       MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
3427         };
3428
3429         if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
3430                 raw_encap_data =
3431                         (const struct rte_flow_action_raw_encap *)action->conf;
3432                 res.size = raw_encap_data->size;
3433                 memcpy(res.buf, raw_encap_data->data, res.size);
3434         } else {
3435                 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
3436                         encap_data =
3437                                 ((const struct rte_flow_action_vxlan_encap *)
3438                                                 action->conf)->definition;
3439                 else
3440                         encap_data =
3441                                 ((const struct rte_flow_action_nvgre_encap *)
3442                                                 action->conf)->definition;
3443                 if (flow_dv_convert_encap_data(encap_data, res.buf,
3444                                                &res.size, error))
3445                         return -rte_errno;
3446         }
3447         if (flow_dv_zero_encap_udp_csum(res.buf, error))
3448                 return -rte_errno;
3449         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3450                 return rte_flow_error_set(error, EINVAL,
3451                                           RTE_FLOW_ERROR_TYPE_ACTION,
3452                                           NULL, "can't create L2 encap action");
3453         return 0;
3454 }
3455
3456 /**
3457  * Convert L2 decap action to DV specification.
3458  *
3459  * @param[in] dev
3460  *   Pointer to rte_eth_dev structure.
3461  * @param[in, out] dev_flow
3462  *   Pointer to the mlx5_flow.
3463  * @param[in] transfer
3464  *   Mark if the flow is E-Switch flow.
3465  * @param[out] error
3466  *   Pointer to the error structure.
3467  *
3468  * @return
3469  *   0 on success, a negative errno value otherwise and rte_errno is set.
3470  */
3471 static int
3472 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
3473                                struct mlx5_flow *dev_flow,
3474                                uint8_t transfer,
3475                                struct rte_flow_error *error)
3476 {
3477         struct mlx5_flow_dv_encap_decap_resource res = {
3478                 .size = 0,
3479                 .reformat_type =
3480                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
3481                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3482                                       MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
3483         };
3484
3485         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3486                 return rte_flow_error_set(error, EINVAL,
3487                                           RTE_FLOW_ERROR_TYPE_ACTION,
3488                                           NULL, "can't create L2 decap action");
3489         return 0;
3490 }
3491
3492 /**
3493  * Convert raw decap/encap (L3 tunnel) action to DV specification.
3494  *
3495  * @param[in] dev
3496  *   Pointer to rte_eth_dev structure.
3497  * @param[in] action
3498  *   Pointer to action structure.
3499  * @param[in, out] dev_flow
3500  *   Pointer to the mlx5_flow.
3501  * @param[in] attr
3502  *   Pointer to the flow attributes.
3503  * @param[out] error
3504  *   Pointer to the error structure.
3505  *
3506  * @return
3507  *   0 on success, a negative errno value otherwise and rte_errno is set.
3508  */
3509 static int
3510 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
3511                                 const struct rte_flow_action *action,
3512                                 struct mlx5_flow *dev_flow,
3513                                 const struct rte_flow_attr *attr,
3514                                 struct rte_flow_error *error)
3515 {
3516         const struct rte_flow_action_raw_encap *encap_data;
3517         struct mlx5_flow_dv_encap_decap_resource res;
3518
3519         memset(&res, 0, sizeof(res));
3520         encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
3521         res.size = encap_data->size;
3522         memcpy(res.buf, encap_data->data, res.size);
3523         res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
3524                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
3525                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
3526         if (attr->transfer)
3527                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3528         else
3529                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3530                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3531         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3532                 return rte_flow_error_set(error, EINVAL,
3533                                           RTE_FLOW_ERROR_TYPE_ACTION,
3534                                           NULL, "can't create encap action");
3535         return 0;
3536 }
3537
3538 /**
3539  * Create action push VLAN.
3540  *
3541  * @param[in] dev
3542  *   Pointer to rte_eth_dev structure.
3543  * @param[in] attr
3544  *   Pointer to the flow attributes.
3545  * @param[in] vlan
3546  *   Pointer to the vlan to push to the Ethernet header.
3547  * @param[in, out] dev_flow
3548  *   Pointer to the mlx5_flow.
3549  * @param[out] error
3550  *   Pointer to the error structure.
3551  *
3552  * @return
3553  *   0 on success, a negative errno value otherwise and rte_errno is set.
3554  */
3555 static int
3556 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
3557                                 const struct rte_flow_attr *attr,
3558                                 const struct rte_vlan_hdr *vlan,
3559                                 struct mlx5_flow *dev_flow,
3560                                 struct rte_flow_error *error)
3561 {
3562         struct mlx5_flow_dv_push_vlan_action_resource res;
3563
3564         memset(&res, 0, sizeof(res));
3565         res.vlan_tag =
3566                 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
3567                                  vlan->vlan_tci);
3568         if (attr->transfer)
3569                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3570         else
3571                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3572                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3573         return flow_dv_push_vlan_action_resource_register
3574                                             (dev, &res, dev_flow, error);
3575 }
3576
3577 static int fdb_mirror;
3578
3579 /**
3580  * Validate the modify-header actions.
3581  *
3582  * @param[in] action_flags
3583  *   Holds the actions detected until now.
3584  * @param[in] action
3585  *   Pointer to the modify action.
3586  * @param[out] error
3587  *   Pointer to error structure.
3588  *
3589  * @return
3590  *   0 on success, a negative errno value otherwise and rte_errno is set.
3591  */
3592 static int
3593 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
3594                                    const struct rte_flow_action *action,
3595                                    struct rte_flow_error *error)
3596 {
3597         if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
3598                 return rte_flow_error_set(error, EINVAL,
3599                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3600                                           NULL, "action configuration not set");
3601         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3602                 return rte_flow_error_set(error, EINVAL,
3603                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3604                                           "can't have encap action before"
3605                                           " modify action");
3606         if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) && fdb_mirror)
3607                 return rte_flow_error_set(error, EINVAL,
3608                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3609                                           "can't support sample action before"
3610                                           " modify action for E-Switch"
3611                                           " mirroring");
3612         return 0;
3613 }
3614
3615 /**
3616  * Validate the modify-header MAC address actions.
3617  *
3618  * @param[in] action_flags
3619  *   Holds the actions detected until now.
3620  * @param[in] action
3621  *   Pointer to the modify action.
3622  * @param[in] item_flags
3623  *   Holds the items detected.
3624  * @param[out] error
3625  *   Pointer to error structure.
3626  *
3627  * @return
3628  *   0 on success, a negative errno value otherwise and rte_errno is set.
3629  */
3630 static int
3631 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
3632                                    const struct rte_flow_action *action,
3633                                    const uint64_t item_flags,
3634                                    struct rte_flow_error *error)
3635 {
3636         int ret = 0;
3637
3638         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3639         if (!ret) {
3640                 if (!(item_flags & MLX5_FLOW_LAYER_L2))
3641                         return rte_flow_error_set(error, EINVAL,
3642                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3643                                                   NULL,
3644                                                   "no L2 item in pattern");
3645         }
3646         return ret;
3647 }
3648
3649 /**
3650  * Validate the modify-header IPv4 address actions.
3651  *
3652  * @param[in] action_flags
3653  *   Holds the actions detected until now.
3654  * @param[in] action
3655  *   Pointer to the modify action.
3656  * @param[in] item_flags
3657  *   Holds the items detected.
3658  * @param[out] error
3659  *   Pointer to error structure.
3660  *
3661  * @return
3662  *   0 on success, a negative errno value otherwise and rte_errno is set.
3663  */
3664 static int
3665 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
3666                                     const struct rte_flow_action *action,
3667                                     const uint64_t item_flags,
3668                                     struct rte_flow_error *error)
3669 {
3670         int ret = 0;
3671         uint64_t layer;
3672
3673         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3674         if (!ret) {
3675                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3676                                  MLX5_FLOW_LAYER_INNER_L3_IPV4 :
3677                                  MLX5_FLOW_LAYER_OUTER_L3_IPV4;
3678                 if (!(item_flags & layer))
3679                         return rte_flow_error_set(error, EINVAL,
3680                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3681                                                   NULL,
3682                                                   "no ipv4 item in pattern");
3683         }
3684         return ret;
3685 }
3686
3687 /**
3688  * Validate the modify-header IPv6 address actions.
3689  *
3690  * @param[in] action_flags
3691  *   Holds the actions detected until now.
3692  * @param[in] action
3693  *   Pointer to the modify action.
3694  * @param[in] item_flags
3695  *   Holds the items detected.
3696  * @param[out] error
3697  *   Pointer to error structure.
3698  *
3699  * @return
3700  *   0 on success, a negative errno value otherwise and rte_errno is set.
3701  */
3702 static int
3703 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
3704                                     const struct rte_flow_action *action,
3705                                     const uint64_t item_flags,
3706                                     struct rte_flow_error *error)
3707 {
3708         int ret = 0;
3709         uint64_t layer;
3710
3711         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3712         if (!ret) {
3713                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3714                                  MLX5_FLOW_LAYER_INNER_L3_IPV6 :
3715                                  MLX5_FLOW_LAYER_OUTER_L3_IPV6;
3716                 if (!(item_flags & layer))
3717                         return rte_flow_error_set(error, EINVAL,
3718                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3719                                                   NULL,
3720                                                   "no ipv6 item in pattern");
3721         }
3722         return ret;
3723 }
3724
3725 /**
3726  * Validate the modify-header TP actions.
3727  *
3728  * @param[in] action_flags
3729  *   Holds the actions detected until now.
3730  * @param[in] action
3731  *   Pointer to the modify action.
3732  * @param[in] item_flags
3733  *   Holds the items detected.
3734  * @param[out] error
3735  *   Pointer to error structure.
3736  *
3737  * @return
3738  *   0 on success, a negative errno value otherwise and rte_errno is set.
3739  */
3740 static int
3741 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
3742                                   const struct rte_flow_action *action,
3743                                   const uint64_t item_flags,
3744                                   struct rte_flow_error *error)
3745 {
3746         int ret = 0;
3747         uint64_t layer;
3748
3749         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3750         if (!ret) {
3751                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3752                                  MLX5_FLOW_LAYER_INNER_L4 :
3753                                  MLX5_FLOW_LAYER_OUTER_L4;
3754                 if (!(item_flags & layer))
3755                         return rte_flow_error_set(error, EINVAL,
3756                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3757                                                   NULL, "no transport layer "
3758                                                   "in pattern");
3759         }
3760         return ret;
3761 }
3762
3763 /**
3764  * Validate the modify-header actions of increment/decrement
3765  * TCP Sequence-number.
3766  *
3767  * @param[in] action_flags
3768  *   Holds the actions detected until now.
3769  * @param[in] action
3770  *   Pointer to the modify action.
3771  * @param[in] item_flags
3772  *   Holds the items detected.
3773  * @param[out] error
3774  *   Pointer to error structure.
3775  *
3776  * @return
3777  *   0 on success, a negative errno value otherwise and rte_errno is set.
3778  */
3779 static int
3780 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
3781                                        const struct rte_flow_action *action,
3782                                        const uint64_t item_flags,
3783                                        struct rte_flow_error *error)
3784 {
3785         int ret = 0;
3786         uint64_t layer;
3787
3788         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3789         if (!ret) {
3790                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3791                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
3792                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
3793                 if (!(item_flags & layer))
3794                         return rte_flow_error_set(error, EINVAL,
3795                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3796                                                   NULL, "no TCP item in"
3797                                                   " pattern");
3798                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
3799                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
3800                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
3801                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
3802                         return rte_flow_error_set(error, EINVAL,
3803                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3804                                                   NULL,
3805                                                   "cannot decrease and increase"
3806                                                   " TCP sequence number"
3807                                                   " at the same time");
3808         }
3809         return ret;
3810 }
3811
3812 /**
3813  * Validate the modify-header actions of increment/decrement
3814  * TCP Acknowledgment number.
3815  *
3816  * @param[in] action_flags
3817  *   Holds the actions detected until now.
3818  * @param[in] action
3819  *   Pointer to the modify action.
3820  * @param[in] item_flags
3821  *   Holds the items detected.
3822  * @param[out] error
3823  *   Pointer to error structure.
3824  *
3825  * @return
3826  *   0 on success, a negative errno value otherwise and rte_errno is set.
3827  */
3828 static int
3829 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
3830                                        const struct rte_flow_action *action,
3831                                        const uint64_t item_flags,
3832                                        struct rte_flow_error *error)
3833 {
3834         int ret = 0;
3835         uint64_t layer;
3836
3837         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3838         if (!ret) {
3839                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3840                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
3841                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
3842                 if (!(item_flags & layer))
3843                         return rte_flow_error_set(error, EINVAL,
3844                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3845                                                   NULL, "no TCP item in"
3846                                                   " pattern");
3847                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
3848                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
3849                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
3850                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
3851                         return rte_flow_error_set(error, EINVAL,
3852                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3853                                                   NULL,
3854                                                   "cannot decrease and increase"
3855                                                   " TCP acknowledgment number"
3856                                                   " at the same time");
3857         }
3858         return ret;
3859 }
3860
3861 /**
3862  * Validate the modify-header TTL actions.
3863  *
3864  * @param[in] action_flags
3865  *   Holds the actions detected until now.
3866  * @param[in] action
3867  *   Pointer to the modify action.
3868  * @param[in] item_flags
3869  *   Holds the items detected.
3870  * @param[out] error
3871  *   Pointer to error structure.
3872  *
3873  * @return
3874  *   0 on success, a negative errno value otherwise and rte_errno is set.
3875  */
3876 static int
3877 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
3878                                    const struct rte_flow_action *action,
3879                                    const uint64_t item_flags,
3880                                    struct rte_flow_error *error)
3881 {
3882         int ret = 0;
3883         uint64_t layer;
3884
3885         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3886         if (!ret) {
3887                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3888                                  MLX5_FLOW_LAYER_INNER_L3 :
3889                                  MLX5_FLOW_LAYER_OUTER_L3;
3890                 if (!(item_flags & layer))
3891                         return rte_flow_error_set(error, EINVAL,
3892                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3893                                                   NULL,
3894                                                   "no IP protocol in pattern");
3895         }
3896         return ret;
3897 }
3898
3899 /**
3900  * Validate jump action.
3901  *
3902  * @param[in] action
3903  *   Pointer to the jump action.
3904  * @param[in] action_flags
3905  *   Holds the actions detected until now.
3906  * @param[in] attributes
3907  *   Pointer to flow attributes
3908  * @param[in] external
3909  *   Action belongs to flow rule created by request external to PMD.
3910  * @param[out] error
3911  *   Pointer to error structure.
3912  *
3913  * @return
3914  *   0 on success, a negative errno value otherwise and rte_errno is set.
3915  */
3916 static int
3917 flow_dv_validate_action_jump(struct rte_eth_dev *dev,
3918                              const struct mlx5_flow_tunnel *tunnel,
3919                              const struct rte_flow_action *action,
3920                              uint64_t action_flags,
3921                              const struct rte_flow_attr *attributes,
3922                              bool external, struct rte_flow_error *error)
3923 {
3924         uint32_t target_group, table;
3925         int ret = 0;
3926         struct flow_grp_info grp_info = {
3927                 .external = !!external,
3928                 .transfer = !!attributes->transfer,
3929                 .fdb_def_rule = 1,
3930                 .std_tbl_fix = 0
3931         };
3932         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3933                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3934                 return rte_flow_error_set(error, EINVAL,
3935                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3936                                           "can't have 2 fate actions in"
3937                                           " same flow");
3938         if (action_flags & MLX5_FLOW_ACTION_METER)
3939                 return rte_flow_error_set(error, ENOTSUP,
3940                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3941                                           "jump with meter not support");
3942         if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) && fdb_mirror)
3943                 return rte_flow_error_set(error, EINVAL,
3944                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3945                                           "E-Switch mirroring can't support"
3946                                           " Sample action and jump action in"
3947                                           " same flow now");
3948         if (!action->conf)
3949                 return rte_flow_error_set(error, EINVAL,
3950                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3951                                           NULL, "action configuration not set");
3952         target_group =
3953                 ((const struct rte_flow_action_jump *)action->conf)->group;
3954         ret = mlx5_flow_group_to_table(dev, tunnel, target_group, &table,
3955                                        &grp_info, error);
3956         if (ret)
3957                 return ret;
3958         if (attributes->group == target_group &&
3959             !(action_flags & (MLX5_FLOW_ACTION_TUNNEL_SET |
3960                               MLX5_FLOW_ACTION_TUNNEL_MATCH)))
3961                 return rte_flow_error_set(error, EINVAL,
3962                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3963                                           "target group must be other than"
3964                                           " the current flow group");
3965         return 0;
3966 }
3967
3968 /*
3969  * Validate the port_id action.
3970  *
3971  * @param[in] dev
3972  *   Pointer to rte_eth_dev structure.
3973  * @param[in] action_flags
3974  *   Bit-fields that holds the actions detected until now.
3975  * @param[in] action
3976  *   Port_id RTE action structure.
3977  * @param[in] attr
3978  *   Attributes of flow that includes this action.
3979  * @param[out] error
3980  *   Pointer to error structure.
3981  *
3982  * @return
3983  *   0 on success, a negative errno value otherwise and rte_errno is set.
3984  */
3985 static int
3986 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
3987                                 uint64_t action_flags,
3988                                 const struct rte_flow_action *action,
3989                                 const struct rte_flow_attr *attr,
3990                                 struct rte_flow_error *error)
3991 {
3992         const struct rte_flow_action_port_id *port_id;
3993         struct mlx5_priv *act_priv;
3994         struct mlx5_priv *dev_priv;
3995         uint16_t port;
3996
3997         if (!attr->transfer)
3998                 return rte_flow_error_set(error, ENOTSUP,
3999                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4000                                           NULL,
4001                                           "port id action is valid in transfer"
4002                                           " mode only");
4003         if (!action || !action->conf)
4004                 return rte_flow_error_set(error, ENOTSUP,
4005                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4006                                           NULL,
4007                                           "port id action parameters must be"
4008                                           " specified");
4009         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
4010                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4011                 return rte_flow_error_set(error, EINVAL,
4012                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4013                                           "can have only one fate actions in"
4014                                           " a flow");
4015         dev_priv = mlx5_dev_to_eswitch_info(dev);
4016         if (!dev_priv)
4017                 return rte_flow_error_set(error, rte_errno,
4018                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4019                                           NULL,
4020                                           "failed to obtain E-Switch info");
4021         port_id = action->conf;
4022         port = port_id->original ? dev->data->port_id : port_id->id;
4023         act_priv = mlx5_port_to_eswitch_info(port, false);
4024         if (!act_priv)
4025                 return rte_flow_error_set
4026                                 (error, rte_errno,
4027                                  RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
4028                                  "failed to obtain E-Switch port id for port");
4029         if (act_priv->domain_id != dev_priv->domain_id)
4030                 return rte_flow_error_set
4031                                 (error, EINVAL,
4032                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4033                                  "port does not belong to"
4034                                  " E-Switch being configured");
4035         return 0;
4036 }
4037
4038 /**
4039  * Get the maximum number of modify header actions.
4040  *
4041  * @param dev
4042  *   Pointer to rte_eth_dev structure.
4043  * @param flags
4044  *   Flags bits to check if root level.
4045  *
4046  * @return
4047  *   Max number of modify header actions device can support.
4048  */
4049 static inline unsigned int
4050 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev __rte_unused,
4051                               uint64_t flags)
4052 {
4053         /*
4054          * There's no way to directly query the max capacity from FW.
4055          * The maximal value on root table should be assumed to be supported.
4056          */
4057         if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
4058                 return MLX5_MAX_MODIFY_NUM;
4059         else
4060                 return MLX5_ROOT_TBL_MODIFY_NUM;
4061 }
4062
4063 /**
4064  * Validate the meter action.
4065  *
4066  * @param[in] dev
4067  *   Pointer to rte_eth_dev structure.
4068  * @param[in] action_flags
4069  *   Bit-fields that holds the actions detected until now.
4070  * @param[in] action
4071  *   Pointer to the meter action.
4072  * @param[in] attr
4073  *   Attributes of flow that includes this action.
4074  * @param[out] error
4075  *   Pointer to error structure.
4076  *
4077  * @return
4078  *   0 on success, a negative errno value otherwise and rte_ernno is set.
4079  */
4080 static int
4081 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
4082                                 uint64_t action_flags,
4083                                 const struct rte_flow_action *action,
4084                                 const struct rte_flow_attr *attr,
4085                                 struct rte_flow_error *error)
4086 {
4087         struct mlx5_priv *priv = dev->data->dev_private;
4088         const struct rte_flow_action_meter *am = action->conf;
4089         struct mlx5_flow_meter *fm;
4090
4091         if (!am)
4092                 return rte_flow_error_set(error, EINVAL,
4093                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4094                                           "meter action conf is NULL");
4095
4096         if (action_flags & MLX5_FLOW_ACTION_METER)
4097                 return rte_flow_error_set(error, ENOTSUP,
4098                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4099                                           "meter chaining not support");
4100         if (action_flags & MLX5_FLOW_ACTION_JUMP)
4101                 return rte_flow_error_set(error, ENOTSUP,
4102                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4103                                           "meter with jump not support");
4104         if (!priv->mtr_en)
4105                 return rte_flow_error_set(error, ENOTSUP,
4106                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4107                                           NULL,
4108                                           "meter action not supported");
4109         fm = mlx5_flow_meter_find(priv, am->mtr_id);
4110         if (!fm)
4111                 return rte_flow_error_set(error, EINVAL,
4112                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4113                                           "Meter not found");
4114         if (fm->ref_cnt && (!(fm->transfer == attr->transfer ||
4115               (!fm->ingress && !attr->ingress && attr->egress) ||
4116               (!fm->egress && !attr->egress && attr->ingress))))
4117                 return rte_flow_error_set(error, EINVAL,
4118                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4119                                           "Flow attributes are either invalid "
4120                                           "or have a conflict with current "
4121                                           "meter attributes");
4122         return 0;
4123 }
4124
4125 /**
4126  * Validate the age action.
4127  *
4128  * @param[in] action_flags
4129  *   Holds the actions detected until now.
4130  * @param[in] action
4131  *   Pointer to the age action.
4132  * @param[in] dev
4133  *   Pointer to the Ethernet device structure.
4134  * @param[out] error
4135  *   Pointer to error structure.
4136  *
4137  * @return
4138  *   0 on success, a negative errno value otherwise and rte_errno is set.
4139  */
4140 static int
4141 flow_dv_validate_action_age(uint64_t action_flags,
4142                             const struct rte_flow_action *action,
4143                             struct rte_eth_dev *dev,
4144                             struct rte_flow_error *error)
4145 {
4146         struct mlx5_priv *priv = dev->data->dev_private;
4147         const struct rte_flow_action_age *age = action->conf;
4148
4149         if (!priv->config.devx || (priv->sh->cmng.counter_fallback &&
4150             !priv->sh->aso_age_mng))
4151                 return rte_flow_error_set(error, ENOTSUP,
4152                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4153                                           NULL,
4154                                           "age action not supported");
4155         if (!(action->conf))
4156                 return rte_flow_error_set(error, EINVAL,
4157                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4158                                           "configuration cannot be null");
4159         if (!(age->timeout))
4160                 return rte_flow_error_set(error, EINVAL,
4161                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4162                                           "invalid timeout value 0");
4163         if (action_flags & MLX5_FLOW_ACTION_AGE)
4164                 return rte_flow_error_set(error, EINVAL,
4165                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4166                                           "duplicate age actions set");
4167         return 0;
4168 }
4169
4170 /**
4171  * Validate the modify-header IPv4 DSCP actions.
4172  *
4173  * @param[in] action_flags
4174  *   Holds the actions detected until now.
4175  * @param[in] action
4176  *   Pointer to the modify action.
4177  * @param[in] item_flags
4178  *   Holds the items detected.
4179  * @param[out] error
4180  *   Pointer to error structure.
4181  *
4182  * @return
4183  *   0 on success, a negative errno value otherwise and rte_errno is set.
4184  */
4185 static int
4186 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
4187                                          const struct rte_flow_action *action,
4188                                          const uint64_t item_flags,
4189                                          struct rte_flow_error *error)
4190 {
4191         int ret = 0;
4192
4193         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4194         if (!ret) {
4195                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
4196                         return rte_flow_error_set(error, EINVAL,
4197                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4198                                                   NULL,
4199                                                   "no ipv4 item in pattern");
4200         }
4201         return ret;
4202 }
4203
4204 /**
4205  * Validate the modify-header IPv6 DSCP actions.
4206  *
4207  * @param[in] action_flags
4208  *   Holds the actions detected until now.
4209  * @param[in] action
4210  *   Pointer to the modify action.
4211  * @param[in] item_flags
4212  *   Holds the items detected.
4213  * @param[out] error
4214  *   Pointer to error structure.
4215  *
4216  * @return
4217  *   0 on success, a negative errno value otherwise and rte_errno is set.
4218  */
4219 static int
4220 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
4221                                          const struct rte_flow_action *action,
4222                                          const uint64_t item_flags,
4223                                          struct rte_flow_error *error)
4224 {
4225         int ret = 0;
4226
4227         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4228         if (!ret) {
4229                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
4230                         return rte_flow_error_set(error, EINVAL,
4231                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4232                                                   NULL,
4233                                                   "no ipv6 item in pattern");
4234         }
4235         return ret;
4236 }
4237
4238 /**
4239  * Match modify-header resource.
4240  *
4241  * @param list
4242  *   Pointer to the hash list.
4243  * @param entry
4244  *   Pointer to exist resource entry object.
4245  * @param key
4246  *   Key of the new entry.
4247  * @param ctx
4248  *   Pointer to new modify-header resource.
4249  *
4250  * @return
4251  *   0 on matching, non-zero otherwise.
4252  */
4253 int
4254 flow_dv_modify_match_cb(struct mlx5_hlist *list __rte_unused,
4255                         struct mlx5_hlist_entry *entry,
4256                         uint64_t key __rte_unused, void *cb_ctx)
4257 {
4258         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
4259         struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
4260         struct mlx5_flow_dv_modify_hdr_resource *resource =
4261                         container_of(entry, typeof(*resource), entry);
4262         uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
4263
4264         key_len += ref->actions_num * sizeof(ref->actions[0]);
4265         return ref->actions_num != resource->actions_num ||
4266                memcmp(&ref->ft_type, &resource->ft_type, key_len);
4267 }
4268
4269 struct mlx5_hlist_entry *
4270 flow_dv_modify_create_cb(struct mlx5_hlist *list, uint64_t key __rte_unused,
4271                          void *cb_ctx)
4272 {
4273         struct mlx5_dev_ctx_shared *sh = list->ctx;
4274         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
4275         struct mlx5dv_dr_domain *ns;
4276         struct mlx5_flow_dv_modify_hdr_resource *entry;
4277         struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
4278         int ret;
4279         uint32_t data_len = ref->actions_num * sizeof(ref->actions[0]);
4280         uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
4281
4282         entry = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*entry) + data_len, 0,
4283                             SOCKET_ID_ANY);
4284         if (!entry) {
4285                 rte_flow_error_set(ctx->error, ENOMEM,
4286                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4287                                    "cannot allocate resource memory");
4288                 return NULL;
4289         }
4290         rte_memcpy(&entry->ft_type,
4291                    RTE_PTR_ADD(ref, offsetof(typeof(*ref), ft_type)),
4292                    key_len + data_len);
4293         if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
4294                 ns = sh->fdb_domain;
4295         else if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
4296                 ns = sh->tx_domain;
4297         else
4298                 ns = sh->rx_domain;
4299         ret = mlx5_flow_os_create_flow_action_modify_header
4300                                         (sh->ctx, ns, entry,
4301                                          data_len, &entry->action);
4302         if (ret) {
4303                 mlx5_free(entry);
4304                 rte_flow_error_set(ctx->error, ENOMEM,
4305                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4306                                    NULL, "cannot create modification action");
4307                 return NULL;
4308         }
4309         return &entry->entry;
4310 }
4311
4312 /**
4313  * Validate the sample action.
4314  *
4315  * @param[in] action_flags
4316  *   Holds the actions detected until now.
4317  * @param[in] action
4318  *   Pointer to the sample action.
4319  * @param[in] dev
4320  *   Pointer to the Ethernet device structure.
4321  * @param[in] attr
4322  *   Attributes of flow that includes this action.
4323  * @param[out] error
4324  *   Pointer to error structure.
4325  *
4326  * @return
4327  *   0 on success, a negative errno value otherwise and rte_errno is set.
4328  */
4329 static int
4330 flow_dv_validate_action_sample(uint64_t action_flags,
4331                                const struct rte_flow_action *action,
4332                                struct rte_eth_dev *dev,
4333                                const struct rte_flow_attr *attr,
4334                                struct rte_flow_error *error)
4335 {
4336         struct mlx5_priv *priv = dev->data->dev_private;
4337         struct mlx5_dev_config *dev_conf = &priv->config;
4338         const struct rte_flow_action_sample *sample = action->conf;
4339         const struct rte_flow_action *act;
4340         uint64_t sub_action_flags = 0;
4341         uint16_t queue_index = 0xFFFF;
4342         int actions_n = 0;
4343         int ret;
4344         fdb_mirror = 0;
4345
4346         if (!sample)
4347                 return rte_flow_error_set(error, EINVAL,
4348                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4349                                           "configuration cannot be NULL");
4350         if (sample->ratio == 0)
4351                 return rte_flow_error_set(error, EINVAL,
4352                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4353                                           "ratio value starts from 1");
4354         if (!priv->config.devx || (sample->ratio > 0 && !priv->sampler_en))
4355                 return rte_flow_error_set(error, ENOTSUP,
4356                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4357                                           NULL,
4358                                           "sample action not supported");
4359         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
4360                 return rte_flow_error_set(error, EINVAL,
4361                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4362                                           "Multiple sample actions not "
4363                                           "supported");
4364         if (action_flags & MLX5_FLOW_ACTION_METER)
4365                 return rte_flow_error_set(error, EINVAL,
4366                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4367                                           "wrong action order, meter should "
4368                                           "be after sample action");
4369         if (action_flags & MLX5_FLOW_ACTION_JUMP)
4370                 return rte_flow_error_set(error, EINVAL,
4371                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4372                                           "wrong action order, jump should "
4373                                           "be after sample action");
4374         act = sample->actions;
4375         for (; act->type != RTE_FLOW_ACTION_TYPE_END; act++) {
4376                 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
4377                         return rte_flow_error_set(error, ENOTSUP,
4378                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4379                                                   act, "too many actions");
4380                 switch (act->type) {
4381                 case RTE_FLOW_ACTION_TYPE_QUEUE:
4382                         ret = mlx5_flow_validate_action_queue(act,
4383                                                               sub_action_flags,
4384                                                               dev,
4385                                                               attr, error);
4386                         if (ret < 0)
4387                                 return ret;
4388                         queue_index = ((const struct rte_flow_action_queue *)
4389                                                         (act->conf))->index;
4390                         sub_action_flags |= MLX5_FLOW_ACTION_QUEUE;
4391                         ++actions_n;
4392                         break;
4393                 case RTE_FLOW_ACTION_TYPE_MARK:
4394                         ret = flow_dv_validate_action_mark(dev, act,
4395                                                            sub_action_flags,
4396                                                            attr, error);
4397                         if (ret < 0)
4398                                 return ret;
4399                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY)
4400                                 sub_action_flags |= MLX5_FLOW_ACTION_MARK |
4401                                                 MLX5_FLOW_ACTION_MARK_EXT;
4402                         else
4403                                 sub_action_flags |= MLX5_FLOW_ACTION_MARK;
4404                         ++actions_n;
4405                         break;
4406                 case RTE_FLOW_ACTION_TYPE_COUNT:
4407                         ret = flow_dv_validate_action_count(dev, error);
4408                         if (ret < 0)
4409                                 return ret;
4410                         sub_action_flags |= MLX5_FLOW_ACTION_COUNT;
4411                         ++actions_n;
4412                         break;
4413                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
4414                         ret = flow_dv_validate_action_port_id(dev,
4415                                                               sub_action_flags,
4416                                                               act,
4417                                                               attr,
4418                                                               error);
4419                         if (ret)
4420                                 return ret;
4421                         sub_action_flags |= MLX5_FLOW_ACTION_PORT_ID;
4422                         ++actions_n;
4423                         break;
4424                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
4425                         ret = flow_dv_validate_action_raw_encap_decap
4426                                 (dev, NULL, act->conf, attr, &sub_action_flags,
4427                                  &actions_n, error);
4428                         if (ret < 0)
4429                                 return ret;
4430                         ++actions_n;
4431                         break;
4432                 default:
4433                         return rte_flow_error_set(error, ENOTSUP,
4434                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4435                                                   NULL,
4436                                                   "Doesn't support optional "
4437                                                   "action");
4438                 }
4439         }
4440         if (attr->ingress && !attr->transfer) {
4441                 if (!(sub_action_flags & MLX5_FLOW_ACTION_QUEUE))
4442                         return rte_flow_error_set(error, EINVAL,
4443                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4444                                                   NULL,
4445                                                   "Ingress must has a dest "
4446                                                   "QUEUE for Sample");
4447         } else if (attr->egress && !attr->transfer) {
4448                 return rte_flow_error_set(error, ENOTSUP,
4449                                           RTE_FLOW_ERROR_TYPE_ACTION,
4450                                           NULL,
4451                                           "Sample Only support Ingress "
4452                                           "or E-Switch");
4453         } else if (sample->actions->type != RTE_FLOW_ACTION_TYPE_END) {
4454                 MLX5_ASSERT(attr->transfer);
4455                 if (sample->ratio > 1)
4456                         return rte_flow_error_set(error, ENOTSUP,
4457                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4458                                                   NULL,
4459                                                   "E-Switch doesn't support "
4460                                                   "any optional action "
4461                                                   "for sampling");
4462                 fdb_mirror = 1;
4463                 if (sub_action_flags & MLX5_FLOW_ACTION_QUEUE)
4464                         return rte_flow_error_set(error, ENOTSUP,
4465                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4466                                                   NULL,
4467                                                   "unsupported action QUEUE");
4468                 if (!(sub_action_flags & MLX5_FLOW_ACTION_PORT_ID))
4469                         return rte_flow_error_set(error, EINVAL,
4470                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4471                                                   NULL,
4472                                                   "E-Switch must has a dest "
4473                                                   "port for mirroring");
4474         }
4475         /* Continue validation for Xcap actions.*/
4476         if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) &&
4477             (queue_index == 0xFFFF ||
4478              mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
4479                 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
4480                      MLX5_FLOW_XCAP_ACTIONS)
4481                         return rte_flow_error_set(error, ENOTSUP,
4482                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4483                                                   NULL, "encap and decap "
4484                                                   "combination aren't "
4485                                                   "supported");
4486                 if (!attr->transfer && attr->ingress && (sub_action_flags &
4487                                                         MLX5_FLOW_ACTION_ENCAP))
4488                         return rte_flow_error_set(error, ENOTSUP,
4489                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4490                                                   NULL, "encap is not supported"
4491                                                   " for ingress traffic");
4492         }
4493         return 0;
4494 }
4495
4496 /**
4497  * Find existing modify-header resource or create and register a new one.
4498  *
4499  * @param dev[in, out]
4500  *   Pointer to rte_eth_dev structure.
4501  * @param[in, out] resource
4502  *   Pointer to modify-header resource.
4503  * @parm[in, out] dev_flow
4504  *   Pointer to the dev_flow.
4505  * @param[out] error
4506  *   pointer to error structure.
4507  *
4508  * @return
4509  *   0 on success otherwise -errno and errno is set.
4510  */
4511 static int
4512 flow_dv_modify_hdr_resource_register
4513                         (struct rte_eth_dev *dev,
4514                          struct mlx5_flow_dv_modify_hdr_resource *resource,
4515                          struct mlx5_flow *dev_flow,
4516                          struct rte_flow_error *error)
4517 {
4518         struct mlx5_priv *priv = dev->data->dev_private;
4519         struct mlx5_dev_ctx_shared *sh = priv->sh;
4520         uint32_t key_len = sizeof(*resource) -
4521                            offsetof(typeof(*resource), ft_type) +
4522                            resource->actions_num * sizeof(resource->actions[0]);
4523         struct mlx5_hlist_entry *entry;
4524         struct mlx5_flow_cb_ctx ctx = {
4525                 .error = error,
4526                 .data = resource,
4527         };
4528
4529         resource->flags = dev_flow->dv.group ? 0 :
4530                           MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
4531         if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
4532                                     resource->flags))
4533                 return rte_flow_error_set(error, EOVERFLOW,
4534                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4535                                           "too many modify header items");
4536         resource->entry.key = __rte_raw_cksum(&resource->ft_type, key_len, 0);
4537         entry = mlx5_hlist_register(sh->modify_cmds, resource->entry.key, &ctx);
4538         if (!entry)
4539                 return -rte_errno;
4540         resource = container_of(entry, typeof(*resource), entry);
4541         dev_flow->handle->dvh.modify_hdr = resource;
4542         return 0;
4543 }
4544
4545 /**
4546  * Get DV flow counter by index.
4547  *
4548  * @param[in] dev
4549  *   Pointer to the Ethernet device structure.
4550  * @param[in] idx
4551  *   mlx5 flow counter index in the container.
4552  * @param[out] ppool
4553  *   mlx5 flow counter pool in the container,
4554  *
4555  * @return
4556  *   Pointer to the counter, NULL otherwise.
4557  */
4558 static struct mlx5_flow_counter *
4559 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
4560                            uint32_t idx,
4561                            struct mlx5_flow_counter_pool **ppool)
4562 {
4563         struct mlx5_priv *priv = dev->data->dev_private;
4564         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4565         struct mlx5_flow_counter_pool *pool;
4566
4567         /* Decrease to original index and clear shared bit. */
4568         idx = (idx - 1) & (MLX5_CNT_SHARED_OFFSET - 1);
4569         MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cmng->n);
4570         pool = cmng->pools[idx / MLX5_COUNTERS_PER_POOL];
4571         MLX5_ASSERT(pool);
4572         if (ppool)
4573                 *ppool = pool;
4574         return MLX5_POOL_GET_CNT(pool, idx % MLX5_COUNTERS_PER_POOL);
4575 }
4576
4577 /**
4578  * Check the devx counter belongs to the pool.
4579  *
4580  * @param[in] pool
4581  *   Pointer to the counter pool.
4582  * @param[in] id
4583  *   The counter devx ID.
4584  *
4585  * @return
4586  *   True if counter belongs to the pool, false otherwise.
4587  */
4588 static bool
4589 flow_dv_is_counter_in_pool(struct mlx5_flow_counter_pool *pool, int id)
4590 {
4591         int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
4592                    MLX5_COUNTERS_PER_POOL;
4593
4594         if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
4595                 return true;
4596         return false;
4597 }
4598
4599 /**
4600  * Get a pool by devx counter ID.
4601  *
4602  * @param[in] cmng
4603  *   Pointer to the counter management.
4604  * @param[in] id
4605  *   The counter devx ID.
4606  *
4607  * @return
4608  *   The counter pool pointer if exists, NULL otherwise,
4609  */
4610 static struct mlx5_flow_counter_pool *
4611 flow_dv_find_pool_by_id(struct mlx5_flow_counter_mng *cmng, int id)
4612 {
4613         uint32_t i;
4614         struct mlx5_flow_counter_pool *pool = NULL;
4615
4616         rte_spinlock_lock(&cmng->pool_update_sl);
4617         /* Check last used pool. */
4618         if (cmng->last_pool_idx != POOL_IDX_INVALID &&
4619             flow_dv_is_counter_in_pool(cmng->pools[cmng->last_pool_idx], id)) {
4620                 pool = cmng->pools[cmng->last_pool_idx];
4621                 goto out;
4622         }
4623         /* ID out of range means no suitable pool in the container. */
4624         if (id > cmng->max_id || id < cmng->min_id)
4625                 goto out;
4626         /*
4627          * Find the pool from the end of the container, since mostly counter
4628          * ID is sequence increasing, and the last pool should be the needed
4629          * one.
4630          */
4631         i = cmng->n_valid;
4632         while (i--) {
4633                 struct mlx5_flow_counter_pool *pool_tmp = cmng->pools[i];
4634
4635                 if (flow_dv_is_counter_in_pool(pool_tmp, id)) {
4636                         pool = pool_tmp;
4637                         break;
4638                 }
4639         }
4640 out:
4641         rte_spinlock_unlock(&cmng->pool_update_sl);
4642         return pool;
4643 }
4644
4645 /**
4646  * Resize a counter container.
4647  *
4648  * @param[in] dev
4649  *   Pointer to the Ethernet device structure.
4650  *
4651  * @return
4652  *   0 on success, otherwise negative errno value and rte_errno is set.
4653  */
4654 static int
4655 flow_dv_container_resize(struct rte_eth_dev *dev)
4656 {
4657         struct mlx5_priv *priv = dev->data->dev_private;
4658         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4659         void *old_pools = cmng->pools;
4660         uint32_t resize = cmng->n + MLX5_CNT_CONTAINER_RESIZE;
4661         uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
4662         void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
4663
4664         if (!pools) {
4665                 rte_errno = ENOMEM;
4666                 return -ENOMEM;
4667         }
4668         if (old_pools)
4669                 memcpy(pools, old_pools, cmng->n *
4670                                        sizeof(struct mlx5_flow_counter_pool *));
4671         cmng->n = resize;
4672         cmng->pools = pools;
4673         if (old_pools)
4674                 mlx5_free(old_pools);
4675         return 0;
4676 }
4677
4678 /**
4679  * Query a devx flow counter.
4680  *
4681  * @param[in] dev
4682  *   Pointer to the Ethernet device structure.
4683  * @param[in] cnt
4684  *   Index to the flow counter.
4685  * @param[out] pkts
4686  *   The statistics value of packets.
4687  * @param[out] bytes
4688  *   The statistics value of bytes.
4689  *
4690  * @return
4691  *   0 on success, otherwise a negative errno value and rte_errno is set.
4692  */
4693 static inline int
4694 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
4695                      uint64_t *bytes)
4696 {
4697         struct mlx5_priv *priv = dev->data->dev_private;
4698         struct mlx5_flow_counter_pool *pool = NULL;
4699         struct mlx5_flow_counter *cnt;
4700         int offset;
4701
4702         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
4703         MLX5_ASSERT(pool);
4704         if (priv->sh->cmng.counter_fallback)
4705                 return mlx5_devx_cmd_flow_counter_query(cnt->dcs_when_active, 0,
4706                                         0, pkts, bytes, 0, NULL, NULL, 0);
4707         rte_spinlock_lock(&pool->sl);
4708         if (!pool->raw) {
4709                 *pkts = 0;
4710                 *bytes = 0;
4711         } else {
4712                 offset = MLX5_CNT_ARRAY_IDX(pool, cnt);
4713                 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
4714                 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
4715         }
4716         rte_spinlock_unlock(&pool->sl);
4717         return 0;
4718 }
4719
4720 /**
4721  * Create and initialize a new counter pool.
4722  *
4723  * @param[in] dev
4724  *   Pointer to the Ethernet device structure.
4725  * @param[out] dcs
4726  *   The devX counter handle.
4727  * @param[in] age
4728  *   Whether the pool is for counter that was allocated for aging.
4729  * @param[in/out] cont_cur
4730  *   Pointer to the container pointer, it will be update in pool resize.
4731  *
4732  * @return
4733  *   The pool container pointer on success, NULL otherwise and rte_errno is set.
4734  */
4735 static struct mlx5_flow_counter_pool *
4736 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
4737                     uint32_t age)
4738 {
4739         struct mlx5_priv *priv = dev->data->dev_private;
4740         struct mlx5_flow_counter_pool *pool;
4741         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4742         bool fallback = priv->sh->cmng.counter_fallback;
4743         uint32_t size = sizeof(*pool);
4744
4745         size += MLX5_COUNTERS_PER_POOL * MLX5_CNT_SIZE;
4746         size += (!age ? 0 : MLX5_COUNTERS_PER_POOL * MLX5_AGE_SIZE);
4747         pool = mlx5_malloc(MLX5_MEM_ZERO, size, 0, SOCKET_ID_ANY);
4748         if (!pool) {
4749                 rte_errno = ENOMEM;
4750                 return NULL;
4751         }
4752         pool->raw = NULL;
4753         pool->is_aged = !!age;
4754         pool->query_gen = 0;
4755         pool->min_dcs = dcs;
4756         rte_spinlock_init(&pool->sl);
4757         rte_spinlock_init(&pool->csl);
4758         TAILQ_INIT(&pool->counters[0]);
4759         TAILQ_INIT(&pool->counters[1]);
4760         pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
4761         rte_spinlock_lock(&cmng->pool_update_sl);
4762         pool->index = cmng->n_valid;
4763         if (pool->index == cmng->n && flow_dv_container_resize(dev)) {
4764                 mlx5_free(pool);
4765                 rte_spinlock_unlock(&cmng->pool_update_sl);
4766                 return NULL;
4767         }
4768         cmng->pools[pool->index] = pool;
4769         cmng->n_valid++;
4770         if (unlikely(fallback)) {
4771                 int base = RTE_ALIGN_FLOOR(dcs->id, MLX5_COUNTERS_PER_POOL);
4772
4773                 if (base < cmng->min_id)
4774                         cmng->min_id = base;
4775                 if (base > cmng->max_id)
4776                         cmng->max_id = base + MLX5_COUNTERS_PER_POOL - 1;
4777                 cmng->last_pool_idx = pool->index;
4778         }
4779         rte_spinlock_unlock(&cmng->pool_update_sl);
4780         return pool;
4781 }
4782
4783 /**
4784  * Prepare a new counter and/or a new counter pool.
4785  *
4786  * @param[in] dev
4787  *   Pointer to the Ethernet device structure.
4788  * @param[out] cnt_free
4789  *   Where to put the pointer of a new counter.
4790  * @param[in] age
4791  *   Whether the pool is for counter that was allocated for aging.
4792  *
4793  * @return
4794  *   The counter pool pointer and @p cnt_free is set on success,
4795  *   NULL otherwise and rte_errno is set.
4796  */
4797 static struct mlx5_flow_counter_pool *
4798 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
4799                              struct mlx5_flow_counter **cnt_free,
4800                              uint32_t age)
4801 {
4802         struct mlx5_priv *priv = dev->data->dev_private;
4803         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4804         struct mlx5_flow_counter_pool *pool;
4805         struct mlx5_counters tmp_tq;
4806         struct mlx5_devx_obj *dcs = NULL;
4807         struct mlx5_flow_counter *cnt;
4808         enum mlx5_counter_type cnt_type =
4809                         age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
4810         bool fallback = priv->sh->cmng.counter_fallback;
4811         uint32_t i;
4812
4813         if (fallback) {
4814                 /* bulk_bitmap must be 0 for single counter allocation. */
4815                 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
4816                 if (!dcs)
4817                         return NULL;
4818                 pool = flow_dv_find_pool_by_id(cmng, dcs->id);
4819                 if (!pool) {
4820                         pool = flow_dv_pool_create(dev, dcs, age);
4821                         if (!pool) {
4822                                 mlx5_devx_cmd_destroy(dcs);
4823                                 return NULL;
4824                         }
4825                 }
4826                 i = dcs->id % MLX5_COUNTERS_PER_POOL;
4827                 cnt = MLX5_POOL_GET_CNT(pool, i);
4828                 cnt->pool = pool;
4829                 cnt->dcs_when_free = dcs;
4830                 *cnt_free = cnt;
4831                 return pool;
4832         }
4833         dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
4834         if (!dcs) {
4835                 rte_errno = ENODATA;
4836                 return NULL;
4837         }
4838         pool = flow_dv_pool_create(dev, dcs, age);
4839         if (!pool) {
4840                 mlx5_devx_cmd_destroy(dcs);
4841                 return NULL;
4842         }
4843         TAILQ_INIT(&tmp_tq);
4844         for (i = 1; i < MLX5_COUNTERS_PER_POOL; ++i) {
4845                 cnt = MLX5_POOL_GET_CNT(pool, i);
4846                 cnt->pool = pool;
4847                 TAILQ_INSERT_HEAD(&tmp_tq, cnt, next);
4848         }
4849         rte_spinlock_lock(&cmng->csl[cnt_type]);
4850         TAILQ_CONCAT(&cmng->counters[cnt_type], &tmp_tq, next);
4851         rte_spinlock_unlock(&cmng->csl[cnt_type]);
4852         *cnt_free = MLX5_POOL_GET_CNT(pool, 0);
4853         (*cnt_free)->pool = pool;
4854         return pool;
4855 }
4856
4857 /**
4858  * Allocate a flow counter.
4859  *
4860  * @param[in] dev
4861  *   Pointer to the Ethernet device structure.
4862  * @param[in] age
4863  *   Whether the counter was allocated for aging.
4864  *
4865  * @return
4866  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
4867  */
4868 static uint32_t
4869 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t age)
4870 {
4871         struct mlx5_priv *priv = dev->data->dev_private;
4872         struct mlx5_flow_counter_pool *pool = NULL;
4873         struct mlx5_flow_counter *cnt_free = NULL;
4874         bool fallback = priv->sh->cmng.counter_fallback;
4875         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4876         enum mlx5_counter_type cnt_type =
4877                         age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
4878         uint32_t cnt_idx;
4879
4880         if (!priv->config.devx) {
4881                 rte_errno = ENOTSUP;
4882                 return 0;
4883         }
4884         /* Get free counters from container. */
4885         rte_spinlock_lock(&cmng->csl[cnt_type]);
4886         cnt_free = TAILQ_FIRST(&cmng->counters[cnt_type]);
4887         if (cnt_free)
4888                 TAILQ_REMOVE(&cmng->counters[cnt_type], cnt_free, next);
4889         rte_spinlock_unlock(&cmng->csl[cnt_type]);
4890         if (!cnt_free && !flow_dv_counter_pool_prepare(dev, &cnt_free, age))
4891                 goto err;
4892         pool = cnt_free->pool;
4893         if (fallback)
4894                 cnt_free->dcs_when_active = cnt_free->dcs_when_free;
4895         /* Create a DV counter action only in the first time usage. */
4896         if (!cnt_free->action) {
4897                 uint16_t offset;
4898                 struct mlx5_devx_obj *dcs;
4899                 int ret;
4900
4901                 if (!fallback) {
4902                         offset = MLX5_CNT_ARRAY_IDX(pool, cnt_free);
4903                         dcs = pool->min_dcs;
4904                 } else {
4905                         offset = 0;
4906                         dcs = cnt_free->dcs_when_free;
4907                 }
4908                 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, offset,
4909                                                             &cnt_free->action);
4910                 if (ret) {
4911                         rte_errno = errno;
4912                         goto err;
4913                 }
4914         }
4915         cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
4916                                 MLX5_CNT_ARRAY_IDX(pool, cnt_free));
4917         /* Update the counter reset values. */
4918         if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
4919                                  &cnt_free->bytes))
4920                 goto err;
4921         if (!fallback && !priv->sh->cmng.query_thread_on)
4922                 /* Start the asynchronous batch query by the host thread. */
4923                 mlx5_set_query_alarm(priv->sh);
4924         return cnt_idx;
4925 err:
4926         if (cnt_free) {
4927                 cnt_free->pool = pool;
4928                 if (fallback)
4929                         cnt_free->dcs_when_free = cnt_free->dcs_when_active;
4930                 rte_spinlock_lock(&cmng->csl[cnt_type]);
4931                 TAILQ_INSERT_TAIL(&cmng->counters[cnt_type], cnt_free, next);
4932                 rte_spinlock_unlock(&cmng->csl[cnt_type]);
4933         }
4934         return 0;
4935 }
4936
4937 /**
4938  * Allocate a shared flow counter.
4939  *
4940  * @param[in] ctx
4941  *   Pointer to the shared counter configuration.
4942  * @param[in] data
4943  *   Pointer to save the allocated counter index.
4944  *
4945  * @return
4946  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
4947  */
4948
4949 static int32_t
4950 flow_dv_counter_alloc_shared_cb(void *ctx, union mlx5_l3t_data *data)
4951 {
4952         struct mlx5_shared_counter_conf *conf = ctx;
4953         struct rte_eth_dev *dev = conf->dev;
4954         struct mlx5_flow_counter *cnt;
4955
4956         data->dword = flow_dv_counter_alloc(dev, 0);
4957         data->dword |= MLX5_CNT_SHARED_OFFSET;
4958         cnt = flow_dv_counter_get_by_idx(dev, data->dword, NULL);
4959         cnt->shared_info.id = conf->id;
4960         return 0;
4961 }
4962
4963 /**
4964  * Get a shared flow counter.
4965  *
4966  * @param[in] dev
4967  *   Pointer to the Ethernet device structure.
4968  * @param[in] id
4969  *   Counter identifier.
4970  *
4971  * @return
4972  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
4973  */
4974 static uint32_t
4975 flow_dv_counter_get_shared(struct rte_eth_dev *dev, uint32_t id)
4976 {
4977         struct mlx5_priv *priv = dev->data->dev_private;
4978         struct mlx5_shared_counter_conf conf = {
4979                 .dev = dev,
4980                 .id = id,
4981         };
4982         union mlx5_l3t_data data = {
4983                 .dword = 0,
4984         };
4985
4986         mlx5_l3t_prepare_entry(priv->sh->cnt_id_tbl, id, &data,
4987                                flow_dv_counter_alloc_shared_cb, &conf);
4988         return data.dword;
4989 }
4990
4991 /**
4992  * Get age param from counter index.
4993  *
4994  * @param[in] dev
4995  *   Pointer to the Ethernet device structure.
4996  * @param[in] counter
4997  *   Index to the counter handler.
4998  *
4999  * @return
5000  *   The aging parameter specified for the counter index.
5001  */
5002 static struct mlx5_age_param*
5003 flow_dv_counter_idx_get_age(struct rte_eth_dev *dev,
5004                                 uint32_t counter)
5005 {
5006         struct mlx5_flow_counter *cnt;
5007         struct mlx5_flow_counter_pool *pool = NULL;
5008
5009         flow_dv_counter_get_by_idx(dev, counter, &pool);
5010         counter = (counter - 1) % MLX5_COUNTERS_PER_POOL;
5011         cnt = MLX5_POOL_GET_CNT(pool, counter);
5012         return MLX5_CNT_TO_AGE(cnt);
5013 }
5014
5015 /**
5016  * Remove a flow counter from aged counter list.
5017  *
5018  * @param[in] dev
5019  *   Pointer to the Ethernet device structure.
5020  * @param[in] counter
5021  *   Index to the counter handler.
5022  * @param[in] cnt
5023  *   Pointer to the counter handler.
5024  */
5025 static void
5026 flow_dv_counter_remove_from_age(struct rte_eth_dev *dev,
5027                                 uint32_t counter, struct mlx5_flow_counter *cnt)
5028 {
5029         struct mlx5_age_info *age_info;
5030         struct mlx5_age_param *age_param;
5031         struct mlx5_priv *priv = dev->data->dev_private;
5032         uint16_t expected = AGE_CANDIDATE;
5033
5034         age_info = GET_PORT_AGE_INFO(priv);
5035         age_param = flow_dv_counter_idx_get_age(dev, counter);
5036         if (!__atomic_compare_exchange_n(&age_param->state, &expected,
5037                                          AGE_FREE, false, __ATOMIC_RELAXED,
5038                                          __ATOMIC_RELAXED)) {
5039                 /**
5040                  * We need the lock even it is age timeout,
5041                  * since counter may still in process.
5042                  */
5043                 rte_spinlock_lock(&age_info->aged_sl);
5044                 TAILQ_REMOVE(&age_info->aged_counters, cnt, next);
5045                 rte_spinlock_unlock(&age_info->aged_sl);
5046                 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
5047         }
5048 }
5049
5050 /**
5051  * Release a flow counter.
5052  *
5053  * @param[in] dev
5054  *   Pointer to the Ethernet device structure.
5055  * @param[in] counter
5056  *   Index to the counter handler.
5057  */
5058 static void
5059 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t counter)
5060 {
5061         struct mlx5_priv *priv = dev->data->dev_private;
5062         struct mlx5_flow_counter_pool *pool = NULL;
5063         struct mlx5_flow_counter *cnt;
5064         enum mlx5_counter_type cnt_type;
5065
5066         if (!counter)
5067                 return;
5068         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
5069         MLX5_ASSERT(pool);
5070         if (IS_SHARED_CNT(counter) &&
5071             mlx5_l3t_clear_entry(priv->sh->cnt_id_tbl, cnt->shared_info.id))
5072                 return;
5073         if (pool->is_aged)
5074                 flow_dv_counter_remove_from_age(dev, counter, cnt);
5075         cnt->pool = pool;
5076         /*
5077          * Put the counter back to list to be updated in none fallback mode.
5078          * Currently, we are using two list alternately, while one is in query,
5079          * add the freed counter to the other list based on the pool query_gen
5080          * value. After query finishes, add counter the list to the global
5081          * container counter list. The list changes while query starts. In
5082          * this case, lock will not be needed as query callback and release
5083          * function both operate with the different list.
5084          *
5085          */
5086         if (!priv->sh->cmng.counter_fallback) {
5087                 rte_spinlock_lock(&pool->csl);
5088                 TAILQ_INSERT_TAIL(&pool->counters[pool->query_gen], cnt, next);
5089                 rte_spinlock_unlock(&pool->csl);
5090         } else {
5091                 cnt->dcs_when_free = cnt->dcs_when_active;
5092                 cnt_type = pool->is_aged ? MLX5_COUNTER_TYPE_AGE :
5093                                            MLX5_COUNTER_TYPE_ORIGIN;
5094                 rte_spinlock_lock(&priv->sh->cmng.csl[cnt_type]);
5095                 TAILQ_INSERT_TAIL(&priv->sh->cmng.counters[cnt_type],
5096                                   cnt, next);
5097                 rte_spinlock_unlock(&priv->sh->cmng.csl[cnt_type]);
5098         }
5099 }
5100
5101 /**
5102  * Verify the @p attributes will be correctly understood by the NIC and store
5103  * them in the @p flow if everything is correct.
5104  *
5105  * @param[in] dev
5106  *   Pointer to dev struct.
5107  * @param[in] attributes
5108  *   Pointer to flow attributes
5109  * @param[in] external
5110  *   This flow rule is created by request external to PMD.
5111  * @param[out] error
5112  *   Pointer to error structure.
5113  *
5114  * @return
5115  *   - 0 on success and non root table.
5116  *   - 1 on success and root table.
5117  *   - a negative errno value otherwise and rte_errno is set.
5118  */
5119 static int
5120 flow_dv_validate_attributes(struct rte_eth_dev *dev,
5121                             const struct mlx5_flow_tunnel *tunnel,
5122                             const struct rte_flow_attr *attributes,
5123                             const struct flow_grp_info *grp_info,
5124                             struct rte_flow_error *error)
5125 {
5126         struct mlx5_priv *priv = dev->data->dev_private;
5127         uint32_t priority_max = priv->config.flow_prio - 1;
5128         int ret = 0;
5129
5130 #ifndef HAVE_MLX5DV_DR
5131         RTE_SET_USED(tunnel);
5132         RTE_SET_USED(grp_info);
5133         if (attributes->group)
5134                 return rte_flow_error_set(error, ENOTSUP,
5135                                           RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
5136                                           NULL,
5137                                           "groups are not supported");
5138 #else
5139         uint32_t table = 0;
5140
5141         ret = mlx5_flow_group_to_table(dev, tunnel, attributes->group, &table,
5142                                        grp_info, error);
5143         if (ret)
5144                 return ret;
5145         if (!table)
5146                 ret = MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
5147 #endif
5148         if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
5149             attributes->priority >= priority_max)
5150                 return rte_flow_error_set(error, ENOTSUP,
5151                                           RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
5152                                           NULL,
5153                                           "priority out of range");
5154         if (attributes->transfer) {
5155                 if (!priv->config.dv_esw_en)
5156                         return rte_flow_error_set
5157                                 (error, ENOTSUP,
5158                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5159                                  "E-Switch dr is not supported");
5160                 if (!(priv->representor || priv->master))
5161                         return rte_flow_error_set
5162                                 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5163                                  NULL, "E-Switch configuration can only be"
5164                                  " done by a master or a representor device");
5165                 if (attributes->egress)
5166                         return rte_flow_error_set
5167                                 (error, ENOTSUP,
5168                                  RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
5169                                  "egress is not supported");
5170         }
5171         if (!(attributes->egress ^ attributes->ingress))
5172                 return rte_flow_error_set(error, ENOTSUP,
5173                                           RTE_FLOW_ERROR_TYPE_ATTR, NULL,
5174                                           "must specify exactly one of "
5175                                           "ingress or egress");
5176         return ret;
5177 }
5178
5179 /**
5180  * Internal validation function. For validating both actions and items.
5181  *
5182  * @param[in] dev
5183  *   Pointer to the rte_eth_dev structure.
5184  * @param[in] attr
5185  *   Pointer to the flow attributes.
5186  * @param[in] items
5187  *   Pointer to the list of items.
5188  * @param[in] actions
5189  *   Pointer to the list of actions.
5190  * @param[in] external
5191  *   This flow rule is created by request external to PMD.
5192  * @param[in] hairpin
5193  *   Number of hairpin TX actions, 0 means classic flow.
5194  * @param[out] error
5195  *   Pointer to the error structure.
5196  *
5197  * @return
5198  *   0 on success, a negative errno value otherwise and rte_errno is set.
5199  */
5200 static int
5201 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
5202                  const struct rte_flow_item items[],
5203                  const struct rte_flow_action actions[],
5204                  bool external, int hairpin, struct rte_flow_error *error)
5205 {
5206         int ret;
5207         uint64_t action_flags = 0;
5208         uint64_t item_flags = 0;
5209         uint64_t last_item = 0;
5210         uint8_t next_protocol = 0xff;
5211         uint16_t ether_type = 0;
5212         int actions_n = 0;
5213         uint8_t item_ipv6_proto = 0;
5214         const struct rte_flow_item *gre_item = NULL;
5215         const struct rte_flow_action_raw_decap *decap;
5216         const struct rte_flow_action_raw_encap *encap;
5217         const struct rte_flow_action_rss *rss;
5218         const struct rte_flow_item_tcp nic_tcp_mask = {
5219                 .hdr = {
5220                         .tcp_flags = 0xFF,
5221                         .src_port = RTE_BE16(UINT16_MAX),
5222                         .dst_port = RTE_BE16(UINT16_MAX),
5223                 }
5224         };
5225         const struct rte_flow_item_ipv6 nic_ipv6_mask = {
5226                 .hdr = {
5227                         .src_addr =
5228                         "\xff\xff\xff\xff\xff\xff\xff\xff"
5229                         "\xff\xff\xff\xff\xff\xff\xff\xff",
5230                         .dst_addr =
5231                         "\xff\xff\xff\xff\xff\xff\xff\xff"
5232                         "\xff\xff\xff\xff\xff\xff\xff\xff",
5233                         .vtc_flow = RTE_BE32(0xffffffff),
5234                         .proto = 0xff,
5235                         .hop_limits = 0xff,
5236                 },
5237                 .has_frag_ext = 1,
5238         };
5239         const struct rte_flow_item_ecpri nic_ecpri_mask = {
5240                 .hdr = {
5241                         .common = {
5242                                 .u32 =
5243                                 RTE_BE32(((const struct rte_ecpri_common_hdr) {
5244                                         .type = 0xFF,
5245                                         }).u32),
5246                         },
5247                         .dummy[0] = 0xffffffff,
5248                 },
5249         };
5250         struct mlx5_priv *priv = dev->data->dev_private;
5251         struct mlx5_dev_config *dev_conf = &priv->config;
5252         uint16_t queue_index = 0xFFFF;
5253         const struct rte_flow_item_vlan *vlan_m = NULL;
5254         int16_t rw_act_num = 0;
5255         uint64_t is_root;
5256         const struct mlx5_flow_tunnel *tunnel;
5257         struct flow_grp_info grp_info = {
5258                 .external = !!external,
5259                 .transfer = !!attr->transfer,
5260                 .fdb_def_rule = !!priv->fdb_def_rule,
5261         };
5262         const struct rte_eth_hairpin_conf *conf;
5263
5264         if (items == NULL)
5265                 return -1;
5266         if (is_flow_tunnel_match_rule(dev, attr, items, actions)) {
5267                 tunnel = flow_items_to_tunnel(items);
5268                 action_flags |= MLX5_FLOW_ACTION_TUNNEL_MATCH |
5269                                 MLX5_FLOW_ACTION_DECAP;
5270         } else if (is_flow_tunnel_steer_rule(dev, attr, items, actions)) {
5271                 tunnel = flow_actions_to_tunnel(actions);
5272                 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
5273         } else {
5274                 tunnel = NULL;
5275         }
5276         grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
5277                                 (dev, tunnel, attr, items, actions);
5278         ret = flow_dv_validate_attributes(dev, tunnel, attr, &grp_info, error);
5279         if (ret < 0)
5280                 return ret;
5281         is_root = (uint64_t)ret;
5282         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
5283                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
5284                 int type = items->type;
5285
5286                 if (!mlx5_flow_os_item_supported(type))
5287                         return rte_flow_error_set(error, ENOTSUP,
5288                                                   RTE_FLOW_ERROR_TYPE_ITEM,
5289                                                   NULL, "item not supported");
5290                 switch (type) {
5291                 case MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL:
5292                         if (items[0].type != (typeof(items[0].type))
5293                                                 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL)
5294                                 return rte_flow_error_set
5295                                                 (error, EINVAL,
5296                                                 RTE_FLOW_ERROR_TYPE_ITEM,
5297                                                 NULL, "MLX5 private items "
5298                                                 "must be the first");
5299                         break;
5300                 case RTE_FLOW_ITEM_TYPE_VOID:
5301                         break;
5302                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
5303                         ret = flow_dv_validate_item_port_id
5304                                         (dev, items, attr, item_flags, error);
5305                         if (ret < 0)
5306                                 return ret;
5307                         last_item = MLX5_FLOW_ITEM_PORT_ID;
5308                         break;
5309                 case RTE_FLOW_ITEM_TYPE_ETH:
5310                         ret = mlx5_flow_validate_item_eth(items, item_flags,
5311                                                           true, error);
5312                         if (ret < 0)
5313                                 return ret;
5314                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
5315                                              MLX5_FLOW_LAYER_OUTER_L2;
5316                         if (items->mask != NULL && items->spec != NULL) {
5317                                 ether_type =
5318                                         ((const struct rte_flow_item_eth *)
5319                                          items->spec)->type;
5320                                 ether_type &=
5321                                         ((const struct rte_flow_item_eth *)
5322                                          items->mask)->type;
5323                                 ether_type = rte_be_to_cpu_16(ether_type);
5324                         } else {
5325                                 ether_type = 0;
5326                         }
5327                         break;
5328                 case RTE_FLOW_ITEM_TYPE_VLAN:
5329                         ret = flow_dv_validate_item_vlan(items, item_flags,
5330                                                          dev, error);
5331                         if (ret < 0)
5332                                 return ret;
5333                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
5334                                              MLX5_FLOW_LAYER_OUTER_VLAN;
5335                         if (items->mask != NULL && items->spec != NULL) {
5336                                 ether_type =
5337                                         ((const struct rte_flow_item_vlan *)
5338                                          items->spec)->inner_type;
5339                                 ether_type &=
5340                                         ((const struct rte_flow_item_vlan *)
5341                                          items->mask)->inner_type;
5342                                 ether_type = rte_be_to_cpu_16(ether_type);
5343                         } else {
5344                                 ether_type = 0;
5345                         }
5346                         /* Store outer VLAN mask for of_push_vlan action. */
5347                         if (!tunnel)
5348                                 vlan_m = items->mask;
5349                         break;
5350                 case RTE_FLOW_ITEM_TYPE_IPV4:
5351                         mlx5_flow_tunnel_ip_check(items, next_protocol,
5352                                                   &item_flags, &tunnel);
5353                         ret = flow_dv_validate_item_ipv4(items, item_flags,
5354                                                          last_item, ether_type,
5355                                                          error);
5356                         if (ret < 0)
5357                                 return ret;
5358                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
5359                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
5360                         if (items->mask != NULL &&
5361                             ((const struct rte_flow_item_ipv4 *)
5362                              items->mask)->hdr.next_proto_id) {
5363                                 next_protocol =
5364                                         ((const struct rte_flow_item_ipv4 *)
5365                                          (items->spec))->hdr.next_proto_id;
5366                                 next_protocol &=
5367                                         ((const struct rte_flow_item_ipv4 *)
5368                                          (items->mask))->hdr.next_proto_id;
5369                         } else {
5370                                 /* Reset for inner layer. */
5371                                 next_protocol = 0xff;
5372                         }
5373                         break;
5374                 case RTE_FLOW_ITEM_TYPE_IPV6:
5375                         mlx5_flow_tunnel_ip_check(items, next_protocol,
5376                                                   &item_flags, &tunnel);
5377                         ret = mlx5_flow_validate_item_ipv6(items, item_flags,
5378                                                            last_item,
5379                                                            ether_type,
5380                                                            &nic_ipv6_mask,
5381                                                            error);
5382                         if (ret < 0)
5383                                 return ret;
5384                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
5385                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
5386                         if (items->mask != NULL &&
5387                             ((const struct rte_flow_item_ipv6 *)
5388                              items->mask)->hdr.proto) {
5389                                 item_ipv6_proto =
5390                                         ((const struct rte_flow_item_ipv6 *)
5391                                          items->spec)->hdr.proto;
5392                                 next_protocol =
5393                                         ((const struct rte_flow_item_ipv6 *)
5394                                          items->spec)->hdr.proto;
5395                                 next_protocol &=
5396                                         ((const struct rte_flow_item_ipv6 *)
5397                                          items->mask)->hdr.proto;
5398                         } else {
5399                                 /* Reset for inner layer. */
5400                                 next_protocol = 0xff;
5401                         }
5402                         break;
5403                 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
5404                         ret = flow_dv_validate_item_ipv6_frag_ext(items,
5405                                                                   item_flags,
5406                                                                   error);
5407                         if (ret < 0)
5408                                 return ret;
5409                         last_item = tunnel ?
5410                                         MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
5411                                         MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
5412                         if (items->mask != NULL &&
5413                             ((const struct rte_flow_item_ipv6_frag_ext *)
5414                              items->mask)->hdr.next_header) {
5415                                 next_protocol =
5416                                 ((const struct rte_flow_item_ipv6_frag_ext *)
5417                                  items->spec)->hdr.next_header;
5418                                 next_protocol &=
5419                                 ((const struct rte_flow_item_ipv6_frag_ext *)
5420                                  items->mask)->hdr.next_header;
5421                         } else {
5422                                 /* Reset for inner layer. */
5423                                 next_protocol = 0xff;
5424                         }
5425                         break;
5426                 case RTE_FLOW_ITEM_TYPE_TCP:
5427                         ret = mlx5_flow_validate_item_tcp
5428                                                 (items, item_flags,
5429                                                  next_protocol,
5430                                                  &nic_tcp_mask,
5431                                                  error);
5432                         if (ret < 0)
5433                                 return ret;
5434                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
5435                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
5436                         break;
5437                 case RTE_FLOW_ITEM_TYPE_UDP:
5438                         ret = mlx5_flow_validate_item_udp(items, item_flags,
5439                                                           next_protocol,
5440                                                           error);
5441                         if (ret < 0)
5442                                 return ret;
5443                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
5444                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
5445                         break;
5446                 case RTE_FLOW_ITEM_TYPE_GRE:
5447                         ret = mlx5_flow_validate_item_gre(items, item_flags,
5448                                                           next_protocol, error);
5449                         if (ret < 0)
5450                                 return ret;
5451                         gre_item = items;
5452                         last_item = MLX5_FLOW_LAYER_GRE;
5453                         break;
5454                 case RTE_FLOW_ITEM_TYPE_NVGRE:
5455                         ret = mlx5_flow_validate_item_nvgre(items, item_flags,
5456                                                             next_protocol,
5457                                                             error);
5458                         if (ret < 0)
5459                                 return ret;
5460                         last_item = MLX5_FLOW_LAYER_NVGRE;
5461                         break;
5462                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
5463                         ret = mlx5_flow_validate_item_gre_key
5464                                 (items, item_flags, gre_item, error);
5465                         if (ret < 0)
5466                                 return ret;
5467                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
5468                         break;
5469                 case RTE_FLOW_ITEM_TYPE_VXLAN:
5470                         ret = mlx5_flow_validate_item_vxlan(items, item_flags,
5471                                                             error);
5472                         if (ret < 0)
5473                                 return ret;
5474                         last_item = MLX5_FLOW_LAYER_VXLAN;
5475                         break;
5476                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
5477                         ret = mlx5_flow_validate_item_vxlan_gpe(items,
5478                                                                 item_flags, dev,
5479                                                                 error);
5480                         if (ret < 0)
5481                                 return ret;
5482                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
5483                         break;
5484                 case RTE_FLOW_ITEM_TYPE_GENEVE:
5485                         ret = mlx5_flow_validate_item_geneve(items,
5486                                                              item_flags, dev,
5487                                                              error);
5488                         if (ret < 0)
5489                                 return ret;
5490                         last_item = MLX5_FLOW_LAYER_GENEVE;
5491                         break;
5492                 case RTE_FLOW_ITEM_TYPE_MPLS:
5493                         ret = mlx5_flow_validate_item_mpls(dev, items,
5494                                                            item_flags,
5495                                                            last_item, error);
5496                         if (ret < 0)
5497                                 return ret;
5498                         last_item = MLX5_FLOW_LAYER_MPLS;
5499                         break;
5500
5501                 case RTE_FLOW_ITEM_TYPE_MARK:
5502                         ret = flow_dv_validate_item_mark(dev, items, attr,
5503                                                          error);
5504                         if (ret < 0)
5505                                 return ret;
5506                         last_item = MLX5_FLOW_ITEM_MARK;
5507                         break;
5508                 case RTE_FLOW_ITEM_TYPE_META:
5509                         ret = flow_dv_validate_item_meta(dev, items, attr,
5510                                                          error);
5511                         if (ret < 0)
5512                                 return ret;
5513                         last_item = MLX5_FLOW_ITEM_METADATA;
5514                         break;
5515                 case RTE_FLOW_ITEM_TYPE_ICMP:
5516                         ret = mlx5_flow_validate_item_icmp(items, item_flags,
5517                                                            next_protocol,
5518                                                            error);
5519                         if (ret < 0)
5520                                 return ret;
5521                         last_item = MLX5_FLOW_LAYER_ICMP;
5522                         break;
5523                 case RTE_FLOW_ITEM_TYPE_ICMP6:
5524                         ret = mlx5_flow_validate_item_icmp6(items, item_flags,
5525                                                             next_protocol,
5526                                                             error);
5527                         if (ret < 0)
5528                                 return ret;
5529                         item_ipv6_proto = IPPROTO_ICMPV6;
5530                         last_item = MLX5_FLOW_LAYER_ICMP6;
5531                         break;
5532                 case RTE_FLOW_ITEM_TYPE_TAG:
5533                         ret = flow_dv_validate_item_tag(dev, items,
5534                                                         attr, error);
5535                         if (ret < 0)
5536                                 return ret;
5537                         last_item = MLX5_FLOW_ITEM_TAG;
5538                         break;
5539                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
5540                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
5541                         break;
5542                 case RTE_FLOW_ITEM_TYPE_GTP:
5543                         ret = flow_dv_validate_item_gtp(dev, items, item_flags,
5544                                                         error);
5545                         if (ret < 0)
5546                                 return ret;
5547                         last_item = MLX5_FLOW_LAYER_GTP;
5548                         break;
5549                 case RTE_FLOW_ITEM_TYPE_ECPRI:
5550                         /* Capacity will be checked in the translate stage. */
5551                         ret = mlx5_flow_validate_item_ecpri(items, item_flags,
5552                                                             last_item,
5553                                                             ether_type,
5554                                                             &nic_ecpri_mask,
5555                                                             error);
5556                         if (ret < 0)
5557                                 return ret;
5558                         last_item = MLX5_FLOW_LAYER_ECPRI;
5559                         break;
5560                 default:
5561                         return rte_flow_error_set(error, ENOTSUP,
5562                                                   RTE_FLOW_ERROR_TYPE_ITEM,
5563                                                   NULL, "item not supported");
5564                 }
5565                 item_flags |= last_item;
5566         }
5567         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
5568                 int type = actions->type;
5569
5570                 if (!mlx5_flow_os_action_supported(type))
5571                         return rte_flow_error_set(error, ENOTSUP,
5572                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5573                                                   actions,
5574                                                   "action not supported");
5575                 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
5576                         return rte_flow_error_set(error, ENOTSUP,
5577                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5578                                                   actions, "too many actions");
5579                 switch (type) {
5580                 case RTE_FLOW_ACTION_TYPE_VOID:
5581                         break;
5582                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5583                         ret = flow_dv_validate_action_port_id(dev,
5584                                                               action_flags,
5585                                                               actions,
5586                                                               attr,
5587                                                               error);
5588                         if (ret)
5589                                 return ret;
5590                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5591                         ++actions_n;
5592                         break;
5593                 case RTE_FLOW_ACTION_TYPE_FLAG:
5594                         ret = flow_dv_validate_action_flag(dev, action_flags,
5595                                                            attr, error);
5596                         if (ret < 0)
5597                                 return ret;
5598                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
5599                                 /* Count all modify-header actions as one. */
5600                                 if (!(action_flags &
5601                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
5602                                         ++actions_n;
5603                                 action_flags |= MLX5_FLOW_ACTION_FLAG |
5604                                                 MLX5_FLOW_ACTION_MARK_EXT;
5605                         } else {
5606                                 action_flags |= MLX5_FLOW_ACTION_FLAG;
5607                                 ++actions_n;
5608                         }
5609                         rw_act_num += MLX5_ACT_NUM_SET_MARK;
5610                         break;
5611                 case RTE_FLOW_ACTION_TYPE_MARK:
5612                         ret = flow_dv_validate_action_mark(dev, actions,
5613                                                            action_flags,
5614                                                            attr, error);
5615                         if (ret < 0)
5616                                 return ret;
5617                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
5618                                 /* Count all modify-header actions as one. */
5619                                 if (!(action_flags &
5620                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
5621                                         ++actions_n;
5622                                 action_flags |= MLX5_FLOW_ACTION_MARK |
5623                                                 MLX5_FLOW_ACTION_MARK_EXT;
5624                         } else {
5625                                 action_flags |= MLX5_FLOW_ACTION_MARK;
5626                                 ++actions_n;
5627                         }
5628                         rw_act_num += MLX5_ACT_NUM_SET_MARK;
5629                         break;
5630                 case RTE_FLOW_ACTION_TYPE_SET_META:
5631                         ret = flow_dv_validate_action_set_meta(dev, actions,
5632                                                                action_flags,
5633                                                                attr, error);
5634                         if (ret < 0)
5635                                 return ret;
5636                         /* Count all modify-header actions as one action. */
5637                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5638                                 ++actions_n;
5639                         action_flags |= MLX5_FLOW_ACTION_SET_META;
5640                         rw_act_num += MLX5_ACT_NUM_SET_META;
5641                         break;
5642                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
5643                         ret = flow_dv_validate_action_set_tag(dev, actions,
5644                                                               action_flags,
5645                                                               attr, error);
5646                         if (ret < 0)
5647                                 return ret;
5648                         /* Count all modify-header actions as one action. */
5649                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5650                                 ++actions_n;
5651                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
5652                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
5653                         break;
5654                 case RTE_FLOW_ACTION_TYPE_DROP:
5655                         ret = mlx5_flow_validate_action_drop(action_flags,
5656                                                              attr, error);
5657                         if (ret < 0)
5658                                 return ret;
5659                         action_flags |= MLX5_FLOW_ACTION_DROP;
5660                         ++actions_n;
5661                         break;
5662                 case RTE_FLOW_ACTION_TYPE_QUEUE:
5663                         ret = mlx5_flow_validate_action_queue(actions,
5664                                                               action_flags, dev,
5665                                                               attr, error);
5666                         if (ret < 0)
5667                                 return ret;
5668                         queue_index = ((const struct rte_flow_action_queue *)
5669                                                         (actions->conf))->index;
5670                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
5671                         ++actions_n;
5672                         break;
5673                 case RTE_FLOW_ACTION_TYPE_RSS:
5674                         rss = actions->conf;
5675                         ret = mlx5_flow_validate_action_rss(actions,
5676                                                             action_flags, dev,
5677                                                             attr, item_flags,
5678                                                             error);
5679                         if (ret < 0)
5680                                 return ret;
5681                         if (rss != NULL && rss->queue_num)
5682                                 queue_index = rss->queue[0];
5683                         action_flags |= MLX5_FLOW_ACTION_RSS;
5684                         ++actions_n;
5685                         break;
5686                 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
5687                         ret =
5688                         mlx5_flow_validate_action_default_miss(action_flags,
5689                                         attr, error);
5690                         if (ret < 0)
5691                                 return ret;
5692                         action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
5693                         ++actions_n;
5694                         break;
5695                 case RTE_FLOW_ACTION_TYPE_COUNT:
5696                         ret = flow_dv_validate_action_count(dev, error);
5697                         if (ret < 0)
5698                                 return ret;
5699                         action_flags |= MLX5_FLOW_ACTION_COUNT;
5700                         ++actions_n;
5701                         break;
5702                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
5703                         if (flow_dv_validate_action_pop_vlan(dev,
5704                                                              action_flags,
5705                                                              actions,
5706                                                              item_flags, attr,
5707                                                              error))
5708                                 return -rte_errno;
5709                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
5710                         ++actions_n;
5711                         break;
5712                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
5713                         ret = flow_dv_validate_action_push_vlan(dev,
5714                                                                 action_flags,
5715                                                                 vlan_m,
5716                                                                 actions, attr,
5717                                                                 error);
5718                         if (ret < 0)
5719                                 return ret;
5720                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
5721                         ++actions_n;
5722                         break;
5723                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
5724                         ret = flow_dv_validate_action_set_vlan_pcp
5725                                                 (action_flags, actions, error);
5726                         if (ret < 0)
5727                                 return ret;
5728                         /* Count PCP with push_vlan command. */
5729                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
5730                         break;
5731                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
5732                         ret = flow_dv_validate_action_set_vlan_vid
5733                                                 (item_flags, action_flags,
5734                                                  actions, error);
5735                         if (ret < 0)
5736                                 return ret;
5737                         /* Count VID with push_vlan command. */
5738                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
5739                         rw_act_num += MLX5_ACT_NUM_MDF_VID;
5740                         break;
5741                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5742                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5743                         ret = flow_dv_validate_action_l2_encap(dev,
5744                                                                action_flags,
5745                                                                actions, attr,
5746                                                                error);
5747                         if (ret < 0)
5748                                 return ret;
5749                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
5750                         ++actions_n;
5751                         break;
5752                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
5753                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
5754                         ret = flow_dv_validate_action_decap(dev, action_flags,
5755                                                             attr, error);
5756                         if (ret < 0)
5757                                 return ret;
5758                         action_flags |= MLX5_FLOW_ACTION_DECAP;
5759                         ++actions_n;
5760                         break;
5761                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5762                         ret = flow_dv_validate_action_raw_encap_decap
5763                                 (dev, NULL, actions->conf, attr, &action_flags,
5764                                  &actions_n, error);
5765                         if (ret < 0)
5766                                 return ret;
5767                         break;
5768                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
5769                         decap = actions->conf;
5770                         while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
5771                                 ;
5772                         if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
5773                                 encap = NULL;
5774                                 actions--;
5775                         } else {
5776                                 encap = actions->conf;
5777                         }
5778                         ret = flow_dv_validate_action_raw_encap_decap
5779                                            (dev,
5780                                             decap ? decap : &empty_decap, encap,
5781                                             attr, &action_flags, &actions_n,
5782                                             error);
5783                         if (ret < 0)
5784                                 return ret;
5785                         break;
5786                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
5787                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
5788                         ret = flow_dv_validate_action_modify_mac(action_flags,
5789                                                                  actions,
5790                                                                  item_flags,
5791                                                                  error);
5792                         if (ret < 0)
5793                                 return ret;
5794                         /* Count all modify-header actions as one action. */
5795                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5796                                 ++actions_n;
5797                         action_flags |= actions->type ==
5798                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
5799                                                 MLX5_FLOW_ACTION_SET_MAC_SRC :
5800                                                 MLX5_FLOW_ACTION_SET_MAC_DST;
5801                         /*
5802                          * Even if the source and destination MAC addresses have
5803                          * overlap in the header with 4B alignment, the convert
5804                          * function will handle them separately and 4 SW actions
5805                          * will be created. And 2 actions will be added each
5806                          * time no matter how many bytes of address will be set.
5807                          */
5808                         rw_act_num += MLX5_ACT_NUM_MDF_MAC;
5809                         break;
5810                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
5811                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
5812                         ret = flow_dv_validate_action_modify_ipv4(action_flags,
5813                                                                   actions,
5814                                                                   item_flags,
5815                                                                   error);
5816                         if (ret < 0)
5817                                 return ret;
5818                         /* Count all modify-header actions as one action. */
5819                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5820                                 ++actions_n;
5821                         action_flags |= actions->type ==
5822                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
5823                                                 MLX5_FLOW_ACTION_SET_IPV4_SRC :
5824                                                 MLX5_FLOW_ACTION_SET_IPV4_DST;
5825                         rw_act_num += MLX5_ACT_NUM_MDF_IPV4;
5826                         break;
5827                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
5828                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
5829                         ret = flow_dv_validate_action_modify_ipv6(action_flags,
5830                                                                   actions,
5831                                                                   item_flags,
5832                                                                   error);
5833                         if (ret < 0)
5834                                 return ret;
5835                         if (item_ipv6_proto == IPPROTO_ICMPV6)
5836                                 return rte_flow_error_set(error, ENOTSUP,
5837                                         RTE_FLOW_ERROR_TYPE_ACTION,
5838                                         actions,
5839                                         "Can't change header "
5840                                         "with ICMPv6 proto");
5841                         /* Count all modify-header actions as one action. */
5842                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5843                                 ++actions_n;
5844                         action_flags |= actions->type ==
5845                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
5846                                                 MLX5_FLOW_ACTION_SET_IPV6_SRC :
5847                                                 MLX5_FLOW_ACTION_SET_IPV6_DST;
5848                         rw_act_num += MLX5_ACT_NUM_MDF_IPV6;
5849                         break;
5850                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
5851                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
5852                         ret = flow_dv_validate_action_modify_tp(action_flags,
5853                                                                 actions,
5854                                                                 item_flags,
5855                                                                 error);
5856                         if (ret < 0)
5857                                 return ret;
5858                         /* Count all modify-header actions as one action. */
5859                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5860                                 ++actions_n;
5861                         action_flags |= actions->type ==
5862                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
5863                                                 MLX5_FLOW_ACTION_SET_TP_SRC :
5864                                                 MLX5_FLOW_ACTION_SET_TP_DST;
5865                         rw_act_num += MLX5_ACT_NUM_MDF_PORT;
5866                         break;
5867                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
5868                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
5869                         ret = flow_dv_validate_action_modify_ttl(action_flags,
5870                                                                  actions,
5871                                                                  item_flags,
5872                                                                  error);
5873                         if (ret < 0)
5874                                 return ret;
5875                         /* Count all modify-header actions as one action. */
5876                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5877                                 ++actions_n;
5878                         action_flags |= actions->type ==
5879                                         RTE_FLOW_ACTION_TYPE_SET_TTL ?
5880                                                 MLX5_FLOW_ACTION_SET_TTL :
5881                                                 MLX5_FLOW_ACTION_DEC_TTL;
5882                         rw_act_num += MLX5_ACT_NUM_MDF_TTL;
5883                         break;
5884                 case RTE_FLOW_ACTION_TYPE_JUMP:
5885                         ret = flow_dv_validate_action_jump(dev, tunnel, actions,
5886                                                            action_flags,
5887                                                            attr, external,
5888                                                            error);
5889                         if (ret)
5890                                 return ret;
5891                         ++actions_n;
5892                         action_flags |= MLX5_FLOW_ACTION_JUMP;
5893                         break;
5894                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
5895                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
5896                         ret = flow_dv_validate_action_modify_tcp_seq
5897                                                                 (action_flags,
5898                                                                  actions,
5899                                                                  item_flags,
5900                                                                  error);
5901                         if (ret < 0)
5902                                 return ret;
5903                         /* Count all modify-header actions as one action. */
5904                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5905                                 ++actions_n;
5906                         action_flags |= actions->type ==
5907                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
5908                                                 MLX5_FLOW_ACTION_INC_TCP_SEQ :
5909                                                 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
5910                         rw_act_num += MLX5_ACT_NUM_MDF_TCPSEQ;
5911                         break;
5912                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
5913                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
5914                         ret = flow_dv_validate_action_modify_tcp_ack
5915                                                                 (action_flags,
5916                                                                  actions,
5917                                                                  item_flags,
5918                                                                  error);
5919                         if (ret < 0)
5920                                 return ret;
5921                         /* Count all modify-header actions as one action. */
5922                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5923                                 ++actions_n;
5924                         action_flags |= actions->type ==
5925                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
5926                                                 MLX5_FLOW_ACTION_INC_TCP_ACK :
5927                                                 MLX5_FLOW_ACTION_DEC_TCP_ACK;
5928                         rw_act_num += MLX5_ACT_NUM_MDF_TCPACK;
5929                         break;
5930                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
5931                         break;
5932                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
5933                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
5934                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
5935                         break;
5936                 case RTE_FLOW_ACTION_TYPE_METER:
5937                         ret = mlx5_flow_validate_action_meter(dev,
5938                                                               action_flags,
5939                                                               actions, attr,
5940                                                               error);
5941                         if (ret < 0)
5942                                 return ret;
5943                         action_flags |= MLX5_FLOW_ACTION_METER;
5944                         ++actions_n;
5945                         /* Meter action will add one more TAG action. */
5946                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
5947                         break;
5948                 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
5949                         if (!attr->group)
5950                                 return rte_flow_error_set(error, ENOTSUP,
5951                                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5952                                                                            NULL,
5953                           "Shared ASO age action is not supported for group 0");
5954                         action_flags |= MLX5_FLOW_ACTION_AGE;
5955                         ++actions_n;
5956                         break;
5957                 case RTE_FLOW_ACTION_TYPE_AGE:
5958                         ret = flow_dv_validate_action_age(action_flags,
5959                                                           actions, dev,
5960                                                           error);
5961                         if (ret < 0)
5962                                 return ret;
5963                         action_flags |= MLX5_FLOW_ACTION_AGE;
5964                         ++actions_n;
5965                         break;
5966                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
5967                         ret = flow_dv_validate_action_modify_ipv4_dscp
5968                                                          (action_flags,
5969                                                           actions,
5970                                                           item_flags,
5971                                                           error);
5972                         if (ret < 0)
5973                                 return ret;
5974                         /* Count all modify-header actions as one action. */
5975                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5976                                 ++actions_n;
5977                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
5978                         rw_act_num += MLX5_ACT_NUM_SET_DSCP;
5979                         break;
5980                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
5981                         ret = flow_dv_validate_action_modify_ipv6_dscp
5982                                                                 (action_flags,
5983                                                                  actions,
5984                                                                  item_flags,
5985                                                                  error);
5986                         if (ret < 0)
5987                                 return ret;
5988                         /* Count all modify-header actions as one action. */
5989                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5990                                 ++actions_n;
5991                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
5992                         rw_act_num += MLX5_ACT_NUM_SET_DSCP;
5993                         break;
5994                 case RTE_FLOW_ACTION_TYPE_SAMPLE:
5995                         ret = flow_dv_validate_action_sample(action_flags,
5996                                                              actions, dev,
5997                                                              attr, error);
5998                         if (ret < 0)
5999                                 return ret;
6000                         action_flags |= MLX5_FLOW_ACTION_SAMPLE;
6001                         ++actions_n;
6002                         break;
6003                 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
6004                         if (actions[0].type != (typeof(actions[0].type))
6005                                 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET)
6006                                 return rte_flow_error_set
6007                                                 (error, EINVAL,
6008                                                 RTE_FLOW_ERROR_TYPE_ACTION,
6009                                                 NULL, "MLX5 private action "
6010                                                 "must be the first");
6011
6012                         action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
6013                         break;
6014                 default:
6015                         return rte_flow_error_set(error, ENOTSUP,
6016                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6017                                                   actions,
6018                                                   "action not supported");
6019                 }
6020         }
6021         /*
6022          * Validate actions in flow rules
6023          * - Explicit decap action is prohibited by the tunnel offload API.
6024          * - Drop action in tunnel steer rule is prohibited by the API.
6025          * - Application cannot use MARK action because it's value can mask
6026          *   tunnel default miss nitification.
6027          * - JUMP in tunnel match rule has no support in current PMD
6028          *   implementation.
6029          * - TAG & META are reserved for future uses.
6030          */
6031         if (action_flags & MLX5_FLOW_ACTION_TUNNEL_SET) {
6032                 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_DECAP    |
6033                                             MLX5_FLOW_ACTION_MARK     |
6034                                             MLX5_FLOW_ACTION_SET_TAG  |
6035                                             MLX5_FLOW_ACTION_SET_META |
6036                                             MLX5_FLOW_ACTION_DROP;
6037
6038                 if (action_flags & bad_actions_mask)
6039                         return rte_flow_error_set
6040                                         (error, EINVAL,
6041                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6042                                         "Invalid RTE action in tunnel "
6043                                         "set decap rule");
6044                 if (!(action_flags & MLX5_FLOW_ACTION_JUMP))
6045                         return rte_flow_error_set
6046                                         (error, EINVAL,
6047                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6048                                         "tunnel set decap rule must terminate "
6049                                         "with JUMP");
6050                 if (!attr->ingress)
6051                         return rte_flow_error_set
6052                                         (error, EINVAL,
6053                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6054                                         "tunnel flows for ingress traffic only");
6055         }
6056         if (action_flags & MLX5_FLOW_ACTION_TUNNEL_MATCH) {
6057                 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_JUMP    |
6058                                             MLX5_FLOW_ACTION_MARK    |
6059                                             MLX5_FLOW_ACTION_SET_TAG |
6060                                             MLX5_FLOW_ACTION_SET_META;
6061
6062                 if (action_flags & bad_actions_mask)
6063                         return rte_flow_error_set
6064                                         (error, EINVAL,
6065                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6066                                         "Invalid RTE action in tunnel "
6067                                         "set match rule");
6068         }
6069         /*
6070          * Validate the drop action mutual exclusion with other actions.
6071          * Drop action is mutually-exclusive with any other action, except for
6072          * Count action.
6073          */
6074         if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
6075             (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
6076                 return rte_flow_error_set(error, EINVAL,
6077                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6078                                           "Drop action is mutually-exclusive "
6079                                           "with any other action, except for "
6080                                           "Count action");
6081         /* Eswitch has few restrictions on using items and actions */
6082         if (attr->transfer) {
6083                 if (!mlx5_flow_ext_mreg_supported(dev) &&
6084                     action_flags & MLX5_FLOW_ACTION_FLAG)
6085                         return rte_flow_error_set(error, ENOTSUP,
6086                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6087                                                   NULL,
6088                                                   "unsupported action FLAG");
6089                 if (!mlx5_flow_ext_mreg_supported(dev) &&
6090                     action_flags & MLX5_FLOW_ACTION_MARK)
6091                         return rte_flow_error_set(error, ENOTSUP,
6092                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6093                                                   NULL,
6094                                                   "unsupported action MARK");
6095                 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
6096                         return rte_flow_error_set(error, ENOTSUP,
6097                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6098                                                   NULL,
6099                                                   "unsupported action QUEUE");
6100                 if (action_flags & MLX5_FLOW_ACTION_RSS)
6101                         return rte_flow_error_set(error, ENOTSUP,
6102                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6103                                                   NULL,
6104                                                   "unsupported action RSS");
6105                 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
6106                         return rte_flow_error_set(error, EINVAL,
6107                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6108                                                   actions,
6109                                                   "no fate action is found");
6110         } else {
6111                 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
6112                         return rte_flow_error_set(error, EINVAL,
6113                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6114                                                   actions,
6115                                                   "no fate action is found");
6116         }
6117         /*
6118          * Continue validation for Xcap and VLAN actions.
6119          * If hairpin is working in explicit TX rule mode, there is no actions
6120          * splitting and the validation of hairpin ingress flow should be the
6121          * same as other standard flows.
6122          */
6123         if ((action_flags & (MLX5_FLOW_XCAP_ACTIONS |
6124                              MLX5_FLOW_VLAN_ACTIONS)) &&
6125             (queue_index == 0xFFFF ||
6126              mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN ||
6127              ((conf = mlx5_rxq_get_hairpin_conf(dev, queue_index)) != NULL &&
6128              conf->tx_explicit != 0))) {
6129                 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
6130                     MLX5_FLOW_XCAP_ACTIONS)
6131                         return rte_flow_error_set(error, ENOTSUP,
6132                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6133                                                   NULL, "encap and decap "
6134                                                   "combination aren't supported");
6135                 if (!attr->transfer && attr->ingress) {
6136                         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
6137                                 return rte_flow_error_set
6138                                                 (error, ENOTSUP,
6139                                                  RTE_FLOW_ERROR_TYPE_ACTION,
6140                                                  NULL, "encap is not supported"
6141                                                  " for ingress traffic");
6142                         else if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
6143                                 return rte_flow_error_set
6144                                                 (error, ENOTSUP,
6145                                                  RTE_FLOW_ERROR_TYPE_ACTION,
6146                                                  NULL, "push VLAN action not "
6147                                                  "supported for ingress");
6148                         else if ((action_flags & MLX5_FLOW_VLAN_ACTIONS) ==
6149                                         MLX5_FLOW_VLAN_ACTIONS)
6150                                 return rte_flow_error_set
6151                                                 (error, ENOTSUP,
6152                                                  RTE_FLOW_ERROR_TYPE_ACTION,
6153                                                  NULL, "no support for "
6154                                                  "multiple VLAN actions");
6155                 }
6156         }
6157         /*
6158          * Hairpin flow will add one more TAG action in TX implicit mode.
6159          * In TX explicit mode, there will be no hairpin flow ID.
6160          */
6161         if (hairpin > 0)
6162                 rw_act_num += MLX5_ACT_NUM_SET_TAG;
6163         /* extra metadata enabled: one more TAG action will be add. */
6164         if (dev_conf->dv_flow_en &&
6165             dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
6166             mlx5_flow_ext_mreg_supported(dev))
6167                 rw_act_num += MLX5_ACT_NUM_SET_TAG;
6168         if ((uint32_t)rw_act_num >
6169                         flow_dv_modify_hdr_action_max(dev, is_root)) {
6170                 return rte_flow_error_set(error, ENOTSUP,
6171                                           RTE_FLOW_ERROR_TYPE_ACTION,
6172                                           NULL, "too many header modify"
6173                                           " actions to support");
6174         }
6175         return 0;
6176 }
6177
6178 /**
6179  * Internal preparation function. Allocates the DV flow size,
6180  * this size is constant.
6181  *
6182  * @param[in] dev
6183  *   Pointer to the rte_eth_dev structure.
6184  * @param[in] attr
6185  *   Pointer to the flow attributes.
6186  * @param[in] items
6187  *   Pointer to the list of items.
6188  * @param[in] actions
6189  *   Pointer to the list of actions.
6190  * @param[out] error
6191  *   Pointer to the error structure.
6192  *
6193  * @return
6194  *   Pointer to mlx5_flow object on success,
6195  *   otherwise NULL and rte_errno is set.
6196  */
6197 static struct mlx5_flow *
6198 flow_dv_prepare(struct rte_eth_dev *dev,
6199                 const struct rte_flow_attr *attr __rte_unused,
6200                 const struct rte_flow_item items[] __rte_unused,
6201                 const struct rte_flow_action actions[] __rte_unused,
6202                 struct rte_flow_error *error)
6203 {
6204         uint32_t handle_idx = 0;
6205         struct mlx5_flow *dev_flow;
6206         struct mlx5_flow_handle *dev_handle;
6207         struct mlx5_priv *priv = dev->data->dev_private;
6208         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
6209
6210         MLX5_ASSERT(wks);
6211         /* In case of corrupting the memory. */
6212         if (wks->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
6213                 rte_flow_error_set(error, ENOSPC,
6214                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6215                                    "not free temporary device flow");
6216                 return NULL;
6217         }
6218         dev_handle = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
6219                                    &handle_idx);
6220         if (!dev_handle) {
6221                 rte_flow_error_set(error, ENOMEM,
6222                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6223                                    "not enough memory to create flow handle");
6224                 return NULL;
6225         }
6226         MLX5_ASSERT(wks->flow_idx + 1 < RTE_DIM(wks->flows));
6227         dev_flow = &wks->flows[wks->flow_idx++];
6228         dev_flow->handle = dev_handle;
6229         dev_flow->handle_idx = handle_idx;
6230         /*
6231          * In some old rdma-core releases, before continuing, a check of the
6232          * length of matching parameter will be done at first. It needs to use
6233          * the length without misc4 param. If the flow has misc4 support, then
6234          * the length needs to be adjusted accordingly. Each param member is
6235          * aligned with a 64B boundary naturally.
6236          */
6237         dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param) -
6238                                   MLX5_ST_SZ_BYTES(fte_match_set_misc4);
6239         /*
6240          * The matching value needs to be cleared to 0 before using. In the
6241          * past, it will be automatically cleared when using rte_*alloc
6242          * API. The time consumption will be almost the same as before.
6243          */
6244         memset(dev_flow->dv.value.buf, 0, MLX5_ST_SZ_BYTES(fte_match_param));
6245         dev_flow->ingress = attr->ingress;
6246         dev_flow->dv.transfer = attr->transfer;
6247         return dev_flow;
6248 }
6249
6250 #ifdef RTE_LIBRTE_MLX5_DEBUG
6251 /**
6252  * Sanity check for match mask and value. Similar to check_valid_spec() in
6253  * kernel driver. If unmasked bit is present in value, it returns failure.
6254  *
6255  * @param match_mask
6256  *   pointer to match mask buffer.
6257  * @param match_value
6258  *   pointer to match value buffer.
6259  *
6260  * @return
6261  *   0 if valid, -EINVAL otherwise.
6262  */
6263 static int
6264 flow_dv_check_valid_spec(void *match_mask, void *match_value)
6265 {
6266         uint8_t *m = match_mask;
6267         uint8_t *v = match_value;
6268         unsigned int i;
6269
6270         for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
6271                 if (v[i] & ~m[i]) {
6272                         DRV_LOG(ERR,
6273                                 "match_value differs from match_criteria"
6274                                 " %p[%u] != %p[%u]",
6275                                 match_value, i, match_mask, i);
6276                         return -EINVAL;
6277                 }
6278         }
6279         return 0;
6280 }
6281 #endif
6282
6283 /**
6284  * Add match of ip_version.
6285  *
6286  * @param[in] group
6287  *   Flow group.
6288  * @param[in] headers_v
6289  *   Values header pointer.
6290  * @param[in] headers_m
6291  *   Masks header pointer.
6292  * @param[in] ip_version
6293  *   The IP version to set.
6294  */
6295 static inline void
6296 flow_dv_set_match_ip_version(uint32_t group,
6297                              void *headers_v,
6298                              void *headers_m,
6299                              uint8_t ip_version)
6300 {
6301         if (group == 0)
6302                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
6303         else
6304                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version,
6305                          ip_version);
6306         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, ip_version);
6307         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, 0);
6308         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype, 0);
6309 }
6310
6311 /**
6312  * Add Ethernet item to matcher and to the value.
6313  *
6314  * @param[in, out] matcher
6315  *   Flow matcher.
6316  * @param[in, out] key
6317  *   Flow matcher value.
6318  * @param[in] item
6319  *   Flow pattern to translate.
6320  * @param[in] inner
6321  *   Item is inner pattern.
6322  */
6323 static void
6324 flow_dv_translate_item_eth(void *matcher, void *key,
6325                            const struct rte_flow_item *item, int inner,
6326                            uint32_t group)
6327 {
6328         const struct rte_flow_item_eth *eth_m = item->mask;
6329         const struct rte_flow_item_eth *eth_v = item->spec;
6330         const struct rte_flow_item_eth nic_mask = {
6331                 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
6332                 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
6333                 .type = RTE_BE16(0xffff),
6334                 .has_vlan = 0,
6335         };
6336         void *hdrs_m;
6337         void *hdrs_v;
6338         char *l24_v;
6339         unsigned int i;
6340
6341         if (!eth_v)
6342                 return;
6343         if (!eth_m)
6344                 eth_m = &nic_mask;
6345         if (inner) {
6346                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
6347                                          inner_headers);
6348                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6349         } else {
6350                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
6351                                          outer_headers);
6352                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6353         }
6354         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, dmac_47_16),
6355                &eth_m->dst, sizeof(eth_m->dst));
6356         /* The value must be in the range of the mask. */
6357         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, dmac_47_16);
6358         for (i = 0; i < sizeof(eth_m->dst); ++i)
6359                 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
6360         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, smac_47_16),
6361                &eth_m->src, sizeof(eth_m->src));
6362         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, smac_47_16);
6363         /* The value must be in the range of the mask. */
6364         for (i = 0; i < sizeof(eth_m->dst); ++i)
6365                 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
6366         /*
6367          * HW supports match on one Ethertype, the Ethertype following the last
6368          * VLAN tag of the packet (see PRM).
6369          * Set match on ethertype only if ETH header is not followed by VLAN.
6370          * HW is optimized for IPv4/IPv6. In such cases, avoid setting
6371          * ethertype, and use ip_version field instead.
6372          * eCPRI over Ether layer will use type value 0xAEFE.
6373          */
6374         if (eth_m->type == 0xFFFF) {
6375                 /* Set cvlan_tag mask for any single\multi\un-tagged case. */
6376                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
6377                 switch (eth_v->type) {
6378                 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
6379                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
6380                         return;
6381                 case RTE_BE16(RTE_ETHER_TYPE_QINQ):
6382                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
6383                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
6384                         return;
6385                 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
6386                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
6387                         return;
6388                 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
6389                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
6390                         return;
6391                 default:
6392                         break;
6393                 }
6394         }
6395         if (eth_m->has_vlan) {
6396                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
6397                 if (eth_v->has_vlan) {
6398                         /*
6399                          * Here, when also has_more_vlan field in VLAN item is
6400                          * not set, only single-tagged packets will be matched.
6401                          */
6402                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
6403                         return;
6404                 }
6405         }
6406         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
6407                  rte_be_to_cpu_16(eth_m->type));
6408         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, ethertype);
6409         *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
6410 }
6411
6412 /**
6413  * Add VLAN item to matcher and to the value.
6414  *
6415  * @param[in, out] dev_flow
6416  *   Flow descriptor.
6417  * @param[in, out] matcher
6418  *   Flow matcher.
6419  * @param[in, out] key
6420  *   Flow matcher value.
6421  * @param[in] item
6422  *   Flow pattern to translate.
6423  * @param[in] inner
6424  *   Item is inner pattern.
6425  */
6426 static void
6427 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
6428                             void *matcher, void *key,
6429                             const struct rte_flow_item *item,
6430                             int inner, uint32_t group)
6431 {
6432         const struct rte_flow_item_vlan *vlan_m = item->mask;
6433         const struct rte_flow_item_vlan *vlan_v = item->spec;
6434         void *hdrs_m;
6435         void *hdrs_v;
6436         uint16_t tci_m;
6437         uint16_t tci_v;
6438
6439         if (inner) {
6440                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
6441                                          inner_headers);
6442                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6443         } else {
6444                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
6445                                          outer_headers);
6446                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6447                 /*
6448                  * This is workaround, masks are not supported,
6449                  * and pre-validated.
6450                  */
6451                 if (vlan_v)
6452                         dev_flow->handle->vf_vlan.tag =
6453                                         rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
6454         }
6455         /*
6456          * When VLAN item exists in flow, mark packet as tagged,
6457          * even if TCI is not specified.
6458          */
6459         if (!MLX5_GET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag)) {
6460                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
6461                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
6462         }
6463         if (!vlan_v)
6464                 return;
6465         if (!vlan_m)
6466                 vlan_m = &rte_flow_item_vlan_mask;
6467         tci_m = rte_be_to_cpu_16(vlan_m->tci);
6468         tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
6469         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_vid, tci_m);
6470         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_vid, tci_v);
6471         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_cfi, tci_m >> 12);
6472         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_cfi, tci_v >> 12);
6473         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_prio, tci_m >> 13);
6474         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_prio, tci_v >> 13);
6475         /*
6476          * HW is optimized for IPv4/IPv6. In such cases, avoid setting
6477          * ethertype, and use ip_version field instead.
6478          */
6479         if (vlan_m->inner_type == 0xFFFF) {
6480                 switch (vlan_v->inner_type) {
6481                 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
6482                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
6483                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
6484                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
6485                         return;
6486                 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
6487                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
6488                         return;
6489                 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
6490                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
6491                         return;
6492                 default:
6493                         break;
6494                 }
6495         }
6496         if (vlan_m->has_more_vlan && vlan_v->has_more_vlan) {
6497                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
6498                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
6499                 /* Only one vlan_tag bit can be set. */
6500                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
6501                 return;
6502         }
6503         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
6504                  rte_be_to_cpu_16(vlan_m->inner_type));
6505         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, ethertype,
6506                  rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
6507 }
6508
6509 /**
6510  * Add IPV4 item to matcher and to the value.
6511  *
6512  * @param[in, out] matcher
6513  *   Flow matcher.
6514  * @param[in, out] key
6515  *   Flow matcher value.
6516  * @param[in] item
6517  *   Flow pattern to translate.
6518  * @param[in] inner
6519  *   Item is inner pattern.
6520  * @param[in] group
6521  *   The group to insert the rule.
6522  */
6523 static void
6524 flow_dv_translate_item_ipv4(void *matcher, void *key,
6525                             const struct rte_flow_item *item,
6526                             int inner, uint32_t group)
6527 {
6528         const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
6529         const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
6530         const struct rte_flow_item_ipv4 nic_mask = {
6531                 .hdr = {
6532                         .src_addr = RTE_BE32(0xffffffff),
6533                         .dst_addr = RTE_BE32(0xffffffff),
6534                         .type_of_service = 0xff,
6535                         .next_proto_id = 0xff,
6536                         .time_to_live = 0xff,
6537                 },
6538         };
6539         void *headers_m;
6540         void *headers_v;
6541         char *l24_m;
6542         char *l24_v;
6543         uint8_t tos;
6544
6545         if (inner) {
6546                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6547                                          inner_headers);
6548                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6549         } else {
6550                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6551                                          outer_headers);
6552                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6553         }
6554         flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
6555         if (!ipv4_v)
6556                 return;
6557         if (!ipv4_m)
6558                 ipv4_m = &nic_mask;
6559         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6560                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
6561         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6562                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
6563         *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
6564         *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
6565         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6566                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
6567         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6568                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
6569         *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
6570         *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
6571         tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
6572         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
6573                  ipv4_m->hdr.type_of_service);
6574         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
6575         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
6576                  ipv4_m->hdr.type_of_service >> 2);
6577         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
6578         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6579                  ipv4_m->hdr.next_proto_id);
6580         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6581                  ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
6582         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
6583                  ipv4_m->hdr.time_to_live);
6584         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
6585                  ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
6586         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
6587                  !!(ipv4_m->hdr.fragment_offset));
6588         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
6589                  !!(ipv4_v->hdr.fragment_offset & ipv4_m->hdr.fragment_offset));
6590 }
6591
6592 /**
6593  * Add IPV6 item to matcher and to the value.
6594  *
6595  * @param[in, out] matcher
6596  *   Flow matcher.
6597  * @param[in, out] key
6598  *   Flow matcher value.
6599  * @param[in] item
6600  *   Flow pattern to translate.
6601  * @param[in] inner
6602  *   Item is inner pattern.
6603  * @param[in] group
6604  *   The group to insert the rule.
6605  */
6606 static void
6607 flow_dv_translate_item_ipv6(void *matcher, void *key,
6608                             const struct rte_flow_item *item,
6609                             int inner, uint32_t group)
6610 {
6611         const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
6612         const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
6613         const struct rte_flow_item_ipv6 nic_mask = {
6614                 .hdr = {
6615                         .src_addr =
6616                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
6617                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
6618                         .dst_addr =
6619                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
6620                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
6621                         .vtc_flow = RTE_BE32(0xffffffff),
6622                         .proto = 0xff,
6623                         .hop_limits = 0xff,
6624                 },
6625         };
6626         void *headers_m;
6627         void *headers_v;
6628         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6629         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6630         char *l24_m;
6631         char *l24_v;
6632         uint32_t vtc_m;
6633         uint32_t vtc_v;
6634         int i;
6635         int size;
6636
6637         if (inner) {
6638                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6639                                          inner_headers);
6640                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6641         } else {
6642                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6643                                          outer_headers);
6644                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6645         }
6646         flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
6647         if (!ipv6_v)
6648                 return;
6649         if (!ipv6_m)
6650                 ipv6_m = &nic_mask;
6651         size = sizeof(ipv6_m->hdr.dst_addr);
6652         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6653                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
6654         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6655                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
6656         memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
6657         for (i = 0; i < size; ++i)
6658                 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
6659         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6660                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
6661         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6662                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
6663         memcpy(l24_m, ipv6_m->hdr.src_addr, size);
6664         for (i = 0; i < size; ++i)
6665                 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
6666         /* TOS. */
6667         vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
6668         vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
6669         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
6670         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
6671         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
6672         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
6673         /* Label. */
6674         if (inner) {
6675                 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
6676                          vtc_m);
6677                 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
6678                          vtc_v);
6679         } else {
6680                 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
6681                          vtc_m);
6682                 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
6683                          vtc_v);
6684         }
6685         /* Protocol. */
6686         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6687                  ipv6_m->hdr.proto);
6688         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6689                  ipv6_v->hdr.proto & ipv6_m->hdr.proto);
6690         /* Hop limit. */
6691         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
6692                  ipv6_m->hdr.hop_limits);
6693         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
6694                  ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
6695         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
6696                  !!(ipv6_m->has_frag_ext));
6697         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
6698                  !!(ipv6_v->has_frag_ext & ipv6_m->has_frag_ext));
6699 }
6700
6701 /**
6702  * Add IPV6 fragment extension item to matcher and to the value.
6703  *
6704  * @param[in, out] matcher
6705  *   Flow matcher.
6706  * @param[in, out] key
6707  *   Flow matcher value.
6708  * @param[in] item
6709  *   Flow pattern to translate.
6710  * @param[in] inner
6711  *   Item is inner pattern.
6712  */
6713 static void
6714 flow_dv_translate_item_ipv6_frag_ext(void *matcher, void *key,
6715                                      const struct rte_flow_item *item,
6716                                      int inner)
6717 {
6718         const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_m = item->mask;
6719         const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_v = item->spec;
6720         const struct rte_flow_item_ipv6_frag_ext nic_mask = {
6721                 .hdr = {
6722                         .next_header = 0xff,
6723                         .frag_data = RTE_BE16(0xffff),
6724                 },
6725         };
6726         void *headers_m;
6727         void *headers_v;
6728
6729         if (inner) {
6730                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6731                                          inner_headers);
6732                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6733         } else {
6734                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6735                                          outer_headers);
6736                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6737         }
6738         /* IPv6 fragment extension item exists, so packet is IP fragment. */
6739         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
6740         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 1);
6741         if (!ipv6_frag_ext_v)
6742                 return;
6743         if (!ipv6_frag_ext_m)
6744                 ipv6_frag_ext_m = &nic_mask;
6745         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6746                  ipv6_frag_ext_m->hdr.next_header);
6747         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6748                  ipv6_frag_ext_v->hdr.next_header &
6749                  ipv6_frag_ext_m->hdr.next_header);
6750 }
6751
6752 /**
6753  * Add TCP item to matcher and to the value.
6754  *
6755  * @param[in, out] matcher
6756  *   Flow matcher.
6757  * @param[in, out] key
6758  *   Flow matcher value.
6759  * @param[in] item
6760  *   Flow pattern to translate.
6761  * @param[in] inner
6762  *   Item is inner pattern.
6763  */
6764 static void
6765 flow_dv_translate_item_tcp(void *matcher, void *key,
6766                            const struct rte_flow_item *item,
6767                            int inner)
6768 {
6769         const struct rte_flow_item_tcp *tcp_m = item->mask;
6770         const struct rte_flow_item_tcp *tcp_v = item->spec;
6771         void *headers_m;
6772         void *headers_v;
6773
6774         if (inner) {
6775                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6776                                          inner_headers);
6777                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6778         } else {
6779                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6780                                          outer_headers);
6781                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6782         }
6783         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6784         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
6785         if (!tcp_v)
6786                 return;
6787         if (!tcp_m)
6788                 tcp_m = &rte_flow_item_tcp_mask;
6789         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
6790                  rte_be_to_cpu_16(tcp_m->hdr.src_port));
6791         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
6792                  rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
6793         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
6794                  rte_be_to_cpu_16(tcp_m->hdr.dst_port));
6795         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
6796                  rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
6797         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
6798                  tcp_m->hdr.tcp_flags);
6799         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
6800                  (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
6801 }
6802
6803 /**
6804  * Add UDP item to matcher and to the value.
6805  *
6806  * @param[in, out] matcher
6807  *   Flow matcher.
6808  * @param[in, out] key
6809  *   Flow matcher value.
6810  * @param[in] item
6811  *   Flow pattern to translate.
6812  * @param[in] inner
6813  *   Item is inner pattern.
6814  */
6815 static void
6816 flow_dv_translate_item_udp(void *matcher, void *key,
6817                            const struct rte_flow_item *item,
6818                            int inner)
6819 {
6820         const struct rte_flow_item_udp *udp_m = item->mask;
6821         const struct rte_flow_item_udp *udp_v = item->spec;
6822         void *headers_m;
6823         void *headers_v;
6824
6825         if (inner) {
6826                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6827                                          inner_headers);
6828                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6829         } else {
6830                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6831                                          outer_headers);
6832                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6833         }
6834         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6835         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
6836         if (!udp_v)
6837                 return;
6838         if (!udp_m)
6839                 udp_m = &rte_flow_item_udp_mask;
6840         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
6841                  rte_be_to_cpu_16(udp_m->hdr.src_port));
6842         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
6843                  rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
6844         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
6845                  rte_be_to_cpu_16(udp_m->hdr.dst_port));
6846         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
6847                  rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
6848 }
6849
6850 /**
6851  * Add GRE optional Key item to matcher and to the value.
6852  *
6853  * @param[in, out] matcher
6854  *   Flow matcher.
6855  * @param[in, out] key
6856  *   Flow matcher value.
6857  * @param[in] item
6858  *   Flow pattern to translate.
6859  * @param[in] inner
6860  *   Item is inner pattern.
6861  */
6862 static void
6863 flow_dv_translate_item_gre_key(void *matcher, void *key,
6864                                    const struct rte_flow_item *item)
6865 {
6866         const rte_be32_t *key_m = item->mask;
6867         const rte_be32_t *key_v = item->spec;
6868         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6869         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6870         rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
6871
6872         /* GRE K bit must be on and should already be validated */
6873         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
6874         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
6875         if (!key_v)
6876                 return;
6877         if (!key_m)
6878                 key_m = &gre_key_default_mask;
6879         MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
6880                  rte_be_to_cpu_32(*key_m) >> 8);
6881         MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
6882                  rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
6883         MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
6884                  rte_be_to_cpu_32(*key_m) & 0xFF);
6885         MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
6886                  rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
6887 }
6888
6889 /**
6890  * Add GRE item to matcher and to the value.
6891  *
6892  * @param[in, out] matcher
6893  *   Flow matcher.
6894  * @param[in, out] key
6895  *   Flow matcher value.
6896  * @param[in] item
6897  *   Flow pattern to translate.
6898  * @param[in] inner
6899  *   Item is inner pattern.
6900  */
6901 static void
6902 flow_dv_translate_item_gre(void *matcher, void *key,
6903                            const struct rte_flow_item *item,
6904                            int inner)
6905 {
6906         const struct rte_flow_item_gre *gre_m = item->mask;
6907         const struct rte_flow_item_gre *gre_v = item->spec;
6908         void *headers_m;
6909         void *headers_v;
6910         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6911         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6912         struct {
6913                 union {
6914                         __extension__
6915                         struct {
6916                                 uint16_t version:3;
6917                                 uint16_t rsvd0:9;
6918                                 uint16_t s_present:1;
6919                                 uint16_t k_present:1;
6920                                 uint16_t rsvd_bit1:1;
6921                                 uint16_t c_present:1;
6922                         };
6923                         uint16_t value;
6924                 };
6925         } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
6926
6927         if (inner) {
6928                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6929                                          inner_headers);
6930                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6931         } else {
6932                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6933                                          outer_headers);
6934                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6935         }
6936         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6937         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
6938         if (!gre_v)
6939                 return;
6940         if (!gre_m)
6941                 gre_m = &rte_flow_item_gre_mask;
6942         MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
6943                  rte_be_to_cpu_16(gre_m->protocol));
6944         MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
6945                  rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
6946         gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
6947         gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
6948         MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
6949                  gre_crks_rsvd0_ver_m.c_present);
6950         MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
6951                  gre_crks_rsvd0_ver_v.c_present &
6952                  gre_crks_rsvd0_ver_m.c_present);
6953         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
6954                  gre_crks_rsvd0_ver_m.k_present);
6955         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
6956                  gre_crks_rsvd0_ver_v.k_present &
6957                  gre_crks_rsvd0_ver_m.k_present);
6958         MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
6959                  gre_crks_rsvd0_ver_m.s_present);
6960         MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
6961                  gre_crks_rsvd0_ver_v.s_present &
6962                  gre_crks_rsvd0_ver_m.s_present);
6963 }
6964
6965 /**
6966  * Add NVGRE item to matcher and to the value.
6967  *
6968  * @param[in, out] matcher
6969  *   Flow matcher.
6970  * @param[in, out] key
6971  *   Flow matcher value.
6972  * @param[in] item
6973  *   Flow pattern to translate.
6974  * @param[in] inner
6975  *   Item is inner pattern.
6976  */
6977 static void
6978 flow_dv_translate_item_nvgre(void *matcher, void *key,
6979                              const struct rte_flow_item *item,
6980                              int inner)
6981 {
6982         const struct rte_flow_item_nvgre *nvgre_m = item->mask;
6983         const struct rte_flow_item_nvgre *nvgre_v = item->spec;
6984         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6985         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6986         const char *tni_flow_id_m;
6987         const char *tni_flow_id_v;
6988         char *gre_key_m;
6989         char *gre_key_v;
6990         int size;
6991         int i;
6992
6993         /* For NVGRE, GRE header fields must be set with defined values. */
6994         const struct rte_flow_item_gre gre_spec = {
6995                 .c_rsvd0_ver = RTE_BE16(0x2000),
6996                 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
6997         };
6998         const struct rte_flow_item_gre gre_mask = {
6999                 .c_rsvd0_ver = RTE_BE16(0xB000),
7000                 .protocol = RTE_BE16(UINT16_MAX),
7001         };
7002         const struct rte_flow_item gre_item = {
7003                 .spec = &gre_spec,
7004                 .mask = &gre_mask,
7005                 .last = NULL,
7006         };
7007         flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
7008         if (!nvgre_v)
7009                 return;
7010         if (!nvgre_m)
7011                 nvgre_m = &rte_flow_item_nvgre_mask;
7012         tni_flow_id_m = (const char *)nvgre_m->tni;
7013         tni_flow_id_v = (const char *)nvgre_v->tni;
7014         size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
7015         gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
7016         gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
7017         memcpy(gre_key_m, tni_flow_id_m, size);
7018         for (i = 0; i < size; ++i)
7019                 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
7020 }
7021
7022 /**
7023  * Add VXLAN item to matcher and to the value.
7024  *
7025  * @param[in, out] matcher
7026  *   Flow matcher.
7027  * @param[in, out] key
7028  *   Flow matcher value.
7029  * @param[in] item
7030  *   Flow pattern to translate.
7031  * @param[in] inner
7032  *   Item is inner pattern.
7033  */
7034 static void
7035 flow_dv_translate_item_vxlan(void *matcher, void *key,
7036                              const struct rte_flow_item *item,
7037                              int inner)
7038 {
7039         const struct rte_flow_item_vxlan *vxlan_m = item->mask;
7040         const struct rte_flow_item_vxlan *vxlan_v = item->spec;
7041         void *headers_m;
7042         void *headers_v;
7043         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7044         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7045         char *vni_m;
7046         char *vni_v;
7047         uint16_t dport;
7048         int size;
7049         int i;
7050
7051         if (inner) {
7052                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7053                                          inner_headers);
7054                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7055         } else {
7056                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7057                                          outer_headers);
7058                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7059         }
7060         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
7061                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
7062         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7063                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7064                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7065         }
7066         if (!vxlan_v)
7067                 return;
7068         if (!vxlan_m)
7069                 vxlan_m = &rte_flow_item_vxlan_mask;
7070         size = sizeof(vxlan_m->vni);
7071         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
7072         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
7073         memcpy(vni_m, vxlan_m->vni, size);
7074         for (i = 0; i < size; ++i)
7075                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
7076 }
7077
7078 /**
7079  * Add VXLAN-GPE item to matcher and to the value.
7080  *
7081  * @param[in, out] matcher
7082  *   Flow matcher.
7083  * @param[in, out] key
7084  *   Flow matcher value.
7085  * @param[in] item
7086  *   Flow pattern to translate.
7087  * @param[in] inner
7088  *   Item is inner pattern.
7089  */
7090
7091 static void
7092 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
7093                                  const struct rte_flow_item *item, int inner)
7094 {
7095         const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
7096         const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
7097         void *headers_m;
7098         void *headers_v;
7099         void *misc_m =
7100                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
7101         void *misc_v =
7102                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7103         char *vni_m;
7104         char *vni_v;
7105         uint16_t dport;
7106         int size;
7107         int i;
7108         uint8_t flags_m = 0xff;
7109         uint8_t flags_v = 0xc;
7110
7111         if (inner) {
7112                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7113                                          inner_headers);
7114                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7115         } else {
7116                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7117                                          outer_headers);
7118                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7119         }
7120         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
7121                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
7122         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7123                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7124                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7125         }
7126         if (!vxlan_v)
7127                 return;
7128         if (!vxlan_m)
7129                 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
7130         size = sizeof(vxlan_m->vni);
7131         vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
7132         vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
7133         memcpy(vni_m, vxlan_m->vni, size);
7134         for (i = 0; i < size; ++i)
7135                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
7136         if (vxlan_m->flags) {
7137                 flags_m = vxlan_m->flags;
7138                 flags_v = vxlan_v->flags;
7139         }
7140         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
7141         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
7142         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
7143                  vxlan_m->protocol);
7144         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
7145                  vxlan_v->protocol);
7146 }
7147
7148 /**
7149  * Add Geneve item to matcher and to the value.
7150  *
7151  * @param[in, out] matcher
7152  *   Flow matcher.
7153  * @param[in, out] key
7154  *   Flow matcher value.
7155  * @param[in] item
7156  *   Flow pattern to translate.
7157  * @param[in] inner
7158  *   Item is inner pattern.
7159  */
7160
7161 static void
7162 flow_dv_translate_item_geneve(void *matcher, void *key,
7163                               const struct rte_flow_item *item, int inner)
7164 {
7165         const struct rte_flow_item_geneve *geneve_m = item->mask;
7166         const struct rte_flow_item_geneve *geneve_v = item->spec;
7167         void *headers_m;
7168         void *headers_v;
7169         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7170         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7171         uint16_t dport;
7172         uint16_t gbhdr_m;
7173         uint16_t gbhdr_v;
7174         char *vni_m;
7175         char *vni_v;
7176         size_t size, i;
7177
7178         if (inner) {
7179                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7180                                          inner_headers);
7181                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7182         } else {
7183                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7184                                          outer_headers);
7185                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7186         }
7187         dport = MLX5_UDP_PORT_GENEVE;
7188         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7189                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7190                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7191         }
7192         if (!geneve_v)
7193                 return;
7194         if (!geneve_m)
7195                 geneve_m = &rte_flow_item_geneve_mask;
7196         size = sizeof(geneve_m->vni);
7197         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
7198         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
7199         memcpy(vni_m, geneve_m->vni, size);
7200         for (i = 0; i < size; ++i)
7201                 vni_v[i] = vni_m[i] & geneve_v->vni[i];
7202         MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
7203                  rte_be_to_cpu_16(geneve_m->protocol));
7204         MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
7205                  rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
7206         gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
7207         gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
7208         MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
7209                  MLX5_GENEVE_OAMF_VAL(gbhdr_m));
7210         MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
7211                  MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
7212         MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
7213                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
7214         MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
7215                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
7216                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
7217 }
7218
7219 /**
7220  * Add MPLS item to matcher and to the value.
7221  *
7222  * @param[in, out] matcher
7223  *   Flow matcher.
7224  * @param[in, out] key
7225  *   Flow matcher value.
7226  * @param[in] item
7227  *   Flow pattern to translate.
7228  * @param[in] prev_layer
7229  *   The protocol layer indicated in previous item.
7230  * @param[in] inner
7231  *   Item is inner pattern.
7232  */
7233 static void
7234 flow_dv_translate_item_mpls(void *matcher, void *key,
7235                             const struct rte_flow_item *item,
7236                             uint64_t prev_layer,
7237                             int inner)
7238 {
7239         const uint32_t *in_mpls_m = item->mask;
7240         const uint32_t *in_mpls_v = item->spec;
7241         uint32_t *out_mpls_m = 0;
7242         uint32_t *out_mpls_v = 0;
7243         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7244         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7245         void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
7246                                      misc_parameters_2);
7247         void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
7248         void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
7249         void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7250
7251         switch (prev_layer) {
7252         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
7253                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
7254                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
7255                          MLX5_UDP_PORT_MPLS);
7256                 break;
7257         case MLX5_FLOW_LAYER_GRE:
7258                 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
7259                 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
7260                          RTE_ETHER_TYPE_MPLS);
7261                 break;
7262         default:
7263                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7264                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
7265                          IPPROTO_MPLS);
7266                 break;
7267         }
7268         if (!in_mpls_v)
7269                 return;
7270         if (!in_mpls_m)
7271                 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
7272         switch (prev_layer) {
7273         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
7274                 out_mpls_m =
7275                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
7276                                                  outer_first_mpls_over_udp);
7277                 out_mpls_v =
7278                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
7279                                                  outer_first_mpls_over_udp);
7280                 break;
7281         case MLX5_FLOW_LAYER_GRE:
7282                 out_mpls_m =
7283                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
7284                                                  outer_first_mpls_over_gre);
7285                 out_mpls_v =
7286                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
7287                                                  outer_first_mpls_over_gre);
7288                 break;
7289         default:
7290                 /* Inner MPLS not over GRE is not supported. */
7291                 if (!inner) {
7292                         out_mpls_m =
7293                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
7294                                                          misc2_m,
7295                                                          outer_first_mpls);
7296                         out_mpls_v =
7297                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
7298                                                          misc2_v,
7299                                                          outer_first_mpls);
7300                 }
7301                 break;
7302         }
7303         if (out_mpls_m && out_mpls_v) {
7304                 *out_mpls_m = *in_mpls_m;
7305                 *out_mpls_v = *in_mpls_v & *in_mpls_m;
7306         }
7307 }
7308
7309 /**
7310  * Add metadata register item to matcher
7311  *
7312  * @param[in, out] matcher
7313  *   Flow matcher.
7314  * @param[in, out] key
7315  *   Flow matcher value.
7316  * @param[in] reg_type
7317  *   Type of device metadata register
7318  * @param[in] value
7319  *   Register value
7320  * @param[in] mask
7321  *   Register mask
7322  */
7323 static void
7324 flow_dv_match_meta_reg(void *matcher, void *key,
7325                        enum modify_reg reg_type,
7326                        uint32_t data, uint32_t mask)
7327 {
7328         void *misc2_m =
7329                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
7330         void *misc2_v =
7331                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
7332         uint32_t temp;
7333
7334         data &= mask;
7335         switch (reg_type) {
7336         case REG_A:
7337                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
7338                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
7339                 break;
7340         case REG_B:
7341                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
7342                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
7343                 break;
7344         case REG_C_0:
7345                 /*
7346                  * The metadata register C0 field might be divided into
7347                  * source vport index and META item value, we should set
7348                  * this field according to specified mask, not as whole one.
7349                  */
7350                 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
7351                 temp |= mask;
7352                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
7353                 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
7354                 temp &= ~mask;
7355                 temp |= data;
7356                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
7357                 break;
7358         case REG_C_1:
7359                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
7360                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
7361                 break;
7362         case REG_C_2:
7363                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
7364                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
7365                 break;
7366         case REG_C_3:
7367                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
7368                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
7369                 break;
7370         case REG_C_4:
7371                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
7372                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
7373                 break;
7374         case REG_C_5:
7375                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
7376                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
7377                 break;
7378         case REG_C_6:
7379                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
7380                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
7381                 break;
7382         case REG_C_7:
7383                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
7384                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
7385                 break;
7386         default:
7387                 MLX5_ASSERT(false);
7388                 break;
7389         }
7390 }
7391
7392 /**
7393  * Add MARK item to matcher
7394  *
7395  * @param[in] dev
7396  *   The device to configure through.
7397  * @param[in, out] matcher
7398  *   Flow matcher.
7399  * @param[in, out] key
7400  *   Flow matcher value.
7401  * @param[in] item
7402  *   Flow pattern to translate.
7403  */
7404 static void
7405 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
7406                             void *matcher, void *key,
7407                             const struct rte_flow_item *item)
7408 {
7409         struct mlx5_priv *priv = dev->data->dev_private;
7410         const struct rte_flow_item_mark *mark;
7411         uint32_t value;
7412         uint32_t mask;
7413
7414         mark = item->mask ? (const void *)item->mask :
7415                             &rte_flow_item_mark_mask;
7416         mask = mark->id & priv->sh->dv_mark_mask;
7417         mark = (const void *)item->spec;
7418         MLX5_ASSERT(mark);
7419         value = mark->id & priv->sh->dv_mark_mask & mask;
7420         if (mask) {
7421                 enum modify_reg reg;
7422
7423                 /* Get the metadata register index for the mark. */
7424                 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
7425                 MLX5_ASSERT(reg > 0);
7426                 if (reg == REG_C_0) {
7427                         struct mlx5_priv *priv = dev->data->dev_private;
7428                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
7429                         uint32_t shl_c0 = rte_bsf32(msk_c0);
7430
7431                         mask &= msk_c0;
7432                         mask <<= shl_c0;
7433                         value <<= shl_c0;
7434                 }
7435                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
7436         }
7437 }
7438
7439 /**
7440  * Add META item to matcher
7441  *
7442  * @param[in] dev
7443  *   The devich to configure through.
7444  * @param[in, out] matcher
7445  *   Flow matcher.
7446  * @param[in, out] key
7447  *   Flow matcher value.
7448  * @param[in] attr
7449  *   Attributes of flow that includes this item.
7450  * @param[in] item
7451  *   Flow pattern to translate.
7452  */
7453 static void
7454 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
7455                             void *matcher, void *key,
7456                             const struct rte_flow_attr *attr,
7457                             const struct rte_flow_item *item)
7458 {
7459         const struct rte_flow_item_meta *meta_m;
7460         const struct rte_flow_item_meta *meta_v;
7461
7462         meta_m = (const void *)item->mask;
7463         if (!meta_m)
7464                 meta_m = &rte_flow_item_meta_mask;
7465         meta_v = (const void *)item->spec;
7466         if (meta_v) {
7467                 int reg;
7468                 uint32_t value = meta_v->data;
7469                 uint32_t mask = meta_m->data;
7470
7471                 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
7472                 if (reg < 0)
7473                         return;
7474                 /*
7475                  * In datapath code there is no endianness
7476                  * coversions for perfromance reasons, all
7477                  * pattern conversions are done in rte_flow.
7478                  */
7479                 value = rte_cpu_to_be_32(value);
7480                 mask = rte_cpu_to_be_32(mask);
7481                 if (reg == REG_C_0) {
7482                         struct mlx5_priv *priv = dev->data->dev_private;
7483                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
7484                         uint32_t shl_c0 = rte_bsf32(msk_c0);
7485 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
7486                         uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
7487
7488                         value >>= shr_c0;
7489                         mask >>= shr_c0;
7490 #endif
7491                         value <<= shl_c0;
7492                         mask <<= shl_c0;
7493                         MLX5_ASSERT(msk_c0);
7494                         MLX5_ASSERT(!(~msk_c0 & mask));
7495                 }
7496                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
7497         }
7498 }
7499
7500 /**
7501  * Add vport metadata Reg C0 item to matcher
7502  *
7503  * @param[in, out] matcher
7504  *   Flow matcher.
7505  * @param[in, out] key
7506  *   Flow matcher value.
7507  * @param[in] reg
7508  *   Flow pattern to translate.
7509  */
7510 static void
7511 flow_dv_translate_item_meta_vport(void *matcher, void *key,
7512                                   uint32_t value, uint32_t mask)
7513 {
7514         flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
7515 }
7516
7517 /**
7518  * Add tag item to matcher
7519  *
7520  * @param[in] dev
7521  *   The devich to configure through.
7522  * @param[in, out] matcher
7523  *   Flow matcher.
7524  * @param[in, out] key
7525  *   Flow matcher value.
7526  * @param[in] item
7527  *   Flow pattern to translate.
7528  */
7529 static void
7530 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
7531                                 void *matcher, void *key,
7532                                 const struct rte_flow_item *item)
7533 {
7534         const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
7535         const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
7536         uint32_t mask, value;
7537
7538         MLX5_ASSERT(tag_v);
7539         value = tag_v->data;
7540         mask = tag_m ? tag_m->data : UINT32_MAX;
7541         if (tag_v->id == REG_C_0) {
7542                 struct mlx5_priv *priv = dev->data->dev_private;
7543                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
7544                 uint32_t shl_c0 = rte_bsf32(msk_c0);
7545
7546                 mask &= msk_c0;
7547                 mask <<= shl_c0;
7548                 value <<= shl_c0;
7549         }
7550         flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
7551 }
7552
7553 /**
7554  * Add TAG item to matcher
7555  *
7556  * @param[in] dev
7557  *   The devich to configure through.
7558  * @param[in, out] matcher
7559  *   Flow matcher.
7560  * @param[in, out] key
7561  *   Flow matcher value.
7562  * @param[in] item
7563  *   Flow pattern to translate.
7564  */
7565 static void
7566 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
7567                            void *matcher, void *key,
7568                            const struct rte_flow_item *item)
7569 {
7570         const struct rte_flow_item_tag *tag_v = item->spec;
7571         const struct rte_flow_item_tag *tag_m = item->mask;
7572         enum modify_reg reg;
7573
7574         MLX5_ASSERT(tag_v);
7575         tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
7576         /* Get the metadata register index for the tag. */
7577         reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
7578         MLX5_ASSERT(reg > 0);
7579         flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
7580 }
7581
7582 /**
7583  * Add source vport match to the specified matcher.
7584  *
7585  * @param[in, out] matcher
7586  *   Flow matcher.
7587  * @param[in, out] key
7588  *   Flow matcher value.
7589  * @param[in] port
7590  *   Source vport value to match
7591  * @param[in] mask
7592  *   Mask
7593  */
7594 static void
7595 flow_dv_translate_item_source_vport(void *matcher, void *key,
7596                                     int16_t port, uint16_t mask)
7597 {
7598         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7599         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7600
7601         MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
7602         MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
7603 }
7604
7605 /**
7606  * Translate port-id item to eswitch match on  port-id.
7607  *
7608  * @param[in] dev
7609  *   The devich to configure through.
7610  * @param[in, out] matcher
7611  *   Flow matcher.
7612  * @param[in, out] key
7613  *   Flow matcher value.
7614  * @param[in] item
7615  *   Flow pattern to translate.
7616  * @param[in]
7617  *   Flow attributes.
7618  *
7619  * @return
7620  *   0 on success, a negative errno value otherwise.
7621  */
7622 static int
7623 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
7624                                void *key, const struct rte_flow_item *item,
7625                                const struct rte_flow_attr *attr)
7626 {
7627         const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
7628         const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
7629         struct mlx5_priv *priv;
7630         uint16_t mask, id;
7631
7632         mask = pid_m ? pid_m->id : 0xffff;
7633         id = pid_v ? pid_v->id : dev->data->port_id;
7634         priv = mlx5_port_to_eswitch_info(id, item == NULL);
7635         if (!priv)
7636                 return -rte_errno;
7637         /*
7638          * Translate to vport field or to metadata, depending on mode.
7639          * Kernel can use either misc.source_port or half of C0 metadata
7640          * register.
7641          */
7642         if (priv->vport_meta_mask) {
7643                 /*
7644                  * Provide the hint for SW steering library
7645                  * to insert the flow into ingress domain and
7646                  * save the extra vport match.
7647                  */
7648                 if (mask == 0xffff && priv->vport_id == 0xffff &&
7649                     priv->pf_bond < 0 && attr->transfer)
7650                         flow_dv_translate_item_source_vport
7651                                 (matcher, key, priv->vport_id, mask);
7652                 else
7653                         flow_dv_translate_item_meta_vport
7654                                 (matcher, key,
7655                                  priv->vport_meta_tag,
7656                                  priv->vport_meta_mask);
7657         } else {
7658                 flow_dv_translate_item_source_vport(matcher, key,
7659                                                     priv->vport_id, mask);
7660         }
7661         return 0;
7662 }
7663
7664 /**
7665  * Add ICMP6 item to matcher and to the value.
7666  *
7667  * @param[in, out] matcher
7668  *   Flow matcher.
7669  * @param[in, out] key
7670  *   Flow matcher value.
7671  * @param[in] item
7672  *   Flow pattern to translate.
7673  * @param[in] inner
7674  *   Item is inner pattern.
7675  */
7676 static void
7677 flow_dv_translate_item_icmp6(void *matcher, void *key,
7678                               const struct rte_flow_item *item,
7679                               int inner)
7680 {
7681         const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
7682         const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
7683         void *headers_m;
7684         void *headers_v;
7685         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7686                                      misc_parameters_3);
7687         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7688         if (inner) {
7689                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7690                                          inner_headers);
7691                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7692         } else {
7693                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7694                                          outer_headers);
7695                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7696         }
7697         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
7698         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
7699         if (!icmp6_v)
7700                 return;
7701         if (!icmp6_m)
7702                 icmp6_m = &rte_flow_item_icmp6_mask;
7703         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
7704         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
7705                  icmp6_v->type & icmp6_m->type);
7706         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
7707         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
7708                  icmp6_v->code & icmp6_m->code);
7709 }
7710
7711 /**
7712  * Add ICMP item to matcher and to the value.
7713  *
7714  * @param[in, out] matcher
7715  *   Flow matcher.
7716  * @param[in, out] key
7717  *   Flow matcher value.
7718  * @param[in] item
7719  *   Flow pattern to translate.
7720  * @param[in] inner
7721  *   Item is inner pattern.
7722  */
7723 static void
7724 flow_dv_translate_item_icmp(void *matcher, void *key,
7725                             const struct rte_flow_item *item,
7726                             int inner)
7727 {
7728         const struct rte_flow_item_icmp *icmp_m = item->mask;
7729         const struct rte_flow_item_icmp *icmp_v = item->spec;
7730         uint32_t icmp_header_data_m = 0;
7731         uint32_t icmp_header_data_v = 0;
7732         void *headers_m;
7733         void *headers_v;
7734         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7735                                      misc_parameters_3);
7736         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7737         if (inner) {
7738                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7739                                          inner_headers);
7740                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7741         } else {
7742                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7743                                          outer_headers);
7744                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7745         }
7746         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
7747         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
7748         if (!icmp_v)
7749                 return;
7750         if (!icmp_m)
7751                 icmp_m = &rte_flow_item_icmp_mask;
7752         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
7753                  icmp_m->hdr.icmp_type);
7754         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
7755                  icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
7756         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
7757                  icmp_m->hdr.icmp_code);
7758         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
7759                  icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
7760         icmp_header_data_m = rte_be_to_cpu_16(icmp_m->hdr.icmp_seq_nb);
7761         icmp_header_data_m |= rte_be_to_cpu_16(icmp_m->hdr.icmp_ident) << 16;
7762         if (icmp_header_data_m) {
7763                 icmp_header_data_v = rte_be_to_cpu_16(icmp_v->hdr.icmp_seq_nb);
7764                 icmp_header_data_v |=
7765                          rte_be_to_cpu_16(icmp_v->hdr.icmp_ident) << 16;
7766                 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_header_data,
7767                          icmp_header_data_m);
7768                 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_header_data,
7769                          icmp_header_data_v & icmp_header_data_m);
7770         }
7771 }
7772
7773 /**
7774  * Add GTP item to matcher and to the value.
7775  *
7776  * @param[in, out] matcher
7777  *   Flow matcher.
7778  * @param[in, out] key
7779  *   Flow matcher value.
7780  * @param[in] item
7781  *   Flow pattern to translate.
7782  * @param[in] inner
7783  *   Item is inner pattern.
7784  */
7785 static void
7786 flow_dv_translate_item_gtp(void *matcher, void *key,
7787                            const struct rte_flow_item *item, int inner)
7788 {
7789         const struct rte_flow_item_gtp *gtp_m = item->mask;
7790         const struct rte_flow_item_gtp *gtp_v = item->spec;
7791         void *headers_m;
7792         void *headers_v;
7793         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7794                                      misc_parameters_3);
7795         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7796         uint16_t dport = RTE_GTPU_UDP_PORT;
7797
7798         if (inner) {
7799                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7800                                          inner_headers);
7801                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7802         } else {
7803                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7804                                          outer_headers);
7805                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7806         }
7807         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7808                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7809                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7810         }
7811         if (!gtp_v)
7812                 return;
7813         if (!gtp_m)
7814                 gtp_m = &rte_flow_item_gtp_mask;
7815         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags,
7816                  gtp_m->v_pt_rsv_flags);
7817         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags,
7818                  gtp_v->v_pt_rsv_flags & gtp_m->v_pt_rsv_flags);
7819         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
7820         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
7821                  gtp_v->msg_type & gtp_m->msg_type);
7822         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
7823                  rte_be_to_cpu_32(gtp_m->teid));
7824         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
7825                  rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
7826 }
7827
7828 /**
7829  * Add eCPRI item to matcher and to the value.
7830  *
7831  * @param[in] dev
7832  *   The devich to configure through.
7833  * @param[in, out] matcher
7834  *   Flow matcher.
7835  * @param[in, out] key
7836  *   Flow matcher value.
7837  * @param[in] item
7838  *   Flow pattern to translate.
7839  * @param[in] samples
7840  *   Sample IDs to be used in the matching.
7841  */
7842 static void
7843 flow_dv_translate_item_ecpri(struct rte_eth_dev *dev, void *matcher,
7844                              void *key, const struct rte_flow_item *item)
7845 {
7846         struct mlx5_priv *priv = dev->data->dev_private;
7847         const struct rte_flow_item_ecpri *ecpri_m = item->mask;
7848         const struct rte_flow_item_ecpri *ecpri_v = item->spec;
7849         struct rte_ecpri_common_hdr common;
7850         void *misc4_m = MLX5_ADDR_OF(fte_match_param, matcher,
7851                                      misc_parameters_4);
7852         void *misc4_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_4);
7853         uint32_t *samples;
7854         void *dw_m;
7855         void *dw_v;
7856
7857         if (!ecpri_v)
7858                 return;
7859         if (!ecpri_m)
7860                 ecpri_m = &rte_flow_item_ecpri_mask;
7861         /*
7862          * Maximal four DW samples are supported in a single matching now.
7863          * Two are used now for a eCPRI matching:
7864          * 1. Type: one byte, mask should be 0x00ff0000 in network order
7865          * 2. ID of a message: one or two bytes, mask 0xffff0000 or 0xff000000
7866          *    if any.
7867          */
7868         if (!ecpri_m->hdr.common.u32)
7869                 return;
7870         samples = priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0].ids;
7871         /* Need to take the whole DW as the mask to fill the entry. */
7872         dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
7873                             prog_sample_field_value_0);
7874         dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
7875                             prog_sample_field_value_0);
7876         /* Already big endian (network order) in the header. */
7877         *(uint32_t *)dw_m = ecpri_m->hdr.common.u32;
7878         *(uint32_t *)dw_v = ecpri_v->hdr.common.u32;
7879         /* Sample#0, used for matching type, offset 0. */
7880         MLX5_SET(fte_match_set_misc4, misc4_m,
7881                  prog_sample_field_id_0, samples[0]);
7882         /* It makes no sense to set the sample ID in the mask field. */
7883         MLX5_SET(fte_match_set_misc4, misc4_v,
7884                  prog_sample_field_id_0, samples[0]);
7885         /*
7886          * Checking if message body part needs to be matched.
7887          * Some wildcard rules only matching type field should be supported.
7888          */
7889         if (ecpri_m->hdr.dummy[0]) {
7890                 common.u32 = rte_be_to_cpu_32(ecpri_v->hdr.common.u32);
7891                 switch (common.type) {
7892                 case RTE_ECPRI_MSG_TYPE_IQ_DATA:
7893                 case RTE_ECPRI_MSG_TYPE_RTC_CTRL:
7894                 case RTE_ECPRI_MSG_TYPE_DLY_MSR:
7895                         dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
7896                                             prog_sample_field_value_1);
7897                         dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
7898                                             prog_sample_field_value_1);
7899                         *(uint32_t *)dw_m = ecpri_m->hdr.dummy[0];
7900                         *(uint32_t *)dw_v = ecpri_v->hdr.dummy[0];
7901                         /* Sample#1, to match message body, offset 4. */
7902                         MLX5_SET(fte_match_set_misc4, misc4_m,
7903                                  prog_sample_field_id_1, samples[1]);
7904                         MLX5_SET(fte_match_set_misc4, misc4_v,
7905                                  prog_sample_field_id_1, samples[1]);
7906                         break;
7907                 default:
7908                         /* Others, do not match any sample ID. */
7909                         break;
7910                 }
7911         }
7912 }
7913
7914 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
7915
7916 #define HEADER_IS_ZERO(match_criteria, headers)                              \
7917         !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers),     \
7918                  matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
7919
7920 /**
7921  * Calculate flow matcher enable bitmap.
7922  *
7923  * @param match_criteria
7924  *   Pointer to flow matcher criteria.
7925  *
7926  * @return
7927  *   Bitmap of enabled fields.
7928  */
7929 static uint8_t
7930 flow_dv_matcher_enable(uint32_t *match_criteria)
7931 {
7932         uint8_t match_criteria_enable;
7933
7934         match_criteria_enable =
7935                 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
7936                 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
7937         match_criteria_enable |=
7938                 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
7939                 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
7940         match_criteria_enable |=
7941                 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
7942                 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
7943         match_criteria_enable |=
7944                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
7945                 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
7946         match_criteria_enable |=
7947                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
7948                 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
7949         match_criteria_enable |=
7950                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_4)) <<
7951                 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT;
7952         return match_criteria_enable;
7953 }
7954
7955 struct mlx5_hlist_entry *
7956 flow_dv_tbl_create_cb(struct mlx5_hlist *list, uint64_t key64, void *cb_ctx)
7957 {
7958         struct mlx5_dev_ctx_shared *sh = list->ctx;
7959         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
7960         struct rte_eth_dev *dev = ctx->dev;
7961         struct mlx5_flow_tbl_data_entry *tbl_data;
7962         struct mlx5_flow_tbl_tunnel_prm *tt_prm = ctx->data;
7963         struct rte_flow_error *error = ctx->error;
7964         union mlx5_flow_tbl_key key = { .v64 = key64 };
7965         struct mlx5_flow_tbl_resource *tbl;
7966         void *domain;
7967         uint32_t idx = 0;
7968         int ret;
7969
7970         tbl_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
7971         if (!tbl_data) {
7972                 rte_flow_error_set(error, ENOMEM,
7973                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7974                                    NULL,
7975                                    "cannot allocate flow table data entry");
7976                 return NULL;
7977         }
7978         tbl_data->idx = idx;
7979         tbl_data->tunnel = tt_prm->tunnel;
7980         tbl_data->group_id = tt_prm->group_id;
7981         tbl_data->external = tt_prm->external;
7982         tbl_data->tunnel_offload = is_tunnel_offload_active(dev);
7983         tbl_data->is_egress = !!key.direction;
7984         tbl = &tbl_data->tbl;
7985         if (key.dummy)
7986                 return &tbl_data->entry;
7987         if (key.domain)
7988                 domain = sh->fdb_domain;
7989         else if (key.direction)
7990                 domain = sh->tx_domain;
7991         else
7992                 domain = sh->rx_domain;
7993         ret = mlx5_flow_os_create_flow_tbl(domain, key.table_id, &tbl->obj);
7994         if (ret) {
7995                 rte_flow_error_set(error, ENOMEM,
7996                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7997                                    NULL, "cannot create flow table object");
7998                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
7999                 return NULL;
8000         }
8001         if (key.table_id) {
8002                 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
8003                                         (tbl->obj, &tbl_data->jump.action);
8004                 if (ret) {
8005                         rte_flow_error_set(error, ENOMEM,
8006                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8007                                            NULL,
8008                                            "cannot create flow jump action");
8009                         mlx5_flow_os_destroy_flow_tbl(tbl->obj);
8010                         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
8011                         return NULL;
8012                 }
8013         }
8014         MKSTR(matcher_name, "%s_%s_%u_matcher_cache",
8015               key.domain ? "FDB" : "NIC", key.direction ? "egress" : "ingress",
8016               key.table_id);
8017         mlx5_cache_list_init(&tbl_data->matchers, matcher_name, 0, sh,
8018                              flow_dv_matcher_create_cb,
8019                              flow_dv_matcher_match_cb,
8020                              flow_dv_matcher_remove_cb);
8021         return &tbl_data->entry;
8022 }
8023
8024 /**
8025  * Get a flow table.
8026  *
8027  * @param[in, out] dev
8028  *   Pointer to rte_eth_dev structure.
8029  * @param[in] table_id
8030  *   Table id to use.
8031  * @param[in] egress
8032  *   Direction of the table.
8033  * @param[in] transfer
8034  *   E-Switch or NIC flow.
8035  * @param[in] dummy
8036  *   Dummy entry for dv API.
8037  * @param[out] error
8038  *   pointer to error structure.
8039  *
8040  * @return
8041  *   Returns tables resource based on the index, NULL in case of failed.
8042  */
8043 struct mlx5_flow_tbl_resource *
8044 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
8045                          uint32_t table_id, uint8_t egress,
8046                          uint8_t transfer,
8047                          bool external,
8048                          const struct mlx5_flow_tunnel *tunnel,
8049                          uint32_t group_id, uint8_t dummy,
8050                          struct rte_flow_error *error)
8051 {
8052         struct mlx5_priv *priv = dev->data->dev_private;
8053         union mlx5_flow_tbl_key table_key = {
8054                 {
8055                         .table_id = table_id,
8056                         .dummy = dummy,
8057                         .domain = !!transfer,
8058                         .direction = !!egress,
8059                 }
8060         };
8061         struct mlx5_flow_tbl_tunnel_prm tt_prm = {
8062                 .tunnel = tunnel,
8063                 .group_id = group_id,
8064                 .external = external,
8065         };
8066         struct mlx5_flow_cb_ctx ctx = {
8067                 .dev = dev,
8068                 .error = error,
8069                 .data = &tt_prm,
8070         };
8071         struct mlx5_hlist_entry *entry;
8072         struct mlx5_flow_tbl_data_entry *tbl_data;
8073
8074         entry = mlx5_hlist_register(priv->sh->flow_tbls, table_key.v64, &ctx);
8075         if (!entry) {
8076                 rte_flow_error_set(error, ENOMEM,
8077                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8078                                    "cannot get table");
8079                 return NULL;
8080         }
8081         DRV_LOG(DEBUG, "Table_id %u tunnel %u group %u registered.",
8082                 table_id, tunnel ? tunnel->tunnel_id : 0, group_id);
8083         tbl_data = container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
8084         return &tbl_data->tbl;
8085 }
8086
8087 void
8088 flow_dv_tbl_remove_cb(struct mlx5_hlist *list,
8089                       struct mlx5_hlist_entry *entry)
8090 {
8091         struct mlx5_dev_ctx_shared *sh = list->ctx;
8092         struct mlx5_flow_tbl_data_entry *tbl_data =
8093                 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
8094
8095         MLX5_ASSERT(entry && sh);
8096         if (tbl_data->jump.action)
8097                 mlx5_flow_os_destroy_flow_action(tbl_data->jump.action);
8098         if (tbl_data->tbl.obj)
8099                 mlx5_flow_os_destroy_flow_tbl(tbl_data->tbl.obj);
8100         if (tbl_data->tunnel_offload && tbl_data->external) {
8101                 struct mlx5_hlist_entry *he;
8102                 struct mlx5_hlist *tunnel_grp_hash;
8103                 struct mlx5_flow_tunnel_hub *thub = sh->tunnel_hub;
8104                 union tunnel_tbl_key tunnel_key = {
8105                         .tunnel_id = tbl_data->tunnel ?
8106                                         tbl_data->tunnel->tunnel_id : 0,
8107                         .group = tbl_data->group_id
8108                 };
8109                 union mlx5_flow_tbl_key table_key = {
8110                         .v64 = entry->key
8111                 };
8112                 uint32_t table_id = table_key.table_id;
8113
8114                 tunnel_grp_hash = tbl_data->tunnel ?
8115                                         tbl_data->tunnel->groups :
8116                                         thub->groups;
8117                 he = mlx5_hlist_lookup(tunnel_grp_hash, tunnel_key.val, NULL);
8118                 if (he)
8119                         mlx5_hlist_unregister(tunnel_grp_hash, he);
8120                 DRV_LOG(DEBUG,
8121                         "Table_id %u tunnel %u group %u released.",
8122                         table_id,
8123                         tbl_data->tunnel ?
8124                         tbl_data->tunnel->tunnel_id : 0,
8125                         tbl_data->group_id);
8126         }
8127         mlx5_cache_list_destroy(&tbl_data->matchers);
8128         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], tbl_data->idx);
8129 }
8130
8131 /**
8132  * Release a flow table.
8133  *
8134  * @param[in] sh
8135  *   Pointer to device shared structure.
8136  * @param[in] tbl
8137  *   Table resource to be released.
8138  *
8139  * @return
8140  *   Returns 0 if table was released, else return 1;
8141  */
8142 static int
8143 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
8144                              struct mlx5_flow_tbl_resource *tbl)
8145 {
8146         struct mlx5_flow_tbl_data_entry *tbl_data =
8147                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
8148
8149         if (!tbl)
8150                 return 0;
8151         return mlx5_hlist_unregister(sh->flow_tbls, &tbl_data->entry);
8152 }
8153
8154 int
8155 flow_dv_matcher_match_cb(struct mlx5_cache_list *list __rte_unused,
8156                          struct mlx5_cache_entry *entry, void *cb_ctx)
8157 {
8158         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
8159         struct mlx5_flow_dv_matcher *ref = ctx->data;
8160         struct mlx5_flow_dv_matcher *cur = container_of(entry, typeof(*cur),
8161                                                         entry);
8162
8163         return cur->crc != ref->crc ||
8164                cur->priority != ref->priority ||
8165                memcmp((const void *)cur->mask.buf,
8166                       (const void *)ref->mask.buf, ref->mask.size);
8167 }
8168
8169 struct mlx5_cache_entry *
8170 flow_dv_matcher_create_cb(struct mlx5_cache_list *list,
8171                           struct mlx5_cache_entry *entry __rte_unused,
8172                           void *cb_ctx)
8173 {
8174         struct mlx5_dev_ctx_shared *sh = list->ctx;
8175         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
8176         struct mlx5_flow_dv_matcher *ref = ctx->data;
8177         struct mlx5_flow_dv_matcher *cache;
8178         struct mlx5dv_flow_matcher_attr dv_attr = {
8179                 .type = IBV_FLOW_ATTR_NORMAL,
8180                 .match_mask = (void *)&ref->mask,
8181         };
8182         struct mlx5_flow_tbl_data_entry *tbl = container_of(ref->tbl,
8183                                                             typeof(*tbl), tbl);
8184         int ret;
8185
8186         cache = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*cache), 0, SOCKET_ID_ANY);
8187         if (!cache) {
8188                 rte_flow_error_set(ctx->error, ENOMEM,
8189                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8190                                    "cannot create matcher");
8191                 return NULL;
8192         }
8193         *cache = *ref;
8194         dv_attr.match_criteria_enable =
8195                 flow_dv_matcher_enable(cache->mask.buf);
8196         dv_attr.priority = ref->priority;
8197         if (tbl->is_egress)
8198                 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
8199         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->tbl.obj,
8200                                                &cache->matcher_object);
8201         if (ret) {
8202                 mlx5_free(cache);
8203                 rte_flow_error_set(ctx->error, ENOMEM,
8204                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8205                                    "cannot create matcher");
8206                 return NULL;
8207         }
8208         return &cache->entry;
8209 }
8210
8211 /**
8212  * Register the flow matcher.
8213  *
8214  * @param[in, out] dev
8215  *   Pointer to rte_eth_dev structure.
8216  * @param[in, out] matcher
8217  *   Pointer to flow matcher.
8218  * @param[in, out] key
8219  *   Pointer to flow table key.
8220  * @parm[in, out] dev_flow
8221  *   Pointer to the dev_flow.
8222  * @param[out] error
8223  *   pointer to error structure.
8224  *
8225  * @return
8226  *   0 on success otherwise -errno and errno is set.
8227  */
8228 static int
8229 flow_dv_matcher_register(struct rte_eth_dev *dev,
8230                          struct mlx5_flow_dv_matcher *ref,
8231                          union mlx5_flow_tbl_key *key,
8232                          struct mlx5_flow *dev_flow,
8233                          const struct mlx5_flow_tunnel *tunnel,
8234                          uint32_t group_id,
8235                          struct rte_flow_error *error)
8236 {
8237         struct mlx5_cache_entry *entry;
8238         struct mlx5_flow_dv_matcher *cache;
8239         struct mlx5_flow_tbl_resource *tbl;
8240         struct mlx5_flow_tbl_data_entry *tbl_data;
8241         struct mlx5_flow_cb_ctx ctx = {
8242                 .error = error,
8243                 .data = ref,
8244         };
8245
8246         /**
8247          * tunnel offload API requires this registration for cases when
8248          * tunnel match rule was inserted before tunnel set rule.
8249          */
8250         tbl = flow_dv_tbl_resource_get(dev, key->table_id,
8251                                        key->direction, key->domain,
8252                                        dev_flow->external, tunnel,
8253                                        group_id, 0, error);
8254         if (!tbl)
8255                 return -rte_errno;      /* No need to refill the error info */
8256         tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
8257         ref->tbl = tbl;
8258         entry = mlx5_cache_register(&tbl_data->matchers, &ctx);
8259         if (!entry) {
8260                 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
8261                 return rte_flow_error_set(error, ENOMEM,
8262                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8263                                           "cannot allocate ref memory");
8264         }
8265         cache = container_of(entry, typeof(*cache), entry);
8266         dev_flow->handle->dvh.matcher = cache;
8267         return 0;
8268 }
8269
8270 struct mlx5_hlist_entry *
8271 flow_dv_tag_create_cb(struct mlx5_hlist *list, uint64_t key, void *ctx)
8272 {
8273         struct mlx5_dev_ctx_shared *sh = list->ctx;
8274         struct rte_flow_error *error = ctx;
8275         struct mlx5_flow_dv_tag_resource *entry;
8276         uint32_t idx = 0;
8277         int ret;
8278
8279         entry = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_TAG], &idx);
8280         if (!entry) {
8281                 rte_flow_error_set(error, ENOMEM,
8282                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8283                                    "cannot allocate resource memory");
8284                 return NULL;
8285         }
8286         entry->idx = idx;
8287         ret = mlx5_flow_os_create_flow_action_tag(key,
8288                                                   &entry->action);
8289         if (ret) {
8290                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], idx);
8291                 rte_flow_error_set(error, ENOMEM,
8292                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8293                                    NULL, "cannot create action");
8294                 return NULL;
8295         }
8296         return &entry->entry;
8297 }
8298
8299 /**
8300  * Find existing tag resource or create and register a new one.
8301  *
8302  * @param dev[in, out]
8303  *   Pointer to rte_eth_dev structure.
8304  * @param[in, out] tag_be24
8305  *   Tag value in big endian then R-shift 8.
8306  * @parm[in, out] dev_flow
8307  *   Pointer to the dev_flow.
8308  * @param[out] error
8309  *   pointer to error structure.
8310  *
8311  * @return
8312  *   0 on success otherwise -errno and errno is set.
8313  */
8314 static int
8315 flow_dv_tag_resource_register
8316                         (struct rte_eth_dev *dev,
8317                          uint32_t tag_be24,
8318                          struct mlx5_flow *dev_flow,
8319                          struct rte_flow_error *error)
8320 {
8321         struct mlx5_priv *priv = dev->data->dev_private;
8322         struct mlx5_flow_dv_tag_resource *cache_resource;
8323         struct mlx5_hlist_entry *entry;
8324
8325         entry = mlx5_hlist_register(priv->sh->tag_table, tag_be24, error);
8326         if (entry) {
8327                 cache_resource = container_of
8328                         (entry, struct mlx5_flow_dv_tag_resource, entry);
8329                 dev_flow->handle->dvh.rix_tag = cache_resource->idx;
8330                 dev_flow->dv.tag_resource = cache_resource;
8331                 return 0;
8332         }
8333         return -rte_errno;
8334 }
8335
8336 void
8337 flow_dv_tag_remove_cb(struct mlx5_hlist *list,
8338                       struct mlx5_hlist_entry *entry)
8339 {
8340         struct mlx5_dev_ctx_shared *sh = list->ctx;
8341         struct mlx5_flow_dv_tag_resource *tag =
8342                 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
8343
8344         MLX5_ASSERT(tag && sh && tag->action);
8345         claim_zero(mlx5_flow_os_destroy_flow_action(tag->action));
8346         DRV_LOG(DEBUG, "Tag %p: removed.", (void *)tag);
8347         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], tag->idx);
8348 }
8349
8350 /**
8351  * Release the tag.
8352  *
8353  * @param dev
8354  *   Pointer to Ethernet device.
8355  * @param tag_idx
8356  *   Tag index.
8357  *
8358  * @return
8359  *   1 while a reference on it exists, 0 when freed.
8360  */
8361 static int
8362 flow_dv_tag_release(struct rte_eth_dev *dev,
8363                     uint32_t tag_idx)
8364 {
8365         struct mlx5_priv *priv = dev->data->dev_private;
8366         struct mlx5_flow_dv_tag_resource *tag;
8367
8368         tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
8369         if (!tag)
8370                 return 0;
8371         DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
8372                 dev->data->port_id, (void *)tag, tag->entry.ref_cnt);
8373         return mlx5_hlist_unregister(priv->sh->tag_table, &tag->entry);
8374 }
8375
8376 /**
8377  * Translate port ID action to vport.
8378  *
8379  * @param[in] dev
8380  *   Pointer to rte_eth_dev structure.
8381  * @param[in] action
8382  *   Pointer to the port ID action.
8383  * @param[out] dst_port_id
8384  *   The target port ID.
8385  * @param[out] error
8386  *   Pointer to the error structure.
8387  *
8388  * @return
8389  *   0 on success, a negative errno value otherwise and rte_errno is set.
8390  */
8391 static int
8392 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
8393                                  const struct rte_flow_action *action,
8394                                  uint32_t *dst_port_id,
8395                                  struct rte_flow_error *error)
8396 {
8397         uint32_t port;
8398         struct mlx5_priv *priv;
8399         const struct rte_flow_action_port_id *conf =
8400                         (const struct rte_flow_action_port_id *)action->conf;
8401
8402         port = conf->original ? dev->data->port_id : conf->id;
8403         priv = mlx5_port_to_eswitch_info(port, false);
8404         if (!priv)
8405                 return rte_flow_error_set(error, -rte_errno,
8406                                           RTE_FLOW_ERROR_TYPE_ACTION,
8407                                           NULL,
8408                                           "No eswitch info was found for port");
8409 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
8410         /*
8411          * This parameter is transferred to
8412          * mlx5dv_dr_action_create_dest_ib_port().
8413          */
8414         *dst_port_id = priv->dev_port;
8415 #else
8416         /*
8417          * Legacy mode, no LAG configurations is supported.
8418          * This parameter is transferred to
8419          * mlx5dv_dr_action_create_dest_vport().
8420          */
8421         *dst_port_id = priv->vport_id;
8422 #endif
8423         return 0;
8424 }
8425
8426 /**
8427  * Create a counter with aging configuration.
8428  *
8429  * @param[in] dev
8430  *   Pointer to rte_eth_dev structure.
8431  * @param[out] count
8432  *   Pointer to the counter action configuration.
8433  * @param[in] age
8434  *   Pointer to the aging action configuration.
8435  *
8436  * @return
8437  *   Index to flow counter on success, 0 otherwise.
8438  */
8439 static uint32_t
8440 flow_dv_translate_create_counter(struct rte_eth_dev *dev,
8441                                 struct mlx5_flow *dev_flow,
8442                                 const struct rte_flow_action_count *count,
8443                                 const struct rte_flow_action_age *age)
8444 {
8445         uint32_t counter;
8446         struct mlx5_age_param *age_param;
8447
8448         if (count && count->shared)
8449                 counter = flow_dv_counter_get_shared(dev, count->id);
8450         else
8451                 counter = flow_dv_counter_alloc(dev, !!age);
8452         if (!counter || age == NULL)
8453                 return counter;
8454         age_param  = flow_dv_counter_idx_get_age(dev, counter);
8455         age_param->context = age->context ? age->context :
8456                 (void *)(uintptr_t)(dev_flow->flow_idx);
8457         age_param->timeout = age->timeout;
8458         age_param->port_id = dev->data->port_id;
8459         __atomic_store_n(&age_param->sec_since_last_hit, 0, __ATOMIC_RELAXED);
8460         __atomic_store_n(&age_param->state, AGE_CANDIDATE, __ATOMIC_RELAXED);
8461         return counter;
8462 }
8463
8464 /**
8465  * Add Tx queue matcher
8466  *
8467  * @param[in] dev
8468  *   Pointer to the dev struct.
8469  * @param[in, out] matcher
8470  *   Flow matcher.
8471  * @param[in, out] key
8472  *   Flow matcher value.
8473  * @param[in] item
8474  *   Flow pattern to translate.
8475  * @param[in] inner
8476  *   Item is inner pattern.
8477  */
8478 static void
8479 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
8480                                 void *matcher, void *key,
8481                                 const struct rte_flow_item *item)
8482 {
8483         const struct mlx5_rte_flow_item_tx_queue *queue_m;
8484         const struct mlx5_rte_flow_item_tx_queue *queue_v;
8485         void *misc_m =
8486                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8487         void *misc_v =
8488                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8489         struct mlx5_txq_ctrl *txq;
8490         uint32_t queue;
8491
8492
8493         queue_m = (const void *)item->mask;
8494         if (!queue_m)
8495                 return;
8496         queue_v = (const void *)item->spec;
8497         if (!queue_v)
8498                 return;
8499         txq = mlx5_txq_get(dev, queue_v->queue);
8500         if (!txq)
8501                 return;
8502         queue = txq->obj->sq->id;
8503         MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
8504         MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
8505                  queue & queue_m->queue);
8506         mlx5_txq_release(dev, queue_v->queue);
8507 }
8508
8509 /**
8510  * Set the hash fields according to the @p flow information.
8511  *
8512  * @param[in] dev_flow
8513  *   Pointer to the mlx5_flow.
8514  * @param[in] rss_desc
8515  *   Pointer to the mlx5_flow_rss_desc.
8516  */
8517 static void
8518 flow_dv_hashfields_set(struct mlx5_flow *dev_flow,
8519                        struct mlx5_flow_rss_desc *rss_desc)
8520 {
8521         uint64_t items = dev_flow->handle->layers;
8522         int rss_inner = 0;
8523         uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
8524
8525         dev_flow->hash_fields = 0;
8526 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
8527         if (rss_desc->level >= 2) {
8528                 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
8529                 rss_inner = 1;
8530         }
8531 #endif
8532         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
8533             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
8534                 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
8535                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
8536                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
8537                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
8538                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
8539                         else
8540                                 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
8541                 }
8542         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
8543                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
8544                 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
8545                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
8546                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
8547                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
8548                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
8549                         else
8550                                 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
8551                 }
8552         }
8553         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
8554             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
8555                 if (rss_types & ETH_RSS_UDP) {
8556                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
8557                                 dev_flow->hash_fields |=
8558                                                 IBV_RX_HASH_SRC_PORT_UDP;
8559                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
8560                                 dev_flow->hash_fields |=
8561                                                 IBV_RX_HASH_DST_PORT_UDP;
8562                         else
8563                                 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
8564                 }
8565         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
8566                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
8567                 if (rss_types & ETH_RSS_TCP) {
8568                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
8569                                 dev_flow->hash_fields |=
8570                                                 IBV_RX_HASH_SRC_PORT_TCP;
8571                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
8572                                 dev_flow->hash_fields |=
8573                                                 IBV_RX_HASH_DST_PORT_TCP;
8574                         else
8575                                 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
8576                 }
8577         }
8578 }
8579
8580 /**
8581  * Prepare an Rx Hash queue.
8582  *
8583  * @param dev
8584  *   Pointer to Ethernet device.
8585  * @param[in] dev_flow
8586  *   Pointer to the mlx5_flow.
8587  * @param[in] rss_desc
8588  *   Pointer to the mlx5_flow_rss_desc.
8589  * @param[out] hrxq_idx
8590  *   Hash Rx queue index.
8591  *
8592  * @return
8593  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
8594  */
8595 static struct mlx5_hrxq *
8596 flow_dv_hrxq_prepare(struct rte_eth_dev *dev,
8597                      struct mlx5_flow *dev_flow,
8598                      struct mlx5_flow_rss_desc *rss_desc,
8599                      uint32_t *hrxq_idx)
8600 {
8601         struct mlx5_priv *priv = dev->data->dev_private;
8602         struct mlx5_flow_handle *dh = dev_flow->handle;
8603         struct mlx5_hrxq *hrxq;
8604
8605         MLX5_ASSERT(rss_desc->queue_num);
8606         rss_desc->key_len = MLX5_RSS_HASH_KEY_LEN;
8607         rss_desc->hash_fields = dev_flow->hash_fields;
8608         rss_desc->tunnel = !!(dh->layers & MLX5_FLOW_LAYER_TUNNEL);
8609         rss_desc->shared_rss = 0;
8610         *hrxq_idx = mlx5_hrxq_get(dev, rss_desc);
8611         if (!*hrxq_idx)
8612                 return NULL;
8613         hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
8614                               *hrxq_idx);
8615         return hrxq;
8616 }
8617
8618 /**
8619  * Release sample sub action resource.
8620  *
8621  * @param[in, out] dev
8622  *   Pointer to rte_eth_dev structure.
8623  * @param[in] act_res
8624  *   Pointer to sample sub action resource.
8625  */
8626 static void
8627 flow_dv_sample_sub_actions_release(struct rte_eth_dev *dev,
8628                                    struct mlx5_flow_sub_actions_idx *act_res)
8629 {
8630         if (act_res->rix_hrxq) {
8631                 mlx5_hrxq_release(dev, act_res->rix_hrxq);
8632                 act_res->rix_hrxq = 0;
8633         }
8634         if (act_res->rix_encap_decap) {
8635                 flow_dv_encap_decap_resource_release(dev,
8636                                                      act_res->rix_encap_decap);
8637                 act_res->rix_encap_decap = 0;
8638         }
8639         if (act_res->rix_port_id_action) {
8640                 flow_dv_port_id_action_resource_release(dev,
8641                                                 act_res->rix_port_id_action);
8642                 act_res->rix_port_id_action = 0;
8643         }
8644         if (act_res->rix_tag) {
8645                 flow_dv_tag_release(dev, act_res->rix_tag);
8646                 act_res->rix_tag = 0;
8647         }
8648         if (act_res->cnt) {
8649                 flow_dv_counter_free(dev, act_res->cnt);
8650                 act_res->cnt = 0;
8651         }
8652 }
8653
8654 int
8655 flow_dv_sample_match_cb(struct mlx5_cache_list *list __rte_unused,
8656                         struct mlx5_cache_entry *entry, void *cb_ctx)
8657 {
8658         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
8659         struct rte_eth_dev *dev = ctx->dev;
8660         struct mlx5_flow_dv_sample_resource *resource = ctx->data;
8661         struct mlx5_flow_dv_sample_resource *cache_resource =
8662                         container_of(entry, typeof(*cache_resource), entry);
8663
8664         if (resource->ratio == cache_resource->ratio &&
8665             resource->ft_type == cache_resource->ft_type &&
8666             resource->ft_id == cache_resource->ft_id &&
8667             resource->set_action == cache_resource->set_action &&
8668             !memcmp((void *)&resource->sample_act,
8669                     (void *)&cache_resource->sample_act,
8670                     sizeof(struct mlx5_flow_sub_actions_list))) {
8671                 /*
8672                  * Existing sample action should release the prepared
8673                  * sub-actions reference counter.
8674                  */
8675                 flow_dv_sample_sub_actions_release(dev,
8676                                                 &resource->sample_idx);
8677                 return 0;
8678         }
8679         return 1;
8680 }
8681
8682 struct mlx5_cache_entry *
8683 flow_dv_sample_create_cb(struct mlx5_cache_list *list __rte_unused,
8684                          struct mlx5_cache_entry *entry __rte_unused,
8685                          void *cb_ctx)
8686 {
8687         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
8688         struct rte_eth_dev *dev = ctx->dev;
8689         struct mlx5_flow_dv_sample_resource *resource = ctx->data;
8690         void **sample_dv_actions = resource->sub_actions;
8691         struct mlx5_flow_dv_sample_resource *cache_resource;
8692         struct mlx5dv_dr_flow_sampler_attr sampler_attr;
8693         struct mlx5_priv *priv = dev->data->dev_private;
8694         struct mlx5_dev_ctx_shared *sh = priv->sh;
8695         struct mlx5_flow_tbl_resource *tbl;
8696         uint32_t idx = 0;
8697         const uint32_t next_ft_step = 1;
8698         uint32_t next_ft_id = resource->ft_id + next_ft_step;
8699         uint8_t is_egress = 0;
8700         uint8_t is_transfer = 0;
8701         struct rte_flow_error *error = ctx->error;
8702
8703         /* Register new sample resource. */
8704         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_SAMPLE], &idx);
8705         if (!cache_resource) {
8706                 rte_flow_error_set(error, ENOMEM,
8707                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8708                                           NULL,
8709                                           "cannot allocate resource memory");
8710                 return NULL;
8711         }
8712         *cache_resource = *resource;
8713         /* Create normal path table level */
8714         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
8715                 is_transfer = 1;
8716         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
8717                 is_egress = 1;
8718         tbl = flow_dv_tbl_resource_get(dev, next_ft_id,
8719                                         is_egress, is_transfer,
8720                                         true, NULL, 0, 0, error);
8721         if (!tbl) {
8722                 rte_flow_error_set(error, ENOMEM,
8723                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8724                                           NULL,
8725                                           "fail to create normal path table "
8726                                           "for sample");
8727                 goto error;
8728         }
8729         cache_resource->normal_path_tbl = tbl;
8730         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB) {
8731                 cache_resource->default_miss =
8732                                 mlx5_glue->dr_create_flow_action_default_miss();
8733                 if (!cache_resource->default_miss) {
8734                         rte_flow_error_set(error, ENOMEM,
8735                                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8736                                                 NULL,
8737                                                 "cannot create default miss "
8738                                                 "action");
8739                         goto error;
8740                 }
8741                 sample_dv_actions[resource->sample_act.actions_num++] =
8742                                                 cache_resource->default_miss;
8743         }
8744         /* Create a DR sample action */
8745         sampler_attr.sample_ratio = cache_resource->ratio;
8746         sampler_attr.default_next_table = tbl->obj;
8747         sampler_attr.num_sample_actions = resource->sample_act.actions_num;
8748         sampler_attr.sample_actions = (struct mlx5dv_dr_action **)
8749                                                         &sample_dv_actions[0];
8750         sampler_attr.action = cache_resource->set_action;
8751         cache_resource->verbs_action =
8752                 mlx5_glue->dr_create_flow_action_sampler(&sampler_attr);
8753         if (!cache_resource->verbs_action) {
8754                 rte_flow_error_set(error, ENOMEM,
8755                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8756                                         NULL, "cannot create sample action");
8757                 goto error;
8758         }
8759         cache_resource->idx = idx;
8760         cache_resource->dev = dev;
8761         return &cache_resource->entry;
8762 error:
8763         if (cache_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB &&
8764             cache_resource->default_miss)
8765                 claim_zero(mlx5_glue->destroy_flow_action
8766                                 (cache_resource->default_miss));
8767         else
8768                 flow_dv_sample_sub_actions_release(dev,
8769                                                    &cache_resource->sample_idx);
8770         if (cache_resource->normal_path_tbl)
8771                 flow_dv_tbl_resource_release(MLX5_SH(dev),
8772                                 cache_resource->normal_path_tbl);
8773         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_SAMPLE], idx);
8774         return NULL;
8775
8776 }
8777
8778 /**
8779  * Find existing sample resource or create and register a new one.
8780  *
8781  * @param[in, out] dev
8782  *   Pointer to rte_eth_dev structure.
8783  * @param[in] resource
8784  *   Pointer to sample resource.
8785  * @parm[in, out] dev_flow
8786  *   Pointer to the dev_flow.
8787  * @param[out] error
8788  *   pointer to error structure.
8789  *
8790  * @return
8791  *   0 on success otherwise -errno and errno is set.
8792  */
8793 static int
8794 flow_dv_sample_resource_register(struct rte_eth_dev *dev,
8795                          struct mlx5_flow_dv_sample_resource *resource,
8796                          struct mlx5_flow *dev_flow,
8797                          struct rte_flow_error *error)
8798 {
8799         struct mlx5_flow_dv_sample_resource *cache_resource;
8800         struct mlx5_cache_entry *entry;
8801         struct mlx5_priv *priv = dev->data->dev_private;
8802         struct mlx5_flow_cb_ctx ctx = {
8803                 .dev = dev,
8804                 .error = error,
8805                 .data = resource,
8806         };
8807
8808         entry = mlx5_cache_register(&priv->sh->sample_action_list, &ctx);
8809         if (!entry)
8810                 return -rte_errno;
8811         cache_resource = container_of(entry, typeof(*cache_resource), entry);
8812         dev_flow->handle->dvh.rix_sample = cache_resource->idx;
8813         dev_flow->dv.sample_res = cache_resource;
8814         return 0;
8815 }
8816
8817 int
8818 flow_dv_dest_array_match_cb(struct mlx5_cache_list *list __rte_unused,
8819                             struct mlx5_cache_entry *entry, void *cb_ctx)
8820 {
8821         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
8822         struct mlx5_flow_dv_dest_array_resource *resource = ctx->data;
8823         struct rte_eth_dev *dev = ctx->dev;
8824         struct mlx5_flow_dv_dest_array_resource *cache_resource =
8825                         container_of(entry, typeof(*cache_resource), entry);
8826         uint32_t idx = 0;
8827
8828         if (resource->num_of_dest == cache_resource->num_of_dest &&
8829             resource->ft_type == cache_resource->ft_type &&
8830             !memcmp((void *)cache_resource->sample_act,
8831                     (void *)resource->sample_act,
8832                    (resource->num_of_dest *
8833                    sizeof(struct mlx5_flow_sub_actions_list)))) {
8834                 /*
8835                  * Existing sample action should release the prepared
8836                  * sub-actions reference counter.
8837                  */
8838                 for (idx = 0; idx < resource->num_of_dest; idx++)
8839                         flow_dv_sample_sub_actions_release(dev,
8840                                         &resource->sample_idx[idx]);
8841                 return 0;
8842         }
8843         return 1;
8844 }
8845
8846 struct mlx5_cache_entry *
8847 flow_dv_dest_array_create_cb(struct mlx5_cache_list *list __rte_unused,
8848                          struct mlx5_cache_entry *entry __rte_unused,
8849                          void *cb_ctx)
8850 {
8851         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
8852         struct rte_eth_dev *dev = ctx->dev;
8853         struct mlx5_flow_dv_dest_array_resource *cache_resource;
8854         struct mlx5_flow_dv_dest_array_resource *resource = ctx->data;
8855         struct mlx5dv_dr_action_dest_attr *dest_attr[MLX5_MAX_DEST_NUM] = { 0 };
8856         struct mlx5dv_dr_action_dest_reformat dest_reformat[MLX5_MAX_DEST_NUM];
8857         struct mlx5_priv *priv = dev->data->dev_private;
8858         struct mlx5_dev_ctx_shared *sh = priv->sh;
8859         struct mlx5_flow_sub_actions_list *sample_act;
8860         struct mlx5dv_dr_domain *domain;
8861         uint32_t idx = 0, res_idx = 0;
8862         struct rte_flow_error *error = ctx->error;
8863
8864         /* Register new destination array resource. */
8865         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
8866                                             &res_idx);
8867         if (!cache_resource) {
8868                 rte_flow_error_set(error, ENOMEM,
8869                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8870                                           NULL,
8871                                           "cannot allocate resource memory");
8872                 return NULL;
8873         }
8874         *cache_resource = *resource;
8875         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
8876                 domain = sh->fdb_domain;
8877         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
8878                 domain = sh->rx_domain;
8879         else
8880                 domain = sh->tx_domain;
8881         for (idx = 0; idx < resource->num_of_dest; idx++) {
8882                 dest_attr[idx] = (struct mlx5dv_dr_action_dest_attr *)
8883                                  mlx5_malloc(MLX5_MEM_ZERO,
8884                                  sizeof(struct mlx5dv_dr_action_dest_attr),
8885                                  0, SOCKET_ID_ANY);
8886                 if (!dest_attr[idx]) {
8887                         rte_flow_error_set(error, ENOMEM,
8888                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8889                                            NULL,
8890                                            "cannot allocate resource memory");
8891                         goto error;
8892                 }
8893                 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST;
8894                 sample_act = &resource->sample_act[idx];
8895                 if (sample_act->action_flags == MLX5_FLOW_ACTION_QUEUE) {
8896                         dest_attr[idx]->dest = sample_act->dr_queue_action;
8897                 } else if (sample_act->action_flags ==
8898                           (MLX5_FLOW_ACTION_PORT_ID | MLX5_FLOW_ACTION_ENCAP)) {
8899                         dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST_REFORMAT;
8900                         dest_attr[idx]->dest_reformat = &dest_reformat[idx];
8901                         dest_attr[idx]->dest_reformat->reformat =
8902                                         sample_act->dr_encap_action;
8903                         dest_attr[idx]->dest_reformat->dest =
8904                                         sample_act->dr_port_id_action;
8905                 } else if (sample_act->action_flags ==
8906                            MLX5_FLOW_ACTION_PORT_ID) {
8907                         dest_attr[idx]->dest = sample_act->dr_port_id_action;
8908                 }
8909         }
8910         /* create a dest array actioin */
8911         cache_resource->action = mlx5_glue->dr_create_flow_action_dest_array
8912                                                 (domain,
8913                                                  cache_resource->num_of_dest,
8914                                                  dest_attr);
8915         if (!cache_resource->action) {
8916                 rte_flow_error_set(error, ENOMEM,
8917                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8918                                    NULL,
8919                                    "cannot create destination array action");
8920                 goto error;
8921         }
8922         cache_resource->idx = res_idx;
8923         cache_resource->dev = dev;
8924         for (idx = 0; idx < resource->num_of_dest; idx++)
8925                 mlx5_free(dest_attr[idx]);
8926         return &cache_resource->entry;
8927 error:
8928         for (idx = 0; idx < resource->num_of_dest; idx++) {
8929                 struct mlx5_flow_sub_actions_idx *act_res =
8930                                         &cache_resource->sample_idx[idx];
8931                 if (act_res->rix_hrxq &&
8932                     !mlx5_hrxq_release(dev,
8933                                 act_res->rix_hrxq))
8934                         act_res->rix_hrxq = 0;
8935                 if (act_res->rix_encap_decap &&
8936                         !flow_dv_encap_decap_resource_release(dev,
8937                                 act_res->rix_encap_decap))
8938                         act_res->rix_encap_decap = 0;
8939                 if (act_res->rix_port_id_action &&
8940                         !flow_dv_port_id_action_resource_release(dev,
8941                                 act_res->rix_port_id_action))
8942                         act_res->rix_port_id_action = 0;
8943                 if (dest_attr[idx])
8944                         mlx5_free(dest_attr[idx]);
8945         }
8946
8947         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DEST_ARRAY], res_idx);
8948         return NULL;
8949 }
8950
8951 /**
8952  * Find existing destination array resource or create and register a new one.
8953  *
8954  * @param[in, out] dev
8955  *   Pointer to rte_eth_dev structure.
8956  * @param[in] resource
8957  *   Pointer to destination array resource.
8958  * @parm[in, out] dev_flow
8959  *   Pointer to the dev_flow.
8960  * @param[out] error
8961  *   pointer to error structure.
8962  *
8963  * @return
8964  *   0 on success otherwise -errno and errno is set.
8965  */
8966 static int
8967 flow_dv_dest_array_resource_register(struct rte_eth_dev *dev,
8968                          struct mlx5_flow_dv_dest_array_resource *resource,
8969                          struct mlx5_flow *dev_flow,
8970                          struct rte_flow_error *error)
8971 {
8972         struct mlx5_flow_dv_dest_array_resource *cache_resource;
8973         struct mlx5_priv *priv = dev->data->dev_private;
8974         struct mlx5_cache_entry *entry;
8975         struct mlx5_flow_cb_ctx ctx = {
8976                 .dev = dev,
8977                 .error = error,
8978                 .data = resource,
8979         };
8980
8981         entry = mlx5_cache_register(&priv->sh->dest_array_list, &ctx);
8982         if (!entry)
8983                 return -rte_errno;
8984         cache_resource = container_of(entry, typeof(*cache_resource), entry);
8985         dev_flow->handle->dvh.rix_dest_array = cache_resource->idx;
8986         dev_flow->dv.dest_array_res = cache_resource;
8987         return 0;
8988 }
8989
8990 /**
8991  * Convert Sample action to DV specification.
8992  *
8993  * @param[in] dev
8994  *   Pointer to rte_eth_dev structure.
8995  * @param[in] action
8996  *   Pointer to action structure.
8997  * @param[in, out] dev_flow
8998  *   Pointer to the mlx5_flow.
8999  * @param[in] attr
9000  *   Pointer to the flow attributes.
9001  * @param[in, out] num_of_dest
9002  *   Pointer to the num of destination.
9003  * @param[in, out] sample_actions
9004  *   Pointer to sample actions list.
9005  * @param[in, out] res
9006  *   Pointer to sample resource.
9007  * @param[out] error
9008  *   Pointer to the error structure.
9009  *
9010  * @return
9011  *   0 on success, a negative errno value otherwise and rte_errno is set.
9012  */
9013 static int
9014 flow_dv_translate_action_sample(struct rte_eth_dev *dev,
9015                                 const struct rte_flow_action *action,
9016                                 struct mlx5_flow *dev_flow,
9017                                 const struct rte_flow_attr *attr,
9018                                 uint32_t *num_of_dest,
9019                                 void **sample_actions,
9020                                 struct mlx5_flow_dv_sample_resource *res,
9021                                 struct rte_flow_error *error)
9022 {
9023         struct mlx5_priv *priv = dev->data->dev_private;
9024         const struct rte_flow_action_sample *sample_action;
9025         const struct rte_flow_action *sub_actions;
9026         const struct rte_flow_action_queue *queue;
9027         struct mlx5_flow_sub_actions_list *sample_act;
9028         struct mlx5_flow_sub_actions_idx *sample_idx;
9029         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
9030         struct mlx5_flow_rss_desc *rss_desc;
9031         uint64_t action_flags = 0;
9032
9033         MLX5_ASSERT(wks);
9034         rss_desc = &wks->rss_desc;
9035         sample_act = &res->sample_act;
9036         sample_idx = &res->sample_idx;
9037         sample_action = (const struct rte_flow_action_sample *)action->conf;
9038         res->ratio = sample_action->ratio;
9039         sub_actions = sample_action->actions;
9040         for (; sub_actions->type != RTE_FLOW_ACTION_TYPE_END; sub_actions++) {
9041                 int type = sub_actions->type;
9042                 uint32_t pre_rix = 0;
9043                 void *pre_r;
9044                 switch (type) {
9045                 case RTE_FLOW_ACTION_TYPE_QUEUE:
9046                 {
9047                         struct mlx5_hrxq *hrxq;
9048                         uint32_t hrxq_idx;
9049
9050                         queue = sub_actions->conf;
9051                         rss_desc->queue_num = 1;
9052                         rss_desc->queue[0] = queue->index;
9053                         hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
9054                                                     rss_desc, &hrxq_idx);
9055                         if (!hrxq)
9056                                 return rte_flow_error_set
9057                                         (error, rte_errno,
9058                                          RTE_FLOW_ERROR_TYPE_ACTION,
9059                                          NULL,
9060                                          "cannot create fate queue");
9061                         sample_act->dr_queue_action = hrxq->action;
9062                         sample_idx->rix_hrxq = hrxq_idx;
9063                         sample_actions[sample_act->actions_num++] =
9064                                                 hrxq->action;
9065                         (*num_of_dest)++;
9066                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
9067                         if (action_flags & MLX5_FLOW_ACTION_MARK)
9068                                 dev_flow->handle->rix_hrxq = hrxq_idx;
9069                         dev_flow->handle->fate_action =
9070                                         MLX5_FLOW_FATE_QUEUE;
9071                         break;
9072                 }
9073                 case RTE_FLOW_ACTION_TYPE_MARK:
9074                 {
9075                         uint32_t tag_be = mlx5_flow_mark_set
9076                                 (((const struct rte_flow_action_mark *)
9077                                 (sub_actions->conf))->id);
9078
9079                         dev_flow->handle->mark = 1;
9080                         pre_rix = dev_flow->handle->dvh.rix_tag;
9081                         /* Save the mark resource before sample */
9082                         pre_r = dev_flow->dv.tag_resource;
9083                         if (flow_dv_tag_resource_register(dev, tag_be,
9084                                                   dev_flow, error))
9085                                 return -rte_errno;
9086                         MLX5_ASSERT(dev_flow->dv.tag_resource);
9087                         sample_act->dr_tag_action =
9088                                 dev_flow->dv.tag_resource->action;
9089                         sample_idx->rix_tag =
9090                                 dev_flow->handle->dvh.rix_tag;
9091                         sample_actions[sample_act->actions_num++] =
9092                                                 sample_act->dr_tag_action;
9093                         /* Recover the mark resource after sample */
9094                         dev_flow->dv.tag_resource = pre_r;
9095                         dev_flow->handle->dvh.rix_tag = pre_rix;
9096                         action_flags |= MLX5_FLOW_ACTION_MARK;
9097                         break;
9098                 }
9099                 case RTE_FLOW_ACTION_TYPE_COUNT:
9100                 {
9101                         uint32_t counter;
9102
9103                         counter = flow_dv_translate_create_counter(dev,
9104                                         dev_flow, sub_actions->conf, 0);
9105                         if (!counter)
9106                                 return rte_flow_error_set
9107                                                 (error, rte_errno,
9108                                                  RTE_FLOW_ERROR_TYPE_ACTION,
9109                                                  NULL,
9110                                                  "cannot create counter"
9111                                                  " object.");
9112                         sample_idx->cnt = counter;
9113                         sample_act->dr_cnt_action =
9114                                   (flow_dv_counter_get_by_idx(dev,
9115                                   counter, NULL))->action;
9116                         sample_actions[sample_act->actions_num++] =
9117                                                 sample_act->dr_cnt_action;
9118                         action_flags |= MLX5_FLOW_ACTION_COUNT;
9119                         break;
9120                 }
9121                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
9122                 {
9123                         struct mlx5_flow_dv_port_id_action_resource
9124                                         port_id_resource;
9125                         uint32_t port_id = 0;
9126
9127                         memset(&port_id_resource, 0, sizeof(port_id_resource));
9128                         /* Save the port id resource before sample */
9129                         pre_rix = dev_flow->handle->rix_port_id_action;
9130                         pre_r = dev_flow->dv.port_id_action;
9131                         if (flow_dv_translate_action_port_id(dev, sub_actions,
9132                                                              &port_id, error))
9133                                 return -rte_errno;
9134                         port_id_resource.port_id = port_id;
9135                         if (flow_dv_port_id_action_resource_register
9136                             (dev, &port_id_resource, dev_flow, error))
9137                                 return -rte_errno;
9138                         sample_act->dr_port_id_action =
9139                                 dev_flow->dv.port_id_action->action;
9140                         sample_idx->rix_port_id_action =
9141                                 dev_flow->handle->rix_port_id_action;
9142                         sample_actions[sample_act->actions_num++] =
9143                                                 sample_act->dr_port_id_action;
9144                         /* Recover the port id resource after sample */
9145                         dev_flow->dv.port_id_action = pre_r;
9146                         dev_flow->handle->rix_port_id_action = pre_rix;
9147                         (*num_of_dest)++;
9148                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
9149                         break;
9150                 }
9151                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
9152                         /* Save the encap resource before sample */
9153                         pre_rix = dev_flow->handle->dvh.rix_encap_decap;
9154                         pre_r = dev_flow->dv.encap_decap;
9155                         if (flow_dv_create_action_l2_encap(dev, sub_actions,
9156                                                            dev_flow,
9157                                                            attr->transfer,
9158                                                            error))
9159                                 return -rte_errno;
9160                         sample_act->dr_encap_action =
9161                                 dev_flow->dv.encap_decap->action;
9162                         sample_idx->rix_encap_decap =
9163                                 dev_flow->handle->dvh.rix_encap_decap;
9164                         sample_actions[sample_act->actions_num++] =
9165                                                 sample_act->dr_encap_action;
9166                         /* Recover the encap resource after sample */
9167                         dev_flow->dv.encap_decap = pre_r;
9168                         dev_flow->handle->dvh.rix_encap_decap = pre_rix;
9169                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
9170                         break;
9171                 default:
9172                         return rte_flow_error_set(error, EINVAL,
9173                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9174                                 NULL,
9175                                 "Not support for sampler action");
9176                 }
9177         }
9178         sample_act->action_flags = action_flags;
9179         res->ft_id = dev_flow->dv.group;
9180         if (attr->transfer) {
9181                 union {
9182                         uint32_t action_in[MLX5_ST_SZ_DW(set_action_in)];
9183                         uint64_t set_action;
9184                 } action_ctx = { .set_action = 0 };
9185
9186                 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
9187                 MLX5_SET(set_action_in, action_ctx.action_in, action_type,
9188                          MLX5_MODIFICATION_TYPE_SET);
9189                 MLX5_SET(set_action_in, action_ctx.action_in, field,
9190                          MLX5_MODI_META_REG_C_0);
9191                 MLX5_SET(set_action_in, action_ctx.action_in, data,
9192                          priv->vport_meta_tag);
9193                 res->set_action = action_ctx.set_action;
9194         } else if (attr->ingress) {
9195                 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
9196         } else {
9197                 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_TX;
9198         }
9199         return 0;
9200 }
9201
9202 /**
9203  * Convert Sample action to DV specification.
9204  *
9205  * @param[in] dev
9206  *   Pointer to rte_eth_dev structure.
9207  * @param[in, out] dev_flow
9208  *   Pointer to the mlx5_flow.
9209  * @param[in] num_of_dest
9210  *   The num of destination.
9211  * @param[in, out] res
9212  *   Pointer to sample resource.
9213  * @param[in, out] mdest_res
9214  *   Pointer to destination array resource.
9215  * @param[in] sample_actions
9216  *   Pointer to sample path actions list.
9217  * @param[in] action_flags
9218  *   Holds the actions detected until now.
9219  * @param[out] error
9220  *   Pointer to the error structure.
9221  *
9222  * @return
9223  *   0 on success, a negative errno value otherwise and rte_errno is set.
9224  */
9225 static int
9226 flow_dv_create_action_sample(struct rte_eth_dev *dev,
9227                              struct mlx5_flow *dev_flow,
9228                              uint32_t num_of_dest,
9229                              struct mlx5_flow_dv_sample_resource *res,
9230                              struct mlx5_flow_dv_dest_array_resource *mdest_res,
9231                              void **sample_actions,
9232                              uint64_t action_flags,
9233                              struct rte_flow_error *error)
9234 {
9235         /* update normal path action resource into last index of array */
9236         uint32_t dest_index = MLX5_MAX_DEST_NUM - 1;
9237         struct mlx5_flow_sub_actions_list *sample_act =
9238                                         &mdest_res->sample_act[dest_index];
9239         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
9240         struct mlx5_flow_rss_desc *rss_desc;
9241         uint32_t normal_idx = 0;
9242         struct mlx5_hrxq *hrxq;
9243         uint32_t hrxq_idx;
9244
9245         MLX5_ASSERT(wks);
9246         rss_desc = &wks->rss_desc;
9247         if (num_of_dest > 1) {
9248                 if (sample_act->action_flags & MLX5_FLOW_ACTION_QUEUE) {
9249                         /* Handle QP action for mirroring */
9250                         hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
9251                                                     rss_desc, &hrxq_idx);
9252                         if (!hrxq)
9253                                 return rte_flow_error_set
9254                                      (error, rte_errno,
9255                                       RTE_FLOW_ERROR_TYPE_ACTION,
9256                                       NULL,
9257                                       "cannot create rx queue");
9258                         normal_idx++;
9259                         mdest_res->sample_idx[dest_index].rix_hrxq = hrxq_idx;
9260                         sample_act->dr_queue_action = hrxq->action;
9261                         if (action_flags & MLX5_FLOW_ACTION_MARK)
9262                                 dev_flow->handle->rix_hrxq = hrxq_idx;
9263                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
9264                 }
9265                 if (sample_act->action_flags & MLX5_FLOW_ACTION_ENCAP) {
9266                         normal_idx++;
9267                         mdest_res->sample_idx[dest_index].rix_encap_decap =
9268                                 dev_flow->handle->dvh.rix_encap_decap;
9269                         sample_act->dr_encap_action =
9270                                 dev_flow->dv.encap_decap->action;
9271                 }
9272                 if (sample_act->action_flags & MLX5_FLOW_ACTION_PORT_ID) {
9273                         normal_idx++;
9274                         mdest_res->sample_idx[dest_index].rix_port_id_action =
9275                                 dev_flow->handle->rix_port_id_action;
9276                         sample_act->dr_port_id_action =
9277                                 dev_flow->dv.port_id_action->action;
9278                 }
9279                 sample_act->actions_num = normal_idx;
9280                 /* update sample action resource into first index of array */
9281                 mdest_res->ft_type = res->ft_type;
9282                 memcpy(&mdest_res->sample_idx[0], &res->sample_idx,
9283                                 sizeof(struct mlx5_flow_sub_actions_idx));
9284                 memcpy(&mdest_res->sample_act[0], &res->sample_act,
9285                                 sizeof(struct mlx5_flow_sub_actions_list));
9286                 mdest_res->num_of_dest = num_of_dest;
9287                 if (flow_dv_dest_array_resource_register(dev, mdest_res,
9288                                                          dev_flow, error))
9289                         return rte_flow_error_set(error, EINVAL,
9290                                                   RTE_FLOW_ERROR_TYPE_ACTION,
9291                                                   NULL, "can't create sample "
9292                                                   "action");
9293         } else {
9294                 res->sub_actions = sample_actions;
9295                 if (flow_dv_sample_resource_register(dev, res, dev_flow, error))
9296                         return rte_flow_error_set(error, EINVAL,
9297                                                   RTE_FLOW_ERROR_TYPE_ACTION,
9298                                                   NULL,
9299                                                   "can't create sample action");
9300         }
9301         return 0;
9302 }
9303
9304 /**
9305  * Remove an ASO age action from age actions list.
9306  *
9307  * @param[in] dev
9308  *   Pointer to the Ethernet device structure.
9309  * @param[in] age
9310  *   Pointer to the aso age action handler.
9311  */
9312 static void
9313 flow_dv_aso_age_remove_from_age(struct rte_eth_dev *dev,
9314                                 struct mlx5_aso_age_action *age)
9315 {
9316         struct mlx5_age_info *age_info;
9317         struct mlx5_age_param *age_param = &age->age_params;
9318         struct mlx5_priv *priv = dev->data->dev_private;
9319         uint16_t expected = AGE_CANDIDATE;
9320
9321         age_info = GET_PORT_AGE_INFO(priv);
9322         if (!__atomic_compare_exchange_n(&age_param->state, &expected,
9323                                          AGE_FREE, false, __ATOMIC_RELAXED,
9324                                          __ATOMIC_RELAXED)) {
9325                 /**
9326                  * We need the lock even it is age timeout,
9327                  * since age action may still in process.
9328                  */
9329                 rte_spinlock_lock(&age_info->aged_sl);
9330                 LIST_REMOVE(age, next);
9331                 rte_spinlock_unlock(&age_info->aged_sl);
9332                 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
9333         }
9334 }
9335
9336 /**
9337  * Release an ASO age action.
9338  *
9339  * @param[in] dev
9340  *   Pointer to the Ethernet device structure.
9341  * @param[in] age_idx
9342  *   Index of ASO age action to release.
9343  * @param[in] flow
9344  *   True if the release operation is during flow destroy operation.
9345  *   False if the release operation is during action destroy operation.
9346  *
9347  * @return
9348  *   0 when age action was removed, otherwise the number of references.
9349  */
9350 static int
9351 flow_dv_aso_age_release(struct rte_eth_dev *dev, uint32_t age_idx)
9352 {
9353         struct mlx5_priv *priv = dev->data->dev_private;
9354         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
9355         struct mlx5_aso_age_action *age = flow_aso_age_get_by_idx(dev, age_idx);
9356         uint32_t ret = __atomic_sub_fetch(&age->refcnt, 1, __ATOMIC_RELAXED);
9357
9358         if (!ret) {
9359                 flow_dv_aso_age_remove_from_age(dev, age);
9360                 rte_spinlock_lock(&mng->free_sl);
9361                 LIST_INSERT_HEAD(&mng->free, age, next);
9362                 rte_spinlock_unlock(&mng->free_sl);
9363         }
9364         return ret;
9365 }
9366
9367 /**
9368  * Resize the ASO age pools array by MLX5_CNT_CONTAINER_RESIZE pools.
9369  *
9370  * @param[in] dev
9371  *   Pointer to the Ethernet device structure.
9372  *
9373  * @return
9374  *   0 on success, otherwise negative errno value and rte_errno is set.
9375  */
9376 static int
9377 flow_dv_aso_age_pools_resize(struct rte_eth_dev *dev)
9378 {
9379         struct mlx5_priv *priv = dev->data->dev_private;
9380         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
9381         void *old_pools = mng->pools;
9382         uint32_t resize = mng->n + MLX5_CNT_CONTAINER_RESIZE;
9383         uint32_t mem_size = sizeof(struct mlx5_aso_age_pool *) * resize;
9384         void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
9385
9386         if (!pools) {
9387                 rte_errno = ENOMEM;
9388                 return -ENOMEM;
9389         }
9390         if (old_pools) {
9391                 memcpy(pools, old_pools,
9392                        mng->n * sizeof(struct mlx5_flow_counter_pool *));
9393                 mlx5_free(old_pools);
9394         } else {
9395                 /* First ASO flow hit allocation - starting ASO data-path. */
9396                 int ret = mlx5_aso_queue_start(priv->sh);
9397
9398                 if (ret) {
9399                         mlx5_free(pools);
9400                         return ret;
9401                 }
9402         }
9403         mng->n = resize;
9404         mng->pools = pools;
9405         return 0;
9406 }
9407
9408 /**
9409  * Create and initialize a new ASO aging pool.
9410  *
9411  * @param[in] dev
9412  *   Pointer to the Ethernet device structure.
9413  * @param[out] age_free
9414  *   Where to put the pointer of a new age action.
9415  *
9416  * @return
9417  *   The age actions pool pointer and @p age_free is set on success,
9418  *   NULL otherwise and rte_errno is set.
9419  */
9420 static struct mlx5_aso_age_pool *
9421 flow_dv_age_pool_create(struct rte_eth_dev *dev,
9422                         struct mlx5_aso_age_action **age_free)
9423 {
9424         struct mlx5_priv *priv = dev->data->dev_private;
9425         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
9426         struct mlx5_aso_age_pool *pool = NULL;
9427         struct mlx5_devx_obj *obj = NULL;
9428         uint32_t i;
9429
9430         obj = mlx5_devx_cmd_create_flow_hit_aso_obj(priv->sh->ctx,
9431                                                     priv->sh->pdn);
9432         if (!obj) {
9433                 rte_errno = ENODATA;
9434                 DRV_LOG(ERR, "Failed to create flow_hit_aso_obj using DevX.");
9435                 return NULL;
9436         }
9437         pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
9438         if (!pool) {
9439                 claim_zero(mlx5_devx_cmd_destroy(obj));
9440                 rte_errno = ENOMEM;
9441                 return NULL;
9442         }
9443         pool->flow_hit_aso_obj = obj;
9444         pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
9445         rte_spinlock_lock(&mng->resize_sl);
9446         pool->index = mng->next;
9447         /* Resize pools array if there is no room for the new pool in it. */
9448         if (pool->index == mng->n && flow_dv_aso_age_pools_resize(dev)) {
9449                 claim_zero(mlx5_devx_cmd_destroy(obj));
9450                 mlx5_free(pool);
9451                 rte_spinlock_unlock(&mng->resize_sl);
9452                 return NULL;
9453         }
9454         mng->pools[pool->index] = pool;
9455         mng->next++;
9456         rte_spinlock_unlock(&mng->resize_sl);
9457         /* Assign the first action in the new pool, the rest go to free list. */
9458         *age_free = &pool->actions[0];
9459         for (i = 1; i < MLX5_ASO_AGE_ACTIONS_PER_POOL; i++) {
9460                 pool->actions[i].offset = i;
9461                 LIST_INSERT_HEAD(&mng->free, &pool->actions[i], next);
9462         }
9463         return pool;
9464 }
9465
9466 /**
9467  * Allocate a ASO aging bit.
9468  *
9469  * @param[in] dev
9470  *   Pointer to the Ethernet device structure.
9471  *
9472  * @return
9473  *   Index to ASO age action on success, 0 otherwise and rte_errno is set.
9474  */
9475 static uint32_t
9476 flow_dv_aso_age_alloc(struct rte_eth_dev *dev)
9477 {
9478         struct mlx5_priv *priv = dev->data->dev_private;
9479         const struct mlx5_aso_age_pool *pool;
9480         struct mlx5_aso_age_action *age_free = NULL;
9481         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
9482
9483         MLX5_ASSERT(mng);
9484         /* Try to get the next free age action bit. */
9485         rte_spinlock_lock(&mng->free_sl);
9486         age_free = LIST_FIRST(&mng->free);
9487         if (age_free) {
9488                 LIST_REMOVE(age_free, next);
9489         } else if (!flow_dv_age_pool_create(dev, &age_free)) {
9490                 rte_spinlock_unlock(&mng->free_sl);
9491                 return 0; /* 0 is an error.*/
9492         }
9493         rte_spinlock_unlock(&mng->free_sl);
9494         pool = container_of
9495           ((const struct mlx5_aso_age_action (*)[MLX5_ASO_AGE_ACTIONS_PER_POOL])
9496                   (age_free - age_free->offset), const struct mlx5_aso_age_pool,
9497                                                                        actions);
9498         if (!age_free->dr_action) {
9499                 age_free->dr_action = mlx5_glue->dr_action_create_flow_hit
9500                                                 (pool->flow_hit_aso_obj->obj,
9501                                                  age_free->offset, REG_C_5);
9502                 if (!age_free->dr_action) {
9503                         rte_errno = errno;
9504                         rte_spinlock_lock(&mng->free_sl);
9505                         LIST_INSERT_HEAD(&mng->free, age_free, next);
9506                         rte_spinlock_unlock(&mng->free_sl);
9507                         return 0; /* 0 is an error.*/
9508                 }
9509         }
9510         __atomic_store_n(&age_free->refcnt, 1, __ATOMIC_RELAXED);
9511         return pool->index | ((age_free->offset + 1) << 16);
9512 }
9513
9514 /**
9515  * Create a age action using ASO mechanism.
9516  *
9517  * @param[in] dev
9518  *   Pointer to rte_eth_dev structure.
9519  * @param[in] age
9520  *   Pointer to the aging action configuration.
9521  *
9522  * @return
9523  *   Index to flow counter on success, 0 otherwise.
9524  */
9525 static uint32_t
9526 flow_dv_translate_create_aso_age(struct rte_eth_dev *dev,
9527                                  const struct rte_flow_action_age *age)
9528 {
9529         uint32_t age_idx = 0;
9530         struct mlx5_aso_age_action *aso_age;
9531
9532         age_idx = flow_dv_aso_age_alloc(dev);
9533         if (!age_idx)
9534                 return 0;
9535         aso_age = flow_aso_age_get_by_idx(dev, age_idx);
9536         aso_age->age_params.context = age->context;
9537         aso_age->age_params.timeout = age->timeout;
9538         aso_age->age_params.port_id = dev->data->port_id;
9539         __atomic_store_n(&aso_age->age_params.sec_since_last_hit, 0,
9540                          __ATOMIC_RELAXED);
9541         __atomic_store_n(&aso_age->age_params.state, AGE_CANDIDATE,
9542                          __ATOMIC_RELAXED);
9543         return age_idx;
9544 }
9545
9546 /**
9547  * Fill the flow with DV spec, lock free
9548  * (mutex should be acquired by caller).
9549  *
9550  * @param[in] dev
9551  *   Pointer to rte_eth_dev structure.
9552  * @param[in, out] dev_flow
9553  *   Pointer to the sub flow.
9554  * @param[in] attr
9555  *   Pointer to the flow attributes.
9556  * @param[in] items
9557  *   Pointer to the list of items.
9558  * @param[in] actions
9559  *   Pointer to the list of actions.
9560  * @param[out] error
9561  *   Pointer to the error structure.
9562  *
9563  * @return
9564  *   0 on success, a negative errno value otherwise and rte_errno is set.
9565  */
9566 static int
9567 flow_dv_translate(struct rte_eth_dev *dev,
9568                   struct mlx5_flow *dev_flow,
9569                   const struct rte_flow_attr *attr,
9570                   const struct rte_flow_item items[],
9571                   const struct rte_flow_action actions[],
9572                   struct rte_flow_error *error)
9573 {
9574         struct mlx5_priv *priv = dev->data->dev_private;
9575         struct mlx5_dev_config *dev_conf = &priv->config;
9576         struct rte_flow *flow = dev_flow->flow;
9577         struct mlx5_flow_handle *handle = dev_flow->handle;
9578         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
9579         struct mlx5_flow_rss_desc *rss_desc;
9580         uint64_t item_flags = 0;
9581         uint64_t last_item = 0;
9582         uint64_t action_flags = 0;
9583         uint64_t priority = attr->priority;
9584         struct mlx5_flow_dv_matcher matcher = {
9585                 .mask = {
9586                         .size = sizeof(matcher.mask.buf) -
9587                                 MLX5_ST_SZ_BYTES(fte_match_set_misc4),
9588                 },
9589         };
9590         int actions_n = 0;
9591         bool actions_end = false;
9592         union {
9593                 struct mlx5_flow_dv_modify_hdr_resource res;
9594                 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
9595                             sizeof(struct mlx5_modification_cmd) *
9596                             (MLX5_MAX_MODIFY_NUM + 1)];
9597         } mhdr_dummy;
9598         struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
9599         const struct rte_flow_action_count *count = NULL;
9600         const struct rte_flow_action_age *age = NULL;
9601         union flow_dv_attr flow_attr = { .attr = 0 };
9602         uint32_t tag_be;
9603         union mlx5_flow_tbl_key tbl_key;
9604         uint32_t modify_action_position = UINT32_MAX;
9605         void *match_mask = matcher.mask.buf;
9606         void *match_value = dev_flow->dv.value.buf;
9607         uint8_t next_protocol = 0xff;
9608         struct rte_vlan_hdr vlan = { 0 };
9609         struct mlx5_flow_dv_dest_array_resource mdest_res;
9610         struct mlx5_flow_dv_sample_resource sample_res;
9611         void *sample_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
9612         struct mlx5_flow_sub_actions_list *sample_act;
9613         uint32_t sample_act_pos = UINT32_MAX;
9614         uint32_t num_of_dest = 0;
9615         int tmp_actions_n = 0;
9616         uint32_t table;
9617         int ret = 0;
9618         const struct mlx5_flow_tunnel *tunnel;
9619         struct flow_grp_info grp_info = {
9620                 .external = !!dev_flow->external,
9621                 .transfer = !!attr->transfer,
9622                 .fdb_def_rule = !!priv->fdb_def_rule,
9623                 .skip_scale = !!dev_flow->skip_scale,
9624         };
9625
9626         if (!wks)
9627                 return rte_flow_error_set(error, ENOMEM,
9628                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9629                                           NULL,
9630                                           "failed to push flow workspace");
9631         rss_desc = &wks->rss_desc;
9632         memset(&mdest_res, 0, sizeof(struct mlx5_flow_dv_dest_array_resource));
9633         memset(&sample_res, 0, sizeof(struct mlx5_flow_dv_sample_resource));
9634         mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
9635                                            MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
9636         /* update normal path action resource into last index of array */
9637         sample_act = &mdest_res.sample_act[MLX5_MAX_DEST_NUM - 1];
9638         tunnel = is_flow_tunnel_match_rule(dev, attr, items, actions) ?
9639                  flow_items_to_tunnel(items) :
9640                  is_flow_tunnel_steer_rule(dev, attr, items, actions) ?
9641                  flow_actions_to_tunnel(actions) :
9642                  dev_flow->tunnel ? dev_flow->tunnel : NULL;
9643         mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
9644                                            MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
9645         grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
9646                                 (dev, tunnel, attr, items, actions);
9647         ret = mlx5_flow_group_to_table(dev, tunnel, attr->group, &table,
9648                                        &grp_info, error);
9649         if (ret)
9650                 return ret;
9651         dev_flow->dv.group = table;
9652         if (attr->transfer)
9653                 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
9654         if (priority == MLX5_FLOW_PRIO_RSVD)
9655                 priority = dev_conf->flow_prio - 1;
9656         /* number of actions must be set to 0 in case of dirty stack. */
9657         mhdr_res->actions_num = 0;
9658         if (is_flow_tunnel_match_rule(dev, attr, items, actions)) {
9659                 /*
9660                  * do not add decap action if match rule drops packet
9661                  * HW rejects rules with decap & drop
9662                  *
9663                  * if tunnel match rule was inserted before matching tunnel set
9664                  * rule flow table used in the match rule must be registered.
9665                  * current implementation handles that in the
9666                  * flow_dv_match_register() at the function end.
9667                  */
9668                 bool add_decap = true;
9669                 const struct rte_flow_action *ptr = actions;
9670
9671                 for (; ptr->type != RTE_FLOW_ACTION_TYPE_END; ptr++) {
9672                         if (ptr->type == RTE_FLOW_ACTION_TYPE_DROP) {
9673                                 add_decap = false;
9674                                 break;
9675                         }
9676                 }
9677                 if (add_decap) {
9678                         if (flow_dv_create_action_l2_decap(dev, dev_flow,
9679                                                            attr->transfer,
9680                                                            error))
9681                                 return -rte_errno;
9682                         dev_flow->dv.actions[actions_n++] =
9683                                         dev_flow->dv.encap_decap->action;
9684                         action_flags |= MLX5_FLOW_ACTION_DECAP;
9685                 }
9686         }
9687         for (; !actions_end ; actions++) {
9688                 const struct rte_flow_action_queue *queue;
9689                 const struct rte_flow_action_rss *rss;
9690                 const struct rte_flow_action *action = actions;
9691                 const uint8_t *rss_key;
9692                 const struct rte_flow_action_meter *mtr;
9693                 struct mlx5_flow_tbl_resource *tbl;
9694                 struct mlx5_aso_age_action *age_act;
9695                 uint32_t port_id = 0;
9696                 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
9697                 int action_type = actions->type;
9698                 const struct rte_flow_action *found_action = NULL;
9699                 struct mlx5_flow_meter *fm = NULL;
9700                 uint32_t jump_group = 0;
9701
9702                 if (!mlx5_flow_os_action_supported(action_type))
9703                         return rte_flow_error_set(error, ENOTSUP,
9704                                                   RTE_FLOW_ERROR_TYPE_ACTION,
9705                                                   actions,
9706                                                   "action not supported");
9707                 switch (action_type) {
9708                 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
9709                         action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
9710                         break;
9711                 case RTE_FLOW_ACTION_TYPE_VOID:
9712                         break;
9713                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
9714                         if (flow_dv_translate_action_port_id(dev, action,
9715                                                              &port_id, error))
9716                                 return -rte_errno;
9717                         port_id_resource.port_id = port_id;
9718                         MLX5_ASSERT(!handle->rix_port_id_action);
9719                         if (flow_dv_port_id_action_resource_register
9720                             (dev, &port_id_resource, dev_flow, error))
9721                                 return -rte_errno;
9722                         dev_flow->dv.actions[actions_n++] =
9723                                         dev_flow->dv.port_id_action->action;
9724                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
9725                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_PORT_ID;
9726                         sample_act->action_flags |= MLX5_FLOW_ACTION_PORT_ID;
9727                         num_of_dest++;
9728                         break;
9729                 case RTE_FLOW_ACTION_TYPE_FLAG:
9730                         action_flags |= MLX5_FLOW_ACTION_FLAG;
9731                         dev_flow->handle->mark = 1;
9732                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
9733                                 struct rte_flow_action_mark mark = {
9734                                         .id = MLX5_FLOW_MARK_DEFAULT,
9735                                 };
9736
9737                                 if (flow_dv_convert_action_mark(dev, &mark,
9738                                                                 mhdr_res,
9739                                                                 error))
9740                                         return -rte_errno;
9741                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
9742                                 break;
9743                         }
9744                         tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
9745                         /*
9746                          * Only one FLAG or MARK is supported per device flow
9747                          * right now. So the pointer to the tag resource must be
9748                          * zero before the register process.
9749                          */
9750                         MLX5_ASSERT(!handle->dvh.rix_tag);
9751                         if (flow_dv_tag_resource_register(dev, tag_be,
9752                                                           dev_flow, error))
9753                                 return -rte_errno;
9754                         MLX5_ASSERT(dev_flow->dv.tag_resource);
9755                         dev_flow->dv.actions[actions_n++] =
9756                                         dev_flow->dv.tag_resource->action;
9757                         break;
9758                 case RTE_FLOW_ACTION_TYPE_MARK:
9759                         action_flags |= MLX5_FLOW_ACTION_MARK;
9760                         dev_flow->handle->mark = 1;
9761                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
9762                                 const struct rte_flow_action_mark *mark =
9763                                         (const struct rte_flow_action_mark *)
9764                                                 actions->conf;
9765
9766                                 if (flow_dv_convert_action_mark(dev, mark,
9767                                                                 mhdr_res,
9768                                                                 error))
9769                                         return -rte_errno;
9770                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
9771                                 break;
9772                         }
9773                         /* Fall-through */
9774                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
9775                         /* Legacy (non-extensive) MARK action. */
9776                         tag_be = mlx5_flow_mark_set
9777                               (((const struct rte_flow_action_mark *)
9778                                (actions->conf))->id);
9779                         MLX5_ASSERT(!handle->dvh.rix_tag);
9780                         if (flow_dv_tag_resource_register(dev, tag_be,
9781                                                           dev_flow, error))
9782                                 return -rte_errno;
9783                         MLX5_ASSERT(dev_flow->dv.tag_resource);
9784                         dev_flow->dv.actions[actions_n++] =
9785                                         dev_flow->dv.tag_resource->action;
9786                         break;
9787                 case RTE_FLOW_ACTION_TYPE_SET_META:
9788                         if (flow_dv_convert_action_set_meta
9789                                 (dev, mhdr_res, attr,
9790                                  (const struct rte_flow_action_set_meta *)
9791                                   actions->conf, error))
9792                                 return -rte_errno;
9793                         action_flags |= MLX5_FLOW_ACTION_SET_META;
9794                         break;
9795                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
9796                         if (flow_dv_convert_action_set_tag
9797                                 (dev, mhdr_res,
9798                                  (const struct rte_flow_action_set_tag *)
9799                                   actions->conf, error))
9800                                 return -rte_errno;
9801                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
9802                         break;
9803                 case RTE_FLOW_ACTION_TYPE_DROP:
9804                         action_flags |= MLX5_FLOW_ACTION_DROP;
9805                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_DROP;
9806                         break;
9807                 case RTE_FLOW_ACTION_TYPE_QUEUE:
9808                         queue = actions->conf;
9809                         rss_desc->queue_num = 1;
9810                         rss_desc->queue[0] = queue->index;
9811                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
9812                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
9813                         sample_act->action_flags |= MLX5_FLOW_ACTION_QUEUE;
9814                         num_of_dest++;
9815                         break;
9816                 case RTE_FLOW_ACTION_TYPE_RSS:
9817                         rss = actions->conf;
9818                         memcpy(rss_desc->queue, rss->queue,
9819                                rss->queue_num * sizeof(uint16_t));
9820                         rss_desc->queue_num = rss->queue_num;
9821                         /* NULL RSS key indicates default RSS key. */
9822                         rss_key = !rss->key ? rss_hash_default_key : rss->key;
9823                         memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
9824                         /*
9825                          * rss->level and rss.types should be set in advance
9826                          * when expanding items for RSS.
9827                          */
9828                         action_flags |= MLX5_FLOW_ACTION_RSS;
9829                         dev_flow->handle->fate_action = rss_desc->shared_rss ?
9830                                 MLX5_FLOW_FATE_SHARED_RSS :
9831                                 MLX5_FLOW_FATE_QUEUE;
9832                         break;
9833                 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
9834                         flow->age = (uint32_t)(uintptr_t)(action->conf);
9835                         age_act = flow_aso_age_get_by_idx(dev, flow->age);
9836                         __atomic_fetch_add(&age_act->refcnt, 1,
9837                                            __ATOMIC_RELAXED);
9838                         dev_flow->dv.actions[actions_n++] = age_act->dr_action;
9839                         action_flags |= MLX5_FLOW_ACTION_AGE;
9840                         break;
9841                 case RTE_FLOW_ACTION_TYPE_AGE:
9842                         if (priv->sh->flow_hit_aso_en && attr->group) {
9843                                 flow->age = flow_dv_translate_create_aso_age
9844                                                 (dev, action->conf);
9845                                 if (!flow->age)
9846                                         return rte_flow_error_set
9847                                                 (error, rte_errno,
9848                                                  RTE_FLOW_ERROR_TYPE_ACTION,
9849                                                  NULL,
9850                                                  "can't create ASO age action");
9851                                 dev_flow->dv.actions[actions_n++] =
9852                                           (flow_aso_age_get_by_idx
9853                                                 (dev, flow->age))->dr_action;
9854                                 action_flags |= MLX5_FLOW_ACTION_AGE;
9855                                 break;
9856                         }
9857                         /* Fall-through */
9858                 case RTE_FLOW_ACTION_TYPE_COUNT:
9859                         if (!dev_conf->devx) {
9860                                 return rte_flow_error_set
9861                                               (error, ENOTSUP,
9862                                                RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9863                                                NULL,
9864                                                "count action not supported");
9865                         }
9866                         /* Save information first, will apply later. */
9867                         if (actions->type == RTE_FLOW_ACTION_TYPE_COUNT)
9868                                 count = action->conf;
9869                         else
9870                                 age = action->conf;
9871                         action_flags |= MLX5_FLOW_ACTION_COUNT;
9872                         break;
9873                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
9874                         dev_flow->dv.actions[actions_n++] =
9875                                                 priv->sh->pop_vlan_action;
9876                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
9877                         break;
9878                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
9879                         if (!(action_flags &
9880                               MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
9881                                 flow_dev_get_vlan_info_from_items(items, &vlan);
9882                         vlan.eth_proto = rte_be_to_cpu_16
9883                              ((((const struct rte_flow_action_of_push_vlan *)
9884                                                    actions->conf)->ethertype));
9885                         found_action = mlx5_flow_find_action
9886                                         (actions + 1,
9887                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
9888                         if (found_action)
9889                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
9890                         found_action = mlx5_flow_find_action
9891                                         (actions + 1,
9892                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
9893                         if (found_action)
9894                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
9895                         if (flow_dv_create_action_push_vlan
9896                                             (dev, attr, &vlan, dev_flow, error))
9897                                 return -rte_errno;
9898                         dev_flow->dv.actions[actions_n++] =
9899                                         dev_flow->dv.push_vlan_res->action;
9900                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
9901                         break;
9902                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
9903                         /* of_vlan_push action handled this action */
9904                         MLX5_ASSERT(action_flags &
9905                                     MLX5_FLOW_ACTION_OF_PUSH_VLAN);
9906                         break;
9907                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
9908                         if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
9909                                 break;
9910                         flow_dev_get_vlan_info_from_items(items, &vlan);
9911                         mlx5_update_vlan_vid_pcp(actions, &vlan);
9912                         /* If no VLAN push - this is a modify header action */
9913                         if (flow_dv_convert_action_modify_vlan_vid
9914                                                 (mhdr_res, actions, error))
9915                                 return -rte_errno;
9916                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
9917                         break;
9918                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
9919                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
9920                         if (flow_dv_create_action_l2_encap(dev, actions,
9921                                                            dev_flow,
9922                                                            attr->transfer,
9923                                                            error))
9924                                 return -rte_errno;
9925                         dev_flow->dv.actions[actions_n++] =
9926                                         dev_flow->dv.encap_decap->action;
9927                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
9928                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
9929                                 sample_act->action_flags |=
9930                                                         MLX5_FLOW_ACTION_ENCAP;
9931                         break;
9932                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
9933                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
9934                         if (flow_dv_create_action_l2_decap(dev, dev_flow,
9935                                                            attr->transfer,
9936                                                            error))
9937                                 return -rte_errno;
9938                         dev_flow->dv.actions[actions_n++] =
9939                                         dev_flow->dv.encap_decap->action;
9940                         action_flags |= MLX5_FLOW_ACTION_DECAP;
9941                         break;
9942                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
9943                         /* Handle encap with preceding decap. */
9944                         if (action_flags & MLX5_FLOW_ACTION_DECAP) {
9945                                 if (flow_dv_create_action_raw_encap
9946                                         (dev, actions, dev_flow, attr, error))
9947                                         return -rte_errno;
9948                                 dev_flow->dv.actions[actions_n++] =
9949                                         dev_flow->dv.encap_decap->action;
9950                         } else {
9951                                 /* Handle encap without preceding decap. */
9952                                 if (flow_dv_create_action_l2_encap
9953                                     (dev, actions, dev_flow, attr->transfer,
9954                                      error))
9955                                         return -rte_errno;
9956                                 dev_flow->dv.actions[actions_n++] =
9957                                         dev_flow->dv.encap_decap->action;
9958                         }
9959                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
9960                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
9961                                 sample_act->action_flags |=
9962                                                         MLX5_FLOW_ACTION_ENCAP;
9963                         break;
9964                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
9965                         while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
9966                                 ;
9967                         if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
9968                                 if (flow_dv_create_action_l2_decap
9969                                     (dev, dev_flow, attr->transfer, error))
9970                                         return -rte_errno;
9971                                 dev_flow->dv.actions[actions_n++] =
9972                                         dev_flow->dv.encap_decap->action;
9973                         }
9974                         /* If decap is followed by encap, handle it at encap. */
9975                         action_flags |= MLX5_FLOW_ACTION_DECAP;
9976                         break;
9977                 case RTE_FLOW_ACTION_TYPE_JUMP:
9978                         jump_group = ((const struct rte_flow_action_jump *)
9979                                                         action->conf)->group;
9980                         grp_info.std_tbl_fix = 0;
9981                         grp_info.skip_scale = 0;
9982                         ret = mlx5_flow_group_to_table(dev, tunnel,
9983                                                        jump_group,
9984                                                        &table,
9985                                                        &grp_info, error);
9986                         if (ret)
9987                                 return ret;
9988                         tbl = flow_dv_tbl_resource_get(dev, table, attr->egress,
9989                                                        attr->transfer,
9990                                                        !!dev_flow->external,
9991                                                        tunnel, jump_group, 0,
9992                                                        error);
9993                         if (!tbl)
9994                                 return rte_flow_error_set
9995                                                 (error, errno,
9996                                                  RTE_FLOW_ERROR_TYPE_ACTION,
9997                                                  NULL,
9998                                                  "cannot create jump action.");
9999                         if (flow_dv_jump_tbl_resource_register
10000                             (dev, tbl, dev_flow, error)) {
10001                                 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
10002                                 return rte_flow_error_set
10003                                                 (error, errno,
10004                                                  RTE_FLOW_ERROR_TYPE_ACTION,
10005                                                  NULL,
10006                                                  "cannot create jump action.");
10007                         }
10008                         dev_flow->dv.actions[actions_n++] =
10009                                         dev_flow->dv.jump->action;
10010                         action_flags |= MLX5_FLOW_ACTION_JUMP;
10011                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_JUMP;
10012                         break;
10013                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
10014                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
10015                         if (flow_dv_convert_action_modify_mac
10016                                         (mhdr_res, actions, error))
10017                                 return -rte_errno;
10018                         action_flags |= actions->type ==
10019                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
10020                                         MLX5_FLOW_ACTION_SET_MAC_SRC :
10021                                         MLX5_FLOW_ACTION_SET_MAC_DST;
10022                         break;
10023                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
10024                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
10025                         if (flow_dv_convert_action_modify_ipv4
10026                                         (mhdr_res, actions, error))
10027                                 return -rte_errno;
10028                         action_flags |= actions->type ==
10029                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
10030                                         MLX5_FLOW_ACTION_SET_IPV4_SRC :
10031                                         MLX5_FLOW_ACTION_SET_IPV4_DST;
10032                         break;
10033                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
10034                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
10035                         if (flow_dv_convert_action_modify_ipv6
10036                                         (mhdr_res, actions, error))
10037                                 return -rte_errno;
10038                         action_flags |= actions->type ==
10039                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
10040                                         MLX5_FLOW_ACTION_SET_IPV6_SRC :
10041                                         MLX5_FLOW_ACTION_SET_IPV6_DST;
10042                         break;
10043                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
10044                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
10045                         if (flow_dv_convert_action_modify_tp
10046                                         (mhdr_res, actions, items,
10047                                          &flow_attr, dev_flow, !!(action_flags &
10048                                          MLX5_FLOW_ACTION_DECAP), error))
10049                                 return -rte_errno;
10050                         action_flags |= actions->type ==
10051                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
10052                                         MLX5_FLOW_ACTION_SET_TP_SRC :
10053                                         MLX5_FLOW_ACTION_SET_TP_DST;
10054                         break;
10055                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
10056                         if (flow_dv_convert_action_modify_dec_ttl
10057                                         (mhdr_res, items, &flow_attr, dev_flow,
10058                                          !!(action_flags &
10059                                          MLX5_FLOW_ACTION_DECAP), error))
10060                                 return -rte_errno;
10061                         action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
10062                         break;
10063                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
10064                         if (flow_dv_convert_action_modify_ttl
10065                                         (mhdr_res, actions, items, &flow_attr,
10066                                          dev_flow, !!(action_flags &
10067                                          MLX5_FLOW_ACTION_DECAP), error))
10068                                 return -rte_errno;
10069                         action_flags |= MLX5_FLOW_ACTION_SET_TTL;
10070                         break;
10071                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
10072                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
10073                         if (flow_dv_convert_action_modify_tcp_seq
10074                                         (mhdr_res, actions, error))
10075                                 return -rte_errno;
10076                         action_flags |= actions->type ==
10077                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
10078                                         MLX5_FLOW_ACTION_INC_TCP_SEQ :
10079                                         MLX5_FLOW_ACTION_DEC_TCP_SEQ;
10080                         break;
10081
10082                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
10083                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
10084                         if (flow_dv_convert_action_modify_tcp_ack
10085                                         (mhdr_res, actions, error))
10086                                 return -rte_errno;
10087                         action_flags |= actions->type ==
10088                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
10089                                         MLX5_FLOW_ACTION_INC_TCP_ACK :
10090                                         MLX5_FLOW_ACTION_DEC_TCP_ACK;
10091                         break;
10092                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
10093                         if (flow_dv_convert_action_set_reg
10094                                         (mhdr_res, actions, error))
10095                                 return -rte_errno;
10096                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
10097                         break;
10098                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
10099                         if (flow_dv_convert_action_copy_mreg
10100                                         (dev, mhdr_res, actions, error))
10101                                 return -rte_errno;
10102                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
10103                         break;
10104                 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
10105                         action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
10106                         dev_flow->handle->fate_action =
10107                                         MLX5_FLOW_FATE_DEFAULT_MISS;
10108                         break;
10109                 case RTE_FLOW_ACTION_TYPE_METER:
10110                         mtr = actions->conf;
10111                         if (!flow->meter) {
10112                                 fm = mlx5_flow_meter_attach(priv, mtr->mtr_id,
10113                                                             attr, error);
10114                                 if (!fm)
10115                                         return rte_flow_error_set(error,
10116                                                 rte_errno,
10117                                                 RTE_FLOW_ERROR_TYPE_ACTION,
10118                                                 NULL,
10119                                                 "meter not found "
10120                                                 "or invalid parameters");
10121                                 flow->meter = fm->idx;
10122                         }
10123                         /* Set the meter action. */
10124                         if (!fm) {
10125                                 fm = mlx5_ipool_get(priv->sh->ipool
10126                                                 [MLX5_IPOOL_MTR], flow->meter);
10127                                 if (!fm)
10128                                         return rte_flow_error_set(error,
10129                                                 rte_errno,
10130                                                 RTE_FLOW_ERROR_TYPE_ACTION,
10131                                                 NULL,
10132                                                 "meter not found "
10133                                                 "or invalid parameters");
10134                         }
10135                         dev_flow->dv.actions[actions_n++] =
10136                                 fm->mfts->meter_action;
10137                         action_flags |= MLX5_FLOW_ACTION_METER;
10138                         break;
10139                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
10140                         if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
10141                                                               actions, error))
10142                                 return -rte_errno;
10143                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
10144                         break;
10145                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
10146                         if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
10147                                                               actions, error))
10148                                 return -rte_errno;
10149                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
10150                         break;
10151                 case RTE_FLOW_ACTION_TYPE_SAMPLE:
10152                         sample_act_pos = actions_n;
10153                         ret = flow_dv_translate_action_sample(dev,
10154                                                               actions,
10155                                                               dev_flow, attr,
10156                                                               &num_of_dest,
10157                                                               sample_actions,
10158                                                               &sample_res,
10159                                                               error);
10160                         if (ret < 0)
10161                                 return ret;
10162                         actions_n++;
10163                         action_flags |= MLX5_FLOW_ACTION_SAMPLE;
10164                         /* put encap action into group if work with port id */
10165                         if ((action_flags & MLX5_FLOW_ACTION_ENCAP) &&
10166                             (action_flags & MLX5_FLOW_ACTION_PORT_ID))
10167                                 sample_act->action_flags |=
10168                                                         MLX5_FLOW_ACTION_ENCAP;
10169                         break;
10170                 case RTE_FLOW_ACTION_TYPE_END:
10171                         actions_end = true;
10172                         if (mhdr_res->actions_num) {
10173                                 /* create modify action if needed. */
10174                                 if (flow_dv_modify_hdr_resource_register
10175                                         (dev, mhdr_res, dev_flow, error))
10176                                         return -rte_errno;
10177                                 dev_flow->dv.actions[modify_action_position] =
10178                                         handle->dvh.modify_hdr->action;
10179                         }
10180                         if (action_flags & MLX5_FLOW_ACTION_COUNT) {
10181                                 flow->counter =
10182                                         flow_dv_translate_create_counter(dev,
10183                                                 dev_flow, count, age);
10184
10185                                 if (!flow->counter)
10186                                         return rte_flow_error_set
10187                                                 (error, rte_errno,
10188                                                 RTE_FLOW_ERROR_TYPE_ACTION,
10189                                                 NULL,
10190                                                 "cannot create counter"
10191                                                 " object.");
10192                                 dev_flow->dv.actions[actions_n] =
10193                                           (flow_dv_counter_get_by_idx(dev,
10194                                           flow->counter, NULL))->action;
10195                                 actions_n++;
10196                         }
10197                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE) {
10198                                 ret = flow_dv_create_action_sample(dev,
10199                                                           dev_flow,
10200                                                           num_of_dest,
10201                                                           &sample_res,
10202                                                           &mdest_res,
10203                                                           sample_actions,
10204                                                           action_flags,
10205                                                           error);
10206                                 if (ret < 0)
10207                                         return rte_flow_error_set
10208                                                 (error, rte_errno,
10209                                                 RTE_FLOW_ERROR_TYPE_ACTION,
10210                                                 NULL,
10211                                                 "cannot create sample action");
10212                                 if (num_of_dest > 1) {
10213                                         dev_flow->dv.actions[sample_act_pos] =
10214                                         dev_flow->dv.dest_array_res->action;
10215                                 } else {
10216                                         dev_flow->dv.actions[sample_act_pos] =
10217                                         dev_flow->dv.sample_res->verbs_action;
10218                                 }
10219                         }
10220                         break;
10221                 default:
10222                         break;
10223                 }
10224                 if (mhdr_res->actions_num &&
10225                     modify_action_position == UINT32_MAX)
10226                         modify_action_position = actions_n++;
10227         }
10228         /*
10229          * For multiple destination (sample action with ratio=1), the encap
10230          * action and port id action will be combined into group action.
10231          * So need remove the original these actions in the flow and only
10232          * use the sample action instead of.
10233          */
10234         if (num_of_dest > 1 && sample_act->dr_port_id_action) {
10235                 int i;
10236                 void *temp_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
10237
10238                 for (i = 0; i < actions_n; i++) {
10239                         if ((sample_act->dr_encap_action &&
10240                                 sample_act->dr_encap_action ==
10241                                 dev_flow->dv.actions[i]) ||
10242                                 (sample_act->dr_port_id_action &&
10243                                 sample_act->dr_port_id_action ==
10244                                 dev_flow->dv.actions[i]))
10245                                 continue;
10246                         temp_actions[tmp_actions_n++] = dev_flow->dv.actions[i];
10247                 }
10248                 memcpy((void *)dev_flow->dv.actions,
10249                                 (void *)temp_actions,
10250                                 tmp_actions_n * sizeof(void *));
10251                 actions_n = tmp_actions_n;
10252         }
10253         dev_flow->dv.actions_n = actions_n;
10254         dev_flow->act_flags = action_flags;
10255         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
10256                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
10257                 int item_type = items->type;
10258
10259                 if (!mlx5_flow_os_item_supported(item_type))
10260                         return rte_flow_error_set(error, ENOTSUP,
10261                                                   RTE_FLOW_ERROR_TYPE_ITEM,
10262                                                   NULL, "item not supported");
10263                 switch (item_type) {
10264                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
10265                         flow_dv_translate_item_port_id
10266                                 (dev, match_mask, match_value, items, attr);
10267                         last_item = MLX5_FLOW_ITEM_PORT_ID;
10268                         break;
10269                 case RTE_FLOW_ITEM_TYPE_ETH:
10270                         flow_dv_translate_item_eth(match_mask, match_value,
10271                                                    items, tunnel,
10272                                                    dev_flow->dv.group);
10273                         matcher.priority = action_flags &
10274                                         MLX5_FLOW_ACTION_DEFAULT_MISS &&
10275                                         !dev_flow->external ?
10276                                         MLX5_PRIORITY_MAP_L3 :
10277                                         MLX5_PRIORITY_MAP_L2;
10278                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
10279                                              MLX5_FLOW_LAYER_OUTER_L2;
10280                         break;
10281                 case RTE_FLOW_ITEM_TYPE_VLAN:
10282                         flow_dv_translate_item_vlan(dev_flow,
10283                                                     match_mask, match_value,
10284                                                     items, tunnel,
10285                                                     dev_flow->dv.group);
10286                         matcher.priority = MLX5_PRIORITY_MAP_L2;
10287                         last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
10288                                               MLX5_FLOW_LAYER_INNER_VLAN) :
10289                                              (MLX5_FLOW_LAYER_OUTER_L2 |
10290                                               MLX5_FLOW_LAYER_OUTER_VLAN);
10291                         break;
10292                 case RTE_FLOW_ITEM_TYPE_IPV4:
10293                         mlx5_flow_tunnel_ip_check(items, next_protocol,
10294                                                   &item_flags, &tunnel);
10295                         flow_dv_translate_item_ipv4(match_mask, match_value,
10296                                                     items, tunnel,
10297                                                     dev_flow->dv.group);
10298                         matcher.priority = MLX5_PRIORITY_MAP_L3;
10299                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
10300                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
10301                         if (items->mask != NULL &&
10302                             ((const struct rte_flow_item_ipv4 *)
10303                              items->mask)->hdr.next_proto_id) {
10304                                 next_protocol =
10305                                         ((const struct rte_flow_item_ipv4 *)
10306                                          (items->spec))->hdr.next_proto_id;
10307                                 next_protocol &=
10308                                         ((const struct rte_flow_item_ipv4 *)
10309                                          (items->mask))->hdr.next_proto_id;
10310                         } else {
10311                                 /* Reset for inner layer. */
10312                                 next_protocol = 0xff;
10313                         }
10314                         break;
10315                 case RTE_FLOW_ITEM_TYPE_IPV6:
10316                         mlx5_flow_tunnel_ip_check(items, next_protocol,
10317                                                   &item_flags, &tunnel);
10318                         flow_dv_translate_item_ipv6(match_mask, match_value,
10319                                                     items, tunnel,
10320                                                     dev_flow->dv.group);
10321                         matcher.priority = MLX5_PRIORITY_MAP_L3;
10322                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
10323                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
10324                         if (items->mask != NULL &&
10325                             ((const struct rte_flow_item_ipv6 *)
10326                              items->mask)->hdr.proto) {
10327                                 next_protocol =
10328                                         ((const struct rte_flow_item_ipv6 *)
10329                                          items->spec)->hdr.proto;
10330                                 next_protocol &=
10331                                         ((const struct rte_flow_item_ipv6 *)
10332                                          items->mask)->hdr.proto;
10333                         } else {
10334                                 /* Reset for inner layer. */
10335                                 next_protocol = 0xff;
10336                         }
10337                         break;
10338                 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
10339                         flow_dv_translate_item_ipv6_frag_ext(match_mask,
10340                                                              match_value,
10341                                                              items, tunnel);
10342                         last_item = tunnel ?
10343                                         MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
10344                                         MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
10345                         if (items->mask != NULL &&
10346                             ((const struct rte_flow_item_ipv6_frag_ext *)
10347                              items->mask)->hdr.next_header) {
10348                                 next_protocol =
10349                                 ((const struct rte_flow_item_ipv6_frag_ext *)
10350                                  items->spec)->hdr.next_header;
10351                                 next_protocol &=
10352                                 ((const struct rte_flow_item_ipv6_frag_ext *)
10353                                  items->mask)->hdr.next_header;
10354                         } else {
10355                                 /* Reset for inner layer. */
10356                                 next_protocol = 0xff;
10357                         }
10358                         break;
10359                 case RTE_FLOW_ITEM_TYPE_TCP:
10360                         flow_dv_translate_item_tcp(match_mask, match_value,
10361                                                    items, tunnel);
10362                         matcher.priority = MLX5_PRIORITY_MAP_L4;
10363                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
10364                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
10365                         break;
10366                 case RTE_FLOW_ITEM_TYPE_UDP:
10367                         flow_dv_translate_item_udp(match_mask, match_value,
10368                                                    items, tunnel);
10369                         matcher.priority = MLX5_PRIORITY_MAP_L4;
10370                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
10371                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
10372                         break;
10373                 case RTE_FLOW_ITEM_TYPE_GRE:
10374                         flow_dv_translate_item_gre(match_mask, match_value,
10375                                                    items, tunnel);
10376                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10377                         last_item = MLX5_FLOW_LAYER_GRE;
10378                         break;
10379                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
10380                         flow_dv_translate_item_gre_key(match_mask,
10381                                                        match_value, items);
10382                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
10383                         break;
10384                 case RTE_FLOW_ITEM_TYPE_NVGRE:
10385                         flow_dv_translate_item_nvgre(match_mask, match_value,
10386                                                      items, tunnel);
10387                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10388                         last_item = MLX5_FLOW_LAYER_GRE;
10389                         break;
10390                 case RTE_FLOW_ITEM_TYPE_VXLAN:
10391                         flow_dv_translate_item_vxlan(match_mask, match_value,
10392                                                      items, tunnel);
10393                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10394                         last_item = MLX5_FLOW_LAYER_VXLAN;
10395                         break;
10396                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
10397                         flow_dv_translate_item_vxlan_gpe(match_mask,
10398                                                          match_value, items,
10399                                                          tunnel);
10400                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10401                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
10402                         break;
10403                 case RTE_FLOW_ITEM_TYPE_GENEVE:
10404                         flow_dv_translate_item_geneve(match_mask, match_value,
10405                                                       items, tunnel);
10406                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10407                         last_item = MLX5_FLOW_LAYER_GENEVE;
10408                         break;
10409                 case RTE_FLOW_ITEM_TYPE_MPLS:
10410                         flow_dv_translate_item_mpls(match_mask, match_value,
10411                                                     items, last_item, tunnel);
10412                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10413                         last_item = MLX5_FLOW_LAYER_MPLS;
10414                         break;
10415                 case RTE_FLOW_ITEM_TYPE_MARK:
10416                         flow_dv_translate_item_mark(dev, match_mask,
10417                                                     match_value, items);
10418                         last_item = MLX5_FLOW_ITEM_MARK;
10419                         break;
10420                 case RTE_FLOW_ITEM_TYPE_META:
10421                         flow_dv_translate_item_meta(dev, match_mask,
10422                                                     match_value, attr, items);
10423                         last_item = MLX5_FLOW_ITEM_METADATA;
10424                         break;
10425                 case RTE_FLOW_ITEM_TYPE_ICMP:
10426                         flow_dv_translate_item_icmp(match_mask, match_value,
10427                                                     items, tunnel);
10428                         last_item = MLX5_FLOW_LAYER_ICMP;
10429                         break;
10430                 case RTE_FLOW_ITEM_TYPE_ICMP6:
10431                         flow_dv_translate_item_icmp6(match_mask, match_value,
10432                                                       items, tunnel);
10433                         last_item = MLX5_FLOW_LAYER_ICMP6;
10434                         break;
10435                 case RTE_FLOW_ITEM_TYPE_TAG:
10436                         flow_dv_translate_item_tag(dev, match_mask,
10437                                                    match_value, items);
10438                         last_item = MLX5_FLOW_ITEM_TAG;
10439                         break;
10440                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
10441                         flow_dv_translate_mlx5_item_tag(dev, match_mask,
10442                                                         match_value, items);
10443                         last_item = MLX5_FLOW_ITEM_TAG;
10444                         break;
10445                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
10446                         flow_dv_translate_item_tx_queue(dev, match_mask,
10447                                                         match_value,
10448                                                         items);
10449                         last_item = MLX5_FLOW_ITEM_TX_QUEUE;
10450                         break;
10451                 case RTE_FLOW_ITEM_TYPE_GTP:
10452                         flow_dv_translate_item_gtp(match_mask, match_value,
10453                                                    items, tunnel);
10454                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10455                         last_item = MLX5_FLOW_LAYER_GTP;
10456                         break;
10457                 case RTE_FLOW_ITEM_TYPE_ECPRI:
10458                         if (!mlx5_flex_parser_ecpri_exist(dev)) {
10459                                 /* Create it only the first time to be used. */
10460                                 ret = mlx5_flex_parser_ecpri_alloc(dev);
10461                                 if (ret)
10462                                         return rte_flow_error_set
10463                                                 (error, -ret,
10464                                                 RTE_FLOW_ERROR_TYPE_ITEM,
10465                                                 NULL,
10466                                                 "cannot create eCPRI parser");
10467                         }
10468                         /* Adjust the length matcher and device flow value. */
10469                         matcher.mask.size = MLX5_ST_SZ_BYTES(fte_match_param);
10470                         dev_flow->dv.value.size =
10471                                         MLX5_ST_SZ_BYTES(fte_match_param);
10472                         flow_dv_translate_item_ecpri(dev, match_mask,
10473                                                      match_value, items);
10474                         /* No other protocol should follow eCPRI layer. */
10475                         last_item = MLX5_FLOW_LAYER_ECPRI;
10476                         break;
10477                 default:
10478                         break;
10479                 }
10480                 item_flags |= last_item;
10481         }
10482         /*
10483          * When E-Switch mode is enabled, we have two cases where we need to
10484          * set the source port manually.
10485          * The first one, is in case of Nic steering rule, and the second is
10486          * E-Switch rule where no port_id item was found. In both cases
10487          * the source port is set according the current port in use.
10488          */
10489         if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
10490             (priv->representor || priv->master)) {
10491                 if (flow_dv_translate_item_port_id(dev, match_mask,
10492                                                    match_value, NULL, attr))
10493                         return -rte_errno;
10494         }
10495 #ifdef RTE_LIBRTE_MLX5_DEBUG
10496         MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
10497                                               dev_flow->dv.value.buf));
10498 #endif
10499         /*
10500          * Layers may be already initialized from prefix flow if this dev_flow
10501          * is the suffix flow.
10502          */
10503         handle->layers |= item_flags;
10504         if (action_flags & MLX5_FLOW_ACTION_RSS)
10505                 flow_dv_hashfields_set(dev_flow, rss_desc);
10506         /* Register matcher. */
10507         matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
10508                                     matcher.mask.size);
10509         matcher.priority = mlx5_flow_adjust_priority(dev, priority,
10510                                                      matcher.priority);
10511         /* reserved field no needs to be set to 0 here. */
10512         tbl_key.domain = attr->transfer;
10513         tbl_key.direction = attr->egress;
10514         tbl_key.table_id = dev_flow->dv.group;
10515         if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow,
10516                                      tunnel, attr->group, error))
10517                 return -rte_errno;
10518         return 0;
10519 }
10520
10521 /**
10522  * Set hash RX queue by hash fields (see enum ibv_rx_hash_fields)
10523  * and tunnel.
10524  *
10525  * @param[in, out] action
10526  *   Shred RSS action holding hash RX queue objects.
10527  * @param[in] hash_fields
10528  *   Defines combination of packet fields to participate in RX hash.
10529  * @param[in] tunnel
10530  *   Tunnel type
10531  * @param[in] hrxq_idx
10532  *   Hash RX queue index to set.
10533  *
10534  * @return
10535  *   0 on success, otherwise negative errno value.
10536  */
10537 static int
10538 __flow_dv_action_rss_hrxq_set(struct mlx5_shared_action_rss *action,
10539                               const uint64_t hash_fields,
10540                               const int tunnel,
10541                               uint32_t hrxq_idx)
10542 {
10543         uint32_t *hrxqs = tunnel ? action->hrxq : action->hrxq_tunnel;
10544
10545         switch (hash_fields & ~IBV_RX_HASH_INNER) {
10546         case MLX5_RSS_HASH_IPV4:
10547                 hrxqs[0] = hrxq_idx;
10548                 return 0;
10549         case MLX5_RSS_HASH_IPV4_TCP:
10550                 hrxqs[1] = hrxq_idx;
10551                 return 0;
10552         case MLX5_RSS_HASH_IPV4_UDP:
10553                 hrxqs[2] = hrxq_idx;
10554                 return 0;
10555         case MLX5_RSS_HASH_IPV6:
10556                 hrxqs[3] = hrxq_idx;
10557                 return 0;
10558         case MLX5_RSS_HASH_IPV6_TCP:
10559                 hrxqs[4] = hrxq_idx;
10560                 return 0;
10561         case MLX5_RSS_HASH_IPV6_UDP:
10562                 hrxqs[5] = hrxq_idx;
10563                 return 0;
10564         case MLX5_RSS_HASH_NONE:
10565                 hrxqs[6] = hrxq_idx;
10566                 return 0;
10567         default:
10568                 return -1;
10569         }
10570 }
10571
10572 /**
10573  * Look up for hash RX queue by hash fields (see enum ibv_rx_hash_fields)
10574  * and tunnel.
10575  *
10576  * @param[in] dev
10577  *   Pointer to the Ethernet device structure.
10578  * @param[in] idx
10579  *   Shared RSS action ID holding hash RX queue objects.
10580  * @param[in] hash_fields
10581  *   Defines combination of packet fields to participate in RX hash.
10582  * @param[in] tunnel
10583  *   Tunnel type
10584  *
10585  * @return
10586  *   Valid hash RX queue index, otherwise 0.
10587  */
10588 static uint32_t
10589 __flow_dv_action_rss_hrxq_lookup(struct rte_eth_dev *dev, uint32_t idx,
10590                                  const uint64_t hash_fields,
10591                                  const int tunnel)
10592 {
10593         struct mlx5_priv *priv = dev->data->dev_private;
10594         struct mlx5_shared_action_rss *shared_rss =
10595             mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
10596         const uint32_t *hrxqs = tunnel ? shared_rss->hrxq :
10597                                                         shared_rss->hrxq_tunnel;
10598
10599         switch (hash_fields & ~IBV_RX_HASH_INNER) {
10600         case MLX5_RSS_HASH_IPV4:
10601                 return hrxqs[0];
10602         case MLX5_RSS_HASH_IPV4_TCP:
10603                 return hrxqs[1];
10604         case MLX5_RSS_HASH_IPV4_UDP:
10605                 return hrxqs[2];
10606         case MLX5_RSS_HASH_IPV6:
10607                 return hrxqs[3];
10608         case MLX5_RSS_HASH_IPV6_TCP:
10609                 return hrxqs[4];
10610         case MLX5_RSS_HASH_IPV6_UDP:
10611                 return hrxqs[5];
10612         case MLX5_RSS_HASH_NONE:
10613                 return hrxqs[6];
10614         default:
10615                 return 0;
10616         }
10617 }
10618
10619 /**
10620  * Retrieves hash RX queue suitable for the *flow*.
10621  * If shared action configured for *flow* suitable hash RX queue will be
10622  * retrieved from attached shared action.
10623  *
10624  * @param[in] dev
10625  *   Pointer to the Ethernet device structure.
10626  * @param[in] dev_flow
10627  *   Pointer to the sub flow.
10628  * @param[in] rss_desc
10629  *   Pointer to the RSS descriptor.
10630  * @param[out] hrxq
10631  *   Pointer to retrieved hash RX queue object.
10632  *
10633  * @return
10634  *   Valid hash RX queue index, otherwise 0 and rte_errno is set.
10635  */
10636 static uint32_t
10637 __flow_dv_rss_get_hrxq(struct rte_eth_dev *dev, struct mlx5_flow *dev_flow,
10638                        struct mlx5_flow_rss_desc *rss_desc,
10639                        struct mlx5_hrxq **hrxq)
10640 {
10641         struct mlx5_priv *priv = dev->data->dev_private;
10642         uint32_t hrxq_idx;
10643
10644         if (rss_desc->shared_rss) {
10645                 hrxq_idx = __flow_dv_action_rss_hrxq_lookup
10646                                 (dev, rss_desc->shared_rss,
10647                                  dev_flow->hash_fields,
10648                                  !!(dev_flow->handle->layers &
10649                                     MLX5_FLOW_LAYER_TUNNEL));
10650                 if (hrxq_idx)
10651                         *hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
10652                                                hrxq_idx);
10653         } else {
10654                 *hrxq = flow_dv_hrxq_prepare(dev, dev_flow, rss_desc,
10655                                              &hrxq_idx);
10656         }
10657         return hrxq_idx;
10658 }
10659
10660 /**
10661  * Apply the flow to the NIC, lock free,
10662  * (mutex should be acquired by caller).
10663  *
10664  * @param[in] dev
10665  *   Pointer to the Ethernet device structure.
10666  * @param[in, out] flow
10667  *   Pointer to flow structure.
10668  * @param[out] error
10669  *   Pointer to error structure.
10670  *
10671  * @return
10672  *   0 on success, a negative errno value otherwise and rte_errno is set.
10673  */
10674 static int
10675 flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
10676               struct rte_flow_error *error)
10677 {
10678         struct mlx5_flow_dv_workspace *dv;
10679         struct mlx5_flow_handle *dh;
10680         struct mlx5_flow_handle_dv *dv_h;
10681         struct mlx5_flow *dev_flow;
10682         struct mlx5_priv *priv = dev->data->dev_private;
10683         uint32_t handle_idx;
10684         int n;
10685         int err;
10686         int idx;
10687         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
10688         struct mlx5_flow_rss_desc *rss_desc = &wks->rss_desc;
10689
10690         MLX5_ASSERT(wks);
10691         if (rss_desc->shared_rss) {
10692                 dh = wks->flows[wks->flow_idx - 1].handle;
10693                 MLX5_ASSERT(dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS);
10694                 dh->rix_srss = rss_desc->shared_rss;
10695         }
10696         for (idx = wks->flow_idx - 1; idx >= 0; idx--) {
10697                 dev_flow = &wks->flows[idx];
10698                 dv = &dev_flow->dv;
10699                 dh = dev_flow->handle;
10700                 dv_h = &dh->dvh;
10701                 n = dv->actions_n;
10702                 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
10703                         if (dv->transfer) {
10704                                 dv->actions[n++] = priv->sh->esw_drop_action;
10705                         } else {
10706                                 MLX5_ASSERT(priv->drop_queue.hrxq);
10707                                 dv->actions[n++] =
10708                                                 priv->drop_queue.hrxq->action;
10709                         }
10710                 } else if ((dh->fate_action == MLX5_FLOW_FATE_QUEUE &&
10711                            !dv_h->rix_sample && !dv_h->rix_dest_array) ||
10712                             (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS)) {
10713                         struct mlx5_hrxq *hrxq = NULL;
10714                         uint32_t hrxq_idx = __flow_dv_rss_get_hrxq
10715                                         (dev, dev_flow, rss_desc, &hrxq);
10716                         if (!hrxq) {
10717                                 rte_flow_error_set
10718                                         (error, rte_errno,
10719                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10720                                          "cannot get hash queue");
10721                                 goto error;
10722                         }
10723                         if (dh->fate_action == MLX5_FLOW_FATE_QUEUE)
10724                                 dh->rix_hrxq = hrxq_idx;
10725                         dv->actions[n++] = hrxq->action;
10726                 } else if (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS) {
10727                         if (!priv->sh->default_miss_action) {
10728                                 rte_flow_error_set
10729                                         (error, rte_errno,
10730                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10731                                          "default miss action not be created.");
10732                                 goto error;
10733                         }
10734                         dv->actions[n++] = priv->sh->default_miss_action;
10735                 }
10736                 err = mlx5_flow_os_create_flow(dv_h->matcher->matcher_object,
10737                                                (void *)&dv->value, n,
10738                                                dv->actions, &dh->drv_flow);
10739                 if (err) {
10740                         rte_flow_error_set(error, errno,
10741                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10742                                            NULL,
10743                                            "hardware refuses to create flow");
10744                         goto error;
10745                 }
10746                 if (priv->vmwa_context &&
10747                     dh->vf_vlan.tag && !dh->vf_vlan.created) {
10748                         /*
10749                          * The rule contains the VLAN pattern.
10750                          * For VF we are going to create VLAN
10751                          * interface to make hypervisor set correct
10752                          * e-Switch vport context.
10753                          */
10754                         mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
10755                 }
10756         }
10757         return 0;
10758 error:
10759         err = rte_errno; /* Save rte_errno before cleanup. */
10760         SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles,
10761                        handle_idx, dh, next) {
10762                 /* hrxq is union, don't clear it if the flag is not set. */
10763                 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE && dh->rix_hrxq) {
10764                         mlx5_hrxq_release(dev, dh->rix_hrxq);
10765                         dh->rix_hrxq = 0;
10766                 }
10767                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
10768                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
10769         }
10770         if (rss_desc->shared_rss)
10771                 wks->flows[wks->flow_idx - 1].handle->rix_srss = 0;
10772         rte_errno = err; /* Restore rte_errno. */
10773         return -rte_errno;
10774 }
10775
10776 void
10777 flow_dv_matcher_remove_cb(struct mlx5_cache_list *list __rte_unused,
10778                           struct mlx5_cache_entry *entry)
10779 {
10780         struct mlx5_flow_dv_matcher *cache = container_of(entry, typeof(*cache),
10781                                                           entry);
10782
10783         claim_zero(mlx5_flow_os_destroy_flow_matcher(cache->matcher_object));
10784         mlx5_free(cache);
10785 }
10786
10787 /**
10788  * Release the flow matcher.
10789  *
10790  * @param dev
10791  *   Pointer to Ethernet device.
10792  * @param handle
10793  *   Pointer to mlx5_flow_handle.
10794  *
10795  * @return
10796  *   1 while a reference on it exists, 0 when freed.
10797  */
10798 static int
10799 flow_dv_matcher_release(struct rte_eth_dev *dev,
10800                         struct mlx5_flow_handle *handle)
10801 {
10802         struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
10803         struct mlx5_flow_tbl_data_entry *tbl = container_of(matcher->tbl,
10804                                                             typeof(*tbl), tbl);
10805         int ret;
10806
10807         MLX5_ASSERT(matcher->matcher_object);
10808         ret = mlx5_cache_unregister(&tbl->matchers, &matcher->entry);
10809         flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl->tbl);
10810         return ret;
10811 }
10812
10813 /**
10814  * Release encap_decap resource.
10815  *
10816  * @param list
10817  *   Pointer to the hash list.
10818  * @param entry
10819  *   Pointer to exist resource entry object.
10820  */
10821 void
10822 flow_dv_encap_decap_remove_cb(struct mlx5_hlist *list,
10823                               struct mlx5_hlist_entry *entry)
10824 {
10825         struct mlx5_dev_ctx_shared *sh = list->ctx;
10826         struct mlx5_flow_dv_encap_decap_resource *res =
10827                 container_of(entry, typeof(*res), entry);
10828
10829         claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
10830         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], res->idx);
10831 }
10832
10833 /**
10834  * Release an encap/decap resource.
10835  *
10836  * @param dev
10837  *   Pointer to Ethernet device.
10838  * @param encap_decap_idx
10839  *   Index of encap decap resource.
10840  *
10841  * @return
10842  *   1 while a reference on it exists, 0 when freed.
10843  */
10844 static int
10845 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
10846                                      uint32_t encap_decap_idx)
10847 {
10848         struct mlx5_priv *priv = dev->data->dev_private;
10849         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
10850
10851         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
10852                                         encap_decap_idx);
10853         if (!cache_resource)
10854                 return 0;
10855         MLX5_ASSERT(cache_resource->action);
10856         return mlx5_hlist_unregister(priv->sh->encaps_decaps,
10857                                      &cache_resource->entry);
10858 }
10859
10860 /**
10861  * Release an jump to table action resource.
10862  *
10863  * @param dev
10864  *   Pointer to Ethernet device.
10865  * @param handle
10866  *   Pointer to mlx5_flow_handle.
10867  *
10868  * @return
10869  *   1 while a reference on it exists, 0 when freed.
10870  */
10871 static int
10872 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
10873                                   struct mlx5_flow_handle *handle)
10874 {
10875         struct mlx5_priv *priv = dev->data->dev_private;
10876         struct mlx5_flow_tbl_data_entry *tbl_data;
10877
10878         tbl_data = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_JUMP],
10879                              handle->rix_jump);
10880         if (!tbl_data)
10881                 return 0;
10882         return flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl_data->tbl);
10883 }
10884
10885 void
10886 flow_dv_modify_remove_cb(struct mlx5_hlist *list __rte_unused,
10887                          struct mlx5_hlist_entry *entry)
10888 {
10889         struct mlx5_flow_dv_modify_hdr_resource *res =
10890                 container_of(entry, typeof(*res), entry);
10891
10892         claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
10893         mlx5_free(entry);
10894 }
10895
10896 /**
10897  * Release a modify-header resource.
10898  *
10899  * @param dev
10900  *   Pointer to Ethernet device.
10901  * @param handle
10902  *   Pointer to mlx5_flow_handle.
10903  *
10904  * @return
10905  *   1 while a reference on it exists, 0 when freed.
10906  */
10907 static int
10908 flow_dv_modify_hdr_resource_release(struct rte_eth_dev *dev,
10909                                     struct mlx5_flow_handle *handle)
10910 {
10911         struct mlx5_priv *priv = dev->data->dev_private;
10912         struct mlx5_flow_dv_modify_hdr_resource *entry = handle->dvh.modify_hdr;
10913
10914         MLX5_ASSERT(entry->action);
10915         return mlx5_hlist_unregister(priv->sh->modify_cmds, &entry->entry);
10916 }
10917
10918 void
10919 flow_dv_port_id_remove_cb(struct mlx5_cache_list *list,
10920                           struct mlx5_cache_entry *entry)
10921 {
10922         struct mlx5_dev_ctx_shared *sh = list->ctx;
10923         struct mlx5_flow_dv_port_id_action_resource *cache =
10924                         container_of(entry, typeof(*cache), entry);
10925
10926         claim_zero(mlx5_flow_os_destroy_flow_action(cache->action));
10927         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], cache->idx);
10928 }
10929
10930 /**
10931  * Release port ID action resource.
10932  *
10933  * @param dev
10934  *   Pointer to Ethernet device.
10935  * @param handle
10936  *   Pointer to mlx5_flow_handle.
10937  *
10938  * @return
10939  *   1 while a reference on it exists, 0 when freed.
10940  */
10941 static int
10942 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
10943                                         uint32_t port_id)
10944 {
10945         struct mlx5_priv *priv = dev->data->dev_private;
10946         struct mlx5_flow_dv_port_id_action_resource *cache;
10947
10948         cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID], port_id);
10949         if (!cache)
10950                 return 0;
10951         MLX5_ASSERT(cache->action);
10952         return mlx5_cache_unregister(&priv->sh->port_id_action_list,
10953                                      &cache->entry);
10954 }
10955
10956 /**
10957  * Release shared RSS action resource.
10958  *
10959  * @param dev
10960  *   Pointer to Ethernet device.
10961  * @param srss
10962  *   Shared RSS action index.
10963  */
10964 static void
10965 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss)
10966 {
10967         struct mlx5_priv *priv = dev->data->dev_private;
10968         struct mlx5_shared_action_rss *shared_rss;
10969
10970         shared_rss = mlx5_ipool_get
10971                         (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], srss);
10972         __atomic_sub_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
10973 }
10974
10975 void
10976 flow_dv_push_vlan_remove_cb(struct mlx5_cache_list *list,
10977                             struct mlx5_cache_entry *entry)
10978 {
10979         struct mlx5_dev_ctx_shared *sh = list->ctx;
10980         struct mlx5_flow_dv_push_vlan_action_resource *cache =
10981                         container_of(entry, typeof(*cache), entry);
10982
10983         claim_zero(mlx5_flow_os_destroy_flow_action(cache->action));
10984         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], cache->idx);
10985 }
10986
10987 /**
10988  * Release push vlan action resource.
10989  *
10990  * @param dev
10991  *   Pointer to Ethernet device.
10992  * @param handle
10993  *   Pointer to mlx5_flow_handle.
10994  *
10995  * @return
10996  *   1 while a reference on it exists, 0 when freed.
10997  */
10998 static int
10999 flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,
11000                                           struct mlx5_flow_handle *handle)
11001 {
11002         struct mlx5_priv *priv = dev->data->dev_private;
11003         struct mlx5_flow_dv_push_vlan_action_resource *cache;
11004         uint32_t idx = handle->dvh.rix_push_vlan;
11005
11006         cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
11007         if (!cache)
11008                 return 0;
11009         MLX5_ASSERT(cache->action);
11010         return mlx5_cache_unregister(&priv->sh->push_vlan_action_list,
11011                                      &cache->entry);
11012 }
11013
11014 /**
11015  * Release the fate resource.
11016  *
11017  * @param dev
11018  *   Pointer to Ethernet device.
11019  * @param handle
11020  *   Pointer to mlx5_flow_handle.
11021  */
11022 static void
11023 flow_dv_fate_resource_release(struct rte_eth_dev *dev,
11024                                struct mlx5_flow_handle *handle)
11025 {
11026         if (!handle->rix_fate)
11027                 return;
11028         switch (handle->fate_action) {
11029         case MLX5_FLOW_FATE_QUEUE:
11030                 mlx5_hrxq_release(dev, handle->rix_hrxq);
11031                 break;
11032         case MLX5_FLOW_FATE_JUMP:
11033                 flow_dv_jump_tbl_resource_release(dev, handle);
11034                 break;
11035         case MLX5_FLOW_FATE_PORT_ID:
11036                 flow_dv_port_id_action_resource_release(dev,
11037                                 handle->rix_port_id_action);
11038                 break;
11039         case MLX5_FLOW_FATE_SHARED_RSS:
11040                 flow_dv_shared_rss_action_release(dev, handle->rix_srss);
11041                 break;
11042         default:
11043                 DRV_LOG(DEBUG, "Incorrect fate action:%d", handle->fate_action);
11044                 break;
11045         }
11046         handle->rix_fate = 0;
11047 }
11048
11049 void
11050 flow_dv_sample_remove_cb(struct mlx5_cache_list *list __rte_unused,
11051                          struct mlx5_cache_entry *entry)
11052 {
11053         struct mlx5_flow_dv_sample_resource *cache_resource =
11054                         container_of(entry, typeof(*cache_resource), entry);
11055         struct rte_eth_dev *dev = cache_resource->dev;
11056         struct mlx5_priv *priv = dev->data->dev_private;
11057
11058         if (cache_resource->verbs_action)
11059                 claim_zero(mlx5_glue->destroy_flow_action
11060                                 (cache_resource->verbs_action));
11061         if (cache_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB) {
11062                 if (cache_resource->default_miss)
11063                         claim_zero(mlx5_glue->destroy_flow_action
11064                           (cache_resource->default_miss));
11065         }
11066         if (cache_resource->normal_path_tbl)
11067                 flow_dv_tbl_resource_release(MLX5_SH(dev),
11068                         cache_resource->normal_path_tbl);
11069         flow_dv_sample_sub_actions_release(dev,
11070                                 &cache_resource->sample_idx);
11071         mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
11072                         cache_resource->idx);
11073         DRV_LOG(DEBUG, "sample resource %p: removed",
11074                 (void *)cache_resource);
11075 }
11076
11077 /**
11078  * Release an sample resource.
11079  *
11080  * @param dev
11081  *   Pointer to Ethernet device.
11082  * @param handle
11083  *   Pointer to mlx5_flow_handle.
11084  *
11085  * @return
11086  *   1 while a reference on it exists, 0 when freed.
11087  */
11088 static int
11089 flow_dv_sample_resource_release(struct rte_eth_dev *dev,
11090                                      struct mlx5_flow_handle *handle)
11091 {
11092         struct mlx5_priv *priv = dev->data->dev_private;
11093         struct mlx5_flow_dv_sample_resource *cache_resource;
11094
11095         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
11096                          handle->dvh.rix_sample);
11097         if (!cache_resource)
11098                 return 0;
11099         MLX5_ASSERT(cache_resource->verbs_action);
11100         return mlx5_cache_unregister(&priv->sh->sample_action_list,
11101                                      &cache_resource->entry);
11102 }
11103
11104 void
11105 flow_dv_dest_array_remove_cb(struct mlx5_cache_list *list __rte_unused,
11106                              struct mlx5_cache_entry *entry)
11107 {
11108         struct mlx5_flow_dv_dest_array_resource *cache_resource =
11109                         container_of(entry, typeof(*cache_resource), entry);
11110         struct rte_eth_dev *dev = cache_resource->dev;
11111         struct mlx5_priv *priv = dev->data->dev_private;
11112         uint32_t i = 0;
11113
11114         MLX5_ASSERT(cache_resource->action);
11115         if (cache_resource->action)
11116                 claim_zero(mlx5_glue->destroy_flow_action
11117                                         (cache_resource->action));
11118         for (; i < cache_resource->num_of_dest; i++)
11119                 flow_dv_sample_sub_actions_release(dev,
11120                                 &cache_resource->sample_idx[i]);
11121         mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
11122                         cache_resource->idx);
11123         DRV_LOG(DEBUG, "destination array resource %p: removed",
11124                 (void *)cache_resource);
11125 }
11126
11127 /**
11128  * Release an destination array resource.
11129  *
11130  * @param dev
11131  *   Pointer to Ethernet device.
11132  * @param handle
11133  *   Pointer to mlx5_flow_handle.
11134  *
11135  * @return
11136  *   1 while a reference on it exists, 0 when freed.
11137  */
11138 static int
11139 flow_dv_dest_array_resource_release(struct rte_eth_dev *dev,
11140                                     struct mlx5_flow_handle *handle)
11141 {
11142         struct mlx5_priv *priv = dev->data->dev_private;
11143         struct mlx5_flow_dv_dest_array_resource *cache;
11144
11145         cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
11146                                handle->dvh.rix_dest_array);
11147         if (!cache)
11148                 return 0;
11149         MLX5_ASSERT(cache->action);
11150         return mlx5_cache_unregister(&priv->sh->dest_array_list,
11151                                      &cache->entry);
11152 }
11153
11154 /**
11155  * Remove the flow from the NIC but keeps it in memory.
11156  * Lock free, (mutex should be acquired by caller).
11157  *
11158  * @param[in] dev
11159  *   Pointer to Ethernet device.
11160  * @param[in, out] flow
11161  *   Pointer to flow structure.
11162  */
11163 static void
11164 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
11165 {
11166         struct mlx5_flow_handle *dh;
11167         uint32_t handle_idx;
11168         struct mlx5_priv *priv = dev->data->dev_private;
11169
11170         if (!flow)
11171                 return;
11172         handle_idx = flow->dev_handles;
11173         while (handle_idx) {
11174                 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
11175                                     handle_idx);
11176                 if (!dh)
11177                         return;
11178                 if (dh->drv_flow) {
11179                         claim_zero(mlx5_flow_os_destroy_flow(dh->drv_flow));
11180                         dh->drv_flow = NULL;
11181                 }
11182                 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE)
11183                         flow_dv_fate_resource_release(dev, dh);
11184                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
11185                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
11186                 handle_idx = dh->next.next;
11187         }
11188 }
11189
11190 /**
11191  * Remove the flow from the NIC and the memory.
11192  * Lock free, (mutex should be acquired by caller).
11193  *
11194  * @param[in] dev
11195  *   Pointer to the Ethernet device structure.
11196  * @param[in, out] flow
11197  *   Pointer to flow structure.
11198  */
11199 static void
11200 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
11201 {
11202         struct mlx5_flow_handle *dev_handle;
11203         struct mlx5_priv *priv = dev->data->dev_private;
11204
11205         if (!flow)
11206                 return;
11207         flow_dv_remove(dev, flow);
11208         if (flow->counter) {
11209                 flow_dv_counter_free(dev, flow->counter);
11210                 flow->counter = 0;
11211         }
11212         if (flow->meter) {
11213                 struct mlx5_flow_meter *fm;
11214
11215                 fm = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MTR],
11216                                     flow->meter);
11217                 if (fm)
11218                         mlx5_flow_meter_detach(fm);
11219                 flow->meter = 0;
11220         }
11221         if (flow->age)
11222                 flow_dv_aso_age_release(dev, flow->age);
11223         while (flow->dev_handles) {
11224                 uint32_t tmp_idx = flow->dev_handles;
11225
11226                 dev_handle = mlx5_ipool_get(priv->sh->ipool
11227                                             [MLX5_IPOOL_MLX5_FLOW], tmp_idx);
11228                 if (!dev_handle)
11229                         return;
11230                 flow->dev_handles = dev_handle->next.next;
11231                 if (dev_handle->dvh.matcher)
11232                         flow_dv_matcher_release(dev, dev_handle);
11233                 if (dev_handle->dvh.rix_sample)
11234                         flow_dv_sample_resource_release(dev, dev_handle);
11235                 if (dev_handle->dvh.rix_dest_array)
11236                         flow_dv_dest_array_resource_release(dev, dev_handle);
11237                 if (dev_handle->dvh.rix_encap_decap)
11238                         flow_dv_encap_decap_resource_release(dev,
11239                                 dev_handle->dvh.rix_encap_decap);
11240                 if (dev_handle->dvh.modify_hdr)
11241                         flow_dv_modify_hdr_resource_release(dev, dev_handle);
11242                 if (dev_handle->dvh.rix_push_vlan)
11243                         flow_dv_push_vlan_action_resource_release(dev,
11244                                                                   dev_handle);
11245                 if (dev_handle->dvh.rix_tag)
11246                         flow_dv_tag_release(dev,
11247                                             dev_handle->dvh.rix_tag);
11248                 flow_dv_fate_resource_release(dev, dev_handle);
11249                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
11250                            tmp_idx);
11251         }
11252 }
11253
11254 /**
11255  * Release array of hash RX queue objects.
11256  * Helper function.
11257  *
11258  * @param[in] dev
11259  *   Pointer to the Ethernet device structure.
11260  * @param[in, out] hrxqs
11261  *   Array of hash RX queue objects.
11262  *
11263  * @return
11264  *   Total number of references to hash RX queue objects in *hrxqs* array
11265  *   after this operation.
11266  */
11267 static int
11268 __flow_dv_hrxqs_release(struct rte_eth_dev *dev,
11269                         uint32_t (*hrxqs)[MLX5_RSS_HASH_FIELDS_LEN])
11270 {
11271         size_t i;
11272         int remaining = 0;
11273
11274         for (i = 0; i < RTE_DIM(*hrxqs); i++) {
11275                 int ret = mlx5_hrxq_release(dev, (*hrxqs)[i]);
11276
11277                 if (!ret)
11278                         (*hrxqs)[i] = 0;
11279                 remaining += ret;
11280         }
11281         return remaining;
11282 }
11283
11284 /**
11285  * Release all hash RX queue objects representing shared RSS action.
11286  *
11287  * @param[in] dev
11288  *   Pointer to the Ethernet device structure.
11289  * @param[in, out] action
11290  *   Shared RSS action to remove hash RX queue objects from.
11291  *
11292  * @return
11293  *   Total number of references to hash RX queue objects stored in *action*
11294  *   after this operation.
11295  *   Expected to be 0 if no external references held.
11296  */
11297 static int
11298 __flow_dv_action_rss_hrxqs_release(struct rte_eth_dev *dev,
11299                                  struct mlx5_shared_action_rss *action)
11300 {
11301         return __flow_dv_hrxqs_release(dev, &action->hrxq) +
11302                 __flow_dv_hrxqs_release(dev, &action->hrxq_tunnel);
11303 }
11304
11305 /**
11306  * Setup shared RSS action.
11307  * Prepare set of hash RX queue objects sufficient to handle all valid
11308  * hash_fields combinations (see enum ibv_rx_hash_fields).
11309  *
11310  * @param[in] dev
11311  *   Pointer to the Ethernet device structure.
11312  * @param[in] action_idx
11313  *   Shared RSS action ipool index.
11314  * @param[in, out] action
11315  *   Partially initialized shared RSS action.
11316  * @param[out] error
11317  *   Perform verbose error reporting if not NULL. Initialized in case of
11318  *   error only.
11319  *
11320  * @return
11321  *   0 on success, otherwise negative errno value.
11322  */
11323 static int
11324 __flow_dv_action_rss_setup(struct rte_eth_dev *dev,
11325                         uint32_t action_idx,
11326                         struct mlx5_shared_action_rss *action,
11327                         struct rte_flow_error *error)
11328 {
11329         struct mlx5_flow_rss_desc rss_desc = { 0 };
11330         size_t i;
11331         int err;
11332
11333         memcpy(rss_desc.key, action->origin.key, MLX5_RSS_HASH_KEY_LEN);
11334         rss_desc.key_len = MLX5_RSS_HASH_KEY_LEN;
11335         rss_desc.const_q = action->origin.queue;
11336         rss_desc.queue_num = action->origin.queue_num;
11337         /* Set non-zero value to indicate a shared RSS. */
11338         rss_desc.shared_rss = action_idx;
11339         for (i = 0; i < MLX5_RSS_HASH_FIELDS_LEN; i++) {
11340                 uint32_t hrxq_idx;
11341                 uint64_t hash_fields = mlx5_rss_hash_fields[i];
11342                 int tunnel;
11343
11344                 for (tunnel = 0; tunnel < 2; tunnel++) {
11345                         rss_desc.tunnel = tunnel;
11346                         rss_desc.hash_fields = hash_fields;
11347                         hrxq_idx = mlx5_hrxq_get(dev, &rss_desc);
11348                         if (!hrxq_idx) {
11349                                 rte_flow_error_set
11350                                         (error, rte_errno,
11351                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11352                                          "cannot get hash queue");
11353                                 goto error_hrxq_new;
11354                         }
11355                         err = __flow_dv_action_rss_hrxq_set
11356                                 (action, hash_fields, tunnel, hrxq_idx);
11357                         MLX5_ASSERT(!err);
11358                 }
11359         }
11360         return 0;
11361 error_hrxq_new:
11362         err = rte_errno;
11363         __flow_dv_action_rss_hrxqs_release(dev, action);
11364         rte_errno = err;
11365         return -rte_errno;
11366 }
11367
11368 /**
11369  * Create shared RSS action.
11370  *
11371  * @param[in] dev
11372  *   Pointer to the Ethernet device structure.
11373  * @param[in] conf
11374  *   Shared action configuration.
11375  * @param[in] rss
11376  *   RSS action specification used to create shared action.
11377  * @param[out] error
11378  *   Perform verbose error reporting if not NULL. Initialized in case of
11379  *   error only.
11380  *
11381  * @return
11382  *   A valid shared action ID in case of success, 0 otherwise and
11383  *   rte_errno is set.
11384  */
11385 static uint32_t
11386 __flow_dv_action_rss_create(struct rte_eth_dev *dev,
11387                             const struct rte_flow_shared_action_conf *conf,
11388                             const struct rte_flow_action_rss *rss,
11389                             struct rte_flow_error *error)
11390 {
11391         struct mlx5_priv *priv = dev->data->dev_private;
11392         struct mlx5_shared_action_rss *shared_action = NULL;
11393         void *queue = NULL;
11394         struct rte_flow_action_rss *origin;
11395         const uint8_t *rss_key;
11396         uint32_t queue_size = rss->queue_num * sizeof(uint16_t);
11397         uint32_t idx;
11398
11399         RTE_SET_USED(conf);
11400         queue = mlx5_malloc(0, RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
11401                             0, SOCKET_ID_ANY);
11402         shared_action = mlx5_ipool_zmalloc
11403                          (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], &idx);
11404         if (!shared_action || !queue) {
11405                 rte_flow_error_set(error, ENOMEM,
11406                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11407                                    "cannot allocate resource memory");
11408                 goto error_rss_init;
11409         }
11410         if (idx > (1u << MLX5_SHARED_ACTION_TYPE_OFFSET)) {
11411                 rte_flow_error_set(error, E2BIG,
11412                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11413                                    "rss action number out of range");
11414                 goto error_rss_init;
11415         }
11416         shared_action->queue = queue;
11417         origin = &shared_action->origin;
11418         origin->func = rss->func;
11419         origin->level = rss->level;
11420         /* RSS type 0 indicates default RSS type (ETH_RSS_IP). */
11421         origin->types = !rss->types ? ETH_RSS_IP : rss->types;
11422         /* NULL RSS key indicates default RSS key. */
11423         rss_key = !rss->key ? rss_hash_default_key : rss->key;
11424         memcpy(shared_action->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
11425         origin->key = &shared_action->key[0];
11426         origin->key_len = MLX5_RSS_HASH_KEY_LEN;
11427         memcpy(shared_action->queue, rss->queue, queue_size);
11428         origin->queue = shared_action->queue;
11429         origin->queue_num = rss->queue_num;
11430         if (__flow_dv_action_rss_setup(dev, idx, shared_action, error))
11431                 goto error_rss_init;
11432         __atomic_add_fetch(&shared_action->refcnt, 1, __ATOMIC_RELAXED);
11433         rte_spinlock_lock(&priv->shared_act_sl);
11434         ILIST_INSERT(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
11435                      &priv->rss_shared_actions, idx, shared_action, next);
11436         rte_spinlock_unlock(&priv->shared_act_sl);
11437         return idx;
11438 error_rss_init:
11439         if (shared_action)
11440                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
11441                                 idx);
11442         if (queue)
11443                 mlx5_free(queue);
11444         return 0;
11445 }
11446
11447 /**
11448  * Destroy the shared RSS action.
11449  * Release related hash RX queue objects.
11450  *
11451  * @param[in] dev
11452  *   Pointer to the Ethernet device structure.
11453  * @param[in] idx
11454  *   The shared RSS action object ID to be removed.
11455  * @param[out] error
11456  *   Perform verbose error reporting if not NULL. Initialized in case of
11457  *   error only.
11458  *
11459  * @return
11460  *   0 on success, otherwise negative errno value.
11461  */
11462 static int
11463 __flow_dv_action_rss_release(struct rte_eth_dev *dev, uint32_t idx,
11464                              struct rte_flow_error *error)
11465 {
11466         struct mlx5_priv *priv = dev->data->dev_private;
11467         struct mlx5_shared_action_rss *shared_rss =
11468             mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
11469         uint32_t old_refcnt = 1;
11470         int remaining;
11471
11472         if (!shared_rss)
11473                 return rte_flow_error_set(error, EINVAL,
11474                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
11475                                           "invalid shared action");
11476         remaining = __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
11477         if (remaining)
11478                 return rte_flow_error_set(error, ETOOMANYREFS,
11479                                           RTE_FLOW_ERROR_TYPE_ACTION,
11480                                           NULL,
11481                                           "shared rss hrxq has references");
11482         if (!__atomic_compare_exchange_n(&shared_rss->refcnt, &old_refcnt,
11483                                          0, 0, __ATOMIC_ACQUIRE,
11484                                          __ATOMIC_RELAXED))
11485                 return rte_flow_error_set(error, ETOOMANYREFS,
11486                                           RTE_FLOW_ERROR_TYPE_ACTION,
11487                                           NULL,
11488                                           "shared rss has references");
11489         rte_free(shared_rss->queue);
11490         rte_spinlock_lock(&priv->shared_act_sl);
11491         ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
11492                      &priv->rss_shared_actions, idx, shared_rss, next);
11493         rte_spinlock_unlock(&priv->shared_act_sl);
11494         mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
11495                         idx);
11496         return 0;
11497 }
11498
11499 /**
11500  * Create shared action, lock free,
11501  * (mutex should be acquired by caller).
11502  * Dispatcher for action type specific call.
11503  *
11504  * @param[in] dev
11505  *   Pointer to the Ethernet device structure.
11506  * @param[in] conf
11507  *   Shared action configuration.
11508  * @param[in] action
11509  *   Action specification used to create shared action.
11510  * @param[out] error
11511  *   Perform verbose error reporting if not NULL. Initialized in case of
11512  *   error only.
11513  *
11514  * @return
11515  *   A valid shared action handle in case of success, NULL otherwise and
11516  *   rte_errno is set.
11517  */
11518 static struct rte_flow_shared_action *
11519 flow_dv_action_create(struct rte_eth_dev *dev,
11520                       const struct rte_flow_shared_action_conf *conf,
11521                       const struct rte_flow_action *action,
11522                       struct rte_flow_error *err)
11523 {
11524         uint32_t idx = 0;
11525         uint32_t ret = 0;
11526
11527         switch (action->type) {
11528         case RTE_FLOW_ACTION_TYPE_RSS:
11529                 ret = __flow_dv_action_rss_create(dev, conf, action->conf, err);
11530                 idx = (MLX5_SHARED_ACTION_TYPE_RSS <<
11531                        MLX5_SHARED_ACTION_TYPE_OFFSET) | ret;
11532                 break;
11533         case RTE_FLOW_ACTION_TYPE_AGE:
11534                 ret = flow_dv_translate_create_aso_age(dev, action->conf);
11535                 idx = (MLX5_SHARED_ACTION_TYPE_AGE <<
11536                        MLX5_SHARED_ACTION_TYPE_OFFSET) | ret;
11537                 if (ret) {
11538                         struct mlx5_aso_age_action *aso_age =
11539                                               flow_aso_age_get_by_idx(dev, ret);
11540
11541                         if (!aso_age->age_params.context)
11542                                 aso_age->age_params.context =
11543                                                          (void *)(uintptr_t)idx;
11544                 }
11545                 break;
11546         default:
11547                 rte_flow_error_set(err, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION,
11548                                    NULL, "action type not supported");
11549                 break;
11550         }
11551         return ret ? (struct rte_flow_shared_action *)(uintptr_t)idx : NULL;
11552 }
11553
11554 /**
11555  * Destroy the shared action.
11556  * Release action related resources on the NIC and the memory.
11557  * Lock free, (mutex should be acquired by caller).
11558  * Dispatcher for action type specific call.
11559  *
11560  * @param[in] dev
11561  *   Pointer to the Ethernet device structure.
11562  * @param[in] action
11563  *   The shared action object to be removed.
11564  * @param[out] error
11565  *   Perform verbose error reporting if not NULL. Initialized in case of
11566  *   error only.
11567  *
11568  * @return
11569  *   0 on success, otherwise negative errno value.
11570  */
11571 static int
11572 flow_dv_action_destroy(struct rte_eth_dev *dev,
11573                        struct rte_flow_shared_action *action,
11574                        struct rte_flow_error *error)
11575 {
11576         uint32_t act_idx = (uint32_t)(uintptr_t)action;
11577         uint32_t type = act_idx >> MLX5_SHARED_ACTION_TYPE_OFFSET;
11578         uint32_t idx = act_idx & ((1u << MLX5_SHARED_ACTION_TYPE_OFFSET) - 1);
11579         int ret;
11580
11581         switch (type) {
11582         case MLX5_SHARED_ACTION_TYPE_RSS:
11583                 return __flow_dv_action_rss_release(dev, idx, error);
11584         case MLX5_SHARED_ACTION_TYPE_AGE:
11585                 ret = flow_dv_aso_age_release(dev, idx);
11586                 if (ret)
11587                         /*
11588                          * In this case, the last flow has a reference will
11589                          * actually release the age action.
11590                          */
11591                         DRV_LOG(DEBUG, "Shared age action %" PRIu32 " was"
11592                                 " released with references %d.", idx, ret);
11593                 return 0;
11594         default:
11595                 return rte_flow_error_set(error, ENOTSUP,
11596                                           RTE_FLOW_ERROR_TYPE_ACTION,
11597                                           NULL,
11598                                           "action type not supported");
11599         }
11600 }
11601
11602 /**
11603  * Updates in place shared RSS action configuration.
11604  *
11605  * @param[in] dev
11606  *   Pointer to the Ethernet device structure.
11607  * @param[in] idx
11608  *   The shared RSS action object ID to be updated.
11609  * @param[in] action_conf
11610  *   RSS action specification used to modify *shared_rss*.
11611  * @param[out] error
11612  *   Perform verbose error reporting if not NULL. Initialized in case of
11613  *   error only.
11614  *
11615  * @return
11616  *   0 on success, otherwise negative errno value.
11617  * @note: currently only support update of RSS queues.
11618  */
11619 static int
11620 __flow_dv_action_rss_update(struct rte_eth_dev *dev, uint32_t idx,
11621                             const struct rte_flow_action_rss *action_conf,
11622                             struct rte_flow_error *error)
11623 {
11624         struct mlx5_priv *priv = dev->data->dev_private;
11625         struct mlx5_shared_action_rss *shared_rss =
11626             mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
11627         size_t i;
11628         int ret;
11629         void *queue = NULL;
11630         const uint8_t *rss_key;
11631         uint32_t rss_key_len;
11632         uint32_t queue_size = action_conf->queue_num * sizeof(uint16_t);
11633
11634         if (!shared_rss)
11635                 return rte_flow_error_set(error, EINVAL,
11636                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
11637                                           "invalid shared action to update");
11638         queue = mlx5_malloc(MLX5_MEM_ZERO,
11639                             RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
11640                             0, SOCKET_ID_ANY);
11641         if (!queue)
11642                 return rte_flow_error_set(error, ENOMEM,
11643                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11644                                           NULL,
11645                                           "cannot allocate resource memory");
11646         if (action_conf->key) {
11647                 rss_key = action_conf->key;
11648                 rss_key_len = action_conf->key_len;
11649         } else {
11650                 rss_key = rss_hash_default_key;
11651                 rss_key_len = MLX5_RSS_HASH_KEY_LEN;
11652         }
11653         for (i = 0; i < MLX5_RSS_HASH_FIELDS_LEN; i++) {
11654                 uint32_t hrxq_idx;
11655                 uint64_t hash_fields = mlx5_rss_hash_fields[i];
11656                 int tunnel;
11657
11658                 for (tunnel = 0; tunnel < 2; tunnel++) {
11659                         hrxq_idx = __flow_dv_action_rss_hrxq_lookup
11660                                         (dev, idx, hash_fields, tunnel);
11661                         MLX5_ASSERT(hrxq_idx);
11662                         ret = mlx5_hrxq_modify
11663                                 (dev, hrxq_idx,
11664                                  rss_key, rss_key_len,
11665                                  hash_fields,
11666                                  action_conf->queue, action_conf->queue_num);
11667                         if (ret) {
11668                                 mlx5_free(queue);
11669                                 return rte_flow_error_set
11670                                         (error, rte_errno,
11671                                          RTE_FLOW_ERROR_TYPE_ACTION, NULL,
11672                                          "cannot update hash queue");
11673                         }
11674                 }
11675         }
11676         mlx5_free(shared_rss->queue);
11677         shared_rss->queue = queue;
11678         memcpy(shared_rss->queue, action_conf->queue, queue_size);
11679         shared_rss->origin.queue = shared_rss->queue;
11680         shared_rss->origin.queue_num = action_conf->queue_num;
11681         return 0;
11682 }
11683
11684 /**
11685  * Updates in place shared action configuration, lock free,
11686  * (mutex should be acquired by caller).
11687  *
11688  * @param[in] dev
11689  *   Pointer to the Ethernet device structure.
11690  * @param[in] action
11691  *   The shared action object to be updated.
11692  * @param[in] action_conf
11693  *   Action specification used to modify *action*.
11694  *   *action_conf* should be of type correlating with type of the *action*,
11695  *   otherwise considered as invalid.
11696  * @param[out] error
11697  *   Perform verbose error reporting if not NULL. Initialized in case of
11698  *   error only.
11699  *
11700  * @return
11701  *   0 on success, otherwise negative errno value.
11702  */
11703 static int
11704 flow_dv_action_update(struct rte_eth_dev *dev,
11705                         struct rte_flow_shared_action *action,
11706                         const void *action_conf,
11707                         struct rte_flow_error *err)
11708 {
11709         uint32_t act_idx = (uint32_t)(uintptr_t)action;
11710         uint32_t type = act_idx >> MLX5_SHARED_ACTION_TYPE_OFFSET;
11711         uint32_t idx = act_idx & ((1u << MLX5_SHARED_ACTION_TYPE_OFFSET) - 1);
11712
11713         switch (type) {
11714         case MLX5_SHARED_ACTION_TYPE_RSS:
11715                 return __flow_dv_action_rss_update(dev, idx, action_conf, err);
11716         default:
11717                 return rte_flow_error_set(err, ENOTSUP,
11718                                           RTE_FLOW_ERROR_TYPE_ACTION,
11719                                           NULL,
11720                                           "action type update not supported");
11721         }
11722 }
11723
11724 static int
11725 flow_dv_action_query(struct rte_eth_dev *dev,
11726                      const struct rte_flow_shared_action *action, void *data,
11727                      struct rte_flow_error *error)
11728 {
11729         struct mlx5_age_param *age_param;
11730         struct rte_flow_query_age *resp;
11731         uint32_t act_idx = (uint32_t)(uintptr_t)action;
11732         uint32_t type = act_idx >> MLX5_SHARED_ACTION_TYPE_OFFSET;
11733         uint32_t idx = act_idx & ((1u << MLX5_SHARED_ACTION_TYPE_OFFSET) - 1);
11734
11735         switch (type) {
11736         case MLX5_SHARED_ACTION_TYPE_AGE:
11737                 age_param = &flow_aso_age_get_by_idx(dev, idx)->age_params;
11738                 resp = data;
11739                 resp->aged = __atomic_load_n(&age_param->state,
11740                                               __ATOMIC_RELAXED) == AGE_TMOUT ?
11741                                                                           1 : 0;
11742                 resp->sec_since_last_hit_valid = !resp->aged;
11743                 if (resp->sec_since_last_hit_valid)
11744                         resp->sec_since_last_hit = __atomic_load_n
11745                              (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
11746                 return 0;
11747         default:
11748                 return rte_flow_error_set(error, ENOTSUP,
11749                                           RTE_FLOW_ERROR_TYPE_ACTION,
11750                                           NULL,
11751                                           "action type query not supported");
11752         }
11753 }
11754
11755 /**
11756  * Query a dv flow  rule for its statistics via devx.
11757  *
11758  * @param[in] dev
11759  *   Pointer to Ethernet device.
11760  * @param[in] flow
11761  *   Pointer to the sub flow.
11762  * @param[out] data
11763  *   data retrieved by the query.
11764  * @param[out] error
11765  *   Perform verbose error reporting if not NULL.
11766  *
11767  * @return
11768  *   0 on success, a negative errno value otherwise and rte_errno is set.
11769  */
11770 static int
11771 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
11772                     void *data, struct rte_flow_error *error)
11773 {
11774         struct mlx5_priv *priv = dev->data->dev_private;
11775         struct rte_flow_query_count *qc = data;
11776
11777         if (!priv->config.devx)
11778                 return rte_flow_error_set(error, ENOTSUP,
11779                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11780                                           NULL,
11781                                           "counters are not supported");
11782         if (flow->counter) {
11783                 uint64_t pkts, bytes;
11784                 struct mlx5_flow_counter *cnt;
11785
11786                 cnt = flow_dv_counter_get_by_idx(dev, flow->counter,
11787                                                  NULL);
11788                 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
11789                                                &bytes);
11790
11791                 if (err)
11792                         return rte_flow_error_set(error, -err,
11793                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11794                                         NULL, "cannot read counters");
11795                 qc->hits_set = 1;
11796                 qc->bytes_set = 1;
11797                 qc->hits = pkts - cnt->hits;
11798                 qc->bytes = bytes - cnt->bytes;
11799                 if (qc->reset) {
11800                         cnt->hits = pkts;
11801                         cnt->bytes = bytes;
11802                 }
11803                 return 0;
11804         }
11805         return rte_flow_error_set(error, EINVAL,
11806                                   RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11807                                   NULL,
11808                                   "counters are not available");
11809 }
11810
11811 /**
11812  * Query a flow rule AGE action for aging information.
11813  *
11814  * @param[in] dev
11815  *   Pointer to Ethernet device.
11816  * @param[in] flow
11817  *   Pointer to the sub flow.
11818  * @param[out] data
11819  *   data retrieved by the query.
11820  * @param[out] error
11821  *   Perform verbose error reporting if not NULL.
11822  *
11823  * @return
11824  *   0 on success, a negative errno value otherwise and rte_errno is set.
11825  */
11826 static int
11827 flow_dv_query_age(struct rte_eth_dev *dev, struct rte_flow *flow,
11828                   void *data, struct rte_flow_error *error)
11829 {
11830         struct rte_flow_query_age *resp = data;
11831         struct mlx5_age_param *age_param;
11832
11833         if (flow->age) {
11834                 struct mlx5_aso_age_action *act =
11835                                      flow_aso_age_get_by_idx(dev, flow->age);
11836
11837                 age_param = &act->age_params;
11838         } else if (flow->counter) {
11839                 age_param = flow_dv_counter_idx_get_age(dev, flow->counter);
11840
11841                 if (!age_param || !age_param->timeout)
11842                         return rte_flow_error_set
11843                                         (error, EINVAL,
11844                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11845                                          NULL, "cannot read age data");
11846         } else {
11847                 return rte_flow_error_set(error, EINVAL,
11848                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11849                                           NULL, "age data not available");
11850         }
11851         resp->aged = __atomic_load_n(&age_param->state, __ATOMIC_RELAXED) ==
11852                                      AGE_TMOUT ? 1 : 0;
11853         resp->sec_since_last_hit_valid = !resp->aged;
11854         if (resp->sec_since_last_hit_valid)
11855                 resp->sec_since_last_hit = __atomic_load_n
11856                              (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
11857         return 0;
11858 }
11859
11860 /**
11861  * Query a flow.
11862  *
11863  * @see rte_flow_query()
11864  * @see rte_flow_ops
11865  */
11866 static int
11867 flow_dv_query(struct rte_eth_dev *dev,
11868               struct rte_flow *flow __rte_unused,
11869               const struct rte_flow_action *actions __rte_unused,
11870               void *data __rte_unused,
11871               struct rte_flow_error *error __rte_unused)
11872 {
11873         int ret = -EINVAL;
11874
11875         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
11876                 switch (actions->type) {
11877                 case RTE_FLOW_ACTION_TYPE_VOID:
11878                         break;
11879                 case RTE_FLOW_ACTION_TYPE_COUNT:
11880                         ret = flow_dv_query_count(dev, flow, data, error);
11881                         break;
11882                 case RTE_FLOW_ACTION_TYPE_AGE:
11883                         ret = flow_dv_query_age(dev, flow, data, error);
11884                         break;
11885                 default:
11886                         return rte_flow_error_set(error, ENOTSUP,
11887                                                   RTE_FLOW_ERROR_TYPE_ACTION,
11888                                                   actions,
11889                                                   "action not supported");
11890                 }
11891         }
11892         return ret;
11893 }
11894
11895 /**
11896  * Destroy the meter table set.
11897  * Lock free, (mutex should be acquired by caller).
11898  *
11899  * @param[in] dev
11900  *   Pointer to Ethernet device.
11901  * @param[in] tbl
11902  *   Pointer to the meter table set.
11903  *
11904  * @return
11905  *   Always 0.
11906  */
11907 static int
11908 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
11909                         struct mlx5_meter_domains_infos *tbl)
11910 {
11911         struct mlx5_priv *priv = dev->data->dev_private;
11912         struct mlx5_meter_domains_infos *mtd =
11913                                 (struct mlx5_meter_domains_infos *)tbl;
11914
11915         if (!mtd || !priv->config.dv_flow_en)
11916                 return 0;
11917         if (mtd->ingress.policer_rules[RTE_MTR_DROPPED])
11918                 claim_zero(mlx5_flow_os_destroy_flow
11919                            (mtd->ingress.policer_rules[RTE_MTR_DROPPED]));
11920         if (mtd->egress.policer_rules[RTE_MTR_DROPPED])
11921                 claim_zero(mlx5_flow_os_destroy_flow
11922                            (mtd->egress.policer_rules[RTE_MTR_DROPPED]));
11923         if (mtd->transfer.policer_rules[RTE_MTR_DROPPED])
11924                 claim_zero(mlx5_flow_os_destroy_flow
11925                            (mtd->transfer.policer_rules[RTE_MTR_DROPPED]));
11926         if (mtd->egress.color_matcher)
11927                 claim_zero(mlx5_flow_os_destroy_flow_matcher
11928                            (mtd->egress.color_matcher));
11929         if (mtd->egress.any_matcher)
11930                 claim_zero(mlx5_flow_os_destroy_flow_matcher
11931                            (mtd->egress.any_matcher));
11932         if (mtd->egress.tbl)
11933                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->egress.tbl);
11934         if (mtd->egress.sfx_tbl)
11935                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->egress.sfx_tbl);
11936         if (mtd->ingress.color_matcher)
11937                 claim_zero(mlx5_flow_os_destroy_flow_matcher
11938                            (mtd->ingress.color_matcher));
11939         if (mtd->ingress.any_matcher)
11940                 claim_zero(mlx5_flow_os_destroy_flow_matcher
11941                            (mtd->ingress.any_matcher));
11942         if (mtd->ingress.tbl)
11943                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->ingress.tbl);
11944         if (mtd->ingress.sfx_tbl)
11945                 flow_dv_tbl_resource_release(MLX5_SH(dev),
11946                                              mtd->ingress.sfx_tbl);
11947         if (mtd->transfer.color_matcher)
11948                 claim_zero(mlx5_flow_os_destroy_flow_matcher
11949                            (mtd->transfer.color_matcher));
11950         if (mtd->transfer.any_matcher)
11951                 claim_zero(mlx5_flow_os_destroy_flow_matcher
11952                            (mtd->transfer.any_matcher));
11953         if (mtd->transfer.tbl)
11954                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->transfer.tbl);
11955         if (mtd->transfer.sfx_tbl)
11956                 flow_dv_tbl_resource_release(MLX5_SH(dev),
11957                                              mtd->transfer.sfx_tbl);
11958         if (mtd->drop_actn)
11959                 claim_zero(mlx5_flow_os_destroy_flow_action(mtd->drop_actn));
11960         mlx5_free(mtd);
11961         return 0;
11962 }
11963
11964 /* Number of meter flow actions, count and jump or count and drop. */
11965 #define METER_ACTIONS 2
11966
11967 /**
11968  * Create specify domain meter table and suffix table.
11969  *
11970  * @param[in] dev
11971  *   Pointer to Ethernet device.
11972  * @param[in,out] mtb
11973  *   Pointer to DV meter table set.
11974  * @param[in] egress
11975  *   Table attribute.
11976  * @param[in] transfer
11977  *   Table attribute.
11978  * @param[in] color_reg_c_idx
11979  *   Reg C index for color match.
11980  *
11981  * @return
11982  *   0 on success, -1 otherwise and rte_errno is set.
11983  */
11984 static int
11985 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
11986                            struct mlx5_meter_domains_infos *mtb,
11987                            uint8_t egress, uint8_t transfer,
11988                            uint32_t color_reg_c_idx)
11989 {
11990         struct mlx5_priv *priv = dev->data->dev_private;
11991         struct mlx5_dev_ctx_shared *sh = priv->sh;
11992         struct mlx5_flow_dv_match_params mask = {
11993                 .size = sizeof(mask.buf),
11994         };
11995         struct mlx5_flow_dv_match_params value = {
11996                 .size = sizeof(value.buf),
11997         };
11998         struct mlx5dv_flow_matcher_attr dv_attr = {
11999                 .type = IBV_FLOW_ATTR_NORMAL,
12000                 .priority = 0,
12001                 .match_criteria_enable = 0,
12002                 .match_mask = (void *)&mask,
12003         };
12004         void *actions[METER_ACTIONS];
12005         struct mlx5_meter_domain_info *dtb;
12006         struct rte_flow_error error;
12007         int i = 0;
12008         int ret;
12009
12010         if (transfer)
12011                 dtb = &mtb->transfer;
12012         else if (egress)
12013                 dtb = &mtb->egress;
12014         else
12015                 dtb = &mtb->ingress;
12016         /* Create the meter table with METER level. */
12017         dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
12018                                             egress, transfer, false, NULL, 0,
12019                                             0, &error);
12020         if (!dtb->tbl) {
12021                 DRV_LOG(ERR, "Failed to create meter policer table.");
12022                 return -1;
12023         }
12024         /* Create the meter suffix table with SUFFIX level. */
12025         dtb->sfx_tbl = flow_dv_tbl_resource_get(dev,
12026                                             MLX5_FLOW_TABLE_LEVEL_SUFFIX,
12027                                             egress, transfer, false, NULL, 0,
12028                                             0, &error);
12029         if (!dtb->sfx_tbl) {
12030                 DRV_LOG(ERR, "Failed to create meter suffix table.");
12031                 return -1;
12032         }
12033         /* Create matchers, Any and Color. */
12034         dv_attr.priority = 3;
12035         dv_attr.match_criteria_enable = 0;
12036         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, dtb->tbl->obj,
12037                                                &dtb->any_matcher);
12038         if (ret) {
12039                 DRV_LOG(ERR, "Failed to create meter"
12040                              " policer default matcher.");
12041                 goto error_exit;
12042         }
12043         dv_attr.priority = 0;
12044         dv_attr.match_criteria_enable =
12045                                 1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
12046         flow_dv_match_meta_reg(mask.buf, value.buf, color_reg_c_idx,
12047                                rte_col_2_mlx5_col(RTE_COLORS), UINT8_MAX);
12048         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, dtb->tbl->obj,
12049                                                &dtb->color_matcher);
12050         if (ret) {
12051                 DRV_LOG(ERR, "Failed to create meter policer color matcher.");
12052                 goto error_exit;
12053         }
12054         if (mtb->count_actns[RTE_MTR_DROPPED])
12055                 actions[i++] = mtb->count_actns[RTE_MTR_DROPPED];
12056         actions[i++] = mtb->drop_actn;
12057         /* Default rule: lowest priority, match any, actions: drop. */
12058         ret = mlx5_flow_os_create_flow(dtb->any_matcher, (void *)&value, i,
12059                                        actions,
12060                                        &dtb->policer_rules[RTE_MTR_DROPPED]);
12061         if (ret) {
12062                 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
12063                 goto error_exit;
12064         }
12065         return 0;
12066 error_exit:
12067         return -1;
12068 }
12069
12070 /**
12071  * Create the needed meter and suffix tables.
12072  * Lock free, (mutex should be acquired by caller).
12073  *
12074  * @param[in] dev
12075  *   Pointer to Ethernet device.
12076  * @param[in] fm
12077  *   Pointer to the flow meter.
12078  *
12079  * @return
12080  *   Pointer to table set on success, NULL otherwise and rte_errno is set.
12081  */
12082 static struct mlx5_meter_domains_infos *
12083 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev,
12084                        const struct mlx5_flow_meter *fm)
12085 {
12086         struct mlx5_priv *priv = dev->data->dev_private;
12087         struct mlx5_meter_domains_infos *mtb;
12088         int ret;
12089         int i;
12090
12091         if (!priv->mtr_en) {
12092                 rte_errno = ENOTSUP;
12093                 return NULL;
12094         }
12095         mtb = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mtb), 0, SOCKET_ID_ANY);
12096         if (!mtb) {
12097                 DRV_LOG(ERR, "Failed to allocate memory for meter.");
12098                 return NULL;
12099         }
12100         /* Create meter count actions */
12101         for (i = 0; i <= RTE_MTR_DROPPED; i++) {
12102                 struct mlx5_flow_counter *cnt;
12103                 if (!fm->policer_stats.cnt[i])
12104                         continue;
12105                 cnt = flow_dv_counter_get_by_idx(dev,
12106                       fm->policer_stats.cnt[i], NULL);
12107                 mtb->count_actns[i] = cnt->action;
12108         }
12109         /* Create drop action. */
12110         ret = mlx5_flow_os_create_flow_action_drop(&mtb->drop_actn);
12111         if (ret) {
12112                 DRV_LOG(ERR, "Failed to create drop action.");
12113                 goto error_exit;
12114         }
12115         /* Egress meter table. */
12116         ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0, priv->mtr_color_reg);
12117         if (ret) {
12118                 DRV_LOG(ERR, "Failed to prepare egress meter table.");
12119                 goto error_exit;
12120         }
12121         /* Ingress meter table. */
12122         ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0, priv->mtr_color_reg);
12123         if (ret) {
12124                 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
12125                 goto error_exit;
12126         }
12127         /* FDB meter table. */
12128         if (priv->config.dv_esw_en) {
12129                 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1,
12130                                                  priv->mtr_color_reg);
12131                 if (ret) {
12132                         DRV_LOG(ERR, "Failed to prepare fdb meter table.");
12133                         goto error_exit;
12134                 }
12135         }
12136         return mtb;
12137 error_exit:
12138         flow_dv_destroy_mtr_tbl(dev, mtb);
12139         return NULL;
12140 }
12141
12142 /**
12143  * Destroy domain policer rule.
12144  *
12145  * @param[in] dt
12146  *   Pointer to domain table.
12147  */
12148 static void
12149 flow_dv_destroy_domain_policer_rule(struct mlx5_meter_domain_info *dt)
12150 {
12151         int i;
12152
12153         for (i = 0; i < RTE_MTR_DROPPED; i++) {
12154                 if (dt->policer_rules[i]) {
12155                         claim_zero(mlx5_flow_os_destroy_flow
12156                                    (dt->policer_rules[i]));
12157                         dt->policer_rules[i] = NULL;
12158                 }
12159         }
12160         if (dt->jump_actn) {
12161                 claim_zero(mlx5_flow_os_destroy_flow_action(dt->jump_actn));
12162                 dt->jump_actn = NULL;
12163         }
12164 }
12165
12166 /**
12167  * Destroy policer rules.
12168  *
12169  * @param[in] dev
12170  *   Pointer to Ethernet device.
12171  * @param[in] fm
12172  *   Pointer to flow meter structure.
12173  * @param[in] attr
12174  *   Pointer to flow attributes.
12175  *
12176  * @return
12177  *   Always 0.
12178  */
12179 static int
12180 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev __rte_unused,
12181                               const struct mlx5_flow_meter *fm,
12182                               const struct rte_flow_attr *attr)
12183 {
12184         struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
12185
12186         if (!mtb)
12187                 return 0;
12188         if (attr->egress)
12189                 flow_dv_destroy_domain_policer_rule(&mtb->egress);
12190         if (attr->ingress)
12191                 flow_dv_destroy_domain_policer_rule(&mtb->ingress);
12192         if (attr->transfer)
12193                 flow_dv_destroy_domain_policer_rule(&mtb->transfer);
12194         return 0;
12195 }
12196
12197 /**
12198  * Create specify domain meter policer rule.
12199  *
12200  * @param[in] fm
12201  *   Pointer to flow meter structure.
12202  * @param[in] mtb
12203  *   Pointer to DV meter table set.
12204  * @param[in] mtr_reg_c
12205  *   Color match REG_C.
12206  *
12207  * @return
12208  *   0 on success, -1 otherwise.
12209  */
12210 static int
12211 flow_dv_create_policer_forward_rule(struct mlx5_flow_meter *fm,
12212                                     struct mlx5_meter_domain_info *dtb,
12213                                     uint8_t mtr_reg_c)
12214 {
12215         struct mlx5_flow_dv_match_params matcher = {
12216                 .size = sizeof(matcher.buf),
12217         };
12218         struct mlx5_flow_dv_match_params value = {
12219                 .size = sizeof(value.buf),
12220         };
12221         struct mlx5_meter_domains_infos *mtb = fm->mfts;
12222         void *actions[METER_ACTIONS];
12223         int i;
12224         int ret = 0;
12225
12226         /* Create jump action. */
12227         if (!dtb->jump_actn)
12228                 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
12229                                 (dtb->sfx_tbl->obj, &dtb->jump_actn);
12230         if (ret) {
12231                 DRV_LOG(ERR, "Failed to create policer jump action.");
12232                 goto error;
12233         }
12234         for (i = 0; i < RTE_MTR_DROPPED; i++) {
12235                 int j = 0;
12236
12237                 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_reg_c,
12238                                        rte_col_2_mlx5_col(i), UINT8_MAX);
12239                 if (mtb->count_actns[i])
12240                         actions[j++] = mtb->count_actns[i];
12241                 if (fm->action[i] == MTR_POLICER_ACTION_DROP)
12242                         actions[j++] = mtb->drop_actn;
12243                 else
12244                         actions[j++] = dtb->jump_actn;
12245                 ret = mlx5_flow_os_create_flow(dtb->color_matcher,
12246                                                (void *)&value, j, actions,
12247                                                &dtb->policer_rules[i]);
12248                 if (ret) {
12249                         DRV_LOG(ERR, "Failed to create policer rule.");
12250                         goto error;
12251                 }
12252         }
12253         return 0;
12254 error:
12255         rte_errno = errno;
12256         return -1;
12257 }
12258
12259 /**
12260  * Create policer rules.
12261  *
12262  * @param[in] dev
12263  *   Pointer to Ethernet device.
12264  * @param[in] fm
12265  *   Pointer to flow meter structure.
12266  * @param[in] attr
12267  *   Pointer to flow attributes.
12268  *
12269  * @return
12270  *   0 on success, -1 otherwise.
12271  */
12272 static int
12273 flow_dv_create_policer_rules(struct rte_eth_dev *dev,
12274                              struct mlx5_flow_meter *fm,
12275                              const struct rte_flow_attr *attr)
12276 {
12277         struct mlx5_priv *priv = dev->data->dev_private;
12278         struct mlx5_meter_domains_infos *mtb = fm->mfts;
12279         int ret;
12280
12281         if (attr->egress) {
12282                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->egress,
12283                                                 priv->mtr_color_reg);
12284                 if (ret) {
12285                         DRV_LOG(ERR, "Failed to create egress policer.");
12286                         goto error;
12287                 }
12288         }
12289         if (attr->ingress) {
12290                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->ingress,
12291                                                 priv->mtr_color_reg);
12292                 if (ret) {
12293                         DRV_LOG(ERR, "Failed to create ingress policer.");
12294                         goto error;
12295                 }
12296         }
12297         if (attr->transfer) {
12298                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->transfer,
12299                                                 priv->mtr_color_reg);
12300                 if (ret) {
12301                         DRV_LOG(ERR, "Failed to create transfer policer.");
12302                         goto error;
12303                 }
12304         }
12305         return 0;
12306 error:
12307         flow_dv_destroy_policer_rules(dev, fm, attr);
12308         return -1;
12309 }
12310
12311 /**
12312  * Validate the batch counter support in root table.
12313  *
12314  * Create a simple flow with invalid counter and drop action on root table to
12315  * validate if batch counter with offset on root table is supported or not.
12316  *
12317  * @param[in] dev
12318  *   Pointer to rte_eth_dev structure.
12319  *
12320  * @return
12321  *   0 on success, a negative errno value otherwise and rte_errno is set.
12322  */
12323 int
12324 mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev)
12325 {
12326         struct mlx5_priv *priv = dev->data->dev_private;
12327         struct mlx5_dev_ctx_shared *sh = priv->sh;
12328         struct mlx5_flow_dv_match_params mask = {
12329                 .size = sizeof(mask.buf),
12330         };
12331         struct mlx5_flow_dv_match_params value = {
12332                 .size = sizeof(value.buf),
12333         };
12334         struct mlx5dv_flow_matcher_attr dv_attr = {
12335                 .type = IBV_FLOW_ATTR_NORMAL,
12336                 .priority = 0,
12337                 .match_criteria_enable = 0,
12338                 .match_mask = (void *)&mask,
12339         };
12340         void *actions[2] = { 0 };
12341         struct mlx5_flow_tbl_resource *tbl = NULL;
12342         struct mlx5_devx_obj *dcs = NULL;
12343         void *matcher = NULL;
12344         void *flow = NULL;
12345         int ret = -1;
12346
12347         tbl = flow_dv_tbl_resource_get(dev, 0, 0, 0, false, NULL, 0, 0, NULL);
12348         if (!tbl)
12349                 goto err;
12350         dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
12351         if (!dcs)
12352                 goto err;
12353         ret = mlx5_flow_os_create_flow_action_count(dcs->obj, UINT16_MAX,
12354                                                     &actions[0]);
12355         if (ret)
12356                 goto err;
12357         actions[1] = priv->drop_queue.hrxq->action;
12358         dv_attr.match_criteria_enable = flow_dv_matcher_enable(mask.buf);
12359         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj,
12360                                                &matcher);
12361         if (ret)
12362                 goto err;
12363         ret = mlx5_flow_os_create_flow(matcher, (void *)&value, 2,
12364                                        actions, &flow);
12365 err:
12366         /*
12367          * If batch counter with offset is not supported, the driver will not
12368          * validate the invalid offset value, flow create should success.
12369          * In this case, it means batch counter is not supported in root table.
12370          *
12371          * Otherwise, if flow create is failed, counter offset is supported.
12372          */
12373         if (flow) {
12374                 DRV_LOG(INFO, "Batch counter is not supported in root "
12375                               "table. Switch to fallback mode.");
12376                 rte_errno = ENOTSUP;
12377                 ret = -rte_errno;
12378                 claim_zero(mlx5_flow_os_destroy_flow(flow));
12379         } else {
12380                 /* Check matcher to make sure validate fail at flow create. */
12381                 if (!matcher || (matcher && errno != EINVAL))
12382                         DRV_LOG(ERR, "Unexpected error in counter offset "
12383                                      "support detection");
12384                 ret = 0;
12385         }
12386         if (actions[0])
12387                 claim_zero(mlx5_flow_os_destroy_flow_action(actions[0]));
12388         if (matcher)
12389                 claim_zero(mlx5_flow_os_destroy_flow_matcher(matcher));
12390         if (tbl)
12391                 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
12392         if (dcs)
12393                 claim_zero(mlx5_devx_cmd_destroy(dcs));
12394         return ret;
12395 }
12396
12397 /**
12398  * Query a devx counter.
12399  *
12400  * @param[in] dev
12401  *   Pointer to the Ethernet device structure.
12402  * @param[in] cnt
12403  *   Index to the flow counter.
12404  * @param[in] clear
12405  *   Set to clear the counter statistics.
12406  * @param[out] pkts
12407  *   The statistics value of packets.
12408  * @param[out] bytes
12409  *   The statistics value of bytes.
12410  *
12411  * @return
12412  *   0 on success, otherwise return -1.
12413  */
12414 static int
12415 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
12416                       uint64_t *pkts, uint64_t *bytes)
12417 {
12418         struct mlx5_priv *priv = dev->data->dev_private;
12419         struct mlx5_flow_counter *cnt;
12420         uint64_t inn_pkts, inn_bytes;
12421         int ret;
12422
12423         if (!priv->config.devx)
12424                 return -1;
12425
12426         ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
12427         if (ret)
12428                 return -1;
12429         cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
12430         *pkts = inn_pkts - cnt->hits;
12431         *bytes = inn_bytes - cnt->bytes;
12432         if (clear) {
12433                 cnt->hits = inn_pkts;
12434                 cnt->bytes = inn_bytes;
12435         }
12436         return 0;
12437 }
12438
12439 /**
12440  * Get aged-out flows.
12441  *
12442  * @param[in] dev
12443  *   Pointer to the Ethernet device structure.
12444  * @param[in] context
12445  *   The address of an array of pointers to the aged-out flows contexts.
12446  * @param[in] nb_contexts
12447  *   The length of context array pointers.
12448  * @param[out] error
12449  *   Perform verbose error reporting if not NULL. Initialized in case of
12450  *   error only.
12451  *
12452  * @return
12453  *   how many contexts get in success, otherwise negative errno value.
12454  *   if nb_contexts is 0, return the amount of all aged contexts.
12455  *   if nb_contexts is not 0 , return the amount of aged flows reported
12456  *   in the context array.
12457  * @note: only stub for now
12458  */
12459 static int
12460 flow_get_aged_flows(struct rte_eth_dev *dev,
12461                     void **context,
12462                     uint32_t nb_contexts,
12463                     struct rte_flow_error *error)
12464 {
12465         struct mlx5_priv *priv = dev->data->dev_private;
12466         struct mlx5_age_info *age_info;
12467         struct mlx5_age_param *age_param;
12468         struct mlx5_flow_counter *counter;
12469         struct mlx5_aso_age_action *act;
12470         int nb_flows = 0;
12471
12472         if (nb_contexts && !context)
12473                 return rte_flow_error_set(error, EINVAL,
12474                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12475                                           NULL, "empty context");
12476         age_info = GET_PORT_AGE_INFO(priv);
12477         rte_spinlock_lock(&age_info->aged_sl);
12478         LIST_FOREACH(act, &age_info->aged_aso, next) {
12479                 nb_flows++;
12480                 if (nb_contexts) {
12481                         context[nb_flows - 1] =
12482                                                 act->age_params.context;
12483                         if (!(--nb_contexts))
12484                                 break;
12485                 }
12486         }
12487         TAILQ_FOREACH(counter, &age_info->aged_counters, next) {
12488                 nb_flows++;
12489                 if (nb_contexts) {
12490                         age_param = MLX5_CNT_TO_AGE(counter);
12491                         context[nb_flows - 1] = age_param->context;
12492                         if (!(--nb_contexts))
12493                                 break;
12494                 }
12495         }
12496         rte_spinlock_unlock(&age_info->aged_sl);
12497         MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
12498         return nb_flows;
12499 }
12500
12501 /*
12502  * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
12503  */
12504 static uint32_t
12505 flow_dv_counter_allocate(struct rte_eth_dev *dev)
12506 {
12507         return flow_dv_counter_alloc(dev, 0);
12508 }
12509
12510 /**
12511  * Validate shared action.
12512  * Dispatcher for action type specific validation.
12513  *
12514  * @param[in] dev
12515  *   Pointer to the Ethernet device structure.
12516  * @param[in] conf
12517  *   Shared action configuration.
12518  * @param[in] action
12519  *   The shared action object to validate.
12520  * @param[out] error
12521  *   Perform verbose error reporting if not NULL. Initialized in case of
12522  *   error only.
12523  *
12524  * @return
12525  *   0 on success, otherwise negative errno value.
12526  */
12527 static int
12528 flow_dv_action_validate(struct rte_eth_dev *dev,
12529                         const struct rte_flow_shared_action_conf *conf,
12530                         const struct rte_flow_action *action,
12531                         struct rte_flow_error *err)
12532 {
12533         struct mlx5_priv *priv = dev->data->dev_private;
12534
12535         RTE_SET_USED(conf);
12536         switch (action->type) {
12537         case RTE_FLOW_ACTION_TYPE_RSS:
12538                 return mlx5_validate_action_rss(dev, action, err);
12539         case RTE_FLOW_ACTION_TYPE_AGE:
12540                 if (!priv->sh->aso_age_mng)
12541                         return rte_flow_error_set(err, ENOTSUP,
12542                                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12543                                                 NULL,
12544                                              "shared age action not supported");
12545                 return flow_dv_validate_action_age(0, action, dev, err);
12546         default:
12547                 return rte_flow_error_set(err, ENOTSUP,
12548                                           RTE_FLOW_ERROR_TYPE_ACTION,
12549                                           NULL,
12550                                           "action type not supported");
12551         }
12552 }
12553
12554 static int
12555 flow_dv_sync_domain(struct rte_eth_dev *dev, uint32_t domains, uint32_t flags)
12556 {
12557         struct mlx5_priv *priv = dev->data->dev_private;
12558         int ret = 0;
12559
12560         if ((domains & MLX5_DOMAIN_BIT_NIC_RX) && priv->sh->rx_domain != NULL) {
12561                 ret = mlx5_glue->dr_sync_domain(priv->sh->rx_domain,
12562                                                 flags);
12563                 if (ret != 0)
12564                         return ret;
12565         }
12566         if ((domains & MLX5_DOMAIN_BIT_NIC_TX) && priv->sh->tx_domain != NULL) {
12567                 ret = mlx5_glue->dr_sync_domain(priv->sh->tx_domain, flags);
12568                 if (ret != 0)
12569                         return ret;
12570         }
12571         if ((domains & MLX5_DOMAIN_BIT_FDB) && priv->sh->fdb_domain != NULL) {
12572                 ret = mlx5_glue->dr_sync_domain(priv->sh->fdb_domain, flags);
12573                 if (ret != 0)
12574                         return ret;
12575         }
12576         return 0;
12577 }
12578
12579 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
12580         .validate = flow_dv_validate,
12581         .prepare = flow_dv_prepare,
12582         .translate = flow_dv_translate,
12583         .apply = flow_dv_apply,
12584         .remove = flow_dv_remove,
12585         .destroy = flow_dv_destroy,
12586         .query = flow_dv_query,
12587         .create_mtr_tbls = flow_dv_create_mtr_tbl,
12588         .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
12589         .create_policer_rules = flow_dv_create_policer_rules,
12590         .destroy_policer_rules = flow_dv_destroy_policer_rules,
12591         .counter_alloc = flow_dv_counter_allocate,
12592         .counter_free = flow_dv_counter_free,
12593         .counter_query = flow_dv_counter_query,
12594         .get_aged_flows = flow_get_aged_flows,
12595         .action_validate = flow_dv_action_validate,
12596         .action_create = flow_dv_action_create,
12597         .action_destroy = flow_dv_action_destroy,
12598         .action_update = flow_dv_action_update,
12599         .action_query = flow_dv_action_query,
12600         .sync_domain = flow_dv_sync_domain,
12601 };
12602
12603 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */
12604