drivers/net/mlx5/mlx5_flow_dv.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2018 Mellanox Technologies, Ltd
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdalign.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10
  11 /* Verbs header. */
  12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  13 #ifdef PEDANTIC
  14 #pragma GCC diagnostic ignored "-Wpedantic"
  15 #endif
  16 #include <infiniband/verbs.h>
  17 #ifdef PEDANTIC
  18 #pragma GCC diagnostic error "-Wpedantic"
  19 #endif
  20
  21 #include <rte_common.h>
  22 #include <rte_ether.h>
  23 #include <rte_ethdev_driver.h>
  24 #include <rte_flow.h>
  25 #include <rte_flow_driver.h>
  26 #include <rte_malloc.h>
  27 #include <rte_ip.h>
  28 #include <rte_gre.h>
  29 #include <rte_vxlan.h>
  30 #include <rte_gtp.h>
  31
  32 #include <mlx5_glue.h>
  33 #include <mlx5_devx_cmds.h>
  34 #include <mlx5_prm.h>
  35
  36 #include "mlx5_defs.h"
  37 #include "mlx5.h"
  38 #include "mlx5_flow.h"
  39 #include "mlx5_rxtx.h"
  40
  41 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
  42
  43 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
  44 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
  45 #endif
  46
  47 #ifndef HAVE_MLX5DV_DR_ESWITCH
  48 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
  49 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
  50 #endif
  51 #endif
  52
  53 #ifndef HAVE_MLX5DV_DR
  54 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
  55 #endif
  56
  57 /* VLAN header definitions */
  58 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
  59 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
  60 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
  61 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
  62 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
  63
  64 union flow_dv_attr {
  65         struct {
  66                 uint32_t valid:1;
  67                 uint32_t ipv4:1;
  68                 uint32_t ipv6:1;
  69                 uint32_t tcp:1;
  70                 uint32_t udp:1;
  71                 uint32_t reserved:27;
  72         };
  73         uint32_t attr;
  74 };
  75
  76 static int
  77 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
  78                              struct mlx5_flow_tbl_resource *tbl);
  79
  80 /**
  81  * Initialize flow attributes structure according to flow items' types.
  82  *
  83  * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
  84  * mode. For tunnel mode, the items to be modified are the outermost ones.
  85  *
  86  * @param[in] item
  87  *   Pointer to item specification.
  88  * @param[out] attr
  89  *   Pointer to flow attributes structure.
  90  * @param[in] dev_flow
  91  *   Pointer to the sub flow.
  92  * @param[in] tunnel_decap
  93  *   Whether action is after tunnel decapsulation.
  94  */
  95 static void
  96 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
  97                   struct mlx5_flow *dev_flow, bool tunnel_decap)
  98 {
  99         uint64_t layers = dev_flow->handle->layers;
 100
 101         /*
 102          * If layers is already initialized, it means this dev_flow is the
 103          * suffix flow, the layers flags is set by the prefix flow. Need to
 104          * use the layer flags from prefix flow as the suffix flow may not
 105          * have the user defined items as the flow is split.
 106          */
 107         if (layers) {
 108                 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
 109                         attr->ipv4 = 1;
 110                 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
 111                         attr->ipv6 = 1;
 112                 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
 113                         attr->tcp = 1;
 114                 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
 115                         attr->udp = 1;
 116                 attr->valid = 1;
 117                 return;
 118         }
 119         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
 120                 uint8_t next_protocol = 0xff;
 121                 switch (item->type) {
 122                 case RTE_FLOW_ITEM_TYPE_GRE:
 123                 case RTE_FLOW_ITEM_TYPE_NVGRE:
 124                 case RTE_FLOW_ITEM_TYPE_VXLAN:
 125                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
 126                 case RTE_FLOW_ITEM_TYPE_GENEVE:
 127                 case RTE_FLOW_ITEM_TYPE_MPLS:
 128                         if (tunnel_decap)
 129                                 attr->attr = 0;
 130                         break;
 131                 case RTE_FLOW_ITEM_TYPE_IPV4:
 132                         if (!attr->ipv6)
 133                                 attr->ipv4 = 1;
 134                         if (item->mask != NULL &&
 135                             ((const struct rte_flow_item_ipv4 *)
 136                             item->mask)->hdr.next_proto_id)
 137                                 next_protocol =
 138                                     ((const struct rte_flow_item_ipv4 *)
 139                                       (item->spec))->hdr.next_proto_id &
 140                                     ((const struct rte_flow_item_ipv4 *)
 141                                       (item->mask))->hdr.next_proto_id;
 142                         if ((next_protocol == IPPROTO_IPIP ||
 143                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 144                                 attr->attr = 0;
 145                         break;
 146                 case RTE_FLOW_ITEM_TYPE_IPV6:
 147                         if (!attr->ipv4)
 148                                 attr->ipv6 = 1;
 149                         if (item->mask != NULL &&
 150                             ((const struct rte_flow_item_ipv6 *)
 151                             item->mask)->hdr.proto)
 152                                 next_protocol =
 153                                     ((const struct rte_flow_item_ipv6 *)
 154                                       (item->spec))->hdr.proto &
 155                                     ((const struct rte_flow_item_ipv6 *)
 156                                       (item->mask))->hdr.proto;
 157                         if ((next_protocol == IPPROTO_IPIP ||
 158                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 159                                 attr->attr = 0;
 160                         break;
 161                 case RTE_FLOW_ITEM_TYPE_UDP:
 162                         if (!attr->tcp)
 163                                 attr->udp = 1;
 164                         break;
 165                 case RTE_FLOW_ITEM_TYPE_TCP:
 166                         if (!attr->udp)
 167                                 attr->tcp = 1;
 168                         break;
 169                 default:
 170                         break;
 171                 }
 172         }
 173         attr->valid = 1;
 174 }
 175
 176 /**
 177  * Convert rte_mtr_color to mlx5 color.
 178  *
 179  * @param[in] rcol
 180  *   rte_mtr_color.
 181  *
 182  * @return
 183  *   mlx5 color.
 184  */
 185 static int
 186 rte_col_2_mlx5_col(enum rte_color rcol)
 187 {
 188         switch (rcol) {
 189         case RTE_COLOR_GREEN:
 190                 return MLX5_FLOW_COLOR_GREEN;
 191         case RTE_COLOR_YELLOW:
 192                 return MLX5_FLOW_COLOR_YELLOW;
 193         case RTE_COLOR_RED:
 194                 return MLX5_FLOW_COLOR_RED;
 195         default:
 196                 break;
 197         }
 198         return MLX5_FLOW_COLOR_UNDEFINED;
 199 }
 200
 201 struct field_modify_info {
 202         uint32_t size; /* Size of field in protocol header, in bytes. */
 203         uint32_t offset; /* Offset of field in protocol header, in bytes. */
 204         enum mlx5_modification_field id;
 205 };
 206
 207 struct field_modify_info modify_eth[] = {
 208         {4,  0, MLX5_MODI_OUT_DMAC_47_16},
 209         {2,  4, MLX5_MODI_OUT_DMAC_15_0},
 210         {4,  6, MLX5_MODI_OUT_SMAC_47_16},
 211         {2, 10, MLX5_MODI_OUT_SMAC_15_0},
 212         {0, 0, 0},
 213 };
 214
 215 struct field_modify_info modify_vlan_out_first_vid[] = {
 216         /* Size in bits !!! */
 217         {12, 0, MLX5_MODI_OUT_FIRST_VID},
 218         {0, 0, 0},
 219 };
 220
 221 struct field_modify_info modify_ipv4[] = {
 222         {1,  1, MLX5_MODI_OUT_IP_DSCP},
 223         {1,  8, MLX5_MODI_OUT_IPV4_TTL},
 224         {4, 12, MLX5_MODI_OUT_SIPV4},
 225         {4, 16, MLX5_MODI_OUT_DIPV4},
 226         {0, 0, 0},
 227 };
 228
 229 struct field_modify_info modify_ipv6[] = {
 230         {1,  0, MLX5_MODI_OUT_IP_DSCP},
 231         {1,  7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
 232         {4,  8, MLX5_MODI_OUT_SIPV6_127_96},
 233         {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
 234         {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
 235         {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
 236         {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
 237         {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
 238         {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
 239         {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
 240         {0, 0, 0},
 241 };
 242
 243 struct field_modify_info modify_udp[] = {
 244         {2, 0, MLX5_MODI_OUT_UDP_SPORT},
 245         {2, 2, MLX5_MODI_OUT_UDP_DPORT},
 246         {0, 0, 0},
 247 };
 248
 249 struct field_modify_info modify_tcp[] = {
 250         {2, 0, MLX5_MODI_OUT_TCP_SPORT},
 251         {2, 2, MLX5_MODI_OUT_TCP_DPORT},
 252         {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
 253         {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
 254         {0, 0, 0},
 255 };
 256
 257 static void
 258 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
 259                           uint8_t next_protocol, uint64_t *item_flags,
 260                           int *tunnel)
 261 {
 262         MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
 263                     item->type == RTE_FLOW_ITEM_TYPE_IPV6);
 264         if (next_protocol == IPPROTO_IPIP) {
 265                 *item_flags |= MLX5_FLOW_LAYER_IPIP;
 266                 *tunnel = 1;
 267         }
 268         if (next_protocol == IPPROTO_IPV6) {
 269                 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
 270                 *tunnel = 1;
 271         }
 272 }
 273
 274 /**
 275  * Acquire the synchronizing object to protect multithreaded access
 276  * to shared dv context. Lock occurs only if context is actually
 277  * shared, i.e. we have multiport IB device and representors are
 278  * created.
 279  *
 280  * @param[in] dev
 281  *   Pointer to the rte_eth_dev structure.
 282  */
 283 static void
 284 flow_dv_shared_lock(struct rte_eth_dev *dev)
 285 {
 286         struct mlx5_priv *priv = dev->data->dev_private;
 287         struct mlx5_ibv_shared *sh = priv->sh;
 288
 289         if (sh->dv_refcnt > 1) {
 290                 int ret;
 291
 292                 ret = pthread_mutex_lock(&sh->dv_mutex);
 293                 MLX5_ASSERT(!ret);
 294                 (void)ret;
 295         }
 296 }
 297
 298 static void
 299 flow_dv_shared_unlock(struct rte_eth_dev *dev)
 300 {
 301         struct mlx5_priv *priv = dev->data->dev_private;
 302         struct mlx5_ibv_shared *sh = priv->sh;
 303
 304         if (sh->dv_refcnt > 1) {
 305                 int ret;
 306
 307                 ret = pthread_mutex_unlock(&sh->dv_mutex);
 308                 MLX5_ASSERT(!ret);
 309                 (void)ret;
 310         }
 311 }
 312
 313 /* Update VLAN's VID/PCP based on input rte_flow_action.
 314  *
 315  * @param[in] action
 316  *   Pointer to struct rte_flow_action.
 317  * @param[out] vlan
 318  *   Pointer to struct rte_vlan_hdr.
 319  */
 320 static void
 321 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
 322                          struct rte_vlan_hdr *vlan)
 323 {
 324         uint16_t vlan_tci;
 325         if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
 326                 vlan_tci =
 327                     ((const struct rte_flow_action_of_set_vlan_pcp *)
 328                                                action->conf)->vlan_pcp;
 329                 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
 330                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
 331                 vlan->vlan_tci |= vlan_tci;
 332         } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
 333                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
 334                 vlan->vlan_tci |= rte_be_to_cpu_16
 335                     (((const struct rte_flow_action_of_set_vlan_vid *)
 336                                              action->conf)->vlan_vid);
 337         }
 338 }
 339
 340 /**
 341  * Fetch 1, 2, 3 or 4 byte field from the byte array
 342  * and return as unsigned integer in host-endian format.
 343  *
 344  * @param[in] data
 345  *   Pointer to data array.
 346  * @param[in] size
 347  *   Size of field to extract.
 348  *
 349  * @return
 350  *   converted field in host endian format.
 351  */
 352 static inline uint32_t
 353 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
 354 {
 355         uint32_t ret;
 356
 357         switch (size) {
 358         case 1:
 359                 ret = *data;
 360                 break;
 361         case 2:
 362                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 363                 break;
 364         case 3:
 365                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 366                 ret = (ret << 8) | *(data + sizeof(uint16_t));
 367                 break;
 368         case 4:
 369                 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
 370                 break;
 371         default:
 372                 MLX5_ASSERT(false);
 373                 ret = 0;
 374                 break;
 375         }
 376         return ret;
 377 }
 378
 379 /**
 380  * Convert modify-header action to DV specification.
 381  *
 382  * Data length of each action is determined by provided field description
 383  * and the item mask. Data bit offset and width of each action is determined
 384  * by provided item mask.
 385  *
 386  * @param[in] item
 387  *   Pointer to item specification.
 388  * @param[in] field
 389  *   Pointer to field modification information.
 390  *     For MLX5_MODIFICATION_TYPE_SET specifies destination field.
 391  *     For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
 392  *     For MLX5_MODIFICATION_TYPE_COPY specifies source field.
 393  * @param[in] dcopy
 394  *   Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
 395  *   Negative offset value sets the same offset as source offset.
 396  *   size field is ignored, value is taken from source field.
 397  * @param[in,out] resource
 398  *   Pointer to the modify-header resource.
 399  * @param[in] type
 400  *   Type of modification.
 401  * @param[out] error
 402  *   Pointer to the error structure.
 403  *
 404  * @return
 405  *   0 on success, a negative errno value otherwise and rte_errno is set.
 406  */
 407 static int
 408 flow_dv_convert_modify_action(struct rte_flow_item *item,
 409                               struct field_modify_info *field,
 410                               struct field_modify_info *dcopy,
 411                               struct mlx5_flow_dv_modify_hdr_resource *resource,
 412                               uint32_t type, struct rte_flow_error *error)
 413 {
 414         uint32_t i = resource->actions_num;
 415         struct mlx5_modification_cmd *actions = resource->actions;
 416
 417         /*
 418          * The item and mask are provided in big-endian format.
 419          * The fields should be presented as in big-endian format either.
 420          * Mask must be always present, it defines the actual field width.
 421          */
 422         MLX5_ASSERT(item->mask);
 423         MLX5_ASSERT(field->size);
 424         do {
 425                 unsigned int size_b;
 426                 unsigned int off_b;
 427                 uint32_t mask;
 428                 uint32_t data;
 429
 430                 if (i >= MLX5_MAX_MODIFY_NUM)
 431                         return rte_flow_error_set(error, EINVAL,
 432                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 433                                  "too many items to modify");
 434                 /* Fetch variable byte size mask from the array. */
 435                 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
 436                                            field->offset, field->size);
 437                 if (!mask) {
 438                         ++field;
 439                         continue;
 440                 }
 441                 /* Deduce actual data width in bits from mask value. */
 442                 off_b = rte_bsf32(mask);
 443                 size_b = sizeof(uint32_t) * CHAR_BIT -
 444                          off_b - __builtin_clz(mask);
 445                 MLX5_ASSERT(size_b);
 446                 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
 447                 actions[i] = (struct mlx5_modification_cmd) {
 448                         .action_type = type,
 449                         .field = field->id,
 450                         .offset = off_b,
 451                         .length = size_b,
 452                 };
 453                 /* Convert entire record to expected big-endian format. */
 454                 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 455                 if (type == MLX5_MODIFICATION_TYPE_COPY) {
 456                         MLX5_ASSERT(dcopy);
 457                         actions[i].dst_field = dcopy->id;
 458                         actions[i].dst_offset =
 459                                 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
 460                         /* Convert entire record to big-endian format. */
 461                         actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
 462                 } else {
 463                         MLX5_ASSERT(item->spec);
 464                         data = flow_dv_fetch_field((const uint8_t *)item->spec +
 465                                                    field->offset, field->size);
 466                         /* Shift out the trailing masked bits from data. */
 467                         data = (data & mask) >> off_b;
 468                         actions[i].data1 = rte_cpu_to_be_32(data);
 469                 }
 470                 ++i;
 471                 ++field;
 472         } while (field->size);
 473         if (resource->actions_num == i)
 474                 return rte_flow_error_set(error, EINVAL,
 475                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 476                                           "invalid modification flow item");
 477         resource->actions_num = i;
 478         return 0;
 479 }
 480
 481 /**
 482  * Convert modify-header set IPv4 address action to DV specification.
 483  *
 484  * @param[in,out] resource
 485  *   Pointer to the modify-header resource.
 486  * @param[in] action
 487  *   Pointer to action specification.
 488  * @param[out] error
 489  *   Pointer to the error structure.
 490  *
 491  * @return
 492  *   0 on success, a negative errno value otherwise and rte_errno is set.
 493  */
 494 static int
 495 flow_dv_convert_action_modify_ipv4
 496                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 497                          const struct rte_flow_action *action,
 498                          struct rte_flow_error *error)
 499 {
 500         const struct rte_flow_action_set_ipv4 *conf =
 501                 (const struct rte_flow_action_set_ipv4 *)(action->conf);
 502         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
 503         struct rte_flow_item_ipv4 ipv4;
 504         struct rte_flow_item_ipv4 ipv4_mask;
 505
 506         memset(&ipv4, 0, sizeof(ipv4));
 507         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 508         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
 509                 ipv4.hdr.src_addr = conf->ipv4_addr;
 510                 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
 511         } else {
 512                 ipv4.hdr.dst_addr = conf->ipv4_addr;
 513                 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
 514         }
 515         item.spec = &ipv4;
 516         item.mask = &ipv4_mask;
 517         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
 518                                              MLX5_MODIFICATION_TYPE_SET, error);
 519 }
 520
 521 /**
 522  * Convert modify-header set IPv6 address action to DV specification.
 523  *
 524  * @param[in,out] resource
 525  *   Pointer to the modify-header resource.
 526  * @param[in] action
 527  *   Pointer to action specification.
 528  * @param[out] error
 529  *   Pointer to the error structure.
 530  *
 531  * @return
 532  *   0 on success, a negative errno value otherwise and rte_errno is set.
 533  */
 534 static int
 535 flow_dv_convert_action_modify_ipv6
 536                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 537                          const struct rte_flow_action *action,
 538                          struct rte_flow_error *error)
 539 {
 540         const struct rte_flow_action_set_ipv6 *conf =
 541                 (const struct rte_flow_action_set_ipv6 *)(action->conf);
 542         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
 543         struct rte_flow_item_ipv6 ipv6;
 544         struct rte_flow_item_ipv6 ipv6_mask;
 545
 546         memset(&ipv6, 0, sizeof(ipv6));
 547         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 548         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
 549                 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
 550                        sizeof(ipv6.hdr.src_addr));
 551                 memcpy(&ipv6_mask.hdr.src_addr,
 552                        &rte_flow_item_ipv6_mask.hdr.src_addr,
 553                        sizeof(ipv6.hdr.src_addr));
 554         } else {
 555                 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
 556                        sizeof(ipv6.hdr.dst_addr));
 557                 memcpy(&ipv6_mask.hdr.dst_addr,
 558                        &rte_flow_item_ipv6_mask.hdr.dst_addr,
 559                        sizeof(ipv6.hdr.dst_addr));
 560         }
 561         item.spec = &ipv6;
 562         item.mask = &ipv6_mask;
 563         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
 564                                              MLX5_MODIFICATION_TYPE_SET, error);
 565 }
 566
 567 /**
 568  * Convert modify-header set MAC address action to DV specification.
 569  *
 570  * @param[in,out] resource
 571  *   Pointer to the modify-header resource.
 572  * @param[in] action
 573  *   Pointer to action specification.
 574  * @param[out] error
 575  *   Pointer to the error structure.
 576  *
 577  * @return
 578  *   0 on success, a negative errno value otherwise and rte_errno is set.
 579  */
 580 static int
 581 flow_dv_convert_action_modify_mac
 582                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 583                          const struct rte_flow_action *action,
 584                          struct rte_flow_error *error)
 585 {
 586         const struct rte_flow_action_set_mac *conf =
 587                 (const struct rte_flow_action_set_mac *)(action->conf);
 588         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
 589         struct rte_flow_item_eth eth;
 590         struct rte_flow_item_eth eth_mask;
 591
 592         memset(&eth, 0, sizeof(eth));
 593         memset(&eth_mask, 0, sizeof(eth_mask));
 594         if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
 595                 memcpy(&eth.src.addr_bytes, &conf->mac_addr,
 596                        sizeof(eth.src.addr_bytes));
 597                 memcpy(&eth_mask.src.addr_bytes,
 598                        &rte_flow_item_eth_mask.src.addr_bytes,
 599                        sizeof(eth_mask.src.addr_bytes));
 600         } else {
 601                 memcpy(&eth.dst.addr_bytes, &conf->mac_addr,
 602                        sizeof(eth.dst.addr_bytes));
 603                 memcpy(&eth_mask.dst.addr_bytes,
 604                        &rte_flow_item_eth_mask.dst.addr_bytes,
 605                        sizeof(eth_mask.dst.addr_bytes));
 606         }
 607         item.spec = &eth;
 608         item.mask = &eth_mask;
 609         return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
 610                                              MLX5_MODIFICATION_TYPE_SET, error);
 611 }
 612
 613 /**
 614  * Convert modify-header set VLAN VID action to DV specification.
 615  *
 616  * @param[in,out] resource
 617  *   Pointer to the modify-header resource.
 618  * @param[in] action
 619  *   Pointer to action specification.
 620  * @param[out] error
 621  *   Pointer to the error structure.
 622  *
 623  * @return
 624  *   0 on success, a negative errno value otherwise and rte_errno is set.
 625  */
 626 static int
 627 flow_dv_convert_action_modify_vlan_vid
 628                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 629                          const struct rte_flow_action *action,
 630                          struct rte_flow_error *error)
 631 {
 632         const struct rte_flow_action_of_set_vlan_vid *conf =
 633                 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
 634         int i = resource->actions_num;
 635         struct mlx5_modification_cmd *actions = resource->actions;
 636         struct field_modify_info *field = modify_vlan_out_first_vid;
 637
 638         if (i >= MLX5_MAX_MODIFY_NUM)
 639                 return rte_flow_error_set(error, EINVAL,
 640                          RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 641                          "too many items to modify");
 642         actions[i] = (struct mlx5_modification_cmd) {
 643                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 644                 .field = field->id,
 645                 .length = field->size,
 646                 .offset = field->offset,
 647         };
 648         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 649         actions[i].data1 = conf->vlan_vid;
 650         actions[i].data1 = actions[i].data1 << 16;
 651         resource->actions_num = ++i;
 652         return 0;
 653 }
 654
 655 /**
 656  * Convert modify-header set TP action to DV specification.
 657  *
 658  * @param[in,out] resource
 659  *   Pointer to the modify-header resource.
 660  * @param[in] action
 661  *   Pointer to action specification.
 662  * @param[in] items
 663  *   Pointer to rte_flow_item objects list.
 664  * @param[in] attr
 665  *   Pointer to flow attributes structure.
 666  * @param[in] dev_flow
 667  *   Pointer to the sub flow.
 668  * @param[in] tunnel_decap
 669  *   Whether action is after tunnel decapsulation.
 670  * @param[out] error
 671  *   Pointer to the error structure.
 672  *
 673  * @return
 674  *   0 on success, a negative errno value otherwise and rte_errno is set.
 675  */
 676 static int
 677 flow_dv_convert_action_modify_tp
 678                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 679                          const struct rte_flow_action *action,
 680                          const struct rte_flow_item *items,
 681                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 682                          bool tunnel_decap, struct rte_flow_error *error)
 683 {
 684         const struct rte_flow_action_set_tp *conf =
 685                 (const struct rte_flow_action_set_tp *)(action->conf);
 686         struct rte_flow_item item;
 687         struct rte_flow_item_udp udp;
 688         struct rte_flow_item_udp udp_mask;
 689         struct rte_flow_item_tcp tcp;
 690         struct rte_flow_item_tcp tcp_mask;
 691         struct field_modify_info *field;
 692
 693         if (!attr->valid)
 694                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 695         if (attr->udp) {
 696                 memset(&udp, 0, sizeof(udp));
 697                 memset(&udp_mask, 0, sizeof(udp_mask));
 698                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 699                         udp.hdr.src_port = conf->port;
 700                         udp_mask.hdr.src_port =
 701                                         rte_flow_item_udp_mask.hdr.src_port;
 702                 } else {
 703                         udp.hdr.dst_port = conf->port;
 704                         udp_mask.hdr.dst_port =
 705                                         rte_flow_item_udp_mask.hdr.dst_port;
 706                 }
 707                 item.type = RTE_FLOW_ITEM_TYPE_UDP;
 708                 item.spec = &udp;
 709                 item.mask = &udp_mask;
 710                 field = modify_udp;
 711         } else {
 712                 MLX5_ASSERT(attr->tcp);
 713                 memset(&tcp, 0, sizeof(tcp));
 714                 memset(&tcp_mask, 0, sizeof(tcp_mask));
 715                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 716                         tcp.hdr.src_port = conf->port;
 717                         tcp_mask.hdr.src_port =
 718                                         rte_flow_item_tcp_mask.hdr.src_port;
 719                 } else {
 720                         tcp.hdr.dst_port = conf->port;
 721                         tcp_mask.hdr.dst_port =
 722                                         rte_flow_item_tcp_mask.hdr.dst_port;
 723                 }
 724                 item.type = RTE_FLOW_ITEM_TYPE_TCP;
 725                 item.spec = &tcp;
 726                 item.mask = &tcp_mask;
 727                 field = modify_tcp;
 728         }
 729         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 730                                              MLX5_MODIFICATION_TYPE_SET, error);
 731 }
 732
 733 /**
 734  * Convert modify-header set TTL action to DV specification.
 735  *
 736  * @param[in,out] resource
 737  *   Pointer to the modify-header resource.
 738  * @param[in] action
 739  *   Pointer to action specification.
 740  * @param[in] items
 741  *   Pointer to rte_flow_item objects list.
 742  * @param[in] attr
 743  *   Pointer to flow attributes structure.
 744  * @param[in] dev_flow
 745  *   Pointer to the sub flow.
 746  * @param[in] tunnel_decap
 747  *   Whether action is after tunnel decapsulation.
 748  * @param[out] error
 749  *   Pointer to the error structure.
 750  *
 751  * @return
 752  *   0 on success, a negative errno value otherwise and rte_errno is set.
 753  */
 754 static int
 755 flow_dv_convert_action_modify_ttl
 756                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 757                          const struct rte_flow_action *action,
 758                          const struct rte_flow_item *items,
 759                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 760                          bool tunnel_decap, struct rte_flow_error *error)
 761 {
 762         const struct rte_flow_action_set_ttl *conf =
 763                 (const struct rte_flow_action_set_ttl *)(action->conf);
 764         struct rte_flow_item item;
 765         struct rte_flow_item_ipv4 ipv4;
 766         struct rte_flow_item_ipv4 ipv4_mask;
 767         struct rte_flow_item_ipv6 ipv6;
 768         struct rte_flow_item_ipv6 ipv6_mask;
 769         struct field_modify_info *field;
 770
 771         if (!attr->valid)
 772                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 773         if (attr->ipv4) {
 774                 memset(&ipv4, 0, sizeof(ipv4));
 775                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 776                 ipv4.hdr.time_to_live = conf->ttl_value;
 777                 ipv4_mask.hdr.time_to_live = 0xFF;
 778                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 779                 item.spec = &ipv4;
 780                 item.mask = &ipv4_mask;
 781                 field = modify_ipv4;
 782         } else {
 783                 MLX5_ASSERT(attr->ipv6);
 784                 memset(&ipv6, 0, sizeof(ipv6));
 785                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 786                 ipv6.hdr.hop_limits = conf->ttl_value;
 787                 ipv6_mask.hdr.hop_limits = 0xFF;
 788                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 789                 item.spec = &ipv6;
 790                 item.mask = &ipv6_mask;
 791                 field = modify_ipv6;
 792         }
 793         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 794                                              MLX5_MODIFICATION_TYPE_SET, error);
 795 }
 796
 797 /**
 798  * Convert modify-header decrement TTL action to DV specification.
 799  *
 800  * @param[in,out] resource
 801  *   Pointer to the modify-header resource.
 802  * @param[in] action
 803  *   Pointer to action specification.
 804  * @param[in] items
 805  *   Pointer to rte_flow_item objects list.
 806  * @param[in] attr
 807  *   Pointer to flow attributes structure.
 808  * @param[in] dev_flow
 809  *   Pointer to the sub flow.
 810  * @param[in] tunnel_decap
 811  *   Whether action is after tunnel decapsulation.
 812  * @param[out] error
 813  *   Pointer to the error structure.
 814  *
 815  * @return
 816  *   0 on success, a negative errno value otherwise and rte_errno is set.
 817  */
 818 static int
 819 flow_dv_convert_action_modify_dec_ttl
 820                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 821                          const struct rte_flow_item *items,
 822                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 823                          bool tunnel_decap, struct rte_flow_error *error)
 824 {
 825         struct rte_flow_item item;
 826         struct rte_flow_item_ipv4 ipv4;
 827         struct rte_flow_item_ipv4 ipv4_mask;
 828         struct rte_flow_item_ipv6 ipv6;
 829         struct rte_flow_item_ipv6 ipv6_mask;
 830         struct field_modify_info *field;
 831
 832         if (!attr->valid)
 833                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 834         if (attr->ipv4) {
 835                 memset(&ipv4, 0, sizeof(ipv4));
 836                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 837                 ipv4.hdr.time_to_live = 0xFF;
 838                 ipv4_mask.hdr.time_to_live = 0xFF;
 839                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 840                 item.spec = &ipv4;
 841                 item.mask = &ipv4_mask;
 842                 field = modify_ipv4;
 843         } else {
 844                 MLX5_ASSERT(attr->ipv6);
 845                 memset(&ipv6, 0, sizeof(ipv6));
 846                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 847                 ipv6.hdr.hop_limits = 0xFF;
 848                 ipv6_mask.hdr.hop_limits = 0xFF;
 849                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 850                 item.spec = &ipv6;
 851                 item.mask = &ipv6_mask;
 852                 field = modify_ipv6;
 853         }
 854         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 855                                              MLX5_MODIFICATION_TYPE_ADD, error);
 856 }
 857
 858 /**
 859  * Convert modify-header increment/decrement TCP Sequence number
 860  * to DV specification.
 861  *
 862  * @param[in,out] resource
 863  *   Pointer to the modify-header resource.
 864  * @param[in] action
 865  *   Pointer to action specification.
 866  * @param[out] error
 867  *   Pointer to the error structure.
 868  *
 869  * @return
 870  *   0 on success, a negative errno value otherwise and rte_errno is set.
 871  */
 872 static int
 873 flow_dv_convert_action_modify_tcp_seq
 874                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 875                          const struct rte_flow_action *action,
 876                          struct rte_flow_error *error)
 877 {
 878         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 879         uint64_t value = rte_be_to_cpu_32(*conf);
 880         struct rte_flow_item item;
 881         struct rte_flow_item_tcp tcp;
 882         struct rte_flow_item_tcp tcp_mask;
 883
 884         memset(&tcp, 0, sizeof(tcp));
 885         memset(&tcp_mask, 0, sizeof(tcp_mask));
 886         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
 887                 /*
 888                  * The HW has no decrement operation, only increment operation.
 889                  * To simulate decrement X from Y using increment operation
 890                  * we need to add UINT32_MAX X times to Y.
 891                  * Each adding of UINT32_MAX decrements Y by 1.
 892                  */
 893                 value *= UINT32_MAX;
 894         tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
 895         tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
 896         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 897         item.spec = &tcp;
 898         item.mask = &tcp_mask;
 899         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 900                                              MLX5_MODIFICATION_TYPE_ADD, error);
 901 }
 902
 903 /**
 904  * Convert modify-header increment/decrement TCP Acknowledgment number
 905  * to DV specification.
 906  *
 907  * @param[in,out] resource
 908  *   Pointer to the modify-header resource.
 909  * @param[in] action
 910  *   Pointer to action specification.
 911  * @param[out] error
 912  *   Pointer to the error structure.
 913  *
 914  * @return
 915  *   0 on success, a negative errno value otherwise and rte_errno is set.
 916  */
 917 static int
 918 flow_dv_convert_action_modify_tcp_ack
 919                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 920                          const struct rte_flow_action *action,
 921                          struct rte_flow_error *error)
 922 {
 923         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 924         uint64_t value = rte_be_to_cpu_32(*conf);
 925         struct rte_flow_item item;
 926         struct rte_flow_item_tcp tcp;
 927         struct rte_flow_item_tcp tcp_mask;
 928
 929         memset(&tcp, 0, sizeof(tcp));
 930         memset(&tcp_mask, 0, sizeof(tcp_mask));
 931         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
 932                 /*
 933                  * The HW has no decrement operation, only increment operation.
 934                  * To simulate decrement X from Y using increment operation
 935                  * we need to add UINT32_MAX X times to Y.
 936                  * Each adding of UINT32_MAX decrements Y by 1.
 937                  */
 938                 value *= UINT32_MAX;
 939         tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
 940         tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
 941         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 942         item.spec = &tcp;
 943         item.mask = &tcp_mask;
 944         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 945                                              MLX5_MODIFICATION_TYPE_ADD, error);
 946 }
 947
 948 static enum mlx5_modification_field reg_to_field[] = {
 949         [REG_NONE] = MLX5_MODI_OUT_NONE,
 950         [REG_A] = MLX5_MODI_META_DATA_REG_A,
 951         [REG_B] = MLX5_MODI_META_DATA_REG_B,
 952         [REG_C_0] = MLX5_MODI_META_REG_C_0,
 953         [REG_C_1] = MLX5_MODI_META_REG_C_1,
 954         [REG_C_2] = MLX5_MODI_META_REG_C_2,
 955         [REG_C_3] = MLX5_MODI_META_REG_C_3,
 956         [REG_C_4] = MLX5_MODI_META_REG_C_4,
 957         [REG_C_5] = MLX5_MODI_META_REG_C_5,
 958         [REG_C_6] = MLX5_MODI_META_REG_C_6,
 959         [REG_C_7] = MLX5_MODI_META_REG_C_7,
 960 };
 961
 962 /**
 963  * Convert register set to DV specification.
 964  *
 965  * @param[in,out] resource
 966  *   Pointer to the modify-header resource.
 967  * @param[in] action
 968  *   Pointer to action specification.
 969  * @param[out] error
 970  *   Pointer to the error structure.
 971  *
 972  * @return
 973  *   0 on success, a negative errno value otherwise and rte_errno is set.
 974  */
 975 static int
 976 flow_dv_convert_action_set_reg
 977                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 978                          const struct rte_flow_action *action,
 979                          struct rte_flow_error *error)
 980 {
 981         const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
 982         struct mlx5_modification_cmd *actions = resource->actions;
 983         uint32_t i = resource->actions_num;
 984
 985         if (i >= MLX5_MAX_MODIFY_NUM)
 986                 return rte_flow_error_set(error, EINVAL,
 987                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 988                                           "too many items to modify");
 989         MLX5_ASSERT(conf->id != REG_NONE);
 990         MLX5_ASSERT(conf->id < RTE_DIM(reg_to_field));
 991         actions[i] = (struct mlx5_modification_cmd) {
 992                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 993                 .field = reg_to_field[conf->id],
 994         };
 995         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 996         actions[i].data1 = rte_cpu_to_be_32(conf->data);
 997         ++i;
 998         resource->actions_num = i;
 999         return 0;
1000 }
1001
1002 /**
1003  * Convert SET_TAG action to DV specification.
1004  *
1005  * @param[in] dev
1006  *   Pointer to the rte_eth_dev structure.
1007  * @param[in,out] resource
1008  *   Pointer to the modify-header resource.
1009  * @param[in] conf
1010  *   Pointer to action specification.
1011  * @param[out] error
1012  *   Pointer to the error structure.
1013  *
1014  * @return
1015  *   0 on success, a negative errno value otherwise and rte_errno is set.
1016  */
1017 static int
1018 flow_dv_convert_action_set_tag
1019                         (struct rte_eth_dev *dev,
1020                          struct mlx5_flow_dv_modify_hdr_resource *resource,
1021                          const struct rte_flow_action_set_tag *conf,
1022                          struct rte_flow_error *error)
1023 {
1024         rte_be32_t data = rte_cpu_to_be_32(conf->data);
1025         rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
1026         struct rte_flow_item item = {
1027                 .spec = &data,
1028                 .mask = &mask,
1029         };
1030         struct field_modify_info reg_c_x[] = {
1031                 [1] = {0, 0, 0},
1032         };
1033         enum mlx5_modification_field reg_type;
1034         int ret;
1035
1036         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1037         if (ret < 0)
1038                 return ret;
1039         MLX5_ASSERT(ret != REG_NONE);
1040         MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1041         reg_type = reg_to_field[ret];
1042         MLX5_ASSERT(reg_type > 0);
1043         reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1044         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1045                                              MLX5_MODIFICATION_TYPE_SET, error);
1046 }
1047
1048 /**
1049  * Convert internal COPY_REG action to DV specification.
1050  *
1051  * @param[in] dev
1052  *   Pointer to the rte_eth_dev structure.
1053  * @param[in,out] res
1054  *   Pointer to the modify-header resource.
1055  * @param[in] action
1056  *   Pointer to action specification.
1057  * @param[out] error
1058  *   Pointer to the error structure.
1059  *
1060  * @return
1061  *   0 on success, a negative errno value otherwise and rte_errno is set.
1062  */
1063 static int
1064 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1065                                  struct mlx5_flow_dv_modify_hdr_resource *res,
1066                                  const struct rte_flow_action *action,
1067                                  struct rte_flow_error *error)
1068 {
1069         const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1070         rte_be32_t mask = RTE_BE32(UINT32_MAX);
1071         struct rte_flow_item item = {
1072                 .spec = NULL,
1073                 .mask = &mask,
1074         };
1075         struct field_modify_info reg_src[] = {
1076                 {4, 0, reg_to_field[conf->src]},
1077                 {0, 0, 0},
1078         };
1079         struct field_modify_info reg_dst = {
1080                 .offset = 0,
1081                 .id = reg_to_field[conf->dst],
1082         };
1083         /* Adjust reg_c[0] usage according to reported mask. */
1084         if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1085                 struct mlx5_priv *priv = dev->data->dev_private;
1086                 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1087
1088                 MLX5_ASSERT(reg_c0);
1089                 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1090                 if (conf->dst == REG_C_0) {
1091                         /* Copy to reg_c[0], within mask only. */
1092                         reg_dst.offset = rte_bsf32(reg_c0);
1093                         /*
1094                          * Mask is ignoring the enianness, because
1095                          * there is no conversion in datapath.
1096                          */
1097 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1098                         /* Copy from destination lower bits to reg_c[0]. */
1099                         mask = reg_c0 >> reg_dst.offset;
1100 #else
1101                         /* Copy from destination upper bits to reg_c[0]. */
1102                         mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1103                                           rte_fls_u32(reg_c0));
1104 #endif
1105                 } else {
1106                         mask = rte_cpu_to_be_32(reg_c0);
1107 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1108                         /* Copy from reg_c[0] to destination lower bits. */
1109                         reg_dst.offset = 0;
1110 #else
1111                         /* Copy from reg_c[0] to destination upper bits. */
1112                         reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1113                                          (rte_fls_u32(reg_c0) -
1114                                           rte_bsf32(reg_c0));
1115 #endif
1116                 }
1117         }
1118         return flow_dv_convert_modify_action(&item,
1119                                              reg_src, &reg_dst, res,
1120                                              MLX5_MODIFICATION_TYPE_COPY,
1121                                              error);
1122 }
1123
1124 /**
1125  * Convert MARK action to DV specification. This routine is used
1126  * in extensive metadata only and requires metadata register to be
1127  * handled. In legacy mode hardware tag resource is engaged.
1128  *
1129  * @param[in] dev
1130  *   Pointer to the rte_eth_dev structure.
1131  * @param[in] conf
1132  *   Pointer to MARK action specification.
1133  * @param[in,out] resource
1134  *   Pointer to the modify-header resource.
1135  * @param[out] error
1136  *   Pointer to the error structure.
1137  *
1138  * @return
1139  *   0 on success, a negative errno value otherwise and rte_errno is set.
1140  */
1141 static int
1142 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1143                             const struct rte_flow_action_mark *conf,
1144                             struct mlx5_flow_dv_modify_hdr_resource *resource,
1145                             struct rte_flow_error *error)
1146 {
1147         struct mlx5_priv *priv = dev->data->dev_private;
1148         rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1149                                            priv->sh->dv_mark_mask);
1150         rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1151         struct rte_flow_item item = {
1152                 .spec = &data,
1153                 .mask = &mask,
1154         };
1155         struct field_modify_info reg_c_x[] = {
1156                 {4, 0, 0}, /* dynamic instead of MLX5_MODI_META_REG_C_1. */
1157                 {0, 0, 0},
1158         };
1159         int reg;
1160
1161         if (!mask)
1162                 return rte_flow_error_set(error, EINVAL,
1163                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1164                                           NULL, "zero mark action mask");
1165         reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1166         if (reg < 0)
1167                 return reg;
1168         MLX5_ASSERT(reg > 0);
1169         if (reg == REG_C_0) {
1170                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1171                 uint32_t shl_c0 = rte_bsf32(msk_c0);
1172
1173                 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1174                 mask = rte_cpu_to_be_32(mask) & msk_c0;
1175                 mask = rte_cpu_to_be_32(mask << shl_c0);
1176         }
1177         reg_c_x[0].id = reg_to_field[reg];
1178         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1179                                              MLX5_MODIFICATION_TYPE_SET, error);
1180 }
1181
1182 /**
1183  * Get metadata register index for specified steering domain.
1184  *
1185  * @param[in] dev
1186  *   Pointer to the rte_eth_dev structure.
1187  * @param[in] attr
1188  *   Attributes of flow to determine steering domain.
1189  * @param[out] error
1190  *   Pointer to the error structure.
1191  *
1192  * @return
1193  *   positive index on success, a negative errno value otherwise
1194  *   and rte_errno is set.
1195  */
1196 static enum modify_reg
1197 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1198                          const struct rte_flow_attr *attr,
1199                          struct rte_flow_error *error)
1200 {
1201         int reg =
1202                 mlx5_flow_get_reg_id(dev, attr->transfer ?
1203                                           MLX5_METADATA_FDB :
1204                                             attr->egress ?
1205                                             MLX5_METADATA_TX :
1206                                             MLX5_METADATA_RX, 0, error);
1207         if (reg < 0)
1208                 return rte_flow_error_set(error,
1209                                           ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1210                                           NULL, "unavailable "
1211                                           "metadata register");
1212         return reg;
1213 }
1214
1215 /**
1216  * Convert SET_META action to DV specification.
1217  *
1218  * @param[in] dev
1219  *   Pointer to the rte_eth_dev structure.
1220  * @param[in,out] resource
1221  *   Pointer to the modify-header resource.
1222  * @param[in] attr
1223  *   Attributes of flow that includes this item.
1224  * @param[in] conf
1225  *   Pointer to action specification.
1226  * @param[out] error
1227  *   Pointer to the error structure.
1228  *
1229  * @return
1230  *   0 on success, a negative errno value otherwise and rte_errno is set.
1231  */
1232 static int
1233 flow_dv_convert_action_set_meta
1234                         (struct rte_eth_dev *dev,
1235                          struct mlx5_flow_dv_modify_hdr_resource *resource,
1236                          const struct rte_flow_attr *attr,
1237                          const struct rte_flow_action_set_meta *conf,
1238                          struct rte_flow_error *error)
1239 {
1240         uint32_t data = conf->data;
1241         uint32_t mask = conf->mask;
1242         struct rte_flow_item item = {
1243                 .spec = &data,
1244                 .mask = &mask,
1245         };
1246         struct field_modify_info reg_c_x[] = {
1247                 [1] = {0, 0, 0},
1248         };
1249         int reg = flow_dv_get_metadata_reg(dev, attr, error);
1250
1251         if (reg < 0)
1252                 return reg;
1253         /*
1254          * In datapath code there is no endianness
1255          * coversions for perfromance reasons, all
1256          * pattern conversions are done in rte_flow.
1257          */
1258         if (reg == REG_C_0) {
1259                 struct mlx5_priv *priv = dev->data->dev_private;
1260                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1261                 uint32_t shl_c0;
1262
1263                 MLX5_ASSERT(msk_c0);
1264 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1265                 shl_c0 = rte_bsf32(msk_c0);
1266 #else
1267                 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1268 #endif
1269                 mask <<= shl_c0;
1270                 data <<= shl_c0;
1271                 MLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1272         }
1273         reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1274         /* The routine expects parameters in memory as big-endian ones. */
1275         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1276                                              MLX5_MODIFICATION_TYPE_SET, error);
1277 }
1278
1279 /**
1280  * Convert modify-header set IPv4 DSCP action to DV specification.
1281  *
1282  * @param[in,out] resource
1283  *   Pointer to the modify-header resource.
1284  * @param[in] action
1285  *   Pointer to action specification.
1286  * @param[out] error
1287  *   Pointer to the error structure.
1288  *
1289  * @return
1290  *   0 on success, a negative errno value otherwise and rte_errno is set.
1291  */
1292 static int
1293 flow_dv_convert_action_modify_ipv4_dscp
1294                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1295                          const struct rte_flow_action *action,
1296                          struct rte_flow_error *error)
1297 {
1298         const struct rte_flow_action_set_dscp *conf =
1299                 (const struct rte_flow_action_set_dscp *)(action->conf);
1300         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1301         struct rte_flow_item_ipv4 ipv4;
1302         struct rte_flow_item_ipv4 ipv4_mask;
1303
1304         memset(&ipv4, 0, sizeof(ipv4));
1305         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1306         ipv4.hdr.type_of_service = conf->dscp;
1307         ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1308         item.spec = &ipv4;
1309         item.mask = &ipv4_mask;
1310         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1311                                              MLX5_MODIFICATION_TYPE_SET, error);
1312 }
1313
1314 /**
1315  * Convert modify-header set IPv6 DSCP action to DV specification.
1316  *
1317  * @param[in,out] resource
1318  *   Pointer to the modify-header resource.
1319  * @param[in] action
1320  *   Pointer to action specification.
1321  * @param[out] error
1322  *   Pointer to the error structure.
1323  *
1324  * @return
1325  *   0 on success, a negative errno value otherwise and rte_errno is set.
1326  */
1327 static int
1328 flow_dv_convert_action_modify_ipv6_dscp
1329                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1330                          const struct rte_flow_action *action,
1331                          struct rte_flow_error *error)
1332 {
1333         const struct rte_flow_action_set_dscp *conf =
1334                 (const struct rte_flow_action_set_dscp *)(action->conf);
1335         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1336         struct rte_flow_item_ipv6 ipv6;
1337         struct rte_flow_item_ipv6 ipv6_mask;
1338
1339         memset(&ipv6, 0, sizeof(ipv6));
1340         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1341         /*
1342          * Even though the DSCP bits offset of IPv6 is not byte aligned,
1343          * rdma-core only accept the DSCP bits byte aligned start from
1344          * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1345          * bits in IPv6 case as rdma-core requires byte aligned value.
1346          */
1347         ipv6.hdr.vtc_flow = conf->dscp;
1348         ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1349         item.spec = &ipv6;
1350         item.mask = &ipv6_mask;
1351         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1352                                              MLX5_MODIFICATION_TYPE_SET, error);
1353 }
1354
1355 /**
1356  * Validate MARK item.
1357  *
1358  * @param[in] dev
1359  *   Pointer to the rte_eth_dev structure.
1360  * @param[in] item
1361  *   Item specification.
1362  * @param[in] attr
1363  *   Attributes of flow that includes this item.
1364  * @param[out] error
1365  *   Pointer to error structure.
1366  *
1367  * @return
1368  *   0 on success, a negative errno value otherwise and rte_errno is set.
1369  */
1370 static int
1371 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1372                            const struct rte_flow_item *item,
1373                            const struct rte_flow_attr *attr __rte_unused,
1374                            struct rte_flow_error *error)
1375 {
1376         struct mlx5_priv *priv = dev->data->dev_private;
1377         struct mlx5_dev_config *config = &priv->config;
1378         const struct rte_flow_item_mark *spec = item->spec;
1379         const struct rte_flow_item_mark *mask = item->mask;
1380         const struct rte_flow_item_mark nic_mask = {
1381                 .id = priv->sh->dv_mark_mask,
1382         };
1383         int ret;
1384
1385         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1386                 return rte_flow_error_set(error, ENOTSUP,
1387                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1388                                           "extended metadata feature"
1389                                           " isn't enabled");
1390         if (!mlx5_flow_ext_mreg_supported(dev))
1391                 return rte_flow_error_set(error, ENOTSUP,
1392                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1393                                           "extended metadata register"
1394                                           " isn't supported");
1395         if (!nic_mask.id)
1396                 return rte_flow_error_set(error, ENOTSUP,
1397                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1398                                           "extended metadata register"
1399                                           " isn't available");
1400         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1401         if (ret < 0)
1402                 return ret;
1403         if (!spec)
1404                 return rte_flow_error_set(error, EINVAL,
1405                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1406                                           item->spec,
1407                                           "data cannot be empty");
1408         if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1409                 return rte_flow_error_set(error, EINVAL,
1410                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1411                                           &spec->id,
1412                                           "mark id exceeds the limit");
1413         if (!mask)
1414                 mask = &nic_mask;
1415         if (!mask->id)
1416                 return rte_flow_error_set(error, EINVAL,
1417                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1418                                         "mask cannot be zero");
1419
1420         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1421                                         (const uint8_t *)&nic_mask,
1422                                         sizeof(struct rte_flow_item_mark),
1423                                         error);
1424         if (ret < 0)
1425                 return ret;
1426         return 0;
1427 }
1428
1429 /**
1430  * Validate META item.
1431  *
1432  * @param[in] dev
1433  *   Pointer to the rte_eth_dev structure.
1434  * @param[in] item
1435  *   Item specification.
1436  * @param[in] attr
1437  *   Attributes of flow that includes this item.
1438  * @param[out] error
1439  *   Pointer to error structure.
1440  *
1441  * @return
1442  *   0 on success, a negative errno value otherwise and rte_errno is set.
1443  */
1444 static int
1445 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1446                            const struct rte_flow_item *item,
1447                            const struct rte_flow_attr *attr,
1448                            struct rte_flow_error *error)
1449 {
1450         struct mlx5_priv *priv = dev->data->dev_private;
1451         struct mlx5_dev_config *config = &priv->config;
1452         const struct rte_flow_item_meta *spec = item->spec;
1453         const struct rte_flow_item_meta *mask = item->mask;
1454         struct rte_flow_item_meta nic_mask = {
1455                 .data = UINT32_MAX
1456         };
1457         int reg;
1458         int ret;
1459
1460         if (!spec)
1461                 return rte_flow_error_set(error, EINVAL,
1462                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1463                                           item->spec,
1464                                           "data cannot be empty");
1465         if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1466                 if (!mlx5_flow_ext_mreg_supported(dev))
1467                         return rte_flow_error_set(error, ENOTSUP,
1468                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1469                                           "extended metadata register"
1470                                           " isn't supported");
1471                 reg = flow_dv_get_metadata_reg(dev, attr, error);
1472                 if (reg < 0)
1473                         return reg;
1474                 if (reg == REG_B)
1475                         return rte_flow_error_set(error, ENOTSUP,
1476                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1477                                           "match on reg_b "
1478                                           "isn't supported");
1479                 if (reg != REG_A)
1480                         nic_mask.data = priv->sh->dv_meta_mask;
1481         }
1482         if (!mask)
1483                 mask = &rte_flow_item_meta_mask;
1484         if (!mask->data)
1485                 return rte_flow_error_set(error, EINVAL,
1486                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1487                                         "mask cannot be zero");
1488
1489         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1490                                         (const uint8_t *)&nic_mask,
1491                                         sizeof(struct rte_flow_item_meta),
1492                                         error);
1493         return ret;
1494 }
1495
1496 /**
1497  * Validate TAG item.
1498  *
1499  * @param[in] dev
1500  *   Pointer to the rte_eth_dev structure.
1501  * @param[in] item
1502  *   Item specification.
1503  * @param[in] attr
1504  *   Attributes of flow that includes this item.
1505  * @param[out] error
1506  *   Pointer to error structure.
1507  *
1508  * @return
1509  *   0 on success, a negative errno value otherwise and rte_errno is set.
1510  */
1511 static int
1512 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
1513                           const struct rte_flow_item *item,
1514                           const struct rte_flow_attr *attr __rte_unused,
1515                           struct rte_flow_error *error)
1516 {
1517         const struct rte_flow_item_tag *spec = item->spec;
1518         const struct rte_flow_item_tag *mask = item->mask;
1519         const struct rte_flow_item_tag nic_mask = {
1520                 .data = RTE_BE32(UINT32_MAX),
1521                 .index = 0xff,
1522         };
1523         int ret;
1524
1525         if (!mlx5_flow_ext_mreg_supported(dev))
1526                 return rte_flow_error_set(error, ENOTSUP,
1527                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1528                                           "extensive metadata register"
1529                                           " isn't supported");
1530         if (!spec)
1531                 return rte_flow_error_set(error, EINVAL,
1532                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1533                                           item->spec,
1534                                           "data cannot be empty");
1535         if (!mask)
1536                 mask = &rte_flow_item_tag_mask;
1537         if (!mask->data)
1538                 return rte_flow_error_set(error, EINVAL,
1539                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1540                                         "mask cannot be zero");
1541
1542         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1543                                         (const uint8_t *)&nic_mask,
1544                                         sizeof(struct rte_flow_item_tag),
1545                                         error);
1546         if (ret < 0)
1547                 return ret;
1548         if (mask->index != 0xff)
1549                 return rte_flow_error_set(error, EINVAL,
1550                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1551                                           "partial mask for tag index"
1552                                           " is not supported");
1553         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
1554         if (ret < 0)
1555                 return ret;
1556         MLX5_ASSERT(ret != REG_NONE);
1557         return 0;
1558 }
1559
1560 /**
1561  * Validate vport item.
1562  *
1563  * @param[in] dev
1564  *   Pointer to the rte_eth_dev structure.
1565  * @param[in] item
1566  *   Item specification.
1567  * @param[in] attr
1568  *   Attributes of flow that includes this item.
1569  * @param[in] item_flags
1570  *   Bit-fields that holds the items detected until now.
1571  * @param[out] error
1572  *   Pointer to error structure.
1573  *
1574  * @return
1575  *   0 on success, a negative errno value otherwise and rte_errno is set.
1576  */
1577 static int
1578 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
1579                               const struct rte_flow_item *item,
1580                               const struct rte_flow_attr *attr,
1581                               uint64_t item_flags,
1582                               struct rte_flow_error *error)
1583 {
1584         const struct rte_flow_item_port_id *spec = item->spec;
1585         const struct rte_flow_item_port_id *mask = item->mask;
1586         const struct rte_flow_item_port_id switch_mask = {
1587                         .id = 0xffffffff,
1588         };
1589         struct mlx5_priv *esw_priv;
1590         struct mlx5_priv *dev_priv;
1591         int ret;
1592
1593         if (!attr->transfer)
1594                 return rte_flow_error_set(error, EINVAL,
1595                                           RTE_FLOW_ERROR_TYPE_ITEM,
1596                                           NULL,
1597                                           "match on port id is valid only"
1598                                           " when transfer flag is enabled");
1599         if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
1600                 return rte_flow_error_set(error, ENOTSUP,
1601                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1602                                           "multiple source ports are not"
1603                                           " supported");
1604         if (!mask)
1605                 mask = &switch_mask;
1606         if (mask->id != 0xffffffff)
1607                 return rte_flow_error_set(error, ENOTSUP,
1608                                            RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1609                                            mask,
1610                                            "no support for partial mask on"
1611                                            " \"id\" field");
1612         ret = mlx5_flow_item_acceptable
1613                                 (item, (const uint8_t *)mask,
1614                                  (const uint8_t *)&rte_flow_item_port_id_mask,
1615                                  sizeof(struct rte_flow_item_port_id),
1616                                  error);
1617         if (ret)
1618                 return ret;
1619         if (!spec)
1620                 return 0;
1621         esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
1622         if (!esw_priv)
1623                 return rte_flow_error_set(error, rte_errno,
1624                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1625                                           "failed to obtain E-Switch info for"
1626                                           " port");
1627         dev_priv = mlx5_dev_to_eswitch_info(dev);
1628         if (!dev_priv)
1629                 return rte_flow_error_set(error, rte_errno,
1630                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1631                                           NULL,
1632                                           "failed to obtain E-Switch info");
1633         if (esw_priv->domain_id != dev_priv->domain_id)
1634                 return rte_flow_error_set(error, EINVAL,
1635                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1636                                           "cannot match on a port from a"
1637                                           " different E-Switch");
1638         return 0;
1639 }
1640
1641 /**
1642  * Validate GTP item.
1643  *
1644  * @param[in] dev
1645  *   Pointer to the rte_eth_dev structure.
1646  * @param[in] item
1647  *   Item specification.
1648  * @param[in] item_flags
1649  *   Bit-fields that holds the items detected until now.
1650  * @param[out] error
1651  *   Pointer to error structure.
1652  *
1653  * @return
1654  *   0 on success, a negative errno value otherwise and rte_errno is set.
1655  */
1656 static int
1657 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
1658                           const struct rte_flow_item *item,
1659                           uint64_t item_flags,
1660                           struct rte_flow_error *error)
1661 {
1662         struct mlx5_priv *priv = dev->data->dev_private;
1663         const struct rte_flow_item_gtp *mask = item->mask;
1664         const struct rte_flow_item_gtp nic_mask = {
1665                 .msg_type = 0xff,
1666                 .teid = RTE_BE32(0xffffffff),
1667         };
1668
1669         if (!priv->config.hca_attr.tunnel_stateless_gtp)
1670                 return rte_flow_error_set(error, ENOTSUP,
1671                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1672                                           "GTP support is not enabled");
1673         if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
1674                 return rte_flow_error_set(error, ENOTSUP,
1675                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1676                                           "multiple tunnel layers not"
1677                                           " supported");
1678         if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
1679                 return rte_flow_error_set(error, EINVAL,
1680                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1681                                           "no outer UDP layer found");
1682         if (!mask)
1683                 mask = &rte_flow_item_gtp_mask;
1684         return mlx5_flow_item_acceptable
1685                 (item, (const uint8_t *)mask,
1686                  (const uint8_t *)&nic_mask,
1687                  sizeof(struct rte_flow_item_gtp),
1688                  error);
1689 }
1690
1691 /**
1692  * Validate the pop VLAN action.
1693  *
1694  * @param[in] dev
1695  *   Pointer to the rte_eth_dev structure.
1696  * @param[in] action_flags
1697  *   Holds the actions detected until now.
1698  * @param[in] action
1699  *   Pointer to the pop vlan action.
1700  * @param[in] item_flags
1701  *   The items found in this flow rule.
1702  * @param[in] attr
1703  *   Pointer to flow attributes.
1704  * @param[out] error
1705  *   Pointer to error structure.
1706  *
1707  * @return
1708  *   0 on success, a negative errno value otherwise and rte_errno is set.
1709  */
1710 static int
1711 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
1712                                  uint64_t action_flags,
1713                                  const struct rte_flow_action *action,
1714                                  uint64_t item_flags,
1715                                  const struct rte_flow_attr *attr,
1716                                  struct rte_flow_error *error)
1717 {
1718         const struct mlx5_priv *priv = dev->data->dev_private;
1719
1720         (void)action;
1721         (void)attr;
1722         if (!priv->sh->pop_vlan_action)
1723                 return rte_flow_error_set(error, ENOTSUP,
1724                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1725                                           NULL,
1726                                           "pop vlan action is not supported");
1727         if (attr->egress)
1728                 return rte_flow_error_set(error, ENOTSUP,
1729                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1730                                           NULL,
1731                                           "pop vlan action not supported for "
1732                                           "egress");
1733         if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
1734                 return rte_flow_error_set(error, ENOTSUP,
1735                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1736                                           "no support for multiple VLAN "
1737                                           "actions");
1738         if (!(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1739                 return rte_flow_error_set(error, ENOTSUP,
1740                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1741                                           NULL,
1742                                           "cannot pop vlan without a "
1743                                           "match on (outer) vlan in the flow");
1744         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1745                 return rte_flow_error_set(error, EINVAL,
1746                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1747                                           "wrong action order, port_id should "
1748                                           "be after pop VLAN action");
1749         if (!attr->transfer && priv->representor)
1750                 return rte_flow_error_set(error, ENOTSUP,
1751                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1752                                           "pop vlan action for VF representor "
1753                                           "not supported on NIC table");
1754         return 0;
1755 }
1756
1757 /**
1758  * Get VLAN default info from vlan match info.
1759  *
1760  * @param[in] items
1761  *   the list of item specifications.
1762  * @param[out] vlan
1763  *   pointer VLAN info to fill to.
1764  *
1765  * @return
1766  *   0 on success, a negative errno value otherwise and rte_errno is set.
1767  */
1768 static void
1769 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
1770                                   struct rte_vlan_hdr *vlan)
1771 {
1772         const struct rte_flow_item_vlan nic_mask = {
1773                 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
1774                                 MLX5DV_FLOW_VLAN_VID_MASK),
1775                 .inner_type = RTE_BE16(0xffff),
1776         };
1777
1778         if (items == NULL)
1779                 return;
1780         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
1781                 int type = items->type;
1782
1783                 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
1784                     type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
1785                         break;
1786         }
1787         if (items->type != RTE_FLOW_ITEM_TYPE_END) {
1788                 const struct rte_flow_item_vlan *vlan_m = items->mask;
1789                 const struct rte_flow_item_vlan *vlan_v = items->spec;
1790
1791                 if (!vlan_m)
1792                         vlan_m = &nic_mask;
1793                 /* Only full match values are accepted */
1794                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
1795                      MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
1796                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
1797                         vlan->vlan_tci |=
1798                                 rte_be_to_cpu_16(vlan_v->tci &
1799                                                  MLX5DV_FLOW_VLAN_PCP_MASK_BE);
1800                 }
1801                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
1802                      MLX5DV_FLOW_VLAN_VID_MASK_BE) {
1803                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
1804                         vlan->vlan_tci |=
1805                                 rte_be_to_cpu_16(vlan_v->tci &
1806                                                  MLX5DV_FLOW_VLAN_VID_MASK_BE);
1807                 }
1808                 if (vlan_m->inner_type == nic_mask.inner_type)
1809                         vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
1810                                                            vlan_m->inner_type);
1811         }
1812 }
1813
1814 /**
1815  * Validate the push VLAN action.
1816  *
1817  * @param[in] dev
1818  *   Pointer to the rte_eth_dev structure.
1819  * @param[in] action_flags
1820  *   Holds the actions detected until now.
1821  * @param[in] item_flags
1822  *   The items found in this flow rule.
1823  * @param[in] action
1824  *   Pointer to the action structure.
1825  * @param[in] attr
1826  *   Pointer to flow attributes
1827  * @param[out] error
1828  *   Pointer to error structure.
1829  *
1830  * @return
1831  *   0 on success, a negative errno value otherwise and rte_errno is set.
1832  */
1833 static int
1834 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
1835                                   uint64_t action_flags,
1836                                   const struct rte_flow_item_vlan *vlan_m,
1837                                   const struct rte_flow_action *action,
1838                                   const struct rte_flow_attr *attr,
1839                                   struct rte_flow_error *error)
1840 {
1841         const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
1842         const struct mlx5_priv *priv = dev->data->dev_private;
1843
1844         if (!attr->transfer && attr->ingress)
1845                 return rte_flow_error_set(error, ENOTSUP,
1846                                           RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1847                                           NULL,
1848                                           "push VLAN action not supported for "
1849                                           "ingress");
1850         if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
1851             push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
1852                 return rte_flow_error_set(error, EINVAL,
1853                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1854                                           "invalid vlan ethertype");
1855         if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
1856                 return rte_flow_error_set(error, ENOTSUP,
1857                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1858                                           "no support for multiple VLAN "
1859                                           "actions");
1860         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1861                 return rte_flow_error_set(error, EINVAL,
1862                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1863                                           "wrong action order, port_id should "
1864                                           "be after push VLAN");
1865         if (!attr->transfer && priv->representor)
1866                 return rte_flow_error_set(error, ENOTSUP,
1867                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1868                                           "push vlan action for VF representor "
1869                                           "not supported on NIC table");
1870         if (vlan_m &&
1871             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
1872             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
1873                 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
1874             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
1875             !(mlx5_flow_find_action
1876                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
1877                 return rte_flow_error_set(error, EINVAL,
1878                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1879                                           "not full match mask on VLAN PCP and "
1880                                           "there is no of_set_vlan_pcp action, "
1881                                           "push VLAN action cannot figure out "
1882                                           "PCP value");
1883         if (vlan_m &&
1884             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
1885             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
1886                 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
1887             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
1888             !(mlx5_flow_find_action
1889                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
1890                 return rte_flow_error_set(error, EINVAL,
1891                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1892                                           "not full match mask on VLAN VID and "
1893                                           "there is no of_set_vlan_vid action, "
1894                                           "push VLAN action cannot figure out "
1895                                           "VID value");
1896         (void)attr;
1897         return 0;
1898 }
1899
1900 /**
1901  * Validate the set VLAN PCP.
1902  *
1903  * @param[in] action_flags
1904  *   Holds the actions detected until now.
1905  * @param[in] actions
1906  *   Pointer to the list of actions remaining in the flow rule.
1907  * @param[out] error
1908  *   Pointer to error structure.
1909  *
1910  * @return
1911  *   0 on success, a negative errno value otherwise and rte_errno is set.
1912  */
1913 static int
1914 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
1915                                      const struct rte_flow_action actions[],
1916                                      struct rte_flow_error *error)
1917 {
1918         const struct rte_flow_action *action = actions;
1919         const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
1920
1921         if (conf->vlan_pcp > 7)
1922                 return rte_flow_error_set(error, EINVAL,
1923                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1924                                           "VLAN PCP value is too big");
1925         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
1926                 return rte_flow_error_set(error, ENOTSUP,
1927                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1928                                           "set VLAN PCP action must follow "
1929                                           "the push VLAN action");
1930         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
1931                 return rte_flow_error_set(error, ENOTSUP,
1932                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1933                                           "Multiple VLAN PCP modification are "
1934                                           "not supported");
1935         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1936                 return rte_flow_error_set(error, EINVAL,
1937                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1938                                           "wrong action order, port_id should "
1939                                           "be after set VLAN PCP");
1940         return 0;
1941 }
1942
1943 /**
1944  * Validate the set VLAN VID.
1945  *
1946  * @param[in] item_flags
1947  *   Holds the items detected in this rule.
1948  * @param[in] action_flags
1949  *   Holds the actions detected until now.
1950  * @param[in] actions
1951  *   Pointer to the list of actions remaining in the flow rule.
1952  * @param[out] error
1953  *   Pointer to error structure.
1954  *
1955  * @return
1956  *   0 on success, a negative errno value otherwise and rte_errno is set.
1957  */
1958 static int
1959 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
1960                                      uint64_t action_flags,
1961                                      const struct rte_flow_action actions[],
1962                                      struct rte_flow_error *error)
1963 {
1964         const struct rte_flow_action *action = actions;
1965         const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
1966
1967         if (conf->vlan_vid > RTE_BE16(0xFFE))
1968                 return rte_flow_error_set(error, EINVAL,
1969                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1970                                           "VLAN VID value is too big");
1971         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
1972             !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1973                 return rte_flow_error_set(error, ENOTSUP,
1974                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1975                                           "set VLAN VID action must follow push"
1976                                           " VLAN action or match on VLAN item");
1977         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
1978                 return rte_flow_error_set(error, ENOTSUP,
1979                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1980                                           "Multiple VLAN VID modifications are "
1981                                           "not supported");
1982         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1983                 return rte_flow_error_set(error, EINVAL,
1984                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1985                                           "wrong action order, port_id should "
1986                                           "be after set VLAN VID");
1987         return 0;
1988 }
1989
1990 /*
1991  * Validate the FLAG action.
1992  *
1993  * @param[in] dev
1994  *   Pointer to the rte_eth_dev structure.
1995  * @param[in] action_flags
1996  *   Holds the actions detected until now.
1997  * @param[in] attr
1998  *   Pointer to flow attributes
1999  * @param[out] error
2000  *   Pointer to error structure.
2001  *
2002  * @return
2003  *   0 on success, a negative errno value otherwise and rte_errno is set.
2004  */
2005 static int
2006 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
2007                              uint64_t action_flags,
2008                              const struct rte_flow_attr *attr,
2009                              struct rte_flow_error *error)
2010 {
2011         struct mlx5_priv *priv = dev->data->dev_private;
2012         struct mlx5_dev_config *config = &priv->config;
2013         int ret;
2014
2015         /* Fall back if no extended metadata register support. */
2016         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2017                 return mlx5_flow_validate_action_flag(action_flags, attr,
2018                                                       error);
2019         /* Extensive metadata mode requires registers. */
2020         if (!mlx5_flow_ext_mreg_supported(dev))
2021                 return rte_flow_error_set(error, ENOTSUP,
2022                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2023                                           "no metadata registers "
2024                                           "to support flag action");
2025         if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
2026                 return rte_flow_error_set(error, ENOTSUP,
2027                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2028                                           "extended metadata register"
2029                                           " isn't available");
2030         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2031         if (ret < 0)
2032                 return ret;
2033         MLX5_ASSERT(ret > 0);
2034         if (action_flags & MLX5_FLOW_ACTION_MARK)
2035                 return rte_flow_error_set(error, EINVAL,
2036                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2037                                           "can't mark and flag in same flow");
2038         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2039                 return rte_flow_error_set(error, EINVAL,
2040                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2041                                           "can't have 2 flag"
2042                                           " actions in same flow");
2043         return 0;
2044 }
2045
2046 /**
2047  * Validate MARK action.
2048  *
2049  * @param[in] dev
2050  *   Pointer to the rte_eth_dev structure.
2051  * @param[in] action
2052  *   Pointer to action.
2053  * @param[in] action_flags
2054  *   Holds the actions detected until now.
2055  * @param[in] attr
2056  *   Pointer to flow attributes
2057  * @param[out] error
2058  *   Pointer to error structure.
2059  *
2060  * @return
2061  *   0 on success, a negative errno value otherwise and rte_errno is set.
2062  */
2063 static int
2064 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
2065                              const struct rte_flow_action *action,
2066                              uint64_t action_flags,
2067                              const struct rte_flow_attr *attr,
2068                              struct rte_flow_error *error)
2069 {
2070         struct mlx5_priv *priv = dev->data->dev_private;
2071         struct mlx5_dev_config *config = &priv->config;
2072         const struct rte_flow_action_mark *mark = action->conf;
2073         int ret;
2074
2075         /* Fall back if no extended metadata register support. */
2076         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2077                 return mlx5_flow_validate_action_mark(action, action_flags,
2078                                                       attr, error);
2079         /* Extensive metadata mode requires registers. */
2080         if (!mlx5_flow_ext_mreg_supported(dev))
2081                 return rte_flow_error_set(error, ENOTSUP,
2082                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2083                                           "no metadata registers "
2084                                           "to support mark action");
2085         if (!priv->sh->dv_mark_mask)
2086                 return rte_flow_error_set(error, ENOTSUP,
2087                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2088                                           "extended metadata register"
2089                                           " isn't available");
2090         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2091         if (ret < 0)
2092                 return ret;
2093         MLX5_ASSERT(ret > 0);
2094         if (!mark)
2095                 return rte_flow_error_set(error, EINVAL,
2096                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2097                                           "configuration cannot be null");
2098         if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
2099                 return rte_flow_error_set(error, EINVAL,
2100                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2101                                           &mark->id,
2102                                           "mark id exceeds the limit");
2103         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2104                 return rte_flow_error_set(error, EINVAL,
2105                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2106                                           "can't flag and mark in same flow");
2107         if (action_flags & MLX5_FLOW_ACTION_MARK)
2108                 return rte_flow_error_set(error, EINVAL,
2109                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2110                                           "can't have 2 mark actions in same"
2111                                           " flow");
2112         return 0;
2113 }
2114
2115 /**
2116  * Validate SET_META action.
2117  *
2118  * @param[in] dev
2119  *   Pointer to the rte_eth_dev structure.
2120  * @param[in] action
2121  *   Pointer to the action structure.
2122  * @param[in] action_flags
2123  *   Holds the actions detected until now.
2124  * @param[in] attr
2125  *   Pointer to flow attributes
2126  * @param[out] error
2127  *   Pointer to error structure.
2128  *
2129  * @return
2130  *   0 on success, a negative errno value otherwise and rte_errno is set.
2131  */
2132 static int
2133 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
2134                                  const struct rte_flow_action *action,
2135                                  uint64_t action_flags __rte_unused,
2136                                  const struct rte_flow_attr *attr,
2137                                  struct rte_flow_error *error)
2138 {
2139         const struct rte_flow_action_set_meta *conf;
2140         uint32_t nic_mask = UINT32_MAX;
2141         int reg;
2142
2143         if (!mlx5_flow_ext_mreg_supported(dev))
2144                 return rte_flow_error_set(error, ENOTSUP,
2145                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2146                                           "extended metadata register"
2147                                           " isn't supported");
2148         reg = flow_dv_get_metadata_reg(dev, attr, error);
2149         if (reg < 0)
2150                 return reg;
2151         if (reg != REG_A && reg != REG_B) {
2152                 struct mlx5_priv *priv = dev->data->dev_private;
2153
2154                 nic_mask = priv->sh->dv_meta_mask;
2155         }
2156         if (!(action->conf))
2157                 return rte_flow_error_set(error, EINVAL,
2158                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2159                                           "configuration cannot be null");
2160         conf = (const struct rte_flow_action_set_meta *)action->conf;
2161         if (!conf->mask)
2162                 return rte_flow_error_set(error, EINVAL,
2163                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2164                                           "zero mask doesn't have any effect");
2165         if (conf->mask & ~nic_mask)
2166                 return rte_flow_error_set(error, EINVAL,
2167                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2168                                           "meta data must be within reg C0");
2169         return 0;
2170 }
2171
2172 /**
2173  * Validate SET_TAG action.
2174  *
2175  * @param[in] dev
2176  *   Pointer to the rte_eth_dev structure.
2177  * @param[in] action
2178  *   Pointer to the action structure.
2179  * @param[in] action_flags
2180  *   Holds the actions detected until now.
2181  * @param[in] attr
2182  *   Pointer to flow attributes
2183  * @param[out] error
2184  *   Pointer to error structure.
2185  *
2186  * @return
2187  *   0 on success, a negative errno value otherwise and rte_errno is set.
2188  */
2189 static int
2190 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
2191                                 const struct rte_flow_action *action,
2192                                 uint64_t action_flags,
2193                                 const struct rte_flow_attr *attr,
2194                                 struct rte_flow_error *error)
2195 {
2196         const struct rte_flow_action_set_tag *conf;
2197         const uint64_t terminal_action_flags =
2198                 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
2199                 MLX5_FLOW_ACTION_RSS;
2200         int ret;
2201
2202         if (!mlx5_flow_ext_mreg_supported(dev))
2203                 return rte_flow_error_set(error, ENOTSUP,
2204                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2205                                           "extensive metadata register"
2206                                           " isn't supported");
2207         if (!(action->conf))
2208                 return rte_flow_error_set(error, EINVAL,
2209                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2210                                           "configuration cannot be null");
2211         conf = (const struct rte_flow_action_set_tag *)action->conf;
2212         if (!conf->mask)
2213                 return rte_flow_error_set(error, EINVAL,
2214                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2215                                           "zero mask doesn't have any effect");
2216         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
2217         if (ret < 0)
2218                 return ret;
2219         if (!attr->transfer && attr->ingress &&
2220             (action_flags & terminal_action_flags))
2221                 return rte_flow_error_set(error, EINVAL,
2222                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2223                                           "set_tag has no effect"
2224                                           " with terminal actions");
2225         return 0;
2226 }
2227
2228 /**
2229  * Validate count action.
2230  *
2231  * @param[in] dev
2232  *   Pointer to rte_eth_dev structure.
2233  * @param[out] error
2234  *   Pointer to error structure.
2235  *
2236  * @return
2237  *   0 on success, a negative errno value otherwise and rte_errno is set.
2238  */
2239 static int
2240 flow_dv_validate_action_count(struct rte_eth_dev *dev,
2241                               struct rte_flow_error *error)
2242 {
2243         struct mlx5_priv *priv = dev->data->dev_private;
2244
2245         if (!priv->config.devx)
2246                 goto notsup_err;
2247 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
2248         return 0;
2249 #endif
2250 notsup_err:
2251         return rte_flow_error_set
2252                       (error, ENOTSUP,
2253                        RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2254                        NULL,
2255                        "count action not supported");
2256 }
2257
2258 /**
2259  * Validate the L2 encap action.
2260  *
2261  * @param[in] dev
2262  *   Pointer to the rte_eth_dev structure.
2263  * @param[in] action_flags
2264  *   Holds the actions detected until now.
2265  * @param[in] action
2266  *   Pointer to the action structure.
2267  * @param[in] attr
2268  *   Pointer to flow attributes.
2269  * @param[out] error
2270  *   Pointer to error structure.
2271  *
2272  * @return
2273  *   0 on success, a negative errno value otherwise and rte_errno is set.
2274  */
2275 static int
2276 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
2277                                  uint64_t action_flags,
2278                                  const struct rte_flow_action *action,
2279                                  const struct rte_flow_attr *attr,
2280                                  struct rte_flow_error *error)
2281 {
2282         const struct mlx5_priv *priv = dev->data->dev_private;
2283
2284         if (!(action->conf))
2285                 return rte_flow_error_set(error, EINVAL,
2286                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2287                                           "configuration cannot be null");
2288         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
2289                 return rte_flow_error_set(error, EINVAL,
2290                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2291                                           "can only have a single encap action "
2292                                           "in a flow");
2293         if (!attr->transfer && priv->representor)
2294                 return rte_flow_error_set(error, ENOTSUP,
2295                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2296                                           "encap action for VF representor "
2297                                           "not supported on NIC table");
2298         return 0;
2299 }
2300
2301 /**
2302  * Validate a decap action.
2303  *
2304  * @param[in] dev
2305  *   Pointer to the rte_eth_dev structure.
2306  * @param[in] action_flags
2307  *   Holds the actions detected until now.
2308  * @param[in] attr
2309  *   Pointer to flow attributes
2310  * @param[out] error
2311  *   Pointer to error structure.
2312  *
2313  * @return
2314  *   0 on success, a negative errno value otherwise and rte_errno is set.
2315  */
2316 static int
2317 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
2318                               uint64_t action_flags,
2319                               const struct rte_flow_attr *attr,
2320                               struct rte_flow_error *error)
2321 {
2322         const struct mlx5_priv *priv = dev->data->dev_private;
2323
2324         if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
2325                 return rte_flow_error_set(error, ENOTSUP,
2326                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2327                                           action_flags &
2328                                           MLX5_FLOW_ACTION_DECAP ? "can only "
2329                                           "have a single decap action" : "decap "
2330                                           "after encap is not supported");
2331         if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
2332                 return rte_flow_error_set(error, EINVAL,
2333                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2334                                           "can't have decap action after"
2335                                           " modify action");
2336         if (attr->egress)
2337                 return rte_flow_error_set(error, ENOTSUP,
2338                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2339                                           NULL,
2340                                           "decap action not supported for "
2341                                           "egress");
2342         if (!attr->transfer && priv->representor)
2343                 return rte_flow_error_set(error, ENOTSUP,
2344                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2345                                           "decap action for VF representor "
2346                                           "not supported on NIC table");
2347         return 0;
2348 }
2349
2350 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
2351
2352 /**
2353  * Validate the raw encap and decap actions.
2354  *
2355  * @param[in] dev
2356  *   Pointer to the rte_eth_dev structure.
2357  * @param[in] decap
2358  *   Pointer to the decap action.
2359  * @param[in] encap
2360  *   Pointer to the encap action.
2361  * @param[in] attr
2362  *   Pointer to flow attributes
2363  * @param[in/out] action_flags
2364  *   Holds the actions detected until now.
2365  * @param[out] actions_n
2366  *   pointer to the number of actions counter.
2367  * @param[out] error
2368  *   Pointer to error structure.
2369  *
2370  * @return
2371  *   0 on success, a negative errno value otherwise and rte_errno is set.
2372  */
2373 static int
2374 flow_dv_validate_action_raw_encap_decap
2375         (struct rte_eth_dev *dev,
2376          const struct rte_flow_action_raw_decap *decap,
2377          const struct rte_flow_action_raw_encap *encap,
2378          const struct rte_flow_attr *attr, uint64_t *action_flags,
2379          int *actions_n, struct rte_flow_error *error)
2380 {
2381         const struct mlx5_priv *priv = dev->data->dev_private;
2382         int ret;
2383
2384         if (encap && (!encap->size || !encap->data))
2385                 return rte_flow_error_set(error, EINVAL,
2386                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2387                                           "raw encap data cannot be empty");
2388         if (decap && encap) {
2389                 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
2390                     encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
2391                         /* L3 encap. */
2392                         decap = NULL;
2393                 else if (encap->size <=
2394                            MLX5_ENCAPSULATION_DECISION_SIZE &&
2395                            decap->size >
2396                            MLX5_ENCAPSULATION_DECISION_SIZE)
2397                         /* L3 decap. */
2398                         encap = NULL;
2399                 else if (encap->size >
2400                            MLX5_ENCAPSULATION_DECISION_SIZE &&
2401                            decap->size >
2402                            MLX5_ENCAPSULATION_DECISION_SIZE)
2403                         /* 2 L2 actions: encap and decap. */
2404                         ;
2405                 else
2406                         return rte_flow_error_set(error,
2407                                 ENOTSUP,
2408                                 RTE_FLOW_ERROR_TYPE_ACTION,
2409                                 NULL, "unsupported too small "
2410                                 "raw decap and too small raw "
2411                                 "encap combination");
2412         }
2413         if (decap) {
2414                 ret = flow_dv_validate_action_decap(dev, *action_flags, attr,
2415                                                     error);
2416                 if (ret < 0)
2417                         return ret;
2418                 *action_flags |= MLX5_FLOW_ACTION_DECAP;
2419                 ++(*actions_n);
2420         }
2421         if (encap) {
2422                 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
2423                         return rte_flow_error_set(error, ENOTSUP,
2424                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2425                                                   NULL,
2426                                                   "small raw encap size");
2427                 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
2428                         return rte_flow_error_set(error, EINVAL,
2429                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2430                                                   NULL,
2431                                                   "more than one encap action");
2432                 if (!attr->transfer && priv->representor)
2433                         return rte_flow_error_set
2434                                         (error, ENOTSUP,
2435                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2436                                          "encap action for VF representor "
2437                                          "not supported on NIC table");
2438                 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
2439                 ++(*actions_n);
2440         }
2441         return 0;
2442 }
2443
2444 /**
2445  * Find existing encap/decap resource or create and register a new one.
2446  *
2447  * @param[in, out] dev
2448  *   Pointer to rte_eth_dev structure.
2449  * @param[in, out] resource
2450  *   Pointer to encap/decap resource.
2451  * @parm[in, out] dev_flow
2452  *   Pointer to the dev_flow.
2453  * @param[out] error
2454  *   pointer to error structure.
2455  *
2456  * @return
2457  *   0 on success otherwise -errno and errno is set.
2458  */
2459 static int
2460 flow_dv_encap_decap_resource_register
2461                         (struct rte_eth_dev *dev,
2462                          struct mlx5_flow_dv_encap_decap_resource *resource,
2463                          struct mlx5_flow *dev_flow,
2464                          struct rte_flow_error *error)
2465 {
2466         struct mlx5_priv *priv = dev->data->dev_private;
2467         struct mlx5_ibv_shared *sh = priv->sh;
2468         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2469         struct mlx5dv_dr_domain *domain;
2470         uint32_t idx = 0;
2471
2472         resource->flags = dev_flow->dv.group ? 0 : 1;
2473         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2474                 domain = sh->fdb_domain;
2475         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2476                 domain = sh->rx_domain;
2477         else
2478                 domain = sh->tx_domain;
2479         /* Lookup a matching resource from cache. */
2480         ILIST_FOREACH(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], sh->encaps_decaps, idx,
2481                       cache_resource, next) {
2482                 if (resource->reformat_type == cache_resource->reformat_type &&
2483                     resource->ft_type == cache_resource->ft_type &&
2484                     resource->flags == cache_resource->flags &&
2485                     resource->size == cache_resource->size &&
2486                     !memcmp((const void *)resource->buf,
2487                             (const void *)cache_resource->buf,
2488                             resource->size)) {
2489                         DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d++",
2490                                 (void *)cache_resource,
2491                                 rte_atomic32_read(&cache_resource->refcnt));
2492                         rte_atomic32_inc(&cache_resource->refcnt);
2493                         dev_flow->handle->dvh.encap_decap = idx;
2494                         dev_flow->dv.encap_decap = cache_resource;
2495                         return 0;
2496                 }
2497         }
2498         /* Register new encap/decap resource. */
2499         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
2500                                        &dev_flow->handle->dvh.encap_decap);
2501         if (!cache_resource)
2502                 return rte_flow_error_set(error, ENOMEM,
2503                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2504                                           "cannot allocate resource memory");
2505         *cache_resource = *resource;
2506         cache_resource->verbs_action =
2507                 mlx5_glue->dv_create_flow_action_packet_reformat
2508                         (sh->ctx, cache_resource->reformat_type,
2509                          cache_resource->ft_type, domain, cache_resource->flags,
2510                          cache_resource->size,
2511                          (cache_resource->size ? cache_resource->buf : NULL));
2512         if (!cache_resource->verbs_action) {
2513                 rte_free(cache_resource);
2514                 return rte_flow_error_set(error, ENOMEM,
2515                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2516                                           NULL, "cannot create action");
2517         }
2518         rte_atomic32_init(&cache_resource->refcnt);
2519         rte_atomic32_inc(&cache_resource->refcnt);
2520         ILIST_INSERT(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], &sh->encaps_decaps,
2521                      dev_flow->handle->dvh.encap_decap, cache_resource, next);
2522         dev_flow->dv.encap_decap = cache_resource;
2523         DRV_LOG(DEBUG, "new encap/decap resource %p: refcnt %d++",
2524                 (void *)cache_resource,
2525                 rte_atomic32_read(&cache_resource->refcnt));
2526         return 0;
2527 }
2528
2529 /**
2530  * Find existing table jump resource or create and register a new one.
2531  *
2532  * @param[in, out] dev
2533  *   Pointer to rte_eth_dev structure.
2534  * @param[in, out] tbl
2535  *   Pointer to flow table resource.
2536  * @parm[in, out] dev_flow
2537  *   Pointer to the dev_flow.
2538  * @param[out] error
2539  *   pointer to error structure.
2540  *
2541  * @return
2542  *   0 on success otherwise -errno and errno is set.
2543  */
2544 static int
2545 flow_dv_jump_tbl_resource_register
2546                         (struct rte_eth_dev *dev __rte_unused,
2547                          struct mlx5_flow_tbl_resource *tbl,
2548                          struct mlx5_flow *dev_flow,
2549                          struct rte_flow_error *error)
2550 {
2551         struct mlx5_flow_tbl_data_entry *tbl_data =
2552                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
2553         int cnt;
2554
2555         MLX5_ASSERT(tbl);
2556         cnt = rte_atomic32_read(&tbl_data->jump.refcnt);
2557         if (!cnt) {
2558                 tbl_data->jump.action =
2559                         mlx5_glue->dr_create_flow_action_dest_flow_tbl
2560                         (tbl->obj);
2561                 if (!tbl_data->jump.action)
2562                         return rte_flow_error_set(error, ENOMEM,
2563                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2564                                         NULL, "cannot create jump action");
2565                 DRV_LOG(DEBUG, "new jump table resource %p: refcnt %d++",
2566                         (void *)&tbl_data->jump, cnt);
2567         } else {
2568                 /* old jump should not make the table ref++. */
2569                 flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
2570                 MLX5_ASSERT(tbl_data->jump.action);
2571                 DRV_LOG(DEBUG, "existed jump table resource %p: refcnt %d++",
2572                         (void *)&tbl_data->jump, cnt);
2573         }
2574         rte_atomic32_inc(&tbl_data->jump.refcnt);
2575         dev_flow->handle->dvh.jump = tbl_data->idx;
2576         dev_flow->dv.jump = &tbl_data->jump;
2577         return 0;
2578 }
2579
2580 /**
2581  * Find existing table port ID resource or create and register a new one.
2582  *
2583  * @param[in, out] dev
2584  *   Pointer to rte_eth_dev structure.
2585  * @param[in, out] resource
2586  *   Pointer to port ID action resource.
2587  * @parm[in, out] dev_flow
2588  *   Pointer to the dev_flow.
2589  * @param[out] error
2590  *   pointer to error structure.
2591  *
2592  * @return
2593  *   0 on success otherwise -errno and errno is set.
2594  */
2595 static int
2596 flow_dv_port_id_action_resource_register
2597                         (struct rte_eth_dev *dev,
2598                          struct mlx5_flow_dv_port_id_action_resource *resource,
2599                          struct mlx5_flow *dev_flow,
2600                          struct rte_flow_error *error)
2601 {
2602         struct mlx5_priv *priv = dev->data->dev_private;
2603         struct mlx5_ibv_shared *sh = priv->sh;
2604         struct mlx5_flow_dv_port_id_action_resource *cache_resource;
2605         uint32_t idx = 0;
2606
2607         /* Lookup a matching resource from cache. */
2608         ILIST_FOREACH(sh->ipool[MLX5_IPOOL_PORT_ID], sh->port_id_action_list,
2609                       idx, cache_resource, next) {
2610                 if (resource->port_id == cache_resource->port_id) {
2611                         DRV_LOG(DEBUG, "port id action resource resource %p: "
2612                                 "refcnt %d++",
2613                                 (void *)cache_resource,
2614                                 rte_atomic32_read(&cache_resource->refcnt));
2615                         rte_atomic32_inc(&cache_resource->refcnt);
2616                         dev_flow->handle->dvh.port_id_action = idx;
2617                         dev_flow->dv.port_id_action = cache_resource;
2618                         return 0;
2619                 }
2620         }
2621         /* Register new port id action resource. */
2622         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID],
2623                                        &dev_flow->handle->dvh.port_id_action);
2624         if (!cache_resource)
2625                 return rte_flow_error_set(error, ENOMEM,
2626                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2627                                           "cannot allocate resource memory");
2628         *cache_resource = *resource;
2629         /*
2630          * Depending on rdma_core version the glue routine calls
2631          * either mlx5dv_dr_action_create_dest_ib_port(domain, ibv_port)
2632          * or mlx5dv_dr_action_create_dest_vport(domain, vport_id).
2633          */
2634         cache_resource->action =
2635                 mlx5_glue->dr_create_flow_action_dest_port
2636                         (priv->sh->fdb_domain, resource->port_id);
2637         if (!cache_resource->action) {
2638                 rte_free(cache_resource);
2639                 return rte_flow_error_set(error, ENOMEM,
2640                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2641                                           NULL, "cannot create action");
2642         }
2643         rte_atomic32_init(&cache_resource->refcnt);
2644         rte_atomic32_inc(&cache_resource->refcnt);
2645         ILIST_INSERT(sh->ipool[MLX5_IPOOL_PORT_ID], &sh->port_id_action_list,
2646                      dev_flow->handle->dvh.port_id_action, cache_resource,
2647                      next);
2648         dev_flow->dv.port_id_action = cache_resource;
2649         DRV_LOG(DEBUG, "new port id action resource %p: refcnt %d++",
2650                 (void *)cache_resource,
2651                 rte_atomic32_read(&cache_resource->refcnt));
2652         return 0;
2653 }
2654
2655 /**
2656  * Find existing push vlan resource or create and register a new one.
2657  *
2658  * @param [in, out] dev
2659  *   Pointer to rte_eth_dev structure.
2660  * @param[in, out] resource
2661  *   Pointer to port ID action resource.
2662  * @parm[in, out] dev_flow
2663  *   Pointer to the dev_flow.
2664  * @param[out] error
2665  *   pointer to error structure.
2666  *
2667  * @return
2668  *   0 on success otherwise -errno and errno is set.
2669  */
2670 static int
2671 flow_dv_push_vlan_action_resource_register
2672                        (struct rte_eth_dev *dev,
2673                         struct mlx5_flow_dv_push_vlan_action_resource *resource,
2674                         struct mlx5_flow *dev_flow,
2675                         struct rte_flow_error *error)
2676 {
2677         struct mlx5_priv *priv = dev->data->dev_private;
2678         struct mlx5_ibv_shared *sh = priv->sh;
2679         struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
2680         struct mlx5dv_dr_domain *domain;
2681         uint32_t idx = 0;
2682
2683         /* Lookup a matching resource from cache. */
2684         ILIST_FOREACH(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2685                       sh->push_vlan_action_list, idx, cache_resource, next) {
2686                 if (resource->vlan_tag == cache_resource->vlan_tag &&
2687                     resource->ft_type == cache_resource->ft_type) {
2688                         DRV_LOG(DEBUG, "push-VLAN action resource resource %p: "
2689                                 "refcnt %d++",
2690                                 (void *)cache_resource,
2691                                 rte_atomic32_read(&cache_resource->refcnt));
2692                         rte_atomic32_inc(&cache_resource->refcnt);
2693                         dev_flow->handle->dvh.push_vlan_res = idx;
2694                         dev_flow->dv.push_vlan_res = cache_resource;
2695                         return 0;
2696                 }
2697         }
2698         /* Register new push_vlan action resource. */
2699         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2700                                        &dev_flow->handle->dvh.push_vlan_res);
2701         if (!cache_resource)
2702                 return rte_flow_error_set(error, ENOMEM,
2703                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2704                                           "cannot allocate resource memory");
2705         *cache_resource = *resource;
2706         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2707                 domain = sh->fdb_domain;
2708         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2709                 domain = sh->rx_domain;
2710         else
2711                 domain = sh->tx_domain;
2712         cache_resource->action =
2713                 mlx5_glue->dr_create_flow_action_push_vlan(domain,
2714                                                            resource->vlan_tag);
2715         if (!cache_resource->action) {
2716                 rte_free(cache_resource);
2717                 return rte_flow_error_set(error, ENOMEM,
2718                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2719                                           NULL, "cannot create action");
2720         }
2721         rte_atomic32_init(&cache_resource->refcnt);
2722         rte_atomic32_inc(&cache_resource->refcnt);
2723         ILIST_INSERT(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2724                      &sh->push_vlan_action_list,
2725                      dev_flow->handle->dvh.push_vlan_res,
2726                      cache_resource, next);
2727         dev_flow->dv.push_vlan_res = cache_resource;
2728         DRV_LOG(DEBUG, "new push vlan action resource %p: refcnt %d++",
2729                 (void *)cache_resource,
2730                 rte_atomic32_read(&cache_resource->refcnt));
2731         return 0;
2732 }
2733 /**
2734  * Get the size of specific rte_flow_item_type
2735  *
2736  * @param[in] item_type
2737  *   Tested rte_flow_item_type.
2738  *
2739  * @return
2740  *   sizeof struct item_type, 0 if void or irrelevant.
2741  */
2742 static size_t
2743 flow_dv_get_item_len(const enum rte_flow_item_type item_type)
2744 {
2745         size_t retval;
2746
2747         switch (item_type) {
2748         case RTE_FLOW_ITEM_TYPE_ETH:
2749                 retval = sizeof(struct rte_flow_item_eth);
2750                 break;
2751         case RTE_FLOW_ITEM_TYPE_VLAN:
2752                 retval = sizeof(struct rte_flow_item_vlan);
2753                 break;
2754         case RTE_FLOW_ITEM_TYPE_IPV4:
2755                 retval = sizeof(struct rte_flow_item_ipv4);
2756                 break;
2757         case RTE_FLOW_ITEM_TYPE_IPV6:
2758                 retval = sizeof(struct rte_flow_item_ipv6);
2759                 break;
2760         case RTE_FLOW_ITEM_TYPE_UDP:
2761                 retval = sizeof(struct rte_flow_item_udp);
2762                 break;
2763         case RTE_FLOW_ITEM_TYPE_TCP:
2764                 retval = sizeof(struct rte_flow_item_tcp);
2765                 break;
2766         case RTE_FLOW_ITEM_TYPE_VXLAN:
2767                 retval = sizeof(struct rte_flow_item_vxlan);
2768                 break;
2769         case RTE_FLOW_ITEM_TYPE_GRE:
2770                 retval = sizeof(struct rte_flow_item_gre);
2771                 break;
2772         case RTE_FLOW_ITEM_TYPE_NVGRE:
2773                 retval = sizeof(struct rte_flow_item_nvgre);
2774                 break;
2775         case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2776                 retval = sizeof(struct rte_flow_item_vxlan_gpe);
2777                 break;
2778         case RTE_FLOW_ITEM_TYPE_MPLS:
2779                 retval = sizeof(struct rte_flow_item_mpls);
2780                 break;
2781         case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
2782         default:
2783                 retval = 0;
2784                 break;
2785         }
2786         return retval;
2787 }
2788
2789 #define MLX5_ENCAP_IPV4_VERSION         0x40
2790 #define MLX5_ENCAP_IPV4_IHL_MIN         0x05
2791 #define MLX5_ENCAP_IPV4_TTL_DEF         0x40
2792 #define MLX5_ENCAP_IPV6_VTC_FLOW        0x60000000
2793 #define MLX5_ENCAP_IPV6_HOP_LIMIT       0xff
2794 #define MLX5_ENCAP_VXLAN_FLAGS          0x08000000
2795 #define MLX5_ENCAP_VXLAN_GPE_FLAGS      0x04
2796
2797 /**
2798  * Convert the encap action data from list of rte_flow_item to raw buffer
2799  *
2800  * @param[in] items
2801  *   Pointer to rte_flow_item objects list.
2802  * @param[out] buf
2803  *   Pointer to the output buffer.
2804  * @param[out] size
2805  *   Pointer to the output buffer size.
2806  * @param[out] error
2807  *   Pointer to the error structure.
2808  *
2809  * @return
2810  *   0 on success, a negative errno value otherwise and rte_errno is set.
2811  */
2812 static int
2813 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
2814                            size_t *size, struct rte_flow_error *error)
2815 {
2816         struct rte_ether_hdr *eth = NULL;
2817         struct rte_vlan_hdr *vlan = NULL;
2818         struct rte_ipv4_hdr *ipv4 = NULL;
2819         struct rte_ipv6_hdr *ipv6 = NULL;
2820         struct rte_udp_hdr *udp = NULL;
2821         struct rte_vxlan_hdr *vxlan = NULL;
2822         struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
2823         struct rte_gre_hdr *gre = NULL;
2824         size_t len;
2825         size_t temp_size = 0;
2826
2827         if (!items)
2828                 return rte_flow_error_set(error, EINVAL,
2829                                           RTE_FLOW_ERROR_TYPE_ACTION,
2830                                           NULL, "invalid empty data");
2831         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2832                 len = flow_dv_get_item_len(items->type);
2833                 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
2834                         return rte_flow_error_set(error, EINVAL,
2835                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2836                                                   (void *)items->type,
2837                                                   "items total size is too big"
2838                                                   " for encap action");
2839                 rte_memcpy((void *)&buf[temp_size], items->spec, len);
2840                 switch (items->type) {
2841                 case RTE_FLOW_ITEM_TYPE_ETH:
2842                         eth = (struct rte_ether_hdr *)&buf[temp_size];
2843                         break;
2844                 case RTE_FLOW_ITEM_TYPE_VLAN:
2845                         vlan = (struct rte_vlan_hdr *)&buf[temp_size];
2846                         if (!eth)
2847                                 return rte_flow_error_set(error, EINVAL,
2848                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2849                                                 (void *)items->type,
2850                                                 "eth header not found");
2851                         if (!eth->ether_type)
2852                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
2853                         break;
2854                 case RTE_FLOW_ITEM_TYPE_IPV4:
2855                         ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
2856                         if (!vlan && !eth)
2857                                 return rte_flow_error_set(error, EINVAL,
2858                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2859                                                 (void *)items->type,
2860                                                 "neither eth nor vlan"
2861                                                 " header found");
2862                         if (vlan && !vlan->eth_proto)
2863                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2864                         else if (eth && !eth->ether_type)
2865                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2866                         if (!ipv4->version_ihl)
2867                                 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
2868                                                     MLX5_ENCAP_IPV4_IHL_MIN;
2869                         if (!ipv4->time_to_live)
2870                                 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
2871                         break;
2872                 case RTE_FLOW_ITEM_TYPE_IPV6:
2873                         ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
2874                         if (!vlan && !eth)
2875                                 return rte_flow_error_set(error, EINVAL,
2876                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2877                                                 (void *)items->type,
2878                                                 "neither eth nor vlan"
2879                                                 " header found");
2880                         if (vlan && !vlan->eth_proto)
2881                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2882                         else if (eth && !eth->ether_type)
2883                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2884                         if (!ipv6->vtc_flow)
2885                                 ipv6->vtc_flow =
2886                                         RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
2887                         if (!ipv6->hop_limits)
2888                                 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
2889                         break;
2890                 case RTE_FLOW_ITEM_TYPE_UDP:
2891                         udp = (struct rte_udp_hdr *)&buf[temp_size];
2892                         if (!ipv4 && !ipv6)
2893                                 return rte_flow_error_set(error, EINVAL,
2894                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2895                                                 (void *)items->type,
2896                                                 "ip header not found");
2897                         if (ipv4 && !ipv4->next_proto_id)
2898                                 ipv4->next_proto_id = IPPROTO_UDP;
2899                         else if (ipv6 && !ipv6->proto)
2900                                 ipv6->proto = IPPROTO_UDP;
2901                         break;
2902                 case RTE_FLOW_ITEM_TYPE_VXLAN:
2903                         vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
2904                         if (!udp)
2905                                 return rte_flow_error_set(error, EINVAL,
2906                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2907                                                 (void *)items->type,
2908                                                 "udp header not found");
2909                         if (!udp->dst_port)
2910                                 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
2911                         if (!vxlan->vx_flags)
2912                                 vxlan->vx_flags =
2913                                         RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
2914                         break;
2915                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2916                         vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
2917                         if (!udp)
2918                                 return rte_flow_error_set(error, EINVAL,
2919                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2920                                                 (void *)items->type,
2921                                                 "udp header not found");
2922                         if (!vxlan_gpe->proto)
2923                                 return rte_flow_error_set(error, EINVAL,
2924                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2925                                                 (void *)items->type,
2926                                                 "next protocol not found");
2927                         if (!udp->dst_port)
2928                                 udp->dst_port =
2929                                         RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
2930                         if (!vxlan_gpe->vx_flags)
2931                                 vxlan_gpe->vx_flags =
2932                                                 MLX5_ENCAP_VXLAN_GPE_FLAGS;
2933                         break;
2934                 case RTE_FLOW_ITEM_TYPE_GRE:
2935                 case RTE_FLOW_ITEM_TYPE_NVGRE:
2936                         gre = (struct rte_gre_hdr *)&buf[temp_size];
2937                         if (!gre->proto)
2938                                 return rte_flow_error_set(error, EINVAL,
2939                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2940                                                 (void *)items->type,
2941                                                 "next protocol not found");
2942                         if (!ipv4 && !ipv6)
2943                                 return rte_flow_error_set(error, EINVAL,
2944                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2945                                                 (void *)items->type,
2946                                                 "ip header not found");
2947                         if (ipv4 && !ipv4->next_proto_id)
2948                                 ipv4->next_proto_id = IPPROTO_GRE;
2949                         else if (ipv6 && !ipv6->proto)
2950                                 ipv6->proto = IPPROTO_GRE;
2951                         break;
2952                 case RTE_FLOW_ITEM_TYPE_VOID:
2953                         break;
2954                 default:
2955                         return rte_flow_error_set(error, EINVAL,
2956                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2957                                                   (void *)items->type,
2958                                                   "unsupported item type");
2959                         break;
2960                 }
2961                 temp_size += len;
2962         }
2963         *size = temp_size;
2964         return 0;
2965 }
2966
2967 static int
2968 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
2969 {
2970         struct rte_ether_hdr *eth = NULL;
2971         struct rte_vlan_hdr *vlan = NULL;
2972         struct rte_ipv6_hdr *ipv6 = NULL;
2973         struct rte_udp_hdr *udp = NULL;
2974         char *next_hdr;
2975         uint16_t proto;
2976
2977         eth = (struct rte_ether_hdr *)data;
2978         next_hdr = (char *)(eth + 1);
2979         proto = RTE_BE16(eth->ether_type);
2980
2981         /* VLAN skipping */
2982         while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
2983                 vlan = (struct rte_vlan_hdr *)next_hdr;
2984                 proto = RTE_BE16(vlan->eth_proto);
2985                 next_hdr += sizeof(struct rte_vlan_hdr);
2986         }
2987
2988         /* HW calculates IPv4 csum. no need to proceed */
2989         if (proto == RTE_ETHER_TYPE_IPV4)
2990                 return 0;
2991
2992         /* non IPv4/IPv6 header. not supported */
2993         if (proto != RTE_ETHER_TYPE_IPV6) {
2994                 return rte_flow_error_set(error, ENOTSUP,
2995                                           RTE_FLOW_ERROR_TYPE_ACTION,
2996                                           NULL, "Cannot offload non IPv4/IPv6");
2997         }
2998
2999         ipv6 = (struct rte_ipv6_hdr *)next_hdr;
3000
3001         /* ignore non UDP */
3002         if (ipv6->proto != IPPROTO_UDP)
3003                 return 0;
3004
3005         udp = (struct rte_udp_hdr *)(ipv6 + 1);
3006         udp->dgram_cksum = 0;
3007
3008         return 0;
3009 }
3010
3011 /**
3012  * Convert L2 encap action to DV specification.
3013  *
3014  * @param[in] dev
3015  *   Pointer to rte_eth_dev structure.
3016  * @param[in] action
3017  *   Pointer to action structure.
3018  * @param[in, out] dev_flow
3019  *   Pointer to the mlx5_flow.
3020  * @param[in] transfer
3021  *   Mark if the flow is E-Switch flow.
3022  * @param[out] error
3023  *   Pointer to the error structure.
3024  *
3025  * @return
3026  *   0 on success, a negative errno value otherwise and rte_errno is set.
3027  */
3028 static int
3029 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
3030                                const struct rte_flow_action *action,
3031                                struct mlx5_flow *dev_flow,
3032                                uint8_t transfer,
3033                                struct rte_flow_error *error)
3034 {
3035         const struct rte_flow_item *encap_data;
3036         const struct rte_flow_action_raw_encap *raw_encap_data;
3037         struct mlx5_flow_dv_encap_decap_resource res = {
3038                 .reformat_type =
3039                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
3040                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3041                                       MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
3042         };
3043
3044         if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
3045                 raw_encap_data =
3046                         (const struct rte_flow_action_raw_encap *)action->conf;
3047                 res.size = raw_encap_data->size;
3048                 memcpy(res.buf, raw_encap_data->data, res.size);
3049         } else {
3050                 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
3051                         encap_data =
3052                                 ((const struct rte_flow_action_vxlan_encap *)
3053                                                 action->conf)->definition;
3054                 else
3055                         encap_data =
3056                                 ((const struct rte_flow_action_nvgre_encap *)
3057                                                 action->conf)->definition;
3058                 if (flow_dv_convert_encap_data(encap_data, res.buf,
3059                                                &res.size, error))
3060                         return -rte_errno;
3061         }
3062         if (flow_dv_zero_encap_udp_csum(res.buf, error))
3063                 return -rte_errno;
3064         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3065                 return rte_flow_error_set(error, EINVAL,
3066                                           RTE_FLOW_ERROR_TYPE_ACTION,
3067                                           NULL, "can't create L2 encap action");
3068         return 0;
3069 }
3070
3071 /**
3072  * Convert L2 decap action to DV specification.
3073  *
3074  * @param[in] dev
3075  *   Pointer to rte_eth_dev structure.
3076  * @param[in, out] dev_flow
3077  *   Pointer to the mlx5_flow.
3078  * @param[in] transfer
3079  *   Mark if the flow is E-Switch flow.
3080  * @param[out] error
3081  *   Pointer to the error structure.
3082  *
3083  * @return
3084  *   0 on success, a negative errno value otherwise and rte_errno is set.
3085  */
3086 static int
3087 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
3088                                struct mlx5_flow *dev_flow,
3089                                uint8_t transfer,
3090                                struct rte_flow_error *error)
3091 {
3092         struct mlx5_flow_dv_encap_decap_resource res = {
3093                 .size = 0,
3094                 .reformat_type =
3095                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
3096                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3097                                       MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
3098         };
3099
3100         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3101                 return rte_flow_error_set(error, EINVAL,
3102                                           RTE_FLOW_ERROR_TYPE_ACTION,
3103                                           NULL, "can't create L2 decap action");
3104         return 0;
3105 }
3106
3107 /**
3108  * Convert raw decap/encap (L3 tunnel) action to DV specification.
3109  *
3110  * @param[in] dev
3111  *   Pointer to rte_eth_dev structure.
3112  * @param[in] action
3113  *   Pointer to action structure.
3114  * @param[in, out] dev_flow
3115  *   Pointer to the mlx5_flow.
3116  * @param[in] attr
3117  *   Pointer to the flow attributes.
3118  * @param[out] error
3119  *   Pointer to the error structure.
3120  *
3121  * @return
3122  *   0 on success, a negative errno value otherwise and rte_errno is set.
3123  */
3124 static int
3125 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
3126                                 const struct rte_flow_action *action,
3127                                 struct mlx5_flow *dev_flow,
3128                                 const struct rte_flow_attr *attr,
3129                                 struct rte_flow_error *error)
3130 {
3131         const struct rte_flow_action_raw_encap *encap_data;
3132         struct mlx5_flow_dv_encap_decap_resource res;
3133
3134         memset(&res, 0, sizeof(res));
3135         encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
3136         res.size = encap_data->size;
3137         memcpy(res.buf, encap_data->data, res.size);
3138         res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
3139                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
3140                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
3141         if (attr->transfer)
3142                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3143         else
3144                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3145                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3146         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3147                 return rte_flow_error_set(error, EINVAL,
3148                                           RTE_FLOW_ERROR_TYPE_ACTION,
3149                                           NULL, "can't create encap action");
3150         return 0;
3151 }
3152
3153 /**
3154  * Create action push VLAN.
3155  *
3156  * @param[in] dev
3157  *   Pointer to rte_eth_dev structure.
3158  * @param[in] attr
3159  *   Pointer to the flow attributes.
3160  * @param[in] vlan
3161  *   Pointer to the vlan to push to the Ethernet header.
3162  * @param[in, out] dev_flow
3163  *   Pointer to the mlx5_flow.
3164  * @param[out] error
3165  *   Pointer to the error structure.
3166  *
3167  * @return
3168  *   0 on success, a negative errno value otherwise and rte_errno is set.
3169  */
3170 static int
3171 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
3172                                 const struct rte_flow_attr *attr,
3173                                 const struct rte_vlan_hdr *vlan,
3174                                 struct mlx5_flow *dev_flow,
3175                                 struct rte_flow_error *error)
3176 {
3177         struct mlx5_flow_dv_push_vlan_action_resource res;
3178
3179         memset(&res, 0, sizeof(res));
3180         res.vlan_tag =
3181                 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
3182                                  vlan->vlan_tci);
3183         if (attr->transfer)
3184                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3185         else
3186                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3187                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3188         return flow_dv_push_vlan_action_resource_register
3189                                             (dev, &res, dev_flow, error);
3190 }
3191
3192 /**
3193  * Validate the modify-header actions.
3194  *
3195  * @param[in] action_flags
3196  *   Holds the actions detected until now.
3197  * @param[in] action
3198  *   Pointer to the modify action.
3199  * @param[out] error
3200  *   Pointer to error structure.
3201  *
3202  * @return
3203  *   0 on success, a negative errno value otherwise and rte_errno is set.
3204  */
3205 static int
3206 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
3207                                    const struct rte_flow_action *action,
3208                                    struct rte_flow_error *error)
3209 {
3210         if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
3211                 return rte_flow_error_set(error, EINVAL,
3212                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3213                                           NULL, "action configuration not set");
3214         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3215                 return rte_flow_error_set(error, EINVAL,
3216                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3217                                           "can't have encap action before"
3218                                           " modify action");
3219         return 0;
3220 }
3221
3222 /**
3223  * Validate the modify-header MAC address actions.
3224  *
3225  * @param[in] action_flags
3226  *   Holds the actions detected until now.
3227  * @param[in] action
3228  *   Pointer to the modify action.
3229  * @param[in] item_flags
3230  *   Holds the items detected.
3231  * @param[out] error
3232  *   Pointer to error structure.
3233  *
3234  * @return
3235  *   0 on success, a negative errno value otherwise and rte_errno is set.
3236  */
3237 static int
3238 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
3239                                    const struct rte_flow_action *action,
3240                                    const uint64_t item_flags,
3241                                    struct rte_flow_error *error)
3242 {
3243         int ret = 0;
3244
3245         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3246         if (!ret) {
3247                 if (!(item_flags & MLX5_FLOW_LAYER_L2))
3248                         return rte_flow_error_set(error, EINVAL,
3249                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3250                                                   NULL,
3251                                                   "no L2 item in pattern");
3252         }
3253         return ret;
3254 }
3255
3256 /**
3257  * Validate the modify-header IPv4 address actions.
3258  *
3259  * @param[in] action_flags
3260  *   Holds the actions detected until now.
3261  * @param[in] action
3262  *   Pointer to the modify action.
3263  * @param[in] item_flags
3264  *   Holds the items detected.
3265  * @param[out] error
3266  *   Pointer to error structure.
3267  *
3268  * @return
3269  *   0 on success, a negative errno value otherwise and rte_errno is set.
3270  */
3271 static int
3272 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
3273                                     const struct rte_flow_action *action,
3274                                     const uint64_t item_flags,
3275                                     struct rte_flow_error *error)
3276 {
3277         int ret = 0;
3278         uint64_t layer;
3279
3280         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3281         if (!ret) {
3282                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3283                                  MLX5_FLOW_LAYER_INNER_L3_IPV4 :
3284                                  MLX5_FLOW_LAYER_OUTER_L3_IPV4;
3285                 if (!(item_flags & layer))
3286                         return rte_flow_error_set(error, EINVAL,
3287                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3288                                                   NULL,
3289                                                   "no ipv4 item in pattern");
3290         }
3291         return ret;
3292 }
3293
3294 /**
3295  * Validate the modify-header IPv6 address actions.
3296  *
3297  * @param[in] action_flags
3298  *   Holds the actions detected until now.
3299  * @param[in] action
3300  *   Pointer to the modify action.
3301  * @param[in] item_flags
3302  *   Holds the items detected.
3303  * @param[out] error
3304  *   Pointer to error structure.
3305  *
3306  * @return
3307  *   0 on success, a negative errno value otherwise and rte_errno is set.
3308  */
3309 static int
3310 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
3311                                     const struct rte_flow_action *action,
3312                                     const uint64_t item_flags,
3313                                     struct rte_flow_error *error)
3314 {
3315         int ret = 0;
3316         uint64_t layer;
3317
3318         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3319         if (!ret) {
3320                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3321                                  MLX5_FLOW_LAYER_INNER_L3_IPV6 :
3322                                  MLX5_FLOW_LAYER_OUTER_L3_IPV6;
3323                 if (!(item_flags & layer))
3324                         return rte_flow_error_set(error, EINVAL,
3325                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3326                                                   NULL,
3327                                                   "no ipv6 item in pattern");
3328         }
3329         return ret;
3330 }
3331
3332 /**
3333  * Validate the modify-header TP actions.
3334  *
3335  * @param[in] action_flags
3336  *   Holds the actions detected until now.
3337  * @param[in] action
3338  *   Pointer to the modify action.
3339  * @param[in] item_flags
3340  *   Holds the items detected.
3341  * @param[out] error
3342  *   Pointer to error structure.
3343  *
3344  * @return
3345  *   0 on success, a negative errno value otherwise and rte_errno is set.
3346  */
3347 static int
3348 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
3349                                   const struct rte_flow_action *action,
3350                                   const uint64_t item_flags,
3351                                   struct rte_flow_error *error)
3352 {
3353         int ret = 0;
3354         uint64_t layer;
3355
3356         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3357         if (!ret) {
3358                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3359                                  MLX5_FLOW_LAYER_INNER_L4 :
3360                                  MLX5_FLOW_LAYER_OUTER_L4;
3361                 if (!(item_flags & layer))
3362                         return rte_flow_error_set(error, EINVAL,
3363                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3364                                                   NULL, "no transport layer "
3365                                                   "in pattern");
3366         }
3367         return ret;
3368 }
3369
3370 /**
3371  * Validate the modify-header actions of increment/decrement
3372  * TCP Sequence-number.
3373  *
3374  * @param[in] action_flags
3375  *   Holds the actions detected until now.
3376  * @param[in] action
3377  *   Pointer to the modify action.
3378  * @param[in] item_flags
3379  *   Holds the items detected.
3380  * @param[out] error
3381  *   Pointer to error structure.
3382  *
3383  * @return
3384  *   0 on success, a negative errno value otherwise and rte_errno is set.
3385  */
3386 static int
3387 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
3388                                        const struct rte_flow_action *action,
3389                                        const uint64_t item_flags,
3390                                        struct rte_flow_error *error)
3391 {
3392         int ret = 0;
3393         uint64_t layer;
3394
3395         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3396         if (!ret) {
3397                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3398                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
3399                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
3400                 if (!(item_flags & layer))
3401                         return rte_flow_error_set(error, EINVAL,
3402                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3403                                                   NULL, "no TCP item in"
3404                                                   " pattern");
3405                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
3406                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
3407                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
3408                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
3409                         return rte_flow_error_set(error, EINVAL,
3410                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3411                                                   NULL,
3412                                                   "cannot decrease and increase"
3413                                                   " TCP sequence number"
3414                                                   " at the same time");
3415         }
3416         return ret;
3417 }
3418
3419 /**
3420  * Validate the modify-header actions of increment/decrement
3421  * TCP Acknowledgment number.
3422  *
3423  * @param[in] action_flags
3424  *   Holds the actions detected until now.
3425  * @param[in] action
3426  *   Pointer to the modify action.
3427  * @param[in] item_flags
3428  *   Holds the items detected.
3429  * @param[out] error
3430  *   Pointer to error structure.
3431  *
3432  * @return
3433  *   0 on success, a negative errno value otherwise and rte_errno is set.
3434  */
3435 static int
3436 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
3437                                        const struct rte_flow_action *action,
3438                                        const uint64_t item_flags,
3439                                        struct rte_flow_error *error)
3440 {
3441         int ret = 0;
3442         uint64_t layer;
3443
3444         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3445         if (!ret) {
3446                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3447                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
3448                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
3449                 if (!(item_flags & layer))
3450                         return rte_flow_error_set(error, EINVAL,
3451                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3452                                                   NULL, "no TCP item in"
3453                                                   " pattern");
3454                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
3455                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
3456                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
3457                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
3458                         return rte_flow_error_set(error, EINVAL,
3459                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3460                                                   NULL,
3461                                                   "cannot decrease and increase"
3462                                                   " TCP acknowledgment number"
3463                                                   " at the same time");
3464         }
3465         return ret;
3466 }
3467
3468 /**
3469  * Validate the modify-header TTL actions.
3470  *
3471  * @param[in] action_flags
3472  *   Holds the actions detected until now.
3473  * @param[in] action
3474  *   Pointer to the modify action.
3475  * @param[in] item_flags
3476  *   Holds the items detected.
3477  * @param[out] error
3478  *   Pointer to error structure.
3479  *
3480  * @return
3481  *   0 on success, a negative errno value otherwise and rte_errno is set.
3482  */
3483 static int
3484 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
3485                                    const struct rte_flow_action *action,
3486                                    const uint64_t item_flags,
3487                                    struct rte_flow_error *error)
3488 {
3489         int ret = 0;
3490         uint64_t layer;
3491
3492         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3493         if (!ret) {
3494                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3495                                  MLX5_FLOW_LAYER_INNER_L3 :
3496                                  MLX5_FLOW_LAYER_OUTER_L3;
3497                 if (!(item_flags & layer))
3498                         return rte_flow_error_set(error, EINVAL,
3499                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3500                                                   NULL,
3501                                                   "no IP protocol in pattern");
3502         }
3503         return ret;
3504 }
3505
3506 /**
3507  * Validate jump action.
3508  *
3509  * @param[in] action
3510  *   Pointer to the jump action.
3511  * @param[in] action_flags
3512  *   Holds the actions detected until now.
3513  * @param[in] attributes
3514  *   Pointer to flow attributes
3515  * @param[in] external
3516  *   Action belongs to flow rule created by request external to PMD.
3517  * @param[out] error
3518  *   Pointer to error structure.
3519  *
3520  * @return
3521  *   0 on success, a negative errno value otherwise and rte_errno is set.
3522  */
3523 static int
3524 flow_dv_validate_action_jump(const struct rte_flow_action *action,
3525                              uint64_t action_flags,
3526                              const struct rte_flow_attr *attributes,
3527                              bool external, struct rte_flow_error *error)
3528 {
3529         uint32_t target_group, table;
3530         int ret = 0;
3531
3532         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3533                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3534                 return rte_flow_error_set(error, EINVAL,
3535                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3536                                           "can't have 2 fate actions in"
3537                                           " same flow");
3538         if (action_flags & MLX5_FLOW_ACTION_METER)
3539                 return rte_flow_error_set(error, ENOTSUP,
3540                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3541                                           "jump with meter not support");
3542         if (!action->conf)
3543                 return rte_flow_error_set(error, EINVAL,
3544                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3545                                           NULL, "action configuration not set");
3546         target_group =
3547                 ((const struct rte_flow_action_jump *)action->conf)->group;
3548         ret = mlx5_flow_group_to_table(attributes, external, target_group,
3549                                        true, &table, error);
3550         if (ret)
3551                 return ret;
3552         if (attributes->group == target_group)
3553                 return rte_flow_error_set(error, EINVAL,
3554                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3555                                           "target group must be other than"
3556                                           " the current flow group");
3557         return 0;
3558 }
3559
3560 /*
3561  * Validate the port_id action.
3562  *
3563  * @param[in] dev
3564  *   Pointer to rte_eth_dev structure.
3565  * @param[in] action_flags
3566  *   Bit-fields that holds the actions detected until now.
3567  * @param[in] action
3568  *   Port_id RTE action structure.
3569  * @param[in] attr
3570  *   Attributes of flow that includes this action.
3571  * @param[out] error
3572  *   Pointer to error structure.
3573  *
3574  * @return
3575  *   0 on success, a negative errno value otherwise and rte_errno is set.
3576  */
3577 static int
3578 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
3579                                 uint64_t action_flags,
3580                                 const struct rte_flow_action *action,
3581                                 const struct rte_flow_attr *attr,
3582                                 struct rte_flow_error *error)
3583 {
3584         const struct rte_flow_action_port_id *port_id;
3585         struct mlx5_priv *act_priv;
3586         struct mlx5_priv *dev_priv;
3587         uint16_t port;
3588
3589         if (!attr->transfer)
3590                 return rte_flow_error_set(error, ENOTSUP,
3591                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3592                                           NULL,
3593                                           "port id action is valid in transfer"
3594                                           " mode only");
3595         if (!action || !action->conf)
3596                 return rte_flow_error_set(error, ENOTSUP,
3597                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3598                                           NULL,
3599                                           "port id action parameters must be"
3600                                           " specified");
3601         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3602                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3603                 return rte_flow_error_set(error, EINVAL,
3604                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3605                                           "can have only one fate actions in"
3606                                           " a flow");
3607         dev_priv = mlx5_dev_to_eswitch_info(dev);
3608         if (!dev_priv)
3609                 return rte_flow_error_set(error, rte_errno,
3610                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3611                                           NULL,
3612                                           "failed to obtain E-Switch info");
3613         port_id = action->conf;
3614         port = port_id->original ? dev->data->port_id : port_id->id;
3615         act_priv = mlx5_port_to_eswitch_info(port, false);
3616         if (!act_priv)
3617                 return rte_flow_error_set
3618                                 (error, rte_errno,
3619                                  RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
3620                                  "failed to obtain E-Switch port id for port");
3621         if (act_priv->domain_id != dev_priv->domain_id)
3622                 return rte_flow_error_set
3623                                 (error, EINVAL,
3624                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3625                                  "port does not belong to"
3626                                  " E-Switch being configured");
3627         return 0;
3628 }
3629
3630 /**
3631  * Get the maximum number of modify header actions.
3632  *
3633  * @param dev
3634  *   Pointer to rte_eth_dev structure.
3635  * @param flags
3636  *   Flags bits to check if root level.
3637  *
3638  * @return
3639  *   Max number of modify header actions device can support.
3640  */
3641 static unsigned int
3642 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev, uint64_t flags)
3643 {
3644         /*
3645          * There's no way to directly query the max cap. Although it has to be
3646          * acquried by iterative trial, it is a safe assumption that more
3647          * actions are supported by FW if extensive metadata register is
3648          * supported. (Only in the root table)
3649          */
3650         if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
3651                 return MLX5_MAX_MODIFY_NUM;
3652         else
3653                 return mlx5_flow_ext_mreg_supported(dev) ?
3654                                         MLX5_ROOT_TBL_MODIFY_NUM :
3655                                         MLX5_ROOT_TBL_MODIFY_NUM_NO_MREG;
3656 }
3657
3658 /**
3659  * Validate the meter action.
3660  *
3661  * @param[in] dev
3662  *   Pointer to rte_eth_dev structure.
3663  * @param[in] action_flags
3664  *   Bit-fields that holds the actions detected until now.
3665  * @param[in] action
3666  *   Pointer to the meter action.
3667  * @param[in] attr
3668  *   Attributes of flow that includes this action.
3669  * @param[out] error
3670  *   Pointer to error structure.
3671  *
3672  * @return
3673  *   0 on success, a negative errno value otherwise and rte_ernno is set.
3674  */
3675 static int
3676 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
3677                                 uint64_t action_flags,
3678                                 const struct rte_flow_action *action,
3679                                 const struct rte_flow_attr *attr,
3680                                 struct rte_flow_error *error)
3681 {
3682         struct mlx5_priv *priv = dev->data->dev_private;
3683         const struct rte_flow_action_meter *am = action->conf;
3684         struct mlx5_flow_meter *fm;
3685
3686         if (!am)
3687                 return rte_flow_error_set(error, EINVAL,
3688                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3689                                           "meter action conf is NULL");
3690
3691         if (action_flags & MLX5_FLOW_ACTION_METER)
3692                 return rte_flow_error_set(error, ENOTSUP,
3693                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3694                                           "meter chaining not support");
3695         if (action_flags & MLX5_FLOW_ACTION_JUMP)
3696                 return rte_flow_error_set(error, ENOTSUP,
3697                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3698                                           "meter with jump not support");
3699         if (!priv->mtr_en)
3700                 return rte_flow_error_set(error, ENOTSUP,
3701                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3702                                           NULL,
3703                                           "meter action not supported");
3704         fm = mlx5_flow_meter_find(priv, am->mtr_id);
3705         if (!fm)
3706                 return rte_flow_error_set(error, EINVAL,
3707                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3708                                           "Meter not found");
3709         if (fm->ref_cnt && (!(fm->attr.transfer == attr->transfer ||
3710               (!fm->attr.ingress && !attr->ingress && attr->egress) ||
3711               (!fm->attr.egress && !attr->egress && attr->ingress))))
3712                 return rte_flow_error_set(error, EINVAL,
3713                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3714                                           "Flow attributes are either invalid "
3715                                           "or have a conflict with current "
3716                                           "meter attributes");
3717         return 0;
3718 }
3719
3720 /**
3721  * Validate the modify-header IPv4 DSCP actions.
3722  *
3723  * @param[in] action_flags
3724  *   Holds the actions detected until now.
3725  * @param[in] action
3726  *   Pointer to the modify action.
3727  * @param[in] item_flags
3728  *   Holds the items detected.
3729  * @param[out] error
3730  *   Pointer to error structure.
3731  *
3732  * @return
3733  *   0 on success, a negative errno value otherwise and rte_errno is set.
3734  */
3735 static int
3736 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
3737                                          const struct rte_flow_action *action,
3738                                          const uint64_t item_flags,
3739                                          struct rte_flow_error *error)
3740 {
3741         int ret = 0;
3742
3743         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3744         if (!ret) {
3745                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
3746                         return rte_flow_error_set(error, EINVAL,
3747                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3748                                                   NULL,
3749                                                   "no ipv4 item in pattern");
3750         }
3751         return ret;
3752 }
3753
3754 /**
3755  * Validate the modify-header IPv6 DSCP actions.
3756  *
3757  * @param[in] action_flags
3758  *   Holds the actions detected until now.
3759  * @param[in] action
3760  *   Pointer to the modify action.
3761  * @param[in] item_flags
3762  *   Holds the items detected.
3763  * @param[out] error
3764  *   Pointer to error structure.
3765  *
3766  * @return
3767  *   0 on success, a negative errno value otherwise and rte_errno is set.
3768  */
3769 static int
3770 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
3771                                          const struct rte_flow_action *action,
3772                                          const uint64_t item_flags,
3773                                          struct rte_flow_error *error)
3774 {
3775         int ret = 0;
3776
3777         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3778         if (!ret) {
3779                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
3780                         return rte_flow_error_set(error, EINVAL,
3781                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3782                                                   NULL,
3783                                                   "no ipv6 item in pattern");
3784         }
3785         return ret;
3786 }
3787
3788 /**
3789  * Find existing modify-header resource or create and register a new one.
3790  *
3791  * @param dev[in, out]
3792  *   Pointer to rte_eth_dev structure.
3793  * @param[in, out] resource
3794  *   Pointer to modify-header resource.
3795  * @parm[in, out] dev_flow
3796  *   Pointer to the dev_flow.
3797  * @param[out] error
3798  *   pointer to error structure.
3799  *
3800  * @return
3801  *   0 on success otherwise -errno and errno is set.
3802  */
3803 static int
3804 flow_dv_modify_hdr_resource_register
3805                         (struct rte_eth_dev *dev,
3806                          struct mlx5_flow_dv_modify_hdr_resource *resource,
3807                          struct mlx5_flow *dev_flow,
3808                          struct rte_flow_error *error)
3809 {
3810         struct mlx5_priv *priv = dev->data->dev_private;
3811         struct mlx5_ibv_shared *sh = priv->sh;
3812         struct mlx5_flow_dv_modify_hdr_resource *cache_resource;
3813         struct mlx5dv_dr_domain *ns;
3814         uint32_t actions_len;
3815
3816         resource->flags = dev_flow->dv.group ? 0 :
3817                           MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
3818         if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
3819                                     resource->flags))
3820                 return rte_flow_error_set(error, EOVERFLOW,
3821                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3822                                           "too many modify header items");
3823         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3824                 ns = sh->fdb_domain;
3825         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
3826                 ns = sh->tx_domain;
3827         else
3828                 ns = sh->rx_domain;
3829         /* Lookup a matching resource from cache. */
3830         actions_len = resource->actions_num * sizeof(resource->actions[0]);
3831         LIST_FOREACH(cache_resource, &sh->modify_cmds, next) {
3832                 if (resource->ft_type == cache_resource->ft_type &&
3833                     resource->actions_num == cache_resource->actions_num &&
3834                     resource->flags == cache_resource->flags &&
3835                     !memcmp((const void *)resource->actions,
3836                             (const void *)cache_resource->actions,
3837                             actions_len)) {
3838                         DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d++",
3839                                 (void *)cache_resource,
3840                                 rte_atomic32_read(&cache_resource->refcnt));
3841                         rte_atomic32_inc(&cache_resource->refcnt);
3842                         dev_flow->handle->dvh.modify_hdr = cache_resource;
3843                         return 0;
3844                 }
3845         }
3846         /* Register new modify-header resource. */
3847         cache_resource = rte_calloc(__func__, 1,
3848                                     sizeof(*cache_resource) + actions_len, 0);
3849         if (!cache_resource)
3850                 return rte_flow_error_set(error, ENOMEM,
3851                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3852                                           "cannot allocate resource memory");
3853         *cache_resource = *resource;
3854         rte_memcpy(cache_resource->actions, resource->actions, actions_len);
3855         cache_resource->verbs_action =
3856                 mlx5_glue->dv_create_flow_action_modify_header
3857                                         (sh->ctx, cache_resource->ft_type, ns,
3858                                          cache_resource->flags, actions_len,
3859                                          (uint64_t *)cache_resource->actions);
3860         if (!cache_resource->verbs_action) {
3861                 rte_free(cache_resource);
3862                 return rte_flow_error_set(error, ENOMEM,
3863                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3864                                           NULL, "cannot create action");
3865         }
3866         rte_atomic32_init(&cache_resource->refcnt);
3867         rte_atomic32_inc(&cache_resource->refcnt);
3868         LIST_INSERT_HEAD(&sh->modify_cmds, cache_resource, next);
3869         dev_flow->handle->dvh.modify_hdr = cache_resource;
3870         DRV_LOG(DEBUG, "new modify-header resource %p: refcnt %d++",
3871                 (void *)cache_resource,
3872                 rte_atomic32_read(&cache_resource->refcnt));
3873         return 0;
3874 }
3875
3876 /**
3877  * Get DV flow counter by index.
3878  *
3879  * @param[in] dev
3880  *   Pointer to the Ethernet device structure.
3881  * @param[in] idx
3882  *   mlx5 flow counter index in the container.
3883  * @param[out] ppool
3884  *   mlx5 flow counter pool in the container,
3885  *
3886  * @return
3887  *   Pointer to the counter, NULL otherwise.
3888  */
3889 static struct mlx5_flow_counter *
3890 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
3891                            uint32_t idx,
3892                            struct mlx5_flow_counter_pool **ppool)
3893 {
3894         struct mlx5_priv *priv = dev->data->dev_private;
3895         struct mlx5_pools_container *cont;
3896         struct mlx5_flow_counter_pool *pool;
3897         uint32_t batch = 0;
3898
3899         idx--;
3900         if (idx >= MLX5_CNT_BATCH_OFFSET) {
3901                 idx -= MLX5_CNT_BATCH_OFFSET;
3902                 batch = 1;
3903         }
3904         cont = MLX5_CNT_CONTAINER(priv->sh, batch, 0);
3905         MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cont->n);
3906         pool = cont->pools[idx / MLX5_COUNTERS_PER_POOL];
3907         MLX5_ASSERT(pool);
3908         if (ppool)
3909                 *ppool = pool;
3910         return &pool->counters_raw[idx % MLX5_COUNTERS_PER_POOL];
3911 }
3912
3913 /**
3914  * Get a pool by devx counter ID.
3915  *
3916  * @param[in] cont
3917  *   Pointer to the counter container.
3918  * @param[in] id
3919  *   The counter devx ID.
3920  *
3921  * @return
3922  *   The counter pool pointer if exists, NULL otherwise,
3923  */
3924 static struct mlx5_flow_counter_pool *
3925 flow_dv_find_pool_by_id(struct mlx5_pools_container *cont, int id)
3926 {
3927         uint32_t i;
3928         uint32_t n_valid = rte_atomic16_read(&cont->n_valid);
3929
3930         for (i = 0; i < n_valid; i++) {
3931                 struct mlx5_flow_counter_pool *pool = cont->pools[i];
3932                 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
3933                            MLX5_COUNTERS_PER_POOL;
3934
3935                 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL) {
3936                         /*
3937                          * Move the pool to the head, as counter allocate
3938                          * always gets the first pool in the container.
3939                          */
3940                         if (pool != TAILQ_FIRST(&cont->pool_list)) {
3941                                 TAILQ_REMOVE(&cont->pool_list, pool, next);
3942                                 TAILQ_INSERT_HEAD(&cont->pool_list, pool, next);
3943                         }
3944                         return pool;
3945                 }
3946         }
3947         return NULL;
3948 }
3949
3950 /**
3951  * Allocate a new memory for the counter values wrapped by all the needed
3952  * management.
3953  *
3954  * @param[in] dev
3955  *   Pointer to the Ethernet device structure.
3956  * @param[in] raws_n
3957  *   The raw memory areas - each one for MLX5_COUNTERS_PER_POOL counters.
3958  *
3959  * @return
3960  *   The new memory management pointer on success, otherwise NULL and rte_errno
3961  *   is set.
3962  */
3963 static struct mlx5_counter_stats_mem_mng *
3964 flow_dv_create_counter_stat_mem_mng(struct rte_eth_dev *dev, int raws_n)
3965 {
3966         struct mlx5_ibv_shared *sh = ((struct mlx5_priv *)
3967                                         (dev->data->dev_private))->sh;
3968         struct mlx5_devx_mkey_attr mkey_attr;
3969         struct mlx5_counter_stats_mem_mng *mem_mng;
3970         volatile struct flow_counter_stats *raw_data;
3971         int size = (sizeof(struct flow_counter_stats) *
3972                         MLX5_COUNTERS_PER_POOL +
3973                         sizeof(struct mlx5_counter_stats_raw)) * raws_n +
3974                         sizeof(struct mlx5_counter_stats_mem_mng);
3975         uint8_t *mem = rte_calloc(__func__, 1, size, sysconf(_SC_PAGESIZE));
3976         int i;
3977
3978         if (!mem) {
3979                 rte_errno = ENOMEM;
3980                 return NULL;
3981         }
3982         mem_mng = (struct mlx5_counter_stats_mem_mng *)(mem + size) - 1;
3983         size = sizeof(*raw_data) * MLX5_COUNTERS_PER_POOL * raws_n;
3984         mem_mng->umem = mlx5_glue->devx_umem_reg(sh->ctx, mem, size,
3985                                                  IBV_ACCESS_LOCAL_WRITE);
3986         if (!mem_mng->umem) {
3987                 rte_errno = errno;
3988                 rte_free(mem);
3989                 return NULL;
3990         }
3991         mkey_attr.addr = (uintptr_t)mem;
3992         mkey_attr.size = size;
3993         mkey_attr.umem_id = mem_mng->umem->umem_id;
3994         mkey_attr.pd = sh->pdn;
3995         mkey_attr.log_entity_size = 0;
3996         mkey_attr.pg_access = 0;
3997         mkey_attr.klm_array = NULL;
3998         mkey_attr.klm_num = 0;
3999         mkey_attr.relaxed_ordering = 1;
4000         mem_mng->dm = mlx5_devx_cmd_mkey_create(sh->ctx, &mkey_attr);
4001         if (!mem_mng->dm) {
4002                 mlx5_glue->devx_umem_dereg(mem_mng->umem);
4003                 rte_errno = errno;
4004                 rte_free(mem);
4005                 return NULL;
4006         }
4007         mem_mng->raws = (struct mlx5_counter_stats_raw *)(mem + size);
4008         raw_data = (volatile struct flow_counter_stats *)mem;
4009         for (i = 0; i < raws_n; ++i) {
4010                 mem_mng->raws[i].mem_mng = mem_mng;
4011                 mem_mng->raws[i].data = raw_data + i * MLX5_COUNTERS_PER_POOL;
4012         }
4013         LIST_INSERT_HEAD(&sh->cmng.mem_mngs, mem_mng, next);
4014         return mem_mng;
4015 }
4016
4017 /**
4018  * Resize a counter container.
4019  *
4020  * @param[in] dev
4021  *   Pointer to the Ethernet device structure.
4022  * @param[in] batch
4023  *   Whether the pool is for counter that was allocated by batch command.
4024  *
4025  * @return
4026  *   The new container pointer on success, otherwise NULL and rte_errno is set.
4027  */
4028 static struct mlx5_pools_container *
4029 flow_dv_container_resize(struct rte_eth_dev *dev, uint32_t batch)
4030 {
4031         struct mlx5_priv *priv = dev->data->dev_private;
4032         struct mlx5_pools_container *cont =
4033                         MLX5_CNT_CONTAINER(priv->sh, batch, 0);
4034         struct mlx5_pools_container *new_cont =
4035                         MLX5_CNT_CONTAINER_UNUSED(priv->sh, batch, 0);
4036         struct mlx5_counter_stats_mem_mng *mem_mng = NULL;
4037         uint32_t resize = cont->n + MLX5_CNT_CONTAINER_RESIZE;
4038         uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
4039         int i;
4040
4041         /* Fallback mode has no background thread. Skip the check. */
4042         if (!priv->counter_fallback &&
4043             cont != MLX5_CNT_CONTAINER(priv->sh, batch, 1)) {
4044                 /* The last resize still hasn't detected by the host thread. */
4045                 rte_errno = EAGAIN;
4046                 return NULL;
4047         }
4048         new_cont->pools = rte_calloc(__func__, 1, mem_size, 0);
4049         if (!new_cont->pools) {
4050                 rte_errno = ENOMEM;
4051                 return NULL;
4052         }
4053         if (cont->n)
4054                 memcpy(new_cont->pools, cont->pools, cont->n *
4055                        sizeof(struct mlx5_flow_counter_pool *));
4056         /*
4057          * Fallback mode query the counter directly, no background query
4058          * resources are needed.
4059          */
4060         if (!priv->counter_fallback) {
4061                 mem_mng = flow_dv_create_counter_stat_mem_mng(dev,
4062                         MLX5_CNT_CONTAINER_RESIZE + MLX5_MAX_PENDING_QUERIES);
4063                 if (!mem_mng) {
4064                         rte_free(new_cont->pools);
4065                         return NULL;
4066                 }
4067                 for (i = 0; i < MLX5_MAX_PENDING_QUERIES; ++i)
4068                         LIST_INSERT_HEAD(&priv->sh->cmng.free_stat_raws,
4069                                          mem_mng->raws +
4070                                          MLX5_CNT_CONTAINER_RESIZE +
4071                                          i, next);
4072         } else {
4073                 /*
4074                  * Release the old container pools directly as no background
4075                  * thread helps that.
4076                  */
4077                 rte_free(cont->pools);
4078         }
4079         new_cont->n = resize;
4080         rte_atomic16_set(&new_cont->n_valid, rte_atomic16_read(&cont->n_valid));
4081         TAILQ_INIT(&new_cont->pool_list);
4082         TAILQ_CONCAT(&new_cont->pool_list, &cont->pool_list, next);
4083         new_cont->init_mem_mng = mem_mng;
4084         rte_cio_wmb();
4085          /* Flip the master container. */
4086         priv->sh->cmng.mhi[batch] ^= (uint8_t)1;
4087         return new_cont;
4088 }
4089
4090 /**
4091  * Query a devx flow counter.
4092  *
4093  * @param[in] dev
4094  *   Pointer to the Ethernet device structure.
4095  * @param[in] cnt
4096  *   Index to the flow counter.
4097  * @param[out] pkts
4098  *   The statistics value of packets.
4099  * @param[out] bytes
4100  *   The statistics value of bytes.
4101  *
4102  * @return
4103  *   0 on success, otherwise a negative errno value and rte_errno is set.
4104  */
4105 static inline int
4106 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
4107                      uint64_t *bytes)
4108 {
4109         struct mlx5_priv *priv = dev->data->dev_private;
4110         struct mlx5_flow_counter_pool *pool = NULL;
4111         struct mlx5_flow_counter *cnt;
4112         struct mlx5_flow_counter_ext *cnt_ext = NULL;
4113         int offset;
4114
4115         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
4116         MLX5_ASSERT(pool);
4117         if (counter < MLX5_CNT_BATCH_OFFSET) {
4118                 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt);
4119                 if (priv->counter_fallback)
4120                         return mlx5_devx_cmd_flow_counter_query(cnt_ext->dcs, 0,
4121                                         0, pkts, bytes, 0, NULL, NULL, 0);
4122         }
4123
4124         rte_spinlock_lock(&pool->sl);
4125         /*
4126          * The single counters allocation may allocate smaller ID than the
4127          * current allocated in parallel to the host reading.
4128          * In this case the new counter values must be reported as 0.
4129          */
4130         if (unlikely(cnt_ext && cnt_ext->dcs->id < pool->raw->min_dcs_id)) {
4131                 *pkts = 0;
4132                 *bytes = 0;
4133         } else {
4134                 offset = cnt - &pool->counters_raw[0];
4135                 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
4136                 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
4137         }
4138         rte_spinlock_unlock(&pool->sl);
4139         return 0;
4140 }
4141
4142 /**
4143  * Create and initialize a new counter pool.
4144  *
4145  * @param[in] dev
4146  *   Pointer to the Ethernet device structure.
4147  * @param[out] dcs
4148  *   The devX counter handle.
4149  * @param[in] batch
4150  *   Whether the pool is for counter that was allocated by batch command.
4151  * @param[in/out] cont_cur
4152  *   Pointer to the container pointer, it will be update in pool resize.
4153  *
4154  * @return
4155  *   The pool container pointer on success, NULL otherwise and rte_errno is set.
4156  */
4157 static struct mlx5_pools_container *
4158 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
4159                     uint32_t batch)
4160 {
4161         struct mlx5_priv *priv = dev->data->dev_private;
4162         struct mlx5_flow_counter_pool *pool;
4163         struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4164                                                                0);
4165         int16_t n_valid = rte_atomic16_read(&cont->n_valid);
4166         uint32_t size;
4167
4168         if (cont->n == n_valid) {
4169                 cont = flow_dv_container_resize(dev, batch);
4170                 if (!cont)
4171                         return NULL;
4172         }
4173         size = sizeof(*pool);
4174         if (!batch)
4175                 size += MLX5_COUNTERS_PER_POOL *
4176                         sizeof(struct mlx5_flow_counter_ext);
4177         pool = rte_calloc(__func__, 1, size, 0);
4178         if (!pool) {
4179                 rte_errno = ENOMEM;
4180                 return NULL;
4181         }
4182         pool->min_dcs = dcs;
4183         if (!priv->counter_fallback)
4184                 pool->raw = cont->init_mem_mng->raws + n_valid %
4185                                                      MLX5_CNT_CONTAINER_RESIZE;
4186         pool->raw_hw = NULL;
4187         rte_spinlock_init(&pool->sl);
4188         /*
4189          * The generation of the new allocated counters in this pool is 0, 2 in
4190          * the pool generation makes all the counters valid for allocation.
4191          * The start and end query generation protect the counters be released
4192          * between the query and update gap period will not be reallocated
4193          * without the last query finished and stats updated to the memory.
4194          */
4195         rte_atomic64_set(&pool->start_query_gen, 0x2);
4196         /*
4197          * There's no background query thread for fallback mode, set the
4198          * end_query_gen to the maximum value since no need to wait for
4199          * statistics update.
4200          */
4201         rte_atomic64_set(&pool->end_query_gen, priv->counter_fallback ?
4202                          INT64_MAX : 0x2);
4203         TAILQ_INIT(&pool->counters);
4204         TAILQ_INSERT_HEAD(&cont->pool_list, pool, next);
4205         pool->index = n_valid;
4206         cont->pools[n_valid] = pool;
4207         /* Pool initialization must be updated before host thread access. */
4208         rte_cio_wmb();
4209         rte_atomic16_add(&cont->n_valid, 1);
4210         return cont;
4211 }
4212
4213 /**
4214  * Prepare a new counter and/or a new counter pool.
4215  *
4216  * @param[in] dev
4217  *   Pointer to the Ethernet device structure.
4218  * @param[out] cnt_free
4219  *   Where to put the pointer of a new counter.
4220  * @param[in] batch
4221  *   Whether the pool is for counter that was allocated by batch command.
4222  *
4223  * @return
4224  *   The counter container pointer and @p cnt_free is set on success,
4225  *   NULL otherwise and rte_errno is set.
4226  */
4227 static struct mlx5_pools_container *
4228 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
4229                              struct mlx5_flow_counter **cnt_free,
4230                              uint32_t batch)
4231 {
4232         struct mlx5_priv *priv = dev->data->dev_private;
4233         struct mlx5_pools_container *cont;
4234         struct mlx5_flow_counter_pool *pool;
4235         struct mlx5_devx_obj *dcs = NULL;
4236         struct mlx5_flow_counter *cnt;
4237         uint32_t i;
4238
4239         cont = MLX5_CNT_CONTAINER(priv->sh, batch, 0);
4240         if (!batch) {
4241                 /* bulk_bitmap must be 0 for single counter allocation. */
4242                 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
4243                 if (!dcs)
4244                         return NULL;
4245                 pool = flow_dv_find_pool_by_id(cont, dcs->id);
4246                 if (!pool) {
4247                         cont = flow_dv_pool_create(dev, dcs, batch);
4248                         if (!cont) {
4249                                 mlx5_devx_cmd_destroy(dcs);
4250                                 return NULL;
4251                         }
4252                         pool = TAILQ_FIRST(&cont->pool_list);
4253                 } else if (dcs->id < pool->min_dcs->id) {
4254                         rte_atomic64_set(&pool->a64_dcs,
4255                                          (int64_t)(uintptr_t)dcs);
4256                 }
4257                 i = dcs->id % MLX5_COUNTERS_PER_POOL;
4258                 cnt = &pool->counters_raw[i];
4259                 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
4260                 MLX5_GET_POOL_CNT_EXT(pool, i)->dcs = dcs;
4261                 *cnt_free = cnt;
4262                 return cont;
4263         }
4264         /* bulk_bitmap is in 128 counters units. */
4265         if (priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4)
4266                 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
4267         if (!dcs) {
4268                 rte_errno = ENODATA;
4269                 return NULL;
4270         }
4271         cont = flow_dv_pool_create(dev, dcs, batch);
4272         if (!cont) {
4273                 mlx5_devx_cmd_destroy(dcs);
4274                 return NULL;
4275         }
4276         pool = TAILQ_FIRST(&cont->pool_list);
4277         for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
4278                 cnt = &pool->counters_raw[i];
4279                 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
4280         }
4281         *cnt_free = &pool->counters_raw[0];
4282         return cont;
4283 }
4284
4285 /**
4286  * Search for existed shared counter.
4287  *
4288  * @param[in] cont
4289  *   Pointer to the relevant counter pool container.
4290  * @param[in] id
4291  *   The shared counter ID to search.
4292  * @param[out] ppool
4293  *   mlx5 flow counter pool in the container,
4294  *
4295  * @return
4296  *   NULL if not existed, otherwise pointer to the shared extend counter.
4297  */
4298 static struct mlx5_flow_counter_ext *
4299 flow_dv_counter_shared_search(struct mlx5_pools_container *cont, uint32_t id,
4300                               struct mlx5_flow_counter_pool **ppool)
4301 {
4302         static struct mlx5_flow_counter_ext *cnt;
4303         struct mlx5_flow_counter_pool *pool;
4304         uint32_t i;
4305         uint32_t n_valid = rte_atomic16_read(&cont->n_valid);
4306
4307         for (i = 0; i < n_valid; i++) {
4308                 pool = cont->pools[i];
4309                 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
4310                         cnt = MLX5_GET_POOL_CNT_EXT(pool, i);
4311                         if (cnt->ref_cnt && cnt->shared && cnt->id == id) {
4312                                 if (ppool)
4313                                         *ppool = cont->pools[i];
4314                                 return cnt;
4315                         }
4316                 }
4317         }
4318         return NULL;
4319 }
4320
4321 /**
4322  * Allocate a flow counter.
4323  *
4324  * @param[in] dev
4325  *   Pointer to the Ethernet device structure.
4326  * @param[in] shared
4327  *   Indicate if this counter is shared with other flows.
4328  * @param[in] id
4329  *   Counter identifier.
4330  * @param[in] group
4331  *   Counter flow group.
4332  *
4333  * @return
4334  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
4335  */
4336 static uint32_t
4337 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t shared, uint32_t id,
4338                       uint16_t group)
4339 {
4340         struct mlx5_priv *priv = dev->data->dev_private;
4341         struct mlx5_flow_counter_pool *pool = NULL;
4342         struct mlx5_flow_counter *cnt_free = NULL;
4343         struct mlx5_flow_counter_ext *cnt_ext = NULL;
4344         /*
4345          * Currently group 0 flow counter cannot be assigned to a flow if it is
4346          * not the first one in the batch counter allocation, so it is better
4347          * to allocate counters one by one for these flows in a separate
4348          * container.
4349          * A counter can be shared between different groups so need to take
4350          * shared counters from the single container.
4351          */
4352         uint32_t batch = (group && !shared && !priv->counter_fallback) ? 1 : 0;
4353         struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4354                                                                0);
4355         uint32_t cnt_idx;
4356
4357         if (!priv->config.devx) {
4358                 rte_errno = ENOTSUP;
4359                 return 0;
4360         }
4361         if (shared) {
4362                 cnt_ext = flow_dv_counter_shared_search(cont, id, &pool);
4363                 if (cnt_ext) {
4364                         if (cnt_ext->ref_cnt + 1 == 0) {
4365                                 rte_errno = E2BIG;
4366                                 return 0;
4367                         }
4368                         cnt_ext->ref_cnt++;
4369                         cnt_idx = pool->index * MLX5_COUNTERS_PER_POOL +
4370                                   (cnt_ext->dcs->id % MLX5_COUNTERS_PER_POOL)
4371                                   + 1;
4372                         return cnt_idx;
4373                 }
4374         }
4375         /* Pools which has a free counters are in the start. */
4376         TAILQ_FOREACH(pool, &cont->pool_list, next) {
4377                 /*
4378                  * The free counter reset values must be updated between the
4379                  * counter release to the counter allocation, so, at least one
4380                  * query must be done in this time. ensure it by saving the
4381                  * query generation in the release time.
4382                  * The free list is sorted according to the generation - so if
4383                  * the first one is not updated, all the others are not
4384                  * updated too.
4385                  */
4386                 cnt_free = TAILQ_FIRST(&pool->counters);
4387                 if (cnt_free && cnt_free->query_gen <
4388                     rte_atomic64_read(&pool->end_query_gen))
4389                         break;
4390                 cnt_free = NULL;
4391         }
4392         if (!cnt_free) {
4393                 cont = flow_dv_counter_pool_prepare(dev, &cnt_free, batch);
4394                 if (!cont)
4395                         return 0;
4396                 pool = TAILQ_FIRST(&cont->pool_list);
4397         }
4398         if (!batch)
4399                 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt_free);
4400         /* Create a DV counter action only in the first time usage. */
4401         if (!cnt_free->action) {
4402                 uint16_t offset;
4403                 struct mlx5_devx_obj *dcs;
4404
4405                 if (batch) {
4406                         offset = cnt_free - &pool->counters_raw[0];
4407                         dcs = pool->min_dcs;
4408                 } else {
4409                         offset = 0;
4410                         dcs = cnt_ext->dcs;
4411                 }
4412                 cnt_free->action = mlx5_glue->dv_create_flow_action_counter
4413                                         (dcs->obj, offset);
4414                 if (!cnt_free->action) {
4415                         rte_errno = errno;
4416                         return 0;
4417                 }
4418         }
4419         cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
4420                                     (cnt_free - pool->counters_raw));
4421         cnt_idx += batch * MLX5_CNT_BATCH_OFFSET;
4422         /* Update the counter reset values. */
4423         if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
4424                                  &cnt_free->bytes))
4425                 return 0;
4426         if (cnt_ext) {
4427                 cnt_ext->shared = shared;
4428                 cnt_ext->ref_cnt = 1;
4429                 cnt_ext->id = id;
4430         }
4431         if (!priv->counter_fallback && !priv->sh->cmng.query_thread_on)
4432                 /* Start the asynchronous batch query by the host thread. */
4433                 mlx5_set_query_alarm(priv->sh);
4434         TAILQ_REMOVE(&pool->counters, cnt_free, next);
4435         if (TAILQ_EMPTY(&pool->counters)) {
4436                 /* Move the pool to the end of the container pool list. */
4437                 TAILQ_REMOVE(&cont->pool_list, pool, next);
4438                 TAILQ_INSERT_TAIL(&cont->pool_list, pool, next);
4439         }
4440         return cnt_idx;
4441 }
4442
4443 /**
4444  * Release a flow counter.
4445  *
4446  * @param[in] dev
4447  *   Pointer to the Ethernet device structure.
4448  * @param[in] counter
4449  *   Index to the counter handler.
4450  */
4451 static void
4452 flow_dv_counter_release(struct rte_eth_dev *dev, uint32_t counter)
4453 {
4454         struct mlx5_flow_counter_pool *pool = NULL;
4455         struct mlx5_flow_counter *cnt;
4456         struct mlx5_flow_counter_ext *cnt_ext = NULL;
4457
4458         if (!counter)
4459                 return;
4460         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
4461         MLX5_ASSERT(pool);
4462         if (counter < MLX5_CNT_BATCH_OFFSET) {
4463                 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt);
4464                 if (cnt_ext && --cnt_ext->ref_cnt)
4465                         return;
4466         }
4467         /* Put the counter in the end - the last updated one. */
4468         TAILQ_INSERT_TAIL(&pool->counters, cnt, next);
4469         /*
4470          * Counters released between query trigger and handler need
4471          * to wait the next round of query. Since the packets arrive
4472          * in the gap period will not be taken into account to the
4473          * old counter.
4474          */
4475         cnt->query_gen = rte_atomic64_read(&pool->start_query_gen);
4476 }
4477
4478 /**
4479  * Verify the @p attributes will be correctly understood by the NIC and store
4480  * them in the @p flow if everything is correct.
4481  *
4482  * @param[in] dev
4483  *   Pointer to dev struct.
4484  * @param[in] attributes
4485  *   Pointer to flow attributes
4486  * @param[in] external
4487  *   This flow rule is created by request external to PMD.
4488  * @param[out] error
4489  *   Pointer to error structure.
4490  *
4491  * @return
4492  *   0 on success, a negative errno value otherwise and rte_errno is set.
4493  */
4494 static int
4495 flow_dv_validate_attributes(struct rte_eth_dev *dev,
4496                             const struct rte_flow_attr *attributes,
4497                             bool external __rte_unused,
4498                             struct rte_flow_error *error)
4499 {
4500         struct mlx5_priv *priv = dev->data->dev_private;
4501         uint32_t priority_max = priv->config.flow_prio - 1;
4502
4503 #ifndef HAVE_MLX5DV_DR
4504         if (attributes->group)
4505                 return rte_flow_error_set(error, ENOTSUP,
4506                                           RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
4507                                           NULL,
4508                                           "groups are not supported");
4509 #else
4510         uint32_t table;
4511         int ret;
4512
4513         ret = mlx5_flow_group_to_table(attributes, external,
4514                                        attributes->group, !!priv->fdb_def_rule,
4515                                        &table, error);
4516         if (ret)
4517                 return ret;
4518 #endif
4519         if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
4520             attributes->priority >= priority_max)
4521                 return rte_flow_error_set(error, ENOTSUP,
4522                                           RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
4523                                           NULL,
4524                                           "priority out of range");
4525         if (attributes->transfer) {
4526                 if (!priv->config.dv_esw_en)
4527                         return rte_flow_error_set
4528                                 (error, ENOTSUP,
4529                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4530                                  "E-Switch dr is not supported");
4531                 if (!(priv->representor || priv->master))
4532                         return rte_flow_error_set
4533                                 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4534                                  NULL, "E-Switch configuration can only be"
4535                                  " done by a master or a representor device");
4536                 if (attributes->egress)
4537                         return rte_flow_error_set
4538                                 (error, ENOTSUP,
4539                                  RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
4540                                  "egress is not supported");
4541         }
4542         if (!(attributes->egress ^ attributes->ingress))
4543                 return rte_flow_error_set(error, ENOTSUP,
4544                                           RTE_FLOW_ERROR_TYPE_ATTR, NULL,
4545                                           "must specify exactly one of "
4546                                           "ingress or egress");
4547         return 0;
4548 }
4549
4550 /**
4551  * Internal validation function. For validating both actions and items.
4552  *
4553  * @param[in] dev
4554  *   Pointer to the rte_eth_dev structure.
4555  * @param[in] attr
4556  *   Pointer to the flow attributes.
4557  * @param[in] items
4558  *   Pointer to the list of items.
4559  * @param[in] actions
4560  *   Pointer to the list of actions.
4561  * @param[in] external
4562  *   This flow rule is created by request external to PMD.
4563  * @param[out] error
4564  *   Pointer to the error structure.
4565  *
4566  * @return
4567  *   0 on success, a negative errno value otherwise and rte_errno is set.
4568  */
4569 static int
4570 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
4571                  const struct rte_flow_item items[],
4572                  const struct rte_flow_action actions[],
4573                  bool external, struct rte_flow_error *error)
4574 {
4575         int ret;
4576         uint64_t action_flags = 0;
4577         uint64_t item_flags = 0;
4578         uint64_t last_item = 0;
4579         uint8_t next_protocol = 0xff;
4580         uint16_t ether_type = 0;
4581         int actions_n = 0;
4582         uint8_t item_ipv6_proto = 0;
4583         const struct rte_flow_item *gre_item = NULL;
4584         const struct rte_flow_action_raw_decap *decap;
4585         const struct rte_flow_action_raw_encap *encap;
4586         const struct rte_flow_action_rss *rss;
4587         const struct rte_flow_item_tcp nic_tcp_mask = {
4588                 .hdr = {
4589                         .tcp_flags = 0xFF,
4590                         .src_port = RTE_BE16(UINT16_MAX),
4591                         .dst_port = RTE_BE16(UINT16_MAX),
4592                 }
4593         };
4594         const struct rte_flow_item_ipv4 nic_ipv4_mask = {
4595                 .hdr = {
4596                         .src_addr = RTE_BE32(0xffffffff),
4597                         .dst_addr = RTE_BE32(0xffffffff),
4598                         .type_of_service = 0xff,
4599                         .next_proto_id = 0xff,
4600                         .time_to_live = 0xff,
4601                 },
4602         };
4603         const struct rte_flow_item_ipv6 nic_ipv6_mask = {
4604                 .hdr = {
4605                         .src_addr =
4606                         "\xff\xff\xff\xff\xff\xff\xff\xff"
4607                         "\xff\xff\xff\xff\xff\xff\xff\xff",
4608                         .dst_addr =
4609                         "\xff\xff\xff\xff\xff\xff\xff\xff"
4610                         "\xff\xff\xff\xff\xff\xff\xff\xff",
4611                         .vtc_flow = RTE_BE32(0xffffffff),
4612                         .proto = 0xff,
4613                         .hop_limits = 0xff,
4614                 },
4615         };
4616         struct mlx5_priv *priv = dev->data->dev_private;
4617         struct mlx5_dev_config *dev_conf = &priv->config;
4618         uint16_t queue_index = 0xFFFF;
4619         const struct rte_flow_item_vlan *vlan_m = NULL;
4620
4621         if (items == NULL)
4622                 return -1;
4623         ret = flow_dv_validate_attributes(dev, attr, external, error);
4624         if (ret < 0)
4625                 return ret;
4626         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
4627                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
4628                 int type = items->type;
4629
4630                 switch (type) {
4631                 case RTE_FLOW_ITEM_TYPE_VOID:
4632                         break;
4633                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
4634                         ret = flow_dv_validate_item_port_id
4635                                         (dev, items, attr, item_flags, error);
4636                         if (ret < 0)
4637                                 return ret;
4638                         last_item = MLX5_FLOW_ITEM_PORT_ID;
4639                         break;
4640                 case RTE_FLOW_ITEM_TYPE_ETH:
4641                         ret = mlx5_flow_validate_item_eth(items, item_flags,
4642                                                           error);
4643                         if (ret < 0)
4644                                 return ret;
4645                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
4646                                              MLX5_FLOW_LAYER_OUTER_L2;
4647                         if (items->mask != NULL && items->spec != NULL) {
4648                                 ether_type =
4649                                         ((const struct rte_flow_item_eth *)
4650                                          items->spec)->type;
4651                                 ether_type &=
4652                                         ((const struct rte_flow_item_eth *)
4653                                          items->mask)->type;
4654                                 ether_type = rte_be_to_cpu_16(ether_type);
4655                         } else {
4656                                 ether_type = 0;
4657                         }
4658                         break;
4659                 case RTE_FLOW_ITEM_TYPE_VLAN:
4660                         ret = mlx5_flow_validate_item_vlan(items, item_flags,
4661                                                            dev, error);
4662                         if (ret < 0)
4663                                 return ret;
4664                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
4665                                              MLX5_FLOW_LAYER_OUTER_VLAN;
4666                         if (items->mask != NULL && items->spec != NULL) {
4667                                 ether_type =
4668                                         ((const struct rte_flow_item_vlan *)
4669                                          items->spec)->inner_type;
4670                                 ether_type &=
4671                                         ((const struct rte_flow_item_vlan *)
4672                                          items->mask)->inner_type;
4673                                 ether_type = rte_be_to_cpu_16(ether_type);
4674                         } else {
4675                                 ether_type = 0;
4676                         }
4677                         /* Store outer VLAN mask for of_push_vlan action. */
4678                         if (!tunnel)
4679                                 vlan_m = items->mask;
4680                         break;
4681                 case RTE_FLOW_ITEM_TYPE_IPV4:
4682                         mlx5_flow_tunnel_ip_check(items, next_protocol,
4683                                                   &item_flags, &tunnel);
4684                         ret = mlx5_flow_validate_item_ipv4(items, item_flags,
4685                                                            last_item,
4686                                                            ether_type,
4687                                                            &nic_ipv4_mask,
4688                                                            error);
4689                         if (ret < 0)
4690                                 return ret;
4691                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
4692                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
4693                         if (items->mask != NULL &&
4694                             ((const struct rte_flow_item_ipv4 *)
4695                              items->mask)->hdr.next_proto_id) {
4696                                 next_protocol =
4697                                         ((const struct rte_flow_item_ipv4 *)
4698                                          (items->spec))->hdr.next_proto_id;
4699                                 next_protocol &=
4700                                         ((const struct rte_flow_item_ipv4 *)
4701                                          (items->mask))->hdr.next_proto_id;
4702                         } else {
4703                                 /* Reset for inner layer. */
4704                                 next_protocol = 0xff;
4705                         }
4706                         break;
4707                 case RTE_FLOW_ITEM_TYPE_IPV6:
4708                         mlx5_flow_tunnel_ip_check(items, next_protocol,
4709                                                   &item_flags, &tunnel);
4710                         ret = mlx5_flow_validate_item_ipv6(items, item_flags,
4711                                                            last_item,
4712                                                            ether_type,
4713                                                            &nic_ipv6_mask,
4714                                                            error);
4715                         if (ret < 0)
4716                                 return ret;
4717                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
4718                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
4719                         if (items->mask != NULL &&
4720                             ((const struct rte_flow_item_ipv6 *)
4721                              items->mask)->hdr.proto) {
4722                                 item_ipv6_proto =
4723                                         ((const struct rte_flow_item_ipv6 *)
4724                                          items->spec)->hdr.proto;
4725                                 next_protocol =
4726                                         ((const struct rte_flow_item_ipv6 *)
4727                                          items->spec)->hdr.proto;
4728                                 next_protocol &=
4729                                         ((const struct rte_flow_item_ipv6 *)
4730                                          items->mask)->hdr.proto;
4731                         } else {
4732                                 /* Reset for inner layer. */
4733                                 next_protocol = 0xff;
4734                         }
4735                         break;
4736                 case RTE_FLOW_ITEM_TYPE_TCP:
4737                         ret = mlx5_flow_validate_item_tcp
4738                                                 (items, item_flags,
4739                                                  next_protocol,
4740                                                  &nic_tcp_mask,
4741                                                  error);
4742                         if (ret < 0)
4743                                 return ret;
4744                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
4745                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
4746                         break;
4747                 case RTE_FLOW_ITEM_TYPE_UDP:
4748                         ret = mlx5_flow_validate_item_udp(items, item_flags,
4749                                                           next_protocol,
4750                                                           error);
4751                         if (ret < 0)
4752                                 return ret;
4753                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
4754                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
4755                         break;
4756                 case RTE_FLOW_ITEM_TYPE_GRE:
4757                         ret = mlx5_flow_validate_item_gre(items, item_flags,
4758                                                           next_protocol, error);
4759                         if (ret < 0)
4760                                 return ret;
4761                         gre_item = items;
4762                         last_item = MLX5_FLOW_LAYER_GRE;
4763                         break;
4764                 case RTE_FLOW_ITEM_TYPE_NVGRE:
4765                         ret = mlx5_flow_validate_item_nvgre(items, item_flags,
4766                                                             next_protocol,
4767                                                             error);
4768                         if (ret < 0)
4769                                 return ret;
4770                         last_item = MLX5_FLOW_LAYER_NVGRE;
4771                         break;
4772                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
4773                         ret = mlx5_flow_validate_item_gre_key
4774                                 (items, item_flags, gre_item, error);
4775                         if (ret < 0)
4776                                 return ret;
4777                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
4778                         break;
4779                 case RTE_FLOW_ITEM_TYPE_VXLAN:
4780                         ret = mlx5_flow_validate_item_vxlan(items, item_flags,
4781                                                             error);
4782                         if (ret < 0)
4783                                 return ret;
4784                         last_item = MLX5_FLOW_LAYER_VXLAN;
4785                         break;
4786                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
4787                         ret = mlx5_flow_validate_item_vxlan_gpe(items,
4788                                                                 item_flags, dev,
4789                                                                 error);
4790                         if (ret < 0)
4791                                 return ret;
4792                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
4793                         break;
4794                 case RTE_FLOW_ITEM_TYPE_GENEVE:
4795                         ret = mlx5_flow_validate_item_geneve(items,
4796                                                              item_flags, dev,
4797                                                              error);
4798                         if (ret < 0)
4799                                 return ret;
4800                         last_item = MLX5_FLOW_LAYER_GENEVE;
4801                         break;
4802                 case RTE_FLOW_ITEM_TYPE_MPLS:
4803                         ret = mlx5_flow_validate_item_mpls(dev, items,
4804                                                            item_flags,
4805                                                            last_item, error);
4806                         if (ret < 0)
4807                                 return ret;
4808                         last_item = MLX5_FLOW_LAYER_MPLS;
4809                         break;
4810
4811                 case RTE_FLOW_ITEM_TYPE_MARK:
4812                         ret = flow_dv_validate_item_mark(dev, items, attr,
4813                                                          error);
4814                         if (ret < 0)
4815                                 return ret;
4816                         last_item = MLX5_FLOW_ITEM_MARK;
4817                         break;
4818                 case RTE_FLOW_ITEM_TYPE_META:
4819                         ret = flow_dv_validate_item_meta(dev, items, attr,
4820                                                          error);
4821                         if (ret < 0)
4822                                 return ret;
4823                         last_item = MLX5_FLOW_ITEM_METADATA;
4824                         break;
4825                 case RTE_FLOW_ITEM_TYPE_ICMP:
4826                         ret = mlx5_flow_validate_item_icmp(items, item_flags,
4827                                                            next_protocol,
4828                                                            error);
4829                         if (ret < 0)
4830                                 return ret;
4831                         last_item = MLX5_FLOW_LAYER_ICMP;
4832                         break;
4833                 case RTE_FLOW_ITEM_TYPE_ICMP6:
4834                         ret = mlx5_flow_validate_item_icmp6(items, item_flags,
4835                                                             next_protocol,
4836                                                             error);
4837                         if (ret < 0)
4838                                 return ret;
4839                         item_ipv6_proto = IPPROTO_ICMPV6;
4840                         last_item = MLX5_FLOW_LAYER_ICMP6;
4841                         break;
4842                 case RTE_FLOW_ITEM_TYPE_TAG:
4843                         ret = flow_dv_validate_item_tag(dev, items,
4844                                                         attr, error);
4845                         if (ret < 0)
4846                                 return ret;
4847                         last_item = MLX5_FLOW_ITEM_TAG;
4848                         break;
4849                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
4850                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
4851                         break;
4852                 case RTE_FLOW_ITEM_TYPE_GTP:
4853                         ret = flow_dv_validate_item_gtp(dev, items, item_flags,
4854                                                         error);
4855                         if (ret < 0)
4856                                 return ret;
4857                         last_item = MLX5_FLOW_LAYER_GTP;
4858                         break;
4859                 default:
4860                         return rte_flow_error_set(error, ENOTSUP,
4861                                                   RTE_FLOW_ERROR_TYPE_ITEM,
4862                                                   NULL, "item not supported");
4863                 }
4864                 item_flags |= last_item;
4865         }
4866         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
4867                 int type = actions->type;
4868                 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
4869                         return rte_flow_error_set(error, ENOTSUP,
4870                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4871                                                   actions, "too many actions");
4872                 switch (type) {
4873                 case RTE_FLOW_ACTION_TYPE_VOID:
4874                         break;
4875                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
4876                         ret = flow_dv_validate_action_port_id(dev,
4877                                                               action_flags,
4878                                                               actions,
4879                                                               attr,
4880                                                               error);
4881                         if (ret)
4882                                 return ret;
4883                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
4884                         ++actions_n;
4885                         break;
4886                 case RTE_FLOW_ACTION_TYPE_FLAG:
4887                         ret = flow_dv_validate_action_flag(dev, action_flags,
4888                                                            attr, error);
4889                         if (ret < 0)
4890                                 return ret;
4891                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
4892                                 /* Count all modify-header actions as one. */
4893                                 if (!(action_flags &
4894                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
4895                                         ++actions_n;
4896                                 action_flags |= MLX5_FLOW_ACTION_FLAG |
4897                                                 MLX5_FLOW_ACTION_MARK_EXT;
4898                         } else {
4899                                 action_flags |= MLX5_FLOW_ACTION_FLAG;
4900                                 ++actions_n;
4901                         }
4902                         break;
4903                 case RTE_FLOW_ACTION_TYPE_MARK:
4904                         ret = flow_dv_validate_action_mark(dev, actions,
4905                                                            action_flags,
4906                                                            attr, error);
4907                         if (ret < 0)
4908                                 return ret;
4909                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
4910                                 /* Count all modify-header actions as one. */
4911                                 if (!(action_flags &
4912                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
4913                                         ++actions_n;
4914                                 action_flags |= MLX5_FLOW_ACTION_MARK |
4915                                                 MLX5_FLOW_ACTION_MARK_EXT;
4916                         } else {
4917                                 action_flags |= MLX5_FLOW_ACTION_MARK;
4918                                 ++actions_n;
4919                         }
4920                         break;
4921                 case RTE_FLOW_ACTION_TYPE_SET_META:
4922                         ret = flow_dv_validate_action_set_meta(dev, actions,
4923                                                                action_flags,
4924                                                                attr, error);
4925                         if (ret < 0)
4926                                 return ret;
4927                         /* Count all modify-header actions as one action. */
4928                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4929                                 ++actions_n;
4930                         action_flags |= MLX5_FLOW_ACTION_SET_META;
4931                         break;
4932                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
4933                         ret = flow_dv_validate_action_set_tag(dev, actions,
4934                                                               action_flags,
4935                                                               attr, error);
4936                         if (ret < 0)
4937                                 return ret;
4938                         /* Count all modify-header actions as one action. */
4939                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4940                                 ++actions_n;
4941                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
4942                         break;
4943                 case RTE_FLOW_ACTION_TYPE_DROP:
4944                         ret = mlx5_flow_validate_action_drop(action_flags,
4945                                                              attr, error);
4946                         if (ret < 0)
4947                                 return ret;
4948                         action_flags |= MLX5_FLOW_ACTION_DROP;
4949                         ++actions_n;
4950                         break;
4951                 case RTE_FLOW_ACTION_TYPE_QUEUE:
4952                         ret = mlx5_flow_validate_action_queue(actions,
4953                                                               action_flags, dev,
4954                                                               attr, error);
4955                         if (ret < 0)
4956                                 return ret;
4957                         queue_index = ((const struct rte_flow_action_queue *)
4958                                                         (actions->conf))->index;
4959                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
4960                         ++actions_n;
4961                         break;
4962                 case RTE_FLOW_ACTION_TYPE_RSS:
4963                         rss = actions->conf;
4964                         ret = mlx5_flow_validate_action_rss(actions,
4965                                                             action_flags, dev,
4966                                                             attr, item_flags,
4967                                                             error);
4968                         if (ret < 0)
4969                                 return ret;
4970                         if (rss != NULL && rss->queue_num)
4971                                 queue_index = rss->queue[0];
4972                         action_flags |= MLX5_FLOW_ACTION_RSS;
4973                         ++actions_n;
4974                         break;
4975                 case RTE_FLOW_ACTION_TYPE_COUNT:
4976                         ret = flow_dv_validate_action_count(dev, error);
4977                         if (ret < 0)
4978                                 return ret;
4979                         action_flags |= MLX5_FLOW_ACTION_COUNT;
4980                         ++actions_n;
4981                         break;
4982                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
4983                         if (flow_dv_validate_action_pop_vlan(dev,
4984                                                              action_flags,
4985                                                              actions,
4986                                                              item_flags, attr,
4987                                                              error))
4988                                 return -rte_errno;
4989                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
4990                         ++actions_n;
4991                         break;
4992                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
4993                         ret = flow_dv_validate_action_push_vlan(dev,
4994                                                                 action_flags,
4995                                                                 vlan_m,
4996                                                                 actions, attr,
4997                                                                 error);
4998                         if (ret < 0)
4999                                 return ret;
5000                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
5001                         ++actions_n;
5002                         break;
5003                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
5004                         ret = flow_dv_validate_action_set_vlan_pcp
5005                                                 (action_flags, actions, error);
5006                         if (ret < 0)
5007                                 return ret;
5008                         /* Count PCP with push_vlan command. */
5009                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
5010                         break;
5011                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
5012                         ret = flow_dv_validate_action_set_vlan_vid
5013                                                 (item_flags, action_flags,
5014                                                  actions, error);
5015                         if (ret < 0)
5016                                 return ret;
5017                         /* Count VID with push_vlan command. */
5018                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
5019                         break;
5020                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5021                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5022                         ret = flow_dv_validate_action_l2_encap(dev,
5023                                                                action_flags,
5024                                                                actions, attr,
5025                                                                error);
5026                         if (ret < 0)
5027                                 return ret;
5028                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
5029                         ++actions_n;
5030                         break;
5031                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
5032                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
5033                         ret = flow_dv_validate_action_decap(dev, action_flags,
5034                                                             attr, error);
5035                         if (ret < 0)
5036                                 return ret;
5037                         action_flags |= MLX5_FLOW_ACTION_DECAP;
5038                         ++actions_n;
5039                         break;
5040                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5041                         ret = flow_dv_validate_action_raw_encap_decap
5042                                 (dev, NULL, actions->conf, attr, &action_flags,
5043                                  &actions_n, error);
5044                         if (ret < 0)
5045                                 return ret;
5046                         break;
5047                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
5048                         decap = actions->conf;
5049                         while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
5050                                 ;
5051                         if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
5052                                 encap = NULL;
5053                                 actions--;
5054                         } else {
5055                                 encap = actions->conf;
5056                         }
5057                         ret = flow_dv_validate_action_raw_encap_decap
5058                                            (dev,
5059                                             decap ? decap : &empty_decap, encap,
5060                                             attr, &action_flags, &actions_n,
5061                                             error);
5062                         if (ret < 0)
5063                                 return ret;
5064                         break;
5065                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
5066                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
5067                         ret = flow_dv_validate_action_modify_mac(action_flags,
5068                                                                  actions,
5069                                                                  item_flags,
5070                                                                  error);
5071                         if (ret < 0)
5072                                 return ret;
5073                         /* Count all modify-header actions as one action. */
5074                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5075                                 ++actions_n;
5076                         action_flags |= actions->type ==
5077                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
5078                                                 MLX5_FLOW_ACTION_SET_MAC_SRC :
5079                                                 MLX5_FLOW_ACTION_SET_MAC_DST;
5080                         break;
5081
5082                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
5083                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
5084                         ret = flow_dv_validate_action_modify_ipv4(action_flags,
5085                                                                   actions,
5086                                                                   item_flags,
5087                                                                   error);
5088                         if (ret < 0)
5089                                 return ret;
5090                         /* Count all modify-header actions as one action. */
5091                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5092                                 ++actions_n;
5093                         action_flags |= actions->type ==
5094                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
5095                                                 MLX5_FLOW_ACTION_SET_IPV4_SRC :
5096                                                 MLX5_FLOW_ACTION_SET_IPV4_DST;
5097                         break;
5098                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
5099                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
5100                         ret = flow_dv_validate_action_modify_ipv6(action_flags,
5101                                                                   actions,
5102                                                                   item_flags,
5103                                                                   error);
5104                         if (ret < 0)
5105                                 return ret;
5106                         if (item_ipv6_proto == IPPROTO_ICMPV6)
5107                                 return rte_flow_error_set(error, ENOTSUP,
5108                                         RTE_FLOW_ERROR_TYPE_ACTION,
5109                                         actions,
5110                                         "Can't change header "
5111                                         "with ICMPv6 proto");
5112                         /* Count all modify-header actions as one action. */
5113                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5114                                 ++actions_n;
5115                         action_flags |= actions->type ==
5116                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
5117                                                 MLX5_FLOW_ACTION_SET_IPV6_SRC :
5118                                                 MLX5_FLOW_ACTION_SET_IPV6_DST;
5119                         break;
5120                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
5121                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
5122                         ret = flow_dv_validate_action_modify_tp(action_flags,
5123                                                                 actions,
5124                                                                 item_flags,
5125                                                                 error);
5126                         if (ret < 0)
5127                                 return ret;
5128                         /* Count all modify-header actions as one action. */
5129                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5130                                 ++actions_n;
5131                         action_flags |= actions->type ==
5132                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
5133                                                 MLX5_FLOW_ACTION_SET_TP_SRC :
5134                                                 MLX5_FLOW_ACTION_SET_TP_DST;
5135                         break;
5136                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
5137                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
5138                         ret = flow_dv_validate_action_modify_ttl(action_flags,
5139                                                                  actions,
5140                                                                  item_flags,
5141                                                                  error);
5142                         if (ret < 0)
5143                                 return ret;
5144                         /* Count all modify-header actions as one action. */
5145                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5146                                 ++actions_n;
5147                         action_flags |= actions->type ==
5148                                         RTE_FLOW_ACTION_TYPE_SET_TTL ?
5149                                                 MLX5_FLOW_ACTION_SET_TTL :
5150                                                 MLX5_FLOW_ACTION_DEC_TTL;
5151                         break;
5152                 case RTE_FLOW_ACTION_TYPE_JUMP:
5153                         ret = flow_dv_validate_action_jump(actions,
5154                                                            action_flags,
5155                                                            attr, external,
5156                                                            error);
5157                         if (ret)
5158                                 return ret;
5159                         ++actions_n;
5160                         action_flags |= MLX5_FLOW_ACTION_JUMP;
5161                         break;
5162                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
5163                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
5164                         ret = flow_dv_validate_action_modify_tcp_seq
5165                                                                 (action_flags,
5166                                                                  actions,
5167                                                                  item_flags,
5168                                                                  error);
5169                         if (ret < 0)
5170                                 return ret;
5171                         /* Count all modify-header actions as one action. */
5172                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5173                                 ++actions_n;
5174                         action_flags |= actions->type ==
5175                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
5176                                                 MLX5_FLOW_ACTION_INC_TCP_SEQ :
5177                                                 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
5178                         break;
5179                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
5180                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
5181                         ret = flow_dv_validate_action_modify_tcp_ack
5182                                                                 (action_flags,
5183                                                                  actions,
5184                                                                  item_flags,
5185                                                                  error);
5186                         if (ret < 0)
5187                                 return ret;
5188                         /* Count all modify-header actions as one action. */
5189                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5190                                 ++actions_n;
5191                         action_flags |= actions->type ==
5192                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
5193                                                 MLX5_FLOW_ACTION_INC_TCP_ACK :
5194                                                 MLX5_FLOW_ACTION_DEC_TCP_ACK;
5195                         break;
5196                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
5197                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
5198                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
5199                         break;
5200                 case RTE_FLOW_ACTION_TYPE_METER:
5201                         ret = mlx5_flow_validate_action_meter(dev,
5202                                                               action_flags,
5203                                                               actions, attr,
5204                                                               error);
5205                         if (ret < 0)
5206                                 return ret;
5207                         action_flags |= MLX5_FLOW_ACTION_METER;
5208                         ++actions_n;
5209                         break;
5210                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
5211                         ret = flow_dv_validate_action_modify_ipv4_dscp
5212                                                          (action_flags,
5213                                                           actions,
5214                                                           item_flags,
5215                                                           error);
5216                         if (ret < 0)
5217                                 return ret;
5218                         /* Count all modify-header actions as one action. */
5219                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5220                                 ++actions_n;
5221                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
5222                         break;
5223                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
5224                         ret = flow_dv_validate_action_modify_ipv6_dscp
5225                                                                 (action_flags,
5226                                                                  actions,
5227                                                                  item_flags,
5228                                                                  error);
5229                         if (ret < 0)
5230                                 return ret;
5231                         /* Count all modify-header actions as one action. */
5232                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5233                                 ++actions_n;
5234                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
5235                         break;
5236                 default:
5237                         return rte_flow_error_set(error, ENOTSUP,
5238                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5239                                                   actions,
5240                                                   "action not supported");
5241                 }
5242         }
5243         /*
5244          * Validate the drop action mutual exclusion with other actions.
5245          * Drop action is mutually-exclusive with any other action, except for
5246          * Count action.
5247          */
5248         if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
5249             (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
5250                 return rte_flow_error_set(error, EINVAL,
5251                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5252                                           "Drop action is mutually-exclusive "
5253                                           "with any other action, except for "
5254                                           "Count action");
5255         /* Eswitch has few restrictions on using items and actions */
5256         if (attr->transfer) {
5257                 if (!mlx5_flow_ext_mreg_supported(dev) &&
5258                     action_flags & MLX5_FLOW_ACTION_FLAG)
5259                         return rte_flow_error_set(error, ENOTSUP,
5260                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5261                                                   NULL,
5262                                                   "unsupported action FLAG");
5263                 if (!mlx5_flow_ext_mreg_supported(dev) &&
5264                     action_flags & MLX5_FLOW_ACTION_MARK)
5265                         return rte_flow_error_set(error, ENOTSUP,
5266                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5267                                                   NULL,
5268                                                   "unsupported action MARK");
5269                 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
5270                         return rte_flow_error_set(error, ENOTSUP,
5271                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5272                                                   NULL,
5273                                                   "unsupported action QUEUE");
5274                 if (action_flags & MLX5_FLOW_ACTION_RSS)
5275                         return rte_flow_error_set(error, ENOTSUP,
5276                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5277                                                   NULL,
5278                                                   "unsupported action RSS");
5279                 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
5280                         return rte_flow_error_set(error, EINVAL,
5281                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5282                                                   actions,
5283                                                   "no fate action is found");
5284         } else {
5285                 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
5286                         return rte_flow_error_set(error, EINVAL,
5287                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5288                                                   actions,
5289                                                   "no fate action is found");
5290         }
5291         /* Continue validation for Xcap actions.*/
5292         if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) && (queue_index == 0xFFFF ||
5293             mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
5294                 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
5295                     MLX5_FLOW_XCAP_ACTIONS)
5296                         return rte_flow_error_set(error, ENOTSUP,
5297                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5298                                                   NULL, "encap and decap "
5299                                                   "combination aren't supported");
5300                 if (!attr->transfer && attr->ingress && (action_flags &
5301                                                         MLX5_FLOW_ACTION_ENCAP))
5302                         return rte_flow_error_set(error, ENOTSUP,
5303                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5304                                                   NULL, "encap is not supported"
5305                                                   " for ingress traffic");
5306         }
5307         return 0;
5308 }
5309
5310 /**
5311  * Internal preparation function. Allocates the DV flow size,
5312  * this size is constant.
5313  *
5314  * @param[in] dev
5315  *   Pointer to the rte_eth_dev structure.
5316  * @param[in] attr
5317  *   Pointer to the flow attributes.
5318  * @param[in] items
5319  *   Pointer to the list of items.
5320  * @param[in] actions
5321  *   Pointer to the list of actions.
5322  * @param[out] error
5323  *   Pointer to the error structure.
5324  *
5325  * @return
5326  *   Pointer to mlx5_flow object on success,
5327  *   otherwise NULL and rte_errno is set.
5328  */
5329 static struct mlx5_flow *
5330 flow_dv_prepare(struct rte_eth_dev *dev,
5331                 const struct rte_flow_attr *attr __rte_unused,
5332                 const struct rte_flow_item items[] __rte_unused,
5333                 const struct rte_flow_action actions[] __rte_unused,
5334                 struct rte_flow_error *error)
5335 {
5336         uint32_t handle_idx = 0;
5337         struct mlx5_flow *dev_flow;
5338         struct mlx5_flow_handle *dev_handle;
5339         struct mlx5_priv *priv = dev->data->dev_private;
5340
5341         /* In case of corrupting the memory. */
5342         if (priv->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
5343                 rte_flow_error_set(error, ENOSPC,
5344                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5345                                    "not free temporary device flow");
5346                 return NULL;
5347         }
5348         dev_handle = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
5349                                    &handle_idx);
5350         if (!dev_handle) {
5351                 rte_flow_error_set(error, ENOMEM,
5352                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5353                                    "not enough memory to create flow handle");
5354                 return NULL;
5355         }
5356         /* No multi-thread supporting. */
5357         dev_flow = &((struct mlx5_flow *)priv->inter_flows)[priv->flow_idx++];
5358         dev_flow->handle = dev_handle;
5359         dev_flow->handle_idx = handle_idx;
5360         dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);
5361         /*
5362          * The matching value needs to be cleared to 0 before using. In the
5363          * past, it will be automatically cleared when using rte_*alloc
5364          * API. The time consumption will be almost the same as before.
5365          */
5366         memset(dev_flow->dv.value.buf, 0, MLX5_ST_SZ_BYTES(fte_match_param));
5367         dev_flow->ingress = attr->ingress;
5368         dev_flow->dv.transfer = attr->transfer;
5369         return dev_flow;
5370 }
5371
5372 #ifdef RTE_LIBRTE_MLX5_DEBUG
5373 /**
5374  * Sanity check for match mask and value. Similar to check_valid_spec() in
5375  * kernel driver. If unmasked bit is present in value, it returns failure.
5376  *
5377  * @param match_mask
5378  *   pointer to match mask buffer.
5379  * @param match_value
5380  *   pointer to match value buffer.
5381  *
5382  * @return
5383  *   0 if valid, -EINVAL otherwise.
5384  */
5385 static int
5386 flow_dv_check_valid_spec(void *match_mask, void *match_value)
5387 {
5388         uint8_t *m = match_mask;
5389         uint8_t *v = match_value;
5390         unsigned int i;
5391
5392         for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
5393                 if (v[i] & ~m[i]) {
5394                         DRV_LOG(ERR,
5395                                 "match_value differs from match_criteria"
5396                                 " %p[%u] != %p[%u]",
5397                                 match_value, i, match_mask, i);
5398                         return -EINVAL;
5399                 }
5400         }
5401         return 0;
5402 }
5403 #endif
5404
5405 /**
5406  * Add Ethernet item to matcher and to the value.
5407  *
5408  * @param[in, out] matcher
5409  *   Flow matcher.
5410  * @param[in, out] key
5411  *   Flow matcher value.
5412  * @param[in] item
5413  *   Flow pattern to translate.
5414  * @param[in] inner
5415  *   Item is inner pattern.
5416  */
5417 static void
5418 flow_dv_translate_item_eth(void *matcher, void *key,
5419                            const struct rte_flow_item *item, int inner)
5420 {
5421         const struct rte_flow_item_eth *eth_m = item->mask;
5422         const struct rte_flow_item_eth *eth_v = item->spec;
5423         const struct rte_flow_item_eth nic_mask = {
5424                 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5425                 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5426                 .type = RTE_BE16(0xffff),
5427         };
5428         void *headers_m;
5429         void *headers_v;
5430         char *l24_v;
5431         unsigned int i;
5432
5433         if (!eth_v)
5434                 return;
5435         if (!eth_m)
5436                 eth_m = &nic_mask;
5437         if (inner) {
5438                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5439                                          inner_headers);
5440                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5441         } else {
5442                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5443                                          outer_headers);
5444                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5445         }
5446         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, dmac_47_16),
5447                &eth_m->dst, sizeof(eth_m->dst));
5448         /* The value must be in the range of the mask. */
5449         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, dmac_47_16);
5450         for (i = 0; i < sizeof(eth_m->dst); ++i)
5451                 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
5452         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, smac_47_16),
5453                &eth_m->src, sizeof(eth_m->src));
5454         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, smac_47_16);
5455         /* The value must be in the range of the mask. */
5456         for (i = 0; i < sizeof(eth_m->dst); ++i)
5457                 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
5458         if (eth_v->type) {
5459                 /* When ethertype is present set mask for tagged VLAN. */
5460                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5461                 /* Set value for tagged VLAN if ethertype is 802.1Q. */
5462                 if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_VLAN) ||
5463                     eth_v->type == RTE_BE16(RTE_ETHER_TYPE_QINQ)) {
5464                         MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag,
5465                                  1);
5466                         /* Return here to avoid setting match on ethertype. */
5467                         return;
5468                 }
5469         }
5470         /*
5471          * HW supports match on one Ethertype, the Ethertype following the last
5472          * VLAN tag of the packet (see PRM).
5473          * Set match on ethertype only if ETH header is not followed by VLAN.
5474          */
5475         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
5476                  rte_be_to_cpu_16(eth_m->type));
5477         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, ethertype);
5478         *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
5479 }
5480
5481 /**
5482  * Add VLAN item to matcher and to the value.
5483  *
5484  * @param[in, out] dev_flow
5485  *   Flow descriptor.
5486  * @param[in, out] matcher
5487  *   Flow matcher.
5488  * @param[in, out] key
5489  *   Flow matcher value.
5490  * @param[in] item
5491  *   Flow pattern to translate.
5492  * @param[in] inner
5493  *   Item is inner pattern.
5494  */
5495 static void
5496 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
5497                             void *matcher, void *key,
5498                             const struct rte_flow_item *item,
5499                             int inner)
5500 {
5501         const struct rte_flow_item_vlan *vlan_m = item->mask;
5502         const struct rte_flow_item_vlan *vlan_v = item->spec;
5503         void *headers_m;
5504         void *headers_v;
5505         uint16_t tci_m;
5506         uint16_t tci_v;
5507
5508         if (!vlan_v)
5509                 return;
5510         if (!vlan_m)
5511                 vlan_m = &rte_flow_item_vlan_mask;
5512         if (inner) {
5513                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5514                                          inner_headers);
5515                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5516         } else {
5517                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5518                                          outer_headers);
5519                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5520                 /*
5521                  * This is workaround, masks are not supported,
5522                  * and pre-validated.
5523                  */
5524                 dev_flow->handle->vf_vlan.tag =
5525                         rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
5526         }
5527         tci_m = rte_be_to_cpu_16(vlan_m->tci);
5528         tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
5529         MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5530         MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
5531         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_vid, tci_m);
5532         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, tci_v);
5533         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_cfi, tci_m >> 12);
5534         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_cfi, tci_v >> 12);
5535         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_prio, tci_m >> 13);
5536         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, tci_v >> 13);
5537         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
5538                  rte_be_to_cpu_16(vlan_m->inner_type));
5539         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
5540                  rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
5541 }
5542
5543 /**
5544  * Add IPV4 item to matcher and to the value.
5545  *
5546  * @param[in, out] matcher
5547  *   Flow matcher.
5548  * @param[in, out] key
5549  *   Flow matcher value.
5550  * @param[in] item
5551  *   Flow pattern to translate.
5552  * @param[in] item_flags
5553  *   Bit-fields that holds the items detected until now.
5554  * @param[in] inner
5555  *   Item is inner pattern.
5556  * @param[in] group
5557  *   The group to insert the rule.
5558  */
5559 static void
5560 flow_dv_translate_item_ipv4(void *matcher, void *key,
5561                             const struct rte_flow_item *item,
5562                             const uint64_t item_flags,
5563                             int inner, uint32_t group)
5564 {
5565         const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
5566         const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
5567         const struct rte_flow_item_ipv4 nic_mask = {
5568                 .hdr = {
5569                         .src_addr = RTE_BE32(0xffffffff),
5570                         .dst_addr = RTE_BE32(0xffffffff),
5571                         .type_of_service = 0xff,
5572                         .next_proto_id = 0xff,
5573                         .time_to_live = 0xff,
5574                 },
5575         };
5576         void *headers_m;
5577         void *headers_v;
5578         char *l24_m;
5579         char *l24_v;
5580         uint8_t tos;
5581
5582         if (inner) {
5583                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5584                                          inner_headers);
5585                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5586         } else {
5587                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5588                                          outer_headers);
5589                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5590         }
5591         if (group == 0)
5592                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
5593         else
5594                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x4);
5595         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 4);
5596         /*
5597          * On outer header (which must contains L2), or inner header with L2,
5598          * set cvlan_tag mask bit to mark this packet as untagged.
5599          * This should be done even if item->spec is empty.
5600          */
5601         if (!inner || item_flags & MLX5_FLOW_LAYER_INNER_L2)
5602                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5603         if (!ipv4_v)
5604                 return;
5605         if (!ipv4_m)
5606                 ipv4_m = &nic_mask;
5607         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5608                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
5609         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5610                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
5611         *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
5612         *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
5613         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5614                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
5615         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5616                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
5617         *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
5618         *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
5619         tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
5620         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
5621                  ipv4_m->hdr.type_of_service);
5622         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
5623         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
5624                  ipv4_m->hdr.type_of_service >> 2);
5625         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
5626         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
5627                  ipv4_m->hdr.next_proto_id);
5628         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
5629                  ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
5630         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
5631                  ipv4_m->hdr.time_to_live);
5632         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
5633                  ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
5634 }
5635
5636 /**
5637  * Add IPV6 item to matcher and to the value.
5638  *
5639  * @param[in, out] matcher
5640  *   Flow matcher.
5641  * @param[in, out] key
5642  *   Flow matcher value.
5643  * @param[in] item
5644  *   Flow pattern to translate.
5645  * @param[in] item_flags
5646  *   Bit-fields that holds the items detected until now.
5647  * @param[in] inner
5648  *   Item is inner pattern.
5649  * @param[in] group
5650  *   The group to insert the rule.
5651  */
5652 static void
5653 flow_dv_translate_item_ipv6(void *matcher, void *key,
5654                             const struct rte_flow_item *item,
5655                             const uint64_t item_flags,
5656                             int inner, uint32_t group)
5657 {
5658         const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
5659         const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
5660         const struct rte_flow_item_ipv6 nic_mask = {
5661                 .hdr = {
5662                         .src_addr =
5663                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
5664                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
5665                         .dst_addr =
5666                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
5667                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
5668                         .vtc_flow = RTE_BE32(0xffffffff),
5669                         .proto = 0xff,
5670                         .hop_limits = 0xff,
5671                 },
5672         };
5673         void *headers_m;
5674         void *headers_v;
5675         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5676         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5677         char *l24_m;
5678         char *l24_v;
5679         uint32_t vtc_m;
5680         uint32_t vtc_v;
5681         int i;
5682         int size;
5683
5684         if (inner) {
5685                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5686                                          inner_headers);
5687                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5688         } else {
5689                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5690                                          outer_headers);
5691                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5692         }
5693         if (group == 0)
5694                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
5695         else
5696                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x6);
5697         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 6);
5698         /*
5699          * On outer header (which must contains L2), or inner header with L2,
5700          * set cvlan_tag mask bit to mark this packet as untagged.
5701          * This should be done even if item->spec is empty.
5702          */
5703         if (!inner || item_flags & MLX5_FLOW_LAYER_INNER_L2)
5704                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5705         if (!ipv6_v)
5706                 return;
5707         if (!ipv6_m)
5708                 ipv6_m = &nic_mask;
5709         size = sizeof(ipv6_m->hdr.dst_addr);
5710         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5711                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
5712         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5713                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
5714         memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
5715         for (i = 0; i < size; ++i)
5716                 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
5717         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5718                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
5719         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5720                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
5721         memcpy(l24_m, ipv6_m->hdr.src_addr, size);
5722         for (i = 0; i < size; ++i)
5723                 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
5724         /* TOS. */
5725         vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
5726         vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
5727         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
5728         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
5729         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
5730         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
5731         /* Label. */
5732         if (inner) {
5733                 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
5734                          vtc_m);
5735                 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
5736                          vtc_v);
5737         } else {
5738                 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
5739                          vtc_m);
5740                 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
5741                          vtc_v);
5742         }
5743         /* Protocol. */
5744         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
5745                  ipv6_m->hdr.proto);
5746         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
5747                  ipv6_v->hdr.proto & ipv6_m->hdr.proto);
5748         /* Hop limit. */
5749         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
5750                  ipv6_m->hdr.hop_limits);
5751         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
5752                  ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
5753 }
5754
5755 /**
5756  * Add TCP item to matcher and to the value.
5757  *
5758  * @param[in, out] matcher
5759  *   Flow matcher.
5760  * @param[in, out] key
5761  *   Flow matcher value.
5762  * @param[in] item
5763  *   Flow pattern to translate.
5764  * @param[in] inner
5765  *   Item is inner pattern.
5766  */
5767 static void
5768 flow_dv_translate_item_tcp(void *matcher, void *key,
5769                            const struct rte_flow_item *item,
5770                            int inner)
5771 {
5772         const struct rte_flow_item_tcp *tcp_m = item->mask;
5773         const struct rte_flow_item_tcp *tcp_v = item->spec;
5774         void *headers_m;
5775         void *headers_v;
5776
5777         if (inner) {
5778                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5779                                          inner_headers);
5780                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5781         } else {
5782                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5783                                          outer_headers);
5784                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5785         }
5786         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5787         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
5788         if (!tcp_v)
5789                 return;
5790         if (!tcp_m)
5791                 tcp_m = &rte_flow_item_tcp_mask;
5792         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
5793                  rte_be_to_cpu_16(tcp_m->hdr.src_port));
5794         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
5795                  rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
5796         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
5797                  rte_be_to_cpu_16(tcp_m->hdr.dst_port));
5798         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
5799                  rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
5800         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
5801                  tcp_m->hdr.tcp_flags);
5802         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
5803                  (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
5804 }
5805
5806 /**
5807  * Add UDP item to matcher and to the value.
5808  *
5809  * @param[in, out] matcher
5810  *   Flow matcher.
5811  * @param[in, out] key
5812  *   Flow matcher value.
5813  * @param[in] item
5814  *   Flow pattern to translate.
5815  * @param[in] inner
5816  *   Item is inner pattern.
5817  */
5818 static void
5819 flow_dv_translate_item_udp(void *matcher, void *key,
5820                            const struct rte_flow_item *item,
5821                            int inner)
5822 {
5823         const struct rte_flow_item_udp *udp_m = item->mask;
5824         const struct rte_flow_item_udp *udp_v = item->spec;
5825         void *headers_m;
5826         void *headers_v;
5827
5828         if (inner) {
5829                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5830                                          inner_headers);
5831                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5832         } else {
5833                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5834                                          outer_headers);
5835                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5836         }
5837         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5838         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
5839         if (!udp_v)
5840                 return;
5841         if (!udp_m)
5842                 udp_m = &rte_flow_item_udp_mask;
5843         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
5844                  rte_be_to_cpu_16(udp_m->hdr.src_port));
5845         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
5846                  rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
5847         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
5848                  rte_be_to_cpu_16(udp_m->hdr.dst_port));
5849         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
5850                  rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
5851 }
5852
5853 /**
5854  * Add GRE optional Key item to matcher and to the value.
5855  *
5856  * @param[in, out] matcher
5857  *   Flow matcher.
5858  * @param[in, out] key
5859  *   Flow matcher value.
5860  * @param[in] item
5861  *   Flow pattern to translate.
5862  * @param[in] inner
5863  *   Item is inner pattern.
5864  */
5865 static void
5866 flow_dv_translate_item_gre_key(void *matcher, void *key,
5867                                    const struct rte_flow_item *item)
5868 {
5869         const rte_be32_t *key_m = item->mask;
5870         const rte_be32_t *key_v = item->spec;
5871         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5872         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5873         rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
5874
5875         /* GRE K bit must be on and should already be validated */
5876         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
5877         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
5878         if (!key_v)
5879                 return;
5880         if (!key_m)
5881                 key_m = &gre_key_default_mask;
5882         MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
5883                  rte_be_to_cpu_32(*key_m) >> 8);
5884         MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
5885                  rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
5886         MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
5887                  rte_be_to_cpu_32(*key_m) & 0xFF);
5888         MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
5889                  rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
5890 }
5891
5892 /**
5893  * Add GRE item to matcher and to the value.
5894  *
5895  * @param[in, out] matcher
5896  *   Flow matcher.
5897  * @param[in, out] key
5898  *   Flow matcher value.
5899  * @param[in] item
5900  *   Flow pattern to translate.
5901  * @param[in] inner
5902  *   Item is inner pattern.
5903  */
5904 static void
5905 flow_dv_translate_item_gre(void *matcher, void *key,
5906                            const struct rte_flow_item *item,
5907                            int inner)
5908 {
5909         const struct rte_flow_item_gre *gre_m = item->mask;
5910         const struct rte_flow_item_gre *gre_v = item->spec;
5911         void *headers_m;
5912         void *headers_v;
5913         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5914         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5915         struct {
5916                 union {
5917                         __extension__
5918                         struct {
5919                                 uint16_t version:3;
5920                                 uint16_t rsvd0:9;
5921                                 uint16_t s_present:1;
5922                                 uint16_t k_present:1;
5923                                 uint16_t rsvd_bit1:1;
5924                                 uint16_t c_present:1;
5925                         };
5926                         uint16_t value;
5927                 };
5928         } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
5929
5930         if (inner) {
5931                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5932                                          inner_headers);
5933                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5934         } else {
5935                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5936                                          outer_headers);
5937                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5938         }
5939         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5940         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
5941         if (!gre_v)
5942                 return;
5943         if (!gre_m)
5944                 gre_m = &rte_flow_item_gre_mask;
5945         MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
5946                  rte_be_to_cpu_16(gre_m->protocol));
5947         MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
5948                  rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
5949         gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
5950         gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
5951         MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
5952                  gre_crks_rsvd0_ver_m.c_present);
5953         MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
5954                  gre_crks_rsvd0_ver_v.c_present &
5955                  gre_crks_rsvd0_ver_m.c_present);
5956         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
5957                  gre_crks_rsvd0_ver_m.k_present);
5958         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
5959                  gre_crks_rsvd0_ver_v.k_present &
5960                  gre_crks_rsvd0_ver_m.k_present);
5961         MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
5962                  gre_crks_rsvd0_ver_m.s_present);
5963         MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
5964                  gre_crks_rsvd0_ver_v.s_present &
5965                  gre_crks_rsvd0_ver_m.s_present);
5966 }
5967
5968 /**
5969  * Add NVGRE item to matcher and to the value.
5970  *
5971  * @param[in, out] matcher
5972  *   Flow matcher.
5973  * @param[in, out] key
5974  *   Flow matcher value.
5975  * @param[in] item
5976  *   Flow pattern to translate.
5977  * @param[in] inner
5978  *   Item is inner pattern.
5979  */
5980 static void
5981 flow_dv_translate_item_nvgre(void *matcher, void *key,
5982                              const struct rte_flow_item *item,
5983                              int inner)
5984 {
5985         const struct rte_flow_item_nvgre *nvgre_m = item->mask;
5986         const struct rte_flow_item_nvgre *nvgre_v = item->spec;
5987         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5988         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5989         const char *tni_flow_id_m = (const char *)nvgre_m->tni;
5990         const char *tni_flow_id_v = (const char *)nvgre_v->tni;
5991         char *gre_key_m;
5992         char *gre_key_v;
5993         int size;
5994         int i;
5995
5996         /* For NVGRE, GRE header fields must be set with defined values. */
5997         const struct rte_flow_item_gre gre_spec = {
5998                 .c_rsvd0_ver = RTE_BE16(0x2000),
5999                 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
6000         };
6001         const struct rte_flow_item_gre gre_mask = {
6002                 .c_rsvd0_ver = RTE_BE16(0xB000),
6003                 .protocol = RTE_BE16(UINT16_MAX),
6004         };
6005         const struct rte_flow_item gre_item = {
6006                 .spec = &gre_spec,
6007                 .mask = &gre_mask,
6008                 .last = NULL,
6009         };
6010         flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
6011         if (!nvgre_v)
6012                 return;
6013         if (!nvgre_m)
6014                 nvgre_m = &rte_flow_item_nvgre_mask;
6015         size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
6016         gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
6017         gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
6018         memcpy(gre_key_m, tni_flow_id_m, size);
6019         for (i = 0; i < size; ++i)
6020                 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
6021 }
6022
6023 /**
6024  * Add VXLAN item to matcher and to the value.
6025  *
6026  * @param[in, out] matcher
6027  *   Flow matcher.
6028  * @param[in, out] key
6029  *   Flow matcher value.
6030  * @param[in] item
6031  *   Flow pattern to translate.
6032  * @param[in] inner
6033  *   Item is inner pattern.
6034  */
6035 static void
6036 flow_dv_translate_item_vxlan(void *matcher, void *key,
6037                              const struct rte_flow_item *item,
6038                              int inner)
6039 {
6040         const struct rte_flow_item_vxlan *vxlan_m = item->mask;
6041         const struct rte_flow_item_vxlan *vxlan_v = item->spec;
6042         void *headers_m;
6043         void *headers_v;
6044         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6045         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6046         char *vni_m;
6047         char *vni_v;
6048         uint16_t dport;
6049         int size;
6050         int i;
6051
6052         if (inner) {
6053                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6054                                          inner_headers);
6055                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6056         } else {
6057                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6058                                          outer_headers);
6059                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6060         }
6061         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
6062                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
6063         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6064                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6065                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6066         }
6067         if (!vxlan_v)
6068                 return;
6069         if (!vxlan_m)
6070                 vxlan_m = &rte_flow_item_vxlan_mask;
6071         size = sizeof(vxlan_m->vni);
6072         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
6073         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
6074         memcpy(vni_m, vxlan_m->vni, size);
6075         for (i = 0; i < size; ++i)
6076                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
6077 }
6078
6079 /**
6080  * Add VXLAN-GPE item to matcher and to the value.
6081  *
6082  * @param[in, out] matcher
6083  *   Flow matcher.
6084  * @param[in, out] key
6085  *   Flow matcher value.
6086  * @param[in] item
6087  *   Flow pattern to translate.
6088  * @param[in] inner
6089  *   Item is inner pattern.
6090  */
6091
6092 static void
6093 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
6094                                  const struct rte_flow_item *item, int inner)
6095 {
6096         const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
6097         const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
6098         void *headers_m;
6099         void *headers_v;
6100         void *misc_m =
6101                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
6102         void *misc_v =
6103                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6104         char *vni_m;
6105         char *vni_v;
6106         uint16_t dport;
6107         int size;
6108         int i;
6109         uint8_t flags_m = 0xff;
6110         uint8_t flags_v = 0xc;
6111
6112         if (inner) {
6113                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6114                                          inner_headers);
6115                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6116         } else {
6117                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6118                                          outer_headers);
6119                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6120         }
6121         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
6122                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
6123         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6124                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6125                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6126         }
6127         if (!vxlan_v)
6128                 return;
6129         if (!vxlan_m)
6130                 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
6131         size = sizeof(vxlan_m->vni);
6132         vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
6133         vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
6134         memcpy(vni_m, vxlan_m->vni, size);
6135         for (i = 0; i < size; ++i)
6136                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
6137         if (vxlan_m->flags) {
6138                 flags_m = vxlan_m->flags;
6139                 flags_v = vxlan_v->flags;
6140         }
6141         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
6142         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
6143         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
6144                  vxlan_m->protocol);
6145         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
6146                  vxlan_v->protocol);
6147 }
6148
6149 /**
6150  * Add Geneve item to matcher and to the value.
6151  *
6152  * @param[in, out] matcher
6153  *   Flow matcher.
6154  * @param[in, out] key
6155  *   Flow matcher value.
6156  * @param[in] item
6157  *   Flow pattern to translate.
6158  * @param[in] inner
6159  *   Item is inner pattern.
6160  */
6161
6162 static void
6163 flow_dv_translate_item_geneve(void *matcher, void *key,
6164                               const struct rte_flow_item *item, int inner)
6165 {
6166         const struct rte_flow_item_geneve *geneve_m = item->mask;
6167         const struct rte_flow_item_geneve *geneve_v = item->spec;
6168         void *headers_m;
6169         void *headers_v;
6170         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6171         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6172         uint16_t dport;
6173         uint16_t gbhdr_m;
6174         uint16_t gbhdr_v;
6175         char *vni_m;
6176         char *vni_v;
6177         size_t size, i;
6178
6179         if (inner) {
6180                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6181                                          inner_headers);
6182                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6183         } else {
6184                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6185                                          outer_headers);
6186                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6187         }
6188         dport = MLX5_UDP_PORT_GENEVE;
6189         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6190                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6191                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6192         }
6193         if (!geneve_v)
6194                 return;
6195         if (!geneve_m)
6196                 geneve_m = &rte_flow_item_geneve_mask;
6197         size = sizeof(geneve_m->vni);
6198         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
6199         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
6200         memcpy(vni_m, geneve_m->vni, size);
6201         for (i = 0; i < size; ++i)
6202                 vni_v[i] = vni_m[i] & geneve_v->vni[i];
6203         MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
6204                  rte_be_to_cpu_16(geneve_m->protocol));
6205         MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
6206                  rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
6207         gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
6208         gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
6209         MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
6210                  MLX5_GENEVE_OAMF_VAL(gbhdr_m));
6211         MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
6212                  MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
6213         MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
6214                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
6215         MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
6216                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
6217                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
6218 }
6219
6220 /**
6221  * Add MPLS item to matcher and to the value.
6222  *
6223  * @param[in, out] matcher
6224  *   Flow matcher.
6225  * @param[in, out] key
6226  *   Flow matcher value.
6227  * @param[in] item
6228  *   Flow pattern to translate.
6229  * @param[in] prev_layer
6230  *   The protocol layer indicated in previous item.
6231  * @param[in] inner
6232  *   Item is inner pattern.
6233  */
6234 static void
6235 flow_dv_translate_item_mpls(void *matcher, void *key,
6236                             const struct rte_flow_item *item,
6237                             uint64_t prev_layer,
6238                             int inner)
6239 {
6240         const uint32_t *in_mpls_m = item->mask;
6241         const uint32_t *in_mpls_v = item->spec;
6242         uint32_t *out_mpls_m = 0;
6243         uint32_t *out_mpls_v = 0;
6244         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6245         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6246         void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
6247                                      misc_parameters_2);
6248         void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
6249         void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
6250         void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6251
6252         switch (prev_layer) {
6253         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
6254                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
6255                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
6256                          MLX5_UDP_PORT_MPLS);
6257                 break;
6258         case MLX5_FLOW_LAYER_GRE:
6259                 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
6260                 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
6261                          RTE_ETHER_TYPE_MPLS);
6262                 break;
6263         default:
6264                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6265                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6266                          IPPROTO_MPLS);
6267                 break;
6268         }
6269         if (!in_mpls_v)
6270                 return;
6271         if (!in_mpls_m)
6272                 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
6273         switch (prev_layer) {
6274         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
6275                 out_mpls_m =
6276                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
6277                                                  outer_first_mpls_over_udp);
6278                 out_mpls_v =
6279                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
6280                                                  outer_first_mpls_over_udp);
6281                 break;
6282         case MLX5_FLOW_LAYER_GRE:
6283                 out_mpls_m =
6284                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
6285                                                  outer_first_mpls_over_gre);
6286                 out_mpls_v =
6287                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
6288                                                  outer_first_mpls_over_gre);
6289                 break;
6290         default:
6291                 /* Inner MPLS not over GRE is not supported. */
6292                 if (!inner) {
6293                         out_mpls_m =
6294                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
6295                                                          misc2_m,
6296                                                          outer_first_mpls);
6297                         out_mpls_v =
6298                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
6299                                                          misc2_v,
6300                                                          outer_first_mpls);
6301                 }
6302                 break;
6303         }
6304         if (out_mpls_m && out_mpls_v) {
6305                 *out_mpls_m = *in_mpls_m;
6306                 *out_mpls_v = *in_mpls_v & *in_mpls_m;
6307         }
6308 }
6309
6310 /**
6311  * Add metadata register item to matcher
6312  *
6313  * @param[in, out] matcher
6314  *   Flow matcher.
6315  * @param[in, out] key
6316  *   Flow matcher value.
6317  * @param[in] reg_type
6318  *   Type of device metadata register
6319  * @param[in] value
6320  *   Register value
6321  * @param[in] mask
6322  *   Register mask
6323  */
6324 static void
6325 flow_dv_match_meta_reg(void *matcher, void *key,
6326                        enum modify_reg reg_type,
6327                        uint32_t data, uint32_t mask)
6328 {
6329         void *misc2_m =
6330                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
6331         void *misc2_v =
6332                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
6333         uint32_t temp;
6334
6335         data &= mask;
6336         switch (reg_type) {
6337         case REG_A:
6338                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
6339                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
6340                 break;
6341         case REG_B:
6342                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
6343                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
6344                 break;
6345         case REG_C_0:
6346                 /*
6347                  * The metadata register C0 field might be divided into
6348                  * source vport index and META item value, we should set
6349                  * this field according to specified mask, not as whole one.
6350                  */
6351                 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
6352                 temp |= mask;
6353                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
6354                 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
6355                 temp &= ~mask;
6356                 temp |= data;
6357                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
6358                 break;
6359         case REG_C_1:
6360                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
6361                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
6362                 break;
6363         case REG_C_2:
6364                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
6365                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
6366                 break;
6367         case REG_C_3:
6368                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
6369                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
6370                 break;
6371         case REG_C_4:
6372                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
6373                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
6374                 break;
6375         case REG_C_5:
6376                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
6377                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
6378                 break;
6379         case REG_C_6:
6380                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
6381                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
6382                 break;
6383         case REG_C_7:
6384                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
6385                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
6386                 break;
6387         default:
6388                 MLX5_ASSERT(false);
6389                 break;
6390         }
6391 }
6392
6393 /**
6394  * Add MARK item to matcher
6395  *
6396  * @param[in] dev
6397  *   The device to configure through.
6398  * @param[in, out] matcher
6399  *   Flow matcher.
6400  * @param[in, out] key
6401  *   Flow matcher value.
6402  * @param[in] item
6403  *   Flow pattern to translate.
6404  */
6405 static void
6406 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
6407                             void *matcher, void *key,
6408                             const struct rte_flow_item *item)
6409 {
6410         struct mlx5_priv *priv = dev->data->dev_private;
6411         const struct rte_flow_item_mark *mark;
6412         uint32_t value;
6413         uint32_t mask;
6414
6415         mark = item->mask ? (const void *)item->mask :
6416                             &rte_flow_item_mark_mask;
6417         mask = mark->id & priv->sh->dv_mark_mask;
6418         mark = (const void *)item->spec;
6419         MLX5_ASSERT(mark);
6420         value = mark->id & priv->sh->dv_mark_mask & mask;
6421         if (mask) {
6422                 enum modify_reg reg;
6423
6424                 /* Get the metadata register index for the mark. */
6425                 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
6426                 MLX5_ASSERT(reg > 0);
6427                 if (reg == REG_C_0) {
6428                         struct mlx5_priv *priv = dev->data->dev_private;
6429                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6430                         uint32_t shl_c0 = rte_bsf32(msk_c0);
6431
6432                         mask &= msk_c0;
6433                         mask <<= shl_c0;
6434                         value <<= shl_c0;
6435                 }
6436                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6437         }
6438 }
6439
6440 /**
6441  * Add META item to matcher
6442  *
6443  * @param[in] dev
6444  *   The devich to configure through.
6445  * @param[in, out] matcher
6446  *   Flow matcher.
6447  * @param[in, out] key
6448  *   Flow matcher value.
6449  * @param[in] attr
6450  *   Attributes of flow that includes this item.
6451  * @param[in] item
6452  *   Flow pattern to translate.
6453  */
6454 static void
6455 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
6456                             void *matcher, void *key,
6457                             const struct rte_flow_attr *attr,
6458                             const struct rte_flow_item *item)
6459 {
6460         const struct rte_flow_item_meta *meta_m;
6461         const struct rte_flow_item_meta *meta_v;
6462
6463         meta_m = (const void *)item->mask;
6464         if (!meta_m)
6465                 meta_m = &rte_flow_item_meta_mask;
6466         meta_v = (const void *)item->spec;
6467         if (meta_v) {
6468                 int reg;
6469                 uint32_t value = meta_v->data;
6470                 uint32_t mask = meta_m->data;
6471
6472                 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
6473                 if (reg < 0)
6474                         return;
6475                 /*
6476                  * In datapath code there is no endianness
6477                  * coversions for perfromance reasons, all
6478                  * pattern conversions are done in rte_flow.
6479                  */
6480                 value = rte_cpu_to_be_32(value);
6481                 mask = rte_cpu_to_be_32(mask);
6482                 if (reg == REG_C_0) {
6483                         struct mlx5_priv *priv = dev->data->dev_private;
6484                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6485                         uint32_t shl_c0 = rte_bsf32(msk_c0);
6486 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
6487                         uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
6488
6489                         value >>= shr_c0;
6490                         mask >>= shr_c0;
6491 #endif
6492                         value <<= shl_c0;
6493                         mask <<= shl_c0;
6494                         MLX5_ASSERT(msk_c0);
6495                         MLX5_ASSERT(!(~msk_c0 & mask));
6496                 }
6497                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6498         }
6499 }
6500
6501 /**
6502  * Add vport metadata Reg C0 item to matcher
6503  *
6504  * @param[in, out] matcher
6505  *   Flow matcher.
6506  * @param[in, out] key
6507  *   Flow matcher value.
6508  * @param[in] reg
6509  *   Flow pattern to translate.
6510  */
6511 static void
6512 flow_dv_translate_item_meta_vport(void *matcher, void *key,
6513                                   uint32_t value, uint32_t mask)
6514 {
6515         flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
6516 }
6517
6518 /**
6519  * Add tag item to matcher
6520  *
6521  * @param[in] dev
6522  *   The devich to configure through.
6523  * @param[in, out] matcher
6524  *   Flow matcher.
6525  * @param[in, out] key
6526  *   Flow matcher value.
6527  * @param[in] item
6528  *   Flow pattern to translate.
6529  */
6530 static void
6531 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
6532                                 void *matcher, void *key,
6533                                 const struct rte_flow_item *item)
6534 {
6535         const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
6536         const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
6537         uint32_t mask, value;
6538
6539         MLX5_ASSERT(tag_v);
6540         value = tag_v->data;
6541         mask = tag_m ? tag_m->data : UINT32_MAX;
6542         if (tag_v->id == REG_C_0) {
6543                 struct mlx5_priv *priv = dev->data->dev_private;
6544                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6545                 uint32_t shl_c0 = rte_bsf32(msk_c0);
6546
6547                 mask &= msk_c0;
6548                 mask <<= shl_c0;
6549                 value <<= shl_c0;
6550         }
6551         flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
6552 }
6553
6554 /**
6555  * Add TAG item to matcher
6556  *
6557  * @param[in] dev
6558  *   The devich to configure through.
6559  * @param[in, out] matcher
6560  *   Flow matcher.
6561  * @param[in, out] key
6562  *   Flow matcher value.
6563  * @param[in] item
6564  *   Flow pattern to translate.
6565  */
6566 static void
6567 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
6568                            void *matcher, void *key,
6569                            const struct rte_flow_item *item)
6570 {
6571         const struct rte_flow_item_tag *tag_v = item->spec;
6572         const struct rte_flow_item_tag *tag_m = item->mask;
6573         enum modify_reg reg;
6574
6575         MLX5_ASSERT(tag_v);
6576         tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
6577         /* Get the metadata register index for the tag. */
6578         reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
6579         MLX5_ASSERT(reg > 0);
6580         flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
6581 }
6582
6583 /**
6584  * Add source vport match to the specified matcher.
6585  *
6586  * @param[in, out] matcher
6587  *   Flow matcher.
6588  * @param[in, out] key
6589  *   Flow matcher value.
6590  * @param[in] port
6591  *   Source vport value to match
6592  * @param[in] mask
6593  *   Mask
6594  */
6595 static void
6596 flow_dv_translate_item_source_vport(void *matcher, void *key,
6597                                     int16_t port, uint16_t mask)
6598 {
6599         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6600         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6601
6602         MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
6603         MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
6604 }
6605
6606 /**
6607  * Translate port-id item to eswitch match on  port-id.
6608  *
6609  * @param[in] dev
6610  *   The devich to configure through.
6611  * @param[in, out] matcher
6612  *   Flow matcher.
6613  * @param[in, out] key
6614  *   Flow matcher value.
6615  * @param[in] item
6616  *   Flow pattern to translate.
6617  *
6618  * @return
6619  *   0 on success, a negative errno value otherwise.
6620  */
6621 static int
6622 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
6623                                void *key, const struct rte_flow_item *item)
6624 {
6625         const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
6626         const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
6627         struct mlx5_priv *priv;
6628         uint16_t mask, id;
6629
6630         mask = pid_m ? pid_m->id : 0xffff;
6631         id = pid_v ? pid_v->id : dev->data->port_id;
6632         priv = mlx5_port_to_eswitch_info(id, item == NULL);
6633         if (!priv)
6634                 return -rte_errno;
6635         /* Translate to vport field or to metadata, depending on mode. */
6636         if (priv->vport_meta_mask)
6637                 flow_dv_translate_item_meta_vport(matcher, key,
6638                                                   priv->vport_meta_tag,
6639                                                   priv->vport_meta_mask);
6640         else
6641                 flow_dv_translate_item_source_vport(matcher, key,
6642                                                     priv->vport_id, mask);
6643         return 0;
6644 }
6645
6646 /**
6647  * Add ICMP6 item to matcher and to the value.
6648  *
6649  * @param[in, out] matcher
6650  *   Flow matcher.
6651  * @param[in, out] key
6652  *   Flow matcher value.
6653  * @param[in] item
6654  *   Flow pattern to translate.
6655  * @param[in] inner
6656  *   Item is inner pattern.
6657  */
6658 static void
6659 flow_dv_translate_item_icmp6(void *matcher, void *key,
6660                               const struct rte_flow_item *item,
6661                               int inner)
6662 {
6663         const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
6664         const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
6665         void *headers_m;
6666         void *headers_v;
6667         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
6668                                      misc_parameters_3);
6669         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6670         if (inner) {
6671                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6672                                          inner_headers);
6673                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6674         } else {
6675                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6676                                          outer_headers);
6677                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6678         }
6679         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
6680         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
6681         if (!icmp6_v)
6682                 return;
6683         if (!icmp6_m)
6684                 icmp6_m = &rte_flow_item_icmp6_mask;
6685         /*
6686          * Force flow only to match the non-fragmented IPv6 ICMPv6 packets.
6687          * If only the protocol is specified, no need to match the frag.
6688          */
6689         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
6690         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
6691         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
6692         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
6693                  icmp6_v->type & icmp6_m->type);
6694         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
6695         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
6696                  icmp6_v->code & icmp6_m->code);
6697 }
6698
6699 /**
6700  * Add ICMP item to matcher and to the value.
6701  *
6702  * @param[in, out] matcher
6703  *   Flow matcher.
6704  * @param[in, out] key
6705  *   Flow matcher value.
6706  * @param[in] item
6707  *   Flow pattern to translate.
6708  * @param[in] inner
6709  *   Item is inner pattern.
6710  */
6711 static void
6712 flow_dv_translate_item_icmp(void *matcher, void *key,
6713                             const struct rte_flow_item *item,
6714                             int inner)
6715 {
6716         const struct rte_flow_item_icmp *icmp_m = item->mask;
6717         const struct rte_flow_item_icmp *icmp_v = item->spec;
6718         void *headers_m;
6719         void *headers_v;
6720         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
6721                                      misc_parameters_3);
6722         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6723         if (inner) {
6724                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6725                                          inner_headers);
6726                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6727         } else {
6728                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6729                                          outer_headers);
6730                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6731         }
6732         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
6733         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
6734         if (!icmp_v)
6735                 return;
6736         if (!icmp_m)
6737                 icmp_m = &rte_flow_item_icmp_mask;
6738         /*
6739          * Force flow only to match the non-fragmented IPv4 ICMP packets.
6740          * If only the protocol is specified, no need to match the frag.
6741          */
6742         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
6743         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
6744         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
6745                  icmp_m->hdr.icmp_type);
6746         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
6747                  icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
6748         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
6749                  icmp_m->hdr.icmp_code);
6750         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
6751                  icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
6752 }
6753
6754 /**
6755  * Add GTP item to matcher and to the value.
6756  *
6757  * @param[in, out] matcher
6758  *   Flow matcher.
6759  * @param[in, out] key
6760  *   Flow matcher value.
6761  * @param[in] item
6762  *   Flow pattern to translate.
6763  * @param[in] inner
6764  *   Item is inner pattern.
6765  */
6766 static void
6767 flow_dv_translate_item_gtp(void *matcher, void *key,
6768                            const struct rte_flow_item *item, int inner)
6769 {
6770         const struct rte_flow_item_gtp *gtp_m = item->mask;
6771         const struct rte_flow_item_gtp *gtp_v = item->spec;
6772         void *headers_m;
6773         void *headers_v;
6774         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
6775                                      misc_parameters_3);
6776         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6777         uint16_t dport = RTE_GTPU_UDP_PORT;
6778
6779         if (inner) {
6780                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6781                                          inner_headers);
6782                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6783         } else {
6784                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6785                                          outer_headers);
6786                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6787         }
6788         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6789                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6790                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6791         }
6792         if (!gtp_v)
6793                 return;
6794         if (!gtp_m)
6795                 gtp_m = &rte_flow_item_gtp_mask;
6796         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
6797         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
6798                  gtp_v->msg_type & gtp_m->msg_type);
6799         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
6800                  rte_be_to_cpu_32(gtp_m->teid));
6801         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
6802                  rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
6803 }
6804
6805 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
6806
6807 #define HEADER_IS_ZERO(match_criteria, headers)                              \
6808         !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers),     \
6809                  matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
6810
6811 /**
6812  * Calculate flow matcher enable bitmap.
6813  *
6814  * @param match_criteria
6815  *   Pointer to flow matcher criteria.
6816  *
6817  * @return
6818  *   Bitmap of enabled fields.
6819  */
6820 static uint8_t
6821 flow_dv_matcher_enable(uint32_t *match_criteria)
6822 {
6823         uint8_t match_criteria_enable;
6824
6825         match_criteria_enable =
6826                 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
6827                 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
6828         match_criteria_enable |=
6829                 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
6830                 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
6831         match_criteria_enable |=
6832                 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
6833                 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
6834         match_criteria_enable |=
6835                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
6836                 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
6837         match_criteria_enable |=
6838                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
6839                 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
6840         return match_criteria_enable;
6841 }
6842
6843
6844 /**
6845  * Get a flow table.
6846  *
6847  * @param[in, out] dev
6848  *   Pointer to rte_eth_dev structure.
6849  * @param[in] table_id
6850  *   Table id to use.
6851  * @param[in] egress
6852  *   Direction of the table.
6853  * @param[in] transfer
6854  *   E-Switch or NIC flow.
6855  * @param[out] error
6856  *   pointer to error structure.
6857  *
6858  * @return
6859  *   Returns tables resource based on the index, NULL in case of failed.
6860  */
6861 static struct mlx5_flow_tbl_resource *
6862 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
6863                          uint32_t table_id, uint8_t egress,
6864                          uint8_t transfer,
6865                          struct rte_flow_error *error)
6866 {
6867         struct mlx5_priv *priv = dev->data->dev_private;
6868         struct mlx5_ibv_shared *sh = priv->sh;
6869         struct mlx5_flow_tbl_resource *tbl;
6870         union mlx5_flow_tbl_key table_key = {
6871                 {
6872                         .table_id = table_id,
6873                         .reserved = 0,
6874                         .domain = !!transfer,
6875                         .direction = !!egress,
6876                 }
6877         };
6878         struct mlx5_hlist_entry *pos = mlx5_hlist_lookup(sh->flow_tbls,
6879                                                          table_key.v64);
6880         struct mlx5_flow_tbl_data_entry *tbl_data;
6881         uint32_t idx = 0;
6882         int ret;
6883         void *domain;
6884
6885         if (pos) {
6886                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
6887                                         entry);
6888                 tbl = &tbl_data->tbl;
6889                 rte_atomic32_inc(&tbl->refcnt);
6890                 return tbl;
6891         }
6892         tbl_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
6893         if (!tbl_data) {
6894                 rte_flow_error_set(error, ENOMEM,
6895                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6896                                    NULL,
6897                                    "cannot allocate flow table data entry");
6898                 return NULL;
6899         }
6900         tbl_data->idx = idx;
6901         tbl = &tbl_data->tbl;
6902         pos = &tbl_data->entry;
6903         if (transfer)
6904                 domain = sh->fdb_domain;
6905         else if (egress)
6906                 domain = sh->tx_domain;
6907         else
6908                 domain = sh->rx_domain;
6909         tbl->obj = mlx5_glue->dr_create_flow_tbl(domain, table_id);
6910         if (!tbl->obj) {
6911                 rte_flow_error_set(error, ENOMEM,
6912                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6913                                    NULL, "cannot create flow table object");
6914                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
6915                 return NULL;
6916         }
6917         /*
6918          * No multi-threads now, but still better to initialize the reference
6919          * count before insert it into the hash list.
6920          */
6921         rte_atomic32_init(&tbl->refcnt);
6922         /* Jump action reference count is initialized here. */
6923         rte_atomic32_init(&tbl_data->jump.refcnt);
6924         pos->key = table_key.v64;
6925         ret = mlx5_hlist_insert(sh->flow_tbls, pos);
6926         if (ret < 0) {
6927                 rte_flow_error_set(error, -ret,
6928                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6929                                    "cannot insert flow table data entry");
6930                 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
6931                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
6932         }
6933         rte_atomic32_inc(&tbl->refcnt);
6934         return tbl;
6935 }
6936
6937 /**
6938  * Release a flow table.
6939  *
6940  * @param[in] dev
6941  *   Pointer to rte_eth_dev structure.
6942  * @param[in] tbl
6943  *   Table resource to be released.
6944  *
6945  * @return
6946  *   Returns 0 if table was released, else return 1;
6947  */
6948 static int
6949 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
6950                              struct mlx5_flow_tbl_resource *tbl)
6951 {
6952         struct mlx5_priv *priv = dev->data->dev_private;
6953         struct mlx5_ibv_shared *sh = priv->sh;
6954         struct mlx5_flow_tbl_data_entry *tbl_data =
6955                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
6956
6957         if (!tbl)
6958                 return 0;
6959         if (rte_atomic32_dec_and_test(&tbl->refcnt)) {
6960                 struct mlx5_hlist_entry *pos = &tbl_data->entry;
6961
6962                 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
6963                 tbl->obj = NULL;
6964                 /* remove the entry from the hash list and free memory. */
6965                 mlx5_hlist_remove(sh->flow_tbls, pos);
6966                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_JUMP],
6967                                 tbl_data->idx);
6968                 return 0;
6969         }
6970         return 1;
6971 }
6972
6973 /**
6974  * Register the flow matcher.
6975  *
6976  * @param[in, out] dev
6977  *   Pointer to rte_eth_dev structure.
6978  * @param[in, out] matcher
6979  *   Pointer to flow matcher.
6980  * @param[in, out] key
6981  *   Pointer to flow table key.
6982  * @parm[in, out] dev_flow
6983  *   Pointer to the dev_flow.
6984  * @param[out] error
6985  *   pointer to error structure.
6986  *
6987  * @return
6988  *   0 on success otherwise -errno and errno is set.
6989  */
6990 static int
6991 flow_dv_matcher_register(struct rte_eth_dev *dev,
6992                          struct mlx5_flow_dv_matcher *matcher,
6993                          union mlx5_flow_tbl_key *key,
6994                          struct mlx5_flow *dev_flow,
6995                          struct rte_flow_error *error)
6996 {
6997         struct mlx5_priv *priv = dev->data->dev_private;
6998         struct mlx5_ibv_shared *sh = priv->sh;
6999         struct mlx5_flow_dv_matcher *cache_matcher;
7000         struct mlx5dv_flow_matcher_attr dv_attr = {
7001                 .type = IBV_FLOW_ATTR_NORMAL,
7002                 .match_mask = (void *)&matcher->mask,
7003         };
7004         struct mlx5_flow_tbl_resource *tbl;
7005         struct mlx5_flow_tbl_data_entry *tbl_data;
7006
7007         tbl = flow_dv_tbl_resource_get(dev, key->table_id, key->direction,
7008                                        key->domain, error);
7009         if (!tbl)
7010                 return -rte_errno;      /* No need to refill the error info */
7011         tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
7012         /* Lookup from cache. */
7013         LIST_FOREACH(cache_matcher, &tbl_data->matchers, next) {
7014                 if (matcher->crc == cache_matcher->crc &&
7015                     matcher->priority == cache_matcher->priority &&
7016                     !memcmp((const void *)matcher->mask.buf,
7017                             (const void *)cache_matcher->mask.buf,
7018                             cache_matcher->mask.size)) {
7019                         DRV_LOG(DEBUG,
7020                                 "%s group %u priority %hd use %s "
7021                                 "matcher %p: refcnt %d++",
7022                                 key->domain ? "FDB" : "NIC", key->table_id,
7023                                 cache_matcher->priority,
7024                                 key->direction ? "tx" : "rx",
7025                                 (void *)cache_matcher,
7026                                 rte_atomic32_read(&cache_matcher->refcnt));
7027                         rte_atomic32_inc(&cache_matcher->refcnt);
7028                         dev_flow->handle->dvh.matcher = cache_matcher;
7029                         /* old matcher should not make the table ref++. */
7030                         flow_dv_tbl_resource_release(dev, tbl);
7031                         return 0;
7032                 }
7033         }
7034         /* Register new matcher. */
7035         cache_matcher = rte_calloc(__func__, 1, sizeof(*cache_matcher), 0);
7036         if (!cache_matcher) {
7037                 flow_dv_tbl_resource_release(dev, tbl);
7038                 return rte_flow_error_set(error, ENOMEM,
7039                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7040                                           "cannot allocate matcher memory");
7041         }
7042         *cache_matcher = *matcher;
7043         dv_attr.match_criteria_enable =
7044                 flow_dv_matcher_enable(cache_matcher->mask.buf);
7045         dv_attr.priority = matcher->priority;
7046         if (key->direction)
7047                 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
7048         cache_matcher->matcher_object =
7049                 mlx5_glue->dv_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj);
7050         if (!cache_matcher->matcher_object) {
7051                 rte_free(cache_matcher);
7052 #ifdef HAVE_MLX5DV_DR
7053                 flow_dv_tbl_resource_release(dev, tbl);
7054 #endif
7055                 return rte_flow_error_set(error, ENOMEM,
7056                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7057                                           NULL, "cannot create matcher");
7058         }
7059         /* Save the table information */
7060         cache_matcher->tbl = tbl;
7061         rte_atomic32_init(&cache_matcher->refcnt);
7062         /* only matcher ref++, table ref++ already done above in get API. */
7063         rte_atomic32_inc(&cache_matcher->refcnt);
7064         LIST_INSERT_HEAD(&tbl_data->matchers, cache_matcher, next);
7065         dev_flow->handle->dvh.matcher = cache_matcher;
7066         DRV_LOG(DEBUG, "%s group %u priority %hd new %s matcher %p: refcnt %d",
7067                 key->domain ? "FDB" : "NIC", key->table_id,
7068                 cache_matcher->priority,
7069                 key->direction ? "tx" : "rx", (void *)cache_matcher,
7070                 rte_atomic32_read(&cache_matcher->refcnt));
7071         return 0;
7072 }
7073
7074 /**
7075  * Find existing tag resource or create and register a new one.
7076  *
7077  * @param dev[in, out]
7078  *   Pointer to rte_eth_dev structure.
7079  * @param[in, out] tag_be24
7080  *   Tag value in big endian then R-shift 8.
7081  * @parm[in, out] dev_flow
7082  *   Pointer to the dev_flow.
7083  * @param[out] error
7084  *   pointer to error structure.
7085  *
7086  * @return
7087  *   0 on success otherwise -errno and errno is set.
7088  */
7089 static int
7090 flow_dv_tag_resource_register
7091                         (struct rte_eth_dev *dev,
7092                          uint32_t tag_be24,
7093                          struct mlx5_flow *dev_flow,
7094                          struct rte_flow_error *error)
7095 {
7096         struct mlx5_priv *priv = dev->data->dev_private;
7097         struct mlx5_ibv_shared *sh = priv->sh;
7098         struct mlx5_flow_dv_tag_resource *cache_resource;
7099         struct mlx5_hlist_entry *entry;
7100
7101         /* Lookup a matching resource from cache. */
7102         entry = mlx5_hlist_lookup(sh->tag_table, (uint64_t)tag_be24);
7103         if (entry) {
7104                 cache_resource = container_of
7105                         (entry, struct mlx5_flow_dv_tag_resource, entry);
7106                 rte_atomic32_inc(&cache_resource->refcnt);
7107                 dev_flow->handle->dvh.tag_resource = cache_resource->idx;
7108                 dev_flow->dv.tag_resource = cache_resource;
7109                 DRV_LOG(DEBUG, "cached tag resource %p: refcnt now %d++",
7110                         (void *)cache_resource,
7111                         rte_atomic32_read(&cache_resource->refcnt));
7112                 return 0;
7113         }
7114         /* Register new resource. */
7115         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_TAG],
7116                                        &dev_flow->handle->dvh.tag_resource);
7117         if (!cache_resource)
7118                 return rte_flow_error_set(error, ENOMEM,
7119                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7120                                           "cannot allocate resource memory");
7121         cache_resource->entry.key = (uint64_t)tag_be24;
7122         cache_resource->action = mlx5_glue->dv_create_flow_action_tag(tag_be24);
7123         if (!cache_resource->action) {
7124                 rte_free(cache_resource);
7125                 return rte_flow_error_set(error, ENOMEM,
7126                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7127                                           NULL, "cannot create action");
7128         }
7129         rte_atomic32_init(&cache_resource->refcnt);
7130         rte_atomic32_inc(&cache_resource->refcnt);
7131         if (mlx5_hlist_insert(sh->tag_table, &cache_resource->entry)) {
7132                 mlx5_glue->destroy_flow_action(cache_resource->action);
7133                 rte_free(cache_resource);
7134                 return rte_flow_error_set(error, EEXIST,
7135                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7136                                           NULL, "cannot insert tag");
7137         }
7138         dev_flow->dv.tag_resource = cache_resource;
7139         DRV_LOG(DEBUG, "new tag resource %p: refcnt now %d++",
7140                 (void *)cache_resource,
7141                 rte_atomic32_read(&cache_resource->refcnt));
7142         return 0;
7143 }
7144
7145 /**
7146  * Release the tag.
7147  *
7148  * @param dev
7149  *   Pointer to Ethernet device.
7150  * @param tag_idx
7151  *   Tag index.
7152  *
7153  * @return
7154  *   1 while a reference on it exists, 0 when freed.
7155  */
7156 static int
7157 flow_dv_tag_release(struct rte_eth_dev *dev,
7158                     uint32_t tag_idx)
7159 {
7160         struct mlx5_priv *priv = dev->data->dev_private;
7161         struct mlx5_ibv_shared *sh = priv->sh;
7162         struct mlx5_flow_dv_tag_resource *tag;
7163
7164         tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
7165         if (!tag)
7166                 return 0;
7167         DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
7168                 dev->data->port_id, (void *)tag,
7169                 rte_atomic32_read(&tag->refcnt));
7170         if (rte_atomic32_dec_and_test(&tag->refcnt)) {
7171                 claim_zero(mlx5_glue->destroy_flow_action(tag->action));
7172                 mlx5_hlist_remove(sh->tag_table, &tag->entry);
7173                 DRV_LOG(DEBUG, "port %u tag %p: removed",
7174                         dev->data->port_id, (void *)tag);
7175                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
7176                 return 0;
7177         }
7178         return 1;
7179 }
7180
7181 /**
7182  * Translate port ID action to vport.
7183  *
7184  * @param[in] dev
7185  *   Pointer to rte_eth_dev structure.
7186  * @param[in] action
7187  *   Pointer to the port ID action.
7188  * @param[out] dst_port_id
7189  *   The target port ID.
7190  * @param[out] error
7191  *   Pointer to the error structure.
7192  *
7193  * @return
7194  *   0 on success, a negative errno value otherwise and rte_errno is set.
7195  */
7196 static int
7197 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
7198                                  const struct rte_flow_action *action,
7199                                  uint32_t *dst_port_id,
7200                                  struct rte_flow_error *error)
7201 {
7202         uint32_t port;
7203         struct mlx5_priv *priv;
7204         const struct rte_flow_action_port_id *conf =
7205                         (const struct rte_flow_action_port_id *)action->conf;
7206
7207         port = conf->original ? dev->data->port_id : conf->id;
7208         priv = mlx5_port_to_eswitch_info(port, false);
7209         if (!priv)
7210                 return rte_flow_error_set(error, -rte_errno,
7211                                           RTE_FLOW_ERROR_TYPE_ACTION,
7212                                           NULL,
7213                                           "No eswitch info was found for port");
7214 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
7215         /*
7216          * This parameter is transferred to
7217          * mlx5dv_dr_action_create_dest_ib_port().
7218          */
7219         *dst_port_id = priv->ibv_port;
7220 #else
7221         /*
7222          * Legacy mode, no LAG configurations is supported.
7223          * This parameter is transferred to
7224          * mlx5dv_dr_action_create_dest_vport().
7225          */
7226         *dst_port_id = priv->vport_id;
7227 #endif
7228         return 0;
7229 }
7230
7231 /**
7232  * Add Tx queue matcher
7233  *
7234  * @param[in] dev
7235  *   Pointer to the dev struct.
7236  * @param[in, out] matcher
7237  *   Flow matcher.
7238  * @param[in, out] key
7239  *   Flow matcher value.
7240  * @param[in] item
7241  *   Flow pattern to translate.
7242  * @param[in] inner
7243  *   Item is inner pattern.
7244  */
7245 static void
7246 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
7247                                 void *matcher, void *key,
7248                                 const struct rte_flow_item *item)
7249 {
7250         const struct mlx5_rte_flow_item_tx_queue *queue_m;
7251         const struct mlx5_rte_flow_item_tx_queue *queue_v;
7252         void *misc_m =
7253                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7254         void *misc_v =
7255                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7256         struct mlx5_txq_ctrl *txq;
7257         uint32_t queue;
7258
7259
7260         queue_m = (const void *)item->mask;
7261         if (!queue_m)
7262                 return;
7263         queue_v = (const void *)item->spec;
7264         if (!queue_v)
7265                 return;
7266         txq = mlx5_txq_get(dev, queue_v->queue);
7267         if (!txq)
7268                 return;
7269         queue = txq->obj->sq->id;
7270         MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
7271         MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
7272                  queue & queue_m->queue);
7273         mlx5_txq_release(dev, queue_v->queue);
7274 }
7275
7276 /**
7277  * Set the hash fields according to the @p flow information.
7278  *
7279  * @param[in] dev_flow
7280  *   Pointer to the mlx5_flow.
7281  */
7282 static void
7283 flow_dv_hashfields_set(struct mlx5_flow *dev_flow)
7284 {
7285         struct rte_flow *flow = dev_flow->flow;
7286         uint64_t items = dev_flow->handle->layers;
7287         int rss_inner = 0;
7288         uint64_t rss_types = rte_eth_rss_hf_refine(flow->rss.types);
7289
7290         dev_flow->hash_fields = 0;
7291 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
7292         if (flow->rss.level >= 2) {
7293                 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
7294                 rss_inner = 1;
7295         }
7296 #endif
7297         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
7298             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
7299                 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
7300                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
7301                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
7302                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
7303                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
7304                         else
7305                                 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
7306                 }
7307         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
7308                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
7309                 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
7310                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
7311                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
7312                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
7313                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
7314                         else
7315                                 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
7316                 }
7317         }
7318         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
7319             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
7320                 if (rss_types & ETH_RSS_UDP) {
7321                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
7322                                 dev_flow->hash_fields |=
7323                                                 IBV_RX_HASH_SRC_PORT_UDP;
7324                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
7325                                 dev_flow->hash_fields |=
7326                                                 IBV_RX_HASH_DST_PORT_UDP;
7327                         else
7328                                 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
7329                 }
7330         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
7331                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
7332                 if (rss_types & ETH_RSS_TCP) {
7333                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
7334                                 dev_flow->hash_fields |=
7335                                                 IBV_RX_HASH_SRC_PORT_TCP;
7336                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
7337                                 dev_flow->hash_fields |=
7338                                                 IBV_RX_HASH_DST_PORT_TCP;
7339                         else
7340                                 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
7341                 }
7342         }
7343 }
7344
7345 /**
7346  * Fill the flow with DV spec, lock free
7347  * (mutex should be acquired by caller).
7348  *
7349  * @param[in] dev
7350  *   Pointer to rte_eth_dev structure.
7351  * @param[in, out] dev_flow
7352  *   Pointer to the sub flow.
7353  * @param[in] attr
7354  *   Pointer to the flow attributes.
7355  * @param[in] items
7356  *   Pointer to the list of items.
7357  * @param[in] actions
7358  *   Pointer to the list of actions.
7359  * @param[out] error
7360  *   Pointer to the error structure.
7361  *
7362  * @return
7363  *   0 on success, a negative errno value otherwise and rte_errno is set.
7364  */
7365 static int
7366 __flow_dv_translate(struct rte_eth_dev *dev,
7367                     struct mlx5_flow *dev_flow,
7368                     const struct rte_flow_attr *attr,
7369                     const struct rte_flow_item items[],
7370                     const struct rte_flow_action actions[],
7371                     struct rte_flow_error *error)
7372 {
7373         struct mlx5_priv *priv = dev->data->dev_private;
7374         struct mlx5_dev_config *dev_conf = &priv->config;
7375         struct rte_flow *flow = dev_flow->flow;
7376         struct mlx5_flow_handle *handle = dev_flow->handle;
7377         uint64_t item_flags = 0;
7378         uint64_t last_item = 0;
7379         uint64_t action_flags = 0;
7380         uint64_t priority = attr->priority;
7381         struct mlx5_flow_dv_matcher matcher = {
7382                 .mask = {
7383                         .size = sizeof(matcher.mask.buf),
7384                 },
7385         };
7386         int actions_n = 0;
7387         bool actions_end = false;
7388         union {
7389                 struct mlx5_flow_dv_modify_hdr_resource res;
7390                 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
7391                             sizeof(struct mlx5_modification_cmd) *
7392                             (MLX5_MAX_MODIFY_NUM + 1)];
7393         } mhdr_dummy;
7394         struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
7395         union flow_dv_attr flow_attr = { .attr = 0 };
7396         uint32_t tag_be;
7397         union mlx5_flow_tbl_key tbl_key;
7398         uint32_t modify_action_position = UINT32_MAX;
7399         void *match_mask = matcher.mask.buf;
7400         void *match_value = dev_flow->dv.value.buf;
7401         uint8_t next_protocol = 0xff;
7402         struct rte_vlan_hdr vlan = { 0 };
7403         uint32_t table;
7404         int ret = 0;
7405
7406         mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
7407                                            MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
7408         ret = mlx5_flow_group_to_table(attr, dev_flow->external, attr->group,
7409                                        !!priv->fdb_def_rule, &table, error);
7410         if (ret)
7411                 return ret;
7412         dev_flow->dv.group = table;
7413         if (attr->transfer)
7414                 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
7415         if (priority == MLX5_FLOW_PRIO_RSVD)
7416                 priority = dev_conf->flow_prio - 1;
7417         /* number of actions must be set to 0 in case of dirty stack. */
7418         mhdr_res->actions_num = 0;
7419         for (; !actions_end ; actions++) {
7420                 const struct rte_flow_action_queue *queue;
7421                 const struct rte_flow_action_rss *rss;
7422                 const struct rte_flow_action *action = actions;
7423                 const struct rte_flow_action_count *count = action->conf;
7424                 const uint8_t *rss_key;
7425                 const struct rte_flow_action_jump *jump_data;
7426                 const struct rte_flow_action_meter *mtr;
7427                 struct mlx5_flow_tbl_resource *tbl;
7428                 uint32_t port_id = 0;
7429                 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
7430                 int action_type = actions->type;
7431                 const struct rte_flow_action *found_action = NULL;
7432
7433                 switch (action_type) {
7434                 case RTE_FLOW_ACTION_TYPE_VOID:
7435                         break;
7436                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
7437                         if (flow_dv_translate_action_port_id(dev, action,
7438                                                              &port_id, error))
7439                                 return -rte_errno;
7440                         memset(&port_id_resource, 0, sizeof(port_id_resource));
7441                         port_id_resource.port_id = port_id;
7442                         if (flow_dv_port_id_action_resource_register
7443                             (dev, &port_id_resource, dev_flow, error))
7444                                 return -rte_errno;
7445                         MLX5_ASSERT(!handle->dvh.port_id_action);
7446                         dev_flow->dv.actions[actions_n++] =
7447                                         dev_flow->dv.port_id_action->action;
7448                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
7449                         break;
7450                 case RTE_FLOW_ACTION_TYPE_FLAG:
7451                         action_flags |= MLX5_FLOW_ACTION_FLAG;
7452                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7453                                 struct rte_flow_action_mark mark = {
7454                                         .id = MLX5_FLOW_MARK_DEFAULT,
7455                                 };
7456
7457                                 if (flow_dv_convert_action_mark(dev, &mark,
7458                                                                 mhdr_res,
7459                                                                 error))
7460                                         return -rte_errno;
7461                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
7462                                 break;
7463                         }
7464                         tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
7465                         /*
7466                          * Only one FLAG or MARK is supported per device flow
7467                          * right now. So the pointer to the tag resource must be
7468                          * zero before the register process.
7469                          */
7470                         MLX5_ASSERT(!handle->dvh.tag_resource);
7471                         if (flow_dv_tag_resource_register(dev, tag_be,
7472                                                           dev_flow, error))
7473                                 return -rte_errno;
7474                         MLX5_ASSERT(dev_flow->dv.tag_resource);
7475                         dev_flow->dv.actions[actions_n++] =
7476                                         dev_flow->dv.tag_resource->action;
7477                         break;
7478                 case RTE_FLOW_ACTION_TYPE_MARK:
7479                         action_flags |= MLX5_FLOW_ACTION_MARK;
7480                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7481                                 const struct rte_flow_action_mark *mark =
7482                                         (const struct rte_flow_action_mark *)
7483                                                 actions->conf;
7484
7485                                 if (flow_dv_convert_action_mark(dev, mark,
7486                                                                 mhdr_res,
7487                                                                 error))
7488                                         return -rte_errno;
7489                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
7490                                 break;
7491                         }
7492                         /* Fall-through */
7493                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
7494                         /* Legacy (non-extensive) MARK action. */
7495                         tag_be = mlx5_flow_mark_set
7496                               (((const struct rte_flow_action_mark *)
7497                                (actions->conf))->id);
7498                         MLX5_ASSERT(!handle->dvh.tag_resource);
7499                         if (flow_dv_tag_resource_register(dev, tag_be,
7500                                                           dev_flow, error))
7501                                 return -rte_errno;
7502                         MLX5_ASSERT(dev_flow->dv.tag_resource);
7503                         dev_flow->dv.actions[actions_n++] =
7504                                         dev_flow->dv.tag_resource->action;
7505                         break;
7506                 case RTE_FLOW_ACTION_TYPE_SET_META:
7507                         if (flow_dv_convert_action_set_meta
7508                                 (dev, mhdr_res, attr,
7509                                  (const struct rte_flow_action_set_meta *)
7510                                   actions->conf, error))
7511                                 return -rte_errno;
7512                         action_flags |= MLX5_FLOW_ACTION_SET_META;
7513                         break;
7514                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
7515                         if (flow_dv_convert_action_set_tag
7516                                 (dev, mhdr_res,
7517                                  (const struct rte_flow_action_set_tag *)
7518                                   actions->conf, error))
7519                                 return -rte_errno;
7520                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7521                         break;
7522                 case RTE_FLOW_ACTION_TYPE_DROP:
7523                         action_flags |= MLX5_FLOW_ACTION_DROP;
7524                         break;
7525                 case RTE_FLOW_ACTION_TYPE_QUEUE:
7526                         MLX5_ASSERT(flow->rss.queue);
7527                         queue = actions->conf;
7528                         flow->rss.queue_num = 1;
7529                         (*flow->rss.queue)[0] = queue->index;
7530                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
7531                         break;
7532                 case RTE_FLOW_ACTION_TYPE_RSS:
7533                         MLX5_ASSERT(flow->rss.queue);
7534                         rss = actions->conf;
7535                         if (flow->rss.queue)
7536                                 memcpy((*flow->rss.queue), rss->queue,
7537                                        rss->queue_num * sizeof(uint16_t));
7538                         flow->rss.queue_num = rss->queue_num;
7539                         /* NULL RSS key indicates default RSS key. */
7540                         rss_key = !rss->key ? rss_hash_default_key : rss->key;
7541                         memcpy(flow->rss.key, rss_key, MLX5_RSS_HASH_KEY_LEN);
7542                         /*
7543                          * rss->level and rss.types should be set in advance
7544                          * when expanding items for RSS.
7545                          */
7546                         action_flags |= MLX5_FLOW_ACTION_RSS;
7547                         break;
7548                 case RTE_FLOW_ACTION_TYPE_COUNT:
7549                         if (!dev_conf->devx) {
7550                                 rte_errno = ENOTSUP;
7551                                 goto cnt_err;
7552                         }
7553                         flow->counter = flow_dv_counter_alloc(dev,
7554                                                         count->shared,
7555                                                         count->id,
7556                                                         dev_flow->dv.group);
7557                         if (!flow->counter)
7558                                 goto cnt_err;
7559                         dev_flow->dv.actions[actions_n++] =
7560                                   (flow_dv_counter_get_by_idx(dev,
7561                                   flow->counter, NULL))->action;
7562                         action_flags |= MLX5_FLOW_ACTION_COUNT;
7563                         break;
7564 cnt_err:
7565                         if (rte_errno == ENOTSUP)
7566                                 return rte_flow_error_set
7567                                               (error, ENOTSUP,
7568                                                RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7569                                                NULL,
7570                                                "count action not supported");
7571                         else
7572                                 return rte_flow_error_set
7573                                                 (error, rte_errno,
7574                                                  RTE_FLOW_ERROR_TYPE_ACTION,
7575                                                  action,
7576                                                  "cannot create counter"
7577                                                   " object.");
7578                         break;
7579                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
7580                         dev_flow->dv.actions[actions_n++] =
7581                                                 priv->sh->pop_vlan_action;
7582                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
7583                         break;
7584                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
7585                         if (!(action_flags &
7586                               MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
7587                                 flow_dev_get_vlan_info_from_items(items, &vlan);
7588                         vlan.eth_proto = rte_be_to_cpu_16
7589                              ((((const struct rte_flow_action_of_push_vlan *)
7590                                                    actions->conf)->ethertype));
7591                         found_action = mlx5_flow_find_action
7592                                         (actions + 1,
7593                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
7594                         if (found_action)
7595                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
7596                         found_action = mlx5_flow_find_action
7597                                         (actions + 1,
7598                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
7599                         if (found_action)
7600                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
7601                         if (flow_dv_create_action_push_vlan
7602                                             (dev, attr, &vlan, dev_flow, error))
7603                                 return -rte_errno;
7604                         dev_flow->dv.actions[actions_n++] =
7605                                         dev_flow->dv.push_vlan_res->action;
7606                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
7607                         break;
7608                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
7609                         /* of_vlan_push action handled this action */
7610                         MLX5_ASSERT(action_flags &
7611                                     MLX5_FLOW_ACTION_OF_PUSH_VLAN);
7612                         break;
7613                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
7614                         if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
7615                                 break;
7616                         flow_dev_get_vlan_info_from_items(items, &vlan);
7617                         mlx5_update_vlan_vid_pcp(actions, &vlan);
7618                         /* If no VLAN push - this is a modify header action */
7619                         if (flow_dv_convert_action_modify_vlan_vid
7620                                                 (mhdr_res, actions, error))
7621                                 return -rte_errno;
7622                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
7623                         break;
7624                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
7625                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
7626                         if (flow_dv_create_action_l2_encap(dev, actions,
7627                                                            dev_flow,
7628                                                            attr->transfer,
7629                                                            error))
7630                                 return -rte_errno;
7631                         dev_flow->dv.actions[actions_n++] =
7632                                         dev_flow->dv.encap_decap->verbs_action;
7633                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
7634                         break;
7635                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
7636                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
7637                         if (flow_dv_create_action_l2_decap(dev, dev_flow,
7638                                                            attr->transfer,
7639                                                            error))
7640                                 return -rte_errno;
7641                         dev_flow->dv.actions[actions_n++] =
7642                                         dev_flow->dv.encap_decap->verbs_action;
7643                         action_flags |= MLX5_FLOW_ACTION_DECAP;
7644                         break;
7645                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
7646                         /* Handle encap with preceding decap. */
7647                         if (action_flags & MLX5_FLOW_ACTION_DECAP) {
7648                                 if (flow_dv_create_action_raw_encap
7649                                         (dev, actions, dev_flow, attr, error))
7650                                         return -rte_errno;
7651                                 dev_flow->dv.actions[actions_n++] =
7652                                         dev_flow->dv.encap_decap->verbs_action;
7653                         } else {
7654                                 /* Handle encap without preceding decap. */
7655                                 if (flow_dv_create_action_l2_encap
7656                                     (dev, actions, dev_flow, attr->transfer,
7657                                      error))
7658                                         return -rte_errno;
7659                                 dev_flow->dv.actions[actions_n++] =
7660                                         dev_flow->dv.encap_decap->verbs_action;
7661                         }
7662                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
7663                         break;
7664                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
7665                         while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
7666                                 ;
7667                         if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
7668                                 if (flow_dv_create_action_l2_decap
7669                                     (dev, dev_flow, attr->transfer, error))
7670                                         return -rte_errno;
7671                                 dev_flow->dv.actions[actions_n++] =
7672                                         dev_flow->dv.encap_decap->verbs_action;
7673                         }
7674                         /* If decap is followed by encap, handle it at encap. */
7675                         action_flags |= MLX5_FLOW_ACTION_DECAP;
7676                         break;
7677                 case RTE_FLOW_ACTION_TYPE_JUMP:
7678                         jump_data = action->conf;
7679                         ret = mlx5_flow_group_to_table(attr, dev_flow->external,
7680                                                        jump_data->group,
7681                                                        !!priv->fdb_def_rule,
7682                                                        &table, error);
7683                         if (ret)
7684                                 return ret;
7685                         tbl = flow_dv_tbl_resource_get(dev, table,
7686                                                        attr->egress,
7687                                                        attr->transfer, error);
7688                         if (!tbl)
7689                                 return rte_flow_error_set
7690                                                 (error, errno,
7691                                                  RTE_FLOW_ERROR_TYPE_ACTION,
7692                                                  NULL,
7693                                                  "cannot create jump action.");
7694                         if (flow_dv_jump_tbl_resource_register
7695                             (dev, tbl, dev_flow, error)) {
7696                                 flow_dv_tbl_resource_release(dev, tbl);
7697                                 return rte_flow_error_set
7698                                                 (error, errno,
7699                                                  RTE_FLOW_ERROR_TYPE_ACTION,
7700                                                  NULL,
7701                                                  "cannot create jump action.");
7702                         }
7703                         dev_flow->dv.actions[actions_n++] =
7704                                         dev_flow->dv.jump->action;
7705                         action_flags |= MLX5_FLOW_ACTION_JUMP;
7706                         break;
7707                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
7708                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
7709                         if (flow_dv_convert_action_modify_mac
7710                                         (mhdr_res, actions, error))
7711                                 return -rte_errno;
7712                         action_flags |= actions->type ==
7713                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
7714                                         MLX5_FLOW_ACTION_SET_MAC_SRC :
7715                                         MLX5_FLOW_ACTION_SET_MAC_DST;
7716                         break;
7717                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
7718                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
7719                         if (flow_dv_convert_action_modify_ipv4
7720                                         (mhdr_res, actions, error))
7721                                 return -rte_errno;
7722                         action_flags |= actions->type ==
7723                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
7724                                         MLX5_FLOW_ACTION_SET_IPV4_SRC :
7725                                         MLX5_FLOW_ACTION_SET_IPV4_DST;
7726                         break;
7727                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
7728                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
7729                         if (flow_dv_convert_action_modify_ipv6
7730                                         (mhdr_res, actions, error))
7731                                 return -rte_errno;
7732                         action_flags |= actions->type ==
7733                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
7734                                         MLX5_FLOW_ACTION_SET_IPV6_SRC :
7735                                         MLX5_FLOW_ACTION_SET_IPV6_DST;
7736                         break;
7737                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
7738                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
7739                         if (flow_dv_convert_action_modify_tp
7740                                         (mhdr_res, actions, items,
7741                                          &flow_attr, dev_flow, !!(action_flags &
7742                                          MLX5_FLOW_ACTION_DECAP), error))
7743                                 return -rte_errno;
7744                         action_flags |= actions->type ==
7745                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
7746                                         MLX5_FLOW_ACTION_SET_TP_SRC :
7747                                         MLX5_FLOW_ACTION_SET_TP_DST;
7748                         break;
7749                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
7750                         if (flow_dv_convert_action_modify_dec_ttl
7751                                         (mhdr_res, items, &flow_attr, dev_flow,
7752                                          !!(action_flags &
7753                                          MLX5_FLOW_ACTION_DECAP), error))
7754                                 return -rte_errno;
7755                         action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
7756                         break;
7757                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
7758                         if (flow_dv_convert_action_modify_ttl
7759                                         (mhdr_res, actions, items, &flow_attr,
7760                                          dev_flow, !!(action_flags &
7761                                          MLX5_FLOW_ACTION_DECAP), error))
7762                                 return -rte_errno;
7763                         action_flags |= MLX5_FLOW_ACTION_SET_TTL;
7764                         break;
7765                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
7766                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
7767                         if (flow_dv_convert_action_modify_tcp_seq
7768                                         (mhdr_res, actions, error))
7769                                 return -rte_errno;
7770                         action_flags |= actions->type ==
7771                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
7772                                         MLX5_FLOW_ACTION_INC_TCP_SEQ :
7773                                         MLX5_FLOW_ACTION_DEC_TCP_SEQ;
7774                         break;
7775
7776                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
7777                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
7778                         if (flow_dv_convert_action_modify_tcp_ack
7779                                         (mhdr_res, actions, error))
7780                                 return -rte_errno;
7781                         action_flags |= actions->type ==
7782                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
7783                                         MLX5_FLOW_ACTION_INC_TCP_ACK :
7784                                         MLX5_FLOW_ACTION_DEC_TCP_ACK;
7785                         break;
7786                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
7787                         if (flow_dv_convert_action_set_reg
7788                                         (mhdr_res, actions, error))
7789                                 return -rte_errno;
7790                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7791                         break;
7792                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
7793                         if (flow_dv_convert_action_copy_mreg
7794                                         (dev, mhdr_res, actions, error))
7795                                 return -rte_errno;
7796                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7797                         break;
7798                 case RTE_FLOW_ACTION_TYPE_METER:
7799                         mtr = actions->conf;
7800                         if (!flow->meter) {
7801                                 flow->meter = mlx5_flow_meter_attach(priv,
7802                                                         mtr->mtr_id, attr,
7803                                                         error);
7804                                 if (!flow->meter)
7805                                         return rte_flow_error_set(error,
7806                                                 rte_errno,
7807                                                 RTE_FLOW_ERROR_TYPE_ACTION,
7808                                                 NULL,
7809                                                 "meter not found "
7810                                                 "or invalid parameters");
7811                         }
7812                         /* Set the meter action. */
7813                         dev_flow->dv.actions[actions_n++] =
7814                                 flow->meter->mfts->meter_action;
7815                         action_flags |= MLX5_FLOW_ACTION_METER;
7816                         break;
7817                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
7818                         if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
7819                                                               actions, error))
7820                                 return -rte_errno;
7821                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
7822                         break;
7823                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
7824                         if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
7825                                                               actions, error))
7826                                 return -rte_errno;
7827                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
7828                         break;
7829                 case RTE_FLOW_ACTION_TYPE_END:
7830                         actions_end = true;
7831                         if (mhdr_res->actions_num) {
7832                                 /* create modify action if needed. */
7833                                 if (flow_dv_modify_hdr_resource_register
7834                                         (dev, mhdr_res, dev_flow, error))
7835                                         return -rte_errno;
7836                                 dev_flow->dv.actions[modify_action_position] =
7837                                         handle->dvh.modify_hdr->verbs_action;
7838                         }
7839                         break;
7840                 default:
7841                         break;
7842                 }
7843                 if (mhdr_res->actions_num &&
7844                     modify_action_position == UINT32_MAX)
7845                         modify_action_position = actions_n++;
7846         }
7847         dev_flow->dv.actions_n = actions_n;
7848         handle->act_flags = action_flags;
7849         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
7850                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
7851                 int item_type = items->type;
7852
7853                 switch (item_type) {
7854                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
7855                         flow_dv_translate_item_port_id(dev, match_mask,
7856                                                        match_value, items);
7857                         last_item = MLX5_FLOW_ITEM_PORT_ID;
7858                         break;
7859                 case RTE_FLOW_ITEM_TYPE_ETH:
7860                         flow_dv_translate_item_eth(match_mask, match_value,
7861                                                    items, tunnel);
7862                         matcher.priority = MLX5_PRIORITY_MAP_L2;
7863                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
7864                                              MLX5_FLOW_LAYER_OUTER_L2;
7865                         break;
7866                 case RTE_FLOW_ITEM_TYPE_VLAN:
7867                         flow_dv_translate_item_vlan(dev_flow,
7868                                                     match_mask, match_value,
7869                                                     items, tunnel);
7870                         matcher.priority = MLX5_PRIORITY_MAP_L2;
7871                         last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
7872                                               MLX5_FLOW_LAYER_INNER_VLAN) :
7873                                              (MLX5_FLOW_LAYER_OUTER_L2 |
7874                                               MLX5_FLOW_LAYER_OUTER_VLAN);
7875                         break;
7876                 case RTE_FLOW_ITEM_TYPE_IPV4:
7877                         mlx5_flow_tunnel_ip_check(items, next_protocol,
7878                                                   &item_flags, &tunnel);
7879                         flow_dv_translate_item_ipv4(match_mask, match_value,
7880                                                     items, item_flags, tunnel,
7881                                                     dev_flow->dv.group);
7882                         matcher.priority = MLX5_PRIORITY_MAP_L3;
7883                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
7884                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
7885                         if (items->mask != NULL &&
7886                             ((const struct rte_flow_item_ipv4 *)
7887                              items->mask)->hdr.next_proto_id) {
7888                                 next_protocol =
7889                                         ((const struct rte_flow_item_ipv4 *)
7890                                          (items->spec))->hdr.next_proto_id;
7891                                 next_protocol &=
7892                                         ((const struct rte_flow_item_ipv4 *)
7893                                          (items->mask))->hdr.next_proto_id;
7894                         } else {
7895                                 /* Reset for inner layer. */
7896                                 next_protocol = 0xff;
7897                         }
7898                         break;
7899                 case RTE_FLOW_ITEM_TYPE_IPV6:
7900                         mlx5_flow_tunnel_ip_check(items, next_protocol,
7901                                                   &item_flags, &tunnel);
7902                         flow_dv_translate_item_ipv6(match_mask, match_value,
7903                                                     items, item_flags, tunnel,
7904                                                     dev_flow->dv.group);
7905                         matcher.priority = MLX5_PRIORITY_MAP_L3;
7906                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
7907                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
7908                         if (items->mask != NULL &&
7909                             ((const struct rte_flow_item_ipv6 *)
7910                              items->mask)->hdr.proto) {
7911                                 next_protocol =
7912                                         ((const struct rte_flow_item_ipv6 *)
7913                                          items->spec)->hdr.proto;
7914                                 next_protocol &=
7915                                         ((const struct rte_flow_item_ipv6 *)
7916                                          items->mask)->hdr.proto;
7917                         } else {
7918                                 /* Reset for inner layer. */
7919                                 next_protocol = 0xff;
7920                         }
7921                         break;
7922                 case RTE_FLOW_ITEM_TYPE_TCP:
7923                         flow_dv_translate_item_tcp(match_mask, match_value,
7924                                                    items, tunnel);
7925                         matcher.priority = MLX5_PRIORITY_MAP_L4;
7926                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
7927                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
7928                         break;
7929                 case RTE_FLOW_ITEM_TYPE_UDP:
7930                         flow_dv_translate_item_udp(match_mask, match_value,
7931                                                    items, tunnel);
7932                         matcher.priority = MLX5_PRIORITY_MAP_L4;
7933                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
7934                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
7935                         break;
7936                 case RTE_FLOW_ITEM_TYPE_GRE:
7937                         flow_dv_translate_item_gre(match_mask, match_value,
7938                                                    items, tunnel);
7939                         matcher.priority = flow->rss.level >= 2 ?
7940                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7941                         last_item = MLX5_FLOW_LAYER_GRE;
7942                         break;
7943                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
7944                         flow_dv_translate_item_gre_key(match_mask,
7945                                                        match_value, items);
7946                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
7947                         break;
7948                 case RTE_FLOW_ITEM_TYPE_NVGRE:
7949                         flow_dv_translate_item_nvgre(match_mask, match_value,
7950                                                      items, tunnel);
7951                         matcher.priority = flow->rss.level >= 2 ?
7952                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7953                         last_item = MLX5_FLOW_LAYER_GRE;
7954                         break;
7955                 case RTE_FLOW_ITEM_TYPE_VXLAN:
7956                         flow_dv_translate_item_vxlan(match_mask, match_value,
7957                                                      items, tunnel);
7958                         matcher.priority = flow->rss.level >= 2 ?
7959                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7960                         last_item = MLX5_FLOW_LAYER_VXLAN;
7961                         break;
7962                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
7963                         flow_dv_translate_item_vxlan_gpe(match_mask,
7964                                                          match_value, items,
7965                                                          tunnel);
7966                         matcher.priority = flow->rss.level >= 2 ?
7967                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7968                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
7969                         break;
7970                 case RTE_FLOW_ITEM_TYPE_GENEVE:
7971                         flow_dv_translate_item_geneve(match_mask, match_value,
7972                                                       items, tunnel);
7973                         matcher.priority = flow->rss.level >= 2 ?
7974                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7975                         last_item = MLX5_FLOW_LAYER_GENEVE;
7976                         break;
7977                 case RTE_FLOW_ITEM_TYPE_MPLS:
7978                         flow_dv_translate_item_mpls(match_mask, match_value,
7979                                                     items, last_item, tunnel);
7980                         matcher.priority = flow->rss.level >= 2 ?
7981                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7982                         last_item = MLX5_FLOW_LAYER_MPLS;
7983                         break;
7984                 case RTE_FLOW_ITEM_TYPE_MARK:
7985                         flow_dv_translate_item_mark(dev, match_mask,
7986                                                     match_value, items);
7987                         last_item = MLX5_FLOW_ITEM_MARK;
7988                         break;
7989                 case RTE_FLOW_ITEM_TYPE_META:
7990                         flow_dv_translate_item_meta(dev, match_mask,
7991                                                     match_value, attr, items);
7992                         last_item = MLX5_FLOW_ITEM_METADATA;
7993                         break;
7994                 case RTE_FLOW_ITEM_TYPE_ICMP:
7995                         flow_dv_translate_item_icmp(match_mask, match_value,
7996                                                     items, tunnel);
7997                         last_item = MLX5_FLOW_LAYER_ICMP;
7998                         break;
7999                 case RTE_FLOW_ITEM_TYPE_ICMP6:
8000                         flow_dv_translate_item_icmp6(match_mask, match_value,
8001                                                       items, tunnel);
8002                         last_item = MLX5_FLOW_LAYER_ICMP6;
8003                         break;
8004                 case RTE_FLOW_ITEM_TYPE_TAG:
8005                         flow_dv_translate_item_tag(dev, match_mask,
8006                                                    match_value, items);
8007                         last_item = MLX5_FLOW_ITEM_TAG;
8008                         break;
8009                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
8010                         flow_dv_translate_mlx5_item_tag(dev, match_mask,
8011                                                         match_value, items);
8012                         last_item = MLX5_FLOW_ITEM_TAG;
8013                         break;
8014                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
8015                         flow_dv_translate_item_tx_queue(dev, match_mask,
8016                                                         match_value,
8017                                                         items);
8018                         last_item = MLX5_FLOW_ITEM_TX_QUEUE;
8019                         break;
8020                 case RTE_FLOW_ITEM_TYPE_GTP:
8021                         flow_dv_translate_item_gtp(match_mask, match_value,
8022                                                    items, tunnel);
8023                         matcher.priority = flow->rss.level >= 2 ?
8024                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8025                         last_item = MLX5_FLOW_LAYER_GTP;
8026                         break;
8027                 default:
8028                         break;
8029                 }
8030                 item_flags |= last_item;
8031         }
8032         /*
8033          * When E-Switch mode is enabled, we have two cases where we need to
8034          * set the source port manually.
8035          * The first one, is in case of Nic steering rule, and the second is
8036          * E-Switch rule where no port_id item was found. In both cases
8037          * the source port is set according the current port in use.
8038          */
8039         if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
8040             (priv->representor || priv->master)) {
8041                 if (flow_dv_translate_item_port_id(dev, match_mask,
8042                                                    match_value, NULL))
8043                         return -rte_errno;
8044         }
8045 #ifdef RTE_LIBRTE_MLX5_DEBUG
8046         MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
8047                                               dev_flow->dv.value.buf));
8048 #endif
8049         /*
8050          * Layers may be already initialized from prefix flow if this dev_flow
8051          * is the suffix flow.
8052          */
8053         handle->layers |= item_flags;
8054         if (action_flags & MLX5_FLOW_ACTION_RSS)
8055                 flow_dv_hashfields_set(dev_flow);
8056         /* Register matcher. */
8057         matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
8058                                     matcher.mask.size);
8059         matcher.priority = mlx5_flow_adjust_priority(dev, priority,
8060                                                      matcher.priority);
8061         /* reserved field no needs to be set to 0 here. */
8062         tbl_key.domain = attr->transfer;
8063         tbl_key.direction = attr->egress;
8064         tbl_key.table_id = dev_flow->dv.group;
8065         if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow, error))
8066                 return -rte_errno;
8067         return 0;
8068 }
8069
8070 /**
8071  * Apply the flow to the NIC, lock free,
8072  * (mutex should be acquired by caller).
8073  *
8074  * @param[in] dev
8075  *   Pointer to the Ethernet device structure.
8076  * @param[in, out] flow
8077  *   Pointer to flow structure.
8078  * @param[out] error
8079  *   Pointer to error structure.
8080  *
8081  * @return
8082  *   0 on success, a negative errno value otherwise and rte_errno is set.
8083  */
8084 static int
8085 __flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
8086                 struct rte_flow_error *error)
8087 {
8088         struct mlx5_flow_dv_workspace *dv;
8089         struct mlx5_flow_handle *dh;
8090         struct mlx5_flow_handle_dv *dv_h;
8091         struct mlx5_flow *dev_flow;
8092         struct mlx5_priv *priv = dev->data->dev_private;
8093         uint32_t handle_idx;
8094         int n;
8095         int err;
8096         int idx;
8097
8098         for (idx = priv->flow_idx - 1; idx >= priv->flow_nested_idx; idx--) {
8099                 dev_flow = &((struct mlx5_flow *)priv->inter_flows)[idx];
8100                 dv = &dev_flow->dv;
8101                 dh = dev_flow->handle;
8102                 dv_h = &dh->dvh;
8103                 n = dv->actions_n;
8104                 if (dh->act_flags & MLX5_FLOW_ACTION_DROP) {
8105                         if (dv->transfer) {
8106                                 dv->actions[n++] = priv->sh->esw_drop_action;
8107                         } else {
8108                                 struct mlx5_hrxq *drop_hrxq;
8109                                 drop_hrxq = mlx5_hrxq_drop_new(dev);
8110                                 if (!drop_hrxq) {
8111                                         rte_flow_error_set
8112                                                 (error, errno,
8113                                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8114                                                  NULL,
8115                                                  "cannot get drop hash queue");
8116                                         goto error;
8117                                 }
8118                                 dv->actions[n++] = drop_hrxq->action;
8119                         }
8120                 } else if (dh->act_flags &
8121                            (MLX5_FLOW_ACTION_QUEUE | MLX5_FLOW_ACTION_RSS)) {
8122                         struct mlx5_hrxq *hrxq;
8123                         uint32_t hrxq_idx;
8124
8125                         MLX5_ASSERT(flow->rss.queue);
8126                         hrxq_idx = mlx5_hrxq_get(dev, flow->rss.key,
8127                                                  MLX5_RSS_HASH_KEY_LEN,
8128                                                  dev_flow->hash_fields,
8129                                                  (*flow->rss.queue),
8130                                                  flow->rss.queue_num);
8131                         if (!hrxq_idx) {
8132                                 hrxq_idx = mlx5_hrxq_new
8133                                                 (dev, flow->rss.key,
8134                                                 MLX5_RSS_HASH_KEY_LEN,
8135                                                 dev_flow->hash_fields,
8136                                                 (*flow->rss.queue),
8137                                                 flow->rss.queue_num,
8138                                                 !!(dh->layers &
8139                                                 MLX5_FLOW_LAYER_TUNNEL));
8140                         }
8141                         hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
8142                                               hrxq_idx);
8143                         if (!hrxq) {
8144                                 rte_flow_error_set
8145                                         (error, rte_errno,
8146                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8147                                          "cannot get hash queue");
8148                                 goto error;
8149                         }
8150                         dh->hrxq = hrxq_idx;
8151                         dv->actions[n++] = hrxq->action;
8152                 }
8153                 dh->ib_flow =
8154                         mlx5_glue->dv_create_flow(dv_h->matcher->matcher_object,
8155                                                   (void *)&dv->value, n,
8156                                                   dv->actions);
8157                 if (!dh->ib_flow) {
8158                         rte_flow_error_set(error, errno,
8159                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8160                                            NULL,
8161                                            "hardware refuses to create flow");
8162                         goto error;
8163                 }
8164                 if (priv->vmwa_context &&
8165                     dh->vf_vlan.tag && !dh->vf_vlan.created) {
8166                         /*
8167                          * The rule contains the VLAN pattern.
8168                          * For VF we are going to create VLAN
8169                          * interface to make hypervisor set correct
8170                          * e-Switch vport context.
8171                          */
8172                         mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
8173                 }
8174         }
8175         return 0;
8176 error:
8177         err = rte_errno; /* Save rte_errno before cleanup. */
8178         SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles,
8179                        handle_idx, dh, next) {
8180                 if (dh->hrxq) {
8181                         if (dh->act_flags & MLX5_FLOW_ACTION_DROP)
8182                                 mlx5_hrxq_drop_release(dev);
8183                         else
8184                                 mlx5_hrxq_release(dev, dh->hrxq);
8185                         dh->hrxq = 0;
8186                 }
8187                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
8188                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
8189         }
8190         rte_errno = err; /* Restore rte_errno. */
8191         return -rte_errno;
8192 }
8193
8194 /**
8195  * Release the flow matcher.
8196  *
8197  * @param dev
8198  *   Pointer to Ethernet device.
8199  * @param handle
8200  *   Pointer to mlx5_flow_handle.
8201  *
8202  * @return
8203  *   1 while a reference on it exists, 0 when freed.
8204  */
8205 static int
8206 flow_dv_matcher_release(struct rte_eth_dev *dev,
8207                         struct mlx5_flow_handle *handle)
8208 {
8209         struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
8210
8211         MLX5_ASSERT(matcher->matcher_object);
8212         DRV_LOG(DEBUG, "port %u matcher %p: refcnt %d--",
8213                 dev->data->port_id, (void *)matcher,
8214                 rte_atomic32_read(&matcher->refcnt));
8215         if (rte_atomic32_dec_and_test(&matcher->refcnt)) {
8216                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8217                            (matcher->matcher_object));
8218                 LIST_REMOVE(matcher, next);
8219                 /* table ref-- in release interface. */
8220                 flow_dv_tbl_resource_release(dev, matcher->tbl);
8221                 rte_free(matcher);
8222                 DRV_LOG(DEBUG, "port %u matcher %p: removed",
8223                         dev->data->port_id, (void *)matcher);
8224                 return 0;
8225         }
8226         return 1;
8227 }
8228
8229 /**
8230  * Release an encap/decap resource.
8231  *
8232  * @param dev
8233  *   Pointer to Ethernet device.
8234  * @param handle
8235  *   Pointer to mlx5_flow_handle.
8236  *
8237  * @return
8238  *   1 while a reference on it exists, 0 when freed.
8239  */
8240 static int
8241 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
8242                                      struct mlx5_flow_handle *handle)
8243 {
8244         struct mlx5_priv *priv = dev->data->dev_private;
8245         uint32_t idx = handle->dvh.encap_decap;
8246         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
8247
8248         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
8249                          idx);
8250         if (!cache_resource)
8251                 return 0;
8252         MLX5_ASSERT(cache_resource->verbs_action);
8253         DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d--",
8254                 (void *)cache_resource,
8255                 rte_atomic32_read(&cache_resource->refcnt));
8256         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8257                 claim_zero(mlx5_glue->destroy_flow_action
8258                                 (cache_resource->verbs_action));
8259                 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
8260                              &priv->sh->encaps_decaps, idx,
8261                              cache_resource, next);
8262                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);
8263                 DRV_LOG(DEBUG, "encap/decap resource %p: removed",
8264                         (void *)cache_resource);
8265                 return 0;
8266         }
8267         return 1;
8268 }
8269
8270 /**
8271  * Release an jump to table action resource.
8272  *
8273  * @param dev
8274  *   Pointer to Ethernet device.
8275  * @param handle
8276  *   Pointer to mlx5_flow_handle.
8277  *
8278  * @return
8279  *   1 while a reference on it exists, 0 when freed.
8280  */
8281 static int
8282 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
8283                                   struct mlx5_flow_handle *handle)
8284 {
8285         struct mlx5_priv *priv = dev->data->dev_private;
8286         struct mlx5_flow_dv_jump_tbl_resource *cache_resource;
8287         struct mlx5_flow_tbl_data_entry *tbl_data;
8288
8289         tbl_data = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_JUMP],
8290                              handle->dvh.jump);
8291         if (!tbl_data)
8292                 return 0;
8293         cache_resource = &tbl_data->jump;
8294         MLX5_ASSERT(cache_resource->action);
8295         DRV_LOG(DEBUG, "jump table resource %p: refcnt %d--",
8296                 (void *)cache_resource,
8297                 rte_atomic32_read(&cache_resource->refcnt));
8298         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8299                 claim_zero(mlx5_glue->destroy_flow_action
8300                                 (cache_resource->action));
8301                 /* jump action memory free is inside the table release. */
8302                 flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
8303                 DRV_LOG(DEBUG, "jump table resource %p: removed",
8304                         (void *)cache_resource);
8305                 return 0;
8306         }
8307         return 1;
8308 }
8309
8310 /**
8311  * Release a modify-header resource.
8312  *
8313  * @param handle
8314  *   Pointer to mlx5_flow_handle.
8315  *
8316  * @return
8317  *   1 while a reference on it exists, 0 when freed.
8318  */
8319 static int
8320 flow_dv_modify_hdr_resource_release(struct mlx5_flow_handle *handle)
8321 {
8322         struct mlx5_flow_dv_modify_hdr_resource *cache_resource =
8323                                                         handle->dvh.modify_hdr;
8324
8325         MLX5_ASSERT(cache_resource->verbs_action);
8326         DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d--",
8327                 (void *)cache_resource,
8328                 rte_atomic32_read(&cache_resource->refcnt));
8329         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8330                 claim_zero(mlx5_glue->destroy_flow_action
8331                                 (cache_resource->verbs_action));
8332                 LIST_REMOVE(cache_resource, next);
8333                 rte_free(cache_resource);
8334                 DRV_LOG(DEBUG, "modify-header resource %p: removed",
8335                         (void *)cache_resource);
8336                 return 0;
8337         }
8338         return 1;
8339 }
8340
8341 /**
8342  * Release port ID action resource.
8343  *
8344  * @param dev
8345  *   Pointer to Ethernet device.
8346  * @param handle
8347  *   Pointer to mlx5_flow_handle.
8348  *
8349  * @return
8350  *   1 while a reference on it exists, 0 when freed.
8351  */
8352 static int
8353 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
8354                                         struct mlx5_flow_handle *handle)
8355 {
8356         struct mlx5_priv *priv = dev->data->dev_private;
8357         struct mlx5_flow_dv_port_id_action_resource *cache_resource;
8358         uint32_t idx = handle->dvh.port_id_action;
8359
8360         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID],
8361                                         idx);
8362         if (!cache_resource)
8363                 return 0;
8364         MLX5_ASSERT(cache_resource->action);
8365         DRV_LOG(DEBUG, "port ID action resource %p: refcnt %d--",
8366                 (void *)cache_resource,
8367                 rte_atomic32_read(&cache_resource->refcnt));
8368         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8369                 claim_zero(mlx5_glue->destroy_flow_action
8370                                 (cache_resource->action));
8371                 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_PORT_ID],
8372                              &priv->sh->port_id_action_list, idx,
8373                              cache_resource, next);
8374                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_PORT_ID], idx);
8375                 DRV_LOG(DEBUG, "port id action resource %p: removed",
8376                         (void *)cache_resource);
8377                 return 0;
8378         }
8379         return 1;
8380 }
8381
8382 /**
8383  * Release push vlan action resource.
8384  *
8385  * @param dev
8386  *   Pointer to Ethernet device.
8387  * @param handle
8388  *   Pointer to mlx5_flow_handle.
8389  *
8390  * @return
8391  *   1 while a reference on it exists, 0 when freed.
8392  */
8393 static int
8394 flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,
8395                                           struct mlx5_flow_handle *handle)
8396 {
8397         struct mlx5_priv *priv = dev->data->dev_private;
8398         uint32_t idx = handle->dvh.push_vlan_res;
8399         struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
8400
8401         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN],
8402                                         idx);
8403         if (!cache_resource)
8404                 return 0;
8405         MLX5_ASSERT(cache_resource->action);
8406         DRV_LOG(DEBUG, "push VLAN action resource %p: refcnt %d--",
8407                 (void *)cache_resource,
8408                 rte_atomic32_read(&cache_resource->refcnt));
8409         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8410                 claim_zero(mlx5_glue->destroy_flow_action
8411                                 (cache_resource->action));
8412                 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN],
8413                              &priv->sh->push_vlan_action_list, idx,
8414                              cache_resource, next);
8415                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
8416                 DRV_LOG(DEBUG, "push vlan action resource %p: removed",
8417                         (void *)cache_resource);
8418                 return 0;
8419         }
8420         return 1;
8421 }
8422
8423 /**
8424  * Remove the flow from the NIC but keeps it in memory.
8425  * Lock free, (mutex should be acquired by caller).
8426  *
8427  * @param[in] dev
8428  *   Pointer to Ethernet device.
8429  * @param[in, out] flow
8430  *   Pointer to flow structure.
8431  */
8432 static void
8433 __flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
8434 {
8435         struct mlx5_flow_handle *dh;
8436         uint32_t handle_idx;
8437         struct mlx5_priv *priv = dev->data->dev_private;
8438
8439         if (!flow)
8440                 return;
8441         handle_idx = flow->dev_handles;
8442         while (handle_idx) {
8443                 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
8444                                     handle_idx);
8445                 if (!dh)
8446                         return;
8447                 if (dh->ib_flow) {
8448                         claim_zero(mlx5_glue->dv_destroy_flow(dh->ib_flow));
8449                         dh->ib_flow = NULL;
8450                 }
8451                 if (dh->hrxq) {
8452                         if (dh->act_flags & MLX5_FLOW_ACTION_DROP)
8453                                 mlx5_hrxq_drop_release(dev);
8454                         else
8455                                 mlx5_hrxq_release(dev, dh->hrxq);
8456                         dh->hrxq = 0;
8457                 }
8458                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
8459                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
8460                 handle_idx = dh->next.next;
8461         }
8462 }
8463
8464 /**
8465  * Remove the flow from the NIC and the memory.
8466  * Lock free, (mutex should be acquired by caller).
8467  *
8468  * @param[in] dev
8469  *   Pointer to the Ethernet device structure.
8470  * @param[in, out] flow
8471  *   Pointer to flow structure.
8472  */
8473 static void
8474 __flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
8475 {
8476         struct mlx5_flow_handle *dev_handle;
8477         struct mlx5_priv *priv = dev->data->dev_private;
8478
8479         if (!flow)
8480                 return;
8481         __flow_dv_remove(dev, flow);
8482         if (flow->counter) {
8483                 flow_dv_counter_release(dev, flow->counter);
8484                 flow->counter = 0;
8485         }
8486         if (flow->meter) {
8487                 mlx5_flow_meter_detach(flow->meter);
8488                 flow->meter = NULL;
8489         }
8490         while (flow->dev_handles) {
8491                 uint32_t tmp_idx = flow->dev_handles;
8492
8493                 dev_handle = mlx5_ipool_get(priv->sh->ipool
8494                                             [MLX5_IPOOL_MLX5_FLOW], tmp_idx);
8495                 if (!dev_handle)
8496                         return;
8497                 flow->dev_handles = dev_handle->next.next;
8498                 if (dev_handle->dvh.matcher)
8499                         flow_dv_matcher_release(dev, dev_handle);
8500                 if (dev_handle->dvh.encap_decap)
8501                         flow_dv_encap_decap_resource_release(dev, dev_handle);
8502                 if (dev_handle->dvh.modify_hdr)
8503                         flow_dv_modify_hdr_resource_release(dev_handle);
8504                 if (dev_handle->dvh.jump)
8505                         flow_dv_jump_tbl_resource_release(dev, dev_handle);
8506                 if (dev_handle->dvh.port_id_action)
8507                         flow_dv_port_id_action_resource_release(dev,
8508                                                                 dev_handle);
8509                 if (dev_handle->dvh.push_vlan_res)
8510                         flow_dv_push_vlan_action_resource_release(dev,
8511                                                                   dev_handle);
8512                 if (dev_handle->dvh.tag_resource)
8513                         flow_dv_tag_release(dev,
8514                                             dev_handle->dvh.tag_resource);
8515                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
8516                            tmp_idx);
8517         }
8518 }
8519
8520 /**
8521  * Query a dv flow  rule for its statistics via devx.
8522  *
8523  * @param[in] dev
8524  *   Pointer to Ethernet device.
8525  * @param[in] flow
8526  *   Pointer to the sub flow.
8527  * @param[out] data
8528  *   data retrieved by the query.
8529  * @param[out] error
8530  *   Perform verbose error reporting if not NULL.
8531  *
8532  * @return
8533  *   0 on success, a negative errno value otherwise and rte_errno is set.
8534  */
8535 static int
8536 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
8537                     void *data, struct rte_flow_error *error)
8538 {
8539         struct mlx5_priv *priv = dev->data->dev_private;
8540         struct rte_flow_query_count *qc = data;
8541
8542         if (!priv->config.devx)
8543                 return rte_flow_error_set(error, ENOTSUP,
8544                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8545                                           NULL,
8546                                           "counters are not supported");
8547         if (flow->counter) {
8548                 uint64_t pkts, bytes;
8549                 struct mlx5_flow_counter *cnt;
8550
8551                 cnt = flow_dv_counter_get_by_idx(dev, flow->counter,
8552                                                  NULL);
8553                 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
8554                                                &bytes);
8555
8556                 if (err)
8557                         return rte_flow_error_set(error, -err,
8558                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8559                                         NULL, "cannot read counters");
8560                 qc->hits_set = 1;
8561                 qc->bytes_set = 1;
8562                 qc->hits = pkts - cnt->hits;
8563                 qc->bytes = bytes - cnt->bytes;
8564                 if (qc->reset) {
8565                         cnt->hits = pkts;
8566                         cnt->bytes = bytes;
8567                 }
8568                 return 0;
8569         }
8570         return rte_flow_error_set(error, EINVAL,
8571                                   RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8572                                   NULL,
8573                                   "counters are not available");
8574 }
8575
8576 /**
8577  * Query a flow.
8578  *
8579  * @see rte_flow_query()
8580  * @see rte_flow_ops
8581  */
8582 static int
8583 flow_dv_query(struct rte_eth_dev *dev,
8584               struct rte_flow *flow __rte_unused,
8585               const struct rte_flow_action *actions __rte_unused,
8586               void *data __rte_unused,
8587               struct rte_flow_error *error __rte_unused)
8588 {
8589         int ret = -EINVAL;
8590
8591         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
8592                 switch (actions->type) {
8593                 case RTE_FLOW_ACTION_TYPE_VOID:
8594                         break;
8595                 case RTE_FLOW_ACTION_TYPE_COUNT:
8596                         ret = flow_dv_query_count(dev, flow, data, error);
8597                         break;
8598                 default:
8599                         return rte_flow_error_set(error, ENOTSUP,
8600                                                   RTE_FLOW_ERROR_TYPE_ACTION,
8601                                                   actions,
8602                                                   "action not supported");
8603                 }
8604         }
8605         return ret;
8606 }
8607
8608 /**
8609  * Destroy the meter table set.
8610  * Lock free, (mutex should be acquired by caller).
8611  *
8612  * @param[in] dev
8613  *   Pointer to Ethernet device.
8614  * @param[in] tbl
8615  *   Pointer to the meter table set.
8616  *
8617  * @return
8618  *   Always 0.
8619  */
8620 static int
8621 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
8622                         struct mlx5_meter_domains_infos *tbl)
8623 {
8624         struct mlx5_priv *priv = dev->data->dev_private;
8625         struct mlx5_meter_domains_infos *mtd =
8626                                 (struct mlx5_meter_domains_infos *)tbl;
8627
8628         if (!mtd || !priv->config.dv_flow_en)
8629                 return 0;
8630         if (mtd->ingress.policer_rules[RTE_MTR_DROPPED])
8631                 claim_zero(mlx5_glue->dv_destroy_flow
8632                           (mtd->ingress.policer_rules[RTE_MTR_DROPPED]));
8633         if (mtd->egress.policer_rules[RTE_MTR_DROPPED])
8634                 claim_zero(mlx5_glue->dv_destroy_flow
8635                           (mtd->egress.policer_rules[RTE_MTR_DROPPED]));
8636         if (mtd->transfer.policer_rules[RTE_MTR_DROPPED])
8637                 claim_zero(mlx5_glue->dv_destroy_flow
8638                           (mtd->transfer.policer_rules[RTE_MTR_DROPPED]));
8639         if (mtd->egress.color_matcher)
8640                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8641                           (mtd->egress.color_matcher));
8642         if (mtd->egress.any_matcher)
8643                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8644                           (mtd->egress.any_matcher));
8645         if (mtd->egress.tbl)
8646                 claim_zero(flow_dv_tbl_resource_release(dev,
8647                                                         mtd->egress.tbl));
8648         if (mtd->egress.sfx_tbl)
8649                 claim_zero(flow_dv_tbl_resource_release(dev,
8650                                                         mtd->egress.sfx_tbl));
8651         if (mtd->ingress.color_matcher)
8652                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8653                           (mtd->ingress.color_matcher));
8654         if (mtd->ingress.any_matcher)
8655                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8656                           (mtd->ingress.any_matcher));
8657         if (mtd->ingress.tbl)
8658                 claim_zero(flow_dv_tbl_resource_release(dev,
8659                                                         mtd->ingress.tbl));
8660         if (mtd->ingress.sfx_tbl)
8661                 claim_zero(flow_dv_tbl_resource_release(dev,
8662                                                         mtd->ingress.sfx_tbl));
8663         if (mtd->transfer.color_matcher)
8664                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8665                           (mtd->transfer.color_matcher));
8666         if (mtd->transfer.any_matcher)
8667                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8668                           (mtd->transfer.any_matcher));
8669         if (mtd->transfer.tbl)
8670                 claim_zero(flow_dv_tbl_resource_release(dev,
8671                                                         mtd->transfer.tbl));
8672         if (mtd->transfer.sfx_tbl)
8673                 claim_zero(flow_dv_tbl_resource_release(dev,
8674                                                         mtd->transfer.sfx_tbl));
8675         if (mtd->drop_actn)
8676                 claim_zero(mlx5_glue->destroy_flow_action(mtd->drop_actn));
8677         rte_free(mtd);
8678         return 0;
8679 }
8680
8681 /* Number of meter flow actions, count and jump or count and drop. */
8682 #define METER_ACTIONS 2
8683
8684 /**
8685  * Create specify domain meter table and suffix table.
8686  *
8687  * @param[in] dev
8688  *   Pointer to Ethernet device.
8689  * @param[in,out] mtb
8690  *   Pointer to DV meter table set.
8691  * @param[in] egress
8692  *   Table attribute.
8693  * @param[in] transfer
8694  *   Table attribute.
8695  * @param[in] color_reg_c_idx
8696  *   Reg C index for color match.
8697  *
8698  * @return
8699  *   0 on success, -1 otherwise and rte_errno is set.
8700  */
8701 static int
8702 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
8703                            struct mlx5_meter_domains_infos *mtb,
8704                            uint8_t egress, uint8_t transfer,
8705                            uint32_t color_reg_c_idx)
8706 {
8707         struct mlx5_priv *priv = dev->data->dev_private;
8708         struct mlx5_ibv_shared *sh = priv->sh;
8709         struct mlx5_flow_dv_match_params mask = {
8710                 .size = sizeof(mask.buf),
8711         };
8712         struct mlx5_flow_dv_match_params value = {
8713                 .size = sizeof(value.buf),
8714         };
8715         struct mlx5dv_flow_matcher_attr dv_attr = {
8716                 .type = IBV_FLOW_ATTR_NORMAL,
8717                 .priority = 0,
8718                 .match_criteria_enable = 0,
8719                 .match_mask = (void *)&mask,
8720         };
8721         void *actions[METER_ACTIONS];
8722         struct mlx5_meter_domain_info *dtb;
8723         struct rte_flow_error error;
8724         int i = 0;
8725
8726         if (transfer)
8727                 dtb = &mtb->transfer;
8728         else if (egress)
8729                 dtb = &mtb->egress;
8730         else
8731                 dtb = &mtb->ingress;
8732         /* Create the meter table with METER level. */
8733         dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
8734                                             egress, transfer, &error);
8735         if (!dtb->tbl) {
8736                 DRV_LOG(ERR, "Failed to create meter policer table.");
8737                 return -1;
8738         }
8739         /* Create the meter suffix table with SUFFIX level. */
8740         dtb->sfx_tbl = flow_dv_tbl_resource_get(dev,
8741                                             MLX5_FLOW_TABLE_LEVEL_SUFFIX,
8742                                             egress, transfer, &error);
8743         if (!dtb->sfx_tbl) {
8744                 DRV_LOG(ERR, "Failed to create meter suffix table.");
8745                 return -1;
8746         }
8747         /* Create matchers, Any and Color. */
8748         dv_attr.priority = 3;
8749         dv_attr.match_criteria_enable = 0;
8750         dtb->any_matcher = mlx5_glue->dv_create_flow_matcher(sh->ctx,
8751                                                              &dv_attr,
8752                                                              dtb->tbl->obj);
8753         if (!dtb->any_matcher) {
8754                 DRV_LOG(ERR, "Failed to create meter"
8755                              " policer default matcher.");
8756                 goto error_exit;
8757         }
8758         dv_attr.priority = 0;
8759         dv_attr.match_criteria_enable =
8760                                 1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
8761         flow_dv_match_meta_reg(mask.buf, value.buf, color_reg_c_idx,
8762                                rte_col_2_mlx5_col(RTE_COLORS), UINT8_MAX);
8763         dtb->color_matcher = mlx5_glue->dv_create_flow_matcher(sh->ctx,
8764                                                                &dv_attr,
8765                                                                dtb->tbl->obj);
8766         if (!dtb->color_matcher) {
8767                 DRV_LOG(ERR, "Failed to create meter policer color matcher.");
8768                 goto error_exit;
8769         }
8770         if (mtb->count_actns[RTE_MTR_DROPPED])
8771                 actions[i++] = mtb->count_actns[RTE_MTR_DROPPED];
8772         actions[i++] = mtb->drop_actn;
8773         /* Default rule: lowest priority, match any, actions: drop. */
8774         dtb->policer_rules[RTE_MTR_DROPPED] =
8775                         mlx5_glue->dv_create_flow(dtb->any_matcher,
8776                                                  (void *)&value, i, actions);
8777         if (!dtb->policer_rules[RTE_MTR_DROPPED]) {
8778                 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
8779                 goto error_exit;
8780         }
8781         return 0;
8782 error_exit:
8783         return -1;
8784 }
8785
8786 /**
8787  * Create the needed meter and suffix tables.
8788  * Lock free, (mutex should be acquired by caller).
8789  *
8790  * @param[in] dev
8791  *   Pointer to Ethernet device.
8792  * @param[in] fm
8793  *   Pointer to the flow meter.
8794  *
8795  * @return
8796  *   Pointer to table set on success, NULL otherwise and rte_errno is set.
8797  */
8798 static struct mlx5_meter_domains_infos *
8799 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev,
8800                        const struct mlx5_flow_meter *fm)
8801 {
8802         struct mlx5_priv *priv = dev->data->dev_private;
8803         struct mlx5_meter_domains_infos *mtb;
8804         int ret;
8805         int i;
8806
8807         if (!priv->mtr_en) {
8808                 rte_errno = ENOTSUP;
8809                 return NULL;
8810         }
8811         mtb = rte_calloc(__func__, 1, sizeof(*mtb), 0);
8812         if (!mtb) {
8813                 DRV_LOG(ERR, "Failed to allocate memory for meter.");
8814                 return NULL;
8815         }
8816         /* Create meter count actions */
8817         for (i = 0; i <= RTE_MTR_DROPPED; i++) {
8818                 struct mlx5_flow_counter *cnt;
8819                 if (!fm->policer_stats.cnt[i])
8820                         continue;
8821                 cnt = flow_dv_counter_get_by_idx(dev,
8822                       fm->policer_stats.cnt[i], NULL);
8823                 mtb->count_actns[i] = cnt->action;
8824         }
8825         /* Create drop action. */
8826         mtb->drop_actn = mlx5_glue->dr_create_flow_action_drop();
8827         if (!mtb->drop_actn) {
8828                 DRV_LOG(ERR, "Failed to create drop action.");
8829                 goto error_exit;
8830         }
8831         /* Egress meter table. */
8832         ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0, priv->mtr_color_reg);
8833         if (ret) {
8834                 DRV_LOG(ERR, "Failed to prepare egress meter table.");
8835                 goto error_exit;
8836         }
8837         /* Ingress meter table. */
8838         ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0, priv->mtr_color_reg);
8839         if (ret) {
8840                 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
8841                 goto error_exit;
8842         }
8843         /* FDB meter table. */
8844         if (priv->config.dv_esw_en) {
8845                 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1,
8846                                                  priv->mtr_color_reg);
8847                 if (ret) {
8848                         DRV_LOG(ERR, "Failed to prepare fdb meter table.");
8849                         goto error_exit;
8850                 }
8851         }
8852         return mtb;
8853 error_exit:
8854         flow_dv_destroy_mtr_tbl(dev, mtb);
8855         return NULL;
8856 }
8857
8858 /**
8859  * Destroy domain policer rule.
8860  *
8861  * @param[in] dt
8862  *   Pointer to domain table.
8863  */
8864 static void
8865 flow_dv_destroy_domain_policer_rule(struct mlx5_meter_domain_info *dt)
8866 {
8867         int i;
8868
8869         for (i = 0; i < RTE_MTR_DROPPED; i++) {
8870                 if (dt->policer_rules[i]) {
8871                         claim_zero(mlx5_glue->dv_destroy_flow
8872                                   (dt->policer_rules[i]));
8873                         dt->policer_rules[i] = NULL;
8874                 }
8875         }
8876         if (dt->jump_actn) {
8877                 claim_zero(mlx5_glue->destroy_flow_action(dt->jump_actn));
8878                 dt->jump_actn = NULL;
8879         }
8880 }
8881
8882 /**
8883  * Destroy policer rules.
8884  *
8885  * @param[in] dev
8886  *   Pointer to Ethernet device.
8887  * @param[in] fm
8888  *   Pointer to flow meter structure.
8889  * @param[in] attr
8890  *   Pointer to flow attributes.
8891  *
8892  * @return
8893  *   Always 0.
8894  */
8895 static int
8896 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev __rte_unused,
8897                               const struct mlx5_flow_meter *fm,
8898                               const struct rte_flow_attr *attr)
8899 {
8900         struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
8901
8902         if (!mtb)
8903                 return 0;
8904         if (attr->egress)
8905                 flow_dv_destroy_domain_policer_rule(&mtb->egress);
8906         if (attr->ingress)
8907                 flow_dv_destroy_domain_policer_rule(&mtb->ingress);
8908         if (attr->transfer)
8909                 flow_dv_destroy_domain_policer_rule(&mtb->transfer);
8910         return 0;
8911 }
8912
8913 /**
8914  * Create specify domain meter policer rule.
8915  *
8916  * @param[in] fm
8917  *   Pointer to flow meter structure.
8918  * @param[in] mtb
8919  *   Pointer to DV meter table set.
8920  * @param[in] mtr_reg_c
8921  *   Color match REG_C.
8922  *
8923  * @return
8924  *   0 on success, -1 otherwise.
8925  */
8926 static int
8927 flow_dv_create_policer_forward_rule(struct mlx5_flow_meter *fm,
8928                                     struct mlx5_meter_domain_info *dtb,
8929                                     uint8_t mtr_reg_c)
8930 {
8931         struct mlx5_flow_dv_match_params matcher = {
8932                 .size = sizeof(matcher.buf),
8933         };
8934         struct mlx5_flow_dv_match_params value = {
8935                 .size = sizeof(value.buf),
8936         };
8937         struct mlx5_meter_domains_infos *mtb = fm->mfts;
8938         void *actions[METER_ACTIONS];
8939         int i;
8940
8941         /* Create jump action. */
8942         if (!dtb->jump_actn)
8943                 dtb->jump_actn =
8944                         mlx5_glue->dr_create_flow_action_dest_flow_tbl
8945                                                         (dtb->sfx_tbl->obj);
8946         if (!dtb->jump_actn) {
8947                 DRV_LOG(ERR, "Failed to create policer jump action.");
8948                 goto error;
8949         }
8950         for (i = 0; i < RTE_MTR_DROPPED; i++) {
8951                 int j = 0;
8952
8953                 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_reg_c,
8954                                        rte_col_2_mlx5_col(i), UINT8_MAX);
8955                 if (mtb->count_actns[i])
8956                         actions[j++] = mtb->count_actns[i];
8957                 if (fm->params.action[i] == MTR_POLICER_ACTION_DROP)
8958                         actions[j++] = mtb->drop_actn;
8959                 else
8960                         actions[j++] = dtb->jump_actn;
8961                 dtb->policer_rules[i] =
8962                         mlx5_glue->dv_create_flow(dtb->color_matcher,
8963                                                  (void *)&value,
8964                                                   j, actions);
8965                 if (!dtb->policer_rules[i]) {
8966                         DRV_LOG(ERR, "Failed to create policer rule.");
8967                         goto error;
8968                 }
8969         }
8970         return 0;
8971 error:
8972         rte_errno = errno;
8973         return -1;
8974 }
8975
8976 /**
8977  * Create policer rules.
8978  *
8979  * @param[in] dev
8980  *   Pointer to Ethernet device.
8981  * @param[in] fm
8982  *   Pointer to flow meter structure.
8983  * @param[in] attr
8984  *   Pointer to flow attributes.
8985  *
8986  * @return
8987  *   0 on success, -1 otherwise.
8988  */
8989 static int
8990 flow_dv_create_policer_rules(struct rte_eth_dev *dev,
8991                              struct mlx5_flow_meter *fm,
8992                              const struct rte_flow_attr *attr)
8993 {
8994         struct mlx5_priv *priv = dev->data->dev_private;
8995         struct mlx5_meter_domains_infos *mtb = fm->mfts;
8996         int ret;
8997
8998         if (attr->egress) {
8999                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->egress,
9000                                                 priv->mtr_color_reg);
9001                 if (ret) {
9002                         DRV_LOG(ERR, "Failed to create egress policer.");
9003                         goto error;
9004                 }
9005         }
9006         if (attr->ingress) {
9007                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->ingress,
9008                                                 priv->mtr_color_reg);
9009                 if (ret) {
9010                         DRV_LOG(ERR, "Failed to create ingress policer.");
9011                         goto error;
9012                 }
9013         }
9014         if (attr->transfer) {
9015                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->transfer,
9016                                                 priv->mtr_color_reg);
9017                 if (ret) {
9018                         DRV_LOG(ERR, "Failed to create transfer policer.");
9019                         goto error;
9020                 }
9021         }
9022         return 0;
9023 error:
9024         flow_dv_destroy_policer_rules(dev, fm, attr);
9025         return -1;
9026 }
9027
9028 /**
9029  * Query a devx counter.
9030  *
9031  * @param[in] dev
9032  *   Pointer to the Ethernet device structure.
9033  * @param[in] cnt
9034  *   Index to the flow counter.
9035  * @param[in] clear
9036  *   Set to clear the counter statistics.
9037  * @param[out] pkts
9038  *   The statistics value of packets.
9039  * @param[out] bytes
9040  *   The statistics value of bytes.
9041  *
9042  * @return
9043  *   0 on success, otherwise return -1.
9044  */
9045 static int
9046 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
9047                       uint64_t *pkts, uint64_t *bytes)
9048 {
9049         struct mlx5_priv *priv = dev->data->dev_private;
9050         struct mlx5_flow_counter *cnt;
9051         uint64_t inn_pkts, inn_bytes;
9052         int ret;
9053
9054         if (!priv->config.devx)
9055                 return -1;
9056
9057         ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
9058         if (ret)
9059                 return -1;
9060         cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
9061         *pkts = inn_pkts - cnt->hits;
9062         *bytes = inn_bytes - cnt->bytes;
9063         if (clear) {
9064                 cnt->hits = inn_pkts;
9065                 cnt->bytes = inn_bytes;
9066         }
9067         return 0;
9068 }
9069
9070 /*
9071  * Mutex-protected thunk to lock-free  __flow_dv_translate().
9072  */
9073 static int
9074 flow_dv_translate(struct rte_eth_dev *dev,
9075                   struct mlx5_flow *dev_flow,
9076                   const struct rte_flow_attr *attr,
9077                   const struct rte_flow_item items[],
9078                   const struct rte_flow_action actions[],
9079                   struct rte_flow_error *error)
9080 {
9081         int ret;
9082
9083         flow_dv_shared_lock(dev);
9084         ret = __flow_dv_translate(dev, dev_flow, attr, items, actions, error);
9085         flow_dv_shared_unlock(dev);
9086         return ret;
9087 }
9088
9089 /*
9090  * Mutex-protected thunk to lock-free  __flow_dv_apply().
9091  */
9092 static int
9093 flow_dv_apply(struct rte_eth_dev *dev,
9094               struct rte_flow *flow,
9095               struct rte_flow_error *error)
9096 {
9097         int ret;
9098
9099         flow_dv_shared_lock(dev);
9100         ret = __flow_dv_apply(dev, flow, error);
9101         flow_dv_shared_unlock(dev);
9102         return ret;
9103 }
9104
9105 /*
9106  * Mutex-protected thunk to lock-free __flow_dv_remove().
9107  */
9108 static void
9109 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
9110 {
9111         flow_dv_shared_lock(dev);
9112         __flow_dv_remove(dev, flow);
9113         flow_dv_shared_unlock(dev);
9114 }
9115
9116 /*
9117  * Mutex-protected thunk to lock-free __flow_dv_destroy().
9118  */
9119 static void
9120 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
9121 {
9122         flow_dv_shared_lock(dev);
9123         __flow_dv_destroy(dev, flow);
9124         flow_dv_shared_unlock(dev);
9125 }
9126
9127 /*
9128  * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
9129  */
9130 static uint32_t
9131 flow_dv_counter_allocate(struct rte_eth_dev *dev)
9132 {
9133         uint32_t cnt;
9134
9135         flow_dv_shared_lock(dev);
9136         cnt = flow_dv_counter_alloc(dev, 0, 0, 1);
9137         flow_dv_shared_unlock(dev);
9138         return cnt;
9139 }
9140
9141 /*
9142  * Mutex-protected thunk to lock-free flow_dv_counter_release().
9143  */
9144 static void
9145 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t cnt)
9146 {
9147         flow_dv_shared_lock(dev);
9148         flow_dv_counter_release(dev, cnt);
9149         flow_dv_shared_unlock(dev);
9150 }
9151
9152 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
9153         .validate = flow_dv_validate,
9154         .prepare = flow_dv_prepare,
9155         .translate = flow_dv_translate,
9156         .apply = flow_dv_apply,
9157         .remove = flow_dv_remove,
9158         .destroy = flow_dv_destroy,
9159         .query = flow_dv_query,
9160         .create_mtr_tbls = flow_dv_create_mtr_tbl,
9161         .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
9162         .create_policer_rules = flow_dv_create_policer_rules,
9163         .destroy_policer_rules = flow_dv_destroy_policer_rules,
9164         .counter_alloc = flow_dv_counter_allocate,
9165         .counter_free = flow_dv_counter_free,
9166         .counter_query = flow_dv_counter_query,
9167 };
9168
9169 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */