drivers/net/mlx5/mlx5_flow_dv.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2018 Mellanox Technologies, Ltd
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdalign.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10
  11 #include <rte_common.h>
  12 #include <rte_ether.h>
  13 #include <ethdev_driver.h>
  14 #include <rte_flow.h>
  15 #include <rte_flow_driver.h>
  16 #include <rte_malloc.h>
  17 #include <rte_cycles.h>
  18 #include <rte_ip.h>
  19 #include <rte_gre.h>
  20 #include <rte_vxlan.h>
  21 #include <rte_gtp.h>
  22 #include <rte_eal_paging.h>
  23 #include <rte_mpls.h>
  24
  25 #include <mlx5_glue.h>
  26 #include <mlx5_devx_cmds.h>
  27 #include <mlx5_prm.h>
  28 #include <mlx5_malloc.h>
  29
  30 #include "mlx5_defs.h"
  31 #include "mlx5.h"
  32 #include "mlx5_common_os.h"
  33 #include "mlx5_flow.h"
  34 #include "mlx5_flow_os.h"
  35 #include "mlx5_rxtx.h"
  36 #include "rte_pmd_mlx5.h"
  37
  38 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
  39
  40 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
  41 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
  42 #endif
  43
  44 #ifndef HAVE_MLX5DV_DR_ESWITCH
  45 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
  46 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
  47 #endif
  48 #endif
  49
  50 #ifndef HAVE_MLX5DV_DR
  51 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
  52 #endif
  53
  54 /* VLAN header definitions */
  55 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
  56 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
  57 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
  58 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
  59 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
  60
  61 union flow_dv_attr {
  62         struct {
  63                 uint32_t valid:1;
  64                 uint32_t ipv4:1;
  65                 uint32_t ipv6:1;
  66                 uint32_t tcp:1;
  67                 uint32_t udp:1;
  68                 uint32_t reserved:27;
  69         };
  70         uint32_t attr;
  71 };
  72
  73 static int
  74 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
  75                              struct mlx5_flow_tbl_resource *tbl);
  76
  77 static int
  78 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
  79                                      uint32_t encap_decap_idx);
  80
  81 static int
  82 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
  83                                         uint32_t port_id);
  84 static void
  85 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss);
  86
  87 static int
  88 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
  89                                   uint32_t rix_jump);
  90
  91 /**
  92  * Initialize flow attributes structure according to flow items' types.
  93  *
  94  * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
  95  * mode. For tunnel mode, the items to be modified are the outermost ones.
  96  *
  97  * @param[in] item
  98  *   Pointer to item specification.
  99  * @param[out] attr
 100  *   Pointer to flow attributes structure.
 101  * @param[in] dev_flow
 102  *   Pointer to the sub flow.
 103  * @param[in] tunnel_decap
 104  *   Whether action is after tunnel decapsulation.
 105  */
 106 static void
 107 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
 108                   struct mlx5_flow *dev_flow, bool tunnel_decap)
 109 {
 110         uint64_t layers = dev_flow->handle->layers;
 111
 112         /*
 113          * If layers is already initialized, it means this dev_flow is the
 114          * suffix flow, the layers flags is set by the prefix flow. Need to
 115          * use the layer flags from prefix flow as the suffix flow may not
 116          * have the user defined items as the flow is split.
 117          */
 118         if (layers) {
 119                 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
 120                         attr->ipv4 = 1;
 121                 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
 122                         attr->ipv6 = 1;
 123                 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
 124                         attr->tcp = 1;
 125                 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
 126                         attr->udp = 1;
 127                 attr->valid = 1;
 128                 return;
 129         }
 130         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
 131                 uint8_t next_protocol = 0xff;
 132                 switch (item->type) {
 133                 case RTE_FLOW_ITEM_TYPE_GRE:
 134                 case RTE_FLOW_ITEM_TYPE_NVGRE:
 135                 case RTE_FLOW_ITEM_TYPE_VXLAN:
 136                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
 137                 case RTE_FLOW_ITEM_TYPE_GENEVE:
 138                 case RTE_FLOW_ITEM_TYPE_MPLS:
 139                         if (tunnel_decap)
 140                                 attr->attr = 0;
 141                         break;
 142                 case RTE_FLOW_ITEM_TYPE_IPV4:
 143                         if (!attr->ipv6)
 144                                 attr->ipv4 = 1;
 145                         if (item->mask != NULL &&
 146                             ((const struct rte_flow_item_ipv4 *)
 147                             item->mask)->hdr.next_proto_id)
 148                                 next_protocol =
 149                                     ((const struct rte_flow_item_ipv4 *)
 150                                       (item->spec))->hdr.next_proto_id &
 151                                     ((const struct rte_flow_item_ipv4 *)
 152                                       (item->mask))->hdr.next_proto_id;
 153                         if ((next_protocol == IPPROTO_IPIP ||
 154                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 155                                 attr->attr = 0;
 156                         break;
 157                 case RTE_FLOW_ITEM_TYPE_IPV6:
 158                         if (!attr->ipv4)
 159                                 attr->ipv6 = 1;
 160                         if (item->mask != NULL &&
 161                             ((const struct rte_flow_item_ipv6 *)
 162                             item->mask)->hdr.proto)
 163                                 next_protocol =
 164                                     ((const struct rte_flow_item_ipv6 *)
 165                                       (item->spec))->hdr.proto &
 166                                     ((const struct rte_flow_item_ipv6 *)
 167                                       (item->mask))->hdr.proto;
 168                         if ((next_protocol == IPPROTO_IPIP ||
 169                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 170                                 attr->attr = 0;
 171                         break;
 172                 case RTE_FLOW_ITEM_TYPE_UDP:
 173                         if (!attr->tcp)
 174                                 attr->udp = 1;
 175                         break;
 176                 case RTE_FLOW_ITEM_TYPE_TCP:
 177                         if (!attr->udp)
 178                                 attr->tcp = 1;
 179                         break;
 180                 default:
 181                         break;
 182                 }
 183         }
 184         attr->valid = 1;
 185 }
 186
 187 /**
 188  * Convert rte_mtr_color to mlx5 color.
 189  *
 190  * @param[in] rcol
 191  *   rte_mtr_color.
 192  *
 193  * @return
 194  *   mlx5 color.
 195  */
 196 static int
 197 rte_col_2_mlx5_col(enum rte_color rcol)
 198 {
 199         switch (rcol) {
 200         case RTE_COLOR_GREEN:
 201                 return MLX5_FLOW_COLOR_GREEN;
 202         case RTE_COLOR_YELLOW:
 203                 return MLX5_FLOW_COLOR_YELLOW;
 204         case RTE_COLOR_RED:
 205                 return MLX5_FLOW_COLOR_RED;
 206         default:
 207                 break;
 208         }
 209         return MLX5_FLOW_COLOR_UNDEFINED;
 210 }
 211
 212 struct field_modify_info {
 213         uint32_t size; /* Size of field in protocol header, in bytes. */
 214         uint32_t offset; /* Offset of field in protocol header, in bytes. */
 215         enum mlx5_modification_field id;
 216 };
 217
 218 struct field_modify_info modify_eth[] = {
 219         {4,  0, MLX5_MODI_OUT_DMAC_47_16},
 220         {2,  4, MLX5_MODI_OUT_DMAC_15_0},
 221         {4,  6, MLX5_MODI_OUT_SMAC_47_16},
 222         {2, 10, MLX5_MODI_OUT_SMAC_15_0},
 223         {0, 0, 0},
 224 };
 225
 226 struct field_modify_info modify_vlan_out_first_vid[] = {
 227         /* Size in bits !!! */
 228         {12, 0, MLX5_MODI_OUT_FIRST_VID},
 229         {0, 0, 0},
 230 };
 231
 232 struct field_modify_info modify_ipv4[] = {
 233         {1,  1, MLX5_MODI_OUT_IP_DSCP},
 234         {1,  8, MLX5_MODI_OUT_IPV4_TTL},
 235         {4, 12, MLX5_MODI_OUT_SIPV4},
 236         {4, 16, MLX5_MODI_OUT_DIPV4},
 237         {0, 0, 0},
 238 };
 239
 240 struct field_modify_info modify_ipv6[] = {
 241         {1,  0, MLX5_MODI_OUT_IP_DSCP},
 242         {1,  7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
 243         {4,  8, MLX5_MODI_OUT_SIPV6_127_96},
 244         {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
 245         {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
 246         {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
 247         {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
 248         {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
 249         {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
 250         {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
 251         {0, 0, 0},
 252 };
 253
 254 struct field_modify_info modify_udp[] = {
 255         {2, 0, MLX5_MODI_OUT_UDP_SPORT},
 256         {2, 2, MLX5_MODI_OUT_UDP_DPORT},
 257         {0, 0, 0},
 258 };
 259
 260 struct field_modify_info modify_tcp[] = {
 261         {2, 0, MLX5_MODI_OUT_TCP_SPORT},
 262         {2, 2, MLX5_MODI_OUT_TCP_DPORT},
 263         {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
 264         {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
 265         {0, 0, 0},
 266 };
 267
 268 static void
 269 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
 270                           uint8_t next_protocol, uint64_t *item_flags,
 271                           int *tunnel)
 272 {
 273         MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
 274                     item->type == RTE_FLOW_ITEM_TYPE_IPV6);
 275         if (next_protocol == IPPROTO_IPIP) {
 276                 *item_flags |= MLX5_FLOW_LAYER_IPIP;
 277                 *tunnel = 1;
 278         }
 279         if (next_protocol == IPPROTO_IPV6) {
 280                 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
 281                 *tunnel = 1;
 282         }
 283 }
 284
 285 /* Update VLAN's VID/PCP based on input rte_flow_action.
 286  *
 287  * @param[in] action
 288  *   Pointer to struct rte_flow_action.
 289  * @param[out] vlan
 290  *   Pointer to struct rte_vlan_hdr.
 291  */
 292 static void
 293 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
 294                          struct rte_vlan_hdr *vlan)
 295 {
 296         uint16_t vlan_tci;
 297         if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
 298                 vlan_tci =
 299                     ((const struct rte_flow_action_of_set_vlan_pcp *)
 300                                                action->conf)->vlan_pcp;
 301                 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
 302                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
 303                 vlan->vlan_tci |= vlan_tci;
 304         } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
 305                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
 306                 vlan->vlan_tci |= rte_be_to_cpu_16
 307                     (((const struct rte_flow_action_of_set_vlan_vid *)
 308                                              action->conf)->vlan_vid);
 309         }
 310 }
 311
 312 /**
 313  * Fetch 1, 2, 3 or 4 byte field from the byte array
 314  * and return as unsigned integer in host-endian format.
 315  *
 316  * @param[in] data
 317  *   Pointer to data array.
 318  * @param[in] size
 319  *   Size of field to extract.
 320  *
 321  * @return
 322  *   converted field in host endian format.
 323  */
 324 static inline uint32_t
 325 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
 326 {
 327         uint32_t ret;
 328
 329         switch (size) {
 330         case 1:
 331                 ret = *data;
 332                 break;
 333         case 2:
 334                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 335                 break;
 336         case 3:
 337                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 338                 ret = (ret << 8) | *(data + sizeof(uint16_t));
 339                 break;
 340         case 4:
 341                 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
 342                 break;
 343         default:
 344                 MLX5_ASSERT(false);
 345                 ret = 0;
 346                 break;
 347         }
 348         return ret;
 349 }
 350
 351 /**
 352  * Convert modify-header action to DV specification.
 353  *
 354  * Data length of each action is determined by provided field description
 355  * and the item mask. Data bit offset and width of each action is determined
 356  * by provided item mask.
 357  *
 358  * @param[in] item
 359  *   Pointer to item specification.
 360  * @param[in] field
 361  *   Pointer to field modification information.
 362  *     For MLX5_MODIFICATION_TYPE_SET specifies destination field.
 363  *     For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
 364  *     For MLX5_MODIFICATION_TYPE_COPY specifies source field.
 365  * @param[in] dcopy
 366  *   Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
 367  *   Negative offset value sets the same offset as source offset.
 368  *   size field is ignored, value is taken from source field.
 369  * @param[in,out] resource
 370  *   Pointer to the modify-header resource.
 371  * @param[in] type
 372  *   Type of modification.
 373  * @param[out] error
 374  *   Pointer to the error structure.
 375  *
 376  * @return
 377  *   0 on success, a negative errno value otherwise and rte_errno is set.
 378  */
 379 static int
 380 flow_dv_convert_modify_action(struct rte_flow_item *item,
 381                               struct field_modify_info *field,
 382                               struct field_modify_info *dcopy,
 383                               struct mlx5_flow_dv_modify_hdr_resource *resource,
 384                               uint32_t type, struct rte_flow_error *error)
 385 {
 386         uint32_t i = resource->actions_num;
 387         struct mlx5_modification_cmd *actions = resource->actions;
 388
 389         /*
 390          * The item and mask are provided in big-endian format.
 391          * The fields should be presented as in big-endian format either.
 392          * Mask must be always present, it defines the actual field width.
 393          */
 394         MLX5_ASSERT(item->mask);
 395         MLX5_ASSERT(field->size);
 396         do {
 397                 unsigned int size_b;
 398                 unsigned int off_b;
 399                 uint32_t mask;
 400                 uint32_t data;
 401
 402                 if (i >= MLX5_MAX_MODIFY_NUM)
 403                         return rte_flow_error_set(error, EINVAL,
 404                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 405                                  "too many items to modify");
 406                 /* Fetch variable byte size mask from the array. */
 407                 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
 408                                            field->offset, field->size);
 409                 if (!mask) {
 410                         ++field;
 411                         continue;
 412                 }
 413                 /* Deduce actual data width in bits from mask value. */
 414                 off_b = rte_bsf32(mask);
 415                 size_b = sizeof(uint32_t) * CHAR_BIT -
 416                          off_b - __builtin_clz(mask);
 417                 MLX5_ASSERT(size_b);
 418                 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
 419                 actions[i] = (struct mlx5_modification_cmd) {
 420                         .action_type = type,
 421                         .field = field->id,
 422                         .offset = off_b,
 423                         .length = size_b,
 424                 };
 425                 /* Convert entire record to expected big-endian format. */
 426                 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 427                 if (type == MLX5_MODIFICATION_TYPE_COPY) {
 428                         MLX5_ASSERT(dcopy);
 429                         actions[i].dst_field = dcopy->id;
 430                         actions[i].dst_offset =
 431                                 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
 432                         /* Convert entire record to big-endian format. */
 433                         actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
 434                         ++dcopy;
 435                 } else {
 436                         MLX5_ASSERT(item->spec);
 437                         data = flow_dv_fetch_field((const uint8_t *)item->spec +
 438                                                    field->offset, field->size);
 439                         /* Shift out the trailing masked bits from data. */
 440                         data = (data & mask) >> off_b;
 441                         actions[i].data1 = rte_cpu_to_be_32(data);
 442                 }
 443                 ++i;
 444                 ++field;
 445         } while (field->size);
 446         if (resource->actions_num == i)
 447                 return rte_flow_error_set(error, EINVAL,
 448                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 449                                           "invalid modification flow item");
 450         resource->actions_num = i;
 451         return 0;
 452 }
 453
 454 /**
 455  * Convert modify-header set IPv4 address action to DV specification.
 456  *
 457  * @param[in,out] resource
 458  *   Pointer to the modify-header resource.
 459  * @param[in] action
 460  *   Pointer to action specification.
 461  * @param[out] error
 462  *   Pointer to the error structure.
 463  *
 464  * @return
 465  *   0 on success, a negative errno value otherwise and rte_errno is set.
 466  */
 467 static int
 468 flow_dv_convert_action_modify_ipv4
 469                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 470                          const struct rte_flow_action *action,
 471                          struct rte_flow_error *error)
 472 {
 473         const struct rte_flow_action_set_ipv4 *conf =
 474                 (const struct rte_flow_action_set_ipv4 *)(action->conf);
 475         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
 476         struct rte_flow_item_ipv4 ipv4;
 477         struct rte_flow_item_ipv4 ipv4_mask;
 478
 479         memset(&ipv4, 0, sizeof(ipv4));
 480         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 481         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
 482                 ipv4.hdr.src_addr = conf->ipv4_addr;
 483                 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
 484         } else {
 485                 ipv4.hdr.dst_addr = conf->ipv4_addr;
 486                 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
 487         }
 488         item.spec = &ipv4;
 489         item.mask = &ipv4_mask;
 490         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
 491                                              MLX5_MODIFICATION_TYPE_SET, error);
 492 }
 493
 494 /**
 495  * Convert modify-header set IPv6 address action to DV specification.
 496  *
 497  * @param[in,out] resource
 498  *   Pointer to the modify-header resource.
 499  * @param[in] action
 500  *   Pointer to action specification.
 501  * @param[out] error
 502  *   Pointer to the error structure.
 503  *
 504  * @return
 505  *   0 on success, a negative errno value otherwise and rte_errno is set.
 506  */
 507 static int
 508 flow_dv_convert_action_modify_ipv6
 509                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 510                          const struct rte_flow_action *action,
 511                          struct rte_flow_error *error)
 512 {
 513         const struct rte_flow_action_set_ipv6 *conf =
 514                 (const struct rte_flow_action_set_ipv6 *)(action->conf);
 515         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
 516         struct rte_flow_item_ipv6 ipv6;
 517         struct rte_flow_item_ipv6 ipv6_mask;
 518
 519         memset(&ipv6, 0, sizeof(ipv6));
 520         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 521         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
 522                 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
 523                        sizeof(ipv6.hdr.src_addr));
 524                 memcpy(&ipv6_mask.hdr.src_addr,
 525                        &rte_flow_item_ipv6_mask.hdr.src_addr,
 526                        sizeof(ipv6.hdr.src_addr));
 527         } else {
 528                 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
 529                        sizeof(ipv6.hdr.dst_addr));
 530                 memcpy(&ipv6_mask.hdr.dst_addr,
 531                        &rte_flow_item_ipv6_mask.hdr.dst_addr,
 532                        sizeof(ipv6.hdr.dst_addr));
 533         }
 534         item.spec = &ipv6;
 535         item.mask = &ipv6_mask;
 536         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
 537                                              MLX5_MODIFICATION_TYPE_SET, error);
 538 }
 539
 540 /**
 541  * Convert modify-header set MAC address action to DV specification.
 542  *
 543  * @param[in,out] resource
 544  *   Pointer to the modify-header resource.
 545  * @param[in] action
 546  *   Pointer to action specification.
 547  * @param[out] error
 548  *   Pointer to the error structure.
 549  *
 550  * @return
 551  *   0 on success, a negative errno value otherwise and rte_errno is set.
 552  */
 553 static int
 554 flow_dv_convert_action_modify_mac
 555                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 556                          const struct rte_flow_action *action,
 557                          struct rte_flow_error *error)
 558 {
 559         const struct rte_flow_action_set_mac *conf =
 560                 (const struct rte_flow_action_set_mac *)(action->conf);
 561         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
 562         struct rte_flow_item_eth eth;
 563         struct rte_flow_item_eth eth_mask;
 564
 565         memset(&eth, 0, sizeof(eth));
 566         memset(&eth_mask, 0, sizeof(eth_mask));
 567         if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
 568                 memcpy(&eth.src.addr_bytes, &conf->mac_addr,
 569                        sizeof(eth.src.addr_bytes));
 570                 memcpy(&eth_mask.src.addr_bytes,
 571                        &rte_flow_item_eth_mask.src.addr_bytes,
 572                        sizeof(eth_mask.src.addr_bytes));
 573         } else {
 574                 memcpy(&eth.dst.addr_bytes, &conf->mac_addr,
 575                        sizeof(eth.dst.addr_bytes));
 576                 memcpy(&eth_mask.dst.addr_bytes,
 577                        &rte_flow_item_eth_mask.dst.addr_bytes,
 578                        sizeof(eth_mask.dst.addr_bytes));
 579         }
 580         item.spec = &eth;
 581         item.mask = &eth_mask;
 582         return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
 583                                              MLX5_MODIFICATION_TYPE_SET, error);
 584 }
 585
 586 /**
 587  * Convert modify-header set VLAN VID action to DV specification.
 588  *
 589  * @param[in,out] resource
 590  *   Pointer to the modify-header resource.
 591  * @param[in] action
 592  *   Pointer to action specification.
 593  * @param[out] error
 594  *   Pointer to the error structure.
 595  *
 596  * @return
 597  *   0 on success, a negative errno value otherwise and rte_errno is set.
 598  */
 599 static int
 600 flow_dv_convert_action_modify_vlan_vid
 601                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 602                          const struct rte_flow_action *action,
 603                          struct rte_flow_error *error)
 604 {
 605         const struct rte_flow_action_of_set_vlan_vid *conf =
 606                 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
 607         int i = resource->actions_num;
 608         struct mlx5_modification_cmd *actions = resource->actions;
 609         struct field_modify_info *field = modify_vlan_out_first_vid;
 610
 611         if (i >= MLX5_MAX_MODIFY_NUM)
 612                 return rte_flow_error_set(error, EINVAL,
 613                          RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 614                          "too many items to modify");
 615         actions[i] = (struct mlx5_modification_cmd) {
 616                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 617                 .field = field->id,
 618                 .length = field->size,
 619                 .offset = field->offset,
 620         };
 621         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 622         actions[i].data1 = conf->vlan_vid;
 623         actions[i].data1 = actions[i].data1 << 16;
 624         resource->actions_num = ++i;
 625         return 0;
 626 }
 627
 628 /**
 629  * Convert modify-header set TP action to DV specification.
 630  *
 631  * @param[in,out] resource
 632  *   Pointer to the modify-header resource.
 633  * @param[in] action
 634  *   Pointer to action specification.
 635  * @param[in] items
 636  *   Pointer to rte_flow_item objects list.
 637  * @param[in] attr
 638  *   Pointer to flow attributes structure.
 639  * @param[in] dev_flow
 640  *   Pointer to the sub flow.
 641  * @param[in] tunnel_decap
 642  *   Whether action is after tunnel decapsulation.
 643  * @param[out] error
 644  *   Pointer to the error structure.
 645  *
 646  * @return
 647  *   0 on success, a negative errno value otherwise and rte_errno is set.
 648  */
 649 static int
 650 flow_dv_convert_action_modify_tp
 651                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 652                          const struct rte_flow_action *action,
 653                          const struct rte_flow_item *items,
 654                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 655                          bool tunnel_decap, struct rte_flow_error *error)
 656 {
 657         const struct rte_flow_action_set_tp *conf =
 658                 (const struct rte_flow_action_set_tp *)(action->conf);
 659         struct rte_flow_item item;
 660         struct rte_flow_item_udp udp;
 661         struct rte_flow_item_udp udp_mask;
 662         struct rte_flow_item_tcp tcp;
 663         struct rte_flow_item_tcp tcp_mask;
 664         struct field_modify_info *field;
 665
 666         if (!attr->valid)
 667                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 668         if (attr->udp) {
 669                 memset(&udp, 0, sizeof(udp));
 670                 memset(&udp_mask, 0, sizeof(udp_mask));
 671                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 672                         udp.hdr.src_port = conf->port;
 673                         udp_mask.hdr.src_port =
 674                                         rte_flow_item_udp_mask.hdr.src_port;
 675                 } else {
 676                         udp.hdr.dst_port = conf->port;
 677                         udp_mask.hdr.dst_port =
 678                                         rte_flow_item_udp_mask.hdr.dst_port;
 679                 }
 680                 item.type = RTE_FLOW_ITEM_TYPE_UDP;
 681                 item.spec = &udp;
 682                 item.mask = &udp_mask;
 683                 field = modify_udp;
 684         } else {
 685                 MLX5_ASSERT(attr->tcp);
 686                 memset(&tcp, 0, sizeof(tcp));
 687                 memset(&tcp_mask, 0, sizeof(tcp_mask));
 688                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 689                         tcp.hdr.src_port = conf->port;
 690                         tcp_mask.hdr.src_port =
 691                                         rte_flow_item_tcp_mask.hdr.src_port;
 692                 } else {
 693                         tcp.hdr.dst_port = conf->port;
 694                         tcp_mask.hdr.dst_port =
 695                                         rte_flow_item_tcp_mask.hdr.dst_port;
 696                 }
 697                 item.type = RTE_FLOW_ITEM_TYPE_TCP;
 698                 item.spec = &tcp;
 699                 item.mask = &tcp_mask;
 700                 field = modify_tcp;
 701         }
 702         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 703                                              MLX5_MODIFICATION_TYPE_SET, error);
 704 }
 705
 706 /**
 707  * Convert modify-header set TTL action to DV specification.
 708  *
 709  * @param[in,out] resource
 710  *   Pointer to the modify-header resource.
 711  * @param[in] action
 712  *   Pointer to action specification.
 713  * @param[in] items
 714  *   Pointer to rte_flow_item objects list.
 715  * @param[in] attr
 716  *   Pointer to flow attributes structure.
 717  * @param[in] dev_flow
 718  *   Pointer to the sub flow.
 719  * @param[in] tunnel_decap
 720  *   Whether action is after tunnel decapsulation.
 721  * @param[out] error
 722  *   Pointer to the error structure.
 723  *
 724  * @return
 725  *   0 on success, a negative errno value otherwise and rte_errno is set.
 726  */
 727 static int
 728 flow_dv_convert_action_modify_ttl
 729                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 730                          const struct rte_flow_action *action,
 731                          const struct rte_flow_item *items,
 732                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 733                          bool tunnel_decap, struct rte_flow_error *error)
 734 {
 735         const struct rte_flow_action_set_ttl *conf =
 736                 (const struct rte_flow_action_set_ttl *)(action->conf);
 737         struct rte_flow_item item;
 738         struct rte_flow_item_ipv4 ipv4;
 739         struct rte_flow_item_ipv4 ipv4_mask;
 740         struct rte_flow_item_ipv6 ipv6;
 741         struct rte_flow_item_ipv6 ipv6_mask;
 742         struct field_modify_info *field;
 743
 744         if (!attr->valid)
 745                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 746         if (attr->ipv4) {
 747                 memset(&ipv4, 0, sizeof(ipv4));
 748                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 749                 ipv4.hdr.time_to_live = conf->ttl_value;
 750                 ipv4_mask.hdr.time_to_live = 0xFF;
 751                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 752                 item.spec = &ipv4;
 753                 item.mask = &ipv4_mask;
 754                 field = modify_ipv4;
 755         } else {
 756                 MLX5_ASSERT(attr->ipv6);
 757                 memset(&ipv6, 0, sizeof(ipv6));
 758                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 759                 ipv6.hdr.hop_limits = conf->ttl_value;
 760                 ipv6_mask.hdr.hop_limits = 0xFF;
 761                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 762                 item.spec = &ipv6;
 763                 item.mask = &ipv6_mask;
 764                 field = modify_ipv6;
 765         }
 766         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 767                                              MLX5_MODIFICATION_TYPE_SET, error);
 768 }
 769
 770 /**
 771  * Convert modify-header decrement TTL action to DV specification.
 772  *
 773  * @param[in,out] resource
 774  *   Pointer to the modify-header resource.
 775  * @param[in] action
 776  *   Pointer to action specification.
 777  * @param[in] items
 778  *   Pointer to rte_flow_item objects list.
 779  * @param[in] attr
 780  *   Pointer to flow attributes structure.
 781  * @param[in] dev_flow
 782  *   Pointer to the sub flow.
 783  * @param[in] tunnel_decap
 784  *   Whether action is after tunnel decapsulation.
 785  * @param[out] error
 786  *   Pointer to the error structure.
 787  *
 788  * @return
 789  *   0 on success, a negative errno value otherwise and rte_errno is set.
 790  */
 791 static int
 792 flow_dv_convert_action_modify_dec_ttl
 793                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 794                          const struct rte_flow_item *items,
 795                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 796                          bool tunnel_decap, struct rte_flow_error *error)
 797 {
 798         struct rte_flow_item item;
 799         struct rte_flow_item_ipv4 ipv4;
 800         struct rte_flow_item_ipv4 ipv4_mask;
 801         struct rte_flow_item_ipv6 ipv6;
 802         struct rte_flow_item_ipv6 ipv6_mask;
 803         struct field_modify_info *field;
 804
 805         if (!attr->valid)
 806                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 807         if (attr->ipv4) {
 808                 memset(&ipv4, 0, sizeof(ipv4));
 809                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 810                 ipv4.hdr.time_to_live = 0xFF;
 811                 ipv4_mask.hdr.time_to_live = 0xFF;
 812                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 813                 item.spec = &ipv4;
 814                 item.mask = &ipv4_mask;
 815                 field = modify_ipv4;
 816         } else {
 817                 MLX5_ASSERT(attr->ipv6);
 818                 memset(&ipv6, 0, sizeof(ipv6));
 819                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 820                 ipv6.hdr.hop_limits = 0xFF;
 821                 ipv6_mask.hdr.hop_limits = 0xFF;
 822                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 823                 item.spec = &ipv6;
 824                 item.mask = &ipv6_mask;
 825                 field = modify_ipv6;
 826         }
 827         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 828                                              MLX5_MODIFICATION_TYPE_ADD, error);
 829 }
 830
 831 /**
 832  * Convert modify-header increment/decrement TCP Sequence number
 833  * to DV specification.
 834  *
 835  * @param[in,out] resource
 836  *   Pointer to the modify-header resource.
 837  * @param[in] action
 838  *   Pointer to action specification.
 839  * @param[out] error
 840  *   Pointer to the error structure.
 841  *
 842  * @return
 843  *   0 on success, a negative errno value otherwise and rte_errno is set.
 844  */
 845 static int
 846 flow_dv_convert_action_modify_tcp_seq
 847                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 848                          const struct rte_flow_action *action,
 849                          struct rte_flow_error *error)
 850 {
 851         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 852         uint64_t value = rte_be_to_cpu_32(*conf);
 853         struct rte_flow_item item;
 854         struct rte_flow_item_tcp tcp;
 855         struct rte_flow_item_tcp tcp_mask;
 856
 857         memset(&tcp, 0, sizeof(tcp));
 858         memset(&tcp_mask, 0, sizeof(tcp_mask));
 859         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
 860                 /*
 861                  * The HW has no decrement operation, only increment operation.
 862                  * To simulate decrement X from Y using increment operation
 863                  * we need to add UINT32_MAX X times to Y.
 864                  * Each adding of UINT32_MAX decrements Y by 1.
 865                  */
 866                 value *= UINT32_MAX;
 867         tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
 868         tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
 869         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 870         item.spec = &tcp;
 871         item.mask = &tcp_mask;
 872         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 873                                              MLX5_MODIFICATION_TYPE_ADD, error);
 874 }
 875
 876 /**
 877  * Convert modify-header increment/decrement TCP Acknowledgment number
 878  * to DV specification.
 879  *
 880  * @param[in,out] resource
 881  *   Pointer to the modify-header resource.
 882  * @param[in] action
 883  *   Pointer to action specification.
 884  * @param[out] error
 885  *   Pointer to the error structure.
 886  *
 887  * @return
 888  *   0 on success, a negative errno value otherwise and rte_errno is set.
 889  */
 890 static int
 891 flow_dv_convert_action_modify_tcp_ack
 892                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 893                          const struct rte_flow_action *action,
 894                          struct rte_flow_error *error)
 895 {
 896         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 897         uint64_t value = rte_be_to_cpu_32(*conf);
 898         struct rte_flow_item item;
 899         struct rte_flow_item_tcp tcp;
 900         struct rte_flow_item_tcp tcp_mask;
 901
 902         memset(&tcp, 0, sizeof(tcp));
 903         memset(&tcp_mask, 0, sizeof(tcp_mask));
 904         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
 905                 /*
 906                  * The HW has no decrement operation, only increment operation.
 907                  * To simulate decrement X from Y using increment operation
 908                  * we need to add UINT32_MAX X times to Y.
 909                  * Each adding of UINT32_MAX decrements Y by 1.
 910                  */
 911                 value *= UINT32_MAX;
 912         tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
 913         tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
 914         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 915         item.spec = &tcp;
 916         item.mask = &tcp_mask;
 917         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 918                                              MLX5_MODIFICATION_TYPE_ADD, error);
 919 }
 920
 921 static enum mlx5_modification_field reg_to_field[] = {
 922         [REG_NON] = MLX5_MODI_OUT_NONE,
 923         [REG_A] = MLX5_MODI_META_DATA_REG_A,
 924         [REG_B] = MLX5_MODI_META_DATA_REG_B,
 925         [REG_C_0] = MLX5_MODI_META_REG_C_0,
 926         [REG_C_1] = MLX5_MODI_META_REG_C_1,
 927         [REG_C_2] = MLX5_MODI_META_REG_C_2,
 928         [REG_C_3] = MLX5_MODI_META_REG_C_3,
 929         [REG_C_4] = MLX5_MODI_META_REG_C_4,
 930         [REG_C_5] = MLX5_MODI_META_REG_C_5,
 931         [REG_C_6] = MLX5_MODI_META_REG_C_6,
 932         [REG_C_7] = MLX5_MODI_META_REG_C_7,
 933 };
 934
 935 /**
 936  * Convert register set to DV specification.
 937  *
 938  * @param[in,out] resource
 939  *   Pointer to the modify-header resource.
 940  * @param[in] action
 941  *   Pointer to action specification.
 942  * @param[out] error
 943  *   Pointer to the error structure.
 944  *
 945  * @return
 946  *   0 on success, a negative errno value otherwise and rte_errno is set.
 947  */
 948 static int
 949 flow_dv_convert_action_set_reg
 950                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 951                          const struct rte_flow_action *action,
 952                          struct rte_flow_error *error)
 953 {
 954         const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
 955         struct mlx5_modification_cmd *actions = resource->actions;
 956         uint32_t i = resource->actions_num;
 957
 958         if (i >= MLX5_MAX_MODIFY_NUM)
 959                 return rte_flow_error_set(error, EINVAL,
 960                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 961                                           "too many items to modify");
 962         MLX5_ASSERT(conf->id != REG_NON);
 963         MLX5_ASSERT(conf->id < (enum modify_reg)RTE_DIM(reg_to_field));
 964         actions[i] = (struct mlx5_modification_cmd) {
 965                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 966                 .field = reg_to_field[conf->id],
 967         };
 968         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 969         actions[i].data1 = rte_cpu_to_be_32(conf->data);
 970         ++i;
 971         resource->actions_num = i;
 972         return 0;
 973 }
 974
 975 /**
 976  * Convert SET_TAG action to DV specification.
 977  *
 978  * @param[in] dev
 979  *   Pointer to the rte_eth_dev structure.
 980  * @param[in,out] resource
 981  *   Pointer to the modify-header resource.
 982  * @param[in] conf
 983  *   Pointer to action specification.
 984  * @param[out] error
 985  *   Pointer to the error structure.
 986  *
 987  * @return
 988  *   0 on success, a negative errno value otherwise and rte_errno is set.
 989  */
 990 static int
 991 flow_dv_convert_action_set_tag
 992                         (struct rte_eth_dev *dev,
 993                          struct mlx5_flow_dv_modify_hdr_resource *resource,
 994                          const struct rte_flow_action_set_tag *conf,
 995                          struct rte_flow_error *error)
 996 {
 997         rte_be32_t data = rte_cpu_to_be_32(conf->data);
 998         rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
 999         struct rte_flow_item item = {
1000                 .spec = &data,
1001                 .mask = &mask,
1002         };
1003         struct field_modify_info reg_c_x[] = {
1004                 [1] = {0, 0, 0},
1005         };
1006         enum mlx5_modification_field reg_type;
1007         int ret;
1008
1009         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1010         if (ret < 0)
1011                 return ret;
1012         MLX5_ASSERT(ret != REG_NON);
1013         MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1014         reg_type = reg_to_field[ret];
1015         MLX5_ASSERT(reg_type > 0);
1016         reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1017         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1018                                              MLX5_MODIFICATION_TYPE_SET, error);
1019 }
1020
1021 /**
1022  * Convert internal COPY_REG action to DV specification.
1023  *
1024  * @param[in] dev
1025  *   Pointer to the rte_eth_dev structure.
1026  * @param[in,out] res
1027  *   Pointer to the modify-header resource.
1028  * @param[in] action
1029  *   Pointer to action specification.
1030  * @param[out] error
1031  *   Pointer to the error structure.
1032  *
1033  * @return
1034  *   0 on success, a negative errno value otherwise and rte_errno is set.
1035  */
1036 static int
1037 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1038                                  struct mlx5_flow_dv_modify_hdr_resource *res,
1039                                  const struct rte_flow_action *action,
1040                                  struct rte_flow_error *error)
1041 {
1042         const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1043         rte_be32_t mask = RTE_BE32(UINT32_MAX);
1044         struct rte_flow_item item = {
1045                 .spec = NULL,
1046                 .mask = &mask,
1047         };
1048         struct field_modify_info reg_src[] = {
1049                 {4, 0, reg_to_field[conf->src]},
1050                 {0, 0, 0},
1051         };
1052         struct field_modify_info reg_dst = {
1053                 .offset = 0,
1054                 .id = reg_to_field[conf->dst],
1055         };
1056         /* Adjust reg_c[0] usage according to reported mask. */
1057         if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1058                 struct mlx5_priv *priv = dev->data->dev_private;
1059                 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1060
1061                 MLX5_ASSERT(reg_c0);
1062                 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1063                 if (conf->dst == REG_C_0) {
1064                         /* Copy to reg_c[0], within mask only. */
1065                         reg_dst.offset = rte_bsf32(reg_c0);
1066                         /*
1067                          * Mask is ignoring the enianness, because
1068                          * there is no conversion in datapath.
1069                          */
1070 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1071                         /* Copy from destination lower bits to reg_c[0]. */
1072                         mask = reg_c0 >> reg_dst.offset;
1073 #else
1074                         /* Copy from destination upper bits to reg_c[0]. */
1075                         mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1076                                           rte_fls_u32(reg_c0));
1077 #endif
1078                 } else {
1079                         mask = rte_cpu_to_be_32(reg_c0);
1080 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1081                         /* Copy from reg_c[0] to destination lower bits. */
1082                         reg_dst.offset = 0;
1083 #else
1084                         /* Copy from reg_c[0] to destination upper bits. */
1085                         reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1086                                          (rte_fls_u32(reg_c0) -
1087                                           rte_bsf32(reg_c0));
1088 #endif
1089                 }
1090         }
1091         return flow_dv_convert_modify_action(&item,
1092                                              reg_src, &reg_dst, res,
1093                                              MLX5_MODIFICATION_TYPE_COPY,
1094                                              error);
1095 }
1096
1097 /**
1098  * Convert MARK action to DV specification. This routine is used
1099  * in extensive metadata only and requires metadata register to be
1100  * handled. In legacy mode hardware tag resource is engaged.
1101  *
1102  * @param[in] dev
1103  *   Pointer to the rte_eth_dev structure.
1104  * @param[in] conf
1105  *   Pointer to MARK action specification.
1106  * @param[in,out] resource
1107  *   Pointer to the modify-header resource.
1108  * @param[out] error
1109  *   Pointer to the error structure.
1110  *
1111  * @return
1112  *   0 on success, a negative errno value otherwise and rte_errno is set.
1113  */
1114 static int
1115 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1116                             const struct rte_flow_action_mark *conf,
1117                             struct mlx5_flow_dv_modify_hdr_resource *resource,
1118                             struct rte_flow_error *error)
1119 {
1120         struct mlx5_priv *priv = dev->data->dev_private;
1121         rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1122                                            priv->sh->dv_mark_mask);
1123         rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1124         struct rte_flow_item item = {
1125                 .spec = &data,
1126                 .mask = &mask,
1127         };
1128         struct field_modify_info reg_c_x[] = {
1129                 [1] = {0, 0, 0},
1130         };
1131         int reg;
1132
1133         if (!mask)
1134                 return rte_flow_error_set(error, EINVAL,
1135                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1136                                           NULL, "zero mark action mask");
1137         reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1138         if (reg < 0)
1139                 return reg;
1140         MLX5_ASSERT(reg > 0);
1141         if (reg == REG_C_0) {
1142                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1143                 uint32_t shl_c0 = rte_bsf32(msk_c0);
1144
1145                 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1146                 mask = rte_cpu_to_be_32(mask) & msk_c0;
1147                 mask = rte_cpu_to_be_32(mask << shl_c0);
1148         }
1149         reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1150         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1151                                              MLX5_MODIFICATION_TYPE_SET, error);
1152 }
1153
1154 /**
1155  * Get metadata register index for specified steering domain.
1156  *
1157  * @param[in] dev
1158  *   Pointer to the rte_eth_dev structure.
1159  * @param[in] attr
1160  *   Attributes of flow to determine steering domain.
1161  * @param[out] error
1162  *   Pointer to the error structure.
1163  *
1164  * @return
1165  *   positive index on success, a negative errno value otherwise
1166  *   and rte_errno is set.
1167  */
1168 static enum modify_reg
1169 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1170                          const struct rte_flow_attr *attr,
1171                          struct rte_flow_error *error)
1172 {
1173         int reg =
1174                 mlx5_flow_get_reg_id(dev, attr->transfer ?
1175                                           MLX5_METADATA_FDB :
1176                                             attr->egress ?
1177                                             MLX5_METADATA_TX :
1178                                             MLX5_METADATA_RX, 0, error);
1179         if (reg < 0)
1180                 return rte_flow_error_set(error,
1181                                           ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1182                                           NULL, "unavailable "
1183                                           "metadata register");
1184         return reg;
1185 }
1186
1187 /**
1188  * Convert SET_META action to DV specification.
1189  *
1190  * @param[in] dev
1191  *   Pointer to the rte_eth_dev structure.
1192  * @param[in,out] resource
1193  *   Pointer to the modify-header resource.
1194  * @param[in] attr
1195  *   Attributes of flow that includes this item.
1196  * @param[in] conf
1197  *   Pointer to action specification.
1198  * @param[out] error
1199  *   Pointer to the error structure.
1200  *
1201  * @return
1202  *   0 on success, a negative errno value otherwise and rte_errno is set.
1203  */
1204 static int
1205 flow_dv_convert_action_set_meta
1206                         (struct rte_eth_dev *dev,
1207                          struct mlx5_flow_dv_modify_hdr_resource *resource,
1208                          const struct rte_flow_attr *attr,
1209                          const struct rte_flow_action_set_meta *conf,
1210                          struct rte_flow_error *error)
1211 {
1212         uint32_t data = conf->data;
1213         uint32_t mask = conf->mask;
1214         struct rte_flow_item item = {
1215                 .spec = &data,
1216                 .mask = &mask,
1217         };
1218         struct field_modify_info reg_c_x[] = {
1219                 [1] = {0, 0, 0},
1220         };
1221         int reg = flow_dv_get_metadata_reg(dev, attr, error);
1222
1223         if (reg < 0)
1224                 return reg;
1225         MLX5_ASSERT(reg != REG_NON);
1226         /*
1227          * In datapath code there is no endianness
1228          * coversions for perfromance reasons, all
1229          * pattern conversions are done in rte_flow.
1230          */
1231         if (reg == REG_C_0) {
1232                 struct mlx5_priv *priv = dev->data->dev_private;
1233                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1234                 uint32_t shl_c0;
1235
1236                 MLX5_ASSERT(msk_c0);
1237 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1238                 shl_c0 = rte_bsf32(msk_c0);
1239 #else
1240                 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1241 #endif
1242                 mask <<= shl_c0;
1243                 data <<= shl_c0;
1244                 MLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1245         }
1246         reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1247         /* The routine expects parameters in memory as big-endian ones. */
1248         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1249                                              MLX5_MODIFICATION_TYPE_SET, error);
1250 }
1251
1252 /**
1253  * Convert modify-header set IPv4 DSCP action to DV specification.
1254  *
1255  * @param[in,out] resource
1256  *   Pointer to the modify-header resource.
1257  * @param[in] action
1258  *   Pointer to action specification.
1259  * @param[out] error
1260  *   Pointer to the error structure.
1261  *
1262  * @return
1263  *   0 on success, a negative errno value otherwise and rte_errno is set.
1264  */
1265 static int
1266 flow_dv_convert_action_modify_ipv4_dscp
1267                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1268                          const struct rte_flow_action *action,
1269                          struct rte_flow_error *error)
1270 {
1271         const struct rte_flow_action_set_dscp *conf =
1272                 (const struct rte_flow_action_set_dscp *)(action->conf);
1273         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1274         struct rte_flow_item_ipv4 ipv4;
1275         struct rte_flow_item_ipv4 ipv4_mask;
1276
1277         memset(&ipv4, 0, sizeof(ipv4));
1278         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1279         ipv4.hdr.type_of_service = conf->dscp;
1280         ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1281         item.spec = &ipv4;
1282         item.mask = &ipv4_mask;
1283         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1284                                              MLX5_MODIFICATION_TYPE_SET, error);
1285 }
1286
1287 /**
1288  * Convert modify-header set IPv6 DSCP action to DV specification.
1289  *
1290  * @param[in,out] resource
1291  *   Pointer to the modify-header resource.
1292  * @param[in] action
1293  *   Pointer to action specification.
1294  * @param[out] error
1295  *   Pointer to the error structure.
1296  *
1297  * @return
1298  *   0 on success, a negative errno value otherwise and rte_errno is set.
1299  */
1300 static int
1301 flow_dv_convert_action_modify_ipv6_dscp
1302                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1303                          const struct rte_flow_action *action,
1304                          struct rte_flow_error *error)
1305 {
1306         const struct rte_flow_action_set_dscp *conf =
1307                 (const struct rte_flow_action_set_dscp *)(action->conf);
1308         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1309         struct rte_flow_item_ipv6 ipv6;
1310         struct rte_flow_item_ipv6 ipv6_mask;
1311
1312         memset(&ipv6, 0, sizeof(ipv6));
1313         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1314         /*
1315          * Even though the DSCP bits offset of IPv6 is not byte aligned,
1316          * rdma-core only accept the DSCP bits byte aligned start from
1317          * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1318          * bits in IPv6 case as rdma-core requires byte aligned value.
1319          */
1320         ipv6.hdr.vtc_flow = conf->dscp;
1321         ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1322         item.spec = &ipv6;
1323         item.mask = &ipv6_mask;
1324         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1325                                              MLX5_MODIFICATION_TYPE_SET, error);
1326 }
1327
1328 static void
1329 mlx5_flow_field_id_to_modify_info
1330                 (const struct rte_flow_action_modify_data *data,
1331                  struct field_modify_info *info,
1332                  uint32_t *mask, uint32_t *value, uint32_t width,
1333                  struct rte_eth_dev *dev,
1334                  const struct rte_flow_attr *attr,
1335                  struct rte_flow_error *error)
1336 {
1337         uint32_t idx = 0;
1338         switch (data->field) {
1339         case RTE_FLOW_FIELD_START:
1340                 /* not supported yet */
1341                 MLX5_ASSERT(false);
1342                 break;
1343         case RTE_FLOW_FIELD_MAC_DST:
1344                 if (mask) {
1345                         if (data->offset < 32) {
1346                                 info[idx] = (struct field_modify_info){4, 0,
1347                                                 MLX5_MODI_OUT_DMAC_47_16};
1348                                 if (width < 32) {
1349                                         mask[idx] =
1350                                                 rte_cpu_to_be_32(0xffffffff >>
1351                                                                  (32 - width));
1352                                         width = 0;
1353                                 } else {
1354                                         mask[idx] = RTE_BE32(0xffffffff);
1355                                         width -= 32;
1356                                 }
1357                                 if (!width)
1358                                         break;
1359                                 ++idx;
1360                         }
1361                         info[idx] = (struct field_modify_info){2, 4 * idx,
1362                                                 MLX5_MODI_OUT_DMAC_15_0};
1363                         mask[idx] = rte_cpu_to_be_32(0x0000ffff >>
1364                                                      (16 - width));
1365                 } else {
1366                         if (data->offset < 32)
1367                                 info[idx++] = (struct field_modify_info){4, 0,
1368                                                 MLX5_MODI_OUT_DMAC_47_16};
1369                         info[idx] = (struct field_modify_info){2, 0,
1370                                                 MLX5_MODI_OUT_DMAC_15_0};
1371                 }
1372                 break;
1373         case RTE_FLOW_FIELD_MAC_SRC:
1374                 if (mask) {
1375                         if (data->offset < 32) {
1376                                 info[idx] = (struct field_modify_info){4, 0,
1377                                                 MLX5_MODI_OUT_SMAC_47_16};
1378                                 if (width < 32) {
1379                                         mask[idx] =
1380                                                 rte_cpu_to_be_32(0xffffffff >>
1381                                                                 (32 - width));
1382                                         width = 0;
1383                                 } else {
1384                                         mask[idx] = RTE_BE32(0xffffffff);
1385                                         width -= 32;
1386                                 }
1387                                 if (!width)
1388                                         break;
1389                                 ++idx;
1390                         }
1391                         info[idx] = (struct field_modify_info){2, 4 * idx,
1392                                                 MLX5_MODI_OUT_SMAC_15_0};
1393                         mask[idx] = rte_cpu_to_be_32(0x0000ffff >>
1394                                                      (16 - width));
1395                 } else {
1396                         if (data->offset < 32)
1397                                 info[idx++] = (struct field_modify_info){4, 0,
1398                                                 MLX5_MODI_OUT_SMAC_47_16};
1399                         info[idx] = (struct field_modify_info){2, 0,
1400                                                 MLX5_MODI_OUT_SMAC_15_0};
1401                 }
1402                 break;
1403         case RTE_FLOW_FIELD_VLAN_TYPE:
1404                 /* not supported yet */
1405                 break;
1406         case RTE_FLOW_FIELD_VLAN_ID:
1407                 info[idx] = (struct field_modify_info){2, 0,
1408                                         MLX5_MODI_OUT_FIRST_VID};
1409                 if (mask)
1410                         mask[idx] = rte_cpu_to_be_32(0x00000fff >>
1411                                                      (12 - width));
1412                 break;
1413         case RTE_FLOW_FIELD_MAC_TYPE:
1414                 info[idx] = (struct field_modify_info){2, 0,
1415                                         MLX5_MODI_OUT_ETHERTYPE};
1416                 if (mask)
1417                         mask[idx] = rte_cpu_to_be_32(0x0000ffff >>
1418                                                      (16 - width));
1419                 break;
1420         case RTE_FLOW_FIELD_IPV4_DSCP:
1421                 info[idx] = (struct field_modify_info){1, 0,
1422                                         MLX5_MODI_OUT_IP_DSCP};
1423                 if (mask)
1424                         mask[idx] = rte_cpu_to_be_32(0x0000003f >>
1425                                                      (6 - width));
1426                 break;
1427         case RTE_FLOW_FIELD_IPV4_TTL:
1428                 info[idx] = (struct field_modify_info){1, 0,
1429                                         MLX5_MODI_OUT_IPV4_TTL};
1430                 if (mask)
1431                         mask[idx] = rte_cpu_to_be_32(0x000000ff >>
1432                                                      (8 - width));
1433                 break;
1434         case RTE_FLOW_FIELD_IPV4_SRC:
1435                 info[idx] = (struct field_modify_info){4, 0,
1436                                         MLX5_MODI_OUT_SIPV4};
1437                 if (mask)
1438                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1439                                                      (32 - width));
1440                 break;
1441         case RTE_FLOW_FIELD_IPV4_DST:
1442                 info[idx] = (struct field_modify_info){4, 0,
1443                                         MLX5_MODI_OUT_DIPV4};
1444                 if (mask)
1445                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1446                                                      (32 - width));
1447                 break;
1448         case RTE_FLOW_FIELD_IPV6_DSCP:
1449                 info[idx] = (struct field_modify_info){1, 0,
1450                                         MLX5_MODI_OUT_IP_DSCP};
1451                 if (mask)
1452                         mask[idx] = rte_cpu_to_be_32(0x0000003f >>
1453                                                      (6 - width));
1454                 break;
1455         case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
1456                 info[idx] = (struct field_modify_info){1, 0,
1457                                         MLX5_MODI_OUT_IPV6_HOPLIMIT};
1458                 if (mask)
1459                         mask[idx] = rte_cpu_to_be_32(0x000000ff >>
1460                                                      (8 - width));
1461                 break;
1462         case RTE_FLOW_FIELD_IPV6_SRC:
1463                 if (mask) {
1464                         if (data->offset < 32) {
1465                                 info[idx] = (struct field_modify_info){4, 0,
1466                                                 MLX5_MODI_OUT_SIPV6_127_96};
1467                                 if (width < 32) {
1468                                         mask[idx] =
1469                                                 rte_cpu_to_be_32(0xffffffff >>
1470                                                                  (32 - width));
1471                                         width = 0;
1472                                 } else {
1473                                         mask[idx] = RTE_BE32(0xffffffff);
1474                                         width -= 32;
1475                                 }
1476                                 if (!width)
1477                                         break;
1478                                 ++idx;
1479                         }
1480                         if (data->offset < 64) {
1481                                 info[idx] = (struct field_modify_info){4,
1482                                                 4 * idx,
1483                                                 MLX5_MODI_OUT_SIPV6_95_64};
1484                                 if (width < 32) {
1485                                         mask[idx] =
1486                                                 rte_cpu_to_be_32(0xffffffff >>
1487                                                                  (32 - width));
1488                                         width = 0;
1489                                 } else {
1490                                         mask[idx] = RTE_BE32(0xffffffff);
1491                                         width -= 32;
1492                                 }
1493                                 if (!width)
1494                                         break;
1495                                 ++idx;
1496                         }
1497                         if (data->offset < 96) {
1498                                 info[idx] = (struct field_modify_info){4,
1499                                                 8 * idx,
1500                                                 MLX5_MODI_OUT_SIPV6_63_32};
1501                                 if (width < 32) {
1502                                         mask[idx] =
1503                                                 rte_cpu_to_be_32(0xffffffff >>
1504                                                                  (32 - width));
1505                                         width = 0;
1506                                 } else {
1507                                         mask[idx] = RTE_BE32(0xffffffff);
1508                                         width -= 32;
1509                                 }
1510                                 if (!width)
1511                                         break;
1512                                 ++idx;
1513                         }
1514                         info[idx] = (struct field_modify_info){4, 12 * idx,
1515                                                 MLX5_MODI_OUT_SIPV6_31_0};
1516                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1517                                                      (32 - width));
1518                 } else {
1519                         if (data->offset < 32)
1520                                 info[idx++] = (struct field_modify_info){4, 0,
1521                                                 MLX5_MODI_OUT_SIPV6_127_96};
1522                         if (data->offset < 64)
1523                                 info[idx++] = (struct field_modify_info){4, 0,
1524                                                 MLX5_MODI_OUT_SIPV6_95_64};
1525                         if (data->offset < 96)
1526                                 info[idx++] = (struct field_modify_info){4, 0,
1527                                                 MLX5_MODI_OUT_SIPV6_63_32};
1528                         if (data->offset < 128)
1529                                 info[idx++] = (struct field_modify_info){4, 0,
1530                                                 MLX5_MODI_OUT_SIPV6_31_0};
1531                 }
1532                 break;
1533         case RTE_FLOW_FIELD_IPV6_DST:
1534                 if (mask) {
1535                         if (data->offset < 32) {
1536                                 info[idx] = (struct field_modify_info){4, 0,
1537                                                 MLX5_MODI_OUT_DIPV6_127_96};
1538                                 if (width < 32) {
1539                                         mask[idx] =
1540                                                 rte_cpu_to_be_32(0xffffffff >>
1541                                                                  (32 - width));
1542                                         width = 0;
1543                                 } else {
1544                                         mask[idx] = RTE_BE32(0xffffffff);
1545                                         width -= 32;
1546                                 }
1547                                 if (!width)
1548                                         break;
1549                                 ++idx;
1550                         }
1551                         if (data->offset < 64) {
1552                                 info[idx] = (struct field_modify_info){4,
1553                                                 4 * idx,
1554                                                 MLX5_MODI_OUT_DIPV6_95_64};
1555                                 if (width < 32) {
1556                                         mask[idx] =
1557                                                 rte_cpu_to_be_32(0xffffffff >>
1558                                                                  (32 - width));
1559                                         width = 0;
1560                                 } else {
1561                                         mask[idx] = RTE_BE32(0xffffffff);
1562                                         width -= 32;
1563                                 }
1564                                 if (!width)
1565                                         break;
1566                                 ++idx;
1567                         }
1568                         if (data->offset < 96) {
1569                                 info[idx] = (struct field_modify_info){4,
1570                                                 8 * idx,
1571                                                 MLX5_MODI_OUT_DIPV6_63_32};
1572                                 if (width < 32) {
1573                                         mask[idx] =
1574                                                 rte_cpu_to_be_32(0xffffffff >>
1575                                                                  (32 - width));
1576                                         width = 0;
1577                                 } else {
1578                                         mask[idx] = RTE_BE32(0xffffffff);
1579                                         width -= 32;
1580                                 }
1581                                 if (!width)
1582                                         break;
1583                                 ++idx;
1584                         }
1585                         info[idx] = (struct field_modify_info){4, 12 * idx,
1586                                                 MLX5_MODI_OUT_DIPV6_31_0};
1587                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1588                                                      (32 - width));
1589                 } else {
1590                         if (data->offset < 32)
1591                                 info[idx++] = (struct field_modify_info){4, 0,
1592                                                 MLX5_MODI_OUT_DIPV6_127_96};
1593                         if (data->offset < 64)
1594                                 info[idx++] = (struct field_modify_info){4, 0,
1595                                                 MLX5_MODI_OUT_DIPV6_95_64};
1596                         if (data->offset < 96)
1597                                 info[idx++] = (struct field_modify_info){4, 0,
1598                                                 MLX5_MODI_OUT_DIPV6_63_32};
1599                         if (data->offset < 128)
1600                                 info[idx++] = (struct field_modify_info){4, 0,
1601                                                 MLX5_MODI_OUT_DIPV6_31_0};
1602                 }
1603                 break;
1604         case RTE_FLOW_FIELD_TCP_PORT_SRC:
1605                 info[idx] = (struct field_modify_info){2, 0,
1606                                         MLX5_MODI_OUT_TCP_SPORT};
1607                 if (mask)
1608                         mask[idx] = rte_cpu_to_be_32(0x0000ffff >>
1609                                                      (16 - width));
1610                 break;
1611         case RTE_FLOW_FIELD_TCP_PORT_DST:
1612                 info[idx] = (struct field_modify_info){2, 0,
1613                                         MLX5_MODI_OUT_TCP_DPORT};
1614                 if (mask)
1615                         mask[idx] = rte_cpu_to_be_32(0x0000ffff >>
1616                                                      (16 - width));
1617                 break;
1618         case RTE_FLOW_FIELD_TCP_SEQ_NUM:
1619                 info[idx] = (struct field_modify_info){4, 0,
1620                                         MLX5_MODI_OUT_TCP_SEQ_NUM};
1621                 if (mask)
1622                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1623                                                      (32 - width));
1624                 break;
1625         case RTE_FLOW_FIELD_TCP_ACK_NUM:
1626                 info[idx] = (struct field_modify_info){4, 0,
1627                                         MLX5_MODI_OUT_TCP_ACK_NUM};
1628                 if (mask)
1629                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1630                                                      (32 - width));
1631                 break;
1632         case RTE_FLOW_FIELD_TCP_FLAGS:
1633                 info[idx] = (struct field_modify_info){1, 0,
1634                                         MLX5_MODI_OUT_TCP_FLAGS};
1635                 if (mask)
1636                         mask[idx] = rte_cpu_to_be_32(0x0000003f >>
1637                                                      (6 - width));
1638                 break;
1639         case RTE_FLOW_FIELD_UDP_PORT_SRC:
1640                 info[idx] = (struct field_modify_info){2, 0,
1641                                         MLX5_MODI_OUT_UDP_SPORT};
1642                 if (mask)
1643                         mask[idx] = rte_cpu_to_be_32(0x0000ffff >>
1644                                                      (16 - width));
1645                 break;
1646         case RTE_FLOW_FIELD_UDP_PORT_DST:
1647                 info[idx] = (struct field_modify_info){2, 0,
1648                                         MLX5_MODI_OUT_UDP_DPORT};
1649                 if (mask)
1650                         mask[idx] = rte_cpu_to_be_32(0x0000ffff >>
1651                                                      (16 - width));
1652                 break;
1653         case RTE_FLOW_FIELD_VXLAN_VNI:
1654                 /* not supported yet */
1655                 break;
1656         case RTE_FLOW_FIELD_GENEVE_VNI:
1657                 /* not supported yet*/
1658                 break;
1659         case RTE_FLOW_FIELD_GTP_TEID:
1660                 info[idx] = (struct field_modify_info){4, 0,
1661                                         MLX5_MODI_GTP_TEID};
1662                 if (mask)
1663                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1664                                                      (32 - width));
1665                 break;
1666         case RTE_FLOW_FIELD_TAG:
1667                 {
1668                         int reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG,
1669                                                    data->level, error);
1670                         if (reg < 0)
1671                                 return;
1672                         MLX5_ASSERT(reg != REG_NON);
1673                         MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1674                         info[idx] = (struct field_modify_info){4, 0,
1675                                                 reg_to_field[reg]};
1676                         if (mask)
1677                                 mask[idx] =
1678                                         rte_cpu_to_be_32(0xffffffff >>
1679                                                          (32 - width));
1680                 }
1681                 break;
1682         case RTE_FLOW_FIELD_MARK:
1683                 {
1684                         int reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK,
1685                                                        0, error);
1686                         if (reg < 0)
1687                                 return;
1688                         MLX5_ASSERT(reg != REG_NON);
1689                         MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1690                         info[idx] = (struct field_modify_info){4, 0,
1691                                                 reg_to_field[reg]};
1692                         if (mask)
1693                                 mask[idx] =
1694                                         rte_cpu_to_be_32(0xffffffff >>
1695                                                          (32 - width));
1696                 }
1697                 break;
1698         case RTE_FLOW_FIELD_META:
1699                 {
1700                         int reg = flow_dv_get_metadata_reg(dev, attr, error);
1701                         if (reg < 0)
1702                                 return;
1703                         MLX5_ASSERT(reg != REG_NON);
1704                         MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1705                         info[idx] = (struct field_modify_info){4, 0,
1706                                                 reg_to_field[reg]};
1707                         if (mask)
1708                                 mask[idx] =
1709                                         rte_cpu_to_be_32(0xffffffff >>
1710                                                          (32 - width));
1711                 }
1712                 break;
1713         case RTE_FLOW_FIELD_POINTER:
1714                 for (idx = 0; idx < MLX5_ACT_MAX_MOD_FIELDS; idx++) {
1715                         if (mask[idx]) {
1716                                 memcpy(&value[idx],
1717                                         (void *)(uintptr_t)data->value, 32);
1718                                 value[idx] = rte_cpu_to_be_32(value[idx]);
1719                                 break;
1720                         }
1721                 }
1722                 break;
1723         case RTE_FLOW_FIELD_VALUE:
1724                 for (idx = 0; idx < MLX5_ACT_MAX_MOD_FIELDS; idx++) {
1725                         if (mask[idx]) {
1726                                 value[idx] =
1727                                         rte_cpu_to_be_32((uint32_t)data->value);
1728                                 break;
1729                         }
1730                 }
1731                 break;
1732         default:
1733                 MLX5_ASSERT(false);
1734                 break;
1735         }
1736 }
1737
1738 /**
1739  * Convert modify_field action to DV specification.
1740  *
1741  * @param[in] dev
1742  *   Pointer to the rte_eth_dev structure.
1743  * @param[in,out] resource
1744  *   Pointer to the modify-header resource.
1745  * @param[in] action
1746  *   Pointer to action specification.
1747  * @param[in] attr
1748  *   Attributes of flow that includes this item.
1749  * @param[out] error
1750  *   Pointer to the error structure.
1751  *
1752  * @return
1753  *   0 on success, a negative errno value otherwise and rte_errno is set.
1754  */
1755 static int
1756 flow_dv_convert_action_modify_field
1757                         (struct rte_eth_dev *dev,
1758                          struct mlx5_flow_dv_modify_hdr_resource *resource,
1759                          const struct rte_flow_action *action,
1760                          const struct rte_flow_attr *attr,
1761                          struct rte_flow_error *error)
1762 {
1763         const struct rte_flow_action_modify_field *conf =
1764                 (const struct rte_flow_action_modify_field *)(action->conf);
1765         struct rte_flow_item item;
1766         struct field_modify_info field[MLX5_ACT_MAX_MOD_FIELDS] = {
1767                                                                 {0, 0, 0} };
1768         struct field_modify_info dcopy[MLX5_ACT_MAX_MOD_FIELDS] = {
1769                                                                 {0, 0, 0} };
1770         uint32_t mask[MLX5_ACT_MAX_MOD_FIELDS] = {0, 0, 0, 0, 0};
1771         uint32_t value[MLX5_ACT_MAX_MOD_FIELDS] = {0, 0, 0, 0, 0};
1772         uint32_t type;
1773
1774         if (conf->src.field == RTE_FLOW_FIELD_POINTER ||
1775                 conf->src.field == RTE_FLOW_FIELD_VALUE) {
1776                 type = MLX5_MODIFICATION_TYPE_SET;
1777                 /** For SET fill the destination field (field) first. */
1778                 mlx5_flow_field_id_to_modify_info(&conf->dst, field, mask,
1779                                           value, conf->width, dev, attr, error);
1780                 /** Then copy immediate value from source as per mask. */
1781                 mlx5_flow_field_id_to_modify_info(&conf->src, dcopy, mask,
1782                                           value, conf->width, dev, attr, error);
1783                 item.spec = &value;
1784         } else {
1785                 type = MLX5_MODIFICATION_TYPE_COPY;
1786                 /** For COPY fill the destination field (dcopy) without mask. */
1787                 mlx5_flow_field_id_to_modify_info(&conf->dst, dcopy, NULL,
1788                                           value, conf->width, dev, attr, error);
1789                 /** Then construct the source field (field) with mask. */
1790                 mlx5_flow_field_id_to_modify_info(&conf->src, field, mask,
1791                                           value, conf->width, dev, attr, error);
1792         }
1793         item.mask = &mask;
1794         return flow_dv_convert_modify_action(&item,
1795                         field, dcopy, resource, type, error);
1796 }
1797
1798 /**
1799  * Validate MARK item.
1800  *
1801  * @param[in] dev
1802  *   Pointer to the rte_eth_dev structure.
1803  * @param[in] item
1804  *   Item specification.
1805  * @param[in] attr
1806  *   Attributes of flow that includes this item.
1807  * @param[out] error
1808  *   Pointer to error structure.
1809  *
1810  * @return
1811  *   0 on success, a negative errno value otherwise and rte_errno is set.
1812  */
1813 static int
1814 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1815                            const struct rte_flow_item *item,
1816                            const struct rte_flow_attr *attr __rte_unused,
1817                            struct rte_flow_error *error)
1818 {
1819         struct mlx5_priv *priv = dev->data->dev_private;
1820         struct mlx5_dev_config *config = &priv->config;
1821         const struct rte_flow_item_mark *spec = item->spec;
1822         const struct rte_flow_item_mark *mask = item->mask;
1823         const struct rte_flow_item_mark nic_mask = {
1824                 .id = priv->sh->dv_mark_mask,
1825         };
1826         int ret;
1827
1828         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1829                 return rte_flow_error_set(error, ENOTSUP,
1830                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1831                                           "extended metadata feature"
1832                                           " isn't enabled");
1833         if (!mlx5_flow_ext_mreg_supported(dev))
1834                 return rte_flow_error_set(error, ENOTSUP,
1835                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1836                                           "extended metadata register"
1837                                           " isn't supported");
1838         if (!nic_mask.id)
1839                 return rte_flow_error_set(error, ENOTSUP,
1840                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1841                                           "extended metadata register"
1842                                           " isn't available");
1843         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1844         if (ret < 0)
1845                 return ret;
1846         if (!spec)
1847                 return rte_flow_error_set(error, EINVAL,
1848                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1849                                           item->spec,
1850                                           "data cannot be empty");
1851         if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1852                 return rte_flow_error_set(error, EINVAL,
1853                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1854                                           &spec->id,
1855                                           "mark id exceeds the limit");
1856         if (!mask)
1857                 mask = &nic_mask;
1858         if (!mask->id)
1859                 return rte_flow_error_set(error, EINVAL,
1860                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1861                                         "mask cannot be zero");
1862
1863         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1864                                         (const uint8_t *)&nic_mask,
1865                                         sizeof(struct rte_flow_item_mark),
1866                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1867         if (ret < 0)
1868                 return ret;
1869         return 0;
1870 }
1871
1872 /**
1873  * Validate META item.
1874  *
1875  * @param[in] dev
1876  *   Pointer to the rte_eth_dev structure.
1877  * @param[in] item
1878  *   Item specification.
1879  * @param[in] attr
1880  *   Attributes of flow that includes this item.
1881  * @param[out] error
1882  *   Pointer to error structure.
1883  *
1884  * @return
1885  *   0 on success, a negative errno value otherwise and rte_errno is set.
1886  */
1887 static int
1888 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1889                            const struct rte_flow_item *item,
1890                            const struct rte_flow_attr *attr,
1891                            struct rte_flow_error *error)
1892 {
1893         struct mlx5_priv *priv = dev->data->dev_private;
1894         struct mlx5_dev_config *config = &priv->config;
1895         const struct rte_flow_item_meta *spec = item->spec;
1896         const struct rte_flow_item_meta *mask = item->mask;
1897         struct rte_flow_item_meta nic_mask = {
1898                 .data = UINT32_MAX
1899         };
1900         int reg;
1901         int ret;
1902
1903         if (!spec)
1904                 return rte_flow_error_set(error, EINVAL,
1905                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1906                                           item->spec,
1907                                           "data cannot be empty");
1908         if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1909                 if (!mlx5_flow_ext_mreg_supported(dev))
1910                         return rte_flow_error_set(error, ENOTSUP,
1911                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1912                                           "extended metadata register"
1913                                           " isn't supported");
1914                 reg = flow_dv_get_metadata_reg(dev, attr, error);
1915                 if (reg < 0)
1916                         return reg;
1917                 if (reg == REG_NON)
1918                         return rte_flow_error_set(error, ENOTSUP,
1919                                         RTE_FLOW_ERROR_TYPE_ITEM, item,
1920                                         "unavalable extended metadata register");
1921                 if (reg == REG_B)
1922                         return rte_flow_error_set(error, ENOTSUP,
1923                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1924                                           "match on reg_b "
1925                                           "isn't supported");
1926                 if (reg != REG_A)
1927                         nic_mask.data = priv->sh->dv_meta_mask;
1928         } else {
1929                 if (attr->transfer)
1930                         return rte_flow_error_set(error, ENOTSUP,
1931                                         RTE_FLOW_ERROR_TYPE_ITEM, item,
1932                                         "extended metadata feature "
1933                                         "should be enabled when "
1934                                         "meta item is requested "
1935                                         "with e-switch mode ");
1936                 if (attr->ingress)
1937                         return rte_flow_error_set(error, ENOTSUP,
1938                                         RTE_FLOW_ERROR_TYPE_ITEM, item,
1939                                         "match on metadata for ingress "
1940                                         "is not supported in legacy "
1941                                         "metadata mode");
1942         }
1943         if (!mask)
1944                 mask = &rte_flow_item_meta_mask;
1945         if (!mask->data)
1946                 return rte_flow_error_set(error, EINVAL,
1947                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1948                                         "mask cannot be zero");
1949
1950         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1951                                         (const uint8_t *)&nic_mask,
1952                                         sizeof(struct rte_flow_item_meta),
1953                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1954         return ret;
1955 }
1956
1957 /**
1958  * Validate TAG item.
1959  *
1960  * @param[in] dev
1961  *   Pointer to the rte_eth_dev structure.
1962  * @param[in] item
1963  *   Item specification.
1964  * @param[in] attr
1965  *   Attributes of flow that includes this item.
1966  * @param[out] error
1967  *   Pointer to error structure.
1968  *
1969  * @return
1970  *   0 on success, a negative errno value otherwise and rte_errno is set.
1971  */
1972 static int
1973 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
1974                           const struct rte_flow_item *item,
1975                           const struct rte_flow_attr *attr __rte_unused,
1976                           struct rte_flow_error *error)
1977 {
1978         const struct rte_flow_item_tag *spec = item->spec;
1979         const struct rte_flow_item_tag *mask = item->mask;
1980         const struct rte_flow_item_tag nic_mask = {
1981                 .data = RTE_BE32(UINT32_MAX),
1982                 .index = 0xff,
1983         };
1984         int ret;
1985
1986         if (!mlx5_flow_ext_mreg_supported(dev))
1987                 return rte_flow_error_set(error, ENOTSUP,
1988                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1989                                           "extensive metadata register"
1990                                           " isn't supported");
1991         if (!spec)
1992                 return rte_flow_error_set(error, EINVAL,
1993                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1994                                           item->spec,
1995                                           "data cannot be empty");
1996         if (!mask)
1997                 mask = &rte_flow_item_tag_mask;
1998         if (!mask->data)
1999                 return rte_flow_error_set(error, EINVAL,
2000                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2001                                         "mask cannot be zero");
2002
2003         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2004                                         (const uint8_t *)&nic_mask,
2005                                         sizeof(struct rte_flow_item_tag),
2006                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2007         if (ret < 0)
2008                 return ret;
2009         if (mask->index != 0xff)
2010                 return rte_flow_error_set(error, EINVAL,
2011                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2012                                           "partial mask for tag index"
2013                                           " is not supported");
2014         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
2015         if (ret < 0)
2016                 return ret;
2017         MLX5_ASSERT(ret != REG_NON);
2018         return 0;
2019 }
2020
2021 /**
2022  * Validate vport item.
2023  *
2024  * @param[in] dev
2025  *   Pointer to the rte_eth_dev structure.
2026  * @param[in] item
2027  *   Item specification.
2028  * @param[in] attr
2029  *   Attributes of flow that includes this item.
2030  * @param[in] item_flags
2031  *   Bit-fields that holds the items detected until now.
2032  * @param[out] error
2033  *   Pointer to error structure.
2034  *
2035  * @return
2036  *   0 on success, a negative errno value otherwise and rte_errno is set.
2037  */
2038 static int
2039 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
2040                               const struct rte_flow_item *item,
2041                               const struct rte_flow_attr *attr,
2042                               uint64_t item_flags,
2043                               struct rte_flow_error *error)
2044 {
2045         const struct rte_flow_item_port_id *spec = item->spec;
2046         const struct rte_flow_item_port_id *mask = item->mask;
2047         const struct rte_flow_item_port_id switch_mask = {
2048                         .id = 0xffffffff,
2049         };
2050         struct mlx5_priv *esw_priv;
2051         struct mlx5_priv *dev_priv;
2052         int ret;
2053
2054         if (!attr->transfer)
2055                 return rte_flow_error_set(error, EINVAL,
2056                                           RTE_FLOW_ERROR_TYPE_ITEM,
2057                                           NULL,
2058                                           "match on port id is valid only"
2059                                           " when transfer flag is enabled");
2060         if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
2061                 return rte_flow_error_set(error, ENOTSUP,
2062                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2063                                           "multiple source ports are not"
2064                                           " supported");
2065         if (!mask)
2066                 mask = &switch_mask;
2067         if (mask->id != 0xffffffff)
2068                 return rte_flow_error_set(error, ENOTSUP,
2069                                            RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2070                                            mask,
2071                                            "no support for partial mask on"
2072                                            " \"id\" field");
2073         ret = mlx5_flow_item_acceptable
2074                                 (item, (const uint8_t *)mask,
2075                                  (const uint8_t *)&rte_flow_item_port_id_mask,
2076                                  sizeof(struct rte_flow_item_port_id),
2077                                  MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2078         if (ret)
2079                 return ret;
2080         if (!spec)
2081                 return 0;
2082         esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
2083         if (!esw_priv)
2084                 return rte_flow_error_set(error, rte_errno,
2085                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
2086                                           "failed to obtain E-Switch info for"
2087                                           " port");
2088         dev_priv = mlx5_dev_to_eswitch_info(dev);
2089         if (!dev_priv)
2090                 return rte_flow_error_set(error, rte_errno,
2091                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2092                                           NULL,
2093                                           "failed to obtain E-Switch info");
2094         if (esw_priv->domain_id != dev_priv->domain_id)
2095                 return rte_flow_error_set(error, EINVAL,
2096                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
2097                                           "cannot match on a port from a"
2098                                           " different E-Switch");
2099         return 0;
2100 }
2101
2102 /**
2103  * Validate VLAN item.
2104  *
2105  * @param[in] item
2106  *   Item specification.
2107  * @param[in] item_flags
2108  *   Bit-fields that holds the items detected until now.
2109  * @param[in] dev
2110  *   Ethernet device flow is being created on.
2111  * @param[out] error
2112  *   Pointer to error structure.
2113  *
2114  * @return
2115  *   0 on success, a negative errno value otherwise and rte_errno is set.
2116  */
2117 static int
2118 flow_dv_validate_item_vlan(const struct rte_flow_item *item,
2119                            uint64_t item_flags,
2120                            struct rte_eth_dev *dev,
2121                            struct rte_flow_error *error)
2122 {
2123         const struct rte_flow_item_vlan *mask = item->mask;
2124         const struct rte_flow_item_vlan nic_mask = {
2125                 .tci = RTE_BE16(UINT16_MAX),
2126                 .inner_type = RTE_BE16(UINT16_MAX),
2127                 .has_more_vlan = 1,
2128         };
2129         const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2130         int ret;
2131         const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 |
2132                                         MLX5_FLOW_LAYER_INNER_L4) :
2133                                        (MLX5_FLOW_LAYER_OUTER_L3 |
2134                                         MLX5_FLOW_LAYER_OUTER_L4);
2135         const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
2136                                         MLX5_FLOW_LAYER_OUTER_VLAN;
2137
2138         if (item_flags & vlanm)
2139                 return rte_flow_error_set(error, EINVAL,
2140                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2141                                           "multiple VLAN layers not supported");
2142         else if ((item_flags & l34m) != 0)
2143                 return rte_flow_error_set(error, EINVAL,
2144                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2145                                           "VLAN cannot follow L3/L4 layer");
2146         if (!mask)
2147                 mask = &rte_flow_item_vlan_mask;
2148         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2149                                         (const uint8_t *)&nic_mask,
2150                                         sizeof(struct rte_flow_item_vlan),
2151                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2152         if (ret)
2153                 return ret;
2154         if (!tunnel && mask->tci != RTE_BE16(0x0fff)) {
2155                 struct mlx5_priv *priv = dev->data->dev_private;
2156
2157                 if (priv->vmwa_context) {
2158                         /*
2159                          * Non-NULL context means we have a virtual machine
2160                          * and SR-IOV enabled, we have to create VLAN interface
2161                          * to make hypervisor to setup E-Switch vport
2162                          * context correctly. We avoid creating the multiple
2163                          * VLAN interfaces, so we cannot support VLAN tag mask.
2164                          */
2165                         return rte_flow_error_set(error, EINVAL,
2166                                                   RTE_FLOW_ERROR_TYPE_ITEM,
2167                                                   item,
2168                                                   "VLAN tag mask is not"
2169                                                   " supported in virtual"
2170                                                   " environment");
2171                 }
2172         }
2173         return 0;
2174 }
2175
2176 /*
2177  * GTP flags are contained in 1 byte of the format:
2178  * -------------------------------------------
2179  * | bit   | 0 - 2   | 3  | 4   | 5 | 6 | 7  |
2180  * |-----------------------------------------|
2181  * | value | Version | PT | Res | E | S | PN |
2182  * -------------------------------------------
2183  *
2184  * Matching is supported only for GTP flags E, S, PN.
2185  */
2186 #define MLX5_GTP_FLAGS_MASK     0x07
2187
2188 /**
2189  * Validate GTP item.
2190  *
2191  * @param[in] dev
2192  *   Pointer to the rte_eth_dev structure.
2193  * @param[in] item
2194  *   Item specification.
2195  * @param[in] item_flags
2196  *   Bit-fields that holds the items detected until now.
2197  * @param[out] error
2198  *   Pointer to error structure.
2199  *
2200  * @return
2201  *   0 on success, a negative errno value otherwise and rte_errno is set.
2202  */
2203 static int
2204 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
2205                           const struct rte_flow_item *item,
2206                           uint64_t item_flags,
2207                           struct rte_flow_error *error)
2208 {
2209         struct mlx5_priv *priv = dev->data->dev_private;
2210         const struct rte_flow_item_gtp *spec = item->spec;
2211         const struct rte_flow_item_gtp *mask = item->mask;
2212         const struct rte_flow_item_gtp nic_mask = {
2213                 .v_pt_rsv_flags = MLX5_GTP_FLAGS_MASK,
2214                 .msg_type = 0xff,
2215                 .teid = RTE_BE32(0xffffffff),
2216         };
2217
2218         if (!priv->config.hca_attr.tunnel_stateless_gtp)
2219                 return rte_flow_error_set(error, ENOTSUP,
2220                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2221                                           "GTP support is not enabled");
2222         if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
2223                 return rte_flow_error_set(error, ENOTSUP,
2224                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2225                                           "multiple tunnel layers not"
2226                                           " supported");
2227         if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
2228                 return rte_flow_error_set(error, EINVAL,
2229                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2230                                           "no outer UDP layer found");
2231         if (!mask)
2232                 mask = &rte_flow_item_gtp_mask;
2233         if (spec && spec->v_pt_rsv_flags & ~MLX5_GTP_FLAGS_MASK)
2234                 return rte_flow_error_set(error, ENOTSUP,
2235                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2236                                           "Match is supported for GTP"
2237                                           " flags only");
2238         return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2239                                          (const uint8_t *)&nic_mask,
2240                                          sizeof(struct rte_flow_item_gtp),
2241                                          MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2242 }
2243
2244 /**
2245  * Validate GTP PSC item.
2246  *
2247  * @param[in] item
2248  *   Item specification.
2249  * @param[in] last_item
2250  *   Previous validated item in the pattern items.
2251  * @param[in] gtp_item
2252  *   Previous GTP item specification.
2253  * @param[in] attr
2254  *   Pointer to flow attributes.
2255  * @param[out] error
2256  *   Pointer to error structure.
2257  *
2258  * @return
2259  *   0 on success, a negative errno value otherwise and rte_errno is set.
2260  */
2261 static int
2262 flow_dv_validate_item_gtp_psc(const struct rte_flow_item *item,
2263                               uint64_t last_item,
2264                               const struct rte_flow_item *gtp_item,
2265                               const struct rte_flow_attr *attr,
2266                               struct rte_flow_error *error)
2267 {
2268         const struct rte_flow_item_gtp *gtp_spec;
2269         const struct rte_flow_item_gtp *gtp_mask;
2270         const struct rte_flow_item_gtp_psc *spec;
2271         const struct rte_flow_item_gtp_psc *mask;
2272         const struct rte_flow_item_gtp_psc nic_mask = {
2273                 .pdu_type = 0xFF,
2274                 .qfi = 0xFF,
2275         };
2276
2277         if (!gtp_item || !(last_item & MLX5_FLOW_LAYER_GTP))
2278                 return rte_flow_error_set
2279                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2280                          "GTP PSC item must be preceded with GTP item");
2281         gtp_spec = gtp_item->spec;
2282         gtp_mask = gtp_item->mask ? gtp_item->mask : &rte_flow_item_gtp_mask;
2283         /* GTP spec and E flag is requested to match zero. */
2284         if (gtp_spec &&
2285                 (gtp_mask->v_pt_rsv_flags &
2286                 ~gtp_spec->v_pt_rsv_flags & MLX5_GTP_EXT_HEADER_FLAG))
2287                 return rte_flow_error_set
2288                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2289                          "GTP E flag must be 1 to match GTP PSC");
2290         /* Check the flow is not created in group zero. */
2291         if (!attr->transfer && !attr->group)
2292                 return rte_flow_error_set
2293                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2294                          "GTP PSC is not supported for group 0");
2295         /* GTP spec is here and E flag is requested to match zero. */
2296         if (!item->spec)
2297                 return 0;
2298         spec = item->spec;
2299         mask = item->mask ? item->mask : &rte_flow_item_gtp_psc_mask;
2300         if (spec->pdu_type > MLX5_GTP_EXT_MAX_PDU_TYPE)
2301                 return rte_flow_error_set
2302                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2303                          "PDU type should be smaller than 16");
2304         return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2305                                          (const uint8_t *)&nic_mask,
2306                                          sizeof(struct rte_flow_item_gtp_psc),
2307                                          MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2308 }
2309
2310 /**
2311  * Validate IPV4 item.
2312  * Use existing validation function mlx5_flow_validate_item_ipv4(), and
2313  * add specific validation of fragment_offset field,
2314  *
2315  * @param[in] item
2316  *   Item specification.
2317  * @param[in] item_flags
2318  *   Bit-fields that holds the items detected until now.
2319  * @param[out] error
2320  *   Pointer to error structure.
2321  *
2322  * @return
2323  *   0 on success, a negative errno value otherwise and rte_errno is set.
2324  */
2325 static int
2326 flow_dv_validate_item_ipv4(const struct rte_flow_item *item,
2327                            uint64_t item_flags,
2328                            uint64_t last_item,
2329                            uint16_t ether_type,
2330                            struct rte_flow_error *error)
2331 {
2332         int ret;
2333         const struct rte_flow_item_ipv4 *spec = item->spec;
2334         const struct rte_flow_item_ipv4 *last = item->last;
2335         const struct rte_flow_item_ipv4 *mask = item->mask;
2336         rte_be16_t fragment_offset_spec = 0;
2337         rte_be16_t fragment_offset_last = 0;
2338         const struct rte_flow_item_ipv4 nic_ipv4_mask = {
2339                 .hdr = {
2340                         .src_addr = RTE_BE32(0xffffffff),
2341                         .dst_addr = RTE_BE32(0xffffffff),
2342                         .type_of_service = 0xff,
2343                         .fragment_offset = RTE_BE16(0xffff),
2344                         .next_proto_id = 0xff,
2345                         .time_to_live = 0xff,
2346                 },
2347         };
2348
2349         ret = mlx5_flow_validate_item_ipv4(item, item_flags, last_item,
2350                                            ether_type, &nic_ipv4_mask,
2351                                            MLX5_ITEM_RANGE_ACCEPTED, error);
2352         if (ret < 0)
2353                 return ret;
2354         if (spec && mask)
2355                 fragment_offset_spec = spec->hdr.fragment_offset &
2356                                        mask->hdr.fragment_offset;
2357         if (!fragment_offset_spec)
2358                 return 0;
2359         /*
2360          * spec and mask are valid, enforce using full mask to make sure the
2361          * complete value is used correctly.
2362          */
2363         if ((mask->hdr.fragment_offset & RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2364                         != RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2365                 return rte_flow_error_set(error, EINVAL,
2366                                           RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2367                                           item, "must use full mask for"
2368                                           " fragment_offset");
2369         /*
2370          * Match on fragment_offset 0x2000 means MF is 1 and frag-offset is 0,
2371          * indicating this is 1st fragment of fragmented packet.
2372          * This is not yet supported in MLX5, return appropriate error message.
2373          */
2374         if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG))
2375                 return rte_flow_error_set(error, ENOTSUP,
2376                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2377                                           "match on first fragment not "
2378                                           "supported");
2379         if (fragment_offset_spec && !last)
2380                 return rte_flow_error_set(error, ENOTSUP,
2381                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2382                                           "specified value not supported");
2383         /* spec and last are valid, validate the specified range. */
2384         fragment_offset_last = last->hdr.fragment_offset &
2385                                mask->hdr.fragment_offset;
2386         /*
2387          * Match on fragment_offset spec 0x2001 and last 0x3fff
2388          * means MF is 1 and frag-offset is > 0.
2389          * This packet is fragment 2nd and onward, excluding last.
2390          * This is not yet supported in MLX5, return appropriate
2391          * error message.
2392          */
2393         if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG + 1) &&
2394             fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2395                 return rte_flow_error_set(error, ENOTSUP,
2396                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2397                                           last, "match on following "
2398                                           "fragments not supported");
2399         /*
2400          * Match on fragment_offset spec 0x0001 and last 0x1fff
2401          * means MF is 0 and frag-offset is > 0.
2402          * This packet is last fragment of fragmented packet.
2403          * This is not yet supported in MLX5, return appropriate
2404          * error message.
2405          */
2406         if (fragment_offset_spec == RTE_BE16(1) &&
2407             fragment_offset_last == RTE_BE16(RTE_IPV4_HDR_OFFSET_MASK))
2408                 return rte_flow_error_set(error, ENOTSUP,
2409                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2410                                           last, "match on last "
2411                                           "fragment not supported");
2412         /*
2413          * Match on fragment_offset spec 0x0001 and last 0x3fff
2414          * means MF and/or frag-offset is not 0.
2415          * This is a fragmented packet.
2416          * Other range values are invalid and rejected.
2417          */
2418         if (!(fragment_offset_spec == RTE_BE16(1) &&
2419               fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK)))
2420                 return rte_flow_error_set(error, ENOTSUP,
2421                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2422                                           "specified range not supported");
2423         return 0;
2424 }
2425
2426 /**
2427  * Validate IPV6 fragment extension item.
2428  *
2429  * @param[in] item
2430  *   Item specification.
2431  * @param[in] item_flags
2432  *   Bit-fields that holds the items detected until now.
2433  * @param[out] error
2434  *   Pointer to error structure.
2435  *
2436  * @return
2437  *   0 on success, a negative errno value otherwise and rte_errno is set.
2438  */
2439 static int
2440 flow_dv_validate_item_ipv6_frag_ext(const struct rte_flow_item *item,
2441                                     uint64_t item_flags,
2442                                     struct rte_flow_error *error)
2443 {
2444         const struct rte_flow_item_ipv6_frag_ext *spec = item->spec;
2445         const struct rte_flow_item_ipv6_frag_ext *last = item->last;
2446         const struct rte_flow_item_ipv6_frag_ext *mask = item->mask;
2447         rte_be16_t frag_data_spec = 0;
2448         rte_be16_t frag_data_last = 0;
2449         const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2450         const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 :
2451                                       MLX5_FLOW_LAYER_OUTER_L4;
2452         int ret = 0;
2453         struct rte_flow_item_ipv6_frag_ext nic_mask = {
2454                 .hdr = {
2455                         .next_header = 0xff,
2456                         .frag_data = RTE_BE16(0xffff),
2457                 },
2458         };
2459
2460         if (item_flags & l4m)
2461                 return rte_flow_error_set(error, EINVAL,
2462                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2463                                           "ipv6 fragment extension item cannot "
2464                                           "follow L4 item.");
2465         if ((tunnel && !(item_flags & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
2466             (!tunnel && !(item_flags & MLX5_FLOW_LAYER_OUTER_L3_IPV6)))
2467                 return rte_flow_error_set(error, EINVAL,
2468                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2469                                           "ipv6 fragment extension item must "
2470                                           "follow ipv6 item");
2471         if (spec && mask)
2472                 frag_data_spec = spec->hdr.frag_data & mask->hdr.frag_data;
2473         if (!frag_data_spec)
2474                 return 0;
2475         /*
2476          * spec and mask are valid, enforce using full mask to make sure the
2477          * complete value is used correctly.
2478          */
2479         if ((mask->hdr.frag_data & RTE_BE16(RTE_IPV6_FRAG_USED_MASK)) !=
2480                                 RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2481                 return rte_flow_error_set(error, EINVAL,
2482                                           RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2483                                           item, "must use full mask for"
2484                                           " frag_data");
2485         /*
2486          * Match on frag_data 0x00001 means M is 1 and frag-offset is 0.
2487          * This is 1st fragment of fragmented packet.
2488          */
2489         if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_MF_MASK))
2490                 return rte_flow_error_set(error, ENOTSUP,
2491                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2492                                           "match on first fragment not "
2493                                           "supported");
2494         if (frag_data_spec && !last)
2495                 return rte_flow_error_set(error, EINVAL,
2496                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2497                                           "specified value not supported");
2498         ret = mlx5_flow_item_acceptable
2499                                 (item, (const uint8_t *)mask,
2500                                  (const uint8_t *)&nic_mask,
2501                                  sizeof(struct rte_flow_item_ipv6_frag_ext),
2502                                  MLX5_ITEM_RANGE_ACCEPTED, error);
2503         if (ret)
2504                 return ret;
2505         /* spec and last are valid, validate the specified range. */
2506         frag_data_last = last->hdr.frag_data & mask->hdr.frag_data;
2507         /*
2508          * Match on frag_data spec 0x0009 and last 0xfff9
2509          * means M is 1 and frag-offset is > 0.
2510          * This packet is fragment 2nd and onward, excluding last.
2511          * This is not yet supported in MLX5, return appropriate
2512          * error message.
2513          */
2514         if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN |
2515                                        RTE_IPV6_EHDR_MF_MASK) &&
2516             frag_data_last == RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2517                 return rte_flow_error_set(error, ENOTSUP,
2518                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2519                                           last, "match on following "
2520                                           "fragments not supported");
2521         /*
2522          * Match on frag_data spec 0x0008 and last 0xfff8
2523          * means M is 0 and frag-offset is > 0.
2524          * This packet is last fragment of fragmented packet.
2525          * This is not yet supported in MLX5, return appropriate
2526          * error message.
2527          */
2528         if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN) &&
2529             frag_data_last == RTE_BE16(RTE_IPV6_EHDR_FO_MASK))
2530                 return rte_flow_error_set(error, ENOTSUP,
2531                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2532                                           last, "match on last "
2533                                           "fragment not supported");
2534         /* Other range values are invalid and rejected. */
2535         return rte_flow_error_set(error, EINVAL,
2536                                   RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2537                                   "specified range not supported");
2538 }
2539
2540 /**
2541  * Validate the pop VLAN action.
2542  *
2543  * @param[in] dev
2544  *   Pointer to the rte_eth_dev structure.
2545  * @param[in] action_flags
2546  *   Holds the actions detected until now.
2547  * @param[in] action
2548  *   Pointer to the pop vlan action.
2549  * @param[in] item_flags
2550  *   The items found in this flow rule.
2551  * @param[in] attr
2552  *   Pointer to flow attributes.
2553  * @param[out] error
2554  *   Pointer to error structure.
2555  *
2556  * @return
2557  *   0 on success, a negative errno value otherwise and rte_errno is set.
2558  */
2559 static int
2560 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
2561                                  uint64_t action_flags,
2562                                  const struct rte_flow_action *action,
2563                                  uint64_t item_flags,
2564                                  const struct rte_flow_attr *attr,
2565                                  struct rte_flow_error *error)
2566 {
2567         const struct mlx5_priv *priv = dev->data->dev_private;
2568
2569         (void)action;
2570         (void)attr;
2571         if (!priv->sh->pop_vlan_action)
2572                 return rte_flow_error_set(error, ENOTSUP,
2573                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2574                                           NULL,
2575                                           "pop vlan action is not supported");
2576         if (attr->egress)
2577                 return rte_flow_error_set(error, ENOTSUP,
2578                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2579                                           NULL,
2580                                           "pop vlan action not supported for "
2581                                           "egress");
2582         if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
2583                 return rte_flow_error_set(error, ENOTSUP,
2584                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2585                                           "no support for multiple VLAN "
2586                                           "actions");
2587         /* Pop VLAN with preceding Decap requires inner header with VLAN. */
2588         if ((action_flags & MLX5_FLOW_ACTION_DECAP) &&
2589             !(item_flags & MLX5_FLOW_LAYER_INNER_VLAN))
2590                 return rte_flow_error_set(error, ENOTSUP,
2591                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2592                                           NULL,
2593                                           "cannot pop vlan after decap without "
2594                                           "match on inner vlan in the flow");
2595         /* Pop VLAN without preceding Decap requires outer header with VLAN. */
2596         if (!(action_flags & MLX5_FLOW_ACTION_DECAP) &&
2597             !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2598                 return rte_flow_error_set(error, ENOTSUP,
2599                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2600                                           NULL,
2601                                           "cannot pop vlan without a "
2602                                           "match on (outer) vlan in the flow");
2603         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2604                 return rte_flow_error_set(error, EINVAL,
2605                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2606                                           "wrong action order, port_id should "
2607                                           "be after pop VLAN action");
2608         if (!attr->transfer && priv->representor)
2609                 return rte_flow_error_set(error, ENOTSUP,
2610                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2611                                           "pop vlan action for VF representor "
2612                                           "not supported on NIC table");
2613         return 0;
2614 }
2615
2616 /**
2617  * Get VLAN default info from vlan match info.
2618  *
2619  * @param[in] items
2620  *   the list of item specifications.
2621  * @param[out] vlan
2622  *   pointer VLAN info to fill to.
2623  *
2624  * @return
2625  *   0 on success, a negative errno value otherwise and rte_errno is set.
2626  */
2627 static void
2628 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
2629                                   struct rte_vlan_hdr *vlan)
2630 {
2631         const struct rte_flow_item_vlan nic_mask = {
2632                 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
2633                                 MLX5DV_FLOW_VLAN_VID_MASK),
2634                 .inner_type = RTE_BE16(0xffff),
2635         };
2636
2637         if (items == NULL)
2638                 return;
2639         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2640                 int type = items->type;
2641
2642                 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
2643                     type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
2644                         break;
2645         }
2646         if (items->type != RTE_FLOW_ITEM_TYPE_END) {
2647                 const struct rte_flow_item_vlan *vlan_m = items->mask;
2648                 const struct rte_flow_item_vlan *vlan_v = items->spec;
2649
2650                 /* If VLAN item in pattern doesn't contain data, return here. */
2651                 if (!vlan_v)
2652                         return;
2653                 if (!vlan_m)
2654                         vlan_m = &nic_mask;
2655                 /* Only full match values are accepted */
2656                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
2657                      MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
2658                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
2659                         vlan->vlan_tci |=
2660                                 rte_be_to_cpu_16(vlan_v->tci &
2661                                                  MLX5DV_FLOW_VLAN_PCP_MASK_BE);
2662                 }
2663                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
2664                      MLX5DV_FLOW_VLAN_VID_MASK_BE) {
2665                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
2666                         vlan->vlan_tci |=
2667                                 rte_be_to_cpu_16(vlan_v->tci &
2668                                                  MLX5DV_FLOW_VLAN_VID_MASK_BE);
2669                 }
2670                 if (vlan_m->inner_type == nic_mask.inner_type)
2671                         vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
2672                                                            vlan_m->inner_type);
2673         }
2674 }
2675
2676 /**
2677  * Validate the push VLAN action.
2678  *
2679  * @param[in] dev
2680  *   Pointer to the rte_eth_dev structure.
2681  * @param[in] action_flags
2682  *   Holds the actions detected until now.
2683  * @param[in] item_flags
2684  *   The items found in this flow rule.
2685  * @param[in] action
2686  *   Pointer to the action structure.
2687  * @param[in] attr
2688  *   Pointer to flow attributes
2689  * @param[out] error
2690  *   Pointer to error structure.
2691  *
2692  * @return
2693  *   0 on success, a negative errno value otherwise and rte_errno is set.
2694  */
2695 static int
2696 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
2697                                   uint64_t action_flags,
2698                                   const struct rte_flow_item_vlan *vlan_m,
2699                                   const struct rte_flow_action *action,
2700                                   const struct rte_flow_attr *attr,
2701                                   struct rte_flow_error *error)
2702 {
2703         const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
2704         const struct mlx5_priv *priv = dev->data->dev_private;
2705
2706         if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
2707             push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
2708                 return rte_flow_error_set(error, EINVAL,
2709                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2710                                           "invalid vlan ethertype");
2711         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2712                 return rte_flow_error_set(error, EINVAL,
2713                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2714                                           "wrong action order, port_id should "
2715                                           "be after push VLAN");
2716         if (!attr->transfer && priv->representor)
2717                 return rte_flow_error_set(error, ENOTSUP,
2718                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2719                                           "push vlan action for VF representor "
2720                                           "not supported on NIC table");
2721         if (vlan_m &&
2722             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
2723             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
2724                 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
2725             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
2726             !(mlx5_flow_find_action
2727                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
2728                 return rte_flow_error_set(error, EINVAL,
2729                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2730                                           "not full match mask on VLAN PCP and "
2731                                           "there is no of_set_vlan_pcp action, "
2732                                           "push VLAN action cannot figure out "
2733                                           "PCP value");
2734         if (vlan_m &&
2735             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
2736             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
2737                 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
2738             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
2739             !(mlx5_flow_find_action
2740                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
2741                 return rte_flow_error_set(error, EINVAL,
2742                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2743                                           "not full match mask on VLAN VID and "
2744                                           "there is no of_set_vlan_vid action, "
2745                                           "push VLAN action cannot figure out "
2746                                           "VID value");
2747         (void)attr;
2748         return 0;
2749 }
2750
2751 /**
2752  * Validate the set VLAN PCP.
2753  *
2754  * @param[in] action_flags
2755  *   Holds the actions detected until now.
2756  * @param[in] actions
2757  *   Pointer to the list of actions remaining in the flow rule.
2758  * @param[out] error
2759  *   Pointer to error structure.
2760  *
2761  * @return
2762  *   0 on success, a negative errno value otherwise and rte_errno is set.
2763  */
2764 static int
2765 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
2766                                      const struct rte_flow_action actions[],
2767                                      struct rte_flow_error *error)
2768 {
2769         const struct rte_flow_action *action = actions;
2770         const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
2771
2772         if (conf->vlan_pcp > 7)
2773                 return rte_flow_error_set(error, EINVAL,
2774                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2775                                           "VLAN PCP value is too big");
2776         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
2777                 return rte_flow_error_set(error, ENOTSUP,
2778                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2779                                           "set VLAN PCP action must follow "
2780                                           "the push VLAN action");
2781         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
2782                 return rte_flow_error_set(error, ENOTSUP,
2783                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2784                                           "Multiple VLAN PCP modification are "
2785                                           "not supported");
2786         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2787                 return rte_flow_error_set(error, EINVAL,
2788                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2789                                           "wrong action order, port_id should "
2790                                           "be after set VLAN PCP");
2791         return 0;
2792 }
2793
2794 /**
2795  * Validate the set VLAN VID.
2796  *
2797  * @param[in] item_flags
2798  *   Holds the items detected in this rule.
2799  * @param[in] action_flags
2800  *   Holds the actions detected until now.
2801  * @param[in] actions
2802  *   Pointer to the list of actions remaining in the flow rule.
2803  * @param[out] error
2804  *   Pointer to error structure.
2805  *
2806  * @return
2807  *   0 on success, a negative errno value otherwise and rte_errno is set.
2808  */
2809 static int
2810 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
2811                                      uint64_t action_flags,
2812                                      const struct rte_flow_action actions[],
2813                                      struct rte_flow_error *error)
2814 {
2815         const struct rte_flow_action *action = actions;
2816         const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
2817
2818         if (rte_be_to_cpu_16(conf->vlan_vid) > 0xFFE)
2819                 return rte_flow_error_set(error, EINVAL,
2820                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2821                                           "VLAN VID value is too big");
2822         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
2823             !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2824                 return rte_flow_error_set(error, ENOTSUP,
2825                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2826                                           "set VLAN VID action must follow push"
2827                                           " VLAN action or match on VLAN item");
2828         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
2829                 return rte_flow_error_set(error, ENOTSUP,
2830                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2831                                           "Multiple VLAN VID modifications are "
2832                                           "not supported");
2833         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2834                 return rte_flow_error_set(error, EINVAL,
2835                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2836                                           "wrong action order, port_id should "
2837                                           "be after set VLAN VID");
2838         return 0;
2839 }
2840
2841 /*
2842  * Validate the FLAG action.
2843  *
2844  * @param[in] dev
2845  *   Pointer to the rte_eth_dev structure.
2846  * @param[in] action_flags
2847  *   Holds the actions detected until now.
2848  * @param[in] attr
2849  *   Pointer to flow attributes
2850  * @param[out] error
2851  *   Pointer to error structure.
2852  *
2853  * @return
2854  *   0 on success, a negative errno value otherwise and rte_errno is set.
2855  */
2856 static int
2857 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
2858                              uint64_t action_flags,
2859                              const struct rte_flow_attr *attr,
2860                              struct rte_flow_error *error)
2861 {
2862         struct mlx5_priv *priv = dev->data->dev_private;
2863         struct mlx5_dev_config *config = &priv->config;
2864         int ret;
2865
2866         /* Fall back if no extended metadata register support. */
2867         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2868                 return mlx5_flow_validate_action_flag(action_flags, attr,
2869                                                       error);
2870         /* Extensive metadata mode requires registers. */
2871         if (!mlx5_flow_ext_mreg_supported(dev))
2872                 return rte_flow_error_set(error, ENOTSUP,
2873                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2874                                           "no metadata registers "
2875                                           "to support flag action");
2876         if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
2877                 return rte_flow_error_set(error, ENOTSUP,
2878                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2879                                           "extended metadata register"
2880                                           " isn't available");
2881         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2882         if (ret < 0)
2883                 return ret;
2884         MLX5_ASSERT(ret > 0);
2885         if (action_flags & MLX5_FLOW_ACTION_MARK)
2886                 return rte_flow_error_set(error, EINVAL,
2887                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2888                                           "can't mark and flag in same flow");
2889         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2890                 return rte_flow_error_set(error, EINVAL,
2891                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2892                                           "can't have 2 flag"
2893                                           " actions in same flow");
2894         return 0;
2895 }
2896
2897 /**
2898  * Validate MARK action.
2899  *
2900  * @param[in] dev
2901  *   Pointer to the rte_eth_dev structure.
2902  * @param[in] action
2903  *   Pointer to action.
2904  * @param[in] action_flags
2905  *   Holds the actions detected until now.
2906  * @param[in] attr
2907  *   Pointer to flow attributes
2908  * @param[out] error
2909  *   Pointer to error structure.
2910  *
2911  * @return
2912  *   0 on success, a negative errno value otherwise and rte_errno is set.
2913  */
2914 static int
2915 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
2916                              const struct rte_flow_action *action,
2917                              uint64_t action_flags,
2918                              const struct rte_flow_attr *attr,
2919                              struct rte_flow_error *error)
2920 {
2921         struct mlx5_priv *priv = dev->data->dev_private;
2922         struct mlx5_dev_config *config = &priv->config;
2923         const struct rte_flow_action_mark *mark = action->conf;
2924         int ret;
2925
2926         if (is_tunnel_offload_active(dev))
2927                 return rte_flow_error_set(error, ENOTSUP,
2928                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2929                                           "no mark action "
2930                                           "if tunnel offload active");
2931         /* Fall back if no extended metadata register support. */
2932         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2933                 return mlx5_flow_validate_action_mark(action, action_flags,
2934                                                       attr, error);
2935         /* Extensive metadata mode requires registers. */
2936         if (!mlx5_flow_ext_mreg_supported(dev))
2937                 return rte_flow_error_set(error, ENOTSUP,
2938                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2939                                           "no metadata registers "
2940                                           "to support mark action");
2941         if (!priv->sh->dv_mark_mask)
2942                 return rte_flow_error_set(error, ENOTSUP,
2943                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2944                                           "extended metadata register"
2945                                           " isn't available");
2946         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2947         if (ret < 0)
2948                 return ret;
2949         MLX5_ASSERT(ret > 0);
2950         if (!mark)
2951                 return rte_flow_error_set(error, EINVAL,
2952                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2953                                           "configuration cannot be null");
2954         if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
2955                 return rte_flow_error_set(error, EINVAL,
2956                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2957                                           &mark->id,
2958                                           "mark id exceeds the limit");
2959         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2960                 return rte_flow_error_set(error, EINVAL,
2961                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2962                                           "can't flag and mark in same flow");
2963         if (action_flags & MLX5_FLOW_ACTION_MARK)
2964                 return rte_flow_error_set(error, EINVAL,
2965                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2966                                           "can't have 2 mark actions in same"
2967                                           " flow");
2968         return 0;
2969 }
2970
2971 /**
2972  * Validate SET_META action.
2973  *
2974  * @param[in] dev
2975  *   Pointer to the rte_eth_dev structure.
2976  * @param[in] action
2977  *   Pointer to the action structure.
2978  * @param[in] action_flags
2979  *   Holds the actions detected until now.
2980  * @param[in] attr
2981  *   Pointer to flow attributes
2982  * @param[out] error
2983  *   Pointer to error structure.
2984  *
2985  * @return
2986  *   0 on success, a negative errno value otherwise and rte_errno is set.
2987  */
2988 static int
2989 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
2990                                  const struct rte_flow_action *action,
2991                                  uint64_t action_flags __rte_unused,
2992                                  const struct rte_flow_attr *attr,
2993                                  struct rte_flow_error *error)
2994 {
2995         const struct rte_flow_action_set_meta *conf;
2996         uint32_t nic_mask = UINT32_MAX;
2997         int reg;
2998
2999         if (!mlx5_flow_ext_mreg_supported(dev))
3000                 return rte_flow_error_set(error, ENOTSUP,
3001                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3002                                           "extended metadata register"
3003                                           " isn't supported");
3004         reg = flow_dv_get_metadata_reg(dev, attr, error);
3005         if (reg < 0)
3006                 return reg;
3007         if (reg == REG_NON)
3008                 return rte_flow_error_set(error, ENOTSUP,
3009                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3010                                           "unavalable extended metadata register");
3011         if (reg != REG_A && reg != REG_B) {
3012                 struct mlx5_priv *priv = dev->data->dev_private;
3013
3014                 nic_mask = priv->sh->dv_meta_mask;
3015         }
3016         if (!(action->conf))
3017                 return rte_flow_error_set(error, EINVAL,
3018                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3019                                           "configuration cannot be null");
3020         conf = (const struct rte_flow_action_set_meta *)action->conf;
3021         if (!conf->mask)
3022                 return rte_flow_error_set(error, EINVAL,
3023                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3024                                           "zero mask doesn't have any effect");
3025         if (conf->mask & ~nic_mask)
3026                 return rte_flow_error_set(error, EINVAL,
3027                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3028                                           "meta data must be within reg C0");
3029         return 0;
3030 }
3031
3032 /**
3033  * Validate SET_TAG action.
3034  *
3035  * @param[in] dev
3036  *   Pointer to the rte_eth_dev structure.
3037  * @param[in] action
3038  *   Pointer to the action structure.
3039  * @param[in] action_flags
3040  *   Holds the actions detected until now.
3041  * @param[in] attr
3042  *   Pointer to flow attributes
3043  * @param[out] error
3044  *   Pointer to error structure.
3045  *
3046  * @return
3047  *   0 on success, a negative errno value otherwise and rte_errno is set.
3048  */
3049 static int
3050 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
3051                                 const struct rte_flow_action *action,
3052                                 uint64_t action_flags,
3053                                 const struct rte_flow_attr *attr,
3054                                 struct rte_flow_error *error)
3055 {
3056         const struct rte_flow_action_set_tag *conf;
3057         const uint64_t terminal_action_flags =
3058                 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
3059                 MLX5_FLOW_ACTION_RSS;
3060         int ret;
3061
3062         if (!mlx5_flow_ext_mreg_supported(dev))
3063                 return rte_flow_error_set(error, ENOTSUP,
3064                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3065                                           "extensive metadata register"
3066                                           " isn't supported");
3067         if (!(action->conf))
3068                 return rte_flow_error_set(error, EINVAL,
3069                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3070                                           "configuration cannot be null");
3071         conf = (const struct rte_flow_action_set_tag *)action->conf;
3072         if (!conf->mask)
3073                 return rte_flow_error_set(error, EINVAL,
3074                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3075                                           "zero mask doesn't have any effect");
3076         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
3077         if (ret < 0)
3078                 return ret;
3079         if (!attr->transfer && attr->ingress &&
3080             (action_flags & terminal_action_flags))
3081                 return rte_flow_error_set(error, EINVAL,
3082                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3083                                           "set_tag has no effect"
3084                                           " with terminal actions");
3085         return 0;
3086 }
3087
3088 /**
3089  * Validate count action.
3090  *
3091  * @param[in] dev
3092  *   Pointer to rte_eth_dev structure.
3093  * @param[in] action
3094  *   Pointer to the action structure.
3095  * @param[in] action_flags
3096  *   Holds the actions detected until now.
3097  * @param[out] error
3098  *   Pointer to error structure.
3099  *
3100  * @return
3101  *   0 on success, a negative errno value otherwise and rte_errno is set.
3102  */
3103 static int
3104 flow_dv_validate_action_count(struct rte_eth_dev *dev,
3105                               const struct rte_flow_action *action,
3106                               uint64_t action_flags,
3107                               struct rte_flow_error *error)
3108 {
3109         struct mlx5_priv *priv = dev->data->dev_private;
3110         const struct rte_flow_action_count *count;
3111
3112         if (!priv->config.devx)
3113                 goto notsup_err;
3114         if (action_flags & MLX5_FLOW_ACTION_COUNT)
3115                 return rte_flow_error_set(error, EINVAL,
3116                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3117                                           "duplicate count actions set");
3118         count = (const struct rte_flow_action_count *)action->conf;
3119         if (count && count->shared && (action_flags & MLX5_FLOW_ACTION_AGE) &&
3120             !priv->sh->flow_hit_aso_en)
3121                 return rte_flow_error_set(error, EINVAL,
3122                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3123                                           "old age and shared count combination is not supported");
3124 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
3125         return 0;
3126 #endif
3127 notsup_err:
3128         return rte_flow_error_set
3129                       (error, ENOTSUP,
3130                        RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3131                        NULL,
3132                        "count action not supported");
3133 }
3134
3135 /**
3136  * Validate the L2 encap action.
3137  *
3138  * @param[in] dev
3139  *   Pointer to the rte_eth_dev structure.
3140  * @param[in] action_flags
3141  *   Holds the actions detected until now.
3142  * @param[in] action
3143  *   Pointer to the action structure.
3144  * @param[in] attr
3145  *   Pointer to flow attributes.
3146  * @param[out] error
3147  *   Pointer to error structure.
3148  *
3149  * @return
3150  *   0 on success, a negative errno value otherwise and rte_errno is set.
3151  */
3152 static int
3153 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
3154                                  uint64_t action_flags,
3155                                  const struct rte_flow_action *action,
3156                                  const struct rte_flow_attr *attr,
3157                                  struct rte_flow_error *error)
3158 {
3159         const struct mlx5_priv *priv = dev->data->dev_private;
3160
3161         if (!(action->conf))
3162                 return rte_flow_error_set(error, EINVAL,
3163                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3164                                           "configuration cannot be null");
3165         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3166                 return rte_flow_error_set(error, EINVAL,
3167                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3168                                           "can only have a single encap action "
3169                                           "in a flow");
3170         if (!attr->transfer && priv->representor)
3171                 return rte_flow_error_set(error, ENOTSUP,
3172                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3173                                           "encap action for VF representor "
3174                                           "not supported on NIC table");
3175         return 0;
3176 }
3177
3178 /**
3179  * Validate a decap action.
3180  *
3181  * @param[in] dev
3182  *   Pointer to the rte_eth_dev structure.
3183  * @param[in] action_flags
3184  *   Holds the actions detected until now.
3185  * @param[in] action
3186  *   Pointer to the action structure.
3187  * @param[in] item_flags
3188  *   Holds the items detected.
3189  * @param[in] attr
3190  *   Pointer to flow attributes
3191  * @param[out] error
3192  *   Pointer to error structure.
3193  *
3194  * @return
3195  *   0 on success, a negative errno value otherwise and rte_errno is set.
3196  */
3197 static int
3198 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
3199                               uint64_t action_flags,
3200                               const struct rte_flow_action *action,
3201                               const uint64_t item_flags,
3202                               const struct rte_flow_attr *attr,
3203                               struct rte_flow_error *error)
3204 {
3205         const struct mlx5_priv *priv = dev->data->dev_private;
3206
3207         if (priv->config.hca_attr.scatter_fcs_w_decap_disable &&
3208             !priv->config.decap_en)
3209                 return rte_flow_error_set(error, ENOTSUP,
3210                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3211                                           "decap is not enabled");
3212         if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
3213                 return rte_flow_error_set(error, ENOTSUP,
3214                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3215                                           action_flags &
3216                                           MLX5_FLOW_ACTION_DECAP ? "can only "
3217                                           "have a single decap action" : "decap "
3218                                           "after encap is not supported");
3219         if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
3220                 return rte_flow_error_set(error, EINVAL,
3221                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3222                                           "can't have decap action after"
3223                                           " modify action");
3224         if (attr->egress)
3225                 return rte_flow_error_set(error, ENOTSUP,
3226                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
3227                                           NULL,
3228                                           "decap action not supported for "
3229                                           "egress");
3230         if (!attr->transfer && priv->representor)
3231                 return rte_flow_error_set(error, ENOTSUP,
3232                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3233                                           "decap action for VF representor "
3234                                           "not supported on NIC table");
3235         if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_DECAP &&
3236             !(item_flags & MLX5_FLOW_LAYER_VXLAN))
3237                 return rte_flow_error_set(error, ENOTSUP,
3238                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3239                                 "VXLAN item should be present for VXLAN decap");
3240         return 0;
3241 }
3242
3243 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
3244
3245 /**
3246  * Validate the raw encap and decap actions.
3247  *
3248  * @param[in] dev
3249  *   Pointer to the rte_eth_dev structure.
3250  * @param[in] decap
3251  *   Pointer to the decap action.
3252  * @param[in] encap
3253  *   Pointer to the encap action.
3254  * @param[in] attr
3255  *   Pointer to flow attributes
3256  * @param[in/out] action_flags
3257  *   Holds the actions detected until now.
3258  * @param[out] actions_n
3259  *   pointer to the number of actions counter.
3260  * @param[in] action
3261  *   Pointer to the action structure.
3262  * @param[in] item_flags
3263  *   Holds the items detected.
3264  * @param[out] error
3265  *   Pointer to error structure.
3266  *
3267  * @return
3268  *   0 on success, a negative errno value otherwise and rte_errno is set.
3269  */
3270 static int
3271 flow_dv_validate_action_raw_encap_decap
3272         (struct rte_eth_dev *dev,
3273          const struct rte_flow_action_raw_decap *decap,
3274          const struct rte_flow_action_raw_encap *encap,
3275          const struct rte_flow_attr *attr, uint64_t *action_flags,
3276          int *actions_n, const struct rte_flow_action *action,
3277          uint64_t item_flags, struct rte_flow_error *error)
3278 {
3279         const struct mlx5_priv *priv = dev->data->dev_private;
3280         int ret;
3281
3282         if (encap && (!encap->size || !encap->data))
3283                 return rte_flow_error_set(error, EINVAL,
3284                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3285                                           "raw encap data cannot be empty");
3286         if (decap && encap) {
3287                 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
3288                     encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
3289                         /* L3 encap. */
3290                         decap = NULL;
3291                 else if (encap->size <=
3292                            MLX5_ENCAPSULATION_DECISION_SIZE &&
3293                            decap->size >
3294                            MLX5_ENCAPSULATION_DECISION_SIZE)
3295                         /* L3 decap. */
3296                         encap = NULL;
3297                 else if (encap->size >
3298                            MLX5_ENCAPSULATION_DECISION_SIZE &&
3299                            decap->size >
3300                            MLX5_ENCAPSULATION_DECISION_SIZE)
3301                         /* 2 L2 actions: encap and decap. */
3302                         ;
3303                 else
3304                         return rte_flow_error_set(error,
3305                                 ENOTSUP,
3306                                 RTE_FLOW_ERROR_TYPE_ACTION,
3307                                 NULL, "unsupported too small "
3308                                 "raw decap and too small raw "
3309                                 "encap combination");
3310         }
3311         if (decap) {
3312                 ret = flow_dv_validate_action_decap(dev, *action_flags, action,
3313                                                     item_flags, attr, error);
3314                 if (ret < 0)
3315                         return ret;
3316                 *action_flags |= MLX5_FLOW_ACTION_DECAP;
3317                 ++(*actions_n);
3318         }
3319         if (encap) {
3320                 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
3321                         return rte_flow_error_set(error, ENOTSUP,
3322                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3323                                                   NULL,
3324                                                   "small raw encap size");
3325                 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
3326                         return rte_flow_error_set(error, EINVAL,
3327                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3328                                                   NULL,
3329                                                   "more than one encap action");
3330                 if (!attr->transfer && priv->representor)
3331                         return rte_flow_error_set
3332                                         (error, ENOTSUP,
3333                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3334                                          "encap action for VF representor "
3335                                          "not supported on NIC table");
3336                 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
3337                 ++(*actions_n);
3338         }
3339         return 0;
3340 }
3341
3342 /**
3343  * Match encap_decap resource.
3344  *
3345  * @param list
3346  *   Pointer to the hash list.
3347  * @param entry
3348  *   Pointer to exist resource entry object.
3349  * @param key
3350  *   Key of the new entry.
3351  * @param ctx_cb
3352  *   Pointer to new encap_decap resource.
3353  *
3354  * @return
3355  *   0 on matching, none-zero otherwise.
3356  */
3357 int
3358 flow_dv_encap_decap_match_cb(struct mlx5_hlist *list __rte_unused,
3359                              struct mlx5_hlist_entry *entry,
3360                              uint64_t key __rte_unused, void *cb_ctx)
3361 {
3362         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3363         struct mlx5_flow_dv_encap_decap_resource *resource = ctx->data;
3364         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
3365
3366         cache_resource = container_of(entry,
3367                                       struct mlx5_flow_dv_encap_decap_resource,
3368                                       entry);
3369         if (resource->reformat_type == cache_resource->reformat_type &&
3370             resource->ft_type == cache_resource->ft_type &&
3371             resource->flags == cache_resource->flags &&
3372             resource->size == cache_resource->size &&
3373             !memcmp((const void *)resource->buf,
3374                     (const void *)cache_resource->buf,
3375                     resource->size))
3376                 return 0;
3377         return -1;
3378 }
3379
3380 /**
3381  * Allocate encap_decap resource.
3382  *
3383  * @param list
3384  *   Pointer to the hash list.
3385  * @param entry
3386  *   Pointer to exist resource entry object.
3387  * @param ctx_cb
3388  *   Pointer to new encap_decap resource.
3389  *
3390  * @return
3391  *   0 on matching, none-zero otherwise.
3392  */
3393 struct mlx5_hlist_entry *
3394 flow_dv_encap_decap_create_cb(struct mlx5_hlist *list,
3395                               uint64_t key __rte_unused,
3396                               void *cb_ctx)
3397 {
3398         struct mlx5_dev_ctx_shared *sh = list->ctx;
3399         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3400         struct mlx5dv_dr_domain *domain;
3401         struct mlx5_flow_dv_encap_decap_resource *resource = ctx->data;
3402         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
3403         uint32_t idx;
3404         int ret;
3405
3406         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3407                 domain = sh->fdb_domain;
3408         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3409                 domain = sh->rx_domain;
3410         else
3411                 domain = sh->tx_domain;
3412         /* Register new encap/decap resource. */
3413         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
3414                                        &idx);
3415         if (!cache_resource) {
3416                 rte_flow_error_set(ctx->error, ENOMEM,
3417                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3418                                    "cannot allocate resource memory");
3419                 return NULL;
3420         }
3421         *cache_resource = *resource;
3422         cache_resource->idx = idx;
3423         ret = mlx5_flow_os_create_flow_action_packet_reformat
3424                                         (sh->ctx, domain, cache_resource,
3425                                          &cache_resource->action);
3426         if (ret) {
3427                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);
3428                 rte_flow_error_set(ctx->error, ENOMEM,
3429                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3430                                    NULL, "cannot create action");
3431                 return NULL;
3432         }
3433
3434         return &cache_resource->entry;
3435 }
3436
3437 /**
3438  * Find existing encap/decap resource or create and register a new one.
3439  *
3440  * @param[in, out] dev
3441  *   Pointer to rte_eth_dev structure.
3442  * @param[in, out] resource
3443  *   Pointer to encap/decap resource.
3444  * @parm[in, out] dev_flow
3445  *   Pointer to the dev_flow.
3446  * @param[out] error
3447  *   pointer to error structure.
3448  *
3449  * @return
3450  *   0 on success otherwise -errno and errno is set.
3451  */
3452 static int
3453 flow_dv_encap_decap_resource_register
3454                         (struct rte_eth_dev *dev,
3455                          struct mlx5_flow_dv_encap_decap_resource *resource,
3456                          struct mlx5_flow *dev_flow,
3457                          struct rte_flow_error *error)
3458 {
3459         struct mlx5_priv *priv = dev->data->dev_private;
3460         struct mlx5_dev_ctx_shared *sh = priv->sh;
3461         struct mlx5_hlist_entry *entry;
3462         union {
3463                 struct {
3464                         uint32_t ft_type:8;
3465                         uint32_t refmt_type:8;
3466                         /*
3467                          * Header reformat actions can be shared between
3468                          * non-root tables. One bit to indicate non-root
3469                          * table or not.
3470                          */
3471                         uint32_t is_root:1;
3472                         uint32_t reserve:15;
3473                 };
3474                 uint32_t v32;
3475         } encap_decap_key = {
3476                 {
3477                         .ft_type = resource->ft_type,
3478                         .refmt_type = resource->reformat_type,
3479                         .is_root = !!dev_flow->dv.group,
3480                         .reserve = 0,
3481                 }
3482         };
3483         struct mlx5_flow_cb_ctx ctx = {
3484                 .error = error,
3485                 .data = resource,
3486         };
3487         uint64_t key64;
3488
3489         resource->flags = dev_flow->dv.group ? 0 : 1;
3490         key64 =  __rte_raw_cksum(&encap_decap_key.v32,
3491                                  sizeof(encap_decap_key.v32), 0);
3492         if (resource->reformat_type !=
3493             MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2 &&
3494             resource->size)
3495                 key64 = __rte_raw_cksum(resource->buf, resource->size, key64);
3496         entry = mlx5_hlist_register(sh->encaps_decaps, key64, &ctx);
3497         if (!entry)
3498                 return -rte_errno;
3499         resource = container_of(entry, typeof(*resource), entry);
3500         dev_flow->dv.encap_decap = resource;
3501         dev_flow->handle->dvh.rix_encap_decap = resource->idx;
3502         return 0;
3503 }
3504
3505 /**
3506  * Find existing table jump resource or create and register a new one.
3507  *
3508  * @param[in, out] dev
3509  *   Pointer to rte_eth_dev structure.
3510  * @param[in, out] tbl
3511  *   Pointer to flow table resource.
3512  * @parm[in, out] dev_flow
3513  *   Pointer to the dev_flow.
3514  * @param[out] error
3515  *   pointer to error structure.
3516  *
3517  * @return
3518  *   0 on success otherwise -errno and errno is set.
3519  */
3520 static int
3521 flow_dv_jump_tbl_resource_register
3522                         (struct rte_eth_dev *dev __rte_unused,
3523                          struct mlx5_flow_tbl_resource *tbl,
3524                          struct mlx5_flow *dev_flow,
3525                          struct rte_flow_error *error __rte_unused)
3526 {
3527         struct mlx5_flow_tbl_data_entry *tbl_data =
3528                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
3529
3530         MLX5_ASSERT(tbl);
3531         MLX5_ASSERT(tbl_data->jump.action);
3532         dev_flow->handle->rix_jump = tbl_data->idx;
3533         dev_flow->dv.jump = &tbl_data->jump;
3534         return 0;
3535 }
3536
3537 int
3538 flow_dv_port_id_match_cb(struct mlx5_cache_list *list __rte_unused,
3539                          struct mlx5_cache_entry *entry, void *cb_ctx)
3540 {
3541         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3542         struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3543         struct mlx5_flow_dv_port_id_action_resource *res =
3544                         container_of(entry, typeof(*res), entry);
3545
3546         return ref->port_id != res->port_id;
3547 }
3548
3549 struct mlx5_cache_entry *
3550 flow_dv_port_id_create_cb(struct mlx5_cache_list *list,
3551                           struct mlx5_cache_entry *entry __rte_unused,
3552                           void *cb_ctx)
3553 {
3554         struct mlx5_dev_ctx_shared *sh = list->ctx;
3555         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3556         struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3557         struct mlx5_flow_dv_port_id_action_resource *cache;
3558         uint32_t idx;
3559         int ret;
3560
3561         /* Register new port id action resource. */
3562         cache = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID], &idx);
3563         if (!cache) {
3564                 rte_flow_error_set(ctx->error, ENOMEM,
3565                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3566                                    "cannot allocate port_id action cache memory");
3567                 return NULL;
3568         }
3569         *cache = *ref;
3570         ret = mlx5_flow_os_create_flow_action_dest_port(sh->fdb_domain,
3571                                                         ref->port_id,
3572                                                         &cache->action);
3573         if (ret) {
3574                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], idx);
3575                 rte_flow_error_set(ctx->error, ENOMEM,
3576                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3577                                    "cannot create action");
3578                 return NULL;
3579         }
3580         cache->idx = idx;
3581         return &cache->entry;
3582 }
3583
3584 /**
3585  * Find existing table port ID resource or create and register a new one.
3586  *
3587  * @param[in, out] dev
3588  *   Pointer to rte_eth_dev structure.
3589  * @param[in, out] resource
3590  *   Pointer to port ID action resource.
3591  * @parm[in, out] dev_flow
3592  *   Pointer to the dev_flow.
3593  * @param[out] error
3594  *   pointer to error structure.
3595  *
3596  * @return
3597  *   0 on success otherwise -errno and errno is set.
3598  */
3599 static int
3600 flow_dv_port_id_action_resource_register
3601                         (struct rte_eth_dev *dev,
3602                          struct mlx5_flow_dv_port_id_action_resource *resource,
3603                          struct mlx5_flow *dev_flow,
3604                          struct rte_flow_error *error)
3605 {
3606         struct mlx5_priv *priv = dev->data->dev_private;
3607         struct mlx5_cache_entry *entry;
3608         struct mlx5_flow_dv_port_id_action_resource *cache;
3609         struct mlx5_flow_cb_ctx ctx = {
3610                 .error = error,
3611                 .data = resource,
3612         };
3613
3614         entry = mlx5_cache_register(&priv->sh->port_id_action_list, &ctx);
3615         if (!entry)
3616                 return -rte_errno;
3617         cache = container_of(entry, typeof(*cache), entry);
3618         dev_flow->dv.port_id_action = cache;
3619         dev_flow->handle->rix_port_id_action = cache->idx;
3620         return 0;
3621 }
3622
3623 int
3624 flow_dv_push_vlan_match_cb(struct mlx5_cache_list *list __rte_unused,
3625                          struct mlx5_cache_entry *entry, void *cb_ctx)
3626 {
3627         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3628         struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3629         struct mlx5_flow_dv_push_vlan_action_resource *res =
3630                         container_of(entry, typeof(*res), entry);
3631
3632         return ref->vlan_tag != res->vlan_tag || ref->ft_type != res->ft_type;
3633 }
3634
3635 struct mlx5_cache_entry *
3636 flow_dv_push_vlan_create_cb(struct mlx5_cache_list *list,
3637                           struct mlx5_cache_entry *entry __rte_unused,
3638                           void *cb_ctx)
3639 {
3640         struct mlx5_dev_ctx_shared *sh = list->ctx;
3641         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3642         struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3643         struct mlx5_flow_dv_push_vlan_action_resource *cache;
3644         struct mlx5dv_dr_domain *domain;
3645         uint32_t idx;
3646         int ret;
3647
3648         /* Register new port id action resource. */
3649         cache = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN], &idx);
3650         if (!cache) {
3651                 rte_flow_error_set(ctx->error, ENOMEM,
3652                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3653                                    "cannot allocate push_vlan action cache memory");
3654                 return NULL;
3655         }
3656         *cache = *ref;
3657         if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3658                 domain = sh->fdb_domain;
3659         else if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3660                 domain = sh->rx_domain;
3661         else
3662                 domain = sh->tx_domain;
3663         ret = mlx5_flow_os_create_flow_action_push_vlan(domain, ref->vlan_tag,
3664                                                         &cache->action);
3665         if (ret) {
3666                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
3667                 rte_flow_error_set(ctx->error, ENOMEM,
3668                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3669                                    "cannot create push vlan action");
3670                 return NULL;
3671         }
3672         cache->idx = idx;
3673         return &cache->entry;
3674 }
3675
3676 /**
3677  * Find existing push vlan resource or create and register a new one.
3678  *
3679  * @param [in, out] dev
3680  *   Pointer to rte_eth_dev structure.
3681  * @param[in, out] resource
3682  *   Pointer to port ID action resource.
3683  * @parm[in, out] dev_flow
3684  *   Pointer to the dev_flow.
3685  * @param[out] error
3686  *   pointer to error structure.
3687  *
3688  * @return
3689  *   0 on success otherwise -errno and errno is set.
3690  */
3691 static int
3692 flow_dv_push_vlan_action_resource_register
3693                        (struct rte_eth_dev *dev,
3694                         struct mlx5_flow_dv_push_vlan_action_resource *resource,
3695                         struct mlx5_flow *dev_flow,
3696                         struct rte_flow_error *error)
3697 {
3698         struct mlx5_priv *priv = dev->data->dev_private;
3699         struct mlx5_flow_dv_push_vlan_action_resource *cache;
3700         struct mlx5_cache_entry *entry;
3701         struct mlx5_flow_cb_ctx ctx = {
3702                 .error = error,
3703                 .data = resource,
3704         };
3705
3706         entry = mlx5_cache_register(&priv->sh->push_vlan_action_list, &ctx);
3707         if (!entry)
3708                 return -rte_errno;
3709         cache = container_of(entry, typeof(*cache), entry);
3710
3711         dev_flow->handle->dvh.rix_push_vlan = cache->idx;
3712         dev_flow->dv.push_vlan_res = cache;
3713         return 0;
3714 }
3715
3716 /**
3717  * Get the size of specific rte_flow_item_type hdr size
3718  *
3719  * @param[in] item_type
3720  *   Tested rte_flow_item_type.
3721  *
3722  * @return
3723  *   sizeof struct item_type, 0 if void or irrelevant.
3724  */
3725 static size_t
3726 flow_dv_get_item_hdr_len(const enum rte_flow_item_type item_type)
3727 {
3728         size_t retval;
3729
3730         switch (item_type) {
3731         case RTE_FLOW_ITEM_TYPE_ETH:
3732                 retval = sizeof(struct rte_ether_hdr);
3733                 break;
3734         case RTE_FLOW_ITEM_TYPE_VLAN:
3735                 retval = sizeof(struct rte_vlan_hdr);
3736                 break;
3737         case RTE_FLOW_ITEM_TYPE_IPV4:
3738                 retval = sizeof(struct rte_ipv4_hdr);
3739                 break;
3740         case RTE_FLOW_ITEM_TYPE_IPV6:
3741                 retval = sizeof(struct rte_ipv6_hdr);
3742                 break;
3743         case RTE_FLOW_ITEM_TYPE_UDP:
3744                 retval = sizeof(struct rte_udp_hdr);
3745                 break;
3746         case RTE_FLOW_ITEM_TYPE_TCP:
3747                 retval = sizeof(struct rte_tcp_hdr);
3748                 break;
3749         case RTE_FLOW_ITEM_TYPE_VXLAN:
3750         case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3751                 retval = sizeof(struct rte_vxlan_hdr);
3752                 break;
3753         case RTE_FLOW_ITEM_TYPE_GRE:
3754         case RTE_FLOW_ITEM_TYPE_NVGRE:
3755                 retval = sizeof(struct rte_gre_hdr);
3756                 break;
3757         case RTE_FLOW_ITEM_TYPE_MPLS:
3758                 retval = sizeof(struct rte_mpls_hdr);
3759                 break;
3760         case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
3761         default:
3762                 retval = 0;
3763                 break;
3764         }
3765         return retval;
3766 }
3767
3768 #define MLX5_ENCAP_IPV4_VERSION         0x40
3769 #define MLX5_ENCAP_IPV4_IHL_MIN         0x05
3770 #define MLX5_ENCAP_IPV4_TTL_DEF         0x40
3771 #define MLX5_ENCAP_IPV6_VTC_FLOW        0x60000000
3772 #define MLX5_ENCAP_IPV6_HOP_LIMIT       0xff
3773 #define MLX5_ENCAP_VXLAN_FLAGS          0x08000000
3774 #define MLX5_ENCAP_VXLAN_GPE_FLAGS      0x04
3775
3776 /**
3777  * Convert the encap action data from list of rte_flow_item to raw buffer
3778  *
3779  * @param[in] items
3780  *   Pointer to rte_flow_item objects list.
3781  * @param[out] buf
3782  *   Pointer to the output buffer.
3783  * @param[out] size
3784  *   Pointer to the output buffer size.
3785  * @param[out] error
3786  *   Pointer to the error structure.
3787  *
3788  * @return
3789  *   0 on success, a negative errno value otherwise and rte_errno is set.
3790  */
3791 static int
3792 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
3793                            size_t *size, struct rte_flow_error *error)
3794 {
3795         struct rte_ether_hdr *eth = NULL;
3796         struct rte_vlan_hdr *vlan = NULL;
3797         struct rte_ipv4_hdr *ipv4 = NULL;
3798         struct rte_ipv6_hdr *ipv6 = NULL;
3799         struct rte_udp_hdr *udp = NULL;
3800         struct rte_vxlan_hdr *vxlan = NULL;
3801         struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
3802         struct rte_gre_hdr *gre = NULL;
3803         size_t len;
3804         size_t temp_size = 0;
3805
3806         if (!items)
3807                 return rte_flow_error_set(error, EINVAL,
3808                                           RTE_FLOW_ERROR_TYPE_ACTION,
3809                                           NULL, "invalid empty data");
3810         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
3811                 len = flow_dv_get_item_hdr_len(items->type);
3812                 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
3813                         return rte_flow_error_set(error, EINVAL,
3814                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3815                                                   (void *)items->type,
3816                                                   "items total size is too big"
3817                                                   " for encap action");
3818                 rte_memcpy((void *)&buf[temp_size], items->spec, len);
3819                 switch (items->type) {
3820                 case RTE_FLOW_ITEM_TYPE_ETH:
3821                         eth = (struct rte_ether_hdr *)&buf[temp_size];
3822                         break;
3823                 case RTE_FLOW_ITEM_TYPE_VLAN:
3824                         vlan = (struct rte_vlan_hdr *)&buf[temp_size];
3825                         if (!eth)
3826                                 return rte_flow_error_set(error, EINVAL,
3827                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3828                                                 (void *)items->type,
3829                                                 "eth header not found");
3830                         if (!eth->ether_type)
3831                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
3832                         break;
3833                 case RTE_FLOW_ITEM_TYPE_IPV4:
3834                         ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
3835                         if (!vlan && !eth)
3836                                 return rte_flow_error_set(error, EINVAL,
3837                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3838                                                 (void *)items->type,
3839                                                 "neither eth nor vlan"
3840                                                 " header found");
3841                         if (vlan && !vlan->eth_proto)
3842                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3843                         else if (eth && !eth->ether_type)
3844                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3845                         if (!ipv4->version_ihl)
3846                                 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
3847                                                     MLX5_ENCAP_IPV4_IHL_MIN;
3848                         if (!ipv4->time_to_live)
3849                                 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
3850                         break;
3851                 case RTE_FLOW_ITEM_TYPE_IPV6:
3852                         ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
3853                         if (!vlan && !eth)
3854                                 return rte_flow_error_set(error, EINVAL,
3855                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3856                                                 (void *)items->type,
3857                                                 "neither eth nor vlan"
3858                                                 " header found");
3859                         if (vlan && !vlan->eth_proto)
3860                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3861                         else if (eth && !eth->ether_type)
3862                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3863                         if (!ipv6->vtc_flow)
3864                                 ipv6->vtc_flow =
3865                                         RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
3866                         if (!ipv6->hop_limits)
3867                                 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
3868                         break;
3869                 case RTE_FLOW_ITEM_TYPE_UDP:
3870                         udp = (struct rte_udp_hdr *)&buf[temp_size];
3871                         if (!ipv4 && !ipv6)
3872                                 return rte_flow_error_set(error, EINVAL,
3873                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3874                                                 (void *)items->type,
3875                                                 "ip header not found");
3876                         if (ipv4 && !ipv4->next_proto_id)
3877                                 ipv4->next_proto_id = IPPROTO_UDP;
3878                         else if (ipv6 && !ipv6->proto)
3879                                 ipv6->proto = IPPROTO_UDP;
3880                         break;
3881                 case RTE_FLOW_ITEM_TYPE_VXLAN:
3882                         vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
3883                         if (!udp)
3884                                 return rte_flow_error_set(error, EINVAL,
3885                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3886                                                 (void *)items->type,
3887                                                 "udp header not found");
3888                         if (!udp->dst_port)
3889                                 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
3890                         if (!vxlan->vx_flags)
3891                                 vxlan->vx_flags =
3892                                         RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
3893                         break;
3894                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3895                         vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
3896                         if (!udp)
3897                                 return rte_flow_error_set(error, EINVAL,
3898                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3899                                                 (void *)items->type,
3900                                                 "udp header not found");
3901                         if (!vxlan_gpe->proto)
3902                                 return rte_flow_error_set(error, EINVAL,
3903                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3904                                                 (void *)items->type,
3905                                                 "next protocol not found");
3906                         if (!udp->dst_port)
3907                                 udp->dst_port =
3908                                         RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
3909                         if (!vxlan_gpe->vx_flags)
3910                                 vxlan_gpe->vx_flags =
3911                                                 MLX5_ENCAP_VXLAN_GPE_FLAGS;
3912                         break;
3913                 case RTE_FLOW_ITEM_TYPE_GRE:
3914                 case RTE_FLOW_ITEM_TYPE_NVGRE:
3915                         gre = (struct rte_gre_hdr *)&buf[temp_size];
3916                         if (!gre->proto)
3917                                 return rte_flow_error_set(error, EINVAL,
3918                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3919                                                 (void *)items->type,
3920                                                 "next protocol not found");
3921                         if (!ipv4 && !ipv6)
3922                                 return rte_flow_error_set(error, EINVAL,
3923                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3924                                                 (void *)items->type,
3925                                                 "ip header not found");
3926                         if (ipv4 && !ipv4->next_proto_id)
3927                                 ipv4->next_proto_id = IPPROTO_GRE;
3928                         else if (ipv6 && !ipv6->proto)
3929                                 ipv6->proto = IPPROTO_GRE;
3930                         break;
3931                 case RTE_FLOW_ITEM_TYPE_VOID:
3932                         break;
3933                 default:
3934                         return rte_flow_error_set(error, EINVAL,
3935                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3936                                                   (void *)items->type,
3937                                                   "unsupported item type");
3938                         break;
3939                 }
3940                 temp_size += len;
3941         }
3942         *size = temp_size;
3943         return 0;
3944 }
3945
3946 static int
3947 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
3948 {
3949         struct rte_ether_hdr *eth = NULL;
3950         struct rte_vlan_hdr *vlan = NULL;
3951         struct rte_ipv6_hdr *ipv6 = NULL;
3952         struct rte_udp_hdr *udp = NULL;
3953         char *next_hdr;
3954         uint16_t proto;
3955
3956         eth = (struct rte_ether_hdr *)data;
3957         next_hdr = (char *)(eth + 1);
3958         proto = RTE_BE16(eth->ether_type);
3959
3960         /* VLAN skipping */
3961         while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
3962                 vlan = (struct rte_vlan_hdr *)next_hdr;
3963                 proto = RTE_BE16(vlan->eth_proto);
3964                 next_hdr += sizeof(struct rte_vlan_hdr);
3965         }
3966
3967         /* HW calculates IPv4 csum. no need to proceed */
3968         if (proto == RTE_ETHER_TYPE_IPV4)
3969                 return 0;
3970
3971         /* non IPv4/IPv6 header. not supported */
3972         if (proto != RTE_ETHER_TYPE_IPV6) {
3973                 return rte_flow_error_set(error, ENOTSUP,
3974                                           RTE_FLOW_ERROR_TYPE_ACTION,
3975                                           NULL, "Cannot offload non IPv4/IPv6");
3976         }
3977
3978         ipv6 = (struct rte_ipv6_hdr *)next_hdr;
3979
3980         /* ignore non UDP */
3981         if (ipv6->proto != IPPROTO_UDP)
3982                 return 0;
3983
3984         udp = (struct rte_udp_hdr *)(ipv6 + 1);
3985         udp->dgram_cksum = 0;
3986
3987         return 0;
3988 }
3989
3990 /**
3991  * Convert L2 encap action to DV specification.
3992  *
3993  * @param[in] dev
3994  *   Pointer to rte_eth_dev structure.
3995  * @param[in] action
3996  *   Pointer to action structure.
3997  * @param[in, out] dev_flow
3998  *   Pointer to the mlx5_flow.
3999  * @param[in] transfer
4000  *   Mark if the flow is E-Switch flow.
4001  * @param[out] error
4002  *   Pointer to the error structure.
4003  *
4004  * @return
4005  *   0 on success, a negative errno value otherwise and rte_errno is set.
4006  */
4007 static int
4008 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
4009                                const struct rte_flow_action *action,
4010                                struct mlx5_flow *dev_flow,
4011                                uint8_t transfer,
4012                                struct rte_flow_error *error)
4013 {
4014         const struct rte_flow_item *encap_data;
4015         const struct rte_flow_action_raw_encap *raw_encap_data;
4016         struct mlx5_flow_dv_encap_decap_resource res = {
4017                 .reformat_type =
4018                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
4019                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
4020                                       MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
4021         };
4022
4023         if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
4024                 raw_encap_data =
4025                         (const struct rte_flow_action_raw_encap *)action->conf;
4026                 res.size = raw_encap_data->size;
4027                 memcpy(res.buf, raw_encap_data->data, res.size);
4028         } else {
4029                 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
4030                         encap_data =
4031                                 ((const struct rte_flow_action_vxlan_encap *)
4032                                                 action->conf)->definition;
4033                 else
4034                         encap_data =
4035                                 ((const struct rte_flow_action_nvgre_encap *)
4036                                                 action->conf)->definition;
4037                 if (flow_dv_convert_encap_data(encap_data, res.buf,
4038                                                &res.size, error))
4039                         return -rte_errno;
4040         }
4041         if (flow_dv_zero_encap_udp_csum(res.buf, error))
4042                 return -rte_errno;
4043         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4044                 return rte_flow_error_set(error, EINVAL,
4045                                           RTE_FLOW_ERROR_TYPE_ACTION,
4046                                           NULL, "can't create L2 encap action");
4047         return 0;
4048 }
4049
4050 /**
4051  * Convert L2 decap action to DV specification.
4052  *
4053  * @param[in] dev
4054  *   Pointer to rte_eth_dev structure.
4055  * @param[in, out] dev_flow
4056  *   Pointer to the mlx5_flow.
4057  * @param[in] transfer
4058  *   Mark if the flow is E-Switch flow.
4059  * @param[out] error
4060  *   Pointer to the error structure.
4061  *
4062  * @return
4063  *   0 on success, a negative errno value otherwise and rte_errno is set.
4064  */
4065 static int
4066 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
4067                                struct mlx5_flow *dev_flow,
4068                                uint8_t transfer,
4069                                struct rte_flow_error *error)
4070 {
4071         struct mlx5_flow_dv_encap_decap_resource res = {
4072                 .size = 0,
4073                 .reformat_type =
4074                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
4075                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
4076                                       MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
4077         };
4078
4079         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4080                 return rte_flow_error_set(error, EINVAL,
4081                                           RTE_FLOW_ERROR_TYPE_ACTION,
4082                                           NULL, "can't create L2 decap action");
4083         return 0;
4084 }
4085
4086 /**
4087  * Convert raw decap/encap (L3 tunnel) action to DV specification.
4088  *
4089  * @param[in] dev
4090  *   Pointer to rte_eth_dev structure.
4091  * @param[in] action
4092  *   Pointer to action structure.
4093  * @param[in, out] dev_flow
4094  *   Pointer to the mlx5_flow.
4095  * @param[in] attr
4096  *   Pointer to the flow attributes.
4097  * @param[out] error
4098  *   Pointer to the error structure.
4099  *
4100  * @return
4101  *   0 on success, a negative errno value otherwise and rte_errno is set.
4102  */
4103 static int
4104 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
4105                                 const struct rte_flow_action *action,
4106                                 struct mlx5_flow *dev_flow,
4107                                 const struct rte_flow_attr *attr,
4108                                 struct rte_flow_error *error)
4109 {
4110         const struct rte_flow_action_raw_encap *encap_data;
4111         struct mlx5_flow_dv_encap_decap_resource res;
4112
4113         memset(&res, 0, sizeof(res));
4114         encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
4115         res.size = encap_data->size;
4116         memcpy(res.buf, encap_data->data, res.size);
4117         res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
4118                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
4119                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
4120         if (attr->transfer)
4121                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
4122         else
4123                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
4124                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
4125         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4126                 return rte_flow_error_set(error, EINVAL,
4127                                           RTE_FLOW_ERROR_TYPE_ACTION,
4128                                           NULL, "can't create encap action");
4129         return 0;
4130 }
4131
4132 /**
4133  * Create action push VLAN.
4134  *
4135  * @param[in] dev
4136  *   Pointer to rte_eth_dev structure.
4137  * @param[in] attr
4138  *   Pointer to the flow attributes.
4139  * @param[in] vlan
4140  *   Pointer to the vlan to push to the Ethernet header.
4141  * @param[in, out] dev_flow
4142  *   Pointer to the mlx5_flow.
4143  * @param[out] error
4144  *   Pointer to the error structure.
4145  *
4146  * @return
4147  *   0 on success, a negative errno value otherwise and rte_errno is set.
4148  */
4149 static int
4150 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
4151                                 const struct rte_flow_attr *attr,
4152                                 const struct rte_vlan_hdr *vlan,
4153                                 struct mlx5_flow *dev_flow,
4154                                 struct rte_flow_error *error)
4155 {
4156         struct mlx5_flow_dv_push_vlan_action_resource res;
4157
4158         memset(&res, 0, sizeof(res));
4159         res.vlan_tag =
4160                 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
4161                                  vlan->vlan_tci);
4162         if (attr->transfer)
4163                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
4164         else
4165                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
4166                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
4167         return flow_dv_push_vlan_action_resource_register
4168                                             (dev, &res, dev_flow, error);
4169 }
4170
4171 /**
4172  * Validate the modify-header actions.
4173  *
4174  * @param[in] action_flags
4175  *   Holds the actions detected until now.
4176  * @param[in] action
4177  *   Pointer to the modify action.
4178  * @param[out] error
4179  *   Pointer to error structure.
4180  *
4181  * @return
4182  *   0 on success, a negative errno value otherwise and rte_errno is set.
4183  */
4184 static int
4185 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
4186                                    const struct rte_flow_action *action,
4187                                    struct rte_flow_error *error)
4188 {
4189         if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
4190                 return rte_flow_error_set(error, EINVAL,
4191                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4192                                           NULL, "action configuration not set");
4193         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
4194                 return rte_flow_error_set(error, EINVAL,
4195                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4196                                           "can't have encap action before"
4197                                           " modify action");
4198         return 0;
4199 }
4200
4201 /**
4202  * Validate the modify-header MAC address actions.
4203  *
4204  * @param[in] action_flags
4205  *   Holds the actions detected until now.
4206  * @param[in] action
4207  *   Pointer to the modify action.
4208  * @param[in] item_flags
4209  *   Holds the items detected.
4210  * @param[out] error
4211  *   Pointer to error structure.
4212  *
4213  * @return
4214  *   0 on success, a negative errno value otherwise and rte_errno is set.
4215  */
4216 static int
4217 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
4218                                    const struct rte_flow_action *action,
4219                                    const uint64_t item_flags,
4220                                    struct rte_flow_error *error)
4221 {
4222         int ret = 0;
4223
4224         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4225         if (!ret) {
4226                 if (!(item_flags & MLX5_FLOW_LAYER_L2))
4227                         return rte_flow_error_set(error, EINVAL,
4228                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4229                                                   NULL,
4230                                                   "no L2 item in pattern");
4231         }
4232         return ret;
4233 }
4234
4235 /**
4236  * Validate the modify-header IPv4 address actions.
4237  *
4238  * @param[in] action_flags
4239  *   Holds the actions detected until now.
4240  * @param[in] action
4241  *   Pointer to the modify action.
4242  * @param[in] item_flags
4243  *   Holds the items detected.
4244  * @param[out] error
4245  *   Pointer to error structure.
4246  *
4247  * @return
4248  *   0 on success, a negative errno value otherwise and rte_errno is set.
4249  */
4250 static int
4251 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
4252                                     const struct rte_flow_action *action,
4253                                     const uint64_t item_flags,
4254                                     struct rte_flow_error *error)
4255 {
4256         int ret = 0;
4257         uint64_t layer;
4258
4259         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4260         if (!ret) {
4261                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4262                                  MLX5_FLOW_LAYER_INNER_L3_IPV4 :
4263                                  MLX5_FLOW_LAYER_OUTER_L3_IPV4;
4264                 if (!(item_flags & layer))
4265                         return rte_flow_error_set(error, EINVAL,
4266                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4267                                                   NULL,
4268                                                   "no ipv4 item in pattern");
4269         }
4270         return ret;
4271 }
4272
4273 /**
4274  * Validate the modify-header IPv6 address actions.
4275  *
4276  * @param[in] action_flags
4277  *   Holds the actions detected until now.
4278  * @param[in] action
4279  *   Pointer to the modify action.
4280  * @param[in] item_flags
4281  *   Holds the items detected.
4282  * @param[out] error
4283  *   Pointer to error structure.
4284  *
4285  * @return
4286  *   0 on success, a negative errno value otherwise and rte_errno is set.
4287  */
4288 static int
4289 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
4290                                     const struct rte_flow_action *action,
4291                                     const uint64_t item_flags,
4292                                     struct rte_flow_error *error)
4293 {
4294         int ret = 0;
4295         uint64_t layer;
4296
4297         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4298         if (!ret) {
4299                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4300                                  MLX5_FLOW_LAYER_INNER_L3_IPV6 :
4301                                  MLX5_FLOW_LAYER_OUTER_L3_IPV6;
4302                 if (!(item_flags & layer))
4303                         return rte_flow_error_set(error, EINVAL,
4304                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4305                                                   NULL,
4306                                                   "no ipv6 item in pattern");
4307         }
4308         return ret;
4309 }
4310
4311 /**
4312  * Validate the modify-header TP actions.
4313  *
4314  * @param[in] action_flags
4315  *   Holds the actions detected until now.
4316  * @param[in] action
4317  *   Pointer to the modify action.
4318  * @param[in] item_flags
4319  *   Holds the items detected.
4320  * @param[out] error
4321  *   Pointer to error structure.
4322  *
4323  * @return
4324  *   0 on success, a negative errno value otherwise and rte_errno is set.
4325  */
4326 static int
4327 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
4328                                   const struct rte_flow_action *action,
4329                                   const uint64_t item_flags,
4330                                   struct rte_flow_error *error)
4331 {
4332         int ret = 0;
4333         uint64_t layer;
4334
4335         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4336         if (!ret) {
4337                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4338                                  MLX5_FLOW_LAYER_INNER_L4 :
4339                                  MLX5_FLOW_LAYER_OUTER_L4;
4340                 if (!(item_flags & layer))
4341                         return rte_flow_error_set(error, EINVAL,
4342                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4343                                                   NULL, "no transport layer "
4344                                                   "in pattern");
4345         }
4346         return ret;
4347 }
4348
4349 /**
4350  * Validate the modify-header actions of increment/decrement
4351  * TCP Sequence-number.
4352  *
4353  * @param[in] action_flags
4354  *   Holds the actions detected until now.
4355  * @param[in] action
4356  *   Pointer to the modify action.
4357  * @param[in] item_flags
4358  *   Holds the items detected.
4359  * @param[out] error
4360  *   Pointer to error structure.
4361  *
4362  * @return
4363  *   0 on success, a negative errno value otherwise and rte_errno is set.
4364  */
4365 static int
4366 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
4367                                        const struct rte_flow_action *action,
4368                                        const uint64_t item_flags,
4369                                        struct rte_flow_error *error)
4370 {
4371         int ret = 0;
4372         uint64_t layer;
4373
4374         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4375         if (!ret) {
4376                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4377                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
4378                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
4379                 if (!(item_flags & layer))
4380                         return rte_flow_error_set(error, EINVAL,
4381                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4382                                                   NULL, "no TCP item in"
4383                                                   " pattern");
4384                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
4385                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
4386                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
4387                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
4388                         return rte_flow_error_set(error, EINVAL,
4389                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4390                                                   NULL,
4391                                                   "cannot decrease and increase"
4392                                                   " TCP sequence number"
4393                                                   " at the same time");
4394         }
4395         return ret;
4396 }
4397
4398 /**
4399  * Validate the modify-header actions of increment/decrement
4400  * TCP Acknowledgment number.
4401  *
4402  * @param[in] action_flags
4403  *   Holds the actions detected until now.
4404  * @param[in] action
4405  *   Pointer to the modify action.
4406  * @param[in] item_flags
4407  *   Holds the items detected.
4408  * @param[out] error
4409  *   Pointer to error structure.
4410  *
4411  * @return
4412  *   0 on success, a negative errno value otherwise and rte_errno is set.
4413  */
4414 static int
4415 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
4416                                        const struct rte_flow_action *action,
4417                                        const uint64_t item_flags,
4418                                        struct rte_flow_error *error)
4419 {
4420         int ret = 0;
4421         uint64_t layer;
4422
4423         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4424         if (!ret) {
4425                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4426                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
4427                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
4428                 if (!(item_flags & layer))
4429                         return rte_flow_error_set(error, EINVAL,
4430                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4431                                                   NULL, "no TCP item in"
4432                                                   " pattern");
4433                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
4434                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
4435                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
4436                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
4437                         return rte_flow_error_set(error, EINVAL,
4438                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4439                                                   NULL,
4440                                                   "cannot decrease and increase"
4441                                                   " TCP acknowledgment number"
4442                                                   " at the same time");
4443         }
4444         return ret;
4445 }
4446
4447 /**
4448  * Validate the modify-header TTL actions.
4449  *
4450  * @param[in] action_flags
4451  *   Holds the actions detected until now.
4452  * @param[in] action
4453  *   Pointer to the modify action.
4454  * @param[in] item_flags
4455  *   Holds the items detected.
4456  * @param[out] error
4457  *   Pointer to error structure.
4458  *
4459  * @return
4460  *   0 on success, a negative errno value otherwise and rte_errno is set.
4461  */
4462 static int
4463 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
4464                                    const struct rte_flow_action *action,
4465                                    const uint64_t item_flags,
4466                                    struct rte_flow_error *error)
4467 {
4468         int ret = 0;
4469         uint64_t layer;
4470
4471         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4472         if (!ret) {
4473                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4474                                  MLX5_FLOW_LAYER_INNER_L3 :
4475                                  MLX5_FLOW_LAYER_OUTER_L3;
4476                 if (!(item_flags & layer))
4477                         return rte_flow_error_set(error, EINVAL,
4478                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4479                                                   NULL,
4480                                                   "no IP protocol in pattern");
4481         }
4482         return ret;
4483 }
4484
4485 static int
4486 mlx5_flow_item_field_width(enum rte_flow_field_id field)
4487 {
4488         switch (field) {
4489         case RTE_FLOW_FIELD_START:
4490                 return 32;
4491         case RTE_FLOW_FIELD_MAC_DST:
4492         case RTE_FLOW_FIELD_MAC_SRC:
4493                 return 48;
4494         case RTE_FLOW_FIELD_VLAN_TYPE:
4495                 return 16;
4496         case RTE_FLOW_FIELD_VLAN_ID:
4497                 return 12;
4498         case RTE_FLOW_FIELD_MAC_TYPE:
4499                 return 16;
4500         case RTE_FLOW_FIELD_IPV4_DSCP:
4501                 return 6;
4502         case RTE_FLOW_FIELD_IPV4_TTL:
4503                 return 8;
4504         case RTE_FLOW_FIELD_IPV4_SRC:
4505         case RTE_FLOW_FIELD_IPV4_DST:
4506                 return 32;
4507         case RTE_FLOW_FIELD_IPV6_DSCP:
4508                 return 6;
4509         case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
4510                 return 8;
4511         case RTE_FLOW_FIELD_IPV6_SRC:
4512         case RTE_FLOW_FIELD_IPV6_DST:
4513                 return 128;
4514         case RTE_FLOW_FIELD_TCP_PORT_SRC:
4515         case RTE_FLOW_FIELD_TCP_PORT_DST:
4516                 return 16;
4517         case RTE_FLOW_FIELD_TCP_SEQ_NUM:
4518         case RTE_FLOW_FIELD_TCP_ACK_NUM:
4519                 return 32;
4520         case RTE_FLOW_FIELD_TCP_FLAGS:
4521                 return 6;
4522         case RTE_FLOW_FIELD_UDP_PORT_SRC:
4523         case RTE_FLOW_FIELD_UDP_PORT_DST:
4524                 return 16;
4525         case RTE_FLOW_FIELD_VXLAN_VNI:
4526         case RTE_FLOW_FIELD_GENEVE_VNI:
4527                 return 24;
4528         case RTE_FLOW_FIELD_GTP_TEID:
4529         case RTE_FLOW_FIELD_TAG:
4530                 return 32;
4531         case RTE_FLOW_FIELD_MARK:
4532                 return 24;
4533         case RTE_FLOW_FIELD_META:
4534         case RTE_FLOW_FIELD_POINTER:
4535         case RTE_FLOW_FIELD_VALUE:
4536                 return 32;
4537         default:
4538                 MLX5_ASSERT(false);
4539         }
4540         return 0;
4541 }
4542
4543 /**
4544  * Validate the generic modify field actions.
4545  * @param[in] dev
4546  *   Pointer to the rte_eth_dev structure.
4547  * @param[in] action_flags
4548  *   Holds the actions detected until now.
4549  * @param[in] action
4550  *   Pointer to the modify action.
4551  * @param[in] item_flags
4552  *   Holds the items detected.
4553  * @param[out] error
4554  *   Pointer to error structure.
4555  *
4556  * @return
4557  *   Number of header fields to modify (0 or more) on success,
4558  *   a negative errno value otherwise and rte_errno is set.
4559  */
4560 static int
4561 flow_dv_validate_action_modify_field(struct rte_eth_dev *dev,
4562                                    const uint64_t action_flags,
4563                                    const struct rte_flow_action *action,
4564                                    struct rte_flow_error *error)
4565 {
4566         int ret = 0;
4567         struct mlx5_priv *priv = dev->data->dev_private;
4568         struct mlx5_dev_config *config = &priv->config;
4569         const struct rte_flow_action_modify_field *action_modify_field =
4570                 action->conf;
4571         uint32_t dst_width =
4572                 mlx5_flow_item_field_width(action_modify_field->dst.field);
4573         uint32_t src_width =
4574                 mlx5_flow_item_field_width(action_modify_field->src.field);
4575
4576         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4577         if (ret)
4578                 return ret;
4579
4580         if (action_modify_field->width == 0)
4581                 return rte_flow_error_set(error, EINVAL,
4582                                         RTE_FLOW_ERROR_TYPE_ACTION,
4583                                         NULL,
4584                                         "no bits are requested to be modified");
4585         else if (action_modify_field->width > dst_width ||
4586                  action_modify_field->width > src_width)
4587                 return rte_flow_error_set(error, EINVAL,
4588                                         RTE_FLOW_ERROR_TYPE_ACTION,
4589                                         NULL,
4590                                         "cannot modify more bits than"
4591                                         " the width of a field");
4592         if (action_modify_field->dst.field != RTE_FLOW_FIELD_VALUE &&
4593             action_modify_field->dst.field != RTE_FLOW_FIELD_POINTER) {
4594                 if ((action_modify_field->dst.offset +
4595                      action_modify_field->width > dst_width) ||
4596                     (action_modify_field->dst.offset % 32))
4597                         return rte_flow_error_set(error, EINVAL,
4598                                                 RTE_FLOW_ERROR_TYPE_ACTION,
4599                                                 NULL,
4600                                                 "destination offset is too big"
4601                                                 " or not aligned to 4 bytes");
4602                 if (action_modify_field->dst.level &&
4603                     action_modify_field->dst.field != RTE_FLOW_FIELD_TAG)
4604                         return rte_flow_error_set(error, EINVAL,
4605                                                 RTE_FLOW_ERROR_TYPE_ACTION,
4606                                                 NULL,
4607                                                 "cannot modify inner headers");
4608         }
4609         if (action_modify_field->src.field != RTE_FLOW_FIELD_VALUE &&
4610             action_modify_field->src.field != RTE_FLOW_FIELD_POINTER) {
4611                 if ((action_modify_field->src.offset +
4612                      action_modify_field->width > src_width) ||
4613                     (action_modify_field->src.offset % 32))
4614                         return rte_flow_error_set(error, EINVAL,
4615                                                 RTE_FLOW_ERROR_TYPE_ACTION,
4616                                                 NULL,
4617                                                 "source offset is too big"
4618                                                 " or not aligned to 4 bytes");
4619                 if (action_modify_field->src.level &&
4620                     action_modify_field->src.field != RTE_FLOW_FIELD_TAG)
4621                         return rte_flow_error_set(error, EINVAL,
4622                                                 RTE_FLOW_ERROR_TYPE_ACTION,
4623                                                 NULL,
4624                                                 "cannot copy from inner headers");
4625         }
4626         if (action_modify_field->dst.field ==
4627             action_modify_field->src.field)
4628                 return rte_flow_error_set(error, EINVAL,
4629                                         RTE_FLOW_ERROR_TYPE_ACTION,
4630                                         NULL,
4631                                         "source and destination fields"
4632                                         " cannot be the same");
4633         if (action_modify_field->dst.field == RTE_FLOW_FIELD_VALUE ||
4634             action_modify_field->dst.field == RTE_FLOW_FIELD_POINTER)
4635                 return rte_flow_error_set(error, EINVAL,
4636                                         RTE_FLOW_ERROR_TYPE_ACTION,
4637                                         NULL,
4638                                         "immediate value or a pointer to it"
4639                                         " cannot be used as a destination");
4640         if (action_modify_field->dst.field == RTE_FLOW_FIELD_START ||
4641             action_modify_field->src.field == RTE_FLOW_FIELD_START)
4642                 return rte_flow_error_set(error, EINVAL,
4643                                 RTE_FLOW_ERROR_TYPE_ACTION,
4644                                 NULL,
4645                                 "modifications of an arbitrary"
4646                                 " place in a packet is not supported");
4647         if (action_modify_field->dst.field == RTE_FLOW_FIELD_MARK ||
4648             action_modify_field->src.field == RTE_FLOW_FIELD_MARK) {
4649                 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY ||
4650                     !mlx5_flow_ext_mreg_supported(dev))
4651                         return rte_flow_error_set(error, ENOTSUP,
4652                                         RTE_FLOW_ERROR_TYPE_ACTION, action,
4653                                         "cannot modify mark without extended"
4654                                         " metadata register support");
4655         }
4656         if (action_modify_field->operation != RTE_FLOW_MODIFY_SET)
4657                 return rte_flow_error_set(error, EINVAL,
4658                                 RTE_FLOW_ERROR_TYPE_ACTION,
4659                                 NULL,
4660                                 "add and sub operations"
4661                                 " are not supported");
4662         return (action_modify_field->width / 32) +
4663                !!(action_modify_field->width % 32);
4664 }
4665
4666 /**
4667  * Validate jump action.
4668  *
4669  * @param[in] action
4670  *   Pointer to the jump action.
4671  * @param[in] action_flags
4672  *   Holds the actions detected until now.
4673  * @param[in] attributes
4674  *   Pointer to flow attributes
4675  * @param[in] external
4676  *   Action belongs to flow rule created by request external to PMD.
4677  * @param[out] error
4678  *   Pointer to error structure.
4679  *
4680  * @return
4681  *   0 on success, a negative errno value otherwise and rte_errno is set.
4682  */
4683 static int
4684 flow_dv_validate_action_jump(struct rte_eth_dev *dev,
4685                              const struct mlx5_flow_tunnel *tunnel,
4686                              const struct rte_flow_action *action,
4687                              uint64_t action_flags,
4688                              const struct rte_flow_attr *attributes,
4689                              bool external, struct rte_flow_error *error)
4690 {
4691         uint32_t target_group, table;
4692         int ret = 0;
4693         struct flow_grp_info grp_info = {
4694                 .external = !!external,
4695                 .transfer = !!attributes->transfer,
4696                 .fdb_def_rule = 1,
4697                 .std_tbl_fix = 0
4698         };
4699         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
4700                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4701                 return rte_flow_error_set(error, EINVAL,
4702                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4703                                           "can't have 2 fate actions in"
4704                                           " same flow");
4705         if (action_flags & MLX5_FLOW_ACTION_METER)
4706                 return rte_flow_error_set(error, ENOTSUP,
4707                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4708                                           "jump with meter not support");
4709         if (!action->conf)
4710                 return rte_flow_error_set(error, EINVAL,
4711                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4712                                           NULL, "action configuration not set");
4713         target_group =
4714                 ((const struct rte_flow_action_jump *)action->conf)->group;
4715         ret = mlx5_flow_group_to_table(dev, tunnel, target_group, &table,
4716                                        &grp_info, error);
4717         if (ret)
4718                 return ret;
4719         if (attributes->group == target_group &&
4720             !(action_flags & (MLX5_FLOW_ACTION_TUNNEL_SET |
4721                               MLX5_FLOW_ACTION_TUNNEL_MATCH)))
4722                 return rte_flow_error_set(error, EINVAL,
4723                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4724                                           "target group must be other than"
4725                                           " the current flow group");
4726         return 0;
4727 }
4728
4729 /*
4730  * Validate the port_id action.
4731  *
4732  * @param[in] dev
4733  *   Pointer to rte_eth_dev structure.
4734  * @param[in] action_flags
4735  *   Bit-fields that holds the actions detected until now.
4736  * @param[in] action
4737  *   Port_id RTE action structure.
4738  * @param[in] attr
4739  *   Attributes of flow that includes this action.
4740  * @param[out] error
4741  *   Pointer to error structure.
4742  *
4743  * @return
4744  *   0 on success, a negative errno value otherwise and rte_errno is set.
4745  */
4746 static int
4747 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
4748                                 uint64_t action_flags,
4749                                 const struct rte_flow_action *action,
4750                                 const struct rte_flow_attr *attr,
4751                                 struct rte_flow_error *error)
4752 {
4753         const struct rte_flow_action_port_id *port_id;
4754         struct mlx5_priv *act_priv;
4755         struct mlx5_priv *dev_priv;
4756         uint16_t port;
4757
4758         if (!attr->transfer)
4759                 return rte_flow_error_set(error, ENOTSUP,
4760                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4761                                           NULL,
4762                                           "port id action is valid in transfer"
4763                                           " mode only");
4764         if (!action || !action->conf)
4765                 return rte_flow_error_set(error, ENOTSUP,
4766                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4767                                           NULL,
4768                                           "port id action parameters must be"
4769                                           " specified");
4770         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
4771                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4772                 return rte_flow_error_set(error, EINVAL,
4773                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4774                                           "can have only one fate actions in"
4775                                           " a flow");
4776         dev_priv = mlx5_dev_to_eswitch_info(dev);
4777         if (!dev_priv)
4778                 return rte_flow_error_set(error, rte_errno,
4779                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4780                                           NULL,
4781                                           "failed to obtain E-Switch info");
4782         port_id = action->conf;
4783         port = port_id->original ? dev->data->port_id : port_id->id;
4784         act_priv = mlx5_port_to_eswitch_info(port, false);
4785         if (!act_priv)
4786                 return rte_flow_error_set
4787                                 (error, rte_errno,
4788                                  RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
4789                                  "failed to obtain E-Switch port id for port");
4790         if (act_priv->domain_id != dev_priv->domain_id)
4791                 return rte_flow_error_set
4792                                 (error, EINVAL,
4793                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4794                                  "port does not belong to"
4795                                  " E-Switch being configured");
4796         return 0;
4797 }
4798
4799 /**
4800  * Get the maximum number of modify header actions.
4801  *
4802  * @param dev
4803  *   Pointer to rte_eth_dev structure.
4804  * @param flags
4805  *   Flags bits to check if root level.
4806  *
4807  * @return
4808  *   Max number of modify header actions device can support.
4809  */
4810 static inline unsigned int
4811 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev __rte_unused,
4812                               uint64_t flags)
4813 {
4814         /*
4815          * There's no way to directly query the max capacity from FW.
4816          * The maximal value on root table should be assumed to be supported.
4817          */
4818         if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
4819                 return MLX5_MAX_MODIFY_NUM;
4820         else
4821                 return MLX5_ROOT_TBL_MODIFY_NUM;
4822 }
4823
4824 /**
4825  * Validate the meter action.
4826  *
4827  * @param[in] dev
4828  *   Pointer to rte_eth_dev structure.
4829  * @param[in] action_flags
4830  *   Bit-fields that holds the actions detected until now.
4831  * @param[in] action
4832  *   Pointer to the meter action.
4833  * @param[in] attr
4834  *   Attributes of flow that includes this action.
4835  * @param[out] error
4836  *   Pointer to error structure.
4837  *
4838  * @return
4839  *   0 on success, a negative errno value otherwise and rte_ernno is set.
4840  */
4841 static int
4842 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
4843                                 uint64_t action_flags,
4844                                 const struct rte_flow_action *action,
4845                                 const struct rte_flow_attr *attr,
4846                                 struct rte_flow_error *error)
4847 {
4848         struct mlx5_priv *priv = dev->data->dev_private;
4849         const struct rte_flow_action_meter *am = action->conf;
4850         struct mlx5_flow_meter *fm;
4851
4852         if (!am)
4853                 return rte_flow_error_set(error, EINVAL,
4854                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4855                                           "meter action conf is NULL");
4856
4857         if (action_flags & MLX5_FLOW_ACTION_METER)
4858                 return rte_flow_error_set(error, ENOTSUP,
4859                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4860                                           "meter chaining not support");
4861         if (action_flags & MLX5_FLOW_ACTION_JUMP)
4862                 return rte_flow_error_set(error, ENOTSUP,
4863                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4864                                           "meter with jump not support");
4865         if (!priv->mtr_en)
4866                 return rte_flow_error_set(error, ENOTSUP,
4867                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4868                                           NULL,
4869                                           "meter action not supported");
4870         fm = mlx5_flow_meter_find(priv, am->mtr_id);
4871         if (!fm)
4872                 return rte_flow_error_set(error, EINVAL,
4873                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4874                                           "Meter not found");
4875         if (fm->ref_cnt && (!(fm->transfer == attr->transfer ||
4876               (!fm->ingress && !attr->ingress && attr->egress) ||
4877               (!fm->egress && !attr->egress && attr->ingress))))
4878                 return rte_flow_error_set(error, EINVAL,
4879                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4880                                           "Flow attributes are either invalid "
4881                                           "or have a conflict with current "
4882                                           "meter attributes");
4883         return 0;
4884 }
4885
4886 /**
4887  * Validate the age action.
4888  *
4889  * @param[in] action_flags
4890  *   Holds the actions detected until now.
4891  * @param[in] action
4892  *   Pointer to the age action.
4893  * @param[in] dev
4894  *   Pointer to the Ethernet device structure.
4895  * @param[out] error
4896  *   Pointer to error structure.
4897  *
4898  * @return
4899  *   0 on success, a negative errno value otherwise and rte_errno is set.
4900  */
4901 static int
4902 flow_dv_validate_action_age(uint64_t action_flags,
4903                             const struct rte_flow_action *action,
4904                             struct rte_eth_dev *dev,
4905                             struct rte_flow_error *error)
4906 {
4907         struct mlx5_priv *priv = dev->data->dev_private;
4908         const struct rte_flow_action_age *age = action->conf;
4909
4910         if (!priv->config.devx || (priv->sh->cmng.counter_fallback &&
4911             !priv->sh->aso_age_mng))
4912                 return rte_flow_error_set(error, ENOTSUP,
4913                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4914                                           NULL,
4915                                           "age action not supported");
4916         if (!(action->conf))
4917                 return rte_flow_error_set(error, EINVAL,
4918                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4919                                           "configuration cannot be null");
4920         if (!(age->timeout))
4921                 return rte_flow_error_set(error, EINVAL,
4922                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4923                                           "invalid timeout value 0");
4924         if (action_flags & MLX5_FLOW_ACTION_AGE)
4925                 return rte_flow_error_set(error, EINVAL,
4926                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4927                                           "duplicate age actions set");
4928         return 0;
4929 }
4930
4931 /**
4932  * Validate the modify-header IPv4 DSCP actions.
4933  *
4934  * @param[in] action_flags
4935  *   Holds the actions detected until now.
4936  * @param[in] action
4937  *   Pointer to the modify action.
4938  * @param[in] item_flags
4939  *   Holds the items detected.
4940  * @param[out] error
4941  *   Pointer to error structure.
4942  *
4943  * @return
4944  *   0 on success, a negative errno value otherwise and rte_errno is set.
4945  */
4946 static int
4947 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
4948                                          const struct rte_flow_action *action,
4949                                          const uint64_t item_flags,
4950                                          struct rte_flow_error *error)
4951 {
4952         int ret = 0;
4953
4954         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4955         if (!ret) {
4956                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
4957                         return rte_flow_error_set(error, EINVAL,
4958                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4959                                                   NULL,
4960                                                   "no ipv4 item in pattern");
4961         }
4962         return ret;
4963 }
4964
4965 /**
4966  * Validate the modify-header IPv6 DSCP actions.
4967  *
4968  * @param[in] action_flags
4969  *   Holds the actions detected until now.
4970  * @param[in] action
4971  *   Pointer to the modify action.
4972  * @param[in] item_flags
4973  *   Holds the items detected.
4974  * @param[out] error
4975  *   Pointer to error structure.
4976  *
4977  * @return
4978  *   0 on success, a negative errno value otherwise and rte_errno is set.
4979  */
4980 static int
4981 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
4982                                          const struct rte_flow_action *action,
4983                                          const uint64_t item_flags,
4984                                          struct rte_flow_error *error)
4985 {
4986         int ret = 0;
4987
4988         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4989         if (!ret) {
4990                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
4991                         return rte_flow_error_set(error, EINVAL,
4992                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4993                                                   NULL,
4994                                                   "no ipv6 item in pattern");
4995         }
4996         return ret;
4997 }
4998
4999 /**
5000  * Match modify-header resource.
5001  *
5002  * @param list
5003  *   Pointer to the hash list.
5004  * @param entry
5005  *   Pointer to exist resource entry object.
5006  * @param key
5007  *   Key of the new entry.
5008  * @param ctx
5009  *   Pointer to new modify-header resource.
5010  *
5011  * @return
5012  *   0 on matching, non-zero otherwise.
5013  */
5014 int
5015 flow_dv_modify_match_cb(struct mlx5_hlist *list __rte_unused,
5016                         struct mlx5_hlist_entry *entry,
5017                         uint64_t key __rte_unused, void *cb_ctx)
5018 {
5019         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5020         struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5021         struct mlx5_flow_dv_modify_hdr_resource *resource =
5022                         container_of(entry, typeof(*resource), entry);
5023         uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
5024
5025         key_len += ref->actions_num * sizeof(ref->actions[0]);
5026         return ref->actions_num != resource->actions_num ||
5027                memcmp(&ref->ft_type, &resource->ft_type, key_len);
5028 }
5029
5030 struct mlx5_hlist_entry *
5031 flow_dv_modify_create_cb(struct mlx5_hlist *list, uint64_t key __rte_unused,
5032                          void *cb_ctx)
5033 {
5034         struct mlx5_dev_ctx_shared *sh = list->ctx;
5035         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5036         struct mlx5dv_dr_domain *ns;
5037         struct mlx5_flow_dv_modify_hdr_resource *entry;
5038         struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5039         int ret;
5040         uint32_t data_len = ref->actions_num * sizeof(ref->actions[0]);
5041         uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
5042
5043         entry = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*entry) + data_len, 0,
5044                             SOCKET_ID_ANY);
5045         if (!entry) {
5046                 rte_flow_error_set(ctx->error, ENOMEM,
5047                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5048                                    "cannot allocate resource memory");
5049                 return NULL;
5050         }
5051         rte_memcpy(&entry->ft_type,
5052                    RTE_PTR_ADD(ref, offsetof(typeof(*ref), ft_type)),
5053                    key_len + data_len);
5054         if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
5055                 ns = sh->fdb_domain;
5056         else if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
5057                 ns = sh->tx_domain;
5058         else
5059                 ns = sh->rx_domain;
5060         ret = mlx5_flow_os_create_flow_action_modify_header
5061                                         (sh->ctx, ns, entry,
5062                                          data_len, &entry->action);
5063         if (ret) {
5064                 mlx5_free(entry);
5065                 rte_flow_error_set(ctx->error, ENOMEM,
5066                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5067                                    NULL, "cannot create modification action");
5068                 return NULL;
5069         }
5070         return &entry->entry;
5071 }
5072
5073 /**
5074  * Validate the sample action.
5075  *
5076  * @param[in, out] action_flags
5077  *   Holds the actions detected until now.
5078  * @param[in] action
5079  *   Pointer to the sample action.
5080  * @param[in] dev
5081  *   Pointer to the Ethernet device structure.
5082  * @param[in] attr
5083  *   Attributes of flow that includes this action.
5084  * @param[in] item_flags
5085  *   Holds the items detected.
5086  * @param[in] rss
5087  *   Pointer to the RSS action.
5088  * @param[out] sample_rss
5089  *   Pointer to the RSS action in sample action list.
5090  * @param[out] count
5091  *   Pointer to the COUNT action in sample action list.
5092  * @param[out] fdb_mirror_limit
5093  *   Pointer to the FDB mirror limitation flag.
5094  * @param[out] error
5095  *   Pointer to error structure.
5096  *
5097  * @return
5098  *   0 on success, a negative errno value otherwise and rte_errno is set.
5099  */
5100 static int
5101 flow_dv_validate_action_sample(uint64_t *action_flags,
5102                                const struct rte_flow_action *action,
5103                                struct rte_eth_dev *dev,
5104                                const struct rte_flow_attr *attr,
5105                                uint64_t item_flags,
5106                                const struct rte_flow_action_rss *rss,
5107                                const struct rte_flow_action_rss **sample_rss,
5108                                const struct rte_flow_action_count **count,
5109                                int *fdb_mirror_limit,
5110                                struct rte_flow_error *error)
5111 {
5112         struct mlx5_priv *priv = dev->data->dev_private;
5113         struct mlx5_dev_config *dev_conf = &priv->config;
5114         const struct rte_flow_action_sample *sample = action->conf;
5115         const struct rte_flow_action *act;
5116         uint64_t sub_action_flags = 0;
5117         uint16_t queue_index = 0xFFFF;
5118         int actions_n = 0;
5119         int ret;
5120
5121         if (!sample)
5122                 return rte_flow_error_set(error, EINVAL,
5123                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
5124                                           "configuration cannot be NULL");
5125         if (sample->ratio == 0)
5126                 return rte_flow_error_set(error, EINVAL,
5127                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
5128                                           "ratio value starts from 1");
5129         if (!priv->config.devx || (sample->ratio > 0 && !priv->sampler_en))
5130                 return rte_flow_error_set(error, ENOTSUP,
5131                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5132                                           NULL,
5133                                           "sample action not supported");
5134         if (*action_flags & MLX5_FLOW_ACTION_SAMPLE)
5135                 return rte_flow_error_set(error, EINVAL,
5136                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5137                                           "Multiple sample actions not "
5138                                           "supported");
5139         if (*action_flags & MLX5_FLOW_ACTION_METER)
5140                 return rte_flow_error_set(error, EINVAL,
5141                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
5142                                           "wrong action order, meter should "
5143                                           "be after sample action");
5144         if (*action_flags & MLX5_FLOW_ACTION_JUMP)
5145                 return rte_flow_error_set(error, EINVAL,
5146                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
5147                                           "wrong action order, jump should "
5148                                           "be after sample action");
5149         act = sample->actions;
5150         for (; act->type != RTE_FLOW_ACTION_TYPE_END; act++) {
5151                 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
5152                         return rte_flow_error_set(error, ENOTSUP,
5153                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5154                                                   act, "too many actions");
5155                 switch (act->type) {
5156                 case RTE_FLOW_ACTION_TYPE_QUEUE:
5157                         ret = mlx5_flow_validate_action_queue(act,
5158                                                               sub_action_flags,
5159                                                               dev,
5160                                                               attr, error);
5161                         if (ret < 0)
5162                                 return ret;
5163                         queue_index = ((const struct rte_flow_action_queue *)
5164                                                         (act->conf))->index;
5165                         sub_action_flags |= MLX5_FLOW_ACTION_QUEUE;
5166                         ++actions_n;
5167                         break;
5168                 case RTE_FLOW_ACTION_TYPE_RSS:
5169                         *sample_rss = act->conf;
5170                         ret = mlx5_flow_validate_action_rss(act,
5171                                                             sub_action_flags,
5172                                                             dev, attr,
5173                                                             item_flags,
5174                                                             error);
5175                         if (ret < 0)
5176                                 return ret;
5177                         if (rss && *sample_rss &&
5178                             ((*sample_rss)->level != rss->level ||
5179                             (*sample_rss)->types != rss->types))
5180                                 return rte_flow_error_set(error, ENOTSUP,
5181                                         RTE_FLOW_ERROR_TYPE_ACTION,
5182                                         NULL,
5183                                         "Can't use the different RSS types "
5184                                         "or level in the same flow");
5185                         if (*sample_rss != NULL && (*sample_rss)->queue_num)
5186                                 queue_index = (*sample_rss)->queue[0];
5187                         sub_action_flags |= MLX5_FLOW_ACTION_RSS;
5188                         ++actions_n;
5189                         break;
5190                 case RTE_FLOW_ACTION_TYPE_MARK:
5191                         ret = flow_dv_validate_action_mark(dev, act,
5192                                                            sub_action_flags,
5193                                                            attr, error);
5194                         if (ret < 0)
5195                                 return ret;
5196                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY)
5197                                 sub_action_flags |= MLX5_FLOW_ACTION_MARK |
5198                                                 MLX5_FLOW_ACTION_MARK_EXT;
5199                         else
5200                                 sub_action_flags |= MLX5_FLOW_ACTION_MARK;
5201                         ++actions_n;
5202                         break;
5203                 case RTE_FLOW_ACTION_TYPE_COUNT:
5204                         ret = flow_dv_validate_action_count
5205                                 (dev, act,
5206                                  *action_flags | sub_action_flags,
5207                                  error);
5208                         if (ret < 0)
5209                                 return ret;
5210                         *count = act->conf;
5211                         sub_action_flags |= MLX5_FLOW_ACTION_COUNT;
5212                         *action_flags |= MLX5_FLOW_ACTION_COUNT;
5213                         ++actions_n;
5214                         break;
5215                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5216                         ret = flow_dv_validate_action_port_id(dev,
5217                                                               sub_action_flags,
5218                                                               act,
5219                                                               attr,
5220                                                               error);
5221                         if (ret)
5222                                 return ret;
5223                         sub_action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5224                         ++actions_n;
5225                         break;
5226                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5227                         ret = flow_dv_validate_action_raw_encap_decap
5228                                 (dev, NULL, act->conf, attr, &sub_action_flags,
5229                                  &actions_n, action, item_flags, error);
5230                         if (ret < 0)
5231                                 return ret;
5232                         ++actions_n;
5233                         break;
5234                 default:
5235                         return rte_flow_error_set(error, ENOTSUP,
5236                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5237                                                   NULL,
5238                                                   "Doesn't support optional "
5239                                                   "action");
5240                 }
5241         }
5242         if (attr->ingress && !attr->transfer) {
5243                 if (!(sub_action_flags & (MLX5_FLOW_ACTION_QUEUE |
5244                                           MLX5_FLOW_ACTION_RSS)))
5245                         return rte_flow_error_set(error, EINVAL,
5246                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5247                                                   NULL,
5248                                                   "Ingress must has a dest "
5249                                                   "QUEUE for Sample");
5250         } else if (attr->egress && !attr->transfer) {
5251                 return rte_flow_error_set(error, ENOTSUP,
5252                                           RTE_FLOW_ERROR_TYPE_ACTION,
5253                                           NULL,
5254                                           "Sample Only support Ingress "
5255                                           "or E-Switch");
5256         } else if (sample->actions->type != RTE_FLOW_ACTION_TYPE_END) {
5257                 MLX5_ASSERT(attr->transfer);
5258                 if (sample->ratio > 1)
5259                         return rte_flow_error_set(error, ENOTSUP,
5260                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5261                                                   NULL,
5262                                                   "E-Switch doesn't support "
5263                                                   "any optional action "
5264                                                   "for sampling");
5265                 if (sub_action_flags & MLX5_FLOW_ACTION_QUEUE)
5266                         return rte_flow_error_set(error, ENOTSUP,
5267                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5268                                                   NULL,
5269                                                   "unsupported action QUEUE");
5270                 if (sub_action_flags & MLX5_FLOW_ACTION_RSS)
5271                         return rte_flow_error_set(error, ENOTSUP,
5272                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5273                                                   NULL,
5274                                                   "unsupported action QUEUE");
5275                 if (!(sub_action_flags & MLX5_FLOW_ACTION_PORT_ID))
5276                         return rte_flow_error_set(error, EINVAL,
5277                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5278                                                   NULL,
5279                                                   "E-Switch must has a dest "
5280                                                   "port for mirroring");
5281                 if (!priv->config.hca_attr.reg_c_preserve &&
5282                      priv->representor_id != -1)
5283                         *fdb_mirror_limit = 1;
5284         }
5285         /* Continue validation for Xcap actions.*/
5286         if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) &&
5287             (queue_index == 0xFFFF ||
5288              mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
5289                 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
5290                      MLX5_FLOW_XCAP_ACTIONS)
5291                         return rte_flow_error_set(error, ENOTSUP,
5292                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5293                                                   NULL, "encap and decap "
5294                                                   "combination aren't "
5295                                                   "supported");
5296                 if (!attr->transfer && attr->ingress && (sub_action_flags &
5297                                                         MLX5_FLOW_ACTION_ENCAP))
5298                         return rte_flow_error_set(error, ENOTSUP,
5299                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5300                                                   NULL, "encap is not supported"
5301                                                   " for ingress traffic");
5302         }
5303         return 0;
5304 }
5305
5306 /**
5307  * Find existing modify-header resource or create and register a new one.
5308  *
5309  * @param dev[in, out]
5310  *   Pointer to rte_eth_dev structure.
5311  * @param[in, out] resource
5312  *   Pointer to modify-header resource.
5313  * @parm[in, out] dev_flow
5314  *   Pointer to the dev_flow.
5315  * @param[out] error
5316  *   pointer to error structure.
5317  *
5318  * @return
5319  *   0 on success otherwise -errno and errno is set.
5320  */
5321 static int
5322 flow_dv_modify_hdr_resource_register
5323                         (struct rte_eth_dev *dev,
5324                          struct mlx5_flow_dv_modify_hdr_resource *resource,
5325                          struct mlx5_flow *dev_flow,
5326                          struct rte_flow_error *error)
5327 {
5328         struct mlx5_priv *priv = dev->data->dev_private;
5329         struct mlx5_dev_ctx_shared *sh = priv->sh;
5330         uint32_t key_len = sizeof(*resource) -
5331                            offsetof(typeof(*resource), ft_type) +
5332                            resource->actions_num * sizeof(resource->actions[0]);
5333         struct mlx5_hlist_entry *entry;
5334         struct mlx5_flow_cb_ctx ctx = {
5335                 .error = error,
5336                 .data = resource,
5337         };
5338         uint64_t key64;
5339
5340         resource->flags = dev_flow->dv.group ? 0 :
5341                           MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
5342         if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
5343                                     resource->flags))
5344                 return rte_flow_error_set(error, EOVERFLOW,
5345                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5346                                           "too many modify header items");
5347         key64 = __rte_raw_cksum(&resource->ft_type, key_len, 0);
5348         entry = mlx5_hlist_register(sh->modify_cmds, key64, &ctx);
5349         if (!entry)
5350                 return -rte_errno;
5351         resource = container_of(entry, typeof(*resource), entry);
5352         dev_flow->handle->dvh.modify_hdr = resource;
5353         return 0;
5354 }
5355
5356 /**
5357  * Get DV flow counter by index.
5358  *
5359  * @param[in] dev
5360  *   Pointer to the Ethernet device structure.
5361  * @param[in] idx
5362  *   mlx5 flow counter index in the container.
5363  * @param[out] ppool
5364  *   mlx5 flow counter pool in the container,
5365  *
5366  * @return
5367  *   Pointer to the counter, NULL otherwise.
5368  */
5369 static struct mlx5_flow_counter *
5370 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
5371                            uint32_t idx,
5372                            struct mlx5_flow_counter_pool **ppool)
5373 {
5374         struct mlx5_priv *priv = dev->data->dev_private;
5375         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5376         struct mlx5_flow_counter_pool *pool;
5377
5378         /* Decrease to original index and clear shared bit. */
5379         idx = (idx - 1) & (MLX5_CNT_SHARED_OFFSET - 1);
5380         MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cmng->n);
5381         pool = cmng->pools[idx / MLX5_COUNTERS_PER_POOL];
5382         MLX5_ASSERT(pool);
5383         if (ppool)
5384                 *ppool = pool;
5385         return MLX5_POOL_GET_CNT(pool, idx % MLX5_COUNTERS_PER_POOL);
5386 }
5387
5388 /**
5389  * Check the devx counter belongs to the pool.
5390  *
5391  * @param[in] pool
5392  *   Pointer to the counter pool.
5393  * @param[in] id
5394  *   The counter devx ID.
5395  *
5396  * @return
5397  *   True if counter belongs to the pool, false otherwise.
5398  */
5399 static bool
5400 flow_dv_is_counter_in_pool(struct mlx5_flow_counter_pool *pool, int id)
5401 {
5402         int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
5403                    MLX5_COUNTERS_PER_POOL;
5404
5405         if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
5406                 return true;
5407         return false;
5408 }
5409
5410 /**
5411  * Get a pool by devx counter ID.
5412  *
5413  * @param[in] cmng
5414  *   Pointer to the counter management.
5415  * @param[in] id
5416  *   The counter devx ID.
5417  *
5418  * @return
5419  *   The counter pool pointer if exists, NULL otherwise,
5420  */
5421 static struct mlx5_flow_counter_pool *
5422 flow_dv_find_pool_by_id(struct mlx5_flow_counter_mng *cmng, int id)
5423 {
5424         uint32_t i;
5425         struct mlx5_flow_counter_pool *pool = NULL;
5426
5427         rte_spinlock_lock(&cmng->pool_update_sl);
5428         /* Check last used pool. */
5429         if (cmng->last_pool_idx != POOL_IDX_INVALID &&
5430             flow_dv_is_counter_in_pool(cmng->pools[cmng->last_pool_idx], id)) {
5431                 pool = cmng->pools[cmng->last_pool_idx];
5432                 goto out;
5433         }
5434         /* ID out of range means no suitable pool in the container. */
5435         if (id > cmng->max_id || id < cmng->min_id)
5436                 goto out;
5437         /*
5438          * Find the pool from the end of the container, since mostly counter
5439          * ID is sequence increasing, and the last pool should be the needed
5440          * one.
5441          */
5442         i = cmng->n_valid;
5443         while (i--) {
5444                 struct mlx5_flow_counter_pool *pool_tmp = cmng->pools[i];
5445
5446                 if (flow_dv_is_counter_in_pool(pool_tmp, id)) {
5447                         pool = pool_tmp;
5448                         break;
5449                 }
5450         }
5451 out:
5452         rte_spinlock_unlock(&cmng->pool_update_sl);
5453         return pool;
5454 }
5455
5456 /**
5457  * Resize a counter container.
5458  *
5459  * @param[in] dev
5460  *   Pointer to the Ethernet device structure.
5461  *
5462  * @return
5463  *   0 on success, otherwise negative errno value and rte_errno is set.
5464  */
5465 static int
5466 flow_dv_container_resize(struct rte_eth_dev *dev)
5467 {
5468         struct mlx5_priv *priv = dev->data->dev_private;
5469         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5470         void *old_pools = cmng->pools;
5471         uint32_t resize = cmng->n + MLX5_CNT_CONTAINER_RESIZE;
5472         uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
5473         void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
5474
5475         if (!pools) {
5476                 rte_errno = ENOMEM;
5477                 return -ENOMEM;
5478         }
5479         if (old_pools)
5480                 memcpy(pools, old_pools, cmng->n *
5481                                        sizeof(struct mlx5_flow_counter_pool *));
5482         cmng->n = resize;
5483         cmng->pools = pools;
5484         if (old_pools)
5485                 mlx5_free(old_pools);
5486         return 0;
5487 }
5488
5489 /**
5490  * Query a devx flow counter.
5491  *
5492  * @param[in] dev
5493  *   Pointer to the Ethernet device structure.
5494  * @param[in] cnt
5495  *   Index to the flow counter.
5496  * @param[out] pkts
5497  *   The statistics value of packets.
5498  * @param[out] bytes
5499  *   The statistics value of bytes.
5500  *
5501  * @return
5502  *   0 on success, otherwise a negative errno value and rte_errno is set.
5503  */
5504 static inline int
5505 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
5506                      uint64_t *bytes)
5507 {
5508         struct mlx5_priv *priv = dev->data->dev_private;
5509         struct mlx5_flow_counter_pool *pool = NULL;
5510         struct mlx5_flow_counter *cnt;
5511         int offset;
5512
5513         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
5514         MLX5_ASSERT(pool);
5515         if (priv->sh->cmng.counter_fallback)
5516                 return mlx5_devx_cmd_flow_counter_query(cnt->dcs_when_active, 0,
5517                                         0, pkts, bytes, 0, NULL, NULL, 0);
5518         rte_spinlock_lock(&pool->sl);
5519         if (!pool->raw) {
5520                 *pkts = 0;
5521                 *bytes = 0;
5522         } else {
5523                 offset = MLX5_CNT_ARRAY_IDX(pool, cnt);
5524                 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
5525                 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
5526         }
5527         rte_spinlock_unlock(&pool->sl);
5528         return 0;
5529 }
5530
5531 /**
5532  * Create and initialize a new counter pool.
5533  *
5534  * @param[in] dev
5535  *   Pointer to the Ethernet device structure.
5536  * @param[out] dcs
5537  *   The devX counter handle.
5538  * @param[in] age
5539  *   Whether the pool is for counter that was allocated for aging.
5540  * @param[in/out] cont_cur
5541  *   Pointer to the container pointer, it will be update in pool resize.
5542  *
5543  * @return
5544  *   The pool container pointer on success, NULL otherwise and rte_errno is set.
5545  */
5546 static struct mlx5_flow_counter_pool *
5547 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
5548                     uint32_t age)
5549 {
5550         struct mlx5_priv *priv = dev->data->dev_private;
5551         struct mlx5_flow_counter_pool *pool;
5552         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5553         bool fallback = priv->sh->cmng.counter_fallback;
5554         uint32_t size = sizeof(*pool);
5555
5556         size += MLX5_COUNTERS_PER_POOL * MLX5_CNT_SIZE;
5557         size += (!age ? 0 : MLX5_COUNTERS_PER_POOL * MLX5_AGE_SIZE);
5558         pool = mlx5_malloc(MLX5_MEM_ZERO, size, 0, SOCKET_ID_ANY);
5559         if (!pool) {
5560                 rte_errno = ENOMEM;
5561                 return NULL;
5562         }
5563         pool->raw = NULL;
5564         pool->is_aged = !!age;
5565         pool->query_gen = 0;
5566         pool->min_dcs = dcs;
5567         rte_spinlock_init(&pool->sl);
5568         rte_spinlock_init(&pool->csl);
5569         TAILQ_INIT(&pool->counters[0]);
5570         TAILQ_INIT(&pool->counters[1]);
5571         pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
5572         rte_spinlock_lock(&cmng->pool_update_sl);
5573         pool->index = cmng->n_valid;
5574         if (pool->index == cmng->n && flow_dv_container_resize(dev)) {
5575                 mlx5_free(pool);
5576                 rte_spinlock_unlock(&cmng->pool_update_sl);
5577                 return NULL;
5578         }
5579         cmng->pools[pool->index] = pool;
5580         cmng->n_valid++;
5581         if (unlikely(fallback)) {
5582                 int base = RTE_ALIGN_FLOOR(dcs->id, MLX5_COUNTERS_PER_POOL);
5583
5584                 if (base < cmng->min_id)
5585                         cmng->min_id = base;
5586                 if (base > cmng->max_id)
5587                         cmng->max_id = base + MLX5_COUNTERS_PER_POOL - 1;
5588                 cmng->last_pool_idx = pool->index;
5589         }
5590         rte_spinlock_unlock(&cmng->pool_update_sl);
5591         return pool;
5592 }
5593
5594 /**
5595  * Prepare a new counter and/or a new counter pool.
5596  *
5597  * @param[in] dev
5598  *   Pointer to the Ethernet device structure.
5599  * @param[out] cnt_free
5600  *   Where to put the pointer of a new counter.
5601  * @param[in] age
5602  *   Whether the pool is for counter that was allocated for aging.
5603  *
5604  * @return
5605  *   The counter pool pointer and @p cnt_free is set on success,
5606  *   NULL otherwise and rte_errno is set.
5607  */
5608 static struct mlx5_flow_counter_pool *
5609 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
5610                              struct mlx5_flow_counter **cnt_free,
5611                              uint32_t age)
5612 {
5613         struct mlx5_priv *priv = dev->data->dev_private;
5614         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5615         struct mlx5_flow_counter_pool *pool;
5616         struct mlx5_counters tmp_tq;
5617         struct mlx5_devx_obj *dcs = NULL;
5618         struct mlx5_flow_counter *cnt;
5619         enum mlx5_counter_type cnt_type =
5620                         age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
5621         bool fallback = priv->sh->cmng.counter_fallback;
5622         uint32_t i;
5623
5624         if (fallback) {
5625                 /* bulk_bitmap must be 0 for single counter allocation. */
5626                 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
5627                 if (!dcs)
5628                         return NULL;
5629                 pool = flow_dv_find_pool_by_id(cmng, dcs->id);
5630                 if (!pool) {
5631                         pool = flow_dv_pool_create(dev, dcs, age);
5632                         if (!pool) {
5633                                 mlx5_devx_cmd_destroy(dcs);
5634                                 return NULL;
5635                         }
5636                 }
5637                 i = dcs->id % MLX5_COUNTERS_PER_POOL;
5638                 cnt = MLX5_POOL_GET_CNT(pool, i);
5639                 cnt->pool = pool;
5640                 cnt->dcs_when_free = dcs;
5641                 *cnt_free = cnt;
5642                 return pool;
5643         }
5644         dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
5645         if (!dcs) {
5646                 rte_errno = ENODATA;
5647                 return NULL;
5648         }
5649         pool = flow_dv_pool_create(dev, dcs, age);
5650         if (!pool) {
5651                 mlx5_devx_cmd_destroy(dcs);
5652                 return NULL;
5653         }
5654         TAILQ_INIT(&tmp_tq);
5655         for (i = 1; i < MLX5_COUNTERS_PER_POOL; ++i) {
5656                 cnt = MLX5_POOL_GET_CNT(pool, i);
5657                 cnt->pool = pool;
5658                 TAILQ_INSERT_HEAD(&tmp_tq, cnt, next);
5659         }
5660         rte_spinlock_lock(&cmng->csl[cnt_type]);
5661         TAILQ_CONCAT(&cmng->counters[cnt_type], &tmp_tq, next);
5662         rte_spinlock_unlock(&cmng->csl[cnt_type]);
5663         *cnt_free = MLX5_POOL_GET_CNT(pool, 0);
5664         (*cnt_free)->pool = pool;
5665         return pool;
5666 }
5667
5668 /**
5669  * Allocate a flow counter.
5670  *
5671  * @param[in] dev
5672  *   Pointer to the Ethernet device structure.
5673  * @param[in] age
5674  *   Whether the counter was allocated for aging.
5675  *
5676  * @return
5677  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
5678  */
5679 static uint32_t
5680 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t age)
5681 {
5682         struct mlx5_priv *priv = dev->data->dev_private;
5683         struct mlx5_flow_counter_pool *pool = NULL;
5684         struct mlx5_flow_counter *cnt_free = NULL;
5685         bool fallback = priv->sh->cmng.counter_fallback;
5686         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5687         enum mlx5_counter_type cnt_type =
5688                         age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
5689         uint32_t cnt_idx;
5690
5691         if (!priv->config.devx) {
5692                 rte_errno = ENOTSUP;
5693                 return 0;
5694         }
5695         /* Get free counters from container. */
5696         rte_spinlock_lock(&cmng->csl[cnt_type]);
5697         cnt_free = TAILQ_FIRST(&cmng->counters[cnt_type]);
5698         if (cnt_free)
5699                 TAILQ_REMOVE(&cmng->counters[cnt_type], cnt_free, next);
5700         rte_spinlock_unlock(&cmng->csl[cnt_type]);
5701         if (!cnt_free && !flow_dv_counter_pool_prepare(dev, &cnt_free, age))
5702                 goto err;
5703         pool = cnt_free->pool;
5704         if (fallback)
5705                 cnt_free->dcs_when_active = cnt_free->dcs_when_free;
5706         /* Create a DV counter action only in the first time usage. */
5707         if (!cnt_free->action) {
5708                 uint16_t offset;
5709                 struct mlx5_devx_obj *dcs;
5710                 int ret;
5711
5712                 if (!fallback) {
5713                         offset = MLX5_CNT_ARRAY_IDX(pool, cnt_free);
5714                         dcs = pool->min_dcs;
5715                 } else {
5716                         offset = 0;
5717                         dcs = cnt_free->dcs_when_free;
5718                 }
5719                 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, offset,
5720                                                             &cnt_free->action);
5721                 if (ret) {
5722                         rte_errno = errno;
5723                         goto err;
5724                 }
5725         }
5726         cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
5727                                 MLX5_CNT_ARRAY_IDX(pool, cnt_free));
5728         /* Update the counter reset values. */
5729         if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
5730                                  &cnt_free->bytes))
5731                 goto err;
5732         if (!fallback && !priv->sh->cmng.query_thread_on)
5733                 /* Start the asynchronous batch query by the host thread. */
5734                 mlx5_set_query_alarm(priv->sh);
5735         return cnt_idx;
5736 err:
5737         if (cnt_free) {
5738                 cnt_free->pool = pool;
5739                 if (fallback)
5740                         cnt_free->dcs_when_free = cnt_free->dcs_when_active;
5741                 rte_spinlock_lock(&cmng->csl[cnt_type]);
5742                 TAILQ_INSERT_TAIL(&cmng->counters[cnt_type], cnt_free, next);
5743                 rte_spinlock_unlock(&cmng->csl[cnt_type]);
5744         }
5745         return 0;
5746 }
5747
5748 /**
5749  * Allocate a shared flow counter.
5750  *
5751  * @param[in] ctx
5752  *   Pointer to the shared counter configuration.
5753  * @param[in] data
5754  *   Pointer to save the allocated counter index.
5755  *
5756  * @return
5757  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
5758  */
5759
5760 static int32_t
5761 flow_dv_counter_alloc_shared_cb(void *ctx, union mlx5_l3t_data *data)
5762 {
5763         struct mlx5_shared_counter_conf *conf = ctx;
5764         struct rte_eth_dev *dev = conf->dev;
5765         struct mlx5_flow_counter *cnt;
5766
5767         data->dword = flow_dv_counter_alloc(dev, 0);
5768         data->dword |= MLX5_CNT_SHARED_OFFSET;
5769         cnt = flow_dv_counter_get_by_idx(dev, data->dword, NULL);
5770         cnt->shared_info.id = conf->id;
5771         return 0;
5772 }
5773
5774 /**
5775  * Get a shared flow counter.
5776  *
5777  * @param[in] dev
5778  *   Pointer to the Ethernet device structure.
5779  * @param[in] id
5780  *   Counter identifier.
5781  *
5782  * @return
5783  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
5784  */
5785 static uint32_t
5786 flow_dv_counter_get_shared(struct rte_eth_dev *dev, uint32_t id)
5787 {
5788         struct mlx5_priv *priv = dev->data->dev_private;
5789         struct mlx5_shared_counter_conf conf = {
5790                 .dev = dev,
5791                 .id = id,
5792         };
5793         union mlx5_l3t_data data = {
5794                 .dword = 0,
5795         };
5796
5797         mlx5_l3t_prepare_entry(priv->sh->cnt_id_tbl, id, &data,
5798                                flow_dv_counter_alloc_shared_cb, &conf);
5799         return data.dword;
5800 }
5801
5802 /**
5803  * Get age param from counter index.
5804  *
5805  * @param[in] dev
5806  *   Pointer to the Ethernet device structure.
5807  * @param[in] counter
5808  *   Index to the counter handler.
5809  *
5810  * @return
5811  *   The aging parameter specified for the counter index.
5812  */
5813 static struct mlx5_age_param*
5814 flow_dv_counter_idx_get_age(struct rte_eth_dev *dev,
5815                                 uint32_t counter)
5816 {
5817         struct mlx5_flow_counter *cnt;
5818         struct mlx5_flow_counter_pool *pool = NULL;
5819
5820         flow_dv_counter_get_by_idx(dev, counter, &pool);
5821         counter = (counter - 1) % MLX5_COUNTERS_PER_POOL;
5822         cnt = MLX5_POOL_GET_CNT(pool, counter);
5823         return MLX5_CNT_TO_AGE(cnt);
5824 }
5825
5826 /**
5827  * Remove a flow counter from aged counter list.
5828  *
5829  * @param[in] dev
5830  *   Pointer to the Ethernet device structure.
5831  * @param[in] counter
5832  *   Index to the counter handler.
5833  * @param[in] cnt
5834  *   Pointer to the counter handler.
5835  */
5836 static void
5837 flow_dv_counter_remove_from_age(struct rte_eth_dev *dev,
5838                                 uint32_t counter, struct mlx5_flow_counter *cnt)
5839 {
5840         struct mlx5_age_info *age_info;
5841         struct mlx5_age_param *age_param;
5842         struct mlx5_priv *priv = dev->data->dev_private;
5843         uint16_t expected = AGE_CANDIDATE;
5844
5845         age_info = GET_PORT_AGE_INFO(priv);
5846         age_param = flow_dv_counter_idx_get_age(dev, counter);
5847         if (!__atomic_compare_exchange_n(&age_param->state, &expected,
5848                                          AGE_FREE, false, __ATOMIC_RELAXED,
5849                                          __ATOMIC_RELAXED)) {
5850                 /**
5851                  * We need the lock even it is age timeout,
5852                  * since counter may still in process.
5853                  */
5854                 rte_spinlock_lock(&age_info->aged_sl);
5855                 TAILQ_REMOVE(&age_info->aged_counters, cnt, next);
5856                 rte_spinlock_unlock(&age_info->aged_sl);
5857                 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
5858         }
5859 }
5860
5861 /**
5862  * Release a flow counter.
5863  *
5864  * @param[in] dev
5865  *   Pointer to the Ethernet device structure.
5866  * @param[in] counter
5867  *   Index to the counter handler.
5868  */
5869 static void
5870 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t counter)
5871 {
5872         struct mlx5_priv *priv = dev->data->dev_private;
5873         struct mlx5_flow_counter_pool *pool = NULL;
5874         struct mlx5_flow_counter *cnt;
5875         enum mlx5_counter_type cnt_type;
5876
5877         if (!counter)
5878                 return;
5879         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
5880         MLX5_ASSERT(pool);
5881         if (IS_SHARED_CNT(counter) &&
5882             mlx5_l3t_clear_entry(priv->sh->cnt_id_tbl, cnt->shared_info.id))
5883                 return;
5884         if (pool->is_aged)
5885                 flow_dv_counter_remove_from_age(dev, counter, cnt);
5886         cnt->pool = pool;
5887         /*
5888          * Put the counter back to list to be updated in none fallback mode.
5889          * Currently, we are using two list alternately, while one is in query,
5890          * add the freed counter to the other list based on the pool query_gen
5891          * value. After query finishes, add counter the list to the global
5892          * container counter list. The list changes while query starts. In
5893          * this case, lock will not be needed as query callback and release
5894          * function both operate with the different list.
5895          *
5896          */
5897         if (!priv->sh->cmng.counter_fallback) {
5898                 rte_spinlock_lock(&pool->csl);
5899                 TAILQ_INSERT_TAIL(&pool->counters[pool->query_gen], cnt, next);
5900                 rte_spinlock_unlock(&pool->csl);
5901         } else {
5902                 cnt->dcs_when_free = cnt->dcs_when_active;
5903                 cnt_type = pool->is_aged ? MLX5_COUNTER_TYPE_AGE :
5904                                            MLX5_COUNTER_TYPE_ORIGIN;
5905                 rte_spinlock_lock(&priv->sh->cmng.csl[cnt_type]);
5906                 TAILQ_INSERT_TAIL(&priv->sh->cmng.counters[cnt_type],
5907                                   cnt, next);
5908                 rte_spinlock_unlock(&priv->sh->cmng.csl[cnt_type]);
5909         }
5910 }
5911
5912 /**
5913  * Verify the @p attributes will be correctly understood by the NIC and store
5914  * them in the @p flow if everything is correct.
5915  *
5916  * @param[in] dev
5917  *   Pointer to dev struct.
5918  * @param[in] attributes
5919  *   Pointer to flow attributes
5920  * @param[in] external
5921  *   This flow rule is created by request external to PMD.
5922  * @param[out] error
5923  *   Pointer to error structure.
5924  *
5925  * @return
5926  *   - 0 on success and non root table.
5927  *   - 1 on success and root table.
5928  *   - a negative errno value otherwise and rte_errno is set.
5929  */
5930 static int
5931 flow_dv_validate_attributes(struct rte_eth_dev *dev,
5932                             const struct mlx5_flow_tunnel *tunnel,
5933                             const struct rte_flow_attr *attributes,
5934                             const struct flow_grp_info *grp_info,
5935                             struct rte_flow_error *error)
5936 {
5937         struct mlx5_priv *priv = dev->data->dev_private;
5938         uint32_t lowest_priority = mlx5_get_lowest_priority(dev, attributes);
5939         int ret = 0;
5940
5941 #ifndef HAVE_MLX5DV_DR
5942         RTE_SET_USED(tunnel);
5943         RTE_SET_USED(grp_info);
5944         if (attributes->group)
5945                 return rte_flow_error_set(error, ENOTSUP,
5946                                           RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
5947                                           NULL,
5948                                           "groups are not supported");
5949 #else
5950         uint32_t table = 0;
5951
5952         ret = mlx5_flow_group_to_table(dev, tunnel, attributes->group, &table,
5953                                        grp_info, error);
5954         if (ret)
5955                 return ret;
5956         if (!table)
5957                 ret = MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
5958 #endif
5959         if (attributes->priority != MLX5_FLOW_LOWEST_PRIO_INDICATOR &&
5960             attributes->priority > lowest_priority)
5961                 return rte_flow_error_set(error, ENOTSUP,
5962                                           RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
5963                                           NULL,
5964                                           "priority out of range");
5965         if (attributes->transfer) {
5966                 if (!priv->config.dv_esw_en)
5967                         return rte_flow_error_set
5968                                 (error, ENOTSUP,
5969                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5970                                  "E-Switch dr is not supported");
5971                 if (!(priv->representor || priv->master))
5972                         return rte_flow_error_set
5973                                 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5974                                  NULL, "E-Switch configuration can only be"
5975                                  " done by a master or a representor device");
5976                 if (attributes->egress)
5977                         return rte_flow_error_set
5978                                 (error, ENOTSUP,
5979                                  RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
5980                                  "egress is not supported");
5981         }
5982         if (!(attributes->egress ^ attributes->ingress))
5983                 return rte_flow_error_set(error, ENOTSUP,
5984                                           RTE_FLOW_ERROR_TYPE_ATTR, NULL,
5985                                           "must specify exactly one of "
5986                                           "ingress or egress");
5987         return ret;
5988 }
5989
5990 /**
5991  * Internal validation function. For validating both actions and items.
5992  *
5993  * @param[in] dev
5994  *   Pointer to the rte_eth_dev structure.
5995  * @param[in] attr
5996  *   Pointer to the flow attributes.
5997  * @param[in] items
5998  *   Pointer to the list of items.
5999  * @param[in] actions
6000  *   Pointer to the list of actions.
6001  * @param[in] external
6002  *   This flow rule is created by request external to PMD.
6003  * @param[in] hairpin
6004  *   Number of hairpin TX actions, 0 means classic flow.
6005  * @param[out] error
6006  *   Pointer to the error structure.
6007  *
6008  * @return
6009  *   0 on success, a negative errno value otherwise and rte_errno is set.
6010  */
6011 static int
6012 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
6013                  const struct rte_flow_item items[],
6014                  const struct rte_flow_action actions[],
6015                  bool external, int hairpin, struct rte_flow_error *error)
6016 {
6017         int ret;
6018         uint64_t action_flags = 0;
6019         uint64_t item_flags = 0;
6020         uint64_t last_item = 0;
6021         uint8_t next_protocol = 0xff;
6022         uint16_t ether_type = 0;
6023         int actions_n = 0;
6024         uint8_t item_ipv6_proto = 0;
6025         int fdb_mirror_limit = 0;
6026         int modify_after_mirror = 0;
6027         const struct rte_flow_item *geneve_item = NULL;
6028         const struct rte_flow_item *gre_item = NULL;
6029         const struct rte_flow_item *gtp_item = NULL;
6030         const struct rte_flow_action_raw_decap *decap;
6031         const struct rte_flow_action_raw_encap *encap;
6032         const struct rte_flow_action_rss *rss = NULL;
6033         const struct rte_flow_action_rss *sample_rss = NULL;
6034         const struct rte_flow_action_count *count = NULL;
6035         const struct rte_flow_action_count *sample_count = NULL;
6036         const struct rte_flow_item_tcp nic_tcp_mask = {
6037                 .hdr = {
6038                         .tcp_flags = 0xFF,
6039                         .src_port = RTE_BE16(UINT16_MAX),
6040                         .dst_port = RTE_BE16(UINT16_MAX),
6041                 }
6042         };
6043         const struct rte_flow_item_ipv6 nic_ipv6_mask = {
6044                 .hdr = {
6045                         .src_addr =
6046                         "\xff\xff\xff\xff\xff\xff\xff\xff"
6047                         "\xff\xff\xff\xff\xff\xff\xff\xff",
6048                         .dst_addr =
6049                         "\xff\xff\xff\xff\xff\xff\xff\xff"
6050                         "\xff\xff\xff\xff\xff\xff\xff\xff",
6051                         .vtc_flow = RTE_BE32(0xffffffff),
6052                         .proto = 0xff,
6053                         .hop_limits = 0xff,
6054                 },
6055                 .has_frag_ext = 1,
6056         };
6057         const struct rte_flow_item_ecpri nic_ecpri_mask = {
6058                 .hdr = {
6059                         .common = {
6060                                 .u32 =
6061                                 RTE_BE32(((const struct rte_ecpri_common_hdr) {
6062                                         .type = 0xFF,
6063                                         }).u32),
6064                         },
6065                         .dummy[0] = 0xffffffff,
6066                 },
6067         };
6068         struct mlx5_priv *priv = dev->data->dev_private;
6069         struct mlx5_dev_config *dev_conf = &priv->config;
6070         uint16_t queue_index = 0xFFFF;
6071         const struct rte_flow_item_vlan *vlan_m = NULL;
6072         uint32_t rw_act_num = 0;
6073         uint64_t is_root;
6074         const struct mlx5_flow_tunnel *tunnel;
6075         struct flow_grp_info grp_info = {
6076                 .external = !!external,
6077                 .transfer = !!attr->transfer,
6078                 .fdb_def_rule = !!priv->fdb_def_rule,
6079         };
6080         const struct rte_eth_hairpin_conf *conf;
6081
6082         if (items == NULL)
6083                 return -1;
6084         if (is_flow_tunnel_match_rule(dev, attr, items, actions)) {
6085                 tunnel = flow_items_to_tunnel(items);
6086                 action_flags |= MLX5_FLOW_ACTION_TUNNEL_MATCH |
6087                                 MLX5_FLOW_ACTION_DECAP;
6088         } else if (is_flow_tunnel_steer_rule(dev, attr, items, actions)) {
6089                 tunnel = flow_actions_to_tunnel(actions);
6090                 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
6091         } else {
6092                 tunnel = NULL;
6093         }
6094         if (tunnel && priv->representor)
6095                 return rte_flow_error_set(error, ENOTSUP,
6096                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6097                                           "decap not supported "
6098                                           "for VF representor");
6099         grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
6100                                 (dev, tunnel, attr, items, actions);
6101         ret = flow_dv_validate_attributes(dev, tunnel, attr, &grp_info, error);
6102         if (ret < 0)
6103                 return ret;
6104         is_root = (uint64_t)ret;
6105         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
6106                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
6107                 int type = items->type;
6108
6109                 if (!mlx5_flow_os_item_supported(type))
6110                         return rte_flow_error_set(error, ENOTSUP,
6111                                                   RTE_FLOW_ERROR_TYPE_ITEM,
6112                                                   NULL, "item not supported");
6113                 switch (type) {
6114                 case MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL:
6115                         if (items[0].type != (typeof(items[0].type))
6116                                                 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL)
6117                                 return rte_flow_error_set
6118                                                 (error, EINVAL,
6119                                                 RTE_FLOW_ERROR_TYPE_ITEM,
6120                                                 NULL, "MLX5 private items "
6121                                                 "must be the first");
6122                         break;
6123                 case RTE_FLOW_ITEM_TYPE_VOID:
6124                         break;
6125                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
6126                         ret = flow_dv_validate_item_port_id
6127                                         (dev, items, attr, item_flags, error);
6128                         if (ret < 0)
6129                                 return ret;
6130                         last_item = MLX5_FLOW_ITEM_PORT_ID;
6131                         break;
6132                 case RTE_FLOW_ITEM_TYPE_ETH:
6133                         ret = mlx5_flow_validate_item_eth(items, item_flags,
6134                                                           true, error);
6135                         if (ret < 0)
6136                                 return ret;
6137                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
6138                                              MLX5_FLOW_LAYER_OUTER_L2;
6139                         if (items->mask != NULL && items->spec != NULL) {
6140                                 ether_type =
6141                                         ((const struct rte_flow_item_eth *)
6142                                          items->spec)->type;
6143                                 ether_type &=
6144                                         ((const struct rte_flow_item_eth *)
6145                                          items->mask)->type;
6146                                 ether_type = rte_be_to_cpu_16(ether_type);
6147                         } else {
6148                                 ether_type = 0;
6149                         }
6150                         break;
6151                 case RTE_FLOW_ITEM_TYPE_VLAN:
6152                         ret = flow_dv_validate_item_vlan(items, item_flags,
6153                                                          dev, error);
6154                         if (ret < 0)
6155                                 return ret;
6156                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
6157                                              MLX5_FLOW_LAYER_OUTER_VLAN;
6158                         if (items->mask != NULL && items->spec != NULL) {
6159                                 ether_type =
6160                                         ((const struct rte_flow_item_vlan *)
6161                                          items->spec)->inner_type;
6162                                 ether_type &=
6163                                         ((const struct rte_flow_item_vlan *)
6164                                          items->mask)->inner_type;
6165                                 ether_type = rte_be_to_cpu_16(ether_type);
6166                         } else {
6167                                 ether_type = 0;
6168                         }
6169                         /* Store outer VLAN mask for of_push_vlan action. */
6170                         if (!tunnel)
6171                                 vlan_m = items->mask;
6172                         break;
6173                 case RTE_FLOW_ITEM_TYPE_IPV4:
6174                         mlx5_flow_tunnel_ip_check(items, next_protocol,
6175                                                   &item_flags, &tunnel);
6176                         ret = flow_dv_validate_item_ipv4(items, item_flags,
6177                                                          last_item, ether_type,
6178                                                          error);
6179                         if (ret < 0)
6180                                 return ret;
6181                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
6182                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
6183                         if (items->mask != NULL &&
6184                             ((const struct rte_flow_item_ipv4 *)
6185                              items->mask)->hdr.next_proto_id) {
6186                                 next_protocol =
6187                                         ((const struct rte_flow_item_ipv4 *)
6188                                          (items->spec))->hdr.next_proto_id;
6189                                 next_protocol &=
6190                                         ((const struct rte_flow_item_ipv4 *)
6191                                          (items->mask))->hdr.next_proto_id;
6192                         } else {
6193                                 /* Reset for inner layer. */
6194                                 next_protocol = 0xff;
6195                         }
6196                         break;
6197                 case RTE_FLOW_ITEM_TYPE_IPV6:
6198                         mlx5_flow_tunnel_ip_check(items, next_protocol,
6199                                                   &item_flags, &tunnel);
6200                         ret = mlx5_flow_validate_item_ipv6(items, item_flags,
6201                                                            last_item,
6202                                                            ether_type,
6203                                                            &nic_ipv6_mask,
6204                                                            error);
6205                         if (ret < 0)
6206                                 return ret;
6207                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
6208                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
6209                         if (items->mask != NULL &&
6210                             ((const struct rte_flow_item_ipv6 *)
6211                              items->mask)->hdr.proto) {
6212                                 item_ipv6_proto =
6213                                         ((const struct rte_flow_item_ipv6 *)
6214                                          items->spec)->hdr.proto;
6215                                 next_protocol =
6216                                         ((const struct rte_flow_item_ipv6 *)
6217                                          items->spec)->hdr.proto;
6218                                 next_protocol &=
6219                                         ((const struct rte_flow_item_ipv6 *)
6220                                          items->mask)->hdr.proto;
6221                         } else {
6222                                 /* Reset for inner layer. */
6223                                 next_protocol = 0xff;
6224                         }
6225                         break;
6226                 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
6227                         ret = flow_dv_validate_item_ipv6_frag_ext(items,
6228                                                                   item_flags,
6229                                                                   error);
6230                         if (ret < 0)
6231                                 return ret;
6232                         last_item = tunnel ?
6233                                         MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
6234                                         MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
6235                         if (items->mask != NULL &&
6236                             ((const struct rte_flow_item_ipv6_frag_ext *)
6237                              items->mask)->hdr.next_header) {
6238                                 next_protocol =
6239                                 ((const struct rte_flow_item_ipv6_frag_ext *)
6240                                  items->spec)->hdr.next_header;
6241                                 next_protocol &=
6242                                 ((const struct rte_flow_item_ipv6_frag_ext *)
6243                                  items->mask)->hdr.next_header;
6244                         } else {
6245                                 /* Reset for inner layer. */
6246                                 next_protocol = 0xff;
6247                         }
6248                         break;
6249                 case RTE_FLOW_ITEM_TYPE_TCP:
6250                         ret = mlx5_flow_validate_item_tcp
6251                                                 (items, item_flags,
6252                                                  next_protocol,
6253                                                  &nic_tcp_mask,
6254                                                  error);
6255                         if (ret < 0)
6256                                 return ret;
6257                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
6258                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
6259                         break;
6260                 case RTE_FLOW_ITEM_TYPE_UDP:
6261                         ret = mlx5_flow_validate_item_udp(items, item_flags,
6262                                                           next_protocol,
6263                                                           error);
6264                         if (ret < 0)
6265                                 return ret;
6266                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
6267                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
6268                         break;
6269                 case RTE_FLOW_ITEM_TYPE_GRE:
6270                         ret = mlx5_flow_validate_item_gre(items, item_flags,
6271                                                           next_protocol, error);
6272                         if (ret < 0)
6273                                 return ret;
6274                         gre_item = items;
6275                         last_item = MLX5_FLOW_LAYER_GRE;
6276                         break;
6277                 case RTE_FLOW_ITEM_TYPE_NVGRE:
6278                         ret = mlx5_flow_validate_item_nvgre(items, item_flags,
6279                                                             next_protocol,
6280                                                             error);
6281                         if (ret < 0)
6282                                 return ret;
6283                         last_item = MLX5_FLOW_LAYER_NVGRE;
6284                         break;
6285                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
6286                         ret = mlx5_flow_validate_item_gre_key
6287                                 (items, item_flags, gre_item, error);
6288                         if (ret < 0)
6289                                 return ret;
6290                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
6291                         break;
6292                 case RTE_FLOW_ITEM_TYPE_VXLAN:
6293                         ret = mlx5_flow_validate_item_vxlan(items, item_flags,
6294                                                             error);
6295                         if (ret < 0)
6296                                 return ret;
6297                         last_item = MLX5_FLOW_LAYER_VXLAN;
6298                         break;
6299                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
6300                         ret = mlx5_flow_validate_item_vxlan_gpe(items,
6301                                                                 item_flags, dev,
6302                                                                 error);
6303                         if (ret < 0)
6304                                 return ret;
6305                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
6306                         break;
6307                 case RTE_FLOW_ITEM_TYPE_GENEVE:
6308                         ret = mlx5_flow_validate_item_geneve(items,
6309                                                              item_flags, dev,
6310                                                              error);
6311                         if (ret < 0)
6312                                 return ret;
6313                         geneve_item = items;
6314                         last_item = MLX5_FLOW_LAYER_GENEVE;
6315                         break;
6316                 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
6317                         ret = mlx5_flow_validate_item_geneve_opt(items,
6318                                                                  last_item,
6319                                                                  geneve_item,
6320                                                                  dev,
6321                                                                  error);
6322                         if (ret < 0)
6323                                 return ret;
6324                         last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
6325                         break;
6326                 case RTE_FLOW_ITEM_TYPE_MPLS:
6327                         ret = mlx5_flow_validate_item_mpls(dev, items,
6328                                                            item_flags,
6329                                                            last_item, error);
6330                         if (ret < 0)
6331                                 return ret;
6332                         last_item = MLX5_FLOW_LAYER_MPLS;
6333                         break;
6334
6335                 case RTE_FLOW_ITEM_TYPE_MARK:
6336                         ret = flow_dv_validate_item_mark(dev, items, attr,
6337                                                          error);
6338                         if (ret < 0)
6339                                 return ret;
6340                         last_item = MLX5_FLOW_ITEM_MARK;
6341                         break;
6342                 case RTE_FLOW_ITEM_TYPE_META:
6343                         ret = flow_dv_validate_item_meta(dev, items, attr,
6344                                                          error);
6345                         if (ret < 0)
6346                                 return ret;
6347                         last_item = MLX5_FLOW_ITEM_METADATA;
6348                         break;
6349                 case RTE_FLOW_ITEM_TYPE_ICMP:
6350                         ret = mlx5_flow_validate_item_icmp(items, item_flags,
6351                                                            next_protocol,
6352                                                            error);
6353                         if (ret < 0)
6354                                 return ret;
6355                         last_item = MLX5_FLOW_LAYER_ICMP;
6356                         break;
6357                 case RTE_FLOW_ITEM_TYPE_ICMP6:
6358                         ret = mlx5_flow_validate_item_icmp6(items, item_flags,
6359                                                             next_protocol,
6360                                                             error);
6361                         if (ret < 0)
6362                                 return ret;
6363                         item_ipv6_proto = IPPROTO_ICMPV6;
6364                         last_item = MLX5_FLOW_LAYER_ICMP6;
6365                         break;
6366                 case RTE_FLOW_ITEM_TYPE_TAG:
6367                         ret = flow_dv_validate_item_tag(dev, items,
6368                                                         attr, error);
6369                         if (ret < 0)
6370                                 return ret;
6371                         last_item = MLX5_FLOW_ITEM_TAG;
6372                         break;
6373                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
6374                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
6375                         break;
6376                 case RTE_FLOW_ITEM_TYPE_GTP:
6377                         ret = flow_dv_validate_item_gtp(dev, items, item_flags,
6378                                                         error);
6379                         if (ret < 0)
6380                                 return ret;
6381                         gtp_item = items;
6382                         last_item = MLX5_FLOW_LAYER_GTP;
6383                         break;
6384                 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
6385                         ret = flow_dv_validate_item_gtp_psc(items, last_item,
6386                                                             gtp_item, attr,
6387                                                             error);
6388                         if (ret < 0)
6389                                 return ret;
6390                         last_item = MLX5_FLOW_LAYER_GTP_PSC;
6391                         break;
6392                 case RTE_FLOW_ITEM_TYPE_ECPRI:
6393                         /* Capacity will be checked in the translate stage. */
6394                         ret = mlx5_flow_validate_item_ecpri(items, item_flags,
6395                                                             last_item,
6396                                                             ether_type,
6397                                                             &nic_ecpri_mask,
6398                                                             error);
6399                         if (ret < 0)
6400                                 return ret;
6401                         last_item = MLX5_FLOW_LAYER_ECPRI;
6402                         break;
6403                 default:
6404                         return rte_flow_error_set(error, ENOTSUP,
6405                                                   RTE_FLOW_ERROR_TYPE_ITEM,
6406                                                   NULL, "item not supported");
6407                 }
6408                 item_flags |= last_item;
6409         }
6410         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
6411                 int type = actions->type;
6412
6413                 if (!mlx5_flow_os_action_supported(type))
6414                         return rte_flow_error_set(error, ENOTSUP,
6415                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6416                                                   actions,
6417                                                   "action not supported");
6418                 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
6419                         return rte_flow_error_set(error, ENOTSUP,
6420                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6421                                                   actions, "too many actions");
6422                 switch (type) {
6423                 case RTE_FLOW_ACTION_TYPE_VOID:
6424                         break;
6425                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
6426                         ret = flow_dv_validate_action_port_id(dev,
6427                                                               action_flags,
6428                                                               actions,
6429                                                               attr,
6430                                                               error);
6431                         if (ret)
6432                                 return ret;
6433                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
6434                         ++actions_n;
6435                         break;
6436                 case RTE_FLOW_ACTION_TYPE_FLAG:
6437                         ret = flow_dv_validate_action_flag(dev, action_flags,
6438                                                            attr, error);
6439                         if (ret < 0)
6440                                 return ret;
6441                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
6442                                 /* Count all modify-header actions as one. */
6443                                 if (!(action_flags &
6444                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
6445                                         ++actions_n;
6446                                 action_flags |= MLX5_FLOW_ACTION_FLAG |
6447                                                 MLX5_FLOW_ACTION_MARK_EXT;
6448                                 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6449                                         modify_after_mirror = 1;
6450
6451                         } else {
6452                                 action_flags |= MLX5_FLOW_ACTION_FLAG;
6453                                 ++actions_n;
6454                         }
6455                         rw_act_num += MLX5_ACT_NUM_SET_MARK;
6456                         break;
6457                 case RTE_FLOW_ACTION_TYPE_MARK:
6458                         ret = flow_dv_validate_action_mark(dev, actions,
6459                                                            action_flags,
6460                                                            attr, error);
6461                         if (ret < 0)
6462                                 return ret;
6463                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
6464                                 /* Count all modify-header actions as one. */
6465                                 if (!(action_flags &
6466                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
6467                                         ++actions_n;
6468                                 action_flags |= MLX5_FLOW_ACTION_MARK |
6469                                                 MLX5_FLOW_ACTION_MARK_EXT;
6470                                 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6471                                         modify_after_mirror = 1;
6472                         } else {
6473                                 action_flags |= MLX5_FLOW_ACTION_MARK;
6474                                 ++actions_n;
6475                         }
6476                         rw_act_num += MLX5_ACT_NUM_SET_MARK;
6477                         break;
6478                 case RTE_FLOW_ACTION_TYPE_SET_META:
6479                         ret = flow_dv_validate_action_set_meta(dev, actions,
6480                                                                action_flags,
6481                                                                attr, error);
6482                         if (ret < 0)
6483                                 return ret;
6484                         /* Count all modify-header actions as one action. */
6485                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6486                                 ++actions_n;
6487                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6488                                 modify_after_mirror = 1;
6489                         action_flags |= MLX5_FLOW_ACTION_SET_META;
6490                         rw_act_num += MLX5_ACT_NUM_SET_META;
6491                         break;
6492                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
6493                         ret = flow_dv_validate_action_set_tag(dev, actions,
6494                                                               action_flags,
6495                                                               attr, error);
6496                         if (ret < 0)
6497                                 return ret;
6498                         /* Count all modify-header actions as one action. */
6499                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6500                                 ++actions_n;
6501                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6502                                 modify_after_mirror = 1;
6503                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
6504                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
6505                         break;
6506                 case RTE_FLOW_ACTION_TYPE_DROP:
6507                         ret = mlx5_flow_validate_action_drop(action_flags,
6508                                                              attr, error);
6509                         if (ret < 0)
6510                                 return ret;
6511                         action_flags |= MLX5_FLOW_ACTION_DROP;
6512                         ++actions_n;
6513                         break;
6514                 case RTE_FLOW_ACTION_TYPE_QUEUE:
6515                         ret = mlx5_flow_validate_action_queue(actions,
6516                                                               action_flags, dev,
6517                                                               attr, error);
6518                         if (ret < 0)
6519                                 return ret;
6520                         queue_index = ((const struct rte_flow_action_queue *)
6521                                                         (actions->conf))->index;
6522                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
6523                         ++actions_n;
6524                         break;
6525                 case RTE_FLOW_ACTION_TYPE_RSS:
6526                         rss = actions->conf;
6527                         ret = mlx5_flow_validate_action_rss(actions,
6528                                                             action_flags, dev,
6529                                                             attr, item_flags,
6530                                                             error);
6531                         if (ret < 0)
6532                                 return ret;
6533                         if (rss && sample_rss &&
6534                             (sample_rss->level != rss->level ||
6535                             sample_rss->types != rss->types))
6536                                 return rte_flow_error_set(error, ENOTSUP,
6537                                         RTE_FLOW_ERROR_TYPE_ACTION,
6538                                         NULL,
6539                                         "Can't use the different RSS types "
6540                                         "or level in the same flow");
6541                         if (rss != NULL && rss->queue_num)
6542                                 queue_index = rss->queue[0];
6543                         action_flags |= MLX5_FLOW_ACTION_RSS;
6544                         ++actions_n;
6545                         break;
6546                 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
6547                         ret =
6548                         mlx5_flow_validate_action_default_miss(action_flags,
6549                                         attr, error);
6550                         if (ret < 0)
6551                                 return ret;
6552                         action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
6553                         ++actions_n;
6554                         break;
6555                 case RTE_FLOW_ACTION_TYPE_COUNT:
6556                         ret = flow_dv_validate_action_count(dev, actions,
6557                                                             action_flags,
6558                                                             error);
6559                         if (ret < 0)
6560                                 return ret;
6561                         count = actions->conf;
6562                         action_flags |= MLX5_FLOW_ACTION_COUNT;
6563                         ++actions_n;
6564                         break;
6565                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
6566                         if (flow_dv_validate_action_pop_vlan(dev,
6567                                                              action_flags,
6568                                                              actions,
6569                                                              item_flags, attr,
6570                                                              error))
6571                                 return -rte_errno;
6572                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
6573                         ++actions_n;
6574                         break;
6575                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
6576                         ret = flow_dv_validate_action_push_vlan(dev,
6577                                                                 action_flags,
6578                                                                 vlan_m,
6579                                                                 actions, attr,
6580                                                                 error);
6581                         if (ret < 0)
6582                                 return ret;
6583                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
6584                         ++actions_n;
6585                         break;
6586                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
6587                         ret = flow_dv_validate_action_set_vlan_pcp
6588                                                 (action_flags, actions, error);
6589                         if (ret < 0)
6590                                 return ret;
6591                         /* Count PCP with push_vlan command. */
6592                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
6593                         break;
6594                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
6595                         ret = flow_dv_validate_action_set_vlan_vid
6596                                                 (item_flags, action_flags,
6597                                                  actions, error);
6598                         if (ret < 0)
6599                                 return ret;
6600                         /* Count VID with push_vlan command. */
6601                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
6602                         rw_act_num += MLX5_ACT_NUM_MDF_VID;
6603                         break;
6604                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
6605                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
6606                         ret = flow_dv_validate_action_l2_encap(dev,
6607                                                                action_flags,
6608                                                                actions, attr,
6609                                                                error);
6610                         if (ret < 0)
6611                                 return ret;
6612                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
6613                         ++actions_n;
6614                         break;
6615                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
6616                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
6617                         ret = flow_dv_validate_action_decap(dev, action_flags,
6618                                                             actions, item_flags,
6619                                                             attr, error);
6620                         if (ret < 0)
6621                                 return ret;
6622                         action_flags |= MLX5_FLOW_ACTION_DECAP;
6623                         ++actions_n;
6624                         break;
6625                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
6626                         ret = flow_dv_validate_action_raw_encap_decap
6627                                 (dev, NULL, actions->conf, attr, &action_flags,
6628                                  &actions_n, actions, item_flags, error);
6629                         if (ret < 0)
6630                                 return ret;
6631                         break;
6632                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
6633                         decap = actions->conf;
6634                         while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
6635                                 ;
6636                         if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
6637                                 encap = NULL;
6638                                 actions--;
6639                         } else {
6640                                 encap = actions->conf;
6641                         }
6642                         ret = flow_dv_validate_action_raw_encap_decap
6643                                            (dev,
6644                                             decap ? decap : &empty_decap, encap,
6645                                             attr, &action_flags, &actions_n,
6646                                             actions, item_flags, error);
6647                         if (ret < 0)
6648                                 return ret;
6649                         break;
6650                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
6651                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
6652                         ret = flow_dv_validate_action_modify_mac(action_flags,
6653                                                                  actions,
6654                                                                  item_flags,
6655                                                                  error);
6656                         if (ret < 0)
6657                                 return ret;
6658                         /* Count all modify-header actions as one action. */
6659                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6660                                 ++actions_n;
6661                         action_flags |= actions->type ==
6662                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
6663                                                 MLX5_FLOW_ACTION_SET_MAC_SRC :
6664                                                 MLX5_FLOW_ACTION_SET_MAC_DST;
6665                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6666                                 modify_after_mirror = 1;
6667                         /*
6668                          * Even if the source and destination MAC addresses have
6669                          * overlap in the header with 4B alignment, the convert
6670                          * function will handle them separately and 4 SW actions
6671                          * will be created. And 2 actions will be added each
6672                          * time no matter how many bytes of address will be set.
6673                          */
6674                         rw_act_num += MLX5_ACT_NUM_MDF_MAC;
6675                         break;
6676                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
6677                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
6678                         ret = flow_dv_validate_action_modify_ipv4(action_flags,
6679                                                                   actions,
6680                                                                   item_flags,
6681                                                                   error);
6682                         if (ret < 0)
6683                                 return ret;
6684                         /* Count all modify-header actions as one action. */
6685                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6686                                 ++actions_n;
6687                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6688                                 modify_after_mirror = 1;
6689                         action_flags |= actions->type ==
6690                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
6691                                                 MLX5_FLOW_ACTION_SET_IPV4_SRC :
6692                                                 MLX5_FLOW_ACTION_SET_IPV4_DST;
6693                         rw_act_num += MLX5_ACT_NUM_MDF_IPV4;
6694                         break;
6695                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
6696                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
6697                         ret = flow_dv_validate_action_modify_ipv6(action_flags,
6698                                                                   actions,
6699                                                                   item_flags,
6700                                                                   error);
6701                         if (ret < 0)
6702                                 return ret;
6703                         if (item_ipv6_proto == IPPROTO_ICMPV6)
6704                                 return rte_flow_error_set(error, ENOTSUP,
6705                                         RTE_FLOW_ERROR_TYPE_ACTION,
6706                                         actions,
6707                                         "Can't change header "
6708                                         "with ICMPv6 proto");
6709                         /* Count all modify-header actions as one action. */
6710                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6711                                 ++actions_n;
6712                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6713                                 modify_after_mirror = 1;
6714                         action_flags |= actions->type ==
6715                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
6716                                                 MLX5_FLOW_ACTION_SET_IPV6_SRC :
6717                                                 MLX5_FLOW_ACTION_SET_IPV6_DST;
6718                         rw_act_num += MLX5_ACT_NUM_MDF_IPV6;
6719                         break;
6720                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
6721                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
6722                         ret = flow_dv_validate_action_modify_tp(action_flags,
6723                                                                 actions,
6724                                                                 item_flags,
6725                                                                 error);
6726                         if (ret < 0)
6727                                 return ret;
6728                         /* Count all modify-header actions as one action. */
6729                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6730                                 ++actions_n;
6731                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6732                                 modify_after_mirror = 1;
6733                         action_flags |= actions->type ==
6734                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
6735                                                 MLX5_FLOW_ACTION_SET_TP_SRC :
6736                                                 MLX5_FLOW_ACTION_SET_TP_DST;
6737                         rw_act_num += MLX5_ACT_NUM_MDF_PORT;
6738                         break;
6739                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
6740                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
6741                         ret = flow_dv_validate_action_modify_ttl(action_flags,
6742                                                                  actions,
6743                                                                  item_flags,
6744                                                                  error);
6745                         if (ret < 0)
6746                                 return ret;
6747                         /* Count all modify-header actions as one action. */
6748                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6749                                 ++actions_n;
6750                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6751                                 modify_after_mirror = 1;
6752                         action_flags |= actions->type ==
6753                                         RTE_FLOW_ACTION_TYPE_SET_TTL ?
6754                                                 MLX5_FLOW_ACTION_SET_TTL :
6755                                                 MLX5_FLOW_ACTION_DEC_TTL;
6756                         rw_act_num += MLX5_ACT_NUM_MDF_TTL;
6757                         break;
6758                 case RTE_FLOW_ACTION_TYPE_JUMP:
6759                         ret = flow_dv_validate_action_jump(dev, tunnel, actions,
6760                                                            action_flags,
6761                                                            attr, external,
6762                                                            error);
6763                         if (ret)
6764                                 return ret;
6765                         if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) &&
6766                             fdb_mirror_limit)
6767                                 return rte_flow_error_set(error, EINVAL,
6768                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6769                                                   NULL,
6770                                                   "sample and jump action combination is not supported");
6771                         ++actions_n;
6772                         action_flags |= MLX5_FLOW_ACTION_JUMP;
6773                         break;
6774                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
6775                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
6776                         ret = flow_dv_validate_action_modify_tcp_seq
6777                                                                 (action_flags,
6778                                                                  actions,
6779                                                                  item_flags,
6780                                                                  error);
6781                         if (ret < 0)
6782                                 return ret;
6783                         /* Count all modify-header actions as one action. */
6784                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6785                                 ++actions_n;
6786                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6787                                 modify_after_mirror = 1;
6788                         action_flags |= actions->type ==
6789                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
6790                                                 MLX5_FLOW_ACTION_INC_TCP_SEQ :
6791                                                 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
6792                         rw_act_num += MLX5_ACT_NUM_MDF_TCPSEQ;
6793                         break;
6794                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
6795                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
6796                         ret = flow_dv_validate_action_modify_tcp_ack
6797                                                                 (action_flags,
6798                                                                  actions,
6799                                                                  item_flags,
6800                                                                  error);
6801                         if (ret < 0)
6802                                 return ret;
6803                         /* Count all modify-header actions as one action. */
6804                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6805                                 ++actions_n;
6806                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6807                                 modify_after_mirror = 1;
6808                         action_flags |= actions->type ==
6809                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
6810                                                 MLX5_FLOW_ACTION_INC_TCP_ACK :
6811                                                 MLX5_FLOW_ACTION_DEC_TCP_ACK;
6812                         rw_act_num += MLX5_ACT_NUM_MDF_TCPACK;
6813                         break;
6814                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
6815                         break;
6816                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
6817                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
6818                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
6819                         break;
6820                 case RTE_FLOW_ACTION_TYPE_METER:
6821                         ret = mlx5_flow_validate_action_meter(dev,
6822                                                               action_flags,
6823                                                               actions, attr,
6824                                                               error);
6825                         if (ret < 0)
6826                                 return ret;
6827                         action_flags |= MLX5_FLOW_ACTION_METER;
6828                         ++actions_n;
6829                         /* Meter action will add one more TAG action. */
6830                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
6831                         break;
6832                 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
6833                         if (!attr->transfer && !attr->group)
6834                                 return rte_flow_error_set(error, ENOTSUP,
6835                                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6836                                                                            NULL,
6837                           "Shared ASO age action is not supported for group 0");
6838                         action_flags |= MLX5_FLOW_ACTION_AGE;
6839                         ++actions_n;
6840                         break;
6841                 case RTE_FLOW_ACTION_TYPE_AGE:
6842                         ret = flow_dv_validate_action_age(action_flags,
6843                                                           actions, dev,
6844                                                           error);
6845                         if (ret < 0)
6846                                 return ret;
6847                         /*
6848                          * Validate the regular AGE action (using counter)
6849                          * mutual exclusion with share counter actions.
6850                          */
6851                         if (!priv->sh->flow_hit_aso_en) {
6852                                 if (count && count->shared)
6853                                         return rte_flow_error_set
6854                                                 (error, EINVAL,
6855                                                 RTE_FLOW_ERROR_TYPE_ACTION,
6856                                                 NULL,
6857                                                 "old age and shared count combination is not supported");
6858                                 if (sample_count)
6859                                         return rte_flow_error_set
6860                                                 (error, EINVAL,
6861                                                 RTE_FLOW_ERROR_TYPE_ACTION,
6862                                                 NULL,
6863                                                 "old age action and count must be in the same sub flow");
6864                         }
6865                         action_flags |= MLX5_FLOW_ACTION_AGE;
6866                         ++actions_n;
6867                         break;
6868                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
6869                         ret = flow_dv_validate_action_modify_ipv4_dscp
6870                                                          (action_flags,
6871                                                           actions,
6872                                                           item_flags,
6873                                                           error);
6874                         if (ret < 0)
6875                                 return ret;
6876                         /* Count all modify-header actions as one action. */
6877                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6878                                 ++actions_n;
6879                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6880                                 modify_after_mirror = 1;
6881                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
6882                         rw_act_num += MLX5_ACT_NUM_SET_DSCP;
6883                         break;
6884                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
6885                         ret = flow_dv_validate_action_modify_ipv6_dscp
6886                                                                 (action_flags,
6887                                                                  actions,
6888                                                                  item_flags,
6889                                                                  error);
6890                         if (ret < 0)
6891                                 return ret;
6892                         /* Count all modify-header actions as one action. */
6893                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6894                                 ++actions_n;
6895                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6896                                 modify_after_mirror = 1;
6897                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
6898                         rw_act_num += MLX5_ACT_NUM_SET_DSCP;
6899                         break;
6900                 case RTE_FLOW_ACTION_TYPE_SAMPLE:
6901                         ret = flow_dv_validate_action_sample(&action_flags,
6902                                                              actions, dev,
6903                                                              attr, item_flags,
6904                                                              rss, &sample_rss,
6905                                                              &sample_count,
6906                                                              &fdb_mirror_limit,
6907                                                              error);
6908                         if (ret < 0)
6909                                 return ret;
6910                         action_flags |= MLX5_FLOW_ACTION_SAMPLE;
6911                         ++actions_n;
6912                         break;
6913                 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
6914                         if (actions[0].type != (typeof(actions[0].type))
6915                                 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET)
6916                                 return rte_flow_error_set
6917                                                 (error, EINVAL,
6918                                                 RTE_FLOW_ERROR_TYPE_ACTION,
6919                                                 NULL, "MLX5 private action "
6920                                                 "must be the first");
6921
6922                         action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
6923                         break;
6924                 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
6925                         if (!attr->transfer && !attr->group)
6926                                 return rte_flow_error_set(error, ENOTSUP,
6927                                                 RTE_FLOW_ERROR_TYPE_ACTION,
6928                                                 NULL, "modify field action "
6929                                                 "is not supported for group 0");
6930                         ret = flow_dv_validate_action_modify_field(dev,
6931                                                                    action_flags,
6932                                                                    actions,
6933                                                                    error);
6934                         if (ret < 0)
6935                                 return ret;
6936                         /* Count all modify-header actions as one action. */
6937                         if (!(action_flags & MLX5_FLOW_ACTION_MODIFY_FIELD))
6938                                 ++actions_n;
6939                         action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
6940                         rw_act_num += ret;
6941                         break;
6942                 default:
6943                         return rte_flow_error_set(error, ENOTSUP,
6944                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6945                                                   actions,
6946                                                   "action not supported");
6947                 }
6948         }
6949         /*
6950          * Validate actions in flow rules
6951          * - Explicit decap action is prohibited by the tunnel offload API.
6952          * - Drop action in tunnel steer rule is prohibited by the API.
6953          * - Application cannot use MARK action because it's value can mask
6954          *   tunnel default miss nitification.
6955          * - JUMP in tunnel match rule has no support in current PMD
6956          *   implementation.
6957          * - TAG & META are reserved for future uses.
6958          */
6959         if (action_flags & MLX5_FLOW_ACTION_TUNNEL_SET) {
6960                 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_DECAP    |
6961                                             MLX5_FLOW_ACTION_MARK     |
6962                                             MLX5_FLOW_ACTION_SET_TAG  |
6963                                             MLX5_FLOW_ACTION_SET_META |
6964                                             MLX5_FLOW_ACTION_DROP;
6965
6966                 if (action_flags & bad_actions_mask)
6967                         return rte_flow_error_set
6968                                         (error, EINVAL,
6969                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6970                                         "Invalid RTE action in tunnel "
6971                                         "set decap rule");
6972                 if (!(action_flags & MLX5_FLOW_ACTION_JUMP))
6973                         return rte_flow_error_set
6974                                         (error, EINVAL,
6975                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6976                                         "tunnel set decap rule must terminate "
6977                                         "with JUMP");
6978                 if (!attr->ingress)
6979                         return rte_flow_error_set
6980                                         (error, EINVAL,
6981                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6982                                         "tunnel flows for ingress traffic only");
6983         }
6984         if (action_flags & MLX5_FLOW_ACTION_TUNNEL_MATCH) {
6985                 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_JUMP    |
6986                                             MLX5_FLOW_ACTION_MARK    |
6987                                             MLX5_FLOW_ACTION_SET_TAG |
6988                                             MLX5_FLOW_ACTION_SET_META;
6989
6990                 if (action_flags & bad_actions_mask)
6991                         return rte_flow_error_set
6992                                         (error, EINVAL,
6993                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6994                                         "Invalid RTE action in tunnel "
6995                                         "set match rule");
6996         }
6997         /*
6998          * Validate the drop action mutual exclusion with other actions.
6999          * Drop action is mutually-exclusive with any other action, except for
7000          * Count action.
7001          * Drop action compatibility with tunnel offload was already validated.
7002          */
7003         if (action_flags & (MLX5_FLOW_ACTION_TUNNEL_MATCH |
7004                             MLX5_FLOW_ACTION_TUNNEL_MATCH));
7005         else if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
7006             (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
7007                 return rte_flow_error_set(error, EINVAL,
7008                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7009                                           "Drop action is mutually-exclusive "
7010                                           "with any other action, except for "
7011                                           "Count action");
7012         /* Eswitch has few restrictions on using items and actions */
7013         if (attr->transfer) {
7014                 if (!mlx5_flow_ext_mreg_supported(dev) &&
7015                     action_flags & MLX5_FLOW_ACTION_FLAG)
7016                         return rte_flow_error_set(error, ENOTSUP,
7017                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7018                                                   NULL,
7019                                                   "unsupported action FLAG");
7020                 if (!mlx5_flow_ext_mreg_supported(dev) &&
7021                     action_flags & MLX5_FLOW_ACTION_MARK)
7022                         return rte_flow_error_set(error, ENOTSUP,
7023                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7024                                                   NULL,
7025                                                   "unsupported action MARK");
7026                 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
7027                         return rte_flow_error_set(error, ENOTSUP,
7028                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7029                                                   NULL,
7030                                                   "unsupported action QUEUE");
7031                 if (action_flags & MLX5_FLOW_ACTION_RSS)
7032                         return rte_flow_error_set(error, ENOTSUP,
7033                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7034                                                   NULL,
7035                                                   "unsupported action RSS");
7036                 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
7037                         return rte_flow_error_set(error, EINVAL,
7038                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7039                                                   actions,
7040                                                   "no fate action is found");
7041         } else {
7042                 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
7043                         return rte_flow_error_set(error, EINVAL,
7044                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7045                                                   actions,
7046                                                   "no fate action is found");
7047         }
7048         /*
7049          * Continue validation for Xcap and VLAN actions.
7050          * If hairpin is working in explicit TX rule mode, there is no actions
7051          * splitting and the validation of hairpin ingress flow should be the
7052          * same as other standard flows.
7053          */
7054         if ((action_flags & (MLX5_FLOW_XCAP_ACTIONS |
7055                              MLX5_FLOW_VLAN_ACTIONS)) &&
7056             (queue_index == 0xFFFF ||
7057              mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN ||
7058              ((conf = mlx5_rxq_get_hairpin_conf(dev, queue_index)) != NULL &&
7059              conf->tx_explicit != 0))) {
7060                 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
7061                     MLX5_FLOW_XCAP_ACTIONS)
7062                         return rte_flow_error_set(error, ENOTSUP,
7063                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7064                                                   NULL, "encap and decap "
7065                                                   "combination aren't supported");
7066                 if (!attr->transfer && attr->ingress) {
7067                         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
7068                                 return rte_flow_error_set
7069                                                 (error, ENOTSUP,
7070                                                  RTE_FLOW_ERROR_TYPE_ACTION,
7071                                                  NULL, "encap is not supported"
7072                                                  " for ingress traffic");
7073                         else if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
7074                                 return rte_flow_error_set
7075                                                 (error, ENOTSUP,
7076                                                  RTE_FLOW_ERROR_TYPE_ACTION,
7077                                                  NULL, "push VLAN action not "
7078                                                  "supported for ingress");
7079                         else if ((action_flags & MLX5_FLOW_VLAN_ACTIONS) ==
7080                                         MLX5_FLOW_VLAN_ACTIONS)
7081                                 return rte_flow_error_set
7082                                                 (error, ENOTSUP,
7083                                                  RTE_FLOW_ERROR_TYPE_ACTION,
7084                                                  NULL, "no support for "
7085                                                  "multiple VLAN actions");
7086                 }
7087         }
7088         /*
7089          * Hairpin flow will add one more TAG action in TX implicit mode.
7090          * In TX explicit mode, there will be no hairpin flow ID.
7091          */
7092         if (hairpin > 0)
7093                 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7094         /* extra metadata enabled: one more TAG action will be add. */
7095         if (dev_conf->dv_flow_en &&
7096             dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
7097             mlx5_flow_ext_mreg_supported(dev))
7098                 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7099         if (rw_act_num >
7100                         flow_dv_modify_hdr_action_max(dev, is_root)) {
7101                 return rte_flow_error_set(error, ENOTSUP,
7102                                           RTE_FLOW_ERROR_TYPE_ACTION,
7103                                           NULL, "too many header modify"
7104                                           " actions to support");
7105         }
7106         /* Eswitch egress mirror and modify flow has limitation on CX5 */
7107         if (fdb_mirror_limit && modify_after_mirror)
7108                 return rte_flow_error_set(error, EINVAL,
7109                                 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7110                                 "sample before modify action is not supported");
7111         return 0;
7112 }
7113
7114 /**
7115  * Internal preparation function. Allocates the DV flow size,
7116  * this size is constant.
7117  *
7118  * @param[in] dev
7119  *   Pointer to the rte_eth_dev structure.
7120  * @param[in] attr
7121  *   Pointer to the flow attributes.
7122  * @param[in] items
7123  *   Pointer to the list of items.
7124  * @param[in] actions
7125  *   Pointer to the list of actions.
7126  * @param[out] error
7127  *   Pointer to the error structure.
7128  *
7129  * @return
7130  *   Pointer to mlx5_flow object on success,
7131  *   otherwise NULL and rte_errno is set.
7132  */
7133 static struct mlx5_flow *
7134 flow_dv_prepare(struct rte_eth_dev *dev,
7135                 const struct rte_flow_attr *attr __rte_unused,
7136                 const struct rte_flow_item items[] __rte_unused,
7137                 const struct rte_flow_action actions[] __rte_unused,
7138                 struct rte_flow_error *error)
7139 {
7140         uint32_t handle_idx = 0;
7141         struct mlx5_flow *dev_flow;
7142         struct mlx5_flow_handle *dev_handle;
7143         struct mlx5_priv *priv = dev->data->dev_private;
7144         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
7145
7146         MLX5_ASSERT(wks);
7147         /* In case of corrupting the memory. */
7148         if (wks->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
7149                 rte_flow_error_set(error, ENOSPC,
7150                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7151                                    "not free temporary device flow");
7152                 return NULL;
7153         }
7154         dev_handle = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
7155                                    &handle_idx);
7156         if (!dev_handle) {
7157                 rte_flow_error_set(error, ENOMEM,
7158                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7159                                    "not enough memory to create flow handle");
7160                 return NULL;
7161         }
7162         MLX5_ASSERT(wks->flow_idx < RTE_DIM(wks->flows));
7163         dev_flow = &wks->flows[wks->flow_idx++];
7164         memset(dev_flow, 0, sizeof(*dev_flow));
7165         dev_flow->handle = dev_handle;
7166         dev_flow->handle_idx = handle_idx;
7167         /*
7168          * In some old rdma-core releases, before continuing, a check of the
7169          * length of matching parameter will be done at first. It needs to use
7170          * the length without misc4 param. If the flow has misc4 support, then
7171          * the length needs to be adjusted accordingly. Each param member is
7172          * aligned with a 64B boundary naturally.
7173          */
7174         dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param) -
7175                                   MLX5_ST_SZ_BYTES(fte_match_set_misc4);
7176         dev_flow->ingress = attr->ingress;
7177         dev_flow->dv.transfer = attr->transfer;
7178         return dev_flow;
7179 }
7180
7181 #ifdef RTE_LIBRTE_MLX5_DEBUG
7182 /**
7183  * Sanity check for match mask and value. Similar to check_valid_spec() in
7184  * kernel driver. If unmasked bit is present in value, it returns failure.
7185  *
7186  * @param match_mask
7187  *   pointer to match mask buffer.
7188  * @param match_value
7189  *   pointer to match value buffer.
7190  *
7191  * @return
7192  *   0 if valid, -EINVAL otherwise.
7193  */
7194 static int
7195 flow_dv_check_valid_spec(void *match_mask, void *match_value)
7196 {
7197         uint8_t *m = match_mask;
7198         uint8_t *v = match_value;
7199         unsigned int i;
7200
7201         for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
7202                 if (v[i] & ~m[i]) {
7203                         DRV_LOG(ERR,
7204                                 "match_value differs from match_criteria"
7205                                 " %p[%u] != %p[%u]",
7206                                 match_value, i, match_mask, i);
7207                         return -EINVAL;
7208                 }
7209         }
7210         return 0;
7211 }
7212 #endif
7213
7214 /**
7215  * Add match of ip_version.
7216  *
7217  * @param[in] group
7218  *   Flow group.
7219  * @param[in] headers_v
7220  *   Values header pointer.
7221  * @param[in] headers_m
7222  *   Masks header pointer.
7223  * @param[in] ip_version
7224  *   The IP version to set.
7225  */
7226 static inline void
7227 flow_dv_set_match_ip_version(uint32_t group,
7228                              void *headers_v,
7229                              void *headers_m,
7230                              uint8_t ip_version)
7231 {
7232         if (group == 0)
7233                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
7234         else
7235                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version,
7236                          ip_version);
7237         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, ip_version);
7238         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, 0);
7239         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype, 0);
7240 }
7241
7242 /**
7243  * Add Ethernet item to matcher and to the value.
7244  *
7245  * @param[in, out] matcher
7246  *   Flow matcher.
7247  * @param[in, out] key
7248  *   Flow matcher value.
7249  * @param[in] item
7250  *   Flow pattern to translate.
7251  * @param[in] inner
7252  *   Item is inner pattern.
7253  */
7254 static void
7255 flow_dv_translate_item_eth(void *matcher, void *key,
7256                            const struct rte_flow_item *item, int inner,
7257                            uint32_t group)
7258 {
7259         const struct rte_flow_item_eth *eth_m = item->mask;
7260         const struct rte_flow_item_eth *eth_v = item->spec;
7261         const struct rte_flow_item_eth nic_mask = {
7262                 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
7263                 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
7264                 .type = RTE_BE16(0xffff),
7265                 .has_vlan = 0,
7266         };
7267         void *hdrs_m;
7268         void *hdrs_v;
7269         char *l24_v;
7270         unsigned int i;
7271
7272         if (!eth_v)
7273                 return;
7274         if (!eth_m)
7275                 eth_m = &nic_mask;
7276         if (inner) {
7277                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7278                                          inner_headers);
7279                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7280         } else {
7281                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7282                                          outer_headers);
7283                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7284         }
7285         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, dmac_47_16),
7286                &eth_m->dst, sizeof(eth_m->dst));
7287         /* The value must be in the range of the mask. */
7288         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, dmac_47_16);
7289         for (i = 0; i < sizeof(eth_m->dst); ++i)
7290                 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
7291         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, smac_47_16),
7292                &eth_m->src, sizeof(eth_m->src));
7293         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, smac_47_16);
7294         /* The value must be in the range of the mask. */
7295         for (i = 0; i < sizeof(eth_m->dst); ++i)
7296                 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
7297         /*
7298          * HW supports match on one Ethertype, the Ethertype following the last
7299          * VLAN tag of the packet (see PRM).
7300          * Set match on ethertype only if ETH header is not followed by VLAN.
7301          * HW is optimized for IPv4/IPv6. In such cases, avoid setting
7302          * ethertype, and use ip_version field instead.
7303          * eCPRI over Ether layer will use type value 0xAEFE.
7304          */
7305         if (eth_m->type == 0xFFFF) {
7306                 /* Set cvlan_tag mask for any single\multi\un-tagged case. */
7307                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
7308                 switch (eth_v->type) {
7309                 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
7310                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
7311                         return;
7312                 case RTE_BE16(RTE_ETHER_TYPE_QINQ):
7313                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
7314                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
7315                         return;
7316                 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
7317                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
7318                         return;
7319                 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
7320                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
7321                         return;
7322                 default:
7323                         break;
7324                 }
7325         }
7326         if (eth_m->has_vlan) {
7327                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
7328                 if (eth_v->has_vlan) {
7329                         /*
7330                          * Here, when also has_more_vlan field in VLAN item is
7331                          * not set, only single-tagged packets will be matched.
7332                          */
7333                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
7334                         return;
7335                 }
7336         }
7337         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
7338                  rte_be_to_cpu_16(eth_m->type));
7339         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, ethertype);
7340         *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
7341 }
7342
7343 /**
7344  * Add VLAN item to matcher and to the value.
7345  *
7346  * @param[in, out] dev_flow
7347  *   Flow descriptor.
7348  * @param[in, out] matcher
7349  *   Flow matcher.
7350  * @param[in, out] key
7351  *   Flow matcher value.
7352  * @param[in] item
7353  *   Flow pattern to translate.
7354  * @param[in] inner
7355  *   Item is inner pattern.
7356  */
7357 static void
7358 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
7359                             void *matcher, void *key,
7360                             const struct rte_flow_item *item,
7361                             int inner, uint32_t group)
7362 {
7363         const struct rte_flow_item_vlan *vlan_m = item->mask;
7364         const struct rte_flow_item_vlan *vlan_v = item->spec;
7365         void *hdrs_m;
7366         void *hdrs_v;
7367         uint16_t tci_m;
7368         uint16_t tci_v;
7369
7370         if (inner) {
7371                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7372                                          inner_headers);
7373                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7374         } else {
7375                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7376                                          outer_headers);
7377                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7378                 /*
7379                  * This is workaround, masks are not supported,
7380                  * and pre-validated.
7381                  */
7382                 if (vlan_v)
7383                         dev_flow->handle->vf_vlan.tag =
7384                                         rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
7385         }
7386         /*
7387          * When VLAN item exists in flow, mark packet as tagged,
7388          * even if TCI is not specified.
7389          */
7390         if (!MLX5_GET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag)) {
7391                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
7392                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
7393         }
7394         if (!vlan_v)
7395                 return;
7396         if (!vlan_m)
7397                 vlan_m = &rte_flow_item_vlan_mask;
7398         tci_m = rte_be_to_cpu_16(vlan_m->tci);
7399         tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
7400         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_vid, tci_m);
7401         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_vid, tci_v);
7402         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_cfi, tci_m >> 12);
7403         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_cfi, tci_v >> 12);
7404         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_prio, tci_m >> 13);
7405         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_prio, tci_v >> 13);
7406         /*
7407          * HW is optimized for IPv4/IPv6. In such cases, avoid setting
7408          * ethertype, and use ip_version field instead.
7409          */
7410         if (vlan_m->inner_type == 0xFFFF) {
7411                 switch (vlan_v->inner_type) {
7412                 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
7413                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
7414                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
7415                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
7416                         return;
7417                 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
7418                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
7419                         return;
7420                 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
7421                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
7422                         return;
7423                 default:
7424                         break;
7425                 }
7426         }
7427         if (vlan_m->has_more_vlan && vlan_v->has_more_vlan) {
7428                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
7429                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
7430                 /* Only one vlan_tag bit can be set. */
7431                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
7432                 return;
7433         }
7434         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
7435                  rte_be_to_cpu_16(vlan_m->inner_type));
7436         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, ethertype,
7437                  rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
7438 }
7439
7440 /**
7441  * Add IPV4 item to matcher and to the value.
7442  *
7443  * @param[in, out] matcher
7444  *   Flow matcher.
7445  * @param[in, out] key
7446  *   Flow matcher value.
7447  * @param[in] item
7448  *   Flow pattern to translate.
7449  * @param[in] inner
7450  *   Item is inner pattern.
7451  * @param[in] group
7452  *   The group to insert the rule.
7453  */
7454 static void
7455 flow_dv_translate_item_ipv4(void *matcher, void *key,
7456                             const struct rte_flow_item *item,
7457                             int inner, uint32_t group)
7458 {
7459         const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
7460         const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
7461         const struct rte_flow_item_ipv4 nic_mask = {
7462                 .hdr = {
7463                         .src_addr = RTE_BE32(0xffffffff),
7464                         .dst_addr = RTE_BE32(0xffffffff),
7465                         .type_of_service = 0xff,
7466                         .next_proto_id = 0xff,
7467                         .time_to_live = 0xff,
7468                 },
7469         };
7470         void *headers_m;
7471         void *headers_v;
7472         char *l24_m;
7473         char *l24_v;
7474         uint8_t tos;
7475
7476         if (inner) {
7477                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7478                                          inner_headers);
7479                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7480         } else {
7481                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7482                                          outer_headers);
7483                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7484         }
7485         flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
7486         if (!ipv4_v)
7487                 return;
7488         if (!ipv4_m)
7489                 ipv4_m = &nic_mask;
7490         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
7491                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
7492         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
7493                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
7494         *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
7495         *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
7496         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
7497                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
7498         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
7499                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
7500         *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
7501         *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
7502         tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
7503         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
7504                  ipv4_m->hdr.type_of_service);
7505         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
7506         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
7507                  ipv4_m->hdr.type_of_service >> 2);
7508         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
7509         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
7510                  ipv4_m->hdr.next_proto_id);
7511         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
7512                  ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
7513         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
7514                  ipv4_m->hdr.time_to_live);
7515         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
7516                  ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
7517         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
7518                  !!(ipv4_m->hdr.fragment_offset));
7519         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
7520                  !!(ipv4_v->hdr.fragment_offset & ipv4_m->hdr.fragment_offset));
7521 }
7522
7523 /**
7524  * Add IPV6 item to matcher and to the value.
7525  *
7526  * @param[in, out] matcher
7527  *   Flow matcher.
7528  * @param[in, out] key
7529  *   Flow matcher value.
7530  * @param[in] item
7531  *   Flow pattern to translate.
7532  * @param[in] inner
7533  *   Item is inner pattern.
7534  * @param[in] group
7535  *   The group to insert the rule.
7536  */
7537 static void
7538 flow_dv_translate_item_ipv6(void *matcher, void *key,
7539                             const struct rte_flow_item *item,
7540                             int inner, uint32_t group)
7541 {
7542         const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
7543         const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
7544         const struct rte_flow_item_ipv6 nic_mask = {
7545                 .hdr = {
7546                         .src_addr =
7547                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
7548                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
7549                         .dst_addr =
7550                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
7551                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
7552                         .vtc_flow = RTE_BE32(0xffffffff),
7553                         .proto = 0xff,
7554                         .hop_limits = 0xff,
7555                 },
7556         };
7557         void *headers_m;
7558         void *headers_v;
7559         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7560         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7561         char *l24_m;
7562         char *l24_v;
7563         uint32_t vtc_m;
7564         uint32_t vtc_v;
7565         int i;
7566         int size;
7567
7568         if (inner) {
7569                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7570                                          inner_headers);
7571                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7572         } else {
7573                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7574                                          outer_headers);
7575                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7576         }
7577         flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
7578         if (!ipv6_v)
7579                 return;
7580         if (!ipv6_m)
7581                 ipv6_m = &nic_mask;
7582         size = sizeof(ipv6_m->hdr.dst_addr);
7583         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
7584                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
7585         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
7586                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
7587         memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
7588         for (i = 0; i < size; ++i)
7589                 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
7590         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
7591                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
7592         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
7593                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
7594         memcpy(l24_m, ipv6_m->hdr.src_addr, size);
7595         for (i = 0; i < size; ++i)
7596                 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
7597         /* TOS. */
7598         vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
7599         vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
7600         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
7601         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
7602         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
7603         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
7604         /* Label. */
7605         if (inner) {
7606                 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
7607                          vtc_m);
7608                 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
7609                          vtc_v);
7610         } else {
7611                 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
7612                          vtc_m);
7613                 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
7614                          vtc_v);
7615         }
7616         /* Protocol. */
7617         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
7618                  ipv6_m->hdr.proto);
7619         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
7620                  ipv6_v->hdr.proto & ipv6_m->hdr.proto);
7621         /* Hop limit. */
7622         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
7623                  ipv6_m->hdr.hop_limits);
7624         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
7625                  ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
7626         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
7627                  !!(ipv6_m->has_frag_ext));
7628         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
7629                  !!(ipv6_v->has_frag_ext & ipv6_m->has_frag_ext));
7630 }
7631
7632 /**
7633  * Add IPV6 fragment extension item to matcher and to the value.
7634  *
7635  * @param[in, out] matcher
7636  *   Flow matcher.
7637  * @param[in, out] key
7638  *   Flow matcher value.
7639  * @param[in] item
7640  *   Flow pattern to translate.
7641  * @param[in] inner
7642  *   Item is inner pattern.
7643  */
7644 static void
7645 flow_dv_translate_item_ipv6_frag_ext(void *matcher, void *key,
7646                                      const struct rte_flow_item *item,
7647                                      int inner)
7648 {
7649         const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_m = item->mask;
7650         const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_v = item->spec;
7651         const struct rte_flow_item_ipv6_frag_ext nic_mask = {
7652                 .hdr = {
7653                         .next_header = 0xff,
7654                         .frag_data = RTE_BE16(0xffff),
7655                 },
7656         };
7657         void *headers_m;
7658         void *headers_v;
7659
7660         if (inner) {
7661                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7662                                          inner_headers);
7663                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7664         } else {
7665                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7666                                          outer_headers);
7667                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7668         }
7669         /* IPv6 fragment extension item exists, so packet is IP fragment. */
7670         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
7671         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 1);
7672         if (!ipv6_frag_ext_v)
7673                 return;
7674         if (!ipv6_frag_ext_m)
7675                 ipv6_frag_ext_m = &nic_mask;
7676         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
7677                  ipv6_frag_ext_m->hdr.next_header);
7678         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
7679                  ipv6_frag_ext_v->hdr.next_header &
7680                  ipv6_frag_ext_m->hdr.next_header);
7681 }
7682
7683 /**
7684  * Add TCP item to matcher and to the value.
7685  *
7686  * @param[in, out] matcher
7687  *   Flow matcher.
7688  * @param[in, out] key
7689  *   Flow matcher value.
7690  * @param[in] item
7691  *   Flow pattern to translate.
7692  * @param[in] inner
7693  *   Item is inner pattern.
7694  */
7695 static void
7696 flow_dv_translate_item_tcp(void *matcher, void *key,
7697                            const struct rte_flow_item *item,
7698                            int inner)
7699 {
7700         const struct rte_flow_item_tcp *tcp_m = item->mask;
7701         const struct rte_flow_item_tcp *tcp_v = item->spec;
7702         void *headers_m;
7703         void *headers_v;
7704
7705         if (inner) {
7706                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7707                                          inner_headers);
7708                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7709         } else {
7710                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7711                                          outer_headers);
7712                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7713         }
7714         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7715         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
7716         if (!tcp_v)
7717                 return;
7718         if (!tcp_m)
7719                 tcp_m = &rte_flow_item_tcp_mask;
7720         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
7721                  rte_be_to_cpu_16(tcp_m->hdr.src_port));
7722         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
7723                  rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
7724         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
7725                  rte_be_to_cpu_16(tcp_m->hdr.dst_port));
7726         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
7727                  rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
7728         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
7729                  tcp_m->hdr.tcp_flags);
7730         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
7731                  (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
7732 }
7733
7734 /**
7735  * Add UDP item to matcher and to the value.
7736  *
7737  * @param[in, out] matcher
7738  *   Flow matcher.
7739  * @param[in, out] key
7740  *   Flow matcher value.
7741  * @param[in] item
7742  *   Flow pattern to translate.
7743  * @param[in] inner
7744  *   Item is inner pattern.
7745  */
7746 static void
7747 flow_dv_translate_item_udp(void *matcher, void *key,
7748                            const struct rte_flow_item *item,
7749                            int inner)
7750 {
7751         const struct rte_flow_item_udp *udp_m = item->mask;
7752         const struct rte_flow_item_udp *udp_v = item->spec;
7753         void *headers_m;
7754         void *headers_v;
7755
7756         if (inner) {
7757                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7758                                          inner_headers);
7759                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7760         } else {
7761                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7762                                          outer_headers);
7763                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7764         }
7765         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7766         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
7767         if (!udp_v)
7768                 return;
7769         if (!udp_m)
7770                 udp_m = &rte_flow_item_udp_mask;
7771         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
7772                  rte_be_to_cpu_16(udp_m->hdr.src_port));
7773         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
7774                  rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
7775         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
7776                  rte_be_to_cpu_16(udp_m->hdr.dst_port));
7777         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
7778                  rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
7779 }
7780
7781 /**
7782  * Add GRE optional Key item to matcher and to the value.
7783  *
7784  * @param[in, out] matcher
7785  *   Flow matcher.
7786  * @param[in, out] key
7787  *   Flow matcher value.
7788  * @param[in] item
7789  *   Flow pattern to translate.
7790  * @param[in] inner
7791  *   Item is inner pattern.
7792  */
7793 static void
7794 flow_dv_translate_item_gre_key(void *matcher, void *key,
7795                                    const struct rte_flow_item *item)
7796 {
7797         const rte_be32_t *key_m = item->mask;
7798         const rte_be32_t *key_v = item->spec;
7799         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7800         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7801         rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
7802
7803         /* GRE K bit must be on and should already be validated */
7804         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
7805         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
7806         if (!key_v)
7807                 return;
7808         if (!key_m)
7809                 key_m = &gre_key_default_mask;
7810         MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
7811                  rte_be_to_cpu_32(*key_m) >> 8);
7812         MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
7813                  rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
7814         MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
7815                  rte_be_to_cpu_32(*key_m) & 0xFF);
7816         MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
7817                  rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
7818 }
7819
7820 /**
7821  * Add GRE item to matcher and to the value.
7822  *
7823  * @param[in, out] matcher
7824  *   Flow matcher.
7825  * @param[in, out] key
7826  *   Flow matcher value.
7827  * @param[in] item
7828  *   Flow pattern to translate.
7829  * @param[in] inner
7830  *   Item is inner pattern.
7831  */
7832 static void
7833 flow_dv_translate_item_gre(void *matcher, void *key,
7834                            const struct rte_flow_item *item,
7835                            int inner)
7836 {
7837         const struct rte_flow_item_gre *gre_m = item->mask;
7838         const struct rte_flow_item_gre *gre_v = item->spec;
7839         void *headers_m;
7840         void *headers_v;
7841         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7842         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7843         struct {
7844                 union {
7845                         __extension__
7846                         struct {
7847                                 uint16_t version:3;
7848                                 uint16_t rsvd0:9;
7849                                 uint16_t s_present:1;
7850                                 uint16_t k_present:1;
7851                                 uint16_t rsvd_bit1:1;
7852                                 uint16_t c_present:1;
7853                         };
7854                         uint16_t value;
7855                 };
7856         } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
7857
7858         if (inner) {
7859                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7860                                          inner_headers);
7861                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7862         } else {
7863                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7864                                          outer_headers);
7865                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7866         }
7867         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7868         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
7869         if (!gre_v)
7870                 return;
7871         if (!gre_m)
7872                 gre_m = &rte_flow_item_gre_mask;
7873         MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
7874                  rte_be_to_cpu_16(gre_m->protocol));
7875         MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
7876                  rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
7877         gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
7878         gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
7879         MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
7880                  gre_crks_rsvd0_ver_m.c_present);
7881         MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
7882                  gre_crks_rsvd0_ver_v.c_present &
7883                  gre_crks_rsvd0_ver_m.c_present);
7884         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
7885                  gre_crks_rsvd0_ver_m.k_present);
7886         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
7887                  gre_crks_rsvd0_ver_v.k_present &
7888                  gre_crks_rsvd0_ver_m.k_present);
7889         MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
7890                  gre_crks_rsvd0_ver_m.s_present);
7891         MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
7892                  gre_crks_rsvd0_ver_v.s_present &
7893                  gre_crks_rsvd0_ver_m.s_present);
7894 }
7895
7896 /**
7897  * Add NVGRE item to matcher and to the value.
7898  *
7899  * @param[in, out] matcher
7900  *   Flow matcher.
7901  * @param[in, out] key
7902  *   Flow matcher value.
7903  * @param[in] item
7904  *   Flow pattern to translate.
7905  * @param[in] inner
7906  *   Item is inner pattern.
7907  */
7908 static void
7909 flow_dv_translate_item_nvgre(void *matcher, void *key,
7910                              const struct rte_flow_item *item,
7911                              int inner)
7912 {
7913         const struct rte_flow_item_nvgre *nvgre_m = item->mask;
7914         const struct rte_flow_item_nvgre *nvgre_v = item->spec;
7915         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7916         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7917         const char *tni_flow_id_m;
7918         const char *tni_flow_id_v;
7919         char *gre_key_m;
7920         char *gre_key_v;
7921         int size;
7922         int i;
7923
7924         /* For NVGRE, GRE header fields must be set with defined values. */
7925         const struct rte_flow_item_gre gre_spec = {
7926                 .c_rsvd0_ver = RTE_BE16(0x2000),
7927                 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
7928         };
7929         const struct rte_flow_item_gre gre_mask = {
7930                 .c_rsvd0_ver = RTE_BE16(0xB000),
7931                 .protocol = RTE_BE16(UINT16_MAX),
7932         };
7933         const struct rte_flow_item gre_item = {
7934                 .spec = &gre_spec,
7935                 .mask = &gre_mask,
7936                 .last = NULL,
7937         };
7938         flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
7939         if (!nvgre_v)
7940                 return;
7941         if (!nvgre_m)
7942                 nvgre_m = &rte_flow_item_nvgre_mask;
7943         tni_flow_id_m = (const char *)nvgre_m->tni;
7944         tni_flow_id_v = (const char *)nvgre_v->tni;
7945         size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
7946         gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
7947         gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
7948         memcpy(gre_key_m, tni_flow_id_m, size);
7949         for (i = 0; i < size; ++i)
7950                 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
7951 }
7952
7953 /**
7954  * Add VXLAN item to matcher and to the value.
7955  *
7956  * @param[in, out] matcher
7957  *   Flow matcher.
7958  * @param[in, out] key
7959  *   Flow matcher value.
7960  * @param[in] item
7961  *   Flow pattern to translate.
7962  * @param[in] inner
7963  *   Item is inner pattern.
7964  */
7965 static void
7966 flow_dv_translate_item_vxlan(void *matcher, void *key,
7967                              const struct rte_flow_item *item,
7968                              int inner)
7969 {
7970         const struct rte_flow_item_vxlan *vxlan_m = item->mask;
7971         const struct rte_flow_item_vxlan *vxlan_v = item->spec;
7972         void *headers_m;
7973         void *headers_v;
7974         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7975         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7976         char *vni_m;
7977         char *vni_v;
7978         uint16_t dport;
7979         int size;
7980         int i;
7981
7982         if (inner) {
7983                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7984                                          inner_headers);
7985                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7986         } else {
7987                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7988                                          outer_headers);
7989                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7990         }
7991         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
7992                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
7993         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7994                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7995                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7996         }
7997         if (!vxlan_v)
7998                 return;
7999         if (!vxlan_m)
8000                 vxlan_m = &rte_flow_item_vxlan_mask;
8001         size = sizeof(vxlan_m->vni);
8002         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
8003         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
8004         memcpy(vni_m, vxlan_m->vni, size);
8005         for (i = 0; i < size; ++i)
8006                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
8007 }
8008
8009 /**
8010  * Add VXLAN-GPE item to matcher and to the value.
8011  *
8012  * @param[in, out] matcher
8013  *   Flow matcher.
8014  * @param[in, out] key
8015  *   Flow matcher value.
8016  * @param[in] item
8017  *   Flow pattern to translate.
8018  * @param[in] inner
8019  *   Item is inner pattern.
8020  */
8021
8022 static void
8023 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
8024                                  const struct rte_flow_item *item, int inner)
8025 {
8026         const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
8027         const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
8028         void *headers_m;
8029         void *headers_v;
8030         void *misc_m =
8031                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
8032         void *misc_v =
8033                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8034         char *vni_m;
8035         char *vni_v;
8036         uint16_t dport;
8037         int size;
8038         int i;
8039         uint8_t flags_m = 0xff;
8040         uint8_t flags_v = 0xc;
8041
8042         if (inner) {
8043                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8044                                          inner_headers);
8045                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8046         } else {
8047                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8048                                          outer_headers);
8049                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8050         }
8051         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
8052                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
8053         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8054                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8055                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8056         }
8057         if (!vxlan_v)
8058                 return;
8059         if (!vxlan_m)
8060                 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
8061         size = sizeof(vxlan_m->vni);
8062         vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
8063         vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
8064         memcpy(vni_m, vxlan_m->vni, size);
8065         for (i = 0; i < size; ++i)
8066                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
8067         if (vxlan_m->flags) {
8068                 flags_m = vxlan_m->flags;
8069                 flags_v = vxlan_v->flags;
8070         }
8071         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
8072         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
8073         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
8074                  vxlan_m->protocol);
8075         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
8076                  vxlan_v->protocol);
8077 }
8078
8079 /**
8080  * Add Geneve item to matcher and to the value.
8081  *
8082  * @param[in, out] matcher
8083  *   Flow matcher.
8084  * @param[in, out] key
8085  *   Flow matcher value.
8086  * @param[in] item
8087  *   Flow pattern to translate.
8088  * @param[in] inner
8089  *   Item is inner pattern.
8090  */
8091
8092 static void
8093 flow_dv_translate_item_geneve(void *matcher, void *key,
8094                               const struct rte_flow_item *item, int inner)
8095 {
8096         const struct rte_flow_item_geneve *geneve_m = item->mask;
8097         const struct rte_flow_item_geneve *geneve_v = item->spec;
8098         void *headers_m;
8099         void *headers_v;
8100         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8101         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8102         uint16_t dport;
8103         uint16_t gbhdr_m;
8104         uint16_t gbhdr_v;
8105         char *vni_m;
8106         char *vni_v;
8107         size_t size, i;
8108
8109         if (inner) {
8110                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8111                                          inner_headers);
8112                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8113         } else {
8114                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8115                                          outer_headers);
8116                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8117         }
8118         dport = MLX5_UDP_PORT_GENEVE;
8119         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8120                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8121                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8122         }
8123         if (!geneve_v)
8124                 return;
8125         if (!geneve_m)
8126                 geneve_m = &rte_flow_item_geneve_mask;
8127         size = sizeof(geneve_m->vni);
8128         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
8129         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
8130         memcpy(vni_m, geneve_m->vni, size);
8131         for (i = 0; i < size; ++i)
8132                 vni_v[i] = vni_m[i] & geneve_v->vni[i];
8133         MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
8134                  rte_be_to_cpu_16(geneve_m->protocol));
8135         MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
8136                  rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
8137         gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
8138         gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
8139         MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
8140                  MLX5_GENEVE_OAMF_VAL(gbhdr_m));
8141         MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
8142                  MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
8143         MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
8144                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
8145         MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
8146                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
8147                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
8148 }
8149
8150 /**
8151  * Create Geneve TLV option resource.
8152  *
8153  * @param dev[in, out]
8154  *   Pointer to rte_eth_dev structure.
8155  * @param[in, out] tag_be24
8156  *   Tag value in big endian then R-shift 8.
8157  * @parm[in, out] dev_flow
8158  *   Pointer to the dev_flow.
8159  * @param[out] error
8160  *   pointer to error structure.
8161  *
8162  * @return
8163  *   0 on success otherwise -errno and errno is set.
8164  */
8165
8166 int
8167 flow_dev_geneve_tlv_option_resource_register(struct rte_eth_dev *dev,
8168                                              const struct rte_flow_item *item,
8169                                              struct rte_flow_error *error)
8170 {
8171         struct mlx5_priv *priv = dev->data->dev_private;
8172         struct mlx5_dev_ctx_shared *sh = priv->sh;
8173         struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
8174                         sh->geneve_tlv_option_resource;
8175         struct mlx5_devx_obj *obj;
8176         const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
8177         int ret = 0;
8178
8179         if (!geneve_opt_v)
8180                 return -1;
8181         rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
8182         if (geneve_opt_resource != NULL) {
8183                 if (geneve_opt_resource->option_class ==
8184                         geneve_opt_v->option_class &&
8185                         geneve_opt_resource->option_type ==
8186                         geneve_opt_v->option_type &&
8187                         geneve_opt_resource->length ==
8188                         geneve_opt_v->option_len) {
8189                         /* We already have GENVE TLV option obj allocated. */
8190                         __atomic_fetch_add(&geneve_opt_resource->refcnt, 1,
8191                                            __ATOMIC_RELAXED);
8192                 } else {
8193                         ret = rte_flow_error_set(error, ENOMEM,
8194                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8195                                 "Only one GENEVE TLV option supported");
8196                         goto exit;
8197                 }
8198         } else {
8199                 /* Create a GENEVE TLV object and resource. */
8200                 obj = mlx5_devx_cmd_create_geneve_tlv_option(sh->ctx,
8201                                 geneve_opt_v->option_class,
8202                                 geneve_opt_v->option_type,
8203                                 geneve_opt_v->option_len);
8204                 if (!obj) {
8205                         ret = rte_flow_error_set(error, ENODATA,
8206                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8207                                 "Failed to create GENEVE TLV Devx object");
8208                         goto exit;
8209                 }
8210                 sh->geneve_tlv_option_resource =
8211                                 mlx5_malloc(MLX5_MEM_ZERO,
8212                                                 sizeof(*geneve_opt_resource),
8213                                                 0, SOCKET_ID_ANY);
8214                 if (!sh->geneve_tlv_option_resource) {
8215                         claim_zero(mlx5_devx_cmd_destroy(obj));
8216                         ret = rte_flow_error_set(error, ENOMEM,
8217                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8218                                 "GENEVE TLV object memory allocation failed");
8219                         goto exit;
8220                 }
8221                 geneve_opt_resource = sh->geneve_tlv_option_resource;
8222                 geneve_opt_resource->obj = obj;
8223                 geneve_opt_resource->option_class = geneve_opt_v->option_class;
8224                 geneve_opt_resource->option_type = geneve_opt_v->option_type;
8225                 geneve_opt_resource->length = geneve_opt_v->option_len;
8226                 __atomic_store_n(&geneve_opt_resource->refcnt, 1,
8227                                 __ATOMIC_RELAXED);
8228         }
8229 exit:
8230         rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
8231         return ret;
8232 }
8233
8234 /**
8235  * Add Geneve TLV option item to matcher.
8236  *
8237  * @param[in, out] dev
8238  *   Pointer to rte_eth_dev structure.
8239  * @param[in, out] matcher
8240  *   Flow matcher.
8241  * @param[in, out] key
8242  *   Flow matcher value.
8243  * @param[in] item
8244  *   Flow pattern to translate.
8245  * @param[out] error
8246  *   Pointer to error structure.
8247  */
8248 static int
8249 flow_dv_translate_item_geneve_opt(struct rte_eth_dev *dev, void *matcher,
8250                                   void *key, const struct rte_flow_item *item,
8251                                   struct rte_flow_error *error)
8252 {
8253         const struct rte_flow_item_geneve_opt *geneve_opt_m = item->mask;
8254         const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
8255         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8256         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8257         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8258                         misc_parameters_3);
8259         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8260         rte_be32_t opt_data_key = 0, opt_data_mask = 0;
8261         int ret = 0;
8262
8263         if (!geneve_opt_v)
8264                 return -1;
8265         if (!geneve_opt_m)
8266                 geneve_opt_m = &rte_flow_item_geneve_opt_mask;
8267         ret = flow_dev_geneve_tlv_option_resource_register(dev, item,
8268                                                            error);
8269         if (ret) {
8270                 DRV_LOG(ERR, "Failed to create geneve_tlv_obj");
8271                 return ret;
8272         }
8273         /*
8274          * Set the option length in GENEVE header if not requested.
8275          * The GENEVE TLV option length is expressed by the option length field
8276          * in the GENEVE header.
8277          * If the option length was not requested but the GENEVE TLV option item
8278          * is present we set the option length field implicitly.
8279          */
8280         if (!MLX5_GET16(fte_match_set_misc, misc_m, geneve_opt_len)) {
8281                 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
8282                          MLX5_GENEVE_OPTLEN_MASK);
8283                 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
8284                          geneve_opt_v->option_len + 1);
8285         }
8286         /* Set the data. */
8287         if (geneve_opt_v->data) {
8288                 memcpy(&opt_data_key, geneve_opt_v->data,
8289                         RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
8290                                 sizeof(opt_data_key)));
8291                 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
8292                                 sizeof(opt_data_key));
8293                 memcpy(&opt_data_mask, geneve_opt_m->data,
8294                         RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
8295                                 sizeof(opt_data_mask)));
8296                 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
8297                                 sizeof(opt_data_mask));
8298                 MLX5_SET(fte_match_set_misc3, misc3_m,
8299                                 geneve_tlv_option_0_data,
8300                                 rte_be_to_cpu_32(opt_data_mask));
8301                 MLX5_SET(fte_match_set_misc3, misc3_v,
8302                                 geneve_tlv_option_0_data,
8303                         rte_be_to_cpu_32(opt_data_key & opt_data_mask));
8304         }
8305         return ret;
8306 }
8307
8308 /**
8309  * Add MPLS item to matcher and to the value.
8310  *
8311  * @param[in, out] matcher
8312  *   Flow matcher.
8313  * @param[in, out] key
8314  *   Flow matcher value.
8315  * @param[in] item
8316  *   Flow pattern to translate.
8317  * @param[in] prev_layer
8318  *   The protocol layer indicated in previous item.
8319  * @param[in] inner
8320  *   Item is inner pattern.
8321  */
8322 static void
8323 flow_dv_translate_item_mpls(void *matcher, void *key,
8324                             const struct rte_flow_item *item,
8325                             uint64_t prev_layer,
8326                             int inner)
8327 {
8328         const uint32_t *in_mpls_m = item->mask;
8329         const uint32_t *in_mpls_v = item->spec;
8330         uint32_t *out_mpls_m = 0;
8331         uint32_t *out_mpls_v = 0;
8332         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8333         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8334         void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
8335                                      misc_parameters_2);
8336         void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
8337         void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
8338         void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8339
8340         switch (prev_layer) {
8341         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
8342                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
8343                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
8344                          MLX5_UDP_PORT_MPLS);
8345                 break;
8346         case MLX5_FLOW_LAYER_GRE:
8347                 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
8348                 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
8349                          RTE_ETHER_TYPE_MPLS);
8350                 break;
8351         default:
8352                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
8353                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8354                          IPPROTO_MPLS);
8355                 break;
8356         }
8357         if (!in_mpls_v)
8358                 return;
8359         if (!in_mpls_m)
8360                 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
8361         switch (prev_layer) {
8362         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
8363                 out_mpls_m =
8364                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
8365                                                  outer_first_mpls_over_udp);
8366                 out_mpls_v =
8367                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
8368                                                  outer_first_mpls_over_udp);
8369                 break;
8370         case MLX5_FLOW_LAYER_GRE:
8371                 out_mpls_m =
8372                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
8373                                                  outer_first_mpls_over_gre);
8374                 out_mpls_v =
8375                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
8376                                                  outer_first_mpls_over_gre);
8377                 break;
8378         default:
8379                 /* Inner MPLS not over GRE is not supported. */
8380                 if (!inner) {
8381                         out_mpls_m =
8382                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
8383                                                          misc2_m,
8384                                                          outer_first_mpls);
8385                         out_mpls_v =
8386                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
8387                                                          misc2_v,
8388                                                          outer_first_mpls);
8389                 }
8390                 break;
8391         }
8392         if (out_mpls_m && out_mpls_v) {
8393                 *out_mpls_m = *in_mpls_m;
8394                 *out_mpls_v = *in_mpls_v & *in_mpls_m;
8395         }
8396 }
8397
8398 /**
8399  * Add metadata register item to matcher
8400  *
8401  * @param[in, out] matcher
8402  *   Flow matcher.
8403  * @param[in, out] key
8404  *   Flow matcher value.
8405  * @param[in] reg_type
8406  *   Type of device metadata register
8407  * @param[in] value
8408  *   Register value
8409  * @param[in] mask
8410  *   Register mask
8411  */
8412 static void
8413 flow_dv_match_meta_reg(void *matcher, void *key,
8414                        enum modify_reg reg_type,
8415                        uint32_t data, uint32_t mask)
8416 {
8417         void *misc2_m =
8418                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
8419         void *misc2_v =
8420                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
8421         uint32_t temp;
8422
8423         data &= mask;
8424         switch (reg_type) {
8425         case REG_A:
8426                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
8427                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
8428                 break;
8429         case REG_B:
8430                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
8431                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
8432                 break;
8433         case REG_C_0:
8434                 /*
8435                  * The metadata register C0 field might be divided into
8436                  * source vport index and META item value, we should set
8437                  * this field according to specified mask, not as whole one.
8438                  */
8439                 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
8440                 temp |= mask;
8441                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
8442                 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
8443                 temp &= ~mask;
8444                 temp |= data;
8445                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
8446                 break;
8447         case REG_C_1:
8448                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
8449                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
8450                 break;
8451         case REG_C_2:
8452                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
8453                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
8454                 break;
8455         case REG_C_3:
8456                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
8457                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
8458                 break;
8459         case REG_C_4:
8460                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
8461                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
8462                 break;
8463         case REG_C_5:
8464                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
8465                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
8466                 break;
8467         case REG_C_6:
8468                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
8469                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
8470                 break;
8471         case REG_C_7:
8472                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
8473                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
8474                 break;
8475         default:
8476                 MLX5_ASSERT(false);
8477                 break;
8478         }
8479 }
8480
8481 /**
8482  * Add MARK item to matcher
8483  *
8484  * @param[in] dev
8485  *   The device to configure through.
8486  * @param[in, out] matcher
8487  *   Flow matcher.
8488  * @param[in, out] key
8489  *   Flow matcher value.
8490  * @param[in] item
8491  *   Flow pattern to translate.
8492  */
8493 static void
8494 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
8495                             void *matcher, void *key,
8496                             const struct rte_flow_item *item)
8497 {
8498         struct mlx5_priv *priv = dev->data->dev_private;
8499         const struct rte_flow_item_mark *mark;
8500         uint32_t value;
8501         uint32_t mask;
8502
8503         mark = item->mask ? (const void *)item->mask :
8504                             &rte_flow_item_mark_mask;
8505         mask = mark->id & priv->sh->dv_mark_mask;
8506         mark = (const void *)item->spec;
8507         MLX5_ASSERT(mark);
8508         value = mark->id & priv->sh->dv_mark_mask & mask;
8509         if (mask) {
8510                 enum modify_reg reg;
8511
8512                 /* Get the metadata register index for the mark. */
8513                 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
8514                 MLX5_ASSERT(reg > 0);
8515                 if (reg == REG_C_0) {
8516                         struct mlx5_priv *priv = dev->data->dev_private;
8517                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
8518                         uint32_t shl_c0 = rte_bsf32(msk_c0);
8519
8520                         mask &= msk_c0;
8521                         mask <<= shl_c0;
8522                         value <<= shl_c0;
8523                 }
8524                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
8525         }
8526 }
8527
8528 /**
8529  * Add META item to matcher
8530  *
8531  * @param[in] dev
8532  *   The devich to configure through.
8533  * @param[in, out] matcher
8534  *   Flow matcher.
8535  * @param[in, out] key
8536  *   Flow matcher value.
8537  * @param[in] attr
8538  *   Attributes of flow that includes this item.
8539  * @param[in] item
8540  *   Flow pattern to translate.
8541  */
8542 static void
8543 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
8544                             void *matcher, void *key,
8545                             const struct rte_flow_attr *attr,
8546                             const struct rte_flow_item *item)
8547 {
8548         const struct rte_flow_item_meta *meta_m;
8549         const struct rte_flow_item_meta *meta_v;
8550
8551         meta_m = (const void *)item->mask;
8552         if (!meta_m)
8553                 meta_m = &rte_flow_item_meta_mask;
8554         meta_v = (const void *)item->spec;
8555         if (meta_v) {
8556                 int reg;
8557                 uint32_t value = meta_v->data;
8558                 uint32_t mask = meta_m->data;
8559
8560                 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
8561                 if (reg < 0)
8562                         return;
8563                 MLX5_ASSERT(reg != REG_NON);
8564                 /*
8565                  * In datapath code there is no endianness
8566                  * coversions for perfromance reasons, all
8567                  * pattern conversions are done in rte_flow.
8568                  */
8569                 value = rte_cpu_to_be_32(value);
8570                 mask = rte_cpu_to_be_32(mask);
8571                 if (reg == REG_C_0) {
8572                         struct mlx5_priv *priv = dev->data->dev_private;
8573                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
8574                         uint32_t shl_c0 = rte_bsf32(msk_c0);
8575 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
8576                         uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
8577
8578                         value >>= shr_c0;
8579                         mask >>= shr_c0;
8580 #endif
8581                         value <<= shl_c0;
8582                         mask <<= shl_c0;
8583                         MLX5_ASSERT(msk_c0);
8584                         MLX5_ASSERT(!(~msk_c0 & mask));
8585                 }
8586                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
8587         }
8588 }
8589
8590 /**
8591  * Add vport metadata Reg C0 item to matcher
8592  *
8593  * @param[in, out] matcher
8594  *   Flow matcher.
8595  * @param[in, out] key
8596  *   Flow matcher value.
8597  * @param[in] reg
8598  *   Flow pattern to translate.
8599  */
8600 static void
8601 flow_dv_translate_item_meta_vport(void *matcher, void *key,
8602                                   uint32_t value, uint32_t mask)
8603 {
8604         flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
8605 }
8606
8607 /**
8608  * Add tag item to matcher
8609  *
8610  * @param[in] dev
8611  *   The devich to configure through.
8612  * @param[in, out] matcher
8613  *   Flow matcher.
8614  * @param[in, out] key
8615  *   Flow matcher value.
8616  * @param[in] item
8617  *   Flow pattern to translate.
8618  */
8619 static void
8620 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
8621                                 void *matcher, void *key,
8622                                 const struct rte_flow_item *item)
8623 {
8624         const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
8625         const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
8626         uint32_t mask, value;
8627
8628         MLX5_ASSERT(tag_v);
8629         value = tag_v->data;
8630         mask = tag_m ? tag_m->data : UINT32_MAX;
8631         if (tag_v->id == REG_C_0) {
8632                 struct mlx5_priv *priv = dev->data->dev_private;
8633                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
8634                 uint32_t shl_c0 = rte_bsf32(msk_c0);
8635
8636                 mask &= msk_c0;
8637                 mask <<= shl_c0;
8638                 value <<= shl_c0;
8639         }
8640         flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
8641 }
8642
8643 /**
8644  * Add TAG item to matcher
8645  *
8646  * @param[in] dev
8647  *   The devich to configure through.
8648  * @param[in, out] matcher
8649  *   Flow matcher.
8650  * @param[in, out] key
8651  *   Flow matcher value.
8652  * @param[in] item
8653  *   Flow pattern to translate.
8654  */
8655 static void
8656 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
8657                            void *matcher, void *key,
8658                            const struct rte_flow_item *item)
8659 {
8660         const struct rte_flow_item_tag *tag_v = item->spec;
8661         const struct rte_flow_item_tag *tag_m = item->mask;
8662         enum modify_reg reg;
8663
8664         MLX5_ASSERT(tag_v);
8665         tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
8666         /* Get the metadata register index for the tag. */
8667         reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
8668         MLX5_ASSERT(reg > 0);
8669         flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
8670 }
8671
8672 /**
8673  * Add source vport match to the specified matcher.
8674  *
8675  * @param[in, out] matcher
8676  *   Flow matcher.
8677  * @param[in, out] key
8678  *   Flow matcher value.
8679  * @param[in] port
8680  *   Source vport value to match
8681  * @param[in] mask
8682  *   Mask
8683  */
8684 static void
8685 flow_dv_translate_item_source_vport(void *matcher, void *key,
8686                                     int16_t port, uint16_t mask)
8687 {
8688         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8689         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8690
8691         MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
8692         MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
8693 }
8694
8695 /**
8696  * Translate port-id item to eswitch match on  port-id.
8697  *
8698  * @param[in] dev
8699  *   The devich to configure through.
8700  * @param[in, out] matcher
8701  *   Flow matcher.
8702  * @param[in, out] key
8703  *   Flow matcher value.
8704  * @param[in] item
8705  *   Flow pattern to translate.
8706  * @param[in]
8707  *   Flow attributes.
8708  *
8709  * @return
8710  *   0 on success, a negative errno value otherwise.
8711  */
8712 static int
8713 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
8714                                void *key, const struct rte_flow_item *item,
8715                                const struct rte_flow_attr *attr)
8716 {
8717         const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
8718         const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
8719         struct mlx5_priv *priv;
8720         uint16_t mask, id;
8721
8722         mask = pid_m ? pid_m->id : 0xffff;
8723         id = pid_v ? pid_v->id : dev->data->port_id;
8724         priv = mlx5_port_to_eswitch_info(id, item == NULL);
8725         if (!priv)
8726                 return -rte_errno;
8727         /*
8728          * Translate to vport field or to metadata, depending on mode.
8729          * Kernel can use either misc.source_port or half of C0 metadata
8730          * register.
8731          */
8732         if (priv->vport_meta_mask) {
8733                 /*
8734                  * Provide the hint for SW steering library
8735                  * to insert the flow into ingress domain and
8736                  * save the extra vport match.
8737                  */
8738                 if (mask == 0xffff && priv->vport_id == 0xffff &&
8739                     priv->pf_bond < 0 && attr->transfer)
8740                         flow_dv_translate_item_source_vport
8741                                 (matcher, key, priv->vport_id, mask);
8742                 /*
8743                  * We should always set the vport metadata register,
8744                  * otherwise the SW steering library can drop
8745                  * the rule if wire vport metadata value is not zero,
8746                  * it depends on kernel configuration.
8747                  */
8748                 flow_dv_translate_item_meta_vport(matcher, key,
8749                                                   priv->vport_meta_tag,
8750                                                   priv->vport_meta_mask);
8751         } else {
8752                 flow_dv_translate_item_source_vport(matcher, key,
8753                                                     priv->vport_id, mask);
8754         }
8755         return 0;
8756 }
8757
8758 /**
8759  * Add ICMP6 item to matcher and to the value.
8760  *
8761  * @param[in, out] matcher
8762  *   Flow matcher.
8763  * @param[in, out] key
8764  *   Flow matcher value.
8765  * @param[in] item
8766  *   Flow pattern to translate.
8767  * @param[in] inner
8768  *   Item is inner pattern.
8769  */
8770 static void
8771 flow_dv_translate_item_icmp6(void *matcher, void *key,
8772                               const struct rte_flow_item *item,
8773                               int inner)
8774 {
8775         const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
8776         const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
8777         void *headers_m;
8778         void *headers_v;
8779         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8780                                      misc_parameters_3);
8781         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8782         if (inner) {
8783                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8784                                          inner_headers);
8785                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8786         } else {
8787                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8788                                          outer_headers);
8789                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8790         }
8791         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
8792         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
8793         if (!icmp6_v)
8794                 return;
8795         if (!icmp6_m)
8796                 icmp6_m = &rte_flow_item_icmp6_mask;
8797         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
8798         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
8799                  icmp6_v->type & icmp6_m->type);
8800         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
8801         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
8802                  icmp6_v->code & icmp6_m->code);
8803 }
8804
8805 /**
8806  * Add ICMP item to matcher and to the value.
8807  *
8808  * @param[in, out] matcher
8809  *   Flow matcher.
8810  * @param[in, out] key
8811  *   Flow matcher value.
8812  * @param[in] item
8813  *   Flow pattern to translate.
8814  * @param[in] inner
8815  *   Item is inner pattern.
8816  */
8817 static void
8818 flow_dv_translate_item_icmp(void *matcher, void *key,
8819                             const struct rte_flow_item *item,
8820                             int inner)
8821 {
8822         const struct rte_flow_item_icmp *icmp_m = item->mask;
8823         const struct rte_flow_item_icmp *icmp_v = item->spec;
8824         uint32_t icmp_header_data_m = 0;
8825         uint32_t icmp_header_data_v = 0;
8826         void *headers_m;
8827         void *headers_v;
8828         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8829                                      misc_parameters_3);
8830         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8831         if (inner) {
8832                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8833                                          inner_headers);
8834                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8835         } else {
8836                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8837                                          outer_headers);
8838                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8839         }
8840         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
8841         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
8842         if (!icmp_v)
8843                 return;
8844         if (!icmp_m)
8845                 icmp_m = &rte_flow_item_icmp_mask;
8846         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
8847                  icmp_m->hdr.icmp_type);
8848         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
8849                  icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
8850         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
8851                  icmp_m->hdr.icmp_code);
8852         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
8853                  icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
8854         icmp_header_data_m = rte_be_to_cpu_16(icmp_m->hdr.icmp_seq_nb);
8855         icmp_header_data_m |= rte_be_to_cpu_16(icmp_m->hdr.icmp_ident) << 16;
8856         if (icmp_header_data_m) {
8857                 icmp_header_data_v = rte_be_to_cpu_16(icmp_v->hdr.icmp_seq_nb);
8858                 icmp_header_data_v |=
8859                          rte_be_to_cpu_16(icmp_v->hdr.icmp_ident) << 16;
8860                 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_header_data,
8861                          icmp_header_data_m);
8862                 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_header_data,
8863                          icmp_header_data_v & icmp_header_data_m);
8864         }
8865 }
8866
8867 /**
8868  * Add GTP item to matcher and to the value.
8869  *
8870  * @param[in, out] matcher
8871  *   Flow matcher.
8872  * @param[in, out] key
8873  *   Flow matcher value.
8874  * @param[in] item
8875  *   Flow pattern to translate.
8876  * @param[in] inner
8877  *   Item is inner pattern.
8878  */
8879 static void
8880 flow_dv_translate_item_gtp(void *matcher, void *key,
8881                            const struct rte_flow_item *item, int inner)
8882 {
8883         const struct rte_flow_item_gtp *gtp_m = item->mask;
8884         const struct rte_flow_item_gtp *gtp_v = item->spec;
8885         void *headers_m;
8886         void *headers_v;
8887         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8888                                      misc_parameters_3);
8889         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8890         uint16_t dport = RTE_GTPU_UDP_PORT;
8891
8892         if (inner) {
8893                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8894                                          inner_headers);
8895                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8896         } else {
8897                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8898                                          outer_headers);
8899                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8900         }
8901         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8902                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8903                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8904         }
8905         if (!gtp_v)
8906                 return;
8907         if (!gtp_m)
8908                 gtp_m = &rte_flow_item_gtp_mask;
8909         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags,
8910                  gtp_m->v_pt_rsv_flags);
8911         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags,
8912                  gtp_v->v_pt_rsv_flags & gtp_m->v_pt_rsv_flags);
8913         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
8914         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
8915                  gtp_v->msg_type & gtp_m->msg_type);
8916         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
8917                  rte_be_to_cpu_32(gtp_m->teid));
8918         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
8919                  rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
8920 }
8921
8922 /**
8923  * Add GTP PSC item to matcher.
8924  *
8925  * @param[in, out] matcher
8926  *   Flow matcher.
8927  * @param[in, out] key
8928  *   Flow matcher value.
8929  * @param[in] item
8930  *   Flow pattern to translate.
8931  */
8932 static int
8933 flow_dv_translate_item_gtp_psc(void *matcher, void *key,
8934                                const struct rte_flow_item *item)
8935 {
8936         const struct rte_flow_item_gtp_psc *gtp_psc_m = item->mask;
8937         const struct rte_flow_item_gtp_psc *gtp_psc_v = item->spec;
8938         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8939                         misc_parameters_3);
8940         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8941         union {
8942                 uint32_t w32;
8943                 struct {
8944                         uint16_t seq_num;
8945                         uint8_t npdu_num;
8946                         uint8_t next_ext_header_type;
8947                 };
8948         } dw_2;
8949         uint8_t gtp_flags;
8950
8951         /* Always set E-flag match on one, regardless of GTP item settings. */
8952         gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_m, gtpu_msg_flags);
8953         gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
8954         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags, gtp_flags);
8955         gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_v, gtpu_msg_flags);
8956         gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
8957         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags, gtp_flags);
8958         /*Set next extension header type. */
8959         dw_2.seq_num = 0;
8960         dw_2.npdu_num = 0;
8961         dw_2.next_ext_header_type = 0xff;
8962         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_dw_2,
8963                  rte_cpu_to_be_32(dw_2.w32));
8964         dw_2.seq_num = 0;
8965         dw_2.npdu_num = 0;
8966         dw_2.next_ext_header_type = 0x85;
8967         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_dw_2,
8968                  rte_cpu_to_be_32(dw_2.w32));
8969         if (gtp_psc_v) {
8970                 union {
8971                         uint32_t w32;
8972                         struct {
8973                                 uint8_t len;
8974                                 uint8_t type_flags;
8975                                 uint8_t qfi;
8976                                 uint8_t reserved;
8977                         };
8978                 } dw_0;
8979
8980                 /*Set extension header PDU type and Qos. */
8981                 if (!gtp_psc_m)
8982                         gtp_psc_m = &rte_flow_item_gtp_psc_mask;
8983                 dw_0.w32 = 0;
8984                 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_m->pdu_type);
8985                 dw_0.qfi = gtp_psc_m->qfi;
8986                 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_first_ext_dw_0,
8987                          rte_cpu_to_be_32(dw_0.w32));
8988                 dw_0.w32 = 0;
8989                 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_v->pdu_type &
8990                                                         gtp_psc_m->pdu_type);
8991                 dw_0.qfi = gtp_psc_v->qfi & gtp_psc_m->qfi;
8992                 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_first_ext_dw_0,
8993                          rte_cpu_to_be_32(dw_0.w32));
8994         }
8995         return 0;
8996 }
8997
8998 /**
8999  * Add eCPRI item to matcher and to the value.
9000  *
9001  * @param[in] dev
9002  *   The devich to configure through.
9003  * @param[in, out] matcher
9004  *   Flow matcher.
9005  * @param[in, out] key
9006  *   Flow matcher value.
9007  * @param[in] item
9008  *   Flow pattern to translate.
9009  * @param[in] samples
9010  *   Sample IDs to be used in the matching.
9011  */
9012 static void
9013 flow_dv_translate_item_ecpri(struct rte_eth_dev *dev, void *matcher,
9014                              void *key, const struct rte_flow_item *item)
9015 {
9016         struct mlx5_priv *priv = dev->data->dev_private;
9017         const struct rte_flow_item_ecpri *ecpri_m = item->mask;
9018         const struct rte_flow_item_ecpri *ecpri_v = item->spec;
9019         struct rte_ecpri_common_hdr common;
9020         void *misc4_m = MLX5_ADDR_OF(fte_match_param, matcher,
9021                                      misc_parameters_4);
9022         void *misc4_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_4);
9023         uint32_t *samples;
9024         void *dw_m;
9025         void *dw_v;
9026
9027         if (!ecpri_v)
9028                 return;
9029         if (!ecpri_m)
9030                 ecpri_m = &rte_flow_item_ecpri_mask;
9031         /*
9032          * Maximal four DW samples are supported in a single matching now.
9033          * Two are used now for a eCPRI matching:
9034          * 1. Type: one byte, mask should be 0x00ff0000 in network order
9035          * 2. ID of a message: one or two bytes, mask 0xffff0000 or 0xff000000
9036          *    if any.
9037          */
9038         if (!ecpri_m->hdr.common.u32)
9039                 return;
9040         samples = priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0].ids;
9041         /* Need to take the whole DW as the mask to fill the entry. */
9042         dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
9043                             prog_sample_field_value_0);
9044         dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
9045                             prog_sample_field_value_0);
9046         /* Already big endian (network order) in the header. */
9047         *(uint32_t *)dw_m = ecpri_m->hdr.common.u32;
9048         *(uint32_t *)dw_v = ecpri_v->hdr.common.u32 & ecpri_m->hdr.common.u32;
9049         /* Sample#0, used for matching type, offset 0. */
9050         MLX5_SET(fte_match_set_misc4, misc4_m,
9051                  prog_sample_field_id_0, samples[0]);
9052         /* It makes no sense to set the sample ID in the mask field. */
9053         MLX5_SET(fte_match_set_misc4, misc4_v,
9054                  prog_sample_field_id_0, samples[0]);
9055         /*
9056          * Checking if message body part needs to be matched.
9057          * Some wildcard rules only matching type field should be supported.
9058          */
9059         if (ecpri_m->hdr.dummy[0]) {
9060                 common.u32 = rte_be_to_cpu_32(ecpri_v->hdr.common.u32);
9061                 switch (common.type) {
9062                 case RTE_ECPRI_MSG_TYPE_IQ_DATA:
9063                 case RTE_ECPRI_MSG_TYPE_RTC_CTRL:
9064                 case RTE_ECPRI_MSG_TYPE_DLY_MSR:
9065                         dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
9066                                             prog_sample_field_value_1);
9067                         dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
9068                                             prog_sample_field_value_1);
9069                         *(uint32_t *)dw_m = ecpri_m->hdr.dummy[0];
9070                         *(uint32_t *)dw_v = ecpri_v->hdr.dummy[0] &
9071                                             ecpri_m->hdr.dummy[0];
9072                         /* Sample#1, to match message body, offset 4. */
9073                         MLX5_SET(fte_match_set_misc4, misc4_m,
9074                                  prog_sample_field_id_1, samples[1]);
9075                         MLX5_SET(fte_match_set_misc4, misc4_v,
9076                                  prog_sample_field_id_1, samples[1]);
9077                         break;
9078                 default:
9079                         /* Others, do not match any sample ID. */
9080                         break;
9081                 }
9082         }
9083 }
9084
9085 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
9086
9087 #define HEADER_IS_ZERO(match_criteria, headers)                              \
9088         !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers),     \
9089                  matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
9090
9091 /**
9092  * Calculate flow matcher enable bitmap.
9093  *
9094  * @param match_criteria
9095  *   Pointer to flow matcher criteria.
9096  *
9097  * @return
9098  *   Bitmap of enabled fields.
9099  */
9100 static uint8_t
9101 flow_dv_matcher_enable(uint32_t *match_criteria)
9102 {
9103         uint8_t match_criteria_enable;
9104
9105         match_criteria_enable =
9106                 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
9107                 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
9108         match_criteria_enable |=
9109                 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
9110                 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
9111         match_criteria_enable |=
9112                 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
9113                 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
9114         match_criteria_enable |=
9115                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
9116                 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
9117         match_criteria_enable |=
9118                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
9119                 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
9120         match_criteria_enable |=
9121                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_4)) <<
9122                 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT;
9123         return match_criteria_enable;
9124 }
9125
9126 struct mlx5_hlist_entry *
9127 flow_dv_tbl_create_cb(struct mlx5_hlist *list, uint64_t key64, void *cb_ctx)
9128 {
9129         struct mlx5_dev_ctx_shared *sh = list->ctx;
9130         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9131         struct rte_eth_dev *dev = ctx->dev;
9132         struct mlx5_flow_tbl_data_entry *tbl_data;
9133         struct mlx5_flow_tbl_tunnel_prm *tt_prm = ctx->data;
9134         struct rte_flow_error *error = ctx->error;
9135         union mlx5_flow_tbl_key key = { .v64 = key64 };
9136         struct mlx5_flow_tbl_resource *tbl;
9137         void *domain;
9138         uint32_t idx = 0;
9139         int ret;
9140
9141         tbl_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
9142         if (!tbl_data) {
9143                 rte_flow_error_set(error, ENOMEM,
9144                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9145                                    NULL,
9146                                    "cannot allocate flow table data entry");
9147                 return NULL;
9148         }
9149         tbl_data->idx = idx;
9150         tbl_data->tunnel = tt_prm->tunnel;
9151         tbl_data->group_id = tt_prm->group_id;
9152         tbl_data->external = !!tt_prm->external;
9153         tbl_data->tunnel_offload = is_tunnel_offload_active(dev);
9154         tbl_data->is_egress = !!key.direction;
9155         tbl_data->is_transfer = !!key.domain;
9156         tbl_data->dummy = !!key.dummy;
9157         tbl_data->table_id = key.table_id;
9158         tbl = &tbl_data->tbl;
9159         if (key.dummy)
9160                 return &tbl_data->entry;
9161         if (key.domain)
9162                 domain = sh->fdb_domain;
9163         else if (key.direction)
9164                 domain = sh->tx_domain;
9165         else
9166                 domain = sh->rx_domain;
9167         ret = mlx5_flow_os_create_flow_tbl(domain, key.table_id, &tbl->obj);
9168         if (ret) {
9169                 rte_flow_error_set(error, ENOMEM,
9170                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9171                                    NULL, "cannot create flow table object");
9172                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
9173                 return NULL;
9174         }
9175         if (key.table_id) {
9176                 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
9177                                         (tbl->obj, &tbl_data->jump.action);
9178                 if (ret) {
9179                         rte_flow_error_set(error, ENOMEM,
9180                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9181                                            NULL,
9182                                            "cannot create flow jump action");
9183                         mlx5_flow_os_destroy_flow_tbl(tbl->obj);
9184                         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
9185                         return NULL;
9186                 }
9187         }
9188         MKSTR(matcher_name, "%s_%s_%u_matcher_cache",
9189               key.domain ? "FDB" : "NIC", key.direction ? "egress" : "ingress",
9190               key.table_id);
9191         mlx5_cache_list_init(&tbl_data->matchers, matcher_name, 0, sh,
9192                              flow_dv_matcher_create_cb,
9193                              flow_dv_matcher_match_cb,
9194                              flow_dv_matcher_remove_cb);
9195         return &tbl_data->entry;
9196 }
9197
9198 int
9199 flow_dv_tbl_match_cb(struct mlx5_hlist *list __rte_unused,
9200                      struct mlx5_hlist_entry *entry, uint64_t key64,
9201                      void *cb_ctx __rte_unused)
9202 {
9203         struct mlx5_flow_tbl_data_entry *tbl_data =
9204                 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
9205         union mlx5_flow_tbl_key key = { .v64 = key64 };
9206
9207         return tbl_data->table_id != key.table_id ||
9208                tbl_data->dummy != key.dummy ||
9209                tbl_data->is_transfer != key.domain ||
9210                tbl_data->is_egress != key.direction;
9211 }
9212
9213 /**
9214  * Get a flow table.
9215  *
9216  * @param[in, out] dev
9217  *   Pointer to rte_eth_dev structure.
9218  * @param[in] table_id
9219  *   Table id to use.
9220  * @param[in] egress
9221  *   Direction of the table.
9222  * @param[in] transfer
9223  *   E-Switch or NIC flow.
9224  * @param[in] dummy
9225  *   Dummy entry for dv API.
9226  * @param[out] error
9227  *   pointer to error structure.
9228  *
9229  * @return
9230  *   Returns tables resource based on the index, NULL in case of failed.
9231  */
9232 struct mlx5_flow_tbl_resource *
9233 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
9234                          uint32_t table_id, uint8_t egress,
9235                          uint8_t transfer,
9236                          bool external,
9237                          const struct mlx5_flow_tunnel *tunnel,
9238                          uint32_t group_id, uint8_t dummy,
9239                          struct rte_flow_error *error)
9240 {
9241         struct mlx5_priv *priv = dev->data->dev_private;
9242         union mlx5_flow_tbl_key table_key = {
9243                 {
9244                         .table_id = table_id,
9245                         .dummy = dummy,
9246                         .domain = !!transfer,
9247                         .direction = !!egress,
9248                 }
9249         };
9250         struct mlx5_flow_tbl_tunnel_prm tt_prm = {
9251                 .tunnel = tunnel,
9252                 .group_id = group_id,
9253                 .external = external,
9254         };
9255         struct mlx5_flow_cb_ctx ctx = {
9256                 .dev = dev,
9257                 .error = error,
9258                 .data = &tt_prm,
9259         };
9260         struct mlx5_hlist_entry *entry;
9261         struct mlx5_flow_tbl_data_entry *tbl_data;
9262
9263         entry = mlx5_hlist_register(priv->sh->flow_tbls, table_key.v64, &ctx);
9264         if (!entry) {
9265                 rte_flow_error_set(error, ENOMEM,
9266                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9267                                    "cannot get table");
9268                 return NULL;
9269         }
9270         DRV_LOG(DEBUG, "Table_id %u tunnel %u group %u registered.",
9271                 table_id, tunnel ? tunnel->tunnel_id : 0, group_id);
9272         tbl_data = container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
9273         return &tbl_data->tbl;
9274 }
9275
9276 void
9277 flow_dv_tbl_remove_cb(struct mlx5_hlist *list,
9278                       struct mlx5_hlist_entry *entry)
9279 {
9280         struct mlx5_dev_ctx_shared *sh = list->ctx;
9281         struct mlx5_flow_tbl_data_entry *tbl_data =
9282                 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
9283
9284         MLX5_ASSERT(entry && sh);
9285         if (tbl_data->jump.action)
9286                 mlx5_flow_os_destroy_flow_action(tbl_data->jump.action);
9287         if (tbl_data->tbl.obj)
9288                 mlx5_flow_os_destroy_flow_tbl(tbl_data->tbl.obj);
9289         if (tbl_data->tunnel_offload && tbl_data->external) {
9290                 struct mlx5_hlist_entry *he;
9291                 struct mlx5_hlist *tunnel_grp_hash;
9292                 struct mlx5_flow_tunnel_hub *thub = sh->tunnel_hub;
9293                 union tunnel_tbl_key tunnel_key = {
9294                         .tunnel_id = tbl_data->tunnel ?
9295                                         tbl_data->tunnel->tunnel_id : 0,
9296                         .group = tbl_data->group_id
9297                 };
9298                 uint32_t table_id = tbl_data->table_id;
9299
9300                 tunnel_grp_hash = tbl_data->tunnel ?
9301                                         tbl_data->tunnel->groups :
9302                                         thub->groups;
9303                 he = mlx5_hlist_lookup(tunnel_grp_hash, tunnel_key.val, NULL);
9304                 if (he)
9305                         mlx5_hlist_unregister(tunnel_grp_hash, he);
9306                 DRV_LOG(DEBUG,
9307                         "Table_id %u tunnel %u group %u released.",
9308                         table_id,
9309                         tbl_data->tunnel ?
9310                         tbl_data->tunnel->tunnel_id : 0,
9311                         tbl_data->group_id);
9312         }
9313         mlx5_cache_list_destroy(&tbl_data->matchers);
9314         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], tbl_data->idx);
9315 }
9316
9317 /**
9318  * Release a flow table.
9319  *
9320  * @param[in] sh
9321  *   Pointer to device shared structure.
9322  * @param[in] tbl
9323  *   Table resource to be released.
9324  *
9325  * @return
9326  *   Returns 0 if table was released, else return 1;
9327  */
9328 static int
9329 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
9330                              struct mlx5_flow_tbl_resource *tbl)
9331 {
9332         struct mlx5_flow_tbl_data_entry *tbl_data =
9333                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
9334
9335         if (!tbl)
9336                 return 0;
9337         return mlx5_hlist_unregister(sh->flow_tbls, &tbl_data->entry);
9338 }
9339
9340 int
9341 flow_dv_matcher_match_cb(struct mlx5_cache_list *list __rte_unused,
9342                          struct mlx5_cache_entry *entry, void *cb_ctx)
9343 {
9344         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9345         struct mlx5_flow_dv_matcher *ref = ctx->data;
9346         struct mlx5_flow_dv_matcher *cur = container_of(entry, typeof(*cur),
9347                                                         entry);
9348
9349         return cur->crc != ref->crc ||
9350                cur->priority != ref->priority ||
9351                memcmp((const void *)cur->mask.buf,
9352                       (const void *)ref->mask.buf, ref->mask.size);
9353 }
9354
9355 struct mlx5_cache_entry *
9356 flow_dv_matcher_create_cb(struct mlx5_cache_list *list,
9357                           struct mlx5_cache_entry *entry __rte_unused,
9358                           void *cb_ctx)
9359 {
9360         struct mlx5_dev_ctx_shared *sh = list->ctx;
9361         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9362         struct mlx5_flow_dv_matcher *ref = ctx->data;
9363         struct mlx5_flow_dv_matcher *cache;
9364         struct mlx5dv_flow_matcher_attr dv_attr = {
9365                 .type = IBV_FLOW_ATTR_NORMAL,
9366                 .match_mask = (void *)&ref->mask,
9367         };
9368         struct mlx5_flow_tbl_data_entry *tbl = container_of(ref->tbl,
9369                                                             typeof(*tbl), tbl);
9370         int ret;
9371
9372         cache = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*cache), 0, SOCKET_ID_ANY);
9373         if (!cache) {
9374                 rte_flow_error_set(ctx->error, ENOMEM,
9375                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9376                                    "cannot create matcher");
9377                 return NULL;
9378         }
9379         *cache = *ref;
9380         dv_attr.match_criteria_enable =
9381                 flow_dv_matcher_enable(cache->mask.buf);
9382         dv_attr.priority = ref->priority;
9383         if (tbl->is_egress)
9384                 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
9385         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->tbl.obj,
9386                                                &cache->matcher_object);
9387         if (ret) {
9388                 mlx5_free(cache);
9389                 rte_flow_error_set(ctx->error, ENOMEM,
9390                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9391                                    "cannot create matcher");
9392                 return NULL;
9393         }
9394         return &cache->entry;
9395 }
9396
9397 /**
9398  * Register the flow matcher.
9399  *
9400  * @param[in, out] dev
9401  *   Pointer to rte_eth_dev structure.
9402  * @param[in, out] matcher
9403  *   Pointer to flow matcher.
9404  * @param[in, out] key
9405  *   Pointer to flow table key.
9406  * @parm[in, out] dev_flow
9407  *   Pointer to the dev_flow.
9408  * @param[out] error
9409  *   pointer to error structure.
9410  *
9411  * @return
9412  *   0 on success otherwise -errno and errno is set.
9413  */
9414 static int
9415 flow_dv_matcher_register(struct rte_eth_dev *dev,
9416                          struct mlx5_flow_dv_matcher *ref,
9417                          union mlx5_flow_tbl_key *key,
9418                          struct mlx5_flow *dev_flow,
9419                          const struct mlx5_flow_tunnel *tunnel,
9420                          uint32_t group_id,
9421                          struct rte_flow_error *error)
9422 {
9423         struct mlx5_cache_entry *entry;
9424         struct mlx5_flow_dv_matcher *cache;
9425         struct mlx5_flow_tbl_resource *tbl;
9426         struct mlx5_flow_tbl_data_entry *tbl_data;
9427         struct mlx5_flow_cb_ctx ctx = {
9428                 .error = error,
9429                 .data = ref,
9430         };
9431
9432         /**
9433          * tunnel offload API requires this registration for cases when
9434          * tunnel match rule was inserted before tunnel set rule.
9435          */
9436         tbl = flow_dv_tbl_resource_get(dev, key->table_id,
9437                                        key->direction, key->domain,
9438                                        dev_flow->external, tunnel,
9439                                        group_id, 0, error);
9440         if (!tbl)
9441                 return -rte_errno;      /* No need to refill the error info */
9442         tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
9443         ref->tbl = tbl;
9444         entry = mlx5_cache_register(&tbl_data->matchers, &ctx);
9445         if (!entry) {
9446                 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
9447                 return rte_flow_error_set(error, ENOMEM,
9448                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9449                                           "cannot allocate ref memory");
9450         }
9451         cache = container_of(entry, typeof(*cache), entry);
9452         dev_flow->handle->dvh.matcher = cache;
9453         return 0;
9454 }
9455
9456 struct mlx5_hlist_entry *
9457 flow_dv_tag_create_cb(struct mlx5_hlist *list, uint64_t key, void *ctx)
9458 {
9459         struct mlx5_dev_ctx_shared *sh = list->ctx;
9460         struct rte_flow_error *error = ctx;
9461         struct mlx5_flow_dv_tag_resource *entry;
9462         uint32_t idx = 0;
9463         int ret;
9464
9465         entry = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_TAG], &idx);
9466         if (!entry) {
9467                 rte_flow_error_set(error, ENOMEM,
9468                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9469                                    "cannot allocate resource memory");
9470                 return NULL;
9471         }
9472         entry->idx = idx;
9473         entry->tag_id = key;
9474         ret = mlx5_flow_os_create_flow_action_tag(key,
9475                                                   &entry->action);
9476         if (ret) {
9477                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], idx);
9478                 rte_flow_error_set(error, ENOMEM,
9479                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9480                                    NULL, "cannot create action");
9481                 return NULL;
9482         }
9483         return &entry->entry;
9484 }
9485
9486 int
9487 flow_dv_tag_match_cb(struct mlx5_hlist *list __rte_unused,
9488                      struct mlx5_hlist_entry *entry, uint64_t key,
9489                      void *cb_ctx __rte_unused)
9490 {
9491         struct mlx5_flow_dv_tag_resource *tag =
9492                 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
9493
9494         return key != tag->tag_id;
9495 }
9496
9497 /**
9498  * Find existing tag resource or create and register a new one.
9499  *
9500  * @param dev[in, out]
9501  *   Pointer to rte_eth_dev structure.
9502  * @param[in, out] tag_be24
9503  *   Tag value in big endian then R-shift 8.
9504  * @parm[in, out] dev_flow
9505  *   Pointer to the dev_flow.
9506  * @param[out] error
9507  *   pointer to error structure.
9508  *
9509  * @return
9510  *   0 on success otherwise -errno and errno is set.
9511  */
9512 static int
9513 flow_dv_tag_resource_register
9514                         (struct rte_eth_dev *dev,
9515                          uint32_t tag_be24,
9516                          struct mlx5_flow *dev_flow,
9517                          struct rte_flow_error *error)
9518 {
9519         struct mlx5_priv *priv = dev->data->dev_private;
9520         struct mlx5_flow_dv_tag_resource *cache_resource;
9521         struct mlx5_hlist_entry *entry;
9522
9523         entry = mlx5_hlist_register(priv->sh->tag_table, tag_be24, error);
9524         if (entry) {
9525                 cache_resource = container_of
9526                         (entry, struct mlx5_flow_dv_tag_resource, entry);
9527                 dev_flow->handle->dvh.rix_tag = cache_resource->idx;
9528                 dev_flow->dv.tag_resource = cache_resource;
9529                 return 0;
9530         }
9531         return -rte_errno;
9532 }
9533
9534 void
9535 flow_dv_tag_remove_cb(struct mlx5_hlist *list,
9536                       struct mlx5_hlist_entry *entry)
9537 {
9538         struct mlx5_dev_ctx_shared *sh = list->ctx;
9539         struct mlx5_flow_dv_tag_resource *tag =
9540                 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
9541
9542         MLX5_ASSERT(tag && sh && tag->action);
9543         claim_zero(mlx5_flow_os_destroy_flow_action(tag->action));
9544         DRV_LOG(DEBUG, "Tag %p: removed.", (void *)tag);
9545         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], tag->idx);
9546 }
9547
9548 /**
9549  * Release the tag.
9550  *
9551  * @param dev
9552  *   Pointer to Ethernet device.
9553  * @param tag_idx
9554  *   Tag index.
9555  *
9556  * @return
9557  *   1 while a reference on it exists, 0 when freed.
9558  */
9559 static int
9560 flow_dv_tag_release(struct rte_eth_dev *dev,
9561                     uint32_t tag_idx)
9562 {
9563         struct mlx5_priv *priv = dev->data->dev_private;
9564         struct mlx5_flow_dv_tag_resource *tag;
9565
9566         tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
9567         if (!tag)
9568                 return 0;
9569         DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
9570                 dev->data->port_id, (void *)tag, tag->entry.ref_cnt);
9571         return mlx5_hlist_unregister(priv->sh->tag_table, &tag->entry);
9572 }
9573
9574 /**
9575  * Translate port ID action to vport.
9576  *
9577  * @param[in] dev
9578  *   Pointer to rte_eth_dev structure.
9579  * @param[in] action
9580  *   Pointer to the port ID action.
9581  * @param[out] dst_port_id
9582  *   The target port ID.
9583  * @param[out] error
9584  *   Pointer to the error structure.
9585  *
9586  * @return
9587  *   0 on success, a negative errno value otherwise and rte_errno is set.
9588  */
9589 static int
9590 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
9591                                  const struct rte_flow_action *action,
9592                                  uint32_t *dst_port_id,
9593                                  struct rte_flow_error *error)
9594 {
9595         uint32_t port;
9596         struct mlx5_priv *priv;
9597         const struct rte_flow_action_port_id *conf =
9598                         (const struct rte_flow_action_port_id *)action->conf;
9599
9600         port = conf->original ? dev->data->port_id : conf->id;
9601         priv = mlx5_port_to_eswitch_info(port, false);
9602         if (!priv)
9603                 return rte_flow_error_set(error, -rte_errno,
9604                                           RTE_FLOW_ERROR_TYPE_ACTION,
9605                                           NULL,
9606                                           "No eswitch info was found for port");
9607 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
9608         /*
9609          * This parameter is transferred to
9610          * mlx5dv_dr_action_create_dest_ib_port().
9611          */
9612         *dst_port_id = priv->dev_port;
9613 #else
9614         /*
9615          * Legacy mode, no LAG configurations is supported.
9616          * This parameter is transferred to
9617          * mlx5dv_dr_action_create_dest_vport().
9618          */
9619         *dst_port_id = priv->vport_id;
9620 #endif
9621         return 0;
9622 }
9623
9624 /**
9625  * Create a counter with aging configuration.
9626  *
9627  * @param[in] dev
9628  *   Pointer to rte_eth_dev structure.
9629  * @param[out] count
9630  *   Pointer to the counter action configuration.
9631  * @param[in] age
9632  *   Pointer to the aging action configuration.
9633  *
9634  * @return
9635  *   Index to flow counter on success, 0 otherwise.
9636  */
9637 static uint32_t
9638 flow_dv_translate_create_counter(struct rte_eth_dev *dev,
9639                                 struct mlx5_flow *dev_flow,
9640                                 const struct rte_flow_action_count *count,
9641                                 const struct rte_flow_action_age *age)
9642 {
9643         uint32_t counter;
9644         struct mlx5_age_param *age_param;
9645
9646         if (count && count->shared)
9647                 counter = flow_dv_counter_get_shared(dev, count->id);
9648         else
9649                 counter = flow_dv_counter_alloc(dev, !!age);
9650         if (!counter || age == NULL)
9651                 return counter;
9652         age_param  = flow_dv_counter_idx_get_age(dev, counter);
9653         age_param->context = age->context ? age->context :
9654                 (void *)(uintptr_t)(dev_flow->flow_idx);
9655         age_param->timeout = age->timeout;
9656         age_param->port_id = dev->data->port_id;
9657         __atomic_store_n(&age_param->sec_since_last_hit, 0, __ATOMIC_RELAXED);
9658         __atomic_store_n(&age_param->state, AGE_CANDIDATE, __ATOMIC_RELAXED);
9659         return counter;
9660 }
9661
9662 /**
9663  * Add Tx queue matcher
9664  *
9665  * @param[in] dev
9666  *   Pointer to the dev struct.
9667  * @param[in, out] matcher
9668  *   Flow matcher.
9669  * @param[in, out] key
9670  *   Flow matcher value.
9671  * @param[in] item
9672  *   Flow pattern to translate.
9673  * @param[in] inner
9674  *   Item is inner pattern.
9675  */
9676 static void
9677 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
9678                                 void *matcher, void *key,
9679                                 const struct rte_flow_item *item)
9680 {
9681         const struct mlx5_rte_flow_item_tx_queue *queue_m;
9682         const struct mlx5_rte_flow_item_tx_queue *queue_v;
9683         void *misc_m =
9684                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
9685         void *misc_v =
9686                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
9687         struct mlx5_txq_ctrl *txq;
9688         uint32_t queue;
9689
9690
9691         queue_m = (const void *)item->mask;
9692         if (!queue_m)
9693                 return;
9694         queue_v = (const void *)item->spec;
9695         if (!queue_v)
9696                 return;
9697         txq = mlx5_txq_get(dev, queue_v->queue);
9698         if (!txq)
9699                 return;
9700         queue = txq->obj->sq->id;
9701         MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
9702         MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
9703                  queue & queue_m->queue);
9704         mlx5_txq_release(dev, queue_v->queue);
9705 }
9706
9707 /**
9708  * Set the hash fields according to the @p flow information.
9709  *
9710  * @param[in] dev_flow
9711  *   Pointer to the mlx5_flow.
9712  * @param[in] rss_desc
9713  *   Pointer to the mlx5_flow_rss_desc.
9714  */
9715 static void
9716 flow_dv_hashfields_set(struct mlx5_flow *dev_flow,
9717                        struct mlx5_flow_rss_desc *rss_desc)
9718 {
9719         uint64_t items = dev_flow->handle->layers;
9720         int rss_inner = 0;
9721         uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
9722
9723         dev_flow->hash_fields = 0;
9724 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
9725         if (rss_desc->level >= 2) {
9726                 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
9727                 rss_inner = 1;
9728         }
9729 #endif
9730         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
9731             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
9732                 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
9733                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
9734                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
9735                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
9736                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
9737                         else
9738                                 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
9739                 }
9740         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
9741                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
9742                 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
9743                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
9744                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
9745                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
9746                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
9747                         else
9748                                 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
9749                 }
9750         }
9751         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
9752             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
9753                 if (rss_types & ETH_RSS_UDP) {
9754                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
9755                                 dev_flow->hash_fields |=
9756                                                 IBV_RX_HASH_SRC_PORT_UDP;
9757                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
9758                                 dev_flow->hash_fields |=
9759                                                 IBV_RX_HASH_DST_PORT_UDP;
9760                         else
9761                                 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
9762                 }
9763         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
9764                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
9765                 if (rss_types & ETH_RSS_TCP) {
9766                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
9767                                 dev_flow->hash_fields |=
9768                                                 IBV_RX_HASH_SRC_PORT_TCP;
9769                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
9770                                 dev_flow->hash_fields |=
9771                                                 IBV_RX_HASH_DST_PORT_TCP;
9772                         else
9773                                 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
9774                 }
9775         }
9776 }
9777
9778 /**
9779  * Prepare an Rx Hash queue.
9780  *
9781  * @param dev
9782  *   Pointer to Ethernet device.
9783  * @param[in] dev_flow
9784  *   Pointer to the mlx5_flow.
9785  * @param[in] rss_desc
9786  *   Pointer to the mlx5_flow_rss_desc.
9787  * @param[out] hrxq_idx
9788  *   Hash Rx queue index.
9789  *
9790  * @return
9791  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
9792  */
9793 static struct mlx5_hrxq *
9794 flow_dv_hrxq_prepare(struct rte_eth_dev *dev,
9795                      struct mlx5_flow *dev_flow,
9796                      struct mlx5_flow_rss_desc *rss_desc,
9797                      uint32_t *hrxq_idx)
9798 {
9799         struct mlx5_priv *priv = dev->data->dev_private;
9800         struct mlx5_flow_handle *dh = dev_flow->handle;
9801         struct mlx5_hrxq *hrxq;
9802
9803         MLX5_ASSERT(rss_desc->queue_num);
9804         rss_desc->key_len = MLX5_RSS_HASH_KEY_LEN;
9805         rss_desc->hash_fields = dev_flow->hash_fields;
9806         rss_desc->tunnel = !!(dh->layers & MLX5_FLOW_LAYER_TUNNEL);
9807         rss_desc->shared_rss = 0;
9808         *hrxq_idx = mlx5_hrxq_get(dev, rss_desc);
9809         if (!*hrxq_idx)
9810                 return NULL;
9811         hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
9812                               *hrxq_idx);
9813         return hrxq;
9814 }
9815
9816 /**
9817  * Release sample sub action resource.
9818  *
9819  * @param[in, out] dev
9820  *   Pointer to rte_eth_dev structure.
9821  * @param[in] act_res
9822  *   Pointer to sample sub action resource.
9823  */
9824 static void
9825 flow_dv_sample_sub_actions_release(struct rte_eth_dev *dev,
9826                                    struct mlx5_flow_sub_actions_idx *act_res)
9827 {
9828         if (act_res->rix_hrxq) {
9829                 mlx5_hrxq_release(dev, act_res->rix_hrxq);
9830                 act_res->rix_hrxq = 0;
9831         }
9832         if (act_res->rix_encap_decap) {
9833                 flow_dv_encap_decap_resource_release(dev,
9834                                                      act_res->rix_encap_decap);
9835                 act_res->rix_encap_decap = 0;
9836         }
9837         if (act_res->rix_port_id_action) {
9838                 flow_dv_port_id_action_resource_release(dev,
9839                                                 act_res->rix_port_id_action);
9840                 act_res->rix_port_id_action = 0;
9841         }
9842         if (act_res->rix_tag) {
9843                 flow_dv_tag_release(dev, act_res->rix_tag);
9844                 act_res->rix_tag = 0;
9845         }
9846         if (act_res->rix_jump) {
9847                 flow_dv_jump_tbl_resource_release(dev, act_res->rix_jump);
9848                 act_res->rix_jump = 0;
9849         }
9850 }
9851
9852 int
9853 flow_dv_sample_match_cb(struct mlx5_cache_list *list __rte_unused,
9854                         struct mlx5_cache_entry *entry, void *cb_ctx)
9855 {
9856         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9857         struct rte_eth_dev *dev = ctx->dev;
9858         struct mlx5_flow_dv_sample_resource *resource = ctx->data;
9859         struct mlx5_flow_dv_sample_resource *cache_resource =
9860                         container_of(entry, typeof(*cache_resource), entry);
9861
9862         if (resource->ratio == cache_resource->ratio &&
9863             resource->ft_type == cache_resource->ft_type &&
9864             resource->ft_id == cache_resource->ft_id &&
9865             resource->set_action == cache_resource->set_action &&
9866             !memcmp((void *)&resource->sample_act,
9867                     (void *)&cache_resource->sample_act,
9868                     sizeof(struct mlx5_flow_sub_actions_list))) {
9869                 /*
9870                  * Existing sample action should release the prepared
9871                  * sub-actions reference counter.
9872                  */
9873                 flow_dv_sample_sub_actions_release(dev,
9874                                                 &resource->sample_idx);
9875                 return 0;
9876         }
9877         return 1;
9878 }
9879
9880 struct mlx5_cache_entry *
9881 flow_dv_sample_create_cb(struct mlx5_cache_list *list __rte_unused,
9882                          struct mlx5_cache_entry *entry __rte_unused,
9883                          void *cb_ctx)
9884 {
9885         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9886         struct rte_eth_dev *dev = ctx->dev;
9887         struct mlx5_flow_dv_sample_resource *resource = ctx->data;
9888         void **sample_dv_actions = resource->sub_actions;
9889         struct mlx5_flow_dv_sample_resource *cache_resource;
9890         struct mlx5dv_dr_flow_sampler_attr sampler_attr;
9891         struct mlx5_priv *priv = dev->data->dev_private;
9892         struct mlx5_dev_ctx_shared *sh = priv->sh;
9893         struct mlx5_flow_tbl_resource *tbl;
9894         uint32_t idx = 0;
9895         const uint32_t next_ft_step = 1;
9896         uint32_t next_ft_id = resource->ft_id + next_ft_step;
9897         uint8_t is_egress = 0;
9898         uint8_t is_transfer = 0;
9899         struct rte_flow_error *error = ctx->error;
9900
9901         /* Register new sample resource. */
9902         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_SAMPLE], &idx);
9903         if (!cache_resource) {
9904                 rte_flow_error_set(error, ENOMEM,
9905                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9906                                           NULL,
9907                                           "cannot allocate resource memory");
9908                 return NULL;
9909         }
9910         *cache_resource = *resource;
9911         /* Create normal path table level */
9912         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
9913                 is_transfer = 1;
9914         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
9915                 is_egress = 1;
9916         tbl = flow_dv_tbl_resource_get(dev, next_ft_id,
9917                                         is_egress, is_transfer,
9918                                         true, NULL, 0, 0, error);
9919         if (!tbl) {
9920                 rte_flow_error_set(error, ENOMEM,
9921                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9922                                           NULL,
9923                                           "fail to create normal path table "
9924                                           "for sample");
9925                 goto error;
9926         }
9927         cache_resource->normal_path_tbl = tbl;
9928         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB) {
9929                 if (!sh->default_miss_action) {
9930                         rte_flow_error_set(error, ENOMEM,
9931                                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9932                                                 NULL,
9933                                                 "default miss action was not "
9934                                                 "created");
9935                         goto error;
9936                 }
9937                 sample_dv_actions[resource->sample_act.actions_num++] =
9938                                                 sh->default_miss_action;
9939         }
9940         /* Create a DR sample action */
9941         sampler_attr.sample_ratio = cache_resource->ratio;
9942         sampler_attr.default_next_table = tbl->obj;
9943         sampler_attr.num_sample_actions = resource->sample_act.actions_num;
9944         sampler_attr.sample_actions = (struct mlx5dv_dr_action **)
9945                                                         &sample_dv_actions[0];
9946         sampler_attr.action = cache_resource->set_action;
9947         if (mlx5_os_flow_dr_create_flow_action_sampler
9948                         (&sampler_attr, &cache_resource->verbs_action)) {
9949                 rte_flow_error_set(error, ENOMEM,
9950                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9951                                         NULL, "cannot create sample action");
9952                 goto error;
9953         }
9954         cache_resource->idx = idx;
9955         cache_resource->dev = dev;
9956         return &cache_resource->entry;
9957 error:
9958         if (cache_resource->ft_type != MLX5DV_FLOW_TABLE_TYPE_FDB)
9959                 flow_dv_sample_sub_actions_release(dev,
9960                                                    &cache_resource->sample_idx);
9961         if (cache_resource->normal_path_tbl)
9962                 flow_dv_tbl_resource_release(MLX5_SH(dev),
9963                                 cache_resource->normal_path_tbl);
9964         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_SAMPLE], idx);
9965         return NULL;
9966
9967 }
9968
9969 /**
9970  * Find existing sample resource or create and register a new one.
9971  *
9972  * @param[in, out] dev
9973  *   Pointer to rte_eth_dev structure.
9974  * @param[in] resource
9975  *   Pointer to sample resource.
9976  * @parm[in, out] dev_flow
9977  *   Pointer to the dev_flow.
9978  * @param[out] error
9979  *   pointer to error structure.
9980  *
9981  * @return
9982  *   0 on success otherwise -errno and errno is set.
9983  */
9984 static int
9985 flow_dv_sample_resource_register(struct rte_eth_dev *dev,
9986                          struct mlx5_flow_dv_sample_resource *resource,
9987                          struct mlx5_flow *dev_flow,
9988                          struct rte_flow_error *error)
9989 {
9990         struct mlx5_flow_dv_sample_resource *cache_resource;
9991         struct mlx5_cache_entry *entry;
9992         struct mlx5_priv *priv = dev->data->dev_private;
9993         struct mlx5_flow_cb_ctx ctx = {
9994                 .dev = dev,
9995                 .error = error,
9996                 .data = resource,
9997         };
9998
9999         entry = mlx5_cache_register(&priv->sh->sample_action_list, &ctx);
10000         if (!entry)
10001                 return -rte_errno;
10002         cache_resource = container_of(entry, typeof(*cache_resource), entry);
10003         dev_flow->handle->dvh.rix_sample = cache_resource->idx;
10004         dev_flow->dv.sample_res = cache_resource;
10005         return 0;
10006 }
10007
10008 int
10009 flow_dv_dest_array_match_cb(struct mlx5_cache_list *list __rte_unused,
10010                             struct mlx5_cache_entry *entry, void *cb_ctx)
10011 {
10012         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10013         struct mlx5_flow_dv_dest_array_resource *resource = ctx->data;
10014         struct rte_eth_dev *dev = ctx->dev;
10015         struct mlx5_flow_dv_dest_array_resource *cache_resource =
10016                         container_of(entry, typeof(*cache_resource), entry);
10017         uint32_t idx = 0;
10018
10019         if (resource->num_of_dest == cache_resource->num_of_dest &&
10020             resource->ft_type == cache_resource->ft_type &&
10021             !memcmp((void *)cache_resource->sample_act,
10022                     (void *)resource->sample_act,
10023                    (resource->num_of_dest *
10024                    sizeof(struct mlx5_flow_sub_actions_list)))) {
10025                 /*
10026                  * Existing sample action should release the prepared
10027                  * sub-actions reference counter.
10028                  */
10029                 for (idx = 0; idx < resource->num_of_dest; idx++)
10030                         flow_dv_sample_sub_actions_release(dev,
10031                                         &resource->sample_idx[idx]);
10032                 return 0;
10033         }
10034         return 1;
10035 }
10036
10037 struct mlx5_cache_entry *
10038 flow_dv_dest_array_create_cb(struct mlx5_cache_list *list __rte_unused,
10039                          struct mlx5_cache_entry *entry __rte_unused,
10040                          void *cb_ctx)
10041 {
10042         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10043         struct rte_eth_dev *dev = ctx->dev;
10044         struct mlx5_flow_dv_dest_array_resource *cache_resource;
10045         struct mlx5_flow_dv_dest_array_resource *resource = ctx->data;
10046         struct mlx5dv_dr_action_dest_attr *dest_attr[MLX5_MAX_DEST_NUM] = { 0 };
10047         struct mlx5dv_dr_action_dest_reformat dest_reformat[MLX5_MAX_DEST_NUM];
10048         struct mlx5_priv *priv = dev->data->dev_private;
10049         struct mlx5_dev_ctx_shared *sh = priv->sh;
10050         struct mlx5_flow_sub_actions_list *sample_act;
10051         struct mlx5dv_dr_domain *domain;
10052         uint32_t idx = 0, res_idx = 0;
10053         struct rte_flow_error *error = ctx->error;
10054         uint64_t action_flags;
10055         int ret;
10056
10057         /* Register new destination array resource. */
10058         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
10059                                             &res_idx);
10060         if (!cache_resource) {
10061                 rte_flow_error_set(error, ENOMEM,
10062                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10063                                           NULL,
10064                                           "cannot allocate resource memory");
10065                 return NULL;
10066         }
10067         *cache_resource = *resource;
10068         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
10069                 domain = sh->fdb_domain;
10070         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
10071                 domain = sh->rx_domain;
10072         else
10073                 domain = sh->tx_domain;
10074         for (idx = 0; idx < resource->num_of_dest; idx++) {
10075                 dest_attr[idx] = (struct mlx5dv_dr_action_dest_attr *)
10076                                  mlx5_malloc(MLX5_MEM_ZERO,
10077                                  sizeof(struct mlx5dv_dr_action_dest_attr),
10078                                  0, SOCKET_ID_ANY);
10079                 if (!dest_attr[idx]) {
10080                         rte_flow_error_set(error, ENOMEM,
10081                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10082                                            NULL,
10083                                            "cannot allocate resource memory");
10084                         goto error;
10085                 }
10086                 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST;
10087                 sample_act = &resource->sample_act[idx];
10088                 action_flags = sample_act->action_flags;
10089                 switch (action_flags) {
10090                 case MLX5_FLOW_ACTION_QUEUE:
10091                         dest_attr[idx]->dest = sample_act->dr_queue_action;
10092                         break;
10093                 case (MLX5_FLOW_ACTION_PORT_ID | MLX5_FLOW_ACTION_ENCAP):
10094                         dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST_REFORMAT;
10095                         dest_attr[idx]->dest_reformat = &dest_reformat[idx];
10096                         dest_attr[idx]->dest_reformat->reformat =
10097                                         sample_act->dr_encap_action;
10098                         dest_attr[idx]->dest_reformat->dest =
10099                                         sample_act->dr_port_id_action;
10100                         break;
10101                 case MLX5_FLOW_ACTION_PORT_ID:
10102                         dest_attr[idx]->dest = sample_act->dr_port_id_action;
10103                         break;
10104                 case MLX5_FLOW_ACTION_JUMP:
10105                         dest_attr[idx]->dest = sample_act->dr_jump_action;
10106                         break;
10107                 default:
10108                         rte_flow_error_set(error, EINVAL,
10109                                            RTE_FLOW_ERROR_TYPE_ACTION,
10110                                            NULL,
10111                                            "unsupported actions type");
10112                         goto error;
10113                 }
10114         }
10115         /* create a dest array actioin */
10116         ret = mlx5_os_flow_dr_create_flow_action_dest_array
10117                                                 (domain,
10118                                                  cache_resource->num_of_dest,
10119                                                  dest_attr,
10120                                                  &cache_resource->action);
10121         if (ret) {
10122                 rte_flow_error_set(error, ENOMEM,
10123                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10124                                    NULL,
10125                                    "cannot create destination array action");
10126                 goto error;
10127         }
10128         cache_resource->idx = res_idx;
10129         cache_resource->dev = dev;
10130         for (idx = 0; idx < resource->num_of_dest; idx++)
10131                 mlx5_free(dest_attr[idx]);
10132         return &cache_resource->entry;
10133 error:
10134         for (idx = 0; idx < resource->num_of_dest; idx++) {
10135                 struct mlx5_flow_sub_actions_idx *act_res =
10136                                         &cache_resource->sample_idx[idx];
10137                 if (act_res->rix_hrxq &&
10138                     !mlx5_hrxq_release(dev,
10139                                 act_res->rix_hrxq))
10140                         act_res->rix_hrxq = 0;
10141                 if (act_res->rix_encap_decap &&
10142                         !flow_dv_encap_decap_resource_release(dev,
10143                                 act_res->rix_encap_decap))
10144                         act_res->rix_encap_decap = 0;
10145                 if (act_res->rix_port_id_action &&
10146                         !flow_dv_port_id_action_resource_release(dev,
10147                                 act_res->rix_port_id_action))
10148                         act_res->rix_port_id_action = 0;
10149                 if (act_res->rix_jump &&
10150                         !flow_dv_jump_tbl_resource_release(dev,
10151                                 act_res->rix_jump))
10152                         act_res->rix_jump = 0;
10153                 if (dest_attr[idx])
10154                         mlx5_free(dest_attr[idx]);
10155         }
10156
10157         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DEST_ARRAY], res_idx);
10158         return NULL;
10159 }
10160
10161 /**
10162  * Find existing destination array resource or create and register a new one.
10163  *
10164  * @param[in, out] dev
10165  *   Pointer to rte_eth_dev structure.
10166  * @param[in] resource
10167  *   Pointer to destination array resource.
10168  * @parm[in, out] dev_flow
10169  *   Pointer to the dev_flow.
10170  * @param[out] error
10171  *   pointer to error structure.
10172  *
10173  * @return
10174  *   0 on success otherwise -errno and errno is set.
10175  */
10176 static int
10177 flow_dv_dest_array_resource_register(struct rte_eth_dev *dev,
10178                          struct mlx5_flow_dv_dest_array_resource *resource,
10179                          struct mlx5_flow *dev_flow,
10180                          struct rte_flow_error *error)
10181 {
10182         struct mlx5_flow_dv_dest_array_resource *cache_resource;
10183         struct mlx5_priv *priv = dev->data->dev_private;
10184         struct mlx5_cache_entry *entry;
10185         struct mlx5_flow_cb_ctx ctx = {
10186                 .dev = dev,
10187                 .error = error,
10188                 .data = resource,
10189         };
10190
10191         entry = mlx5_cache_register(&priv->sh->dest_array_list, &ctx);
10192         if (!entry)
10193                 return -rte_errno;
10194         cache_resource = container_of(entry, typeof(*cache_resource), entry);
10195         dev_flow->handle->dvh.rix_dest_array = cache_resource->idx;
10196         dev_flow->dv.dest_array_res = cache_resource;
10197         return 0;
10198 }
10199
10200 /**
10201  * Convert Sample action to DV specification.
10202  *
10203  * @param[in] dev
10204  *   Pointer to rte_eth_dev structure.
10205  * @param[in] action
10206  *   Pointer to sample action structure.
10207  * @param[in, out] dev_flow
10208  *   Pointer to the mlx5_flow.
10209  * @param[in] attr
10210  *   Pointer to the flow attributes.
10211  * @param[in, out] num_of_dest
10212  *   Pointer to the num of destination.
10213  * @param[in, out] sample_actions
10214  *   Pointer to sample actions list.
10215  * @param[in, out] res
10216  *   Pointer to sample resource.
10217  * @param[out] error
10218  *   Pointer to the error structure.
10219  *
10220  * @return
10221  *   0 on success, a negative errno value otherwise and rte_errno is set.
10222  */
10223 static int
10224 flow_dv_translate_action_sample(struct rte_eth_dev *dev,
10225                                 const struct rte_flow_action_sample *action,
10226                                 struct mlx5_flow *dev_flow,
10227                                 const struct rte_flow_attr *attr,
10228                                 uint32_t *num_of_dest,
10229                                 void **sample_actions,
10230                                 struct mlx5_flow_dv_sample_resource *res,
10231                                 struct rte_flow_error *error)
10232 {
10233         struct mlx5_priv *priv = dev->data->dev_private;
10234         const struct rte_flow_action *sub_actions;
10235         struct mlx5_flow_sub_actions_list *sample_act;
10236         struct mlx5_flow_sub_actions_idx *sample_idx;
10237         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
10238         struct rte_flow *flow = dev_flow->flow;
10239         struct mlx5_flow_rss_desc *rss_desc;
10240         uint64_t action_flags = 0;
10241
10242         MLX5_ASSERT(wks);
10243         rss_desc = &wks->rss_desc;
10244         sample_act = &res->sample_act;
10245         sample_idx = &res->sample_idx;
10246         res->ratio = action->ratio;
10247         sub_actions = action->actions;
10248         for (; sub_actions->type != RTE_FLOW_ACTION_TYPE_END; sub_actions++) {
10249                 int type = sub_actions->type;
10250                 uint32_t pre_rix = 0;
10251                 void *pre_r;
10252                 switch (type) {
10253                 case RTE_FLOW_ACTION_TYPE_QUEUE:
10254                 {
10255                         const struct rte_flow_action_queue *queue;
10256                         struct mlx5_hrxq *hrxq;
10257                         uint32_t hrxq_idx;
10258
10259                         queue = sub_actions->conf;
10260                         rss_desc->queue_num = 1;
10261                         rss_desc->queue[0] = queue->index;
10262                         hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
10263                                                     rss_desc, &hrxq_idx);
10264                         if (!hrxq)
10265                                 return rte_flow_error_set
10266                                         (error, rte_errno,
10267                                          RTE_FLOW_ERROR_TYPE_ACTION,
10268                                          NULL,
10269                                          "cannot create fate queue");
10270                         sample_act->dr_queue_action = hrxq->action;
10271                         sample_idx->rix_hrxq = hrxq_idx;
10272                         sample_actions[sample_act->actions_num++] =
10273                                                 hrxq->action;
10274                         (*num_of_dest)++;
10275                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
10276                         if (action_flags & MLX5_FLOW_ACTION_MARK)
10277                                 dev_flow->handle->rix_hrxq = hrxq_idx;
10278                         dev_flow->handle->fate_action =
10279                                         MLX5_FLOW_FATE_QUEUE;
10280                         break;
10281                 }
10282                 case RTE_FLOW_ACTION_TYPE_RSS:
10283                 {
10284                         struct mlx5_hrxq *hrxq;
10285                         uint32_t hrxq_idx;
10286                         const struct rte_flow_action_rss *rss;
10287                         const uint8_t *rss_key;
10288
10289                         rss = sub_actions->conf;
10290                         memcpy(rss_desc->queue, rss->queue,
10291                                rss->queue_num * sizeof(uint16_t));
10292                         rss_desc->queue_num = rss->queue_num;
10293                         /* NULL RSS key indicates default RSS key. */
10294                         rss_key = !rss->key ? rss_hash_default_key : rss->key;
10295                         memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
10296                         /*
10297                          * rss->level and rss.types should be set in advance
10298                          * when expanding items for RSS.
10299                          */
10300                         flow_dv_hashfields_set(dev_flow, rss_desc);
10301                         hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
10302                                                     rss_desc, &hrxq_idx);
10303                         if (!hrxq)
10304                                 return rte_flow_error_set
10305                                         (error, rte_errno,
10306                                          RTE_FLOW_ERROR_TYPE_ACTION,
10307                                          NULL,
10308                                          "cannot create fate queue");
10309                         sample_act->dr_queue_action = hrxq->action;
10310                         sample_idx->rix_hrxq = hrxq_idx;
10311                         sample_actions[sample_act->actions_num++] =
10312                                                 hrxq->action;
10313                         (*num_of_dest)++;
10314                         action_flags |= MLX5_FLOW_ACTION_RSS;
10315                         if (action_flags & MLX5_FLOW_ACTION_MARK)
10316                                 dev_flow->handle->rix_hrxq = hrxq_idx;
10317                         dev_flow->handle->fate_action =
10318                                         MLX5_FLOW_FATE_QUEUE;
10319                         break;
10320                 }
10321                 case RTE_FLOW_ACTION_TYPE_MARK:
10322                 {
10323                         uint32_t tag_be = mlx5_flow_mark_set
10324                                 (((const struct rte_flow_action_mark *)
10325                                 (sub_actions->conf))->id);
10326
10327                         dev_flow->handle->mark = 1;
10328                         pre_rix = dev_flow->handle->dvh.rix_tag;
10329                         /* Save the mark resource before sample */
10330                         pre_r = dev_flow->dv.tag_resource;
10331                         if (flow_dv_tag_resource_register(dev, tag_be,
10332                                                   dev_flow, error))
10333                                 return -rte_errno;
10334                         MLX5_ASSERT(dev_flow->dv.tag_resource);
10335                         sample_act->dr_tag_action =
10336                                 dev_flow->dv.tag_resource->action;
10337                         sample_idx->rix_tag =
10338                                 dev_flow->handle->dvh.rix_tag;
10339                         sample_actions[sample_act->actions_num++] =
10340                                                 sample_act->dr_tag_action;
10341                         /* Recover the mark resource after sample */
10342                         dev_flow->dv.tag_resource = pre_r;
10343                         dev_flow->handle->dvh.rix_tag = pre_rix;
10344                         action_flags |= MLX5_FLOW_ACTION_MARK;
10345                         break;
10346                 }
10347                 case RTE_FLOW_ACTION_TYPE_COUNT:
10348                 {
10349                         if (!flow->counter) {
10350                                 flow->counter =
10351                                         flow_dv_translate_create_counter(dev,
10352                                                 dev_flow, sub_actions->conf,
10353                                                 0);
10354                                 if (!flow->counter)
10355                                         return rte_flow_error_set
10356                                                 (error, rte_errno,
10357                                                 RTE_FLOW_ERROR_TYPE_ACTION,
10358                                                 NULL,
10359                                                 "cannot create counter"
10360                                                 " object.");
10361                         }
10362                         sample_act->dr_cnt_action =
10363                                   (flow_dv_counter_get_by_idx(dev,
10364                                   flow->counter, NULL))->action;
10365                         sample_actions[sample_act->actions_num++] =
10366                                                 sample_act->dr_cnt_action;
10367                         action_flags |= MLX5_FLOW_ACTION_COUNT;
10368                         break;
10369                 }
10370                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
10371                 {
10372                         struct mlx5_flow_dv_port_id_action_resource
10373                                         port_id_resource;
10374                         uint32_t port_id = 0;
10375
10376                         memset(&port_id_resource, 0, sizeof(port_id_resource));
10377                         /* Save the port id resource before sample */
10378                         pre_rix = dev_flow->handle->rix_port_id_action;
10379                         pre_r = dev_flow->dv.port_id_action;
10380                         if (flow_dv_translate_action_port_id(dev, sub_actions,
10381                                                              &port_id, error))
10382                                 return -rte_errno;
10383                         port_id_resource.port_id = port_id;
10384                         if (flow_dv_port_id_action_resource_register
10385                             (dev, &port_id_resource, dev_flow, error))
10386                                 return -rte_errno;
10387                         sample_act->dr_port_id_action =
10388                                 dev_flow->dv.port_id_action->action;
10389                         sample_idx->rix_port_id_action =
10390                                 dev_flow->handle->rix_port_id_action;
10391                         sample_actions[sample_act->actions_num++] =
10392                                                 sample_act->dr_port_id_action;
10393                         /* Recover the port id resource after sample */
10394                         dev_flow->dv.port_id_action = pre_r;
10395                         dev_flow->handle->rix_port_id_action = pre_rix;
10396                         (*num_of_dest)++;
10397                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
10398                         break;
10399                 }
10400                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
10401                         /* Save the encap resource before sample */
10402                         pre_rix = dev_flow->handle->dvh.rix_encap_decap;
10403                         pre_r = dev_flow->dv.encap_decap;
10404                         if (flow_dv_create_action_l2_encap(dev, sub_actions,
10405                                                            dev_flow,
10406                                                            attr->transfer,
10407                                                            error))
10408                                 return -rte_errno;
10409                         sample_act->dr_encap_action =
10410                                 dev_flow->dv.encap_decap->action;
10411                         sample_idx->rix_encap_decap =
10412                                 dev_flow->handle->dvh.rix_encap_decap;
10413                         sample_actions[sample_act->actions_num++] =
10414                                                 sample_act->dr_encap_action;
10415                         /* Recover the encap resource after sample */
10416                         dev_flow->dv.encap_decap = pre_r;
10417                         dev_flow->handle->dvh.rix_encap_decap = pre_rix;
10418                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
10419                         break;
10420                 default:
10421                         return rte_flow_error_set(error, EINVAL,
10422                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10423                                 NULL,
10424                                 "Not support for sampler action");
10425                 }
10426         }
10427         sample_act->action_flags = action_flags;
10428         res->ft_id = dev_flow->dv.group;
10429         if (attr->transfer) {
10430                 union {
10431                         uint32_t action_in[MLX5_ST_SZ_DW(set_action_in)];
10432                         uint64_t set_action;
10433                 } action_ctx = { .set_action = 0 };
10434
10435                 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
10436                 MLX5_SET(set_action_in, action_ctx.action_in, action_type,
10437                          MLX5_MODIFICATION_TYPE_SET);
10438                 MLX5_SET(set_action_in, action_ctx.action_in, field,
10439                          MLX5_MODI_META_REG_C_0);
10440                 MLX5_SET(set_action_in, action_ctx.action_in, data,
10441                          priv->vport_meta_tag);
10442                 res->set_action = action_ctx.set_action;
10443         } else if (attr->ingress) {
10444                 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
10445         } else {
10446                 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_TX;
10447         }
10448         return 0;
10449 }
10450
10451 /**
10452  * Convert Sample action to DV specification.
10453  *
10454  * @param[in] dev
10455  *   Pointer to rte_eth_dev structure.
10456  * @param[in, out] dev_flow
10457  *   Pointer to the mlx5_flow.
10458  * @param[in] num_of_dest
10459  *   The num of destination.
10460  * @param[in, out] res
10461  *   Pointer to sample resource.
10462  * @param[in, out] mdest_res
10463  *   Pointer to destination array resource.
10464  * @param[in] sample_actions
10465  *   Pointer to sample path actions list.
10466  * @param[in] action_flags
10467  *   Holds the actions detected until now.
10468  * @param[out] error
10469  *   Pointer to the error structure.
10470  *
10471  * @return
10472  *   0 on success, a negative errno value otherwise and rte_errno is set.
10473  */
10474 static int
10475 flow_dv_create_action_sample(struct rte_eth_dev *dev,
10476                              struct mlx5_flow *dev_flow,
10477                              uint32_t num_of_dest,
10478                              struct mlx5_flow_dv_sample_resource *res,
10479                              struct mlx5_flow_dv_dest_array_resource *mdest_res,
10480                              void **sample_actions,
10481                              uint64_t action_flags,
10482                              struct rte_flow_error *error)
10483 {
10484         /* update normal path action resource into last index of array */
10485         uint32_t dest_index = MLX5_MAX_DEST_NUM - 1;
10486         struct mlx5_flow_sub_actions_list *sample_act =
10487                                         &mdest_res->sample_act[dest_index];
10488         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
10489         struct mlx5_flow_rss_desc *rss_desc;
10490         uint32_t normal_idx = 0;
10491         struct mlx5_hrxq *hrxq;
10492         uint32_t hrxq_idx;
10493
10494         MLX5_ASSERT(wks);
10495         rss_desc = &wks->rss_desc;
10496         if (num_of_dest > 1) {
10497                 if (sample_act->action_flags & MLX5_FLOW_ACTION_QUEUE) {
10498                         /* Handle QP action for mirroring */
10499                         hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
10500                                                     rss_desc, &hrxq_idx);
10501                         if (!hrxq)
10502                                 return rte_flow_error_set
10503                                      (error, rte_errno,
10504                                       RTE_FLOW_ERROR_TYPE_ACTION,
10505                                       NULL,
10506                                       "cannot create rx queue");
10507                         normal_idx++;
10508                         mdest_res->sample_idx[dest_index].rix_hrxq = hrxq_idx;
10509                         sample_act->dr_queue_action = hrxq->action;
10510                         if (action_flags & MLX5_FLOW_ACTION_MARK)
10511                                 dev_flow->handle->rix_hrxq = hrxq_idx;
10512                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
10513                 }
10514                 if (sample_act->action_flags & MLX5_FLOW_ACTION_ENCAP) {
10515                         normal_idx++;
10516                         mdest_res->sample_idx[dest_index].rix_encap_decap =
10517                                 dev_flow->handle->dvh.rix_encap_decap;
10518                         sample_act->dr_encap_action =
10519                                 dev_flow->dv.encap_decap->action;
10520                 }
10521                 if (sample_act->action_flags & MLX5_FLOW_ACTION_PORT_ID) {
10522                         normal_idx++;
10523                         mdest_res->sample_idx[dest_index].rix_port_id_action =
10524                                 dev_flow->handle->rix_port_id_action;
10525                         sample_act->dr_port_id_action =
10526                                 dev_flow->dv.port_id_action->action;
10527                 }
10528                 if (sample_act->action_flags & MLX5_FLOW_ACTION_JUMP) {
10529                         normal_idx++;
10530                         mdest_res->sample_idx[dest_index].rix_jump =
10531                                 dev_flow->handle->rix_jump;
10532                         sample_act->dr_jump_action =
10533                                 dev_flow->dv.jump->action;
10534                         dev_flow->handle->rix_jump = 0;
10535                 }
10536                 sample_act->actions_num = normal_idx;
10537                 /* update sample action resource into first index of array */
10538                 mdest_res->ft_type = res->ft_type;
10539                 memcpy(&mdest_res->sample_idx[0], &res->sample_idx,
10540                                 sizeof(struct mlx5_flow_sub_actions_idx));
10541                 memcpy(&mdest_res->sample_act[0], &res->sample_act,
10542                                 sizeof(struct mlx5_flow_sub_actions_list));
10543                 mdest_res->num_of_dest = num_of_dest;
10544                 if (flow_dv_dest_array_resource_register(dev, mdest_res,
10545                                                          dev_flow, error))
10546                         return rte_flow_error_set(error, EINVAL,
10547                                                   RTE_FLOW_ERROR_TYPE_ACTION,
10548                                                   NULL, "can't create sample "
10549                                                   "action");
10550         } else {
10551                 res->sub_actions = sample_actions;
10552                 if (flow_dv_sample_resource_register(dev, res, dev_flow, error))
10553                         return rte_flow_error_set(error, EINVAL,
10554                                                   RTE_FLOW_ERROR_TYPE_ACTION,
10555                                                   NULL,
10556                                                   "can't create sample action");
10557         }
10558         return 0;
10559 }
10560
10561 /**
10562  * Remove an ASO age action from age actions list.
10563  *
10564  * @param[in] dev
10565  *   Pointer to the Ethernet device structure.
10566  * @param[in] age
10567  *   Pointer to the aso age action handler.
10568  */
10569 static void
10570 flow_dv_aso_age_remove_from_age(struct rte_eth_dev *dev,
10571                                 struct mlx5_aso_age_action *age)
10572 {
10573         struct mlx5_age_info *age_info;
10574         struct mlx5_age_param *age_param = &age->age_params;
10575         struct mlx5_priv *priv = dev->data->dev_private;
10576         uint16_t expected = AGE_CANDIDATE;
10577
10578         age_info = GET_PORT_AGE_INFO(priv);
10579         if (!__atomic_compare_exchange_n(&age_param->state, &expected,
10580                                          AGE_FREE, false, __ATOMIC_RELAXED,
10581                                          __ATOMIC_RELAXED)) {
10582                 /**
10583                  * We need the lock even it is age timeout,
10584                  * since age action may still in process.
10585                  */
10586                 rte_spinlock_lock(&age_info->aged_sl);
10587                 LIST_REMOVE(age, next);
10588                 rte_spinlock_unlock(&age_info->aged_sl);
10589                 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
10590         }
10591 }
10592
10593 /**
10594  * Release an ASO age action.
10595  *
10596  * @param[in] dev
10597  *   Pointer to the Ethernet device structure.
10598  * @param[in] age_idx
10599  *   Index of ASO age action to release.
10600  * @param[in] flow
10601  *   True if the release operation is during flow destroy operation.
10602  *   False if the release operation is during action destroy operation.
10603  *
10604  * @return
10605  *   0 when age action was removed, otherwise the number of references.
10606  */
10607 static int
10608 flow_dv_aso_age_release(struct rte_eth_dev *dev, uint32_t age_idx)
10609 {
10610         struct mlx5_priv *priv = dev->data->dev_private;
10611         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
10612         struct mlx5_aso_age_action *age = flow_aso_age_get_by_idx(dev, age_idx);
10613         uint32_t ret = __atomic_sub_fetch(&age->refcnt, 1, __ATOMIC_RELAXED);
10614
10615         if (!ret) {
10616                 flow_dv_aso_age_remove_from_age(dev, age);
10617                 rte_spinlock_lock(&mng->free_sl);
10618                 LIST_INSERT_HEAD(&mng->free, age, next);
10619                 rte_spinlock_unlock(&mng->free_sl);
10620         }
10621         return ret;
10622 }
10623
10624 /**
10625  * Resize the ASO age pools array by MLX5_CNT_CONTAINER_RESIZE pools.
10626  *
10627  * @param[in] dev
10628  *   Pointer to the Ethernet device structure.
10629  *
10630  * @return
10631  *   0 on success, otherwise negative errno value and rte_errno is set.
10632  */
10633 static int
10634 flow_dv_aso_age_pools_resize(struct rte_eth_dev *dev)
10635 {
10636         struct mlx5_priv *priv = dev->data->dev_private;
10637         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
10638         void *old_pools = mng->pools;
10639         uint32_t resize = mng->n + MLX5_CNT_CONTAINER_RESIZE;
10640         uint32_t mem_size = sizeof(struct mlx5_aso_age_pool *) * resize;
10641         void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
10642
10643         if (!pools) {
10644                 rte_errno = ENOMEM;
10645                 return -ENOMEM;
10646         }
10647         if (old_pools) {
10648                 memcpy(pools, old_pools,
10649                        mng->n * sizeof(struct mlx5_flow_counter_pool *));
10650                 mlx5_free(old_pools);
10651         } else {
10652                 /* First ASO flow hit allocation - starting ASO data-path. */
10653                 int ret = mlx5_aso_queue_start(priv->sh);
10654
10655                 if (ret) {
10656                         mlx5_free(pools);
10657                         return ret;
10658                 }
10659         }
10660         mng->n = resize;
10661         mng->pools = pools;
10662         return 0;
10663 }
10664
10665 /**
10666  * Create and initialize a new ASO aging pool.
10667  *
10668  * @param[in] dev
10669  *   Pointer to the Ethernet device structure.
10670  * @param[out] age_free
10671  *   Where to put the pointer of a new age action.
10672  *
10673  * @return
10674  *   The age actions pool pointer and @p age_free is set on success,
10675  *   NULL otherwise and rte_errno is set.
10676  */
10677 static struct mlx5_aso_age_pool *
10678 flow_dv_age_pool_create(struct rte_eth_dev *dev,
10679                         struct mlx5_aso_age_action **age_free)
10680 {
10681         struct mlx5_priv *priv = dev->data->dev_private;
10682         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
10683         struct mlx5_aso_age_pool *pool = NULL;
10684         struct mlx5_devx_obj *obj = NULL;
10685         uint32_t i;
10686
10687         obj = mlx5_devx_cmd_create_flow_hit_aso_obj(priv->sh->ctx,
10688                                                     priv->sh->pdn);
10689         if (!obj) {
10690                 rte_errno = ENODATA;
10691                 DRV_LOG(ERR, "Failed to create flow_hit_aso_obj using DevX.");
10692                 return NULL;
10693         }
10694         pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
10695         if (!pool) {
10696                 claim_zero(mlx5_devx_cmd_destroy(obj));
10697                 rte_errno = ENOMEM;
10698                 return NULL;
10699         }
10700         pool->flow_hit_aso_obj = obj;
10701         pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
10702         rte_spinlock_lock(&mng->resize_sl);
10703         pool->index = mng->next;
10704         /* Resize pools array if there is no room for the new pool in it. */
10705         if (pool->index == mng->n && flow_dv_aso_age_pools_resize(dev)) {
10706                 claim_zero(mlx5_devx_cmd_destroy(obj));
10707                 mlx5_free(pool);
10708                 rte_spinlock_unlock(&mng->resize_sl);
10709                 return NULL;
10710         }
10711         mng->pools[pool->index] = pool;
10712         mng->next++;
10713         rte_spinlock_unlock(&mng->resize_sl);
10714         /* Assign the first action in the new pool, the rest go to free list. */
10715         *age_free = &pool->actions[0];
10716         for (i = 1; i < MLX5_ASO_AGE_ACTIONS_PER_POOL; i++) {
10717                 pool->actions[i].offset = i;
10718                 LIST_INSERT_HEAD(&mng->free, &pool->actions[i], next);
10719         }
10720         return pool;
10721 }
10722
10723 /**
10724  * Allocate a ASO aging bit.
10725  *
10726  * @param[in] dev
10727  *   Pointer to the Ethernet device structure.
10728  * @param[out] error
10729  *   Pointer to the error structure.
10730  *
10731  * @return
10732  *   Index to ASO age action on success, 0 otherwise and rte_errno is set.
10733  */
10734 static uint32_t
10735 flow_dv_aso_age_alloc(struct rte_eth_dev *dev, struct rte_flow_error *error)
10736 {
10737         struct mlx5_priv *priv = dev->data->dev_private;
10738         const struct mlx5_aso_age_pool *pool;
10739         struct mlx5_aso_age_action *age_free = NULL;
10740         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
10741
10742         MLX5_ASSERT(mng);
10743         /* Try to get the next free age action bit. */
10744         rte_spinlock_lock(&mng->free_sl);
10745         age_free = LIST_FIRST(&mng->free);
10746         if (age_free) {
10747                 LIST_REMOVE(age_free, next);
10748         } else if (!flow_dv_age_pool_create(dev, &age_free)) {
10749                 rte_spinlock_unlock(&mng->free_sl);
10750                 rte_flow_error_set(error, rte_errno, RTE_FLOW_ERROR_TYPE_ACTION,
10751                                    NULL, "failed to create ASO age pool");
10752                 return 0; /* 0 is an error. */
10753         }
10754         rte_spinlock_unlock(&mng->free_sl);
10755         pool = container_of
10756           ((const struct mlx5_aso_age_action (*)[MLX5_ASO_AGE_ACTIONS_PER_POOL])
10757                   (age_free - age_free->offset), const struct mlx5_aso_age_pool,
10758                                                                        actions);
10759         if (!age_free->dr_action) {
10760                 int reg_c = mlx5_flow_get_reg_id(dev, MLX5_ASO_FLOW_HIT, 0,
10761                                                  error);
10762
10763                 if (reg_c < 0) {
10764                         rte_flow_error_set(error, rte_errno,
10765                                            RTE_FLOW_ERROR_TYPE_ACTION,
10766                                            NULL, "failed to get reg_c "
10767                                            "for ASO flow hit");
10768                         return 0; /* 0 is an error. */
10769                 }
10770 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
10771                 age_free->dr_action = mlx5_glue->dv_create_flow_action_aso
10772                                 (priv->sh->rx_domain,
10773                                  pool->flow_hit_aso_obj->obj, age_free->offset,
10774                                  MLX5DV_DR_ACTION_FLAGS_ASO_FIRST_HIT_SET,
10775                                  (reg_c - REG_C_0));
10776 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
10777                 if (!age_free->dr_action) {
10778                         rte_errno = errno;
10779                         rte_spinlock_lock(&mng->free_sl);
10780                         LIST_INSERT_HEAD(&mng->free, age_free, next);
10781                         rte_spinlock_unlock(&mng->free_sl);
10782                         rte_flow_error_set(error, rte_errno,
10783                                            RTE_FLOW_ERROR_TYPE_ACTION,
10784                                            NULL, "failed to create ASO "
10785                                            "flow hit action");
10786                         return 0; /* 0 is an error. */
10787                 }
10788         }
10789         __atomic_store_n(&age_free->refcnt, 1, __ATOMIC_RELAXED);
10790         return pool->index | ((age_free->offset + 1) << 16);
10791 }
10792
10793 /**
10794  * Create a age action using ASO mechanism.
10795  *
10796  * @param[in] dev
10797  *   Pointer to rte_eth_dev structure.
10798  * @param[in] age
10799  *   Pointer to the aging action configuration.
10800  * @param[out] error
10801  *   Pointer to the error structure.
10802  *
10803  * @return
10804  *   Index to flow counter on success, 0 otherwise.
10805  */
10806 static uint32_t
10807 flow_dv_translate_create_aso_age(struct rte_eth_dev *dev,
10808                                  const struct rte_flow_action_age *age,
10809                                  struct rte_flow_error *error)
10810 {
10811         uint32_t age_idx = 0;
10812         struct mlx5_aso_age_action *aso_age;
10813
10814         age_idx = flow_dv_aso_age_alloc(dev, error);
10815         if (!age_idx)
10816                 return 0;
10817         aso_age = flow_aso_age_get_by_idx(dev, age_idx);
10818         aso_age->age_params.context = age->context;
10819         aso_age->age_params.timeout = age->timeout;
10820         aso_age->age_params.port_id = dev->data->port_id;
10821         __atomic_store_n(&aso_age->age_params.sec_since_last_hit, 0,
10822                          __ATOMIC_RELAXED);
10823         __atomic_store_n(&aso_age->age_params.state, AGE_CANDIDATE,
10824                          __ATOMIC_RELAXED);
10825         return age_idx;
10826 }
10827
10828 /**
10829  * Fill the flow with DV spec, lock free
10830  * (mutex should be acquired by caller).
10831  *
10832  * @param[in] dev
10833  *   Pointer to rte_eth_dev structure.
10834  * @param[in, out] dev_flow
10835  *   Pointer to the sub flow.
10836  * @param[in] attr
10837  *   Pointer to the flow attributes.
10838  * @param[in] items
10839  *   Pointer to the list of items.
10840  * @param[in] actions
10841  *   Pointer to the list of actions.
10842  * @param[out] error
10843  *   Pointer to the error structure.
10844  *
10845  * @return
10846  *   0 on success, a negative errno value otherwise and rte_errno is set.
10847  */
10848 static int
10849 flow_dv_translate(struct rte_eth_dev *dev,
10850                   struct mlx5_flow *dev_flow,
10851                   const struct rte_flow_attr *attr,
10852                   const struct rte_flow_item items[],
10853                   const struct rte_flow_action actions[],
10854                   struct rte_flow_error *error)
10855 {
10856         struct mlx5_priv *priv = dev->data->dev_private;
10857         struct mlx5_dev_config *dev_conf = &priv->config;
10858         struct rte_flow *flow = dev_flow->flow;
10859         struct mlx5_flow_handle *handle = dev_flow->handle;
10860         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
10861         struct mlx5_flow_rss_desc *rss_desc;
10862         uint64_t item_flags = 0;
10863         uint64_t last_item = 0;
10864         uint64_t action_flags = 0;
10865         struct mlx5_flow_dv_matcher matcher = {
10866                 .mask = {
10867                         .size = sizeof(matcher.mask.buf) -
10868                                 MLX5_ST_SZ_BYTES(fte_match_set_misc4),
10869                 },
10870         };
10871         int actions_n = 0;
10872         bool actions_end = false;
10873         union {
10874                 struct mlx5_flow_dv_modify_hdr_resource res;
10875                 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
10876                             sizeof(struct mlx5_modification_cmd) *
10877                             (MLX5_MAX_MODIFY_NUM + 1)];
10878         } mhdr_dummy;
10879         struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
10880         const struct rte_flow_action_count *count = NULL;
10881         const struct rte_flow_action_age *age = NULL;
10882         union flow_dv_attr flow_attr = { .attr = 0 };
10883         uint32_t tag_be;
10884         union mlx5_flow_tbl_key tbl_key;
10885         uint32_t modify_action_position = UINT32_MAX;
10886         void *match_mask = matcher.mask.buf;
10887         void *match_value = dev_flow->dv.value.buf;
10888         uint8_t next_protocol = 0xff;
10889         struct rte_vlan_hdr vlan = { 0 };
10890         struct mlx5_flow_dv_dest_array_resource mdest_res;
10891         struct mlx5_flow_dv_sample_resource sample_res;
10892         void *sample_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
10893         const struct rte_flow_action_sample *sample = NULL;
10894         struct mlx5_flow_sub_actions_list *sample_act;
10895         uint32_t sample_act_pos = UINT32_MAX;
10896         uint32_t num_of_dest = 0;
10897         int tmp_actions_n = 0;
10898         uint32_t table;
10899         int ret = 0;
10900         const struct mlx5_flow_tunnel *tunnel;
10901         struct flow_grp_info grp_info = {
10902                 .external = !!dev_flow->external,
10903                 .transfer = !!attr->transfer,
10904                 .fdb_def_rule = !!priv->fdb_def_rule,
10905                 .skip_scale = dev_flow->skip_scale &
10906                         (1 << MLX5_SCALE_FLOW_GROUP_BIT),
10907         };
10908
10909         if (!wks)
10910                 return rte_flow_error_set(error, ENOMEM,
10911                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10912                                           NULL,
10913                                           "failed to push flow workspace");
10914         rss_desc = &wks->rss_desc;
10915         memset(&mdest_res, 0, sizeof(struct mlx5_flow_dv_dest_array_resource));
10916         memset(&sample_res, 0, sizeof(struct mlx5_flow_dv_sample_resource));
10917         mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
10918                                            MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
10919         /* update normal path action resource into last index of array */
10920         sample_act = &mdest_res.sample_act[MLX5_MAX_DEST_NUM - 1];
10921         tunnel = is_flow_tunnel_match_rule(dev, attr, items, actions) ?
10922                  flow_items_to_tunnel(items) :
10923                  is_flow_tunnel_steer_rule(dev, attr, items, actions) ?
10924                  flow_actions_to_tunnel(actions) :
10925                  dev_flow->tunnel ? dev_flow->tunnel : NULL;
10926         mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
10927                                            MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
10928         grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
10929                                 (dev, tunnel, attr, items, actions);
10930         ret = mlx5_flow_group_to_table(dev, tunnel, attr->group, &table,
10931                                        &grp_info, error);
10932         if (ret)
10933                 return ret;
10934         dev_flow->dv.group = table;
10935         if (attr->transfer)
10936                 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
10937         /* number of actions must be set to 0 in case of dirty stack. */
10938         mhdr_res->actions_num = 0;
10939         if (is_flow_tunnel_match_rule(dev, attr, items, actions)) {
10940                 /*
10941                  * do not add decap action if match rule drops packet
10942                  * HW rejects rules with decap & drop
10943                  *
10944                  * if tunnel match rule was inserted before matching tunnel set
10945                  * rule flow table used in the match rule must be registered.
10946                  * current implementation handles that in the
10947                  * flow_dv_match_register() at the function end.
10948                  */
10949                 bool add_decap = true;
10950                 const struct rte_flow_action *ptr = actions;
10951
10952                 for (; ptr->type != RTE_FLOW_ACTION_TYPE_END; ptr++) {
10953                         if (ptr->type == RTE_FLOW_ACTION_TYPE_DROP) {
10954                                 add_decap = false;
10955                                 break;
10956                         }
10957                 }
10958                 if (add_decap) {
10959                         if (flow_dv_create_action_l2_decap(dev, dev_flow,
10960                                                            attr->transfer,
10961                                                            error))
10962                                 return -rte_errno;
10963                         dev_flow->dv.actions[actions_n++] =
10964                                         dev_flow->dv.encap_decap->action;
10965                         action_flags |= MLX5_FLOW_ACTION_DECAP;
10966                 }
10967         }
10968         for (; !actions_end ; actions++) {
10969                 const struct rte_flow_action_queue *queue;
10970                 const struct rte_flow_action_rss *rss;
10971                 const struct rte_flow_action *action = actions;
10972                 const uint8_t *rss_key;
10973                 const struct rte_flow_action_meter *mtr;
10974                 struct mlx5_flow_tbl_resource *tbl;
10975                 struct mlx5_aso_age_action *age_act;
10976                 uint32_t port_id = 0;
10977                 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
10978                 int action_type = actions->type;
10979                 const struct rte_flow_action *found_action = NULL;
10980                 struct mlx5_flow_meter *fm = NULL;
10981                 uint32_t jump_group = 0;
10982
10983                 if (!mlx5_flow_os_action_supported(action_type))
10984                         return rte_flow_error_set(error, ENOTSUP,
10985                                                   RTE_FLOW_ERROR_TYPE_ACTION,
10986                                                   actions,
10987                                                   "action not supported");
10988                 switch (action_type) {
10989                 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
10990                         action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
10991                         break;
10992                 case RTE_FLOW_ACTION_TYPE_VOID:
10993                         break;
10994                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
10995                         if (flow_dv_translate_action_port_id(dev, action,
10996                                                              &port_id, error))
10997                                 return -rte_errno;
10998                         port_id_resource.port_id = port_id;
10999                         MLX5_ASSERT(!handle->rix_port_id_action);
11000                         if (flow_dv_port_id_action_resource_register
11001                             (dev, &port_id_resource, dev_flow, error))
11002                                 return -rte_errno;
11003                         dev_flow->dv.actions[actions_n++] =
11004                                         dev_flow->dv.port_id_action->action;
11005                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
11006                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_PORT_ID;
11007                         sample_act->action_flags |= MLX5_FLOW_ACTION_PORT_ID;
11008                         num_of_dest++;
11009                         break;
11010                 case RTE_FLOW_ACTION_TYPE_FLAG:
11011                         action_flags |= MLX5_FLOW_ACTION_FLAG;
11012                         dev_flow->handle->mark = 1;
11013                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
11014                                 struct rte_flow_action_mark mark = {
11015                                         .id = MLX5_FLOW_MARK_DEFAULT,
11016                                 };
11017
11018                                 if (flow_dv_convert_action_mark(dev, &mark,
11019                                                                 mhdr_res,
11020                                                                 error))
11021                                         return -rte_errno;
11022                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
11023                                 break;
11024                         }
11025                         tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
11026                         /*
11027                          * Only one FLAG or MARK is supported per device flow
11028                          * right now. So the pointer to the tag resource must be
11029                          * zero before the register process.
11030                          */
11031                         MLX5_ASSERT(!handle->dvh.rix_tag);
11032                         if (flow_dv_tag_resource_register(dev, tag_be,
11033                                                           dev_flow, error))
11034                                 return -rte_errno;
11035                         MLX5_ASSERT(dev_flow->dv.tag_resource);
11036                         dev_flow->dv.actions[actions_n++] =
11037                                         dev_flow->dv.tag_resource->action;
11038                         break;
11039                 case RTE_FLOW_ACTION_TYPE_MARK:
11040                         action_flags |= MLX5_FLOW_ACTION_MARK;
11041                         dev_flow->handle->mark = 1;
11042                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
11043                                 const struct rte_flow_action_mark *mark =
11044                                         (const struct rte_flow_action_mark *)
11045                                                 actions->conf;
11046
11047                                 if (flow_dv_convert_action_mark(dev, mark,
11048                                                                 mhdr_res,
11049                                                                 error))
11050                                         return -rte_errno;
11051                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
11052                                 break;
11053                         }
11054                         /* Fall-through */
11055                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
11056                         /* Legacy (non-extensive) MARK action. */
11057                         tag_be = mlx5_flow_mark_set
11058                               (((const struct rte_flow_action_mark *)
11059                                (actions->conf))->id);
11060                         MLX5_ASSERT(!handle->dvh.rix_tag);
11061                         if (flow_dv_tag_resource_register(dev, tag_be,
11062                                                           dev_flow, error))
11063                                 return -rte_errno;
11064                         MLX5_ASSERT(dev_flow->dv.tag_resource);
11065                         dev_flow->dv.actions[actions_n++] =
11066                                         dev_flow->dv.tag_resource->action;
11067                         break;
11068                 case RTE_FLOW_ACTION_TYPE_SET_META:
11069                         if (flow_dv_convert_action_set_meta
11070                                 (dev, mhdr_res, attr,
11071                                  (const struct rte_flow_action_set_meta *)
11072                                   actions->conf, error))
11073                                 return -rte_errno;
11074                         action_flags |= MLX5_FLOW_ACTION_SET_META;
11075                         break;
11076                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
11077                         if (flow_dv_convert_action_set_tag
11078                                 (dev, mhdr_res,
11079                                  (const struct rte_flow_action_set_tag *)
11080                                   actions->conf, error))
11081                                 return -rte_errno;
11082                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
11083                         break;
11084                 case RTE_FLOW_ACTION_TYPE_DROP:
11085                         action_flags |= MLX5_FLOW_ACTION_DROP;
11086                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_DROP;
11087                         break;
11088                 case RTE_FLOW_ACTION_TYPE_QUEUE:
11089                         queue = actions->conf;
11090                         rss_desc->queue_num = 1;
11091                         rss_desc->queue[0] = queue->index;
11092                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
11093                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
11094                         sample_act->action_flags |= MLX5_FLOW_ACTION_QUEUE;
11095                         num_of_dest++;
11096                         break;
11097                 case RTE_FLOW_ACTION_TYPE_RSS:
11098                         rss = actions->conf;
11099                         memcpy(rss_desc->queue, rss->queue,
11100                                rss->queue_num * sizeof(uint16_t));
11101                         rss_desc->queue_num = rss->queue_num;
11102                         /* NULL RSS key indicates default RSS key. */
11103                         rss_key = !rss->key ? rss_hash_default_key : rss->key;
11104                         memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
11105                         /*
11106                          * rss->level and rss.types should be set in advance
11107                          * when expanding items for RSS.
11108                          */
11109                         action_flags |= MLX5_FLOW_ACTION_RSS;
11110                         dev_flow->handle->fate_action = rss_desc->shared_rss ?
11111                                 MLX5_FLOW_FATE_SHARED_RSS :
11112                                 MLX5_FLOW_FATE_QUEUE;
11113                         break;
11114                 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
11115                         flow->age = (uint32_t)(uintptr_t)(action->conf);
11116                         age_act = flow_aso_age_get_by_idx(dev, flow->age);
11117                         __atomic_fetch_add(&age_act->refcnt, 1,
11118                                            __ATOMIC_RELAXED);
11119                         dev_flow->dv.actions[actions_n++] = age_act->dr_action;
11120                         action_flags |= MLX5_FLOW_ACTION_AGE;
11121                         break;
11122                 case RTE_FLOW_ACTION_TYPE_AGE:
11123                         if (priv->sh->flow_hit_aso_en && attr->group) {
11124                                 /*
11125                                  * Create one shared age action, to be used
11126                                  * by all sub-flows.
11127                                  */
11128                                 if (!flow->age) {
11129                                         flow->age =
11130                                                 flow_dv_translate_create_aso_age
11131                                                         (dev, action->conf,
11132                                                          error);
11133                                         if (!flow->age)
11134                                                 return rte_flow_error_set
11135                                                 (error, rte_errno,
11136                                                  RTE_FLOW_ERROR_TYPE_ACTION,
11137                                                  NULL,
11138                                                  "can't create ASO age action");
11139                                 }
11140                                 dev_flow->dv.actions[actions_n++] =
11141                                           (flow_aso_age_get_by_idx
11142                                                 (dev, flow->age))->dr_action;
11143                                 action_flags |= MLX5_FLOW_ACTION_AGE;
11144                                 break;
11145                         }
11146                         /* Fall-through */
11147                 case RTE_FLOW_ACTION_TYPE_COUNT:
11148                         if (!dev_conf->devx) {
11149                                 return rte_flow_error_set
11150                                               (error, ENOTSUP,
11151                                                RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11152                                                NULL,
11153                                                "count action not supported");
11154                         }
11155                         /* Save information first, will apply later. */
11156                         if (actions->type == RTE_FLOW_ACTION_TYPE_COUNT)
11157                                 count = action->conf;
11158                         else
11159                                 age = action->conf;
11160                         action_flags |= MLX5_FLOW_ACTION_COUNT;
11161                         break;
11162                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
11163                         dev_flow->dv.actions[actions_n++] =
11164                                                 priv->sh->pop_vlan_action;
11165                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
11166                         break;
11167                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
11168                         if (!(action_flags &
11169                               MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
11170                                 flow_dev_get_vlan_info_from_items(items, &vlan);
11171                         vlan.eth_proto = rte_be_to_cpu_16
11172                              ((((const struct rte_flow_action_of_push_vlan *)
11173                                                    actions->conf)->ethertype));
11174                         found_action = mlx5_flow_find_action
11175                                         (actions + 1,
11176                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
11177                         if (found_action)
11178                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
11179                         found_action = mlx5_flow_find_action
11180                                         (actions + 1,
11181                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
11182                         if (found_action)
11183                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
11184                         if (flow_dv_create_action_push_vlan
11185                                             (dev, attr, &vlan, dev_flow, error))
11186                                 return -rte_errno;
11187                         dev_flow->dv.actions[actions_n++] =
11188                                         dev_flow->dv.push_vlan_res->action;
11189                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
11190                         break;
11191                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
11192                         /* of_vlan_push action handled this action */
11193                         MLX5_ASSERT(action_flags &
11194                                     MLX5_FLOW_ACTION_OF_PUSH_VLAN);
11195                         break;
11196                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
11197                         if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
11198                                 break;
11199                         flow_dev_get_vlan_info_from_items(items, &vlan);
11200                         mlx5_update_vlan_vid_pcp(actions, &vlan);
11201                         /* If no VLAN push - this is a modify header action */
11202                         if (flow_dv_convert_action_modify_vlan_vid
11203                                                 (mhdr_res, actions, error))
11204                                 return -rte_errno;
11205                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
11206                         break;
11207                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
11208                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
11209                         if (flow_dv_create_action_l2_encap(dev, actions,
11210                                                            dev_flow,
11211                                                            attr->transfer,
11212                                                            error))
11213                                 return -rte_errno;
11214                         dev_flow->dv.actions[actions_n++] =
11215                                         dev_flow->dv.encap_decap->action;
11216                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
11217                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
11218                                 sample_act->action_flags |=
11219                                                         MLX5_FLOW_ACTION_ENCAP;
11220                         break;
11221                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
11222                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
11223                         if (flow_dv_create_action_l2_decap(dev, dev_flow,
11224                                                            attr->transfer,
11225                                                            error))
11226                                 return -rte_errno;
11227                         dev_flow->dv.actions[actions_n++] =
11228                                         dev_flow->dv.encap_decap->action;
11229                         action_flags |= MLX5_FLOW_ACTION_DECAP;
11230                         break;
11231                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
11232                         /* Handle encap with preceding decap. */
11233                         if (action_flags & MLX5_FLOW_ACTION_DECAP) {
11234                                 if (flow_dv_create_action_raw_encap
11235                                         (dev, actions, dev_flow, attr, error))
11236                                         return -rte_errno;
11237                                 dev_flow->dv.actions[actions_n++] =
11238                                         dev_flow->dv.encap_decap->action;
11239                         } else {
11240                                 /* Handle encap without preceding decap. */
11241                                 if (flow_dv_create_action_l2_encap
11242                                     (dev, actions, dev_flow, attr->transfer,
11243                                      error))
11244                                         return -rte_errno;
11245                                 dev_flow->dv.actions[actions_n++] =
11246                                         dev_flow->dv.encap_decap->action;
11247                         }
11248                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
11249                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
11250                                 sample_act->action_flags |=
11251                                                         MLX5_FLOW_ACTION_ENCAP;
11252                         break;
11253                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
11254                         while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
11255                                 ;
11256                         if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
11257                                 if (flow_dv_create_action_l2_decap
11258                                     (dev, dev_flow, attr->transfer, error))
11259                                         return -rte_errno;
11260                                 dev_flow->dv.actions[actions_n++] =
11261                                         dev_flow->dv.encap_decap->action;
11262                         }
11263                         /* If decap is followed by encap, handle it at encap. */
11264                         action_flags |= MLX5_FLOW_ACTION_DECAP;
11265                         break;
11266                 case RTE_FLOW_ACTION_TYPE_JUMP:
11267                         jump_group = ((const struct rte_flow_action_jump *)
11268                                                         action->conf)->group;
11269                         grp_info.std_tbl_fix = 0;
11270                         if (dev_flow->skip_scale &
11271                                 (1 << MLX5_SCALE_JUMP_FLOW_GROUP_BIT))
11272                                 grp_info.skip_scale = 1;
11273                         else
11274                                 grp_info.skip_scale = 0;
11275                         ret = mlx5_flow_group_to_table(dev, tunnel,
11276                                                        jump_group,
11277                                                        &table,
11278                                                        &grp_info, error);
11279                         if (ret)
11280                                 return ret;
11281                         tbl = flow_dv_tbl_resource_get(dev, table, attr->egress,
11282                                                        attr->transfer,
11283                                                        !!dev_flow->external,
11284                                                        tunnel, jump_group, 0,
11285                                                        error);
11286                         if (!tbl)
11287                                 return rte_flow_error_set
11288                                                 (error, errno,
11289                                                  RTE_FLOW_ERROR_TYPE_ACTION,
11290                                                  NULL,
11291                                                  "cannot create jump action.");
11292                         if (flow_dv_jump_tbl_resource_register
11293                             (dev, tbl, dev_flow, error)) {
11294                                 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
11295                                 return rte_flow_error_set
11296                                                 (error, errno,
11297                                                  RTE_FLOW_ERROR_TYPE_ACTION,
11298                                                  NULL,
11299                                                  "cannot create jump action.");
11300                         }
11301                         dev_flow->dv.actions[actions_n++] =
11302                                         dev_flow->dv.jump->action;
11303                         action_flags |= MLX5_FLOW_ACTION_JUMP;
11304                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_JUMP;
11305                         sample_act->action_flags |= MLX5_FLOW_ACTION_JUMP;
11306                         num_of_dest++;
11307                         break;
11308                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
11309                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
11310                         if (flow_dv_convert_action_modify_mac
11311                                         (mhdr_res, actions, error))
11312                                 return -rte_errno;
11313                         action_flags |= actions->type ==
11314                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
11315                                         MLX5_FLOW_ACTION_SET_MAC_SRC :
11316                                         MLX5_FLOW_ACTION_SET_MAC_DST;
11317                         break;
11318                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
11319                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
11320                         if (flow_dv_convert_action_modify_ipv4
11321                                         (mhdr_res, actions, error))
11322                                 return -rte_errno;
11323                         action_flags |= actions->type ==
11324                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
11325                                         MLX5_FLOW_ACTION_SET_IPV4_SRC :
11326                                         MLX5_FLOW_ACTION_SET_IPV4_DST;
11327                         break;
11328                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
11329                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
11330                         if (flow_dv_convert_action_modify_ipv6
11331                                         (mhdr_res, actions, error))
11332                                 return -rte_errno;
11333                         action_flags |= actions->type ==
11334                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
11335                                         MLX5_FLOW_ACTION_SET_IPV6_SRC :
11336                                         MLX5_FLOW_ACTION_SET_IPV6_DST;
11337                         break;
11338                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
11339                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
11340                         if (flow_dv_convert_action_modify_tp
11341                                         (mhdr_res, actions, items,
11342                                          &flow_attr, dev_flow, !!(action_flags &
11343                                          MLX5_FLOW_ACTION_DECAP), error))
11344                                 return -rte_errno;
11345                         action_flags |= actions->type ==
11346                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
11347                                         MLX5_FLOW_ACTION_SET_TP_SRC :
11348                                         MLX5_FLOW_ACTION_SET_TP_DST;
11349                         break;
11350                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
11351                         if (flow_dv_convert_action_modify_dec_ttl
11352                                         (mhdr_res, items, &flow_attr, dev_flow,
11353                                          !!(action_flags &
11354                                          MLX5_FLOW_ACTION_DECAP), error))
11355                                 return -rte_errno;
11356                         action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
11357                         break;
11358                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
11359                         if (flow_dv_convert_action_modify_ttl
11360                                         (mhdr_res, actions, items, &flow_attr,
11361                                          dev_flow, !!(action_flags &
11362                                          MLX5_FLOW_ACTION_DECAP), error))
11363                                 return -rte_errno;
11364                         action_flags |= MLX5_FLOW_ACTION_SET_TTL;
11365                         break;
11366                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
11367                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
11368                         if (flow_dv_convert_action_modify_tcp_seq
11369                                         (mhdr_res, actions, error))
11370                                 return -rte_errno;
11371                         action_flags |= actions->type ==
11372                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
11373                                         MLX5_FLOW_ACTION_INC_TCP_SEQ :
11374                                         MLX5_FLOW_ACTION_DEC_TCP_SEQ;
11375                         break;
11376
11377                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
11378                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
11379                         if (flow_dv_convert_action_modify_tcp_ack
11380                                         (mhdr_res, actions, error))
11381                                 return -rte_errno;
11382                         action_flags |= actions->type ==
11383                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
11384                                         MLX5_FLOW_ACTION_INC_TCP_ACK :
11385                                         MLX5_FLOW_ACTION_DEC_TCP_ACK;
11386                         break;
11387                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
11388                         if (flow_dv_convert_action_set_reg
11389                                         (mhdr_res, actions, error))
11390                                 return -rte_errno;
11391                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
11392                         break;
11393                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
11394                         if (flow_dv_convert_action_copy_mreg
11395                                         (dev, mhdr_res, actions, error))
11396                                 return -rte_errno;
11397                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
11398                         break;
11399                 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
11400                         action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
11401                         dev_flow->handle->fate_action =
11402                                         MLX5_FLOW_FATE_DEFAULT_MISS;
11403                         break;
11404                 case RTE_FLOW_ACTION_TYPE_METER:
11405                         mtr = actions->conf;
11406                         if (!flow->meter) {
11407                                 fm = mlx5_flow_meter_attach(priv, mtr->mtr_id,
11408                                                             attr, error);
11409                                 if (!fm)
11410                                         return rte_flow_error_set(error,
11411                                                 rte_errno,
11412                                                 RTE_FLOW_ERROR_TYPE_ACTION,
11413                                                 NULL,
11414                                                 "meter not found "
11415                                                 "or invalid parameters");
11416                                 flow->meter = fm->idx;
11417                         }
11418                         /* Set the meter action. */
11419                         if (!fm) {
11420                                 fm = mlx5_ipool_get(priv->sh->ipool
11421                                                 [MLX5_IPOOL_MTR], flow->meter);
11422                                 if (!fm)
11423                                         return rte_flow_error_set(error,
11424                                                 rte_errno,
11425                                                 RTE_FLOW_ERROR_TYPE_ACTION,
11426                                                 NULL,
11427                                                 "meter not found "
11428                                                 "or invalid parameters");
11429                         }
11430                         dev_flow->dv.actions[actions_n++] =
11431                                 fm->mfts->meter_action;
11432                         action_flags |= MLX5_FLOW_ACTION_METER;
11433                         break;
11434                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
11435                         if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
11436                                                               actions, error))
11437                                 return -rte_errno;
11438                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
11439                         break;
11440                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
11441                         if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
11442                                                               actions, error))
11443                                 return -rte_errno;
11444                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
11445                         break;
11446                 case RTE_FLOW_ACTION_TYPE_SAMPLE:
11447                         sample_act_pos = actions_n;
11448                         sample = (const struct rte_flow_action_sample *)
11449                                  action->conf;
11450                         actions_n++;
11451                         action_flags |= MLX5_FLOW_ACTION_SAMPLE;
11452                         /* put encap action into group if work with port id */
11453                         if ((action_flags & MLX5_FLOW_ACTION_ENCAP) &&
11454                             (action_flags & MLX5_FLOW_ACTION_PORT_ID))
11455                                 sample_act->action_flags |=
11456                                                         MLX5_FLOW_ACTION_ENCAP;
11457                         break;
11458                 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
11459                         if (flow_dv_convert_action_modify_field
11460                                         (dev, mhdr_res, actions, attr, error))
11461                                 return -rte_errno;
11462                         action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
11463                         break;
11464                 case RTE_FLOW_ACTION_TYPE_END:
11465                         actions_end = true;
11466                         if (mhdr_res->actions_num) {
11467                                 /* create modify action if needed. */
11468                                 if (flow_dv_modify_hdr_resource_register
11469                                         (dev, mhdr_res, dev_flow, error))
11470                                         return -rte_errno;
11471                                 dev_flow->dv.actions[modify_action_position] =
11472                                         handle->dvh.modify_hdr->action;
11473                         }
11474                         if (action_flags & MLX5_FLOW_ACTION_COUNT) {
11475                                 /*
11476                                  * Create one count action, to be used
11477                                  * by all sub-flows.
11478                                  */
11479                                 if (!flow->counter) {
11480                                         flow->counter =
11481                                                 flow_dv_translate_create_counter
11482                                                         (dev, dev_flow, count,
11483                                                          age);
11484                                         if (!flow->counter)
11485                                                 return rte_flow_error_set
11486                                                 (error, rte_errno,
11487                                                  RTE_FLOW_ERROR_TYPE_ACTION,
11488                                                  NULL, "cannot create counter"
11489                                                  " object.");
11490                                 }
11491                                 dev_flow->dv.actions[actions_n] =
11492                                           (flow_dv_counter_get_by_idx(dev,
11493                                           flow->counter, NULL))->action;
11494                                 actions_n++;
11495                         }
11496                 default:
11497                         break;
11498                 }
11499                 if (mhdr_res->actions_num &&
11500                     modify_action_position == UINT32_MAX)
11501                         modify_action_position = actions_n++;
11502         }
11503         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
11504                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
11505                 int item_type = items->type;
11506
11507                 if (!mlx5_flow_os_item_supported(item_type))
11508                         return rte_flow_error_set(error, ENOTSUP,
11509                                                   RTE_FLOW_ERROR_TYPE_ITEM,
11510                                                   NULL, "item not supported");
11511                 switch (item_type) {
11512                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
11513                         flow_dv_translate_item_port_id
11514                                 (dev, match_mask, match_value, items, attr);
11515                         last_item = MLX5_FLOW_ITEM_PORT_ID;
11516                         break;
11517                 case RTE_FLOW_ITEM_TYPE_ETH:
11518                         flow_dv_translate_item_eth(match_mask, match_value,
11519                                                    items, tunnel,
11520                                                    dev_flow->dv.group);
11521                         matcher.priority = action_flags &
11522                                         MLX5_FLOW_ACTION_DEFAULT_MISS &&
11523                                         !dev_flow->external ?
11524                                         MLX5_PRIORITY_MAP_L3 :
11525                                         MLX5_PRIORITY_MAP_L2;
11526                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
11527                                              MLX5_FLOW_LAYER_OUTER_L2;
11528                         break;
11529                 case RTE_FLOW_ITEM_TYPE_VLAN:
11530                         flow_dv_translate_item_vlan(dev_flow,
11531                                                     match_mask, match_value,
11532                                                     items, tunnel,
11533                                                     dev_flow->dv.group);
11534                         matcher.priority = MLX5_PRIORITY_MAP_L2;
11535                         last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
11536                                               MLX5_FLOW_LAYER_INNER_VLAN) :
11537                                              (MLX5_FLOW_LAYER_OUTER_L2 |
11538                                               MLX5_FLOW_LAYER_OUTER_VLAN);
11539                         break;
11540                 case RTE_FLOW_ITEM_TYPE_IPV4:
11541                         mlx5_flow_tunnel_ip_check(items, next_protocol,
11542                                                   &item_flags, &tunnel);
11543                         flow_dv_translate_item_ipv4(match_mask, match_value,
11544                                                     items, tunnel,
11545                                                     dev_flow->dv.group);
11546                         matcher.priority = MLX5_PRIORITY_MAP_L3;
11547                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
11548                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
11549                         if (items->mask != NULL &&
11550                             ((const struct rte_flow_item_ipv4 *)
11551                              items->mask)->hdr.next_proto_id) {
11552                                 next_protocol =
11553                                         ((const struct rte_flow_item_ipv4 *)
11554                                          (items->spec))->hdr.next_proto_id;
11555                                 next_protocol &=
11556                                         ((const struct rte_flow_item_ipv4 *)
11557                                          (items->mask))->hdr.next_proto_id;
11558                         } else {
11559                                 /* Reset for inner layer. */
11560                                 next_protocol = 0xff;
11561                         }
11562                         break;
11563                 case RTE_FLOW_ITEM_TYPE_IPV6:
11564                         mlx5_flow_tunnel_ip_check(items, next_protocol,
11565                                                   &item_flags, &tunnel);
11566                         flow_dv_translate_item_ipv6(match_mask, match_value,
11567                                                     items, tunnel,
11568                                                     dev_flow->dv.group);
11569                         matcher.priority = MLX5_PRIORITY_MAP_L3;
11570                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
11571                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
11572                         if (items->mask != NULL &&
11573                             ((const struct rte_flow_item_ipv6 *)
11574                              items->mask)->hdr.proto) {
11575                                 next_protocol =
11576                                         ((const struct rte_flow_item_ipv6 *)
11577                                          items->spec)->hdr.proto;
11578                                 next_protocol &=
11579                                         ((const struct rte_flow_item_ipv6 *)
11580                                          items->mask)->hdr.proto;
11581                         } else {
11582                                 /* Reset for inner layer. */
11583                                 next_protocol = 0xff;
11584                         }
11585                         break;
11586                 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
11587                         flow_dv_translate_item_ipv6_frag_ext(match_mask,
11588                                                              match_value,
11589                                                              items, tunnel);
11590                         last_item = tunnel ?
11591                                         MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
11592                                         MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
11593                         if (items->mask != NULL &&
11594                             ((const struct rte_flow_item_ipv6_frag_ext *)
11595                              items->mask)->hdr.next_header) {
11596                                 next_protocol =
11597                                 ((const struct rte_flow_item_ipv6_frag_ext *)
11598                                  items->spec)->hdr.next_header;
11599                                 next_protocol &=
11600                                 ((const struct rte_flow_item_ipv6_frag_ext *)
11601                                  items->mask)->hdr.next_header;
11602                         } else {
11603                                 /* Reset for inner layer. */
11604                                 next_protocol = 0xff;
11605                         }
11606                         break;
11607                 case RTE_FLOW_ITEM_TYPE_TCP:
11608                         flow_dv_translate_item_tcp(match_mask, match_value,
11609                                                    items, tunnel);
11610                         matcher.priority = MLX5_PRIORITY_MAP_L4;
11611                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
11612                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
11613                         break;
11614                 case RTE_FLOW_ITEM_TYPE_UDP:
11615                         flow_dv_translate_item_udp(match_mask, match_value,
11616                                                    items, tunnel);
11617                         matcher.priority = MLX5_PRIORITY_MAP_L4;
11618                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
11619                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
11620                         break;
11621                 case RTE_FLOW_ITEM_TYPE_GRE:
11622                         flow_dv_translate_item_gre(match_mask, match_value,
11623                                                    items, tunnel);
11624                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11625                         last_item = MLX5_FLOW_LAYER_GRE;
11626                         break;
11627                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
11628                         flow_dv_translate_item_gre_key(match_mask,
11629                                                        match_value, items);
11630                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
11631                         break;
11632                 case RTE_FLOW_ITEM_TYPE_NVGRE:
11633                         flow_dv_translate_item_nvgre(match_mask, match_value,
11634                                                      items, tunnel);
11635                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11636                         last_item = MLX5_FLOW_LAYER_GRE;
11637                         break;
11638                 case RTE_FLOW_ITEM_TYPE_VXLAN:
11639                         flow_dv_translate_item_vxlan(match_mask, match_value,
11640                                                      items, tunnel);
11641                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11642                         last_item = MLX5_FLOW_LAYER_VXLAN;
11643                         break;
11644                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
11645                         flow_dv_translate_item_vxlan_gpe(match_mask,
11646                                                          match_value, items,
11647                                                          tunnel);
11648                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11649                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
11650                         break;
11651                 case RTE_FLOW_ITEM_TYPE_GENEVE:
11652                         flow_dv_translate_item_geneve(match_mask, match_value,
11653                                                       items, tunnel);
11654                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11655                         last_item = MLX5_FLOW_LAYER_GENEVE;
11656                         break;
11657                 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
11658                         ret = flow_dv_translate_item_geneve_opt(dev, match_mask,
11659                                                           match_value,
11660                                                           items, error);
11661                         if (ret)
11662                                 return rte_flow_error_set(error, -ret,
11663                                         RTE_FLOW_ERROR_TYPE_ITEM, NULL,
11664                                         "cannot create GENEVE TLV option");
11665                         flow->geneve_tlv_option = 1;
11666                         last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
11667                         break;
11668                 case RTE_FLOW_ITEM_TYPE_MPLS:
11669                         flow_dv_translate_item_mpls(match_mask, match_value,
11670                                                     items, last_item, tunnel);
11671                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11672                         last_item = MLX5_FLOW_LAYER_MPLS;
11673                         break;
11674                 case RTE_FLOW_ITEM_TYPE_MARK:
11675                         flow_dv_translate_item_mark(dev, match_mask,
11676                                                     match_value, items);
11677                         last_item = MLX5_FLOW_ITEM_MARK;
11678                         break;
11679                 case RTE_FLOW_ITEM_TYPE_META:
11680                         flow_dv_translate_item_meta(dev, match_mask,
11681                                                     match_value, attr, items);
11682                         last_item = MLX5_FLOW_ITEM_METADATA;
11683                         break;
11684                 case RTE_FLOW_ITEM_TYPE_ICMP:
11685                         flow_dv_translate_item_icmp(match_mask, match_value,
11686                                                     items, tunnel);
11687                         last_item = MLX5_FLOW_LAYER_ICMP;
11688                         break;
11689                 case RTE_FLOW_ITEM_TYPE_ICMP6:
11690                         flow_dv_translate_item_icmp6(match_mask, match_value,
11691                                                       items, tunnel);
11692                         last_item = MLX5_FLOW_LAYER_ICMP6;
11693                         break;
11694                 case RTE_FLOW_ITEM_TYPE_TAG:
11695                         flow_dv_translate_item_tag(dev, match_mask,
11696                                                    match_value, items);
11697                         last_item = MLX5_FLOW_ITEM_TAG;
11698                         break;
11699                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
11700                         flow_dv_translate_mlx5_item_tag(dev, match_mask,
11701                                                         match_value, items);
11702                         last_item = MLX5_FLOW_ITEM_TAG;
11703                         break;
11704                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
11705                         flow_dv_translate_item_tx_queue(dev, match_mask,
11706                                                         match_value,
11707                                                         items);
11708                         last_item = MLX5_FLOW_ITEM_TX_QUEUE;
11709                         break;
11710                 case RTE_FLOW_ITEM_TYPE_GTP:
11711                         flow_dv_translate_item_gtp(match_mask, match_value,
11712                                                    items, tunnel);
11713                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11714                         last_item = MLX5_FLOW_LAYER_GTP;
11715                         break;
11716                 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
11717                         ret = flow_dv_translate_item_gtp_psc(match_mask,
11718                                                           match_value,
11719                                                           items);
11720                         if (ret)
11721                                 return rte_flow_error_set(error, -ret,
11722                                         RTE_FLOW_ERROR_TYPE_ITEM, NULL,
11723                                         "cannot create GTP PSC item");
11724                         last_item = MLX5_FLOW_LAYER_GTP_PSC;
11725                         break;
11726                 case RTE_FLOW_ITEM_TYPE_ECPRI:
11727                         if (!mlx5_flex_parser_ecpri_exist(dev)) {
11728                                 /* Create it only the first time to be used. */
11729                                 ret = mlx5_flex_parser_ecpri_alloc(dev);
11730                                 if (ret)
11731                                         return rte_flow_error_set
11732                                                 (error, -ret,
11733                                                 RTE_FLOW_ERROR_TYPE_ITEM,
11734                                                 NULL,
11735                                                 "cannot create eCPRI parser");
11736                         }
11737                         /* Adjust the length matcher and device flow value. */
11738                         matcher.mask.size = MLX5_ST_SZ_BYTES(fte_match_param);
11739                         dev_flow->dv.value.size =
11740                                         MLX5_ST_SZ_BYTES(fte_match_param);
11741                         flow_dv_translate_item_ecpri(dev, match_mask,
11742                                                      match_value, items);
11743                         /* No other protocol should follow eCPRI layer. */
11744                         last_item = MLX5_FLOW_LAYER_ECPRI;
11745                         break;
11746                 default:
11747                         break;
11748                 }
11749                 item_flags |= last_item;
11750         }
11751         /*
11752          * When E-Switch mode is enabled, we have two cases where we need to
11753          * set the source port manually.
11754          * The first one, is in case of Nic steering rule, and the second is
11755          * E-Switch rule where no port_id item was found. In both cases
11756          * the source port is set according the current port in use.
11757          */
11758         if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
11759             (priv->representor || priv->master)) {
11760                 if (flow_dv_translate_item_port_id(dev, match_mask,
11761                                                    match_value, NULL, attr))
11762                         return -rte_errno;
11763         }
11764 #ifdef RTE_LIBRTE_MLX5_DEBUG
11765         MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
11766                                               dev_flow->dv.value.buf));
11767 #endif
11768         /*
11769          * Layers may be already initialized from prefix flow if this dev_flow
11770          * is the suffix flow.
11771          */
11772         handle->layers |= item_flags;
11773         if (action_flags & MLX5_FLOW_ACTION_RSS)
11774                 flow_dv_hashfields_set(dev_flow, rss_desc);
11775         /* If has RSS action in the sample action, the Sample/Mirror resource
11776          * should be registered after the hash filed be update.
11777          */
11778         if (action_flags & MLX5_FLOW_ACTION_SAMPLE) {
11779                 ret = flow_dv_translate_action_sample(dev,
11780                                                       sample,
11781                                                       dev_flow, attr,
11782                                                       &num_of_dest,
11783                                                       sample_actions,
11784                                                       &sample_res,
11785                                                       error);
11786                 if (ret < 0)
11787                         return ret;
11788                 ret = flow_dv_create_action_sample(dev,
11789                                                    dev_flow,
11790                                                    num_of_dest,
11791                                                    &sample_res,
11792                                                    &mdest_res,
11793                                                    sample_actions,
11794                                                    action_flags,
11795                                                    error);
11796                 if (ret < 0)
11797                         return rte_flow_error_set
11798                                                 (error, rte_errno,
11799                                                 RTE_FLOW_ERROR_TYPE_ACTION,
11800                                                 NULL,
11801                                                 "cannot create sample action");
11802                 if (num_of_dest > 1) {
11803                         dev_flow->dv.actions[sample_act_pos] =
11804                         dev_flow->dv.dest_array_res->action;
11805                 } else {
11806                         dev_flow->dv.actions[sample_act_pos] =
11807                         dev_flow->dv.sample_res->verbs_action;
11808                 }
11809         }
11810         /*
11811          * For multiple destination (sample action with ratio=1), the encap
11812          * action and port id action will be combined into group action.
11813          * So need remove the original these actions in the flow and only
11814          * use the sample action instead of.
11815          */
11816         if (num_of_dest > 1 &&
11817             (sample_act->dr_port_id_action || sample_act->dr_jump_action)) {
11818                 int i;
11819                 void *temp_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
11820
11821                 for (i = 0; i < actions_n; i++) {
11822                         if ((sample_act->dr_encap_action &&
11823                                 sample_act->dr_encap_action ==
11824                                 dev_flow->dv.actions[i]) ||
11825                                 (sample_act->dr_port_id_action &&
11826                                 sample_act->dr_port_id_action ==
11827                                 dev_flow->dv.actions[i]) ||
11828                                 (sample_act->dr_jump_action &&
11829                                 sample_act->dr_jump_action ==
11830                                 dev_flow->dv.actions[i]))
11831                                 continue;
11832                         temp_actions[tmp_actions_n++] = dev_flow->dv.actions[i];
11833                 }
11834                 memcpy((void *)dev_flow->dv.actions,
11835                                 (void *)temp_actions,
11836                                 tmp_actions_n * sizeof(void *));
11837                 actions_n = tmp_actions_n;
11838         }
11839         dev_flow->dv.actions_n = actions_n;
11840         dev_flow->act_flags = action_flags;
11841         /* Register matcher. */
11842         matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
11843                                     matcher.mask.size);
11844         matcher.priority = mlx5_get_matcher_priority(dev, attr,
11845                                         matcher.priority);
11846         /* reserved field no needs to be set to 0 here. */
11847         tbl_key.domain = attr->transfer;
11848         tbl_key.direction = attr->egress;
11849         tbl_key.table_id = dev_flow->dv.group;
11850         if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow,
11851                                      tunnel, attr->group, error))
11852                 return -rte_errno;
11853         return 0;
11854 }
11855
11856 /**
11857  * Set hash RX queue by hash fields (see enum ibv_rx_hash_fields)
11858  * and tunnel.
11859  *
11860  * @param[in, out] action
11861  *   Shred RSS action holding hash RX queue objects.
11862  * @param[in] hash_fields
11863  *   Defines combination of packet fields to participate in RX hash.
11864  * @param[in] tunnel
11865  *   Tunnel type
11866  * @param[in] hrxq_idx
11867  *   Hash RX queue index to set.
11868  *
11869  * @return
11870  *   0 on success, otherwise negative errno value.
11871  */
11872 static int
11873 __flow_dv_action_rss_hrxq_set(struct mlx5_shared_action_rss *action,
11874                               const uint64_t hash_fields,
11875                               const int tunnel,
11876                               uint32_t hrxq_idx)
11877 {
11878         uint32_t *hrxqs = tunnel ? action->hrxq : action->hrxq_tunnel;
11879
11880         switch (hash_fields & ~IBV_RX_HASH_INNER) {
11881         case MLX5_RSS_HASH_IPV4:
11882                 hrxqs[0] = hrxq_idx;
11883                 return 0;
11884         case MLX5_RSS_HASH_IPV4_TCP:
11885                 hrxqs[1] = hrxq_idx;
11886                 return 0;
11887         case MLX5_RSS_HASH_IPV4_UDP:
11888                 hrxqs[2] = hrxq_idx;
11889                 return 0;
11890         case MLX5_RSS_HASH_IPV6:
11891                 hrxqs[3] = hrxq_idx;
11892                 return 0;
11893         case MLX5_RSS_HASH_IPV6_TCP:
11894                 hrxqs[4] = hrxq_idx;
11895                 return 0;
11896         case MLX5_RSS_HASH_IPV6_UDP:
11897                 hrxqs[5] = hrxq_idx;
11898                 return 0;
11899         case MLX5_RSS_HASH_NONE:
11900                 hrxqs[6] = hrxq_idx;
11901                 return 0;
11902         default:
11903                 return -1;
11904         }
11905 }
11906
11907 /**
11908  * Look up for hash RX queue by hash fields (see enum ibv_rx_hash_fields)
11909  * and tunnel.
11910  *
11911  * @param[in] dev
11912  *   Pointer to the Ethernet device structure.
11913  * @param[in] idx
11914  *   Shared RSS action ID holding hash RX queue objects.
11915  * @param[in] hash_fields
11916  *   Defines combination of packet fields to participate in RX hash.
11917  * @param[in] tunnel
11918  *   Tunnel type
11919  *
11920  * @return
11921  *   Valid hash RX queue index, otherwise 0.
11922  */
11923 static uint32_t
11924 __flow_dv_action_rss_hrxq_lookup(struct rte_eth_dev *dev, uint32_t idx,
11925                                  const uint64_t hash_fields,
11926                                  const int tunnel)
11927 {
11928         struct mlx5_priv *priv = dev->data->dev_private;
11929         struct mlx5_shared_action_rss *shared_rss =
11930             mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
11931         const uint32_t *hrxqs = tunnel ? shared_rss->hrxq :
11932                                                         shared_rss->hrxq_tunnel;
11933
11934         switch (hash_fields & ~IBV_RX_HASH_INNER) {
11935         case MLX5_RSS_HASH_IPV4:
11936                 return hrxqs[0];
11937         case MLX5_RSS_HASH_IPV4_TCP:
11938                 return hrxqs[1];
11939         case MLX5_RSS_HASH_IPV4_UDP:
11940                 return hrxqs[2];
11941         case MLX5_RSS_HASH_IPV6:
11942                 return hrxqs[3];
11943         case MLX5_RSS_HASH_IPV6_TCP:
11944                 return hrxqs[4];
11945         case MLX5_RSS_HASH_IPV6_UDP:
11946                 return hrxqs[5];
11947         case MLX5_RSS_HASH_NONE:
11948                 return hrxqs[6];
11949         default:
11950                 return 0;
11951         }
11952 }
11953
11954 /**
11955  * Apply the flow to the NIC, lock free,
11956  * (mutex should be acquired by caller).
11957  *
11958  * @param[in] dev
11959  *   Pointer to the Ethernet device structure.
11960  * @param[in, out] flow
11961  *   Pointer to flow structure.
11962  * @param[out] error
11963  *   Pointer to error structure.
11964  *
11965  * @return
11966  *   0 on success, a negative errno value otherwise and rte_errno is set.
11967  */
11968 static int
11969 flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
11970               struct rte_flow_error *error)
11971 {
11972         struct mlx5_flow_dv_workspace *dv;
11973         struct mlx5_flow_handle *dh;
11974         struct mlx5_flow_handle_dv *dv_h;
11975         struct mlx5_flow *dev_flow;
11976         struct mlx5_priv *priv = dev->data->dev_private;
11977         uint32_t handle_idx;
11978         int n;
11979         int err;
11980         int idx;
11981         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
11982         struct mlx5_flow_rss_desc *rss_desc = &wks->rss_desc;
11983
11984         MLX5_ASSERT(wks);
11985         for (idx = wks->flow_idx - 1; idx >= 0; idx--) {
11986                 dev_flow = &wks->flows[idx];
11987                 dv = &dev_flow->dv;
11988                 dh = dev_flow->handle;
11989                 dv_h = &dh->dvh;
11990                 n = dv->actions_n;
11991                 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
11992                         if (dv->transfer) {
11993                                 dv->actions[n++] = priv->sh->esw_drop_action;
11994                         } else {
11995                                 MLX5_ASSERT(priv->drop_queue.hrxq);
11996                                 dv->actions[n++] =
11997                                                 priv->drop_queue.hrxq->action;
11998                         }
11999                 } else if ((dh->fate_action == MLX5_FLOW_FATE_QUEUE &&
12000                            !dv_h->rix_sample && !dv_h->rix_dest_array)) {
12001                         struct mlx5_hrxq *hrxq;
12002                         uint32_t hrxq_idx;
12003
12004                         hrxq = flow_dv_hrxq_prepare(dev, dev_flow, rss_desc,
12005                                                     &hrxq_idx);
12006                         if (!hrxq) {
12007                                 rte_flow_error_set
12008                                         (error, rte_errno,
12009                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12010                                          "cannot get hash queue");
12011                                 goto error;
12012                         }
12013                         dh->rix_hrxq = hrxq_idx;
12014                         dv->actions[n++] = hrxq->action;
12015                 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
12016                         struct mlx5_hrxq *hrxq = NULL;
12017                         uint32_t hrxq_idx;
12018
12019                         hrxq_idx = __flow_dv_action_rss_hrxq_lookup(dev,
12020                                                 rss_desc->shared_rss,
12021                                                 dev_flow->hash_fields,
12022                                                 !!(dh->layers &
12023                                                 MLX5_FLOW_LAYER_TUNNEL));
12024                         if (hrxq_idx)
12025                                 hrxq = mlx5_ipool_get
12026                                         (priv->sh->ipool[MLX5_IPOOL_HRXQ],
12027                                          hrxq_idx);
12028                         if (!hrxq) {
12029                                 rte_flow_error_set
12030                                         (error, rte_errno,
12031                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12032                                          "cannot get hash queue");
12033                                 goto error;
12034                         }
12035                         dh->rix_srss = rss_desc->shared_rss;
12036                         dv->actions[n++] = hrxq->action;
12037                 } else if (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS) {
12038                         if (!priv->sh->default_miss_action) {
12039                                 rte_flow_error_set
12040                                         (error, rte_errno,
12041                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12042                                          "default miss action not be created.");
12043                                 goto error;
12044                         }
12045                         dv->actions[n++] = priv->sh->default_miss_action;
12046                 }
12047                 err = mlx5_flow_os_create_flow(dv_h->matcher->matcher_object,
12048                                                (void *)&dv->value, n,
12049                                                dv->actions, &dh->drv_flow);
12050                 if (err) {
12051                         rte_flow_error_set(error, errno,
12052                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12053                                            NULL,
12054                                            "hardware refuses to create flow");
12055                         goto error;
12056                 }
12057                 if (priv->vmwa_context &&
12058                     dh->vf_vlan.tag && !dh->vf_vlan.created) {
12059                         /*
12060                          * The rule contains the VLAN pattern.
12061                          * For VF we are going to create VLAN
12062                          * interface to make hypervisor set correct
12063                          * e-Switch vport context.
12064                          */
12065                         mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
12066                 }
12067         }
12068         return 0;
12069 error:
12070         err = rte_errno; /* Save rte_errno before cleanup. */
12071         SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles,
12072                        handle_idx, dh, next) {
12073                 /* hrxq is union, don't clear it if the flag is not set. */
12074                 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE && dh->rix_hrxq) {
12075                         mlx5_hrxq_release(dev, dh->rix_hrxq);
12076                         dh->rix_hrxq = 0;
12077                 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
12078                         dh->rix_srss = 0;
12079                 }
12080                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
12081                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
12082         }
12083         rte_errno = err; /* Restore rte_errno. */
12084         return -rte_errno;
12085 }
12086
12087 void
12088 flow_dv_matcher_remove_cb(struct mlx5_cache_list *list __rte_unused,
12089                           struct mlx5_cache_entry *entry)
12090 {
12091         struct mlx5_flow_dv_matcher *cache = container_of(entry, typeof(*cache),
12092                                                           entry);
12093
12094         claim_zero(mlx5_flow_os_destroy_flow_matcher(cache->matcher_object));
12095         mlx5_free(cache);
12096 }
12097
12098 /**
12099  * Release the flow matcher.
12100  *
12101  * @param dev
12102  *   Pointer to Ethernet device.
12103  * @param port_id
12104  *   Index to port ID action resource.
12105  *
12106  * @return
12107  *   1 while a reference on it exists, 0 when freed.
12108  */
12109 static int
12110 flow_dv_matcher_release(struct rte_eth_dev *dev,
12111                         struct mlx5_flow_handle *handle)
12112 {
12113         struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
12114         struct mlx5_flow_tbl_data_entry *tbl = container_of(matcher->tbl,
12115                                                             typeof(*tbl), tbl);
12116         int ret;
12117
12118         MLX5_ASSERT(matcher->matcher_object);
12119         ret = mlx5_cache_unregister(&tbl->matchers, &matcher->entry);
12120         flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl->tbl);
12121         return ret;
12122 }
12123
12124 /**
12125  * Release encap_decap resource.
12126  *
12127  * @param list
12128  *   Pointer to the hash list.
12129  * @param entry
12130  *   Pointer to exist resource entry object.
12131  */
12132 void
12133 flow_dv_encap_decap_remove_cb(struct mlx5_hlist *list,
12134                               struct mlx5_hlist_entry *entry)
12135 {
12136         struct mlx5_dev_ctx_shared *sh = list->ctx;
12137         struct mlx5_flow_dv_encap_decap_resource *res =
12138                 container_of(entry, typeof(*res), entry);
12139
12140         claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
12141         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], res->idx);
12142 }
12143
12144 /**
12145  * Release an encap/decap resource.
12146  *
12147  * @param dev
12148  *   Pointer to Ethernet device.
12149  * @param encap_decap_idx
12150  *   Index of encap decap resource.
12151  *
12152  * @return
12153  *   1 while a reference on it exists, 0 when freed.
12154  */
12155 static int
12156 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
12157                                      uint32_t encap_decap_idx)
12158 {
12159         struct mlx5_priv *priv = dev->data->dev_private;
12160         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
12161
12162         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
12163                                         encap_decap_idx);
12164         if (!cache_resource)
12165                 return 0;
12166         MLX5_ASSERT(cache_resource->action);
12167         return mlx5_hlist_unregister(priv->sh->encaps_decaps,
12168                                      &cache_resource->entry);
12169 }
12170
12171 /**
12172  * Release an jump to table action resource.
12173  *
12174  * @param dev
12175  *   Pointer to Ethernet device.
12176  * @param rix_jump
12177  *   Index to the jump action resource.
12178  *
12179  * @return
12180  *   1 while a reference on it exists, 0 when freed.
12181  */
12182 static int
12183 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
12184                                   uint32_t rix_jump)
12185 {
12186         struct mlx5_priv *priv = dev->data->dev_private;
12187         struct mlx5_flow_tbl_data_entry *tbl_data;
12188
12189         tbl_data = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_JUMP],
12190                                   rix_jump);
12191         if (!tbl_data)
12192                 return 0;
12193         return flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl_data->tbl);
12194 }
12195
12196 void
12197 flow_dv_modify_remove_cb(struct mlx5_hlist *list __rte_unused,
12198                          struct mlx5_hlist_entry *entry)
12199 {
12200         struct mlx5_flow_dv_modify_hdr_resource *res =
12201                 container_of(entry, typeof(*res), entry);
12202
12203         claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
12204         mlx5_free(entry);
12205 }
12206
12207 /**
12208  * Release a modify-header resource.
12209  *
12210  * @param dev
12211  *   Pointer to Ethernet device.
12212  * @param handle
12213  *   Pointer to mlx5_flow_handle.
12214  *
12215  * @return
12216  *   1 while a reference on it exists, 0 when freed.
12217  */
12218 static int
12219 flow_dv_modify_hdr_resource_release(struct rte_eth_dev *dev,
12220                                     struct mlx5_flow_handle *handle)
12221 {
12222         struct mlx5_priv *priv = dev->data->dev_private;
12223         struct mlx5_flow_dv_modify_hdr_resource *entry = handle->dvh.modify_hdr;
12224
12225         MLX5_ASSERT(entry->action);
12226         return mlx5_hlist_unregister(priv->sh->modify_cmds, &entry->entry);
12227 }
12228
12229 void
12230 flow_dv_port_id_remove_cb(struct mlx5_cache_list *list,
12231                           struct mlx5_cache_entry *entry)
12232 {
12233         struct mlx5_dev_ctx_shared *sh = list->ctx;
12234         struct mlx5_flow_dv_port_id_action_resource *cache =
12235                         container_of(entry, typeof(*cache), entry);
12236
12237         claim_zero(mlx5_flow_os_destroy_flow_action(cache->action));
12238         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], cache->idx);
12239 }
12240
12241 /**
12242  * Release port ID action resource.
12243  *
12244  * @param dev
12245  *   Pointer to Ethernet device.
12246  * @param handle
12247  *   Pointer to mlx5_flow_handle.
12248  *
12249  * @return
12250  *   1 while a reference on it exists, 0 when freed.
12251  */
12252 static int
12253 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
12254                                         uint32_t port_id)
12255 {
12256         struct mlx5_priv *priv = dev->data->dev_private;
12257         struct mlx5_flow_dv_port_id_action_resource *cache;
12258
12259         cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID], port_id);
12260         if (!cache)
12261                 return 0;
12262         MLX5_ASSERT(cache->action);
12263         return mlx5_cache_unregister(&priv->sh->port_id_action_list,
12264                                      &cache->entry);
12265 }
12266
12267 /**
12268  * Release shared RSS action resource.
12269  *
12270  * @param dev
12271  *   Pointer to Ethernet device.
12272  * @param srss
12273  *   Shared RSS action index.
12274  */
12275 static void
12276 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss)
12277 {
12278         struct mlx5_priv *priv = dev->data->dev_private;
12279         struct mlx5_shared_action_rss *shared_rss;
12280
12281         shared_rss = mlx5_ipool_get
12282                         (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], srss);
12283         __atomic_sub_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
12284 }
12285
12286 void
12287 flow_dv_push_vlan_remove_cb(struct mlx5_cache_list *list,
12288                             struct mlx5_cache_entry *entry)
12289 {
12290         struct mlx5_dev_ctx_shared *sh = list->ctx;
12291         struct mlx5_flow_dv_push_vlan_action_resource *cache =
12292                         container_of(entry, typeof(*cache), entry);
12293
12294         claim_zero(mlx5_flow_os_destroy_flow_action(cache->action));
12295         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], cache->idx);
12296 }
12297
12298 /**
12299  * Release push vlan action resource.
12300  *
12301  * @param dev
12302  *   Pointer to Ethernet device.
12303  * @param handle
12304  *   Pointer to mlx5_flow_handle.
12305  *
12306  * @return
12307  *   1 while a reference on it exists, 0 when freed.
12308  */
12309 static int
12310 flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,
12311                                           struct mlx5_flow_handle *handle)
12312 {
12313         struct mlx5_priv *priv = dev->data->dev_private;
12314         struct mlx5_flow_dv_push_vlan_action_resource *cache;
12315         uint32_t idx = handle->dvh.rix_push_vlan;
12316
12317         cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
12318         if (!cache)
12319                 return 0;
12320         MLX5_ASSERT(cache->action);
12321         return mlx5_cache_unregister(&priv->sh->push_vlan_action_list,
12322                                      &cache->entry);
12323 }
12324
12325 /**
12326  * Release the fate resource.
12327  *
12328  * @param dev
12329  *   Pointer to Ethernet device.
12330  * @param handle
12331  *   Pointer to mlx5_flow_handle.
12332  */
12333 static void
12334 flow_dv_fate_resource_release(struct rte_eth_dev *dev,
12335                                struct mlx5_flow_handle *handle)
12336 {
12337         if (!handle->rix_fate)
12338                 return;
12339         switch (handle->fate_action) {
12340         case MLX5_FLOW_FATE_QUEUE:
12341                 mlx5_hrxq_release(dev, handle->rix_hrxq);
12342                 break;
12343         case MLX5_FLOW_FATE_JUMP:
12344                 flow_dv_jump_tbl_resource_release(dev, handle->rix_jump);
12345                 break;
12346         case MLX5_FLOW_FATE_PORT_ID:
12347                 flow_dv_port_id_action_resource_release(dev,
12348                                 handle->rix_port_id_action);
12349                 break;
12350         default:
12351                 DRV_LOG(DEBUG, "Incorrect fate action:%d", handle->fate_action);
12352                 break;
12353         }
12354         handle->rix_fate = 0;
12355 }
12356
12357 void
12358 flow_dv_sample_remove_cb(struct mlx5_cache_list *list __rte_unused,
12359                          struct mlx5_cache_entry *entry)
12360 {
12361         struct mlx5_flow_dv_sample_resource *cache_resource =
12362                         container_of(entry, typeof(*cache_resource), entry);
12363         struct rte_eth_dev *dev = cache_resource->dev;
12364         struct mlx5_priv *priv = dev->data->dev_private;
12365
12366         if (cache_resource->verbs_action)
12367                 claim_zero(mlx5_flow_os_destroy_flow_action
12368                                 (cache_resource->verbs_action));
12369         if (cache_resource->normal_path_tbl)
12370                 flow_dv_tbl_resource_release(MLX5_SH(dev),
12371                         cache_resource->normal_path_tbl);
12372         flow_dv_sample_sub_actions_release(dev,
12373                                 &cache_resource->sample_idx);
12374         mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
12375                         cache_resource->idx);
12376         DRV_LOG(DEBUG, "sample resource %p: removed",
12377                 (void *)cache_resource);
12378 }
12379
12380 /**
12381  * Release an sample resource.
12382  *
12383  * @param dev
12384  *   Pointer to Ethernet device.
12385  * @param handle
12386  *   Pointer to mlx5_flow_handle.
12387  *
12388  * @return
12389  *   1 while a reference on it exists, 0 when freed.
12390  */
12391 static int
12392 flow_dv_sample_resource_release(struct rte_eth_dev *dev,
12393                                      struct mlx5_flow_handle *handle)
12394 {
12395         struct mlx5_priv *priv = dev->data->dev_private;
12396         struct mlx5_flow_dv_sample_resource *cache_resource;
12397
12398         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
12399                          handle->dvh.rix_sample);
12400         if (!cache_resource)
12401                 return 0;
12402         MLX5_ASSERT(cache_resource->verbs_action);
12403         return mlx5_cache_unregister(&priv->sh->sample_action_list,
12404                                      &cache_resource->entry);
12405 }
12406
12407 void
12408 flow_dv_dest_array_remove_cb(struct mlx5_cache_list *list __rte_unused,
12409                              struct mlx5_cache_entry *entry)
12410 {
12411         struct mlx5_flow_dv_dest_array_resource *cache_resource =
12412                         container_of(entry, typeof(*cache_resource), entry);
12413         struct rte_eth_dev *dev = cache_resource->dev;
12414         struct mlx5_priv *priv = dev->data->dev_private;
12415         uint32_t i = 0;
12416
12417         MLX5_ASSERT(cache_resource->action);
12418         if (cache_resource->action)
12419                 claim_zero(mlx5_flow_os_destroy_flow_action
12420                                         (cache_resource->action));
12421         for (; i < cache_resource->num_of_dest; i++)
12422                 flow_dv_sample_sub_actions_release(dev,
12423                                 &cache_resource->sample_idx[i]);
12424         mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
12425                         cache_resource->idx);
12426         DRV_LOG(DEBUG, "destination array resource %p: removed",
12427                 (void *)cache_resource);
12428 }
12429
12430 /**
12431  * Release an destination array resource.
12432  *
12433  * @param dev
12434  *   Pointer to Ethernet device.
12435  * @param handle
12436  *   Pointer to mlx5_flow_handle.
12437  *
12438  * @return
12439  *   1 while a reference on it exists, 0 when freed.
12440  */
12441 static int
12442 flow_dv_dest_array_resource_release(struct rte_eth_dev *dev,
12443                                     struct mlx5_flow_handle *handle)
12444 {
12445         struct mlx5_priv *priv = dev->data->dev_private;
12446         struct mlx5_flow_dv_dest_array_resource *cache;
12447
12448         cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
12449                                handle->dvh.rix_dest_array);
12450         if (!cache)
12451                 return 0;
12452         MLX5_ASSERT(cache->action);
12453         return mlx5_cache_unregister(&priv->sh->dest_array_list,
12454                                      &cache->entry);
12455 }
12456
12457 static void
12458 flow_dv_geneve_tlv_option_resource_release(struct rte_eth_dev *dev)
12459 {
12460         struct mlx5_priv *priv = dev->data->dev_private;
12461         struct mlx5_dev_ctx_shared *sh = priv->sh;
12462         struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
12463                                 sh->geneve_tlv_option_resource;
12464         rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
12465         if (geneve_opt_resource) {
12466                 if (!(__atomic_sub_fetch(&geneve_opt_resource->refcnt, 1,
12467                                          __ATOMIC_RELAXED))) {
12468                         claim_zero(mlx5_devx_cmd_destroy
12469                                         (geneve_opt_resource->obj));
12470                         mlx5_free(sh->geneve_tlv_option_resource);
12471                         sh->geneve_tlv_option_resource = NULL;
12472                 }
12473         }
12474         rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
12475 }
12476
12477 /**
12478  * Remove the flow from the NIC but keeps it in memory.
12479  * Lock free, (mutex should be acquired by caller).
12480  *
12481  * @param[in] dev
12482  *   Pointer to Ethernet device.
12483  * @param[in, out] flow
12484  *   Pointer to flow structure.
12485  */
12486 static void
12487 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
12488 {
12489         struct mlx5_flow_handle *dh;
12490         uint32_t handle_idx;
12491         struct mlx5_priv *priv = dev->data->dev_private;
12492
12493         if (!flow)
12494                 return;
12495         handle_idx = flow->dev_handles;
12496         while (handle_idx) {
12497                 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
12498                                     handle_idx);
12499                 if (!dh)
12500                         return;
12501                 if (dh->drv_flow) {
12502                         claim_zero(mlx5_flow_os_destroy_flow(dh->drv_flow));
12503                         dh->drv_flow = NULL;
12504                 }
12505                 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE)
12506                         flow_dv_fate_resource_release(dev, dh);
12507                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
12508                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
12509                 handle_idx = dh->next.next;
12510         }
12511 }
12512
12513 /**
12514  * Remove the flow from the NIC and the memory.
12515  * Lock free, (mutex should be acquired by caller).
12516  *
12517  * @param[in] dev
12518  *   Pointer to the Ethernet device structure.
12519  * @param[in, out] flow
12520  *   Pointer to flow structure.
12521  */
12522 static void
12523 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
12524 {
12525         struct mlx5_flow_handle *dev_handle;
12526         struct mlx5_priv *priv = dev->data->dev_private;
12527         uint32_t srss = 0;
12528
12529         if (!flow)
12530                 return;
12531         flow_dv_remove(dev, flow);
12532         if (flow->counter) {
12533                 flow_dv_counter_free(dev, flow->counter);
12534                 flow->counter = 0;
12535         }
12536         if (flow->meter) {
12537                 struct mlx5_flow_meter *fm;
12538
12539                 fm = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MTR],
12540                                     flow->meter);
12541                 if (fm)
12542                         mlx5_flow_meter_detach(fm);
12543                 flow->meter = 0;
12544         }
12545         if (flow->age)
12546                 flow_dv_aso_age_release(dev, flow->age);
12547         if (flow->geneve_tlv_option) {
12548                 flow_dv_geneve_tlv_option_resource_release(dev);
12549                 flow->geneve_tlv_option = 0;
12550         }
12551         while (flow->dev_handles) {
12552                 uint32_t tmp_idx = flow->dev_handles;
12553
12554                 dev_handle = mlx5_ipool_get(priv->sh->ipool
12555                                             [MLX5_IPOOL_MLX5_FLOW], tmp_idx);
12556                 if (!dev_handle)
12557                         return;
12558                 flow->dev_handles = dev_handle->next.next;
12559                 if (dev_handle->dvh.matcher)
12560                         flow_dv_matcher_release(dev, dev_handle);
12561                 if (dev_handle->dvh.rix_sample)
12562                         flow_dv_sample_resource_release(dev, dev_handle);
12563                 if (dev_handle->dvh.rix_dest_array)
12564                         flow_dv_dest_array_resource_release(dev, dev_handle);
12565                 if (dev_handle->dvh.rix_encap_decap)
12566                         flow_dv_encap_decap_resource_release(dev,
12567                                 dev_handle->dvh.rix_encap_decap);
12568                 if (dev_handle->dvh.modify_hdr)
12569                         flow_dv_modify_hdr_resource_release(dev, dev_handle);
12570                 if (dev_handle->dvh.rix_push_vlan)
12571                         flow_dv_push_vlan_action_resource_release(dev,
12572                                                                   dev_handle);
12573                 if (dev_handle->dvh.rix_tag)
12574                         flow_dv_tag_release(dev,
12575                                             dev_handle->dvh.rix_tag);
12576                 if (dev_handle->fate_action != MLX5_FLOW_FATE_SHARED_RSS)
12577                         flow_dv_fate_resource_release(dev, dev_handle);
12578                 else if (!srss)
12579                         srss = dev_handle->rix_srss;
12580                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
12581                            tmp_idx);
12582         }
12583         if (srss)
12584                 flow_dv_shared_rss_action_release(dev, srss);
12585 }
12586
12587 /**
12588  * Release array of hash RX queue objects.
12589  * Helper function.
12590  *
12591  * @param[in] dev
12592  *   Pointer to the Ethernet device structure.
12593  * @param[in, out] hrxqs
12594  *   Array of hash RX queue objects.
12595  *
12596  * @return
12597  *   Total number of references to hash RX queue objects in *hrxqs* array
12598  *   after this operation.
12599  */
12600 static int
12601 __flow_dv_hrxqs_release(struct rte_eth_dev *dev,
12602                         uint32_t (*hrxqs)[MLX5_RSS_HASH_FIELDS_LEN])
12603 {
12604         size_t i;
12605         int remaining = 0;
12606
12607         for (i = 0; i < RTE_DIM(*hrxqs); i++) {
12608                 int ret = mlx5_hrxq_release(dev, (*hrxqs)[i]);
12609
12610                 if (!ret)
12611                         (*hrxqs)[i] = 0;
12612                 remaining += ret;
12613         }
12614         return remaining;
12615 }
12616
12617 /**
12618  * Release all hash RX queue objects representing shared RSS action.
12619  *
12620  * @param[in] dev
12621  *   Pointer to the Ethernet device structure.
12622  * @param[in, out] action
12623  *   Shared RSS action to remove hash RX queue objects from.
12624  *
12625  * @return
12626  *   Total number of references to hash RX queue objects stored in *action*
12627  *   after this operation.
12628  *   Expected to be 0 if no external references held.
12629  */
12630 static int
12631 __flow_dv_action_rss_hrxqs_release(struct rte_eth_dev *dev,
12632                                  struct mlx5_shared_action_rss *shared_rss)
12633 {
12634         return __flow_dv_hrxqs_release(dev, &shared_rss->hrxq) +
12635                 __flow_dv_hrxqs_release(dev, &shared_rss->hrxq_tunnel);
12636 }
12637
12638 /**
12639  * Setup shared RSS action.
12640  * Prepare set of hash RX queue objects sufficient to handle all valid
12641  * hash_fields combinations (see enum ibv_rx_hash_fields).
12642  *
12643  * @param[in] dev
12644  *   Pointer to the Ethernet device structure.
12645  * @param[in] action_idx
12646  *   Shared RSS action ipool index.
12647  * @param[in, out] action
12648  *   Partially initialized shared RSS action.
12649  * @param[out] error
12650  *   Perform verbose error reporting if not NULL. Initialized in case of
12651  *   error only.
12652  *
12653  * @return
12654  *   0 on success, otherwise negative errno value.
12655  */
12656 static int
12657 __flow_dv_action_rss_setup(struct rte_eth_dev *dev,
12658                            uint32_t action_idx,
12659                            struct mlx5_shared_action_rss *shared_rss,
12660                            struct rte_flow_error *error)
12661 {
12662         struct mlx5_flow_rss_desc rss_desc = { 0 };
12663         size_t i;
12664         int err;
12665
12666         if (mlx5_ind_table_obj_setup(dev, shared_rss->ind_tbl)) {
12667                 return rte_flow_error_set(error, rte_errno,
12668                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12669                                           "cannot setup indirection table");
12670         }
12671         memcpy(rss_desc.key, shared_rss->origin.key, MLX5_RSS_HASH_KEY_LEN);
12672         rss_desc.key_len = MLX5_RSS_HASH_KEY_LEN;
12673         rss_desc.const_q = shared_rss->origin.queue;
12674         rss_desc.queue_num = shared_rss->origin.queue_num;
12675         /* Set non-zero value to indicate a shared RSS. */
12676         rss_desc.shared_rss = action_idx;
12677         rss_desc.ind_tbl = shared_rss->ind_tbl;
12678         for (i = 0; i < MLX5_RSS_HASH_FIELDS_LEN; i++) {
12679                 uint32_t hrxq_idx;
12680                 uint64_t hash_fields = mlx5_rss_hash_fields[i];
12681                 int tunnel;
12682
12683                 for (tunnel = 0; tunnel < 2; tunnel++) {
12684                         rss_desc.tunnel = tunnel;
12685                         rss_desc.hash_fields = hash_fields;
12686                         hrxq_idx = mlx5_hrxq_get(dev, &rss_desc);
12687                         if (!hrxq_idx) {
12688                                 rte_flow_error_set
12689                                         (error, rte_errno,
12690                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12691                                          "cannot get hash queue");
12692                                 goto error_hrxq_new;
12693                         }
12694                         err = __flow_dv_action_rss_hrxq_set
12695                                 (shared_rss, hash_fields, tunnel, hrxq_idx);
12696                         MLX5_ASSERT(!err);
12697                 }
12698         }
12699         return 0;
12700 error_hrxq_new:
12701         err = rte_errno;
12702         __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
12703         if (!mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl, true))
12704                 shared_rss->ind_tbl = NULL;
12705         rte_errno = err;
12706         return -rte_errno;
12707 }
12708
12709 /**
12710  * Create shared RSS action.
12711  *
12712  * @param[in] dev
12713  *   Pointer to the Ethernet device structure.
12714  * @param[in] conf
12715  *   Shared action configuration.
12716  * @param[in] rss
12717  *   RSS action specification used to create shared action.
12718  * @param[out] error
12719  *   Perform verbose error reporting if not NULL. Initialized in case of
12720  *   error only.
12721  *
12722  * @return
12723  *   A valid shared action ID in case of success, 0 otherwise and
12724  *   rte_errno is set.
12725  */
12726 static uint32_t
12727 __flow_dv_action_rss_create(struct rte_eth_dev *dev,
12728                             const struct rte_flow_shared_action_conf *conf,
12729                             const struct rte_flow_action_rss *rss,
12730                             struct rte_flow_error *error)
12731 {
12732         struct mlx5_priv *priv = dev->data->dev_private;
12733         struct mlx5_shared_action_rss *shared_rss = NULL;
12734         void *queue = NULL;
12735         struct rte_flow_action_rss *origin;
12736         const uint8_t *rss_key;
12737         uint32_t queue_size = rss->queue_num * sizeof(uint16_t);
12738         uint32_t idx;
12739
12740         RTE_SET_USED(conf);
12741         queue = mlx5_malloc(0, RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
12742                             0, SOCKET_ID_ANY);
12743         shared_rss = mlx5_ipool_zmalloc
12744                          (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], &idx);
12745         if (!shared_rss || !queue) {
12746                 rte_flow_error_set(error, ENOMEM,
12747                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12748                                    "cannot allocate resource memory");
12749                 goto error_rss_init;
12750         }
12751         if (idx > (1u << MLX5_SHARED_ACTION_TYPE_OFFSET)) {
12752                 rte_flow_error_set(error, E2BIG,
12753                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12754                                    "rss action number out of range");
12755                 goto error_rss_init;
12756         }
12757         shared_rss->ind_tbl = mlx5_malloc(MLX5_MEM_ZERO,
12758                                           sizeof(*shared_rss->ind_tbl),
12759                                           0, SOCKET_ID_ANY);
12760         if (!shared_rss->ind_tbl) {
12761                 rte_flow_error_set(error, ENOMEM,
12762                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12763                                    "cannot allocate resource memory");
12764                 goto error_rss_init;
12765         }
12766         memcpy(queue, rss->queue, queue_size);
12767         shared_rss->ind_tbl->queues = queue;
12768         shared_rss->ind_tbl->queues_n = rss->queue_num;
12769         origin = &shared_rss->origin;
12770         origin->func = rss->func;
12771         origin->level = rss->level;
12772         /* RSS type 0 indicates default RSS type (ETH_RSS_IP). */
12773         origin->types = !rss->types ? ETH_RSS_IP : rss->types;
12774         /* NULL RSS key indicates default RSS key. */
12775         rss_key = !rss->key ? rss_hash_default_key : rss->key;
12776         memcpy(shared_rss->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
12777         origin->key = &shared_rss->key[0];
12778         origin->key_len = MLX5_RSS_HASH_KEY_LEN;
12779         origin->queue = queue;
12780         origin->queue_num = rss->queue_num;
12781         if (__flow_dv_action_rss_setup(dev, idx, shared_rss, error))
12782                 goto error_rss_init;
12783         rte_spinlock_init(&shared_rss->action_rss_sl);
12784         __atomic_add_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
12785         rte_spinlock_lock(&priv->shared_act_sl);
12786         ILIST_INSERT(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
12787                      &priv->rss_shared_actions, idx, shared_rss, next);
12788         rte_spinlock_unlock(&priv->shared_act_sl);
12789         return idx;
12790 error_rss_init:
12791         if (shared_rss) {
12792                 if (shared_rss->ind_tbl)
12793                         mlx5_free(shared_rss->ind_tbl);
12794                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
12795                                 idx);
12796         }
12797         if (queue)
12798                 mlx5_free(queue);
12799         return 0;
12800 }
12801
12802 /**
12803  * Destroy the shared RSS action.
12804  * Release related hash RX queue objects.
12805  *
12806  * @param[in] dev
12807  *   Pointer to the Ethernet device structure.
12808  * @param[in] idx
12809  *   The shared RSS action object ID to be removed.
12810  * @param[out] error
12811  *   Perform verbose error reporting if not NULL. Initialized in case of
12812  *   error only.
12813  *
12814  * @return
12815  *   0 on success, otherwise negative errno value.
12816  */
12817 static int
12818 __flow_dv_action_rss_release(struct rte_eth_dev *dev, uint32_t idx,
12819                              struct rte_flow_error *error)
12820 {
12821         struct mlx5_priv *priv = dev->data->dev_private;
12822         struct mlx5_shared_action_rss *shared_rss =
12823             mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
12824         uint32_t old_refcnt = 1;
12825         int remaining;
12826         uint16_t *queue = NULL;
12827
12828         if (!shared_rss)
12829                 return rte_flow_error_set(error, EINVAL,
12830                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12831                                           "invalid shared action");
12832         remaining = __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
12833         if (remaining)
12834                 return rte_flow_error_set(error, EBUSY,
12835                                           RTE_FLOW_ERROR_TYPE_ACTION,
12836                                           NULL,
12837                                           "shared rss hrxq has references");
12838         if (!__atomic_compare_exchange_n(&shared_rss->refcnt, &old_refcnt,
12839                                          0, 0, __ATOMIC_ACQUIRE,
12840                                          __ATOMIC_RELAXED))
12841                 return rte_flow_error_set(error, EBUSY,
12842                                           RTE_FLOW_ERROR_TYPE_ACTION,
12843                                           NULL,
12844                                           "shared rss has references");
12845         queue = shared_rss->ind_tbl->queues;
12846         remaining = mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl, true);
12847         if (remaining)
12848                 return rte_flow_error_set(error, EBUSY,
12849                                           RTE_FLOW_ERROR_TYPE_ACTION,
12850                                           NULL,
12851                                           "shared rss indirection table has"
12852                                           " references");
12853         mlx5_free(queue);
12854         rte_spinlock_lock(&priv->shared_act_sl);
12855         ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
12856                      &priv->rss_shared_actions, idx, shared_rss, next);
12857         rte_spinlock_unlock(&priv->shared_act_sl);
12858         mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
12859                         idx);
12860         return 0;
12861 }
12862
12863 /**
12864  * Create shared action, lock free,
12865  * (mutex should be acquired by caller).
12866  * Dispatcher for action type specific call.
12867  *
12868  * @param[in] dev
12869  *   Pointer to the Ethernet device structure.
12870  * @param[in] conf
12871  *   Shared action configuration.
12872  * @param[in] action
12873  *   Action specification used to create shared action.
12874  * @param[out] error
12875  *   Perform verbose error reporting if not NULL. Initialized in case of
12876  *   error only.
12877  *
12878  * @return
12879  *   A valid shared action handle in case of success, NULL otherwise and
12880  *   rte_errno is set.
12881  */
12882 static struct rte_flow_shared_action *
12883 flow_dv_action_create(struct rte_eth_dev *dev,
12884                       const struct rte_flow_shared_action_conf *conf,
12885                       const struct rte_flow_action *action,
12886                       struct rte_flow_error *err)
12887 {
12888         uint32_t idx = 0;
12889         uint32_t ret = 0;
12890
12891         switch (action->type) {
12892         case RTE_FLOW_ACTION_TYPE_RSS:
12893                 ret = __flow_dv_action_rss_create(dev, conf, action->conf, err);
12894                 idx = (MLX5_SHARED_ACTION_TYPE_RSS <<
12895                        MLX5_SHARED_ACTION_TYPE_OFFSET) | ret;
12896                 break;
12897         case RTE_FLOW_ACTION_TYPE_AGE:
12898                 ret = flow_dv_translate_create_aso_age(dev, action->conf, err);
12899                 idx = (MLX5_SHARED_ACTION_TYPE_AGE <<
12900                        MLX5_SHARED_ACTION_TYPE_OFFSET) | ret;
12901                 if (ret) {
12902                         struct mlx5_aso_age_action *aso_age =
12903                                               flow_aso_age_get_by_idx(dev, ret);
12904
12905                         if (!aso_age->age_params.context)
12906                                 aso_age->age_params.context =
12907                                                          (void *)(uintptr_t)idx;
12908                 }
12909                 break;
12910         default:
12911                 rte_flow_error_set(err, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION,
12912                                    NULL, "action type not supported");
12913                 break;
12914         }
12915         return ret ? (struct rte_flow_shared_action *)(uintptr_t)idx : NULL;
12916 }
12917
12918 /**
12919  * Destroy the shared action.
12920  * Release action related resources on the NIC and the memory.
12921  * Lock free, (mutex should be acquired by caller).
12922  * Dispatcher for action type specific call.
12923  *
12924  * @param[in] dev
12925  *   Pointer to the Ethernet device structure.
12926  * @param[in] action
12927  *   The shared action object to be removed.
12928  * @param[out] error
12929  *   Perform verbose error reporting if not NULL. Initialized in case of
12930  *   error only.
12931  *
12932  * @return
12933  *   0 on success, otherwise negative errno value.
12934  */
12935 static int
12936 flow_dv_action_destroy(struct rte_eth_dev *dev,
12937                        struct rte_flow_shared_action *action,
12938                        struct rte_flow_error *error)
12939 {
12940         uint32_t act_idx = (uint32_t)(uintptr_t)action;
12941         uint32_t type = act_idx >> MLX5_SHARED_ACTION_TYPE_OFFSET;
12942         uint32_t idx = act_idx & ((1u << MLX5_SHARED_ACTION_TYPE_OFFSET) - 1);
12943         int ret;
12944
12945         switch (type) {
12946         case MLX5_SHARED_ACTION_TYPE_RSS:
12947                 return __flow_dv_action_rss_release(dev, idx, error);
12948         case MLX5_SHARED_ACTION_TYPE_AGE:
12949                 ret = flow_dv_aso_age_release(dev, idx);
12950                 if (ret)
12951                         /*
12952                          * In this case, the last flow has a reference will
12953                          * actually release the age action.
12954                          */
12955                         DRV_LOG(DEBUG, "Shared age action %" PRIu32 " was"
12956                                 " released with references %d.", idx, ret);
12957                 return 0;
12958         default:
12959                 return rte_flow_error_set(error, ENOTSUP,
12960                                           RTE_FLOW_ERROR_TYPE_ACTION,
12961                                           NULL,
12962                                           "action type not supported");
12963         }
12964 }
12965
12966 /**
12967  * Updates in place shared RSS action configuration.
12968  *
12969  * @param[in] dev
12970  *   Pointer to the Ethernet device structure.
12971  * @param[in] idx
12972  *   The shared RSS action object ID to be updated.
12973  * @param[in] action_conf
12974  *   RSS action specification used to modify *shared_rss*.
12975  * @param[out] error
12976  *   Perform verbose error reporting if not NULL. Initialized in case of
12977  *   error only.
12978  *
12979  * @return
12980  *   0 on success, otherwise negative errno value.
12981  * @note: currently only support update of RSS queues.
12982  */
12983 static int
12984 __flow_dv_action_rss_update(struct rte_eth_dev *dev, uint32_t idx,
12985                             const struct rte_flow_action_rss *action_conf,
12986                             struct rte_flow_error *error)
12987 {
12988         struct mlx5_priv *priv = dev->data->dev_private;
12989         struct mlx5_shared_action_rss *shared_rss =
12990             mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
12991         int ret = 0;
12992         void *queue = NULL;
12993         uint16_t *queue_old = NULL;
12994         uint32_t queue_size = action_conf->queue_num * sizeof(uint16_t);
12995
12996         if (!shared_rss)
12997                 return rte_flow_error_set(error, EINVAL,
12998                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12999                                           "invalid shared action to update");
13000         if (priv->obj_ops.ind_table_modify == NULL)
13001                 return rte_flow_error_set(error, ENOTSUP,
13002                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
13003                                           "cannot modify indirection table");
13004         queue = mlx5_malloc(MLX5_MEM_ZERO,
13005                             RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
13006                             0, SOCKET_ID_ANY);
13007         if (!queue)
13008                 return rte_flow_error_set(error, ENOMEM,
13009                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13010                                           NULL,
13011                                           "cannot allocate resource memory");
13012         memcpy(queue, action_conf->queue, queue_size);
13013         MLX5_ASSERT(shared_rss->ind_tbl);
13014         rte_spinlock_lock(&shared_rss->action_rss_sl);
13015         queue_old = shared_rss->ind_tbl->queues;
13016         ret = mlx5_ind_table_obj_modify(dev, shared_rss->ind_tbl,
13017                                         queue, action_conf->queue_num, true);
13018         if (ret) {
13019                 mlx5_free(queue);
13020                 ret = rte_flow_error_set(error, rte_errno,
13021                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
13022                                           "cannot update indirection table");
13023         } else {
13024                 mlx5_free(queue_old);
13025                 shared_rss->origin.queue = queue;
13026                 shared_rss->origin.queue_num = action_conf->queue_num;
13027         }
13028         rte_spinlock_unlock(&shared_rss->action_rss_sl);
13029         return ret;
13030 }
13031
13032 /**
13033  * Updates in place shared action configuration, lock free,
13034  * (mutex should be acquired by caller).
13035  *
13036  * @param[in] dev
13037  *   Pointer to the Ethernet device structure.
13038  * @param[in] action
13039  *   The shared action object to be updated.
13040  * @param[in] action_conf
13041  *   Action specification used to modify *action*.
13042  *   *action_conf* should be of type correlating with type of the *action*,
13043  *   otherwise considered as invalid.
13044  * @param[out] error
13045  *   Perform verbose error reporting if not NULL. Initialized in case of
13046  *   error only.
13047  *
13048  * @return
13049  *   0 on success, otherwise negative errno value.
13050  */
13051 static int
13052 flow_dv_action_update(struct rte_eth_dev *dev,
13053                         struct rte_flow_shared_action *action,
13054                         const void *action_conf,
13055                         struct rte_flow_error *err)
13056 {
13057         uint32_t act_idx = (uint32_t)(uintptr_t)action;
13058         uint32_t type = act_idx >> MLX5_SHARED_ACTION_TYPE_OFFSET;
13059         uint32_t idx = act_idx & ((1u << MLX5_SHARED_ACTION_TYPE_OFFSET) - 1);
13060
13061         switch (type) {
13062         case MLX5_SHARED_ACTION_TYPE_RSS:
13063                 return __flow_dv_action_rss_update(dev, idx, action_conf, err);
13064         default:
13065                 return rte_flow_error_set(err, ENOTSUP,
13066                                           RTE_FLOW_ERROR_TYPE_ACTION,
13067                                           NULL,
13068                                           "action type update not supported");
13069         }
13070 }
13071
13072 static int
13073 flow_dv_action_query(struct rte_eth_dev *dev,
13074                      const struct rte_flow_shared_action *action, void *data,
13075                      struct rte_flow_error *error)
13076 {
13077         struct mlx5_age_param *age_param;
13078         struct rte_flow_query_age *resp;
13079         uint32_t act_idx = (uint32_t)(uintptr_t)action;
13080         uint32_t type = act_idx >> MLX5_SHARED_ACTION_TYPE_OFFSET;
13081         uint32_t idx = act_idx & ((1u << MLX5_SHARED_ACTION_TYPE_OFFSET) - 1);
13082
13083         switch (type) {
13084         case MLX5_SHARED_ACTION_TYPE_AGE:
13085                 age_param = &flow_aso_age_get_by_idx(dev, idx)->age_params;
13086                 resp = data;
13087                 resp->aged = __atomic_load_n(&age_param->state,
13088                                               __ATOMIC_RELAXED) == AGE_TMOUT ?
13089                                                                           1 : 0;
13090                 resp->sec_since_last_hit_valid = !resp->aged;
13091                 if (resp->sec_since_last_hit_valid)
13092                         resp->sec_since_last_hit = __atomic_load_n
13093                              (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
13094                 return 0;
13095         default:
13096                 return rte_flow_error_set(error, ENOTSUP,
13097                                           RTE_FLOW_ERROR_TYPE_ACTION,
13098                                           NULL,
13099                                           "action type query not supported");
13100         }
13101 }
13102
13103 /**
13104  * Query a dv flow  rule for its statistics via devx.
13105  *
13106  * @param[in] dev
13107  *   Pointer to Ethernet device.
13108  * @param[in] flow
13109  *   Pointer to the sub flow.
13110  * @param[out] data
13111  *   data retrieved by the query.
13112  * @param[out] error
13113  *   Perform verbose error reporting if not NULL.
13114  *
13115  * @return
13116  *   0 on success, a negative errno value otherwise and rte_errno is set.
13117  */
13118 static int
13119 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
13120                     void *data, struct rte_flow_error *error)
13121 {
13122         struct mlx5_priv *priv = dev->data->dev_private;
13123         struct rte_flow_query_count *qc = data;
13124
13125         if (!priv->config.devx)
13126                 return rte_flow_error_set(error, ENOTSUP,
13127                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13128                                           NULL,
13129                                           "counters are not supported");
13130         if (flow->counter) {
13131                 uint64_t pkts, bytes;
13132                 struct mlx5_flow_counter *cnt;
13133
13134                 cnt = flow_dv_counter_get_by_idx(dev, flow->counter,
13135                                                  NULL);
13136                 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
13137                                                &bytes);
13138
13139                 if (err)
13140                         return rte_flow_error_set(error, -err,
13141                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13142                                         NULL, "cannot read counters");
13143                 qc->hits_set = 1;
13144                 qc->bytes_set = 1;
13145                 qc->hits = pkts - cnt->hits;
13146                 qc->bytes = bytes - cnt->bytes;
13147                 if (qc->reset) {
13148                         cnt->hits = pkts;
13149                         cnt->bytes = bytes;
13150                 }
13151                 return 0;
13152         }
13153         return rte_flow_error_set(error, EINVAL,
13154                                   RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13155                                   NULL,
13156                                   "counters are not available");
13157 }
13158
13159 /**
13160  * Query a flow rule AGE action for aging information.
13161  *
13162  * @param[in] dev
13163  *   Pointer to Ethernet device.
13164  * @param[in] flow
13165  *   Pointer to the sub flow.
13166  * @param[out] data
13167  *   data retrieved by the query.
13168  * @param[out] error
13169  *   Perform verbose error reporting if not NULL.
13170  *
13171  * @return
13172  *   0 on success, a negative errno value otherwise and rte_errno is set.
13173  */
13174 static int
13175 flow_dv_query_age(struct rte_eth_dev *dev, struct rte_flow *flow,
13176                   void *data, struct rte_flow_error *error)
13177 {
13178         struct rte_flow_query_age *resp = data;
13179         struct mlx5_age_param *age_param;
13180
13181         if (flow->age) {
13182                 struct mlx5_aso_age_action *act =
13183                                      flow_aso_age_get_by_idx(dev, flow->age);
13184
13185                 age_param = &act->age_params;
13186         } else if (flow->counter) {
13187                 age_param = flow_dv_counter_idx_get_age(dev, flow->counter);
13188
13189                 if (!age_param || !age_param->timeout)
13190                         return rte_flow_error_set
13191                                         (error, EINVAL,
13192                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13193                                          NULL, "cannot read age data");
13194         } else {
13195                 return rte_flow_error_set(error, EINVAL,
13196                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13197                                           NULL, "age data not available");
13198         }
13199         resp->aged = __atomic_load_n(&age_param->state, __ATOMIC_RELAXED) ==
13200                                      AGE_TMOUT ? 1 : 0;
13201         resp->sec_since_last_hit_valid = !resp->aged;
13202         if (resp->sec_since_last_hit_valid)
13203                 resp->sec_since_last_hit = __atomic_load_n
13204                              (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
13205         return 0;
13206 }
13207
13208 /**
13209  * Query a flow.
13210  *
13211  * @see rte_flow_query()
13212  * @see rte_flow_ops
13213  */
13214 static int
13215 flow_dv_query(struct rte_eth_dev *dev,
13216               struct rte_flow *flow __rte_unused,
13217               const struct rte_flow_action *actions __rte_unused,
13218               void *data __rte_unused,
13219               struct rte_flow_error *error __rte_unused)
13220 {
13221         int ret = -EINVAL;
13222
13223         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
13224                 switch (actions->type) {
13225                 case RTE_FLOW_ACTION_TYPE_VOID:
13226                         break;
13227                 case RTE_FLOW_ACTION_TYPE_COUNT:
13228                         ret = flow_dv_query_count(dev, flow, data, error);
13229                         break;
13230                 case RTE_FLOW_ACTION_TYPE_AGE:
13231                         ret = flow_dv_query_age(dev, flow, data, error);
13232                         break;
13233                 default:
13234                         return rte_flow_error_set(error, ENOTSUP,
13235                                                   RTE_FLOW_ERROR_TYPE_ACTION,
13236                                                   actions,
13237                                                   "action not supported");
13238                 }
13239         }
13240         return ret;
13241 }
13242
13243 /**
13244  * Destroy the meter table set.
13245  * Lock free, (mutex should be acquired by caller).
13246  *
13247  * @param[in] dev
13248  *   Pointer to Ethernet device.
13249  * @param[in] tbl
13250  *   Pointer to the meter table set.
13251  *
13252  * @return
13253  *   Always 0.
13254  */
13255 static int
13256 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
13257                         struct mlx5_meter_domains_infos *tbl)
13258 {
13259         struct mlx5_priv *priv = dev->data->dev_private;
13260         struct mlx5_meter_domains_infos *mtd =
13261                                 (struct mlx5_meter_domains_infos *)tbl;
13262
13263         if (!mtd || !priv->config.dv_flow_en)
13264                 return 0;
13265         if (mtd->ingress.policer_rules[RTE_MTR_DROPPED])
13266                 claim_zero(mlx5_flow_os_destroy_flow
13267                            (mtd->ingress.policer_rules[RTE_MTR_DROPPED]));
13268         if (mtd->egress.policer_rules[RTE_MTR_DROPPED])
13269                 claim_zero(mlx5_flow_os_destroy_flow
13270                            (mtd->egress.policer_rules[RTE_MTR_DROPPED]));
13271         if (mtd->transfer.policer_rules[RTE_MTR_DROPPED])
13272                 claim_zero(mlx5_flow_os_destroy_flow
13273                            (mtd->transfer.policer_rules[RTE_MTR_DROPPED]));
13274         if (mtd->egress.color_matcher)
13275                 claim_zero(mlx5_flow_os_destroy_flow_matcher
13276                            (mtd->egress.color_matcher));
13277         if (mtd->egress.any_matcher)
13278                 claim_zero(mlx5_flow_os_destroy_flow_matcher
13279                            (mtd->egress.any_matcher));
13280         if (mtd->egress.tbl)
13281                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->egress.tbl);
13282         if (mtd->egress.sfx_tbl)
13283                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->egress.sfx_tbl);
13284         if (mtd->ingress.color_matcher)
13285                 claim_zero(mlx5_flow_os_destroy_flow_matcher
13286                            (mtd->ingress.color_matcher));
13287         if (mtd->ingress.any_matcher)
13288                 claim_zero(mlx5_flow_os_destroy_flow_matcher
13289                            (mtd->ingress.any_matcher));
13290         if (mtd->ingress.tbl)
13291                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->ingress.tbl);
13292         if (mtd->ingress.sfx_tbl)
13293                 flow_dv_tbl_resource_release(MLX5_SH(dev),
13294                                              mtd->ingress.sfx_tbl);
13295         if (mtd->transfer.color_matcher)
13296                 claim_zero(mlx5_flow_os_destroy_flow_matcher
13297                            (mtd->transfer.color_matcher));
13298         if (mtd->transfer.any_matcher)
13299                 claim_zero(mlx5_flow_os_destroy_flow_matcher
13300                            (mtd->transfer.any_matcher));
13301         if (mtd->transfer.tbl)
13302                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->transfer.tbl);
13303         if (mtd->transfer.sfx_tbl)
13304                 flow_dv_tbl_resource_release(MLX5_SH(dev),
13305                                              mtd->transfer.sfx_tbl);
13306         if (mtd->drop_actn)
13307                 claim_zero(mlx5_flow_os_destroy_flow_action(mtd->drop_actn));
13308         mlx5_free(mtd);
13309         return 0;
13310 }
13311
13312 /* Number of meter flow actions, count and jump or count and drop. */
13313 #define METER_ACTIONS 2
13314
13315 /**
13316  * Create specify domain meter table and suffix table.
13317  *
13318  * @param[in] dev
13319  *   Pointer to Ethernet device.
13320  * @param[in,out] mtb
13321  *   Pointer to DV meter table set.
13322  * @param[in] egress
13323  *   Table attribute.
13324  * @param[in] transfer
13325  *   Table attribute.
13326  * @param[in] color_reg_c_idx
13327  *   Reg C index for color match.
13328  *
13329  * @return
13330  *   0 on success, -1 otherwise and rte_errno is set.
13331  */
13332 static int
13333 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
13334                            struct mlx5_meter_domains_infos *mtb,
13335                            uint8_t egress, uint8_t transfer,
13336                            uint32_t color_reg_c_idx)
13337 {
13338         struct mlx5_priv *priv = dev->data->dev_private;
13339         struct mlx5_dev_ctx_shared *sh = priv->sh;
13340         struct mlx5_flow_dv_match_params mask = {
13341                 .size = sizeof(mask.buf),
13342         };
13343         struct mlx5_flow_dv_match_params value = {
13344                 .size = sizeof(value.buf),
13345         };
13346         struct mlx5dv_flow_matcher_attr dv_attr = {
13347                 .type = IBV_FLOW_ATTR_NORMAL,
13348                 .priority = 0,
13349                 .match_criteria_enable = 0,
13350                 .match_mask = (void *)&mask,
13351         };
13352         void *actions[METER_ACTIONS];
13353         struct mlx5_meter_domain_info *dtb;
13354         struct rte_flow_error error;
13355         int i = 0;
13356         int ret;
13357
13358         if (transfer)
13359                 dtb = &mtb->transfer;
13360         else if (egress)
13361                 dtb = &mtb->egress;
13362         else
13363                 dtb = &mtb->ingress;
13364         /* Create the meter table with METER level. */
13365         dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
13366                                             egress, transfer, false, NULL, 0,
13367                                             0, &error);
13368         if (!dtb->tbl) {
13369                 DRV_LOG(ERR, "Failed to create meter policer table.");
13370                 return -1;
13371         }
13372         /* Create the meter suffix table with SUFFIX level. */
13373         dtb->sfx_tbl = flow_dv_tbl_resource_get(dev,
13374                                             MLX5_FLOW_TABLE_LEVEL_SUFFIX,
13375                                             egress, transfer, false, NULL, 0,
13376                                             0, &error);
13377         if (!dtb->sfx_tbl) {
13378                 DRV_LOG(ERR, "Failed to create meter suffix table.");
13379                 return -1;
13380         }
13381         /* Create matchers, Any and Color. */
13382         dv_attr.priority = 3;
13383         dv_attr.match_criteria_enable = 0;
13384         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, dtb->tbl->obj,
13385                                                &dtb->any_matcher);
13386         if (ret) {
13387                 DRV_LOG(ERR, "Failed to create meter"
13388                              " policer default matcher.");
13389                 goto error_exit;
13390         }
13391         dv_attr.priority = 0;
13392         dv_attr.match_criteria_enable =
13393                                 1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
13394         flow_dv_match_meta_reg(mask.buf, value.buf, color_reg_c_idx,
13395                                rte_col_2_mlx5_col(RTE_COLORS), UINT8_MAX);
13396         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, dtb->tbl->obj,
13397                                                &dtb->color_matcher);
13398         if (ret) {
13399                 DRV_LOG(ERR, "Failed to create meter policer color matcher.");
13400                 goto error_exit;
13401         }
13402         if (mtb->count_actns[RTE_MTR_DROPPED])
13403                 actions[i++] = mtb->count_actns[RTE_MTR_DROPPED];
13404         actions[i++] = mtb->drop_actn;
13405         /* Default rule: lowest priority, match any, actions: drop. */
13406         ret = mlx5_flow_os_create_flow(dtb->any_matcher, (void *)&value, i,
13407                                        actions,
13408                                        &dtb->policer_rules[RTE_MTR_DROPPED]);
13409         if (ret) {
13410                 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
13411                 goto error_exit;
13412         }
13413         return 0;
13414 error_exit:
13415         return -1;
13416 }
13417
13418 /**
13419  * Create the needed meter and suffix tables.
13420  * Lock free, (mutex should be acquired by caller).
13421  *
13422  * @param[in] dev
13423  *   Pointer to Ethernet device.
13424  * @param[in] fm
13425  *   Pointer to the flow meter.
13426  *
13427  * @return
13428  *   Pointer to table set on success, NULL otherwise and rte_errno is set.
13429  */
13430 static struct mlx5_meter_domains_infos *
13431 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev,
13432                        const struct mlx5_flow_meter *fm)
13433 {
13434         struct mlx5_priv *priv = dev->data->dev_private;
13435         struct mlx5_meter_domains_infos *mtb;
13436         int ret;
13437         int i;
13438
13439         if (!priv->mtr_en) {
13440                 rte_errno = ENOTSUP;
13441                 return NULL;
13442         }
13443         mtb = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mtb), 0, SOCKET_ID_ANY);
13444         if (!mtb) {
13445                 DRV_LOG(ERR, "Failed to allocate memory for meter.");
13446                 return NULL;
13447         }
13448         /* Create meter count actions */
13449         for (i = 0; i <= RTE_MTR_DROPPED; i++) {
13450                 struct mlx5_flow_counter *cnt;
13451                 if (!fm->policer_stats.cnt[i])
13452                         continue;
13453                 cnt = flow_dv_counter_get_by_idx(dev,
13454                       fm->policer_stats.cnt[i], NULL);
13455                 mtb->count_actns[i] = cnt->action;
13456         }
13457         /* Create drop action. */
13458         ret = mlx5_flow_os_create_flow_action_drop(&mtb->drop_actn);
13459         if (ret) {
13460                 DRV_LOG(ERR, "Failed to create drop action.");
13461                 goto error_exit;
13462         }
13463         /* Egress meter table. */
13464         ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0, priv->mtr_color_reg);
13465         if (ret) {
13466                 DRV_LOG(ERR, "Failed to prepare egress meter table.");
13467                 goto error_exit;
13468         }
13469         /* Ingress meter table. */
13470         ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0, priv->mtr_color_reg);
13471         if (ret) {
13472                 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
13473                 goto error_exit;
13474         }
13475         /* FDB meter table. */
13476         if (priv->config.dv_esw_en) {
13477                 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1,
13478                                                  priv->mtr_color_reg);
13479                 if (ret) {
13480                         DRV_LOG(ERR, "Failed to prepare fdb meter table.");
13481                         goto error_exit;
13482                 }
13483         }
13484         return mtb;
13485 error_exit:
13486         flow_dv_destroy_mtr_tbl(dev, mtb);
13487         return NULL;
13488 }
13489
13490 /**
13491  * Destroy domain policer rule.
13492  *
13493  * @param[in] dt
13494  *   Pointer to domain table.
13495  */
13496 static void
13497 flow_dv_destroy_domain_policer_rule(struct mlx5_meter_domain_info *dt)
13498 {
13499         int i;
13500
13501         for (i = 0; i < RTE_MTR_DROPPED; i++) {
13502                 if (dt->policer_rules[i]) {
13503                         claim_zero(mlx5_flow_os_destroy_flow
13504                                    (dt->policer_rules[i]));
13505                         dt->policer_rules[i] = NULL;
13506                 }
13507         }
13508         if (dt->jump_actn) {
13509                 claim_zero(mlx5_flow_os_destroy_flow_action(dt->jump_actn));
13510                 dt->jump_actn = NULL;
13511         }
13512 }
13513
13514 /**
13515  * Destroy policer rules.
13516  *
13517  * @param[in] dev
13518  *   Pointer to Ethernet device.
13519  * @param[in] fm
13520  *   Pointer to flow meter structure.
13521  * @param[in] attr
13522  *   Pointer to flow attributes.
13523  *
13524  * @return
13525  *   Always 0.
13526  */
13527 static int
13528 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev __rte_unused,
13529                               const struct mlx5_flow_meter *fm,
13530                               const struct rte_flow_attr *attr)
13531 {
13532         struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
13533
13534         if (!mtb)
13535                 return 0;
13536         if (attr->egress)
13537                 flow_dv_destroy_domain_policer_rule(&mtb->egress);
13538         if (attr->ingress)
13539                 flow_dv_destroy_domain_policer_rule(&mtb->ingress);
13540         if (attr->transfer)
13541                 flow_dv_destroy_domain_policer_rule(&mtb->transfer);
13542         return 0;
13543 }
13544
13545 /**
13546  * Create specify domain meter policer rule.
13547  *
13548  * @param[in] fm
13549  *   Pointer to flow meter structure.
13550  * @param[in] mtb
13551  *   Pointer to DV meter table set.
13552  * @param[in] mtr_reg_c
13553  *   Color match REG_C.
13554  *
13555  * @return
13556  *   0 on success, -1 otherwise.
13557  */
13558 static int
13559 flow_dv_create_policer_forward_rule(struct mlx5_flow_meter *fm,
13560                                     struct mlx5_meter_domain_info *dtb,
13561                                     uint8_t mtr_reg_c)
13562 {
13563         struct mlx5_flow_dv_match_params matcher = {
13564                 .size = sizeof(matcher.buf),
13565         };
13566         struct mlx5_flow_dv_match_params value = {
13567                 .size = sizeof(value.buf),
13568         };
13569         struct mlx5_meter_domains_infos *mtb = fm->mfts;
13570         void *actions[METER_ACTIONS];
13571         int i;
13572         int ret = 0;
13573
13574         /* Create jump action. */
13575         if (!dtb->jump_actn)
13576                 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
13577                                 (dtb->sfx_tbl->obj, &dtb->jump_actn);
13578         if (ret) {
13579                 DRV_LOG(ERR, "Failed to create policer jump action.");
13580                 goto error;
13581         }
13582         for (i = 0; i < RTE_MTR_DROPPED; i++) {
13583                 int j = 0;
13584
13585                 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_reg_c,
13586                                        rte_col_2_mlx5_col(i), UINT8_MAX);
13587                 if (mtb->count_actns[i])
13588                         actions[j++] = mtb->count_actns[i];
13589                 if (fm->action[i] == MTR_POLICER_ACTION_DROP)
13590                         actions[j++] = mtb->drop_actn;
13591                 else
13592                         actions[j++] = dtb->jump_actn;
13593                 ret = mlx5_flow_os_create_flow(dtb->color_matcher,
13594                                                (void *)&value, j, actions,
13595                                                &dtb->policer_rules[i]);
13596                 if (ret) {
13597                         DRV_LOG(ERR, "Failed to create policer rule.");
13598                         goto error;
13599                 }
13600         }
13601         return 0;
13602 error:
13603         rte_errno = errno;
13604         return -1;
13605 }
13606
13607 /**
13608  * Create policer rules.
13609  *
13610  * @param[in] dev
13611  *   Pointer to Ethernet device.
13612  * @param[in] fm
13613  *   Pointer to flow meter structure.
13614  * @param[in] attr
13615  *   Pointer to flow attributes.
13616  *
13617  * @return
13618  *   0 on success, -1 otherwise.
13619  */
13620 static int
13621 flow_dv_create_policer_rules(struct rte_eth_dev *dev,
13622                              struct mlx5_flow_meter *fm,
13623                              const struct rte_flow_attr *attr)
13624 {
13625         struct mlx5_priv *priv = dev->data->dev_private;
13626         struct mlx5_meter_domains_infos *mtb = fm->mfts;
13627         int ret;
13628
13629         if (attr->egress) {
13630                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->egress,
13631                                                 priv->mtr_color_reg);
13632                 if (ret) {
13633                         DRV_LOG(ERR, "Failed to create egress policer.");
13634                         goto error;
13635                 }
13636         }
13637         if (attr->ingress) {
13638                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->ingress,
13639                                                 priv->mtr_color_reg);
13640                 if (ret) {
13641                         DRV_LOG(ERR, "Failed to create ingress policer.");
13642                         goto error;
13643                 }
13644         }
13645         if (attr->transfer) {
13646                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->transfer,
13647                                                 priv->mtr_color_reg);
13648                 if (ret) {
13649                         DRV_LOG(ERR, "Failed to create transfer policer.");
13650                         goto error;
13651                 }
13652         }
13653         return 0;
13654 error:
13655         flow_dv_destroy_policer_rules(dev, fm, attr);
13656         return -1;
13657 }
13658
13659 /**
13660  * Validate the batch counter support in root table.
13661  *
13662  * Create a simple flow with invalid counter and drop action on root table to
13663  * validate if batch counter with offset on root table is supported or not.
13664  *
13665  * @param[in] dev
13666  *   Pointer to rte_eth_dev structure.
13667  *
13668  * @return
13669  *   0 on success, a negative errno value otherwise and rte_errno is set.
13670  */
13671 int
13672 mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev)
13673 {
13674         struct mlx5_priv *priv = dev->data->dev_private;
13675         struct mlx5_dev_ctx_shared *sh = priv->sh;
13676         struct mlx5_flow_dv_match_params mask = {
13677                 .size = sizeof(mask.buf),
13678         };
13679         struct mlx5_flow_dv_match_params value = {
13680                 .size = sizeof(value.buf),
13681         };
13682         struct mlx5dv_flow_matcher_attr dv_attr = {
13683                 .type = IBV_FLOW_ATTR_NORMAL,
13684                 .priority = 0,
13685                 .match_criteria_enable = 0,
13686                 .match_mask = (void *)&mask,
13687         };
13688         void *actions[2] = { 0 };
13689         struct mlx5_flow_tbl_resource *tbl = NULL;
13690         struct mlx5_devx_obj *dcs = NULL;
13691         void *matcher = NULL;
13692         void *flow = NULL;
13693         int ret = -1;
13694
13695         tbl = flow_dv_tbl_resource_get(dev, 0, 0, 0, false, NULL, 0, 0, NULL);
13696         if (!tbl)
13697                 goto err;
13698         dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
13699         if (!dcs)
13700                 goto err;
13701         ret = mlx5_flow_os_create_flow_action_count(dcs->obj, UINT16_MAX,
13702                                                     &actions[0]);
13703         if (ret)
13704                 goto err;
13705         actions[1] = priv->drop_queue.hrxq->action;
13706         dv_attr.match_criteria_enable = flow_dv_matcher_enable(mask.buf);
13707         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj,
13708                                                &matcher);
13709         if (ret)
13710                 goto err;
13711         ret = mlx5_flow_os_create_flow(matcher, (void *)&value, 2,
13712                                        actions, &flow);
13713 err:
13714         /*
13715          * If batch counter with offset is not supported, the driver will not
13716          * validate the invalid offset value, flow create should success.
13717          * In this case, it means batch counter is not supported in root table.
13718          *
13719          * Otherwise, if flow create is failed, counter offset is supported.
13720          */
13721         if (flow) {
13722                 DRV_LOG(INFO, "Batch counter is not supported in root "
13723                               "table. Switch to fallback mode.");
13724                 rte_errno = ENOTSUP;
13725                 ret = -rte_errno;
13726                 claim_zero(mlx5_flow_os_destroy_flow(flow));
13727         } else {
13728                 /* Check matcher to make sure validate fail at flow create. */
13729                 if (!matcher || (matcher && errno != EINVAL))
13730                         DRV_LOG(ERR, "Unexpected error in counter offset "
13731                                      "support detection");
13732                 ret = 0;
13733         }
13734         if (actions[0])
13735                 claim_zero(mlx5_flow_os_destroy_flow_action(actions[0]));
13736         if (matcher)
13737                 claim_zero(mlx5_flow_os_destroy_flow_matcher(matcher));
13738         if (tbl)
13739                 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
13740         if (dcs)
13741                 claim_zero(mlx5_devx_cmd_destroy(dcs));
13742         return ret;
13743 }
13744
13745 /**
13746  * Query a devx counter.
13747  *
13748  * @param[in] dev
13749  *   Pointer to the Ethernet device structure.
13750  * @param[in] cnt
13751  *   Index to the flow counter.
13752  * @param[in] clear
13753  *   Set to clear the counter statistics.
13754  * @param[out] pkts
13755  *   The statistics value of packets.
13756  * @param[out] bytes
13757  *   The statistics value of bytes.
13758  *
13759  * @return
13760  *   0 on success, otherwise return -1.
13761  */
13762 static int
13763 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
13764                       uint64_t *pkts, uint64_t *bytes)
13765 {
13766         struct mlx5_priv *priv = dev->data->dev_private;
13767         struct mlx5_flow_counter *cnt;
13768         uint64_t inn_pkts, inn_bytes;
13769         int ret;
13770
13771         if (!priv->config.devx)
13772                 return -1;
13773
13774         ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
13775         if (ret)
13776                 return -1;
13777         cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
13778         *pkts = inn_pkts - cnt->hits;
13779         *bytes = inn_bytes - cnt->bytes;
13780         if (clear) {
13781                 cnt->hits = inn_pkts;
13782                 cnt->bytes = inn_bytes;
13783         }
13784         return 0;
13785 }
13786
13787 /**
13788  * Get aged-out flows.
13789  *
13790  * @param[in] dev
13791  *   Pointer to the Ethernet device structure.
13792  * @param[in] context
13793  *   The address of an array of pointers to the aged-out flows contexts.
13794  * @param[in] nb_contexts
13795  *   The length of context array pointers.
13796  * @param[out] error
13797  *   Perform verbose error reporting if not NULL. Initialized in case of
13798  *   error only.
13799  *
13800  * @return
13801  *   how many contexts get in success, otherwise negative errno value.
13802  *   if nb_contexts is 0, return the amount of all aged contexts.
13803  *   if nb_contexts is not 0 , return the amount of aged flows reported
13804  *   in the context array.
13805  * @note: only stub for now
13806  */
13807 static int
13808 flow_get_aged_flows(struct rte_eth_dev *dev,
13809                     void **context,
13810                     uint32_t nb_contexts,
13811                     struct rte_flow_error *error)
13812 {
13813         struct mlx5_priv *priv = dev->data->dev_private;
13814         struct mlx5_age_info *age_info;
13815         struct mlx5_age_param *age_param;
13816         struct mlx5_flow_counter *counter;
13817         struct mlx5_aso_age_action *act;
13818         int nb_flows = 0;
13819
13820         if (nb_contexts && !context)
13821                 return rte_flow_error_set(error, EINVAL,
13822                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13823                                           NULL, "empty context");
13824         age_info = GET_PORT_AGE_INFO(priv);
13825         rte_spinlock_lock(&age_info->aged_sl);
13826         LIST_FOREACH(act, &age_info->aged_aso, next) {
13827                 nb_flows++;
13828                 if (nb_contexts) {
13829                         context[nb_flows - 1] =
13830                                                 act->age_params.context;
13831                         if (!(--nb_contexts))
13832                                 break;
13833                 }
13834         }
13835         TAILQ_FOREACH(counter, &age_info->aged_counters, next) {
13836                 nb_flows++;
13837                 if (nb_contexts) {
13838                         age_param = MLX5_CNT_TO_AGE(counter);
13839                         context[nb_flows - 1] = age_param->context;
13840                         if (!(--nb_contexts))
13841                                 break;
13842                 }
13843         }
13844         rte_spinlock_unlock(&age_info->aged_sl);
13845         MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
13846         return nb_flows;
13847 }
13848
13849 /*
13850  * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
13851  */
13852 static uint32_t
13853 flow_dv_counter_allocate(struct rte_eth_dev *dev)
13854 {
13855         return flow_dv_counter_alloc(dev, 0);
13856 }
13857
13858 /**
13859  * Validate shared action.
13860  * Dispatcher for action type specific validation.
13861  *
13862  * @param[in] dev
13863  *   Pointer to the Ethernet device structure.
13864  * @param[in] conf
13865  *   Shared action configuration.
13866  * @param[in] action
13867  *   The shared action object to validate.
13868  * @param[out] error
13869  *   Perform verbose error reporting if not NULL. Initialized in case of
13870  *   error only.
13871  *
13872  * @return
13873  *   0 on success, otherwise negative errno value.
13874  */
13875 static int
13876 flow_dv_action_validate(struct rte_eth_dev *dev,
13877                         const struct rte_flow_shared_action_conf *conf,
13878                         const struct rte_flow_action *action,
13879                         struct rte_flow_error *err)
13880 {
13881         struct mlx5_priv *priv = dev->data->dev_private;
13882
13883         RTE_SET_USED(conf);
13884         switch (action->type) {
13885         case RTE_FLOW_ACTION_TYPE_RSS:
13886                 /*
13887                  * priv->obj_ops is set according to driver capabilities.
13888                  * When DevX capabilities are
13889                  * sufficient, it is set to devx_obj_ops.
13890                  * Otherwise, it is set to ibv_obj_ops.
13891                  * ibv_obj_ops doesn't support ind_table_modify operation.
13892                  * In this case the shared RSS action can't be used.
13893                  */
13894                 if (priv->obj_ops.ind_table_modify == NULL)
13895                         return rte_flow_error_set
13896                                         (err, ENOTSUP,
13897                                          RTE_FLOW_ERROR_TYPE_ACTION,
13898                                          NULL,
13899                                          "shared RSS action not supported");
13900                 return mlx5_validate_action_rss(dev, action, err);
13901         case RTE_FLOW_ACTION_TYPE_AGE:
13902                 if (!priv->sh->aso_age_mng)
13903                         return rte_flow_error_set(err, ENOTSUP,
13904                                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13905                                                 NULL,
13906                                              "shared age action not supported");
13907                 return flow_dv_validate_action_age(0, action, dev, err);
13908         default:
13909                 return rte_flow_error_set(err, ENOTSUP,
13910                                           RTE_FLOW_ERROR_TYPE_ACTION,
13911                                           NULL,
13912                                           "action type not supported");
13913         }
13914 }
13915
13916 static int
13917 flow_dv_sync_domain(struct rte_eth_dev *dev, uint32_t domains, uint32_t flags)
13918 {
13919         struct mlx5_priv *priv = dev->data->dev_private;
13920         int ret = 0;
13921
13922         if ((domains & MLX5_DOMAIN_BIT_NIC_RX) && priv->sh->rx_domain != NULL) {
13923                 ret = mlx5_os_flow_dr_sync_domain(priv->sh->rx_domain,
13924                                                 flags);
13925                 if (ret != 0)
13926                         return ret;
13927         }
13928         if ((domains & MLX5_DOMAIN_BIT_NIC_TX) && priv->sh->tx_domain != NULL) {
13929                 ret = mlx5_os_flow_dr_sync_domain(priv->sh->tx_domain, flags);
13930                 if (ret != 0)
13931                         return ret;
13932         }
13933         if ((domains & MLX5_DOMAIN_BIT_FDB) && priv->sh->fdb_domain != NULL) {
13934                 ret = mlx5_os_flow_dr_sync_domain(priv->sh->fdb_domain, flags);
13935                 if (ret != 0)
13936                         return ret;
13937         }
13938         return 0;
13939 }
13940
13941 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
13942         .validate = flow_dv_validate,
13943         .prepare = flow_dv_prepare,
13944         .translate = flow_dv_translate,
13945         .apply = flow_dv_apply,
13946         .remove = flow_dv_remove,
13947         .destroy = flow_dv_destroy,
13948         .query = flow_dv_query,
13949         .create_mtr_tbls = flow_dv_create_mtr_tbl,
13950         .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
13951         .create_policer_rules = flow_dv_create_policer_rules,
13952         .destroy_policer_rules = flow_dv_destroy_policer_rules,
13953         .counter_alloc = flow_dv_counter_allocate,
13954         .counter_free = flow_dv_counter_free,
13955         .counter_query = flow_dv_counter_query,
13956         .get_aged_flows = flow_get_aged_flows,
13957         .action_validate = flow_dv_action_validate,
13958         .action_create = flow_dv_action_create,
13959         .action_destroy = flow_dv_action_destroy,
13960         .action_update = flow_dv_action_update,
13961         .action_query = flow_dv_action_query,
13962         .sync_domain = flow_dv_sync_domain,
13963 };
13964
13965 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */
13966