drivers/net/mlx5/mlx5_flow_dv.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2018 Mellanox Technologies, Ltd
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdalign.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10
  11 /* Verbs header. */
  12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  13 #ifdef PEDANTIC
  14 #pragma GCC diagnostic ignored "-Wpedantic"
  15 #endif
  16 #include <infiniband/verbs.h>
  17 #ifdef PEDANTIC
  18 #pragma GCC diagnostic error "-Wpedantic"
  19 #endif
  20
  21 #include <rte_common.h>
  22 #include <rte_ether.h>
  23 #include <rte_ethdev_driver.h>
  24 #include <rte_flow.h>
  25 #include <rte_flow_driver.h>
  26 #include <rte_malloc.h>
  27 #include <rte_cycles.h>
  28 #include <rte_ip.h>
  29 #include <rte_gre.h>
  30 #include <rte_vxlan.h>
  31 #include <rte_gtp.h>
  32
  33 #include <mlx5_glue.h>
  34 #include <mlx5_devx_cmds.h>
  35 #include <mlx5_prm.h>
  36
  37 #include "mlx5_defs.h"
  38 #include "mlx5.h"
  39 #include "mlx5_flow.h"
  40 #include "mlx5_rxtx.h"
  41
  42 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
  43
  44 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
  45 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
  46 #endif
  47
  48 #ifndef HAVE_MLX5DV_DR_ESWITCH
  49 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
  50 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
  51 #endif
  52 #endif
  53
  54 #ifndef HAVE_MLX5DV_DR
  55 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
  56 #endif
  57
  58 /* VLAN header definitions */
  59 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
  60 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
  61 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
  62 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
  63 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
  64
  65 union flow_dv_attr {
  66         struct {
  67                 uint32_t valid:1;
  68                 uint32_t ipv4:1;
  69                 uint32_t ipv6:1;
  70                 uint32_t tcp:1;
  71                 uint32_t udp:1;
  72                 uint32_t reserved:27;
  73         };
  74         uint32_t attr;
  75 };
  76
  77 static int
  78 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
  79                              struct mlx5_flow_tbl_resource *tbl);
  80
  81 /**
  82  * Initialize flow attributes structure according to flow items' types.
  83  *
  84  * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
  85  * mode. For tunnel mode, the items to be modified are the outermost ones.
  86  *
  87  * @param[in] item
  88  *   Pointer to item specification.
  89  * @param[out] attr
  90  *   Pointer to flow attributes structure.
  91  * @param[in] dev_flow
  92  *   Pointer to the sub flow.
  93  * @param[in] tunnel_decap
  94  *   Whether action is after tunnel decapsulation.
  95  */
  96 static void
  97 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
  98                   struct mlx5_flow *dev_flow, bool tunnel_decap)
  99 {
 100         uint64_t layers = dev_flow->handle->layers;
 101
 102         /*
 103          * If layers is already initialized, it means this dev_flow is the
 104          * suffix flow, the layers flags is set by the prefix flow. Need to
 105          * use the layer flags from prefix flow as the suffix flow may not
 106          * have the user defined items as the flow is split.
 107          */
 108         if (layers) {
 109                 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
 110                         attr->ipv4 = 1;
 111                 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
 112                         attr->ipv6 = 1;
 113                 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
 114                         attr->tcp = 1;
 115                 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
 116                         attr->udp = 1;
 117                 attr->valid = 1;
 118                 return;
 119         }
 120         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
 121                 uint8_t next_protocol = 0xff;
 122                 switch (item->type) {
 123                 case RTE_FLOW_ITEM_TYPE_GRE:
 124                 case RTE_FLOW_ITEM_TYPE_NVGRE:
 125                 case RTE_FLOW_ITEM_TYPE_VXLAN:
 126                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
 127                 case RTE_FLOW_ITEM_TYPE_GENEVE:
 128                 case RTE_FLOW_ITEM_TYPE_MPLS:
 129                         if (tunnel_decap)
 130                                 attr->attr = 0;
 131                         break;
 132                 case RTE_FLOW_ITEM_TYPE_IPV4:
 133                         if (!attr->ipv6)
 134                                 attr->ipv4 = 1;
 135                         if (item->mask != NULL &&
 136                             ((const struct rte_flow_item_ipv4 *)
 137                             item->mask)->hdr.next_proto_id)
 138                                 next_protocol =
 139                                     ((const struct rte_flow_item_ipv4 *)
 140                                       (item->spec))->hdr.next_proto_id &
 141                                     ((const struct rte_flow_item_ipv4 *)
 142                                       (item->mask))->hdr.next_proto_id;
 143                         if ((next_protocol == IPPROTO_IPIP ||
 144                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 145                                 attr->attr = 0;
 146                         break;
 147                 case RTE_FLOW_ITEM_TYPE_IPV6:
 148                         if (!attr->ipv4)
 149                                 attr->ipv6 = 1;
 150                         if (item->mask != NULL &&
 151                             ((const struct rte_flow_item_ipv6 *)
 152                             item->mask)->hdr.proto)
 153                                 next_protocol =
 154                                     ((const struct rte_flow_item_ipv6 *)
 155                                       (item->spec))->hdr.proto &
 156                                     ((const struct rte_flow_item_ipv6 *)
 157                                       (item->mask))->hdr.proto;
 158                         if ((next_protocol == IPPROTO_IPIP ||
 159                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 160                                 attr->attr = 0;
 161                         break;
 162                 case RTE_FLOW_ITEM_TYPE_UDP:
 163                         if (!attr->tcp)
 164                                 attr->udp = 1;
 165                         break;
 166                 case RTE_FLOW_ITEM_TYPE_TCP:
 167                         if (!attr->udp)
 168                                 attr->tcp = 1;
 169                         break;
 170                 default:
 171                         break;
 172                 }
 173         }
 174         attr->valid = 1;
 175 }
 176
 177 /**
 178  * Convert rte_mtr_color to mlx5 color.
 179  *
 180  * @param[in] rcol
 181  *   rte_mtr_color.
 182  *
 183  * @return
 184  *   mlx5 color.
 185  */
 186 static int
 187 rte_col_2_mlx5_col(enum rte_color rcol)
 188 {
 189         switch (rcol) {
 190         case RTE_COLOR_GREEN:
 191                 return MLX5_FLOW_COLOR_GREEN;
 192         case RTE_COLOR_YELLOW:
 193                 return MLX5_FLOW_COLOR_YELLOW;
 194         case RTE_COLOR_RED:
 195                 return MLX5_FLOW_COLOR_RED;
 196         default:
 197                 break;
 198         }
 199         return MLX5_FLOW_COLOR_UNDEFINED;
 200 }
 201
 202 struct field_modify_info {
 203         uint32_t size; /* Size of field in protocol header, in bytes. */
 204         uint32_t offset; /* Offset of field in protocol header, in bytes. */
 205         enum mlx5_modification_field id;
 206 };
 207
 208 struct field_modify_info modify_eth[] = {
 209         {4,  0, MLX5_MODI_OUT_DMAC_47_16},
 210         {2,  4, MLX5_MODI_OUT_DMAC_15_0},
 211         {4,  6, MLX5_MODI_OUT_SMAC_47_16},
 212         {2, 10, MLX5_MODI_OUT_SMAC_15_0},
 213         {0, 0, 0},
 214 };
 215
 216 struct field_modify_info modify_vlan_out_first_vid[] = {
 217         /* Size in bits !!! */
 218         {12, 0, MLX5_MODI_OUT_FIRST_VID},
 219         {0, 0, 0},
 220 };
 221
 222 struct field_modify_info modify_ipv4[] = {
 223         {1,  1, MLX5_MODI_OUT_IP_DSCP},
 224         {1,  8, MLX5_MODI_OUT_IPV4_TTL},
 225         {4, 12, MLX5_MODI_OUT_SIPV4},
 226         {4, 16, MLX5_MODI_OUT_DIPV4},
 227         {0, 0, 0},
 228 };
 229
 230 struct field_modify_info modify_ipv6[] = {
 231         {1,  0, MLX5_MODI_OUT_IP_DSCP},
 232         {1,  7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
 233         {4,  8, MLX5_MODI_OUT_SIPV6_127_96},
 234         {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
 235         {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
 236         {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
 237         {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
 238         {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
 239         {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
 240         {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
 241         {0, 0, 0},
 242 };
 243
 244 struct field_modify_info modify_udp[] = {
 245         {2, 0, MLX5_MODI_OUT_UDP_SPORT},
 246         {2, 2, MLX5_MODI_OUT_UDP_DPORT},
 247         {0, 0, 0},
 248 };
 249
 250 struct field_modify_info modify_tcp[] = {
 251         {2, 0, MLX5_MODI_OUT_TCP_SPORT},
 252         {2, 2, MLX5_MODI_OUT_TCP_DPORT},
 253         {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
 254         {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
 255         {0, 0, 0},
 256 };
 257
 258 static void
 259 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
 260                           uint8_t next_protocol, uint64_t *item_flags,
 261                           int *tunnel)
 262 {
 263         MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
 264                     item->type == RTE_FLOW_ITEM_TYPE_IPV6);
 265         if (next_protocol == IPPROTO_IPIP) {
 266                 *item_flags |= MLX5_FLOW_LAYER_IPIP;
 267                 *tunnel = 1;
 268         }
 269         if (next_protocol == IPPROTO_IPV6) {
 270                 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
 271                 *tunnel = 1;
 272         }
 273 }
 274
 275 /**
 276  * Acquire the synchronizing object to protect multithreaded access
 277  * to shared dv context. Lock occurs only if context is actually
 278  * shared, i.e. we have multiport IB device and representors are
 279  * created.
 280  *
 281  * @param[in] dev
 282  *   Pointer to the rte_eth_dev structure.
 283  */
 284 static void
 285 flow_dv_shared_lock(struct rte_eth_dev *dev)
 286 {
 287         struct mlx5_priv *priv = dev->data->dev_private;
 288         struct mlx5_ibv_shared *sh = priv->sh;
 289
 290         if (sh->dv_refcnt > 1) {
 291                 int ret;
 292
 293                 ret = pthread_mutex_lock(&sh->dv_mutex);
 294                 MLX5_ASSERT(!ret);
 295                 (void)ret;
 296         }
 297 }
 298
 299 static void
 300 flow_dv_shared_unlock(struct rte_eth_dev *dev)
 301 {
 302         struct mlx5_priv *priv = dev->data->dev_private;
 303         struct mlx5_ibv_shared *sh = priv->sh;
 304
 305         if (sh->dv_refcnt > 1) {
 306                 int ret;
 307
 308                 ret = pthread_mutex_unlock(&sh->dv_mutex);
 309                 MLX5_ASSERT(!ret);
 310                 (void)ret;
 311         }
 312 }
 313
 314 /* Update VLAN's VID/PCP based on input rte_flow_action.
 315  *
 316  * @param[in] action
 317  *   Pointer to struct rte_flow_action.
 318  * @param[out] vlan
 319  *   Pointer to struct rte_vlan_hdr.
 320  */
 321 static void
 322 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
 323                          struct rte_vlan_hdr *vlan)
 324 {
 325         uint16_t vlan_tci;
 326         if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
 327                 vlan_tci =
 328                     ((const struct rte_flow_action_of_set_vlan_pcp *)
 329                                                action->conf)->vlan_pcp;
 330                 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
 331                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
 332                 vlan->vlan_tci |= vlan_tci;
 333         } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
 334                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
 335                 vlan->vlan_tci |= rte_be_to_cpu_16
 336                     (((const struct rte_flow_action_of_set_vlan_vid *)
 337                                              action->conf)->vlan_vid);
 338         }
 339 }
 340
 341 /**
 342  * Fetch 1, 2, 3 or 4 byte field from the byte array
 343  * and return as unsigned integer in host-endian format.
 344  *
 345  * @param[in] data
 346  *   Pointer to data array.
 347  * @param[in] size
 348  *   Size of field to extract.
 349  *
 350  * @return
 351  *   converted field in host endian format.
 352  */
 353 static inline uint32_t
 354 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
 355 {
 356         uint32_t ret;
 357
 358         switch (size) {
 359         case 1:
 360                 ret = *data;
 361                 break;
 362         case 2:
 363                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 364                 break;
 365         case 3:
 366                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 367                 ret = (ret << 8) | *(data + sizeof(uint16_t));
 368                 break;
 369         case 4:
 370                 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
 371                 break;
 372         default:
 373                 MLX5_ASSERT(false);
 374                 ret = 0;
 375                 break;
 376         }
 377         return ret;
 378 }
 379
 380 /**
 381  * Convert modify-header action to DV specification.
 382  *
 383  * Data length of each action is determined by provided field description
 384  * and the item mask. Data bit offset and width of each action is determined
 385  * by provided item mask.
 386  *
 387  * @param[in] item
 388  *   Pointer to item specification.
 389  * @param[in] field
 390  *   Pointer to field modification information.
 391  *     For MLX5_MODIFICATION_TYPE_SET specifies destination field.
 392  *     For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
 393  *     For MLX5_MODIFICATION_TYPE_COPY specifies source field.
 394  * @param[in] dcopy
 395  *   Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
 396  *   Negative offset value sets the same offset as source offset.
 397  *   size field is ignored, value is taken from source field.
 398  * @param[in,out] resource
 399  *   Pointer to the modify-header resource.
 400  * @param[in] type
 401  *   Type of modification.
 402  * @param[out] error
 403  *   Pointer to the error structure.
 404  *
 405  * @return
 406  *   0 on success, a negative errno value otherwise and rte_errno is set.
 407  */
 408 static int
 409 flow_dv_convert_modify_action(struct rte_flow_item *item,
 410                               struct field_modify_info *field,
 411                               struct field_modify_info *dcopy,
 412                               struct mlx5_flow_dv_modify_hdr_resource *resource,
 413                               uint32_t type, struct rte_flow_error *error)
 414 {
 415         uint32_t i = resource->actions_num;
 416         struct mlx5_modification_cmd *actions = resource->actions;
 417
 418         /*
 419          * The item and mask are provided in big-endian format.
 420          * The fields should be presented as in big-endian format either.
 421          * Mask must be always present, it defines the actual field width.
 422          */
 423         MLX5_ASSERT(item->mask);
 424         MLX5_ASSERT(field->size);
 425         do {
 426                 unsigned int size_b;
 427                 unsigned int off_b;
 428                 uint32_t mask;
 429                 uint32_t data;
 430
 431                 if (i >= MLX5_MAX_MODIFY_NUM)
 432                         return rte_flow_error_set(error, EINVAL,
 433                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 434                                  "too many items to modify");
 435                 /* Fetch variable byte size mask from the array. */
 436                 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
 437                                            field->offset, field->size);
 438                 if (!mask) {
 439                         ++field;
 440                         continue;
 441                 }
 442                 /* Deduce actual data width in bits from mask value. */
 443                 off_b = rte_bsf32(mask);
 444                 size_b = sizeof(uint32_t) * CHAR_BIT -
 445                          off_b - __builtin_clz(mask);
 446                 MLX5_ASSERT(size_b);
 447                 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
 448                 actions[i] = (struct mlx5_modification_cmd) {
 449                         .action_type = type,
 450                         .field = field->id,
 451                         .offset = off_b,
 452                         .length = size_b,
 453                 };
 454                 /* Convert entire record to expected big-endian format. */
 455                 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 456                 if (type == MLX5_MODIFICATION_TYPE_COPY) {
 457                         MLX5_ASSERT(dcopy);
 458                         actions[i].dst_field = dcopy->id;
 459                         actions[i].dst_offset =
 460                                 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
 461                         /* Convert entire record to big-endian format. */
 462                         actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
 463                 } else {
 464                         MLX5_ASSERT(item->spec);
 465                         data = flow_dv_fetch_field((const uint8_t *)item->spec +
 466                                                    field->offset, field->size);
 467                         /* Shift out the trailing masked bits from data. */
 468                         data = (data & mask) >> off_b;
 469                         actions[i].data1 = rte_cpu_to_be_32(data);
 470                 }
 471                 ++i;
 472                 ++field;
 473         } while (field->size);
 474         if (resource->actions_num == i)
 475                 return rte_flow_error_set(error, EINVAL,
 476                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 477                                           "invalid modification flow item");
 478         resource->actions_num = i;
 479         return 0;
 480 }
 481
 482 /**
 483  * Convert modify-header set IPv4 address action to DV specification.
 484  *
 485  * @param[in,out] resource
 486  *   Pointer to the modify-header resource.
 487  * @param[in] action
 488  *   Pointer to action specification.
 489  * @param[out] error
 490  *   Pointer to the error structure.
 491  *
 492  * @return
 493  *   0 on success, a negative errno value otherwise and rte_errno is set.
 494  */
 495 static int
 496 flow_dv_convert_action_modify_ipv4
 497                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 498                          const struct rte_flow_action *action,
 499                          struct rte_flow_error *error)
 500 {
 501         const struct rte_flow_action_set_ipv4 *conf =
 502                 (const struct rte_flow_action_set_ipv4 *)(action->conf);
 503         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
 504         struct rte_flow_item_ipv4 ipv4;
 505         struct rte_flow_item_ipv4 ipv4_mask;
 506
 507         memset(&ipv4, 0, sizeof(ipv4));
 508         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 509         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
 510                 ipv4.hdr.src_addr = conf->ipv4_addr;
 511                 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
 512         } else {
 513                 ipv4.hdr.dst_addr = conf->ipv4_addr;
 514                 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
 515         }
 516         item.spec = &ipv4;
 517         item.mask = &ipv4_mask;
 518         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
 519                                              MLX5_MODIFICATION_TYPE_SET, error);
 520 }
 521
 522 /**
 523  * Convert modify-header set IPv6 address action to DV specification.
 524  *
 525  * @param[in,out] resource
 526  *   Pointer to the modify-header resource.
 527  * @param[in] action
 528  *   Pointer to action specification.
 529  * @param[out] error
 530  *   Pointer to the error structure.
 531  *
 532  * @return
 533  *   0 on success, a negative errno value otherwise and rte_errno is set.
 534  */
 535 static int
 536 flow_dv_convert_action_modify_ipv6
 537                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 538                          const struct rte_flow_action *action,
 539                          struct rte_flow_error *error)
 540 {
 541         const struct rte_flow_action_set_ipv6 *conf =
 542                 (const struct rte_flow_action_set_ipv6 *)(action->conf);
 543         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
 544         struct rte_flow_item_ipv6 ipv6;
 545         struct rte_flow_item_ipv6 ipv6_mask;
 546
 547         memset(&ipv6, 0, sizeof(ipv6));
 548         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 549         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
 550                 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
 551                        sizeof(ipv6.hdr.src_addr));
 552                 memcpy(&ipv6_mask.hdr.src_addr,
 553                        &rte_flow_item_ipv6_mask.hdr.src_addr,
 554                        sizeof(ipv6.hdr.src_addr));
 555         } else {
 556                 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
 557                        sizeof(ipv6.hdr.dst_addr));
 558                 memcpy(&ipv6_mask.hdr.dst_addr,
 559                        &rte_flow_item_ipv6_mask.hdr.dst_addr,
 560                        sizeof(ipv6.hdr.dst_addr));
 561         }
 562         item.spec = &ipv6;
 563         item.mask = &ipv6_mask;
 564         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
 565                                              MLX5_MODIFICATION_TYPE_SET, error);
 566 }
 567
 568 /**
 569  * Convert modify-header set MAC address action to DV specification.
 570  *
 571  * @param[in,out] resource
 572  *   Pointer to the modify-header resource.
 573  * @param[in] action
 574  *   Pointer to action specification.
 575  * @param[out] error
 576  *   Pointer to the error structure.
 577  *
 578  * @return
 579  *   0 on success, a negative errno value otherwise and rte_errno is set.
 580  */
 581 static int
 582 flow_dv_convert_action_modify_mac
 583                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 584                          const struct rte_flow_action *action,
 585                          struct rte_flow_error *error)
 586 {
 587         const struct rte_flow_action_set_mac *conf =
 588                 (const struct rte_flow_action_set_mac *)(action->conf);
 589         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
 590         struct rte_flow_item_eth eth;
 591         struct rte_flow_item_eth eth_mask;
 592
 593         memset(&eth, 0, sizeof(eth));
 594         memset(&eth_mask, 0, sizeof(eth_mask));
 595         if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
 596                 memcpy(&eth.src.addr_bytes, &conf->mac_addr,
 597                        sizeof(eth.src.addr_bytes));
 598                 memcpy(&eth_mask.src.addr_bytes,
 599                        &rte_flow_item_eth_mask.src.addr_bytes,
 600                        sizeof(eth_mask.src.addr_bytes));
 601         } else {
 602                 memcpy(&eth.dst.addr_bytes, &conf->mac_addr,
 603                        sizeof(eth.dst.addr_bytes));
 604                 memcpy(&eth_mask.dst.addr_bytes,
 605                        &rte_flow_item_eth_mask.dst.addr_bytes,
 606                        sizeof(eth_mask.dst.addr_bytes));
 607         }
 608         item.spec = &eth;
 609         item.mask = &eth_mask;
 610         return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
 611                                              MLX5_MODIFICATION_TYPE_SET, error);
 612 }
 613
 614 /**
 615  * Convert modify-header set VLAN VID action to DV specification.
 616  *
 617  * @param[in,out] resource
 618  *   Pointer to the modify-header resource.
 619  * @param[in] action
 620  *   Pointer to action specification.
 621  * @param[out] error
 622  *   Pointer to the error structure.
 623  *
 624  * @return
 625  *   0 on success, a negative errno value otherwise and rte_errno is set.
 626  */
 627 static int
 628 flow_dv_convert_action_modify_vlan_vid
 629                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 630                          const struct rte_flow_action *action,
 631                          struct rte_flow_error *error)
 632 {
 633         const struct rte_flow_action_of_set_vlan_vid *conf =
 634                 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
 635         int i = resource->actions_num;
 636         struct mlx5_modification_cmd *actions = resource->actions;
 637         struct field_modify_info *field = modify_vlan_out_first_vid;
 638
 639         if (i >= MLX5_MAX_MODIFY_NUM)
 640                 return rte_flow_error_set(error, EINVAL,
 641                          RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 642                          "too many items to modify");
 643         actions[i] = (struct mlx5_modification_cmd) {
 644                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 645                 .field = field->id,
 646                 .length = field->size,
 647                 .offset = field->offset,
 648         };
 649         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 650         actions[i].data1 = conf->vlan_vid;
 651         actions[i].data1 = actions[i].data1 << 16;
 652         resource->actions_num = ++i;
 653         return 0;
 654 }
 655
 656 /**
 657  * Convert modify-header set TP action to DV specification.
 658  *
 659  * @param[in,out] resource
 660  *   Pointer to the modify-header resource.
 661  * @param[in] action
 662  *   Pointer to action specification.
 663  * @param[in] items
 664  *   Pointer to rte_flow_item objects list.
 665  * @param[in] attr
 666  *   Pointer to flow attributes structure.
 667  * @param[in] dev_flow
 668  *   Pointer to the sub flow.
 669  * @param[in] tunnel_decap
 670  *   Whether action is after tunnel decapsulation.
 671  * @param[out] error
 672  *   Pointer to the error structure.
 673  *
 674  * @return
 675  *   0 on success, a negative errno value otherwise and rte_errno is set.
 676  */
 677 static int
 678 flow_dv_convert_action_modify_tp
 679                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 680                          const struct rte_flow_action *action,
 681                          const struct rte_flow_item *items,
 682                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 683                          bool tunnel_decap, struct rte_flow_error *error)
 684 {
 685         const struct rte_flow_action_set_tp *conf =
 686                 (const struct rte_flow_action_set_tp *)(action->conf);
 687         struct rte_flow_item item;
 688         struct rte_flow_item_udp udp;
 689         struct rte_flow_item_udp udp_mask;
 690         struct rte_flow_item_tcp tcp;
 691         struct rte_flow_item_tcp tcp_mask;
 692         struct field_modify_info *field;
 693
 694         if (!attr->valid)
 695                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 696         if (attr->udp) {
 697                 memset(&udp, 0, sizeof(udp));
 698                 memset(&udp_mask, 0, sizeof(udp_mask));
 699                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 700                         udp.hdr.src_port = conf->port;
 701                         udp_mask.hdr.src_port =
 702                                         rte_flow_item_udp_mask.hdr.src_port;
 703                 } else {
 704                         udp.hdr.dst_port = conf->port;
 705                         udp_mask.hdr.dst_port =
 706                                         rte_flow_item_udp_mask.hdr.dst_port;
 707                 }
 708                 item.type = RTE_FLOW_ITEM_TYPE_UDP;
 709                 item.spec = &udp;
 710                 item.mask = &udp_mask;
 711                 field = modify_udp;
 712         } else {
 713                 MLX5_ASSERT(attr->tcp);
 714                 memset(&tcp, 0, sizeof(tcp));
 715                 memset(&tcp_mask, 0, sizeof(tcp_mask));
 716                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 717                         tcp.hdr.src_port = conf->port;
 718                         tcp_mask.hdr.src_port =
 719                                         rte_flow_item_tcp_mask.hdr.src_port;
 720                 } else {
 721                         tcp.hdr.dst_port = conf->port;
 722                         tcp_mask.hdr.dst_port =
 723                                         rte_flow_item_tcp_mask.hdr.dst_port;
 724                 }
 725                 item.type = RTE_FLOW_ITEM_TYPE_TCP;
 726                 item.spec = &tcp;
 727                 item.mask = &tcp_mask;
 728                 field = modify_tcp;
 729         }
 730         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 731                                              MLX5_MODIFICATION_TYPE_SET, error);
 732 }
 733
 734 /**
 735  * Convert modify-header set TTL action to DV specification.
 736  *
 737  * @param[in,out] resource
 738  *   Pointer to the modify-header resource.
 739  * @param[in] action
 740  *   Pointer to action specification.
 741  * @param[in] items
 742  *   Pointer to rte_flow_item objects list.
 743  * @param[in] attr
 744  *   Pointer to flow attributes structure.
 745  * @param[in] dev_flow
 746  *   Pointer to the sub flow.
 747  * @param[in] tunnel_decap
 748  *   Whether action is after tunnel decapsulation.
 749  * @param[out] error
 750  *   Pointer to the error structure.
 751  *
 752  * @return
 753  *   0 on success, a negative errno value otherwise and rte_errno is set.
 754  */
 755 static int
 756 flow_dv_convert_action_modify_ttl
 757                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 758                          const struct rte_flow_action *action,
 759                          const struct rte_flow_item *items,
 760                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 761                          bool tunnel_decap, struct rte_flow_error *error)
 762 {
 763         const struct rte_flow_action_set_ttl *conf =
 764                 (const struct rte_flow_action_set_ttl *)(action->conf);
 765         struct rte_flow_item item;
 766         struct rte_flow_item_ipv4 ipv4;
 767         struct rte_flow_item_ipv4 ipv4_mask;
 768         struct rte_flow_item_ipv6 ipv6;
 769         struct rte_flow_item_ipv6 ipv6_mask;
 770         struct field_modify_info *field;
 771
 772         if (!attr->valid)
 773                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 774         if (attr->ipv4) {
 775                 memset(&ipv4, 0, sizeof(ipv4));
 776                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 777                 ipv4.hdr.time_to_live = conf->ttl_value;
 778                 ipv4_mask.hdr.time_to_live = 0xFF;
 779                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 780                 item.spec = &ipv4;
 781                 item.mask = &ipv4_mask;
 782                 field = modify_ipv4;
 783         } else {
 784                 MLX5_ASSERT(attr->ipv6);
 785                 memset(&ipv6, 0, sizeof(ipv6));
 786                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 787                 ipv6.hdr.hop_limits = conf->ttl_value;
 788                 ipv6_mask.hdr.hop_limits = 0xFF;
 789                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 790                 item.spec = &ipv6;
 791                 item.mask = &ipv6_mask;
 792                 field = modify_ipv6;
 793         }
 794         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 795                                              MLX5_MODIFICATION_TYPE_SET, error);
 796 }
 797
 798 /**
 799  * Convert modify-header decrement TTL action to DV specification.
 800  *
 801  * @param[in,out] resource
 802  *   Pointer to the modify-header resource.
 803  * @param[in] action
 804  *   Pointer to action specification.
 805  * @param[in] items
 806  *   Pointer to rte_flow_item objects list.
 807  * @param[in] attr
 808  *   Pointer to flow attributes structure.
 809  * @param[in] dev_flow
 810  *   Pointer to the sub flow.
 811  * @param[in] tunnel_decap
 812  *   Whether action is after tunnel decapsulation.
 813  * @param[out] error
 814  *   Pointer to the error structure.
 815  *
 816  * @return
 817  *   0 on success, a negative errno value otherwise and rte_errno is set.
 818  */
 819 static int
 820 flow_dv_convert_action_modify_dec_ttl
 821                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 822                          const struct rte_flow_item *items,
 823                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 824                          bool tunnel_decap, struct rte_flow_error *error)
 825 {
 826         struct rte_flow_item item;
 827         struct rte_flow_item_ipv4 ipv4;
 828         struct rte_flow_item_ipv4 ipv4_mask;
 829         struct rte_flow_item_ipv6 ipv6;
 830         struct rte_flow_item_ipv6 ipv6_mask;
 831         struct field_modify_info *field;
 832
 833         if (!attr->valid)
 834                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 835         if (attr->ipv4) {
 836                 memset(&ipv4, 0, sizeof(ipv4));
 837                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 838                 ipv4.hdr.time_to_live = 0xFF;
 839                 ipv4_mask.hdr.time_to_live = 0xFF;
 840                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 841                 item.spec = &ipv4;
 842                 item.mask = &ipv4_mask;
 843                 field = modify_ipv4;
 844         } else {
 845                 MLX5_ASSERT(attr->ipv6);
 846                 memset(&ipv6, 0, sizeof(ipv6));
 847                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 848                 ipv6.hdr.hop_limits = 0xFF;
 849                 ipv6_mask.hdr.hop_limits = 0xFF;
 850                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 851                 item.spec = &ipv6;
 852                 item.mask = &ipv6_mask;
 853                 field = modify_ipv6;
 854         }
 855         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 856                                              MLX5_MODIFICATION_TYPE_ADD, error);
 857 }
 858
 859 /**
 860  * Convert modify-header increment/decrement TCP Sequence number
 861  * to DV specification.
 862  *
 863  * @param[in,out] resource
 864  *   Pointer to the modify-header resource.
 865  * @param[in] action
 866  *   Pointer to action specification.
 867  * @param[out] error
 868  *   Pointer to the error structure.
 869  *
 870  * @return
 871  *   0 on success, a negative errno value otherwise and rte_errno is set.
 872  */
 873 static int
 874 flow_dv_convert_action_modify_tcp_seq
 875                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 876                          const struct rte_flow_action *action,
 877                          struct rte_flow_error *error)
 878 {
 879         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 880         uint64_t value = rte_be_to_cpu_32(*conf);
 881         struct rte_flow_item item;
 882         struct rte_flow_item_tcp tcp;
 883         struct rte_flow_item_tcp tcp_mask;
 884
 885         memset(&tcp, 0, sizeof(tcp));
 886         memset(&tcp_mask, 0, sizeof(tcp_mask));
 887         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
 888                 /*
 889                  * The HW has no decrement operation, only increment operation.
 890                  * To simulate decrement X from Y using increment operation
 891                  * we need to add UINT32_MAX X times to Y.
 892                  * Each adding of UINT32_MAX decrements Y by 1.
 893                  */
 894                 value *= UINT32_MAX;
 895         tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
 896         tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
 897         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 898         item.spec = &tcp;
 899         item.mask = &tcp_mask;
 900         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 901                                              MLX5_MODIFICATION_TYPE_ADD, error);
 902 }
 903
 904 /**
 905  * Convert modify-header increment/decrement TCP Acknowledgment number
 906  * to DV specification.
 907  *
 908  * @param[in,out] resource
 909  *   Pointer to the modify-header resource.
 910  * @param[in] action
 911  *   Pointer to action specification.
 912  * @param[out] error
 913  *   Pointer to the error structure.
 914  *
 915  * @return
 916  *   0 on success, a negative errno value otherwise and rte_errno is set.
 917  */
 918 static int
 919 flow_dv_convert_action_modify_tcp_ack
 920                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 921                          const struct rte_flow_action *action,
 922                          struct rte_flow_error *error)
 923 {
 924         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 925         uint64_t value = rte_be_to_cpu_32(*conf);
 926         struct rte_flow_item item;
 927         struct rte_flow_item_tcp tcp;
 928         struct rte_flow_item_tcp tcp_mask;
 929
 930         memset(&tcp, 0, sizeof(tcp));
 931         memset(&tcp_mask, 0, sizeof(tcp_mask));
 932         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
 933                 /*
 934                  * The HW has no decrement operation, only increment operation.
 935                  * To simulate decrement X from Y using increment operation
 936                  * we need to add UINT32_MAX X times to Y.
 937                  * Each adding of UINT32_MAX decrements Y by 1.
 938                  */
 939                 value *= UINT32_MAX;
 940         tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
 941         tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
 942         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 943         item.spec = &tcp;
 944         item.mask = &tcp_mask;
 945         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 946                                              MLX5_MODIFICATION_TYPE_ADD, error);
 947 }
 948
 949 static enum mlx5_modification_field reg_to_field[] = {
 950         [REG_NONE] = MLX5_MODI_OUT_NONE,
 951         [REG_A] = MLX5_MODI_META_DATA_REG_A,
 952         [REG_B] = MLX5_MODI_META_DATA_REG_B,
 953         [REG_C_0] = MLX5_MODI_META_REG_C_0,
 954         [REG_C_1] = MLX5_MODI_META_REG_C_1,
 955         [REG_C_2] = MLX5_MODI_META_REG_C_2,
 956         [REG_C_3] = MLX5_MODI_META_REG_C_3,
 957         [REG_C_4] = MLX5_MODI_META_REG_C_4,
 958         [REG_C_5] = MLX5_MODI_META_REG_C_5,
 959         [REG_C_6] = MLX5_MODI_META_REG_C_6,
 960         [REG_C_7] = MLX5_MODI_META_REG_C_7,
 961 };
 962
 963 /**
 964  * Convert register set to DV specification.
 965  *
 966  * @param[in,out] resource
 967  *   Pointer to the modify-header resource.
 968  * @param[in] action
 969  *   Pointer to action specification.
 970  * @param[out] error
 971  *   Pointer to the error structure.
 972  *
 973  * @return
 974  *   0 on success, a negative errno value otherwise and rte_errno is set.
 975  */
 976 static int
 977 flow_dv_convert_action_set_reg
 978                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 979                          const struct rte_flow_action *action,
 980                          struct rte_flow_error *error)
 981 {
 982         const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
 983         struct mlx5_modification_cmd *actions = resource->actions;
 984         uint32_t i = resource->actions_num;
 985
 986         if (i >= MLX5_MAX_MODIFY_NUM)
 987                 return rte_flow_error_set(error, EINVAL,
 988                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 989                                           "too many items to modify");
 990         MLX5_ASSERT(conf->id != REG_NONE);
 991         MLX5_ASSERT(conf->id < RTE_DIM(reg_to_field));
 992         actions[i] = (struct mlx5_modification_cmd) {
 993                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 994                 .field = reg_to_field[conf->id],
 995         };
 996         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 997         actions[i].data1 = rte_cpu_to_be_32(conf->data);
 998         ++i;
 999         resource->actions_num = i;
1000         return 0;
1001 }
1002
1003 /**
1004  * Convert SET_TAG action to DV specification.
1005  *
1006  * @param[in] dev
1007  *   Pointer to the rte_eth_dev structure.
1008  * @param[in,out] resource
1009  *   Pointer to the modify-header resource.
1010  * @param[in] conf
1011  *   Pointer to action specification.
1012  * @param[out] error
1013  *   Pointer to the error structure.
1014  *
1015  * @return
1016  *   0 on success, a negative errno value otherwise and rte_errno is set.
1017  */
1018 static int
1019 flow_dv_convert_action_set_tag
1020                         (struct rte_eth_dev *dev,
1021                          struct mlx5_flow_dv_modify_hdr_resource *resource,
1022                          const struct rte_flow_action_set_tag *conf,
1023                          struct rte_flow_error *error)
1024 {
1025         rte_be32_t data = rte_cpu_to_be_32(conf->data);
1026         rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
1027         struct rte_flow_item item = {
1028                 .spec = &data,
1029                 .mask = &mask,
1030         };
1031         struct field_modify_info reg_c_x[] = {
1032                 [1] = {0, 0, 0},
1033         };
1034         enum mlx5_modification_field reg_type;
1035         int ret;
1036
1037         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1038         if (ret < 0)
1039                 return ret;
1040         MLX5_ASSERT(ret != REG_NONE);
1041         MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1042         reg_type = reg_to_field[ret];
1043         MLX5_ASSERT(reg_type > 0);
1044         reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1045         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1046                                              MLX5_MODIFICATION_TYPE_SET, error);
1047 }
1048
1049 /**
1050  * Convert internal COPY_REG action to DV specification.
1051  *
1052  * @param[in] dev
1053  *   Pointer to the rte_eth_dev structure.
1054  * @param[in,out] res
1055  *   Pointer to the modify-header resource.
1056  * @param[in] action
1057  *   Pointer to action specification.
1058  * @param[out] error
1059  *   Pointer to the error structure.
1060  *
1061  * @return
1062  *   0 on success, a negative errno value otherwise and rte_errno is set.
1063  */
1064 static int
1065 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1066                                  struct mlx5_flow_dv_modify_hdr_resource *res,
1067                                  const struct rte_flow_action *action,
1068                                  struct rte_flow_error *error)
1069 {
1070         const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1071         rte_be32_t mask = RTE_BE32(UINT32_MAX);
1072         struct rte_flow_item item = {
1073                 .spec = NULL,
1074                 .mask = &mask,
1075         };
1076         struct field_modify_info reg_src[] = {
1077                 {4, 0, reg_to_field[conf->src]},
1078                 {0, 0, 0},
1079         };
1080         struct field_modify_info reg_dst = {
1081                 .offset = 0,
1082                 .id = reg_to_field[conf->dst],
1083         };
1084         /* Adjust reg_c[0] usage according to reported mask. */
1085         if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1086                 struct mlx5_priv *priv = dev->data->dev_private;
1087                 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1088
1089                 MLX5_ASSERT(reg_c0);
1090                 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1091                 if (conf->dst == REG_C_0) {
1092                         /* Copy to reg_c[0], within mask only. */
1093                         reg_dst.offset = rte_bsf32(reg_c0);
1094                         /*
1095                          * Mask is ignoring the enianness, because
1096                          * there is no conversion in datapath.
1097                          */
1098 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1099                         /* Copy from destination lower bits to reg_c[0]. */
1100                         mask = reg_c0 >> reg_dst.offset;
1101 #else
1102                         /* Copy from destination upper bits to reg_c[0]. */
1103                         mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1104                                           rte_fls_u32(reg_c0));
1105 #endif
1106                 } else {
1107                         mask = rte_cpu_to_be_32(reg_c0);
1108 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1109                         /* Copy from reg_c[0] to destination lower bits. */
1110                         reg_dst.offset = 0;
1111 #else
1112                         /* Copy from reg_c[0] to destination upper bits. */
1113                         reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1114                                          (rte_fls_u32(reg_c0) -
1115                                           rte_bsf32(reg_c0));
1116 #endif
1117                 }
1118         }
1119         return flow_dv_convert_modify_action(&item,
1120                                              reg_src, &reg_dst, res,
1121                                              MLX5_MODIFICATION_TYPE_COPY,
1122                                              error);
1123 }
1124
1125 /**
1126  * Convert MARK action to DV specification. This routine is used
1127  * in extensive metadata only and requires metadata register to be
1128  * handled. In legacy mode hardware tag resource is engaged.
1129  *
1130  * @param[in] dev
1131  *   Pointer to the rte_eth_dev structure.
1132  * @param[in] conf
1133  *   Pointer to MARK action specification.
1134  * @param[in,out] resource
1135  *   Pointer to the modify-header resource.
1136  * @param[out] error
1137  *   Pointer to the error structure.
1138  *
1139  * @return
1140  *   0 on success, a negative errno value otherwise and rte_errno is set.
1141  */
1142 static int
1143 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1144                             const struct rte_flow_action_mark *conf,
1145                             struct mlx5_flow_dv_modify_hdr_resource *resource,
1146                             struct rte_flow_error *error)
1147 {
1148         struct mlx5_priv *priv = dev->data->dev_private;
1149         rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1150                                            priv->sh->dv_mark_mask);
1151         rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1152         struct rte_flow_item item = {
1153                 .spec = &data,
1154                 .mask = &mask,
1155         };
1156         struct field_modify_info reg_c_x[] = {
1157                 {4, 0, 0}, /* dynamic instead of MLX5_MODI_META_REG_C_1. */
1158                 {0, 0, 0},
1159         };
1160         int reg;
1161
1162         if (!mask)
1163                 return rte_flow_error_set(error, EINVAL,
1164                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1165                                           NULL, "zero mark action mask");
1166         reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1167         if (reg < 0)
1168                 return reg;
1169         MLX5_ASSERT(reg > 0);
1170         if (reg == REG_C_0) {
1171                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1172                 uint32_t shl_c0 = rte_bsf32(msk_c0);
1173
1174                 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1175                 mask = rte_cpu_to_be_32(mask) & msk_c0;
1176                 mask = rte_cpu_to_be_32(mask << shl_c0);
1177         }
1178         reg_c_x[0].id = reg_to_field[reg];
1179         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1180                                              MLX5_MODIFICATION_TYPE_SET, error);
1181 }
1182
1183 /**
1184  * Get metadata register index for specified steering domain.
1185  *
1186  * @param[in] dev
1187  *   Pointer to the rte_eth_dev structure.
1188  * @param[in] attr
1189  *   Attributes of flow to determine steering domain.
1190  * @param[out] error
1191  *   Pointer to the error structure.
1192  *
1193  * @return
1194  *   positive index on success, a negative errno value otherwise
1195  *   and rte_errno is set.
1196  */
1197 static enum modify_reg
1198 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1199                          const struct rte_flow_attr *attr,
1200                          struct rte_flow_error *error)
1201 {
1202         int reg =
1203                 mlx5_flow_get_reg_id(dev, attr->transfer ?
1204                                           MLX5_METADATA_FDB :
1205                                             attr->egress ?
1206                                             MLX5_METADATA_TX :
1207                                             MLX5_METADATA_RX, 0, error);
1208         if (reg < 0)
1209                 return rte_flow_error_set(error,
1210                                           ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1211                                           NULL, "unavailable "
1212                                           "metadata register");
1213         return reg;
1214 }
1215
1216 /**
1217  * Convert SET_META action to DV specification.
1218  *
1219  * @param[in] dev
1220  *   Pointer to the rte_eth_dev structure.
1221  * @param[in,out] resource
1222  *   Pointer to the modify-header resource.
1223  * @param[in] attr
1224  *   Attributes of flow that includes this item.
1225  * @param[in] conf
1226  *   Pointer to action specification.
1227  * @param[out] error
1228  *   Pointer to the error structure.
1229  *
1230  * @return
1231  *   0 on success, a negative errno value otherwise and rte_errno is set.
1232  */
1233 static int
1234 flow_dv_convert_action_set_meta
1235                         (struct rte_eth_dev *dev,
1236                          struct mlx5_flow_dv_modify_hdr_resource *resource,
1237                          const struct rte_flow_attr *attr,
1238                          const struct rte_flow_action_set_meta *conf,
1239                          struct rte_flow_error *error)
1240 {
1241         uint32_t data = conf->data;
1242         uint32_t mask = conf->mask;
1243         struct rte_flow_item item = {
1244                 .spec = &data,
1245                 .mask = &mask,
1246         };
1247         struct field_modify_info reg_c_x[] = {
1248                 [1] = {0, 0, 0},
1249         };
1250         int reg = flow_dv_get_metadata_reg(dev, attr, error);
1251
1252         if (reg < 0)
1253                 return reg;
1254         /*
1255          * In datapath code there is no endianness
1256          * coversions for perfromance reasons, all
1257          * pattern conversions are done in rte_flow.
1258          */
1259         if (reg == REG_C_0) {
1260                 struct mlx5_priv *priv = dev->data->dev_private;
1261                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1262                 uint32_t shl_c0;
1263
1264                 MLX5_ASSERT(msk_c0);
1265 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1266                 shl_c0 = rte_bsf32(msk_c0);
1267 #else
1268                 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1269 #endif
1270                 mask <<= shl_c0;
1271                 data <<= shl_c0;
1272                 MLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1273         }
1274         reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1275         /* The routine expects parameters in memory as big-endian ones. */
1276         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1277                                              MLX5_MODIFICATION_TYPE_SET, error);
1278 }
1279
1280 /**
1281  * Convert modify-header set IPv4 DSCP action to DV specification.
1282  *
1283  * @param[in,out] resource
1284  *   Pointer to the modify-header resource.
1285  * @param[in] action
1286  *   Pointer to action specification.
1287  * @param[out] error
1288  *   Pointer to the error structure.
1289  *
1290  * @return
1291  *   0 on success, a negative errno value otherwise and rte_errno is set.
1292  */
1293 static int
1294 flow_dv_convert_action_modify_ipv4_dscp
1295                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1296                          const struct rte_flow_action *action,
1297                          struct rte_flow_error *error)
1298 {
1299         const struct rte_flow_action_set_dscp *conf =
1300                 (const struct rte_flow_action_set_dscp *)(action->conf);
1301         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1302         struct rte_flow_item_ipv4 ipv4;
1303         struct rte_flow_item_ipv4 ipv4_mask;
1304
1305         memset(&ipv4, 0, sizeof(ipv4));
1306         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1307         ipv4.hdr.type_of_service = conf->dscp;
1308         ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1309         item.spec = &ipv4;
1310         item.mask = &ipv4_mask;
1311         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1312                                              MLX5_MODIFICATION_TYPE_SET, error);
1313 }
1314
1315 /**
1316  * Convert modify-header set IPv6 DSCP action to DV specification.
1317  *
1318  * @param[in,out] resource
1319  *   Pointer to the modify-header resource.
1320  * @param[in] action
1321  *   Pointer to action specification.
1322  * @param[out] error
1323  *   Pointer to the error structure.
1324  *
1325  * @return
1326  *   0 on success, a negative errno value otherwise and rte_errno is set.
1327  */
1328 static int
1329 flow_dv_convert_action_modify_ipv6_dscp
1330                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1331                          const struct rte_flow_action *action,
1332                          struct rte_flow_error *error)
1333 {
1334         const struct rte_flow_action_set_dscp *conf =
1335                 (const struct rte_flow_action_set_dscp *)(action->conf);
1336         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1337         struct rte_flow_item_ipv6 ipv6;
1338         struct rte_flow_item_ipv6 ipv6_mask;
1339
1340         memset(&ipv6, 0, sizeof(ipv6));
1341         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1342         /*
1343          * Even though the DSCP bits offset of IPv6 is not byte aligned,
1344          * rdma-core only accept the DSCP bits byte aligned start from
1345          * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1346          * bits in IPv6 case as rdma-core requires byte aligned value.
1347          */
1348         ipv6.hdr.vtc_flow = conf->dscp;
1349         ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1350         item.spec = &ipv6;
1351         item.mask = &ipv6_mask;
1352         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1353                                              MLX5_MODIFICATION_TYPE_SET, error);
1354 }
1355
1356 /**
1357  * Validate MARK item.
1358  *
1359  * @param[in] dev
1360  *   Pointer to the rte_eth_dev structure.
1361  * @param[in] item
1362  *   Item specification.
1363  * @param[in] attr
1364  *   Attributes of flow that includes this item.
1365  * @param[out] error
1366  *   Pointer to error structure.
1367  *
1368  * @return
1369  *   0 on success, a negative errno value otherwise and rte_errno is set.
1370  */
1371 static int
1372 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1373                            const struct rte_flow_item *item,
1374                            const struct rte_flow_attr *attr __rte_unused,
1375                            struct rte_flow_error *error)
1376 {
1377         struct mlx5_priv *priv = dev->data->dev_private;
1378         struct mlx5_dev_config *config = &priv->config;
1379         const struct rte_flow_item_mark *spec = item->spec;
1380         const struct rte_flow_item_mark *mask = item->mask;
1381         const struct rte_flow_item_mark nic_mask = {
1382                 .id = priv->sh->dv_mark_mask,
1383         };
1384         int ret;
1385
1386         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1387                 return rte_flow_error_set(error, ENOTSUP,
1388                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1389                                           "extended metadata feature"
1390                                           " isn't enabled");
1391         if (!mlx5_flow_ext_mreg_supported(dev))
1392                 return rte_flow_error_set(error, ENOTSUP,
1393                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1394                                           "extended metadata register"
1395                                           " isn't supported");
1396         if (!nic_mask.id)
1397                 return rte_flow_error_set(error, ENOTSUP,
1398                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1399                                           "extended metadata register"
1400                                           " isn't available");
1401         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1402         if (ret < 0)
1403                 return ret;
1404         if (!spec)
1405                 return rte_flow_error_set(error, EINVAL,
1406                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1407                                           item->spec,
1408                                           "data cannot be empty");
1409         if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1410                 return rte_flow_error_set(error, EINVAL,
1411                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1412                                           &spec->id,
1413                                           "mark id exceeds the limit");
1414         if (!mask)
1415                 mask = &nic_mask;
1416         if (!mask->id)
1417                 return rte_flow_error_set(error, EINVAL,
1418                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1419                                         "mask cannot be zero");
1420
1421         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1422                                         (const uint8_t *)&nic_mask,
1423                                         sizeof(struct rte_flow_item_mark),
1424                                         error);
1425         if (ret < 0)
1426                 return ret;
1427         return 0;
1428 }
1429
1430 /**
1431  * Validate META item.
1432  *
1433  * @param[in] dev
1434  *   Pointer to the rte_eth_dev structure.
1435  * @param[in] item
1436  *   Item specification.
1437  * @param[in] attr
1438  *   Attributes of flow that includes this item.
1439  * @param[out] error
1440  *   Pointer to error structure.
1441  *
1442  * @return
1443  *   0 on success, a negative errno value otherwise and rte_errno is set.
1444  */
1445 static int
1446 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1447                            const struct rte_flow_item *item,
1448                            const struct rte_flow_attr *attr,
1449                            struct rte_flow_error *error)
1450 {
1451         struct mlx5_priv *priv = dev->data->dev_private;
1452         struct mlx5_dev_config *config = &priv->config;
1453         const struct rte_flow_item_meta *spec = item->spec;
1454         const struct rte_flow_item_meta *mask = item->mask;
1455         struct rte_flow_item_meta nic_mask = {
1456                 .data = UINT32_MAX
1457         };
1458         int reg;
1459         int ret;
1460
1461         if (!spec)
1462                 return rte_flow_error_set(error, EINVAL,
1463                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1464                                           item->spec,
1465                                           "data cannot be empty");
1466         if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1467                 if (!mlx5_flow_ext_mreg_supported(dev))
1468                         return rte_flow_error_set(error, ENOTSUP,
1469                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1470                                           "extended metadata register"
1471                                           " isn't supported");
1472                 reg = flow_dv_get_metadata_reg(dev, attr, error);
1473                 if (reg < 0)
1474                         return reg;
1475                 if (reg == REG_B)
1476                         return rte_flow_error_set(error, ENOTSUP,
1477                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1478                                           "match on reg_b "
1479                                           "isn't supported");
1480                 if (reg != REG_A)
1481                         nic_mask.data = priv->sh->dv_meta_mask;
1482         }
1483         if (!mask)
1484                 mask = &rte_flow_item_meta_mask;
1485         if (!mask->data)
1486                 return rte_flow_error_set(error, EINVAL,
1487                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1488                                         "mask cannot be zero");
1489
1490         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1491                                         (const uint8_t *)&nic_mask,
1492                                         sizeof(struct rte_flow_item_meta),
1493                                         error);
1494         return ret;
1495 }
1496
1497 /**
1498  * Validate TAG item.
1499  *
1500  * @param[in] dev
1501  *   Pointer to the rte_eth_dev structure.
1502  * @param[in] item
1503  *   Item specification.
1504  * @param[in] attr
1505  *   Attributes of flow that includes this item.
1506  * @param[out] error
1507  *   Pointer to error structure.
1508  *
1509  * @return
1510  *   0 on success, a negative errno value otherwise and rte_errno is set.
1511  */
1512 static int
1513 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
1514                           const struct rte_flow_item *item,
1515                           const struct rte_flow_attr *attr __rte_unused,
1516                           struct rte_flow_error *error)
1517 {
1518         const struct rte_flow_item_tag *spec = item->spec;
1519         const struct rte_flow_item_tag *mask = item->mask;
1520         const struct rte_flow_item_tag nic_mask = {
1521                 .data = RTE_BE32(UINT32_MAX),
1522                 .index = 0xff,
1523         };
1524         int ret;
1525
1526         if (!mlx5_flow_ext_mreg_supported(dev))
1527                 return rte_flow_error_set(error, ENOTSUP,
1528                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1529                                           "extensive metadata register"
1530                                           " isn't supported");
1531         if (!spec)
1532                 return rte_flow_error_set(error, EINVAL,
1533                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1534                                           item->spec,
1535                                           "data cannot be empty");
1536         if (!mask)
1537                 mask = &rte_flow_item_tag_mask;
1538         if (!mask->data)
1539                 return rte_flow_error_set(error, EINVAL,
1540                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1541                                         "mask cannot be zero");
1542
1543         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1544                                         (const uint8_t *)&nic_mask,
1545                                         sizeof(struct rte_flow_item_tag),
1546                                         error);
1547         if (ret < 0)
1548                 return ret;
1549         if (mask->index != 0xff)
1550                 return rte_flow_error_set(error, EINVAL,
1551                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1552                                           "partial mask for tag index"
1553                                           " is not supported");
1554         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
1555         if (ret < 0)
1556                 return ret;
1557         MLX5_ASSERT(ret != REG_NONE);
1558         return 0;
1559 }
1560
1561 /**
1562  * Validate vport item.
1563  *
1564  * @param[in] dev
1565  *   Pointer to the rte_eth_dev structure.
1566  * @param[in] item
1567  *   Item specification.
1568  * @param[in] attr
1569  *   Attributes of flow that includes this item.
1570  * @param[in] item_flags
1571  *   Bit-fields that holds the items detected until now.
1572  * @param[out] error
1573  *   Pointer to error structure.
1574  *
1575  * @return
1576  *   0 on success, a negative errno value otherwise and rte_errno is set.
1577  */
1578 static int
1579 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
1580                               const struct rte_flow_item *item,
1581                               const struct rte_flow_attr *attr,
1582                               uint64_t item_flags,
1583                               struct rte_flow_error *error)
1584 {
1585         const struct rte_flow_item_port_id *spec = item->spec;
1586         const struct rte_flow_item_port_id *mask = item->mask;
1587         const struct rte_flow_item_port_id switch_mask = {
1588                         .id = 0xffffffff,
1589         };
1590         struct mlx5_priv *esw_priv;
1591         struct mlx5_priv *dev_priv;
1592         int ret;
1593
1594         if (!attr->transfer)
1595                 return rte_flow_error_set(error, EINVAL,
1596                                           RTE_FLOW_ERROR_TYPE_ITEM,
1597                                           NULL,
1598                                           "match on port id is valid only"
1599                                           " when transfer flag is enabled");
1600         if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
1601                 return rte_flow_error_set(error, ENOTSUP,
1602                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1603                                           "multiple source ports are not"
1604                                           " supported");
1605         if (!mask)
1606                 mask = &switch_mask;
1607         if (mask->id != 0xffffffff)
1608                 return rte_flow_error_set(error, ENOTSUP,
1609                                            RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1610                                            mask,
1611                                            "no support for partial mask on"
1612                                            " \"id\" field");
1613         ret = mlx5_flow_item_acceptable
1614                                 (item, (const uint8_t *)mask,
1615                                  (const uint8_t *)&rte_flow_item_port_id_mask,
1616                                  sizeof(struct rte_flow_item_port_id),
1617                                  error);
1618         if (ret)
1619                 return ret;
1620         if (!spec)
1621                 return 0;
1622         esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
1623         if (!esw_priv)
1624                 return rte_flow_error_set(error, rte_errno,
1625                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1626                                           "failed to obtain E-Switch info for"
1627                                           " port");
1628         dev_priv = mlx5_dev_to_eswitch_info(dev);
1629         if (!dev_priv)
1630                 return rte_flow_error_set(error, rte_errno,
1631                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1632                                           NULL,
1633                                           "failed to obtain E-Switch info");
1634         if (esw_priv->domain_id != dev_priv->domain_id)
1635                 return rte_flow_error_set(error, EINVAL,
1636                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1637                                           "cannot match on a port from a"
1638                                           " different E-Switch");
1639         return 0;
1640 }
1641
1642 /*
1643  * GTP flags are contained in 1 byte of the format:
1644  * -------------------------------------------
1645  * | bit   | 0 - 2   | 3  | 4   | 5 | 6 | 7  |
1646  * |-----------------------------------------|
1647  * | value | Version | PT | Res | E | S | PN |
1648  * -------------------------------------------
1649  *
1650  * Matching is supported only for GTP flags E, S, PN.
1651  */
1652 #define MLX5_GTP_FLAGS_MASK     0x07
1653
1654 /**
1655  * Validate VLAN item.
1656  *
1657  * @param[in] item
1658  *   Item specification.
1659  * @param[in] item_flags
1660  *   Bit-fields that holds the items detected until now.
1661  * @param[in] dev
1662  *   Ethernet device flow is being created on.
1663  * @param[out] error
1664  *   Pointer to error structure.
1665  *
1666  * @return
1667  *   0 on success, a negative errno value otherwise and rte_errno is set.
1668  */
1669 static int
1670 flow_dv_validate_item_vlan(const struct rte_flow_item *item,
1671                            uint64_t item_flags,
1672                            struct rte_eth_dev *dev,
1673                            struct rte_flow_error *error)
1674 {
1675         const struct rte_flow_item_vlan *mask = item->mask;
1676         const struct rte_flow_item_vlan nic_mask = {
1677                 .tci = RTE_BE16(UINT16_MAX),
1678                 .inner_type = RTE_BE16(UINT16_MAX),
1679         };
1680         const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
1681         int ret;
1682         const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 |
1683                                         MLX5_FLOW_LAYER_INNER_L4) :
1684                                        (MLX5_FLOW_LAYER_OUTER_L3 |
1685                                         MLX5_FLOW_LAYER_OUTER_L4);
1686         const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
1687                                         MLX5_FLOW_LAYER_OUTER_VLAN;
1688
1689         if (item_flags & vlanm)
1690                 return rte_flow_error_set(error, EINVAL,
1691                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1692                                           "multiple VLAN layers not supported");
1693         else if ((item_flags & l34m) != 0)
1694                 return rte_flow_error_set(error, EINVAL,
1695                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1696                                           "VLAN cannot follow L3/L4 layer");
1697         if (!mask)
1698                 mask = &rte_flow_item_vlan_mask;
1699         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1700                                         (const uint8_t *)&nic_mask,
1701                                         sizeof(struct rte_flow_item_vlan),
1702                                         error);
1703         if (ret)
1704                 return ret;
1705         if (!tunnel && mask->tci != RTE_BE16(0x0fff)) {
1706                 struct mlx5_priv *priv = dev->data->dev_private;
1707
1708                 if (priv->vmwa_context) {
1709                         /*
1710                          * Non-NULL context means we have a virtual machine
1711                          * and SR-IOV enabled, we have to create VLAN interface
1712                          * to make hypervisor to setup E-Switch vport
1713                          * context correctly. We avoid creating the multiple
1714                          * VLAN interfaces, so we cannot support VLAN tag mask.
1715                          */
1716                         return rte_flow_error_set(error, EINVAL,
1717                                                   RTE_FLOW_ERROR_TYPE_ITEM,
1718                                                   item,
1719                                                   "VLAN tag mask is not"
1720                                                   " supported in virtual"
1721                                                   " environment");
1722                 }
1723         }
1724         return 0;
1725 }
1726
1727 /**
1728  * Validate GTP item.
1729  *
1730  * @param[in] dev
1731  *   Pointer to the rte_eth_dev structure.
1732  * @param[in] item
1733  *   Item specification.
1734  * @param[in] item_flags
1735  *   Bit-fields that holds the items detected until now.
1736  * @param[out] error
1737  *   Pointer to error structure.
1738  *
1739  * @return
1740  *   0 on success, a negative errno value otherwise and rte_errno is set.
1741  */
1742 static int
1743 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
1744                           const struct rte_flow_item *item,
1745                           uint64_t item_flags,
1746                           struct rte_flow_error *error)
1747 {
1748         struct mlx5_priv *priv = dev->data->dev_private;
1749         const struct rte_flow_item_gtp *spec = item->spec;
1750         const struct rte_flow_item_gtp *mask = item->mask;
1751         const struct rte_flow_item_gtp nic_mask = {
1752                 .v_pt_rsv_flags = MLX5_GTP_FLAGS_MASK,
1753                 .msg_type = 0xff,
1754                 .teid = RTE_BE32(0xffffffff),
1755         };
1756
1757         if (!priv->config.hca_attr.tunnel_stateless_gtp)
1758                 return rte_flow_error_set(error, ENOTSUP,
1759                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1760                                           "GTP support is not enabled");
1761         if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
1762                 return rte_flow_error_set(error, ENOTSUP,
1763                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1764                                           "multiple tunnel layers not"
1765                                           " supported");
1766         if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
1767                 return rte_flow_error_set(error, EINVAL,
1768                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1769                                           "no outer UDP layer found");
1770         if (!mask)
1771                 mask = &rte_flow_item_gtp_mask;
1772         if (spec && spec->v_pt_rsv_flags & ~MLX5_GTP_FLAGS_MASK)
1773                 return rte_flow_error_set(error, ENOTSUP,
1774                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1775                                           "Match is supported for GTP"
1776                                           " flags only");
1777         return mlx5_flow_item_acceptable
1778                 (item, (const uint8_t *)mask,
1779                  (const uint8_t *)&nic_mask,
1780                  sizeof(struct rte_flow_item_gtp),
1781                  error);
1782 }
1783
1784 /**
1785  * Validate the pop VLAN action.
1786  *
1787  * @param[in] dev
1788  *   Pointer to the rte_eth_dev structure.
1789  * @param[in] action_flags
1790  *   Holds the actions detected until now.
1791  * @param[in] action
1792  *   Pointer to the pop vlan action.
1793  * @param[in] item_flags
1794  *   The items found in this flow rule.
1795  * @param[in] attr
1796  *   Pointer to flow attributes.
1797  * @param[out] error
1798  *   Pointer to error structure.
1799  *
1800  * @return
1801  *   0 on success, a negative errno value otherwise and rte_errno is set.
1802  */
1803 static int
1804 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
1805                                  uint64_t action_flags,
1806                                  const struct rte_flow_action *action,
1807                                  uint64_t item_flags,
1808                                  const struct rte_flow_attr *attr,
1809                                  struct rte_flow_error *error)
1810 {
1811         const struct mlx5_priv *priv = dev->data->dev_private;
1812
1813         (void)action;
1814         (void)attr;
1815         if (!priv->sh->pop_vlan_action)
1816                 return rte_flow_error_set(error, ENOTSUP,
1817                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1818                                           NULL,
1819                                           "pop vlan action is not supported");
1820         if (attr->egress)
1821                 return rte_flow_error_set(error, ENOTSUP,
1822                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1823                                           NULL,
1824                                           "pop vlan action not supported for "
1825                                           "egress");
1826         if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
1827                 return rte_flow_error_set(error, ENOTSUP,
1828                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1829                                           "no support for multiple VLAN "
1830                                           "actions");
1831         if (!(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1832                 return rte_flow_error_set(error, ENOTSUP,
1833                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1834                                           NULL,
1835                                           "cannot pop vlan without a "
1836                                           "match on (outer) vlan in the flow");
1837         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1838                 return rte_flow_error_set(error, EINVAL,
1839                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1840                                           "wrong action order, port_id should "
1841                                           "be after pop VLAN action");
1842         if (!attr->transfer && priv->representor)
1843                 return rte_flow_error_set(error, ENOTSUP,
1844                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1845                                           "pop vlan action for VF representor "
1846                                           "not supported on NIC table");
1847         return 0;
1848 }
1849
1850 /**
1851  * Get VLAN default info from vlan match info.
1852  *
1853  * @param[in] items
1854  *   the list of item specifications.
1855  * @param[out] vlan
1856  *   pointer VLAN info to fill to.
1857  *
1858  * @return
1859  *   0 on success, a negative errno value otherwise and rte_errno is set.
1860  */
1861 static void
1862 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
1863                                   struct rte_vlan_hdr *vlan)
1864 {
1865         const struct rte_flow_item_vlan nic_mask = {
1866                 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
1867                                 MLX5DV_FLOW_VLAN_VID_MASK),
1868                 .inner_type = RTE_BE16(0xffff),
1869         };
1870
1871         if (items == NULL)
1872                 return;
1873         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
1874                 int type = items->type;
1875
1876                 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
1877                     type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
1878                         break;
1879         }
1880         if (items->type != RTE_FLOW_ITEM_TYPE_END) {
1881                 const struct rte_flow_item_vlan *vlan_m = items->mask;
1882                 const struct rte_flow_item_vlan *vlan_v = items->spec;
1883
1884                 if (!vlan_m)
1885                         vlan_m = &nic_mask;
1886                 /* Only full match values are accepted */
1887                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
1888                      MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
1889                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
1890                         vlan->vlan_tci |=
1891                                 rte_be_to_cpu_16(vlan_v->tci &
1892                                                  MLX5DV_FLOW_VLAN_PCP_MASK_BE);
1893                 }
1894                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
1895                      MLX5DV_FLOW_VLAN_VID_MASK_BE) {
1896                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
1897                         vlan->vlan_tci |=
1898                                 rte_be_to_cpu_16(vlan_v->tci &
1899                                                  MLX5DV_FLOW_VLAN_VID_MASK_BE);
1900                 }
1901                 if (vlan_m->inner_type == nic_mask.inner_type)
1902                         vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
1903                                                            vlan_m->inner_type);
1904         }
1905 }
1906
1907 /**
1908  * Validate the push VLAN action.
1909  *
1910  * @param[in] dev
1911  *   Pointer to the rte_eth_dev structure.
1912  * @param[in] action_flags
1913  *   Holds the actions detected until now.
1914  * @param[in] item_flags
1915  *   The items found in this flow rule.
1916  * @param[in] action
1917  *   Pointer to the action structure.
1918  * @param[in] attr
1919  *   Pointer to flow attributes
1920  * @param[out] error
1921  *   Pointer to error structure.
1922  *
1923  * @return
1924  *   0 on success, a negative errno value otherwise and rte_errno is set.
1925  */
1926 static int
1927 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
1928                                   uint64_t action_flags,
1929                                   const struct rte_flow_item_vlan *vlan_m,
1930                                   const struct rte_flow_action *action,
1931                                   const struct rte_flow_attr *attr,
1932                                   struct rte_flow_error *error)
1933 {
1934         const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
1935         const struct mlx5_priv *priv = dev->data->dev_private;
1936
1937         if (!attr->transfer && attr->ingress)
1938                 return rte_flow_error_set(error, ENOTSUP,
1939                                           RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1940                                           NULL,
1941                                           "push VLAN action not supported for "
1942                                           "ingress");
1943         if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
1944             push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
1945                 return rte_flow_error_set(error, EINVAL,
1946                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1947                                           "invalid vlan ethertype");
1948         if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
1949                 return rte_flow_error_set(error, ENOTSUP,
1950                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1951                                           "no support for multiple VLAN "
1952                                           "actions");
1953         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1954                 return rte_flow_error_set(error, EINVAL,
1955                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1956                                           "wrong action order, port_id should "
1957                                           "be after push VLAN");
1958         if (!attr->transfer && priv->representor)
1959                 return rte_flow_error_set(error, ENOTSUP,
1960                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1961                                           "push vlan action for VF representor "
1962                                           "not supported on NIC table");
1963         if (vlan_m &&
1964             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
1965             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
1966                 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
1967             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
1968             !(mlx5_flow_find_action
1969                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
1970                 return rte_flow_error_set(error, EINVAL,
1971                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1972                                           "not full match mask on VLAN PCP and "
1973                                           "there is no of_set_vlan_pcp action, "
1974                                           "push VLAN action cannot figure out "
1975                                           "PCP value");
1976         if (vlan_m &&
1977             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
1978             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
1979                 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
1980             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
1981             !(mlx5_flow_find_action
1982                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
1983                 return rte_flow_error_set(error, EINVAL,
1984                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1985                                           "not full match mask on VLAN VID and "
1986                                           "there is no of_set_vlan_vid action, "
1987                                           "push VLAN action cannot figure out "
1988                                           "VID value");
1989         (void)attr;
1990         return 0;
1991 }
1992
1993 /**
1994  * Validate the set VLAN PCP.
1995  *
1996  * @param[in] action_flags
1997  *   Holds the actions detected until now.
1998  * @param[in] actions
1999  *   Pointer to the list of actions remaining in the flow rule.
2000  * @param[out] error
2001  *   Pointer to error structure.
2002  *
2003  * @return
2004  *   0 on success, a negative errno value otherwise and rte_errno is set.
2005  */
2006 static int
2007 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
2008                                      const struct rte_flow_action actions[],
2009                                      struct rte_flow_error *error)
2010 {
2011         const struct rte_flow_action *action = actions;
2012         const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
2013
2014         if (conf->vlan_pcp > 7)
2015                 return rte_flow_error_set(error, EINVAL,
2016                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2017                                           "VLAN PCP value is too big");
2018         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
2019                 return rte_flow_error_set(error, ENOTSUP,
2020                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2021                                           "set VLAN PCP action must follow "
2022                                           "the push VLAN action");
2023         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
2024                 return rte_flow_error_set(error, ENOTSUP,
2025                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2026                                           "Multiple VLAN PCP modification are "
2027                                           "not supported");
2028         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2029                 return rte_flow_error_set(error, EINVAL,
2030                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2031                                           "wrong action order, port_id should "
2032                                           "be after set VLAN PCP");
2033         return 0;
2034 }
2035
2036 /**
2037  * Validate the set VLAN VID.
2038  *
2039  * @param[in] item_flags
2040  *   Holds the items detected in this rule.
2041  * @param[in] action_flags
2042  *   Holds the actions detected until now.
2043  * @param[in] actions
2044  *   Pointer to the list of actions remaining in the flow rule.
2045  * @param[out] error
2046  *   Pointer to error structure.
2047  *
2048  * @return
2049  *   0 on success, a negative errno value otherwise and rte_errno is set.
2050  */
2051 static int
2052 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
2053                                      uint64_t action_flags,
2054                                      const struct rte_flow_action actions[],
2055                                      struct rte_flow_error *error)
2056 {
2057         const struct rte_flow_action *action = actions;
2058         const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
2059
2060         if (rte_be_to_cpu_16(conf->vlan_vid) > 0xFFE)
2061                 return rte_flow_error_set(error, EINVAL,
2062                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2063                                           "VLAN VID value is too big");
2064         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
2065             !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2066                 return rte_flow_error_set(error, ENOTSUP,
2067                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2068                                           "set VLAN VID action must follow push"
2069                                           " VLAN action or match on VLAN item");
2070         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
2071                 return rte_flow_error_set(error, ENOTSUP,
2072                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2073                                           "Multiple VLAN VID modifications are "
2074                                           "not supported");
2075         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2076                 return rte_flow_error_set(error, EINVAL,
2077                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2078                                           "wrong action order, port_id should "
2079                                           "be after set VLAN VID");
2080         return 0;
2081 }
2082
2083 /*
2084  * Validate the FLAG action.
2085  *
2086  * @param[in] dev
2087  *   Pointer to the rte_eth_dev structure.
2088  * @param[in] action_flags
2089  *   Holds the actions detected until now.
2090  * @param[in] attr
2091  *   Pointer to flow attributes
2092  * @param[out] error
2093  *   Pointer to error structure.
2094  *
2095  * @return
2096  *   0 on success, a negative errno value otherwise and rte_errno is set.
2097  */
2098 static int
2099 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
2100                              uint64_t action_flags,
2101                              const struct rte_flow_attr *attr,
2102                              struct rte_flow_error *error)
2103 {
2104         struct mlx5_priv *priv = dev->data->dev_private;
2105         struct mlx5_dev_config *config = &priv->config;
2106         int ret;
2107
2108         /* Fall back if no extended metadata register support. */
2109         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2110                 return mlx5_flow_validate_action_flag(action_flags, attr,
2111                                                       error);
2112         /* Extensive metadata mode requires registers. */
2113         if (!mlx5_flow_ext_mreg_supported(dev))
2114                 return rte_flow_error_set(error, ENOTSUP,
2115                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2116                                           "no metadata registers "
2117                                           "to support flag action");
2118         if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
2119                 return rte_flow_error_set(error, ENOTSUP,
2120                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2121                                           "extended metadata register"
2122                                           " isn't available");
2123         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2124         if (ret < 0)
2125                 return ret;
2126         MLX5_ASSERT(ret > 0);
2127         if (action_flags & MLX5_FLOW_ACTION_MARK)
2128                 return rte_flow_error_set(error, EINVAL,
2129                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2130                                           "can't mark and flag in same flow");
2131         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2132                 return rte_flow_error_set(error, EINVAL,
2133                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2134                                           "can't have 2 flag"
2135                                           " actions in same flow");
2136         return 0;
2137 }
2138
2139 /**
2140  * Validate MARK action.
2141  *
2142  * @param[in] dev
2143  *   Pointer to the rte_eth_dev structure.
2144  * @param[in] action
2145  *   Pointer to action.
2146  * @param[in] action_flags
2147  *   Holds the actions detected until now.
2148  * @param[in] attr
2149  *   Pointer to flow attributes
2150  * @param[out] error
2151  *   Pointer to error structure.
2152  *
2153  * @return
2154  *   0 on success, a negative errno value otherwise and rte_errno is set.
2155  */
2156 static int
2157 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
2158                              const struct rte_flow_action *action,
2159                              uint64_t action_flags,
2160                              const struct rte_flow_attr *attr,
2161                              struct rte_flow_error *error)
2162 {
2163         struct mlx5_priv *priv = dev->data->dev_private;
2164         struct mlx5_dev_config *config = &priv->config;
2165         const struct rte_flow_action_mark *mark = action->conf;
2166         int ret;
2167
2168         /* Fall back if no extended metadata register support. */
2169         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2170                 return mlx5_flow_validate_action_mark(action, action_flags,
2171                                                       attr, error);
2172         /* Extensive metadata mode requires registers. */
2173         if (!mlx5_flow_ext_mreg_supported(dev))
2174                 return rte_flow_error_set(error, ENOTSUP,
2175                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2176                                           "no metadata registers "
2177                                           "to support mark action");
2178         if (!priv->sh->dv_mark_mask)
2179                 return rte_flow_error_set(error, ENOTSUP,
2180                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2181                                           "extended metadata register"
2182                                           " isn't available");
2183         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2184         if (ret < 0)
2185                 return ret;
2186         MLX5_ASSERT(ret > 0);
2187         if (!mark)
2188                 return rte_flow_error_set(error, EINVAL,
2189                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2190                                           "configuration cannot be null");
2191         if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
2192                 return rte_flow_error_set(error, EINVAL,
2193                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2194                                           &mark->id,
2195                                           "mark id exceeds the limit");
2196         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2197                 return rte_flow_error_set(error, EINVAL,
2198                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2199                                           "can't flag and mark in same flow");
2200         if (action_flags & MLX5_FLOW_ACTION_MARK)
2201                 return rte_flow_error_set(error, EINVAL,
2202                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2203                                           "can't have 2 mark actions in same"
2204                                           " flow");
2205         return 0;
2206 }
2207
2208 /**
2209  * Validate SET_META action.
2210  *
2211  * @param[in] dev
2212  *   Pointer to the rte_eth_dev structure.
2213  * @param[in] action
2214  *   Pointer to the action structure.
2215  * @param[in] action_flags
2216  *   Holds the actions detected until now.
2217  * @param[in] attr
2218  *   Pointer to flow attributes
2219  * @param[out] error
2220  *   Pointer to error structure.
2221  *
2222  * @return
2223  *   0 on success, a negative errno value otherwise and rte_errno is set.
2224  */
2225 static int
2226 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
2227                                  const struct rte_flow_action *action,
2228                                  uint64_t action_flags __rte_unused,
2229                                  const struct rte_flow_attr *attr,
2230                                  struct rte_flow_error *error)
2231 {
2232         const struct rte_flow_action_set_meta *conf;
2233         uint32_t nic_mask = UINT32_MAX;
2234         int reg;
2235
2236         if (!mlx5_flow_ext_mreg_supported(dev))
2237                 return rte_flow_error_set(error, ENOTSUP,
2238                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2239                                           "extended metadata register"
2240                                           " isn't supported");
2241         reg = flow_dv_get_metadata_reg(dev, attr, error);
2242         if (reg < 0)
2243                 return reg;
2244         if (reg != REG_A && reg != REG_B) {
2245                 struct mlx5_priv *priv = dev->data->dev_private;
2246
2247                 nic_mask = priv->sh->dv_meta_mask;
2248         }
2249         if (!(action->conf))
2250                 return rte_flow_error_set(error, EINVAL,
2251                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2252                                           "configuration cannot be null");
2253         conf = (const struct rte_flow_action_set_meta *)action->conf;
2254         if (!conf->mask)
2255                 return rte_flow_error_set(error, EINVAL,
2256                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2257                                           "zero mask doesn't have any effect");
2258         if (conf->mask & ~nic_mask)
2259                 return rte_flow_error_set(error, EINVAL,
2260                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2261                                           "meta data must be within reg C0");
2262         return 0;
2263 }
2264
2265 /**
2266  * Validate SET_TAG action.
2267  *
2268  * @param[in] dev
2269  *   Pointer to the rte_eth_dev structure.
2270  * @param[in] action
2271  *   Pointer to the action structure.
2272  * @param[in] action_flags
2273  *   Holds the actions detected until now.
2274  * @param[in] attr
2275  *   Pointer to flow attributes
2276  * @param[out] error
2277  *   Pointer to error structure.
2278  *
2279  * @return
2280  *   0 on success, a negative errno value otherwise and rte_errno is set.
2281  */
2282 static int
2283 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
2284                                 const struct rte_flow_action *action,
2285                                 uint64_t action_flags,
2286                                 const struct rte_flow_attr *attr,
2287                                 struct rte_flow_error *error)
2288 {
2289         const struct rte_flow_action_set_tag *conf;
2290         const uint64_t terminal_action_flags =
2291                 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
2292                 MLX5_FLOW_ACTION_RSS;
2293         int ret;
2294
2295         if (!mlx5_flow_ext_mreg_supported(dev))
2296                 return rte_flow_error_set(error, ENOTSUP,
2297                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2298                                           "extensive metadata register"
2299                                           " isn't supported");
2300         if (!(action->conf))
2301                 return rte_flow_error_set(error, EINVAL,
2302                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2303                                           "configuration cannot be null");
2304         conf = (const struct rte_flow_action_set_tag *)action->conf;
2305         if (!conf->mask)
2306                 return rte_flow_error_set(error, EINVAL,
2307                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2308                                           "zero mask doesn't have any effect");
2309         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
2310         if (ret < 0)
2311                 return ret;
2312         if (!attr->transfer && attr->ingress &&
2313             (action_flags & terminal_action_flags))
2314                 return rte_flow_error_set(error, EINVAL,
2315                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2316                                           "set_tag has no effect"
2317                                           " with terminal actions");
2318         return 0;
2319 }
2320
2321 /**
2322  * Validate count action.
2323  *
2324  * @param[in] dev
2325  *   Pointer to rte_eth_dev structure.
2326  * @param[out] error
2327  *   Pointer to error structure.
2328  *
2329  * @return
2330  *   0 on success, a negative errno value otherwise and rte_errno is set.
2331  */
2332 static int
2333 flow_dv_validate_action_count(struct rte_eth_dev *dev,
2334                               struct rte_flow_error *error)
2335 {
2336         struct mlx5_priv *priv = dev->data->dev_private;
2337
2338         if (!priv->config.devx)
2339                 goto notsup_err;
2340 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
2341         return 0;
2342 #endif
2343 notsup_err:
2344         return rte_flow_error_set
2345                       (error, ENOTSUP,
2346                        RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2347                        NULL,
2348                        "count action not supported");
2349 }
2350
2351 /**
2352  * Validate the L2 encap action.
2353  *
2354  * @param[in] dev
2355  *   Pointer to the rte_eth_dev structure.
2356  * @param[in] action_flags
2357  *   Holds the actions detected until now.
2358  * @param[in] action
2359  *   Pointer to the action structure.
2360  * @param[in] attr
2361  *   Pointer to flow attributes.
2362  * @param[out] error
2363  *   Pointer to error structure.
2364  *
2365  * @return
2366  *   0 on success, a negative errno value otherwise and rte_errno is set.
2367  */
2368 static int
2369 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
2370                                  uint64_t action_flags,
2371                                  const struct rte_flow_action *action,
2372                                  const struct rte_flow_attr *attr,
2373                                  struct rte_flow_error *error)
2374 {
2375         const struct mlx5_priv *priv = dev->data->dev_private;
2376
2377         if (!(action->conf))
2378                 return rte_flow_error_set(error, EINVAL,
2379                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2380                                           "configuration cannot be null");
2381         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
2382                 return rte_flow_error_set(error, EINVAL,
2383                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2384                                           "can only have a single encap action "
2385                                           "in a flow");
2386         if (!attr->transfer && priv->representor)
2387                 return rte_flow_error_set(error, ENOTSUP,
2388                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2389                                           "encap action for VF representor "
2390                                           "not supported on NIC table");
2391         return 0;
2392 }
2393
2394 /**
2395  * Validate a decap action.
2396  *
2397  * @param[in] dev
2398  *   Pointer to the rte_eth_dev structure.
2399  * @param[in] action_flags
2400  *   Holds the actions detected until now.
2401  * @param[in] attr
2402  *   Pointer to flow attributes
2403  * @param[out] error
2404  *   Pointer to error structure.
2405  *
2406  * @return
2407  *   0 on success, a negative errno value otherwise and rte_errno is set.
2408  */
2409 static int
2410 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
2411                               uint64_t action_flags,
2412                               const struct rte_flow_attr *attr,
2413                               struct rte_flow_error *error)
2414 {
2415         const struct mlx5_priv *priv = dev->data->dev_private;
2416
2417         if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
2418                 return rte_flow_error_set(error, ENOTSUP,
2419                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2420                                           action_flags &
2421                                           MLX5_FLOW_ACTION_DECAP ? "can only "
2422                                           "have a single decap action" : "decap "
2423                                           "after encap is not supported");
2424         if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
2425                 return rte_flow_error_set(error, EINVAL,
2426                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2427                                           "can't have decap action after"
2428                                           " modify action");
2429         if (attr->egress)
2430                 return rte_flow_error_set(error, ENOTSUP,
2431                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2432                                           NULL,
2433                                           "decap action not supported for "
2434                                           "egress");
2435         if (!attr->transfer && priv->representor)
2436                 return rte_flow_error_set(error, ENOTSUP,
2437                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2438                                           "decap action for VF representor "
2439                                           "not supported on NIC table");
2440         return 0;
2441 }
2442
2443 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
2444
2445 /**
2446  * Validate the raw encap and decap actions.
2447  *
2448  * @param[in] dev
2449  *   Pointer to the rte_eth_dev structure.
2450  * @param[in] decap
2451  *   Pointer to the decap action.
2452  * @param[in] encap
2453  *   Pointer to the encap action.
2454  * @param[in] attr
2455  *   Pointer to flow attributes
2456  * @param[in/out] action_flags
2457  *   Holds the actions detected until now.
2458  * @param[out] actions_n
2459  *   pointer to the number of actions counter.
2460  * @param[out] error
2461  *   Pointer to error structure.
2462  *
2463  * @return
2464  *   0 on success, a negative errno value otherwise and rte_errno is set.
2465  */
2466 static int
2467 flow_dv_validate_action_raw_encap_decap
2468         (struct rte_eth_dev *dev,
2469          const struct rte_flow_action_raw_decap *decap,
2470          const struct rte_flow_action_raw_encap *encap,
2471          const struct rte_flow_attr *attr, uint64_t *action_flags,
2472          int *actions_n, struct rte_flow_error *error)
2473 {
2474         const struct mlx5_priv *priv = dev->data->dev_private;
2475         int ret;
2476
2477         if (encap && (!encap->size || !encap->data))
2478                 return rte_flow_error_set(error, EINVAL,
2479                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2480                                           "raw encap data cannot be empty");
2481         if (decap && encap) {
2482                 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
2483                     encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
2484                         /* L3 encap. */
2485                         decap = NULL;
2486                 else if (encap->size <=
2487                            MLX5_ENCAPSULATION_DECISION_SIZE &&
2488                            decap->size >
2489                            MLX5_ENCAPSULATION_DECISION_SIZE)
2490                         /* L3 decap. */
2491                         encap = NULL;
2492                 else if (encap->size >
2493                            MLX5_ENCAPSULATION_DECISION_SIZE &&
2494                            decap->size >
2495                            MLX5_ENCAPSULATION_DECISION_SIZE)
2496                         /* 2 L2 actions: encap and decap. */
2497                         ;
2498                 else
2499                         return rte_flow_error_set(error,
2500                                 ENOTSUP,
2501                                 RTE_FLOW_ERROR_TYPE_ACTION,
2502                                 NULL, "unsupported too small "
2503                                 "raw decap and too small raw "
2504                                 "encap combination");
2505         }
2506         if (decap) {
2507                 ret = flow_dv_validate_action_decap(dev, *action_flags, attr,
2508                                                     error);
2509                 if (ret < 0)
2510                         return ret;
2511                 *action_flags |= MLX5_FLOW_ACTION_DECAP;
2512                 ++(*actions_n);
2513         }
2514         if (encap) {
2515                 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
2516                         return rte_flow_error_set(error, ENOTSUP,
2517                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2518                                                   NULL,
2519                                                   "small raw encap size");
2520                 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
2521                         return rte_flow_error_set(error, EINVAL,
2522                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2523                                                   NULL,
2524                                                   "more than one encap action");
2525                 if (!attr->transfer && priv->representor)
2526                         return rte_flow_error_set
2527                                         (error, ENOTSUP,
2528                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2529                                          "encap action for VF representor "
2530                                          "not supported on NIC table");
2531                 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
2532                 ++(*actions_n);
2533         }
2534         return 0;
2535 }
2536
2537 /**
2538  * Find existing encap/decap resource or create and register a new one.
2539  *
2540  * @param[in, out] dev
2541  *   Pointer to rte_eth_dev structure.
2542  * @param[in, out] resource
2543  *   Pointer to encap/decap resource.
2544  * @parm[in, out] dev_flow
2545  *   Pointer to the dev_flow.
2546  * @param[out] error
2547  *   pointer to error structure.
2548  *
2549  * @return
2550  *   0 on success otherwise -errno and errno is set.
2551  */
2552 static int
2553 flow_dv_encap_decap_resource_register
2554                         (struct rte_eth_dev *dev,
2555                          struct mlx5_flow_dv_encap_decap_resource *resource,
2556                          struct mlx5_flow *dev_flow,
2557                          struct rte_flow_error *error)
2558 {
2559         struct mlx5_priv *priv = dev->data->dev_private;
2560         struct mlx5_ibv_shared *sh = priv->sh;
2561         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2562         struct mlx5dv_dr_domain *domain;
2563         uint32_t idx = 0;
2564
2565         resource->flags = dev_flow->dv.group ? 0 : 1;
2566         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2567                 domain = sh->fdb_domain;
2568         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2569                 domain = sh->rx_domain;
2570         else
2571                 domain = sh->tx_domain;
2572         /* Lookup a matching resource from cache. */
2573         ILIST_FOREACH(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], sh->encaps_decaps, idx,
2574                       cache_resource, next) {
2575                 if (resource->reformat_type == cache_resource->reformat_type &&
2576                     resource->ft_type == cache_resource->ft_type &&
2577                     resource->flags == cache_resource->flags &&
2578                     resource->size == cache_resource->size &&
2579                     !memcmp((const void *)resource->buf,
2580                             (const void *)cache_resource->buf,
2581                             resource->size)) {
2582                         DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d++",
2583                                 (void *)cache_resource,
2584                                 rte_atomic32_read(&cache_resource->refcnt));
2585                         rte_atomic32_inc(&cache_resource->refcnt);
2586                         dev_flow->handle->dvh.rix_encap_decap = idx;
2587                         dev_flow->dv.encap_decap = cache_resource;
2588                         return 0;
2589                 }
2590         }
2591         /* Register new encap/decap resource. */
2592         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
2593                                        &dev_flow->handle->dvh.rix_encap_decap);
2594         if (!cache_resource)
2595                 return rte_flow_error_set(error, ENOMEM,
2596                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2597                                           "cannot allocate resource memory");
2598         *cache_resource = *resource;
2599         cache_resource->verbs_action =
2600                 mlx5_glue->dv_create_flow_action_packet_reformat
2601                         (sh->ctx, cache_resource->reformat_type,
2602                          cache_resource->ft_type, domain, cache_resource->flags,
2603                          cache_resource->size,
2604                          (cache_resource->size ? cache_resource->buf : NULL));
2605         if (!cache_resource->verbs_action) {
2606                 rte_free(cache_resource);
2607                 return rte_flow_error_set(error, ENOMEM,
2608                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2609                                           NULL, "cannot create action");
2610         }
2611         rte_atomic32_init(&cache_resource->refcnt);
2612         rte_atomic32_inc(&cache_resource->refcnt);
2613         ILIST_INSERT(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], &sh->encaps_decaps,
2614                      dev_flow->handle->dvh.rix_encap_decap, cache_resource,
2615                      next);
2616         dev_flow->dv.encap_decap = cache_resource;
2617         DRV_LOG(DEBUG, "new encap/decap resource %p: refcnt %d++",
2618                 (void *)cache_resource,
2619                 rte_atomic32_read(&cache_resource->refcnt));
2620         return 0;
2621 }
2622
2623 /**
2624  * Find existing table jump resource or create and register a new one.
2625  *
2626  * @param[in, out] dev
2627  *   Pointer to rte_eth_dev structure.
2628  * @param[in, out] tbl
2629  *   Pointer to flow table resource.
2630  * @parm[in, out] dev_flow
2631  *   Pointer to the dev_flow.
2632  * @param[out] error
2633  *   pointer to error structure.
2634  *
2635  * @return
2636  *   0 on success otherwise -errno and errno is set.
2637  */
2638 static int
2639 flow_dv_jump_tbl_resource_register
2640                         (struct rte_eth_dev *dev __rte_unused,
2641                          struct mlx5_flow_tbl_resource *tbl,
2642                          struct mlx5_flow *dev_flow,
2643                          struct rte_flow_error *error)
2644 {
2645         struct mlx5_flow_tbl_data_entry *tbl_data =
2646                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
2647         int cnt;
2648
2649         MLX5_ASSERT(tbl);
2650         cnt = rte_atomic32_read(&tbl_data->jump.refcnt);
2651         if (!cnt) {
2652                 tbl_data->jump.action =
2653                         mlx5_glue->dr_create_flow_action_dest_flow_tbl
2654                         (tbl->obj);
2655                 if (!tbl_data->jump.action)
2656                         return rte_flow_error_set(error, ENOMEM,
2657                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2658                                         NULL, "cannot create jump action");
2659                 DRV_LOG(DEBUG, "new jump table resource %p: refcnt %d++",
2660                         (void *)&tbl_data->jump, cnt);
2661         } else {
2662                 /* old jump should not make the table ref++. */
2663                 flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
2664                 MLX5_ASSERT(tbl_data->jump.action);
2665                 DRV_LOG(DEBUG, "existed jump table resource %p: refcnt %d++",
2666                         (void *)&tbl_data->jump, cnt);
2667         }
2668         rte_atomic32_inc(&tbl_data->jump.refcnt);
2669         dev_flow->handle->rix_jump = tbl_data->idx;
2670         dev_flow->dv.jump = &tbl_data->jump;
2671         return 0;
2672 }
2673
2674 /**
2675  * Find existing table port ID resource or create and register a new one.
2676  *
2677  * @param[in, out] dev
2678  *   Pointer to rte_eth_dev structure.
2679  * @param[in, out] resource
2680  *   Pointer to port ID action resource.
2681  * @parm[in, out] dev_flow
2682  *   Pointer to the dev_flow.
2683  * @param[out] error
2684  *   pointer to error structure.
2685  *
2686  * @return
2687  *   0 on success otherwise -errno and errno is set.
2688  */
2689 static int
2690 flow_dv_port_id_action_resource_register
2691                         (struct rte_eth_dev *dev,
2692                          struct mlx5_flow_dv_port_id_action_resource *resource,
2693                          struct mlx5_flow *dev_flow,
2694                          struct rte_flow_error *error)
2695 {
2696         struct mlx5_priv *priv = dev->data->dev_private;
2697         struct mlx5_ibv_shared *sh = priv->sh;
2698         struct mlx5_flow_dv_port_id_action_resource *cache_resource;
2699         uint32_t idx = 0;
2700
2701         /* Lookup a matching resource from cache. */
2702         ILIST_FOREACH(sh->ipool[MLX5_IPOOL_PORT_ID], sh->port_id_action_list,
2703                       idx, cache_resource, next) {
2704                 if (resource->port_id == cache_resource->port_id) {
2705                         DRV_LOG(DEBUG, "port id action resource resource %p: "
2706                                 "refcnt %d++",
2707                                 (void *)cache_resource,
2708                                 rte_atomic32_read(&cache_resource->refcnt));
2709                         rte_atomic32_inc(&cache_resource->refcnt);
2710                         dev_flow->handle->rix_port_id_action = idx;
2711                         dev_flow->dv.port_id_action = cache_resource;
2712                         return 0;
2713                 }
2714         }
2715         /* Register new port id action resource. */
2716         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID],
2717                                        &dev_flow->handle->rix_port_id_action);
2718         if (!cache_resource)
2719                 return rte_flow_error_set(error, ENOMEM,
2720                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2721                                           "cannot allocate resource memory");
2722         *cache_resource = *resource;
2723         /*
2724          * Depending on rdma_core version the glue routine calls
2725          * either mlx5dv_dr_action_create_dest_ib_port(domain, ibv_port)
2726          * or mlx5dv_dr_action_create_dest_vport(domain, vport_id).
2727          */
2728         cache_resource->action =
2729                 mlx5_glue->dr_create_flow_action_dest_port
2730                         (priv->sh->fdb_domain, resource->port_id);
2731         if (!cache_resource->action) {
2732                 rte_free(cache_resource);
2733                 return rte_flow_error_set(error, ENOMEM,
2734                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2735                                           NULL, "cannot create action");
2736         }
2737         rte_atomic32_init(&cache_resource->refcnt);
2738         rte_atomic32_inc(&cache_resource->refcnt);
2739         ILIST_INSERT(sh->ipool[MLX5_IPOOL_PORT_ID], &sh->port_id_action_list,
2740                      dev_flow->handle->rix_port_id_action, cache_resource,
2741                      next);
2742         dev_flow->dv.port_id_action = cache_resource;
2743         DRV_LOG(DEBUG, "new port id action resource %p: refcnt %d++",
2744                 (void *)cache_resource,
2745                 rte_atomic32_read(&cache_resource->refcnt));
2746         return 0;
2747 }
2748
2749 /**
2750  * Find existing push vlan resource or create and register a new one.
2751  *
2752  * @param [in, out] dev
2753  *   Pointer to rte_eth_dev structure.
2754  * @param[in, out] resource
2755  *   Pointer to port ID action resource.
2756  * @parm[in, out] dev_flow
2757  *   Pointer to the dev_flow.
2758  * @param[out] error
2759  *   pointer to error structure.
2760  *
2761  * @return
2762  *   0 on success otherwise -errno and errno is set.
2763  */
2764 static int
2765 flow_dv_push_vlan_action_resource_register
2766                        (struct rte_eth_dev *dev,
2767                         struct mlx5_flow_dv_push_vlan_action_resource *resource,
2768                         struct mlx5_flow *dev_flow,
2769                         struct rte_flow_error *error)
2770 {
2771         struct mlx5_priv *priv = dev->data->dev_private;
2772         struct mlx5_ibv_shared *sh = priv->sh;
2773         struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
2774         struct mlx5dv_dr_domain *domain;
2775         uint32_t idx = 0;
2776
2777         /* Lookup a matching resource from cache. */
2778         ILIST_FOREACH(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2779                       sh->push_vlan_action_list, idx, cache_resource, next) {
2780                 if (resource->vlan_tag == cache_resource->vlan_tag &&
2781                     resource->ft_type == cache_resource->ft_type) {
2782                         DRV_LOG(DEBUG, "push-VLAN action resource resource %p: "
2783                                 "refcnt %d++",
2784                                 (void *)cache_resource,
2785                                 rte_atomic32_read(&cache_resource->refcnt));
2786                         rte_atomic32_inc(&cache_resource->refcnt);
2787                         dev_flow->handle->dvh.rix_push_vlan = idx;
2788                         dev_flow->dv.push_vlan_res = cache_resource;
2789                         return 0;
2790                 }
2791         }
2792         /* Register new push_vlan action resource. */
2793         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2794                                        &dev_flow->handle->dvh.rix_push_vlan);
2795         if (!cache_resource)
2796                 return rte_flow_error_set(error, ENOMEM,
2797                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2798                                           "cannot allocate resource memory");
2799         *cache_resource = *resource;
2800         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2801                 domain = sh->fdb_domain;
2802         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2803                 domain = sh->rx_domain;
2804         else
2805                 domain = sh->tx_domain;
2806         cache_resource->action =
2807                 mlx5_glue->dr_create_flow_action_push_vlan(domain,
2808                                                            resource->vlan_tag);
2809         if (!cache_resource->action) {
2810                 rte_free(cache_resource);
2811                 return rte_flow_error_set(error, ENOMEM,
2812                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2813                                           NULL, "cannot create action");
2814         }
2815         rte_atomic32_init(&cache_resource->refcnt);
2816         rte_atomic32_inc(&cache_resource->refcnt);
2817         ILIST_INSERT(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2818                      &sh->push_vlan_action_list,
2819                      dev_flow->handle->dvh.rix_push_vlan,
2820                      cache_resource, next);
2821         dev_flow->dv.push_vlan_res = cache_resource;
2822         DRV_LOG(DEBUG, "new push vlan action resource %p: refcnt %d++",
2823                 (void *)cache_resource,
2824                 rte_atomic32_read(&cache_resource->refcnt));
2825         return 0;
2826 }
2827 /**
2828  * Get the size of specific rte_flow_item_type
2829  *
2830  * @param[in] item_type
2831  *   Tested rte_flow_item_type.
2832  *
2833  * @return
2834  *   sizeof struct item_type, 0 if void or irrelevant.
2835  */
2836 static size_t
2837 flow_dv_get_item_len(const enum rte_flow_item_type item_type)
2838 {
2839         size_t retval;
2840
2841         switch (item_type) {
2842         case RTE_FLOW_ITEM_TYPE_ETH:
2843                 retval = sizeof(struct rte_flow_item_eth);
2844                 break;
2845         case RTE_FLOW_ITEM_TYPE_VLAN:
2846                 retval = sizeof(struct rte_flow_item_vlan);
2847                 break;
2848         case RTE_FLOW_ITEM_TYPE_IPV4:
2849                 retval = sizeof(struct rte_flow_item_ipv4);
2850                 break;
2851         case RTE_FLOW_ITEM_TYPE_IPV6:
2852                 retval = sizeof(struct rte_flow_item_ipv6);
2853                 break;
2854         case RTE_FLOW_ITEM_TYPE_UDP:
2855                 retval = sizeof(struct rte_flow_item_udp);
2856                 break;
2857         case RTE_FLOW_ITEM_TYPE_TCP:
2858                 retval = sizeof(struct rte_flow_item_tcp);
2859                 break;
2860         case RTE_FLOW_ITEM_TYPE_VXLAN:
2861                 retval = sizeof(struct rte_flow_item_vxlan);
2862                 break;
2863         case RTE_FLOW_ITEM_TYPE_GRE:
2864                 retval = sizeof(struct rte_flow_item_gre);
2865                 break;
2866         case RTE_FLOW_ITEM_TYPE_NVGRE:
2867                 retval = sizeof(struct rte_flow_item_nvgre);
2868                 break;
2869         case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2870                 retval = sizeof(struct rte_flow_item_vxlan_gpe);
2871                 break;
2872         case RTE_FLOW_ITEM_TYPE_MPLS:
2873                 retval = sizeof(struct rte_flow_item_mpls);
2874                 break;
2875         case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
2876         default:
2877                 retval = 0;
2878                 break;
2879         }
2880         return retval;
2881 }
2882
2883 #define MLX5_ENCAP_IPV4_VERSION         0x40
2884 #define MLX5_ENCAP_IPV4_IHL_MIN         0x05
2885 #define MLX5_ENCAP_IPV4_TTL_DEF         0x40
2886 #define MLX5_ENCAP_IPV6_VTC_FLOW        0x60000000
2887 #define MLX5_ENCAP_IPV6_HOP_LIMIT       0xff
2888 #define MLX5_ENCAP_VXLAN_FLAGS          0x08000000
2889 #define MLX5_ENCAP_VXLAN_GPE_FLAGS      0x04
2890
2891 /**
2892  * Convert the encap action data from list of rte_flow_item to raw buffer
2893  *
2894  * @param[in] items
2895  *   Pointer to rte_flow_item objects list.
2896  * @param[out] buf
2897  *   Pointer to the output buffer.
2898  * @param[out] size
2899  *   Pointer to the output buffer size.
2900  * @param[out] error
2901  *   Pointer to the error structure.
2902  *
2903  * @return
2904  *   0 on success, a negative errno value otherwise and rte_errno is set.
2905  */
2906 static int
2907 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
2908                            size_t *size, struct rte_flow_error *error)
2909 {
2910         struct rte_ether_hdr *eth = NULL;
2911         struct rte_vlan_hdr *vlan = NULL;
2912         struct rte_ipv4_hdr *ipv4 = NULL;
2913         struct rte_ipv6_hdr *ipv6 = NULL;
2914         struct rte_udp_hdr *udp = NULL;
2915         struct rte_vxlan_hdr *vxlan = NULL;
2916         struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
2917         struct rte_gre_hdr *gre = NULL;
2918         size_t len;
2919         size_t temp_size = 0;
2920
2921         if (!items)
2922                 return rte_flow_error_set(error, EINVAL,
2923                                           RTE_FLOW_ERROR_TYPE_ACTION,
2924                                           NULL, "invalid empty data");
2925         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2926                 len = flow_dv_get_item_len(items->type);
2927                 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
2928                         return rte_flow_error_set(error, EINVAL,
2929                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2930                                                   (void *)items->type,
2931                                                   "items total size is too big"
2932                                                   " for encap action");
2933                 rte_memcpy((void *)&buf[temp_size], items->spec, len);
2934                 switch (items->type) {
2935                 case RTE_FLOW_ITEM_TYPE_ETH:
2936                         eth = (struct rte_ether_hdr *)&buf[temp_size];
2937                         break;
2938                 case RTE_FLOW_ITEM_TYPE_VLAN:
2939                         vlan = (struct rte_vlan_hdr *)&buf[temp_size];
2940                         if (!eth)
2941                                 return rte_flow_error_set(error, EINVAL,
2942                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2943                                                 (void *)items->type,
2944                                                 "eth header not found");
2945                         if (!eth->ether_type)
2946                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
2947                         break;
2948                 case RTE_FLOW_ITEM_TYPE_IPV4:
2949                         ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
2950                         if (!vlan && !eth)
2951                                 return rte_flow_error_set(error, EINVAL,
2952                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2953                                                 (void *)items->type,
2954                                                 "neither eth nor vlan"
2955                                                 " header found");
2956                         if (vlan && !vlan->eth_proto)
2957                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2958                         else if (eth && !eth->ether_type)
2959                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2960                         if (!ipv4->version_ihl)
2961                                 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
2962                                                     MLX5_ENCAP_IPV4_IHL_MIN;
2963                         if (!ipv4->time_to_live)
2964                                 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
2965                         break;
2966                 case RTE_FLOW_ITEM_TYPE_IPV6:
2967                         ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
2968                         if (!vlan && !eth)
2969                                 return rte_flow_error_set(error, EINVAL,
2970                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2971                                                 (void *)items->type,
2972                                                 "neither eth nor vlan"
2973                                                 " header found");
2974                         if (vlan && !vlan->eth_proto)
2975                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2976                         else if (eth && !eth->ether_type)
2977                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2978                         if (!ipv6->vtc_flow)
2979                                 ipv6->vtc_flow =
2980                                         RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
2981                         if (!ipv6->hop_limits)
2982                                 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
2983                         break;
2984                 case RTE_FLOW_ITEM_TYPE_UDP:
2985                         udp = (struct rte_udp_hdr *)&buf[temp_size];
2986                         if (!ipv4 && !ipv6)
2987                                 return rte_flow_error_set(error, EINVAL,
2988                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2989                                                 (void *)items->type,
2990                                                 "ip header not found");
2991                         if (ipv4 && !ipv4->next_proto_id)
2992                                 ipv4->next_proto_id = IPPROTO_UDP;
2993                         else if (ipv6 && !ipv6->proto)
2994                                 ipv6->proto = IPPROTO_UDP;
2995                         break;
2996                 case RTE_FLOW_ITEM_TYPE_VXLAN:
2997                         vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
2998                         if (!udp)
2999                                 return rte_flow_error_set(error, EINVAL,
3000                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3001                                                 (void *)items->type,
3002                                                 "udp header not found");
3003                         if (!udp->dst_port)
3004                                 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
3005                         if (!vxlan->vx_flags)
3006                                 vxlan->vx_flags =
3007                                         RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
3008                         break;
3009                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3010                         vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
3011                         if (!udp)
3012                                 return rte_flow_error_set(error, EINVAL,
3013                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3014                                                 (void *)items->type,
3015                                                 "udp header not found");
3016                         if (!vxlan_gpe->proto)
3017                                 return rte_flow_error_set(error, EINVAL,
3018                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3019                                                 (void *)items->type,
3020                                                 "next protocol not found");
3021                         if (!udp->dst_port)
3022                                 udp->dst_port =
3023                                         RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
3024                         if (!vxlan_gpe->vx_flags)
3025                                 vxlan_gpe->vx_flags =
3026                                                 MLX5_ENCAP_VXLAN_GPE_FLAGS;
3027                         break;
3028                 case RTE_FLOW_ITEM_TYPE_GRE:
3029                 case RTE_FLOW_ITEM_TYPE_NVGRE:
3030                         gre = (struct rte_gre_hdr *)&buf[temp_size];
3031                         if (!gre->proto)
3032                                 return rte_flow_error_set(error, EINVAL,
3033                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3034                                                 (void *)items->type,
3035                                                 "next protocol not found");
3036                         if (!ipv4 && !ipv6)
3037                                 return rte_flow_error_set(error, EINVAL,
3038                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3039                                                 (void *)items->type,
3040                                                 "ip header not found");
3041                         if (ipv4 && !ipv4->next_proto_id)
3042                                 ipv4->next_proto_id = IPPROTO_GRE;
3043                         else if (ipv6 && !ipv6->proto)
3044                                 ipv6->proto = IPPROTO_GRE;
3045                         break;
3046                 case RTE_FLOW_ITEM_TYPE_VOID:
3047                         break;
3048                 default:
3049                         return rte_flow_error_set(error, EINVAL,
3050                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3051                                                   (void *)items->type,
3052                                                   "unsupported item type");
3053                         break;
3054                 }
3055                 temp_size += len;
3056         }
3057         *size = temp_size;
3058         return 0;
3059 }
3060
3061 static int
3062 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
3063 {
3064         struct rte_ether_hdr *eth = NULL;
3065         struct rte_vlan_hdr *vlan = NULL;
3066         struct rte_ipv6_hdr *ipv6 = NULL;
3067         struct rte_udp_hdr *udp = NULL;
3068         char *next_hdr;
3069         uint16_t proto;
3070
3071         eth = (struct rte_ether_hdr *)data;
3072         next_hdr = (char *)(eth + 1);
3073         proto = RTE_BE16(eth->ether_type);
3074
3075         /* VLAN skipping */
3076         while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
3077                 vlan = (struct rte_vlan_hdr *)next_hdr;
3078                 proto = RTE_BE16(vlan->eth_proto);
3079                 next_hdr += sizeof(struct rte_vlan_hdr);
3080         }
3081
3082         /* HW calculates IPv4 csum. no need to proceed */
3083         if (proto == RTE_ETHER_TYPE_IPV4)
3084                 return 0;
3085
3086         /* non IPv4/IPv6 header. not supported */
3087         if (proto != RTE_ETHER_TYPE_IPV6) {
3088                 return rte_flow_error_set(error, ENOTSUP,
3089                                           RTE_FLOW_ERROR_TYPE_ACTION,
3090                                           NULL, "Cannot offload non IPv4/IPv6");
3091         }
3092
3093         ipv6 = (struct rte_ipv6_hdr *)next_hdr;
3094
3095         /* ignore non UDP */
3096         if (ipv6->proto != IPPROTO_UDP)
3097                 return 0;
3098
3099         udp = (struct rte_udp_hdr *)(ipv6 + 1);
3100         udp->dgram_cksum = 0;
3101
3102         return 0;
3103 }
3104
3105 /**
3106  * Convert L2 encap action to DV specification.
3107  *
3108  * @param[in] dev
3109  *   Pointer to rte_eth_dev structure.
3110  * @param[in] action
3111  *   Pointer to action structure.
3112  * @param[in, out] dev_flow
3113  *   Pointer to the mlx5_flow.
3114  * @param[in] transfer
3115  *   Mark if the flow is E-Switch flow.
3116  * @param[out] error
3117  *   Pointer to the error structure.
3118  *
3119  * @return
3120  *   0 on success, a negative errno value otherwise and rte_errno is set.
3121  */
3122 static int
3123 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
3124                                const struct rte_flow_action *action,
3125                                struct mlx5_flow *dev_flow,
3126                                uint8_t transfer,
3127                                struct rte_flow_error *error)
3128 {
3129         const struct rte_flow_item *encap_data;
3130         const struct rte_flow_action_raw_encap *raw_encap_data;
3131         struct mlx5_flow_dv_encap_decap_resource res = {
3132                 .reformat_type =
3133                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
3134                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3135                                       MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
3136         };
3137
3138         if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
3139                 raw_encap_data =
3140                         (const struct rte_flow_action_raw_encap *)action->conf;
3141                 res.size = raw_encap_data->size;
3142                 memcpy(res.buf, raw_encap_data->data, res.size);
3143         } else {
3144                 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
3145                         encap_data =
3146                                 ((const struct rte_flow_action_vxlan_encap *)
3147                                                 action->conf)->definition;
3148                 else
3149                         encap_data =
3150                                 ((const struct rte_flow_action_nvgre_encap *)
3151                                                 action->conf)->definition;
3152                 if (flow_dv_convert_encap_data(encap_data, res.buf,
3153                                                &res.size, error))
3154                         return -rte_errno;
3155         }
3156         if (flow_dv_zero_encap_udp_csum(res.buf, error))
3157                 return -rte_errno;
3158         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3159                 return rte_flow_error_set(error, EINVAL,
3160                                           RTE_FLOW_ERROR_TYPE_ACTION,
3161                                           NULL, "can't create L2 encap action");
3162         return 0;
3163 }
3164
3165 /**
3166  * Convert L2 decap action to DV specification.
3167  *
3168  * @param[in] dev
3169  *   Pointer to rte_eth_dev structure.
3170  * @param[in, out] dev_flow
3171  *   Pointer to the mlx5_flow.
3172  * @param[in] transfer
3173  *   Mark if the flow is E-Switch flow.
3174  * @param[out] error
3175  *   Pointer to the error structure.
3176  *
3177  * @return
3178  *   0 on success, a negative errno value otherwise and rte_errno is set.
3179  */
3180 static int
3181 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
3182                                struct mlx5_flow *dev_flow,
3183                                uint8_t transfer,
3184                                struct rte_flow_error *error)
3185 {
3186         struct mlx5_flow_dv_encap_decap_resource res = {
3187                 .size = 0,
3188                 .reformat_type =
3189                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
3190                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3191                                       MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
3192         };
3193
3194         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3195                 return rte_flow_error_set(error, EINVAL,
3196                                           RTE_FLOW_ERROR_TYPE_ACTION,
3197                                           NULL, "can't create L2 decap action");
3198         return 0;
3199 }
3200
3201 /**
3202  * Convert raw decap/encap (L3 tunnel) action to DV specification.
3203  *
3204  * @param[in] dev
3205  *   Pointer to rte_eth_dev structure.
3206  * @param[in] action
3207  *   Pointer to action structure.
3208  * @param[in, out] dev_flow
3209  *   Pointer to the mlx5_flow.
3210  * @param[in] attr
3211  *   Pointer to the flow attributes.
3212  * @param[out] error
3213  *   Pointer to the error structure.
3214  *
3215  * @return
3216  *   0 on success, a negative errno value otherwise and rte_errno is set.
3217  */
3218 static int
3219 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
3220                                 const struct rte_flow_action *action,
3221                                 struct mlx5_flow *dev_flow,
3222                                 const struct rte_flow_attr *attr,
3223                                 struct rte_flow_error *error)
3224 {
3225         const struct rte_flow_action_raw_encap *encap_data;
3226         struct mlx5_flow_dv_encap_decap_resource res;
3227
3228         memset(&res, 0, sizeof(res));
3229         encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
3230         res.size = encap_data->size;
3231         memcpy(res.buf, encap_data->data, res.size);
3232         res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
3233                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
3234                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
3235         if (attr->transfer)
3236                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3237         else
3238                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3239                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3240         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3241                 return rte_flow_error_set(error, EINVAL,
3242                                           RTE_FLOW_ERROR_TYPE_ACTION,
3243                                           NULL, "can't create encap action");
3244         return 0;
3245 }
3246
3247 /**
3248  * Create action push VLAN.
3249  *
3250  * @param[in] dev
3251  *   Pointer to rte_eth_dev structure.
3252  * @param[in] attr
3253  *   Pointer to the flow attributes.
3254  * @param[in] vlan
3255  *   Pointer to the vlan to push to the Ethernet header.
3256  * @param[in, out] dev_flow
3257  *   Pointer to the mlx5_flow.
3258  * @param[out] error
3259  *   Pointer to the error structure.
3260  *
3261  * @return
3262  *   0 on success, a negative errno value otherwise and rte_errno is set.
3263  */
3264 static int
3265 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
3266                                 const struct rte_flow_attr *attr,
3267                                 const struct rte_vlan_hdr *vlan,
3268                                 struct mlx5_flow *dev_flow,
3269                                 struct rte_flow_error *error)
3270 {
3271         struct mlx5_flow_dv_push_vlan_action_resource res;
3272
3273         memset(&res, 0, sizeof(res));
3274         res.vlan_tag =
3275                 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
3276                                  vlan->vlan_tci);
3277         if (attr->transfer)
3278                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3279         else
3280                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3281                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3282         return flow_dv_push_vlan_action_resource_register
3283                                             (dev, &res, dev_flow, error);
3284 }
3285
3286 /**
3287  * Validate the modify-header actions.
3288  *
3289  * @param[in] action_flags
3290  *   Holds the actions detected until now.
3291  * @param[in] action
3292  *   Pointer to the modify action.
3293  * @param[out] error
3294  *   Pointer to error structure.
3295  *
3296  * @return
3297  *   0 on success, a negative errno value otherwise and rte_errno is set.
3298  */
3299 static int
3300 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
3301                                    const struct rte_flow_action *action,
3302                                    struct rte_flow_error *error)
3303 {
3304         if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
3305                 return rte_flow_error_set(error, EINVAL,
3306                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3307                                           NULL, "action configuration not set");
3308         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3309                 return rte_flow_error_set(error, EINVAL,
3310                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3311                                           "can't have encap action before"
3312                                           " modify action");
3313         return 0;
3314 }
3315
3316 /**
3317  * Validate the modify-header MAC address actions.
3318  *
3319  * @param[in] action_flags
3320  *   Holds the actions detected until now.
3321  * @param[in] action
3322  *   Pointer to the modify action.
3323  * @param[in] item_flags
3324  *   Holds the items detected.
3325  * @param[out] error
3326  *   Pointer to error structure.
3327  *
3328  * @return
3329  *   0 on success, a negative errno value otherwise and rte_errno is set.
3330  */
3331 static int
3332 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
3333                                    const struct rte_flow_action *action,
3334                                    const uint64_t item_flags,
3335                                    struct rte_flow_error *error)
3336 {
3337         int ret = 0;
3338
3339         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3340         if (!ret) {
3341                 if (!(item_flags & MLX5_FLOW_LAYER_L2))
3342                         return rte_flow_error_set(error, EINVAL,
3343                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3344                                                   NULL,
3345                                                   "no L2 item in pattern");
3346         }
3347         return ret;
3348 }
3349
3350 /**
3351  * Validate the modify-header IPv4 address actions.
3352  *
3353  * @param[in] action_flags
3354  *   Holds the actions detected until now.
3355  * @param[in] action
3356  *   Pointer to the modify action.
3357  * @param[in] item_flags
3358  *   Holds the items detected.
3359  * @param[out] error
3360  *   Pointer to error structure.
3361  *
3362  * @return
3363  *   0 on success, a negative errno value otherwise and rte_errno is set.
3364  */
3365 static int
3366 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
3367                                     const struct rte_flow_action *action,
3368                                     const uint64_t item_flags,
3369                                     struct rte_flow_error *error)
3370 {
3371         int ret = 0;
3372         uint64_t layer;
3373
3374         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3375         if (!ret) {
3376                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3377                                  MLX5_FLOW_LAYER_INNER_L3_IPV4 :
3378                                  MLX5_FLOW_LAYER_OUTER_L3_IPV4;
3379                 if (!(item_flags & layer))
3380                         return rte_flow_error_set(error, EINVAL,
3381                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3382                                                   NULL,
3383                                                   "no ipv4 item in pattern");
3384         }
3385         return ret;
3386 }
3387
3388 /**
3389  * Validate the modify-header IPv6 address actions.
3390  *
3391  * @param[in] action_flags
3392  *   Holds the actions detected until now.
3393  * @param[in] action
3394  *   Pointer to the modify action.
3395  * @param[in] item_flags
3396  *   Holds the items detected.
3397  * @param[out] error
3398  *   Pointer to error structure.
3399  *
3400  * @return
3401  *   0 on success, a negative errno value otherwise and rte_errno is set.
3402  */
3403 static int
3404 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
3405                                     const struct rte_flow_action *action,
3406                                     const uint64_t item_flags,
3407                                     struct rte_flow_error *error)
3408 {
3409         int ret = 0;
3410         uint64_t layer;
3411
3412         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3413         if (!ret) {
3414                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3415                                  MLX5_FLOW_LAYER_INNER_L3_IPV6 :
3416                                  MLX5_FLOW_LAYER_OUTER_L3_IPV6;
3417                 if (!(item_flags & layer))
3418                         return rte_flow_error_set(error, EINVAL,
3419                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3420                                                   NULL,
3421                                                   "no ipv6 item in pattern");
3422         }
3423         return ret;
3424 }
3425
3426 /**
3427  * Validate the modify-header TP actions.
3428  *
3429  * @param[in] action_flags
3430  *   Holds the actions detected until now.
3431  * @param[in] action
3432  *   Pointer to the modify action.
3433  * @param[in] item_flags
3434  *   Holds the items detected.
3435  * @param[out] error
3436  *   Pointer to error structure.
3437  *
3438  * @return
3439  *   0 on success, a negative errno value otherwise and rte_errno is set.
3440  */
3441 static int
3442 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
3443                                   const struct rte_flow_action *action,
3444                                   const uint64_t item_flags,
3445                                   struct rte_flow_error *error)
3446 {
3447         int ret = 0;
3448         uint64_t layer;
3449
3450         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3451         if (!ret) {
3452                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3453                                  MLX5_FLOW_LAYER_INNER_L4 :
3454                                  MLX5_FLOW_LAYER_OUTER_L4;
3455                 if (!(item_flags & layer))
3456                         return rte_flow_error_set(error, EINVAL,
3457                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3458                                                   NULL, "no transport layer "
3459                                                   "in pattern");
3460         }
3461         return ret;
3462 }
3463
3464 /**
3465  * Validate the modify-header actions of increment/decrement
3466  * TCP Sequence-number.
3467  *
3468  * @param[in] action_flags
3469  *   Holds the actions detected until now.
3470  * @param[in] action
3471  *   Pointer to the modify action.
3472  * @param[in] item_flags
3473  *   Holds the items detected.
3474  * @param[out] error
3475  *   Pointer to error structure.
3476  *
3477  * @return
3478  *   0 on success, a negative errno value otherwise and rte_errno is set.
3479  */
3480 static int
3481 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
3482                                        const struct rte_flow_action *action,
3483                                        const uint64_t item_flags,
3484                                        struct rte_flow_error *error)
3485 {
3486         int ret = 0;
3487         uint64_t layer;
3488
3489         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3490         if (!ret) {
3491                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3492                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
3493                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
3494                 if (!(item_flags & layer))
3495                         return rte_flow_error_set(error, EINVAL,
3496                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3497                                                   NULL, "no TCP item in"
3498                                                   " pattern");
3499                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
3500                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
3501                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
3502                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
3503                         return rte_flow_error_set(error, EINVAL,
3504                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3505                                                   NULL,
3506                                                   "cannot decrease and increase"
3507                                                   " TCP sequence number"
3508                                                   " at the same time");
3509         }
3510         return ret;
3511 }
3512
3513 /**
3514  * Validate the modify-header actions of increment/decrement
3515  * TCP Acknowledgment number.
3516  *
3517  * @param[in] action_flags
3518  *   Holds the actions detected until now.
3519  * @param[in] action
3520  *   Pointer to the modify action.
3521  * @param[in] item_flags
3522  *   Holds the items detected.
3523  * @param[out] error
3524  *   Pointer to error structure.
3525  *
3526  * @return
3527  *   0 on success, a negative errno value otherwise and rte_errno is set.
3528  */
3529 static int
3530 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
3531                                        const struct rte_flow_action *action,
3532                                        const uint64_t item_flags,
3533                                        struct rte_flow_error *error)
3534 {
3535         int ret = 0;
3536         uint64_t layer;
3537
3538         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3539         if (!ret) {
3540                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3541                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
3542                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
3543                 if (!(item_flags & layer))
3544                         return rte_flow_error_set(error, EINVAL,
3545                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3546                                                   NULL, "no TCP item in"
3547                                                   " pattern");
3548                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
3549                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
3550                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
3551                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
3552                         return rte_flow_error_set(error, EINVAL,
3553                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3554                                                   NULL,
3555                                                   "cannot decrease and increase"
3556                                                   " TCP acknowledgment number"
3557                                                   " at the same time");
3558         }
3559         return ret;
3560 }
3561
3562 /**
3563  * Validate the modify-header TTL actions.
3564  *
3565  * @param[in] action_flags
3566  *   Holds the actions detected until now.
3567  * @param[in] action
3568  *   Pointer to the modify action.
3569  * @param[in] item_flags
3570  *   Holds the items detected.
3571  * @param[out] error
3572  *   Pointer to error structure.
3573  *
3574  * @return
3575  *   0 on success, a negative errno value otherwise and rte_errno is set.
3576  */
3577 static int
3578 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
3579                                    const struct rte_flow_action *action,
3580                                    const uint64_t item_flags,
3581                                    struct rte_flow_error *error)
3582 {
3583         int ret = 0;
3584         uint64_t layer;
3585
3586         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3587         if (!ret) {
3588                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3589                                  MLX5_FLOW_LAYER_INNER_L3 :
3590                                  MLX5_FLOW_LAYER_OUTER_L3;
3591                 if (!(item_flags & layer))
3592                         return rte_flow_error_set(error, EINVAL,
3593                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3594                                                   NULL,
3595                                                   "no IP protocol in pattern");
3596         }
3597         return ret;
3598 }
3599
3600 /**
3601  * Validate jump action.
3602  *
3603  * @param[in] action
3604  *   Pointer to the jump action.
3605  * @param[in] action_flags
3606  *   Holds the actions detected until now.
3607  * @param[in] attributes
3608  *   Pointer to flow attributes
3609  * @param[in] external
3610  *   Action belongs to flow rule created by request external to PMD.
3611  * @param[out] error
3612  *   Pointer to error structure.
3613  *
3614  * @return
3615  *   0 on success, a negative errno value otherwise and rte_errno is set.
3616  */
3617 static int
3618 flow_dv_validate_action_jump(const struct rte_flow_action *action,
3619                              uint64_t action_flags,
3620                              const struct rte_flow_attr *attributes,
3621                              bool external, struct rte_flow_error *error)
3622 {
3623         uint32_t target_group, table;
3624         int ret = 0;
3625
3626         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3627                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3628                 return rte_flow_error_set(error, EINVAL,
3629                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3630                                           "can't have 2 fate actions in"
3631                                           " same flow");
3632         if (action_flags & MLX5_FLOW_ACTION_METER)
3633                 return rte_flow_error_set(error, ENOTSUP,
3634                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3635                                           "jump with meter not support");
3636         if (!action->conf)
3637                 return rte_flow_error_set(error, EINVAL,
3638                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3639                                           NULL, "action configuration not set");
3640         target_group =
3641                 ((const struct rte_flow_action_jump *)action->conf)->group;
3642         ret = mlx5_flow_group_to_table(attributes, external, target_group,
3643                                        true, &table, error);
3644         if (ret)
3645                 return ret;
3646         if (attributes->group == target_group)
3647                 return rte_flow_error_set(error, EINVAL,
3648                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3649                                           "target group must be other than"
3650                                           " the current flow group");
3651         return 0;
3652 }
3653
3654 /*
3655  * Validate the port_id action.
3656  *
3657  * @param[in] dev
3658  *   Pointer to rte_eth_dev structure.
3659  * @param[in] action_flags
3660  *   Bit-fields that holds the actions detected until now.
3661  * @param[in] action
3662  *   Port_id RTE action structure.
3663  * @param[in] attr
3664  *   Attributes of flow that includes this action.
3665  * @param[out] error
3666  *   Pointer to error structure.
3667  *
3668  * @return
3669  *   0 on success, a negative errno value otherwise and rte_errno is set.
3670  */
3671 static int
3672 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
3673                                 uint64_t action_flags,
3674                                 const struct rte_flow_action *action,
3675                                 const struct rte_flow_attr *attr,
3676                                 struct rte_flow_error *error)
3677 {
3678         const struct rte_flow_action_port_id *port_id;
3679         struct mlx5_priv *act_priv;
3680         struct mlx5_priv *dev_priv;
3681         uint16_t port;
3682
3683         if (!attr->transfer)
3684                 return rte_flow_error_set(error, ENOTSUP,
3685                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3686                                           NULL,
3687                                           "port id action is valid in transfer"
3688                                           " mode only");
3689         if (!action || !action->conf)
3690                 return rte_flow_error_set(error, ENOTSUP,
3691                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3692                                           NULL,
3693                                           "port id action parameters must be"
3694                                           " specified");
3695         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3696                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3697                 return rte_flow_error_set(error, EINVAL,
3698                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3699                                           "can have only one fate actions in"
3700                                           " a flow");
3701         dev_priv = mlx5_dev_to_eswitch_info(dev);
3702         if (!dev_priv)
3703                 return rte_flow_error_set(error, rte_errno,
3704                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3705                                           NULL,
3706                                           "failed to obtain E-Switch info");
3707         port_id = action->conf;
3708         port = port_id->original ? dev->data->port_id : port_id->id;
3709         act_priv = mlx5_port_to_eswitch_info(port, false);
3710         if (!act_priv)
3711                 return rte_flow_error_set
3712                                 (error, rte_errno,
3713                                  RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
3714                                  "failed to obtain E-Switch port id for port");
3715         if (act_priv->domain_id != dev_priv->domain_id)
3716                 return rte_flow_error_set
3717                                 (error, EINVAL,
3718                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3719                                  "port does not belong to"
3720                                  " E-Switch being configured");
3721         return 0;
3722 }
3723
3724 /**
3725  * Get the maximum number of modify header actions.
3726  *
3727  * @param dev
3728  *   Pointer to rte_eth_dev structure.
3729  * @param flags
3730  *   Flags bits to check if root level.
3731  *
3732  * @return
3733  *   Max number of modify header actions device can support.
3734  */
3735 static inline unsigned int
3736 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev __rte_unused,
3737                               uint64_t flags)
3738 {
3739         /*
3740          * There's no way to directly query the max capacity from FW.
3741          * The maximal value on root table should be assumed to be supported.
3742          */
3743         if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
3744                 return MLX5_MAX_MODIFY_NUM;
3745         else
3746                 return MLX5_ROOT_TBL_MODIFY_NUM;
3747 }
3748
3749 /**
3750  * Validate the meter action.
3751  *
3752  * @param[in] dev
3753  *   Pointer to rte_eth_dev structure.
3754  * @param[in] action_flags
3755  *   Bit-fields that holds the actions detected until now.
3756  * @param[in] action
3757  *   Pointer to the meter action.
3758  * @param[in] attr
3759  *   Attributes of flow that includes this action.
3760  * @param[out] error
3761  *   Pointer to error structure.
3762  *
3763  * @return
3764  *   0 on success, a negative errno value otherwise and rte_ernno is set.
3765  */
3766 static int
3767 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
3768                                 uint64_t action_flags,
3769                                 const struct rte_flow_action *action,
3770                                 const struct rte_flow_attr *attr,
3771                                 struct rte_flow_error *error)
3772 {
3773         struct mlx5_priv *priv = dev->data->dev_private;
3774         const struct rte_flow_action_meter *am = action->conf;
3775         struct mlx5_flow_meter *fm;
3776
3777         if (!am)
3778                 return rte_flow_error_set(error, EINVAL,
3779                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3780                                           "meter action conf is NULL");
3781
3782         if (action_flags & MLX5_FLOW_ACTION_METER)
3783                 return rte_flow_error_set(error, ENOTSUP,
3784                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3785                                           "meter chaining not support");
3786         if (action_flags & MLX5_FLOW_ACTION_JUMP)
3787                 return rte_flow_error_set(error, ENOTSUP,
3788                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3789                                           "meter with jump not support");
3790         if (!priv->mtr_en)
3791                 return rte_flow_error_set(error, ENOTSUP,
3792                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3793                                           NULL,
3794                                           "meter action not supported");
3795         fm = mlx5_flow_meter_find(priv, am->mtr_id);
3796         if (!fm)
3797                 return rte_flow_error_set(error, EINVAL,
3798                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3799                                           "Meter not found");
3800         if (fm->ref_cnt && (!(fm->transfer == attr->transfer ||
3801               (!fm->ingress && !attr->ingress && attr->egress) ||
3802               (!fm->egress && !attr->egress && attr->ingress))))
3803                 return rte_flow_error_set(error, EINVAL,
3804                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3805                                           "Flow attributes are either invalid "
3806                                           "or have a conflict with current "
3807                                           "meter attributes");
3808         return 0;
3809 }
3810
3811 /**
3812  * Validate the age action.
3813  *
3814  * @param[in] action_flags
3815  *   Holds the actions detected until now.
3816  * @param[in] action
3817  *   Pointer to the age action.
3818  * @param[in] dev
3819  *   Pointer to the Ethernet device structure.
3820  * @param[out] error
3821  *   Pointer to error structure.
3822  *
3823  * @return
3824  *   0 on success, a negative errno value otherwise and rte_errno is set.
3825  */
3826 static int
3827 flow_dv_validate_action_age(uint64_t action_flags,
3828                             const struct rte_flow_action *action,
3829                             struct rte_eth_dev *dev,
3830                             struct rte_flow_error *error)
3831 {
3832         struct mlx5_priv *priv = dev->data->dev_private;
3833         const struct rte_flow_action_age *age = action->conf;
3834
3835         if (!priv->config.devx || priv->counter_fallback)
3836                 return rte_flow_error_set(error, ENOTSUP,
3837                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3838                                           NULL,
3839                                           "age action not supported");
3840         if (!(action->conf))
3841                 return rte_flow_error_set(error, EINVAL,
3842                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3843                                           "configuration cannot be null");
3844         if (age->timeout >= UINT16_MAX / 2 / 10)
3845                 return rte_flow_error_set(error, ENOTSUP,
3846                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3847                                           "Max age time: 3275 seconds");
3848         if (action_flags & MLX5_FLOW_ACTION_AGE)
3849                 return rte_flow_error_set(error, EINVAL,
3850                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3851                                           "Duplicate age ctions set");
3852         return 0;
3853 }
3854
3855 /**
3856  * Validate the modify-header IPv4 DSCP actions.
3857  *
3858  * @param[in] action_flags
3859  *   Holds the actions detected until now.
3860  * @param[in] action
3861  *   Pointer to the modify action.
3862  * @param[in] item_flags
3863  *   Holds the items detected.
3864  * @param[out] error
3865  *   Pointer to error structure.
3866  *
3867  * @return
3868  *   0 on success, a negative errno value otherwise and rte_errno is set.
3869  */
3870 static int
3871 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
3872                                          const struct rte_flow_action *action,
3873                                          const uint64_t item_flags,
3874                                          struct rte_flow_error *error)
3875 {
3876         int ret = 0;
3877
3878         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3879         if (!ret) {
3880                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
3881                         return rte_flow_error_set(error, EINVAL,
3882                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3883                                                   NULL,
3884                                                   "no ipv4 item in pattern");
3885         }
3886         return ret;
3887 }
3888
3889 /**
3890  * Validate the modify-header IPv6 DSCP actions.
3891  *
3892  * @param[in] action_flags
3893  *   Holds the actions detected until now.
3894  * @param[in] action
3895  *   Pointer to the modify action.
3896  * @param[in] item_flags
3897  *   Holds the items detected.
3898  * @param[out] error
3899  *   Pointer to error structure.
3900  *
3901  * @return
3902  *   0 on success, a negative errno value otherwise and rte_errno is set.
3903  */
3904 static int
3905 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
3906                                          const struct rte_flow_action *action,
3907                                          const uint64_t item_flags,
3908                                          struct rte_flow_error *error)
3909 {
3910         int ret = 0;
3911
3912         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3913         if (!ret) {
3914                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
3915                         return rte_flow_error_set(error, EINVAL,
3916                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3917                                                   NULL,
3918                                                   "no ipv6 item in pattern");
3919         }
3920         return ret;
3921 }
3922
3923 /**
3924  * Find existing modify-header resource or create and register a new one.
3925  *
3926  * @param dev[in, out]
3927  *   Pointer to rte_eth_dev structure.
3928  * @param[in, out] resource
3929  *   Pointer to modify-header resource.
3930  * @parm[in, out] dev_flow
3931  *   Pointer to the dev_flow.
3932  * @param[out] error
3933  *   pointer to error structure.
3934  *
3935  * @return
3936  *   0 on success otherwise -errno and errno is set.
3937  */
3938 static int
3939 flow_dv_modify_hdr_resource_register
3940                         (struct rte_eth_dev *dev,
3941                          struct mlx5_flow_dv_modify_hdr_resource *resource,
3942                          struct mlx5_flow *dev_flow,
3943                          struct rte_flow_error *error)
3944 {
3945         struct mlx5_priv *priv = dev->data->dev_private;
3946         struct mlx5_ibv_shared *sh = priv->sh;
3947         struct mlx5_flow_dv_modify_hdr_resource *cache_resource;
3948         struct mlx5dv_dr_domain *ns;
3949         uint32_t actions_len;
3950
3951         resource->flags = dev_flow->dv.group ? 0 :
3952                           MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
3953         if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
3954                                     resource->flags))
3955                 return rte_flow_error_set(error, EOVERFLOW,
3956                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3957                                           "too many modify header items");
3958         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3959                 ns = sh->fdb_domain;
3960         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
3961                 ns = sh->tx_domain;
3962         else
3963                 ns = sh->rx_domain;
3964         /* Lookup a matching resource from cache. */
3965         actions_len = resource->actions_num * sizeof(resource->actions[0]);
3966         LIST_FOREACH(cache_resource, &sh->modify_cmds, next) {
3967                 if (resource->ft_type == cache_resource->ft_type &&
3968                     resource->actions_num == cache_resource->actions_num &&
3969                     resource->flags == cache_resource->flags &&
3970                     !memcmp((const void *)resource->actions,
3971                             (const void *)cache_resource->actions,
3972                             actions_len)) {
3973                         DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d++",
3974                                 (void *)cache_resource,
3975                                 rte_atomic32_read(&cache_resource->refcnt));
3976                         rte_atomic32_inc(&cache_resource->refcnt);
3977                         dev_flow->handle->dvh.modify_hdr = cache_resource;
3978                         return 0;
3979                 }
3980         }
3981         /* Register new modify-header resource. */
3982         cache_resource = rte_calloc(__func__, 1,
3983                                     sizeof(*cache_resource) + actions_len, 0);
3984         if (!cache_resource)
3985                 return rte_flow_error_set(error, ENOMEM,
3986                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3987                                           "cannot allocate resource memory");
3988         *cache_resource = *resource;
3989         rte_memcpy(cache_resource->actions, resource->actions, actions_len);
3990         cache_resource->verbs_action =
3991                 mlx5_glue->dv_create_flow_action_modify_header
3992                                         (sh->ctx, cache_resource->ft_type, ns,
3993                                          cache_resource->flags, actions_len,
3994                                          (uint64_t *)cache_resource->actions);
3995         if (!cache_resource->verbs_action) {
3996                 rte_free(cache_resource);
3997                 return rte_flow_error_set(error, ENOMEM,
3998                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3999                                           NULL, "cannot create action");
4000         }
4001         rte_atomic32_init(&cache_resource->refcnt);
4002         rte_atomic32_inc(&cache_resource->refcnt);
4003         LIST_INSERT_HEAD(&sh->modify_cmds, cache_resource, next);
4004         dev_flow->handle->dvh.modify_hdr = cache_resource;
4005         DRV_LOG(DEBUG, "new modify-header resource %p: refcnt %d++",
4006                 (void *)cache_resource,
4007                 rte_atomic32_read(&cache_resource->refcnt));
4008         return 0;
4009 }
4010
4011 /**
4012  * Get DV flow counter by index.
4013  *
4014  * @param[in] dev
4015  *   Pointer to the Ethernet device structure.
4016  * @param[in] idx
4017  *   mlx5 flow counter index in the container.
4018  * @param[out] ppool
4019  *   mlx5 flow counter pool in the container,
4020  *
4021  * @return
4022  *   Pointer to the counter, NULL otherwise.
4023  */
4024 static struct mlx5_flow_counter *
4025 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
4026                            uint32_t idx,
4027                            struct mlx5_flow_counter_pool **ppool)
4028 {
4029         struct mlx5_priv *priv = dev->data->dev_private;
4030         struct mlx5_pools_container *cont;
4031         struct mlx5_flow_counter_pool *pool;
4032         uint32_t batch = 0, age = 0;
4033
4034         idx--;
4035         age = MLX_CNT_IS_AGE(idx);
4036         idx = age ? idx - MLX5_CNT_AGE_OFFSET : idx;
4037         if (idx >= MLX5_CNT_BATCH_OFFSET) {
4038                 idx -= MLX5_CNT_BATCH_OFFSET;
4039                 batch = 1;
4040         }
4041         cont = MLX5_CNT_CONTAINER(priv->sh, batch, age);
4042         MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cont->n);
4043         pool = cont->pools[idx / MLX5_COUNTERS_PER_POOL];
4044         MLX5_ASSERT(pool);
4045         if (ppool)
4046                 *ppool = pool;
4047         return MLX5_POOL_GET_CNT(pool, idx % MLX5_COUNTERS_PER_POOL);
4048 }
4049
4050 /**
4051  * Get a pool by devx counter ID.
4052  *
4053  * @param[in] cont
4054  *   Pointer to the counter container.
4055  * @param[in] id
4056  *   The counter devx ID.
4057  *
4058  * @return
4059  *   The counter pool pointer if exists, NULL otherwise,
4060  */
4061 static struct mlx5_flow_counter_pool *
4062 flow_dv_find_pool_by_id(struct mlx5_pools_container *cont, int id)
4063 {
4064         uint32_t i;
4065         uint32_t n_valid = rte_atomic16_read(&cont->n_valid);
4066
4067         for (i = 0; i < n_valid; i++) {
4068                 struct mlx5_flow_counter_pool *pool = cont->pools[i];
4069                 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
4070                            MLX5_COUNTERS_PER_POOL;
4071
4072                 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL) {
4073                         /*
4074                          * Move the pool to the head, as counter allocate
4075                          * always gets the first pool in the container.
4076                          */
4077                         if (pool != TAILQ_FIRST(&cont->pool_list)) {
4078                                 TAILQ_REMOVE(&cont->pool_list, pool, next);
4079                                 TAILQ_INSERT_HEAD(&cont->pool_list, pool, next);
4080                         }
4081                         return pool;
4082                 }
4083         }
4084         return NULL;
4085 }
4086
4087 /**
4088  * Allocate a new memory for the counter values wrapped by all the needed
4089  * management.
4090  *
4091  * @param[in] dev
4092  *   Pointer to the Ethernet device structure.
4093  * @param[in] raws_n
4094  *   The raw memory areas - each one for MLX5_COUNTERS_PER_POOL counters.
4095  *
4096  * @return
4097  *   The new memory management pointer on success, otherwise NULL and rte_errno
4098  *   is set.
4099  */
4100 static struct mlx5_counter_stats_mem_mng *
4101 flow_dv_create_counter_stat_mem_mng(struct rte_eth_dev *dev, int raws_n)
4102 {
4103         struct mlx5_priv *priv = dev->data->dev_private;
4104         struct mlx5_ibv_shared *sh = priv->sh;
4105         struct mlx5_devx_mkey_attr mkey_attr;
4106         struct mlx5_counter_stats_mem_mng *mem_mng;
4107         volatile struct flow_counter_stats *raw_data;
4108         int size = (sizeof(struct flow_counter_stats) *
4109                         MLX5_COUNTERS_PER_POOL +
4110                         sizeof(struct mlx5_counter_stats_raw)) * raws_n +
4111                         sizeof(struct mlx5_counter_stats_mem_mng);
4112         uint8_t *mem = rte_calloc(__func__, 1, size, sysconf(_SC_PAGESIZE));
4113         int i;
4114
4115         if (!mem) {
4116                 rte_errno = ENOMEM;
4117                 return NULL;
4118         }
4119         mem_mng = (struct mlx5_counter_stats_mem_mng *)(mem + size) - 1;
4120         size = sizeof(*raw_data) * MLX5_COUNTERS_PER_POOL * raws_n;
4121         mem_mng->umem = mlx5_glue->devx_umem_reg(sh->ctx, mem, size,
4122                                                  IBV_ACCESS_LOCAL_WRITE);
4123         if (!mem_mng->umem) {
4124                 rte_errno = errno;
4125                 rte_free(mem);
4126                 return NULL;
4127         }
4128         mkey_attr.addr = (uintptr_t)mem;
4129         mkey_attr.size = size;
4130         mkey_attr.umem_id = mem_mng->umem->umem_id;
4131         mkey_attr.pd = sh->pdn;
4132         mkey_attr.log_entity_size = 0;
4133         mkey_attr.pg_access = 0;
4134         mkey_attr.klm_array = NULL;
4135         mkey_attr.klm_num = 0;
4136         if (priv->config.hca_attr.relaxed_ordering_write &&
4137                 priv->config.hca_attr.relaxed_ordering_read  &&
4138                 !haswell_broadwell_cpu)
4139                 mkey_attr.relaxed_ordering = 1;
4140         mem_mng->dm = mlx5_devx_cmd_mkey_create(sh->ctx, &mkey_attr);
4141         if (!mem_mng->dm) {
4142                 mlx5_glue->devx_umem_dereg(mem_mng->umem);
4143                 rte_errno = errno;
4144                 rte_free(mem);
4145                 return NULL;
4146         }
4147         mem_mng->raws = (struct mlx5_counter_stats_raw *)(mem + size);
4148         raw_data = (volatile struct flow_counter_stats *)mem;
4149         for (i = 0; i < raws_n; ++i) {
4150                 mem_mng->raws[i].mem_mng = mem_mng;
4151                 mem_mng->raws[i].data = raw_data + i * MLX5_COUNTERS_PER_POOL;
4152         }
4153         LIST_INSERT_HEAD(&sh->cmng.mem_mngs, mem_mng, next);
4154         return mem_mng;
4155 }
4156
4157 /**
4158  * Resize a counter container.
4159  *
4160  * @param[in] dev
4161  *   Pointer to the Ethernet device structure.
4162  * @param[in] batch
4163  *   Whether the pool is for counter that was allocated by batch command.
4164  * @param[in] age
4165  *   Whether the pool is for Aging counter.
4166  *
4167  * @return
4168  *   0 on success, otherwise negative errno value and rte_errno is set.
4169  */
4170 static int
4171 flow_dv_container_resize(struct rte_eth_dev *dev,
4172                                 uint32_t batch, uint32_t age)
4173 {
4174         struct mlx5_priv *priv = dev->data->dev_private;
4175         struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4176                                                                age);
4177         struct mlx5_counter_stats_mem_mng *mem_mng = NULL;
4178         void *old_pools = cont->pools;
4179         uint32_t resize = cont->n + MLX5_CNT_CONTAINER_RESIZE;
4180         uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
4181         void *pools = rte_calloc(__func__, 1, mem_size, 0);
4182
4183         if (!pools) {
4184                 rte_errno = ENOMEM;
4185                 return -ENOMEM;
4186         }
4187         if (old_pools)
4188                 memcpy(pools, old_pools, cont->n *
4189                                        sizeof(struct mlx5_flow_counter_pool *));
4190         /*
4191          * Fallback mode query the counter directly, no background query
4192          * resources are needed.
4193          */
4194         if (!priv->counter_fallback) {
4195                 int i;
4196
4197                 mem_mng = flow_dv_create_counter_stat_mem_mng(dev,
4198                           MLX5_CNT_CONTAINER_RESIZE + MLX5_MAX_PENDING_QUERIES);
4199                 if (!mem_mng) {
4200                         rte_free(pools);
4201                         return -ENOMEM;
4202                 }
4203                 for (i = 0; i < MLX5_MAX_PENDING_QUERIES; ++i)
4204                         LIST_INSERT_HEAD(&priv->sh->cmng.free_stat_raws,
4205                                          mem_mng->raws +
4206                                          MLX5_CNT_CONTAINER_RESIZE +
4207                                          i, next);
4208         }
4209         rte_spinlock_lock(&cont->resize_sl);
4210         cont->n = resize;
4211         cont->mem_mng = mem_mng;
4212         cont->pools = pools;
4213         rte_spinlock_unlock(&cont->resize_sl);
4214         if (old_pools)
4215                 rte_free(old_pools);
4216         return 0;
4217 }
4218
4219 /**
4220  * Query a devx flow counter.
4221  *
4222  * @param[in] dev
4223  *   Pointer to the Ethernet device structure.
4224  * @param[in] cnt
4225  *   Index to the flow counter.
4226  * @param[out] pkts
4227  *   The statistics value of packets.
4228  * @param[out] bytes
4229  *   The statistics value of bytes.
4230  *
4231  * @return
4232  *   0 on success, otherwise a negative errno value and rte_errno is set.
4233  */
4234 static inline int
4235 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
4236                      uint64_t *bytes)
4237 {
4238         struct mlx5_priv *priv = dev->data->dev_private;
4239         struct mlx5_flow_counter_pool *pool = NULL;
4240         struct mlx5_flow_counter *cnt;
4241         struct mlx5_flow_counter_ext *cnt_ext = NULL;
4242         int offset;
4243
4244         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
4245         MLX5_ASSERT(pool);
4246         if (counter < MLX5_CNT_BATCH_OFFSET) {
4247                 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt);
4248                 if (priv->counter_fallback)
4249                         return mlx5_devx_cmd_flow_counter_query(cnt_ext->dcs, 0,
4250                                         0, pkts, bytes, 0, NULL, NULL, 0);
4251         }
4252
4253         rte_spinlock_lock(&pool->sl);
4254         /*
4255          * The single counters allocation may allocate smaller ID than the
4256          * current allocated in parallel to the host reading.
4257          * In this case the new counter values must be reported as 0.
4258          */
4259         if (unlikely(cnt_ext && cnt_ext->dcs->id < pool->raw->min_dcs_id)) {
4260                 *pkts = 0;
4261                 *bytes = 0;
4262         } else {
4263                 offset = MLX5_CNT_ARRAY_IDX(pool, cnt);
4264                 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
4265                 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
4266         }
4267         rte_spinlock_unlock(&pool->sl);
4268         return 0;
4269 }
4270
4271 /**
4272  * Create and initialize a new counter pool.
4273  *
4274  * @param[in] dev
4275  *   Pointer to the Ethernet device structure.
4276  * @param[out] dcs
4277  *   The devX counter handle.
4278  * @param[in] batch
4279  *   Whether the pool is for counter that was allocated by batch command.
4280  * @param[in] age
4281  *   Whether the pool is for counter that was allocated for aging.
4282  * @param[in/out] cont_cur
4283  *   Pointer to the container pointer, it will be update in pool resize.
4284  *
4285  * @return
4286  *   The pool container pointer on success, NULL otherwise and rte_errno is set.
4287  */
4288 static struct mlx5_flow_counter_pool *
4289 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
4290                     uint32_t batch, uint32_t age)
4291 {
4292         struct mlx5_priv *priv = dev->data->dev_private;
4293         struct mlx5_flow_counter_pool *pool;
4294         struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4295                                                                age);
4296         int16_t n_valid = rte_atomic16_read(&cont->n_valid);
4297         uint32_t size = sizeof(*pool);
4298
4299         if (cont->n == n_valid && flow_dv_container_resize(dev, batch, age))
4300                 return NULL;
4301         size += MLX5_COUNTERS_PER_POOL * CNT_SIZE;
4302         size += (batch ? 0 : MLX5_COUNTERS_PER_POOL * CNTEXT_SIZE);
4303         size += (!age ? 0 : MLX5_COUNTERS_PER_POOL * AGE_SIZE);
4304         pool = rte_calloc(__func__, 1, size, 0);
4305         if (!pool) {
4306                 rte_errno = ENOMEM;
4307                 return NULL;
4308         }
4309         pool->min_dcs = dcs;
4310         if (!priv->counter_fallback)
4311                 pool->raw = cont->mem_mng->raws + n_valid %
4312                                                       MLX5_CNT_CONTAINER_RESIZE;
4313         pool->raw_hw = NULL;
4314         pool->type = 0;
4315         pool->type |= (batch ? 0 :  CNT_POOL_TYPE_EXT);
4316         pool->type |= (!age ? 0 :  CNT_POOL_TYPE_AGE);
4317         rte_spinlock_init(&pool->sl);
4318         /*
4319          * The generation of the new allocated counters in this pool is 0, 2 in
4320          * the pool generation makes all the counters valid for allocation.
4321          * The start and end query generation protect the counters be released
4322          * between the query and update gap period will not be reallocated
4323          * without the last query finished and stats updated to the memory.
4324          */
4325         rte_atomic64_set(&pool->start_query_gen, 0x2);
4326         /*
4327          * There's no background query thread for fallback mode, set the
4328          * end_query_gen to the maximum value since no need to wait for
4329          * statistics update.
4330          */
4331         rte_atomic64_set(&pool->end_query_gen, priv->counter_fallback ?
4332                          INT64_MAX : 0x2);
4333         TAILQ_INIT(&pool->counters);
4334         TAILQ_INSERT_HEAD(&cont->pool_list, pool, next);
4335         pool->index = n_valid;
4336         cont->pools[n_valid] = pool;
4337         /* Pool initialization must be updated before host thread access. */
4338         rte_cio_wmb();
4339         rte_atomic16_add(&cont->n_valid, 1);
4340         return pool;
4341 }
4342
4343 /**
4344  * Update the minimum dcs-id for aged or no-aged counter pool.
4345  *
4346  * @param[in] dev
4347  *   Pointer to the Ethernet device structure.
4348  * @param[in] pool
4349  *   Current counter pool.
4350  * @param[in] batch
4351  *   Whether the pool is for counter that was allocated by batch command.
4352  * @param[in] age
4353  *   Whether the counter is for aging.
4354  */
4355 static void
4356 flow_dv_counter_update_min_dcs(struct rte_eth_dev *dev,
4357                         struct mlx5_flow_counter_pool *pool,
4358                         uint32_t batch, uint32_t age)
4359 {
4360         struct mlx5_priv *priv = dev->data->dev_private;
4361         struct mlx5_flow_counter_pool *other;
4362         struct mlx5_pools_container *cont;
4363
4364         cont = MLX5_CNT_CONTAINER(priv->sh, batch, (age ^ 0x1));
4365         other = flow_dv_find_pool_by_id(cont, pool->min_dcs->id);
4366         if (!other)
4367                 return;
4368         if (pool->min_dcs->id < other->min_dcs->id) {
4369                 rte_atomic64_set(&other->a64_dcs,
4370                         rte_atomic64_read(&pool->a64_dcs));
4371         } else {
4372                 rte_atomic64_set(&pool->a64_dcs,
4373                         rte_atomic64_read(&other->a64_dcs));
4374         }
4375 }
4376 /**
4377  * Prepare a new counter and/or a new counter pool.
4378  *
4379  * @param[in] dev
4380  *   Pointer to the Ethernet device structure.
4381  * @param[out] cnt_free
4382  *   Where to put the pointer of a new counter.
4383  * @param[in] batch
4384  *   Whether the pool is for counter that was allocated by batch command.
4385  * @param[in] age
4386  *   Whether the pool is for counter that was allocated for aging.
4387  *
4388  * @return
4389  *   The counter pool pointer and @p cnt_free is set on success,
4390  *   NULL otherwise and rte_errno is set.
4391  */
4392 static struct mlx5_flow_counter_pool *
4393 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
4394                              struct mlx5_flow_counter **cnt_free,
4395                              uint32_t batch, uint32_t age)
4396 {
4397         struct mlx5_priv *priv = dev->data->dev_private;
4398         struct mlx5_pools_container *cont;
4399         struct mlx5_flow_counter_pool *pool;
4400         struct mlx5_devx_obj *dcs = NULL;
4401         struct mlx5_flow_counter *cnt;
4402         uint32_t i;
4403
4404         cont = MLX5_CNT_CONTAINER(priv->sh, batch, age);
4405         if (!batch) {
4406                 /* bulk_bitmap must be 0 for single counter allocation. */
4407                 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
4408                 if (!dcs)
4409                         return NULL;
4410                 pool = flow_dv_find_pool_by_id(cont, dcs->id);
4411                 if (!pool) {
4412                         pool = flow_dv_pool_create(dev, dcs, batch, age);
4413                         if (!pool) {
4414                                 mlx5_devx_cmd_destroy(dcs);
4415                                 return NULL;
4416                         }
4417                 } else if (dcs->id < pool->min_dcs->id) {
4418                         rte_atomic64_set(&pool->a64_dcs,
4419                                          (int64_t)(uintptr_t)dcs);
4420                 }
4421                 flow_dv_counter_update_min_dcs(dev,
4422                                                 pool, batch, age);
4423                 i = dcs->id % MLX5_COUNTERS_PER_POOL;
4424                 cnt = MLX5_POOL_GET_CNT(pool, i);
4425                 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
4426                 MLX5_GET_POOL_CNT_EXT(pool, i)->dcs = dcs;
4427                 *cnt_free = cnt;
4428                 return pool;
4429         }
4430         /* bulk_bitmap is in 128 counters units. */
4431         if (priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4)
4432                 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
4433         if (!dcs) {
4434                 rte_errno = ENODATA;
4435                 return NULL;
4436         }
4437         pool = flow_dv_pool_create(dev, dcs, batch, age);
4438         if (!pool) {
4439                 mlx5_devx_cmd_destroy(dcs);
4440                 return NULL;
4441         }
4442         for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
4443                 cnt = MLX5_POOL_GET_CNT(pool, i);
4444                 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
4445         }
4446         *cnt_free = MLX5_POOL_GET_CNT(pool, 0);
4447         return pool;
4448 }
4449
4450 /**
4451  * Search for existed shared counter.
4452  *
4453  * @param[in] cont
4454  *   Pointer to the relevant counter pool container.
4455  * @param[in] id
4456  *   The shared counter ID to search.
4457  * @param[out] ppool
4458  *   mlx5 flow counter pool in the container,
4459  *
4460  * @return
4461  *   NULL if not existed, otherwise pointer to the shared extend counter.
4462  */
4463 static struct mlx5_flow_counter_ext *
4464 flow_dv_counter_shared_search(struct mlx5_pools_container *cont, uint32_t id,
4465                               struct mlx5_flow_counter_pool **ppool)
4466 {
4467         static struct mlx5_flow_counter_ext *cnt;
4468         struct mlx5_flow_counter_pool *pool;
4469         uint32_t i;
4470         uint32_t n_valid = rte_atomic16_read(&cont->n_valid);
4471
4472         for (i = 0; i < n_valid; i++) {
4473                 pool = cont->pools[i];
4474                 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
4475                         cnt = MLX5_GET_POOL_CNT_EXT(pool, i);
4476                         if (cnt->ref_cnt && cnt->shared && cnt->id == id) {
4477                                 if (ppool)
4478                                         *ppool = cont->pools[i];
4479                                 return cnt;
4480                         }
4481                 }
4482         }
4483         return NULL;
4484 }
4485
4486 /**
4487  * Allocate a flow counter.
4488  *
4489  * @param[in] dev
4490  *   Pointer to the Ethernet device structure.
4491  * @param[in] shared
4492  *   Indicate if this counter is shared with other flows.
4493  * @param[in] id
4494  *   Counter identifier.
4495  * @param[in] group
4496  *   Counter flow group.
4497  * @param[in] age
4498  *   Whether the counter was allocated for aging.
4499  *
4500  * @return
4501  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
4502  */
4503 static uint32_t
4504 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t shared, uint32_t id,
4505                       uint16_t group, uint32_t age)
4506 {
4507         struct mlx5_priv *priv = dev->data->dev_private;
4508         struct mlx5_flow_counter_pool *pool = NULL;
4509         struct mlx5_flow_counter *cnt_free = NULL;
4510         struct mlx5_flow_counter_ext *cnt_ext = NULL;
4511         /*
4512          * Currently group 0 flow counter cannot be assigned to a flow if it is
4513          * not the first one in the batch counter allocation, so it is better
4514          * to allocate counters one by one for these flows in a separate
4515          * container.
4516          * A counter can be shared between different groups so need to take
4517          * shared counters from the single container.
4518          */
4519         uint32_t batch = (group && !shared && !priv->counter_fallback) ? 1 : 0;
4520         struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4521                                                                age);
4522         uint32_t cnt_idx;
4523
4524         if (!priv->config.devx) {
4525                 rte_errno = ENOTSUP;
4526                 return 0;
4527         }
4528         if (shared) {
4529                 cnt_ext = flow_dv_counter_shared_search(cont, id, &pool);
4530                 if (cnt_ext) {
4531                         if (cnt_ext->ref_cnt + 1 == 0) {
4532                                 rte_errno = E2BIG;
4533                                 return 0;
4534                         }
4535                         cnt_ext->ref_cnt++;
4536                         cnt_idx = pool->index * MLX5_COUNTERS_PER_POOL +
4537                                   (cnt_ext->dcs->id % MLX5_COUNTERS_PER_POOL)
4538                                   + 1;
4539                         return cnt_idx;
4540                 }
4541         }
4542         /* Pools which has a free counters are in the start. */
4543         TAILQ_FOREACH(pool, &cont->pool_list, next) {
4544                 /*
4545                  * The free counter reset values must be updated between the
4546                  * counter release to the counter allocation, so, at least one
4547                  * query must be done in this time. ensure it by saving the
4548                  * query generation in the release time.
4549                  * The free list is sorted according to the generation - so if
4550                  * the first one is not updated, all the others are not
4551                  * updated too.
4552                  */
4553                 cnt_free = TAILQ_FIRST(&pool->counters);
4554                 if (cnt_free && cnt_free->query_gen <
4555                     rte_atomic64_read(&pool->end_query_gen))
4556                         break;
4557                 cnt_free = NULL;
4558         }
4559         if (!cnt_free) {
4560                 pool = flow_dv_counter_pool_prepare(dev, &cnt_free, batch, age);
4561                 if (!pool)
4562                         return 0;
4563         }
4564         if (!batch)
4565                 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt_free);
4566         /* Create a DV counter action only in the first time usage. */
4567         if (!cnt_free->action) {
4568                 uint16_t offset;
4569                 struct mlx5_devx_obj *dcs;
4570
4571                 if (batch) {
4572                         offset = MLX5_CNT_ARRAY_IDX(pool, cnt_free);
4573                         dcs = pool->min_dcs;
4574                 } else {
4575                         offset = 0;
4576                         dcs = cnt_ext->dcs;
4577                 }
4578                 cnt_free->action = mlx5_glue->dv_create_flow_action_counter
4579                                         (dcs->obj, offset);
4580                 if (!cnt_free->action) {
4581                         rte_errno = errno;
4582                         return 0;
4583                 }
4584         }
4585         cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
4586                                 MLX5_CNT_ARRAY_IDX(pool, cnt_free));
4587         cnt_idx += batch * MLX5_CNT_BATCH_OFFSET;
4588         cnt_idx += age * MLX5_CNT_AGE_OFFSET;
4589         /* Update the counter reset values. */
4590         if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
4591                                  &cnt_free->bytes))
4592                 return 0;
4593         if (cnt_ext) {
4594                 cnt_ext->shared = shared;
4595                 cnt_ext->ref_cnt = 1;
4596                 cnt_ext->id = id;
4597         }
4598         if (!priv->counter_fallback && !priv->sh->cmng.query_thread_on)
4599                 /* Start the asynchronous batch query by the host thread. */
4600                 mlx5_set_query_alarm(priv->sh);
4601         TAILQ_REMOVE(&pool->counters, cnt_free, next);
4602         if (TAILQ_EMPTY(&pool->counters)) {
4603                 /* Move the pool to the end of the container pool list. */
4604                 TAILQ_REMOVE(&cont->pool_list, pool, next);
4605                 TAILQ_INSERT_TAIL(&cont->pool_list, pool, next);
4606         }
4607         return cnt_idx;
4608 }
4609
4610 /**
4611  * Get age param from counter index.
4612  *
4613  * @param[in] dev
4614  *   Pointer to the Ethernet device structure.
4615  * @param[in] counter
4616  *   Index to the counter handler.
4617  *
4618  * @return
4619  *   The aging parameter specified for the counter index.
4620  */
4621 static struct mlx5_age_param*
4622 flow_dv_counter_idx_get_age(struct rte_eth_dev *dev,
4623                                 uint32_t counter)
4624 {
4625         struct mlx5_flow_counter *cnt;
4626         struct mlx5_flow_counter_pool *pool = NULL;
4627
4628         flow_dv_counter_get_by_idx(dev, counter, &pool);
4629         counter = (counter - 1) % MLX5_COUNTERS_PER_POOL;
4630         cnt = MLX5_POOL_GET_CNT(pool, counter);
4631         return MLX5_CNT_TO_AGE(cnt);
4632 }
4633
4634 /**
4635  * Remove a flow counter from aged counter list.
4636  *
4637  * @param[in] dev
4638  *   Pointer to the Ethernet device structure.
4639  * @param[in] counter
4640  *   Index to the counter handler.
4641  * @param[in] cnt
4642  *   Pointer to the counter handler.
4643  */
4644 static void
4645 flow_dv_counter_remove_from_age(struct rte_eth_dev *dev,
4646                                 uint32_t counter, struct mlx5_flow_counter *cnt)
4647 {
4648         struct mlx5_age_info *age_info;
4649         struct mlx5_age_param *age_param;
4650         struct mlx5_priv *priv = dev->data->dev_private;
4651
4652         age_info = GET_PORT_AGE_INFO(priv);
4653         age_param = flow_dv_counter_idx_get_age(dev, counter);
4654         if (rte_atomic16_cmpset((volatile uint16_t *)
4655                         &age_param->state,
4656                         AGE_CANDIDATE, AGE_FREE)
4657                         != AGE_CANDIDATE) {
4658                 /**
4659                  * We need the lock even it is age timeout,
4660                  * since counter may still in process.
4661                  */
4662                 rte_spinlock_lock(&age_info->aged_sl);
4663                 TAILQ_REMOVE(&age_info->aged_counters, cnt, next);
4664                 rte_spinlock_unlock(&age_info->aged_sl);
4665         }
4666         rte_atomic16_set(&age_param->state, AGE_FREE);
4667 }
4668 /**
4669  * Release a flow counter.
4670  *
4671  * @param[in] dev
4672  *   Pointer to the Ethernet device structure.
4673  * @param[in] counter
4674  *   Index to the counter handler.
4675  */
4676 static void
4677 flow_dv_counter_release(struct rte_eth_dev *dev, uint32_t counter)
4678 {
4679         struct mlx5_flow_counter_pool *pool = NULL;
4680         struct mlx5_flow_counter *cnt;
4681         struct mlx5_flow_counter_ext *cnt_ext = NULL;
4682
4683         if (!counter)
4684                 return;
4685         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
4686         MLX5_ASSERT(pool);
4687         if (counter < MLX5_CNT_BATCH_OFFSET) {
4688                 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt);
4689                 if (cnt_ext && --cnt_ext->ref_cnt)
4690                         return;
4691         }
4692         if (IS_AGE_POOL(pool))
4693                 flow_dv_counter_remove_from_age(dev, counter, cnt);
4694         /* Put the counter in the end - the last updated one. */
4695         TAILQ_INSERT_TAIL(&pool->counters, cnt, next);
4696         /*
4697          * Counters released between query trigger and handler need
4698          * to wait the next round of query. Since the packets arrive
4699          * in the gap period will not be taken into account to the
4700          * old counter.
4701          */
4702         cnt->query_gen = rte_atomic64_read(&pool->start_query_gen);
4703 }
4704
4705 /**
4706  * Verify the @p attributes will be correctly understood by the NIC and store
4707  * them in the @p flow if everything is correct.
4708  *
4709  * @param[in] dev
4710  *   Pointer to dev struct.
4711  * @param[in] attributes
4712  *   Pointer to flow attributes
4713  * @param[in] external
4714  *   This flow rule is created by request external to PMD.
4715  * @param[out] error
4716  *   Pointer to error structure.
4717  *
4718  * @return
4719  *   - 0 on success and non root table.
4720  *   - 1 on success and root table.
4721  *   - a negative errno value otherwise and rte_errno is set.
4722  */
4723 static int
4724 flow_dv_validate_attributes(struct rte_eth_dev *dev,
4725                             const struct rte_flow_attr *attributes,
4726                             bool external __rte_unused,
4727                             struct rte_flow_error *error)
4728 {
4729         struct mlx5_priv *priv = dev->data->dev_private;
4730         uint32_t priority_max = priv->config.flow_prio - 1;
4731         int ret = 0;
4732
4733 #ifndef HAVE_MLX5DV_DR
4734         if (attributes->group)
4735                 return rte_flow_error_set(error, ENOTSUP,
4736                                           RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
4737                                           NULL,
4738                                           "groups are not supported");
4739 #else
4740         uint32_t table = 0;
4741
4742         ret = mlx5_flow_group_to_table(attributes, external,
4743                                        attributes->group, !!priv->fdb_def_rule,
4744                                        &table, error);
4745         if (ret)
4746                 return ret;
4747         if (!table)
4748                 ret = MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
4749 #endif
4750         if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
4751             attributes->priority >= priority_max)
4752                 return rte_flow_error_set(error, ENOTSUP,
4753                                           RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
4754                                           NULL,
4755                                           "priority out of range");
4756         if (attributes->transfer) {
4757                 if (!priv->config.dv_esw_en)
4758                         return rte_flow_error_set
4759                                 (error, ENOTSUP,
4760                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4761                                  "E-Switch dr is not supported");
4762                 if (!(priv->representor || priv->master))
4763                         return rte_flow_error_set
4764                                 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4765                                  NULL, "E-Switch configuration can only be"
4766                                  " done by a master or a representor device");
4767                 if (attributes->egress)
4768                         return rte_flow_error_set
4769                                 (error, ENOTSUP,
4770                                  RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
4771                                  "egress is not supported");
4772         }
4773         if (!(attributes->egress ^ attributes->ingress))
4774                 return rte_flow_error_set(error, ENOTSUP,
4775                                           RTE_FLOW_ERROR_TYPE_ATTR, NULL,
4776                                           "must specify exactly one of "
4777                                           "ingress or egress");
4778         return ret;
4779 }
4780
4781 /**
4782  * Internal validation function. For validating both actions and items.
4783  *
4784  * @param[in] dev
4785  *   Pointer to the rte_eth_dev structure.
4786  * @param[in] attr
4787  *   Pointer to the flow attributes.
4788  * @param[in] items
4789  *   Pointer to the list of items.
4790  * @param[in] actions
4791  *   Pointer to the list of actions.
4792  * @param[in] external
4793  *   This flow rule is created by request external to PMD.
4794  * @param[in] hairpin
4795  *   Number of hairpin TX actions, 0 means classic flow.
4796  * @param[out] error
4797  *   Pointer to the error structure.
4798  *
4799  * @return
4800  *   0 on success, a negative errno value otherwise and rte_errno is set.
4801  */
4802 static int
4803 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
4804                  const struct rte_flow_item items[],
4805                  const struct rte_flow_action actions[],
4806                  bool external, int hairpin, struct rte_flow_error *error)
4807 {
4808         int ret;
4809         uint64_t action_flags = 0;
4810         uint64_t item_flags = 0;
4811         uint64_t last_item = 0;
4812         uint8_t next_protocol = 0xff;
4813         uint16_t ether_type = 0;
4814         int actions_n = 0;
4815         uint8_t item_ipv6_proto = 0;
4816         const struct rte_flow_item *gre_item = NULL;
4817         const struct rte_flow_action_raw_decap *decap;
4818         const struct rte_flow_action_raw_encap *encap;
4819         const struct rte_flow_action_rss *rss;
4820         const struct rte_flow_item_tcp nic_tcp_mask = {
4821                 .hdr = {
4822                         .tcp_flags = 0xFF,
4823                         .src_port = RTE_BE16(UINT16_MAX),
4824                         .dst_port = RTE_BE16(UINT16_MAX),
4825                 }
4826         };
4827         const struct rte_flow_item_ipv4 nic_ipv4_mask = {
4828                 .hdr = {
4829                         .src_addr = RTE_BE32(0xffffffff),
4830                         .dst_addr = RTE_BE32(0xffffffff),
4831                         .type_of_service = 0xff,
4832                         .next_proto_id = 0xff,
4833                         .time_to_live = 0xff,
4834                 },
4835         };
4836         const struct rte_flow_item_ipv6 nic_ipv6_mask = {
4837                 .hdr = {
4838                         .src_addr =
4839                         "\xff\xff\xff\xff\xff\xff\xff\xff"
4840                         "\xff\xff\xff\xff\xff\xff\xff\xff",
4841                         .dst_addr =
4842                         "\xff\xff\xff\xff\xff\xff\xff\xff"
4843                         "\xff\xff\xff\xff\xff\xff\xff\xff",
4844                         .vtc_flow = RTE_BE32(0xffffffff),
4845                         .proto = 0xff,
4846                         .hop_limits = 0xff,
4847                 },
4848         };
4849         struct mlx5_priv *priv = dev->data->dev_private;
4850         struct mlx5_dev_config *dev_conf = &priv->config;
4851         uint16_t queue_index = 0xFFFF;
4852         const struct rte_flow_item_vlan *vlan_m = NULL;
4853         int16_t rw_act_num = 0;
4854         uint64_t is_root;
4855
4856         if (items == NULL)
4857                 return -1;
4858         ret = flow_dv_validate_attributes(dev, attr, external, error);
4859         if (ret < 0)
4860                 return ret;
4861         is_root = (uint64_t)ret;
4862         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
4863                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
4864                 int type = items->type;
4865
4866                 switch (type) {
4867                 case RTE_FLOW_ITEM_TYPE_VOID:
4868                         break;
4869                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
4870                         ret = flow_dv_validate_item_port_id
4871                                         (dev, items, attr, item_flags, error);
4872                         if (ret < 0)
4873                                 return ret;
4874                         last_item = MLX5_FLOW_ITEM_PORT_ID;
4875                         break;
4876                 case RTE_FLOW_ITEM_TYPE_ETH:
4877                         ret = mlx5_flow_validate_item_eth(items, item_flags,
4878                                                           error);
4879                         if (ret < 0)
4880                                 return ret;
4881                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
4882                                              MLX5_FLOW_LAYER_OUTER_L2;
4883                         if (items->mask != NULL && items->spec != NULL) {
4884                                 ether_type =
4885                                         ((const struct rte_flow_item_eth *)
4886                                          items->spec)->type;
4887                                 ether_type &=
4888                                         ((const struct rte_flow_item_eth *)
4889                                          items->mask)->type;
4890                                 ether_type = rte_be_to_cpu_16(ether_type);
4891                         } else {
4892                                 ether_type = 0;
4893                         }
4894                         break;
4895                 case RTE_FLOW_ITEM_TYPE_VLAN:
4896                         ret = flow_dv_validate_item_vlan(items, item_flags,
4897                                                          dev, error);
4898                         if (ret < 0)
4899                                 return ret;
4900                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
4901                                              MLX5_FLOW_LAYER_OUTER_VLAN;
4902                         if (items->mask != NULL && items->spec != NULL) {
4903                                 ether_type =
4904                                         ((const struct rte_flow_item_vlan *)
4905                                          items->spec)->inner_type;
4906                                 ether_type &=
4907                                         ((const struct rte_flow_item_vlan *)
4908                                          items->mask)->inner_type;
4909                                 ether_type = rte_be_to_cpu_16(ether_type);
4910                         } else {
4911                                 ether_type = 0;
4912                         }
4913                         /* Store outer VLAN mask for of_push_vlan action. */
4914                         if (!tunnel)
4915                                 vlan_m = items->mask;
4916                         break;
4917                 case RTE_FLOW_ITEM_TYPE_IPV4:
4918                         mlx5_flow_tunnel_ip_check(items, next_protocol,
4919                                                   &item_flags, &tunnel);
4920                         ret = mlx5_flow_validate_item_ipv4(items, item_flags,
4921                                                            last_item,
4922                                                            ether_type,
4923                                                            &nic_ipv4_mask,
4924                                                            error);
4925                         if (ret < 0)
4926                                 return ret;
4927                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
4928                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
4929                         if (items->mask != NULL &&
4930                             ((const struct rte_flow_item_ipv4 *)
4931                              items->mask)->hdr.next_proto_id) {
4932                                 next_protocol =
4933                                         ((const struct rte_flow_item_ipv4 *)
4934                                          (items->spec))->hdr.next_proto_id;
4935                                 next_protocol &=
4936                                         ((const struct rte_flow_item_ipv4 *)
4937                                          (items->mask))->hdr.next_proto_id;
4938                         } else {
4939                                 /* Reset for inner layer. */
4940                                 next_protocol = 0xff;
4941                         }
4942                         break;
4943                 case RTE_FLOW_ITEM_TYPE_IPV6:
4944                         mlx5_flow_tunnel_ip_check(items, next_protocol,
4945                                                   &item_flags, &tunnel);
4946                         ret = mlx5_flow_validate_item_ipv6(items, item_flags,
4947                                                            last_item,
4948                                                            ether_type,
4949                                                            &nic_ipv6_mask,
4950                                                            error);
4951                         if (ret < 0)
4952                                 return ret;
4953                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
4954                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
4955                         if (items->mask != NULL &&
4956                             ((const struct rte_flow_item_ipv6 *)
4957                              items->mask)->hdr.proto) {
4958                                 item_ipv6_proto =
4959                                         ((const struct rte_flow_item_ipv6 *)
4960                                          items->spec)->hdr.proto;
4961                                 next_protocol =
4962                                         ((const struct rte_flow_item_ipv6 *)
4963                                          items->spec)->hdr.proto;
4964                                 next_protocol &=
4965                                         ((const struct rte_flow_item_ipv6 *)
4966                                          items->mask)->hdr.proto;
4967                         } else {
4968                                 /* Reset for inner layer. */
4969                                 next_protocol = 0xff;
4970                         }
4971                         break;
4972                 case RTE_FLOW_ITEM_TYPE_TCP:
4973                         ret = mlx5_flow_validate_item_tcp
4974                                                 (items, item_flags,
4975                                                  next_protocol,
4976                                                  &nic_tcp_mask,
4977                                                  error);
4978                         if (ret < 0)
4979                                 return ret;
4980                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
4981                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
4982                         break;
4983                 case RTE_FLOW_ITEM_TYPE_UDP:
4984                         ret = mlx5_flow_validate_item_udp(items, item_flags,
4985                                                           next_protocol,
4986                                                           error);
4987                         if (ret < 0)
4988                                 return ret;
4989                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
4990                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
4991                         break;
4992                 case RTE_FLOW_ITEM_TYPE_GRE:
4993                         ret = mlx5_flow_validate_item_gre(items, item_flags,
4994                                                           next_protocol, error);
4995                         if (ret < 0)
4996                                 return ret;
4997                         gre_item = items;
4998                         last_item = MLX5_FLOW_LAYER_GRE;
4999                         break;
5000                 case RTE_FLOW_ITEM_TYPE_NVGRE:
5001                         ret = mlx5_flow_validate_item_nvgre(items, item_flags,
5002                                                             next_protocol,
5003                                                             error);
5004                         if (ret < 0)
5005                                 return ret;
5006                         last_item = MLX5_FLOW_LAYER_NVGRE;
5007                         break;
5008                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
5009                         ret = mlx5_flow_validate_item_gre_key
5010                                 (items, item_flags, gre_item, error);
5011                         if (ret < 0)
5012                                 return ret;
5013                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
5014                         break;
5015                 case RTE_FLOW_ITEM_TYPE_VXLAN:
5016                         ret = mlx5_flow_validate_item_vxlan(items, item_flags,
5017                                                             error);
5018                         if (ret < 0)
5019                                 return ret;
5020                         last_item = MLX5_FLOW_LAYER_VXLAN;
5021                         break;
5022                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
5023                         ret = mlx5_flow_validate_item_vxlan_gpe(items,
5024                                                                 item_flags, dev,
5025                                                                 error);
5026                         if (ret < 0)
5027                                 return ret;
5028                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
5029                         break;
5030                 case RTE_FLOW_ITEM_TYPE_GENEVE:
5031                         ret = mlx5_flow_validate_item_geneve(items,
5032                                                              item_flags, dev,
5033                                                              error);
5034                         if (ret < 0)
5035                                 return ret;
5036                         last_item = MLX5_FLOW_LAYER_GENEVE;
5037                         break;
5038                 case RTE_FLOW_ITEM_TYPE_MPLS:
5039                         ret = mlx5_flow_validate_item_mpls(dev, items,
5040                                                            item_flags,
5041                                                            last_item, error);
5042                         if (ret < 0)
5043                                 return ret;
5044                         last_item = MLX5_FLOW_LAYER_MPLS;
5045                         break;
5046
5047                 case RTE_FLOW_ITEM_TYPE_MARK:
5048                         ret = flow_dv_validate_item_mark(dev, items, attr,
5049                                                          error);
5050                         if (ret < 0)
5051                                 return ret;
5052                         last_item = MLX5_FLOW_ITEM_MARK;
5053                         break;
5054                 case RTE_FLOW_ITEM_TYPE_META:
5055                         ret = flow_dv_validate_item_meta(dev, items, attr,
5056                                                          error);
5057                         if (ret < 0)
5058                                 return ret;
5059                         last_item = MLX5_FLOW_ITEM_METADATA;
5060                         break;
5061                 case RTE_FLOW_ITEM_TYPE_ICMP:
5062                         ret = mlx5_flow_validate_item_icmp(items, item_flags,
5063                                                            next_protocol,
5064                                                            error);
5065                         if (ret < 0)
5066                                 return ret;
5067                         last_item = MLX5_FLOW_LAYER_ICMP;
5068                         break;
5069                 case RTE_FLOW_ITEM_TYPE_ICMP6:
5070                         ret = mlx5_flow_validate_item_icmp6(items, item_flags,
5071                                                             next_protocol,
5072                                                             error);
5073                         if (ret < 0)
5074                                 return ret;
5075                         item_ipv6_proto = IPPROTO_ICMPV6;
5076                         last_item = MLX5_FLOW_LAYER_ICMP6;
5077                         break;
5078                 case RTE_FLOW_ITEM_TYPE_TAG:
5079                         ret = flow_dv_validate_item_tag(dev, items,
5080                                                         attr, error);
5081                         if (ret < 0)
5082                                 return ret;
5083                         last_item = MLX5_FLOW_ITEM_TAG;
5084                         break;
5085                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
5086                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
5087                         break;
5088                 case RTE_FLOW_ITEM_TYPE_GTP:
5089                         ret = flow_dv_validate_item_gtp(dev, items, item_flags,
5090                                                         error);
5091                         if (ret < 0)
5092                                 return ret;
5093                         last_item = MLX5_FLOW_LAYER_GTP;
5094                         break;
5095                 default:
5096                         return rte_flow_error_set(error, ENOTSUP,
5097                                                   RTE_FLOW_ERROR_TYPE_ITEM,
5098                                                   NULL, "item not supported");
5099                 }
5100                 item_flags |= last_item;
5101         }
5102         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
5103                 int type = actions->type;
5104                 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
5105                         return rte_flow_error_set(error, ENOTSUP,
5106                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5107                                                   actions, "too many actions");
5108                 switch (type) {
5109                 case RTE_FLOW_ACTION_TYPE_VOID:
5110                         break;
5111                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5112                         ret = flow_dv_validate_action_port_id(dev,
5113                                                               action_flags,
5114                                                               actions,
5115                                                               attr,
5116                                                               error);
5117                         if (ret)
5118                                 return ret;
5119                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5120                         ++actions_n;
5121                         break;
5122                 case RTE_FLOW_ACTION_TYPE_FLAG:
5123                         ret = flow_dv_validate_action_flag(dev, action_flags,
5124                                                            attr, error);
5125                         if (ret < 0)
5126                                 return ret;
5127                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
5128                                 /* Count all modify-header actions as one. */
5129                                 if (!(action_flags &
5130                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
5131                                         ++actions_n;
5132                                 action_flags |= MLX5_FLOW_ACTION_FLAG |
5133                                                 MLX5_FLOW_ACTION_MARK_EXT;
5134                         } else {
5135                                 action_flags |= MLX5_FLOW_ACTION_FLAG;
5136                                 ++actions_n;
5137                         }
5138                         rw_act_num += MLX5_ACT_NUM_SET_MARK;
5139                         break;
5140                 case RTE_FLOW_ACTION_TYPE_MARK:
5141                         ret = flow_dv_validate_action_mark(dev, actions,
5142                                                            action_flags,
5143                                                            attr, error);
5144                         if (ret < 0)
5145                                 return ret;
5146                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
5147                                 /* Count all modify-header actions as one. */
5148                                 if (!(action_flags &
5149                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
5150                                         ++actions_n;
5151                                 action_flags |= MLX5_FLOW_ACTION_MARK |
5152                                                 MLX5_FLOW_ACTION_MARK_EXT;
5153                         } else {
5154                                 action_flags |= MLX5_FLOW_ACTION_MARK;
5155                                 ++actions_n;
5156                         }
5157                         rw_act_num += MLX5_ACT_NUM_SET_MARK;
5158                         break;
5159                 case RTE_FLOW_ACTION_TYPE_SET_META:
5160                         ret = flow_dv_validate_action_set_meta(dev, actions,
5161                                                                action_flags,
5162                                                                attr, error);
5163                         if (ret < 0)
5164                                 return ret;
5165                         /* Count all modify-header actions as one action. */
5166                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5167                                 ++actions_n;
5168                         action_flags |= MLX5_FLOW_ACTION_SET_META;
5169                         rw_act_num += MLX5_ACT_NUM_SET_META;
5170                         break;
5171                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
5172                         ret = flow_dv_validate_action_set_tag(dev, actions,
5173                                                               action_flags,
5174                                                               attr, error);
5175                         if (ret < 0)
5176                                 return ret;
5177                         /* Count all modify-header actions as one action. */
5178                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5179                                 ++actions_n;
5180                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
5181                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
5182                         break;
5183                 case RTE_FLOW_ACTION_TYPE_DROP:
5184                         ret = mlx5_flow_validate_action_drop(action_flags,
5185                                                              attr, error);
5186                         if (ret < 0)
5187                                 return ret;
5188                         action_flags |= MLX5_FLOW_ACTION_DROP;
5189                         ++actions_n;
5190                         break;
5191                 case RTE_FLOW_ACTION_TYPE_QUEUE:
5192                         ret = mlx5_flow_validate_action_queue(actions,
5193                                                               action_flags, dev,
5194                                                               attr, error);
5195                         if (ret < 0)
5196                                 return ret;
5197                         queue_index = ((const struct rte_flow_action_queue *)
5198                                                         (actions->conf))->index;
5199                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
5200                         ++actions_n;
5201                         break;
5202                 case RTE_FLOW_ACTION_TYPE_RSS:
5203                         rss = actions->conf;
5204                         ret = mlx5_flow_validate_action_rss(actions,
5205                                                             action_flags, dev,
5206                                                             attr, item_flags,
5207                                                             error);
5208                         if (ret < 0)
5209                                 return ret;
5210                         if (rss != NULL && rss->queue_num)
5211                                 queue_index = rss->queue[0];
5212                         action_flags |= MLX5_FLOW_ACTION_RSS;
5213                         ++actions_n;
5214                         break;
5215                 case RTE_FLOW_ACTION_TYPE_COUNT:
5216                         ret = flow_dv_validate_action_count(dev, error);
5217                         if (ret < 0)
5218                                 return ret;
5219                         action_flags |= MLX5_FLOW_ACTION_COUNT;
5220                         ++actions_n;
5221                         break;
5222                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
5223                         if (flow_dv_validate_action_pop_vlan(dev,
5224                                                              action_flags,
5225                                                              actions,
5226                                                              item_flags, attr,
5227                                                              error))
5228                                 return -rte_errno;
5229                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
5230                         ++actions_n;
5231                         break;
5232                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
5233                         ret = flow_dv_validate_action_push_vlan(dev,
5234                                                                 action_flags,
5235                                                                 vlan_m,
5236                                                                 actions, attr,
5237                                                                 error);
5238                         if (ret < 0)
5239                                 return ret;
5240                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
5241                         ++actions_n;
5242                         break;
5243                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
5244                         ret = flow_dv_validate_action_set_vlan_pcp
5245                                                 (action_flags, actions, error);
5246                         if (ret < 0)
5247                                 return ret;
5248                         /* Count PCP with push_vlan command. */
5249                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
5250                         break;
5251                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
5252                         ret = flow_dv_validate_action_set_vlan_vid
5253                                                 (item_flags, action_flags,
5254                                                  actions, error);
5255                         if (ret < 0)
5256                                 return ret;
5257                         /* Count VID with push_vlan command. */
5258                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
5259                         rw_act_num += MLX5_ACT_NUM_MDF_VID;
5260                         break;
5261                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5262                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5263                         ret = flow_dv_validate_action_l2_encap(dev,
5264                                                                action_flags,
5265                                                                actions, attr,
5266                                                                error);
5267                         if (ret < 0)
5268                                 return ret;
5269                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
5270                         ++actions_n;
5271                         break;
5272                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
5273                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
5274                         ret = flow_dv_validate_action_decap(dev, action_flags,
5275                                                             attr, error);
5276                         if (ret < 0)
5277                                 return ret;
5278                         action_flags |= MLX5_FLOW_ACTION_DECAP;
5279                         ++actions_n;
5280                         break;
5281                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5282                         ret = flow_dv_validate_action_raw_encap_decap
5283                                 (dev, NULL, actions->conf, attr, &action_flags,
5284                                  &actions_n, error);
5285                         if (ret < 0)
5286                                 return ret;
5287                         break;
5288                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
5289                         decap = actions->conf;
5290                         while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
5291                                 ;
5292                         if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
5293                                 encap = NULL;
5294                                 actions--;
5295                         } else {
5296                                 encap = actions->conf;
5297                         }
5298                         ret = flow_dv_validate_action_raw_encap_decap
5299                                            (dev,
5300                                             decap ? decap : &empty_decap, encap,
5301                                             attr, &action_flags, &actions_n,
5302                                             error);
5303                         if (ret < 0)
5304                                 return ret;
5305                         break;
5306                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
5307                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
5308                         ret = flow_dv_validate_action_modify_mac(action_flags,
5309                                                                  actions,
5310                                                                  item_flags,
5311                                                                  error);
5312                         if (ret < 0)
5313                                 return ret;
5314                         /* Count all modify-header actions as one action. */
5315                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5316                                 ++actions_n;
5317                         action_flags |= actions->type ==
5318                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
5319                                                 MLX5_FLOW_ACTION_SET_MAC_SRC :
5320                                                 MLX5_FLOW_ACTION_SET_MAC_DST;
5321                         /*
5322                          * Even if the source and destination MAC addresses have
5323                          * overlap in the header with 4B alignment, the convert
5324                          * function will handle them separately and 4 SW actions
5325                          * will be created. And 2 actions will be added each
5326                          * time no matter how many bytes of address will be set.
5327                          */
5328                         rw_act_num += MLX5_ACT_NUM_MDF_MAC;
5329                         break;
5330                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
5331                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
5332                         ret = flow_dv_validate_action_modify_ipv4(action_flags,
5333                                                                   actions,
5334                                                                   item_flags,
5335                                                                   error);
5336                         if (ret < 0)
5337                                 return ret;
5338                         /* Count all modify-header actions as one action. */
5339                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5340                                 ++actions_n;
5341                         action_flags |= actions->type ==
5342                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
5343                                                 MLX5_FLOW_ACTION_SET_IPV4_SRC :
5344                                                 MLX5_FLOW_ACTION_SET_IPV4_DST;
5345                         rw_act_num += MLX5_ACT_NUM_MDF_IPV4;
5346                         break;
5347                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
5348                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
5349                         ret = flow_dv_validate_action_modify_ipv6(action_flags,
5350                                                                   actions,
5351                                                                   item_flags,
5352                                                                   error);
5353                         if (ret < 0)
5354                                 return ret;
5355                         if (item_ipv6_proto == IPPROTO_ICMPV6)
5356                                 return rte_flow_error_set(error, ENOTSUP,
5357                                         RTE_FLOW_ERROR_TYPE_ACTION,
5358                                         actions,
5359                                         "Can't change header "
5360                                         "with ICMPv6 proto");
5361                         /* Count all modify-header actions as one action. */
5362                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5363                                 ++actions_n;
5364                         action_flags |= actions->type ==
5365                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
5366                                                 MLX5_FLOW_ACTION_SET_IPV6_SRC :
5367                                                 MLX5_FLOW_ACTION_SET_IPV6_DST;
5368                         rw_act_num += MLX5_ACT_NUM_MDF_IPV6;
5369                         break;
5370                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
5371                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
5372                         ret = flow_dv_validate_action_modify_tp(action_flags,
5373                                                                 actions,
5374                                                                 item_flags,
5375                                                                 error);
5376                         if (ret < 0)
5377                                 return ret;
5378                         /* Count all modify-header actions as one action. */
5379                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5380                                 ++actions_n;
5381                         action_flags |= actions->type ==
5382                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
5383                                                 MLX5_FLOW_ACTION_SET_TP_SRC :
5384                                                 MLX5_FLOW_ACTION_SET_TP_DST;
5385                         rw_act_num += MLX5_ACT_NUM_MDF_PORT;
5386                         break;
5387                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
5388                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
5389                         ret = flow_dv_validate_action_modify_ttl(action_flags,
5390                                                                  actions,
5391                                                                  item_flags,
5392                                                                  error);
5393                         if (ret < 0)
5394                                 return ret;
5395                         /* Count all modify-header actions as one action. */
5396                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5397                                 ++actions_n;
5398                         action_flags |= actions->type ==
5399                                         RTE_FLOW_ACTION_TYPE_SET_TTL ?
5400                                                 MLX5_FLOW_ACTION_SET_TTL :
5401                                                 MLX5_FLOW_ACTION_DEC_TTL;
5402                         rw_act_num += MLX5_ACT_NUM_MDF_TTL;
5403                         break;
5404                 case RTE_FLOW_ACTION_TYPE_JUMP:
5405                         ret = flow_dv_validate_action_jump(actions,
5406                                                            action_flags,
5407                                                            attr, external,
5408                                                            error);
5409                         if (ret)
5410                                 return ret;
5411                         ++actions_n;
5412                         action_flags |= MLX5_FLOW_ACTION_JUMP;
5413                         break;
5414                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
5415                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
5416                         ret = flow_dv_validate_action_modify_tcp_seq
5417                                                                 (action_flags,
5418                                                                  actions,
5419                                                                  item_flags,
5420                                                                  error);
5421                         if (ret < 0)
5422                                 return ret;
5423                         /* Count all modify-header actions as one action. */
5424                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5425                                 ++actions_n;
5426                         action_flags |= actions->type ==
5427                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
5428                                                 MLX5_FLOW_ACTION_INC_TCP_SEQ :
5429                                                 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
5430                         rw_act_num += MLX5_ACT_NUM_MDF_TCPSEQ;
5431                         break;
5432                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
5433                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
5434                         ret = flow_dv_validate_action_modify_tcp_ack
5435                                                                 (action_flags,
5436                                                                  actions,
5437                                                                  item_flags,
5438                                                                  error);
5439                         if (ret < 0)
5440                                 return ret;
5441                         /* Count all modify-header actions as one action. */
5442                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5443                                 ++actions_n;
5444                         action_flags |= actions->type ==
5445                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
5446                                                 MLX5_FLOW_ACTION_INC_TCP_ACK :
5447                                                 MLX5_FLOW_ACTION_DEC_TCP_ACK;
5448                         rw_act_num += MLX5_ACT_NUM_MDF_TCPACK;
5449                         break;
5450                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
5451                         break;
5452                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
5453                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
5454                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
5455                         break;
5456                 case RTE_FLOW_ACTION_TYPE_METER:
5457                         ret = mlx5_flow_validate_action_meter(dev,
5458                                                               action_flags,
5459                                                               actions, attr,
5460                                                               error);
5461                         if (ret < 0)
5462                                 return ret;
5463                         action_flags |= MLX5_FLOW_ACTION_METER;
5464                         ++actions_n;
5465                         /* Meter action will add one more TAG action. */
5466                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
5467                         break;
5468                 case RTE_FLOW_ACTION_TYPE_AGE:
5469                         ret = flow_dv_validate_action_age(action_flags,
5470                                                           actions, dev,
5471                                                           error);
5472                         if (ret < 0)
5473                                 return ret;
5474                         action_flags |= MLX5_FLOW_ACTION_AGE;
5475                         ++actions_n;
5476                         break;
5477                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
5478                         ret = flow_dv_validate_action_modify_ipv4_dscp
5479                                                          (action_flags,
5480                                                           actions,
5481                                                           item_flags,
5482                                                           error);
5483                         if (ret < 0)
5484                                 return ret;
5485                         /* Count all modify-header actions as one action. */
5486                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5487                                 ++actions_n;
5488                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
5489                         rw_act_num += MLX5_ACT_NUM_SET_DSCP;
5490                         break;
5491                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
5492                         ret = flow_dv_validate_action_modify_ipv6_dscp
5493                                                                 (action_flags,
5494                                                                  actions,
5495                                                                  item_flags,
5496                                                                  error);
5497                         if (ret < 0)
5498                                 return ret;
5499                         /* Count all modify-header actions as one action. */
5500                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5501                                 ++actions_n;
5502                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
5503                         rw_act_num += MLX5_ACT_NUM_SET_DSCP;
5504                         break;
5505                 default:
5506                         return rte_flow_error_set(error, ENOTSUP,
5507                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5508                                                   actions,
5509                                                   "action not supported");
5510                 }
5511         }
5512         /*
5513          * Validate the drop action mutual exclusion with other actions.
5514          * Drop action is mutually-exclusive with any other action, except for
5515          * Count action.
5516          */
5517         if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
5518             (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
5519                 return rte_flow_error_set(error, EINVAL,
5520                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5521                                           "Drop action is mutually-exclusive "
5522                                           "with any other action, except for "
5523                                           "Count action");
5524         /* Eswitch has few restrictions on using items and actions */
5525         if (attr->transfer) {
5526                 if (!mlx5_flow_ext_mreg_supported(dev) &&
5527                     action_flags & MLX5_FLOW_ACTION_FLAG)
5528                         return rte_flow_error_set(error, ENOTSUP,
5529                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5530                                                   NULL,
5531                                                   "unsupported action FLAG");
5532                 if (!mlx5_flow_ext_mreg_supported(dev) &&
5533                     action_flags & MLX5_FLOW_ACTION_MARK)
5534                         return rte_flow_error_set(error, ENOTSUP,
5535                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5536                                                   NULL,
5537                                                   "unsupported action MARK");
5538                 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
5539                         return rte_flow_error_set(error, ENOTSUP,
5540                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5541                                                   NULL,
5542                                                   "unsupported action QUEUE");
5543                 if (action_flags & MLX5_FLOW_ACTION_RSS)
5544                         return rte_flow_error_set(error, ENOTSUP,
5545                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5546                                                   NULL,
5547                                                   "unsupported action RSS");
5548                 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
5549                         return rte_flow_error_set(error, EINVAL,
5550                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5551                                                   actions,
5552                                                   "no fate action is found");
5553         } else {
5554                 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
5555                         return rte_flow_error_set(error, EINVAL,
5556                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5557                                                   actions,
5558                                                   "no fate action is found");
5559         }
5560         /* Continue validation for Xcap actions.*/
5561         if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) && (queue_index == 0xFFFF ||
5562             mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
5563                 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
5564                     MLX5_FLOW_XCAP_ACTIONS)
5565                         return rte_flow_error_set(error, ENOTSUP,
5566                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5567                                                   NULL, "encap and decap "
5568                                                   "combination aren't supported");
5569                 if (!attr->transfer && attr->ingress && (action_flags &
5570                                                         MLX5_FLOW_ACTION_ENCAP))
5571                         return rte_flow_error_set(error, ENOTSUP,
5572                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5573                                                   NULL, "encap is not supported"
5574                                                   " for ingress traffic");
5575         }
5576         /* Hairpin flow will add one more TAG action. */
5577         if (hairpin > 0)
5578                 rw_act_num += MLX5_ACT_NUM_SET_TAG;
5579         /* extra metadata enabled: one more TAG action will be add. */
5580         if (dev_conf->dv_flow_en &&
5581             dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
5582             mlx5_flow_ext_mreg_supported(dev))
5583                 rw_act_num += MLX5_ACT_NUM_SET_TAG;
5584         if ((uint32_t)rw_act_num >
5585                         flow_dv_modify_hdr_action_max(dev, is_root)) {
5586                 return rte_flow_error_set(error, ENOTSUP,
5587                                           RTE_FLOW_ERROR_TYPE_ACTION,
5588                                           NULL, "too many header modify"
5589                                           " actions to support");
5590         }
5591         return 0;
5592 }
5593
5594 /**
5595  * Internal preparation function. Allocates the DV flow size,
5596  * this size is constant.
5597  *
5598  * @param[in] dev
5599  *   Pointer to the rte_eth_dev structure.
5600  * @param[in] attr
5601  *   Pointer to the flow attributes.
5602  * @param[in] items
5603  *   Pointer to the list of items.
5604  * @param[in] actions
5605  *   Pointer to the list of actions.
5606  * @param[out] error
5607  *   Pointer to the error structure.
5608  *
5609  * @return
5610  *   Pointer to mlx5_flow object on success,
5611  *   otherwise NULL and rte_errno is set.
5612  */
5613 static struct mlx5_flow *
5614 flow_dv_prepare(struct rte_eth_dev *dev,
5615                 const struct rte_flow_attr *attr __rte_unused,
5616                 const struct rte_flow_item items[] __rte_unused,
5617                 const struct rte_flow_action actions[] __rte_unused,
5618                 struct rte_flow_error *error)
5619 {
5620         uint32_t handle_idx = 0;
5621         struct mlx5_flow *dev_flow;
5622         struct mlx5_flow_handle *dev_handle;
5623         struct mlx5_priv *priv = dev->data->dev_private;
5624
5625         /* In case of corrupting the memory. */
5626         if (priv->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
5627                 rte_flow_error_set(error, ENOSPC,
5628                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5629                                    "not free temporary device flow");
5630                 return NULL;
5631         }
5632         dev_handle = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
5633                                    &handle_idx);
5634         if (!dev_handle) {
5635                 rte_flow_error_set(error, ENOMEM,
5636                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5637                                    "not enough memory to create flow handle");
5638                 return NULL;
5639         }
5640         /* No multi-thread supporting. */
5641         dev_flow = &((struct mlx5_flow *)priv->inter_flows)[priv->flow_idx++];
5642         dev_flow->handle = dev_handle;
5643         dev_flow->handle_idx = handle_idx;
5644         dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);
5645         /*
5646          * The matching value needs to be cleared to 0 before using. In the
5647          * past, it will be automatically cleared when using rte_*alloc
5648          * API. The time consumption will be almost the same as before.
5649          */
5650         memset(dev_flow->dv.value.buf, 0, MLX5_ST_SZ_BYTES(fte_match_param));
5651         dev_flow->ingress = attr->ingress;
5652         dev_flow->dv.transfer = attr->transfer;
5653         return dev_flow;
5654 }
5655
5656 #ifdef RTE_LIBRTE_MLX5_DEBUG
5657 /**
5658  * Sanity check for match mask and value. Similar to check_valid_spec() in
5659  * kernel driver. If unmasked bit is present in value, it returns failure.
5660  *
5661  * @param match_mask
5662  *   pointer to match mask buffer.
5663  * @param match_value
5664  *   pointer to match value buffer.
5665  *
5666  * @return
5667  *   0 if valid, -EINVAL otherwise.
5668  */
5669 static int
5670 flow_dv_check_valid_spec(void *match_mask, void *match_value)
5671 {
5672         uint8_t *m = match_mask;
5673         uint8_t *v = match_value;
5674         unsigned int i;
5675
5676         for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
5677                 if (v[i] & ~m[i]) {
5678                         DRV_LOG(ERR,
5679                                 "match_value differs from match_criteria"
5680                                 " %p[%u] != %p[%u]",
5681                                 match_value, i, match_mask, i);
5682                         return -EINVAL;
5683                 }
5684         }
5685         return 0;
5686 }
5687 #endif
5688
5689 /**
5690  * Add match of ip_version.
5691  *
5692  * @param[in] group
5693  *   Flow group.
5694  * @param[in] headers_v
5695  *   Values header pointer.
5696  * @param[in] headers_m
5697  *   Masks header pointer.
5698  * @param[in] ip_version
5699  *   The IP version to set.
5700  */
5701 static inline void
5702 flow_dv_set_match_ip_version(uint32_t group,
5703                              void *headers_v,
5704                              void *headers_m,
5705                              uint8_t ip_version)
5706 {
5707         if (group == 0)
5708                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
5709         else
5710                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version,
5711                          ip_version);
5712         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, ip_version);
5713         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, 0);
5714         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype, 0);
5715 }
5716
5717 /**
5718  * Add Ethernet item to matcher and to the value.
5719  *
5720  * @param[in, out] matcher
5721  *   Flow matcher.
5722  * @param[in, out] key
5723  *   Flow matcher value.
5724  * @param[in] item
5725  *   Flow pattern to translate.
5726  * @param[in] inner
5727  *   Item is inner pattern.
5728  */
5729 static void
5730 flow_dv_translate_item_eth(void *matcher, void *key,
5731                            const struct rte_flow_item *item, int inner,
5732                            uint32_t group)
5733 {
5734         const struct rte_flow_item_eth *eth_m = item->mask;
5735         const struct rte_flow_item_eth *eth_v = item->spec;
5736         const struct rte_flow_item_eth nic_mask = {
5737                 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5738                 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5739                 .type = RTE_BE16(0xffff),
5740         };
5741         void *headers_m;
5742         void *headers_v;
5743         char *l24_v;
5744         unsigned int i;
5745
5746         if (!eth_v)
5747                 return;
5748         if (!eth_m)
5749                 eth_m = &nic_mask;
5750         if (inner) {
5751                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5752                                          inner_headers);
5753                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5754         } else {
5755                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5756                                          outer_headers);
5757                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5758         }
5759         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, dmac_47_16),
5760                &eth_m->dst, sizeof(eth_m->dst));
5761         /* The value must be in the range of the mask. */
5762         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, dmac_47_16);
5763         for (i = 0; i < sizeof(eth_m->dst); ++i)
5764                 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
5765         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, smac_47_16),
5766                &eth_m->src, sizeof(eth_m->src));
5767         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, smac_47_16);
5768         /* The value must be in the range of the mask. */
5769         for (i = 0; i < sizeof(eth_m->dst); ++i)
5770                 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
5771         if (eth_v->type) {
5772                 /* When ethertype is present set mask for tagged VLAN. */
5773                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5774                 /* Set value for tagged VLAN if ethertype is 802.1Q. */
5775                 if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_VLAN) ||
5776                     eth_v->type == RTE_BE16(RTE_ETHER_TYPE_QINQ)) {
5777                         MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag,
5778                                  1);
5779                         /* Return here to avoid setting match on ethertype. */
5780                         return;
5781                 }
5782         }
5783         /*
5784          * HW supports match on one Ethertype, the Ethertype following the last
5785          * VLAN tag of the packet (see PRM).
5786          * Set match on ethertype only if ETH header is not followed by VLAN.
5787          * HW is optimized for IPv4/IPv6. In such cases, avoid setting
5788          * ethertype, and use ip_version field instead.
5789          */
5790         if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_IPV4) &&
5791             eth_m->type == 0xFFFF) {
5792                 flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
5793         } else if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_IPV6) &&
5794                    eth_m->type == 0xFFFF) {
5795                 flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
5796         } else {
5797                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
5798                          rte_be_to_cpu_16(eth_m->type));
5799                 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5800                                      ethertype);
5801                 *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
5802         }
5803 }
5804
5805 /**
5806  * Add VLAN item to matcher and to the value.
5807  *
5808  * @param[in, out] dev_flow
5809  *   Flow descriptor.
5810  * @param[in, out] matcher
5811  *   Flow matcher.
5812  * @param[in, out] key
5813  *   Flow matcher value.
5814  * @param[in] item
5815  *   Flow pattern to translate.
5816  * @param[in] inner
5817  *   Item is inner pattern.
5818  */
5819 static void
5820 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
5821                             void *matcher, void *key,
5822                             const struct rte_flow_item *item,
5823                             int inner, uint32_t group)
5824 {
5825         const struct rte_flow_item_vlan *vlan_m = item->mask;
5826         const struct rte_flow_item_vlan *vlan_v = item->spec;
5827         void *headers_m;
5828         void *headers_v;
5829         uint16_t tci_m;
5830         uint16_t tci_v;
5831
5832         if (inner) {
5833                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5834                                          inner_headers);
5835                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5836         } else {
5837                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5838                                          outer_headers);
5839                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5840                 /*
5841                  * This is workaround, masks are not supported,
5842                  * and pre-validated.
5843                  */
5844                 if (vlan_v)
5845                         dev_flow->handle->vf_vlan.tag =
5846                                         rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
5847         }
5848         /*
5849          * When VLAN item exists in flow, mark packet as tagged,
5850          * even if TCI is not specified.
5851          */
5852         MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5853         MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
5854         if (!vlan_v)
5855                 return;
5856         if (!vlan_m)
5857                 vlan_m = &rte_flow_item_vlan_mask;
5858         tci_m = rte_be_to_cpu_16(vlan_m->tci);
5859         tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
5860         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_vid, tci_m);
5861         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, tci_v);
5862         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_cfi, tci_m >> 12);
5863         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_cfi, tci_v >> 12);
5864         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_prio, tci_m >> 13);
5865         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, tci_v >> 13);
5866         /*
5867          * HW is optimized for IPv4/IPv6. In such cases, avoid setting
5868          * ethertype, and use ip_version field instead.
5869          */
5870         if (vlan_v->inner_type == RTE_BE16(RTE_ETHER_TYPE_IPV4) &&
5871             vlan_m->inner_type == 0xFFFF) {
5872                 flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
5873         } else if (vlan_v->inner_type == RTE_BE16(RTE_ETHER_TYPE_IPV6) &&
5874                    vlan_m->inner_type == 0xFFFF) {
5875                 flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
5876         } else {
5877                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
5878                          rte_be_to_cpu_16(vlan_m->inner_type));
5879                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
5880                          rte_be_to_cpu_16(vlan_m->inner_type &
5881                                           vlan_v->inner_type));
5882         }
5883 }
5884
5885 /**
5886  * Add IPV4 item to matcher and to the value.
5887  *
5888  * @param[in, out] matcher
5889  *   Flow matcher.
5890  * @param[in, out] key
5891  *   Flow matcher value.
5892  * @param[in] item
5893  *   Flow pattern to translate.
5894  * @param[in] item_flags
5895  *   Bit-fields that holds the items detected until now.
5896  * @param[in] inner
5897  *   Item is inner pattern.
5898  * @param[in] group
5899  *   The group to insert the rule.
5900  */
5901 static void
5902 flow_dv_translate_item_ipv4(void *matcher, void *key,
5903                             const struct rte_flow_item *item,
5904                             const uint64_t item_flags,
5905                             int inner, uint32_t group)
5906 {
5907         const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
5908         const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
5909         const struct rte_flow_item_ipv4 nic_mask = {
5910                 .hdr = {
5911                         .src_addr = RTE_BE32(0xffffffff),
5912                         .dst_addr = RTE_BE32(0xffffffff),
5913                         .type_of_service = 0xff,
5914                         .next_proto_id = 0xff,
5915                         .time_to_live = 0xff,
5916                 },
5917         };
5918         void *headers_m;
5919         void *headers_v;
5920         char *l24_m;
5921         char *l24_v;
5922         uint8_t tos;
5923
5924         if (inner) {
5925                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5926                                          inner_headers);
5927                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5928         } else {
5929                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5930                                          outer_headers);
5931                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5932         }
5933         flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
5934         /*
5935          * On outer header (which must contains L2), or inner header with L2,
5936          * set cvlan_tag mask bit to mark this packet as untagged.
5937          * This should be done even if item->spec is empty.
5938          */
5939         if (!inner || item_flags & MLX5_FLOW_LAYER_INNER_L2)
5940                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5941         if (!ipv4_v)
5942                 return;
5943         if (!ipv4_m)
5944                 ipv4_m = &nic_mask;
5945         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5946                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
5947         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5948                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
5949         *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
5950         *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
5951         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5952                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
5953         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5954                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
5955         *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
5956         *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
5957         tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
5958         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
5959                  ipv4_m->hdr.type_of_service);
5960         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
5961         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
5962                  ipv4_m->hdr.type_of_service >> 2);
5963         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
5964         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
5965                  ipv4_m->hdr.next_proto_id);
5966         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
5967                  ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
5968         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
5969                  ipv4_m->hdr.time_to_live);
5970         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
5971                  ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
5972 }
5973
5974 /**
5975  * Add IPV6 item to matcher and to the value.
5976  *
5977  * @param[in, out] matcher
5978  *   Flow matcher.
5979  * @param[in, out] key
5980  *   Flow matcher value.
5981  * @param[in] item
5982  *   Flow pattern to translate.
5983  * @param[in] item_flags
5984  *   Bit-fields that holds the items detected until now.
5985  * @param[in] inner
5986  *   Item is inner pattern.
5987  * @param[in] group
5988  *   The group to insert the rule.
5989  */
5990 static void
5991 flow_dv_translate_item_ipv6(void *matcher, void *key,
5992                             const struct rte_flow_item *item,
5993                             const uint64_t item_flags,
5994                             int inner, uint32_t group)
5995 {
5996         const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
5997         const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
5998         const struct rte_flow_item_ipv6 nic_mask = {
5999                 .hdr = {
6000                         .src_addr =
6001                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
6002                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
6003                         .dst_addr =
6004                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
6005                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
6006                         .vtc_flow = RTE_BE32(0xffffffff),
6007                         .proto = 0xff,
6008                         .hop_limits = 0xff,
6009                 },
6010         };
6011         void *headers_m;
6012         void *headers_v;
6013         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6014         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6015         char *l24_m;
6016         char *l24_v;
6017         uint32_t vtc_m;
6018         uint32_t vtc_v;
6019         int i;
6020         int size;
6021
6022         if (inner) {
6023                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6024                                          inner_headers);
6025                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6026         } else {
6027                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6028                                          outer_headers);
6029                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6030         }
6031         flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
6032         /*
6033          * On outer header (which must contains L2), or inner header with L2,
6034          * set cvlan_tag mask bit to mark this packet as untagged.
6035          * This should be done even if item->spec is empty.
6036          */
6037         if (!inner || item_flags & MLX5_FLOW_LAYER_INNER_L2)
6038                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
6039         if (!ipv6_v)
6040                 return;
6041         if (!ipv6_m)
6042                 ipv6_m = &nic_mask;
6043         size = sizeof(ipv6_m->hdr.dst_addr);
6044         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6045                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
6046         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6047                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
6048         memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
6049         for (i = 0; i < size; ++i)
6050                 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
6051         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6052                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
6053         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6054                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
6055         memcpy(l24_m, ipv6_m->hdr.src_addr, size);
6056         for (i = 0; i < size; ++i)
6057                 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
6058         /* TOS. */
6059         vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
6060         vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
6061         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
6062         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
6063         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
6064         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
6065         /* Label. */
6066         if (inner) {
6067                 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
6068                          vtc_m);
6069                 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
6070                          vtc_v);
6071         } else {
6072                 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
6073                          vtc_m);
6074                 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
6075                          vtc_v);
6076         }
6077         /* Protocol. */
6078         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6079                  ipv6_m->hdr.proto);
6080         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6081                  ipv6_v->hdr.proto & ipv6_m->hdr.proto);
6082         /* Hop limit. */
6083         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
6084                  ipv6_m->hdr.hop_limits);
6085         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
6086                  ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
6087 }
6088
6089 /**
6090  * Add TCP item to matcher and to the value.
6091  *
6092  * @param[in, out] matcher
6093  *   Flow matcher.
6094  * @param[in, out] key
6095  *   Flow matcher value.
6096  * @param[in] item
6097  *   Flow pattern to translate.
6098  * @param[in] inner
6099  *   Item is inner pattern.
6100  */
6101 static void
6102 flow_dv_translate_item_tcp(void *matcher, void *key,
6103                            const struct rte_flow_item *item,
6104                            int inner)
6105 {
6106         const struct rte_flow_item_tcp *tcp_m = item->mask;
6107         const struct rte_flow_item_tcp *tcp_v = item->spec;
6108         void *headers_m;
6109         void *headers_v;
6110
6111         if (inner) {
6112                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6113                                          inner_headers);
6114                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6115         } else {
6116                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6117                                          outer_headers);
6118                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6119         }
6120         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6121         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
6122         if (!tcp_v)
6123                 return;
6124         if (!tcp_m)
6125                 tcp_m = &rte_flow_item_tcp_mask;
6126         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
6127                  rte_be_to_cpu_16(tcp_m->hdr.src_port));
6128         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
6129                  rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
6130         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
6131                  rte_be_to_cpu_16(tcp_m->hdr.dst_port));
6132         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
6133                  rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
6134         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
6135                  tcp_m->hdr.tcp_flags);
6136         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
6137                  (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
6138 }
6139
6140 /**
6141  * Add UDP item to matcher and to the value.
6142  *
6143  * @param[in, out] matcher
6144  *   Flow matcher.
6145  * @param[in, out] key
6146  *   Flow matcher value.
6147  * @param[in] item
6148  *   Flow pattern to translate.
6149  * @param[in] inner
6150  *   Item is inner pattern.
6151  */
6152 static void
6153 flow_dv_translate_item_udp(void *matcher, void *key,
6154                            const struct rte_flow_item *item,
6155                            int inner)
6156 {
6157         const struct rte_flow_item_udp *udp_m = item->mask;
6158         const struct rte_flow_item_udp *udp_v = item->spec;
6159         void *headers_m;
6160         void *headers_v;
6161
6162         if (inner) {
6163                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6164                                          inner_headers);
6165                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6166         } else {
6167                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6168                                          outer_headers);
6169                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6170         }
6171         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6172         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
6173         if (!udp_v)
6174                 return;
6175         if (!udp_m)
6176                 udp_m = &rte_flow_item_udp_mask;
6177         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
6178                  rte_be_to_cpu_16(udp_m->hdr.src_port));
6179         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
6180                  rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
6181         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
6182                  rte_be_to_cpu_16(udp_m->hdr.dst_port));
6183         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
6184                  rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
6185 }
6186
6187 /**
6188  * Add GRE optional Key item to matcher and to the value.
6189  *
6190  * @param[in, out] matcher
6191  *   Flow matcher.
6192  * @param[in, out] key
6193  *   Flow matcher value.
6194  * @param[in] item
6195  *   Flow pattern to translate.
6196  * @param[in] inner
6197  *   Item is inner pattern.
6198  */
6199 static void
6200 flow_dv_translate_item_gre_key(void *matcher, void *key,
6201                                    const struct rte_flow_item *item)
6202 {
6203         const rte_be32_t *key_m = item->mask;
6204         const rte_be32_t *key_v = item->spec;
6205         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6206         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6207         rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
6208
6209         /* GRE K bit must be on and should already be validated */
6210         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
6211         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
6212         if (!key_v)
6213                 return;
6214         if (!key_m)
6215                 key_m = &gre_key_default_mask;
6216         MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
6217                  rte_be_to_cpu_32(*key_m) >> 8);
6218         MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
6219                  rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
6220         MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
6221                  rte_be_to_cpu_32(*key_m) & 0xFF);
6222         MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
6223                  rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
6224 }
6225
6226 /**
6227  * Add GRE item to matcher and to the value.
6228  *
6229  * @param[in, out] matcher
6230  *   Flow matcher.
6231  * @param[in, out] key
6232  *   Flow matcher value.
6233  * @param[in] item
6234  *   Flow pattern to translate.
6235  * @param[in] inner
6236  *   Item is inner pattern.
6237  */
6238 static void
6239 flow_dv_translate_item_gre(void *matcher, void *key,
6240                            const struct rte_flow_item *item,
6241                            int inner)
6242 {
6243         const struct rte_flow_item_gre *gre_m = item->mask;
6244         const struct rte_flow_item_gre *gre_v = item->spec;
6245         void *headers_m;
6246         void *headers_v;
6247         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6248         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6249         struct {
6250                 union {
6251                         __extension__
6252                         struct {
6253                                 uint16_t version:3;
6254                                 uint16_t rsvd0:9;
6255                                 uint16_t s_present:1;
6256                                 uint16_t k_present:1;
6257                                 uint16_t rsvd_bit1:1;
6258                                 uint16_t c_present:1;
6259                         };
6260                         uint16_t value;
6261                 };
6262         } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
6263
6264         if (inner) {
6265                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6266                                          inner_headers);
6267                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6268         } else {
6269                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6270                                          outer_headers);
6271                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6272         }
6273         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6274         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
6275         if (!gre_v)
6276                 return;
6277         if (!gre_m)
6278                 gre_m = &rte_flow_item_gre_mask;
6279         MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
6280                  rte_be_to_cpu_16(gre_m->protocol));
6281         MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
6282                  rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
6283         gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
6284         gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
6285         MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
6286                  gre_crks_rsvd0_ver_m.c_present);
6287         MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
6288                  gre_crks_rsvd0_ver_v.c_present &
6289                  gre_crks_rsvd0_ver_m.c_present);
6290         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
6291                  gre_crks_rsvd0_ver_m.k_present);
6292         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
6293                  gre_crks_rsvd0_ver_v.k_present &
6294                  gre_crks_rsvd0_ver_m.k_present);
6295         MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
6296                  gre_crks_rsvd0_ver_m.s_present);
6297         MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
6298                  gre_crks_rsvd0_ver_v.s_present &
6299                  gre_crks_rsvd0_ver_m.s_present);
6300 }
6301
6302 /**
6303  * Add NVGRE item to matcher and to the value.
6304  *
6305  * @param[in, out] matcher
6306  *   Flow matcher.
6307  * @param[in, out] key
6308  *   Flow matcher value.
6309  * @param[in] item
6310  *   Flow pattern to translate.
6311  * @param[in] inner
6312  *   Item is inner pattern.
6313  */
6314 static void
6315 flow_dv_translate_item_nvgre(void *matcher, void *key,
6316                              const struct rte_flow_item *item,
6317                              int inner)
6318 {
6319         const struct rte_flow_item_nvgre *nvgre_m = item->mask;
6320         const struct rte_flow_item_nvgre *nvgre_v = item->spec;
6321         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6322         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6323         const char *tni_flow_id_m = (const char *)nvgre_m->tni;
6324         const char *tni_flow_id_v = (const char *)nvgre_v->tni;
6325         char *gre_key_m;
6326         char *gre_key_v;
6327         int size;
6328         int i;
6329
6330         /* For NVGRE, GRE header fields must be set with defined values. */
6331         const struct rte_flow_item_gre gre_spec = {
6332                 .c_rsvd0_ver = RTE_BE16(0x2000),
6333                 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
6334         };
6335         const struct rte_flow_item_gre gre_mask = {
6336                 .c_rsvd0_ver = RTE_BE16(0xB000),
6337                 .protocol = RTE_BE16(UINT16_MAX),
6338         };
6339         const struct rte_flow_item gre_item = {
6340                 .spec = &gre_spec,
6341                 .mask = &gre_mask,
6342                 .last = NULL,
6343         };
6344         flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
6345         if (!nvgre_v)
6346                 return;
6347         if (!nvgre_m)
6348                 nvgre_m = &rte_flow_item_nvgre_mask;
6349         size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
6350         gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
6351         gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
6352         memcpy(gre_key_m, tni_flow_id_m, size);
6353         for (i = 0; i < size; ++i)
6354                 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
6355 }
6356
6357 /**
6358  * Add VXLAN item to matcher and to the value.
6359  *
6360  * @param[in, out] matcher
6361  *   Flow matcher.
6362  * @param[in, out] key
6363  *   Flow matcher value.
6364  * @param[in] item
6365  *   Flow pattern to translate.
6366  * @param[in] inner
6367  *   Item is inner pattern.
6368  */
6369 static void
6370 flow_dv_translate_item_vxlan(void *matcher, void *key,
6371                              const struct rte_flow_item *item,
6372                              int inner)
6373 {
6374         const struct rte_flow_item_vxlan *vxlan_m = item->mask;
6375         const struct rte_flow_item_vxlan *vxlan_v = item->spec;
6376         void *headers_m;
6377         void *headers_v;
6378         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6379         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6380         char *vni_m;
6381         char *vni_v;
6382         uint16_t dport;
6383         int size;
6384         int i;
6385
6386         if (inner) {
6387                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6388                                          inner_headers);
6389                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6390         } else {
6391                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6392                                          outer_headers);
6393                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6394         }
6395         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
6396                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
6397         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6398                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6399                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6400         }
6401         if (!vxlan_v)
6402                 return;
6403         if (!vxlan_m)
6404                 vxlan_m = &rte_flow_item_vxlan_mask;
6405         size = sizeof(vxlan_m->vni);
6406         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
6407         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
6408         memcpy(vni_m, vxlan_m->vni, size);
6409         for (i = 0; i < size; ++i)
6410                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
6411 }
6412
6413 /**
6414  * Add VXLAN-GPE item to matcher and to the value.
6415  *
6416  * @param[in, out] matcher
6417  *   Flow matcher.
6418  * @param[in, out] key
6419  *   Flow matcher value.
6420  * @param[in] item
6421  *   Flow pattern to translate.
6422  * @param[in] inner
6423  *   Item is inner pattern.
6424  */
6425
6426 static void
6427 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
6428                                  const struct rte_flow_item *item, int inner)
6429 {
6430         const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
6431         const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
6432         void *headers_m;
6433         void *headers_v;
6434         void *misc_m =
6435                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
6436         void *misc_v =
6437                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6438         char *vni_m;
6439         char *vni_v;
6440         uint16_t dport;
6441         int size;
6442         int i;
6443         uint8_t flags_m = 0xff;
6444         uint8_t flags_v = 0xc;
6445
6446         if (inner) {
6447                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6448                                          inner_headers);
6449                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6450         } else {
6451                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6452                                          outer_headers);
6453                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6454         }
6455         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
6456                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
6457         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6458                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6459                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6460         }
6461         if (!vxlan_v)
6462                 return;
6463         if (!vxlan_m)
6464                 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
6465         size = sizeof(vxlan_m->vni);
6466         vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
6467         vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
6468         memcpy(vni_m, vxlan_m->vni, size);
6469         for (i = 0; i < size; ++i)
6470                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
6471         if (vxlan_m->flags) {
6472                 flags_m = vxlan_m->flags;
6473                 flags_v = vxlan_v->flags;
6474         }
6475         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
6476         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
6477         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
6478                  vxlan_m->protocol);
6479         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
6480                  vxlan_v->protocol);
6481 }
6482
6483 /**
6484  * Add Geneve item to matcher and to the value.
6485  *
6486  * @param[in, out] matcher
6487  *   Flow matcher.
6488  * @param[in, out] key
6489  *   Flow matcher value.
6490  * @param[in] item
6491  *   Flow pattern to translate.
6492  * @param[in] inner
6493  *   Item is inner pattern.
6494  */
6495
6496 static void
6497 flow_dv_translate_item_geneve(void *matcher, void *key,
6498                               const struct rte_flow_item *item, int inner)
6499 {
6500         const struct rte_flow_item_geneve *geneve_m = item->mask;
6501         const struct rte_flow_item_geneve *geneve_v = item->spec;
6502         void *headers_m;
6503         void *headers_v;
6504         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6505         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6506         uint16_t dport;
6507         uint16_t gbhdr_m;
6508         uint16_t gbhdr_v;
6509         char *vni_m;
6510         char *vni_v;
6511         size_t size, i;
6512
6513         if (inner) {
6514                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6515                                          inner_headers);
6516                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6517         } else {
6518                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6519                                          outer_headers);
6520                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6521         }
6522         dport = MLX5_UDP_PORT_GENEVE;
6523         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6524                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6525                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6526         }
6527         if (!geneve_v)
6528                 return;
6529         if (!geneve_m)
6530                 geneve_m = &rte_flow_item_geneve_mask;
6531         size = sizeof(geneve_m->vni);
6532         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
6533         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
6534         memcpy(vni_m, geneve_m->vni, size);
6535         for (i = 0; i < size; ++i)
6536                 vni_v[i] = vni_m[i] & geneve_v->vni[i];
6537         MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
6538                  rte_be_to_cpu_16(geneve_m->protocol));
6539         MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
6540                  rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
6541         gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
6542         gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
6543         MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
6544                  MLX5_GENEVE_OAMF_VAL(gbhdr_m));
6545         MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
6546                  MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
6547         MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
6548                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
6549         MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
6550                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
6551                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
6552 }
6553
6554 /**
6555  * Add MPLS item to matcher and to the value.
6556  *
6557  * @param[in, out] matcher
6558  *   Flow matcher.
6559  * @param[in, out] key
6560  *   Flow matcher value.
6561  * @param[in] item
6562  *   Flow pattern to translate.
6563  * @param[in] prev_layer
6564  *   The protocol layer indicated in previous item.
6565  * @param[in] inner
6566  *   Item is inner pattern.
6567  */
6568 static void
6569 flow_dv_translate_item_mpls(void *matcher, void *key,
6570                             const struct rte_flow_item *item,
6571                             uint64_t prev_layer,
6572                             int inner)
6573 {
6574         const uint32_t *in_mpls_m = item->mask;
6575         const uint32_t *in_mpls_v = item->spec;
6576         uint32_t *out_mpls_m = 0;
6577         uint32_t *out_mpls_v = 0;
6578         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6579         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6580         void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
6581                                      misc_parameters_2);
6582         void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
6583         void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
6584         void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6585
6586         switch (prev_layer) {
6587         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
6588                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
6589                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
6590                          MLX5_UDP_PORT_MPLS);
6591                 break;
6592         case MLX5_FLOW_LAYER_GRE:
6593                 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
6594                 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
6595                          RTE_ETHER_TYPE_MPLS);
6596                 break;
6597         default:
6598                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6599                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6600                          IPPROTO_MPLS);
6601                 break;
6602         }
6603         if (!in_mpls_v)
6604                 return;
6605         if (!in_mpls_m)
6606                 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
6607         switch (prev_layer) {
6608         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
6609                 out_mpls_m =
6610                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
6611                                                  outer_first_mpls_over_udp);
6612                 out_mpls_v =
6613                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
6614                                                  outer_first_mpls_over_udp);
6615                 break;
6616         case MLX5_FLOW_LAYER_GRE:
6617                 out_mpls_m =
6618                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
6619                                                  outer_first_mpls_over_gre);
6620                 out_mpls_v =
6621                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
6622                                                  outer_first_mpls_over_gre);
6623                 break;
6624         default:
6625                 /* Inner MPLS not over GRE is not supported. */
6626                 if (!inner) {
6627                         out_mpls_m =
6628                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
6629                                                          misc2_m,
6630                                                          outer_first_mpls);
6631                         out_mpls_v =
6632                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
6633                                                          misc2_v,
6634                                                          outer_first_mpls);
6635                 }
6636                 break;
6637         }
6638         if (out_mpls_m && out_mpls_v) {
6639                 *out_mpls_m = *in_mpls_m;
6640                 *out_mpls_v = *in_mpls_v & *in_mpls_m;
6641         }
6642 }
6643
6644 /**
6645  * Add metadata register item to matcher
6646  *
6647  * @param[in, out] matcher
6648  *   Flow matcher.
6649  * @param[in, out] key
6650  *   Flow matcher value.
6651  * @param[in] reg_type
6652  *   Type of device metadata register
6653  * @param[in] value
6654  *   Register value
6655  * @param[in] mask
6656  *   Register mask
6657  */
6658 static void
6659 flow_dv_match_meta_reg(void *matcher, void *key,
6660                        enum modify_reg reg_type,
6661                        uint32_t data, uint32_t mask)
6662 {
6663         void *misc2_m =
6664                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
6665         void *misc2_v =
6666                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
6667         uint32_t temp;
6668
6669         data &= mask;
6670         switch (reg_type) {
6671         case REG_A:
6672                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
6673                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
6674                 break;
6675         case REG_B:
6676                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
6677                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
6678                 break;
6679         case REG_C_0:
6680                 /*
6681                  * The metadata register C0 field might be divided into
6682                  * source vport index and META item value, we should set
6683                  * this field according to specified mask, not as whole one.
6684                  */
6685                 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
6686                 temp |= mask;
6687                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
6688                 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
6689                 temp &= ~mask;
6690                 temp |= data;
6691                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
6692                 break;
6693         case REG_C_1:
6694                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
6695                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
6696                 break;
6697         case REG_C_2:
6698                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
6699                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
6700                 break;
6701         case REG_C_3:
6702                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
6703                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
6704                 break;
6705         case REG_C_4:
6706                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
6707                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
6708                 break;
6709         case REG_C_5:
6710                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
6711                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
6712                 break;
6713         case REG_C_6:
6714                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
6715                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
6716                 break;
6717         case REG_C_7:
6718                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
6719                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
6720                 break;
6721         default:
6722                 MLX5_ASSERT(false);
6723                 break;
6724         }
6725 }
6726
6727 /**
6728  * Add MARK item to matcher
6729  *
6730  * @param[in] dev
6731  *   The device to configure through.
6732  * @param[in, out] matcher
6733  *   Flow matcher.
6734  * @param[in, out] key
6735  *   Flow matcher value.
6736  * @param[in] item
6737  *   Flow pattern to translate.
6738  */
6739 static void
6740 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
6741                             void *matcher, void *key,
6742                             const struct rte_flow_item *item)
6743 {
6744         struct mlx5_priv *priv = dev->data->dev_private;
6745         const struct rte_flow_item_mark *mark;
6746         uint32_t value;
6747         uint32_t mask;
6748
6749         mark = item->mask ? (const void *)item->mask :
6750                             &rte_flow_item_mark_mask;
6751         mask = mark->id & priv->sh->dv_mark_mask;
6752         mark = (const void *)item->spec;
6753         MLX5_ASSERT(mark);
6754         value = mark->id & priv->sh->dv_mark_mask & mask;
6755         if (mask) {
6756                 enum modify_reg reg;
6757
6758                 /* Get the metadata register index for the mark. */
6759                 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
6760                 MLX5_ASSERT(reg > 0);
6761                 if (reg == REG_C_0) {
6762                         struct mlx5_priv *priv = dev->data->dev_private;
6763                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6764                         uint32_t shl_c0 = rte_bsf32(msk_c0);
6765
6766                         mask &= msk_c0;
6767                         mask <<= shl_c0;
6768                         value <<= shl_c0;
6769                 }
6770                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6771         }
6772 }
6773
6774 /**
6775  * Add META item to matcher
6776  *
6777  * @param[in] dev
6778  *   The devich to configure through.
6779  * @param[in, out] matcher
6780  *   Flow matcher.
6781  * @param[in, out] key
6782  *   Flow matcher value.
6783  * @param[in] attr
6784  *   Attributes of flow that includes this item.
6785  * @param[in] item
6786  *   Flow pattern to translate.
6787  */
6788 static void
6789 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
6790                             void *matcher, void *key,
6791                             const struct rte_flow_attr *attr,
6792                             const struct rte_flow_item *item)
6793 {
6794         const struct rte_flow_item_meta *meta_m;
6795         const struct rte_flow_item_meta *meta_v;
6796
6797         meta_m = (const void *)item->mask;
6798         if (!meta_m)
6799                 meta_m = &rte_flow_item_meta_mask;
6800         meta_v = (const void *)item->spec;
6801         if (meta_v) {
6802                 int reg;
6803                 uint32_t value = meta_v->data;
6804                 uint32_t mask = meta_m->data;
6805
6806                 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
6807                 if (reg < 0)
6808                         return;
6809                 /*
6810                  * In datapath code there is no endianness
6811                  * coversions for perfromance reasons, all
6812                  * pattern conversions are done in rte_flow.
6813                  */
6814                 value = rte_cpu_to_be_32(value);
6815                 mask = rte_cpu_to_be_32(mask);
6816                 if (reg == REG_C_0) {
6817                         struct mlx5_priv *priv = dev->data->dev_private;
6818                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6819                         uint32_t shl_c0 = rte_bsf32(msk_c0);
6820 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
6821                         uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
6822
6823                         value >>= shr_c0;
6824                         mask >>= shr_c0;
6825 #endif
6826                         value <<= shl_c0;
6827                         mask <<= shl_c0;
6828                         MLX5_ASSERT(msk_c0);
6829                         MLX5_ASSERT(!(~msk_c0 & mask));
6830                 }
6831                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6832         }
6833 }
6834
6835 /**
6836  * Add vport metadata Reg C0 item to matcher
6837  *
6838  * @param[in, out] matcher
6839  *   Flow matcher.
6840  * @param[in, out] key
6841  *   Flow matcher value.
6842  * @param[in] reg
6843  *   Flow pattern to translate.
6844  */
6845 static void
6846 flow_dv_translate_item_meta_vport(void *matcher, void *key,
6847                                   uint32_t value, uint32_t mask)
6848 {
6849         flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
6850 }
6851
6852 /**
6853  * Add tag item to matcher
6854  *
6855  * @param[in] dev
6856  *   The devich to configure through.
6857  * @param[in, out] matcher
6858  *   Flow matcher.
6859  * @param[in, out] key
6860  *   Flow matcher value.
6861  * @param[in] item
6862  *   Flow pattern to translate.
6863  */
6864 static void
6865 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
6866                                 void *matcher, void *key,
6867                                 const struct rte_flow_item *item)
6868 {
6869         const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
6870         const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
6871         uint32_t mask, value;
6872
6873         MLX5_ASSERT(tag_v);
6874         value = tag_v->data;
6875         mask = tag_m ? tag_m->data : UINT32_MAX;
6876         if (tag_v->id == REG_C_0) {
6877                 struct mlx5_priv *priv = dev->data->dev_private;
6878                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6879                 uint32_t shl_c0 = rte_bsf32(msk_c0);
6880
6881                 mask &= msk_c0;
6882                 mask <<= shl_c0;
6883                 value <<= shl_c0;
6884         }
6885         flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
6886 }
6887
6888 /**
6889  * Add TAG item to matcher
6890  *
6891  * @param[in] dev
6892  *   The devich to configure through.
6893  * @param[in, out] matcher
6894  *   Flow matcher.
6895  * @param[in, out] key
6896  *   Flow matcher value.
6897  * @param[in] item
6898  *   Flow pattern to translate.
6899  */
6900 static void
6901 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
6902                            void *matcher, void *key,
6903                            const struct rte_flow_item *item)
6904 {
6905         const struct rte_flow_item_tag *tag_v = item->spec;
6906         const struct rte_flow_item_tag *tag_m = item->mask;
6907         enum modify_reg reg;
6908
6909         MLX5_ASSERT(tag_v);
6910         tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
6911         /* Get the metadata register index for the tag. */
6912         reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
6913         MLX5_ASSERT(reg > 0);
6914         flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
6915 }
6916
6917 /**
6918  * Add source vport match to the specified matcher.
6919  *
6920  * @param[in, out] matcher
6921  *   Flow matcher.
6922  * @param[in, out] key
6923  *   Flow matcher value.
6924  * @param[in] port
6925  *   Source vport value to match
6926  * @param[in] mask
6927  *   Mask
6928  */
6929 static void
6930 flow_dv_translate_item_source_vport(void *matcher, void *key,
6931                                     int16_t port, uint16_t mask)
6932 {
6933         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6934         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6935
6936         MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
6937         MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
6938 }
6939
6940 /**
6941  * Translate port-id item to eswitch match on  port-id.
6942  *
6943  * @param[in] dev
6944  *   The devich to configure through.
6945  * @param[in, out] matcher
6946  *   Flow matcher.
6947  * @param[in, out] key
6948  *   Flow matcher value.
6949  * @param[in] item
6950  *   Flow pattern to translate.
6951  *
6952  * @return
6953  *   0 on success, a negative errno value otherwise.
6954  */
6955 static int
6956 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
6957                                void *key, const struct rte_flow_item *item)
6958 {
6959         const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
6960         const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
6961         struct mlx5_priv *priv;
6962         uint16_t mask, id;
6963
6964         mask = pid_m ? pid_m->id : 0xffff;
6965         id = pid_v ? pid_v->id : dev->data->port_id;
6966         priv = mlx5_port_to_eswitch_info(id, item == NULL);
6967         if (!priv)
6968                 return -rte_errno;
6969         /* Translate to vport field or to metadata, depending on mode. */
6970         if (priv->vport_meta_mask)
6971                 flow_dv_translate_item_meta_vport(matcher, key,
6972                                                   priv->vport_meta_tag,
6973                                                   priv->vport_meta_mask);
6974         else
6975                 flow_dv_translate_item_source_vport(matcher, key,
6976                                                     priv->vport_id, mask);
6977         return 0;
6978 }
6979
6980 /**
6981  * Add ICMP6 item to matcher and to the value.
6982  *
6983  * @param[in, out] matcher
6984  *   Flow matcher.
6985  * @param[in, out] key
6986  *   Flow matcher value.
6987  * @param[in] item
6988  *   Flow pattern to translate.
6989  * @param[in] inner
6990  *   Item is inner pattern.
6991  */
6992 static void
6993 flow_dv_translate_item_icmp6(void *matcher, void *key,
6994                               const struct rte_flow_item *item,
6995                               int inner)
6996 {
6997         const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
6998         const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
6999         void *headers_m;
7000         void *headers_v;
7001         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7002                                      misc_parameters_3);
7003         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7004         if (inner) {
7005                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7006                                          inner_headers);
7007                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7008         } else {
7009                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7010                                          outer_headers);
7011                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7012         }
7013         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
7014         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
7015         if (!icmp6_v)
7016                 return;
7017         if (!icmp6_m)
7018                 icmp6_m = &rte_flow_item_icmp6_mask;
7019         /*
7020          * Force flow only to match the non-fragmented IPv6 ICMPv6 packets.
7021          * If only the protocol is specified, no need to match the frag.
7022          */
7023         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
7024         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
7025         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
7026         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
7027                  icmp6_v->type & icmp6_m->type);
7028         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
7029         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
7030                  icmp6_v->code & icmp6_m->code);
7031 }
7032
7033 /**
7034  * Add ICMP item to matcher and to the value.
7035  *
7036  * @param[in, out] matcher
7037  *   Flow matcher.
7038  * @param[in, out] key
7039  *   Flow matcher value.
7040  * @param[in] item
7041  *   Flow pattern to translate.
7042  * @param[in] inner
7043  *   Item is inner pattern.
7044  */
7045 static void
7046 flow_dv_translate_item_icmp(void *matcher, void *key,
7047                             const struct rte_flow_item *item,
7048                             int inner)
7049 {
7050         const struct rte_flow_item_icmp *icmp_m = item->mask;
7051         const struct rte_flow_item_icmp *icmp_v = item->spec;
7052         void *headers_m;
7053         void *headers_v;
7054         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7055                                      misc_parameters_3);
7056         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7057         if (inner) {
7058                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7059                                          inner_headers);
7060                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7061         } else {
7062                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7063                                          outer_headers);
7064                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7065         }
7066         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
7067         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
7068         if (!icmp_v)
7069                 return;
7070         if (!icmp_m)
7071                 icmp_m = &rte_flow_item_icmp_mask;
7072         /*
7073          * Force flow only to match the non-fragmented IPv4 ICMP packets.
7074          * If only the protocol is specified, no need to match the frag.
7075          */
7076         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
7077         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
7078         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
7079                  icmp_m->hdr.icmp_type);
7080         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
7081                  icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
7082         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
7083                  icmp_m->hdr.icmp_code);
7084         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
7085                  icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
7086 }
7087
7088 /**
7089  * Add GTP item to matcher and to the value.
7090  *
7091  * @param[in, out] matcher
7092  *   Flow matcher.
7093  * @param[in, out] key
7094  *   Flow matcher value.
7095  * @param[in] item
7096  *   Flow pattern to translate.
7097  * @param[in] inner
7098  *   Item is inner pattern.
7099  */
7100 static void
7101 flow_dv_translate_item_gtp(void *matcher, void *key,
7102                            const struct rte_flow_item *item, int inner)
7103 {
7104         const struct rte_flow_item_gtp *gtp_m = item->mask;
7105         const struct rte_flow_item_gtp *gtp_v = item->spec;
7106         void *headers_m;
7107         void *headers_v;
7108         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7109                                      misc_parameters_3);
7110         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7111         uint16_t dport = RTE_GTPU_UDP_PORT;
7112
7113         if (inner) {
7114                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7115                                          inner_headers);
7116                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7117         } else {
7118                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7119                                          outer_headers);
7120                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7121         }
7122         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7123                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7124                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7125         }
7126         if (!gtp_v)
7127                 return;
7128         if (!gtp_m)
7129                 gtp_m = &rte_flow_item_gtp_mask;
7130         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags,
7131                  gtp_m->v_pt_rsv_flags);
7132         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags,
7133                  gtp_v->v_pt_rsv_flags & gtp_m->v_pt_rsv_flags);
7134         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
7135         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
7136                  gtp_v->msg_type & gtp_m->msg_type);
7137         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
7138                  rte_be_to_cpu_32(gtp_m->teid));
7139         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
7140                  rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
7141 }
7142
7143 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
7144
7145 #define HEADER_IS_ZERO(match_criteria, headers)                              \
7146         !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers),     \
7147                  matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
7148
7149 /**
7150  * Calculate flow matcher enable bitmap.
7151  *
7152  * @param match_criteria
7153  *   Pointer to flow matcher criteria.
7154  *
7155  * @return
7156  *   Bitmap of enabled fields.
7157  */
7158 static uint8_t
7159 flow_dv_matcher_enable(uint32_t *match_criteria)
7160 {
7161         uint8_t match_criteria_enable;
7162
7163         match_criteria_enable =
7164                 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
7165                 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
7166         match_criteria_enable |=
7167                 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
7168                 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
7169         match_criteria_enable |=
7170                 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
7171                 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
7172         match_criteria_enable |=
7173                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
7174                 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
7175         match_criteria_enable |=
7176                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
7177                 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
7178         return match_criteria_enable;
7179 }
7180
7181
7182 /**
7183  * Get a flow table.
7184  *
7185  * @param[in, out] dev
7186  *   Pointer to rte_eth_dev structure.
7187  * @param[in] table_id
7188  *   Table id to use.
7189  * @param[in] egress
7190  *   Direction of the table.
7191  * @param[in] transfer
7192  *   E-Switch or NIC flow.
7193  * @param[out] error
7194  *   pointer to error structure.
7195  *
7196  * @return
7197  *   Returns tables resource based on the index, NULL in case of failed.
7198  */
7199 static struct mlx5_flow_tbl_resource *
7200 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
7201                          uint32_t table_id, uint8_t egress,
7202                          uint8_t transfer,
7203                          struct rte_flow_error *error)
7204 {
7205         struct mlx5_priv *priv = dev->data->dev_private;
7206         struct mlx5_ibv_shared *sh = priv->sh;
7207         struct mlx5_flow_tbl_resource *tbl;
7208         union mlx5_flow_tbl_key table_key = {
7209                 {
7210                         .table_id = table_id,
7211                         .reserved = 0,
7212                         .domain = !!transfer,
7213                         .direction = !!egress,
7214                 }
7215         };
7216         struct mlx5_hlist_entry *pos = mlx5_hlist_lookup(sh->flow_tbls,
7217                                                          table_key.v64);
7218         struct mlx5_flow_tbl_data_entry *tbl_data;
7219         uint32_t idx = 0;
7220         int ret;
7221         void *domain;
7222
7223         if (pos) {
7224                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
7225                                         entry);
7226                 tbl = &tbl_data->tbl;
7227                 rte_atomic32_inc(&tbl->refcnt);
7228                 return tbl;
7229         }
7230         tbl_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
7231         if (!tbl_data) {
7232                 rte_flow_error_set(error, ENOMEM,
7233                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7234                                    NULL,
7235                                    "cannot allocate flow table data entry");
7236                 return NULL;
7237         }
7238         tbl_data->idx = idx;
7239         tbl = &tbl_data->tbl;
7240         pos = &tbl_data->entry;
7241         if (transfer)
7242                 domain = sh->fdb_domain;
7243         else if (egress)
7244                 domain = sh->tx_domain;
7245         else
7246                 domain = sh->rx_domain;
7247         tbl->obj = mlx5_glue->dr_create_flow_tbl(domain, table_id);
7248         if (!tbl->obj) {
7249                 rte_flow_error_set(error, ENOMEM,
7250                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7251                                    NULL, "cannot create flow table object");
7252                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
7253                 return NULL;
7254         }
7255         /*
7256          * No multi-threads now, but still better to initialize the reference
7257          * count before insert it into the hash list.
7258          */
7259         rte_atomic32_init(&tbl->refcnt);
7260         /* Jump action reference count is initialized here. */
7261         rte_atomic32_init(&tbl_data->jump.refcnt);
7262         pos->key = table_key.v64;
7263         ret = mlx5_hlist_insert(sh->flow_tbls, pos);
7264         if (ret < 0) {
7265                 rte_flow_error_set(error, -ret,
7266                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7267                                    "cannot insert flow table data entry");
7268                 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
7269                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
7270         }
7271         rte_atomic32_inc(&tbl->refcnt);
7272         return tbl;
7273 }
7274
7275 /**
7276  * Release a flow table.
7277  *
7278  * @param[in] dev
7279  *   Pointer to rte_eth_dev structure.
7280  * @param[in] tbl
7281  *   Table resource to be released.
7282  *
7283  * @return
7284  *   Returns 0 if table was released, else return 1;
7285  */
7286 static int
7287 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
7288                              struct mlx5_flow_tbl_resource *tbl)
7289 {
7290         struct mlx5_priv *priv = dev->data->dev_private;
7291         struct mlx5_ibv_shared *sh = priv->sh;
7292         struct mlx5_flow_tbl_data_entry *tbl_data =
7293                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
7294
7295         if (!tbl)
7296                 return 0;
7297         if (rte_atomic32_dec_and_test(&tbl->refcnt)) {
7298                 struct mlx5_hlist_entry *pos = &tbl_data->entry;
7299
7300                 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
7301                 tbl->obj = NULL;
7302                 /* remove the entry from the hash list and free memory. */
7303                 mlx5_hlist_remove(sh->flow_tbls, pos);
7304                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_JUMP],
7305                                 tbl_data->idx);
7306                 return 0;
7307         }
7308         return 1;
7309 }
7310
7311 /**
7312  * Register the flow matcher.
7313  *
7314  * @param[in, out] dev
7315  *   Pointer to rte_eth_dev structure.
7316  * @param[in, out] matcher
7317  *   Pointer to flow matcher.
7318  * @param[in, out] key
7319  *   Pointer to flow table key.
7320  * @parm[in, out] dev_flow
7321  *   Pointer to the dev_flow.
7322  * @param[out] error
7323  *   pointer to error structure.
7324  *
7325  * @return
7326  *   0 on success otherwise -errno and errno is set.
7327  */
7328 static int
7329 flow_dv_matcher_register(struct rte_eth_dev *dev,
7330                          struct mlx5_flow_dv_matcher *matcher,
7331                          union mlx5_flow_tbl_key *key,
7332                          struct mlx5_flow *dev_flow,
7333                          struct rte_flow_error *error)
7334 {
7335         struct mlx5_priv *priv = dev->data->dev_private;
7336         struct mlx5_ibv_shared *sh = priv->sh;
7337         struct mlx5_flow_dv_matcher *cache_matcher;
7338         struct mlx5dv_flow_matcher_attr dv_attr = {
7339                 .type = IBV_FLOW_ATTR_NORMAL,
7340                 .match_mask = (void *)&matcher->mask,
7341         };
7342         struct mlx5_flow_tbl_resource *tbl;
7343         struct mlx5_flow_tbl_data_entry *tbl_data;
7344
7345         tbl = flow_dv_tbl_resource_get(dev, key->table_id, key->direction,
7346                                        key->domain, error);
7347         if (!tbl)
7348                 return -rte_errno;      /* No need to refill the error info */
7349         tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
7350         /* Lookup from cache. */
7351         LIST_FOREACH(cache_matcher, &tbl_data->matchers, next) {
7352                 if (matcher->crc == cache_matcher->crc &&
7353                     matcher->priority == cache_matcher->priority &&
7354                     !memcmp((const void *)matcher->mask.buf,
7355                             (const void *)cache_matcher->mask.buf,
7356                             cache_matcher->mask.size)) {
7357                         DRV_LOG(DEBUG,
7358                                 "%s group %u priority %hd use %s "
7359                                 "matcher %p: refcnt %d++",
7360                                 key->domain ? "FDB" : "NIC", key->table_id,
7361                                 cache_matcher->priority,
7362                                 key->direction ? "tx" : "rx",
7363                                 (void *)cache_matcher,
7364                                 rte_atomic32_read(&cache_matcher->refcnt));
7365                         rte_atomic32_inc(&cache_matcher->refcnt);
7366                         dev_flow->handle->dvh.matcher = cache_matcher;
7367                         /* old matcher should not make the table ref++. */
7368                         flow_dv_tbl_resource_release(dev, tbl);
7369                         return 0;
7370                 }
7371         }
7372         /* Register new matcher. */
7373         cache_matcher = rte_calloc(__func__, 1, sizeof(*cache_matcher), 0);
7374         if (!cache_matcher) {
7375                 flow_dv_tbl_resource_release(dev, tbl);
7376                 return rte_flow_error_set(error, ENOMEM,
7377                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7378                                           "cannot allocate matcher memory");
7379         }
7380         *cache_matcher = *matcher;
7381         dv_attr.match_criteria_enable =
7382                 flow_dv_matcher_enable(cache_matcher->mask.buf);
7383         dv_attr.priority = matcher->priority;
7384         if (key->direction)
7385                 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
7386         cache_matcher->matcher_object =
7387                 mlx5_glue->dv_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj);
7388         if (!cache_matcher->matcher_object) {
7389                 rte_free(cache_matcher);
7390 #ifdef HAVE_MLX5DV_DR
7391                 flow_dv_tbl_resource_release(dev, tbl);
7392 #endif
7393                 return rte_flow_error_set(error, ENOMEM,
7394                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7395                                           NULL, "cannot create matcher");
7396         }
7397         /* Save the table information */
7398         cache_matcher->tbl = tbl;
7399         rte_atomic32_init(&cache_matcher->refcnt);
7400         /* only matcher ref++, table ref++ already done above in get API. */
7401         rte_atomic32_inc(&cache_matcher->refcnt);
7402         LIST_INSERT_HEAD(&tbl_data->matchers, cache_matcher, next);
7403         dev_flow->handle->dvh.matcher = cache_matcher;
7404         DRV_LOG(DEBUG, "%s group %u priority %hd new %s matcher %p: refcnt %d",
7405                 key->domain ? "FDB" : "NIC", key->table_id,
7406                 cache_matcher->priority,
7407                 key->direction ? "tx" : "rx", (void *)cache_matcher,
7408                 rte_atomic32_read(&cache_matcher->refcnt));
7409         return 0;
7410 }
7411
7412 /**
7413  * Find existing tag resource or create and register a new one.
7414  *
7415  * @param dev[in, out]
7416  *   Pointer to rte_eth_dev structure.
7417  * @param[in, out] tag_be24
7418  *   Tag value in big endian then R-shift 8.
7419  * @parm[in, out] dev_flow
7420  *   Pointer to the dev_flow.
7421  * @param[out] error
7422  *   pointer to error structure.
7423  *
7424  * @return
7425  *   0 on success otherwise -errno and errno is set.
7426  */
7427 static int
7428 flow_dv_tag_resource_register
7429                         (struct rte_eth_dev *dev,
7430                          uint32_t tag_be24,
7431                          struct mlx5_flow *dev_flow,
7432                          struct rte_flow_error *error)
7433 {
7434         struct mlx5_priv *priv = dev->data->dev_private;
7435         struct mlx5_ibv_shared *sh = priv->sh;
7436         struct mlx5_flow_dv_tag_resource *cache_resource;
7437         struct mlx5_hlist_entry *entry;
7438
7439         /* Lookup a matching resource from cache. */
7440         entry = mlx5_hlist_lookup(sh->tag_table, (uint64_t)tag_be24);
7441         if (entry) {
7442                 cache_resource = container_of
7443                         (entry, struct mlx5_flow_dv_tag_resource, entry);
7444                 rte_atomic32_inc(&cache_resource->refcnt);
7445                 dev_flow->handle->dvh.rix_tag = cache_resource->idx;
7446                 dev_flow->dv.tag_resource = cache_resource;
7447                 DRV_LOG(DEBUG, "cached tag resource %p: refcnt now %d++",
7448                         (void *)cache_resource,
7449                         rte_atomic32_read(&cache_resource->refcnt));
7450                 return 0;
7451         }
7452         /* Register new resource. */
7453         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_TAG],
7454                                        &dev_flow->handle->dvh.rix_tag);
7455         if (!cache_resource)
7456                 return rte_flow_error_set(error, ENOMEM,
7457                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7458                                           "cannot allocate resource memory");
7459         cache_resource->entry.key = (uint64_t)tag_be24;
7460         cache_resource->action = mlx5_glue->dv_create_flow_action_tag(tag_be24);
7461         if (!cache_resource->action) {
7462                 rte_free(cache_resource);
7463                 return rte_flow_error_set(error, ENOMEM,
7464                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7465                                           NULL, "cannot create action");
7466         }
7467         rte_atomic32_init(&cache_resource->refcnt);
7468         rte_atomic32_inc(&cache_resource->refcnt);
7469         if (mlx5_hlist_insert(sh->tag_table, &cache_resource->entry)) {
7470                 mlx5_glue->destroy_flow_action(cache_resource->action);
7471                 rte_free(cache_resource);
7472                 return rte_flow_error_set(error, EEXIST,
7473                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7474                                           NULL, "cannot insert tag");
7475         }
7476         dev_flow->dv.tag_resource = cache_resource;
7477         DRV_LOG(DEBUG, "new tag resource %p: refcnt now %d++",
7478                 (void *)cache_resource,
7479                 rte_atomic32_read(&cache_resource->refcnt));
7480         return 0;
7481 }
7482
7483 /**
7484  * Release the tag.
7485  *
7486  * @param dev
7487  *   Pointer to Ethernet device.
7488  * @param tag_idx
7489  *   Tag index.
7490  *
7491  * @return
7492  *   1 while a reference on it exists, 0 when freed.
7493  */
7494 static int
7495 flow_dv_tag_release(struct rte_eth_dev *dev,
7496                     uint32_t tag_idx)
7497 {
7498         struct mlx5_priv *priv = dev->data->dev_private;
7499         struct mlx5_ibv_shared *sh = priv->sh;
7500         struct mlx5_flow_dv_tag_resource *tag;
7501
7502         tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
7503         if (!tag)
7504                 return 0;
7505         DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
7506                 dev->data->port_id, (void *)tag,
7507                 rte_atomic32_read(&tag->refcnt));
7508         if (rte_atomic32_dec_and_test(&tag->refcnt)) {
7509                 claim_zero(mlx5_glue->destroy_flow_action(tag->action));
7510                 mlx5_hlist_remove(sh->tag_table, &tag->entry);
7511                 DRV_LOG(DEBUG, "port %u tag %p: removed",
7512                         dev->data->port_id, (void *)tag);
7513                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
7514                 return 0;
7515         }
7516         return 1;
7517 }
7518
7519 /**
7520  * Translate port ID action to vport.
7521  *
7522  * @param[in] dev
7523  *   Pointer to rte_eth_dev structure.
7524  * @param[in] action
7525  *   Pointer to the port ID action.
7526  * @param[out] dst_port_id
7527  *   The target port ID.
7528  * @param[out] error
7529  *   Pointer to the error structure.
7530  *
7531  * @return
7532  *   0 on success, a negative errno value otherwise and rte_errno is set.
7533  */
7534 static int
7535 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
7536                                  const struct rte_flow_action *action,
7537                                  uint32_t *dst_port_id,
7538                                  struct rte_flow_error *error)
7539 {
7540         uint32_t port;
7541         struct mlx5_priv *priv;
7542         const struct rte_flow_action_port_id *conf =
7543                         (const struct rte_flow_action_port_id *)action->conf;
7544
7545         port = conf->original ? dev->data->port_id : conf->id;
7546         priv = mlx5_port_to_eswitch_info(port, false);
7547         if (!priv)
7548                 return rte_flow_error_set(error, -rte_errno,
7549                                           RTE_FLOW_ERROR_TYPE_ACTION,
7550                                           NULL,
7551                                           "No eswitch info was found for port");
7552 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
7553         /*
7554          * This parameter is transferred to
7555          * mlx5dv_dr_action_create_dest_ib_port().
7556          */
7557         *dst_port_id = priv->ibv_port;
7558 #else
7559         /*
7560          * Legacy mode, no LAG configurations is supported.
7561          * This parameter is transferred to
7562          * mlx5dv_dr_action_create_dest_vport().
7563          */
7564         *dst_port_id = priv->vport_id;
7565 #endif
7566         return 0;
7567 }
7568
7569 /**
7570  * Create a counter with aging configuration.
7571  *
7572  * @param[in] dev
7573  *   Pointer to rte_eth_dev structure.
7574  * @param[out] count
7575  *   Pointer to the counter action configuration.
7576  * @param[in] age
7577  *   Pointer to the aging action configuration.
7578  *
7579  * @return
7580  *   Index to flow counter on success, 0 otherwise.
7581  */
7582 static uint32_t
7583 flow_dv_translate_create_counter(struct rte_eth_dev *dev,
7584                                 struct mlx5_flow *dev_flow,
7585                                 const struct rte_flow_action_count *count,
7586                                 const struct rte_flow_action_age *age)
7587 {
7588         uint32_t counter;
7589         struct mlx5_age_param *age_param;
7590
7591         counter = flow_dv_counter_alloc(dev,
7592                                 count ? count->shared : 0,
7593                                 count ? count->id : 0,
7594                                 dev_flow->dv.group, !!age);
7595         if (!counter || age == NULL)
7596                 return counter;
7597         age_param  = flow_dv_counter_idx_get_age(dev, counter);
7598         /*
7599          * The counter age accuracy may have a bit delay. Have 3/4
7600          * second bias on the timeount in order to let it age in time.
7601          */
7602         age_param->context = age->context ? age->context :
7603                 (void *)(uintptr_t)(dev_flow->flow_idx);
7604         /*
7605          * The counter age accuracy may have a bit delay. Have 3/4
7606          * second bias on the timeount in order to let it age in time.
7607          */
7608         age_param->timeout = age->timeout * 10 - MLX5_AGING_TIME_DELAY;
7609         /* Set expire time in unit of 0.1 sec. */
7610         age_param->port_id = dev->data->port_id;
7611         age_param->expire = age_param->timeout +
7612                         rte_rdtsc() / (rte_get_tsc_hz() / 10);
7613         rte_atomic16_set(&age_param->state, AGE_CANDIDATE);
7614         return counter;
7615 }
7616 /**
7617  * Add Tx queue matcher
7618  *
7619  * @param[in] dev
7620  *   Pointer to the dev struct.
7621  * @param[in, out] matcher
7622  *   Flow matcher.
7623  * @param[in, out] key
7624  *   Flow matcher value.
7625  * @param[in] item
7626  *   Flow pattern to translate.
7627  * @param[in] inner
7628  *   Item is inner pattern.
7629  */
7630 static void
7631 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
7632                                 void *matcher, void *key,
7633                                 const struct rte_flow_item *item)
7634 {
7635         const struct mlx5_rte_flow_item_tx_queue *queue_m;
7636         const struct mlx5_rte_flow_item_tx_queue *queue_v;
7637         void *misc_m =
7638                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7639         void *misc_v =
7640                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7641         struct mlx5_txq_ctrl *txq;
7642         uint32_t queue;
7643
7644
7645         queue_m = (const void *)item->mask;
7646         if (!queue_m)
7647                 return;
7648         queue_v = (const void *)item->spec;
7649         if (!queue_v)
7650                 return;
7651         txq = mlx5_txq_get(dev, queue_v->queue);
7652         if (!txq)
7653                 return;
7654         queue = txq->obj->sq->id;
7655         MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
7656         MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
7657                  queue & queue_m->queue);
7658         mlx5_txq_release(dev, queue_v->queue);
7659 }
7660
7661 /**
7662  * Set the hash fields according to the @p flow information.
7663  *
7664  * @param[in] dev_flow
7665  *   Pointer to the mlx5_flow.
7666  * @param[in] rss_desc
7667  *   Pointer to the mlx5_flow_rss_desc.
7668  */
7669 static void
7670 flow_dv_hashfields_set(struct mlx5_flow *dev_flow,
7671                        struct mlx5_flow_rss_desc *rss_desc)
7672 {
7673         uint64_t items = dev_flow->handle->layers;
7674         int rss_inner = 0;
7675         uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
7676
7677         dev_flow->hash_fields = 0;
7678 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
7679         if (rss_desc->level >= 2) {
7680                 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
7681                 rss_inner = 1;
7682         }
7683 #endif
7684         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
7685             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
7686                 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
7687                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
7688                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
7689                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
7690                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
7691                         else
7692                                 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
7693                 }
7694         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
7695                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
7696                 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
7697                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
7698                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
7699                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
7700                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
7701                         else
7702                                 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
7703                 }
7704         }
7705         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
7706             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
7707                 if (rss_types & ETH_RSS_UDP) {
7708                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
7709                                 dev_flow->hash_fields |=
7710                                                 IBV_RX_HASH_SRC_PORT_UDP;
7711                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
7712                                 dev_flow->hash_fields |=
7713                                                 IBV_RX_HASH_DST_PORT_UDP;
7714                         else
7715                                 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
7716                 }
7717         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
7718                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
7719                 if (rss_types & ETH_RSS_TCP) {
7720                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
7721                                 dev_flow->hash_fields |=
7722                                                 IBV_RX_HASH_SRC_PORT_TCP;
7723                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
7724                                 dev_flow->hash_fields |=
7725                                                 IBV_RX_HASH_DST_PORT_TCP;
7726                         else
7727                                 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
7728                 }
7729         }
7730 }
7731
7732 /**
7733  * Fill the flow with DV spec, lock free
7734  * (mutex should be acquired by caller).
7735  *
7736  * @param[in] dev
7737  *   Pointer to rte_eth_dev structure.
7738  * @param[in, out] dev_flow
7739  *   Pointer to the sub flow.
7740  * @param[in] attr
7741  *   Pointer to the flow attributes.
7742  * @param[in] items
7743  *   Pointer to the list of items.
7744  * @param[in] actions
7745  *   Pointer to the list of actions.
7746  * @param[out] error
7747  *   Pointer to the error structure.
7748  *
7749  * @return
7750  *   0 on success, a negative errno value otherwise and rte_errno is set.
7751  */
7752 static int
7753 __flow_dv_translate(struct rte_eth_dev *dev,
7754                     struct mlx5_flow *dev_flow,
7755                     const struct rte_flow_attr *attr,
7756                     const struct rte_flow_item items[],
7757                     const struct rte_flow_action actions[],
7758                     struct rte_flow_error *error)
7759 {
7760         struct mlx5_priv *priv = dev->data->dev_private;
7761         struct mlx5_dev_config *dev_conf = &priv->config;
7762         struct rte_flow *flow = dev_flow->flow;
7763         struct mlx5_flow_handle *handle = dev_flow->handle;
7764         struct mlx5_flow_rss_desc *rss_desc = &((struct mlx5_flow_rss_desc *)
7765                                               priv->rss_desc)
7766                                               [!!priv->flow_nested_idx];
7767         uint64_t item_flags = 0;
7768         uint64_t last_item = 0;
7769         uint64_t action_flags = 0;
7770         uint64_t priority = attr->priority;
7771         struct mlx5_flow_dv_matcher matcher = {
7772                 .mask = {
7773                         .size = sizeof(matcher.mask.buf),
7774                 },
7775         };
7776         int actions_n = 0;
7777         bool actions_end = false;
7778         union {
7779                 struct mlx5_flow_dv_modify_hdr_resource res;
7780                 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
7781                             sizeof(struct mlx5_modification_cmd) *
7782                             (MLX5_MAX_MODIFY_NUM + 1)];
7783         } mhdr_dummy;
7784         struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
7785         const struct rte_flow_action_count *count = NULL;
7786         const struct rte_flow_action_age *age = NULL;
7787         union flow_dv_attr flow_attr = { .attr = 0 };
7788         uint32_t tag_be;
7789         union mlx5_flow_tbl_key tbl_key;
7790         uint32_t modify_action_position = UINT32_MAX;
7791         void *match_mask = matcher.mask.buf;
7792         void *match_value = dev_flow->dv.value.buf;
7793         uint8_t next_protocol = 0xff;
7794         struct rte_vlan_hdr vlan = { 0 };
7795         uint32_t table;
7796         int ret = 0;
7797
7798         mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
7799                                            MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
7800         ret = mlx5_flow_group_to_table(attr, dev_flow->external, attr->group,
7801                                        !!priv->fdb_def_rule, &table, error);
7802         if (ret)
7803                 return ret;
7804         dev_flow->dv.group = table;
7805         if (attr->transfer)
7806                 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
7807         if (priority == MLX5_FLOW_PRIO_RSVD)
7808                 priority = dev_conf->flow_prio - 1;
7809         /* number of actions must be set to 0 in case of dirty stack. */
7810         mhdr_res->actions_num = 0;
7811         for (; !actions_end ; actions++) {
7812                 const struct rte_flow_action_queue *queue;
7813                 const struct rte_flow_action_rss *rss;
7814                 const struct rte_flow_action *action = actions;
7815                 const uint8_t *rss_key;
7816                 const struct rte_flow_action_jump *jump_data;
7817                 const struct rte_flow_action_meter *mtr;
7818                 struct mlx5_flow_tbl_resource *tbl;
7819                 uint32_t port_id = 0;
7820                 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
7821                 int action_type = actions->type;
7822                 const struct rte_flow_action *found_action = NULL;
7823                 struct mlx5_flow_meter *fm = NULL;
7824
7825                 switch (action_type) {
7826                 case RTE_FLOW_ACTION_TYPE_VOID:
7827                         break;
7828                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
7829                         if (flow_dv_translate_action_port_id(dev, action,
7830                                                              &port_id, error))
7831                                 return -rte_errno;
7832                         memset(&port_id_resource, 0, sizeof(port_id_resource));
7833                         port_id_resource.port_id = port_id;
7834                         if (flow_dv_port_id_action_resource_register
7835                             (dev, &port_id_resource, dev_flow, error))
7836                                 return -rte_errno;
7837                         MLX5_ASSERT(!handle->rix_port_id_action);
7838                         dev_flow->dv.actions[actions_n++] =
7839                                         dev_flow->dv.port_id_action->action;
7840                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
7841                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_PORT_ID;
7842                         break;
7843                 case RTE_FLOW_ACTION_TYPE_FLAG:
7844                         action_flags |= MLX5_FLOW_ACTION_FLAG;
7845                         dev_flow->handle->mark = 1;
7846                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7847                                 struct rte_flow_action_mark mark = {
7848                                         .id = MLX5_FLOW_MARK_DEFAULT,
7849                                 };
7850
7851                                 if (flow_dv_convert_action_mark(dev, &mark,
7852                                                                 mhdr_res,
7853                                                                 error))
7854                                         return -rte_errno;
7855                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
7856                                 break;
7857                         }
7858                         tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
7859                         /*
7860                          * Only one FLAG or MARK is supported per device flow
7861                          * right now. So the pointer to the tag resource must be
7862                          * zero before the register process.
7863                          */
7864                         MLX5_ASSERT(!handle->dvh.rix_tag);
7865                         if (flow_dv_tag_resource_register(dev, tag_be,
7866                                                           dev_flow, error))
7867                                 return -rte_errno;
7868                         MLX5_ASSERT(dev_flow->dv.tag_resource);
7869                         dev_flow->dv.actions[actions_n++] =
7870                                         dev_flow->dv.tag_resource->action;
7871                         break;
7872                 case RTE_FLOW_ACTION_TYPE_MARK:
7873                         action_flags |= MLX5_FLOW_ACTION_MARK;
7874                         dev_flow->handle->mark = 1;
7875                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7876                                 const struct rte_flow_action_mark *mark =
7877                                         (const struct rte_flow_action_mark *)
7878                                                 actions->conf;
7879
7880                                 if (flow_dv_convert_action_mark(dev, mark,
7881                                                                 mhdr_res,
7882                                                                 error))
7883                                         return -rte_errno;
7884                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
7885                                 break;
7886                         }
7887                         /* Fall-through */
7888                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
7889                         /* Legacy (non-extensive) MARK action. */
7890                         tag_be = mlx5_flow_mark_set
7891                               (((const struct rte_flow_action_mark *)
7892                                (actions->conf))->id);
7893                         MLX5_ASSERT(!handle->dvh.rix_tag);
7894                         if (flow_dv_tag_resource_register(dev, tag_be,
7895                                                           dev_flow, error))
7896                                 return -rte_errno;
7897                         MLX5_ASSERT(dev_flow->dv.tag_resource);
7898                         dev_flow->dv.actions[actions_n++] =
7899                                         dev_flow->dv.tag_resource->action;
7900                         break;
7901                 case RTE_FLOW_ACTION_TYPE_SET_META:
7902                         if (flow_dv_convert_action_set_meta
7903                                 (dev, mhdr_res, attr,
7904                                  (const struct rte_flow_action_set_meta *)
7905                                   actions->conf, error))
7906                                 return -rte_errno;
7907                         action_flags |= MLX5_FLOW_ACTION_SET_META;
7908                         break;
7909                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
7910                         if (flow_dv_convert_action_set_tag
7911                                 (dev, mhdr_res,
7912                                  (const struct rte_flow_action_set_tag *)
7913                                   actions->conf, error))
7914                                 return -rte_errno;
7915                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7916                         break;
7917                 case RTE_FLOW_ACTION_TYPE_DROP:
7918                         action_flags |= MLX5_FLOW_ACTION_DROP;
7919                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_DROP;
7920                         break;
7921                 case RTE_FLOW_ACTION_TYPE_QUEUE:
7922                         queue = actions->conf;
7923                         rss_desc->queue_num = 1;
7924                         rss_desc->queue[0] = queue->index;
7925                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
7926                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
7927                         break;
7928                 case RTE_FLOW_ACTION_TYPE_RSS:
7929                         rss = actions->conf;
7930                         memcpy(rss_desc->queue, rss->queue,
7931                                rss->queue_num * sizeof(uint16_t));
7932                         rss_desc->queue_num = rss->queue_num;
7933                         /* NULL RSS key indicates default RSS key. */
7934                         rss_key = !rss->key ? rss_hash_default_key : rss->key;
7935                         memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
7936                         /*
7937                          * rss->level and rss.types should be set in advance
7938                          * when expanding items for RSS.
7939                          */
7940                         action_flags |= MLX5_FLOW_ACTION_RSS;
7941                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
7942                         break;
7943                 case RTE_FLOW_ACTION_TYPE_AGE:
7944                 case RTE_FLOW_ACTION_TYPE_COUNT:
7945                         if (!dev_conf->devx) {
7946                                 return rte_flow_error_set
7947                                               (error, ENOTSUP,
7948                                                RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7949                                                NULL,
7950                                                "count action not supported");
7951                         }
7952                         /* Save information first, will apply later. */
7953                         if (actions->type == RTE_FLOW_ACTION_TYPE_COUNT)
7954                                 count = action->conf;
7955                         else
7956                                 age = action->conf;
7957                         action_flags |= MLX5_FLOW_ACTION_COUNT;
7958                         break;
7959                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
7960                         dev_flow->dv.actions[actions_n++] =
7961                                                 priv->sh->pop_vlan_action;
7962                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
7963                         break;
7964                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
7965                         if (!(action_flags &
7966                               MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
7967                                 flow_dev_get_vlan_info_from_items(items, &vlan);
7968                         vlan.eth_proto = rte_be_to_cpu_16
7969                              ((((const struct rte_flow_action_of_push_vlan *)
7970                                                    actions->conf)->ethertype));
7971                         found_action = mlx5_flow_find_action
7972                                         (actions + 1,
7973                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
7974                         if (found_action)
7975                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
7976                         found_action = mlx5_flow_find_action
7977                                         (actions + 1,
7978                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
7979                         if (found_action)
7980                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
7981                         if (flow_dv_create_action_push_vlan
7982                                             (dev, attr, &vlan, dev_flow, error))
7983                                 return -rte_errno;
7984                         dev_flow->dv.actions[actions_n++] =
7985                                         dev_flow->dv.push_vlan_res->action;
7986                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
7987                         break;
7988                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
7989                         /* of_vlan_push action handled this action */
7990                         MLX5_ASSERT(action_flags &
7991                                     MLX5_FLOW_ACTION_OF_PUSH_VLAN);
7992                         break;
7993                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
7994                         if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
7995                                 break;
7996                         flow_dev_get_vlan_info_from_items(items, &vlan);
7997                         mlx5_update_vlan_vid_pcp(actions, &vlan);
7998                         /* If no VLAN push - this is a modify header action */
7999                         if (flow_dv_convert_action_modify_vlan_vid
8000                                                 (mhdr_res, actions, error))
8001                                 return -rte_errno;
8002                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
8003                         break;
8004                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
8005                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
8006                         if (flow_dv_create_action_l2_encap(dev, actions,
8007                                                            dev_flow,
8008                                                            attr->transfer,
8009                                                            error))
8010                                 return -rte_errno;
8011                         dev_flow->dv.actions[actions_n++] =
8012                                         dev_flow->dv.encap_decap->verbs_action;
8013                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
8014                         break;
8015                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
8016                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
8017                         if (flow_dv_create_action_l2_decap(dev, dev_flow,
8018                                                            attr->transfer,
8019                                                            error))
8020                                 return -rte_errno;
8021                         dev_flow->dv.actions[actions_n++] =
8022                                         dev_flow->dv.encap_decap->verbs_action;
8023                         action_flags |= MLX5_FLOW_ACTION_DECAP;
8024                         break;
8025                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
8026                         /* Handle encap with preceding decap. */
8027                         if (action_flags & MLX5_FLOW_ACTION_DECAP) {
8028                                 if (flow_dv_create_action_raw_encap
8029                                         (dev, actions, dev_flow, attr, error))
8030                                         return -rte_errno;
8031                                 dev_flow->dv.actions[actions_n++] =
8032                                         dev_flow->dv.encap_decap->verbs_action;
8033                         } else {
8034                                 /* Handle encap without preceding decap. */
8035                                 if (flow_dv_create_action_l2_encap
8036                                     (dev, actions, dev_flow, attr->transfer,
8037                                      error))
8038                                         return -rte_errno;
8039                                 dev_flow->dv.actions[actions_n++] =
8040                                         dev_flow->dv.encap_decap->verbs_action;
8041                         }
8042                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
8043                         break;
8044                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
8045                         while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
8046                                 ;
8047                         if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
8048                                 if (flow_dv_create_action_l2_decap
8049                                     (dev, dev_flow, attr->transfer, error))
8050                                         return -rte_errno;
8051                                 dev_flow->dv.actions[actions_n++] =
8052                                         dev_flow->dv.encap_decap->verbs_action;
8053                         }
8054                         /* If decap is followed by encap, handle it at encap. */
8055                         action_flags |= MLX5_FLOW_ACTION_DECAP;
8056                         break;
8057                 case RTE_FLOW_ACTION_TYPE_JUMP:
8058                         jump_data = action->conf;
8059                         ret = mlx5_flow_group_to_table(attr, dev_flow->external,
8060                                                        jump_data->group,
8061                                                        !!priv->fdb_def_rule,
8062                                                        &table, error);
8063                         if (ret)
8064                                 return ret;
8065                         tbl = flow_dv_tbl_resource_get(dev, table,
8066                                                        attr->egress,
8067                                                        attr->transfer, error);
8068                         if (!tbl)
8069                                 return rte_flow_error_set
8070                                                 (error, errno,
8071                                                  RTE_FLOW_ERROR_TYPE_ACTION,
8072                                                  NULL,
8073                                                  "cannot create jump action.");
8074                         if (flow_dv_jump_tbl_resource_register
8075                             (dev, tbl, dev_flow, error)) {
8076                                 flow_dv_tbl_resource_release(dev, tbl);
8077                                 return rte_flow_error_set
8078                                                 (error, errno,
8079                                                  RTE_FLOW_ERROR_TYPE_ACTION,
8080                                                  NULL,
8081                                                  "cannot create jump action.");
8082                         }
8083                         dev_flow->dv.actions[actions_n++] =
8084                                         dev_flow->dv.jump->action;
8085                         action_flags |= MLX5_FLOW_ACTION_JUMP;
8086                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_JUMP;
8087                         break;
8088                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
8089                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
8090                         if (flow_dv_convert_action_modify_mac
8091                                         (mhdr_res, actions, error))
8092                                 return -rte_errno;
8093                         action_flags |= actions->type ==
8094                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
8095                                         MLX5_FLOW_ACTION_SET_MAC_SRC :
8096                                         MLX5_FLOW_ACTION_SET_MAC_DST;
8097                         break;
8098                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
8099                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
8100                         if (flow_dv_convert_action_modify_ipv4
8101                                         (mhdr_res, actions, error))
8102                                 return -rte_errno;
8103                         action_flags |= actions->type ==
8104                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
8105                                         MLX5_FLOW_ACTION_SET_IPV4_SRC :
8106                                         MLX5_FLOW_ACTION_SET_IPV4_DST;
8107                         break;
8108                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
8109                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
8110                         if (flow_dv_convert_action_modify_ipv6
8111                                         (mhdr_res, actions, error))
8112                                 return -rte_errno;
8113                         action_flags |= actions->type ==
8114                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
8115                                         MLX5_FLOW_ACTION_SET_IPV6_SRC :
8116                                         MLX5_FLOW_ACTION_SET_IPV6_DST;
8117                         break;
8118                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
8119                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
8120                         if (flow_dv_convert_action_modify_tp
8121                                         (mhdr_res, actions, items,
8122                                          &flow_attr, dev_flow, !!(action_flags &
8123                                          MLX5_FLOW_ACTION_DECAP), error))
8124                                 return -rte_errno;
8125                         action_flags |= actions->type ==
8126                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
8127                                         MLX5_FLOW_ACTION_SET_TP_SRC :
8128                                         MLX5_FLOW_ACTION_SET_TP_DST;
8129                         break;
8130                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
8131                         if (flow_dv_convert_action_modify_dec_ttl
8132                                         (mhdr_res, items, &flow_attr, dev_flow,
8133                                          !!(action_flags &
8134                                          MLX5_FLOW_ACTION_DECAP), error))
8135                                 return -rte_errno;
8136                         action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
8137                         break;
8138                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
8139                         if (flow_dv_convert_action_modify_ttl
8140                                         (mhdr_res, actions, items, &flow_attr,
8141                                          dev_flow, !!(action_flags &
8142                                          MLX5_FLOW_ACTION_DECAP), error))
8143                                 return -rte_errno;
8144                         action_flags |= MLX5_FLOW_ACTION_SET_TTL;
8145                         break;
8146                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
8147                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
8148                         if (flow_dv_convert_action_modify_tcp_seq
8149                                         (mhdr_res, actions, error))
8150                                 return -rte_errno;
8151                         action_flags |= actions->type ==
8152                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
8153                                         MLX5_FLOW_ACTION_INC_TCP_SEQ :
8154                                         MLX5_FLOW_ACTION_DEC_TCP_SEQ;
8155                         break;
8156
8157                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
8158                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
8159                         if (flow_dv_convert_action_modify_tcp_ack
8160                                         (mhdr_res, actions, error))
8161                                 return -rte_errno;
8162                         action_flags |= actions->type ==
8163                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
8164                                         MLX5_FLOW_ACTION_INC_TCP_ACK :
8165                                         MLX5_FLOW_ACTION_DEC_TCP_ACK;
8166                         break;
8167                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
8168                         if (flow_dv_convert_action_set_reg
8169                                         (mhdr_res, actions, error))
8170                                 return -rte_errno;
8171                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
8172                         break;
8173                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
8174                         if (flow_dv_convert_action_copy_mreg
8175                                         (dev, mhdr_res, actions, error))
8176                                 return -rte_errno;
8177                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
8178                         break;
8179                 case RTE_FLOW_ACTION_TYPE_METER:
8180                         mtr = actions->conf;
8181                         if (!flow->meter) {
8182                                 fm = mlx5_flow_meter_attach(priv, mtr->mtr_id,
8183                                                             attr, error);
8184                                 if (!fm)
8185                                         return rte_flow_error_set(error,
8186                                                 rte_errno,
8187                                                 RTE_FLOW_ERROR_TYPE_ACTION,
8188                                                 NULL,
8189                                                 "meter not found "
8190                                                 "or invalid parameters");
8191                                 flow->meter = fm->idx;
8192                         }
8193                         /* Set the meter action. */
8194                         if (!fm) {
8195                                 fm = mlx5_ipool_get(priv->sh->ipool
8196                                                 [MLX5_IPOOL_MTR], flow->meter);
8197                                 if (!fm)
8198                                         return rte_flow_error_set(error,
8199                                                 rte_errno,
8200                                                 RTE_FLOW_ERROR_TYPE_ACTION,
8201                                                 NULL,
8202                                                 "meter not found "
8203                                                 "or invalid parameters");
8204                         }
8205                         dev_flow->dv.actions[actions_n++] =
8206                                 fm->mfts->meter_action;
8207                         action_flags |= MLX5_FLOW_ACTION_METER;
8208                         break;
8209                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
8210                         if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
8211                                                               actions, error))
8212                                 return -rte_errno;
8213                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
8214                         break;
8215                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
8216                         if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
8217                                                               actions, error))
8218                                 return -rte_errno;
8219                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
8220                         break;
8221                 case RTE_FLOW_ACTION_TYPE_END:
8222                         actions_end = true;
8223                         if (mhdr_res->actions_num) {
8224                                 /* create modify action if needed. */
8225                                 if (flow_dv_modify_hdr_resource_register
8226                                         (dev, mhdr_res, dev_flow, error))
8227                                         return -rte_errno;
8228                                 dev_flow->dv.actions[modify_action_position] =
8229                                         handle->dvh.modify_hdr->verbs_action;
8230                         }
8231                         if (action_flags & MLX5_FLOW_ACTION_COUNT) {
8232                                 flow->counter =
8233                                         flow_dv_translate_create_counter(dev,
8234                                                 dev_flow, count, age);
8235
8236                                 if (!flow->counter)
8237                                         return rte_flow_error_set
8238                                                 (error, rte_errno,
8239                                                 RTE_FLOW_ERROR_TYPE_ACTION,
8240                                                 NULL,
8241                                                 "cannot create counter"
8242                                                 " object.");
8243                                 dev_flow->dv.actions[actions_n++] =
8244                                           (flow_dv_counter_get_by_idx(dev,
8245                                           flow->counter, NULL))->action;
8246                         }
8247                         break;
8248                 default:
8249                         break;
8250                 }
8251                 if (mhdr_res->actions_num &&
8252                     modify_action_position == UINT32_MAX)
8253                         modify_action_position = actions_n++;
8254         }
8255         dev_flow->dv.actions_n = actions_n;
8256         dev_flow->act_flags = action_flags;
8257         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
8258                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
8259                 int item_type = items->type;
8260
8261                 switch (item_type) {
8262                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
8263                         flow_dv_translate_item_port_id(dev, match_mask,
8264                                                        match_value, items);
8265                         last_item = MLX5_FLOW_ITEM_PORT_ID;
8266                         break;
8267                 case RTE_FLOW_ITEM_TYPE_ETH:
8268                         flow_dv_translate_item_eth(match_mask, match_value,
8269                                                    items, tunnel,
8270                                                    dev_flow->dv.group);
8271                         matcher.priority = MLX5_PRIORITY_MAP_L2;
8272                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
8273                                              MLX5_FLOW_LAYER_OUTER_L2;
8274                         break;
8275                 case RTE_FLOW_ITEM_TYPE_VLAN:
8276                         flow_dv_translate_item_vlan(dev_flow,
8277                                                     match_mask, match_value,
8278                                                     items, tunnel,
8279                                                     dev_flow->dv.group);
8280                         matcher.priority = MLX5_PRIORITY_MAP_L2;
8281                         last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
8282                                               MLX5_FLOW_LAYER_INNER_VLAN) :
8283                                              (MLX5_FLOW_LAYER_OUTER_L2 |
8284                                               MLX5_FLOW_LAYER_OUTER_VLAN);
8285                         break;
8286                 case RTE_FLOW_ITEM_TYPE_IPV4:
8287                         mlx5_flow_tunnel_ip_check(items, next_protocol,
8288                                                   &item_flags, &tunnel);
8289                         flow_dv_translate_item_ipv4(match_mask, match_value,
8290                                                     items, item_flags, tunnel,
8291                                                     dev_flow->dv.group);
8292                         matcher.priority = MLX5_PRIORITY_MAP_L3;
8293                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
8294                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
8295                         if (items->mask != NULL &&
8296                             ((const struct rte_flow_item_ipv4 *)
8297                              items->mask)->hdr.next_proto_id) {
8298                                 next_protocol =
8299                                         ((const struct rte_flow_item_ipv4 *)
8300                                          (items->spec))->hdr.next_proto_id;
8301                                 next_protocol &=
8302                                         ((const struct rte_flow_item_ipv4 *)
8303                                          (items->mask))->hdr.next_proto_id;
8304                         } else {
8305                                 /* Reset for inner layer. */
8306                                 next_protocol = 0xff;
8307                         }
8308                         break;
8309                 case RTE_FLOW_ITEM_TYPE_IPV6:
8310                         mlx5_flow_tunnel_ip_check(items, next_protocol,
8311                                                   &item_flags, &tunnel);
8312                         flow_dv_translate_item_ipv6(match_mask, match_value,
8313                                                     items, item_flags, tunnel,
8314                                                     dev_flow->dv.group);
8315                         matcher.priority = MLX5_PRIORITY_MAP_L3;
8316                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
8317                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
8318                         if (items->mask != NULL &&
8319                             ((const struct rte_flow_item_ipv6 *)
8320                              items->mask)->hdr.proto) {
8321                                 next_protocol =
8322                                         ((const struct rte_flow_item_ipv6 *)
8323                                          items->spec)->hdr.proto;
8324                                 next_protocol &=
8325                                         ((const struct rte_flow_item_ipv6 *)
8326                                          items->mask)->hdr.proto;
8327                         } else {
8328                                 /* Reset for inner layer. */
8329                                 next_protocol = 0xff;
8330                         }
8331                         break;
8332                 case RTE_FLOW_ITEM_TYPE_TCP:
8333                         flow_dv_translate_item_tcp(match_mask, match_value,
8334                                                    items, tunnel);
8335                         matcher.priority = MLX5_PRIORITY_MAP_L4;
8336                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
8337                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
8338                         break;
8339                 case RTE_FLOW_ITEM_TYPE_UDP:
8340                         flow_dv_translate_item_udp(match_mask, match_value,
8341                                                    items, tunnel);
8342                         matcher.priority = MLX5_PRIORITY_MAP_L4;
8343                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
8344                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
8345                         break;
8346                 case RTE_FLOW_ITEM_TYPE_GRE:
8347                         flow_dv_translate_item_gre(match_mask, match_value,
8348                                                    items, tunnel);
8349                         matcher.priority = rss_desc->level >= 2 ?
8350                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8351                         last_item = MLX5_FLOW_LAYER_GRE;
8352                         break;
8353                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
8354                         flow_dv_translate_item_gre_key(match_mask,
8355                                                        match_value, items);
8356                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
8357                         break;
8358                 case RTE_FLOW_ITEM_TYPE_NVGRE:
8359                         flow_dv_translate_item_nvgre(match_mask, match_value,
8360                                                      items, tunnel);
8361                         matcher.priority = rss_desc->level >= 2 ?
8362                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8363                         last_item = MLX5_FLOW_LAYER_GRE;
8364                         break;
8365                 case RTE_FLOW_ITEM_TYPE_VXLAN:
8366                         flow_dv_translate_item_vxlan(match_mask, match_value,
8367                                                      items, tunnel);
8368                         matcher.priority = rss_desc->level >= 2 ?
8369                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8370                         last_item = MLX5_FLOW_LAYER_VXLAN;
8371                         break;
8372                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
8373                         flow_dv_translate_item_vxlan_gpe(match_mask,
8374                                                          match_value, items,
8375                                                          tunnel);
8376                         matcher.priority = rss_desc->level >= 2 ?
8377                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8378                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
8379                         break;
8380                 case RTE_FLOW_ITEM_TYPE_GENEVE:
8381                         flow_dv_translate_item_geneve(match_mask, match_value,
8382                                                       items, tunnel);
8383                         matcher.priority = rss_desc->level >= 2 ?
8384                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8385                         last_item = MLX5_FLOW_LAYER_GENEVE;
8386                         break;
8387                 case RTE_FLOW_ITEM_TYPE_MPLS:
8388                         flow_dv_translate_item_mpls(match_mask, match_value,
8389                                                     items, last_item, tunnel);
8390                         matcher.priority = rss_desc->level >= 2 ?
8391                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8392                         last_item = MLX5_FLOW_LAYER_MPLS;
8393                         break;
8394                 case RTE_FLOW_ITEM_TYPE_MARK:
8395                         flow_dv_translate_item_mark(dev, match_mask,
8396                                                     match_value, items);
8397                         last_item = MLX5_FLOW_ITEM_MARK;
8398                         break;
8399                 case RTE_FLOW_ITEM_TYPE_META:
8400                         flow_dv_translate_item_meta(dev, match_mask,
8401                                                     match_value, attr, items);
8402                         last_item = MLX5_FLOW_ITEM_METADATA;
8403                         break;
8404                 case RTE_FLOW_ITEM_TYPE_ICMP:
8405                         flow_dv_translate_item_icmp(match_mask, match_value,
8406                                                     items, tunnel);
8407                         last_item = MLX5_FLOW_LAYER_ICMP;
8408                         break;
8409                 case RTE_FLOW_ITEM_TYPE_ICMP6:
8410                         flow_dv_translate_item_icmp6(match_mask, match_value,
8411                                                       items, tunnel);
8412                         last_item = MLX5_FLOW_LAYER_ICMP6;
8413                         break;
8414                 case RTE_FLOW_ITEM_TYPE_TAG:
8415                         flow_dv_translate_item_tag(dev, match_mask,
8416                                                    match_value, items);
8417                         last_item = MLX5_FLOW_ITEM_TAG;
8418                         break;
8419                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
8420                         flow_dv_translate_mlx5_item_tag(dev, match_mask,
8421                                                         match_value, items);
8422                         last_item = MLX5_FLOW_ITEM_TAG;
8423                         break;
8424                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
8425                         flow_dv_translate_item_tx_queue(dev, match_mask,
8426                                                         match_value,
8427                                                         items);
8428                         last_item = MLX5_FLOW_ITEM_TX_QUEUE;
8429                         break;
8430                 case RTE_FLOW_ITEM_TYPE_GTP:
8431                         flow_dv_translate_item_gtp(match_mask, match_value,
8432                                                    items, tunnel);
8433                         matcher.priority = rss_desc->level >= 2 ?
8434                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8435                         last_item = MLX5_FLOW_LAYER_GTP;
8436                         break;
8437                 default:
8438                         break;
8439                 }
8440                 item_flags |= last_item;
8441         }
8442         /*
8443          * When E-Switch mode is enabled, we have two cases where we need to
8444          * set the source port manually.
8445          * The first one, is in case of Nic steering rule, and the second is
8446          * E-Switch rule where no port_id item was found. In both cases
8447          * the source port is set according the current port in use.
8448          */
8449         if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
8450             (priv->representor || priv->master)) {
8451                 if (flow_dv_translate_item_port_id(dev, match_mask,
8452                                                    match_value, NULL))
8453                         return -rte_errno;
8454         }
8455 #ifdef RTE_LIBRTE_MLX5_DEBUG
8456         MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
8457                                               dev_flow->dv.value.buf));
8458 #endif
8459         /*
8460          * Layers may be already initialized from prefix flow if this dev_flow
8461          * is the suffix flow.
8462          */
8463         handle->layers |= item_flags;
8464         if (action_flags & MLX5_FLOW_ACTION_RSS)
8465                 flow_dv_hashfields_set(dev_flow, rss_desc);
8466         /* Register matcher. */
8467         matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
8468                                     matcher.mask.size);
8469         matcher.priority = mlx5_flow_adjust_priority(dev, priority,
8470                                                      matcher.priority);
8471         /* reserved field no needs to be set to 0 here. */
8472         tbl_key.domain = attr->transfer;
8473         tbl_key.direction = attr->egress;
8474         tbl_key.table_id = dev_flow->dv.group;
8475         if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow, error))
8476                 return -rte_errno;
8477         return 0;
8478 }
8479
8480 /**
8481  * Apply the flow to the NIC, lock free,
8482  * (mutex should be acquired by caller).
8483  *
8484  * @param[in] dev
8485  *   Pointer to the Ethernet device structure.
8486  * @param[in, out] flow
8487  *   Pointer to flow structure.
8488  * @param[out] error
8489  *   Pointer to error structure.
8490  *
8491  * @return
8492  *   0 on success, a negative errno value otherwise and rte_errno is set.
8493  */
8494 static int
8495 __flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
8496                 struct rte_flow_error *error)
8497 {
8498         struct mlx5_flow_dv_workspace *dv;
8499         struct mlx5_flow_handle *dh;
8500         struct mlx5_flow_handle_dv *dv_h;
8501         struct mlx5_flow *dev_flow;
8502         struct mlx5_priv *priv = dev->data->dev_private;
8503         uint32_t handle_idx;
8504         int n;
8505         int err;
8506         int idx;
8507
8508         for (idx = priv->flow_idx - 1; idx >= priv->flow_nested_idx; idx--) {
8509                 dev_flow = &((struct mlx5_flow *)priv->inter_flows)[idx];
8510                 dv = &dev_flow->dv;
8511                 dh = dev_flow->handle;
8512                 dv_h = &dh->dvh;
8513                 n = dv->actions_n;
8514                 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
8515                         if (dv->transfer) {
8516                                 dv->actions[n++] = priv->sh->esw_drop_action;
8517                         } else {
8518                                 struct mlx5_hrxq *drop_hrxq;
8519                                 drop_hrxq = mlx5_hrxq_drop_new(dev);
8520                                 if (!drop_hrxq) {
8521                                         rte_flow_error_set
8522                                                 (error, errno,
8523                                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8524                                                  NULL,
8525                                                  "cannot get drop hash queue");
8526                                         goto error;
8527                                 }
8528                                 /*
8529                                  * Drop queues will be released by the specify
8530                                  * mlx5_hrxq_drop_release() function. Assign
8531                                  * the special index to hrxq to mark the queue
8532                                  * has been allocated.
8533                                  */
8534                                 dh->rix_hrxq = UINT32_MAX;
8535                                 dv->actions[n++] = drop_hrxq->action;
8536                         }
8537                 } else if (dh->fate_action == MLX5_FLOW_FATE_QUEUE) {
8538                         struct mlx5_hrxq *hrxq;
8539                         uint32_t hrxq_idx;
8540                         struct mlx5_flow_rss_desc *rss_desc =
8541                                 &((struct mlx5_flow_rss_desc *)priv->rss_desc)
8542                                 [!!priv->flow_nested_idx];
8543
8544                         MLX5_ASSERT(rss_desc->queue_num);
8545                         hrxq_idx = mlx5_hrxq_get(dev, rss_desc->key,
8546                                                  MLX5_RSS_HASH_KEY_LEN,
8547                                                  dev_flow->hash_fields,
8548                                                  rss_desc->queue,
8549                                                  rss_desc->queue_num);
8550                         if (!hrxq_idx) {
8551                                 hrxq_idx = mlx5_hrxq_new
8552                                                 (dev, rss_desc->key,
8553                                                 MLX5_RSS_HASH_KEY_LEN,
8554                                                 dev_flow->hash_fields,
8555                                                 rss_desc->queue,
8556                                                 rss_desc->queue_num,
8557                                                 !!(dh->layers &
8558                                                 MLX5_FLOW_LAYER_TUNNEL));
8559                         }
8560                         hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
8561                                               hrxq_idx);
8562                         if (!hrxq) {
8563                                 rte_flow_error_set
8564                                         (error, rte_errno,
8565                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8566                                          "cannot get hash queue");
8567                                 goto error;
8568                         }
8569                         dh->rix_hrxq = hrxq_idx;
8570                         dv->actions[n++] = hrxq->action;
8571                 }
8572                 dh->ib_flow =
8573                         mlx5_glue->dv_create_flow(dv_h->matcher->matcher_object,
8574                                                   (void *)&dv->value, n,
8575                                                   dv->actions);
8576                 if (!dh->ib_flow) {
8577                         rte_flow_error_set(error, errno,
8578                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8579                                            NULL,
8580                                            "hardware refuses to create flow");
8581                         goto error;
8582                 }
8583                 if (priv->vmwa_context &&
8584                     dh->vf_vlan.tag && !dh->vf_vlan.created) {
8585                         /*
8586                          * The rule contains the VLAN pattern.
8587                          * For VF we are going to create VLAN
8588                          * interface to make hypervisor set correct
8589                          * e-Switch vport context.
8590                          */
8591                         mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
8592                 }
8593         }
8594         return 0;
8595 error:
8596         err = rte_errno; /* Save rte_errno before cleanup. */
8597         SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles,
8598                        handle_idx, dh, next) {
8599                 /* hrxq is union, don't clear it if the flag is not set. */
8600                 if (dh->rix_hrxq) {
8601                         if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
8602                                 mlx5_hrxq_drop_release(dev);
8603                                 dh->rix_hrxq = 0;
8604                         } else if (dh->fate_action == MLX5_FLOW_FATE_QUEUE) {
8605                                 mlx5_hrxq_release(dev, dh->rix_hrxq);
8606                                 dh->rix_hrxq = 0;
8607                         }
8608                 }
8609                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
8610                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
8611         }
8612         rte_errno = err; /* Restore rte_errno. */
8613         return -rte_errno;
8614 }
8615
8616 /**
8617  * Release the flow matcher.
8618  *
8619  * @param dev
8620  *   Pointer to Ethernet device.
8621  * @param handle
8622  *   Pointer to mlx5_flow_handle.
8623  *
8624  * @return
8625  *   1 while a reference on it exists, 0 when freed.
8626  */
8627 static int
8628 flow_dv_matcher_release(struct rte_eth_dev *dev,
8629                         struct mlx5_flow_handle *handle)
8630 {
8631         struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
8632
8633         MLX5_ASSERT(matcher->matcher_object);
8634         DRV_LOG(DEBUG, "port %u matcher %p: refcnt %d--",
8635                 dev->data->port_id, (void *)matcher,
8636                 rte_atomic32_read(&matcher->refcnt));
8637         if (rte_atomic32_dec_and_test(&matcher->refcnt)) {
8638                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8639                            (matcher->matcher_object));
8640                 LIST_REMOVE(matcher, next);
8641                 /* table ref-- in release interface. */
8642                 flow_dv_tbl_resource_release(dev, matcher->tbl);
8643                 rte_free(matcher);
8644                 DRV_LOG(DEBUG, "port %u matcher %p: removed",
8645                         dev->data->port_id, (void *)matcher);
8646                 return 0;
8647         }
8648         return 1;
8649 }
8650
8651 /**
8652  * Release an encap/decap resource.
8653  *
8654  * @param dev
8655  *   Pointer to Ethernet device.
8656  * @param handle
8657  *   Pointer to mlx5_flow_handle.
8658  *
8659  * @return
8660  *   1 while a reference on it exists, 0 when freed.
8661  */
8662 static int
8663 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
8664                                      struct mlx5_flow_handle *handle)
8665 {
8666         struct mlx5_priv *priv = dev->data->dev_private;
8667         uint32_t idx = handle->dvh.rix_encap_decap;
8668         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
8669
8670         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
8671                          idx);
8672         if (!cache_resource)
8673                 return 0;
8674         MLX5_ASSERT(cache_resource->verbs_action);
8675         DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d--",
8676                 (void *)cache_resource,
8677                 rte_atomic32_read(&cache_resource->refcnt));
8678         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8679                 claim_zero(mlx5_glue->destroy_flow_action
8680                                 (cache_resource->verbs_action));
8681                 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
8682                              &priv->sh->encaps_decaps, idx,
8683                              cache_resource, next);
8684                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);
8685                 DRV_LOG(DEBUG, "encap/decap resource %p: removed",
8686                         (void *)cache_resource);
8687                 return 0;
8688         }
8689         return 1;
8690 }
8691
8692 /**
8693  * Release an jump to table action resource.
8694  *
8695  * @param dev
8696  *   Pointer to Ethernet device.
8697  * @param handle
8698  *   Pointer to mlx5_flow_handle.
8699  *
8700  * @return
8701  *   1 while a reference on it exists, 0 when freed.
8702  */
8703 static int
8704 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
8705                                   struct mlx5_flow_handle *handle)
8706 {
8707         struct mlx5_priv *priv = dev->data->dev_private;
8708         struct mlx5_flow_dv_jump_tbl_resource *cache_resource;
8709         struct mlx5_flow_tbl_data_entry *tbl_data;
8710
8711         tbl_data = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_JUMP],
8712                              handle->rix_jump);
8713         if (!tbl_data)
8714                 return 0;
8715         cache_resource = &tbl_data->jump;
8716         MLX5_ASSERT(cache_resource->action);
8717         DRV_LOG(DEBUG, "jump table resource %p: refcnt %d--",
8718                 (void *)cache_resource,
8719                 rte_atomic32_read(&cache_resource->refcnt));
8720         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8721                 claim_zero(mlx5_glue->destroy_flow_action
8722                                 (cache_resource->action));
8723                 /* jump action memory free is inside the table release. */
8724                 flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
8725                 DRV_LOG(DEBUG, "jump table resource %p: removed",
8726                         (void *)cache_resource);
8727                 return 0;
8728         }
8729         return 1;
8730 }
8731
8732 /**
8733  * Release a modify-header resource.
8734  *
8735  * @param handle
8736  *   Pointer to mlx5_flow_handle.
8737  *
8738  * @return
8739  *   1 while a reference on it exists, 0 when freed.
8740  */
8741 static int
8742 flow_dv_modify_hdr_resource_release(struct mlx5_flow_handle *handle)
8743 {
8744         struct mlx5_flow_dv_modify_hdr_resource *cache_resource =
8745                                                         handle->dvh.modify_hdr;
8746
8747         MLX5_ASSERT(cache_resource->verbs_action);
8748         DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d--",
8749                 (void *)cache_resource,
8750                 rte_atomic32_read(&cache_resource->refcnt));
8751         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8752                 claim_zero(mlx5_glue->destroy_flow_action
8753                                 (cache_resource->verbs_action));
8754                 LIST_REMOVE(cache_resource, next);
8755                 rte_free(cache_resource);
8756                 DRV_LOG(DEBUG, "modify-header resource %p: removed",
8757                         (void *)cache_resource);
8758                 return 0;
8759         }
8760         return 1;
8761 }
8762
8763 /**
8764  * Release port ID action resource.
8765  *
8766  * @param dev
8767  *   Pointer to Ethernet device.
8768  * @param handle
8769  *   Pointer to mlx5_flow_handle.
8770  *
8771  * @return
8772  *   1 while a reference on it exists, 0 when freed.
8773  */
8774 static int
8775 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
8776                                         struct mlx5_flow_handle *handle)
8777 {
8778         struct mlx5_priv *priv = dev->data->dev_private;
8779         struct mlx5_flow_dv_port_id_action_resource *cache_resource;
8780         uint32_t idx = handle->rix_port_id_action;
8781
8782         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID],
8783                                         idx);
8784         if (!cache_resource)
8785                 return 0;
8786         MLX5_ASSERT(cache_resource->action);
8787         DRV_LOG(DEBUG, "port ID action resource %p: refcnt %d--",
8788                 (void *)cache_resource,
8789                 rte_atomic32_read(&cache_resource->refcnt));
8790         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8791                 claim_zero(mlx5_glue->destroy_flow_action
8792                                 (cache_resource->action));
8793                 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_PORT_ID],
8794                              &priv->sh->port_id_action_list, idx,
8795                              cache_resource, next);
8796                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_PORT_ID], idx);
8797                 DRV_LOG(DEBUG, "port id action resource %p: removed",
8798                         (void *)cache_resource);
8799                 return 0;
8800         }
8801         return 1;
8802 }
8803
8804 /**
8805  * Release push vlan action resource.
8806  *
8807  * @param dev
8808  *   Pointer to Ethernet device.
8809  * @param handle
8810  *   Pointer to mlx5_flow_handle.
8811  *
8812  * @return
8813  *   1 while a reference on it exists, 0 when freed.
8814  */
8815 static int
8816 flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,
8817                                           struct mlx5_flow_handle *handle)
8818 {
8819         struct mlx5_priv *priv = dev->data->dev_private;
8820         uint32_t idx = handle->dvh.rix_push_vlan;
8821         struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
8822
8823         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN],
8824                                         idx);
8825         if (!cache_resource)
8826                 return 0;
8827         MLX5_ASSERT(cache_resource->action);
8828         DRV_LOG(DEBUG, "push VLAN action resource %p: refcnt %d--",
8829                 (void *)cache_resource,
8830                 rte_atomic32_read(&cache_resource->refcnt));
8831         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8832                 claim_zero(mlx5_glue->destroy_flow_action
8833                                 (cache_resource->action));
8834                 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN],
8835                              &priv->sh->push_vlan_action_list, idx,
8836                              cache_resource, next);
8837                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
8838                 DRV_LOG(DEBUG, "push vlan action resource %p: removed",
8839                         (void *)cache_resource);
8840                 return 0;
8841         }
8842         return 1;
8843 }
8844
8845 /**
8846  * Release the fate resource.
8847  *
8848  * @param dev
8849  *   Pointer to Ethernet device.
8850  * @param handle
8851  *   Pointer to mlx5_flow_handle.
8852  */
8853 static void
8854 flow_dv_fate_resource_release(struct rte_eth_dev *dev,
8855                                struct mlx5_flow_handle *handle)
8856 {
8857         if (!handle->rix_fate)
8858                 return;
8859         if (handle->fate_action == MLX5_FLOW_FATE_DROP)
8860                 mlx5_hrxq_drop_release(dev);
8861         else if (handle->fate_action == MLX5_FLOW_FATE_QUEUE)
8862                 mlx5_hrxq_release(dev, handle->rix_hrxq);
8863         else if (handle->fate_action == MLX5_FLOW_FATE_JUMP)
8864                 flow_dv_jump_tbl_resource_release(dev, handle);
8865         else if (handle->fate_action == MLX5_FLOW_FATE_PORT_ID)
8866                 flow_dv_port_id_action_resource_release(dev, handle);
8867         else
8868                 DRV_LOG(DEBUG, "Incorrect fate action:%d", handle->fate_action);
8869         handle->rix_fate = 0;
8870 }
8871
8872 /**
8873  * Remove the flow from the NIC but keeps it in memory.
8874  * Lock free, (mutex should be acquired by caller).
8875  *
8876  * @param[in] dev
8877  *   Pointer to Ethernet device.
8878  * @param[in, out] flow
8879  *   Pointer to flow structure.
8880  */
8881 static void
8882 __flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
8883 {
8884         struct mlx5_flow_handle *dh;
8885         uint32_t handle_idx;
8886         struct mlx5_priv *priv = dev->data->dev_private;
8887
8888         if (!flow)
8889                 return;
8890         handle_idx = flow->dev_handles;
8891         while (handle_idx) {
8892                 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
8893                                     handle_idx);
8894                 if (!dh)
8895                         return;
8896                 if (dh->ib_flow) {
8897                         claim_zero(mlx5_glue->dv_destroy_flow(dh->ib_flow));
8898                         dh->ib_flow = NULL;
8899                 }
8900                 if (dh->fate_action == MLX5_FLOW_FATE_DROP ||
8901                     dh->fate_action == MLX5_FLOW_FATE_QUEUE)
8902                         flow_dv_fate_resource_release(dev, dh);
8903                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
8904                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
8905                 handle_idx = dh->next.next;
8906         }
8907 }
8908
8909 /**
8910  * Remove the flow from the NIC and the memory.
8911  * Lock free, (mutex should be acquired by caller).
8912  *
8913  * @param[in] dev
8914  *   Pointer to the Ethernet device structure.
8915  * @param[in, out] flow
8916  *   Pointer to flow structure.
8917  */
8918 static void
8919 __flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
8920 {
8921         struct mlx5_flow_handle *dev_handle;
8922         struct mlx5_priv *priv = dev->data->dev_private;
8923
8924         if (!flow)
8925                 return;
8926         __flow_dv_remove(dev, flow);
8927         if (flow->counter) {
8928                 flow_dv_counter_release(dev, flow->counter);
8929                 flow->counter = 0;
8930         }
8931         if (flow->meter) {
8932                 struct mlx5_flow_meter *fm;
8933
8934                 fm = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MTR],
8935                                     flow->meter);
8936                 if (fm)
8937                         mlx5_flow_meter_detach(fm);
8938                 flow->meter = 0;
8939         }
8940         while (flow->dev_handles) {
8941                 uint32_t tmp_idx = flow->dev_handles;
8942
8943                 dev_handle = mlx5_ipool_get(priv->sh->ipool
8944                                             [MLX5_IPOOL_MLX5_FLOW], tmp_idx);
8945                 if (!dev_handle)
8946                         return;
8947                 flow->dev_handles = dev_handle->next.next;
8948                 if (dev_handle->dvh.matcher)
8949                         flow_dv_matcher_release(dev, dev_handle);
8950                 if (dev_handle->dvh.rix_encap_decap)
8951                         flow_dv_encap_decap_resource_release(dev, dev_handle);
8952                 if (dev_handle->dvh.modify_hdr)
8953                         flow_dv_modify_hdr_resource_release(dev_handle);
8954                 if (dev_handle->dvh.rix_push_vlan)
8955                         flow_dv_push_vlan_action_resource_release(dev,
8956                                                                   dev_handle);
8957                 if (dev_handle->dvh.rix_tag)
8958                         flow_dv_tag_release(dev,
8959                                             dev_handle->dvh.rix_tag);
8960                 flow_dv_fate_resource_release(dev, dev_handle);
8961                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
8962                            tmp_idx);
8963         }
8964 }
8965
8966 /**
8967  * Query a dv flow  rule for its statistics via devx.
8968  *
8969  * @param[in] dev
8970  *   Pointer to Ethernet device.
8971  * @param[in] flow
8972  *   Pointer to the sub flow.
8973  * @param[out] data
8974  *   data retrieved by the query.
8975  * @param[out] error
8976  *   Perform verbose error reporting if not NULL.
8977  *
8978  * @return
8979  *   0 on success, a negative errno value otherwise and rte_errno is set.
8980  */
8981 static int
8982 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
8983                     void *data, struct rte_flow_error *error)
8984 {
8985         struct mlx5_priv *priv = dev->data->dev_private;
8986         struct rte_flow_query_count *qc = data;
8987
8988         if (!priv->config.devx)
8989                 return rte_flow_error_set(error, ENOTSUP,
8990                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8991                                           NULL,
8992                                           "counters are not supported");
8993         if (flow->counter) {
8994                 uint64_t pkts, bytes;
8995                 struct mlx5_flow_counter *cnt;
8996
8997                 cnt = flow_dv_counter_get_by_idx(dev, flow->counter,
8998                                                  NULL);
8999                 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
9000                                                &bytes);
9001
9002                 if (err)
9003                         return rte_flow_error_set(error, -err,
9004                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9005                                         NULL, "cannot read counters");
9006                 qc->hits_set = 1;
9007                 qc->bytes_set = 1;
9008                 qc->hits = pkts - cnt->hits;
9009                 qc->bytes = bytes - cnt->bytes;
9010                 if (qc->reset) {
9011                         cnt->hits = pkts;
9012                         cnt->bytes = bytes;
9013                 }
9014                 return 0;
9015         }
9016         return rte_flow_error_set(error, EINVAL,
9017                                   RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9018                                   NULL,
9019                                   "counters are not available");
9020 }
9021
9022 /**
9023  * Query a flow.
9024  *
9025  * @see rte_flow_query()
9026  * @see rte_flow_ops
9027  */
9028 static int
9029 flow_dv_query(struct rte_eth_dev *dev,
9030               struct rte_flow *flow __rte_unused,
9031               const struct rte_flow_action *actions __rte_unused,
9032               void *data __rte_unused,
9033               struct rte_flow_error *error __rte_unused)
9034 {
9035         int ret = -EINVAL;
9036
9037         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
9038                 switch (actions->type) {
9039                 case RTE_FLOW_ACTION_TYPE_VOID:
9040                         break;
9041                 case RTE_FLOW_ACTION_TYPE_COUNT:
9042                         ret = flow_dv_query_count(dev, flow, data, error);
9043                         break;
9044                 default:
9045                         return rte_flow_error_set(error, ENOTSUP,
9046                                                   RTE_FLOW_ERROR_TYPE_ACTION,
9047                                                   actions,
9048                                                   "action not supported");
9049                 }
9050         }
9051         return ret;
9052 }
9053
9054 /**
9055  * Destroy the meter table set.
9056  * Lock free, (mutex should be acquired by caller).
9057  *
9058  * @param[in] dev
9059  *   Pointer to Ethernet device.
9060  * @param[in] tbl
9061  *   Pointer to the meter table set.
9062  *
9063  * @return
9064  *   Always 0.
9065  */
9066 static int
9067 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
9068                         struct mlx5_meter_domains_infos *tbl)
9069 {
9070         struct mlx5_priv *priv = dev->data->dev_private;
9071         struct mlx5_meter_domains_infos *mtd =
9072                                 (struct mlx5_meter_domains_infos *)tbl;
9073
9074         if (!mtd || !priv->config.dv_flow_en)
9075                 return 0;
9076         if (mtd->ingress.policer_rules[RTE_MTR_DROPPED])
9077                 claim_zero(mlx5_glue->dv_destroy_flow
9078                           (mtd->ingress.policer_rules[RTE_MTR_DROPPED]));
9079         if (mtd->egress.policer_rules[RTE_MTR_DROPPED])
9080                 claim_zero(mlx5_glue->dv_destroy_flow
9081                           (mtd->egress.policer_rules[RTE_MTR_DROPPED]));
9082         if (mtd->transfer.policer_rules[RTE_MTR_DROPPED])
9083                 claim_zero(mlx5_glue->dv_destroy_flow
9084                           (mtd->transfer.policer_rules[RTE_MTR_DROPPED]));
9085         if (mtd->egress.color_matcher)
9086                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
9087                           (mtd->egress.color_matcher));
9088         if (mtd->egress.any_matcher)
9089                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
9090                           (mtd->egress.any_matcher));
9091         if (mtd->egress.tbl)
9092                 flow_dv_tbl_resource_release(dev, mtd->egress.tbl);
9093         if (mtd->egress.sfx_tbl)
9094                 flow_dv_tbl_resource_release(dev, mtd->egress.sfx_tbl);
9095         if (mtd->ingress.color_matcher)
9096                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
9097                           (mtd->ingress.color_matcher));
9098         if (mtd->ingress.any_matcher)
9099                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
9100                           (mtd->ingress.any_matcher));
9101         if (mtd->ingress.tbl)
9102                 flow_dv_tbl_resource_release(dev, mtd->ingress.tbl);
9103         if (mtd->ingress.sfx_tbl)
9104                 flow_dv_tbl_resource_release(dev, mtd->ingress.sfx_tbl);
9105         if (mtd->transfer.color_matcher)
9106                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
9107                           (mtd->transfer.color_matcher));
9108         if (mtd->transfer.any_matcher)
9109                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
9110                           (mtd->transfer.any_matcher));
9111         if (mtd->transfer.tbl)
9112                 flow_dv_tbl_resource_release(dev, mtd->transfer.tbl);
9113         if (mtd->transfer.sfx_tbl)
9114                 flow_dv_tbl_resource_release(dev, mtd->transfer.sfx_tbl);
9115         if (mtd->drop_actn)
9116                 claim_zero(mlx5_glue->destroy_flow_action(mtd->drop_actn));
9117         rte_free(mtd);
9118         return 0;
9119 }
9120
9121 /* Number of meter flow actions, count and jump or count and drop. */
9122 #define METER_ACTIONS 2
9123
9124 /**
9125  * Create specify domain meter table and suffix table.
9126  *
9127  * @param[in] dev
9128  *   Pointer to Ethernet device.
9129  * @param[in,out] mtb
9130  *   Pointer to DV meter table set.
9131  * @param[in] egress
9132  *   Table attribute.
9133  * @param[in] transfer
9134  *   Table attribute.
9135  * @param[in] color_reg_c_idx
9136  *   Reg C index for color match.
9137  *
9138  * @return
9139  *   0 on success, -1 otherwise and rte_errno is set.
9140  */
9141 static int
9142 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
9143                            struct mlx5_meter_domains_infos *mtb,
9144                            uint8_t egress, uint8_t transfer,
9145                            uint32_t color_reg_c_idx)
9146 {
9147         struct mlx5_priv *priv = dev->data->dev_private;
9148         struct mlx5_ibv_shared *sh = priv->sh;
9149         struct mlx5_flow_dv_match_params mask = {
9150                 .size = sizeof(mask.buf),
9151         };
9152         struct mlx5_flow_dv_match_params value = {
9153                 .size = sizeof(value.buf),
9154         };
9155         struct mlx5dv_flow_matcher_attr dv_attr = {
9156                 .type = IBV_FLOW_ATTR_NORMAL,
9157                 .priority = 0,
9158                 .match_criteria_enable = 0,
9159                 .match_mask = (void *)&mask,
9160         };
9161         void *actions[METER_ACTIONS];
9162         struct mlx5_meter_domain_info *dtb;
9163         struct rte_flow_error error;
9164         int i = 0;
9165
9166         if (transfer)
9167                 dtb = &mtb->transfer;
9168         else if (egress)
9169                 dtb = &mtb->egress;
9170         else
9171                 dtb = &mtb->ingress;
9172         /* Create the meter table with METER level. */
9173         dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
9174                                             egress, transfer, &error);
9175         if (!dtb->tbl) {
9176                 DRV_LOG(ERR, "Failed to create meter policer table.");
9177                 return -1;
9178         }
9179         /* Create the meter suffix table with SUFFIX level. */
9180         dtb->sfx_tbl = flow_dv_tbl_resource_get(dev,
9181                                             MLX5_FLOW_TABLE_LEVEL_SUFFIX,
9182                                             egress, transfer, &error);
9183         if (!dtb->sfx_tbl) {
9184                 DRV_LOG(ERR, "Failed to create meter suffix table.");
9185                 return -1;
9186         }
9187         /* Create matchers, Any and Color. */
9188         dv_attr.priority = 3;
9189         dv_attr.match_criteria_enable = 0;
9190         dtb->any_matcher = mlx5_glue->dv_create_flow_matcher(sh->ctx,
9191                                                              &dv_attr,
9192                                                              dtb->tbl->obj);
9193         if (!dtb->any_matcher) {
9194                 DRV_LOG(ERR, "Failed to create meter"
9195                              " policer default matcher.");
9196                 goto error_exit;
9197         }
9198         dv_attr.priority = 0;
9199         dv_attr.match_criteria_enable =
9200                                 1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
9201         flow_dv_match_meta_reg(mask.buf, value.buf, color_reg_c_idx,
9202                                rte_col_2_mlx5_col(RTE_COLORS), UINT8_MAX);
9203         dtb->color_matcher = mlx5_glue->dv_create_flow_matcher(sh->ctx,
9204                                                                &dv_attr,
9205                                                                dtb->tbl->obj);
9206         if (!dtb->color_matcher) {
9207                 DRV_LOG(ERR, "Failed to create meter policer color matcher.");
9208                 goto error_exit;
9209         }
9210         if (mtb->count_actns[RTE_MTR_DROPPED])
9211                 actions[i++] = mtb->count_actns[RTE_MTR_DROPPED];
9212         actions[i++] = mtb->drop_actn;
9213         /* Default rule: lowest priority, match any, actions: drop. */
9214         dtb->policer_rules[RTE_MTR_DROPPED] =
9215                         mlx5_glue->dv_create_flow(dtb->any_matcher,
9216                                                  (void *)&value, i, actions);
9217         if (!dtb->policer_rules[RTE_MTR_DROPPED]) {
9218                 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
9219                 goto error_exit;
9220         }
9221         return 0;
9222 error_exit:
9223         return -1;
9224 }
9225
9226 /**
9227  * Create the needed meter and suffix tables.
9228  * Lock free, (mutex should be acquired by caller).
9229  *
9230  * @param[in] dev
9231  *   Pointer to Ethernet device.
9232  * @param[in] fm
9233  *   Pointer to the flow meter.
9234  *
9235  * @return
9236  *   Pointer to table set on success, NULL otherwise and rte_errno is set.
9237  */
9238 static struct mlx5_meter_domains_infos *
9239 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev,
9240                        const struct mlx5_flow_meter *fm)
9241 {
9242         struct mlx5_priv *priv = dev->data->dev_private;
9243         struct mlx5_meter_domains_infos *mtb;
9244         int ret;
9245         int i;
9246
9247         if (!priv->mtr_en) {
9248                 rte_errno = ENOTSUP;
9249                 return NULL;
9250         }
9251         mtb = rte_calloc(__func__, 1, sizeof(*mtb), 0);
9252         if (!mtb) {
9253                 DRV_LOG(ERR, "Failed to allocate memory for meter.");
9254                 return NULL;
9255         }
9256         /* Create meter count actions */
9257         for (i = 0; i <= RTE_MTR_DROPPED; i++) {
9258                 struct mlx5_flow_counter *cnt;
9259                 if (!fm->policer_stats.cnt[i])
9260                         continue;
9261                 cnt = flow_dv_counter_get_by_idx(dev,
9262                       fm->policer_stats.cnt[i], NULL);
9263                 mtb->count_actns[i] = cnt->action;
9264         }
9265         /* Create drop action. */
9266         mtb->drop_actn = mlx5_glue->dr_create_flow_action_drop();
9267         if (!mtb->drop_actn) {
9268                 DRV_LOG(ERR, "Failed to create drop action.");
9269                 goto error_exit;
9270         }
9271         /* Egress meter table. */
9272         ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0, priv->mtr_color_reg);
9273         if (ret) {
9274                 DRV_LOG(ERR, "Failed to prepare egress meter table.");
9275                 goto error_exit;
9276         }
9277         /* Ingress meter table. */
9278         ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0, priv->mtr_color_reg);
9279         if (ret) {
9280                 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
9281                 goto error_exit;
9282         }
9283         /* FDB meter table. */
9284         if (priv->config.dv_esw_en) {
9285                 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1,
9286                                                  priv->mtr_color_reg);
9287                 if (ret) {
9288                         DRV_LOG(ERR, "Failed to prepare fdb meter table.");
9289                         goto error_exit;
9290                 }
9291         }
9292         return mtb;
9293 error_exit:
9294         flow_dv_destroy_mtr_tbl(dev, mtb);
9295         return NULL;
9296 }
9297
9298 /**
9299  * Destroy domain policer rule.
9300  *
9301  * @param[in] dt
9302  *   Pointer to domain table.
9303  */
9304 static void
9305 flow_dv_destroy_domain_policer_rule(struct mlx5_meter_domain_info *dt)
9306 {
9307         int i;
9308
9309         for (i = 0; i < RTE_MTR_DROPPED; i++) {
9310                 if (dt->policer_rules[i]) {
9311                         claim_zero(mlx5_glue->dv_destroy_flow
9312                                   (dt->policer_rules[i]));
9313                         dt->policer_rules[i] = NULL;
9314                 }
9315         }
9316         if (dt->jump_actn) {
9317                 claim_zero(mlx5_glue->destroy_flow_action(dt->jump_actn));
9318                 dt->jump_actn = NULL;
9319         }
9320 }
9321
9322 /**
9323  * Destroy policer rules.
9324  *
9325  * @param[in] dev
9326  *   Pointer to Ethernet device.
9327  * @param[in] fm
9328  *   Pointer to flow meter structure.
9329  * @param[in] attr
9330  *   Pointer to flow attributes.
9331  *
9332  * @return
9333  *   Always 0.
9334  */
9335 static int
9336 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev __rte_unused,
9337                               const struct mlx5_flow_meter *fm,
9338                               const struct rte_flow_attr *attr)
9339 {
9340         struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
9341
9342         if (!mtb)
9343                 return 0;
9344         if (attr->egress)
9345                 flow_dv_destroy_domain_policer_rule(&mtb->egress);
9346         if (attr->ingress)
9347                 flow_dv_destroy_domain_policer_rule(&mtb->ingress);
9348         if (attr->transfer)
9349                 flow_dv_destroy_domain_policer_rule(&mtb->transfer);
9350         return 0;
9351 }
9352
9353 /**
9354  * Create specify domain meter policer rule.
9355  *
9356  * @param[in] fm
9357  *   Pointer to flow meter structure.
9358  * @param[in] mtb
9359  *   Pointer to DV meter table set.
9360  * @param[in] mtr_reg_c
9361  *   Color match REG_C.
9362  *
9363  * @return
9364  *   0 on success, -1 otherwise.
9365  */
9366 static int
9367 flow_dv_create_policer_forward_rule(struct mlx5_flow_meter *fm,
9368                                     struct mlx5_meter_domain_info *dtb,
9369                                     uint8_t mtr_reg_c)
9370 {
9371         struct mlx5_flow_dv_match_params matcher = {
9372                 .size = sizeof(matcher.buf),
9373         };
9374         struct mlx5_flow_dv_match_params value = {
9375                 .size = sizeof(value.buf),
9376         };
9377         struct mlx5_meter_domains_infos *mtb = fm->mfts;
9378         void *actions[METER_ACTIONS];
9379         int i;
9380
9381         /* Create jump action. */
9382         if (!dtb->jump_actn)
9383                 dtb->jump_actn =
9384                         mlx5_glue->dr_create_flow_action_dest_flow_tbl
9385                                                         (dtb->sfx_tbl->obj);
9386         if (!dtb->jump_actn) {
9387                 DRV_LOG(ERR, "Failed to create policer jump action.");
9388                 goto error;
9389         }
9390         for (i = 0; i < RTE_MTR_DROPPED; i++) {
9391                 int j = 0;
9392
9393                 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_reg_c,
9394                                        rte_col_2_mlx5_col(i), UINT8_MAX);
9395                 if (mtb->count_actns[i])
9396                         actions[j++] = mtb->count_actns[i];
9397                 if (fm->action[i] == MTR_POLICER_ACTION_DROP)
9398                         actions[j++] = mtb->drop_actn;
9399                 else
9400                         actions[j++] = dtb->jump_actn;
9401                 dtb->policer_rules[i] =
9402                         mlx5_glue->dv_create_flow(dtb->color_matcher,
9403                                                  (void *)&value,
9404                                                   j, actions);
9405                 if (!dtb->policer_rules[i]) {
9406                         DRV_LOG(ERR, "Failed to create policer rule.");
9407                         goto error;
9408                 }
9409         }
9410         return 0;
9411 error:
9412         rte_errno = errno;
9413         return -1;
9414 }
9415
9416 /**
9417  * Create policer rules.
9418  *
9419  * @param[in] dev
9420  *   Pointer to Ethernet device.
9421  * @param[in] fm
9422  *   Pointer to flow meter structure.
9423  * @param[in] attr
9424  *   Pointer to flow attributes.
9425  *
9426  * @return
9427  *   0 on success, -1 otherwise.
9428  */
9429 static int
9430 flow_dv_create_policer_rules(struct rte_eth_dev *dev,
9431                              struct mlx5_flow_meter *fm,
9432                              const struct rte_flow_attr *attr)
9433 {
9434         struct mlx5_priv *priv = dev->data->dev_private;
9435         struct mlx5_meter_domains_infos *mtb = fm->mfts;
9436         int ret;
9437
9438         if (attr->egress) {
9439                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->egress,
9440                                                 priv->mtr_color_reg);
9441                 if (ret) {
9442                         DRV_LOG(ERR, "Failed to create egress policer.");
9443                         goto error;
9444                 }
9445         }
9446         if (attr->ingress) {
9447                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->ingress,
9448                                                 priv->mtr_color_reg);
9449                 if (ret) {
9450                         DRV_LOG(ERR, "Failed to create ingress policer.");
9451                         goto error;
9452                 }
9453         }
9454         if (attr->transfer) {
9455                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->transfer,
9456                                                 priv->mtr_color_reg);
9457                 if (ret) {
9458                         DRV_LOG(ERR, "Failed to create transfer policer.");
9459                         goto error;
9460                 }
9461         }
9462         return 0;
9463 error:
9464         flow_dv_destroy_policer_rules(dev, fm, attr);
9465         return -1;
9466 }
9467
9468 /**
9469  * Query a devx counter.
9470  *
9471  * @param[in] dev
9472  *   Pointer to the Ethernet device structure.
9473  * @param[in] cnt
9474  *   Index to the flow counter.
9475  * @param[in] clear
9476  *   Set to clear the counter statistics.
9477  * @param[out] pkts
9478  *   The statistics value of packets.
9479  * @param[out] bytes
9480  *   The statistics value of bytes.
9481  *
9482  * @return
9483  *   0 on success, otherwise return -1.
9484  */
9485 static int
9486 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
9487                       uint64_t *pkts, uint64_t *bytes)
9488 {
9489         struct mlx5_priv *priv = dev->data->dev_private;
9490         struct mlx5_flow_counter *cnt;
9491         uint64_t inn_pkts, inn_bytes;
9492         int ret;
9493
9494         if (!priv->config.devx)
9495                 return -1;
9496
9497         ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
9498         if (ret)
9499                 return -1;
9500         cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
9501         *pkts = inn_pkts - cnt->hits;
9502         *bytes = inn_bytes - cnt->bytes;
9503         if (clear) {
9504                 cnt->hits = inn_pkts;
9505                 cnt->bytes = inn_bytes;
9506         }
9507         return 0;
9508 }
9509
9510 /**
9511  * Get aged-out flows.
9512  *
9513  * @param[in] dev
9514  *   Pointer to the Ethernet device structure.
9515  * @param[in] context
9516  *   The address of an array of pointers to the aged-out flows contexts.
9517  * @param[in] nb_contexts
9518  *   The length of context array pointers.
9519  * @param[out] error
9520  *   Perform verbose error reporting if not NULL. Initialized in case of
9521  *   error only.
9522  *
9523  * @return
9524  *   how many contexts get in success, otherwise negative errno value.
9525  *   if nb_contexts is 0, return the amount of all aged contexts.
9526  *   if nb_contexts is not 0 , return the amount of aged flows reported
9527  *   in the context array.
9528  * @note: only stub for now
9529  */
9530 static int
9531 flow_get_aged_flows(struct rte_eth_dev *dev,
9532                     void **context,
9533                     uint32_t nb_contexts,
9534                     struct rte_flow_error *error)
9535 {
9536         struct mlx5_priv *priv = dev->data->dev_private;
9537         struct mlx5_age_info *age_info;
9538         struct mlx5_age_param *age_param;
9539         struct mlx5_flow_counter *counter;
9540         int nb_flows = 0;
9541
9542         if (nb_contexts && !context)
9543                 return rte_flow_error_set(error, EINVAL,
9544                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9545                                           NULL,
9546                                           "Should assign at least one flow or"
9547                                           " context to get if nb_contexts != 0");
9548         age_info = GET_PORT_AGE_INFO(priv);
9549         rte_spinlock_lock(&age_info->aged_sl);
9550         TAILQ_FOREACH(counter, &age_info->aged_counters, next) {
9551                 nb_flows++;
9552                 if (nb_contexts) {
9553                         age_param = MLX5_CNT_TO_AGE(counter);
9554                         context[nb_flows - 1] = age_param->context;
9555                         if (!(--nb_contexts))
9556                                 break;
9557                 }
9558         }
9559         rte_spinlock_unlock(&age_info->aged_sl);
9560         MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
9561         return nb_flows;
9562 }
9563
9564 /*
9565  * Mutex-protected thunk to lock-free  __flow_dv_translate().
9566  */
9567 static int
9568 flow_dv_translate(struct rte_eth_dev *dev,
9569                   struct mlx5_flow *dev_flow,
9570                   const struct rte_flow_attr *attr,
9571                   const struct rte_flow_item items[],
9572                   const struct rte_flow_action actions[],
9573                   struct rte_flow_error *error)
9574 {
9575         int ret;
9576
9577         flow_dv_shared_lock(dev);
9578         ret = __flow_dv_translate(dev, dev_flow, attr, items, actions, error);
9579         flow_dv_shared_unlock(dev);
9580         return ret;
9581 }
9582
9583 /*
9584  * Mutex-protected thunk to lock-free  __flow_dv_apply().
9585  */
9586 static int
9587 flow_dv_apply(struct rte_eth_dev *dev,
9588               struct rte_flow *flow,
9589               struct rte_flow_error *error)
9590 {
9591         int ret;
9592
9593         flow_dv_shared_lock(dev);
9594         ret = __flow_dv_apply(dev, flow, error);
9595         flow_dv_shared_unlock(dev);
9596         return ret;
9597 }
9598
9599 /*
9600  * Mutex-protected thunk to lock-free __flow_dv_remove().
9601  */
9602 static void
9603 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
9604 {
9605         flow_dv_shared_lock(dev);
9606         __flow_dv_remove(dev, flow);
9607         flow_dv_shared_unlock(dev);
9608 }
9609
9610 /*
9611  * Mutex-protected thunk to lock-free __flow_dv_destroy().
9612  */
9613 static void
9614 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
9615 {
9616         flow_dv_shared_lock(dev);
9617         __flow_dv_destroy(dev, flow);
9618         flow_dv_shared_unlock(dev);
9619 }
9620
9621 /*
9622  * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
9623  */
9624 static uint32_t
9625 flow_dv_counter_allocate(struct rte_eth_dev *dev)
9626 {
9627         uint32_t cnt;
9628
9629         flow_dv_shared_lock(dev);
9630         cnt = flow_dv_counter_alloc(dev, 0, 0, 1, 0);
9631         flow_dv_shared_unlock(dev);
9632         return cnt;
9633 }
9634
9635 /*
9636  * Mutex-protected thunk to lock-free flow_dv_counter_release().
9637  */
9638 static void
9639 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t cnt)
9640 {
9641         flow_dv_shared_lock(dev);
9642         flow_dv_counter_release(dev, cnt);
9643         flow_dv_shared_unlock(dev);
9644 }
9645
9646 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
9647         .validate = flow_dv_validate,
9648         .prepare = flow_dv_prepare,
9649         .translate = flow_dv_translate,
9650         .apply = flow_dv_apply,
9651         .remove = flow_dv_remove,
9652         .destroy = flow_dv_destroy,
9653         .query = flow_dv_query,
9654         .create_mtr_tbls = flow_dv_create_mtr_tbl,
9655         .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
9656         .create_policer_rules = flow_dv_create_policer_rules,
9657         .destroy_policer_rules = flow_dv_destroy_policer_rules,
9658         .counter_alloc = flow_dv_counter_allocate,
9659         .counter_free = flow_dv_counter_free,
9660         .counter_query = flow_dv_counter_query,
9661         .get_aged_flows = flow_get_aged_flows,
9662 };
9663
9664 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */