drivers/net/mlx5/mlx5_flow_dv.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2018 Mellanox Technologies, Ltd
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdalign.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10
  11 #include <rte_common.h>
  12 #include <rte_ether.h>
  13 #include <rte_ethdev_driver.h>
  14 #include <rte_flow.h>
  15 #include <rte_flow_driver.h>
  16 #include <rte_malloc.h>
  17 #include <rte_cycles.h>
  18 #include <rte_ip.h>
  19 #include <rte_gre.h>
  20 #include <rte_vxlan.h>
  21 #include <rte_gtp.h>
  22 #include <rte_eal_paging.h>
  23 #include <rte_mpls.h>
  24
  25 #include <mlx5_glue.h>
  26 #include <mlx5_devx_cmds.h>
  27 #include <mlx5_prm.h>
  28 #include <mlx5_malloc.h>
  29
  30 #include "mlx5_defs.h"
  31 #include "mlx5.h"
  32 #include "mlx5_common_os.h"
  33 #include "mlx5_flow.h"
  34 #include "mlx5_flow_os.h"
  35 #include "mlx5_rxtx.h"
  36
  37 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
  38
  39 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
  40 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
  41 #endif
  42
  43 #ifndef HAVE_MLX5DV_DR_ESWITCH
  44 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
  45 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
  46 #endif
  47 #endif
  48
  49 #ifndef HAVE_MLX5DV_DR
  50 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
  51 #endif
  52
  53 /* VLAN header definitions */
  54 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
  55 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
  56 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
  57 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
  58 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
  59
  60 union flow_dv_attr {
  61         struct {
  62                 uint32_t valid:1;
  63                 uint32_t ipv4:1;
  64                 uint32_t ipv6:1;
  65                 uint32_t tcp:1;
  66                 uint32_t udp:1;
  67                 uint32_t reserved:27;
  68         };
  69         uint32_t attr;
  70 };
  71
  72 static int
  73 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
  74                              struct mlx5_flow_tbl_resource *tbl);
  75
  76 static int
  77 flow_dv_default_miss_resource_release(struct rte_eth_dev *dev);
  78
  79 static int
  80 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
  81                                       uint32_t encap_decap_idx);
  82
  83 /**
  84  * Initialize flow attributes structure according to flow items' types.
  85  *
  86  * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
  87  * mode. For tunnel mode, the items to be modified are the outermost ones.
  88  *
  89  * @param[in] item
  90  *   Pointer to item specification.
  91  * @param[out] attr
  92  *   Pointer to flow attributes structure.
  93  * @param[in] dev_flow
  94  *   Pointer to the sub flow.
  95  * @param[in] tunnel_decap
  96  *   Whether action is after tunnel decapsulation.
  97  */
  98 static void
  99 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
 100                   struct mlx5_flow *dev_flow, bool tunnel_decap)
 101 {
 102         uint64_t layers = dev_flow->handle->layers;
 103
 104         /*
 105          * If layers is already initialized, it means this dev_flow is the
 106          * suffix flow, the layers flags is set by the prefix flow. Need to
 107          * use the layer flags from prefix flow as the suffix flow may not
 108          * have the user defined items as the flow is split.
 109          */
 110         if (layers) {
 111                 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
 112                         attr->ipv4 = 1;
 113                 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
 114                         attr->ipv6 = 1;
 115                 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
 116                         attr->tcp = 1;
 117                 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
 118                         attr->udp = 1;
 119                 attr->valid = 1;
 120                 return;
 121         }
 122         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
 123                 uint8_t next_protocol = 0xff;
 124                 switch (item->type) {
 125                 case RTE_FLOW_ITEM_TYPE_GRE:
 126                 case RTE_FLOW_ITEM_TYPE_NVGRE:
 127                 case RTE_FLOW_ITEM_TYPE_VXLAN:
 128                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
 129                 case RTE_FLOW_ITEM_TYPE_GENEVE:
 130                 case RTE_FLOW_ITEM_TYPE_MPLS:
 131                         if (tunnel_decap)
 132                                 attr->attr = 0;
 133                         break;
 134                 case RTE_FLOW_ITEM_TYPE_IPV4:
 135                         if (!attr->ipv6)
 136                                 attr->ipv4 = 1;
 137                         if (item->mask != NULL &&
 138                             ((const struct rte_flow_item_ipv4 *)
 139                             item->mask)->hdr.next_proto_id)
 140                                 next_protocol =
 141                                     ((const struct rte_flow_item_ipv4 *)
 142                                       (item->spec))->hdr.next_proto_id &
 143                                     ((const struct rte_flow_item_ipv4 *)
 144                                       (item->mask))->hdr.next_proto_id;
 145                         if ((next_protocol == IPPROTO_IPIP ||
 146                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 147                                 attr->attr = 0;
 148                         break;
 149                 case RTE_FLOW_ITEM_TYPE_IPV6:
 150                         if (!attr->ipv4)
 151                                 attr->ipv6 = 1;
 152                         if (item->mask != NULL &&
 153                             ((const struct rte_flow_item_ipv6 *)
 154                             item->mask)->hdr.proto)
 155                                 next_protocol =
 156                                     ((const struct rte_flow_item_ipv6 *)
 157                                       (item->spec))->hdr.proto &
 158                                     ((const struct rte_flow_item_ipv6 *)
 159                                       (item->mask))->hdr.proto;
 160                         if ((next_protocol == IPPROTO_IPIP ||
 161                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 162                                 attr->attr = 0;
 163                         break;
 164                 case RTE_FLOW_ITEM_TYPE_UDP:
 165                         if (!attr->tcp)
 166                                 attr->udp = 1;
 167                         break;
 168                 case RTE_FLOW_ITEM_TYPE_TCP:
 169                         if (!attr->udp)
 170                                 attr->tcp = 1;
 171                         break;
 172                 default:
 173                         break;
 174                 }
 175         }
 176         attr->valid = 1;
 177 }
 178
 179 /**
 180  * Convert rte_mtr_color to mlx5 color.
 181  *
 182  * @param[in] rcol
 183  *   rte_mtr_color.
 184  *
 185  * @return
 186  *   mlx5 color.
 187  */
 188 static int
 189 rte_col_2_mlx5_col(enum rte_color rcol)
 190 {
 191         switch (rcol) {
 192         case RTE_COLOR_GREEN:
 193                 return MLX5_FLOW_COLOR_GREEN;
 194         case RTE_COLOR_YELLOW:
 195                 return MLX5_FLOW_COLOR_YELLOW;
 196         case RTE_COLOR_RED:
 197                 return MLX5_FLOW_COLOR_RED;
 198         default:
 199                 break;
 200         }
 201         return MLX5_FLOW_COLOR_UNDEFINED;
 202 }
 203
 204 struct field_modify_info {
 205         uint32_t size; /* Size of field in protocol header, in bytes. */
 206         uint32_t offset; /* Offset of field in protocol header, in bytes. */
 207         enum mlx5_modification_field id;
 208 };
 209
 210 struct field_modify_info modify_eth[] = {
 211         {4,  0, MLX5_MODI_OUT_DMAC_47_16},
 212         {2,  4, MLX5_MODI_OUT_DMAC_15_0},
 213         {4,  6, MLX5_MODI_OUT_SMAC_47_16},
 214         {2, 10, MLX5_MODI_OUT_SMAC_15_0},
 215         {0, 0, 0},
 216 };
 217
 218 struct field_modify_info modify_vlan_out_first_vid[] = {
 219         /* Size in bits !!! */
 220         {12, 0, MLX5_MODI_OUT_FIRST_VID},
 221         {0, 0, 0},
 222 };
 223
 224 struct field_modify_info modify_ipv4[] = {
 225         {1,  1, MLX5_MODI_OUT_IP_DSCP},
 226         {1,  8, MLX5_MODI_OUT_IPV4_TTL},
 227         {4, 12, MLX5_MODI_OUT_SIPV4},
 228         {4, 16, MLX5_MODI_OUT_DIPV4},
 229         {0, 0, 0},
 230 };
 231
 232 struct field_modify_info modify_ipv6[] = {
 233         {1,  0, MLX5_MODI_OUT_IP_DSCP},
 234         {1,  7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
 235         {4,  8, MLX5_MODI_OUT_SIPV6_127_96},
 236         {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
 237         {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
 238         {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
 239         {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
 240         {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
 241         {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
 242         {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
 243         {0, 0, 0},
 244 };
 245
 246 struct field_modify_info modify_udp[] = {
 247         {2, 0, MLX5_MODI_OUT_UDP_SPORT},
 248         {2, 2, MLX5_MODI_OUT_UDP_DPORT},
 249         {0, 0, 0},
 250 };
 251
 252 struct field_modify_info modify_tcp[] = {
 253         {2, 0, MLX5_MODI_OUT_TCP_SPORT},
 254         {2, 2, MLX5_MODI_OUT_TCP_DPORT},
 255         {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
 256         {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
 257         {0, 0, 0},
 258 };
 259
 260 static void
 261 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
 262                           uint8_t next_protocol, uint64_t *item_flags,
 263                           int *tunnel)
 264 {
 265         MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
 266                     item->type == RTE_FLOW_ITEM_TYPE_IPV6);
 267         if (next_protocol == IPPROTO_IPIP) {
 268                 *item_flags |= MLX5_FLOW_LAYER_IPIP;
 269                 *tunnel = 1;
 270         }
 271         if (next_protocol == IPPROTO_IPV6) {
 272                 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
 273                 *tunnel = 1;
 274         }
 275 }
 276
 277 /**
 278  * Acquire the synchronizing object to protect multithreaded access
 279  * to shared dv context. Lock occurs only if context is actually
 280  * shared, i.e. we have multiport IB device and representors are
 281  * created.
 282  *
 283  * @param[in] dev
 284  *   Pointer to the rte_eth_dev structure.
 285  */
 286 static void
 287 flow_dv_shared_lock(struct rte_eth_dev *dev)
 288 {
 289         struct mlx5_priv *priv = dev->data->dev_private;
 290         struct mlx5_dev_ctx_shared *sh = priv->sh;
 291
 292         if (sh->dv_refcnt > 1) {
 293                 int ret;
 294
 295                 ret = pthread_mutex_lock(&sh->dv_mutex);
 296                 MLX5_ASSERT(!ret);
 297                 (void)ret;
 298         }
 299 }
 300
 301 static void
 302 flow_dv_shared_unlock(struct rte_eth_dev *dev)
 303 {
 304         struct mlx5_priv *priv = dev->data->dev_private;
 305         struct mlx5_dev_ctx_shared *sh = priv->sh;
 306
 307         if (sh->dv_refcnt > 1) {
 308                 int ret;
 309
 310                 ret = pthread_mutex_unlock(&sh->dv_mutex);
 311                 MLX5_ASSERT(!ret);
 312                 (void)ret;
 313         }
 314 }
 315
 316 /* Update VLAN's VID/PCP based on input rte_flow_action.
 317  *
 318  * @param[in] action
 319  *   Pointer to struct rte_flow_action.
 320  * @param[out] vlan
 321  *   Pointer to struct rte_vlan_hdr.
 322  */
 323 static void
 324 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
 325                          struct rte_vlan_hdr *vlan)
 326 {
 327         uint16_t vlan_tci;
 328         if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
 329                 vlan_tci =
 330                     ((const struct rte_flow_action_of_set_vlan_pcp *)
 331                                                action->conf)->vlan_pcp;
 332                 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
 333                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
 334                 vlan->vlan_tci |= vlan_tci;
 335         } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
 336                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
 337                 vlan->vlan_tci |= rte_be_to_cpu_16
 338                     (((const struct rte_flow_action_of_set_vlan_vid *)
 339                                              action->conf)->vlan_vid);
 340         }
 341 }
 342
 343 /**
 344  * Fetch 1, 2, 3 or 4 byte field from the byte array
 345  * and return as unsigned integer in host-endian format.
 346  *
 347  * @param[in] data
 348  *   Pointer to data array.
 349  * @param[in] size
 350  *   Size of field to extract.
 351  *
 352  * @return
 353  *   converted field in host endian format.
 354  */
 355 static inline uint32_t
 356 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
 357 {
 358         uint32_t ret;
 359
 360         switch (size) {
 361         case 1:
 362                 ret = *data;
 363                 break;
 364         case 2:
 365                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 366                 break;
 367         case 3:
 368                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 369                 ret = (ret << 8) | *(data + sizeof(uint16_t));
 370                 break;
 371         case 4:
 372                 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
 373                 break;
 374         default:
 375                 MLX5_ASSERT(false);
 376                 ret = 0;
 377                 break;
 378         }
 379         return ret;
 380 }
 381
 382 /**
 383  * Convert modify-header action to DV specification.
 384  *
 385  * Data length of each action is determined by provided field description
 386  * and the item mask. Data bit offset and width of each action is determined
 387  * by provided item mask.
 388  *
 389  * @param[in] item
 390  *   Pointer to item specification.
 391  * @param[in] field
 392  *   Pointer to field modification information.
 393  *     For MLX5_MODIFICATION_TYPE_SET specifies destination field.
 394  *     For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
 395  *     For MLX5_MODIFICATION_TYPE_COPY specifies source field.
 396  * @param[in] dcopy
 397  *   Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
 398  *   Negative offset value sets the same offset as source offset.
 399  *   size field is ignored, value is taken from source field.
 400  * @param[in,out] resource
 401  *   Pointer to the modify-header resource.
 402  * @param[in] type
 403  *   Type of modification.
 404  * @param[out] error
 405  *   Pointer to the error structure.
 406  *
 407  * @return
 408  *   0 on success, a negative errno value otherwise and rte_errno is set.
 409  */
 410 static int
 411 flow_dv_convert_modify_action(struct rte_flow_item *item,
 412                               struct field_modify_info *field,
 413                               struct field_modify_info *dcopy,
 414                               struct mlx5_flow_dv_modify_hdr_resource *resource,
 415                               uint32_t type, struct rte_flow_error *error)
 416 {
 417         uint32_t i = resource->actions_num;
 418         struct mlx5_modification_cmd *actions = resource->actions;
 419
 420         /*
 421          * The item and mask are provided in big-endian format.
 422          * The fields should be presented as in big-endian format either.
 423          * Mask must be always present, it defines the actual field width.
 424          */
 425         MLX5_ASSERT(item->mask);
 426         MLX5_ASSERT(field->size);
 427         do {
 428                 unsigned int size_b;
 429                 unsigned int off_b;
 430                 uint32_t mask;
 431                 uint32_t data;
 432
 433                 if (i >= MLX5_MAX_MODIFY_NUM)
 434                         return rte_flow_error_set(error, EINVAL,
 435                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 436                                  "too many items to modify");
 437                 /* Fetch variable byte size mask from the array. */
 438                 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
 439                                            field->offset, field->size);
 440                 if (!mask) {
 441                         ++field;
 442                         continue;
 443                 }
 444                 /* Deduce actual data width in bits from mask value. */
 445                 off_b = rte_bsf32(mask);
 446                 size_b = sizeof(uint32_t) * CHAR_BIT -
 447                          off_b - __builtin_clz(mask);
 448                 MLX5_ASSERT(size_b);
 449                 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
 450                 actions[i] = (struct mlx5_modification_cmd) {
 451                         .action_type = type,
 452                         .field = field->id,
 453                         .offset = off_b,
 454                         .length = size_b,
 455                 };
 456                 /* Convert entire record to expected big-endian format. */
 457                 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 458                 if (type == MLX5_MODIFICATION_TYPE_COPY) {
 459                         MLX5_ASSERT(dcopy);
 460                         actions[i].dst_field = dcopy->id;
 461                         actions[i].dst_offset =
 462                                 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
 463                         /* Convert entire record to big-endian format. */
 464                         actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
 465                 } else {
 466                         MLX5_ASSERT(item->spec);
 467                         data = flow_dv_fetch_field((const uint8_t *)item->spec +
 468                                                    field->offset, field->size);
 469                         /* Shift out the trailing masked bits from data. */
 470                         data = (data & mask) >> off_b;
 471                         actions[i].data1 = rte_cpu_to_be_32(data);
 472                 }
 473                 ++i;
 474                 ++field;
 475         } while (field->size);
 476         if (resource->actions_num == i)
 477                 return rte_flow_error_set(error, EINVAL,
 478                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 479                                           "invalid modification flow item");
 480         resource->actions_num = i;
 481         return 0;
 482 }
 483
 484 /**
 485  * Convert modify-header set IPv4 address action to DV specification.
 486  *
 487  * @param[in,out] resource
 488  *   Pointer to the modify-header resource.
 489  * @param[in] action
 490  *   Pointer to action specification.
 491  * @param[out] error
 492  *   Pointer to the error structure.
 493  *
 494  * @return
 495  *   0 on success, a negative errno value otherwise and rte_errno is set.
 496  */
 497 static int
 498 flow_dv_convert_action_modify_ipv4
 499                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 500                          const struct rte_flow_action *action,
 501                          struct rte_flow_error *error)
 502 {
 503         const struct rte_flow_action_set_ipv4 *conf =
 504                 (const struct rte_flow_action_set_ipv4 *)(action->conf);
 505         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
 506         struct rte_flow_item_ipv4 ipv4;
 507         struct rte_flow_item_ipv4 ipv4_mask;
 508
 509         memset(&ipv4, 0, sizeof(ipv4));
 510         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 511         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
 512                 ipv4.hdr.src_addr = conf->ipv4_addr;
 513                 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
 514         } else {
 515                 ipv4.hdr.dst_addr = conf->ipv4_addr;
 516                 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
 517         }
 518         item.spec = &ipv4;
 519         item.mask = &ipv4_mask;
 520         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
 521                                              MLX5_MODIFICATION_TYPE_SET, error);
 522 }
 523
 524 /**
 525  * Convert modify-header set IPv6 address action to DV specification.
 526  *
 527  * @param[in,out] resource
 528  *   Pointer to the modify-header resource.
 529  * @param[in] action
 530  *   Pointer to action specification.
 531  * @param[out] error
 532  *   Pointer to the error structure.
 533  *
 534  * @return
 535  *   0 on success, a negative errno value otherwise and rte_errno is set.
 536  */
 537 static int
 538 flow_dv_convert_action_modify_ipv6
 539                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 540                          const struct rte_flow_action *action,
 541                          struct rte_flow_error *error)
 542 {
 543         const struct rte_flow_action_set_ipv6 *conf =
 544                 (const struct rte_flow_action_set_ipv6 *)(action->conf);
 545         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
 546         struct rte_flow_item_ipv6 ipv6;
 547         struct rte_flow_item_ipv6 ipv6_mask;
 548
 549         memset(&ipv6, 0, sizeof(ipv6));
 550         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 551         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
 552                 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
 553                        sizeof(ipv6.hdr.src_addr));
 554                 memcpy(&ipv6_mask.hdr.src_addr,
 555                        &rte_flow_item_ipv6_mask.hdr.src_addr,
 556                        sizeof(ipv6.hdr.src_addr));
 557         } else {
 558                 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
 559                        sizeof(ipv6.hdr.dst_addr));
 560                 memcpy(&ipv6_mask.hdr.dst_addr,
 561                        &rte_flow_item_ipv6_mask.hdr.dst_addr,
 562                        sizeof(ipv6.hdr.dst_addr));
 563         }
 564         item.spec = &ipv6;
 565         item.mask = &ipv6_mask;
 566         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
 567                                              MLX5_MODIFICATION_TYPE_SET, error);
 568 }
 569
 570 /**
 571  * Convert modify-header set MAC address action to DV specification.
 572  *
 573  * @param[in,out] resource
 574  *   Pointer to the modify-header resource.
 575  * @param[in] action
 576  *   Pointer to action specification.
 577  * @param[out] error
 578  *   Pointer to the error structure.
 579  *
 580  * @return
 581  *   0 on success, a negative errno value otherwise and rte_errno is set.
 582  */
 583 static int
 584 flow_dv_convert_action_modify_mac
 585                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 586                          const struct rte_flow_action *action,
 587                          struct rte_flow_error *error)
 588 {
 589         const struct rte_flow_action_set_mac *conf =
 590                 (const struct rte_flow_action_set_mac *)(action->conf);
 591         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
 592         struct rte_flow_item_eth eth;
 593         struct rte_flow_item_eth eth_mask;
 594
 595         memset(&eth, 0, sizeof(eth));
 596         memset(&eth_mask, 0, sizeof(eth_mask));
 597         if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
 598                 memcpy(&eth.src.addr_bytes, &conf->mac_addr,
 599                        sizeof(eth.src.addr_bytes));
 600                 memcpy(&eth_mask.src.addr_bytes,
 601                        &rte_flow_item_eth_mask.src.addr_bytes,
 602                        sizeof(eth_mask.src.addr_bytes));
 603         } else {
 604                 memcpy(&eth.dst.addr_bytes, &conf->mac_addr,
 605                        sizeof(eth.dst.addr_bytes));
 606                 memcpy(&eth_mask.dst.addr_bytes,
 607                        &rte_flow_item_eth_mask.dst.addr_bytes,
 608                        sizeof(eth_mask.dst.addr_bytes));
 609         }
 610         item.spec = &eth;
 611         item.mask = &eth_mask;
 612         return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
 613                                              MLX5_MODIFICATION_TYPE_SET, error);
 614 }
 615
 616 /**
 617  * Convert modify-header set VLAN VID action to DV specification.
 618  *
 619  * @param[in,out] resource
 620  *   Pointer to the modify-header resource.
 621  * @param[in] action
 622  *   Pointer to action specification.
 623  * @param[out] error
 624  *   Pointer to the error structure.
 625  *
 626  * @return
 627  *   0 on success, a negative errno value otherwise and rte_errno is set.
 628  */
 629 static int
 630 flow_dv_convert_action_modify_vlan_vid
 631                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 632                          const struct rte_flow_action *action,
 633                          struct rte_flow_error *error)
 634 {
 635         const struct rte_flow_action_of_set_vlan_vid *conf =
 636                 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
 637         int i = resource->actions_num;
 638         struct mlx5_modification_cmd *actions = resource->actions;
 639         struct field_modify_info *field = modify_vlan_out_first_vid;
 640
 641         if (i >= MLX5_MAX_MODIFY_NUM)
 642                 return rte_flow_error_set(error, EINVAL,
 643                          RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 644                          "too many items to modify");
 645         actions[i] = (struct mlx5_modification_cmd) {
 646                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 647                 .field = field->id,
 648                 .length = field->size,
 649                 .offset = field->offset,
 650         };
 651         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 652         actions[i].data1 = conf->vlan_vid;
 653         actions[i].data1 = actions[i].data1 << 16;
 654         resource->actions_num = ++i;
 655         return 0;
 656 }
 657
 658 /**
 659  * Convert modify-header set TP action to DV specification.
 660  *
 661  * @param[in,out] resource
 662  *   Pointer to the modify-header resource.
 663  * @param[in] action
 664  *   Pointer to action specification.
 665  * @param[in] items
 666  *   Pointer to rte_flow_item objects list.
 667  * @param[in] attr
 668  *   Pointer to flow attributes structure.
 669  * @param[in] dev_flow
 670  *   Pointer to the sub flow.
 671  * @param[in] tunnel_decap
 672  *   Whether action is after tunnel decapsulation.
 673  * @param[out] error
 674  *   Pointer to the error structure.
 675  *
 676  * @return
 677  *   0 on success, a negative errno value otherwise and rte_errno is set.
 678  */
 679 static int
 680 flow_dv_convert_action_modify_tp
 681                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 682                          const struct rte_flow_action *action,
 683                          const struct rte_flow_item *items,
 684                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 685                          bool tunnel_decap, struct rte_flow_error *error)
 686 {
 687         const struct rte_flow_action_set_tp *conf =
 688                 (const struct rte_flow_action_set_tp *)(action->conf);
 689         struct rte_flow_item item;
 690         struct rte_flow_item_udp udp;
 691         struct rte_flow_item_udp udp_mask;
 692         struct rte_flow_item_tcp tcp;
 693         struct rte_flow_item_tcp tcp_mask;
 694         struct field_modify_info *field;
 695
 696         if (!attr->valid)
 697                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 698         if (attr->udp) {
 699                 memset(&udp, 0, sizeof(udp));
 700                 memset(&udp_mask, 0, sizeof(udp_mask));
 701                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 702                         udp.hdr.src_port = conf->port;
 703                         udp_mask.hdr.src_port =
 704                                         rte_flow_item_udp_mask.hdr.src_port;
 705                 } else {
 706                         udp.hdr.dst_port = conf->port;
 707                         udp_mask.hdr.dst_port =
 708                                         rte_flow_item_udp_mask.hdr.dst_port;
 709                 }
 710                 item.type = RTE_FLOW_ITEM_TYPE_UDP;
 711                 item.spec = &udp;
 712                 item.mask = &udp_mask;
 713                 field = modify_udp;
 714         } else {
 715                 MLX5_ASSERT(attr->tcp);
 716                 memset(&tcp, 0, sizeof(tcp));
 717                 memset(&tcp_mask, 0, sizeof(tcp_mask));
 718                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 719                         tcp.hdr.src_port = conf->port;
 720                         tcp_mask.hdr.src_port =
 721                                         rte_flow_item_tcp_mask.hdr.src_port;
 722                 } else {
 723                         tcp.hdr.dst_port = conf->port;
 724                         tcp_mask.hdr.dst_port =
 725                                         rte_flow_item_tcp_mask.hdr.dst_port;
 726                 }
 727                 item.type = RTE_FLOW_ITEM_TYPE_TCP;
 728                 item.spec = &tcp;
 729                 item.mask = &tcp_mask;
 730                 field = modify_tcp;
 731         }
 732         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 733                                              MLX5_MODIFICATION_TYPE_SET, error);
 734 }
 735
 736 /**
 737  * Convert modify-header set TTL action to DV specification.
 738  *
 739  * @param[in,out] resource
 740  *   Pointer to the modify-header resource.
 741  * @param[in] action
 742  *   Pointer to action specification.
 743  * @param[in] items
 744  *   Pointer to rte_flow_item objects list.
 745  * @param[in] attr
 746  *   Pointer to flow attributes structure.
 747  * @param[in] dev_flow
 748  *   Pointer to the sub flow.
 749  * @param[in] tunnel_decap
 750  *   Whether action is after tunnel decapsulation.
 751  * @param[out] error
 752  *   Pointer to the error structure.
 753  *
 754  * @return
 755  *   0 on success, a negative errno value otherwise and rte_errno is set.
 756  */
 757 static int
 758 flow_dv_convert_action_modify_ttl
 759                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 760                          const struct rte_flow_action *action,
 761                          const struct rte_flow_item *items,
 762                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 763                          bool tunnel_decap, struct rte_flow_error *error)
 764 {
 765         const struct rte_flow_action_set_ttl *conf =
 766                 (const struct rte_flow_action_set_ttl *)(action->conf);
 767         struct rte_flow_item item;
 768         struct rte_flow_item_ipv4 ipv4;
 769         struct rte_flow_item_ipv4 ipv4_mask;
 770         struct rte_flow_item_ipv6 ipv6;
 771         struct rte_flow_item_ipv6 ipv6_mask;
 772         struct field_modify_info *field;
 773
 774         if (!attr->valid)
 775                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 776         if (attr->ipv4) {
 777                 memset(&ipv4, 0, sizeof(ipv4));
 778                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 779                 ipv4.hdr.time_to_live = conf->ttl_value;
 780                 ipv4_mask.hdr.time_to_live = 0xFF;
 781                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 782                 item.spec = &ipv4;
 783                 item.mask = &ipv4_mask;
 784                 field = modify_ipv4;
 785         } else {
 786                 MLX5_ASSERT(attr->ipv6);
 787                 memset(&ipv6, 0, sizeof(ipv6));
 788                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 789                 ipv6.hdr.hop_limits = conf->ttl_value;
 790                 ipv6_mask.hdr.hop_limits = 0xFF;
 791                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 792                 item.spec = &ipv6;
 793                 item.mask = &ipv6_mask;
 794                 field = modify_ipv6;
 795         }
 796         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 797                                              MLX5_MODIFICATION_TYPE_SET, error);
 798 }
 799
 800 /**
 801  * Convert modify-header decrement TTL action to DV specification.
 802  *
 803  * @param[in,out] resource
 804  *   Pointer to the modify-header resource.
 805  * @param[in] action
 806  *   Pointer to action specification.
 807  * @param[in] items
 808  *   Pointer to rte_flow_item objects list.
 809  * @param[in] attr
 810  *   Pointer to flow attributes structure.
 811  * @param[in] dev_flow
 812  *   Pointer to the sub flow.
 813  * @param[in] tunnel_decap
 814  *   Whether action is after tunnel decapsulation.
 815  * @param[out] error
 816  *   Pointer to the error structure.
 817  *
 818  * @return
 819  *   0 on success, a negative errno value otherwise and rte_errno is set.
 820  */
 821 static int
 822 flow_dv_convert_action_modify_dec_ttl
 823                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 824                          const struct rte_flow_item *items,
 825                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 826                          bool tunnel_decap, struct rte_flow_error *error)
 827 {
 828         struct rte_flow_item item;
 829         struct rte_flow_item_ipv4 ipv4;
 830         struct rte_flow_item_ipv4 ipv4_mask;
 831         struct rte_flow_item_ipv6 ipv6;
 832         struct rte_flow_item_ipv6 ipv6_mask;
 833         struct field_modify_info *field;
 834
 835         if (!attr->valid)
 836                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 837         if (attr->ipv4) {
 838                 memset(&ipv4, 0, sizeof(ipv4));
 839                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 840                 ipv4.hdr.time_to_live = 0xFF;
 841                 ipv4_mask.hdr.time_to_live = 0xFF;
 842                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 843                 item.spec = &ipv4;
 844                 item.mask = &ipv4_mask;
 845                 field = modify_ipv4;
 846         } else {
 847                 MLX5_ASSERT(attr->ipv6);
 848                 memset(&ipv6, 0, sizeof(ipv6));
 849                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 850                 ipv6.hdr.hop_limits = 0xFF;
 851                 ipv6_mask.hdr.hop_limits = 0xFF;
 852                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 853                 item.spec = &ipv6;
 854                 item.mask = &ipv6_mask;
 855                 field = modify_ipv6;
 856         }
 857         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 858                                              MLX5_MODIFICATION_TYPE_ADD, error);
 859 }
 860
 861 /**
 862  * Convert modify-header increment/decrement TCP Sequence number
 863  * to DV specification.
 864  *
 865  * @param[in,out] resource
 866  *   Pointer to the modify-header resource.
 867  * @param[in] action
 868  *   Pointer to action specification.
 869  * @param[out] error
 870  *   Pointer to the error structure.
 871  *
 872  * @return
 873  *   0 on success, a negative errno value otherwise and rte_errno is set.
 874  */
 875 static int
 876 flow_dv_convert_action_modify_tcp_seq
 877                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 878                          const struct rte_flow_action *action,
 879                          struct rte_flow_error *error)
 880 {
 881         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 882         uint64_t value = rte_be_to_cpu_32(*conf);
 883         struct rte_flow_item item;
 884         struct rte_flow_item_tcp tcp;
 885         struct rte_flow_item_tcp tcp_mask;
 886
 887         memset(&tcp, 0, sizeof(tcp));
 888         memset(&tcp_mask, 0, sizeof(tcp_mask));
 889         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
 890                 /*
 891                  * The HW has no decrement operation, only increment operation.
 892                  * To simulate decrement X from Y using increment operation
 893                  * we need to add UINT32_MAX X times to Y.
 894                  * Each adding of UINT32_MAX decrements Y by 1.
 895                  */
 896                 value *= UINT32_MAX;
 897         tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
 898         tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
 899         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 900         item.spec = &tcp;
 901         item.mask = &tcp_mask;
 902         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 903                                              MLX5_MODIFICATION_TYPE_ADD, error);
 904 }
 905
 906 /**
 907  * Convert modify-header increment/decrement TCP Acknowledgment number
 908  * to DV specification.
 909  *
 910  * @param[in,out] resource
 911  *   Pointer to the modify-header resource.
 912  * @param[in] action
 913  *   Pointer to action specification.
 914  * @param[out] error
 915  *   Pointer to the error structure.
 916  *
 917  * @return
 918  *   0 on success, a negative errno value otherwise and rte_errno is set.
 919  */
 920 static int
 921 flow_dv_convert_action_modify_tcp_ack
 922                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 923                          const struct rte_flow_action *action,
 924                          struct rte_flow_error *error)
 925 {
 926         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 927         uint64_t value = rte_be_to_cpu_32(*conf);
 928         struct rte_flow_item item;
 929         struct rte_flow_item_tcp tcp;
 930         struct rte_flow_item_tcp tcp_mask;
 931
 932         memset(&tcp, 0, sizeof(tcp));
 933         memset(&tcp_mask, 0, sizeof(tcp_mask));
 934         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
 935                 /*
 936                  * The HW has no decrement operation, only increment operation.
 937                  * To simulate decrement X from Y using increment operation
 938                  * we need to add UINT32_MAX X times to Y.
 939                  * Each adding of UINT32_MAX decrements Y by 1.
 940                  */
 941                 value *= UINT32_MAX;
 942         tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
 943         tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
 944         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 945         item.spec = &tcp;
 946         item.mask = &tcp_mask;
 947         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 948                                              MLX5_MODIFICATION_TYPE_ADD, error);
 949 }
 950
 951 static enum mlx5_modification_field reg_to_field[] = {
 952         [REG_NON] = MLX5_MODI_OUT_NONE,
 953         [REG_A] = MLX5_MODI_META_DATA_REG_A,
 954         [REG_B] = MLX5_MODI_META_DATA_REG_B,
 955         [REG_C_0] = MLX5_MODI_META_REG_C_0,
 956         [REG_C_1] = MLX5_MODI_META_REG_C_1,
 957         [REG_C_2] = MLX5_MODI_META_REG_C_2,
 958         [REG_C_3] = MLX5_MODI_META_REG_C_3,
 959         [REG_C_4] = MLX5_MODI_META_REG_C_4,
 960         [REG_C_5] = MLX5_MODI_META_REG_C_5,
 961         [REG_C_6] = MLX5_MODI_META_REG_C_6,
 962         [REG_C_7] = MLX5_MODI_META_REG_C_7,
 963 };
 964
 965 /**
 966  * Convert register set to DV specification.
 967  *
 968  * @param[in,out] resource
 969  *   Pointer to the modify-header resource.
 970  * @param[in] action
 971  *   Pointer to action specification.
 972  * @param[out] error
 973  *   Pointer to the error structure.
 974  *
 975  * @return
 976  *   0 on success, a negative errno value otherwise and rte_errno is set.
 977  */
 978 static int
 979 flow_dv_convert_action_set_reg
 980                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 981                          const struct rte_flow_action *action,
 982                          struct rte_flow_error *error)
 983 {
 984         const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
 985         struct mlx5_modification_cmd *actions = resource->actions;
 986         uint32_t i = resource->actions_num;
 987
 988         if (i >= MLX5_MAX_MODIFY_NUM)
 989                 return rte_flow_error_set(error, EINVAL,
 990                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 991                                           "too many items to modify");
 992         MLX5_ASSERT(conf->id != REG_NON);
 993         MLX5_ASSERT(conf->id < RTE_DIM(reg_to_field));
 994         actions[i] = (struct mlx5_modification_cmd) {
 995                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 996                 .field = reg_to_field[conf->id],
 997         };
 998         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 999         actions[i].data1 = rte_cpu_to_be_32(conf->data);
1000         ++i;
1001         resource->actions_num = i;
1002         return 0;
1003 }
1004
1005 /**
1006  * Convert SET_TAG action to DV specification.
1007  *
1008  * @param[in] dev
1009  *   Pointer to the rte_eth_dev structure.
1010  * @param[in,out] resource
1011  *   Pointer to the modify-header resource.
1012  * @param[in] conf
1013  *   Pointer to action specification.
1014  * @param[out] error
1015  *   Pointer to the error structure.
1016  *
1017  * @return
1018  *   0 on success, a negative errno value otherwise and rte_errno is set.
1019  */
1020 static int
1021 flow_dv_convert_action_set_tag
1022                         (struct rte_eth_dev *dev,
1023                          struct mlx5_flow_dv_modify_hdr_resource *resource,
1024                          const struct rte_flow_action_set_tag *conf,
1025                          struct rte_flow_error *error)
1026 {
1027         rte_be32_t data = rte_cpu_to_be_32(conf->data);
1028         rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
1029         struct rte_flow_item item = {
1030                 .spec = &data,
1031                 .mask = &mask,
1032         };
1033         struct field_modify_info reg_c_x[] = {
1034                 [1] = {0, 0, 0},
1035         };
1036         enum mlx5_modification_field reg_type;
1037         int ret;
1038
1039         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1040         if (ret < 0)
1041                 return ret;
1042         MLX5_ASSERT(ret != REG_NON);
1043         MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1044         reg_type = reg_to_field[ret];
1045         MLX5_ASSERT(reg_type > 0);
1046         reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1047         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1048                                              MLX5_MODIFICATION_TYPE_SET, error);
1049 }
1050
1051 /**
1052  * Convert internal COPY_REG action to DV specification.
1053  *
1054  * @param[in] dev
1055  *   Pointer to the rte_eth_dev structure.
1056  * @param[in,out] res
1057  *   Pointer to the modify-header resource.
1058  * @param[in] action
1059  *   Pointer to action specification.
1060  * @param[out] error
1061  *   Pointer to the error structure.
1062  *
1063  * @return
1064  *   0 on success, a negative errno value otherwise and rte_errno is set.
1065  */
1066 static int
1067 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1068                                  struct mlx5_flow_dv_modify_hdr_resource *res,
1069                                  const struct rte_flow_action *action,
1070                                  struct rte_flow_error *error)
1071 {
1072         const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1073         rte_be32_t mask = RTE_BE32(UINT32_MAX);
1074         struct rte_flow_item item = {
1075                 .spec = NULL,
1076                 .mask = &mask,
1077         };
1078         struct field_modify_info reg_src[] = {
1079                 {4, 0, reg_to_field[conf->src]},
1080                 {0, 0, 0},
1081         };
1082         struct field_modify_info reg_dst = {
1083                 .offset = 0,
1084                 .id = reg_to_field[conf->dst],
1085         };
1086         /* Adjust reg_c[0] usage according to reported mask. */
1087         if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1088                 struct mlx5_priv *priv = dev->data->dev_private;
1089                 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1090
1091                 MLX5_ASSERT(reg_c0);
1092                 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1093                 if (conf->dst == REG_C_0) {
1094                         /* Copy to reg_c[0], within mask only. */
1095                         reg_dst.offset = rte_bsf32(reg_c0);
1096                         /*
1097                          * Mask is ignoring the enianness, because
1098                          * there is no conversion in datapath.
1099                          */
1100 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1101                         /* Copy from destination lower bits to reg_c[0]. */
1102                         mask = reg_c0 >> reg_dst.offset;
1103 #else
1104                         /* Copy from destination upper bits to reg_c[0]. */
1105                         mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1106                                           rte_fls_u32(reg_c0));
1107 #endif
1108                 } else {
1109                         mask = rte_cpu_to_be_32(reg_c0);
1110 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1111                         /* Copy from reg_c[0] to destination lower bits. */
1112                         reg_dst.offset = 0;
1113 #else
1114                         /* Copy from reg_c[0] to destination upper bits. */
1115                         reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1116                                          (rte_fls_u32(reg_c0) -
1117                                           rte_bsf32(reg_c0));
1118 #endif
1119                 }
1120         }
1121         return flow_dv_convert_modify_action(&item,
1122                                              reg_src, &reg_dst, res,
1123                                              MLX5_MODIFICATION_TYPE_COPY,
1124                                              error);
1125 }
1126
1127 /**
1128  * Convert MARK action to DV specification. This routine is used
1129  * in extensive metadata only and requires metadata register to be
1130  * handled. In legacy mode hardware tag resource is engaged.
1131  *
1132  * @param[in] dev
1133  *   Pointer to the rte_eth_dev structure.
1134  * @param[in] conf
1135  *   Pointer to MARK action specification.
1136  * @param[in,out] resource
1137  *   Pointer to the modify-header resource.
1138  * @param[out] error
1139  *   Pointer to the error structure.
1140  *
1141  * @return
1142  *   0 on success, a negative errno value otherwise and rte_errno is set.
1143  */
1144 static int
1145 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1146                             const struct rte_flow_action_mark *conf,
1147                             struct mlx5_flow_dv_modify_hdr_resource *resource,
1148                             struct rte_flow_error *error)
1149 {
1150         struct mlx5_priv *priv = dev->data->dev_private;
1151         rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1152                                            priv->sh->dv_mark_mask);
1153         rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1154         struct rte_flow_item item = {
1155                 .spec = &data,
1156                 .mask = &mask,
1157         };
1158         struct field_modify_info reg_c_x[] = {
1159                 [1] = {0, 0, 0},
1160         };
1161         int reg;
1162
1163         if (!mask)
1164                 return rte_flow_error_set(error, EINVAL,
1165                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1166                                           NULL, "zero mark action mask");
1167         reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1168         if (reg < 0)
1169                 return reg;
1170         MLX5_ASSERT(reg > 0);
1171         if (reg == REG_C_0) {
1172                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1173                 uint32_t shl_c0 = rte_bsf32(msk_c0);
1174
1175                 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1176                 mask = rte_cpu_to_be_32(mask) & msk_c0;
1177                 mask = rte_cpu_to_be_32(mask << shl_c0);
1178         }
1179         reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1180         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1181                                              MLX5_MODIFICATION_TYPE_SET, error);
1182 }
1183
1184 /**
1185  * Get metadata register index for specified steering domain.
1186  *
1187  * @param[in] dev
1188  *   Pointer to the rte_eth_dev structure.
1189  * @param[in] attr
1190  *   Attributes of flow to determine steering domain.
1191  * @param[out] error
1192  *   Pointer to the error structure.
1193  *
1194  * @return
1195  *   positive index on success, a negative errno value otherwise
1196  *   and rte_errno is set.
1197  */
1198 static enum modify_reg
1199 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1200                          const struct rte_flow_attr *attr,
1201                          struct rte_flow_error *error)
1202 {
1203         int reg =
1204                 mlx5_flow_get_reg_id(dev, attr->transfer ?
1205                                           MLX5_METADATA_FDB :
1206                                             attr->egress ?
1207                                             MLX5_METADATA_TX :
1208                                             MLX5_METADATA_RX, 0, error);
1209         if (reg < 0)
1210                 return rte_flow_error_set(error,
1211                                           ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1212                                           NULL, "unavailable "
1213                                           "metadata register");
1214         return reg;
1215 }
1216
1217 /**
1218  * Convert SET_META action to DV specification.
1219  *
1220  * @param[in] dev
1221  *   Pointer to the rte_eth_dev structure.
1222  * @param[in,out] resource
1223  *   Pointer to the modify-header resource.
1224  * @param[in] attr
1225  *   Attributes of flow that includes this item.
1226  * @param[in] conf
1227  *   Pointer to action specification.
1228  * @param[out] error
1229  *   Pointer to the error structure.
1230  *
1231  * @return
1232  *   0 on success, a negative errno value otherwise and rte_errno is set.
1233  */
1234 static int
1235 flow_dv_convert_action_set_meta
1236                         (struct rte_eth_dev *dev,
1237                          struct mlx5_flow_dv_modify_hdr_resource *resource,
1238                          const struct rte_flow_attr *attr,
1239                          const struct rte_flow_action_set_meta *conf,
1240                          struct rte_flow_error *error)
1241 {
1242         uint32_t data = conf->data;
1243         uint32_t mask = conf->mask;
1244         struct rte_flow_item item = {
1245                 .spec = &data,
1246                 .mask = &mask,
1247         };
1248         struct field_modify_info reg_c_x[] = {
1249                 [1] = {0, 0, 0},
1250         };
1251         int reg = flow_dv_get_metadata_reg(dev, attr, error);
1252
1253         if (reg < 0)
1254                 return reg;
1255         /*
1256          * In datapath code there is no endianness
1257          * coversions for perfromance reasons, all
1258          * pattern conversions are done in rte_flow.
1259          */
1260         if (reg == REG_C_0) {
1261                 struct mlx5_priv *priv = dev->data->dev_private;
1262                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1263                 uint32_t shl_c0;
1264
1265                 MLX5_ASSERT(msk_c0);
1266 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1267                 shl_c0 = rte_bsf32(msk_c0);
1268 #else
1269                 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1270 #endif
1271                 mask <<= shl_c0;
1272                 data <<= shl_c0;
1273                 MLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1274         }
1275         reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1276         /* The routine expects parameters in memory as big-endian ones. */
1277         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1278                                              MLX5_MODIFICATION_TYPE_SET, error);
1279 }
1280
1281 /**
1282  * Convert modify-header set IPv4 DSCP action to DV specification.
1283  *
1284  * @param[in,out] resource
1285  *   Pointer to the modify-header resource.
1286  * @param[in] action
1287  *   Pointer to action specification.
1288  * @param[out] error
1289  *   Pointer to the error structure.
1290  *
1291  * @return
1292  *   0 on success, a negative errno value otherwise and rte_errno is set.
1293  */
1294 static int
1295 flow_dv_convert_action_modify_ipv4_dscp
1296                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1297                          const struct rte_flow_action *action,
1298                          struct rte_flow_error *error)
1299 {
1300         const struct rte_flow_action_set_dscp *conf =
1301                 (const struct rte_flow_action_set_dscp *)(action->conf);
1302         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1303         struct rte_flow_item_ipv4 ipv4;
1304         struct rte_flow_item_ipv4 ipv4_mask;
1305
1306         memset(&ipv4, 0, sizeof(ipv4));
1307         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1308         ipv4.hdr.type_of_service = conf->dscp;
1309         ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1310         item.spec = &ipv4;
1311         item.mask = &ipv4_mask;
1312         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1313                                              MLX5_MODIFICATION_TYPE_SET, error);
1314 }
1315
1316 /**
1317  * Convert modify-header set IPv6 DSCP action to DV specification.
1318  *
1319  * @param[in,out] resource
1320  *   Pointer to the modify-header resource.
1321  * @param[in] action
1322  *   Pointer to action specification.
1323  * @param[out] error
1324  *   Pointer to the error structure.
1325  *
1326  * @return
1327  *   0 on success, a negative errno value otherwise and rte_errno is set.
1328  */
1329 static int
1330 flow_dv_convert_action_modify_ipv6_dscp
1331                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1332                          const struct rte_flow_action *action,
1333                          struct rte_flow_error *error)
1334 {
1335         const struct rte_flow_action_set_dscp *conf =
1336                 (const struct rte_flow_action_set_dscp *)(action->conf);
1337         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1338         struct rte_flow_item_ipv6 ipv6;
1339         struct rte_flow_item_ipv6 ipv6_mask;
1340
1341         memset(&ipv6, 0, sizeof(ipv6));
1342         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1343         /*
1344          * Even though the DSCP bits offset of IPv6 is not byte aligned,
1345          * rdma-core only accept the DSCP bits byte aligned start from
1346          * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1347          * bits in IPv6 case as rdma-core requires byte aligned value.
1348          */
1349         ipv6.hdr.vtc_flow = conf->dscp;
1350         ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1351         item.spec = &ipv6;
1352         item.mask = &ipv6_mask;
1353         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1354                                              MLX5_MODIFICATION_TYPE_SET, error);
1355 }
1356
1357 /**
1358  * Validate MARK item.
1359  *
1360  * @param[in] dev
1361  *   Pointer to the rte_eth_dev structure.
1362  * @param[in] item
1363  *   Item specification.
1364  * @param[in] attr
1365  *   Attributes of flow that includes this item.
1366  * @param[out] error
1367  *   Pointer to error structure.
1368  *
1369  * @return
1370  *   0 on success, a negative errno value otherwise and rte_errno is set.
1371  */
1372 static int
1373 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1374                            const struct rte_flow_item *item,
1375                            const struct rte_flow_attr *attr __rte_unused,
1376                            struct rte_flow_error *error)
1377 {
1378         struct mlx5_priv *priv = dev->data->dev_private;
1379         struct mlx5_dev_config *config = &priv->config;
1380         const struct rte_flow_item_mark *spec = item->spec;
1381         const struct rte_flow_item_mark *mask = item->mask;
1382         const struct rte_flow_item_mark nic_mask = {
1383                 .id = priv->sh->dv_mark_mask,
1384         };
1385         int ret;
1386
1387         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1388                 return rte_flow_error_set(error, ENOTSUP,
1389                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1390                                           "extended metadata feature"
1391                                           " isn't enabled");
1392         if (!mlx5_flow_ext_mreg_supported(dev))
1393                 return rte_flow_error_set(error, ENOTSUP,
1394                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1395                                           "extended metadata register"
1396                                           " isn't supported");
1397         if (!nic_mask.id)
1398                 return rte_flow_error_set(error, ENOTSUP,
1399                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1400                                           "extended metadata register"
1401                                           " isn't available");
1402         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1403         if (ret < 0)
1404                 return ret;
1405         if (!spec)
1406                 return rte_flow_error_set(error, EINVAL,
1407                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1408                                           item->spec,
1409                                           "data cannot be empty");
1410         if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1411                 return rte_flow_error_set(error, EINVAL,
1412                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1413                                           &spec->id,
1414                                           "mark id exceeds the limit");
1415         if (!mask)
1416                 mask = &nic_mask;
1417         if (!mask->id)
1418                 return rte_flow_error_set(error, EINVAL,
1419                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1420                                         "mask cannot be zero");
1421
1422         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1423                                         (const uint8_t *)&nic_mask,
1424                                         sizeof(struct rte_flow_item_mark),
1425                                         error);
1426         if (ret < 0)
1427                 return ret;
1428         return 0;
1429 }
1430
1431 /**
1432  * Validate META item.
1433  *
1434  * @param[in] dev
1435  *   Pointer to the rte_eth_dev structure.
1436  * @param[in] item
1437  *   Item specification.
1438  * @param[in] attr
1439  *   Attributes of flow that includes this item.
1440  * @param[out] error
1441  *   Pointer to error structure.
1442  *
1443  * @return
1444  *   0 on success, a negative errno value otherwise and rte_errno is set.
1445  */
1446 static int
1447 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1448                            const struct rte_flow_item *item,
1449                            const struct rte_flow_attr *attr,
1450                            struct rte_flow_error *error)
1451 {
1452         struct mlx5_priv *priv = dev->data->dev_private;
1453         struct mlx5_dev_config *config = &priv->config;
1454         const struct rte_flow_item_meta *spec = item->spec;
1455         const struct rte_flow_item_meta *mask = item->mask;
1456         struct rte_flow_item_meta nic_mask = {
1457                 .data = UINT32_MAX
1458         };
1459         int reg;
1460         int ret;
1461
1462         if (!spec)
1463                 return rte_flow_error_set(error, EINVAL,
1464                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1465                                           item->spec,
1466                                           "data cannot be empty");
1467         if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1468                 if (!mlx5_flow_ext_mreg_supported(dev))
1469                         return rte_flow_error_set(error, ENOTSUP,
1470                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1471                                           "extended metadata register"
1472                                           " isn't supported");
1473                 reg = flow_dv_get_metadata_reg(dev, attr, error);
1474                 if (reg < 0)
1475                         return reg;
1476                 if (reg == REG_B)
1477                         return rte_flow_error_set(error, ENOTSUP,
1478                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1479                                           "match on reg_b "
1480                                           "isn't supported");
1481                 if (reg != REG_A)
1482                         nic_mask.data = priv->sh->dv_meta_mask;
1483         } else if (attr->transfer) {
1484                 return rte_flow_error_set(error, ENOTSUP,
1485                                         RTE_FLOW_ERROR_TYPE_ITEM, item,
1486                                         "extended metadata feature "
1487                                         "should be enabled when "
1488                                         "meta item is requested "
1489                                         "with e-switch mode ");
1490         }
1491         if (!mask)
1492                 mask = &rte_flow_item_meta_mask;
1493         if (!mask->data)
1494                 return rte_flow_error_set(error, EINVAL,
1495                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1496                                         "mask cannot be zero");
1497
1498         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1499                                         (const uint8_t *)&nic_mask,
1500                                         sizeof(struct rte_flow_item_meta),
1501                                         error);
1502         return ret;
1503 }
1504
1505 /**
1506  * Validate TAG item.
1507  *
1508  * @param[in] dev
1509  *   Pointer to the rte_eth_dev structure.
1510  * @param[in] item
1511  *   Item specification.
1512  * @param[in] attr
1513  *   Attributes of flow that includes this item.
1514  * @param[out] error
1515  *   Pointer to error structure.
1516  *
1517  * @return
1518  *   0 on success, a negative errno value otherwise and rte_errno is set.
1519  */
1520 static int
1521 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
1522                           const struct rte_flow_item *item,
1523                           const struct rte_flow_attr *attr __rte_unused,
1524                           struct rte_flow_error *error)
1525 {
1526         const struct rte_flow_item_tag *spec = item->spec;
1527         const struct rte_flow_item_tag *mask = item->mask;
1528         const struct rte_flow_item_tag nic_mask = {
1529                 .data = RTE_BE32(UINT32_MAX),
1530                 .index = 0xff,
1531         };
1532         int ret;
1533
1534         if (!mlx5_flow_ext_mreg_supported(dev))
1535                 return rte_flow_error_set(error, ENOTSUP,
1536                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1537                                           "extensive metadata register"
1538                                           " isn't supported");
1539         if (!spec)
1540                 return rte_flow_error_set(error, EINVAL,
1541                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1542                                           item->spec,
1543                                           "data cannot be empty");
1544         if (!mask)
1545                 mask = &rte_flow_item_tag_mask;
1546         if (!mask->data)
1547                 return rte_flow_error_set(error, EINVAL,
1548                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1549                                         "mask cannot be zero");
1550
1551         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1552                                         (const uint8_t *)&nic_mask,
1553                                         sizeof(struct rte_flow_item_tag),
1554                                         error);
1555         if (ret < 0)
1556                 return ret;
1557         if (mask->index != 0xff)
1558                 return rte_flow_error_set(error, EINVAL,
1559                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1560                                           "partial mask for tag index"
1561                                           " is not supported");
1562         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
1563         if (ret < 0)
1564                 return ret;
1565         MLX5_ASSERT(ret != REG_NON);
1566         return 0;
1567 }
1568
1569 /**
1570  * Validate vport item.
1571  *
1572  * @param[in] dev
1573  *   Pointer to the rte_eth_dev structure.
1574  * @param[in] item
1575  *   Item specification.
1576  * @param[in] attr
1577  *   Attributes of flow that includes this item.
1578  * @param[in] item_flags
1579  *   Bit-fields that holds the items detected until now.
1580  * @param[out] error
1581  *   Pointer to error structure.
1582  *
1583  * @return
1584  *   0 on success, a negative errno value otherwise and rte_errno is set.
1585  */
1586 static int
1587 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
1588                               const struct rte_flow_item *item,
1589                               const struct rte_flow_attr *attr,
1590                               uint64_t item_flags,
1591                               struct rte_flow_error *error)
1592 {
1593         const struct rte_flow_item_port_id *spec = item->spec;
1594         const struct rte_flow_item_port_id *mask = item->mask;
1595         const struct rte_flow_item_port_id switch_mask = {
1596                         .id = 0xffffffff,
1597         };
1598         struct mlx5_priv *esw_priv;
1599         struct mlx5_priv *dev_priv;
1600         int ret;
1601
1602         if (!attr->transfer)
1603                 return rte_flow_error_set(error, EINVAL,
1604                                           RTE_FLOW_ERROR_TYPE_ITEM,
1605                                           NULL,
1606                                           "match on port id is valid only"
1607                                           " when transfer flag is enabled");
1608         if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
1609                 return rte_flow_error_set(error, ENOTSUP,
1610                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1611                                           "multiple source ports are not"
1612                                           " supported");
1613         if (!mask)
1614                 mask = &switch_mask;
1615         if (mask->id != 0xffffffff)
1616                 return rte_flow_error_set(error, ENOTSUP,
1617                                            RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1618                                            mask,
1619                                            "no support for partial mask on"
1620                                            " \"id\" field");
1621         ret = mlx5_flow_item_acceptable
1622                                 (item, (const uint8_t *)mask,
1623                                  (const uint8_t *)&rte_flow_item_port_id_mask,
1624                                  sizeof(struct rte_flow_item_port_id),
1625                                  error);
1626         if (ret)
1627                 return ret;
1628         if (!spec)
1629                 return 0;
1630         esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
1631         if (!esw_priv)
1632                 return rte_flow_error_set(error, rte_errno,
1633                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1634                                           "failed to obtain E-Switch info for"
1635                                           " port");
1636         dev_priv = mlx5_dev_to_eswitch_info(dev);
1637         if (!dev_priv)
1638                 return rte_flow_error_set(error, rte_errno,
1639                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1640                                           NULL,
1641                                           "failed to obtain E-Switch info");
1642         if (esw_priv->domain_id != dev_priv->domain_id)
1643                 return rte_flow_error_set(error, EINVAL,
1644                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1645                                           "cannot match on a port from a"
1646                                           " different E-Switch");
1647         return 0;
1648 }
1649
1650 /**
1651  * Validate VLAN item.
1652  *
1653  * @param[in] item
1654  *   Item specification.
1655  * @param[in] item_flags
1656  *   Bit-fields that holds the items detected until now.
1657  * @param[in] dev
1658  *   Ethernet device flow is being created on.
1659  * @param[out] error
1660  *   Pointer to error structure.
1661  *
1662  * @return
1663  *   0 on success, a negative errno value otherwise and rte_errno is set.
1664  */
1665 static int
1666 flow_dv_validate_item_vlan(const struct rte_flow_item *item,
1667                            uint64_t item_flags,
1668                            struct rte_eth_dev *dev,
1669                            struct rte_flow_error *error)
1670 {
1671         const struct rte_flow_item_vlan *mask = item->mask;
1672         const struct rte_flow_item_vlan nic_mask = {
1673                 .tci = RTE_BE16(UINT16_MAX),
1674                 .inner_type = RTE_BE16(UINT16_MAX),
1675         };
1676         const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
1677         int ret;
1678         const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 |
1679                                         MLX5_FLOW_LAYER_INNER_L4) :
1680                                        (MLX5_FLOW_LAYER_OUTER_L3 |
1681                                         MLX5_FLOW_LAYER_OUTER_L4);
1682         const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
1683                                         MLX5_FLOW_LAYER_OUTER_VLAN;
1684
1685         if (item_flags & vlanm)
1686                 return rte_flow_error_set(error, EINVAL,
1687                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1688                                           "multiple VLAN layers not supported");
1689         else if ((item_flags & l34m) != 0)
1690                 return rte_flow_error_set(error, EINVAL,
1691                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1692                                           "VLAN cannot follow L3/L4 layer");
1693         if (!mask)
1694                 mask = &rte_flow_item_vlan_mask;
1695         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1696                                         (const uint8_t *)&nic_mask,
1697                                         sizeof(struct rte_flow_item_vlan),
1698                                         error);
1699         if (ret)
1700                 return ret;
1701         if (!tunnel && mask->tci != RTE_BE16(0x0fff)) {
1702                 struct mlx5_priv *priv = dev->data->dev_private;
1703
1704                 if (priv->vmwa_context) {
1705                         /*
1706                          * Non-NULL context means we have a virtual machine
1707                          * and SR-IOV enabled, we have to create VLAN interface
1708                          * to make hypervisor to setup E-Switch vport
1709                          * context correctly. We avoid creating the multiple
1710                          * VLAN interfaces, so we cannot support VLAN tag mask.
1711                          */
1712                         return rte_flow_error_set(error, EINVAL,
1713                                                   RTE_FLOW_ERROR_TYPE_ITEM,
1714                                                   item,
1715                                                   "VLAN tag mask is not"
1716                                                   " supported in virtual"
1717                                                   " environment");
1718                 }
1719         }
1720         return 0;
1721 }
1722
1723 /*
1724  * GTP flags are contained in 1 byte of the format:
1725  * -------------------------------------------
1726  * | bit   | 0 - 2   | 3  | 4   | 5 | 6 | 7  |
1727  * |-----------------------------------------|
1728  * | value | Version | PT | Res | E | S | PN |
1729  * -------------------------------------------
1730  *
1731  * Matching is supported only for GTP flags E, S, PN.
1732  */
1733 #define MLX5_GTP_FLAGS_MASK     0x07
1734
1735 /**
1736  * Validate GTP item.
1737  *
1738  * @param[in] dev
1739  *   Pointer to the rte_eth_dev structure.
1740  * @param[in] item
1741  *   Item specification.
1742  * @param[in] item_flags
1743  *   Bit-fields that holds the items detected until now.
1744  * @param[out] error
1745  *   Pointer to error structure.
1746  *
1747  * @return
1748  *   0 on success, a negative errno value otherwise and rte_errno is set.
1749  */
1750 static int
1751 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
1752                           const struct rte_flow_item *item,
1753                           uint64_t item_flags,
1754                           struct rte_flow_error *error)
1755 {
1756         struct mlx5_priv *priv = dev->data->dev_private;
1757         const struct rte_flow_item_gtp *spec = item->spec;
1758         const struct rte_flow_item_gtp *mask = item->mask;
1759         const struct rte_flow_item_gtp nic_mask = {
1760                 .v_pt_rsv_flags = MLX5_GTP_FLAGS_MASK,
1761                 .msg_type = 0xff,
1762                 .teid = RTE_BE32(0xffffffff),
1763         };
1764
1765         if (!priv->config.hca_attr.tunnel_stateless_gtp)
1766                 return rte_flow_error_set(error, ENOTSUP,
1767                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1768                                           "GTP support is not enabled");
1769         if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
1770                 return rte_flow_error_set(error, ENOTSUP,
1771                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1772                                           "multiple tunnel layers not"
1773                                           " supported");
1774         if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
1775                 return rte_flow_error_set(error, EINVAL,
1776                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1777                                           "no outer UDP layer found");
1778         if (!mask)
1779                 mask = &rte_flow_item_gtp_mask;
1780         if (spec && spec->v_pt_rsv_flags & ~MLX5_GTP_FLAGS_MASK)
1781                 return rte_flow_error_set(error, ENOTSUP,
1782                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1783                                           "Match is supported for GTP"
1784                                           " flags only");
1785         return mlx5_flow_item_acceptable
1786                 (item, (const uint8_t *)mask,
1787                  (const uint8_t *)&nic_mask,
1788                  sizeof(struct rte_flow_item_gtp),
1789                  error);
1790 }
1791
1792 /**
1793  * Validate the pop VLAN action.
1794  *
1795  * @param[in] dev
1796  *   Pointer to the rte_eth_dev structure.
1797  * @param[in] action_flags
1798  *   Holds the actions detected until now.
1799  * @param[in] action
1800  *   Pointer to the pop vlan action.
1801  * @param[in] item_flags
1802  *   The items found in this flow rule.
1803  * @param[in] attr
1804  *   Pointer to flow attributes.
1805  * @param[out] error
1806  *   Pointer to error structure.
1807  *
1808  * @return
1809  *   0 on success, a negative errno value otherwise and rte_errno is set.
1810  */
1811 static int
1812 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
1813                                  uint64_t action_flags,
1814                                  const struct rte_flow_action *action,
1815                                  uint64_t item_flags,
1816                                  const struct rte_flow_attr *attr,
1817                                  struct rte_flow_error *error)
1818 {
1819         const struct mlx5_priv *priv = dev->data->dev_private;
1820
1821         (void)action;
1822         (void)attr;
1823         if (!priv->sh->pop_vlan_action)
1824                 return rte_flow_error_set(error, ENOTSUP,
1825                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1826                                           NULL,
1827                                           "pop vlan action is not supported");
1828         if (attr->egress)
1829                 return rte_flow_error_set(error, ENOTSUP,
1830                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1831                                           NULL,
1832                                           "pop vlan action not supported for "
1833                                           "egress");
1834         if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
1835                 return rte_flow_error_set(error, ENOTSUP,
1836                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1837                                           "no support for multiple VLAN "
1838                                           "actions");
1839         /* Pop VLAN with preceding Decap requires inner header with VLAN. */
1840         if ((action_flags & MLX5_FLOW_ACTION_DECAP) &&
1841             !(item_flags & MLX5_FLOW_LAYER_INNER_VLAN))
1842                 return rte_flow_error_set(error, ENOTSUP,
1843                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1844                                           NULL,
1845                                           "cannot pop vlan after decap without "
1846                                           "match on inner vlan in the flow");
1847         /* Pop VLAN without preceding Decap requires outer header with VLAN. */
1848         if (!(action_flags & MLX5_FLOW_ACTION_DECAP) &&
1849             !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1850                 return rte_flow_error_set(error, ENOTSUP,
1851                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1852                                           NULL,
1853                                           "cannot pop vlan without a "
1854                                           "match on (outer) vlan in the flow");
1855         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1856                 return rte_flow_error_set(error, EINVAL,
1857                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1858                                           "wrong action order, port_id should "
1859                                           "be after pop VLAN action");
1860         if (!attr->transfer && priv->representor)
1861                 return rte_flow_error_set(error, ENOTSUP,
1862                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1863                                           "pop vlan action for VF representor "
1864                                           "not supported on NIC table");
1865         return 0;
1866 }
1867
1868 /**
1869  * Get VLAN default info from vlan match info.
1870  *
1871  * @param[in] items
1872  *   the list of item specifications.
1873  * @param[out] vlan
1874  *   pointer VLAN info to fill to.
1875  *
1876  * @return
1877  *   0 on success, a negative errno value otherwise and rte_errno is set.
1878  */
1879 static void
1880 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
1881                                   struct rte_vlan_hdr *vlan)
1882 {
1883         const struct rte_flow_item_vlan nic_mask = {
1884                 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
1885                                 MLX5DV_FLOW_VLAN_VID_MASK),
1886                 .inner_type = RTE_BE16(0xffff),
1887         };
1888
1889         if (items == NULL)
1890                 return;
1891         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
1892                 int type = items->type;
1893
1894                 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
1895                     type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
1896                         break;
1897         }
1898         if (items->type != RTE_FLOW_ITEM_TYPE_END) {
1899                 const struct rte_flow_item_vlan *vlan_m = items->mask;
1900                 const struct rte_flow_item_vlan *vlan_v = items->spec;
1901
1902                 /* If VLAN item in pattern doesn't contain data, return here. */
1903                 if (!vlan_v)
1904                         return;
1905                 if (!vlan_m)
1906                         vlan_m = &nic_mask;
1907                 /* Only full match values are accepted */
1908                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
1909                      MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
1910                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
1911                         vlan->vlan_tci |=
1912                                 rte_be_to_cpu_16(vlan_v->tci &
1913                                                  MLX5DV_FLOW_VLAN_PCP_MASK_BE);
1914                 }
1915                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
1916                      MLX5DV_FLOW_VLAN_VID_MASK_BE) {
1917                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
1918                         vlan->vlan_tci |=
1919                                 rte_be_to_cpu_16(vlan_v->tci &
1920                                                  MLX5DV_FLOW_VLAN_VID_MASK_BE);
1921                 }
1922                 if (vlan_m->inner_type == nic_mask.inner_type)
1923                         vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
1924                                                            vlan_m->inner_type);
1925         }
1926 }
1927
1928 /**
1929  * Validate the push VLAN action.
1930  *
1931  * @param[in] dev
1932  *   Pointer to the rte_eth_dev structure.
1933  * @param[in] action_flags
1934  *   Holds the actions detected until now.
1935  * @param[in] item_flags
1936  *   The items found in this flow rule.
1937  * @param[in] action
1938  *   Pointer to the action structure.
1939  * @param[in] attr
1940  *   Pointer to flow attributes
1941  * @param[out] error
1942  *   Pointer to error structure.
1943  *
1944  * @return
1945  *   0 on success, a negative errno value otherwise and rte_errno is set.
1946  */
1947 static int
1948 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
1949                                   uint64_t action_flags,
1950                                   const struct rte_flow_item_vlan *vlan_m,
1951                                   const struct rte_flow_action *action,
1952                                   const struct rte_flow_attr *attr,
1953                                   struct rte_flow_error *error)
1954 {
1955         const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
1956         const struct mlx5_priv *priv = dev->data->dev_private;
1957
1958         if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
1959             push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
1960                 return rte_flow_error_set(error, EINVAL,
1961                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1962                                           "invalid vlan ethertype");
1963         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1964                 return rte_flow_error_set(error, EINVAL,
1965                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1966                                           "wrong action order, port_id should "
1967                                           "be after push VLAN");
1968         if (!attr->transfer && priv->representor)
1969                 return rte_flow_error_set(error, ENOTSUP,
1970                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1971                                           "push vlan action for VF representor "
1972                                           "not supported on NIC table");
1973         if (vlan_m &&
1974             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
1975             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
1976                 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
1977             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
1978             !(mlx5_flow_find_action
1979                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
1980                 return rte_flow_error_set(error, EINVAL,
1981                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1982                                           "not full match mask on VLAN PCP and "
1983                                           "there is no of_set_vlan_pcp action, "
1984                                           "push VLAN action cannot figure out "
1985                                           "PCP value");
1986         if (vlan_m &&
1987             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
1988             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
1989                 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
1990             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
1991             !(mlx5_flow_find_action
1992                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
1993                 return rte_flow_error_set(error, EINVAL,
1994                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1995                                           "not full match mask on VLAN VID and "
1996                                           "there is no of_set_vlan_vid action, "
1997                                           "push VLAN action cannot figure out "
1998                                           "VID value");
1999         (void)attr;
2000         return 0;
2001 }
2002
2003 /**
2004  * Validate the set VLAN PCP.
2005  *
2006  * @param[in] action_flags
2007  *   Holds the actions detected until now.
2008  * @param[in] actions
2009  *   Pointer to the list of actions remaining in the flow rule.
2010  * @param[out] error
2011  *   Pointer to error structure.
2012  *
2013  * @return
2014  *   0 on success, a negative errno value otherwise and rte_errno is set.
2015  */
2016 static int
2017 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
2018                                      const struct rte_flow_action actions[],
2019                                      struct rte_flow_error *error)
2020 {
2021         const struct rte_flow_action *action = actions;
2022         const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
2023
2024         if (conf->vlan_pcp > 7)
2025                 return rte_flow_error_set(error, EINVAL,
2026                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2027                                           "VLAN PCP value is too big");
2028         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
2029                 return rte_flow_error_set(error, ENOTSUP,
2030                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2031                                           "set VLAN PCP action must follow "
2032                                           "the push VLAN action");
2033         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
2034                 return rte_flow_error_set(error, ENOTSUP,
2035                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2036                                           "Multiple VLAN PCP modification are "
2037                                           "not supported");
2038         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2039                 return rte_flow_error_set(error, EINVAL,
2040                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2041                                           "wrong action order, port_id should "
2042                                           "be after set VLAN PCP");
2043         return 0;
2044 }
2045
2046 /**
2047  * Validate the set VLAN VID.
2048  *
2049  * @param[in] item_flags
2050  *   Holds the items detected in this rule.
2051  * @param[in] action_flags
2052  *   Holds the actions detected until now.
2053  * @param[in] actions
2054  *   Pointer to the list of actions remaining in the flow rule.
2055  * @param[out] error
2056  *   Pointer to error structure.
2057  *
2058  * @return
2059  *   0 on success, a negative errno value otherwise and rte_errno is set.
2060  */
2061 static int
2062 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
2063                                      uint64_t action_flags,
2064                                      const struct rte_flow_action actions[],
2065                                      struct rte_flow_error *error)
2066 {
2067         const struct rte_flow_action *action = actions;
2068         const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
2069
2070         if (rte_be_to_cpu_16(conf->vlan_vid) > 0xFFE)
2071                 return rte_flow_error_set(error, EINVAL,
2072                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2073                                           "VLAN VID value is too big");
2074         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
2075             !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2076                 return rte_flow_error_set(error, ENOTSUP,
2077                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2078                                           "set VLAN VID action must follow push"
2079                                           " VLAN action or match on VLAN item");
2080         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
2081                 return rte_flow_error_set(error, ENOTSUP,
2082                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2083                                           "Multiple VLAN VID modifications are "
2084                                           "not supported");
2085         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2086                 return rte_flow_error_set(error, EINVAL,
2087                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2088                                           "wrong action order, port_id should "
2089                                           "be after set VLAN VID");
2090         return 0;
2091 }
2092
2093 /*
2094  * Validate the FLAG action.
2095  *
2096  * @param[in] dev
2097  *   Pointer to the rte_eth_dev structure.
2098  * @param[in] action_flags
2099  *   Holds the actions detected until now.
2100  * @param[in] attr
2101  *   Pointer to flow attributes
2102  * @param[out] error
2103  *   Pointer to error structure.
2104  *
2105  * @return
2106  *   0 on success, a negative errno value otherwise and rte_errno is set.
2107  */
2108 static int
2109 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
2110                              uint64_t action_flags,
2111                              const struct rte_flow_attr *attr,
2112                              struct rte_flow_error *error)
2113 {
2114         struct mlx5_priv *priv = dev->data->dev_private;
2115         struct mlx5_dev_config *config = &priv->config;
2116         int ret;
2117
2118         /* Fall back if no extended metadata register support. */
2119         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2120                 return mlx5_flow_validate_action_flag(action_flags, attr,
2121                                                       error);
2122         /* Extensive metadata mode requires registers. */
2123         if (!mlx5_flow_ext_mreg_supported(dev))
2124                 return rte_flow_error_set(error, ENOTSUP,
2125                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2126                                           "no metadata registers "
2127                                           "to support flag action");
2128         if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
2129                 return rte_flow_error_set(error, ENOTSUP,
2130                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2131                                           "extended metadata register"
2132                                           " isn't available");
2133         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2134         if (ret < 0)
2135                 return ret;
2136         MLX5_ASSERT(ret > 0);
2137         if (action_flags & MLX5_FLOW_ACTION_MARK)
2138                 return rte_flow_error_set(error, EINVAL,
2139                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2140                                           "can't mark and flag in same flow");
2141         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2142                 return rte_flow_error_set(error, EINVAL,
2143                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2144                                           "can't have 2 flag"
2145                                           " actions in same flow");
2146         return 0;
2147 }
2148
2149 /**
2150  * Validate MARK action.
2151  *
2152  * @param[in] dev
2153  *   Pointer to the rte_eth_dev structure.
2154  * @param[in] action
2155  *   Pointer to action.
2156  * @param[in] action_flags
2157  *   Holds the actions detected until now.
2158  * @param[in] attr
2159  *   Pointer to flow attributes
2160  * @param[out] error
2161  *   Pointer to error structure.
2162  *
2163  * @return
2164  *   0 on success, a negative errno value otherwise and rte_errno is set.
2165  */
2166 static int
2167 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
2168                              const struct rte_flow_action *action,
2169                              uint64_t action_flags,
2170                              const struct rte_flow_attr *attr,
2171                              struct rte_flow_error *error)
2172 {
2173         struct mlx5_priv *priv = dev->data->dev_private;
2174         struct mlx5_dev_config *config = &priv->config;
2175         const struct rte_flow_action_mark *mark = action->conf;
2176         int ret;
2177
2178         /* Fall back if no extended metadata register support. */
2179         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2180                 return mlx5_flow_validate_action_mark(action, action_flags,
2181                                                       attr, error);
2182         /* Extensive metadata mode requires registers. */
2183         if (!mlx5_flow_ext_mreg_supported(dev))
2184                 return rte_flow_error_set(error, ENOTSUP,
2185                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2186                                           "no metadata registers "
2187                                           "to support mark action");
2188         if (!priv->sh->dv_mark_mask)
2189                 return rte_flow_error_set(error, ENOTSUP,
2190                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2191                                           "extended metadata register"
2192                                           " isn't available");
2193         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2194         if (ret < 0)
2195                 return ret;
2196         MLX5_ASSERT(ret > 0);
2197         if (!mark)
2198                 return rte_flow_error_set(error, EINVAL,
2199                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2200                                           "configuration cannot be null");
2201         if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
2202                 return rte_flow_error_set(error, EINVAL,
2203                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2204                                           &mark->id,
2205                                           "mark id exceeds the limit");
2206         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2207                 return rte_flow_error_set(error, EINVAL,
2208                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2209                                           "can't flag and mark in same flow");
2210         if (action_flags & MLX5_FLOW_ACTION_MARK)
2211                 return rte_flow_error_set(error, EINVAL,
2212                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2213                                           "can't have 2 mark actions in same"
2214                                           " flow");
2215         return 0;
2216 }
2217
2218 /**
2219  * Validate SET_META action.
2220  *
2221  * @param[in] dev
2222  *   Pointer to the rte_eth_dev structure.
2223  * @param[in] action
2224  *   Pointer to the action structure.
2225  * @param[in] action_flags
2226  *   Holds the actions detected until now.
2227  * @param[in] attr
2228  *   Pointer to flow attributes
2229  * @param[out] error
2230  *   Pointer to error structure.
2231  *
2232  * @return
2233  *   0 on success, a negative errno value otherwise and rte_errno is set.
2234  */
2235 static int
2236 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
2237                                  const struct rte_flow_action *action,
2238                                  uint64_t action_flags __rte_unused,
2239                                  const struct rte_flow_attr *attr,
2240                                  struct rte_flow_error *error)
2241 {
2242         const struct rte_flow_action_set_meta *conf;
2243         uint32_t nic_mask = UINT32_MAX;
2244         int reg;
2245
2246         if (!mlx5_flow_ext_mreg_supported(dev))
2247                 return rte_flow_error_set(error, ENOTSUP,
2248                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2249                                           "extended metadata register"
2250                                           " isn't supported");
2251         reg = flow_dv_get_metadata_reg(dev, attr, error);
2252         if (reg < 0)
2253                 return reg;
2254         if (reg != REG_A && reg != REG_B) {
2255                 struct mlx5_priv *priv = dev->data->dev_private;
2256
2257                 nic_mask = priv->sh->dv_meta_mask;
2258         }
2259         if (!(action->conf))
2260                 return rte_flow_error_set(error, EINVAL,
2261                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2262                                           "configuration cannot be null");
2263         conf = (const struct rte_flow_action_set_meta *)action->conf;
2264         if (!conf->mask)
2265                 return rte_flow_error_set(error, EINVAL,
2266                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2267                                           "zero mask doesn't have any effect");
2268         if (conf->mask & ~nic_mask)
2269                 return rte_flow_error_set(error, EINVAL,
2270                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2271                                           "meta data must be within reg C0");
2272         return 0;
2273 }
2274
2275 /**
2276  * Validate SET_TAG action.
2277  *
2278  * @param[in] dev
2279  *   Pointer to the rte_eth_dev structure.
2280  * @param[in] action
2281  *   Pointer to the action structure.
2282  * @param[in] action_flags
2283  *   Holds the actions detected until now.
2284  * @param[in] attr
2285  *   Pointer to flow attributes
2286  * @param[out] error
2287  *   Pointer to error structure.
2288  *
2289  * @return
2290  *   0 on success, a negative errno value otherwise and rte_errno is set.
2291  */
2292 static int
2293 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
2294                                 const struct rte_flow_action *action,
2295                                 uint64_t action_flags,
2296                                 const struct rte_flow_attr *attr,
2297                                 struct rte_flow_error *error)
2298 {
2299         const struct rte_flow_action_set_tag *conf;
2300         const uint64_t terminal_action_flags =
2301                 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
2302                 MLX5_FLOW_ACTION_RSS;
2303         int ret;
2304
2305         if (!mlx5_flow_ext_mreg_supported(dev))
2306                 return rte_flow_error_set(error, ENOTSUP,
2307                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2308                                           "extensive metadata register"
2309                                           " isn't supported");
2310         if (!(action->conf))
2311                 return rte_flow_error_set(error, EINVAL,
2312                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2313                                           "configuration cannot be null");
2314         conf = (const struct rte_flow_action_set_tag *)action->conf;
2315         if (!conf->mask)
2316                 return rte_flow_error_set(error, EINVAL,
2317                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2318                                           "zero mask doesn't have any effect");
2319         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
2320         if (ret < 0)
2321                 return ret;
2322         if (!attr->transfer && attr->ingress &&
2323             (action_flags & terminal_action_flags))
2324                 return rte_flow_error_set(error, EINVAL,
2325                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2326                                           "set_tag has no effect"
2327                                           " with terminal actions");
2328         return 0;
2329 }
2330
2331 /**
2332  * Validate count action.
2333  *
2334  * @param[in] dev
2335  *   Pointer to rte_eth_dev structure.
2336  * @param[out] error
2337  *   Pointer to error structure.
2338  *
2339  * @return
2340  *   0 on success, a negative errno value otherwise and rte_errno is set.
2341  */
2342 static int
2343 flow_dv_validate_action_count(struct rte_eth_dev *dev,
2344                               struct rte_flow_error *error)
2345 {
2346         struct mlx5_priv *priv = dev->data->dev_private;
2347
2348         if (!priv->config.devx)
2349                 goto notsup_err;
2350 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
2351         return 0;
2352 #endif
2353 notsup_err:
2354         return rte_flow_error_set
2355                       (error, ENOTSUP,
2356                        RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2357                        NULL,
2358                        "count action not supported");
2359 }
2360
2361 /**
2362  * Validate the L2 encap action.
2363  *
2364  * @param[in] dev
2365  *   Pointer to the rte_eth_dev structure.
2366  * @param[in] action_flags
2367  *   Holds the actions detected until now.
2368  * @param[in] action
2369  *   Pointer to the action structure.
2370  * @param[in] attr
2371  *   Pointer to flow attributes.
2372  * @param[out] error
2373  *   Pointer to error structure.
2374  *
2375  * @return
2376  *   0 on success, a negative errno value otherwise and rte_errno is set.
2377  */
2378 static int
2379 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
2380                                  uint64_t action_flags,
2381                                  const struct rte_flow_action *action,
2382                                  const struct rte_flow_attr *attr,
2383                                  struct rte_flow_error *error)
2384 {
2385         const struct mlx5_priv *priv = dev->data->dev_private;
2386
2387         if (!(action->conf))
2388                 return rte_flow_error_set(error, EINVAL,
2389                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2390                                           "configuration cannot be null");
2391         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
2392                 return rte_flow_error_set(error, EINVAL,
2393                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2394                                           "can only have a single encap action "
2395                                           "in a flow");
2396         if (!attr->transfer && priv->representor)
2397                 return rte_flow_error_set(error, ENOTSUP,
2398                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2399                                           "encap action for VF representor "
2400                                           "not supported on NIC table");
2401         return 0;
2402 }
2403
2404 /**
2405  * Validate a decap action.
2406  *
2407  * @param[in] dev
2408  *   Pointer to the rte_eth_dev structure.
2409  * @param[in] action_flags
2410  *   Holds the actions detected until now.
2411  * @param[in] attr
2412  *   Pointer to flow attributes
2413  * @param[out] error
2414  *   Pointer to error structure.
2415  *
2416  * @return
2417  *   0 on success, a negative errno value otherwise and rte_errno is set.
2418  */
2419 static int
2420 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
2421                               uint64_t action_flags,
2422                               const struct rte_flow_attr *attr,
2423                               struct rte_flow_error *error)
2424 {
2425         const struct mlx5_priv *priv = dev->data->dev_private;
2426
2427         if (priv->config.hca_attr.scatter_fcs_w_decap_disable &&
2428             !priv->config.decap_en)
2429                 return rte_flow_error_set(error, ENOTSUP,
2430                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2431                                           "decap is not enabled");
2432         if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
2433                 return rte_flow_error_set(error, ENOTSUP,
2434                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2435                                           action_flags &
2436                                           MLX5_FLOW_ACTION_DECAP ? "can only "
2437                                           "have a single decap action" : "decap "
2438                                           "after encap is not supported");
2439         if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
2440                 return rte_flow_error_set(error, EINVAL,
2441                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2442                                           "can't have decap action after"
2443                                           " modify action");
2444         if (attr->egress)
2445                 return rte_flow_error_set(error, ENOTSUP,
2446                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2447                                           NULL,
2448                                           "decap action not supported for "
2449                                           "egress");
2450         if (!attr->transfer && priv->representor)
2451                 return rte_flow_error_set(error, ENOTSUP,
2452                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2453                                           "decap action for VF representor "
2454                                           "not supported on NIC table");
2455         return 0;
2456 }
2457
2458 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
2459
2460 /**
2461  * Validate the raw encap and decap actions.
2462  *
2463  * @param[in] dev
2464  *   Pointer to the rte_eth_dev structure.
2465  * @param[in] decap
2466  *   Pointer to the decap action.
2467  * @param[in] encap
2468  *   Pointer to the encap action.
2469  * @param[in] attr
2470  *   Pointer to flow attributes
2471  * @param[in/out] action_flags
2472  *   Holds the actions detected until now.
2473  * @param[out] actions_n
2474  *   pointer to the number of actions counter.
2475  * @param[out] error
2476  *   Pointer to error structure.
2477  *
2478  * @return
2479  *   0 on success, a negative errno value otherwise and rte_errno is set.
2480  */
2481 static int
2482 flow_dv_validate_action_raw_encap_decap
2483         (struct rte_eth_dev *dev,
2484          const struct rte_flow_action_raw_decap *decap,
2485          const struct rte_flow_action_raw_encap *encap,
2486          const struct rte_flow_attr *attr, uint64_t *action_flags,
2487          int *actions_n, struct rte_flow_error *error)
2488 {
2489         const struct mlx5_priv *priv = dev->data->dev_private;
2490         int ret;
2491
2492         if (encap && (!encap->size || !encap->data))
2493                 return rte_flow_error_set(error, EINVAL,
2494                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2495                                           "raw encap data cannot be empty");
2496         if (decap && encap) {
2497                 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
2498                     encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
2499                         /* L3 encap. */
2500                         decap = NULL;
2501                 else if (encap->size <=
2502                            MLX5_ENCAPSULATION_DECISION_SIZE &&
2503                            decap->size >
2504                            MLX5_ENCAPSULATION_DECISION_SIZE)
2505                         /* L3 decap. */
2506                         encap = NULL;
2507                 else if (encap->size >
2508                            MLX5_ENCAPSULATION_DECISION_SIZE &&
2509                            decap->size >
2510                            MLX5_ENCAPSULATION_DECISION_SIZE)
2511                         /* 2 L2 actions: encap and decap. */
2512                         ;
2513                 else
2514                         return rte_flow_error_set(error,
2515                                 ENOTSUP,
2516                                 RTE_FLOW_ERROR_TYPE_ACTION,
2517                                 NULL, "unsupported too small "
2518                                 "raw decap and too small raw "
2519                                 "encap combination");
2520         }
2521         if (decap) {
2522                 ret = flow_dv_validate_action_decap(dev, *action_flags, attr,
2523                                                     error);
2524                 if (ret < 0)
2525                         return ret;
2526                 *action_flags |= MLX5_FLOW_ACTION_DECAP;
2527                 ++(*actions_n);
2528         }
2529         if (encap) {
2530                 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
2531                         return rte_flow_error_set(error, ENOTSUP,
2532                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2533                                                   NULL,
2534                                                   "small raw encap size");
2535                 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
2536                         return rte_flow_error_set(error, EINVAL,
2537                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2538                                                   NULL,
2539                                                   "more than one encap action");
2540                 if (!attr->transfer && priv->representor)
2541                         return rte_flow_error_set
2542                                         (error, ENOTSUP,
2543                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2544                                          "encap action for VF representor "
2545                                          "not supported on NIC table");
2546                 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
2547                 ++(*actions_n);
2548         }
2549         return 0;
2550 }
2551
2552 /**
2553  * Match encap_decap resource.
2554  *
2555  * @param entry
2556  *   Pointer to exist resource entry object.
2557  * @param ctx
2558  *   Pointer to new encap_decap resource.
2559  *
2560  * @return
2561  *   0 on matching, -1 otherwise.
2562  */
2563 static int
2564 flow_dv_encap_decap_resource_match(struct mlx5_hlist_entry *entry, void *ctx)
2565 {
2566         struct mlx5_flow_dv_encap_decap_resource *resource;
2567         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2568
2569         resource = (struct mlx5_flow_dv_encap_decap_resource *)ctx;
2570         cache_resource = container_of(entry,
2571                                       struct mlx5_flow_dv_encap_decap_resource,
2572                                       entry);
2573         if (resource->entry.key == cache_resource->entry.key &&
2574             resource->reformat_type == cache_resource->reformat_type &&
2575             resource->ft_type == cache_resource->ft_type &&
2576             resource->flags == cache_resource->flags &&
2577             resource->size == cache_resource->size &&
2578             !memcmp((const void *)resource->buf,
2579                     (const void *)cache_resource->buf,
2580                     resource->size))
2581                 return 0;
2582         return -1;
2583 }
2584
2585 /**
2586  * Find existing encap/decap resource or create and register a new one.
2587  *
2588  * @param[in, out] dev
2589  *   Pointer to rte_eth_dev structure.
2590  * @param[in, out] resource
2591  *   Pointer to encap/decap resource.
2592  * @parm[in, out] dev_flow
2593  *   Pointer to the dev_flow.
2594  * @param[out] error
2595  *   pointer to error structure.
2596  *
2597  * @return
2598  *   0 on success otherwise -errno and errno is set.
2599  */
2600 static int
2601 flow_dv_encap_decap_resource_register
2602                         (struct rte_eth_dev *dev,
2603                          struct mlx5_flow_dv_encap_decap_resource *resource,
2604                          struct mlx5_flow *dev_flow,
2605                          struct rte_flow_error *error)
2606 {
2607         struct mlx5_priv *priv = dev->data->dev_private;
2608         struct mlx5_dev_ctx_shared *sh = priv->sh;
2609         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2610         struct mlx5dv_dr_domain *domain;
2611         struct mlx5_hlist_entry *entry;
2612         union mlx5_flow_encap_decap_key encap_decap_key = {
2613                 {
2614                         .ft_type = resource->ft_type,
2615                         .refmt_type = resource->reformat_type,
2616                         .buf_size = resource->size,
2617                         .table_level = !!dev_flow->dv.group,
2618                         .cksum = 0,
2619                 }
2620         };
2621         int ret;
2622
2623         resource->flags = dev_flow->dv.group ? 0 : 1;
2624         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2625                 domain = sh->fdb_domain;
2626         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2627                 domain = sh->rx_domain;
2628         else
2629                 domain = sh->tx_domain;
2630         encap_decap_key.cksum = __rte_raw_cksum(resource->buf,
2631                                                 resource->size, 0);
2632         resource->entry.key = encap_decap_key.v64;
2633         /* Lookup a matching resource from cache. */
2634         entry = mlx5_hlist_lookup_ex(sh->encaps_decaps, resource->entry.key,
2635                                      flow_dv_encap_decap_resource_match,
2636                                      (void *)resource);
2637         if (entry) {
2638                 cache_resource = container_of(entry,
2639                         struct mlx5_flow_dv_encap_decap_resource, entry);
2640                 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d++",
2641                         (void *)cache_resource,
2642                         rte_atomic32_read(&cache_resource->refcnt));
2643                 rte_atomic32_inc(&cache_resource->refcnt);
2644                 dev_flow->handle->dvh.rix_encap_decap = cache_resource->idx;
2645                 dev_flow->dv.encap_decap = cache_resource;
2646                 return 0;
2647         }
2648         /* Register new encap/decap resource. */
2649         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
2650                                        &dev_flow->handle->dvh.rix_encap_decap);
2651         if (!cache_resource)
2652                 return rte_flow_error_set(error, ENOMEM,
2653                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2654                                           "cannot allocate resource memory");
2655         *cache_resource = *resource;
2656         cache_resource->idx = dev_flow->handle->dvh.rix_encap_decap;
2657         ret = mlx5_flow_os_create_flow_action_packet_reformat
2658                                         (sh->ctx, domain, cache_resource,
2659                                          &cache_resource->action);
2660         if (ret) {
2661                 mlx5_free(cache_resource);
2662                 return rte_flow_error_set(error, ENOMEM,
2663                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2664                                           NULL, "cannot create action");
2665         }
2666         rte_atomic32_init(&cache_resource->refcnt);
2667         rte_atomic32_inc(&cache_resource->refcnt);
2668         if (mlx5_hlist_insert_ex(sh->encaps_decaps, &cache_resource->entry,
2669                                  flow_dv_encap_decap_resource_match,
2670                                  (void *)cache_resource)) {
2671                 claim_zero(mlx5_flow_os_destroy_flow_action
2672                                                 (cache_resource->action));
2673                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
2674                                 cache_resource->idx);
2675                 return rte_flow_error_set(error, EEXIST,
2676                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2677                                           NULL, "action exist");
2678         }
2679         dev_flow->dv.encap_decap = cache_resource;
2680         DRV_LOG(DEBUG, "new encap/decap resource %p: refcnt %d++",
2681                 (void *)cache_resource,
2682                 rte_atomic32_read(&cache_resource->refcnt));
2683         return 0;
2684 }
2685
2686 /**
2687  * Find existing table jump resource or create and register a new one.
2688  *
2689  * @param[in, out] dev
2690  *   Pointer to rte_eth_dev structure.
2691  * @param[in, out] tbl
2692  *   Pointer to flow table resource.
2693  * @parm[in, out] dev_flow
2694  *   Pointer to the dev_flow.
2695  * @param[out] error
2696  *   pointer to error structure.
2697  *
2698  * @return
2699  *   0 on success otherwise -errno and errno is set.
2700  */
2701 static int
2702 flow_dv_jump_tbl_resource_register
2703                         (struct rte_eth_dev *dev __rte_unused,
2704                          struct mlx5_flow_tbl_resource *tbl,
2705                          struct mlx5_flow *dev_flow,
2706                          struct rte_flow_error *error)
2707 {
2708         struct mlx5_flow_tbl_data_entry *tbl_data =
2709                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
2710         int cnt, ret;
2711
2712         MLX5_ASSERT(tbl);
2713         cnt = rte_atomic32_read(&tbl_data->jump.refcnt);
2714         if (!cnt) {
2715                 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
2716                                 (tbl->obj, &tbl_data->jump.action);
2717                 if (ret)
2718                         return rte_flow_error_set(error, ENOMEM,
2719                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2720                                         NULL, "cannot create jump action");
2721                 DRV_LOG(DEBUG, "new jump table resource %p: refcnt %d++",
2722                         (void *)&tbl_data->jump, cnt);
2723         } else {
2724                 /* old jump should not make the table ref++. */
2725                 flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
2726                 MLX5_ASSERT(tbl_data->jump.action);
2727                 DRV_LOG(DEBUG, "existed jump table resource %p: refcnt %d++",
2728                         (void *)&tbl_data->jump, cnt);
2729         }
2730         rte_atomic32_inc(&tbl_data->jump.refcnt);
2731         dev_flow->handle->rix_jump = tbl_data->idx;
2732         dev_flow->dv.jump = &tbl_data->jump;
2733         return 0;
2734 }
2735
2736 /**
2737  * Find existing default miss resource or create and register a new one.
2738  *
2739  * @param[in, out] dev
2740  *   Pointer to rte_eth_dev structure.
2741  * @param[out] error
2742  *   pointer to error structure.
2743  *
2744  * @return
2745  *   0 on success otherwise -errno and errno is set.
2746  */
2747 static int
2748 flow_dv_default_miss_resource_register(struct rte_eth_dev *dev,
2749                 struct rte_flow_error *error)
2750 {
2751         struct mlx5_priv *priv = dev->data->dev_private;
2752         struct mlx5_dev_ctx_shared *sh = priv->sh;
2753         struct mlx5_flow_default_miss_resource *cache_resource =
2754                         &sh->default_miss;
2755         int cnt = rte_atomic32_read(&cache_resource->refcnt);
2756
2757         if (!cnt) {
2758                 MLX5_ASSERT(cache_resource->action);
2759                 cache_resource->action =
2760                 mlx5_glue->dr_create_flow_action_default_miss();
2761                 if (!cache_resource->action)
2762                         return rte_flow_error_set(error, ENOMEM,
2763                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2764                                         "cannot create default miss action");
2765                 DRV_LOG(DEBUG, "new default miss resource %p: refcnt %d++",
2766                                 (void *)cache_resource->action, cnt);
2767         }
2768         rte_atomic32_inc(&cache_resource->refcnt);
2769         return 0;
2770 }
2771
2772 /**
2773  * Find existing table port ID resource or create and register a new one.
2774  *
2775  * @param[in, out] dev
2776  *   Pointer to rte_eth_dev structure.
2777  * @param[in, out] resource
2778  *   Pointer to port ID action resource.
2779  * @parm[in, out] dev_flow
2780  *   Pointer to the dev_flow.
2781  * @param[out] error
2782  *   pointer to error structure.
2783  *
2784  * @return
2785  *   0 on success otherwise -errno and errno is set.
2786  */
2787 static int
2788 flow_dv_port_id_action_resource_register
2789                         (struct rte_eth_dev *dev,
2790                          struct mlx5_flow_dv_port_id_action_resource *resource,
2791                          struct mlx5_flow *dev_flow,
2792                          struct rte_flow_error *error)
2793 {
2794         struct mlx5_priv *priv = dev->data->dev_private;
2795         struct mlx5_dev_ctx_shared *sh = priv->sh;
2796         struct mlx5_flow_dv_port_id_action_resource *cache_resource;
2797         uint32_t idx = 0;
2798         int ret;
2799
2800         /* Lookup a matching resource from cache. */
2801         ILIST_FOREACH(sh->ipool[MLX5_IPOOL_PORT_ID], sh->port_id_action_list,
2802                       idx, cache_resource, next) {
2803                 if (resource->port_id == cache_resource->port_id) {
2804                         DRV_LOG(DEBUG, "port id action resource resource %p: "
2805                                 "refcnt %d++",
2806                                 (void *)cache_resource,
2807                                 rte_atomic32_read(&cache_resource->refcnt));
2808                         rte_atomic32_inc(&cache_resource->refcnt);
2809                         dev_flow->handle->rix_port_id_action = idx;
2810                         dev_flow->dv.port_id_action = cache_resource;
2811                         return 0;
2812                 }
2813         }
2814         /* Register new port id action resource. */
2815         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID],
2816                                        &dev_flow->handle->rix_port_id_action);
2817         if (!cache_resource)
2818                 return rte_flow_error_set(error, ENOMEM,
2819                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2820                                           "cannot allocate resource memory");
2821         *cache_resource = *resource;
2822         ret = mlx5_flow_os_create_flow_action_dest_port
2823                                 (priv->sh->fdb_domain, resource->port_id,
2824                                  &cache_resource->action);
2825         if (ret) {
2826                 mlx5_free(cache_resource);
2827                 return rte_flow_error_set(error, ENOMEM,
2828                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2829                                           NULL, "cannot create action");
2830         }
2831         rte_atomic32_init(&cache_resource->refcnt);
2832         rte_atomic32_inc(&cache_resource->refcnt);
2833         ILIST_INSERT(sh->ipool[MLX5_IPOOL_PORT_ID], &sh->port_id_action_list,
2834                      dev_flow->handle->rix_port_id_action, cache_resource,
2835                      next);
2836         dev_flow->dv.port_id_action = cache_resource;
2837         DRV_LOG(DEBUG, "new port id action resource %p: refcnt %d++",
2838                 (void *)cache_resource,
2839                 rte_atomic32_read(&cache_resource->refcnt));
2840         return 0;
2841 }
2842
2843 /**
2844  * Find existing push vlan resource or create and register a new one.
2845  *
2846  * @param [in, out] dev
2847  *   Pointer to rte_eth_dev structure.
2848  * @param[in, out] resource
2849  *   Pointer to port ID action resource.
2850  * @parm[in, out] dev_flow
2851  *   Pointer to the dev_flow.
2852  * @param[out] error
2853  *   pointer to error structure.
2854  *
2855  * @return
2856  *   0 on success otherwise -errno and errno is set.
2857  */
2858 static int
2859 flow_dv_push_vlan_action_resource_register
2860                        (struct rte_eth_dev *dev,
2861                         struct mlx5_flow_dv_push_vlan_action_resource *resource,
2862                         struct mlx5_flow *dev_flow,
2863                         struct rte_flow_error *error)
2864 {
2865         struct mlx5_priv *priv = dev->data->dev_private;
2866         struct mlx5_dev_ctx_shared *sh = priv->sh;
2867         struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
2868         struct mlx5dv_dr_domain *domain;
2869         uint32_t idx = 0;
2870         int ret;
2871
2872         /* Lookup a matching resource from cache. */
2873         ILIST_FOREACH(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2874                       sh->push_vlan_action_list, idx, cache_resource, next) {
2875                 if (resource->vlan_tag == cache_resource->vlan_tag &&
2876                     resource->ft_type == cache_resource->ft_type) {
2877                         DRV_LOG(DEBUG, "push-VLAN action resource resource %p: "
2878                                 "refcnt %d++",
2879                                 (void *)cache_resource,
2880                                 rte_atomic32_read(&cache_resource->refcnt));
2881                         rte_atomic32_inc(&cache_resource->refcnt);
2882                         dev_flow->handle->dvh.rix_push_vlan = idx;
2883                         dev_flow->dv.push_vlan_res = cache_resource;
2884                         return 0;
2885                 }
2886         }
2887         /* Register new push_vlan action resource. */
2888         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2889                                        &dev_flow->handle->dvh.rix_push_vlan);
2890         if (!cache_resource)
2891                 return rte_flow_error_set(error, ENOMEM,
2892                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2893                                           "cannot allocate resource memory");
2894         *cache_resource = *resource;
2895         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2896                 domain = sh->fdb_domain;
2897         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2898                 domain = sh->rx_domain;
2899         else
2900                 domain = sh->tx_domain;
2901         ret = mlx5_flow_os_create_flow_action_push_vlan
2902                                         (domain, resource->vlan_tag,
2903                                          &cache_resource->action);
2904         if (ret) {
2905                 mlx5_free(cache_resource);
2906                 return rte_flow_error_set(error, ENOMEM,
2907                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2908                                           NULL, "cannot create action");
2909         }
2910         rte_atomic32_init(&cache_resource->refcnt);
2911         rte_atomic32_inc(&cache_resource->refcnt);
2912         ILIST_INSERT(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2913                      &sh->push_vlan_action_list,
2914                      dev_flow->handle->dvh.rix_push_vlan,
2915                      cache_resource, next);
2916         dev_flow->dv.push_vlan_res = cache_resource;
2917         DRV_LOG(DEBUG, "new push vlan action resource %p: refcnt %d++",
2918                 (void *)cache_resource,
2919                 rte_atomic32_read(&cache_resource->refcnt));
2920         return 0;
2921 }
2922 /**
2923  * Get the size of specific rte_flow_item_type hdr size
2924  *
2925  * @param[in] item_type
2926  *   Tested rte_flow_item_type.
2927  *
2928  * @return
2929  *   sizeof struct item_type, 0 if void or irrelevant.
2930  */
2931 static size_t
2932 flow_dv_get_item_hdr_len(const enum rte_flow_item_type item_type)
2933 {
2934         size_t retval;
2935
2936         switch (item_type) {
2937         case RTE_FLOW_ITEM_TYPE_ETH:
2938                 retval = sizeof(struct rte_ether_hdr);
2939                 break;
2940         case RTE_FLOW_ITEM_TYPE_VLAN:
2941                 retval = sizeof(struct rte_vlan_hdr);
2942                 break;
2943         case RTE_FLOW_ITEM_TYPE_IPV4:
2944                 retval = sizeof(struct rte_ipv4_hdr);
2945                 break;
2946         case RTE_FLOW_ITEM_TYPE_IPV6:
2947                 retval = sizeof(struct rte_ipv6_hdr);
2948                 break;
2949         case RTE_FLOW_ITEM_TYPE_UDP:
2950                 retval = sizeof(struct rte_udp_hdr);
2951                 break;
2952         case RTE_FLOW_ITEM_TYPE_TCP:
2953                 retval = sizeof(struct rte_tcp_hdr);
2954                 break;
2955         case RTE_FLOW_ITEM_TYPE_VXLAN:
2956         case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2957                 retval = sizeof(struct rte_vxlan_hdr);
2958                 break;
2959         case RTE_FLOW_ITEM_TYPE_GRE:
2960         case RTE_FLOW_ITEM_TYPE_NVGRE:
2961                 retval = sizeof(struct rte_gre_hdr);
2962                 break;
2963         case RTE_FLOW_ITEM_TYPE_MPLS:
2964                 retval = sizeof(struct rte_mpls_hdr);
2965                 break;
2966         case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
2967         default:
2968                 retval = 0;
2969                 break;
2970         }
2971         return retval;
2972 }
2973
2974 #define MLX5_ENCAP_IPV4_VERSION         0x40
2975 #define MLX5_ENCAP_IPV4_IHL_MIN         0x05
2976 #define MLX5_ENCAP_IPV4_TTL_DEF         0x40
2977 #define MLX5_ENCAP_IPV6_VTC_FLOW        0x60000000
2978 #define MLX5_ENCAP_IPV6_HOP_LIMIT       0xff
2979 #define MLX5_ENCAP_VXLAN_FLAGS          0x08000000
2980 #define MLX5_ENCAP_VXLAN_GPE_FLAGS      0x04
2981
2982 /**
2983  * Convert the encap action data from list of rte_flow_item to raw buffer
2984  *
2985  * @param[in] items
2986  *   Pointer to rte_flow_item objects list.
2987  * @param[out] buf
2988  *   Pointer to the output buffer.
2989  * @param[out] size
2990  *   Pointer to the output buffer size.
2991  * @param[out] error
2992  *   Pointer to the error structure.
2993  *
2994  * @return
2995  *   0 on success, a negative errno value otherwise and rte_errno is set.
2996  */
2997 static int
2998 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
2999                            size_t *size, struct rte_flow_error *error)
3000 {
3001         struct rte_ether_hdr *eth = NULL;
3002         struct rte_vlan_hdr *vlan = NULL;
3003         struct rte_ipv4_hdr *ipv4 = NULL;
3004         struct rte_ipv6_hdr *ipv6 = NULL;
3005         struct rte_udp_hdr *udp = NULL;
3006         struct rte_vxlan_hdr *vxlan = NULL;
3007         struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
3008         struct rte_gre_hdr *gre = NULL;
3009         size_t len;
3010         size_t temp_size = 0;
3011
3012         if (!items)
3013                 return rte_flow_error_set(error, EINVAL,
3014                                           RTE_FLOW_ERROR_TYPE_ACTION,
3015                                           NULL, "invalid empty data");
3016         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
3017                 len = flow_dv_get_item_hdr_len(items->type);
3018                 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
3019                         return rte_flow_error_set(error, EINVAL,
3020                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3021                                                   (void *)items->type,
3022                                                   "items total size is too big"
3023                                                   " for encap action");
3024                 rte_memcpy((void *)&buf[temp_size], items->spec, len);
3025                 switch (items->type) {
3026                 case RTE_FLOW_ITEM_TYPE_ETH:
3027                         eth = (struct rte_ether_hdr *)&buf[temp_size];
3028                         break;
3029                 case RTE_FLOW_ITEM_TYPE_VLAN:
3030                         vlan = (struct rte_vlan_hdr *)&buf[temp_size];
3031                         if (!eth)
3032                                 return rte_flow_error_set(error, EINVAL,
3033                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3034                                                 (void *)items->type,
3035                                                 "eth header not found");
3036                         if (!eth->ether_type)
3037                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
3038                         break;
3039                 case RTE_FLOW_ITEM_TYPE_IPV4:
3040                         ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
3041                         if (!vlan && !eth)
3042                                 return rte_flow_error_set(error, EINVAL,
3043                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3044                                                 (void *)items->type,
3045                                                 "neither eth nor vlan"
3046                                                 " header found");
3047                         if (vlan && !vlan->eth_proto)
3048                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3049                         else if (eth && !eth->ether_type)
3050                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3051                         if (!ipv4->version_ihl)
3052                                 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
3053                                                     MLX5_ENCAP_IPV4_IHL_MIN;
3054                         if (!ipv4->time_to_live)
3055                                 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
3056                         break;
3057                 case RTE_FLOW_ITEM_TYPE_IPV6:
3058                         ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
3059                         if (!vlan && !eth)
3060                                 return rte_flow_error_set(error, EINVAL,
3061                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3062                                                 (void *)items->type,
3063                                                 "neither eth nor vlan"
3064                                                 " header found");
3065                         if (vlan && !vlan->eth_proto)
3066                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3067                         else if (eth && !eth->ether_type)
3068                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3069                         if (!ipv6->vtc_flow)
3070                                 ipv6->vtc_flow =
3071                                         RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
3072                         if (!ipv6->hop_limits)
3073                                 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
3074                         break;
3075                 case RTE_FLOW_ITEM_TYPE_UDP:
3076                         udp = (struct rte_udp_hdr *)&buf[temp_size];
3077                         if (!ipv4 && !ipv6)
3078                                 return rte_flow_error_set(error, EINVAL,
3079                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3080                                                 (void *)items->type,
3081                                                 "ip header not found");
3082                         if (ipv4 && !ipv4->next_proto_id)
3083                                 ipv4->next_proto_id = IPPROTO_UDP;
3084                         else if (ipv6 && !ipv6->proto)
3085                                 ipv6->proto = IPPROTO_UDP;
3086                         break;
3087                 case RTE_FLOW_ITEM_TYPE_VXLAN:
3088                         vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
3089                         if (!udp)
3090                                 return rte_flow_error_set(error, EINVAL,
3091                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3092                                                 (void *)items->type,
3093                                                 "udp header not found");
3094                         if (!udp->dst_port)
3095                                 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
3096                         if (!vxlan->vx_flags)
3097                                 vxlan->vx_flags =
3098                                         RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
3099                         break;
3100                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3101                         vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
3102                         if (!udp)
3103                                 return rte_flow_error_set(error, EINVAL,
3104                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3105                                                 (void *)items->type,
3106                                                 "udp header not found");
3107                         if (!vxlan_gpe->proto)
3108                                 return rte_flow_error_set(error, EINVAL,
3109                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3110                                                 (void *)items->type,
3111                                                 "next protocol not found");
3112                         if (!udp->dst_port)
3113                                 udp->dst_port =
3114                                         RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
3115                         if (!vxlan_gpe->vx_flags)
3116                                 vxlan_gpe->vx_flags =
3117                                                 MLX5_ENCAP_VXLAN_GPE_FLAGS;
3118                         break;
3119                 case RTE_FLOW_ITEM_TYPE_GRE:
3120                 case RTE_FLOW_ITEM_TYPE_NVGRE:
3121                         gre = (struct rte_gre_hdr *)&buf[temp_size];
3122                         if (!gre->proto)
3123                                 return rte_flow_error_set(error, EINVAL,
3124                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3125                                                 (void *)items->type,
3126                                                 "next protocol not found");
3127                         if (!ipv4 && !ipv6)
3128                                 return rte_flow_error_set(error, EINVAL,
3129                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3130                                                 (void *)items->type,
3131                                                 "ip header not found");
3132                         if (ipv4 && !ipv4->next_proto_id)
3133                                 ipv4->next_proto_id = IPPROTO_GRE;
3134                         else if (ipv6 && !ipv6->proto)
3135                                 ipv6->proto = IPPROTO_GRE;
3136                         break;
3137                 case RTE_FLOW_ITEM_TYPE_VOID:
3138                         break;
3139                 default:
3140                         return rte_flow_error_set(error, EINVAL,
3141                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3142                                                   (void *)items->type,
3143                                                   "unsupported item type");
3144                         break;
3145                 }
3146                 temp_size += len;
3147         }
3148         *size = temp_size;
3149         return 0;
3150 }
3151
3152 static int
3153 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
3154 {
3155         struct rte_ether_hdr *eth = NULL;
3156         struct rte_vlan_hdr *vlan = NULL;
3157         struct rte_ipv6_hdr *ipv6 = NULL;
3158         struct rte_udp_hdr *udp = NULL;
3159         char *next_hdr;
3160         uint16_t proto;
3161
3162         eth = (struct rte_ether_hdr *)data;
3163         next_hdr = (char *)(eth + 1);
3164         proto = RTE_BE16(eth->ether_type);
3165
3166         /* VLAN skipping */
3167         while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
3168                 vlan = (struct rte_vlan_hdr *)next_hdr;
3169                 proto = RTE_BE16(vlan->eth_proto);
3170                 next_hdr += sizeof(struct rte_vlan_hdr);
3171         }
3172
3173         /* HW calculates IPv4 csum. no need to proceed */
3174         if (proto == RTE_ETHER_TYPE_IPV4)
3175                 return 0;
3176
3177         /* non IPv4/IPv6 header. not supported */
3178         if (proto != RTE_ETHER_TYPE_IPV6) {
3179                 return rte_flow_error_set(error, ENOTSUP,
3180                                           RTE_FLOW_ERROR_TYPE_ACTION,
3181                                           NULL, "Cannot offload non IPv4/IPv6");
3182         }
3183
3184         ipv6 = (struct rte_ipv6_hdr *)next_hdr;
3185
3186         /* ignore non UDP */
3187         if (ipv6->proto != IPPROTO_UDP)
3188                 return 0;
3189
3190         udp = (struct rte_udp_hdr *)(ipv6 + 1);
3191         udp->dgram_cksum = 0;
3192
3193         return 0;
3194 }
3195
3196 /**
3197  * Convert L2 encap action to DV specification.
3198  *
3199  * @param[in] dev
3200  *   Pointer to rte_eth_dev structure.
3201  * @param[in] action
3202  *   Pointer to action structure.
3203  * @param[in, out] dev_flow
3204  *   Pointer to the mlx5_flow.
3205  * @param[in] transfer
3206  *   Mark if the flow is E-Switch flow.
3207  * @param[out] error
3208  *   Pointer to the error structure.
3209  *
3210  * @return
3211  *   0 on success, a negative errno value otherwise and rte_errno is set.
3212  */
3213 static int
3214 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
3215                                const struct rte_flow_action *action,
3216                                struct mlx5_flow *dev_flow,
3217                                uint8_t transfer,
3218                                struct rte_flow_error *error)
3219 {
3220         const struct rte_flow_item *encap_data;
3221         const struct rte_flow_action_raw_encap *raw_encap_data;
3222         struct mlx5_flow_dv_encap_decap_resource res = {
3223                 .reformat_type =
3224                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
3225                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3226                                       MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
3227         };
3228
3229         if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
3230                 raw_encap_data =
3231                         (const struct rte_flow_action_raw_encap *)action->conf;
3232                 res.size = raw_encap_data->size;
3233                 memcpy(res.buf, raw_encap_data->data, res.size);
3234         } else {
3235                 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
3236                         encap_data =
3237                                 ((const struct rte_flow_action_vxlan_encap *)
3238                                                 action->conf)->definition;
3239                 else
3240                         encap_data =
3241                                 ((const struct rte_flow_action_nvgre_encap *)
3242                                                 action->conf)->definition;
3243                 if (flow_dv_convert_encap_data(encap_data, res.buf,
3244                                                &res.size, error))
3245                         return -rte_errno;
3246         }
3247         if (flow_dv_zero_encap_udp_csum(res.buf, error))
3248                 return -rte_errno;
3249         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3250                 return rte_flow_error_set(error, EINVAL,
3251                                           RTE_FLOW_ERROR_TYPE_ACTION,
3252                                           NULL, "can't create L2 encap action");
3253         return 0;
3254 }
3255
3256 /**
3257  * Convert L2 decap action to DV specification.
3258  *
3259  * @param[in] dev
3260  *   Pointer to rte_eth_dev structure.
3261  * @param[in, out] dev_flow
3262  *   Pointer to the mlx5_flow.
3263  * @param[in] transfer
3264  *   Mark if the flow is E-Switch flow.
3265  * @param[out] error
3266  *   Pointer to the error structure.
3267  *
3268  * @return
3269  *   0 on success, a negative errno value otherwise and rte_errno is set.
3270  */
3271 static int
3272 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
3273                                struct mlx5_flow *dev_flow,
3274                                uint8_t transfer,
3275                                struct rte_flow_error *error)
3276 {
3277         struct mlx5_flow_dv_encap_decap_resource res = {
3278                 .size = 0,
3279                 .reformat_type =
3280                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
3281                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3282                                       MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
3283         };
3284
3285         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3286                 return rte_flow_error_set(error, EINVAL,
3287                                           RTE_FLOW_ERROR_TYPE_ACTION,
3288                                           NULL, "can't create L2 decap action");
3289         return 0;
3290 }
3291
3292 /**
3293  * Convert raw decap/encap (L3 tunnel) action to DV specification.
3294  *
3295  * @param[in] dev
3296  *   Pointer to rte_eth_dev structure.
3297  * @param[in] action
3298  *   Pointer to action structure.
3299  * @param[in, out] dev_flow
3300  *   Pointer to the mlx5_flow.
3301  * @param[in] attr
3302  *   Pointer to the flow attributes.
3303  * @param[out] error
3304  *   Pointer to the error structure.
3305  *
3306  * @return
3307  *   0 on success, a negative errno value otherwise and rte_errno is set.
3308  */
3309 static int
3310 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
3311                                 const struct rte_flow_action *action,
3312                                 struct mlx5_flow *dev_flow,
3313                                 const struct rte_flow_attr *attr,
3314                                 struct rte_flow_error *error)
3315 {
3316         const struct rte_flow_action_raw_encap *encap_data;
3317         struct mlx5_flow_dv_encap_decap_resource res;
3318
3319         memset(&res, 0, sizeof(res));
3320         encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
3321         res.size = encap_data->size;
3322         memcpy(res.buf, encap_data->data, res.size);
3323         res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
3324                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
3325                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
3326         if (attr->transfer)
3327                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3328         else
3329                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3330                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3331         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3332                 return rte_flow_error_set(error, EINVAL,
3333                                           RTE_FLOW_ERROR_TYPE_ACTION,
3334                                           NULL, "can't create encap action");
3335         return 0;
3336 }
3337
3338 /**
3339  * Create action push VLAN.
3340  *
3341  * @param[in] dev
3342  *   Pointer to rte_eth_dev structure.
3343  * @param[in] attr
3344  *   Pointer to the flow attributes.
3345  * @param[in] vlan
3346  *   Pointer to the vlan to push to the Ethernet header.
3347  * @param[in, out] dev_flow
3348  *   Pointer to the mlx5_flow.
3349  * @param[out] error
3350  *   Pointer to the error structure.
3351  *
3352  * @return
3353  *   0 on success, a negative errno value otherwise and rte_errno is set.
3354  */
3355 static int
3356 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
3357                                 const struct rte_flow_attr *attr,
3358                                 const struct rte_vlan_hdr *vlan,
3359                                 struct mlx5_flow *dev_flow,
3360                                 struct rte_flow_error *error)
3361 {
3362         struct mlx5_flow_dv_push_vlan_action_resource res;
3363
3364         memset(&res, 0, sizeof(res));
3365         res.vlan_tag =
3366                 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
3367                                  vlan->vlan_tci);
3368         if (attr->transfer)
3369                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3370         else
3371                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3372                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3373         return flow_dv_push_vlan_action_resource_register
3374                                             (dev, &res, dev_flow, error);
3375 }
3376
3377 /**
3378  * Validate the modify-header actions.
3379  *
3380  * @param[in] action_flags
3381  *   Holds the actions detected until now.
3382  * @param[in] action
3383  *   Pointer to the modify action.
3384  * @param[out] error
3385  *   Pointer to error structure.
3386  *
3387  * @return
3388  *   0 on success, a negative errno value otherwise and rte_errno is set.
3389  */
3390 static int
3391 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
3392                                    const struct rte_flow_action *action,
3393                                    struct rte_flow_error *error)
3394 {
3395         if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
3396                 return rte_flow_error_set(error, EINVAL,
3397                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3398                                           NULL, "action configuration not set");
3399         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3400                 return rte_flow_error_set(error, EINVAL,
3401                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3402                                           "can't have encap action before"
3403                                           " modify action");
3404         return 0;
3405 }
3406
3407 /**
3408  * Validate the modify-header MAC address actions.
3409  *
3410  * @param[in] action_flags
3411  *   Holds the actions detected until now.
3412  * @param[in] action
3413  *   Pointer to the modify action.
3414  * @param[in] item_flags
3415  *   Holds the items detected.
3416  * @param[out] error
3417  *   Pointer to error structure.
3418  *
3419  * @return
3420  *   0 on success, a negative errno value otherwise and rte_errno is set.
3421  */
3422 static int
3423 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
3424                                    const struct rte_flow_action *action,
3425                                    const uint64_t item_flags,
3426                                    struct rte_flow_error *error)
3427 {
3428         int ret = 0;
3429
3430         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3431         if (!ret) {
3432                 if (!(item_flags & MLX5_FLOW_LAYER_L2))
3433                         return rte_flow_error_set(error, EINVAL,
3434                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3435                                                   NULL,
3436                                                   "no L2 item in pattern");
3437         }
3438         return ret;
3439 }
3440
3441 /**
3442  * Validate the modify-header IPv4 address actions.
3443  *
3444  * @param[in] action_flags
3445  *   Holds the actions detected until now.
3446  * @param[in] action
3447  *   Pointer to the modify action.
3448  * @param[in] item_flags
3449  *   Holds the items detected.
3450  * @param[out] error
3451  *   Pointer to error structure.
3452  *
3453  * @return
3454  *   0 on success, a negative errno value otherwise and rte_errno is set.
3455  */
3456 static int
3457 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
3458                                     const struct rte_flow_action *action,
3459                                     const uint64_t item_flags,
3460                                     struct rte_flow_error *error)
3461 {
3462         int ret = 0;
3463         uint64_t layer;
3464
3465         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3466         if (!ret) {
3467                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3468                                  MLX5_FLOW_LAYER_INNER_L3_IPV4 :
3469                                  MLX5_FLOW_LAYER_OUTER_L3_IPV4;
3470                 if (!(item_flags & layer))
3471                         return rte_flow_error_set(error, EINVAL,
3472                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3473                                                   NULL,
3474                                                   "no ipv4 item in pattern");
3475         }
3476         return ret;
3477 }
3478
3479 /**
3480  * Validate the modify-header IPv6 address actions.
3481  *
3482  * @param[in] action_flags
3483  *   Holds the actions detected until now.
3484  * @param[in] action
3485  *   Pointer to the modify action.
3486  * @param[in] item_flags
3487  *   Holds the items detected.
3488  * @param[out] error
3489  *   Pointer to error structure.
3490  *
3491  * @return
3492  *   0 on success, a negative errno value otherwise and rte_errno is set.
3493  */
3494 static int
3495 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
3496                                     const struct rte_flow_action *action,
3497                                     const uint64_t item_flags,
3498                                     struct rte_flow_error *error)
3499 {
3500         int ret = 0;
3501         uint64_t layer;
3502
3503         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3504         if (!ret) {
3505                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3506                                  MLX5_FLOW_LAYER_INNER_L3_IPV6 :
3507                                  MLX5_FLOW_LAYER_OUTER_L3_IPV6;
3508                 if (!(item_flags & layer))
3509                         return rte_flow_error_set(error, EINVAL,
3510                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3511                                                   NULL,
3512                                                   "no ipv6 item in pattern");
3513         }
3514         return ret;
3515 }
3516
3517 /**
3518  * Validate the modify-header TP actions.
3519  *
3520  * @param[in] action_flags
3521  *   Holds the actions detected until now.
3522  * @param[in] action
3523  *   Pointer to the modify action.
3524  * @param[in] item_flags
3525  *   Holds the items detected.
3526  * @param[out] error
3527  *   Pointer to error structure.
3528  *
3529  * @return
3530  *   0 on success, a negative errno value otherwise and rte_errno is set.
3531  */
3532 static int
3533 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
3534                                   const struct rte_flow_action *action,
3535                                   const uint64_t item_flags,
3536                                   struct rte_flow_error *error)
3537 {
3538         int ret = 0;
3539         uint64_t layer;
3540
3541         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3542         if (!ret) {
3543                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3544                                  MLX5_FLOW_LAYER_INNER_L4 :
3545                                  MLX5_FLOW_LAYER_OUTER_L4;
3546                 if (!(item_flags & layer))
3547                         return rte_flow_error_set(error, EINVAL,
3548                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3549                                                   NULL, "no transport layer "
3550                                                   "in pattern");
3551         }
3552         return ret;
3553 }
3554
3555 /**
3556  * Validate the modify-header actions of increment/decrement
3557  * TCP Sequence-number.
3558  *
3559  * @param[in] action_flags
3560  *   Holds the actions detected until now.
3561  * @param[in] action
3562  *   Pointer to the modify action.
3563  * @param[in] item_flags
3564  *   Holds the items detected.
3565  * @param[out] error
3566  *   Pointer to error structure.
3567  *
3568  * @return
3569  *   0 on success, a negative errno value otherwise and rte_errno is set.
3570  */
3571 static int
3572 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
3573                                        const struct rte_flow_action *action,
3574                                        const uint64_t item_flags,
3575                                        struct rte_flow_error *error)
3576 {
3577         int ret = 0;
3578         uint64_t layer;
3579
3580         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3581         if (!ret) {
3582                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3583                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
3584                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
3585                 if (!(item_flags & layer))
3586                         return rte_flow_error_set(error, EINVAL,
3587                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3588                                                   NULL, "no TCP item in"
3589                                                   " pattern");
3590                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
3591                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
3592                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
3593                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
3594                         return rte_flow_error_set(error, EINVAL,
3595                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3596                                                   NULL,
3597                                                   "cannot decrease and increase"
3598                                                   " TCP sequence number"
3599                                                   " at the same time");
3600         }
3601         return ret;
3602 }
3603
3604 /**
3605  * Validate the modify-header actions of increment/decrement
3606  * TCP Acknowledgment number.
3607  *
3608  * @param[in] action_flags
3609  *   Holds the actions detected until now.
3610  * @param[in] action
3611  *   Pointer to the modify action.
3612  * @param[in] item_flags
3613  *   Holds the items detected.
3614  * @param[out] error
3615  *   Pointer to error structure.
3616  *
3617  * @return
3618  *   0 on success, a negative errno value otherwise and rte_errno is set.
3619  */
3620 static int
3621 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
3622                                        const struct rte_flow_action *action,
3623                                        const uint64_t item_flags,
3624                                        struct rte_flow_error *error)
3625 {
3626         int ret = 0;
3627         uint64_t layer;
3628
3629         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3630         if (!ret) {
3631                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3632                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
3633                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
3634                 if (!(item_flags & layer))
3635                         return rte_flow_error_set(error, EINVAL,
3636                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3637                                                   NULL, "no TCP item in"
3638                                                   " pattern");
3639                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
3640                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
3641                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
3642                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
3643                         return rte_flow_error_set(error, EINVAL,
3644                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3645                                                   NULL,
3646                                                   "cannot decrease and increase"
3647                                                   " TCP acknowledgment number"
3648                                                   " at the same time");
3649         }
3650         return ret;
3651 }
3652
3653 /**
3654  * Validate the modify-header TTL actions.
3655  *
3656  * @param[in] action_flags
3657  *   Holds the actions detected until now.
3658  * @param[in] action
3659  *   Pointer to the modify action.
3660  * @param[in] item_flags
3661  *   Holds the items detected.
3662  * @param[out] error
3663  *   Pointer to error structure.
3664  *
3665  * @return
3666  *   0 on success, a negative errno value otherwise and rte_errno is set.
3667  */
3668 static int
3669 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
3670                                    const struct rte_flow_action *action,
3671                                    const uint64_t item_flags,
3672                                    struct rte_flow_error *error)
3673 {
3674         int ret = 0;
3675         uint64_t layer;
3676
3677         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3678         if (!ret) {
3679                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3680                                  MLX5_FLOW_LAYER_INNER_L3 :
3681                                  MLX5_FLOW_LAYER_OUTER_L3;
3682                 if (!(item_flags & layer))
3683                         return rte_flow_error_set(error, EINVAL,
3684                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3685                                                   NULL,
3686                                                   "no IP protocol in pattern");
3687         }
3688         return ret;
3689 }
3690
3691 /**
3692  * Validate jump action.
3693  *
3694  * @param[in] action
3695  *   Pointer to the jump action.
3696  * @param[in] action_flags
3697  *   Holds the actions detected until now.
3698  * @param[in] attributes
3699  *   Pointer to flow attributes
3700  * @param[in] external
3701  *   Action belongs to flow rule created by request external to PMD.
3702  * @param[out] error
3703  *   Pointer to error structure.
3704  *
3705  * @return
3706  *   0 on success, a negative errno value otherwise and rte_errno is set.
3707  */
3708 static int
3709 flow_dv_validate_action_jump(const struct rte_flow_action *action,
3710                              uint64_t action_flags,
3711                              const struct rte_flow_attr *attributes,
3712                              bool external, struct rte_flow_error *error)
3713 {
3714         uint32_t target_group, table;
3715         int ret = 0;
3716
3717         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3718                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3719                 return rte_flow_error_set(error, EINVAL,
3720                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3721                                           "can't have 2 fate actions in"
3722                                           " same flow");
3723         if (action_flags & MLX5_FLOW_ACTION_METER)
3724                 return rte_flow_error_set(error, ENOTSUP,
3725                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3726                                           "jump with meter not support");
3727         if (!action->conf)
3728                 return rte_flow_error_set(error, EINVAL,
3729                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3730                                           NULL, "action configuration not set");
3731         target_group =
3732                 ((const struct rte_flow_action_jump *)action->conf)->group;
3733         ret = mlx5_flow_group_to_table(attributes, external, target_group,
3734                                        true, &table, error);
3735         if (ret)
3736                 return ret;
3737         if (attributes->group == target_group)
3738                 return rte_flow_error_set(error, EINVAL,
3739                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3740                                           "target group must be other than"
3741                                           " the current flow group");
3742         return 0;
3743 }
3744
3745 /*
3746  * Validate the port_id action.
3747  *
3748  * @param[in] dev
3749  *   Pointer to rte_eth_dev structure.
3750  * @param[in] action_flags
3751  *   Bit-fields that holds the actions detected until now.
3752  * @param[in] action
3753  *   Port_id RTE action structure.
3754  * @param[in] attr
3755  *   Attributes of flow that includes this action.
3756  * @param[out] error
3757  *   Pointer to error structure.
3758  *
3759  * @return
3760  *   0 on success, a negative errno value otherwise and rte_errno is set.
3761  */
3762 static int
3763 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
3764                                 uint64_t action_flags,
3765                                 const struct rte_flow_action *action,
3766                                 const struct rte_flow_attr *attr,
3767                                 struct rte_flow_error *error)
3768 {
3769         const struct rte_flow_action_port_id *port_id;
3770         struct mlx5_priv *act_priv;
3771         struct mlx5_priv *dev_priv;
3772         uint16_t port;
3773
3774         if (!attr->transfer)
3775                 return rte_flow_error_set(error, ENOTSUP,
3776                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3777                                           NULL,
3778                                           "port id action is valid in transfer"
3779                                           " mode only");
3780         if (!action || !action->conf)
3781                 return rte_flow_error_set(error, ENOTSUP,
3782                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3783                                           NULL,
3784                                           "port id action parameters must be"
3785                                           " specified");
3786         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3787                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3788                 return rte_flow_error_set(error, EINVAL,
3789                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3790                                           "can have only one fate actions in"
3791                                           " a flow");
3792         dev_priv = mlx5_dev_to_eswitch_info(dev);
3793         if (!dev_priv)
3794                 return rte_flow_error_set(error, rte_errno,
3795                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3796                                           NULL,
3797                                           "failed to obtain E-Switch info");
3798         port_id = action->conf;
3799         port = port_id->original ? dev->data->port_id : port_id->id;
3800         act_priv = mlx5_port_to_eswitch_info(port, false);
3801         if (!act_priv)
3802                 return rte_flow_error_set
3803                                 (error, rte_errno,
3804                                  RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
3805                                  "failed to obtain E-Switch port id for port");
3806         if (act_priv->domain_id != dev_priv->domain_id)
3807                 return rte_flow_error_set
3808                                 (error, EINVAL,
3809                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3810                                  "port does not belong to"
3811                                  " E-Switch being configured");
3812         return 0;
3813 }
3814
3815 /**
3816  * Get the maximum number of modify header actions.
3817  *
3818  * @param dev
3819  *   Pointer to rte_eth_dev structure.
3820  * @param flags
3821  *   Flags bits to check if root level.
3822  *
3823  * @return
3824  *   Max number of modify header actions device can support.
3825  */
3826 static inline unsigned int
3827 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev __rte_unused,
3828                               uint64_t flags)
3829 {
3830         /*
3831          * There's no way to directly query the max capacity from FW.
3832          * The maximal value on root table should be assumed to be supported.
3833          */
3834         if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
3835                 return MLX5_MAX_MODIFY_NUM;
3836         else
3837                 return MLX5_ROOT_TBL_MODIFY_NUM;
3838 }
3839
3840 /**
3841  * Validate the meter action.
3842  *
3843  * @param[in] dev
3844  *   Pointer to rte_eth_dev structure.
3845  * @param[in] action_flags
3846  *   Bit-fields that holds the actions detected until now.
3847  * @param[in] action
3848  *   Pointer to the meter action.
3849  * @param[in] attr
3850  *   Attributes of flow that includes this action.
3851  * @param[out] error
3852  *   Pointer to error structure.
3853  *
3854  * @return
3855  *   0 on success, a negative errno value otherwise and rte_ernno is set.
3856  */
3857 static int
3858 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
3859                                 uint64_t action_flags,
3860                                 const struct rte_flow_action *action,
3861                                 const struct rte_flow_attr *attr,
3862                                 struct rte_flow_error *error)
3863 {
3864         struct mlx5_priv *priv = dev->data->dev_private;
3865         const struct rte_flow_action_meter *am = action->conf;
3866         struct mlx5_flow_meter *fm;
3867
3868         if (!am)
3869                 return rte_flow_error_set(error, EINVAL,
3870                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3871                                           "meter action conf is NULL");
3872
3873         if (action_flags & MLX5_FLOW_ACTION_METER)
3874                 return rte_flow_error_set(error, ENOTSUP,
3875                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3876                                           "meter chaining not support");
3877         if (action_flags & MLX5_FLOW_ACTION_JUMP)
3878                 return rte_flow_error_set(error, ENOTSUP,
3879                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3880                                           "meter with jump not support");
3881         if (!priv->mtr_en)
3882                 return rte_flow_error_set(error, ENOTSUP,
3883                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3884                                           NULL,
3885                                           "meter action not supported");
3886         fm = mlx5_flow_meter_find(priv, am->mtr_id);
3887         if (!fm)
3888                 return rte_flow_error_set(error, EINVAL,
3889                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3890                                           "Meter not found");
3891         if (fm->ref_cnt && (!(fm->transfer == attr->transfer ||
3892               (!fm->ingress && !attr->ingress && attr->egress) ||
3893               (!fm->egress && !attr->egress && attr->ingress))))
3894                 return rte_flow_error_set(error, EINVAL,
3895                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3896                                           "Flow attributes are either invalid "
3897                                           "or have a conflict with current "
3898                                           "meter attributes");
3899         return 0;
3900 }
3901
3902 /**
3903  * Validate the age action.
3904  *
3905  * @param[in] action_flags
3906  *   Holds the actions detected until now.
3907  * @param[in] action
3908  *   Pointer to the age action.
3909  * @param[in] dev
3910  *   Pointer to the Ethernet device structure.
3911  * @param[out] error
3912  *   Pointer to error structure.
3913  *
3914  * @return
3915  *   0 on success, a negative errno value otherwise and rte_errno is set.
3916  */
3917 static int
3918 flow_dv_validate_action_age(uint64_t action_flags,
3919                             const struct rte_flow_action *action,
3920                             struct rte_eth_dev *dev,
3921                             struct rte_flow_error *error)
3922 {
3923         struct mlx5_priv *priv = dev->data->dev_private;
3924         const struct rte_flow_action_age *age = action->conf;
3925
3926         if (!priv->config.devx || priv->counter_fallback)
3927                 return rte_flow_error_set(error, ENOTSUP,
3928                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3929                                           NULL,
3930                                           "age action not supported");
3931         if (!(action->conf))
3932                 return rte_flow_error_set(error, EINVAL,
3933                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3934                                           "configuration cannot be null");
3935         if (age->timeout >= UINT16_MAX / 2 / 10)
3936                 return rte_flow_error_set(error, ENOTSUP,
3937                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3938                                           "Max age time: 3275 seconds");
3939         if (action_flags & MLX5_FLOW_ACTION_AGE)
3940                 return rte_flow_error_set(error, EINVAL,
3941                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3942                                           "Duplicate age ctions set");
3943         return 0;
3944 }
3945
3946 /**
3947  * Validate the modify-header IPv4 DSCP actions.
3948  *
3949  * @param[in] action_flags
3950  *   Holds the actions detected until now.
3951  * @param[in] action
3952  *   Pointer to the modify action.
3953  * @param[in] item_flags
3954  *   Holds the items detected.
3955  * @param[out] error
3956  *   Pointer to error structure.
3957  *
3958  * @return
3959  *   0 on success, a negative errno value otherwise and rte_errno is set.
3960  */
3961 static int
3962 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
3963                                          const struct rte_flow_action *action,
3964                                          const uint64_t item_flags,
3965                                          struct rte_flow_error *error)
3966 {
3967         int ret = 0;
3968
3969         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3970         if (!ret) {
3971                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
3972                         return rte_flow_error_set(error, EINVAL,
3973                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3974                                                   NULL,
3975                                                   "no ipv4 item in pattern");
3976         }
3977         return ret;
3978 }
3979
3980 /**
3981  * Validate the modify-header IPv6 DSCP actions.
3982  *
3983  * @param[in] action_flags
3984  *   Holds the actions detected until now.
3985  * @param[in] action
3986  *   Pointer to the modify action.
3987  * @param[in] item_flags
3988  *   Holds the items detected.
3989  * @param[out] error
3990  *   Pointer to error structure.
3991  *
3992  * @return
3993  *   0 on success, a negative errno value otherwise and rte_errno is set.
3994  */
3995 static int
3996 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
3997                                          const struct rte_flow_action *action,
3998                                          const uint64_t item_flags,
3999                                          struct rte_flow_error *error)
4000 {
4001         int ret = 0;
4002
4003         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4004         if (!ret) {
4005                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
4006                         return rte_flow_error_set(error, EINVAL,
4007                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4008                                                   NULL,
4009                                                   "no ipv6 item in pattern");
4010         }
4011         return ret;
4012 }
4013
4014 /**
4015  * Match modify-header resource.
4016  *
4017  * @param entry
4018  *   Pointer to exist resource entry object.
4019  * @param ctx
4020  *   Pointer to new modify-header resource.
4021  *
4022  * @return
4023  *   0 on matching, -1 otherwise.
4024  */
4025 static int
4026 flow_dv_modify_hdr_resource_match(struct mlx5_hlist_entry *entry, void *ctx)
4027 {
4028         struct mlx5_flow_dv_modify_hdr_resource *resource;
4029         struct mlx5_flow_dv_modify_hdr_resource *cache_resource;
4030         uint32_t actions_len;
4031
4032         resource = (struct mlx5_flow_dv_modify_hdr_resource *)ctx;
4033         cache_resource = container_of(entry,
4034                                       struct mlx5_flow_dv_modify_hdr_resource,
4035                                       entry);
4036         actions_len = resource->actions_num * sizeof(resource->actions[0]);
4037         if (resource->entry.key == cache_resource->entry.key &&
4038             resource->ft_type == cache_resource->ft_type &&
4039             resource->actions_num == cache_resource->actions_num &&
4040             resource->flags == cache_resource->flags &&
4041             !memcmp((const void *)resource->actions,
4042                     (const void *)cache_resource->actions,
4043                     actions_len))
4044                 return 0;
4045         return -1;
4046 }
4047
4048 /**
4049  * Validate the sample action.
4050  *
4051  * @param[in] action_flags
4052  *   Holds the actions detected until now.
4053  * @param[in] action
4054  *   Pointer to the sample action.
4055  * @param[in] dev
4056  *   Pointer to the Ethernet device structure.
4057  * @param[in] attr
4058  *   Attributes of flow that includes this action.
4059  * @param[out] error
4060  *   Pointer to error structure.
4061  *
4062  * @return
4063  *   0 on success, a negative errno value otherwise and rte_errno is set.
4064  */
4065 static int
4066 flow_dv_validate_action_sample(uint64_t action_flags,
4067                                const struct rte_flow_action *action,
4068                                struct rte_eth_dev *dev,
4069                                const struct rte_flow_attr *attr,
4070                                struct rte_flow_error *error)
4071 {
4072         struct mlx5_priv *priv = dev->data->dev_private;
4073         struct mlx5_dev_config *dev_conf = &priv->config;
4074         const struct rte_flow_action_sample *sample = action->conf;
4075         const struct rte_flow_action *act;
4076         uint64_t sub_action_flags = 0;
4077         int actions_n = 0;
4078         int ret;
4079
4080         if (!sample)
4081                 return rte_flow_error_set(error, EINVAL,
4082                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4083                                           "configuration cannot be NULL");
4084         if (sample->ratio == 0)
4085                 return rte_flow_error_set(error, EINVAL,
4086                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4087                                           "ratio value starts from 1");
4088         if (!priv->config.devx || (sample->ratio > 0 && !priv->sampler_en))
4089                 return rte_flow_error_set(error, ENOTSUP,
4090                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4091                                           NULL,
4092                                           "sample action not supported");
4093         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
4094                 return rte_flow_error_set(error, EINVAL,
4095                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4096                                           "Multiple sample actions not "
4097                                           "supported");
4098         if (action_flags & MLX5_FLOW_ACTION_METER)
4099                 return rte_flow_error_set(error, EINVAL,
4100                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4101                                           "wrong action order, meter should "
4102                                           "be after sample action");
4103         if (action_flags & MLX5_FLOW_ACTION_JUMP)
4104                 return rte_flow_error_set(error, EINVAL,
4105                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4106                                           "wrong action order, jump should "
4107                                           "be after sample action");
4108         act = sample->actions;
4109         for (; act->type != RTE_FLOW_ACTION_TYPE_END; act++) {
4110                 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
4111                         return rte_flow_error_set(error, ENOTSUP,
4112                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4113                                                   act, "too many actions");
4114                 switch (act->type) {
4115                 case RTE_FLOW_ACTION_TYPE_QUEUE:
4116                         ret = mlx5_flow_validate_action_queue(act,
4117                                                               sub_action_flags,
4118                                                               dev,
4119                                                               attr, error);
4120                         if (ret < 0)
4121                                 return ret;
4122                         sub_action_flags |= MLX5_FLOW_ACTION_QUEUE;
4123                         ++actions_n;
4124                         break;
4125                 case RTE_FLOW_ACTION_TYPE_MARK:
4126                         ret = flow_dv_validate_action_mark(dev, act,
4127                                                            sub_action_flags,
4128                                                            attr, error);
4129                         if (ret < 0)
4130                                 return ret;
4131                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY)
4132                                 sub_action_flags |= MLX5_FLOW_ACTION_MARK |
4133                                                 MLX5_FLOW_ACTION_MARK_EXT;
4134                         else
4135                                 sub_action_flags |= MLX5_FLOW_ACTION_MARK;
4136                         ++actions_n;
4137                         break;
4138                 case RTE_FLOW_ACTION_TYPE_COUNT:
4139                         ret = flow_dv_validate_action_count(dev, error);
4140                         if (ret < 0)
4141                                 return ret;
4142                         sub_action_flags |= MLX5_FLOW_ACTION_COUNT;
4143                         ++actions_n;
4144                         break;
4145                 default:
4146                         return rte_flow_error_set(error, ENOTSUP,
4147                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4148                                                   NULL,
4149                                                   "Doesn't support optional "
4150                                                   "action");
4151                 }
4152         }
4153         if (attr->ingress && !attr->transfer) {
4154                 if (!(sub_action_flags & MLX5_FLOW_ACTION_QUEUE))
4155                         return rte_flow_error_set(error, EINVAL,
4156                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4157                                                   NULL,
4158                                                   "Ingress must has a dest "
4159                                                   "QUEUE for Sample");
4160         } else if (attr->egress && !attr->transfer) {
4161                 return rte_flow_error_set(error, ENOTSUP,
4162                                           RTE_FLOW_ERROR_TYPE_ACTION,
4163                                           NULL,
4164                                           "Sample Only support Ingress "
4165                                           "or E-Switch");
4166         } else if (sample->actions->type != RTE_FLOW_ACTION_TYPE_END) {
4167                 MLX5_ASSERT(attr->transfer);
4168                 return rte_flow_error_set(error, ENOTSUP,
4169                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4170                                           "E-Switch doesn't support any "
4171                                           "optional action for sampling");
4172         }
4173         return 0;
4174 }
4175
4176 /**
4177  * Find existing modify-header resource or create and register a new one.
4178  *
4179  * @param dev[in, out]
4180  *   Pointer to rte_eth_dev structure.
4181  * @param[in, out] resource
4182  *   Pointer to modify-header resource.
4183  * @parm[in, out] dev_flow
4184  *   Pointer to the dev_flow.
4185  * @param[out] error
4186  *   pointer to error structure.
4187  *
4188  * @return
4189  *   0 on success otherwise -errno and errno is set.
4190  */
4191 static int
4192 flow_dv_modify_hdr_resource_register
4193                         (struct rte_eth_dev *dev,
4194                          struct mlx5_flow_dv_modify_hdr_resource *resource,
4195                          struct mlx5_flow *dev_flow,
4196                          struct rte_flow_error *error)
4197 {
4198         struct mlx5_priv *priv = dev->data->dev_private;
4199         struct mlx5_dev_ctx_shared *sh = priv->sh;
4200         struct mlx5_flow_dv_modify_hdr_resource *cache_resource;
4201         struct mlx5dv_dr_domain *ns;
4202         uint32_t actions_len;
4203         struct mlx5_hlist_entry *entry;
4204         union mlx5_flow_modify_hdr_key hdr_mod_key = {
4205                 {
4206                         .ft_type = resource->ft_type,
4207                         .actions_num = resource->actions_num,
4208                         .group = dev_flow->dv.group,
4209                         .cksum = 0,
4210                 }
4211         };
4212         int ret;
4213
4214         resource->flags = dev_flow->dv.group ? 0 :
4215                           MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
4216         if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
4217                                     resource->flags))
4218                 return rte_flow_error_set(error, EOVERFLOW,
4219                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4220                                           "too many modify header items");
4221         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
4222                 ns = sh->fdb_domain;
4223         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
4224                 ns = sh->tx_domain;
4225         else
4226                 ns = sh->rx_domain;
4227         /* Lookup a matching resource from cache. */
4228         actions_len = resource->actions_num * sizeof(resource->actions[0]);
4229         hdr_mod_key.cksum = __rte_raw_cksum(resource->actions, actions_len, 0);
4230         resource->entry.key = hdr_mod_key.v64;
4231         entry = mlx5_hlist_lookup_ex(sh->modify_cmds, resource->entry.key,
4232                                      flow_dv_modify_hdr_resource_match,
4233                                      (void *)resource);
4234         if (entry) {
4235                 cache_resource = container_of(entry,
4236                                         struct mlx5_flow_dv_modify_hdr_resource,
4237                                         entry);
4238                 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d++",
4239                         (void *)cache_resource,
4240                         rte_atomic32_read(&cache_resource->refcnt));
4241                 rte_atomic32_inc(&cache_resource->refcnt);
4242                 dev_flow->handle->dvh.modify_hdr = cache_resource;
4243                 return 0;
4244
4245         }
4246         /* Register new modify-header resource. */
4247         cache_resource = mlx5_malloc(MLX5_MEM_ZERO,
4248                                     sizeof(*cache_resource) + actions_len, 0,
4249                                     SOCKET_ID_ANY);
4250         if (!cache_resource)
4251                 return rte_flow_error_set(error, ENOMEM,
4252                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4253                                           "cannot allocate resource memory");
4254         *cache_resource = *resource;
4255         rte_memcpy(cache_resource->actions, resource->actions, actions_len);
4256         ret = mlx5_flow_os_create_flow_action_modify_header
4257                                         (sh->ctx, ns, cache_resource,
4258                                          actions_len, &cache_resource->action);
4259         if (ret) {
4260                 mlx5_free(cache_resource);
4261                 return rte_flow_error_set(error, ENOMEM,
4262                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4263                                           NULL, "cannot create action");
4264         }
4265         rte_atomic32_init(&cache_resource->refcnt);
4266         rte_atomic32_inc(&cache_resource->refcnt);
4267         if (mlx5_hlist_insert_ex(sh->modify_cmds, &cache_resource->entry,
4268                                  flow_dv_modify_hdr_resource_match,
4269                                  (void *)cache_resource)) {
4270                 claim_zero(mlx5_flow_os_destroy_flow_action
4271                                                 (cache_resource->action));
4272                 mlx5_free(cache_resource);
4273                 return rte_flow_error_set(error, EEXIST,
4274                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4275                                           NULL, "action exist");
4276         }
4277         dev_flow->handle->dvh.modify_hdr = cache_resource;
4278         DRV_LOG(DEBUG, "new modify-header resource %p: refcnt %d++",
4279                 (void *)cache_resource,
4280                 rte_atomic32_read(&cache_resource->refcnt));
4281         return 0;
4282 }
4283
4284 /**
4285  * Get DV flow counter by index.
4286  *
4287  * @param[in] dev
4288  *   Pointer to the Ethernet device structure.
4289  * @param[in] idx
4290  *   mlx5 flow counter index in the container.
4291  * @param[out] ppool
4292  *   mlx5 flow counter pool in the container,
4293  *
4294  * @return
4295  *   Pointer to the counter, NULL otherwise.
4296  */
4297 static struct mlx5_flow_counter *
4298 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
4299                            uint32_t idx,
4300                            struct mlx5_flow_counter_pool **ppool)
4301 {
4302         struct mlx5_priv *priv = dev->data->dev_private;
4303         struct mlx5_pools_container *cont;
4304         struct mlx5_flow_counter_pool *pool;
4305         uint32_t batch = 0, age = 0;
4306
4307         idx--;
4308         age = MLX_CNT_IS_AGE(idx);
4309         idx = age ? idx - MLX5_CNT_AGE_OFFSET : idx;
4310         if (idx >= MLX5_CNT_BATCH_OFFSET) {
4311                 idx -= MLX5_CNT_BATCH_OFFSET;
4312                 batch = 1;
4313         }
4314         cont = MLX5_CNT_CONTAINER(priv->sh, batch, age);
4315         MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cont->n);
4316         pool = cont->pools[idx / MLX5_COUNTERS_PER_POOL];
4317         MLX5_ASSERT(pool);
4318         if (ppool)
4319                 *ppool = pool;
4320         return MLX5_POOL_GET_CNT(pool, idx % MLX5_COUNTERS_PER_POOL);
4321 }
4322
4323 /**
4324  * Check the devx counter belongs to the pool.
4325  *
4326  * @param[in] pool
4327  *   Pointer to the counter pool.
4328  * @param[in] id
4329  *   The counter devx ID.
4330  *
4331  * @return
4332  *   True if counter belongs to the pool, false otherwise.
4333  */
4334 static bool
4335 flow_dv_is_counter_in_pool(struct mlx5_flow_counter_pool *pool, int id)
4336 {
4337         int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
4338                    MLX5_COUNTERS_PER_POOL;
4339
4340         if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
4341                 return true;
4342         return false;
4343 }
4344
4345 /**
4346  * Get a pool by devx counter ID.
4347  *
4348  * @param[in] cont
4349  *   Pointer to the counter container.
4350  * @param[in] id
4351  *   The counter devx ID.
4352  *
4353  * @return
4354  *   The counter pool pointer if exists, NULL otherwise,
4355  */
4356 static struct mlx5_flow_counter_pool *
4357 flow_dv_find_pool_by_id(struct mlx5_pools_container *cont, int id)
4358 {
4359         uint32_t i;
4360
4361         /* Check last used pool. */
4362         if (cont->last_pool_idx != POOL_IDX_INVALID &&
4363             flow_dv_is_counter_in_pool(cont->pools[cont->last_pool_idx], id))
4364                 return cont->pools[cont->last_pool_idx];
4365         /* ID out of range means no suitable pool in the container. */
4366         if (id > cont->max_id || id < cont->min_id)
4367                 return NULL;
4368         /*
4369          * Find the pool from the end of the container, since mostly counter
4370          * ID is sequence increasing, and the last pool should be the needed
4371          * one.
4372          */
4373         i = rte_atomic16_read(&cont->n_valid);
4374         while (i--) {
4375                 struct mlx5_flow_counter_pool *pool = cont->pools[i];
4376
4377                 if (flow_dv_is_counter_in_pool(pool, id))
4378                         return pool;
4379         }
4380         return NULL;
4381 }
4382
4383 /**
4384  * Allocate a new memory for the counter values wrapped by all the needed
4385  * management.
4386  *
4387  * @param[in] dev
4388  *   Pointer to the Ethernet device structure.
4389  * @param[in] raws_n
4390  *   The raw memory areas - each one for MLX5_COUNTERS_PER_POOL counters.
4391  *
4392  * @return
4393  *   The new memory management pointer on success, otherwise NULL and rte_errno
4394  *   is set.
4395  */
4396 static struct mlx5_counter_stats_mem_mng *
4397 flow_dv_create_counter_stat_mem_mng(struct rte_eth_dev *dev, int raws_n)
4398 {
4399         struct mlx5_priv *priv = dev->data->dev_private;
4400         struct mlx5_dev_ctx_shared *sh = priv->sh;
4401         struct mlx5_devx_mkey_attr mkey_attr;
4402         struct mlx5_counter_stats_mem_mng *mem_mng;
4403         volatile struct flow_counter_stats *raw_data;
4404         int size = (sizeof(struct flow_counter_stats) *
4405                         MLX5_COUNTERS_PER_POOL +
4406                         sizeof(struct mlx5_counter_stats_raw)) * raws_n +
4407                         sizeof(struct mlx5_counter_stats_mem_mng);
4408         size_t pgsize = rte_mem_page_size();
4409         if (pgsize == (size_t)-1) {
4410                 DRV_LOG(ERR, "Failed to get mem page size");
4411                 rte_errno = ENOMEM;
4412                 return NULL;
4413         }
4414         uint8_t *mem = mlx5_malloc(MLX5_MEM_ZERO, size, pgsize,
4415                                   SOCKET_ID_ANY);
4416         int i;
4417
4418         if (!mem) {
4419                 rte_errno = ENOMEM;
4420                 return NULL;
4421         }
4422         mem_mng = (struct mlx5_counter_stats_mem_mng *)(mem + size) - 1;
4423         size = sizeof(*raw_data) * MLX5_COUNTERS_PER_POOL * raws_n;
4424         mem_mng->umem = mlx5_glue->devx_umem_reg(sh->ctx, mem, size,
4425                                                  IBV_ACCESS_LOCAL_WRITE);
4426         if (!mem_mng->umem) {
4427                 rte_errno = errno;
4428                 mlx5_free(mem);
4429                 return NULL;
4430         }
4431         mkey_attr.addr = (uintptr_t)mem;
4432         mkey_attr.size = size;
4433         mkey_attr.umem_id = mlx5_os_get_umem_id(mem_mng->umem);
4434         mkey_attr.pd = sh->pdn;
4435         mkey_attr.log_entity_size = 0;
4436         mkey_attr.pg_access = 0;
4437         mkey_attr.klm_array = NULL;
4438         mkey_attr.klm_num = 0;
4439         if (priv->config.hca_attr.relaxed_ordering_write &&
4440                 priv->config.hca_attr.relaxed_ordering_read  &&
4441                 !haswell_broadwell_cpu)
4442                 mkey_attr.relaxed_ordering = 1;
4443         mem_mng->dm = mlx5_devx_cmd_mkey_create(sh->ctx, &mkey_attr);
4444         if (!mem_mng->dm) {
4445                 mlx5_glue->devx_umem_dereg(mem_mng->umem);
4446                 rte_errno = errno;
4447                 mlx5_free(mem);
4448                 return NULL;
4449         }
4450         mem_mng->raws = (struct mlx5_counter_stats_raw *)(mem + size);
4451         raw_data = (volatile struct flow_counter_stats *)mem;
4452         for (i = 0; i < raws_n; ++i) {
4453                 mem_mng->raws[i].mem_mng = mem_mng;
4454                 mem_mng->raws[i].data = raw_data + i * MLX5_COUNTERS_PER_POOL;
4455         }
4456         LIST_INSERT_HEAD(&sh->cmng.mem_mngs, mem_mng, next);
4457         return mem_mng;
4458 }
4459
4460 /**
4461  * Resize a counter container.
4462  *
4463  * @param[in] dev
4464  *   Pointer to the Ethernet device structure.
4465  * @param[in] batch
4466  *   Whether the pool is for counter that was allocated by batch command.
4467  * @param[in] age
4468  *   Whether the pool is for Aging counter.
4469  *
4470  * @return
4471  *   0 on success, otherwise negative errno value and rte_errno is set.
4472  */
4473 static int
4474 flow_dv_container_resize(struct rte_eth_dev *dev,
4475                                 uint32_t batch, uint32_t age)
4476 {
4477         struct mlx5_priv *priv = dev->data->dev_private;
4478         struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4479                                                                age);
4480         struct mlx5_counter_stats_mem_mng *mem_mng = NULL;
4481         void *old_pools = cont->pools;
4482         uint32_t resize = cont->n + MLX5_CNT_CONTAINER_RESIZE;
4483         uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
4484         void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
4485
4486         if (!pools) {
4487                 rte_errno = ENOMEM;
4488                 return -ENOMEM;
4489         }
4490         if (old_pools)
4491                 memcpy(pools, old_pools, cont->n *
4492                                        sizeof(struct mlx5_flow_counter_pool *));
4493         /*
4494          * Fallback mode query the counter directly, no background query
4495          * resources are needed.
4496          */
4497         if (!priv->counter_fallback) {
4498                 int i;
4499
4500                 mem_mng = flow_dv_create_counter_stat_mem_mng(dev,
4501                           MLX5_CNT_CONTAINER_RESIZE + MLX5_MAX_PENDING_QUERIES);
4502                 if (!mem_mng) {
4503                         mlx5_free(pools);
4504                         return -ENOMEM;
4505                 }
4506                 for (i = 0; i < MLX5_MAX_PENDING_QUERIES; ++i)
4507                         LIST_INSERT_HEAD(&priv->sh->cmng.free_stat_raws,
4508                                          mem_mng->raws +
4509                                          MLX5_CNT_CONTAINER_RESIZE +
4510                                          i, next);
4511         }
4512         rte_spinlock_lock(&cont->resize_sl);
4513         cont->n = resize;
4514         cont->mem_mng = mem_mng;
4515         cont->pools = pools;
4516         rte_spinlock_unlock(&cont->resize_sl);
4517         if (old_pools)
4518                 mlx5_free(old_pools);
4519         return 0;
4520 }
4521
4522 /**
4523  * Query a devx flow counter.
4524  *
4525  * @param[in] dev
4526  *   Pointer to the Ethernet device structure.
4527  * @param[in] cnt
4528  *   Index to the flow counter.
4529  * @param[out] pkts
4530  *   The statistics value of packets.
4531  * @param[out] bytes
4532  *   The statistics value of bytes.
4533  *
4534  * @return
4535  *   0 on success, otherwise a negative errno value and rte_errno is set.
4536  */
4537 static inline int
4538 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
4539                      uint64_t *bytes)
4540 {
4541         struct mlx5_priv *priv = dev->data->dev_private;
4542         struct mlx5_flow_counter_pool *pool = NULL;
4543         struct mlx5_flow_counter *cnt;
4544         struct mlx5_flow_counter_ext *cnt_ext = NULL;
4545         int offset;
4546
4547         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
4548         MLX5_ASSERT(pool);
4549         if (counter < MLX5_CNT_BATCH_OFFSET) {
4550                 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt);
4551                 if (priv->counter_fallback)
4552                         return mlx5_devx_cmd_flow_counter_query(cnt_ext->dcs, 0,
4553                                         0, pkts, bytes, 0, NULL, NULL, 0);
4554         }
4555
4556         rte_spinlock_lock(&pool->sl);
4557         /*
4558          * The single counters allocation may allocate smaller ID than the
4559          * current allocated in parallel to the host reading.
4560          * In this case the new counter values must be reported as 0.
4561          */
4562         if (unlikely(cnt_ext && cnt_ext->dcs->id < pool->raw->min_dcs_id)) {
4563                 *pkts = 0;
4564                 *bytes = 0;
4565         } else {
4566                 offset = MLX5_CNT_ARRAY_IDX(pool, cnt);
4567                 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
4568                 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
4569         }
4570         rte_spinlock_unlock(&pool->sl);
4571         return 0;
4572 }
4573
4574 /**
4575  * Create and initialize a new counter pool.
4576  *
4577  * @param[in] dev
4578  *   Pointer to the Ethernet device structure.
4579  * @param[out] dcs
4580  *   The devX counter handle.
4581  * @param[in] batch
4582  *   Whether the pool is for counter that was allocated by batch command.
4583  * @param[in] age
4584  *   Whether the pool is for counter that was allocated for aging.
4585  * @param[in/out] cont_cur
4586  *   Pointer to the container pointer, it will be update in pool resize.
4587  *
4588  * @return
4589  *   The pool container pointer on success, NULL otherwise and rte_errno is set.
4590  */
4591 static struct mlx5_flow_counter_pool *
4592 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
4593                     uint32_t batch, uint32_t age)
4594 {
4595         struct mlx5_priv *priv = dev->data->dev_private;
4596         struct mlx5_flow_counter_pool *pool;
4597         struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4598                                                                age);
4599         int16_t n_valid = rte_atomic16_read(&cont->n_valid);
4600         uint32_t size = sizeof(*pool);
4601
4602         if (cont->n == n_valid && flow_dv_container_resize(dev, batch, age))
4603                 return NULL;
4604         size += MLX5_COUNTERS_PER_POOL * CNT_SIZE;
4605         size += (batch ? 0 : MLX5_COUNTERS_PER_POOL * CNTEXT_SIZE);
4606         size += (!age ? 0 : MLX5_COUNTERS_PER_POOL * AGE_SIZE);
4607         pool = mlx5_malloc(MLX5_MEM_ZERO, size, 0, SOCKET_ID_ANY);
4608         if (!pool) {
4609                 rte_errno = ENOMEM;
4610                 return NULL;
4611         }
4612         pool->min_dcs = dcs;
4613         if (!priv->counter_fallback)
4614                 pool->raw = cont->mem_mng->raws + n_valid %
4615                                                       MLX5_CNT_CONTAINER_RESIZE;
4616         pool->raw_hw = NULL;
4617         pool->type = 0;
4618         pool->type |= (batch ? 0 :  CNT_POOL_TYPE_EXT);
4619         pool->type |= (!age ? 0 :  CNT_POOL_TYPE_AGE);
4620         pool->query_gen = 0;
4621         rte_spinlock_init(&pool->sl);
4622         TAILQ_INIT(&pool->counters[0]);
4623         TAILQ_INIT(&pool->counters[1]);
4624         TAILQ_INSERT_HEAD(&cont->pool_list, pool, next);
4625         pool->index = n_valid;
4626         cont->pools[n_valid] = pool;
4627         if (!batch) {
4628                 int base = RTE_ALIGN_FLOOR(dcs->id, MLX5_COUNTERS_PER_POOL);
4629
4630                 if (base < cont->min_id)
4631                         cont->min_id = base;
4632                 if (base > cont->max_id)
4633                         cont->max_id = base + MLX5_COUNTERS_PER_POOL - 1;
4634                 cont->last_pool_idx = pool->index;
4635         }
4636         /* Pool initialization must be updated before host thread access. */
4637         rte_io_wmb();
4638         rte_atomic16_add(&cont->n_valid, 1);
4639         return pool;
4640 }
4641
4642 /**
4643  * Restore skipped counters in the pool.
4644  *
4645  * As counter pool query requires the first counter dcs
4646  * ID start with 4 alinged, if the pool counters with
4647  * min_dcs ID are not aligned with 4, the counters will
4648  * be skipped.
4649  * Once other min_dcs ID less than these skipped counter
4650  * dcs ID appears, the skipped counters will be safe to
4651  * use.
4652  * Should be called when min_dcs is updated.
4653  *
4654  * @param[in] pool
4655  *   Current counter pool.
4656  * @param[in] last_min_dcs
4657  *   Last min_dcs.
4658  */
4659 static void
4660 flow_dv_counter_restore(struct mlx5_flow_counter_pool *pool,
4661                         struct mlx5_devx_obj *last_min_dcs)
4662 {
4663         struct mlx5_flow_counter_ext *cnt_ext;
4664         uint32_t offset, new_offset;
4665         uint32_t skip_cnt = 0;
4666         uint32_t i;
4667
4668         if (!pool->skip_cnt)
4669                 return;
4670         /*
4671          * If last min_dcs is not valid. The skipped counter may even after
4672          * last min_dcs, set the offset to the whole pool.
4673          */
4674         if (last_min_dcs->id & (MLX5_CNT_BATCH_QUERY_ID_ALIGNMENT - 1))
4675                 offset = MLX5_COUNTERS_PER_POOL;
4676         else
4677                 offset = last_min_dcs->id % MLX5_COUNTERS_PER_POOL;
4678         new_offset = pool->min_dcs->id % MLX5_COUNTERS_PER_POOL;
4679         /*
4680          * Check the counters from 1 to the last_min_dcs range. Counters
4681          * before new min_dcs indicates pool still has skipped counters.
4682          * Counters be skipped after new min_dcs will be ready to use.
4683          * Offset 0 counter must be empty or min_dcs, start from 1.
4684          */
4685         for (i = 1; i < offset; i++) {
4686                 cnt_ext = MLX5_GET_POOL_CNT_EXT(pool, i);
4687                 if (cnt_ext->skipped) {
4688                         if (i > new_offset) {
4689                                 cnt_ext->skipped = 0;
4690                                 TAILQ_INSERT_TAIL
4691                                         (&pool->counters[pool->query_gen],
4692                                          MLX5_POOL_GET_CNT(pool, i), next);
4693                         } else {
4694                                 skip_cnt++;
4695                         }
4696                 }
4697         }
4698         if (!skip_cnt)
4699                 pool->skip_cnt = 0;
4700 }
4701
4702 /**
4703  * Prepare a new counter and/or a new counter pool.
4704  *
4705  * @param[in] dev
4706  *   Pointer to the Ethernet device structure.
4707  * @param[out] cnt_free
4708  *   Where to put the pointer of a new counter.
4709  * @param[in] batch
4710  *   Whether the pool is for counter that was allocated by batch command.
4711  * @param[in] age
4712  *   Whether the pool is for counter that was allocated for aging.
4713  *
4714  * @return
4715  *   The counter pool pointer and @p cnt_free is set on success,
4716  *   NULL otherwise and rte_errno is set.
4717  */
4718 static struct mlx5_flow_counter_pool *
4719 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
4720                              struct mlx5_flow_counter **cnt_free,
4721                              uint32_t batch, uint32_t age)
4722 {
4723         struct mlx5_priv *priv = dev->data->dev_private;
4724         struct mlx5_pools_container *cont;
4725         struct mlx5_flow_counter_pool *pool;
4726         struct mlx5_counters tmp_tq;
4727         struct mlx5_devx_obj *last_min_dcs;
4728         struct mlx5_devx_obj *dcs = NULL;
4729         struct mlx5_flow_counter *cnt;
4730         uint32_t add2other;
4731         uint32_t i;
4732
4733         cont = MLX5_CNT_CONTAINER(priv->sh, batch, age);
4734         if (!batch) {
4735 retry:
4736                 add2other = 0;
4737                 /* bulk_bitmap must be 0 for single counter allocation. */
4738                 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
4739                 if (!dcs)
4740                         return NULL;
4741                 pool = flow_dv_find_pool_by_id(cont, dcs->id);
4742                 /* Check if counter belongs to exist pool ID range. */
4743                 if (!pool) {
4744                         pool = flow_dv_find_pool_by_id
4745                                (MLX5_CNT_CONTAINER
4746                                (priv->sh, batch, (age ^ 0x1)), dcs->id);
4747                         /*
4748                          * Pool eixsts, counter will be added to the other
4749                          * container, need to reallocate it later.
4750                          */
4751                         if (pool) {
4752                                 add2other = 1;
4753                         } else {
4754                                 pool = flow_dv_pool_create(dev, dcs, batch,
4755                                                            age);
4756                                 if (!pool) {
4757                                         mlx5_devx_cmd_destroy(dcs);
4758                                         return NULL;
4759                                 }
4760                         }
4761                 }
4762                 if ((dcs->id < pool->min_dcs->id ||
4763                     pool->min_dcs->id &
4764                     (MLX5_CNT_BATCH_QUERY_ID_ALIGNMENT - 1)) &&
4765                     !(dcs->id & (MLX5_CNT_BATCH_QUERY_ID_ALIGNMENT - 1))) {
4766                         /*
4767                          * Update the pool min_dcs only if current dcs is
4768                          * valid and exist min_dcs is not valid or greater
4769                          * than new dcs.
4770                          */
4771                         last_min_dcs = pool->min_dcs;
4772                         rte_atomic64_set(&pool->a64_dcs,
4773                                          (int64_t)(uintptr_t)dcs);
4774                         /*
4775                          * Restore any skipped counters if the new min_dcs
4776                          * ID is smaller or min_dcs is not valid.
4777                          */
4778                         if (dcs->id < last_min_dcs->id ||
4779                             last_min_dcs->id &
4780                             (MLX5_CNT_BATCH_QUERY_ID_ALIGNMENT - 1))
4781                                 flow_dv_counter_restore(pool, last_min_dcs);
4782                 }
4783                 i = dcs->id % MLX5_COUNTERS_PER_POOL;
4784                 cnt = MLX5_POOL_GET_CNT(pool, i);
4785                 cnt->pool = pool;
4786                 MLX5_GET_POOL_CNT_EXT(pool, i)->dcs = dcs;
4787                 /*
4788                  * If min_dcs is not valid, it means the new allocated dcs
4789                  * also fail to become the valid min_dcs, just skip it.
4790                  * Or if min_dcs is valid, and new dcs ID is smaller than
4791                  * min_dcs, but not become the min_dcs, also skip it.
4792                  */
4793                 if (pool->min_dcs->id &
4794                     (MLX5_CNT_BATCH_QUERY_ID_ALIGNMENT - 1) ||
4795                     dcs->id < pool->min_dcs->id) {
4796                         MLX5_GET_POOL_CNT_EXT(pool, i)->skipped = 1;
4797                         pool->skip_cnt = 1;
4798                         goto retry;
4799                 }
4800                 if (add2other) {
4801                         TAILQ_INSERT_TAIL(&pool->counters[pool->query_gen],
4802                                           cnt, next);
4803                         goto retry;
4804                 }
4805                 *cnt_free = cnt;
4806                 return pool;
4807         }
4808         /* bulk_bitmap is in 128 counters units. */
4809         if (priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4)
4810                 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
4811         if (!dcs) {
4812                 rte_errno = ENODATA;
4813                 return NULL;
4814         }
4815         pool = flow_dv_pool_create(dev, dcs, batch, age);
4816         if (!pool) {
4817                 mlx5_devx_cmd_destroy(dcs);
4818                 return NULL;
4819         }
4820         TAILQ_INIT(&tmp_tq);
4821         for (i = 1; i < MLX5_COUNTERS_PER_POOL; ++i) {
4822                 cnt = MLX5_POOL_GET_CNT(pool, i);
4823                 cnt->pool = pool;
4824                 TAILQ_INSERT_HEAD(&tmp_tq, cnt, next);
4825         }
4826         rte_spinlock_lock(&cont->csl);
4827         TAILQ_CONCAT(&cont->counters, &tmp_tq, next);
4828         rte_spinlock_unlock(&cont->csl);
4829         *cnt_free = MLX5_POOL_GET_CNT(pool, 0);
4830         (*cnt_free)->pool = pool;
4831         return pool;
4832 }
4833
4834 /**
4835  * Search for existed shared counter.
4836  *
4837  * @param[in] dev
4838  *   Pointer to the Ethernet device structure.
4839  * @param[in] id
4840  *   The shared counter ID to search.
4841  * @param[out] ppool
4842  *   mlx5 flow counter pool in the container,
4843  *
4844  * @return
4845  *   NULL if not existed, otherwise pointer to the shared extend counter.
4846  */
4847 static struct mlx5_flow_counter_ext *
4848 flow_dv_counter_shared_search(struct rte_eth_dev *dev, uint32_t id,
4849                               struct mlx5_flow_counter_pool **ppool)
4850 {
4851         struct mlx5_priv *priv = dev->data->dev_private;
4852         union mlx5_l3t_data data;
4853         uint32_t cnt_idx;
4854
4855         if (mlx5_l3t_get_entry(priv->sh->cnt_id_tbl, id, &data) || !data.dword)
4856                 return NULL;
4857         cnt_idx = data.dword;
4858         /*
4859          * Shared counters don't have age info. The counter extend is after
4860          * the counter datat structure.
4861          */
4862         return (struct mlx5_flow_counter_ext *)
4863                ((flow_dv_counter_get_by_idx(dev, cnt_idx, ppool)) + 1);
4864 }
4865
4866 /**
4867  * Allocate a flow counter.
4868  *
4869  * @param[in] dev
4870  *   Pointer to the Ethernet device structure.
4871  * @param[in] shared
4872  *   Indicate if this counter is shared with other flows.
4873  * @param[in] id
4874  *   Counter identifier.
4875  * @param[in] group
4876  *   Counter flow group.
4877  * @param[in] age
4878  *   Whether the counter was allocated for aging.
4879  *
4880  * @return
4881  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
4882  */
4883 static uint32_t
4884 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t shared, uint32_t id,
4885                       uint16_t group, uint32_t age)
4886 {
4887         struct mlx5_priv *priv = dev->data->dev_private;
4888         struct mlx5_flow_counter_pool *pool = NULL;
4889         struct mlx5_flow_counter *cnt_free = NULL;
4890         struct mlx5_flow_counter_ext *cnt_ext = NULL;
4891         /*
4892          * Currently group 0 flow counter cannot be assigned to a flow if it is
4893          * not the first one in the batch counter allocation, so it is better
4894          * to allocate counters one by one for these flows in a separate
4895          * container.
4896          * A counter can be shared between different groups so need to take
4897          * shared counters from the single container.
4898          */
4899         uint32_t batch = (group && !shared && !priv->counter_fallback) ? 1 : 0;
4900         struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4901                                                                age);
4902         uint32_t cnt_idx;
4903
4904         if (!priv->config.devx) {
4905                 rte_errno = ENOTSUP;
4906                 return 0;
4907         }
4908         if (shared) {
4909                 cnt_ext = flow_dv_counter_shared_search(dev, id, &pool);
4910                 if (cnt_ext) {
4911                         if (cnt_ext->ref_cnt + 1 == 0) {
4912                                 rte_errno = E2BIG;
4913                                 return 0;
4914                         }
4915                         cnt_ext->ref_cnt++;
4916                         cnt_idx = pool->index * MLX5_COUNTERS_PER_POOL +
4917                                   (cnt_ext->dcs->id % MLX5_COUNTERS_PER_POOL)
4918                                   + 1;
4919                         return cnt_idx;
4920                 }
4921         }
4922         /* Get free counters from container. */
4923         rte_spinlock_lock(&cont->csl);
4924         cnt_free = TAILQ_FIRST(&cont->counters);
4925         if (cnt_free)
4926                 TAILQ_REMOVE(&cont->counters, cnt_free, next);
4927         rte_spinlock_unlock(&cont->csl);
4928         if (!cnt_free && !flow_dv_counter_pool_prepare(dev, &cnt_free,
4929                                                        batch, age))
4930                 goto err;
4931         pool = cnt_free->pool;
4932         if (!batch)
4933                 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt_free);
4934         /* Create a DV counter action only in the first time usage. */
4935         if (!cnt_free->action) {
4936                 uint16_t offset;
4937                 struct mlx5_devx_obj *dcs;
4938                 int ret;
4939
4940                 if (batch) {
4941                         offset = MLX5_CNT_ARRAY_IDX(pool, cnt_free);
4942                         dcs = pool->min_dcs;
4943                 } else {
4944                         offset = 0;
4945                         dcs = cnt_ext->dcs;
4946                 }
4947                 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, offset,
4948                                                             &cnt_free->action);
4949                 if (ret) {
4950                         rte_errno = errno;
4951                         goto err;
4952                 }
4953         }
4954         cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
4955                                 MLX5_CNT_ARRAY_IDX(pool, cnt_free));
4956         cnt_idx += batch * MLX5_CNT_BATCH_OFFSET;
4957         cnt_idx += age * MLX5_CNT_AGE_OFFSET;
4958         /* Update the counter reset values. */
4959         if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
4960                                  &cnt_free->bytes))
4961                 goto err;
4962         if (cnt_ext) {
4963                 cnt_ext->shared = shared;
4964                 cnt_ext->ref_cnt = 1;
4965                 cnt_ext->id = id;
4966                 if (shared) {
4967                         union mlx5_l3t_data data;
4968
4969                         data.dword = cnt_idx;
4970                         if (mlx5_l3t_set_entry(priv->sh->cnt_id_tbl, id, &data))
4971                                 return 0;
4972                 }
4973         }
4974         if (!priv->counter_fallback && !priv->sh->cmng.query_thread_on)
4975                 /* Start the asynchronous batch query by the host thread. */
4976                 mlx5_set_query_alarm(priv->sh);
4977         return cnt_idx;
4978 err:
4979         if (cnt_free) {
4980                 cnt_free->pool = pool;
4981                 rte_spinlock_lock(&cont->csl);
4982                 TAILQ_INSERT_TAIL(&cont->counters, cnt_free, next);
4983                 rte_spinlock_unlock(&cont->csl);
4984         }
4985         return 0;
4986 }
4987
4988 /**
4989  * Get age param from counter index.
4990  *
4991  * @param[in] dev
4992  *   Pointer to the Ethernet device structure.
4993  * @param[in] counter
4994  *   Index to the counter handler.
4995  *
4996  * @return
4997  *   The aging parameter specified for the counter index.
4998  */
4999 static struct mlx5_age_param*
5000 flow_dv_counter_idx_get_age(struct rte_eth_dev *dev,
5001                                 uint32_t counter)
5002 {
5003         struct mlx5_flow_counter *cnt;
5004         struct mlx5_flow_counter_pool *pool = NULL;
5005
5006         flow_dv_counter_get_by_idx(dev, counter, &pool);
5007         counter = (counter - 1) % MLX5_COUNTERS_PER_POOL;
5008         cnt = MLX5_POOL_GET_CNT(pool, counter);
5009         return MLX5_CNT_TO_AGE(cnt);
5010 }
5011
5012 /**
5013  * Remove a flow counter from aged counter list.
5014  *
5015  * @param[in] dev
5016  *   Pointer to the Ethernet device structure.
5017  * @param[in] counter
5018  *   Index to the counter handler.
5019  * @param[in] cnt
5020  *   Pointer to the counter handler.
5021  */
5022 static void
5023 flow_dv_counter_remove_from_age(struct rte_eth_dev *dev,
5024                                 uint32_t counter, struct mlx5_flow_counter *cnt)
5025 {
5026         struct mlx5_age_info *age_info;
5027         struct mlx5_age_param *age_param;
5028         struct mlx5_priv *priv = dev->data->dev_private;
5029
5030         age_info = GET_PORT_AGE_INFO(priv);
5031         age_param = flow_dv_counter_idx_get_age(dev, counter);
5032         if (rte_atomic16_cmpset((volatile uint16_t *)
5033                         &age_param->state,
5034                         AGE_CANDIDATE, AGE_FREE)
5035                         != AGE_CANDIDATE) {
5036                 /**
5037                  * We need the lock even it is age timeout,
5038                  * since counter may still in process.
5039                  */
5040                 rte_spinlock_lock(&age_info->aged_sl);
5041                 TAILQ_REMOVE(&age_info->aged_counters, cnt, next);
5042                 rte_spinlock_unlock(&age_info->aged_sl);
5043         }
5044         rte_atomic16_set(&age_param->state, AGE_FREE);
5045 }
5046 /**
5047  * Release a flow counter.
5048  *
5049  * @param[in] dev
5050  *   Pointer to the Ethernet device structure.
5051  * @param[in] counter
5052  *   Index to the counter handler.
5053  */
5054 static void
5055 flow_dv_counter_release(struct rte_eth_dev *dev, uint32_t counter)
5056 {
5057         struct mlx5_priv *priv = dev->data->dev_private;
5058         struct mlx5_flow_counter_pool *pool = NULL;
5059         struct mlx5_flow_counter *cnt;
5060         struct mlx5_flow_counter_ext *cnt_ext = NULL;
5061
5062         if (!counter)
5063                 return;
5064         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
5065         MLX5_ASSERT(pool);
5066         if (counter < MLX5_CNT_BATCH_OFFSET) {
5067                 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt);
5068                 if (cnt_ext) {
5069                         if (--cnt_ext->ref_cnt)
5070                                 return;
5071                         if (cnt_ext->shared)
5072                                 mlx5_l3t_clear_entry(priv->sh->cnt_id_tbl,
5073                                                      cnt_ext->id);
5074                 }
5075         }
5076         if (IS_AGE_POOL(pool))
5077                 flow_dv_counter_remove_from_age(dev, counter, cnt);
5078         cnt->pool = pool;
5079         /*
5080          * Put the counter back to list to be updated in none fallback mode.
5081          * Currently, we are using two list alternately, while one is in query,
5082          * add the freed counter to the other list based on the pool query_gen
5083          * value. After query finishes, add counter the list to the global
5084          * container counter list. The list changes while query starts. In
5085          * this case, lock will not be needed as query callback and release
5086          * function both operate with the different list.
5087          *
5088          */
5089         if (!priv->counter_fallback)
5090                 TAILQ_INSERT_TAIL(&pool->counters[pool->query_gen], cnt, next);
5091         else
5092                 TAILQ_INSERT_TAIL(&((MLX5_CNT_CONTAINER
5093                                   (priv->sh, 0, 0))->counters),
5094                                   cnt, next);
5095 }
5096
5097 /**
5098  * Verify the @p attributes will be correctly understood by the NIC and store
5099  * them in the @p flow if everything is correct.
5100  *
5101  * @param[in] dev
5102  *   Pointer to dev struct.
5103  * @param[in] attributes
5104  *   Pointer to flow attributes
5105  * @param[in] external
5106  *   This flow rule is created by request external to PMD.
5107  * @param[out] error
5108  *   Pointer to error structure.
5109  *
5110  * @return
5111  *   - 0 on success and non root table.
5112  *   - 1 on success and root table.
5113  *   - a negative errno value otherwise and rte_errno is set.
5114  */
5115 static int
5116 flow_dv_validate_attributes(struct rte_eth_dev *dev,
5117                             const struct rte_flow_attr *attributes,
5118                             bool external __rte_unused,
5119                             struct rte_flow_error *error)
5120 {
5121         struct mlx5_priv *priv = dev->data->dev_private;
5122         uint32_t priority_max = priv->config.flow_prio - 1;
5123         int ret = 0;
5124
5125 #ifndef HAVE_MLX5DV_DR
5126         if (attributes->group)
5127                 return rte_flow_error_set(error, ENOTSUP,
5128                                           RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
5129                                           NULL,
5130                                           "groups are not supported");
5131 #else
5132         uint32_t table = 0;
5133
5134         ret = mlx5_flow_group_to_table(attributes, external,
5135                                        attributes->group, !!priv->fdb_def_rule,
5136                                        &table, error);
5137         if (ret)
5138                 return ret;
5139         if (!table)
5140                 ret = MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
5141 #endif
5142         if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
5143             attributes->priority >= priority_max)
5144                 return rte_flow_error_set(error, ENOTSUP,
5145                                           RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
5146                                           NULL,
5147                                           "priority out of range");
5148         if (attributes->transfer) {
5149                 if (!priv->config.dv_esw_en)
5150                         return rte_flow_error_set
5151                                 (error, ENOTSUP,
5152                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5153                                  "E-Switch dr is not supported");
5154                 if (!(priv->representor || priv->master))
5155                         return rte_flow_error_set
5156                                 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5157                                  NULL, "E-Switch configuration can only be"
5158                                  " done by a master or a representor device");
5159                 if (attributes->egress)
5160                         return rte_flow_error_set
5161                                 (error, ENOTSUP,
5162                                  RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
5163                                  "egress is not supported");
5164         }
5165         if (!(attributes->egress ^ attributes->ingress))
5166                 return rte_flow_error_set(error, ENOTSUP,
5167                                           RTE_FLOW_ERROR_TYPE_ATTR, NULL,
5168                                           "must specify exactly one of "
5169                                           "ingress or egress");
5170         return ret;
5171 }
5172
5173 /**
5174  * Internal validation function. For validating both actions and items.
5175  *
5176  * @param[in] dev
5177  *   Pointer to the rte_eth_dev structure.
5178  * @param[in] attr
5179  *   Pointer to the flow attributes.
5180  * @param[in] items
5181  *   Pointer to the list of items.
5182  * @param[in] actions
5183  *   Pointer to the list of actions.
5184  * @param[in] external
5185  *   This flow rule is created by request external to PMD.
5186  * @param[in] hairpin
5187  *   Number of hairpin TX actions, 0 means classic flow.
5188  * @param[out] error
5189  *   Pointer to the error structure.
5190  *
5191  * @return
5192  *   0 on success, a negative errno value otherwise and rte_errno is set.
5193  */
5194 static int
5195 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
5196                  const struct rte_flow_item items[],
5197                  const struct rte_flow_action actions[],
5198                  bool external, int hairpin, struct rte_flow_error *error)
5199 {
5200         int ret;
5201         uint64_t action_flags = 0;
5202         uint64_t item_flags = 0;
5203         uint64_t last_item = 0;
5204         uint8_t next_protocol = 0xff;
5205         uint16_t ether_type = 0;
5206         int actions_n = 0;
5207         uint8_t item_ipv6_proto = 0;
5208         const struct rte_flow_item *gre_item = NULL;
5209         const struct rte_flow_action_raw_decap *decap;
5210         const struct rte_flow_action_raw_encap *encap;
5211         const struct rte_flow_action_rss *rss;
5212         const struct rte_flow_item_tcp nic_tcp_mask = {
5213                 .hdr = {
5214                         .tcp_flags = 0xFF,
5215                         .src_port = RTE_BE16(UINT16_MAX),
5216                         .dst_port = RTE_BE16(UINT16_MAX),
5217                 }
5218         };
5219         const struct rte_flow_item_ipv4 nic_ipv4_mask = {
5220                 .hdr = {
5221                         .src_addr = RTE_BE32(0xffffffff),
5222                         .dst_addr = RTE_BE32(0xffffffff),
5223                         .type_of_service = 0xff,
5224                         .next_proto_id = 0xff,
5225                         .time_to_live = 0xff,
5226                 },
5227         };
5228         const struct rte_flow_item_ipv6 nic_ipv6_mask = {
5229                 .hdr = {
5230                         .src_addr =
5231                         "\xff\xff\xff\xff\xff\xff\xff\xff"
5232                         "\xff\xff\xff\xff\xff\xff\xff\xff",
5233                         .dst_addr =
5234                         "\xff\xff\xff\xff\xff\xff\xff\xff"
5235                         "\xff\xff\xff\xff\xff\xff\xff\xff",
5236                         .vtc_flow = RTE_BE32(0xffffffff),
5237                         .proto = 0xff,
5238                         .hop_limits = 0xff,
5239                 },
5240         };
5241         const struct rte_flow_item_ecpri nic_ecpri_mask = {
5242                 .hdr = {
5243                         .common = {
5244                                 .u32 =
5245                                 RTE_BE32(((const struct rte_ecpri_common_hdr) {
5246                                         .type = 0xFF,
5247                                         }).u32),
5248                         },
5249                         .dummy[0] = 0xffffffff,
5250                 },
5251         };
5252         struct mlx5_priv *priv = dev->data->dev_private;
5253         struct mlx5_dev_config *dev_conf = &priv->config;
5254         uint16_t queue_index = 0xFFFF;
5255         const struct rte_flow_item_vlan *vlan_m = NULL;
5256         int16_t rw_act_num = 0;
5257         uint64_t is_root;
5258
5259         if (items == NULL)
5260                 return -1;
5261         ret = flow_dv_validate_attributes(dev, attr, external, error);
5262         if (ret < 0)
5263                 return ret;
5264         is_root = (uint64_t)ret;
5265         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
5266                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
5267                 int type = items->type;
5268
5269                 if (!mlx5_flow_os_item_supported(type))
5270                         return rte_flow_error_set(error, ENOTSUP,
5271                                                   RTE_FLOW_ERROR_TYPE_ITEM,
5272                                                   NULL, "item not supported");
5273                 switch (type) {
5274                 case RTE_FLOW_ITEM_TYPE_VOID:
5275                         break;
5276                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
5277                         ret = flow_dv_validate_item_port_id
5278                                         (dev, items, attr, item_flags, error);
5279                         if (ret < 0)
5280                                 return ret;
5281                         last_item = MLX5_FLOW_ITEM_PORT_ID;
5282                         break;
5283                 case RTE_FLOW_ITEM_TYPE_ETH:
5284                         ret = mlx5_flow_validate_item_eth(items, item_flags,
5285                                                           error);
5286                         if (ret < 0)
5287                                 return ret;
5288                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
5289                                              MLX5_FLOW_LAYER_OUTER_L2;
5290                         if (items->mask != NULL && items->spec != NULL) {
5291                                 ether_type =
5292                                         ((const struct rte_flow_item_eth *)
5293                                          items->spec)->type;
5294                                 ether_type &=
5295                                         ((const struct rte_flow_item_eth *)
5296                                          items->mask)->type;
5297                                 ether_type = rte_be_to_cpu_16(ether_type);
5298                         } else {
5299                                 ether_type = 0;
5300                         }
5301                         break;
5302                 case RTE_FLOW_ITEM_TYPE_VLAN:
5303                         ret = flow_dv_validate_item_vlan(items, item_flags,
5304                                                          dev, error);
5305                         if (ret < 0)
5306                                 return ret;
5307                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
5308                                              MLX5_FLOW_LAYER_OUTER_VLAN;
5309                         if (items->mask != NULL && items->spec != NULL) {
5310                                 ether_type =
5311                                         ((const struct rte_flow_item_vlan *)
5312                                          items->spec)->inner_type;
5313                                 ether_type &=
5314                                         ((const struct rte_flow_item_vlan *)
5315                                          items->mask)->inner_type;
5316                                 ether_type = rte_be_to_cpu_16(ether_type);
5317                         } else {
5318                                 ether_type = 0;
5319                         }
5320                         /* Store outer VLAN mask for of_push_vlan action. */
5321                         if (!tunnel)
5322                                 vlan_m = items->mask;
5323                         break;
5324                 case RTE_FLOW_ITEM_TYPE_IPV4:
5325                         mlx5_flow_tunnel_ip_check(items, next_protocol,
5326                                                   &item_flags, &tunnel);
5327                         ret = mlx5_flow_validate_item_ipv4(items, item_flags,
5328                                                            last_item,
5329                                                            ether_type,
5330                                                            &nic_ipv4_mask,
5331                                                            error);
5332                         if (ret < 0)
5333                                 return ret;
5334                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
5335                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
5336                         if (items->mask != NULL &&
5337                             ((const struct rte_flow_item_ipv4 *)
5338                              items->mask)->hdr.next_proto_id) {
5339                                 next_protocol =
5340                                         ((const struct rte_flow_item_ipv4 *)
5341                                          (items->spec))->hdr.next_proto_id;
5342                                 next_protocol &=
5343                                         ((const struct rte_flow_item_ipv4 *)
5344                                          (items->mask))->hdr.next_proto_id;
5345                         } else {
5346                                 /* Reset for inner layer. */
5347                                 next_protocol = 0xff;
5348                         }
5349                         break;
5350                 case RTE_FLOW_ITEM_TYPE_IPV6:
5351                         mlx5_flow_tunnel_ip_check(items, next_protocol,
5352                                                   &item_flags, &tunnel);
5353                         ret = mlx5_flow_validate_item_ipv6(items, item_flags,
5354                                                            last_item,
5355                                                            ether_type,
5356                                                            &nic_ipv6_mask,
5357                                                            error);
5358                         if (ret < 0)
5359                                 return ret;
5360                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
5361                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
5362                         if (items->mask != NULL &&
5363                             ((const struct rte_flow_item_ipv6 *)
5364                              items->mask)->hdr.proto) {
5365                                 item_ipv6_proto =
5366                                         ((const struct rte_flow_item_ipv6 *)
5367                                          items->spec)->hdr.proto;
5368                                 next_protocol =
5369                                         ((const struct rte_flow_item_ipv6 *)
5370                                          items->spec)->hdr.proto;
5371                                 next_protocol &=
5372                                         ((const struct rte_flow_item_ipv6 *)
5373                                          items->mask)->hdr.proto;
5374                         } else {
5375                                 /* Reset for inner layer. */
5376                                 next_protocol = 0xff;
5377                         }
5378                         break;
5379                 case RTE_FLOW_ITEM_TYPE_TCP:
5380                         ret = mlx5_flow_validate_item_tcp
5381                                                 (items, item_flags,
5382                                                  next_protocol,
5383                                                  &nic_tcp_mask,
5384                                                  error);
5385                         if (ret < 0)
5386                                 return ret;
5387                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
5388                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
5389                         break;
5390                 case RTE_FLOW_ITEM_TYPE_UDP:
5391                         ret = mlx5_flow_validate_item_udp(items, item_flags,
5392                                                           next_protocol,
5393                                                           error);
5394                         if (ret < 0)
5395                                 return ret;
5396                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
5397                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
5398                         break;
5399                 case RTE_FLOW_ITEM_TYPE_GRE:
5400                         ret = mlx5_flow_validate_item_gre(items, item_flags,
5401                                                           next_protocol, error);
5402                         if (ret < 0)
5403                                 return ret;
5404                         gre_item = items;
5405                         last_item = MLX5_FLOW_LAYER_GRE;
5406                         break;
5407                 case RTE_FLOW_ITEM_TYPE_NVGRE:
5408                         ret = mlx5_flow_validate_item_nvgre(items, item_flags,
5409                                                             next_protocol,
5410                                                             error);
5411                         if (ret < 0)
5412                                 return ret;
5413                         last_item = MLX5_FLOW_LAYER_NVGRE;
5414                         break;
5415                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
5416                         ret = mlx5_flow_validate_item_gre_key
5417                                 (items, item_flags, gre_item, error);
5418                         if (ret < 0)
5419                                 return ret;
5420                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
5421                         break;
5422                 case RTE_FLOW_ITEM_TYPE_VXLAN:
5423                         ret = mlx5_flow_validate_item_vxlan(items, item_flags,
5424                                                             error);
5425                         if (ret < 0)
5426                                 return ret;
5427                         last_item = MLX5_FLOW_LAYER_VXLAN;
5428                         break;
5429                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
5430                         ret = mlx5_flow_validate_item_vxlan_gpe(items,
5431                                                                 item_flags, dev,
5432                                                                 error);
5433                         if (ret < 0)
5434                                 return ret;
5435                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
5436                         break;
5437                 case RTE_FLOW_ITEM_TYPE_GENEVE:
5438                         ret = mlx5_flow_validate_item_geneve(items,
5439                                                              item_flags, dev,
5440                                                              error);
5441                         if (ret < 0)
5442                                 return ret;
5443                         last_item = MLX5_FLOW_LAYER_GENEVE;
5444                         break;
5445                 case RTE_FLOW_ITEM_TYPE_MPLS:
5446                         ret = mlx5_flow_validate_item_mpls(dev, items,
5447                                                            item_flags,
5448                                                            last_item, error);
5449                         if (ret < 0)
5450                                 return ret;
5451                         last_item = MLX5_FLOW_LAYER_MPLS;
5452                         break;
5453
5454                 case RTE_FLOW_ITEM_TYPE_MARK:
5455                         ret = flow_dv_validate_item_mark(dev, items, attr,
5456                                                          error);
5457                         if (ret < 0)
5458                                 return ret;
5459                         last_item = MLX5_FLOW_ITEM_MARK;
5460                         break;
5461                 case RTE_FLOW_ITEM_TYPE_META:
5462                         ret = flow_dv_validate_item_meta(dev, items, attr,
5463                                                          error);
5464                         if (ret < 0)
5465                                 return ret;
5466                         last_item = MLX5_FLOW_ITEM_METADATA;
5467                         break;
5468                 case RTE_FLOW_ITEM_TYPE_ICMP:
5469                         ret = mlx5_flow_validate_item_icmp(items, item_flags,
5470                                                            next_protocol,
5471                                                            error);
5472                         if (ret < 0)
5473                                 return ret;
5474                         last_item = MLX5_FLOW_LAYER_ICMP;
5475                         break;
5476                 case RTE_FLOW_ITEM_TYPE_ICMP6:
5477                         ret = mlx5_flow_validate_item_icmp6(items, item_flags,
5478                                                             next_protocol,
5479                                                             error);
5480                         if (ret < 0)
5481                                 return ret;
5482                         item_ipv6_proto = IPPROTO_ICMPV6;
5483                         last_item = MLX5_FLOW_LAYER_ICMP6;
5484                         break;
5485                 case RTE_FLOW_ITEM_TYPE_TAG:
5486                         ret = flow_dv_validate_item_tag(dev, items,
5487                                                         attr, error);
5488                         if (ret < 0)
5489                                 return ret;
5490                         last_item = MLX5_FLOW_ITEM_TAG;
5491                         break;
5492                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
5493                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
5494                         break;
5495                 case RTE_FLOW_ITEM_TYPE_GTP:
5496                         ret = flow_dv_validate_item_gtp(dev, items, item_flags,
5497                                                         error);
5498                         if (ret < 0)
5499                                 return ret;
5500                         last_item = MLX5_FLOW_LAYER_GTP;
5501                         break;
5502                 case RTE_FLOW_ITEM_TYPE_ECPRI:
5503                         /* Capacity will be checked in the translate stage. */
5504                         ret = mlx5_flow_validate_item_ecpri(items, item_flags,
5505                                                             last_item,
5506                                                             ether_type,
5507                                                             &nic_ecpri_mask,
5508                                                             error);
5509                         if (ret < 0)
5510                                 return ret;
5511                         last_item = MLX5_FLOW_LAYER_ECPRI;
5512                         break;
5513                 default:
5514                         return rte_flow_error_set(error, ENOTSUP,
5515                                                   RTE_FLOW_ERROR_TYPE_ITEM,
5516                                                   NULL, "item not supported");
5517                 }
5518                 item_flags |= last_item;
5519         }
5520         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
5521                 int type = actions->type;
5522
5523                 if (!mlx5_flow_os_action_supported(type))
5524                         return rte_flow_error_set(error, ENOTSUP,
5525                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5526                                                   actions,
5527                                                   "action not supported");
5528                 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
5529                         return rte_flow_error_set(error, ENOTSUP,
5530                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5531                                                   actions, "too many actions");
5532                 switch (type) {
5533                 case RTE_FLOW_ACTION_TYPE_VOID:
5534                         break;
5535                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5536                         ret = flow_dv_validate_action_port_id(dev,
5537                                                               action_flags,
5538                                                               actions,
5539                                                               attr,
5540                                                               error);
5541                         if (ret)
5542                                 return ret;
5543                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5544                         ++actions_n;
5545                         break;
5546                 case RTE_FLOW_ACTION_TYPE_FLAG:
5547                         ret = flow_dv_validate_action_flag(dev, action_flags,
5548                                                            attr, error);
5549                         if (ret < 0)
5550                                 return ret;
5551                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
5552                                 /* Count all modify-header actions as one. */
5553                                 if (!(action_flags &
5554                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
5555                                         ++actions_n;
5556                                 action_flags |= MLX5_FLOW_ACTION_FLAG |
5557                                                 MLX5_FLOW_ACTION_MARK_EXT;
5558                         } else {
5559                                 action_flags |= MLX5_FLOW_ACTION_FLAG;
5560                                 ++actions_n;
5561                         }
5562                         rw_act_num += MLX5_ACT_NUM_SET_MARK;
5563                         break;
5564                 case RTE_FLOW_ACTION_TYPE_MARK:
5565                         ret = flow_dv_validate_action_mark(dev, actions,
5566                                                            action_flags,
5567                                                            attr, error);
5568                         if (ret < 0)
5569                                 return ret;
5570                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
5571                                 /* Count all modify-header actions as one. */
5572                                 if (!(action_flags &
5573                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
5574                                         ++actions_n;
5575                                 action_flags |= MLX5_FLOW_ACTION_MARK |
5576                                                 MLX5_FLOW_ACTION_MARK_EXT;
5577                         } else {
5578                                 action_flags |= MLX5_FLOW_ACTION_MARK;
5579                                 ++actions_n;
5580                         }
5581                         rw_act_num += MLX5_ACT_NUM_SET_MARK;
5582                         break;
5583                 case RTE_FLOW_ACTION_TYPE_SET_META:
5584                         ret = flow_dv_validate_action_set_meta(dev, actions,
5585                                                                action_flags,
5586                                                                attr, error);
5587                         if (ret < 0)
5588                                 return ret;
5589                         /* Count all modify-header actions as one action. */
5590                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5591                                 ++actions_n;
5592                         action_flags |= MLX5_FLOW_ACTION_SET_META;
5593                         rw_act_num += MLX5_ACT_NUM_SET_META;
5594                         break;
5595                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
5596                         ret = flow_dv_validate_action_set_tag(dev, actions,
5597                                                               action_flags,
5598                                                               attr, error);
5599                         if (ret < 0)
5600                                 return ret;
5601                         /* Count all modify-header actions as one action. */
5602                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5603                                 ++actions_n;
5604                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
5605                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
5606                         break;
5607                 case RTE_FLOW_ACTION_TYPE_DROP:
5608                         ret = mlx5_flow_validate_action_drop(action_flags,
5609                                                              attr, error);
5610                         if (ret < 0)
5611                                 return ret;
5612                         action_flags |= MLX5_FLOW_ACTION_DROP;
5613                         ++actions_n;
5614                         break;
5615                 case RTE_FLOW_ACTION_TYPE_QUEUE:
5616                         ret = mlx5_flow_validate_action_queue(actions,
5617                                                               action_flags, dev,
5618                                                               attr, error);
5619                         if (ret < 0)
5620                                 return ret;
5621                         queue_index = ((const struct rte_flow_action_queue *)
5622                                                         (actions->conf))->index;
5623                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
5624                         ++actions_n;
5625                         break;
5626                 case RTE_FLOW_ACTION_TYPE_RSS:
5627                         rss = actions->conf;
5628                         ret = mlx5_flow_validate_action_rss(actions,
5629                                                             action_flags, dev,
5630                                                             attr, item_flags,
5631                                                             error);
5632                         if (ret < 0)
5633                                 return ret;
5634                         if (rss != NULL && rss->queue_num)
5635                                 queue_index = rss->queue[0];
5636                         action_flags |= MLX5_FLOW_ACTION_RSS;
5637                         ++actions_n;
5638                         break;
5639                 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
5640                         ret =
5641                         mlx5_flow_validate_action_default_miss(action_flags,
5642                                         attr, error);
5643                         if (ret < 0)
5644                                 return ret;
5645                         action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
5646                         ++actions_n;
5647                         break;
5648                 case RTE_FLOW_ACTION_TYPE_COUNT:
5649                         ret = flow_dv_validate_action_count(dev, error);
5650                         if (ret < 0)
5651                                 return ret;
5652                         action_flags |= MLX5_FLOW_ACTION_COUNT;
5653                         ++actions_n;
5654                         break;
5655                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
5656                         if (flow_dv_validate_action_pop_vlan(dev,
5657                                                              action_flags,
5658                                                              actions,
5659                                                              item_flags, attr,
5660                                                              error))
5661                                 return -rte_errno;
5662                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
5663                         ++actions_n;
5664                         break;
5665                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
5666                         ret = flow_dv_validate_action_push_vlan(dev,
5667                                                                 action_flags,
5668                                                                 vlan_m,
5669                                                                 actions, attr,
5670                                                                 error);
5671                         if (ret < 0)
5672                                 return ret;
5673                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
5674                         ++actions_n;
5675                         break;
5676                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
5677                         ret = flow_dv_validate_action_set_vlan_pcp
5678                                                 (action_flags, actions, error);
5679                         if (ret < 0)
5680                                 return ret;
5681                         /* Count PCP with push_vlan command. */
5682                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
5683                         break;
5684                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
5685                         ret = flow_dv_validate_action_set_vlan_vid
5686                                                 (item_flags, action_flags,
5687                                                  actions, error);
5688                         if (ret < 0)
5689                                 return ret;
5690                         /* Count VID with push_vlan command. */
5691                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
5692                         rw_act_num += MLX5_ACT_NUM_MDF_VID;
5693                         break;
5694                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5695                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5696                         ret = flow_dv_validate_action_l2_encap(dev,
5697                                                                action_flags,
5698                                                                actions, attr,
5699                                                                error);
5700                         if (ret < 0)
5701                                 return ret;
5702                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
5703                         ++actions_n;
5704                         break;
5705                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
5706                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
5707                         ret = flow_dv_validate_action_decap(dev, action_flags,
5708                                                             attr, error);
5709                         if (ret < 0)
5710                                 return ret;
5711                         action_flags |= MLX5_FLOW_ACTION_DECAP;
5712                         ++actions_n;
5713                         break;
5714                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5715                         ret = flow_dv_validate_action_raw_encap_decap
5716                                 (dev, NULL, actions->conf, attr, &action_flags,
5717                                  &actions_n, error);
5718                         if (ret < 0)
5719                                 return ret;
5720                         break;
5721                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
5722                         decap = actions->conf;
5723                         while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
5724                                 ;
5725                         if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
5726                                 encap = NULL;
5727                                 actions--;
5728                         } else {
5729                                 encap = actions->conf;
5730                         }
5731                         ret = flow_dv_validate_action_raw_encap_decap
5732                                            (dev,
5733                                             decap ? decap : &empty_decap, encap,
5734                                             attr, &action_flags, &actions_n,
5735                                             error);
5736                         if (ret < 0)
5737                                 return ret;
5738                         break;
5739                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
5740                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
5741                         ret = flow_dv_validate_action_modify_mac(action_flags,
5742                                                                  actions,
5743                                                                  item_flags,
5744                                                                  error);
5745                         if (ret < 0)
5746                                 return ret;
5747                         /* Count all modify-header actions as one action. */
5748                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5749                                 ++actions_n;
5750                         action_flags |= actions->type ==
5751                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
5752                                                 MLX5_FLOW_ACTION_SET_MAC_SRC :
5753                                                 MLX5_FLOW_ACTION_SET_MAC_DST;
5754                         /*
5755                          * Even if the source and destination MAC addresses have
5756                          * overlap in the header with 4B alignment, the convert
5757                          * function will handle them separately and 4 SW actions
5758                          * will be created. And 2 actions will be added each
5759                          * time no matter how many bytes of address will be set.
5760                          */
5761                         rw_act_num += MLX5_ACT_NUM_MDF_MAC;
5762                         break;
5763                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
5764                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
5765                         ret = flow_dv_validate_action_modify_ipv4(action_flags,
5766                                                                   actions,
5767                                                                   item_flags,
5768                                                                   error);
5769                         if (ret < 0)
5770                                 return ret;
5771                         /* Count all modify-header actions as one action. */
5772                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5773                                 ++actions_n;
5774                         action_flags |= actions->type ==
5775                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
5776                                                 MLX5_FLOW_ACTION_SET_IPV4_SRC :
5777                                                 MLX5_FLOW_ACTION_SET_IPV4_DST;
5778                         rw_act_num += MLX5_ACT_NUM_MDF_IPV4;
5779                         break;
5780                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
5781                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
5782                         ret = flow_dv_validate_action_modify_ipv6(action_flags,
5783                                                                   actions,
5784                                                                   item_flags,
5785                                                                   error);
5786                         if (ret < 0)
5787                                 return ret;
5788                         if (item_ipv6_proto == IPPROTO_ICMPV6)
5789                                 return rte_flow_error_set(error, ENOTSUP,
5790                                         RTE_FLOW_ERROR_TYPE_ACTION,
5791                                         actions,
5792                                         "Can't change header "
5793                                         "with ICMPv6 proto");
5794                         /* Count all modify-header actions as one action. */
5795                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5796                                 ++actions_n;
5797                         action_flags |= actions->type ==
5798                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
5799                                                 MLX5_FLOW_ACTION_SET_IPV6_SRC :
5800                                                 MLX5_FLOW_ACTION_SET_IPV6_DST;
5801                         rw_act_num += MLX5_ACT_NUM_MDF_IPV6;
5802                         break;
5803                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
5804                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
5805                         ret = flow_dv_validate_action_modify_tp(action_flags,
5806                                                                 actions,
5807                                                                 item_flags,
5808                                                                 error);
5809                         if (ret < 0)
5810                                 return ret;
5811                         /* Count all modify-header actions as one action. */
5812                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5813                                 ++actions_n;
5814                         action_flags |= actions->type ==
5815                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
5816                                                 MLX5_FLOW_ACTION_SET_TP_SRC :
5817                                                 MLX5_FLOW_ACTION_SET_TP_DST;
5818                         rw_act_num += MLX5_ACT_NUM_MDF_PORT;
5819                         break;
5820                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
5821                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
5822                         ret = flow_dv_validate_action_modify_ttl(action_flags,
5823                                                                  actions,
5824                                                                  item_flags,
5825                                                                  error);
5826                         if (ret < 0)
5827                                 return ret;
5828                         /* Count all modify-header actions as one action. */
5829                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5830                                 ++actions_n;
5831                         action_flags |= actions->type ==
5832                                         RTE_FLOW_ACTION_TYPE_SET_TTL ?
5833                                                 MLX5_FLOW_ACTION_SET_TTL :
5834                                                 MLX5_FLOW_ACTION_DEC_TTL;
5835                         rw_act_num += MLX5_ACT_NUM_MDF_TTL;
5836                         break;
5837                 case RTE_FLOW_ACTION_TYPE_JUMP:
5838                         ret = flow_dv_validate_action_jump(actions,
5839                                                            action_flags,
5840                                                            attr, external,
5841                                                            error);
5842                         if (ret)
5843                                 return ret;
5844                         ++actions_n;
5845                         action_flags |= MLX5_FLOW_ACTION_JUMP;
5846                         break;
5847                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
5848                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
5849                         ret = flow_dv_validate_action_modify_tcp_seq
5850                                                                 (action_flags,
5851                                                                  actions,
5852                                                                  item_flags,
5853                                                                  error);
5854                         if (ret < 0)
5855                                 return ret;
5856                         /* Count all modify-header actions as one action. */
5857                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5858                                 ++actions_n;
5859                         action_flags |= actions->type ==
5860                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
5861                                                 MLX5_FLOW_ACTION_INC_TCP_SEQ :
5862                                                 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
5863                         rw_act_num += MLX5_ACT_NUM_MDF_TCPSEQ;
5864                         break;
5865                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
5866                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
5867                         ret = flow_dv_validate_action_modify_tcp_ack
5868                                                                 (action_flags,
5869                                                                  actions,
5870                                                                  item_flags,
5871                                                                  error);
5872                         if (ret < 0)
5873                                 return ret;
5874                         /* Count all modify-header actions as one action. */
5875                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5876                                 ++actions_n;
5877                         action_flags |= actions->type ==
5878                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
5879                                                 MLX5_FLOW_ACTION_INC_TCP_ACK :
5880                                                 MLX5_FLOW_ACTION_DEC_TCP_ACK;
5881                         rw_act_num += MLX5_ACT_NUM_MDF_TCPACK;
5882                         break;
5883                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
5884                         break;
5885                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
5886                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
5887                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
5888                         break;
5889                 case RTE_FLOW_ACTION_TYPE_METER:
5890                         ret = mlx5_flow_validate_action_meter(dev,
5891                                                               action_flags,
5892                                                               actions, attr,
5893                                                               error);
5894                         if (ret < 0)
5895                                 return ret;
5896                         action_flags |= MLX5_FLOW_ACTION_METER;
5897                         ++actions_n;
5898                         /* Meter action will add one more TAG action. */
5899                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
5900                         break;
5901                 case RTE_FLOW_ACTION_TYPE_AGE:
5902                         ret = flow_dv_validate_action_age(action_flags,
5903                                                           actions, dev,
5904                                                           error);
5905                         if (ret < 0)
5906                                 return ret;
5907                         action_flags |= MLX5_FLOW_ACTION_AGE;
5908                         ++actions_n;
5909                         break;
5910                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
5911                         ret = flow_dv_validate_action_modify_ipv4_dscp
5912                                                          (action_flags,
5913                                                           actions,
5914                                                           item_flags,
5915                                                           error);
5916                         if (ret < 0)
5917                                 return ret;
5918                         /* Count all modify-header actions as one action. */
5919                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5920                                 ++actions_n;
5921                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
5922                         rw_act_num += MLX5_ACT_NUM_SET_DSCP;
5923                         break;
5924                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
5925                         ret = flow_dv_validate_action_modify_ipv6_dscp
5926                                                                 (action_flags,
5927                                                                  actions,
5928                                                                  item_flags,
5929                                                                  error);
5930                         if (ret < 0)
5931                                 return ret;
5932                         /* Count all modify-header actions as one action. */
5933                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5934                                 ++actions_n;
5935                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
5936                         rw_act_num += MLX5_ACT_NUM_SET_DSCP;
5937                         break;
5938                 case RTE_FLOW_ACTION_TYPE_SAMPLE:
5939                         ret = flow_dv_validate_action_sample(action_flags,
5940                                                              actions, dev,
5941                                                              attr, error);
5942                         if (ret < 0)
5943                                 return ret;
5944                         action_flags |= MLX5_FLOW_ACTION_SAMPLE;
5945                         ++actions_n;
5946                         break;
5947                 default:
5948                         return rte_flow_error_set(error, ENOTSUP,
5949                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5950                                                   actions,
5951                                                   "action not supported");
5952                 }
5953         }
5954         /*
5955          * Validate the drop action mutual exclusion with other actions.
5956          * Drop action is mutually-exclusive with any other action, except for
5957          * Count action.
5958          */
5959         if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
5960             (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
5961                 return rte_flow_error_set(error, EINVAL,
5962                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5963                                           "Drop action is mutually-exclusive "
5964                                           "with any other action, except for "
5965                                           "Count action");
5966         /* Eswitch has few restrictions on using items and actions */
5967         if (attr->transfer) {
5968                 if (!mlx5_flow_ext_mreg_supported(dev) &&
5969                     action_flags & MLX5_FLOW_ACTION_FLAG)
5970                         return rte_flow_error_set(error, ENOTSUP,
5971                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5972                                                   NULL,
5973                                                   "unsupported action FLAG");
5974                 if (!mlx5_flow_ext_mreg_supported(dev) &&
5975                     action_flags & MLX5_FLOW_ACTION_MARK)
5976                         return rte_flow_error_set(error, ENOTSUP,
5977                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5978                                                   NULL,
5979                                                   "unsupported action MARK");
5980                 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
5981                         return rte_flow_error_set(error, ENOTSUP,
5982                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5983                                                   NULL,
5984                                                   "unsupported action QUEUE");
5985                 if (action_flags & MLX5_FLOW_ACTION_RSS)
5986                         return rte_flow_error_set(error, ENOTSUP,
5987                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5988                                                   NULL,
5989                                                   "unsupported action RSS");
5990                 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
5991                         return rte_flow_error_set(error, EINVAL,
5992                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5993                                                   actions,
5994                                                   "no fate action is found");
5995         } else {
5996                 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
5997                         return rte_flow_error_set(error, EINVAL,
5998                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5999                                                   actions,
6000                                                   "no fate action is found");
6001         }
6002         /* Continue validation for Xcap and VLAN actions.*/
6003         if ((action_flags & (MLX5_FLOW_XCAP_ACTIONS |
6004                              MLX5_FLOW_VLAN_ACTIONS)) &&
6005             (queue_index == 0xFFFF ||
6006              mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
6007                 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
6008                     MLX5_FLOW_XCAP_ACTIONS)
6009                         return rte_flow_error_set(error, ENOTSUP,
6010                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6011                                                   NULL, "encap and decap "
6012                                                   "combination aren't supported");
6013                 if (!attr->transfer && attr->ingress) {
6014                         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
6015                                 return rte_flow_error_set
6016                                                 (error, ENOTSUP,
6017                                                  RTE_FLOW_ERROR_TYPE_ACTION,
6018                                                  NULL, "encap is not supported"
6019                                                  " for ingress traffic");
6020                         else if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
6021                                 return rte_flow_error_set
6022                                                 (error, ENOTSUP,
6023                                                  RTE_FLOW_ERROR_TYPE_ACTION,
6024                                                  NULL, "push VLAN action not "
6025                                                  "supported for ingress");
6026                         else if ((action_flags & MLX5_FLOW_VLAN_ACTIONS) ==
6027                                         MLX5_FLOW_VLAN_ACTIONS)
6028                                 return rte_flow_error_set
6029                                                 (error, ENOTSUP,
6030                                                  RTE_FLOW_ERROR_TYPE_ACTION,
6031                                                  NULL, "no support for "
6032                                                  "multiple VLAN actions");
6033                 }
6034         }
6035         /* Hairpin flow will add one more TAG action. */
6036         if (hairpin > 0)
6037                 rw_act_num += MLX5_ACT_NUM_SET_TAG;
6038         /* extra metadata enabled: one more TAG action will be add. */
6039         if (dev_conf->dv_flow_en &&
6040             dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
6041             mlx5_flow_ext_mreg_supported(dev))
6042                 rw_act_num += MLX5_ACT_NUM_SET_TAG;
6043         if ((uint32_t)rw_act_num >
6044                         flow_dv_modify_hdr_action_max(dev, is_root)) {
6045                 return rte_flow_error_set(error, ENOTSUP,
6046                                           RTE_FLOW_ERROR_TYPE_ACTION,
6047                                           NULL, "too many header modify"
6048                                           " actions to support");
6049         }
6050         return 0;
6051 }
6052
6053 /**
6054  * Internal preparation function. Allocates the DV flow size,
6055  * this size is constant.
6056  *
6057  * @param[in] dev
6058  *   Pointer to the rte_eth_dev structure.
6059  * @param[in] attr
6060  *   Pointer to the flow attributes.
6061  * @param[in] items
6062  *   Pointer to the list of items.
6063  * @param[in] actions
6064  *   Pointer to the list of actions.
6065  * @param[out] error
6066  *   Pointer to the error structure.
6067  *
6068  * @return
6069  *   Pointer to mlx5_flow object on success,
6070  *   otherwise NULL and rte_errno is set.
6071  */
6072 static struct mlx5_flow *
6073 flow_dv_prepare(struct rte_eth_dev *dev,
6074                 const struct rte_flow_attr *attr __rte_unused,
6075                 const struct rte_flow_item items[] __rte_unused,
6076                 const struct rte_flow_action actions[] __rte_unused,
6077                 struct rte_flow_error *error)
6078 {
6079         uint32_t handle_idx = 0;
6080         struct mlx5_flow *dev_flow;
6081         struct mlx5_flow_handle *dev_handle;
6082         struct mlx5_priv *priv = dev->data->dev_private;
6083
6084         /* In case of corrupting the memory. */
6085         if (priv->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
6086                 rte_flow_error_set(error, ENOSPC,
6087                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6088                                    "not free temporary device flow");
6089                 return NULL;
6090         }
6091         dev_handle = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
6092                                    &handle_idx);
6093         if (!dev_handle) {
6094                 rte_flow_error_set(error, ENOMEM,
6095                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6096                                    "not enough memory to create flow handle");
6097                 return NULL;
6098         }
6099         /* No multi-thread supporting. */
6100         dev_flow = &((struct mlx5_flow *)priv->inter_flows)[priv->flow_idx++];
6101         dev_flow->handle = dev_handle;
6102         dev_flow->handle_idx = handle_idx;
6103         /*
6104          * In some old rdma-core releases, before continuing, a check of the
6105          * length of matching parameter will be done at first. It needs to use
6106          * the length without misc4 param. If the flow has misc4 support, then
6107          * the length needs to be adjusted accordingly. Each param member is
6108          * aligned with a 64B boundary naturally.
6109          */
6110         dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param) -
6111                                   MLX5_ST_SZ_BYTES(fte_match_set_misc4);
6112         /*
6113          * The matching value needs to be cleared to 0 before using. In the
6114          * past, it will be automatically cleared when using rte_*alloc
6115          * API. The time consumption will be almost the same as before.
6116          */
6117         memset(dev_flow->dv.value.buf, 0, MLX5_ST_SZ_BYTES(fte_match_param));
6118         dev_flow->ingress = attr->ingress;
6119         dev_flow->dv.transfer = attr->transfer;
6120         return dev_flow;
6121 }
6122
6123 #ifdef RTE_LIBRTE_MLX5_DEBUG
6124 /**
6125  * Sanity check for match mask and value. Similar to check_valid_spec() in
6126  * kernel driver. If unmasked bit is present in value, it returns failure.
6127  *
6128  * @param match_mask
6129  *   pointer to match mask buffer.
6130  * @param match_value
6131  *   pointer to match value buffer.
6132  *
6133  * @return
6134  *   0 if valid, -EINVAL otherwise.
6135  */
6136 static int
6137 flow_dv_check_valid_spec(void *match_mask, void *match_value)
6138 {
6139         uint8_t *m = match_mask;
6140         uint8_t *v = match_value;
6141         unsigned int i;
6142
6143         for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
6144                 if (v[i] & ~m[i]) {
6145                         DRV_LOG(ERR,
6146                                 "match_value differs from match_criteria"
6147                                 " %p[%u] != %p[%u]",
6148                                 match_value, i, match_mask, i);
6149                         return -EINVAL;
6150                 }
6151         }
6152         return 0;
6153 }
6154 #endif
6155
6156 /**
6157  * Add match of ip_version.
6158  *
6159  * @param[in] group
6160  *   Flow group.
6161  * @param[in] headers_v
6162  *   Values header pointer.
6163  * @param[in] headers_m
6164  *   Masks header pointer.
6165  * @param[in] ip_version
6166  *   The IP version to set.
6167  */
6168 static inline void
6169 flow_dv_set_match_ip_version(uint32_t group,
6170                              void *headers_v,
6171                              void *headers_m,
6172                              uint8_t ip_version)
6173 {
6174         if (group == 0)
6175                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
6176         else
6177                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version,
6178                          ip_version);
6179         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, ip_version);
6180         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, 0);
6181         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype, 0);
6182 }
6183
6184 /**
6185  * Add Ethernet item to matcher and to the value.
6186  *
6187  * @param[in, out] matcher
6188  *   Flow matcher.
6189  * @param[in, out] key
6190  *   Flow matcher value.
6191  * @param[in] item
6192  *   Flow pattern to translate.
6193  * @param[in] inner
6194  *   Item is inner pattern.
6195  */
6196 static void
6197 flow_dv_translate_item_eth(void *matcher, void *key,
6198                            const struct rte_flow_item *item, int inner,
6199                            uint32_t group)
6200 {
6201         const struct rte_flow_item_eth *eth_m = item->mask;
6202         const struct rte_flow_item_eth *eth_v = item->spec;
6203         const struct rte_flow_item_eth nic_mask = {
6204                 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
6205                 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
6206                 .type = RTE_BE16(0xffff),
6207         };
6208         void *headers_m;
6209         void *headers_v;
6210         char *l24_v;
6211         unsigned int i;
6212
6213         if (!eth_v)
6214                 return;
6215         if (!eth_m)
6216                 eth_m = &nic_mask;
6217         if (inner) {
6218                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6219                                          inner_headers);
6220                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6221         } else {
6222                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6223                                          outer_headers);
6224                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6225         }
6226         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, dmac_47_16),
6227                &eth_m->dst, sizeof(eth_m->dst));
6228         /* The value must be in the range of the mask. */
6229         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, dmac_47_16);
6230         for (i = 0; i < sizeof(eth_m->dst); ++i)
6231                 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
6232         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, smac_47_16),
6233                &eth_m->src, sizeof(eth_m->src));
6234         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, smac_47_16);
6235         /* The value must be in the range of the mask. */
6236         for (i = 0; i < sizeof(eth_m->dst); ++i)
6237                 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
6238         if (eth_v->type) {
6239                 /* When ethertype is present set mask for tagged VLAN. */
6240                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
6241                 /* Set value for tagged VLAN if ethertype is 802.1Q. */
6242                 if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_VLAN) ||
6243                     eth_v->type == RTE_BE16(RTE_ETHER_TYPE_QINQ)) {
6244                         MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag,
6245                                  1);
6246                         /* Return here to avoid setting match on ethertype. */
6247                         return;
6248                 }
6249         }
6250         /*
6251          * HW supports match on one Ethertype, the Ethertype following the last
6252          * VLAN tag of the packet (see PRM).
6253          * Set match on ethertype only if ETH header is not followed by VLAN.
6254          * HW is optimized for IPv4/IPv6. In such cases, avoid setting
6255          * ethertype, and use ip_version field instead.
6256          * eCPRI over Ether layer will use type value 0xAEFE.
6257          */
6258         if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_IPV4) &&
6259             eth_m->type == 0xFFFF) {
6260                 flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
6261         } else if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_IPV6) &&
6262                    eth_m->type == 0xFFFF) {
6263                 flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
6264         } else {
6265                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
6266                          rte_be_to_cpu_16(eth_m->type));
6267                 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6268                                      ethertype);
6269                 *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
6270         }
6271 }
6272
6273 /**
6274  * Add VLAN item to matcher and to the value.
6275  *
6276  * @param[in, out] dev_flow
6277  *   Flow descriptor.
6278  * @param[in, out] matcher
6279  *   Flow matcher.
6280  * @param[in, out] key
6281  *   Flow matcher value.
6282  * @param[in] item
6283  *   Flow pattern to translate.
6284  * @param[in] inner
6285  *   Item is inner pattern.
6286  */
6287 static void
6288 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
6289                             void *matcher, void *key,
6290                             const struct rte_flow_item *item,
6291                             int inner, uint32_t group)
6292 {
6293         const struct rte_flow_item_vlan *vlan_m = item->mask;
6294         const struct rte_flow_item_vlan *vlan_v = item->spec;
6295         void *headers_m;
6296         void *headers_v;
6297         uint16_t tci_m;
6298         uint16_t tci_v;
6299
6300         if (inner) {
6301                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6302                                          inner_headers);
6303                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6304         } else {
6305                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6306                                          outer_headers);
6307                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6308                 /*
6309                  * This is workaround, masks are not supported,
6310                  * and pre-validated.
6311                  */
6312                 if (vlan_v)
6313                         dev_flow->handle->vf_vlan.tag =
6314                                         rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
6315         }
6316         /*
6317          * When VLAN item exists in flow, mark packet as tagged,
6318          * even if TCI is not specified.
6319          */
6320         MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
6321         MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
6322         if (!vlan_v)
6323                 return;
6324         if (!vlan_m)
6325                 vlan_m = &rte_flow_item_vlan_mask;
6326         tci_m = rte_be_to_cpu_16(vlan_m->tci);
6327         tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
6328         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_vid, tci_m);
6329         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, tci_v);
6330         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_cfi, tci_m >> 12);
6331         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_cfi, tci_v >> 12);
6332         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_prio, tci_m >> 13);
6333         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, tci_v >> 13);
6334         /*
6335          * HW is optimized for IPv4/IPv6. In such cases, avoid setting
6336          * ethertype, and use ip_version field instead.
6337          */
6338         if (vlan_v->inner_type == RTE_BE16(RTE_ETHER_TYPE_IPV4) &&
6339             vlan_m->inner_type == 0xFFFF) {
6340                 flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
6341         } else if (vlan_v->inner_type == RTE_BE16(RTE_ETHER_TYPE_IPV6) &&
6342                    vlan_m->inner_type == 0xFFFF) {
6343                 flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
6344         } else {
6345                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
6346                          rte_be_to_cpu_16(vlan_m->inner_type));
6347                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
6348                          rte_be_to_cpu_16(vlan_m->inner_type &
6349                                           vlan_v->inner_type));
6350         }
6351 }
6352
6353 /**
6354  * Add IPV4 item to matcher and to the value.
6355  *
6356  * @param[in, out] matcher
6357  *   Flow matcher.
6358  * @param[in, out] key
6359  *   Flow matcher value.
6360  * @param[in] item
6361  *   Flow pattern to translate.
6362  * @param[in] item_flags
6363  *   Bit-fields that holds the items detected until now.
6364  * @param[in] inner
6365  *   Item is inner pattern.
6366  * @param[in] group
6367  *   The group to insert the rule.
6368  */
6369 static void
6370 flow_dv_translate_item_ipv4(void *matcher, void *key,
6371                             const struct rte_flow_item *item,
6372                             const uint64_t item_flags,
6373                             int inner, uint32_t group)
6374 {
6375         const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
6376         const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
6377         const struct rte_flow_item_ipv4 nic_mask = {
6378                 .hdr = {
6379                         .src_addr = RTE_BE32(0xffffffff),
6380                         .dst_addr = RTE_BE32(0xffffffff),
6381                         .type_of_service = 0xff,
6382                         .next_proto_id = 0xff,
6383                         .time_to_live = 0xff,
6384                 },
6385         };
6386         void *headers_m;
6387         void *headers_v;
6388         char *l24_m;
6389         char *l24_v;
6390         uint8_t tos;
6391
6392         if (inner) {
6393                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6394                                          inner_headers);
6395                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6396         } else {
6397                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6398                                          outer_headers);
6399                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6400         }
6401         flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
6402         /*
6403          * On outer header (which must contains L2), or inner header with L2,
6404          * set cvlan_tag mask bit to mark this packet as untagged.
6405          * This should be done even if item->spec is empty.
6406          */
6407         if (!inner || item_flags & MLX5_FLOW_LAYER_INNER_L2)
6408                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
6409         if (!ipv4_v)
6410                 return;
6411         if (!ipv4_m)
6412                 ipv4_m = &nic_mask;
6413         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6414                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
6415         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6416                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
6417         *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
6418         *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
6419         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6420                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
6421         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6422                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
6423         *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
6424         *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
6425         tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
6426         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
6427                  ipv4_m->hdr.type_of_service);
6428         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
6429         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
6430                  ipv4_m->hdr.type_of_service >> 2);
6431         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
6432         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6433                  ipv4_m->hdr.next_proto_id);
6434         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6435                  ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
6436         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
6437                  ipv4_m->hdr.time_to_live);
6438         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
6439                  ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
6440 }
6441
6442 /**
6443  * Add IPV6 item to matcher and to the value.
6444  *
6445  * @param[in, out] matcher
6446  *   Flow matcher.
6447  * @param[in, out] key
6448  *   Flow matcher value.
6449  * @param[in] item
6450  *   Flow pattern to translate.
6451  * @param[in] item_flags
6452  *   Bit-fields that holds the items detected until now.
6453  * @param[in] inner
6454  *   Item is inner pattern.
6455  * @param[in] group
6456  *   The group to insert the rule.
6457  */
6458 static void
6459 flow_dv_translate_item_ipv6(void *matcher, void *key,
6460                             const struct rte_flow_item *item,
6461                             const uint64_t item_flags,
6462                             int inner, uint32_t group)
6463 {
6464         const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
6465         const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
6466         const struct rte_flow_item_ipv6 nic_mask = {
6467                 .hdr = {
6468                         .src_addr =
6469                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
6470                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
6471                         .dst_addr =
6472                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
6473                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
6474                         .vtc_flow = RTE_BE32(0xffffffff),
6475                         .proto = 0xff,
6476                         .hop_limits = 0xff,
6477                 },
6478         };
6479         void *headers_m;
6480         void *headers_v;
6481         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6482         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6483         char *l24_m;
6484         char *l24_v;
6485         uint32_t vtc_m;
6486         uint32_t vtc_v;
6487         int i;
6488         int size;
6489
6490         if (inner) {
6491                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6492                                          inner_headers);
6493                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6494         } else {
6495                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6496                                          outer_headers);
6497                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6498         }
6499         flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
6500         /*
6501          * On outer header (which must contains L2), or inner header with L2,
6502          * set cvlan_tag mask bit to mark this packet as untagged.
6503          * This should be done even if item->spec is empty.
6504          */
6505         if (!inner || item_flags & MLX5_FLOW_LAYER_INNER_L2)
6506                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
6507         if (!ipv6_v)
6508                 return;
6509         if (!ipv6_m)
6510                 ipv6_m = &nic_mask;
6511         size = sizeof(ipv6_m->hdr.dst_addr);
6512         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6513                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
6514         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6515                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
6516         memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
6517         for (i = 0; i < size; ++i)
6518                 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
6519         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6520                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
6521         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6522                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
6523         memcpy(l24_m, ipv6_m->hdr.src_addr, size);
6524         for (i = 0; i < size; ++i)
6525                 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
6526         /* TOS. */
6527         vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
6528         vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
6529         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
6530         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
6531         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
6532         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
6533         /* Label. */
6534         if (inner) {
6535                 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
6536                          vtc_m);
6537                 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
6538                          vtc_v);
6539         } else {
6540                 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
6541                          vtc_m);
6542                 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
6543                          vtc_v);
6544         }
6545         /* Protocol. */
6546         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6547                  ipv6_m->hdr.proto);
6548         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6549                  ipv6_v->hdr.proto & ipv6_m->hdr.proto);
6550         /* Hop limit. */
6551         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
6552                  ipv6_m->hdr.hop_limits);
6553         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
6554                  ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
6555 }
6556
6557 /**
6558  * Add TCP item to matcher and to the value.
6559  *
6560  * @param[in, out] matcher
6561  *   Flow matcher.
6562  * @param[in, out] key
6563  *   Flow matcher value.
6564  * @param[in] item
6565  *   Flow pattern to translate.
6566  * @param[in] inner
6567  *   Item is inner pattern.
6568  */
6569 static void
6570 flow_dv_translate_item_tcp(void *matcher, void *key,
6571                            const struct rte_flow_item *item,
6572                            int inner)
6573 {
6574         const struct rte_flow_item_tcp *tcp_m = item->mask;
6575         const struct rte_flow_item_tcp *tcp_v = item->spec;
6576         void *headers_m;
6577         void *headers_v;
6578
6579         if (inner) {
6580                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6581                                          inner_headers);
6582                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6583         } else {
6584                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6585                                          outer_headers);
6586                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6587         }
6588         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6589         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
6590         if (!tcp_v)
6591                 return;
6592         if (!tcp_m)
6593                 tcp_m = &rte_flow_item_tcp_mask;
6594         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
6595                  rte_be_to_cpu_16(tcp_m->hdr.src_port));
6596         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
6597                  rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
6598         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
6599                  rte_be_to_cpu_16(tcp_m->hdr.dst_port));
6600         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
6601                  rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
6602         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
6603                  tcp_m->hdr.tcp_flags);
6604         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
6605                  (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
6606 }
6607
6608 /**
6609  * Add UDP item to matcher and to the value.
6610  *
6611  * @param[in, out] matcher
6612  *   Flow matcher.
6613  * @param[in, out] key
6614  *   Flow matcher value.
6615  * @param[in] item
6616  *   Flow pattern to translate.
6617  * @param[in] inner
6618  *   Item is inner pattern.
6619  */
6620 static void
6621 flow_dv_translate_item_udp(void *matcher, void *key,
6622                            const struct rte_flow_item *item,
6623                            int inner)
6624 {
6625         const struct rte_flow_item_udp *udp_m = item->mask;
6626         const struct rte_flow_item_udp *udp_v = item->spec;
6627         void *headers_m;
6628         void *headers_v;
6629
6630         if (inner) {
6631                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6632                                          inner_headers);
6633                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6634         } else {
6635                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6636                                          outer_headers);
6637                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6638         }
6639         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6640         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
6641         if (!udp_v)
6642                 return;
6643         if (!udp_m)
6644                 udp_m = &rte_flow_item_udp_mask;
6645         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
6646                  rte_be_to_cpu_16(udp_m->hdr.src_port));
6647         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
6648                  rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
6649         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
6650                  rte_be_to_cpu_16(udp_m->hdr.dst_port));
6651         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
6652                  rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
6653 }
6654
6655 /**
6656  * Add GRE optional Key item to matcher and to the value.
6657  *
6658  * @param[in, out] matcher
6659  *   Flow matcher.
6660  * @param[in, out] key
6661  *   Flow matcher value.
6662  * @param[in] item
6663  *   Flow pattern to translate.
6664  * @param[in] inner
6665  *   Item is inner pattern.
6666  */
6667 static void
6668 flow_dv_translate_item_gre_key(void *matcher, void *key,
6669                                    const struct rte_flow_item *item)
6670 {
6671         const rte_be32_t *key_m = item->mask;
6672         const rte_be32_t *key_v = item->spec;
6673         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6674         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6675         rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
6676
6677         /* GRE K bit must be on and should already be validated */
6678         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
6679         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
6680         if (!key_v)
6681                 return;
6682         if (!key_m)
6683                 key_m = &gre_key_default_mask;
6684         MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
6685                  rte_be_to_cpu_32(*key_m) >> 8);
6686         MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
6687                  rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
6688         MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
6689                  rte_be_to_cpu_32(*key_m) & 0xFF);
6690         MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
6691                  rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
6692 }
6693
6694 /**
6695  * Add GRE item to matcher and to the value.
6696  *
6697  * @param[in, out] matcher
6698  *   Flow matcher.
6699  * @param[in, out] key
6700  *   Flow matcher value.
6701  * @param[in] item
6702  *   Flow pattern to translate.
6703  * @param[in] inner
6704  *   Item is inner pattern.
6705  */
6706 static void
6707 flow_dv_translate_item_gre(void *matcher, void *key,
6708                            const struct rte_flow_item *item,
6709                            int inner)
6710 {
6711         const struct rte_flow_item_gre *gre_m = item->mask;
6712         const struct rte_flow_item_gre *gre_v = item->spec;
6713         void *headers_m;
6714         void *headers_v;
6715         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6716         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6717         struct {
6718                 union {
6719                         __extension__
6720                         struct {
6721                                 uint16_t version:3;
6722                                 uint16_t rsvd0:9;
6723                                 uint16_t s_present:1;
6724                                 uint16_t k_present:1;
6725                                 uint16_t rsvd_bit1:1;
6726                                 uint16_t c_present:1;
6727                         };
6728                         uint16_t value;
6729                 };
6730         } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
6731
6732         if (inner) {
6733                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6734                                          inner_headers);
6735                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6736         } else {
6737                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6738                                          outer_headers);
6739                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6740         }
6741         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6742         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
6743         if (!gre_v)
6744                 return;
6745         if (!gre_m)
6746                 gre_m = &rte_flow_item_gre_mask;
6747         MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
6748                  rte_be_to_cpu_16(gre_m->protocol));
6749         MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
6750                  rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
6751         gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
6752         gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
6753         MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
6754                  gre_crks_rsvd0_ver_m.c_present);
6755         MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
6756                  gre_crks_rsvd0_ver_v.c_present &
6757                  gre_crks_rsvd0_ver_m.c_present);
6758         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
6759                  gre_crks_rsvd0_ver_m.k_present);
6760         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
6761                  gre_crks_rsvd0_ver_v.k_present &
6762                  gre_crks_rsvd0_ver_m.k_present);
6763         MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
6764                  gre_crks_rsvd0_ver_m.s_present);
6765         MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
6766                  gre_crks_rsvd0_ver_v.s_present &
6767                  gre_crks_rsvd0_ver_m.s_present);
6768 }
6769
6770 /**
6771  * Add NVGRE item to matcher and to the value.
6772  *
6773  * @param[in, out] matcher
6774  *   Flow matcher.
6775  * @param[in, out] key
6776  *   Flow matcher value.
6777  * @param[in] item
6778  *   Flow pattern to translate.
6779  * @param[in] inner
6780  *   Item is inner pattern.
6781  */
6782 static void
6783 flow_dv_translate_item_nvgre(void *matcher, void *key,
6784                              const struct rte_flow_item *item,
6785                              int inner)
6786 {
6787         const struct rte_flow_item_nvgre *nvgre_m = item->mask;
6788         const struct rte_flow_item_nvgre *nvgre_v = item->spec;
6789         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6790         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6791         const char *tni_flow_id_m;
6792         const char *tni_flow_id_v;
6793         char *gre_key_m;
6794         char *gre_key_v;
6795         int size;
6796         int i;
6797
6798         /* For NVGRE, GRE header fields must be set with defined values. */
6799         const struct rte_flow_item_gre gre_spec = {
6800                 .c_rsvd0_ver = RTE_BE16(0x2000),
6801                 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
6802         };
6803         const struct rte_flow_item_gre gre_mask = {
6804                 .c_rsvd0_ver = RTE_BE16(0xB000),
6805                 .protocol = RTE_BE16(UINT16_MAX),
6806         };
6807         const struct rte_flow_item gre_item = {
6808                 .spec = &gre_spec,
6809                 .mask = &gre_mask,
6810                 .last = NULL,
6811         };
6812         flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
6813         if (!nvgre_v)
6814                 return;
6815         if (!nvgre_m)
6816                 nvgre_m = &rte_flow_item_nvgre_mask;
6817         tni_flow_id_m = (const char *)nvgre_m->tni;
6818         tni_flow_id_v = (const char *)nvgre_v->tni;
6819         size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
6820         gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
6821         gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
6822         memcpy(gre_key_m, tni_flow_id_m, size);
6823         for (i = 0; i < size; ++i)
6824                 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
6825 }
6826
6827 /**
6828  * Add VXLAN item to matcher and to the value.
6829  *
6830  * @param[in, out] matcher
6831  *   Flow matcher.
6832  * @param[in, out] key
6833  *   Flow matcher value.
6834  * @param[in] item
6835  *   Flow pattern to translate.
6836  * @param[in] inner
6837  *   Item is inner pattern.
6838  */
6839 static void
6840 flow_dv_translate_item_vxlan(void *matcher, void *key,
6841                              const struct rte_flow_item *item,
6842                              int inner)
6843 {
6844         const struct rte_flow_item_vxlan *vxlan_m = item->mask;
6845         const struct rte_flow_item_vxlan *vxlan_v = item->spec;
6846         void *headers_m;
6847         void *headers_v;
6848         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6849         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6850         char *vni_m;
6851         char *vni_v;
6852         uint16_t dport;
6853         int size;
6854         int i;
6855
6856         if (inner) {
6857                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6858                                          inner_headers);
6859                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6860         } else {
6861                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6862                                          outer_headers);
6863                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6864         }
6865         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
6866                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
6867         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6868                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6869                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6870         }
6871         if (!vxlan_v)
6872                 return;
6873         if (!vxlan_m)
6874                 vxlan_m = &rte_flow_item_vxlan_mask;
6875         size = sizeof(vxlan_m->vni);
6876         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
6877         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
6878         memcpy(vni_m, vxlan_m->vni, size);
6879         for (i = 0; i < size; ++i)
6880                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
6881 }
6882
6883 /**
6884  * Add VXLAN-GPE item to matcher and to the value.
6885  *
6886  * @param[in, out] matcher
6887  *   Flow matcher.
6888  * @param[in, out] key
6889  *   Flow matcher value.
6890  * @param[in] item
6891  *   Flow pattern to translate.
6892  * @param[in] inner
6893  *   Item is inner pattern.
6894  */
6895
6896 static void
6897 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
6898                                  const struct rte_flow_item *item, int inner)
6899 {
6900         const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
6901         const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
6902         void *headers_m;
6903         void *headers_v;
6904         void *misc_m =
6905                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
6906         void *misc_v =
6907                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6908         char *vni_m;
6909         char *vni_v;
6910         uint16_t dport;
6911         int size;
6912         int i;
6913         uint8_t flags_m = 0xff;
6914         uint8_t flags_v = 0xc;
6915
6916         if (inner) {
6917                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6918                                          inner_headers);
6919                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6920         } else {
6921                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6922                                          outer_headers);
6923                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6924         }
6925         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
6926                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
6927         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6928                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6929                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6930         }
6931         if (!vxlan_v)
6932                 return;
6933         if (!vxlan_m)
6934                 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
6935         size = sizeof(vxlan_m->vni);
6936         vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
6937         vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
6938         memcpy(vni_m, vxlan_m->vni, size);
6939         for (i = 0; i < size; ++i)
6940                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
6941         if (vxlan_m->flags) {
6942                 flags_m = vxlan_m->flags;
6943                 flags_v = vxlan_v->flags;
6944         }
6945         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
6946         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
6947         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
6948                  vxlan_m->protocol);
6949         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
6950                  vxlan_v->protocol);
6951 }
6952
6953 /**
6954  * Add Geneve item to matcher and to the value.
6955  *
6956  * @param[in, out] matcher
6957  *   Flow matcher.
6958  * @param[in, out] key
6959  *   Flow matcher value.
6960  * @param[in] item
6961  *   Flow pattern to translate.
6962  * @param[in] inner
6963  *   Item is inner pattern.
6964  */
6965
6966 static void
6967 flow_dv_translate_item_geneve(void *matcher, void *key,
6968                               const struct rte_flow_item *item, int inner)
6969 {
6970         const struct rte_flow_item_geneve *geneve_m = item->mask;
6971         const struct rte_flow_item_geneve *geneve_v = item->spec;
6972         void *headers_m;
6973         void *headers_v;
6974         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6975         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6976         uint16_t dport;
6977         uint16_t gbhdr_m;
6978         uint16_t gbhdr_v;
6979         char *vni_m;
6980         char *vni_v;
6981         size_t size, i;
6982
6983         if (inner) {
6984                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6985                                          inner_headers);
6986                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6987         } else {
6988                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6989                                          outer_headers);
6990                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6991         }
6992         dport = MLX5_UDP_PORT_GENEVE;
6993         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6994                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6995                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6996         }
6997         if (!geneve_v)
6998                 return;
6999         if (!geneve_m)
7000                 geneve_m = &rte_flow_item_geneve_mask;
7001         size = sizeof(geneve_m->vni);
7002         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
7003         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
7004         memcpy(vni_m, geneve_m->vni, size);
7005         for (i = 0; i < size; ++i)
7006                 vni_v[i] = vni_m[i] & geneve_v->vni[i];
7007         MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
7008                  rte_be_to_cpu_16(geneve_m->protocol));
7009         MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
7010                  rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
7011         gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
7012         gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
7013         MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
7014                  MLX5_GENEVE_OAMF_VAL(gbhdr_m));
7015         MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
7016                  MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
7017         MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
7018                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
7019         MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
7020                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
7021                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
7022 }
7023
7024 /**
7025  * Add MPLS item to matcher and to the value.
7026  *
7027  * @param[in, out] matcher
7028  *   Flow matcher.
7029  * @param[in, out] key
7030  *   Flow matcher value.
7031  * @param[in] item
7032  *   Flow pattern to translate.
7033  * @param[in] prev_layer
7034  *   The protocol layer indicated in previous item.
7035  * @param[in] inner
7036  *   Item is inner pattern.
7037  */
7038 static void
7039 flow_dv_translate_item_mpls(void *matcher, void *key,
7040                             const struct rte_flow_item *item,
7041                             uint64_t prev_layer,
7042                             int inner)
7043 {
7044         const uint32_t *in_mpls_m = item->mask;
7045         const uint32_t *in_mpls_v = item->spec;
7046         uint32_t *out_mpls_m = 0;
7047         uint32_t *out_mpls_v = 0;
7048         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7049         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7050         void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
7051                                      misc_parameters_2);
7052         void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
7053         void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
7054         void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7055
7056         switch (prev_layer) {
7057         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
7058                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
7059                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
7060                          MLX5_UDP_PORT_MPLS);
7061                 break;
7062         case MLX5_FLOW_LAYER_GRE:
7063                 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
7064                 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
7065                          RTE_ETHER_TYPE_MPLS);
7066                 break;
7067         default:
7068                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7069                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
7070                          IPPROTO_MPLS);
7071                 break;
7072         }
7073         if (!in_mpls_v)
7074                 return;
7075         if (!in_mpls_m)
7076                 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
7077         switch (prev_layer) {
7078         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
7079                 out_mpls_m =
7080                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
7081                                                  outer_first_mpls_over_udp);
7082                 out_mpls_v =
7083                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
7084                                                  outer_first_mpls_over_udp);
7085                 break;
7086         case MLX5_FLOW_LAYER_GRE:
7087                 out_mpls_m =
7088                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
7089                                                  outer_first_mpls_over_gre);
7090                 out_mpls_v =
7091                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
7092                                                  outer_first_mpls_over_gre);
7093                 break;
7094         default:
7095                 /* Inner MPLS not over GRE is not supported. */
7096                 if (!inner) {
7097                         out_mpls_m =
7098                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
7099                                                          misc2_m,
7100                                                          outer_first_mpls);
7101                         out_mpls_v =
7102                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
7103                                                          misc2_v,
7104                                                          outer_first_mpls);
7105                 }
7106                 break;
7107         }
7108         if (out_mpls_m && out_mpls_v) {
7109                 *out_mpls_m = *in_mpls_m;
7110                 *out_mpls_v = *in_mpls_v & *in_mpls_m;
7111         }
7112 }
7113
7114 /**
7115  * Add metadata register item to matcher
7116  *
7117  * @param[in, out] matcher
7118  *   Flow matcher.
7119  * @param[in, out] key
7120  *   Flow matcher value.
7121  * @param[in] reg_type
7122  *   Type of device metadata register
7123  * @param[in] value
7124  *   Register value
7125  * @param[in] mask
7126  *   Register mask
7127  */
7128 static void
7129 flow_dv_match_meta_reg(void *matcher, void *key,
7130                        enum modify_reg reg_type,
7131                        uint32_t data, uint32_t mask)
7132 {
7133         void *misc2_m =
7134                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
7135         void *misc2_v =
7136                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
7137         uint32_t temp;
7138
7139         data &= mask;
7140         switch (reg_type) {
7141         case REG_A:
7142                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
7143                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
7144                 break;
7145         case REG_B:
7146                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
7147                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
7148                 break;
7149         case REG_C_0:
7150                 /*
7151                  * The metadata register C0 field might be divided into
7152                  * source vport index and META item value, we should set
7153                  * this field according to specified mask, not as whole one.
7154                  */
7155                 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
7156                 temp |= mask;
7157                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
7158                 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
7159                 temp &= ~mask;
7160                 temp |= data;
7161                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
7162                 break;
7163         case REG_C_1:
7164                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
7165                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
7166                 break;
7167         case REG_C_2:
7168                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
7169                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
7170                 break;
7171         case REG_C_3:
7172                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
7173                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
7174                 break;
7175         case REG_C_4:
7176                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
7177                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
7178                 break;
7179         case REG_C_5:
7180                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
7181                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
7182                 break;
7183         case REG_C_6:
7184                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
7185                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
7186                 break;
7187         case REG_C_7:
7188                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
7189                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
7190                 break;
7191         default:
7192                 MLX5_ASSERT(false);
7193                 break;
7194         }
7195 }
7196
7197 /**
7198  * Add MARK item to matcher
7199  *
7200  * @param[in] dev
7201  *   The device to configure through.
7202  * @param[in, out] matcher
7203  *   Flow matcher.
7204  * @param[in, out] key
7205  *   Flow matcher value.
7206  * @param[in] item
7207  *   Flow pattern to translate.
7208  */
7209 static void
7210 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
7211                             void *matcher, void *key,
7212                             const struct rte_flow_item *item)
7213 {
7214         struct mlx5_priv *priv = dev->data->dev_private;
7215         const struct rte_flow_item_mark *mark;
7216         uint32_t value;
7217         uint32_t mask;
7218
7219         mark = item->mask ? (const void *)item->mask :
7220                             &rte_flow_item_mark_mask;
7221         mask = mark->id & priv->sh->dv_mark_mask;
7222         mark = (const void *)item->spec;
7223         MLX5_ASSERT(mark);
7224         value = mark->id & priv->sh->dv_mark_mask & mask;
7225         if (mask) {
7226                 enum modify_reg reg;
7227
7228                 /* Get the metadata register index for the mark. */
7229                 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
7230                 MLX5_ASSERT(reg > 0);
7231                 if (reg == REG_C_0) {
7232                         struct mlx5_priv *priv = dev->data->dev_private;
7233                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
7234                         uint32_t shl_c0 = rte_bsf32(msk_c0);
7235
7236                         mask &= msk_c0;
7237                         mask <<= shl_c0;
7238                         value <<= shl_c0;
7239                 }
7240                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
7241         }
7242 }
7243
7244 /**
7245  * Add META item to matcher
7246  *
7247  * @param[in] dev
7248  *   The devich to configure through.
7249  * @param[in, out] matcher
7250  *   Flow matcher.
7251  * @param[in, out] key
7252  *   Flow matcher value.
7253  * @param[in] attr
7254  *   Attributes of flow that includes this item.
7255  * @param[in] item
7256  *   Flow pattern to translate.
7257  */
7258 static void
7259 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
7260                             void *matcher, void *key,
7261                             const struct rte_flow_attr *attr,
7262                             const struct rte_flow_item *item)
7263 {
7264         const struct rte_flow_item_meta *meta_m;
7265         const struct rte_flow_item_meta *meta_v;
7266
7267         meta_m = (const void *)item->mask;
7268         if (!meta_m)
7269                 meta_m = &rte_flow_item_meta_mask;
7270         meta_v = (const void *)item->spec;
7271         if (meta_v) {
7272                 int reg;
7273                 uint32_t value = meta_v->data;
7274                 uint32_t mask = meta_m->data;
7275
7276                 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
7277                 if (reg < 0)
7278                         return;
7279                 /*
7280                  * In datapath code there is no endianness
7281                  * coversions for perfromance reasons, all
7282                  * pattern conversions are done in rte_flow.
7283                  */
7284                 value = rte_cpu_to_be_32(value);
7285                 mask = rte_cpu_to_be_32(mask);
7286                 if (reg == REG_C_0) {
7287                         struct mlx5_priv *priv = dev->data->dev_private;
7288                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
7289                         uint32_t shl_c0 = rte_bsf32(msk_c0);
7290 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
7291                         uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
7292
7293                         value >>= shr_c0;
7294                         mask >>= shr_c0;
7295 #endif
7296                         value <<= shl_c0;
7297                         mask <<= shl_c0;
7298                         MLX5_ASSERT(msk_c0);
7299                         MLX5_ASSERT(!(~msk_c0 & mask));
7300                 }
7301                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
7302         }
7303 }
7304
7305 /**
7306  * Add vport metadata Reg C0 item to matcher
7307  *
7308  * @param[in, out] matcher
7309  *   Flow matcher.
7310  * @param[in, out] key
7311  *   Flow matcher value.
7312  * @param[in] reg
7313  *   Flow pattern to translate.
7314  */
7315 static void
7316 flow_dv_translate_item_meta_vport(void *matcher, void *key,
7317                                   uint32_t value, uint32_t mask)
7318 {
7319         flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
7320 }
7321
7322 /**
7323  * Add tag item to matcher
7324  *
7325  * @param[in] dev
7326  *   The devich to configure through.
7327  * @param[in, out] matcher
7328  *   Flow matcher.
7329  * @param[in, out] key
7330  *   Flow matcher value.
7331  * @param[in] item
7332  *   Flow pattern to translate.
7333  */
7334 static void
7335 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
7336                                 void *matcher, void *key,
7337                                 const struct rte_flow_item *item)
7338 {
7339         const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
7340         const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
7341         uint32_t mask, value;
7342
7343         MLX5_ASSERT(tag_v);
7344         value = tag_v->data;
7345         mask = tag_m ? tag_m->data : UINT32_MAX;
7346         if (tag_v->id == REG_C_0) {
7347                 struct mlx5_priv *priv = dev->data->dev_private;
7348                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
7349                 uint32_t shl_c0 = rte_bsf32(msk_c0);
7350
7351                 mask &= msk_c0;
7352                 mask <<= shl_c0;
7353                 value <<= shl_c0;
7354         }
7355         flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
7356 }
7357
7358 /**
7359  * Add TAG item to matcher
7360  *
7361  * @param[in] dev
7362  *   The devich to configure through.
7363  * @param[in, out] matcher
7364  *   Flow matcher.
7365  * @param[in, out] key
7366  *   Flow matcher value.
7367  * @param[in] item
7368  *   Flow pattern to translate.
7369  */
7370 static void
7371 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
7372                            void *matcher, void *key,
7373                            const struct rte_flow_item *item)
7374 {
7375         const struct rte_flow_item_tag *tag_v = item->spec;
7376         const struct rte_flow_item_tag *tag_m = item->mask;
7377         enum modify_reg reg;
7378
7379         MLX5_ASSERT(tag_v);
7380         tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
7381         /* Get the metadata register index for the tag. */
7382         reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
7383         MLX5_ASSERT(reg > 0);
7384         flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
7385 }
7386
7387 /**
7388  * Add source vport match to the specified matcher.
7389  *
7390  * @param[in, out] matcher
7391  *   Flow matcher.
7392  * @param[in, out] key
7393  *   Flow matcher value.
7394  * @param[in] port
7395  *   Source vport value to match
7396  * @param[in] mask
7397  *   Mask
7398  */
7399 static void
7400 flow_dv_translate_item_source_vport(void *matcher, void *key,
7401                                     int16_t port, uint16_t mask)
7402 {
7403         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7404         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7405
7406         MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
7407         MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
7408 }
7409
7410 /**
7411  * Translate port-id item to eswitch match on  port-id.
7412  *
7413  * @param[in] dev
7414  *   The devich to configure through.
7415  * @param[in, out] matcher
7416  *   Flow matcher.
7417  * @param[in, out] key
7418  *   Flow matcher value.
7419  * @param[in] item
7420  *   Flow pattern to translate.
7421  *
7422  * @return
7423  *   0 on success, a negative errno value otherwise.
7424  */
7425 static int
7426 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
7427                                void *key, const struct rte_flow_item *item)
7428 {
7429         const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
7430         const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
7431         struct mlx5_priv *priv;
7432         uint16_t mask, id;
7433
7434         mask = pid_m ? pid_m->id : 0xffff;
7435         id = pid_v ? pid_v->id : dev->data->port_id;
7436         priv = mlx5_port_to_eswitch_info(id, item == NULL);
7437         if (!priv)
7438                 return -rte_errno;
7439         /* Translate to vport field or to metadata, depending on mode. */
7440         if (priv->vport_meta_mask)
7441                 flow_dv_translate_item_meta_vport(matcher, key,
7442                                                   priv->vport_meta_tag,
7443                                                   priv->vport_meta_mask);
7444         else
7445                 flow_dv_translate_item_source_vport(matcher, key,
7446                                                     priv->vport_id, mask);
7447         return 0;
7448 }
7449
7450 /**
7451  * Add ICMP6 item to matcher and to the value.
7452  *
7453  * @param[in, out] matcher
7454  *   Flow matcher.
7455  * @param[in, out] key
7456  *   Flow matcher value.
7457  * @param[in] item
7458  *   Flow pattern to translate.
7459  * @param[in] inner
7460  *   Item is inner pattern.
7461  */
7462 static void
7463 flow_dv_translate_item_icmp6(void *matcher, void *key,
7464                               const struct rte_flow_item *item,
7465                               int inner)
7466 {
7467         const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
7468         const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
7469         void *headers_m;
7470         void *headers_v;
7471         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7472                                      misc_parameters_3);
7473         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7474         if (inner) {
7475                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7476                                          inner_headers);
7477                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7478         } else {
7479                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7480                                          outer_headers);
7481                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7482         }
7483         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
7484         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
7485         if (!icmp6_v)
7486                 return;
7487         if (!icmp6_m)
7488                 icmp6_m = &rte_flow_item_icmp6_mask;
7489         /*
7490          * Force flow only to match the non-fragmented IPv6 ICMPv6 packets.
7491          * If only the protocol is specified, no need to match the frag.
7492          */
7493         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
7494         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
7495         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
7496         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
7497                  icmp6_v->type & icmp6_m->type);
7498         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
7499         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
7500                  icmp6_v->code & icmp6_m->code);
7501 }
7502
7503 /**
7504  * Add ICMP item to matcher and to the value.
7505  *
7506  * @param[in, out] matcher
7507  *   Flow matcher.
7508  * @param[in, out] key
7509  *   Flow matcher value.
7510  * @param[in] item
7511  *   Flow pattern to translate.
7512  * @param[in] inner
7513  *   Item is inner pattern.
7514  */
7515 static void
7516 flow_dv_translate_item_icmp(void *matcher, void *key,
7517                             const struct rte_flow_item *item,
7518                             int inner)
7519 {
7520         const struct rte_flow_item_icmp *icmp_m = item->mask;
7521         const struct rte_flow_item_icmp *icmp_v = item->spec;
7522         uint32_t icmp_header_data_m = 0;
7523         uint32_t icmp_header_data_v = 0;
7524         void *headers_m;
7525         void *headers_v;
7526         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7527                                      misc_parameters_3);
7528         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7529         if (inner) {
7530                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7531                                          inner_headers);
7532                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7533         } else {
7534                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7535                                          outer_headers);
7536                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7537         }
7538         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
7539         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
7540         if (!icmp_v)
7541                 return;
7542         if (!icmp_m)
7543                 icmp_m = &rte_flow_item_icmp_mask;
7544         /*
7545          * Force flow only to match the non-fragmented IPv4 ICMP packets.
7546          * If only the protocol is specified, no need to match the frag.
7547          */
7548         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
7549         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
7550         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
7551                  icmp_m->hdr.icmp_type);
7552         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
7553                  icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
7554         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
7555                  icmp_m->hdr.icmp_code);
7556         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
7557                  icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
7558         icmp_header_data_m = rte_be_to_cpu_16(icmp_m->hdr.icmp_seq_nb);
7559         icmp_header_data_m |= rte_be_to_cpu_16(icmp_m->hdr.icmp_ident) << 16;
7560         if (icmp_header_data_m) {
7561                 icmp_header_data_v = rte_be_to_cpu_16(icmp_v->hdr.icmp_seq_nb);
7562                 icmp_header_data_v |=
7563                          rte_be_to_cpu_16(icmp_v->hdr.icmp_ident) << 16;
7564                 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_header_data,
7565                          icmp_header_data_m);
7566                 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_header_data,
7567                          icmp_header_data_v & icmp_header_data_m);
7568         }
7569 }
7570
7571 /**
7572  * Add GTP item to matcher and to the value.
7573  *
7574  * @param[in, out] matcher
7575  *   Flow matcher.
7576  * @param[in, out] key
7577  *   Flow matcher value.
7578  * @param[in] item
7579  *   Flow pattern to translate.
7580  * @param[in] inner
7581  *   Item is inner pattern.
7582  */
7583 static void
7584 flow_dv_translate_item_gtp(void *matcher, void *key,
7585                            const struct rte_flow_item *item, int inner)
7586 {
7587         const struct rte_flow_item_gtp *gtp_m = item->mask;
7588         const struct rte_flow_item_gtp *gtp_v = item->spec;
7589         void *headers_m;
7590         void *headers_v;
7591         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7592                                      misc_parameters_3);
7593         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7594         uint16_t dport = RTE_GTPU_UDP_PORT;
7595
7596         if (inner) {
7597                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7598                                          inner_headers);
7599                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7600         } else {
7601                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7602                                          outer_headers);
7603                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7604         }
7605         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7606                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7607                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7608         }
7609         if (!gtp_v)
7610                 return;
7611         if (!gtp_m)
7612                 gtp_m = &rte_flow_item_gtp_mask;
7613         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags,
7614                  gtp_m->v_pt_rsv_flags);
7615         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags,
7616                  gtp_v->v_pt_rsv_flags & gtp_m->v_pt_rsv_flags);
7617         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
7618         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
7619                  gtp_v->msg_type & gtp_m->msg_type);
7620         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
7621                  rte_be_to_cpu_32(gtp_m->teid));
7622         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
7623                  rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
7624 }
7625
7626 /**
7627  * Add eCPRI item to matcher and to the value.
7628  *
7629  * @param[in] dev
7630  *   The devich to configure through.
7631  * @param[in, out] matcher
7632  *   Flow matcher.
7633  * @param[in, out] key
7634  *   Flow matcher value.
7635  * @param[in] item
7636  *   Flow pattern to translate.
7637  * @param[in] samples
7638  *   Sample IDs to be used in the matching.
7639  */
7640 static void
7641 flow_dv_translate_item_ecpri(struct rte_eth_dev *dev, void *matcher,
7642                              void *key, const struct rte_flow_item *item)
7643 {
7644         struct mlx5_priv *priv = dev->data->dev_private;
7645         const struct rte_flow_item_ecpri *ecpri_m = item->mask;
7646         const struct rte_flow_item_ecpri *ecpri_v = item->spec;
7647         void *misc4_m = MLX5_ADDR_OF(fte_match_param, matcher,
7648                                      misc_parameters_4);
7649         void *misc4_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_4);
7650         uint32_t *samples;
7651         void *dw_m;
7652         void *dw_v;
7653
7654         if (!ecpri_v)
7655                 return;
7656         if (!ecpri_m)
7657                 ecpri_m = &rte_flow_item_ecpri_mask;
7658         /*
7659          * Maximal four DW samples are supported in a single matching now.
7660          * Two are used now for a eCPRI matching:
7661          * 1. Type: one byte, mask should be 0x00ff0000 in network order
7662          * 2. ID of a message: one or two bytes, mask 0xffff0000 or 0xff000000
7663          *    if any.
7664          */
7665         if (!ecpri_m->hdr.common.u32)
7666                 return;
7667         samples = priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0].ids;
7668         /* Need to take the whole DW as the mask to fill the entry. */
7669         dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
7670                             prog_sample_field_value_0);
7671         dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
7672                             prog_sample_field_value_0);
7673         /* Already big endian (network order) in the header. */
7674         *(uint32_t *)dw_m = ecpri_m->hdr.common.u32;
7675         *(uint32_t *)dw_v = ecpri_v->hdr.common.u32;
7676         /* Sample#0, used for matching type, offset 0. */
7677         MLX5_SET(fte_match_set_misc4, misc4_m,
7678                  prog_sample_field_id_0, samples[0]);
7679         /* It makes no sense to set the sample ID in the mask field. */
7680         MLX5_SET(fte_match_set_misc4, misc4_v,
7681                  prog_sample_field_id_0, samples[0]);
7682         /*
7683          * Checking if message body part needs to be matched.
7684          * Some wildcard rules only matching type field should be supported.
7685          */
7686         if (ecpri_m->hdr.dummy[0]) {
7687                 switch (ecpri_v->hdr.common.type) {
7688                 case RTE_ECPRI_MSG_TYPE_IQ_DATA:
7689                 case RTE_ECPRI_MSG_TYPE_RTC_CTRL:
7690                 case RTE_ECPRI_MSG_TYPE_DLY_MSR:
7691                         dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
7692                                             prog_sample_field_value_1);
7693                         dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
7694                                             prog_sample_field_value_1);
7695                         *(uint32_t *)dw_m = ecpri_m->hdr.dummy[0];
7696                         *(uint32_t *)dw_v = ecpri_v->hdr.dummy[0];
7697                         /* Sample#1, to match message body, offset 4. */
7698                         MLX5_SET(fte_match_set_misc4, misc4_m,
7699                                  prog_sample_field_id_1, samples[1]);
7700                         MLX5_SET(fte_match_set_misc4, misc4_v,
7701                                  prog_sample_field_id_1, samples[1]);
7702                         break;
7703                 default:
7704                         /* Others, do not match any sample ID. */
7705                         break;
7706                 }
7707         }
7708 }
7709
7710 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
7711
7712 #define HEADER_IS_ZERO(match_criteria, headers)                              \
7713         !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers),     \
7714                  matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
7715
7716 /**
7717  * Calculate flow matcher enable bitmap.
7718  *
7719  * @param match_criteria
7720  *   Pointer to flow matcher criteria.
7721  *
7722  * @return
7723  *   Bitmap of enabled fields.
7724  */
7725 static uint8_t
7726 flow_dv_matcher_enable(uint32_t *match_criteria)
7727 {
7728         uint8_t match_criteria_enable;
7729
7730         match_criteria_enable =
7731                 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
7732                 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
7733         match_criteria_enable |=
7734                 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
7735                 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
7736         match_criteria_enable |=
7737                 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
7738                 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
7739         match_criteria_enable |=
7740                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
7741                 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
7742         match_criteria_enable |=
7743                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
7744                 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
7745         match_criteria_enable |=
7746                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_4)) <<
7747                 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT;
7748         return match_criteria_enable;
7749 }
7750
7751
7752 /**
7753  * Get a flow table.
7754  *
7755  * @param[in, out] dev
7756  *   Pointer to rte_eth_dev structure.
7757  * @param[in] table_id
7758  *   Table id to use.
7759  * @param[in] egress
7760  *   Direction of the table.
7761  * @param[in] transfer
7762  *   E-Switch or NIC flow.
7763  * @param[out] error
7764  *   pointer to error structure.
7765  *
7766  * @return
7767  *   Returns tables resource based on the index, NULL in case of failed.
7768  */
7769 static struct mlx5_flow_tbl_resource *
7770 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
7771                          uint32_t table_id, uint8_t egress,
7772                          uint8_t transfer,
7773                          struct rte_flow_error *error)
7774 {
7775         struct mlx5_priv *priv = dev->data->dev_private;
7776         struct mlx5_dev_ctx_shared *sh = priv->sh;
7777         struct mlx5_flow_tbl_resource *tbl;
7778         union mlx5_flow_tbl_key table_key = {
7779                 {
7780                         .table_id = table_id,
7781                         .reserved = 0,
7782                         .domain = !!transfer,
7783                         .direction = !!egress,
7784                 }
7785         };
7786         struct mlx5_hlist_entry *pos = mlx5_hlist_lookup(sh->flow_tbls,
7787                                                          table_key.v64);
7788         struct mlx5_flow_tbl_data_entry *tbl_data;
7789         uint32_t idx = 0;
7790         int ret;
7791         void *domain;
7792
7793         if (pos) {
7794                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
7795                                         entry);
7796                 tbl = &tbl_data->tbl;
7797                 rte_atomic32_inc(&tbl->refcnt);
7798                 return tbl;
7799         }
7800         tbl_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
7801         if (!tbl_data) {
7802                 rte_flow_error_set(error, ENOMEM,
7803                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7804                                    NULL,
7805                                    "cannot allocate flow table data entry");
7806                 return NULL;
7807         }
7808         tbl_data->idx = idx;
7809         tbl = &tbl_data->tbl;
7810         pos = &tbl_data->entry;
7811         if (transfer)
7812                 domain = sh->fdb_domain;
7813         else if (egress)
7814                 domain = sh->tx_domain;
7815         else
7816                 domain = sh->rx_domain;
7817         ret = mlx5_flow_os_create_flow_tbl(domain, table_id, &tbl->obj);
7818         if (ret) {
7819                 rte_flow_error_set(error, ENOMEM,
7820                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7821                                    NULL, "cannot create flow table object");
7822                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
7823                 return NULL;
7824         }
7825         /*
7826          * No multi-threads now, but still better to initialize the reference
7827          * count before insert it into the hash list.
7828          */
7829         rte_atomic32_init(&tbl->refcnt);
7830         /* Jump action reference count is initialized here. */
7831         rte_atomic32_init(&tbl_data->jump.refcnt);
7832         pos->key = table_key.v64;
7833         ret = mlx5_hlist_insert(sh->flow_tbls, pos);
7834         if (ret < 0) {
7835                 rte_flow_error_set(error, -ret,
7836                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7837                                    "cannot insert flow table data entry");
7838                 mlx5_flow_os_destroy_flow_tbl(tbl->obj);
7839                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
7840         }
7841         rte_atomic32_inc(&tbl->refcnt);
7842         return tbl;
7843 }
7844
7845 /**
7846  * Release a flow table.
7847  *
7848  * @param[in] dev
7849  *   Pointer to rte_eth_dev structure.
7850  * @param[in] tbl
7851  *   Table resource to be released.
7852  *
7853  * @return
7854  *   Returns 0 if table was released, else return 1;
7855  */
7856 static int
7857 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
7858                              struct mlx5_flow_tbl_resource *tbl)
7859 {
7860         struct mlx5_priv *priv = dev->data->dev_private;
7861         struct mlx5_dev_ctx_shared *sh = priv->sh;
7862         struct mlx5_flow_tbl_data_entry *tbl_data =
7863                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
7864
7865         if (!tbl)
7866                 return 0;
7867         if (rte_atomic32_dec_and_test(&tbl->refcnt)) {
7868                 struct mlx5_hlist_entry *pos = &tbl_data->entry;
7869
7870                 mlx5_flow_os_destroy_flow_tbl(tbl->obj);
7871                 tbl->obj = NULL;
7872                 /* remove the entry from the hash list and free memory. */
7873                 mlx5_hlist_remove(sh->flow_tbls, pos);
7874                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_JUMP],
7875                                 tbl_data->idx);
7876                 return 0;
7877         }
7878         return 1;
7879 }
7880
7881 /**
7882  * Register the flow matcher.
7883  *
7884  * @param[in, out] dev
7885  *   Pointer to rte_eth_dev structure.
7886  * @param[in, out] matcher
7887  *   Pointer to flow matcher.
7888  * @param[in, out] key
7889  *   Pointer to flow table key.
7890  * @parm[in, out] dev_flow
7891  *   Pointer to the dev_flow.
7892  * @param[out] error
7893  *   pointer to error structure.
7894  *
7895  * @return
7896  *   0 on success otherwise -errno and errno is set.
7897  */
7898 static int
7899 flow_dv_matcher_register(struct rte_eth_dev *dev,
7900                          struct mlx5_flow_dv_matcher *matcher,
7901                          union mlx5_flow_tbl_key *key,
7902                          struct mlx5_flow *dev_flow,
7903                          struct rte_flow_error *error)
7904 {
7905         struct mlx5_priv *priv = dev->data->dev_private;
7906         struct mlx5_dev_ctx_shared *sh = priv->sh;
7907         struct mlx5_flow_dv_matcher *cache_matcher;
7908         struct mlx5dv_flow_matcher_attr dv_attr = {
7909                 .type = IBV_FLOW_ATTR_NORMAL,
7910                 .match_mask = (void *)&matcher->mask,
7911         };
7912         struct mlx5_flow_tbl_resource *tbl;
7913         struct mlx5_flow_tbl_data_entry *tbl_data;
7914         int ret;
7915
7916         tbl = flow_dv_tbl_resource_get(dev, key->table_id, key->direction,
7917                                        key->domain, error);
7918         if (!tbl)
7919                 return -rte_errno;      /* No need to refill the error info */
7920         tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
7921         /* Lookup from cache. */
7922         LIST_FOREACH(cache_matcher, &tbl_data->matchers, next) {
7923                 if (matcher->crc == cache_matcher->crc &&
7924                     matcher->priority == cache_matcher->priority &&
7925                     !memcmp((const void *)matcher->mask.buf,
7926                             (const void *)cache_matcher->mask.buf,
7927                             cache_matcher->mask.size)) {
7928                         DRV_LOG(DEBUG,
7929                                 "%s group %u priority %hd use %s "
7930                                 "matcher %p: refcnt %d++",
7931                                 key->domain ? "FDB" : "NIC", key->table_id,
7932                                 cache_matcher->priority,
7933                                 key->direction ? "tx" : "rx",
7934                                 (void *)cache_matcher,
7935                                 rte_atomic32_read(&cache_matcher->refcnt));
7936                         rte_atomic32_inc(&cache_matcher->refcnt);
7937                         dev_flow->handle->dvh.matcher = cache_matcher;
7938                         /* old matcher should not make the table ref++. */
7939                         flow_dv_tbl_resource_release(dev, tbl);
7940                         return 0;
7941                 }
7942         }
7943         /* Register new matcher. */
7944         cache_matcher = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*cache_matcher), 0,
7945                                     SOCKET_ID_ANY);
7946         if (!cache_matcher) {
7947                 flow_dv_tbl_resource_release(dev, tbl);
7948                 return rte_flow_error_set(error, ENOMEM,
7949                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7950                                           "cannot allocate matcher memory");
7951         }
7952         *cache_matcher = *matcher;
7953         dv_attr.match_criteria_enable =
7954                 flow_dv_matcher_enable(cache_matcher->mask.buf);
7955         dv_attr.priority = matcher->priority;
7956         if (key->direction)
7957                 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
7958         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj,
7959                                                &cache_matcher->matcher_object);
7960         if (ret) {
7961                 mlx5_free(cache_matcher);
7962 #ifdef HAVE_MLX5DV_DR
7963                 flow_dv_tbl_resource_release(dev, tbl);
7964 #endif
7965                 return rte_flow_error_set(error, ENOMEM,
7966                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7967                                           NULL, "cannot create matcher");
7968         }
7969         /* Save the table information */
7970         cache_matcher->tbl = tbl;
7971         rte_atomic32_init(&cache_matcher->refcnt);
7972         /* only matcher ref++, table ref++ already done above in get API. */
7973         rte_atomic32_inc(&cache_matcher->refcnt);
7974         LIST_INSERT_HEAD(&tbl_data->matchers, cache_matcher, next);
7975         dev_flow->handle->dvh.matcher = cache_matcher;
7976         DRV_LOG(DEBUG, "%s group %u priority %hd new %s matcher %p: refcnt %d",
7977                 key->domain ? "FDB" : "NIC", key->table_id,
7978                 cache_matcher->priority,
7979                 key->direction ? "tx" : "rx", (void *)cache_matcher,
7980                 rte_atomic32_read(&cache_matcher->refcnt));
7981         return 0;
7982 }
7983
7984 /**
7985  * Find existing tag resource or create and register a new one.
7986  *
7987  * @param dev[in, out]
7988  *   Pointer to rte_eth_dev structure.
7989  * @param[in, out] tag_be24
7990  *   Tag value in big endian then R-shift 8.
7991  * @parm[in, out] dev_flow
7992  *   Pointer to the dev_flow.
7993  * @param[out] error
7994  *   pointer to error structure.
7995  *
7996  * @return
7997  *   0 on success otherwise -errno and errno is set.
7998  */
7999 static int
8000 flow_dv_tag_resource_register
8001                         (struct rte_eth_dev *dev,
8002                          uint32_t tag_be24,
8003                          struct mlx5_flow *dev_flow,
8004                          struct rte_flow_error *error)
8005 {
8006         struct mlx5_priv *priv = dev->data->dev_private;
8007         struct mlx5_dev_ctx_shared *sh = priv->sh;
8008         struct mlx5_flow_dv_tag_resource *cache_resource;
8009         struct mlx5_hlist_entry *entry;
8010         int ret;
8011
8012         /* Lookup a matching resource from cache. */
8013         entry = mlx5_hlist_lookup(sh->tag_table, (uint64_t)tag_be24);
8014         if (entry) {
8015                 cache_resource = container_of
8016                         (entry, struct mlx5_flow_dv_tag_resource, entry);
8017                 rte_atomic32_inc(&cache_resource->refcnt);
8018                 dev_flow->handle->dvh.rix_tag = cache_resource->idx;
8019                 dev_flow->dv.tag_resource = cache_resource;
8020                 DRV_LOG(DEBUG, "cached tag resource %p: refcnt now %d++",
8021                         (void *)cache_resource,
8022                         rte_atomic32_read(&cache_resource->refcnt));
8023                 return 0;
8024         }
8025         /* Register new resource. */
8026         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_TAG],
8027                                        &dev_flow->handle->dvh.rix_tag);
8028         if (!cache_resource)
8029                 return rte_flow_error_set(error, ENOMEM,
8030                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8031                                           "cannot allocate resource memory");
8032         cache_resource->entry.key = (uint64_t)tag_be24;
8033         ret = mlx5_flow_os_create_flow_action_tag(tag_be24,
8034                                                   &cache_resource->action);
8035         if (ret) {
8036                 mlx5_free(cache_resource);
8037                 return rte_flow_error_set(error, ENOMEM,
8038                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8039                                           NULL, "cannot create action");
8040         }
8041         rte_atomic32_init(&cache_resource->refcnt);
8042         rte_atomic32_inc(&cache_resource->refcnt);
8043         if (mlx5_hlist_insert(sh->tag_table, &cache_resource->entry)) {
8044                 mlx5_flow_os_destroy_flow_action(cache_resource->action);
8045                 mlx5_free(cache_resource);
8046                 return rte_flow_error_set(error, EEXIST,
8047                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8048                                           NULL, "cannot insert tag");
8049         }
8050         dev_flow->dv.tag_resource = cache_resource;
8051         DRV_LOG(DEBUG, "new tag resource %p: refcnt now %d++",
8052                 (void *)cache_resource,
8053                 rte_atomic32_read(&cache_resource->refcnt));
8054         return 0;
8055 }
8056
8057 /**
8058  * Release the tag.
8059  *
8060  * @param dev
8061  *   Pointer to Ethernet device.
8062  * @param tag_idx
8063  *   Tag index.
8064  *
8065  * @return
8066  *   1 while a reference on it exists, 0 when freed.
8067  */
8068 static int
8069 flow_dv_tag_release(struct rte_eth_dev *dev,
8070                     uint32_t tag_idx)
8071 {
8072         struct mlx5_priv *priv = dev->data->dev_private;
8073         struct mlx5_dev_ctx_shared *sh = priv->sh;
8074         struct mlx5_flow_dv_tag_resource *tag;
8075
8076         tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
8077         if (!tag)
8078                 return 0;
8079         DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
8080                 dev->data->port_id, (void *)tag,
8081                 rte_atomic32_read(&tag->refcnt));
8082         if (rte_atomic32_dec_and_test(&tag->refcnt)) {
8083                 claim_zero(mlx5_flow_os_destroy_flow_action(tag->action));
8084                 mlx5_hlist_remove(sh->tag_table, &tag->entry);
8085                 DRV_LOG(DEBUG, "port %u tag %p: removed",
8086                         dev->data->port_id, (void *)tag);
8087                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
8088                 return 0;
8089         }
8090         return 1;
8091 }
8092
8093 /**
8094  * Translate port ID action to vport.
8095  *
8096  * @param[in] dev
8097  *   Pointer to rte_eth_dev structure.
8098  * @param[in] action
8099  *   Pointer to the port ID action.
8100  * @param[out] dst_port_id
8101  *   The target port ID.
8102  * @param[out] error
8103  *   Pointer to the error structure.
8104  *
8105  * @return
8106  *   0 on success, a negative errno value otherwise and rte_errno is set.
8107  */
8108 static int
8109 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
8110                                  const struct rte_flow_action *action,
8111                                  uint32_t *dst_port_id,
8112                                  struct rte_flow_error *error)
8113 {
8114         uint32_t port;
8115         struct mlx5_priv *priv;
8116         const struct rte_flow_action_port_id *conf =
8117                         (const struct rte_flow_action_port_id *)action->conf;
8118
8119         port = conf->original ? dev->data->port_id : conf->id;
8120         priv = mlx5_port_to_eswitch_info(port, false);
8121         if (!priv)
8122                 return rte_flow_error_set(error, -rte_errno,
8123                                           RTE_FLOW_ERROR_TYPE_ACTION,
8124                                           NULL,
8125                                           "No eswitch info was found for port");
8126 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
8127         /*
8128          * This parameter is transferred to
8129          * mlx5dv_dr_action_create_dest_ib_port().
8130          */
8131         *dst_port_id = priv->dev_port;
8132 #else
8133         /*
8134          * Legacy mode, no LAG configurations is supported.
8135          * This parameter is transferred to
8136          * mlx5dv_dr_action_create_dest_vport().
8137          */
8138         *dst_port_id = priv->vport_id;
8139 #endif
8140         return 0;
8141 }
8142
8143 /**
8144  * Create a counter with aging configuration.
8145  *
8146  * @param[in] dev
8147  *   Pointer to rte_eth_dev structure.
8148  * @param[out] count
8149  *   Pointer to the counter action configuration.
8150  * @param[in] age
8151  *   Pointer to the aging action configuration.
8152  *
8153  * @return
8154  *   Index to flow counter on success, 0 otherwise.
8155  */
8156 static uint32_t
8157 flow_dv_translate_create_counter(struct rte_eth_dev *dev,
8158                                 struct mlx5_flow *dev_flow,
8159                                 const struct rte_flow_action_count *count,
8160                                 const struct rte_flow_action_age *age)
8161 {
8162         uint32_t counter;
8163         struct mlx5_age_param *age_param;
8164
8165         counter = flow_dv_counter_alloc(dev,
8166                                 count ? count->shared : 0,
8167                                 count ? count->id : 0,
8168                                 dev_flow->dv.group, !!age);
8169         if (!counter || age == NULL)
8170                 return counter;
8171         age_param  = flow_dv_counter_idx_get_age(dev, counter);
8172         /*
8173          * The counter age accuracy may have a bit delay. Have 3/4
8174          * second bias on the timeount in order to let it age in time.
8175          */
8176         age_param->context = age->context ? age->context :
8177                 (void *)(uintptr_t)(dev_flow->flow_idx);
8178         /*
8179          * The counter age accuracy may have a bit delay. Have 3/4
8180          * second bias on the timeount in order to let it age in time.
8181          */
8182         age_param->timeout = age->timeout * 10 - MLX5_AGING_TIME_DELAY;
8183         /* Set expire time in unit of 0.1 sec. */
8184         age_param->port_id = dev->data->port_id;
8185         age_param->expire = age_param->timeout +
8186                         rte_rdtsc() / (rte_get_tsc_hz() / 10);
8187         rte_atomic16_set(&age_param->state, AGE_CANDIDATE);
8188         return counter;
8189 }
8190 /**
8191  * Add Tx queue matcher
8192  *
8193  * @param[in] dev
8194  *   Pointer to the dev struct.
8195  * @param[in, out] matcher
8196  *   Flow matcher.
8197  * @param[in, out] key
8198  *   Flow matcher value.
8199  * @param[in] item
8200  *   Flow pattern to translate.
8201  * @param[in] inner
8202  *   Item is inner pattern.
8203  */
8204 static void
8205 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
8206                                 void *matcher, void *key,
8207                                 const struct rte_flow_item *item)
8208 {
8209         const struct mlx5_rte_flow_item_tx_queue *queue_m;
8210         const struct mlx5_rte_flow_item_tx_queue *queue_v;
8211         void *misc_m =
8212                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8213         void *misc_v =
8214                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8215         struct mlx5_txq_ctrl *txq;
8216         uint32_t queue;
8217
8218
8219         queue_m = (const void *)item->mask;
8220         if (!queue_m)
8221                 return;
8222         queue_v = (const void *)item->spec;
8223         if (!queue_v)
8224                 return;
8225         txq = mlx5_txq_get(dev, queue_v->queue);
8226         if (!txq)
8227                 return;
8228         queue = txq->obj->sq->id;
8229         MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
8230         MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
8231                  queue & queue_m->queue);
8232         mlx5_txq_release(dev, queue_v->queue);
8233 }
8234
8235 /**
8236  * Set the hash fields according to the @p flow information.
8237  *
8238  * @param[in] dev_flow
8239  *   Pointer to the mlx5_flow.
8240  * @param[in] rss_desc
8241  *   Pointer to the mlx5_flow_rss_desc.
8242  */
8243 static void
8244 flow_dv_hashfields_set(struct mlx5_flow *dev_flow,
8245                        struct mlx5_flow_rss_desc *rss_desc)
8246 {
8247         uint64_t items = dev_flow->handle->layers;
8248         int rss_inner = 0;
8249         uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
8250
8251         dev_flow->hash_fields = 0;
8252 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
8253         if (rss_desc->level >= 2) {
8254                 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
8255                 rss_inner = 1;
8256         }
8257 #endif
8258         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
8259             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
8260                 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
8261                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
8262                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
8263                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
8264                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
8265                         else
8266                                 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
8267                 }
8268         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
8269                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
8270                 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
8271                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
8272                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
8273                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
8274                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
8275                         else
8276                                 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
8277                 }
8278         }
8279         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
8280             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
8281                 if (rss_types & ETH_RSS_UDP) {
8282                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
8283                                 dev_flow->hash_fields |=
8284                                                 IBV_RX_HASH_SRC_PORT_UDP;
8285                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
8286                                 dev_flow->hash_fields |=
8287                                                 IBV_RX_HASH_DST_PORT_UDP;
8288                         else
8289                                 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
8290                 }
8291         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
8292                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
8293                 if (rss_types & ETH_RSS_TCP) {
8294                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
8295                                 dev_flow->hash_fields |=
8296                                                 IBV_RX_HASH_SRC_PORT_TCP;
8297                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
8298                                 dev_flow->hash_fields |=
8299                                                 IBV_RX_HASH_DST_PORT_TCP;
8300                         else
8301                                 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
8302                 }
8303         }
8304 }
8305
8306 /**
8307  * Create an Rx Hash queue.
8308  *
8309  * @param dev
8310  *   Pointer to Ethernet device.
8311  * @param[in] dev_flow
8312  *   Pointer to the mlx5_flow.
8313  * @param[in] rss_desc
8314  *   Pointer to the mlx5_flow_rss_desc.
8315  * @param[out] hrxq_idx
8316  *   Hash Rx queue index.
8317  *
8318  * @return
8319  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
8320  */
8321 static struct mlx5_hrxq *
8322 flow_dv_handle_rx_queue(struct rte_eth_dev *dev,
8323                           struct mlx5_flow *dev_flow,
8324                           struct mlx5_flow_rss_desc *rss_desc,
8325                           uint32_t *hrxq_idx)
8326 {
8327         struct mlx5_priv *priv = dev->data->dev_private;
8328         struct mlx5_flow_handle *dh = dev_flow->handle;
8329         struct mlx5_hrxq *hrxq;
8330
8331         MLX5_ASSERT(rss_desc->queue_num);
8332         *hrxq_idx = mlx5_hrxq_get(dev, rss_desc->key,
8333                                  MLX5_RSS_HASH_KEY_LEN,
8334                                  dev_flow->hash_fields,
8335                                  rss_desc->queue,
8336                                  rss_desc->queue_num);
8337         if (!*hrxq_idx) {
8338                 *hrxq_idx = mlx5_hrxq_new
8339                                 (dev, rss_desc->key,
8340                                 MLX5_RSS_HASH_KEY_LEN,
8341                                 dev_flow->hash_fields,
8342                                 rss_desc->queue,
8343                                 rss_desc->queue_num,
8344                                 !!(dh->layers &
8345                                 MLX5_FLOW_LAYER_TUNNEL));
8346                 if (!*hrxq_idx)
8347                         return NULL;
8348         }
8349         hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
8350                               *hrxq_idx);
8351         return hrxq;
8352 }
8353
8354 /**
8355  * Find existing sample resource or create and register a new one.
8356  *
8357  * @param[in, out] dev
8358  *   Pointer to rte_eth_dev structure.
8359  * @param[in] attr
8360  *   Attributes of flow that includes this item.
8361  * @param[in] resource
8362  *   Pointer to sample resource.
8363  * @parm[in, out] dev_flow
8364  *   Pointer to the dev_flow.
8365  * @param[in, out] sample_dv_actions
8366  *   Pointer to sample actions list.
8367  * @param[out] error
8368  *   pointer to error structure.
8369  *
8370  * @return
8371  *   0 on success otherwise -errno and errno is set.
8372  */
8373 static int
8374 flow_dv_sample_resource_register(struct rte_eth_dev *dev,
8375                          const struct rte_flow_attr *attr,
8376                          struct mlx5_flow_dv_sample_resource *resource,
8377                          struct mlx5_flow *dev_flow,
8378                          void **sample_dv_actions,
8379                          struct rte_flow_error *error)
8380 {
8381         struct mlx5_flow_dv_sample_resource *cache_resource;
8382         struct mlx5dv_dr_flow_sampler_attr sampler_attr;
8383         struct mlx5_priv *priv = dev->data->dev_private;
8384         struct mlx5_dev_ctx_shared *sh = priv->sh;
8385         struct mlx5_flow_tbl_resource *tbl;
8386         uint32_t idx = 0;
8387         const uint32_t next_ft_step = 1;
8388         uint32_t next_ft_id = resource->ft_id + next_ft_step;
8389
8390         /* Lookup a matching resource from cache. */
8391         ILIST_FOREACH(sh->ipool[MLX5_IPOOL_SAMPLE], sh->sample_action_list,
8392                       idx, cache_resource, next) {
8393                 if (resource->ratio == cache_resource->ratio &&
8394                     resource->ft_type == cache_resource->ft_type &&
8395                     resource->ft_id == cache_resource->ft_id &&
8396                     resource->set_action == cache_resource->set_action &&
8397                     !memcmp((void *)&resource->sample_act,
8398                             (void *)&cache_resource->sample_act,
8399                             sizeof(struct mlx5_flow_sub_actions_list))) {
8400                         DRV_LOG(DEBUG, "sample resource %p: refcnt %d++",
8401                                 (void *)cache_resource,
8402                                 __atomic_load_n(&cache_resource->refcnt,
8403                                                 __ATOMIC_RELAXED));
8404                         __atomic_fetch_add(&cache_resource->refcnt, 1,
8405                                            __ATOMIC_RELAXED);
8406                         dev_flow->handle->dvh.rix_sample = idx;
8407                         dev_flow->dv.sample_res = cache_resource;
8408                         return 0;
8409                 }
8410         }
8411         /* Register new sample resource. */
8412         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_SAMPLE],
8413                                        &dev_flow->handle->dvh.rix_sample);
8414         if (!cache_resource)
8415                 return rte_flow_error_set(error, ENOMEM,
8416                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8417                                           NULL,
8418                                           "cannot allocate resource memory");
8419         *cache_resource = *resource;
8420         /* Create normal path table level */
8421         tbl = flow_dv_tbl_resource_get(dev, next_ft_id,
8422                                         attr->egress, attr->transfer, error);
8423         if (!tbl) {
8424                 rte_flow_error_set(error, ENOMEM,
8425                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8426                                           NULL,
8427                                           "fail to create normal path table "
8428                                           "for sample");
8429                 goto error;
8430         }
8431         cache_resource->normal_path_tbl = tbl;
8432         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB) {
8433                 cache_resource->default_miss =
8434                                 mlx5_glue->dr_create_flow_action_default_miss();
8435                 if (!cache_resource->default_miss) {
8436                         rte_flow_error_set(error, ENOMEM,
8437                                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8438                                                 NULL,
8439                                                 "cannot create default miss "
8440                                                 "action");
8441                         goto error;
8442                 }
8443                 sample_dv_actions[resource->sample_act.actions_num++] =
8444                                                 cache_resource->default_miss;
8445         }
8446         /* Create a DR sample action */
8447         sampler_attr.sample_ratio = cache_resource->ratio;
8448         sampler_attr.default_next_table = tbl->obj;
8449         sampler_attr.num_sample_actions = resource->sample_act.actions_num;
8450         sampler_attr.sample_actions = (struct mlx5dv_dr_action **)
8451                                                         &sample_dv_actions[0];
8452         sampler_attr.action = cache_resource->set_action;
8453         cache_resource->verbs_action =
8454                 mlx5_glue->dr_create_flow_action_sampler(&sampler_attr);
8455         if (!cache_resource->verbs_action) {
8456                 rte_flow_error_set(error, ENOMEM,
8457                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8458                                         NULL, "cannot create sample action");
8459                 goto error;
8460         }
8461         __atomic_store_n(&cache_resource->refcnt, 1, __ATOMIC_RELAXED);
8462         ILIST_INSERT(sh->ipool[MLX5_IPOOL_SAMPLE], &sh->sample_action_list,
8463                      dev_flow->handle->dvh.rix_sample, cache_resource,
8464                      next);
8465         dev_flow->dv.sample_res = cache_resource;
8466         DRV_LOG(DEBUG, "new sample resource %p: refcnt %d++",
8467                 (void *)cache_resource,
8468                 __atomic_load_n(&cache_resource->refcnt, __ATOMIC_RELAXED));
8469         return 0;
8470 error:
8471         if (cache_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB) {
8472                 if (cache_resource->default_miss)
8473                         claim_zero(mlx5_glue->destroy_flow_action
8474                                 (cache_resource->default_miss));
8475         } else {
8476                 if (cache_resource->sample_idx.rix_hrxq &&
8477                     !mlx5_hrxq_release(dev,
8478                                 cache_resource->sample_idx.rix_hrxq))
8479                         cache_resource->sample_idx.rix_hrxq = 0;
8480                 if (cache_resource->sample_idx.rix_tag &&
8481                     !flow_dv_tag_release(dev,
8482                                 cache_resource->sample_idx.rix_tag))
8483                         cache_resource->sample_idx.rix_tag = 0;
8484                 if (cache_resource->sample_idx.cnt) {
8485                         flow_dv_counter_release(dev,
8486                                 cache_resource->sample_idx.cnt);
8487                         cache_resource->sample_idx.cnt = 0;
8488                 }
8489         }
8490         if (cache_resource->normal_path_tbl)
8491                 flow_dv_tbl_resource_release(dev,
8492                                 cache_resource->normal_path_tbl);
8493         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_SAMPLE],
8494                                 dev_flow->handle->dvh.rix_sample);
8495         dev_flow->handle->dvh.rix_sample = 0;
8496         return -rte_errno;
8497 }
8498
8499 /**
8500  * Convert Sample action to DV specification.
8501  *
8502  * @param[in] dev
8503  *   Pointer to rte_eth_dev structure.
8504  * @param[in] action
8505  *   Pointer to action structure.
8506  * @param[in, out] dev_flow
8507  *   Pointer to the mlx5_flow.
8508  * @param[in] attr
8509  *   Pointer to the flow attributes.
8510  * @param[in, out] sample_actions
8511  *   Pointer to sample actions list.
8512  * @param[in, out] res
8513  *   Pointer to sample resource.
8514  * @param[out] error
8515  *   Pointer to the error structure.
8516  *
8517  * @return
8518  *   0 on success, a negative errno value otherwise and rte_errno is set.
8519  */
8520 static int
8521 flow_dv_translate_action_sample(struct rte_eth_dev *dev,
8522                                 const struct rte_flow_action *action,
8523                                 struct mlx5_flow *dev_flow,
8524                                 const struct rte_flow_attr *attr,
8525                                 void **sample_actions,
8526                                 struct mlx5_flow_dv_sample_resource *res,
8527                                 struct rte_flow_error *error)
8528 {
8529         struct mlx5_priv *priv = dev->data->dev_private;
8530         const struct rte_flow_action_sample *sample_action;
8531         const struct rte_flow_action *sub_actions;
8532         const struct rte_flow_action_queue *queue;
8533         struct mlx5_flow_sub_actions_list *sample_act;
8534         struct mlx5_flow_sub_actions_idx *sample_idx;
8535         struct mlx5_flow_rss_desc *rss_desc = &((struct mlx5_flow_rss_desc *)
8536                                               priv->rss_desc)
8537                                               [!!priv->flow_nested_idx];
8538         uint64_t action_flags = 0;
8539
8540         sample_act = &res->sample_act;
8541         sample_idx = &res->sample_idx;
8542         sample_action = (const struct rte_flow_action_sample *)action->conf;
8543         res->ratio = sample_action->ratio;
8544         sub_actions = sample_action->actions;
8545         for (; sub_actions->type != RTE_FLOW_ACTION_TYPE_END; sub_actions++) {
8546                 int type = sub_actions->type;
8547                 uint32_t pre_rix = 0;
8548                 void *pre_r;
8549                 switch (type) {
8550                 case RTE_FLOW_ACTION_TYPE_QUEUE:
8551                 {
8552                         struct mlx5_hrxq *hrxq;
8553                         uint32_t hrxq_idx;
8554
8555                         queue = sub_actions->conf;
8556                         rss_desc->queue_num = 1;
8557                         rss_desc->queue[0] = queue->index;
8558                         hrxq = flow_dv_handle_rx_queue(dev, dev_flow,
8559                                         rss_desc, &hrxq_idx);
8560                         if (!hrxq)
8561                                 return rte_flow_error_set
8562                                         (error, rte_errno,
8563                                          RTE_FLOW_ERROR_TYPE_ACTION,
8564                                          NULL,
8565                                          "cannot create fate queue");
8566                         sample_act->dr_queue_action = hrxq->action;
8567                         sample_idx->rix_hrxq = hrxq_idx;
8568                         sample_actions[sample_act->actions_num++] =
8569                                                 hrxq->action;
8570                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
8571                         if (action_flags & MLX5_FLOW_ACTION_MARK)
8572                                 dev_flow->handle->rix_hrxq = hrxq_idx;
8573                         dev_flow->handle->fate_action =
8574                                         MLX5_FLOW_FATE_QUEUE;
8575                         break;
8576                 }
8577                 case RTE_FLOW_ACTION_TYPE_MARK:
8578                 {
8579                         uint32_t tag_be = mlx5_flow_mark_set
8580                                 (((const struct rte_flow_action_mark *)
8581                                 (sub_actions->conf))->id);
8582                         dev_flow->handle->mark = 1;
8583                         pre_rix = dev_flow->handle->dvh.rix_tag;
8584                         /* Save the mark resource before sample */
8585                         pre_r = dev_flow->dv.tag_resource;
8586                         if (flow_dv_tag_resource_register(dev, tag_be,
8587                                                   dev_flow, error))
8588                                 return -rte_errno;
8589                         MLX5_ASSERT(dev_flow->dv.tag_resource);
8590                         sample_act->dr_tag_action =
8591                                 dev_flow->dv.tag_resource->action;
8592                         sample_idx->rix_tag =
8593                                 dev_flow->handle->dvh.rix_tag;
8594                         sample_actions[sample_act->actions_num++] =
8595                                                 sample_act->dr_tag_action;
8596                         /* Recover the mark resource after sample */
8597                         dev_flow->dv.tag_resource = pre_r;
8598                         dev_flow->handle->dvh.rix_tag = pre_rix;
8599                         action_flags |= MLX5_FLOW_ACTION_MARK;
8600                         break;
8601                 }
8602                 case RTE_FLOW_ACTION_TYPE_COUNT:
8603                 {
8604                         uint32_t counter;
8605
8606                         counter = flow_dv_translate_create_counter(dev,
8607                                         dev_flow, sub_actions->conf, 0);
8608                         if (!counter)
8609                                 return rte_flow_error_set
8610                                                 (error, rte_errno,
8611                                                  RTE_FLOW_ERROR_TYPE_ACTION,
8612                                                  NULL,
8613                                                  "cannot create counter"
8614                                                  " object.");
8615                         sample_idx->cnt = counter;
8616                         sample_act->dr_cnt_action =
8617                                   (flow_dv_counter_get_by_idx(dev,
8618                                   counter, NULL))->action;
8619                         sample_actions[sample_act->actions_num++] =
8620                                                 sample_act->dr_cnt_action;
8621                         action_flags |= MLX5_FLOW_ACTION_COUNT;
8622                         break;
8623                 }
8624                 default:
8625                         return rte_flow_error_set(error, EINVAL,
8626                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8627                                 NULL,
8628                                 "Not support for sampler action");
8629                 }
8630         }
8631         sample_act->action_flags = action_flags;
8632         res->ft_id = dev_flow->dv.group;
8633         if (attr->transfer) {
8634                 union {
8635                         uint32_t action_in[MLX5_ST_SZ_DW(set_action_in)];
8636                         uint64_t set_action;
8637                 } action_ctx = { .set_action = 0 };
8638
8639                 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
8640                 MLX5_SET(set_action_in, action_ctx.action_in, action_type,
8641                          MLX5_MODIFICATION_TYPE_SET);
8642                 MLX5_SET(set_action_in, action_ctx.action_in, field,
8643                          MLX5_MODI_META_REG_C_0);
8644                 MLX5_SET(set_action_in, action_ctx.action_in, data,
8645                          priv->vport_meta_tag);
8646                 res->set_action = action_ctx.set_action;
8647         } else if (attr->ingress) {
8648                 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
8649         }
8650         return 0;
8651 }
8652
8653 /**
8654  * Convert Sample action to DV specification.
8655  *
8656  * @param[in] dev
8657  *   Pointer to rte_eth_dev structure.
8658  * @param[in, out] dev_flow
8659  *   Pointer to the mlx5_flow.
8660  * @param[in] attr
8661  *   Pointer to the flow attributes.
8662  * @param[in, out] res
8663  *   Pointer to sample resource.
8664  * @param[in] sample_actions
8665  *   Pointer to sample path actions list.
8666  * @param[out] error
8667  *   Pointer to the error structure.
8668  *
8669  * @return
8670  *   0 on success, a negative errno value otherwise and rte_errno is set.
8671  */
8672 static int
8673 flow_dv_create_action_sample(struct rte_eth_dev *dev,
8674                                 struct mlx5_flow *dev_flow,
8675                                 const struct rte_flow_attr *attr,
8676                                 struct mlx5_flow_dv_sample_resource *res,
8677                                 void **sample_actions,
8678                                 struct rte_flow_error *error)
8679 {
8680         if (flow_dv_sample_resource_register(dev, attr, res, dev_flow,
8681                                                 sample_actions, error))
8682                 return rte_flow_error_set(error, EINVAL,
8683                                           RTE_FLOW_ERROR_TYPE_ACTION,
8684                                           NULL, "can't create sample action");
8685         return 0;
8686 }
8687
8688 /**
8689  * Fill the flow with DV spec, lock free
8690  * (mutex should be acquired by caller).
8691  *
8692  * @param[in] dev
8693  *   Pointer to rte_eth_dev structure.
8694  * @param[in, out] dev_flow
8695  *   Pointer to the sub flow.
8696  * @param[in] attr
8697  *   Pointer to the flow attributes.
8698  * @param[in] items
8699  *   Pointer to the list of items.
8700  * @param[in] actions
8701  *   Pointer to the list of actions.
8702  * @param[out] error
8703  *   Pointer to the error structure.
8704  *
8705  * @return
8706  *   0 on success, a negative errno value otherwise and rte_errno is set.
8707  */
8708 static int
8709 __flow_dv_translate(struct rte_eth_dev *dev,
8710                     struct mlx5_flow *dev_flow,
8711                     const struct rte_flow_attr *attr,
8712                     const struct rte_flow_item items[],
8713                     const struct rte_flow_action actions[],
8714                     struct rte_flow_error *error)
8715 {
8716         struct mlx5_priv *priv = dev->data->dev_private;
8717         struct mlx5_dev_config *dev_conf = &priv->config;
8718         struct rte_flow *flow = dev_flow->flow;
8719         struct mlx5_flow_handle *handle = dev_flow->handle;
8720         struct mlx5_flow_rss_desc *rss_desc = &((struct mlx5_flow_rss_desc *)
8721                                               priv->rss_desc)
8722                                               [!!priv->flow_nested_idx];
8723         uint64_t item_flags = 0;
8724         uint64_t last_item = 0;
8725         uint64_t action_flags = 0;
8726         uint64_t priority = attr->priority;
8727         struct mlx5_flow_dv_matcher matcher = {
8728                 .mask = {
8729                         .size = sizeof(matcher.mask.buf) -
8730                                 MLX5_ST_SZ_BYTES(fte_match_set_misc4),
8731                 },
8732         };
8733         int actions_n = 0;
8734         bool actions_end = false;
8735         union {
8736                 struct mlx5_flow_dv_modify_hdr_resource res;
8737                 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
8738                             sizeof(struct mlx5_modification_cmd) *
8739                             (MLX5_MAX_MODIFY_NUM + 1)];
8740         } mhdr_dummy;
8741         struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
8742         const struct rte_flow_action_count *count = NULL;
8743         const struct rte_flow_action_age *age = NULL;
8744         union flow_dv_attr flow_attr = { .attr = 0 };
8745         uint32_t tag_be;
8746         union mlx5_flow_tbl_key tbl_key;
8747         uint32_t modify_action_position = UINT32_MAX;
8748         void *match_mask = matcher.mask.buf;
8749         void *match_value = dev_flow->dv.value.buf;
8750         uint8_t next_protocol = 0xff;
8751         struct rte_vlan_hdr vlan = { 0 };
8752         struct mlx5_flow_dv_sample_resource sample_res;
8753         void *sample_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
8754         uint32_t sample_act_pos = UINT32_MAX;
8755         uint32_t table;
8756         int ret = 0;
8757
8758         memset(&sample_res, 0, sizeof(struct mlx5_flow_dv_sample_resource));
8759         mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
8760                                            MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
8761         ret = mlx5_flow_group_to_table(attr, dev_flow->external, attr->group,
8762                                        !!priv->fdb_def_rule, &table, error);
8763         if (ret)
8764                 return ret;
8765         dev_flow->dv.group = table;
8766         if (attr->transfer)
8767                 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
8768         if (priority == MLX5_FLOW_PRIO_RSVD)
8769                 priority = dev_conf->flow_prio - 1;
8770         /* number of actions must be set to 0 in case of dirty stack. */
8771         mhdr_res->actions_num = 0;
8772         for (; !actions_end ; actions++) {
8773                 const struct rte_flow_action_queue *queue;
8774                 const struct rte_flow_action_rss *rss;
8775                 const struct rte_flow_action *action = actions;
8776                 const uint8_t *rss_key;
8777                 const struct rte_flow_action_meter *mtr;
8778                 struct mlx5_flow_tbl_resource *tbl;
8779                 uint32_t port_id = 0;
8780                 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
8781                 int action_type = actions->type;
8782                 const struct rte_flow_action *found_action = NULL;
8783                 struct mlx5_flow_meter *fm = NULL;
8784                 uint32_t jump_group = 0;
8785
8786                 if (!mlx5_flow_os_action_supported(action_type))
8787                         return rte_flow_error_set(error, ENOTSUP,
8788                                                   RTE_FLOW_ERROR_TYPE_ACTION,
8789                                                   actions,
8790                                                   "action not supported");
8791                 switch (action_type) {
8792                 case RTE_FLOW_ACTION_TYPE_VOID:
8793                         break;
8794                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
8795                         if (flow_dv_translate_action_port_id(dev, action,
8796                                                              &port_id, error))
8797                                 return -rte_errno;
8798                         port_id_resource.port_id = port_id;
8799                         MLX5_ASSERT(!handle->rix_port_id_action);
8800                         if (flow_dv_port_id_action_resource_register
8801                             (dev, &port_id_resource, dev_flow, error))
8802                                 return -rte_errno;
8803                         dev_flow->dv.actions[actions_n++] =
8804                                         dev_flow->dv.port_id_action->action;
8805                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
8806                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_PORT_ID;
8807                         break;
8808                 case RTE_FLOW_ACTION_TYPE_FLAG:
8809                         action_flags |= MLX5_FLOW_ACTION_FLAG;
8810                         dev_flow->handle->mark = 1;
8811                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
8812                                 struct rte_flow_action_mark mark = {
8813                                         .id = MLX5_FLOW_MARK_DEFAULT,
8814                                 };
8815
8816                                 if (flow_dv_convert_action_mark(dev, &mark,
8817                                                                 mhdr_res,
8818                                                                 error))
8819                                         return -rte_errno;
8820                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
8821                                 break;
8822                         }
8823                         tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
8824                         /*
8825                          * Only one FLAG or MARK is supported per device flow
8826                          * right now. So the pointer to the tag resource must be
8827                          * zero before the register process.
8828                          */
8829                         MLX5_ASSERT(!handle->dvh.rix_tag);
8830                         if (flow_dv_tag_resource_register(dev, tag_be,
8831                                                           dev_flow, error))
8832                                 return -rte_errno;
8833                         MLX5_ASSERT(dev_flow->dv.tag_resource);
8834                         dev_flow->dv.actions[actions_n++] =
8835                                         dev_flow->dv.tag_resource->action;
8836                         break;
8837                 case RTE_FLOW_ACTION_TYPE_MARK:
8838                         action_flags |= MLX5_FLOW_ACTION_MARK;
8839                         dev_flow->handle->mark = 1;
8840                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
8841                                 const struct rte_flow_action_mark *mark =
8842                                         (const struct rte_flow_action_mark *)
8843                                                 actions->conf;
8844
8845                                 if (flow_dv_convert_action_mark(dev, mark,
8846                                                                 mhdr_res,
8847                                                                 error))
8848                                         return -rte_errno;
8849                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
8850                                 break;
8851                         }
8852                         /* Fall-through */
8853                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
8854                         /* Legacy (non-extensive) MARK action. */
8855                         tag_be = mlx5_flow_mark_set
8856                               (((const struct rte_flow_action_mark *)
8857                                (actions->conf))->id);
8858                         MLX5_ASSERT(!handle->dvh.rix_tag);
8859                         if (flow_dv_tag_resource_register(dev, tag_be,
8860                                                           dev_flow, error))
8861                                 return -rte_errno;
8862                         MLX5_ASSERT(dev_flow->dv.tag_resource);
8863                         dev_flow->dv.actions[actions_n++] =
8864                                         dev_flow->dv.tag_resource->action;
8865                         break;
8866                 case RTE_FLOW_ACTION_TYPE_SET_META:
8867                         if (flow_dv_convert_action_set_meta
8868                                 (dev, mhdr_res, attr,
8869                                  (const struct rte_flow_action_set_meta *)
8870                                   actions->conf, error))
8871                                 return -rte_errno;
8872                         action_flags |= MLX5_FLOW_ACTION_SET_META;
8873                         break;
8874                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
8875                         if (flow_dv_convert_action_set_tag
8876                                 (dev, mhdr_res,
8877                                  (const struct rte_flow_action_set_tag *)
8878                                   actions->conf, error))
8879                                 return -rte_errno;
8880                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
8881                         break;
8882                 case RTE_FLOW_ACTION_TYPE_DROP:
8883                         action_flags |= MLX5_FLOW_ACTION_DROP;
8884                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_DROP;
8885                         break;
8886                 case RTE_FLOW_ACTION_TYPE_QUEUE:
8887                         queue = actions->conf;
8888                         rss_desc->queue_num = 1;
8889                         rss_desc->queue[0] = queue->index;
8890                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
8891                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
8892                         break;
8893                 case RTE_FLOW_ACTION_TYPE_RSS:
8894                         rss = actions->conf;
8895                         memcpy(rss_desc->queue, rss->queue,
8896                                rss->queue_num * sizeof(uint16_t));
8897                         rss_desc->queue_num = rss->queue_num;
8898                         /* NULL RSS key indicates default RSS key. */
8899                         rss_key = !rss->key ? rss_hash_default_key : rss->key;
8900                         memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
8901                         /*
8902                          * rss->level and rss.types should be set in advance
8903                          * when expanding items for RSS.
8904                          */
8905                         action_flags |= MLX5_FLOW_ACTION_RSS;
8906                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
8907                         break;
8908                 case RTE_FLOW_ACTION_TYPE_AGE:
8909                 case RTE_FLOW_ACTION_TYPE_COUNT:
8910                         if (!dev_conf->devx) {
8911                                 return rte_flow_error_set
8912                                               (error, ENOTSUP,
8913                                                RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8914                                                NULL,
8915                                                "count action not supported");
8916                         }
8917                         /* Save information first, will apply later. */
8918                         if (actions->type == RTE_FLOW_ACTION_TYPE_COUNT)
8919                                 count = action->conf;
8920                         else
8921                                 age = action->conf;
8922                         action_flags |= MLX5_FLOW_ACTION_COUNT;
8923                         break;
8924                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
8925                         dev_flow->dv.actions[actions_n++] =
8926                                                 priv->sh->pop_vlan_action;
8927                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
8928                         break;
8929                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
8930                         if (!(action_flags &
8931                               MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
8932                                 flow_dev_get_vlan_info_from_items(items, &vlan);
8933                         vlan.eth_proto = rte_be_to_cpu_16
8934                              ((((const struct rte_flow_action_of_push_vlan *)
8935                                                    actions->conf)->ethertype));
8936                         found_action = mlx5_flow_find_action
8937                                         (actions + 1,
8938                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
8939                         if (found_action)
8940                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
8941                         found_action = mlx5_flow_find_action
8942                                         (actions + 1,
8943                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
8944                         if (found_action)
8945                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
8946                         if (flow_dv_create_action_push_vlan
8947                                             (dev, attr, &vlan, dev_flow, error))
8948                                 return -rte_errno;
8949                         dev_flow->dv.actions[actions_n++] =
8950                                         dev_flow->dv.push_vlan_res->action;
8951                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
8952                         break;
8953                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
8954                         /* of_vlan_push action handled this action */
8955                         MLX5_ASSERT(action_flags &
8956                                     MLX5_FLOW_ACTION_OF_PUSH_VLAN);
8957                         break;
8958                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
8959                         if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
8960                                 break;
8961                         flow_dev_get_vlan_info_from_items(items, &vlan);
8962                         mlx5_update_vlan_vid_pcp(actions, &vlan);
8963                         /* If no VLAN push - this is a modify header action */
8964                         if (flow_dv_convert_action_modify_vlan_vid
8965                                                 (mhdr_res, actions, error))
8966                                 return -rte_errno;
8967                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
8968                         break;
8969                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
8970                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
8971                         if (flow_dv_create_action_l2_encap(dev, actions,
8972                                                            dev_flow,
8973                                                            attr->transfer,
8974                                                            error))
8975                                 return -rte_errno;
8976                         dev_flow->dv.actions[actions_n++] =
8977                                         dev_flow->dv.encap_decap->action;
8978                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
8979                         break;
8980                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
8981                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
8982                         if (flow_dv_create_action_l2_decap(dev, dev_flow,
8983                                                            attr->transfer,
8984                                                            error))
8985                                 return -rte_errno;
8986                         dev_flow->dv.actions[actions_n++] =
8987                                         dev_flow->dv.encap_decap->action;
8988                         action_flags |= MLX5_FLOW_ACTION_DECAP;
8989                         break;
8990                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
8991                         /* Handle encap with preceding decap. */
8992                         if (action_flags & MLX5_FLOW_ACTION_DECAP) {
8993                                 if (flow_dv_create_action_raw_encap
8994                                         (dev, actions, dev_flow, attr, error))
8995                                         return -rte_errno;
8996                                 dev_flow->dv.actions[actions_n++] =
8997                                         dev_flow->dv.encap_decap->action;
8998                         } else {
8999                                 /* Handle encap without preceding decap. */
9000                                 if (flow_dv_create_action_l2_encap
9001                                     (dev, actions, dev_flow, attr->transfer,
9002                                      error))
9003                                         return -rte_errno;
9004                                 dev_flow->dv.actions[actions_n++] =
9005                                         dev_flow->dv.encap_decap->action;
9006                         }
9007                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
9008                         break;
9009                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
9010                         while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
9011                                 ;
9012                         if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
9013                                 if (flow_dv_create_action_l2_decap
9014                                     (dev, dev_flow, attr->transfer, error))
9015                                         return -rte_errno;
9016                                 dev_flow->dv.actions[actions_n++] =
9017                                         dev_flow->dv.encap_decap->action;
9018                         }
9019                         /* If decap is followed by encap, handle it at encap. */
9020                         action_flags |= MLX5_FLOW_ACTION_DECAP;
9021                         break;
9022                 case RTE_FLOW_ACTION_TYPE_JUMP:
9023                         jump_group = ((const struct rte_flow_action_jump *)
9024                                                         action->conf)->group;
9025                         if (dev_flow->external && jump_group <
9026                                         MLX5_MAX_TABLES_EXTERNAL)
9027                                 jump_group *= MLX5_FLOW_TABLE_FACTOR;
9028                         ret = mlx5_flow_group_to_table(attr, dev_flow->external,
9029                                                        jump_group,
9030                                                        !!priv->fdb_def_rule,
9031                                                        &table, error);
9032                         if (ret)
9033                                 return ret;
9034                         tbl = flow_dv_tbl_resource_get(dev, table,
9035                                                        attr->egress,
9036                                                        attr->transfer, error);
9037                         if (!tbl)
9038                                 return rte_flow_error_set
9039                                                 (error, errno,
9040                                                  RTE_FLOW_ERROR_TYPE_ACTION,
9041                                                  NULL,
9042                                                  "cannot create jump action.");
9043                         if (flow_dv_jump_tbl_resource_register
9044                             (dev, tbl, dev_flow, error)) {
9045                                 flow_dv_tbl_resource_release(dev, tbl);
9046                                 return rte_flow_error_set
9047                                                 (error, errno,
9048                                                  RTE_FLOW_ERROR_TYPE_ACTION,
9049                                                  NULL,
9050                                                  "cannot create jump action.");
9051                         }
9052                         dev_flow->dv.actions[actions_n++] =
9053                                         dev_flow->dv.jump->action;
9054                         action_flags |= MLX5_FLOW_ACTION_JUMP;
9055                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_JUMP;
9056                         break;
9057                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
9058                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
9059                         if (flow_dv_convert_action_modify_mac
9060                                         (mhdr_res, actions, error))
9061                                 return -rte_errno;
9062                         action_flags |= actions->type ==
9063                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
9064                                         MLX5_FLOW_ACTION_SET_MAC_SRC :
9065                                         MLX5_FLOW_ACTION_SET_MAC_DST;
9066                         break;
9067                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
9068                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
9069                         if (flow_dv_convert_action_modify_ipv4
9070                                         (mhdr_res, actions, error))
9071                                 return -rte_errno;
9072                         action_flags |= actions->type ==
9073                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
9074                                         MLX5_FLOW_ACTION_SET_IPV4_SRC :
9075                                         MLX5_FLOW_ACTION_SET_IPV4_DST;
9076                         break;
9077                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
9078                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
9079                         if (flow_dv_convert_action_modify_ipv6
9080                                         (mhdr_res, actions, error))
9081                                 return -rte_errno;
9082                         action_flags |= actions->type ==
9083                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
9084                                         MLX5_FLOW_ACTION_SET_IPV6_SRC :
9085                                         MLX5_FLOW_ACTION_SET_IPV6_DST;
9086                         break;
9087                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
9088                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
9089                         if (flow_dv_convert_action_modify_tp
9090                                         (mhdr_res, actions, items,
9091                                          &flow_attr, dev_flow, !!(action_flags &
9092                                          MLX5_FLOW_ACTION_DECAP), error))
9093                                 return -rte_errno;
9094                         action_flags |= actions->type ==
9095                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
9096                                         MLX5_FLOW_ACTION_SET_TP_SRC :
9097                                         MLX5_FLOW_ACTION_SET_TP_DST;
9098                         break;
9099                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
9100                         if (flow_dv_convert_action_modify_dec_ttl
9101                                         (mhdr_res, items, &flow_attr, dev_flow,
9102                                          !!(action_flags &
9103                                          MLX5_FLOW_ACTION_DECAP), error))
9104                                 return -rte_errno;
9105                         action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
9106                         break;
9107                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
9108                         if (flow_dv_convert_action_modify_ttl
9109                                         (mhdr_res, actions, items, &flow_attr,
9110                                          dev_flow, !!(action_flags &
9111                                          MLX5_FLOW_ACTION_DECAP), error))
9112                                 return -rte_errno;
9113                         action_flags |= MLX5_FLOW_ACTION_SET_TTL;
9114                         break;
9115                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
9116                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
9117                         if (flow_dv_convert_action_modify_tcp_seq
9118                                         (mhdr_res, actions, error))
9119                                 return -rte_errno;
9120                         action_flags |= actions->type ==
9121                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
9122                                         MLX5_FLOW_ACTION_INC_TCP_SEQ :
9123                                         MLX5_FLOW_ACTION_DEC_TCP_SEQ;
9124                         break;
9125
9126                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
9127                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
9128                         if (flow_dv_convert_action_modify_tcp_ack
9129                                         (mhdr_res, actions, error))
9130                                 return -rte_errno;
9131                         action_flags |= actions->type ==
9132                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
9133                                         MLX5_FLOW_ACTION_INC_TCP_ACK :
9134                                         MLX5_FLOW_ACTION_DEC_TCP_ACK;
9135                         break;
9136                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
9137                         if (flow_dv_convert_action_set_reg
9138                                         (mhdr_res, actions, error))
9139                                 return -rte_errno;
9140                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
9141                         break;
9142                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
9143                         if (flow_dv_convert_action_copy_mreg
9144                                         (dev, mhdr_res, actions, error))
9145                                 return -rte_errno;
9146                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
9147                         break;
9148                 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
9149                         action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
9150                         dev_flow->handle->fate_action =
9151                                         MLX5_FLOW_FATE_DEFAULT_MISS;
9152                         break;
9153                 case RTE_FLOW_ACTION_TYPE_METER:
9154                         mtr = actions->conf;
9155                         if (!flow->meter) {
9156                                 fm = mlx5_flow_meter_attach(priv, mtr->mtr_id,
9157                                                             attr, error);
9158                                 if (!fm)
9159                                         return rte_flow_error_set(error,
9160                                                 rte_errno,
9161                                                 RTE_FLOW_ERROR_TYPE_ACTION,
9162                                                 NULL,
9163                                                 "meter not found "
9164                                                 "or invalid parameters");
9165                                 flow->meter = fm->idx;
9166                         }
9167                         /* Set the meter action. */
9168                         if (!fm) {
9169                                 fm = mlx5_ipool_get(priv->sh->ipool
9170                                                 [MLX5_IPOOL_MTR], flow->meter);
9171                                 if (!fm)
9172                                         return rte_flow_error_set(error,
9173                                                 rte_errno,
9174                                                 RTE_FLOW_ERROR_TYPE_ACTION,
9175                                                 NULL,
9176                                                 "meter not found "
9177                                                 "or invalid parameters");
9178                         }
9179                         dev_flow->dv.actions[actions_n++] =
9180                                 fm->mfts->meter_action;
9181                         action_flags |= MLX5_FLOW_ACTION_METER;
9182                         break;
9183                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
9184                         if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
9185                                                               actions, error))
9186                                 return -rte_errno;
9187                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
9188                         break;
9189                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
9190                         if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
9191                                                               actions, error))
9192                                 return -rte_errno;
9193                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
9194                         break;
9195                 case RTE_FLOW_ACTION_TYPE_SAMPLE:
9196                         sample_act_pos = actions_n;
9197                         ret = flow_dv_translate_action_sample(dev,
9198                                                               actions,
9199                                                               dev_flow, attr,
9200                                                               sample_actions,
9201                                                               &sample_res,
9202                                                               error);
9203                         if (ret < 0)
9204                                 return ret;
9205                         actions_n++;
9206                         action_flags |= MLX5_FLOW_ACTION_SAMPLE;
9207                         break;
9208                 case RTE_FLOW_ACTION_TYPE_END:
9209                         actions_end = true;
9210                         if (mhdr_res->actions_num) {
9211                                 /* create modify action if needed. */
9212                                 if (flow_dv_modify_hdr_resource_register
9213                                         (dev, mhdr_res, dev_flow, error))
9214                                         return -rte_errno;
9215                                 dev_flow->dv.actions[modify_action_position] =
9216                                         handle->dvh.modify_hdr->action;
9217                         }
9218                         if (action_flags & MLX5_FLOW_ACTION_COUNT) {
9219                                 flow->counter =
9220                                         flow_dv_translate_create_counter(dev,
9221                                                 dev_flow, count, age);
9222
9223                                 if (!flow->counter)
9224                                         return rte_flow_error_set
9225                                                 (error, rte_errno,
9226                                                 RTE_FLOW_ERROR_TYPE_ACTION,
9227                                                 NULL,
9228                                                 "cannot create counter"
9229                                                 " object.");
9230                                 dev_flow->dv.actions[actions_n++] =
9231                                           (flow_dv_counter_get_by_idx(dev,
9232                                           flow->counter, NULL))->action;
9233                         }
9234                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE) {
9235                                 ret = flow_dv_create_action_sample(dev,
9236                                                           dev_flow, attr,
9237                                                           &sample_res,
9238                                                           sample_actions,
9239                                                           error);
9240                                 if (ret < 0)
9241                                         return rte_flow_error_set
9242                                                 (error, rte_errno,
9243                                                 RTE_FLOW_ERROR_TYPE_ACTION,
9244                                                 NULL,
9245                                                 "cannot create sample action");
9246                                 dev_flow->dv.actions[sample_act_pos] =
9247                                         dev_flow->dv.sample_res->verbs_action;
9248                         }
9249                         break;
9250                 default:
9251                         break;
9252                 }
9253                 if (mhdr_res->actions_num &&
9254                     modify_action_position == UINT32_MAX)
9255                         modify_action_position = actions_n++;
9256         }
9257         dev_flow->dv.actions_n = actions_n;
9258         dev_flow->act_flags = action_flags;
9259         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
9260                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
9261                 int item_type = items->type;
9262
9263                 if (!mlx5_flow_os_item_supported(item_type))
9264                         return rte_flow_error_set(error, ENOTSUP,
9265                                                   RTE_FLOW_ERROR_TYPE_ITEM,
9266                                                   NULL, "item not supported");
9267                 switch (item_type) {
9268                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
9269                         flow_dv_translate_item_port_id(dev, match_mask,
9270                                                        match_value, items);
9271                         last_item = MLX5_FLOW_ITEM_PORT_ID;
9272                         break;
9273                 case RTE_FLOW_ITEM_TYPE_ETH:
9274                         flow_dv_translate_item_eth(match_mask, match_value,
9275                                                    items, tunnel,
9276                                                    dev_flow->dv.group);
9277                         matcher.priority = action_flags &
9278                                         MLX5_FLOW_ACTION_DEFAULT_MISS &&
9279                                         !dev_flow->external ?
9280                                         MLX5_PRIORITY_MAP_L3 :
9281                                         MLX5_PRIORITY_MAP_L2;
9282                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
9283                                              MLX5_FLOW_LAYER_OUTER_L2;
9284                         break;
9285                 case RTE_FLOW_ITEM_TYPE_VLAN:
9286                         flow_dv_translate_item_vlan(dev_flow,
9287                                                     match_mask, match_value,
9288                                                     items, tunnel,
9289                                                     dev_flow->dv.group);
9290                         matcher.priority = MLX5_PRIORITY_MAP_L2;
9291                         last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
9292                                               MLX5_FLOW_LAYER_INNER_VLAN) :
9293                                              (MLX5_FLOW_LAYER_OUTER_L2 |
9294                                               MLX5_FLOW_LAYER_OUTER_VLAN);
9295                         break;
9296                 case RTE_FLOW_ITEM_TYPE_IPV4:
9297                         mlx5_flow_tunnel_ip_check(items, next_protocol,
9298                                                   &item_flags, &tunnel);
9299                         flow_dv_translate_item_ipv4(match_mask, match_value,
9300                                                     items, item_flags, tunnel,
9301                                                     dev_flow->dv.group);
9302                         matcher.priority = MLX5_PRIORITY_MAP_L3;
9303                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
9304                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
9305                         if (items->mask != NULL &&
9306                             ((const struct rte_flow_item_ipv4 *)
9307                              items->mask)->hdr.next_proto_id) {
9308                                 next_protocol =
9309                                         ((const struct rte_flow_item_ipv4 *)
9310                                          (items->spec))->hdr.next_proto_id;
9311                                 next_protocol &=
9312                                         ((const struct rte_flow_item_ipv4 *)
9313                                          (items->mask))->hdr.next_proto_id;
9314                         } else {
9315                                 /* Reset for inner layer. */
9316                                 next_protocol = 0xff;
9317                         }
9318                         break;
9319                 case RTE_FLOW_ITEM_TYPE_IPV6:
9320                         mlx5_flow_tunnel_ip_check(items, next_protocol,
9321                                                   &item_flags, &tunnel);
9322                         flow_dv_translate_item_ipv6(match_mask, match_value,
9323                                                     items, item_flags, tunnel,
9324                                                     dev_flow->dv.group);
9325                         matcher.priority = MLX5_PRIORITY_MAP_L3;
9326                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
9327                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
9328                         if (items->mask != NULL &&
9329                             ((const struct rte_flow_item_ipv6 *)
9330                              items->mask)->hdr.proto) {
9331                                 next_protocol =
9332                                         ((const struct rte_flow_item_ipv6 *)
9333                                          items->spec)->hdr.proto;
9334                                 next_protocol &=
9335                                         ((const struct rte_flow_item_ipv6 *)
9336                                          items->mask)->hdr.proto;
9337                         } else {
9338                                 /* Reset for inner layer. */
9339                                 next_protocol = 0xff;
9340                         }
9341                         break;
9342                 case RTE_FLOW_ITEM_TYPE_TCP:
9343                         flow_dv_translate_item_tcp(match_mask, match_value,
9344                                                    items, tunnel);
9345                         matcher.priority = MLX5_PRIORITY_MAP_L4;
9346                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
9347                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
9348                         break;
9349                 case RTE_FLOW_ITEM_TYPE_UDP:
9350                         flow_dv_translate_item_udp(match_mask, match_value,
9351                                                    items, tunnel);
9352                         matcher.priority = MLX5_PRIORITY_MAP_L4;
9353                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
9354                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
9355                         break;
9356                 case RTE_FLOW_ITEM_TYPE_GRE:
9357                         flow_dv_translate_item_gre(match_mask, match_value,
9358                                                    items, tunnel);
9359                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
9360                         last_item = MLX5_FLOW_LAYER_GRE;
9361                         break;
9362                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
9363                         flow_dv_translate_item_gre_key(match_mask,
9364                                                        match_value, items);
9365                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
9366                         break;
9367                 case RTE_FLOW_ITEM_TYPE_NVGRE:
9368                         flow_dv_translate_item_nvgre(match_mask, match_value,
9369                                                      items, tunnel);
9370                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
9371                         last_item = MLX5_FLOW_LAYER_GRE;
9372                         break;
9373                 case RTE_FLOW_ITEM_TYPE_VXLAN:
9374                         flow_dv_translate_item_vxlan(match_mask, match_value,
9375                                                      items, tunnel);
9376                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
9377                         last_item = MLX5_FLOW_LAYER_VXLAN;
9378                         break;
9379                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
9380                         flow_dv_translate_item_vxlan_gpe(match_mask,
9381                                                          match_value, items,
9382                                                          tunnel);
9383                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
9384                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
9385                         break;
9386                 case RTE_FLOW_ITEM_TYPE_GENEVE:
9387                         flow_dv_translate_item_geneve(match_mask, match_value,
9388                                                       items, tunnel);
9389                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
9390                         last_item = MLX5_FLOW_LAYER_GENEVE;
9391                         break;
9392                 case RTE_FLOW_ITEM_TYPE_MPLS:
9393                         flow_dv_translate_item_mpls(match_mask, match_value,
9394                                                     items, last_item, tunnel);
9395                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
9396                         last_item = MLX5_FLOW_LAYER_MPLS;
9397                         break;
9398                 case RTE_FLOW_ITEM_TYPE_MARK:
9399                         flow_dv_translate_item_mark(dev, match_mask,
9400                                                     match_value, items);
9401                         last_item = MLX5_FLOW_ITEM_MARK;
9402                         break;
9403                 case RTE_FLOW_ITEM_TYPE_META:
9404                         flow_dv_translate_item_meta(dev, match_mask,
9405                                                     match_value, attr, items);
9406                         last_item = MLX5_FLOW_ITEM_METADATA;
9407                         break;
9408                 case RTE_FLOW_ITEM_TYPE_ICMP:
9409                         flow_dv_translate_item_icmp(match_mask, match_value,
9410                                                     items, tunnel);
9411                         last_item = MLX5_FLOW_LAYER_ICMP;
9412                         break;
9413                 case RTE_FLOW_ITEM_TYPE_ICMP6:
9414                         flow_dv_translate_item_icmp6(match_mask, match_value,
9415                                                       items, tunnel);
9416                         last_item = MLX5_FLOW_LAYER_ICMP6;
9417                         break;
9418                 case RTE_FLOW_ITEM_TYPE_TAG:
9419                         flow_dv_translate_item_tag(dev, match_mask,
9420                                                    match_value, items);
9421                         last_item = MLX5_FLOW_ITEM_TAG;
9422                         break;
9423                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
9424                         flow_dv_translate_mlx5_item_tag(dev, match_mask,
9425                                                         match_value, items);
9426                         last_item = MLX5_FLOW_ITEM_TAG;
9427                         break;
9428                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
9429                         flow_dv_translate_item_tx_queue(dev, match_mask,
9430                                                         match_value,
9431                                                         items);
9432                         last_item = MLX5_FLOW_ITEM_TX_QUEUE;
9433                         break;
9434                 case RTE_FLOW_ITEM_TYPE_GTP:
9435                         flow_dv_translate_item_gtp(match_mask, match_value,
9436                                                    items, tunnel);
9437                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
9438                         last_item = MLX5_FLOW_LAYER_GTP;
9439                         break;
9440                 case RTE_FLOW_ITEM_TYPE_ECPRI:
9441                         if (!mlx5_flex_parser_ecpri_exist(dev)) {
9442                                 /* Create it only the first time to be used. */
9443                                 ret = mlx5_flex_parser_ecpri_alloc(dev);
9444                                 if (ret)
9445                                         return rte_flow_error_set
9446                                                 (error, -ret,
9447                                                 RTE_FLOW_ERROR_TYPE_ITEM,
9448                                                 NULL,
9449                                                 "cannot create eCPRI parser");
9450                         }
9451                         /* Adjust the length matcher and device flow value. */
9452                         matcher.mask.size = MLX5_ST_SZ_BYTES(fte_match_param);
9453                         dev_flow->dv.value.size =
9454                                         MLX5_ST_SZ_BYTES(fte_match_param);
9455                         flow_dv_translate_item_ecpri(dev, match_mask,
9456                                                      match_value, items);
9457                         /* No other protocol should follow eCPRI layer. */
9458                         last_item = MLX5_FLOW_LAYER_ECPRI;
9459                         break;
9460                 default:
9461                         break;
9462                 }
9463                 item_flags |= last_item;
9464         }
9465         /*
9466          * When E-Switch mode is enabled, we have two cases where we need to
9467          * set the source port manually.
9468          * The first one, is in case of Nic steering rule, and the second is
9469          * E-Switch rule where no port_id item was found. In both cases
9470          * the source port is set according the current port in use.
9471          */
9472         if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
9473             (priv->representor || priv->master)) {
9474                 if (flow_dv_translate_item_port_id(dev, match_mask,
9475                                                    match_value, NULL))
9476                         return -rte_errno;
9477         }
9478 #ifdef RTE_LIBRTE_MLX5_DEBUG
9479         MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
9480                                               dev_flow->dv.value.buf));
9481 #endif
9482         /*
9483          * Layers may be already initialized from prefix flow if this dev_flow
9484          * is the suffix flow.
9485          */
9486         handle->layers |= item_flags;
9487         if (action_flags & MLX5_FLOW_ACTION_RSS)
9488                 flow_dv_hashfields_set(dev_flow, rss_desc);
9489         /* Register matcher. */
9490         matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
9491                                     matcher.mask.size);
9492         matcher.priority = mlx5_flow_adjust_priority(dev, priority,
9493                                                      matcher.priority);
9494         /* reserved field no needs to be set to 0 here. */
9495         tbl_key.domain = attr->transfer;
9496         tbl_key.direction = attr->egress;
9497         tbl_key.table_id = dev_flow->dv.group;
9498         if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow, error))
9499                 return -rte_errno;
9500         return 0;
9501 }
9502
9503 /**
9504  * Apply the flow to the NIC, lock free,
9505  * (mutex should be acquired by caller).
9506  *
9507  * @param[in] dev
9508  *   Pointer to the Ethernet device structure.
9509  * @param[in, out] flow
9510  *   Pointer to flow structure.
9511  * @param[out] error
9512  *   Pointer to error structure.
9513  *
9514  * @return
9515  *   0 on success, a negative errno value otherwise and rte_errno is set.
9516  */
9517 static int
9518 __flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
9519                 struct rte_flow_error *error)
9520 {
9521         struct mlx5_flow_dv_workspace *dv;
9522         struct mlx5_flow_handle *dh;
9523         struct mlx5_flow_handle_dv *dv_h;
9524         struct mlx5_flow *dev_flow;
9525         struct mlx5_priv *priv = dev->data->dev_private;
9526         uint32_t handle_idx;
9527         int n;
9528         int err;
9529         int idx;
9530
9531         for (idx = priv->flow_idx - 1; idx >= priv->flow_nested_idx; idx--) {
9532                 dev_flow = &((struct mlx5_flow *)priv->inter_flows)[idx];
9533                 dv = &dev_flow->dv;
9534                 dh = dev_flow->handle;
9535                 dv_h = &dh->dvh;
9536                 n = dv->actions_n;
9537                 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
9538                         if (dv->transfer) {
9539                                 dv->actions[n++] = priv->sh->esw_drop_action;
9540                         } else {
9541                                 struct mlx5_hrxq *drop_hrxq;
9542                                 drop_hrxq = mlx5_drop_action_create(dev);
9543                                 if (!drop_hrxq) {
9544                                         rte_flow_error_set
9545                                                 (error, errno,
9546                                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9547                                                  NULL,
9548                                                  "cannot get drop hash queue");
9549                                         goto error;
9550                                 }
9551                                 /*
9552                                  * Drop queues will be released by the specify
9553                                  * mlx5_drop_action_destroy() function. Assign
9554                                  * the special index to hrxq to mark the queue
9555                                  * has been allocated.
9556                                  */
9557                                 dh->rix_hrxq = UINT32_MAX;
9558                                 dv->actions[n++] = drop_hrxq->action;
9559                         }
9560                 } else if (dh->fate_action == MLX5_FLOW_FATE_QUEUE &&
9561                            !dv_h->rix_sample) {
9562                         struct mlx5_hrxq *hrxq;
9563                         uint32_t hrxq_idx;
9564                         struct mlx5_flow_rss_desc *rss_desc =
9565                                 &((struct mlx5_flow_rss_desc *)priv->rss_desc)
9566                                 [!!priv->flow_nested_idx];
9567
9568                         MLX5_ASSERT(rss_desc->queue_num);
9569                         hrxq_idx = mlx5_hrxq_get(dev, rss_desc->key,
9570                                                  MLX5_RSS_HASH_KEY_LEN,
9571                                                  dev_flow->hash_fields,
9572                                                  rss_desc->queue,
9573                                                  rss_desc->queue_num);
9574                         if (!hrxq_idx) {
9575                                 hrxq_idx = mlx5_hrxq_new
9576                                                 (dev, rss_desc->key,
9577                                                  MLX5_RSS_HASH_KEY_LEN,
9578                                                  dev_flow->hash_fields,
9579                                                  rss_desc->queue,
9580                                                  rss_desc->queue_num,
9581                                                  !!(dh->layers &
9582                                                  MLX5_FLOW_LAYER_TUNNEL));
9583                         }
9584                         hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
9585                                               hrxq_idx);
9586                         if (!hrxq) {
9587                                 rte_flow_error_set
9588                                         (error, rte_errno,
9589                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9590                                          "cannot get hash queue");
9591                                 goto error;
9592                         }
9593                         dh->rix_hrxq = hrxq_idx;
9594                         dv->actions[n++] = hrxq->action;
9595                 } else if (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS) {
9596                         if (flow_dv_default_miss_resource_register
9597                                         (dev, error)) {
9598                                 rte_flow_error_set
9599                                         (error, rte_errno,
9600                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9601                                          "cannot create default miss resource");
9602                                 goto error_default_miss;
9603                         }
9604                         dh->rix_default_fate =  MLX5_FLOW_FATE_DEFAULT_MISS;
9605                         dv->actions[n++] = priv->sh->default_miss.action;
9606                 }
9607                 err = mlx5_flow_os_create_flow(dv_h->matcher->matcher_object,
9608                                                (void *)&dv->value, n,
9609                                                dv->actions, &dh->drv_flow);
9610                 if (err) {
9611                         rte_flow_error_set(error, errno,
9612                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9613                                            NULL,
9614                                            "hardware refuses to create flow");
9615                         goto error;
9616                 }
9617                 if (priv->vmwa_context &&
9618                     dh->vf_vlan.tag && !dh->vf_vlan.created) {
9619                         /*
9620                          * The rule contains the VLAN pattern.
9621                          * For VF we are going to create VLAN
9622                          * interface to make hypervisor set correct
9623                          * e-Switch vport context.
9624                          */
9625                         mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
9626                 }
9627         }
9628         return 0;
9629 error:
9630         if (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS)
9631                 flow_dv_default_miss_resource_release(dev);
9632 error_default_miss:
9633         err = rte_errno; /* Save rte_errno before cleanup. */
9634         SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles,
9635                        handle_idx, dh, next) {
9636                 /* hrxq is union, don't clear it if the flag is not set. */
9637                 if (dh->rix_hrxq) {
9638                         if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
9639                                 mlx5_drop_action_destroy(dev);
9640                                 dh->rix_hrxq = 0;
9641                         } else if (dh->fate_action == MLX5_FLOW_FATE_QUEUE) {
9642                                 mlx5_hrxq_release(dev, dh->rix_hrxq);
9643                                 dh->rix_hrxq = 0;
9644                         }
9645                 }
9646                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
9647                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
9648         }
9649         rte_errno = err; /* Restore rte_errno. */
9650         return -rte_errno;
9651 }
9652
9653 /**
9654  * Release the flow matcher.
9655  *
9656  * @param dev
9657  *   Pointer to Ethernet device.
9658  * @param handle
9659  *   Pointer to mlx5_flow_handle.
9660  *
9661  * @return
9662  *   1 while a reference on it exists, 0 when freed.
9663  */
9664 static int
9665 flow_dv_matcher_release(struct rte_eth_dev *dev,
9666                         struct mlx5_flow_handle *handle)
9667 {
9668         struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
9669
9670         MLX5_ASSERT(matcher->matcher_object);
9671         DRV_LOG(DEBUG, "port %u matcher %p: refcnt %d--",
9672                 dev->data->port_id, (void *)matcher,
9673                 rte_atomic32_read(&matcher->refcnt));
9674         if (rte_atomic32_dec_and_test(&matcher->refcnt)) {
9675                 claim_zero(mlx5_flow_os_destroy_flow_matcher
9676                            (matcher->matcher_object));
9677                 LIST_REMOVE(matcher, next);
9678                 /* table ref-- in release interface. */
9679                 flow_dv_tbl_resource_release(dev, matcher->tbl);
9680                 mlx5_free(matcher);
9681                 DRV_LOG(DEBUG, "port %u matcher %p: removed",
9682                         dev->data->port_id, (void *)matcher);
9683                 return 0;
9684         }
9685         return 1;
9686 }
9687
9688 /**
9689  * Release an encap/decap resource.
9690  *
9691  * @param dev
9692  *   Pointer to Ethernet device.
9693  * @param encap_decap_idx
9694  *   Index of encap decap resource.
9695  *
9696  * @return
9697  *   1 while a reference on it exists, 0 when freed.
9698  */
9699 static int
9700 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
9701                                      uint32_t encap_decap_idx)
9702 {
9703         struct mlx5_priv *priv = dev->data->dev_private;
9704         uint32_t idx = encap_decap_idx;
9705         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
9706
9707         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
9708                          idx);
9709         if (!cache_resource)
9710                 return 0;
9711         MLX5_ASSERT(cache_resource->action);
9712         DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d--",
9713                 (void *)cache_resource,
9714                 rte_atomic32_read(&cache_resource->refcnt));
9715         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
9716                 claim_zero(mlx5_flow_os_destroy_flow_action
9717                                                 (cache_resource->action));
9718                 mlx5_hlist_remove(priv->sh->encaps_decaps,
9719                                   &cache_resource->entry);
9720                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);
9721                 DRV_LOG(DEBUG, "encap/decap resource %p: removed",
9722                         (void *)cache_resource);
9723                 return 0;
9724         }
9725         return 1;
9726 }
9727
9728 /**
9729  * Release an jump to table action resource.
9730  *
9731  * @param dev
9732  *   Pointer to Ethernet device.
9733  * @param handle
9734  *   Pointer to mlx5_flow_handle.
9735  *
9736  * @return
9737  *   1 while a reference on it exists, 0 when freed.
9738  */
9739 static int
9740 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
9741                                   struct mlx5_flow_handle *handle)
9742 {
9743         struct mlx5_priv *priv = dev->data->dev_private;
9744         struct mlx5_flow_dv_jump_tbl_resource *cache_resource;
9745         struct mlx5_flow_tbl_data_entry *tbl_data;
9746
9747         tbl_data = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_JUMP],
9748                              handle->rix_jump);
9749         if (!tbl_data)
9750                 return 0;
9751         cache_resource = &tbl_data->jump;
9752         MLX5_ASSERT(cache_resource->action);
9753         DRV_LOG(DEBUG, "jump table resource %p: refcnt %d--",
9754                 (void *)cache_resource,
9755                 rte_atomic32_read(&cache_resource->refcnt));
9756         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
9757                 claim_zero(mlx5_flow_os_destroy_flow_action
9758                                                 (cache_resource->action));
9759                 /* jump action memory free is inside the table release. */
9760                 flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
9761                 DRV_LOG(DEBUG, "jump table resource %p: removed",
9762                         (void *)cache_resource);
9763                 return 0;
9764         }
9765         return 1;
9766 }
9767
9768 /**
9769  * Release a default miss resource.
9770  *
9771  * @param dev
9772  *   Pointer to Ethernet device.
9773  * @return
9774  *   1 while a reference on it exists, 0 when freed.
9775  */
9776 static int
9777 flow_dv_default_miss_resource_release(struct rte_eth_dev *dev)
9778 {
9779         struct mlx5_priv *priv = dev->data->dev_private;
9780         struct mlx5_dev_ctx_shared *sh = priv->sh;
9781         struct mlx5_flow_default_miss_resource *cache_resource =
9782                         &sh->default_miss;
9783
9784         MLX5_ASSERT(cache_resource->action);
9785         DRV_LOG(DEBUG, "default miss resource %p: refcnt %d--",
9786                         (void *)cache_resource->action,
9787                         rte_atomic32_read(&cache_resource->refcnt));
9788         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
9789                 claim_zero(mlx5_glue->destroy_flow_action
9790                                 (cache_resource->action));
9791                 DRV_LOG(DEBUG, "default miss resource %p: removed",
9792                                 (void *)cache_resource->action);
9793                 return 0;
9794         }
9795         return 1;
9796 }
9797
9798 /**
9799  * Release a modify-header resource.
9800  *
9801  * @param dev
9802  *   Pointer to Ethernet device.
9803  * @param handle
9804  *   Pointer to mlx5_flow_handle.
9805  *
9806  * @return
9807  *   1 while a reference on it exists, 0 when freed.
9808  */
9809 static int
9810 flow_dv_modify_hdr_resource_release(struct rte_eth_dev *dev,
9811                                     struct mlx5_flow_handle *handle)
9812 {
9813         struct mlx5_priv *priv = dev->data->dev_private;
9814         struct mlx5_flow_dv_modify_hdr_resource *cache_resource =
9815                                                         handle->dvh.modify_hdr;
9816
9817         MLX5_ASSERT(cache_resource->action);
9818         DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d--",
9819                 (void *)cache_resource,
9820                 rte_atomic32_read(&cache_resource->refcnt));
9821         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
9822                 claim_zero(mlx5_flow_os_destroy_flow_action
9823                                                 (cache_resource->action));
9824                 mlx5_hlist_remove(priv->sh->modify_cmds,
9825                                   &cache_resource->entry);
9826                 mlx5_free(cache_resource);
9827                 DRV_LOG(DEBUG, "modify-header resource %p: removed",
9828                         (void *)cache_resource);
9829                 return 0;
9830         }
9831         return 1;
9832 }
9833
9834 /**
9835  * Release port ID action resource.
9836  *
9837  * @param dev
9838  *   Pointer to Ethernet device.
9839  * @param handle
9840  *   Pointer to mlx5_flow_handle.
9841  *
9842  * @return
9843  *   1 while a reference on it exists, 0 when freed.
9844  */
9845 static int
9846 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
9847                                         struct mlx5_flow_handle *handle)
9848 {
9849         struct mlx5_priv *priv = dev->data->dev_private;
9850         struct mlx5_flow_dv_port_id_action_resource *cache_resource;
9851         uint32_t idx = handle->rix_port_id_action;
9852
9853         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID],
9854                                         idx);
9855         if (!cache_resource)
9856                 return 0;
9857         MLX5_ASSERT(cache_resource->action);
9858         DRV_LOG(DEBUG, "port ID action resource %p: refcnt %d--",
9859                 (void *)cache_resource,
9860                 rte_atomic32_read(&cache_resource->refcnt));
9861         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
9862                 claim_zero(mlx5_flow_os_destroy_flow_action
9863                                                 (cache_resource->action));
9864                 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_PORT_ID],
9865                              &priv->sh->port_id_action_list, idx,
9866                              cache_resource, next);
9867                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_PORT_ID], idx);
9868                 DRV_LOG(DEBUG, "port id action resource %p: removed",
9869                         (void *)cache_resource);
9870                 return 0;
9871         }
9872         return 1;
9873 }
9874
9875 /**
9876  * Release push vlan action resource.
9877  *
9878  * @param dev
9879  *   Pointer to Ethernet device.
9880  * @param handle
9881  *   Pointer to mlx5_flow_handle.
9882  *
9883  * @return
9884  *   1 while a reference on it exists, 0 when freed.
9885  */
9886 static int
9887 flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,
9888                                           struct mlx5_flow_handle *handle)
9889 {
9890         struct mlx5_priv *priv = dev->data->dev_private;
9891         uint32_t idx = handle->dvh.rix_push_vlan;
9892         struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
9893
9894         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN],
9895                                         idx);
9896         if (!cache_resource)
9897                 return 0;
9898         MLX5_ASSERT(cache_resource->action);
9899         DRV_LOG(DEBUG, "push VLAN action resource %p: refcnt %d--",
9900                 (void *)cache_resource,
9901                 rte_atomic32_read(&cache_resource->refcnt));
9902         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
9903                 claim_zero(mlx5_flow_os_destroy_flow_action
9904                                                 (cache_resource->action));
9905                 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN],
9906                              &priv->sh->push_vlan_action_list, idx,
9907                              cache_resource, next);
9908                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
9909                 DRV_LOG(DEBUG, "push vlan action resource %p: removed",
9910                         (void *)cache_resource);
9911                 return 0;
9912         }
9913         return 1;
9914 }
9915
9916 /**
9917  * Release the fate resource.
9918  *
9919  * @param dev
9920  *   Pointer to Ethernet device.
9921  * @param handle
9922  *   Pointer to mlx5_flow_handle.
9923  */
9924 static void
9925 flow_dv_fate_resource_release(struct rte_eth_dev *dev,
9926                                struct mlx5_flow_handle *handle)
9927 {
9928         if (!handle->rix_fate)
9929                 return;
9930         switch (handle->fate_action) {
9931         case MLX5_FLOW_FATE_DROP:
9932                 mlx5_drop_action_destroy(dev);
9933                 break;
9934         case MLX5_FLOW_FATE_QUEUE:
9935                 mlx5_hrxq_release(dev, handle->rix_hrxq);
9936                 break;
9937         case MLX5_FLOW_FATE_JUMP:
9938                 flow_dv_jump_tbl_resource_release(dev, handle);
9939                 break;
9940         case MLX5_FLOW_FATE_PORT_ID:
9941                 flow_dv_port_id_action_resource_release(dev, handle);
9942                 break;
9943         case MLX5_FLOW_FATE_DEFAULT_MISS:
9944                 flow_dv_default_miss_resource_release(dev);
9945                 break;
9946         default:
9947                 DRV_LOG(DEBUG, "Incorrect fate action:%d", handle->fate_action);
9948                 break;
9949         }
9950         handle->rix_fate = 0;
9951 }
9952
9953 /**
9954  * Release an sample resource.
9955  *
9956  * @param dev
9957  *   Pointer to Ethernet device.
9958  * @param handle
9959  *   Pointer to mlx5_flow_handle.
9960  *
9961  * @return
9962  *   1 while a reference on it exists, 0 when freed.
9963  */
9964 static int
9965 flow_dv_sample_resource_release(struct rte_eth_dev *dev,
9966                                      struct mlx5_flow_handle *handle)
9967 {
9968         struct mlx5_priv *priv = dev->data->dev_private;
9969         uint32_t idx = handle->dvh.rix_sample;
9970         struct mlx5_flow_dv_sample_resource *cache_resource;
9971
9972         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
9973                          idx);
9974         if (!cache_resource)
9975                 return 0;
9976         MLX5_ASSERT(cache_resource->verbs_action);
9977         DRV_LOG(DEBUG, "sample resource %p: refcnt %d--",
9978                 (void *)cache_resource,
9979                 __atomic_load_n(&cache_resource->refcnt, __ATOMIC_RELAXED));
9980         if (__atomic_sub_fetch(&cache_resource->refcnt, 1,
9981                                __ATOMIC_RELAXED) == 0) {
9982                 if (cache_resource->verbs_action)
9983                         claim_zero(mlx5_glue->destroy_flow_action
9984                                         (cache_resource->verbs_action));
9985                 if (cache_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB) {
9986                         if (cache_resource->default_miss)
9987                                 claim_zero(mlx5_glue->destroy_flow_action
9988                                   (cache_resource->default_miss));
9989                 }
9990                 if (cache_resource->normal_path_tbl)
9991                         flow_dv_tbl_resource_release(dev,
9992                                 cache_resource->normal_path_tbl);
9993         }
9994         if (cache_resource->sample_idx.rix_hrxq &&
9995                 !mlx5_hrxq_release(dev,
9996                         cache_resource->sample_idx.rix_hrxq))
9997                 cache_resource->sample_idx.rix_hrxq = 0;
9998         if (cache_resource->sample_idx.rix_tag &&
9999                 !flow_dv_tag_release(dev,
10000                         cache_resource->sample_idx.rix_tag))
10001                 cache_resource->sample_idx.rix_tag = 0;
10002         if (cache_resource->sample_idx.cnt) {
10003                 flow_dv_counter_release(dev,
10004                         cache_resource->sample_idx.cnt);
10005                 cache_resource->sample_idx.cnt = 0;
10006         }
10007         if (!__atomic_load_n(&cache_resource->refcnt, __ATOMIC_RELAXED)) {
10008                 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
10009                              &priv->sh->sample_action_list, idx,
10010                              cache_resource, next);
10011                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_SAMPLE], idx);
10012                 DRV_LOG(DEBUG, "sample resource %p: removed",
10013                         (void *)cache_resource);
10014                 return 0;
10015         }
10016         return 1;
10017 }
10018
10019 /**
10020  * Remove the flow from the NIC but keeps it in memory.
10021  * Lock free, (mutex should be acquired by caller).
10022  *
10023  * @param[in] dev
10024  *   Pointer to Ethernet device.
10025  * @param[in, out] flow
10026  *   Pointer to flow structure.
10027  */
10028 static void
10029 __flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
10030 {
10031         struct mlx5_flow_handle *dh;
10032         uint32_t handle_idx;
10033         struct mlx5_priv *priv = dev->data->dev_private;
10034
10035         if (!flow)
10036                 return;
10037         handle_idx = flow->dev_handles;
10038         while (handle_idx) {
10039                 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
10040                                     handle_idx);
10041                 if (!dh)
10042                         return;
10043                 if (dh->drv_flow) {
10044                         claim_zero(mlx5_flow_os_destroy_flow(dh->drv_flow));
10045                         dh->drv_flow = NULL;
10046                 }
10047                 if (dh->fate_action == MLX5_FLOW_FATE_DROP ||
10048                     dh->fate_action == MLX5_FLOW_FATE_QUEUE ||
10049                     dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS)
10050                         flow_dv_fate_resource_release(dev, dh);
10051                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
10052                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
10053                 handle_idx = dh->next.next;
10054         }
10055 }
10056
10057 /**
10058  * Remove the flow from the NIC and the memory.
10059  * Lock free, (mutex should be acquired by caller).
10060  *
10061  * @param[in] dev
10062  *   Pointer to the Ethernet device structure.
10063  * @param[in, out] flow
10064  *   Pointer to flow structure.
10065  */
10066 static void
10067 __flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
10068 {
10069         struct mlx5_flow_handle *dev_handle;
10070         struct mlx5_priv *priv = dev->data->dev_private;
10071
10072         if (!flow)
10073                 return;
10074         __flow_dv_remove(dev, flow);
10075         if (flow->counter) {
10076                 flow_dv_counter_release(dev, flow->counter);
10077                 flow->counter = 0;
10078         }
10079         if (flow->meter) {
10080                 struct mlx5_flow_meter *fm;
10081
10082                 fm = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MTR],
10083                                     flow->meter);
10084                 if (fm)
10085                         mlx5_flow_meter_detach(fm);
10086                 flow->meter = 0;
10087         }
10088         while (flow->dev_handles) {
10089                 uint32_t tmp_idx = flow->dev_handles;
10090
10091                 dev_handle = mlx5_ipool_get(priv->sh->ipool
10092                                             [MLX5_IPOOL_MLX5_FLOW], tmp_idx);
10093                 if (!dev_handle)
10094                         return;
10095                 flow->dev_handles = dev_handle->next.next;
10096                 if (dev_handle->dvh.matcher)
10097                         flow_dv_matcher_release(dev, dev_handle);
10098                 if (dev_handle->dvh.rix_sample)
10099                         flow_dv_sample_resource_release(dev, dev_handle);
10100                 if (dev_handle->dvh.rix_encap_decap)
10101                         flow_dv_encap_decap_resource_release(dev,
10102                                 dev_handle->dvh.rix_encap_decap);
10103                 if (dev_handle->dvh.modify_hdr)
10104                         flow_dv_modify_hdr_resource_release(dev, dev_handle);
10105                 if (dev_handle->dvh.rix_push_vlan)
10106                         flow_dv_push_vlan_action_resource_release(dev,
10107                                                                   dev_handle);
10108                 if (dev_handle->dvh.rix_tag)
10109                         flow_dv_tag_release(dev,
10110                                             dev_handle->dvh.rix_tag);
10111                 flow_dv_fate_resource_release(dev, dev_handle);
10112                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
10113                            tmp_idx);
10114         }
10115 }
10116
10117 /**
10118  * Query a dv flow  rule for its statistics via devx.
10119  *
10120  * @param[in] dev
10121  *   Pointer to Ethernet device.
10122  * @param[in] flow
10123  *   Pointer to the sub flow.
10124  * @param[out] data
10125  *   data retrieved by the query.
10126  * @param[out] error
10127  *   Perform verbose error reporting if not NULL.
10128  *
10129  * @return
10130  *   0 on success, a negative errno value otherwise and rte_errno is set.
10131  */
10132 static int
10133 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
10134                     void *data, struct rte_flow_error *error)
10135 {
10136         struct mlx5_priv *priv = dev->data->dev_private;
10137         struct rte_flow_query_count *qc = data;
10138
10139         if (!priv->config.devx)
10140                 return rte_flow_error_set(error, ENOTSUP,
10141                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10142                                           NULL,
10143                                           "counters are not supported");
10144         if (flow->counter) {
10145                 uint64_t pkts, bytes;
10146                 struct mlx5_flow_counter *cnt;
10147
10148                 cnt = flow_dv_counter_get_by_idx(dev, flow->counter,
10149                                                  NULL);
10150                 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
10151                                                &bytes);
10152
10153                 if (err)
10154                         return rte_flow_error_set(error, -err,
10155                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10156                                         NULL, "cannot read counters");
10157                 qc->hits_set = 1;
10158                 qc->bytes_set = 1;
10159                 qc->hits = pkts - cnt->hits;
10160                 qc->bytes = bytes - cnt->bytes;
10161                 if (qc->reset) {
10162                         cnt->hits = pkts;
10163                         cnt->bytes = bytes;
10164                 }
10165                 return 0;
10166         }
10167         return rte_flow_error_set(error, EINVAL,
10168                                   RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10169                                   NULL,
10170                                   "counters are not available");
10171 }
10172
10173 /**
10174  * Query a flow.
10175  *
10176  * @see rte_flow_query()
10177  * @see rte_flow_ops
10178  */
10179 static int
10180 flow_dv_query(struct rte_eth_dev *dev,
10181               struct rte_flow *flow __rte_unused,
10182               const struct rte_flow_action *actions __rte_unused,
10183               void *data __rte_unused,
10184               struct rte_flow_error *error __rte_unused)
10185 {
10186         int ret = -EINVAL;
10187
10188         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
10189                 switch (actions->type) {
10190                 case RTE_FLOW_ACTION_TYPE_VOID:
10191                         break;
10192                 case RTE_FLOW_ACTION_TYPE_COUNT:
10193                         ret = flow_dv_query_count(dev, flow, data, error);
10194                         break;
10195                 default:
10196                         return rte_flow_error_set(error, ENOTSUP,
10197                                                   RTE_FLOW_ERROR_TYPE_ACTION,
10198                                                   actions,
10199                                                   "action not supported");
10200                 }
10201         }
10202         return ret;
10203 }
10204
10205 /**
10206  * Destroy the meter table set.
10207  * Lock free, (mutex should be acquired by caller).
10208  *
10209  * @param[in] dev
10210  *   Pointer to Ethernet device.
10211  * @param[in] tbl
10212  *   Pointer to the meter table set.
10213  *
10214  * @return
10215  *   Always 0.
10216  */
10217 static int
10218 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
10219                         struct mlx5_meter_domains_infos *tbl)
10220 {
10221         struct mlx5_priv *priv = dev->data->dev_private;
10222         struct mlx5_meter_domains_infos *mtd =
10223                                 (struct mlx5_meter_domains_infos *)tbl;
10224
10225         if (!mtd || !priv->config.dv_flow_en)
10226                 return 0;
10227         if (mtd->ingress.policer_rules[RTE_MTR_DROPPED])
10228                 claim_zero(mlx5_flow_os_destroy_flow
10229                            (mtd->ingress.policer_rules[RTE_MTR_DROPPED]));
10230         if (mtd->egress.policer_rules[RTE_MTR_DROPPED])
10231                 claim_zero(mlx5_flow_os_destroy_flow
10232                            (mtd->egress.policer_rules[RTE_MTR_DROPPED]));
10233         if (mtd->transfer.policer_rules[RTE_MTR_DROPPED])
10234                 claim_zero(mlx5_flow_os_destroy_flow
10235                            (mtd->transfer.policer_rules[RTE_MTR_DROPPED]));
10236         if (mtd->egress.color_matcher)
10237                 claim_zero(mlx5_flow_os_destroy_flow_matcher
10238                            (mtd->egress.color_matcher));
10239         if (mtd->egress.any_matcher)
10240                 claim_zero(mlx5_flow_os_destroy_flow_matcher
10241                            (mtd->egress.any_matcher));
10242         if (mtd->egress.tbl)
10243                 flow_dv_tbl_resource_release(dev, mtd->egress.tbl);
10244         if (mtd->egress.sfx_tbl)
10245                 flow_dv_tbl_resource_release(dev, mtd->egress.sfx_tbl);
10246         if (mtd->ingress.color_matcher)
10247                 claim_zero(mlx5_flow_os_destroy_flow_matcher
10248                            (mtd->ingress.color_matcher));
10249         if (mtd->ingress.any_matcher)
10250                 claim_zero(mlx5_flow_os_destroy_flow_matcher
10251                            (mtd->ingress.any_matcher));
10252         if (mtd->ingress.tbl)
10253                 flow_dv_tbl_resource_release(dev, mtd->ingress.tbl);
10254         if (mtd->ingress.sfx_tbl)
10255                 flow_dv_tbl_resource_release(dev, mtd->ingress.sfx_tbl);
10256         if (mtd->transfer.color_matcher)
10257                 claim_zero(mlx5_flow_os_destroy_flow_matcher
10258                            (mtd->transfer.color_matcher));
10259         if (mtd->transfer.any_matcher)
10260                 claim_zero(mlx5_flow_os_destroy_flow_matcher
10261                            (mtd->transfer.any_matcher));
10262         if (mtd->transfer.tbl)
10263                 flow_dv_tbl_resource_release(dev, mtd->transfer.tbl);
10264         if (mtd->transfer.sfx_tbl)
10265                 flow_dv_tbl_resource_release(dev, mtd->transfer.sfx_tbl);
10266         if (mtd->drop_actn)
10267                 claim_zero(mlx5_flow_os_destroy_flow_action(mtd->drop_actn));
10268         mlx5_free(mtd);
10269         return 0;
10270 }
10271
10272 /* Number of meter flow actions, count and jump or count and drop. */
10273 #define METER_ACTIONS 2
10274
10275 /**
10276  * Create specify domain meter table and suffix table.
10277  *
10278  * @param[in] dev
10279  *   Pointer to Ethernet device.
10280  * @param[in,out] mtb
10281  *   Pointer to DV meter table set.
10282  * @param[in] egress
10283  *   Table attribute.
10284  * @param[in] transfer
10285  *   Table attribute.
10286  * @param[in] color_reg_c_idx
10287  *   Reg C index for color match.
10288  *
10289  * @return
10290  *   0 on success, -1 otherwise and rte_errno is set.
10291  */
10292 static int
10293 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
10294                            struct mlx5_meter_domains_infos *mtb,
10295                            uint8_t egress, uint8_t transfer,
10296                            uint32_t color_reg_c_idx)
10297 {
10298         struct mlx5_priv *priv = dev->data->dev_private;
10299         struct mlx5_dev_ctx_shared *sh = priv->sh;
10300         struct mlx5_flow_dv_match_params mask = {
10301                 .size = sizeof(mask.buf),
10302         };
10303         struct mlx5_flow_dv_match_params value = {
10304                 .size = sizeof(value.buf),
10305         };
10306         struct mlx5dv_flow_matcher_attr dv_attr = {
10307                 .type = IBV_FLOW_ATTR_NORMAL,
10308                 .priority = 0,
10309                 .match_criteria_enable = 0,
10310                 .match_mask = (void *)&mask,
10311         };
10312         void *actions[METER_ACTIONS];
10313         struct mlx5_meter_domain_info *dtb;
10314         struct rte_flow_error error;
10315         int i = 0;
10316         int ret;
10317
10318         if (transfer)
10319                 dtb = &mtb->transfer;
10320         else if (egress)
10321                 dtb = &mtb->egress;
10322         else
10323                 dtb = &mtb->ingress;
10324         /* Create the meter table with METER level. */
10325         dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
10326                                             egress, transfer, &error);
10327         if (!dtb->tbl) {
10328                 DRV_LOG(ERR, "Failed to create meter policer table.");
10329                 return -1;
10330         }
10331         /* Create the meter suffix table with SUFFIX level. */
10332         dtb->sfx_tbl = flow_dv_tbl_resource_get(dev,
10333                                             MLX5_FLOW_TABLE_LEVEL_SUFFIX,
10334                                             egress, transfer, &error);
10335         if (!dtb->sfx_tbl) {
10336                 DRV_LOG(ERR, "Failed to create meter suffix table.");
10337                 return -1;
10338         }
10339         /* Create matchers, Any and Color. */
10340         dv_attr.priority = 3;
10341         dv_attr.match_criteria_enable = 0;
10342         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, dtb->tbl->obj,
10343                                                &dtb->any_matcher);
10344         if (ret) {
10345                 DRV_LOG(ERR, "Failed to create meter"
10346                              " policer default matcher.");
10347                 goto error_exit;
10348         }
10349         dv_attr.priority = 0;
10350         dv_attr.match_criteria_enable =
10351                                 1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
10352         flow_dv_match_meta_reg(mask.buf, value.buf, color_reg_c_idx,
10353                                rte_col_2_mlx5_col(RTE_COLORS), UINT8_MAX);
10354         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, dtb->tbl->obj,
10355                                                &dtb->color_matcher);
10356         if (ret) {
10357                 DRV_LOG(ERR, "Failed to create meter policer color matcher.");
10358                 goto error_exit;
10359         }
10360         if (mtb->count_actns[RTE_MTR_DROPPED])
10361                 actions[i++] = mtb->count_actns[RTE_MTR_DROPPED];
10362         actions[i++] = mtb->drop_actn;
10363         /* Default rule: lowest priority, match any, actions: drop. */
10364         ret = mlx5_flow_os_create_flow(dtb->any_matcher, (void *)&value, i,
10365                                        actions,
10366                                        &dtb->policer_rules[RTE_MTR_DROPPED]);
10367         if (ret) {
10368                 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
10369                 goto error_exit;
10370         }
10371         return 0;
10372 error_exit:
10373         return -1;
10374 }
10375
10376 /**
10377  * Create the needed meter and suffix tables.
10378  * Lock free, (mutex should be acquired by caller).
10379  *
10380  * @param[in] dev
10381  *   Pointer to Ethernet device.
10382  * @param[in] fm
10383  *   Pointer to the flow meter.
10384  *
10385  * @return
10386  *   Pointer to table set on success, NULL otherwise and rte_errno is set.
10387  */
10388 static struct mlx5_meter_domains_infos *
10389 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev,
10390                        const struct mlx5_flow_meter *fm)
10391 {
10392         struct mlx5_priv *priv = dev->data->dev_private;
10393         struct mlx5_meter_domains_infos *mtb;
10394         int ret;
10395         int i;
10396
10397         if (!priv->mtr_en) {
10398                 rte_errno = ENOTSUP;
10399                 return NULL;
10400         }
10401         mtb = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mtb), 0, SOCKET_ID_ANY);
10402         if (!mtb) {
10403                 DRV_LOG(ERR, "Failed to allocate memory for meter.");
10404                 return NULL;
10405         }
10406         /* Create meter count actions */
10407         for (i = 0; i <= RTE_MTR_DROPPED; i++) {
10408                 struct mlx5_flow_counter *cnt;
10409                 if (!fm->policer_stats.cnt[i])
10410                         continue;
10411                 cnt = flow_dv_counter_get_by_idx(dev,
10412                       fm->policer_stats.cnt[i], NULL);
10413                 mtb->count_actns[i] = cnt->action;
10414         }
10415         /* Create drop action. */
10416         ret = mlx5_flow_os_create_flow_action_drop(&mtb->drop_actn);
10417         if (ret) {
10418                 DRV_LOG(ERR, "Failed to create drop action.");
10419                 goto error_exit;
10420         }
10421         /* Egress meter table. */
10422         ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0, priv->mtr_color_reg);
10423         if (ret) {
10424                 DRV_LOG(ERR, "Failed to prepare egress meter table.");
10425                 goto error_exit;
10426         }
10427         /* Ingress meter table. */
10428         ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0, priv->mtr_color_reg);
10429         if (ret) {
10430                 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
10431                 goto error_exit;
10432         }
10433         /* FDB meter table. */
10434         if (priv->config.dv_esw_en) {
10435                 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1,
10436                                                  priv->mtr_color_reg);
10437                 if (ret) {
10438                         DRV_LOG(ERR, "Failed to prepare fdb meter table.");
10439                         goto error_exit;
10440                 }
10441         }
10442         return mtb;
10443 error_exit:
10444         flow_dv_destroy_mtr_tbl(dev, mtb);
10445         return NULL;
10446 }
10447
10448 /**
10449  * Destroy domain policer rule.
10450  *
10451  * @param[in] dt
10452  *   Pointer to domain table.
10453  */
10454 static void
10455 flow_dv_destroy_domain_policer_rule(struct mlx5_meter_domain_info *dt)
10456 {
10457         int i;
10458
10459         for (i = 0; i < RTE_MTR_DROPPED; i++) {
10460                 if (dt->policer_rules[i]) {
10461                         claim_zero(mlx5_flow_os_destroy_flow
10462                                    (dt->policer_rules[i]));
10463                         dt->policer_rules[i] = NULL;
10464                 }
10465         }
10466         if (dt->jump_actn) {
10467                 claim_zero(mlx5_flow_os_destroy_flow_action(dt->jump_actn));
10468                 dt->jump_actn = NULL;
10469         }
10470 }
10471
10472 /**
10473  * Destroy policer rules.
10474  *
10475  * @param[in] dev
10476  *   Pointer to Ethernet device.
10477  * @param[in] fm
10478  *   Pointer to flow meter structure.
10479  * @param[in] attr
10480  *   Pointer to flow attributes.
10481  *
10482  * @return
10483  *   Always 0.
10484  */
10485 static int
10486 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev __rte_unused,
10487                               const struct mlx5_flow_meter *fm,
10488                               const struct rte_flow_attr *attr)
10489 {
10490         struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
10491
10492         if (!mtb)
10493                 return 0;
10494         if (attr->egress)
10495                 flow_dv_destroy_domain_policer_rule(&mtb->egress);
10496         if (attr->ingress)
10497                 flow_dv_destroy_domain_policer_rule(&mtb->ingress);
10498         if (attr->transfer)
10499                 flow_dv_destroy_domain_policer_rule(&mtb->transfer);
10500         return 0;
10501 }
10502
10503 /**
10504  * Create specify domain meter policer rule.
10505  *
10506  * @param[in] fm
10507  *   Pointer to flow meter structure.
10508  * @param[in] mtb
10509  *   Pointer to DV meter table set.
10510  * @param[in] mtr_reg_c
10511  *   Color match REG_C.
10512  *
10513  * @return
10514  *   0 on success, -1 otherwise.
10515  */
10516 static int
10517 flow_dv_create_policer_forward_rule(struct mlx5_flow_meter *fm,
10518                                     struct mlx5_meter_domain_info *dtb,
10519                                     uint8_t mtr_reg_c)
10520 {
10521         struct mlx5_flow_dv_match_params matcher = {
10522                 .size = sizeof(matcher.buf),
10523         };
10524         struct mlx5_flow_dv_match_params value = {
10525                 .size = sizeof(value.buf),
10526         };
10527         struct mlx5_meter_domains_infos *mtb = fm->mfts;
10528         void *actions[METER_ACTIONS];
10529         int i;
10530         int ret = 0;
10531
10532         /* Create jump action. */
10533         if (!dtb->jump_actn)
10534                 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
10535                                 (dtb->sfx_tbl->obj, &dtb->jump_actn);
10536         if (ret) {
10537                 DRV_LOG(ERR, "Failed to create policer jump action.");
10538                 goto error;
10539         }
10540         for (i = 0; i < RTE_MTR_DROPPED; i++) {
10541                 int j = 0;
10542
10543                 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_reg_c,
10544                                        rte_col_2_mlx5_col(i), UINT8_MAX);
10545                 if (mtb->count_actns[i])
10546                         actions[j++] = mtb->count_actns[i];
10547                 if (fm->action[i] == MTR_POLICER_ACTION_DROP)
10548                         actions[j++] = mtb->drop_actn;
10549                 else
10550                         actions[j++] = dtb->jump_actn;
10551                 ret = mlx5_flow_os_create_flow(dtb->color_matcher,
10552                                                (void *)&value, j, actions,
10553                                                &dtb->policer_rules[i]);
10554                 if (ret) {
10555                         DRV_LOG(ERR, "Failed to create policer rule.");
10556                         goto error;
10557                 }
10558         }
10559         return 0;
10560 error:
10561         rte_errno = errno;
10562         return -1;
10563 }
10564
10565 /**
10566  * Create policer rules.
10567  *
10568  * @param[in] dev
10569  *   Pointer to Ethernet device.
10570  * @param[in] fm
10571  *   Pointer to flow meter structure.
10572  * @param[in] attr
10573  *   Pointer to flow attributes.
10574  *
10575  * @return
10576  *   0 on success, -1 otherwise.
10577  */
10578 static int
10579 flow_dv_create_policer_rules(struct rte_eth_dev *dev,
10580                              struct mlx5_flow_meter *fm,
10581                              const struct rte_flow_attr *attr)
10582 {
10583         struct mlx5_priv *priv = dev->data->dev_private;
10584         struct mlx5_meter_domains_infos *mtb = fm->mfts;
10585         int ret;
10586
10587         if (attr->egress) {
10588                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->egress,
10589                                                 priv->mtr_color_reg);
10590                 if (ret) {
10591                         DRV_LOG(ERR, "Failed to create egress policer.");
10592                         goto error;
10593                 }
10594         }
10595         if (attr->ingress) {
10596                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->ingress,
10597                                                 priv->mtr_color_reg);
10598                 if (ret) {
10599                         DRV_LOG(ERR, "Failed to create ingress policer.");
10600                         goto error;
10601                 }
10602         }
10603         if (attr->transfer) {
10604                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->transfer,
10605                                                 priv->mtr_color_reg);
10606                 if (ret) {
10607                         DRV_LOG(ERR, "Failed to create transfer policer.");
10608                         goto error;
10609                 }
10610         }
10611         return 0;
10612 error:
10613         flow_dv_destroy_policer_rules(dev, fm, attr);
10614         return -1;
10615 }
10616
10617 /**
10618  * Query a devx counter.
10619  *
10620  * @param[in] dev
10621  *   Pointer to the Ethernet device structure.
10622  * @param[in] cnt
10623  *   Index to the flow counter.
10624  * @param[in] clear
10625  *   Set to clear the counter statistics.
10626  * @param[out] pkts
10627  *   The statistics value of packets.
10628  * @param[out] bytes
10629  *   The statistics value of bytes.
10630  *
10631  * @return
10632  *   0 on success, otherwise return -1.
10633  */
10634 static int
10635 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
10636                       uint64_t *pkts, uint64_t *bytes)
10637 {
10638         struct mlx5_priv *priv = dev->data->dev_private;
10639         struct mlx5_flow_counter *cnt;
10640         uint64_t inn_pkts, inn_bytes;
10641         int ret;
10642
10643         if (!priv->config.devx)
10644                 return -1;
10645
10646         ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
10647         if (ret)
10648                 return -1;
10649         cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
10650         *pkts = inn_pkts - cnt->hits;
10651         *bytes = inn_bytes - cnt->bytes;
10652         if (clear) {
10653                 cnt->hits = inn_pkts;
10654                 cnt->bytes = inn_bytes;
10655         }
10656         return 0;
10657 }
10658
10659 /**
10660  * Get aged-out flows.
10661  *
10662  * @param[in] dev
10663  *   Pointer to the Ethernet device structure.
10664  * @param[in] context
10665  *   The address of an array of pointers to the aged-out flows contexts.
10666  * @param[in] nb_contexts
10667  *   The length of context array pointers.
10668  * @param[out] error
10669  *   Perform verbose error reporting if not NULL. Initialized in case of
10670  *   error only.
10671  *
10672  * @return
10673  *   how many contexts get in success, otherwise negative errno value.
10674  *   if nb_contexts is 0, return the amount of all aged contexts.
10675  *   if nb_contexts is not 0 , return the amount of aged flows reported
10676  *   in the context array.
10677  * @note: only stub for now
10678  */
10679 static int
10680 flow_get_aged_flows(struct rte_eth_dev *dev,
10681                     void **context,
10682                     uint32_t nb_contexts,
10683                     struct rte_flow_error *error)
10684 {
10685         struct mlx5_priv *priv = dev->data->dev_private;
10686         struct mlx5_age_info *age_info;
10687         struct mlx5_age_param *age_param;
10688         struct mlx5_flow_counter *counter;
10689         int nb_flows = 0;
10690
10691         if (nb_contexts && !context)
10692                 return rte_flow_error_set(error, EINVAL,
10693                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10694                                           NULL,
10695                                           "Should assign at least one flow or"
10696                                           " context to get if nb_contexts != 0");
10697         age_info = GET_PORT_AGE_INFO(priv);
10698         rte_spinlock_lock(&age_info->aged_sl);
10699         TAILQ_FOREACH(counter, &age_info->aged_counters, next) {
10700                 nb_flows++;
10701                 if (nb_contexts) {
10702                         age_param = MLX5_CNT_TO_AGE(counter);
10703                         context[nb_flows - 1] = age_param->context;
10704                         if (!(--nb_contexts))
10705                                 break;
10706                 }
10707         }
10708         rte_spinlock_unlock(&age_info->aged_sl);
10709         MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
10710         return nb_flows;
10711 }
10712
10713 /*
10714  * Mutex-protected thunk to lock-free  __flow_dv_translate().
10715  */
10716 static int
10717 flow_dv_translate(struct rte_eth_dev *dev,
10718                   struct mlx5_flow *dev_flow,
10719                   const struct rte_flow_attr *attr,
10720                   const struct rte_flow_item items[],
10721                   const struct rte_flow_action actions[],
10722                   struct rte_flow_error *error)
10723 {
10724         int ret;
10725
10726         flow_dv_shared_lock(dev);
10727         ret = __flow_dv_translate(dev, dev_flow, attr, items, actions, error);
10728         flow_dv_shared_unlock(dev);
10729         return ret;
10730 }
10731
10732 /*
10733  * Mutex-protected thunk to lock-free  __flow_dv_apply().
10734  */
10735 static int
10736 flow_dv_apply(struct rte_eth_dev *dev,
10737               struct rte_flow *flow,
10738               struct rte_flow_error *error)
10739 {
10740         int ret;
10741
10742         flow_dv_shared_lock(dev);
10743         ret = __flow_dv_apply(dev, flow, error);
10744         flow_dv_shared_unlock(dev);
10745         return ret;
10746 }
10747
10748 /*
10749  * Mutex-protected thunk to lock-free __flow_dv_remove().
10750  */
10751 static void
10752 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
10753 {
10754         flow_dv_shared_lock(dev);
10755         __flow_dv_remove(dev, flow);
10756         flow_dv_shared_unlock(dev);
10757 }
10758
10759 /*
10760  * Mutex-protected thunk to lock-free __flow_dv_destroy().
10761  */
10762 static void
10763 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
10764 {
10765         flow_dv_shared_lock(dev);
10766         __flow_dv_destroy(dev, flow);
10767         flow_dv_shared_unlock(dev);
10768 }
10769
10770 /*
10771  * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
10772  */
10773 static uint32_t
10774 flow_dv_counter_allocate(struct rte_eth_dev *dev)
10775 {
10776         uint32_t cnt;
10777
10778         flow_dv_shared_lock(dev);
10779         cnt = flow_dv_counter_alloc(dev, 0, 0, 1, 0);
10780         flow_dv_shared_unlock(dev);
10781         return cnt;
10782 }
10783
10784 /*
10785  * Mutex-protected thunk to lock-free flow_dv_counter_release().
10786  */
10787 static void
10788 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t cnt)
10789 {
10790         flow_dv_shared_lock(dev);
10791         flow_dv_counter_release(dev, cnt);
10792         flow_dv_shared_unlock(dev);
10793 }
10794
10795 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
10796         .validate = flow_dv_validate,
10797         .prepare = flow_dv_prepare,
10798         .translate = flow_dv_translate,
10799         .apply = flow_dv_apply,
10800         .remove = flow_dv_remove,
10801         .destroy = flow_dv_destroy,
10802         .query = flow_dv_query,
10803         .create_mtr_tbls = flow_dv_create_mtr_tbl,
10804         .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
10805         .create_policer_rules = flow_dv_create_policer_rules,
10806         .destroy_policer_rules = flow_dv_destroy_policer_rules,
10807         .counter_alloc = flow_dv_counter_allocate,
10808         .counter_free = flow_dv_counter_free,
10809         .counter_query = flow_dv_counter_query,
10810         .get_aged_flows = flow_get_aged_flows,
10811 };
10812
10813 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */
10814