drivers/net/mlx5/mlx5_flow_dv.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2018 Mellanox Technologies, Ltd
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdalign.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10
  11 #include <rte_common.h>
  12 #include <rte_ether.h>
  13 #include <ethdev_driver.h>
  14 #include <rte_flow.h>
  15 #include <rte_flow_driver.h>
  16 #include <rte_malloc.h>
  17 #include <rte_cycles.h>
  18 #include <rte_ip.h>
  19 #include <rte_gre.h>
  20 #include <rte_vxlan.h>
  21 #include <rte_gtp.h>
  22 #include <rte_eal_paging.h>
  23 #include <rte_mpls.h>
  24
  25 #include <mlx5_glue.h>
  26 #include <mlx5_devx_cmds.h>
  27 #include <mlx5_prm.h>
  28 #include <mlx5_malloc.h>
  29
  30 #include "mlx5_defs.h"
  31 #include "mlx5.h"
  32 #include "mlx5_common_os.h"
  33 #include "mlx5_flow.h"
  34 #include "mlx5_flow_os.h"
  35 #include "mlx5_rxtx.h"
  36 #include "rte_pmd_mlx5.h"
  37
  38 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
  39
  40 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
  41 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
  42 #endif
  43
  44 #ifndef HAVE_MLX5DV_DR_ESWITCH
  45 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
  46 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
  47 #endif
  48 #endif
  49
  50 #ifndef HAVE_MLX5DV_DR
  51 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
  52 #endif
  53
  54 /* VLAN header definitions */
  55 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
  56 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
  57 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
  58 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
  59 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
  60
  61 union flow_dv_attr {
  62         struct {
  63                 uint32_t valid:1;
  64                 uint32_t ipv4:1;
  65                 uint32_t ipv6:1;
  66                 uint32_t tcp:1;
  67                 uint32_t udp:1;
  68                 uint32_t reserved:27;
  69         };
  70         uint32_t attr;
  71 };
  72
  73 static int
  74 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
  75                              struct mlx5_flow_tbl_resource *tbl);
  76
  77 static int
  78 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
  79                                      uint32_t encap_decap_idx);
  80
  81 static int
  82 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
  83                                         uint32_t port_id);
  84 static void
  85 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss);
  86
  87 static int
  88 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
  89                                   uint32_t rix_jump);
  90
  91 /**
  92  * Initialize flow attributes structure according to flow items' types.
  93  *
  94  * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
  95  * mode. For tunnel mode, the items to be modified are the outermost ones.
  96  *
  97  * @param[in] item
  98  *   Pointer to item specification.
  99  * @param[out] attr
 100  *   Pointer to flow attributes structure.
 101  * @param[in] dev_flow
 102  *   Pointer to the sub flow.
 103  * @param[in] tunnel_decap
 104  *   Whether action is after tunnel decapsulation.
 105  */
 106 static void
 107 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
 108                   struct mlx5_flow *dev_flow, bool tunnel_decap)
 109 {
 110         uint64_t layers = dev_flow->handle->layers;
 111
 112         /*
 113          * If layers is already initialized, it means this dev_flow is the
 114          * suffix flow, the layers flags is set by the prefix flow. Need to
 115          * use the layer flags from prefix flow as the suffix flow may not
 116          * have the user defined items as the flow is split.
 117          */
 118         if (layers) {
 119                 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
 120                         attr->ipv4 = 1;
 121                 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
 122                         attr->ipv6 = 1;
 123                 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
 124                         attr->tcp = 1;
 125                 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
 126                         attr->udp = 1;
 127                 attr->valid = 1;
 128                 return;
 129         }
 130         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
 131                 uint8_t next_protocol = 0xff;
 132                 switch (item->type) {
 133                 case RTE_FLOW_ITEM_TYPE_GRE:
 134                 case RTE_FLOW_ITEM_TYPE_NVGRE:
 135                 case RTE_FLOW_ITEM_TYPE_VXLAN:
 136                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
 137                 case RTE_FLOW_ITEM_TYPE_GENEVE:
 138                 case RTE_FLOW_ITEM_TYPE_MPLS:
 139                         if (tunnel_decap)
 140                                 attr->attr = 0;
 141                         break;
 142                 case RTE_FLOW_ITEM_TYPE_IPV4:
 143                         if (!attr->ipv6)
 144                                 attr->ipv4 = 1;
 145                         if (item->mask != NULL &&
 146                             ((const struct rte_flow_item_ipv4 *)
 147                             item->mask)->hdr.next_proto_id)
 148                                 next_protocol =
 149                                     ((const struct rte_flow_item_ipv4 *)
 150                                       (item->spec))->hdr.next_proto_id &
 151                                     ((const struct rte_flow_item_ipv4 *)
 152                                       (item->mask))->hdr.next_proto_id;
 153                         if ((next_protocol == IPPROTO_IPIP ||
 154                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 155                                 attr->attr = 0;
 156                         break;
 157                 case RTE_FLOW_ITEM_TYPE_IPV6:
 158                         if (!attr->ipv4)
 159                                 attr->ipv6 = 1;
 160                         if (item->mask != NULL &&
 161                             ((const struct rte_flow_item_ipv6 *)
 162                             item->mask)->hdr.proto)
 163                                 next_protocol =
 164                                     ((const struct rte_flow_item_ipv6 *)
 165                                       (item->spec))->hdr.proto &
 166                                     ((const struct rte_flow_item_ipv6 *)
 167                                       (item->mask))->hdr.proto;
 168                         if ((next_protocol == IPPROTO_IPIP ||
 169                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 170                                 attr->attr = 0;
 171                         break;
 172                 case RTE_FLOW_ITEM_TYPE_UDP:
 173                         if (!attr->tcp)
 174                                 attr->udp = 1;
 175                         break;
 176                 case RTE_FLOW_ITEM_TYPE_TCP:
 177                         if (!attr->udp)
 178                                 attr->tcp = 1;
 179                         break;
 180                 default:
 181                         break;
 182                 }
 183         }
 184         attr->valid = 1;
 185 }
 186
 187 /**
 188  * Convert rte_mtr_color to mlx5 color.
 189  *
 190  * @param[in] rcol
 191  *   rte_mtr_color.
 192  *
 193  * @return
 194  *   mlx5 color.
 195  */
 196 static int
 197 rte_col_2_mlx5_col(enum rte_color rcol)
 198 {
 199         switch (rcol) {
 200         case RTE_COLOR_GREEN:
 201                 return MLX5_FLOW_COLOR_GREEN;
 202         case RTE_COLOR_YELLOW:
 203                 return MLX5_FLOW_COLOR_YELLOW;
 204         case RTE_COLOR_RED:
 205                 return MLX5_FLOW_COLOR_RED;
 206         default:
 207                 break;
 208         }
 209         return MLX5_FLOW_COLOR_UNDEFINED;
 210 }
 211
 212 struct field_modify_info {
 213         uint32_t size; /* Size of field in protocol header, in bytes. */
 214         uint32_t offset; /* Offset of field in protocol header, in bytes. */
 215         enum mlx5_modification_field id;
 216 };
 217
 218 struct field_modify_info modify_eth[] = {
 219         {4,  0, MLX5_MODI_OUT_DMAC_47_16},
 220         {2,  4, MLX5_MODI_OUT_DMAC_15_0},
 221         {4,  6, MLX5_MODI_OUT_SMAC_47_16},
 222         {2, 10, MLX5_MODI_OUT_SMAC_15_0},
 223         {0, 0, 0},
 224 };
 225
 226 struct field_modify_info modify_vlan_out_first_vid[] = {
 227         /* Size in bits !!! */
 228         {12, 0, MLX5_MODI_OUT_FIRST_VID},
 229         {0, 0, 0},
 230 };
 231
 232 struct field_modify_info modify_ipv4[] = {
 233         {1,  1, MLX5_MODI_OUT_IP_DSCP},
 234         {1,  8, MLX5_MODI_OUT_IPV4_TTL},
 235         {4, 12, MLX5_MODI_OUT_SIPV4},
 236         {4, 16, MLX5_MODI_OUT_DIPV4},
 237         {0, 0, 0},
 238 };
 239
 240 struct field_modify_info modify_ipv6[] = {
 241         {1,  0, MLX5_MODI_OUT_IP_DSCP},
 242         {1,  7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
 243         {4,  8, MLX5_MODI_OUT_SIPV6_127_96},
 244         {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
 245         {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
 246         {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
 247         {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
 248         {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
 249         {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
 250         {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
 251         {0, 0, 0},
 252 };
 253
 254 struct field_modify_info modify_udp[] = {
 255         {2, 0, MLX5_MODI_OUT_UDP_SPORT},
 256         {2, 2, MLX5_MODI_OUT_UDP_DPORT},
 257         {0, 0, 0},
 258 };
 259
 260 struct field_modify_info modify_tcp[] = {
 261         {2, 0, MLX5_MODI_OUT_TCP_SPORT},
 262         {2, 2, MLX5_MODI_OUT_TCP_DPORT},
 263         {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
 264         {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
 265         {0, 0, 0},
 266 };
 267
 268 static void
 269 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
 270                           uint8_t next_protocol, uint64_t *item_flags,
 271                           int *tunnel)
 272 {
 273         MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
 274                     item->type == RTE_FLOW_ITEM_TYPE_IPV6);
 275         if (next_protocol == IPPROTO_IPIP) {
 276                 *item_flags |= MLX5_FLOW_LAYER_IPIP;
 277                 *tunnel = 1;
 278         }
 279         if (next_protocol == IPPROTO_IPV6) {
 280                 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
 281                 *tunnel = 1;
 282         }
 283 }
 284
 285 /* Update VLAN's VID/PCP based on input rte_flow_action.
 286  *
 287  * @param[in] action
 288  *   Pointer to struct rte_flow_action.
 289  * @param[out] vlan
 290  *   Pointer to struct rte_vlan_hdr.
 291  */
 292 static void
 293 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
 294                          struct rte_vlan_hdr *vlan)
 295 {
 296         uint16_t vlan_tci;
 297         if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
 298                 vlan_tci =
 299                     ((const struct rte_flow_action_of_set_vlan_pcp *)
 300                                                action->conf)->vlan_pcp;
 301                 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
 302                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
 303                 vlan->vlan_tci |= vlan_tci;
 304         } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
 305                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
 306                 vlan->vlan_tci |= rte_be_to_cpu_16
 307                     (((const struct rte_flow_action_of_set_vlan_vid *)
 308                                              action->conf)->vlan_vid);
 309         }
 310 }
 311
 312 /**
 313  * Fetch 1, 2, 3 or 4 byte field from the byte array
 314  * and return as unsigned integer in host-endian format.
 315  *
 316  * @param[in] data
 317  *   Pointer to data array.
 318  * @param[in] size
 319  *   Size of field to extract.
 320  *
 321  * @return
 322  *   converted field in host endian format.
 323  */
 324 static inline uint32_t
 325 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
 326 {
 327         uint32_t ret;
 328
 329         switch (size) {
 330         case 1:
 331                 ret = *data;
 332                 break;
 333         case 2:
 334                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 335                 break;
 336         case 3:
 337                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 338                 ret = (ret << 8) | *(data + sizeof(uint16_t));
 339                 break;
 340         case 4:
 341                 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
 342                 break;
 343         default:
 344                 MLX5_ASSERT(false);
 345                 ret = 0;
 346                 break;
 347         }
 348         return ret;
 349 }
 350
 351 /**
 352  * Convert modify-header action to DV specification.
 353  *
 354  * Data length of each action is determined by provided field description
 355  * and the item mask. Data bit offset and width of each action is determined
 356  * by provided item mask.
 357  *
 358  * @param[in] item
 359  *   Pointer to item specification.
 360  * @param[in] field
 361  *   Pointer to field modification information.
 362  *     For MLX5_MODIFICATION_TYPE_SET specifies destination field.
 363  *     For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
 364  *     For MLX5_MODIFICATION_TYPE_COPY specifies source field.
 365  * @param[in] dcopy
 366  *   Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
 367  *   Negative offset value sets the same offset as source offset.
 368  *   size field is ignored, value is taken from source field.
 369  * @param[in,out] resource
 370  *   Pointer to the modify-header resource.
 371  * @param[in] type
 372  *   Type of modification.
 373  * @param[out] error
 374  *   Pointer to the error structure.
 375  *
 376  * @return
 377  *   0 on success, a negative errno value otherwise and rte_errno is set.
 378  */
 379 static int
 380 flow_dv_convert_modify_action(struct rte_flow_item *item,
 381                               struct field_modify_info *field,
 382                               struct field_modify_info *dcopy,
 383                               struct mlx5_flow_dv_modify_hdr_resource *resource,
 384                               uint32_t type, struct rte_flow_error *error)
 385 {
 386         uint32_t i = resource->actions_num;
 387         struct mlx5_modification_cmd *actions = resource->actions;
 388
 389         /*
 390          * The item and mask are provided in big-endian format.
 391          * The fields should be presented as in big-endian format either.
 392          * Mask must be always present, it defines the actual field width.
 393          */
 394         MLX5_ASSERT(item->mask);
 395         MLX5_ASSERT(field->size);
 396         do {
 397                 unsigned int size_b;
 398                 unsigned int off_b;
 399                 uint32_t mask;
 400                 uint32_t data;
 401
 402                 if (i >= MLX5_MAX_MODIFY_NUM)
 403                         return rte_flow_error_set(error, EINVAL,
 404                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 405                                  "too many items to modify");
 406                 /* Fetch variable byte size mask from the array. */
 407                 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
 408                                            field->offset, field->size);
 409                 if (!mask) {
 410                         ++field;
 411                         continue;
 412                 }
 413                 /* Deduce actual data width in bits from mask value. */
 414                 off_b = rte_bsf32(mask);
 415                 size_b = sizeof(uint32_t) * CHAR_BIT -
 416                          off_b - __builtin_clz(mask);
 417                 MLX5_ASSERT(size_b);
 418                 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
 419                 actions[i] = (struct mlx5_modification_cmd) {
 420                         .action_type = type,
 421                         .field = field->id,
 422                         .offset = off_b,
 423                         .length = size_b,
 424                 };
 425                 /* Convert entire record to expected big-endian format. */
 426                 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 427                 if (type == MLX5_MODIFICATION_TYPE_COPY) {
 428                         MLX5_ASSERT(dcopy);
 429                         actions[i].dst_field = dcopy->id;
 430                         actions[i].dst_offset =
 431                                 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
 432                         /* Convert entire record to big-endian format. */
 433                         actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
 434                         ++dcopy;
 435                 } else {
 436                         MLX5_ASSERT(item->spec);
 437                         data = flow_dv_fetch_field((const uint8_t *)item->spec +
 438                                                    field->offset, field->size);
 439                         /* Shift out the trailing masked bits from data. */
 440                         data = (data & mask) >> off_b;
 441                         actions[i].data1 = rte_cpu_to_be_32(data);
 442                 }
 443                 ++i;
 444                 ++field;
 445         } while (field->size);
 446         if (resource->actions_num == i)
 447                 return rte_flow_error_set(error, EINVAL,
 448                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 449                                           "invalid modification flow item");
 450         resource->actions_num = i;
 451         return 0;
 452 }
 453
 454 /**
 455  * Convert modify-header set IPv4 address action to DV specification.
 456  *
 457  * @param[in,out] resource
 458  *   Pointer to the modify-header resource.
 459  * @param[in] action
 460  *   Pointer to action specification.
 461  * @param[out] error
 462  *   Pointer to the error structure.
 463  *
 464  * @return
 465  *   0 on success, a negative errno value otherwise and rte_errno is set.
 466  */
 467 static int
 468 flow_dv_convert_action_modify_ipv4
 469                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 470                          const struct rte_flow_action *action,
 471                          struct rte_flow_error *error)
 472 {
 473         const struct rte_flow_action_set_ipv4 *conf =
 474                 (const struct rte_flow_action_set_ipv4 *)(action->conf);
 475         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
 476         struct rte_flow_item_ipv4 ipv4;
 477         struct rte_flow_item_ipv4 ipv4_mask;
 478
 479         memset(&ipv4, 0, sizeof(ipv4));
 480         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 481         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
 482                 ipv4.hdr.src_addr = conf->ipv4_addr;
 483                 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
 484         } else {
 485                 ipv4.hdr.dst_addr = conf->ipv4_addr;
 486                 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
 487         }
 488         item.spec = &ipv4;
 489         item.mask = &ipv4_mask;
 490         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
 491                                              MLX5_MODIFICATION_TYPE_SET, error);
 492 }
 493
 494 /**
 495  * Convert modify-header set IPv6 address action to DV specification.
 496  *
 497  * @param[in,out] resource
 498  *   Pointer to the modify-header resource.
 499  * @param[in] action
 500  *   Pointer to action specification.
 501  * @param[out] error
 502  *   Pointer to the error structure.
 503  *
 504  * @return
 505  *   0 on success, a negative errno value otherwise and rte_errno is set.
 506  */
 507 static int
 508 flow_dv_convert_action_modify_ipv6
 509                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 510                          const struct rte_flow_action *action,
 511                          struct rte_flow_error *error)
 512 {
 513         const struct rte_flow_action_set_ipv6 *conf =
 514                 (const struct rte_flow_action_set_ipv6 *)(action->conf);
 515         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
 516         struct rte_flow_item_ipv6 ipv6;
 517         struct rte_flow_item_ipv6 ipv6_mask;
 518
 519         memset(&ipv6, 0, sizeof(ipv6));
 520         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 521         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
 522                 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
 523                        sizeof(ipv6.hdr.src_addr));
 524                 memcpy(&ipv6_mask.hdr.src_addr,
 525                        &rte_flow_item_ipv6_mask.hdr.src_addr,
 526                        sizeof(ipv6.hdr.src_addr));
 527         } else {
 528                 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
 529                        sizeof(ipv6.hdr.dst_addr));
 530                 memcpy(&ipv6_mask.hdr.dst_addr,
 531                        &rte_flow_item_ipv6_mask.hdr.dst_addr,
 532                        sizeof(ipv6.hdr.dst_addr));
 533         }
 534         item.spec = &ipv6;
 535         item.mask = &ipv6_mask;
 536         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
 537                                              MLX5_MODIFICATION_TYPE_SET, error);
 538 }
 539
 540 /**
 541  * Convert modify-header set MAC address action to DV specification.
 542  *
 543  * @param[in,out] resource
 544  *   Pointer to the modify-header resource.
 545  * @param[in] action
 546  *   Pointer to action specification.
 547  * @param[out] error
 548  *   Pointer to the error structure.
 549  *
 550  * @return
 551  *   0 on success, a negative errno value otherwise and rte_errno is set.
 552  */
 553 static int
 554 flow_dv_convert_action_modify_mac
 555                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 556                          const struct rte_flow_action *action,
 557                          struct rte_flow_error *error)
 558 {
 559         const struct rte_flow_action_set_mac *conf =
 560                 (const struct rte_flow_action_set_mac *)(action->conf);
 561         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
 562         struct rte_flow_item_eth eth;
 563         struct rte_flow_item_eth eth_mask;
 564
 565         memset(&eth, 0, sizeof(eth));
 566         memset(&eth_mask, 0, sizeof(eth_mask));
 567         if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
 568                 memcpy(&eth.src.addr_bytes, &conf->mac_addr,
 569                        sizeof(eth.src.addr_bytes));
 570                 memcpy(&eth_mask.src.addr_bytes,
 571                        &rte_flow_item_eth_mask.src.addr_bytes,
 572                        sizeof(eth_mask.src.addr_bytes));
 573         } else {
 574                 memcpy(&eth.dst.addr_bytes, &conf->mac_addr,
 575                        sizeof(eth.dst.addr_bytes));
 576                 memcpy(&eth_mask.dst.addr_bytes,
 577                        &rte_flow_item_eth_mask.dst.addr_bytes,
 578                        sizeof(eth_mask.dst.addr_bytes));
 579         }
 580         item.spec = &eth;
 581         item.mask = &eth_mask;
 582         return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
 583                                              MLX5_MODIFICATION_TYPE_SET, error);
 584 }
 585
 586 /**
 587  * Convert modify-header set VLAN VID action to DV specification.
 588  *
 589  * @param[in,out] resource
 590  *   Pointer to the modify-header resource.
 591  * @param[in] action
 592  *   Pointer to action specification.
 593  * @param[out] error
 594  *   Pointer to the error structure.
 595  *
 596  * @return
 597  *   0 on success, a negative errno value otherwise and rte_errno is set.
 598  */
 599 static int
 600 flow_dv_convert_action_modify_vlan_vid
 601                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 602                          const struct rte_flow_action *action,
 603                          struct rte_flow_error *error)
 604 {
 605         const struct rte_flow_action_of_set_vlan_vid *conf =
 606                 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
 607         int i = resource->actions_num;
 608         struct mlx5_modification_cmd *actions = resource->actions;
 609         struct field_modify_info *field = modify_vlan_out_first_vid;
 610
 611         if (i >= MLX5_MAX_MODIFY_NUM)
 612                 return rte_flow_error_set(error, EINVAL,
 613                          RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 614                          "too many items to modify");
 615         actions[i] = (struct mlx5_modification_cmd) {
 616                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 617                 .field = field->id,
 618                 .length = field->size,
 619                 .offset = field->offset,
 620         };
 621         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 622         actions[i].data1 = conf->vlan_vid;
 623         actions[i].data1 = actions[i].data1 << 16;
 624         resource->actions_num = ++i;
 625         return 0;
 626 }
 627
 628 /**
 629  * Convert modify-header set TP action to DV specification.
 630  *
 631  * @param[in,out] resource
 632  *   Pointer to the modify-header resource.
 633  * @param[in] action
 634  *   Pointer to action specification.
 635  * @param[in] items
 636  *   Pointer to rte_flow_item objects list.
 637  * @param[in] attr
 638  *   Pointer to flow attributes structure.
 639  * @param[in] dev_flow
 640  *   Pointer to the sub flow.
 641  * @param[in] tunnel_decap
 642  *   Whether action is after tunnel decapsulation.
 643  * @param[out] error
 644  *   Pointer to the error structure.
 645  *
 646  * @return
 647  *   0 on success, a negative errno value otherwise and rte_errno is set.
 648  */
 649 static int
 650 flow_dv_convert_action_modify_tp
 651                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 652                          const struct rte_flow_action *action,
 653                          const struct rte_flow_item *items,
 654                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 655                          bool tunnel_decap, struct rte_flow_error *error)
 656 {
 657         const struct rte_flow_action_set_tp *conf =
 658                 (const struct rte_flow_action_set_tp *)(action->conf);
 659         struct rte_flow_item item;
 660         struct rte_flow_item_udp udp;
 661         struct rte_flow_item_udp udp_mask;
 662         struct rte_flow_item_tcp tcp;
 663         struct rte_flow_item_tcp tcp_mask;
 664         struct field_modify_info *field;
 665
 666         if (!attr->valid)
 667                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 668         if (attr->udp) {
 669                 memset(&udp, 0, sizeof(udp));
 670                 memset(&udp_mask, 0, sizeof(udp_mask));
 671                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 672                         udp.hdr.src_port = conf->port;
 673                         udp_mask.hdr.src_port =
 674                                         rte_flow_item_udp_mask.hdr.src_port;
 675                 } else {
 676                         udp.hdr.dst_port = conf->port;
 677                         udp_mask.hdr.dst_port =
 678                                         rte_flow_item_udp_mask.hdr.dst_port;
 679                 }
 680                 item.type = RTE_FLOW_ITEM_TYPE_UDP;
 681                 item.spec = &udp;
 682                 item.mask = &udp_mask;
 683                 field = modify_udp;
 684         } else {
 685                 MLX5_ASSERT(attr->tcp);
 686                 memset(&tcp, 0, sizeof(tcp));
 687                 memset(&tcp_mask, 0, sizeof(tcp_mask));
 688                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 689                         tcp.hdr.src_port = conf->port;
 690                         tcp_mask.hdr.src_port =
 691                                         rte_flow_item_tcp_mask.hdr.src_port;
 692                 } else {
 693                         tcp.hdr.dst_port = conf->port;
 694                         tcp_mask.hdr.dst_port =
 695                                         rte_flow_item_tcp_mask.hdr.dst_port;
 696                 }
 697                 item.type = RTE_FLOW_ITEM_TYPE_TCP;
 698                 item.spec = &tcp;
 699                 item.mask = &tcp_mask;
 700                 field = modify_tcp;
 701         }
 702         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 703                                              MLX5_MODIFICATION_TYPE_SET, error);
 704 }
 705
 706 /**
 707  * Convert modify-header set TTL action to DV specification.
 708  *
 709  * @param[in,out] resource
 710  *   Pointer to the modify-header resource.
 711  * @param[in] action
 712  *   Pointer to action specification.
 713  * @param[in] items
 714  *   Pointer to rte_flow_item objects list.
 715  * @param[in] attr
 716  *   Pointer to flow attributes structure.
 717  * @param[in] dev_flow
 718  *   Pointer to the sub flow.
 719  * @param[in] tunnel_decap
 720  *   Whether action is after tunnel decapsulation.
 721  * @param[out] error
 722  *   Pointer to the error structure.
 723  *
 724  * @return
 725  *   0 on success, a negative errno value otherwise and rte_errno is set.
 726  */
 727 static int
 728 flow_dv_convert_action_modify_ttl
 729                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 730                          const struct rte_flow_action *action,
 731                          const struct rte_flow_item *items,
 732                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 733                          bool tunnel_decap, struct rte_flow_error *error)
 734 {
 735         const struct rte_flow_action_set_ttl *conf =
 736                 (const struct rte_flow_action_set_ttl *)(action->conf);
 737         struct rte_flow_item item;
 738         struct rte_flow_item_ipv4 ipv4;
 739         struct rte_flow_item_ipv4 ipv4_mask;
 740         struct rte_flow_item_ipv6 ipv6;
 741         struct rte_flow_item_ipv6 ipv6_mask;
 742         struct field_modify_info *field;
 743
 744         if (!attr->valid)
 745                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 746         if (attr->ipv4) {
 747                 memset(&ipv4, 0, sizeof(ipv4));
 748                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 749                 ipv4.hdr.time_to_live = conf->ttl_value;
 750                 ipv4_mask.hdr.time_to_live = 0xFF;
 751                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 752                 item.spec = &ipv4;
 753                 item.mask = &ipv4_mask;
 754                 field = modify_ipv4;
 755         } else {
 756                 MLX5_ASSERT(attr->ipv6);
 757                 memset(&ipv6, 0, sizeof(ipv6));
 758                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 759                 ipv6.hdr.hop_limits = conf->ttl_value;
 760                 ipv6_mask.hdr.hop_limits = 0xFF;
 761                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 762                 item.spec = &ipv6;
 763                 item.mask = &ipv6_mask;
 764                 field = modify_ipv6;
 765         }
 766         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 767                                              MLX5_MODIFICATION_TYPE_SET, error);
 768 }
 769
 770 /**
 771  * Convert modify-header decrement TTL action to DV specification.
 772  *
 773  * @param[in,out] resource
 774  *   Pointer to the modify-header resource.
 775  * @param[in] action
 776  *   Pointer to action specification.
 777  * @param[in] items
 778  *   Pointer to rte_flow_item objects list.
 779  * @param[in] attr
 780  *   Pointer to flow attributes structure.
 781  * @param[in] dev_flow
 782  *   Pointer to the sub flow.
 783  * @param[in] tunnel_decap
 784  *   Whether action is after tunnel decapsulation.
 785  * @param[out] error
 786  *   Pointer to the error structure.
 787  *
 788  * @return
 789  *   0 on success, a negative errno value otherwise and rte_errno is set.
 790  */
 791 static int
 792 flow_dv_convert_action_modify_dec_ttl
 793                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 794                          const struct rte_flow_item *items,
 795                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 796                          bool tunnel_decap, struct rte_flow_error *error)
 797 {
 798         struct rte_flow_item item;
 799         struct rte_flow_item_ipv4 ipv4;
 800         struct rte_flow_item_ipv4 ipv4_mask;
 801         struct rte_flow_item_ipv6 ipv6;
 802         struct rte_flow_item_ipv6 ipv6_mask;
 803         struct field_modify_info *field;
 804
 805         if (!attr->valid)
 806                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 807         if (attr->ipv4) {
 808                 memset(&ipv4, 0, sizeof(ipv4));
 809                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 810                 ipv4.hdr.time_to_live = 0xFF;
 811                 ipv4_mask.hdr.time_to_live = 0xFF;
 812                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 813                 item.spec = &ipv4;
 814                 item.mask = &ipv4_mask;
 815                 field = modify_ipv4;
 816         } else {
 817                 MLX5_ASSERT(attr->ipv6);
 818                 memset(&ipv6, 0, sizeof(ipv6));
 819                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 820                 ipv6.hdr.hop_limits = 0xFF;
 821                 ipv6_mask.hdr.hop_limits = 0xFF;
 822                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 823                 item.spec = &ipv6;
 824                 item.mask = &ipv6_mask;
 825                 field = modify_ipv6;
 826         }
 827         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 828                                              MLX5_MODIFICATION_TYPE_ADD, error);
 829 }
 830
 831 /**
 832  * Convert modify-header increment/decrement TCP Sequence number
 833  * to DV specification.
 834  *
 835  * @param[in,out] resource
 836  *   Pointer to the modify-header resource.
 837  * @param[in] action
 838  *   Pointer to action specification.
 839  * @param[out] error
 840  *   Pointer to the error structure.
 841  *
 842  * @return
 843  *   0 on success, a negative errno value otherwise and rte_errno is set.
 844  */
 845 static int
 846 flow_dv_convert_action_modify_tcp_seq
 847                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 848                          const struct rte_flow_action *action,
 849                          struct rte_flow_error *error)
 850 {
 851         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 852         uint64_t value = rte_be_to_cpu_32(*conf);
 853         struct rte_flow_item item;
 854         struct rte_flow_item_tcp tcp;
 855         struct rte_flow_item_tcp tcp_mask;
 856
 857         memset(&tcp, 0, sizeof(tcp));
 858         memset(&tcp_mask, 0, sizeof(tcp_mask));
 859         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
 860                 /*
 861                  * The HW has no decrement operation, only increment operation.
 862                  * To simulate decrement X from Y using increment operation
 863                  * we need to add UINT32_MAX X times to Y.
 864                  * Each adding of UINT32_MAX decrements Y by 1.
 865                  */
 866                 value *= UINT32_MAX;
 867         tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
 868         tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
 869         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 870         item.spec = &tcp;
 871         item.mask = &tcp_mask;
 872         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 873                                              MLX5_MODIFICATION_TYPE_ADD, error);
 874 }
 875
 876 /**
 877  * Convert modify-header increment/decrement TCP Acknowledgment number
 878  * to DV specification.
 879  *
 880  * @param[in,out] resource
 881  *   Pointer to the modify-header resource.
 882  * @param[in] action
 883  *   Pointer to action specification.
 884  * @param[out] error
 885  *   Pointer to the error structure.
 886  *
 887  * @return
 888  *   0 on success, a negative errno value otherwise and rte_errno is set.
 889  */
 890 static int
 891 flow_dv_convert_action_modify_tcp_ack
 892                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 893                          const struct rte_flow_action *action,
 894                          struct rte_flow_error *error)
 895 {
 896         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 897         uint64_t value = rte_be_to_cpu_32(*conf);
 898         struct rte_flow_item item;
 899         struct rte_flow_item_tcp tcp;
 900         struct rte_flow_item_tcp tcp_mask;
 901
 902         memset(&tcp, 0, sizeof(tcp));
 903         memset(&tcp_mask, 0, sizeof(tcp_mask));
 904         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
 905                 /*
 906                  * The HW has no decrement operation, only increment operation.
 907                  * To simulate decrement X from Y using increment operation
 908                  * we need to add UINT32_MAX X times to Y.
 909                  * Each adding of UINT32_MAX decrements Y by 1.
 910                  */
 911                 value *= UINT32_MAX;
 912         tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
 913         tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
 914         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 915         item.spec = &tcp;
 916         item.mask = &tcp_mask;
 917         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 918                                              MLX5_MODIFICATION_TYPE_ADD, error);
 919 }
 920
 921 static enum mlx5_modification_field reg_to_field[] = {
 922         [REG_NON] = MLX5_MODI_OUT_NONE,
 923         [REG_A] = MLX5_MODI_META_DATA_REG_A,
 924         [REG_B] = MLX5_MODI_META_DATA_REG_B,
 925         [REG_C_0] = MLX5_MODI_META_REG_C_0,
 926         [REG_C_1] = MLX5_MODI_META_REG_C_1,
 927         [REG_C_2] = MLX5_MODI_META_REG_C_2,
 928         [REG_C_3] = MLX5_MODI_META_REG_C_3,
 929         [REG_C_4] = MLX5_MODI_META_REG_C_4,
 930         [REG_C_5] = MLX5_MODI_META_REG_C_5,
 931         [REG_C_6] = MLX5_MODI_META_REG_C_6,
 932         [REG_C_7] = MLX5_MODI_META_REG_C_7,
 933 };
 934
 935 /**
 936  * Convert register set to DV specification.
 937  *
 938  * @param[in,out] resource
 939  *   Pointer to the modify-header resource.
 940  * @param[in] action
 941  *   Pointer to action specification.
 942  * @param[out] error
 943  *   Pointer to the error structure.
 944  *
 945  * @return
 946  *   0 on success, a negative errno value otherwise and rte_errno is set.
 947  */
 948 static int
 949 flow_dv_convert_action_set_reg
 950                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 951                          const struct rte_flow_action *action,
 952                          struct rte_flow_error *error)
 953 {
 954         const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
 955         struct mlx5_modification_cmd *actions = resource->actions;
 956         uint32_t i = resource->actions_num;
 957
 958         if (i >= MLX5_MAX_MODIFY_NUM)
 959                 return rte_flow_error_set(error, EINVAL,
 960                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 961                                           "too many items to modify");
 962         MLX5_ASSERT(conf->id != REG_NON);
 963         MLX5_ASSERT(conf->id < (enum modify_reg)RTE_DIM(reg_to_field));
 964         actions[i] = (struct mlx5_modification_cmd) {
 965                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 966                 .field = reg_to_field[conf->id],
 967         };
 968         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 969         actions[i].data1 = rte_cpu_to_be_32(conf->data);
 970         ++i;
 971         resource->actions_num = i;
 972         return 0;
 973 }
 974
 975 /**
 976  * Convert SET_TAG action to DV specification.
 977  *
 978  * @param[in] dev
 979  *   Pointer to the rte_eth_dev structure.
 980  * @param[in,out] resource
 981  *   Pointer to the modify-header resource.
 982  * @param[in] conf
 983  *   Pointer to action specification.
 984  * @param[out] error
 985  *   Pointer to the error structure.
 986  *
 987  * @return
 988  *   0 on success, a negative errno value otherwise and rte_errno is set.
 989  */
 990 static int
 991 flow_dv_convert_action_set_tag
 992                         (struct rte_eth_dev *dev,
 993                          struct mlx5_flow_dv_modify_hdr_resource *resource,
 994                          const struct rte_flow_action_set_tag *conf,
 995                          struct rte_flow_error *error)
 996 {
 997         rte_be32_t data = rte_cpu_to_be_32(conf->data);
 998         rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
 999         struct rte_flow_item item = {
1000                 .spec = &data,
1001                 .mask = &mask,
1002         };
1003         struct field_modify_info reg_c_x[] = {
1004                 [1] = {0, 0, 0},
1005         };
1006         enum mlx5_modification_field reg_type;
1007         int ret;
1008
1009         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1010         if (ret < 0)
1011                 return ret;
1012         MLX5_ASSERT(ret != REG_NON);
1013         MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1014         reg_type = reg_to_field[ret];
1015         MLX5_ASSERT(reg_type > 0);
1016         reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1017         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1018                                              MLX5_MODIFICATION_TYPE_SET, error);
1019 }
1020
1021 /**
1022  * Convert internal COPY_REG action to DV specification.
1023  *
1024  * @param[in] dev
1025  *   Pointer to the rte_eth_dev structure.
1026  * @param[in,out] res
1027  *   Pointer to the modify-header resource.
1028  * @param[in] action
1029  *   Pointer to action specification.
1030  * @param[out] error
1031  *   Pointer to the error structure.
1032  *
1033  * @return
1034  *   0 on success, a negative errno value otherwise and rte_errno is set.
1035  */
1036 static int
1037 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1038                                  struct mlx5_flow_dv_modify_hdr_resource *res,
1039                                  const struct rte_flow_action *action,
1040                                  struct rte_flow_error *error)
1041 {
1042         const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1043         rte_be32_t mask = RTE_BE32(UINT32_MAX);
1044         struct rte_flow_item item = {
1045                 .spec = NULL,
1046                 .mask = &mask,
1047         };
1048         struct field_modify_info reg_src[] = {
1049                 {4, 0, reg_to_field[conf->src]},
1050                 {0, 0, 0},
1051         };
1052         struct field_modify_info reg_dst = {
1053                 .offset = 0,
1054                 .id = reg_to_field[conf->dst],
1055         };
1056         /* Adjust reg_c[0] usage according to reported mask. */
1057         if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1058                 struct mlx5_priv *priv = dev->data->dev_private;
1059                 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1060
1061                 MLX5_ASSERT(reg_c0);
1062                 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1063                 if (conf->dst == REG_C_0) {
1064                         /* Copy to reg_c[0], within mask only. */
1065                         reg_dst.offset = rte_bsf32(reg_c0);
1066                         /*
1067                          * Mask is ignoring the enianness, because
1068                          * there is no conversion in datapath.
1069                          */
1070 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1071                         /* Copy from destination lower bits to reg_c[0]. */
1072                         mask = reg_c0 >> reg_dst.offset;
1073 #else
1074                         /* Copy from destination upper bits to reg_c[0]. */
1075                         mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1076                                           rte_fls_u32(reg_c0));
1077 #endif
1078                 } else {
1079                         mask = rte_cpu_to_be_32(reg_c0);
1080 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1081                         /* Copy from reg_c[0] to destination lower bits. */
1082                         reg_dst.offset = 0;
1083 #else
1084                         /* Copy from reg_c[0] to destination upper bits. */
1085                         reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1086                                          (rte_fls_u32(reg_c0) -
1087                                           rte_bsf32(reg_c0));
1088 #endif
1089                 }
1090         }
1091         return flow_dv_convert_modify_action(&item,
1092                                              reg_src, &reg_dst, res,
1093                                              MLX5_MODIFICATION_TYPE_COPY,
1094                                              error);
1095 }
1096
1097 /**
1098  * Convert MARK action to DV specification. This routine is used
1099  * in extensive metadata only and requires metadata register to be
1100  * handled. In legacy mode hardware tag resource is engaged.
1101  *
1102  * @param[in] dev
1103  *   Pointer to the rte_eth_dev structure.
1104  * @param[in] conf
1105  *   Pointer to MARK action specification.
1106  * @param[in,out] resource
1107  *   Pointer to the modify-header resource.
1108  * @param[out] error
1109  *   Pointer to the error structure.
1110  *
1111  * @return
1112  *   0 on success, a negative errno value otherwise and rte_errno is set.
1113  */
1114 static int
1115 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1116                             const struct rte_flow_action_mark *conf,
1117                             struct mlx5_flow_dv_modify_hdr_resource *resource,
1118                             struct rte_flow_error *error)
1119 {
1120         struct mlx5_priv *priv = dev->data->dev_private;
1121         rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1122                                            priv->sh->dv_mark_mask);
1123         rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1124         struct rte_flow_item item = {
1125                 .spec = &data,
1126                 .mask = &mask,
1127         };
1128         struct field_modify_info reg_c_x[] = {
1129                 [1] = {0, 0, 0},
1130         };
1131         int reg;
1132
1133         if (!mask)
1134                 return rte_flow_error_set(error, EINVAL,
1135                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1136                                           NULL, "zero mark action mask");
1137         reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1138         if (reg < 0)
1139                 return reg;
1140         MLX5_ASSERT(reg > 0);
1141         if (reg == REG_C_0) {
1142                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1143                 uint32_t shl_c0 = rte_bsf32(msk_c0);
1144
1145                 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1146                 mask = rte_cpu_to_be_32(mask) & msk_c0;
1147                 mask = rte_cpu_to_be_32(mask << shl_c0);
1148         }
1149         reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1150         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1151                                              MLX5_MODIFICATION_TYPE_SET, error);
1152 }
1153
1154 /**
1155  * Get metadata register index for specified steering domain.
1156  *
1157  * @param[in] dev
1158  *   Pointer to the rte_eth_dev structure.
1159  * @param[in] attr
1160  *   Attributes of flow to determine steering domain.
1161  * @param[out] error
1162  *   Pointer to the error structure.
1163  *
1164  * @return
1165  *   positive index on success, a negative errno value otherwise
1166  *   and rte_errno is set.
1167  */
1168 static enum modify_reg
1169 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1170                          const struct rte_flow_attr *attr,
1171                          struct rte_flow_error *error)
1172 {
1173         int reg =
1174                 mlx5_flow_get_reg_id(dev, attr->transfer ?
1175                                           MLX5_METADATA_FDB :
1176                                             attr->egress ?
1177                                             MLX5_METADATA_TX :
1178                                             MLX5_METADATA_RX, 0, error);
1179         if (reg < 0)
1180                 return rte_flow_error_set(error,
1181                                           ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1182                                           NULL, "unavailable "
1183                                           "metadata register");
1184         return reg;
1185 }
1186
1187 /**
1188  * Convert SET_META action to DV specification.
1189  *
1190  * @param[in] dev
1191  *   Pointer to the rte_eth_dev structure.
1192  * @param[in,out] resource
1193  *   Pointer to the modify-header resource.
1194  * @param[in] attr
1195  *   Attributes of flow that includes this item.
1196  * @param[in] conf
1197  *   Pointer to action specification.
1198  * @param[out] error
1199  *   Pointer to the error structure.
1200  *
1201  * @return
1202  *   0 on success, a negative errno value otherwise and rte_errno is set.
1203  */
1204 static int
1205 flow_dv_convert_action_set_meta
1206                         (struct rte_eth_dev *dev,
1207                          struct mlx5_flow_dv_modify_hdr_resource *resource,
1208                          const struct rte_flow_attr *attr,
1209                          const struct rte_flow_action_set_meta *conf,
1210                          struct rte_flow_error *error)
1211 {
1212         uint32_t data = conf->data;
1213         uint32_t mask = conf->mask;
1214         struct rte_flow_item item = {
1215                 .spec = &data,
1216                 .mask = &mask,
1217         };
1218         struct field_modify_info reg_c_x[] = {
1219                 [1] = {0, 0, 0},
1220         };
1221         int reg = flow_dv_get_metadata_reg(dev, attr, error);
1222
1223         if (reg < 0)
1224                 return reg;
1225         MLX5_ASSERT(reg != REG_NON);
1226         /*
1227          * In datapath code there is no endianness
1228          * coversions for perfromance reasons, all
1229          * pattern conversions are done in rte_flow.
1230          */
1231         if (reg == REG_C_0) {
1232                 struct mlx5_priv *priv = dev->data->dev_private;
1233                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1234                 uint32_t shl_c0;
1235
1236                 MLX5_ASSERT(msk_c0);
1237 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1238                 shl_c0 = rte_bsf32(msk_c0);
1239 #else
1240                 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1241 #endif
1242                 mask <<= shl_c0;
1243                 data <<= shl_c0;
1244                 MLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1245         }
1246         reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1247         /* The routine expects parameters in memory as big-endian ones. */
1248         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1249                                              MLX5_MODIFICATION_TYPE_SET, error);
1250 }
1251
1252 /**
1253  * Convert modify-header set IPv4 DSCP action to DV specification.
1254  *
1255  * @param[in,out] resource
1256  *   Pointer to the modify-header resource.
1257  * @param[in] action
1258  *   Pointer to action specification.
1259  * @param[out] error
1260  *   Pointer to the error structure.
1261  *
1262  * @return
1263  *   0 on success, a negative errno value otherwise and rte_errno is set.
1264  */
1265 static int
1266 flow_dv_convert_action_modify_ipv4_dscp
1267                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1268                          const struct rte_flow_action *action,
1269                          struct rte_flow_error *error)
1270 {
1271         const struct rte_flow_action_set_dscp *conf =
1272                 (const struct rte_flow_action_set_dscp *)(action->conf);
1273         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1274         struct rte_flow_item_ipv4 ipv4;
1275         struct rte_flow_item_ipv4 ipv4_mask;
1276
1277         memset(&ipv4, 0, sizeof(ipv4));
1278         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1279         ipv4.hdr.type_of_service = conf->dscp;
1280         ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1281         item.spec = &ipv4;
1282         item.mask = &ipv4_mask;
1283         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1284                                              MLX5_MODIFICATION_TYPE_SET, error);
1285 }
1286
1287 /**
1288  * Convert modify-header set IPv6 DSCP action to DV specification.
1289  *
1290  * @param[in,out] resource
1291  *   Pointer to the modify-header resource.
1292  * @param[in] action
1293  *   Pointer to action specification.
1294  * @param[out] error
1295  *   Pointer to the error structure.
1296  *
1297  * @return
1298  *   0 on success, a negative errno value otherwise and rte_errno is set.
1299  */
1300 static int
1301 flow_dv_convert_action_modify_ipv6_dscp
1302                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1303                          const struct rte_flow_action *action,
1304                          struct rte_flow_error *error)
1305 {
1306         const struct rte_flow_action_set_dscp *conf =
1307                 (const struct rte_flow_action_set_dscp *)(action->conf);
1308         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1309         struct rte_flow_item_ipv6 ipv6;
1310         struct rte_flow_item_ipv6 ipv6_mask;
1311
1312         memset(&ipv6, 0, sizeof(ipv6));
1313         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1314         /*
1315          * Even though the DSCP bits offset of IPv6 is not byte aligned,
1316          * rdma-core only accept the DSCP bits byte aligned start from
1317          * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1318          * bits in IPv6 case as rdma-core requires byte aligned value.
1319          */
1320         ipv6.hdr.vtc_flow = conf->dscp;
1321         ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1322         item.spec = &ipv6;
1323         item.mask = &ipv6_mask;
1324         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1325                                              MLX5_MODIFICATION_TYPE_SET, error);
1326 }
1327
1328 static void
1329 mlx5_flow_field_id_to_modify_info
1330                 (const struct rte_flow_action_modify_data *data,
1331                  struct field_modify_info *info,
1332                  uint32_t *mask, uint32_t *value, uint32_t width,
1333                  struct rte_eth_dev *dev,
1334                  const struct rte_flow_attr *attr,
1335                  struct rte_flow_error *error)
1336 {
1337         uint32_t idx = 0;
1338         switch (data->field) {
1339         case RTE_FLOW_FIELD_START:
1340                 /* not supported yet */
1341                 MLX5_ASSERT(false);
1342                 break;
1343         case RTE_FLOW_FIELD_MAC_DST:
1344                 if (mask) {
1345                         if (data->offset < 32) {
1346                                 info[idx] = (struct field_modify_info){4, 0,
1347                                                 MLX5_MODI_OUT_DMAC_47_16};
1348                                 mask[idx] = 0xffffffff;
1349                                 if (width < 32) {
1350                                         mask[idx] = mask[idx] << (32 - width);
1351                                         width = 0;
1352                                 } else {
1353                                         width -= 32;
1354                                 }
1355                                 if (!width)
1356                                         break;
1357                                 ++idx;
1358                         }
1359                         info[idx] = (struct field_modify_info){2, 4 * idx,
1360                                                 MLX5_MODI_OUT_DMAC_15_0};
1361                         mask[idx] = (width) ? 0x0000ffff : 0x0;
1362                         if (width < 16)
1363                                 mask[idx] = (mask[idx] << (16 - width)) &
1364                                                 0x0000ffff;
1365                 } else {
1366                         if (data->offset < 32)
1367                                 info[idx++] = (struct field_modify_info){4, 0,
1368                                                 MLX5_MODI_OUT_DMAC_47_16};
1369                         info[idx] = (struct field_modify_info){2, 0,
1370                                                 MLX5_MODI_OUT_DMAC_15_0};
1371                 }
1372                 break;
1373         case RTE_FLOW_FIELD_MAC_SRC:
1374                 if (mask) {
1375                         if (data->offset < 32) {
1376                                 info[idx] = (struct field_modify_info){4, 0,
1377                                                 MLX5_MODI_OUT_SMAC_47_16};
1378                                 mask[idx] = 0xffffffff;
1379                                 if (width < 32) {
1380                                         mask[idx] = mask[idx] << (32 - width);
1381                                         width = 0;
1382                                 } else {
1383                                         width -= 32;
1384                                 }
1385                                 if (!width)
1386                                         break;
1387                                 ++idx;
1388                         }
1389                         info[idx] = (struct field_modify_info){2, 4 * idx,
1390                                                 MLX5_MODI_OUT_SMAC_15_0};
1391                         mask[idx] = (width) ? 0x0000ffff : 0x0;
1392                         if (width < 16)
1393                                 mask[idx] = (mask[idx] << (16 - width)) &
1394                                                 0x0000ffff;
1395                 } else {
1396                         if (data->offset < 32)
1397                                 info[idx++] = (struct field_modify_info){4, 0,
1398                                                 MLX5_MODI_OUT_SMAC_47_16};
1399                         info[idx] = (struct field_modify_info){2, 0,
1400                                                 MLX5_MODI_OUT_SMAC_15_0};
1401                 }
1402                 break;
1403         case RTE_FLOW_FIELD_VLAN_TYPE:
1404                 /* not supported yet */
1405                 break;
1406         case RTE_FLOW_FIELD_VLAN_ID:
1407                 info[idx] = (struct field_modify_info){2, 0,
1408                                         MLX5_MODI_OUT_FIRST_VID};
1409                 if (mask) {
1410                         mask[idx] = 0x00000fff;
1411                         if (width < 12)
1412                                 mask[idx] = (mask[idx] << (12 - width)) &
1413                                                 0x00000fff;
1414                 }
1415                 break;
1416         case RTE_FLOW_FIELD_MAC_TYPE:
1417                 info[idx] = (struct field_modify_info){2, 0,
1418                                         MLX5_MODI_OUT_ETHERTYPE};
1419                 if (mask) {
1420                         mask[idx] = 0x0000ffff;
1421                         if (width < 16)
1422                                 mask[idx] = (mask[idx] << (16 - width)) &
1423                                                 0x0000ffff;
1424                 }
1425                 break;
1426         case RTE_FLOW_FIELD_IPV4_DSCP:
1427                 info[idx] = (struct field_modify_info){1, 0,
1428                                         MLX5_MODI_OUT_IP_DSCP};
1429                 if (mask) {
1430                         mask[idx] = 0x0000003f;
1431                         if (width < 6)
1432                                 mask[idx] = (mask[idx] << (6 - width)) &
1433                                                 0x0000003f;
1434                 }
1435                 break;
1436         case RTE_FLOW_FIELD_IPV4_TTL:
1437                 info[idx] = (struct field_modify_info){1, 0,
1438                                         MLX5_MODI_OUT_IPV4_TTL};
1439                 if (mask) {
1440                         mask[idx] = 0x000000ff;
1441                         if (width < 8)
1442                                 mask[idx] = (mask[idx] << (8 - width)) &
1443                                                 0x000000ff;
1444                 }
1445                 break;
1446         case RTE_FLOW_FIELD_IPV4_SRC:
1447                 info[idx] = (struct field_modify_info){4, 0,
1448                                         MLX5_MODI_OUT_SIPV4};
1449                 if (mask) {
1450                         mask[idx] = 0xffffffff;
1451                         if (width < 32)
1452                                 mask[idx] = mask[idx] << (32 - width);
1453                 }
1454                 break;
1455         case RTE_FLOW_FIELD_IPV4_DST:
1456                 info[idx] = (struct field_modify_info){4, 0,
1457                                         MLX5_MODI_OUT_DIPV4};
1458                 if (mask) {
1459                         mask[idx] = 0xffffffff;
1460                         if (width < 32)
1461                                 mask[idx] = mask[idx] << (32 - width);
1462                 }
1463                 break;
1464         case RTE_FLOW_FIELD_IPV6_DSCP:
1465                 info[idx] = (struct field_modify_info){1, 0,
1466                                         MLX5_MODI_OUT_IP_DSCP};
1467                 if (mask) {
1468                         mask[idx] = 0x0000003f;
1469                         if (width < 6)
1470                                 mask[idx] = (mask[idx] << (6 - width)) &
1471                                                 0x0000003f;
1472                 }
1473                 break;
1474         case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
1475                 info[idx] = (struct field_modify_info){1, 0,
1476                                         MLX5_MODI_OUT_IPV6_HOPLIMIT};
1477                 if (mask) {
1478                         mask[idx] = 0x000000ff;
1479                         if (width < 8)
1480                                 mask[idx] = (mask[idx] << (8 - width)) &
1481                                                 0x000000ff;
1482                 }
1483                 break;
1484         case RTE_FLOW_FIELD_IPV6_SRC:
1485                 if (mask) {
1486                         if (data->offset < 32) {
1487                                 info[idx] = (struct field_modify_info){4, 0,
1488                                                 MLX5_MODI_OUT_SIPV6_127_96};
1489                                 mask[idx] = 0xffffffff;
1490                                 if (width < 32) {
1491                                         mask[idx] = mask[idx] << (32 - width);
1492                                         width = 0;
1493                                 } else {
1494                                         width -= 32;
1495                                 }
1496                                 if (!width)
1497                                         break;
1498                                 ++idx;
1499                         }
1500                         if (data->offset < 64) {
1501                                 info[idx] = (struct field_modify_info){4,
1502                                                 4 * idx,
1503                                                 MLX5_MODI_OUT_SIPV6_95_64};
1504                                 mask[idx] = 0xffffffff;
1505                                 if (width < 32) {
1506                                         mask[idx] = mask[idx] << (32 - width);
1507                                         width = 0;
1508                                 } else {
1509                                         width -= 32;
1510                                 }
1511                                 if (!width)
1512                                         break;
1513                                 ++idx;
1514                         }
1515                         if (data->offset < 96) {
1516                                 info[idx] = (struct field_modify_info){4,
1517                                                 8 * idx,
1518                                                 MLX5_MODI_OUT_SIPV6_63_32};
1519                                 mask[idx] = 0xffffffff;
1520                                 if (width < 32) {
1521                                         mask[idx] = mask[idx] << (32 - width);
1522                                         width = 0;
1523                                 } else {
1524                                         width -= 32;
1525                                 }
1526                                 if (!width)
1527                                         break;
1528                                 ++idx;
1529                         }
1530                         info[idx] = (struct field_modify_info){4, 12 * idx,
1531                                                 MLX5_MODI_OUT_SIPV6_31_0};
1532                         mask[idx] = 0xffffffff;
1533                         if (width < 32)
1534                                 mask[idx] = mask[idx] << (32 - width);
1535                 } else {
1536                         if (data->offset < 32)
1537                                 info[idx++] = (struct field_modify_info){4, 0,
1538                                                 MLX5_MODI_OUT_SIPV6_127_96};
1539                         if (data->offset < 64)
1540                                 info[idx++] = (struct field_modify_info){4, 0,
1541                                                 MLX5_MODI_OUT_SIPV6_95_64};
1542                         if (data->offset < 96)
1543                                 info[idx++] = (struct field_modify_info){4, 0,
1544                                                 MLX5_MODI_OUT_SIPV6_63_32};
1545                         if (data->offset < 128)
1546                                 info[idx++] = (struct field_modify_info){4, 0,
1547                                                 MLX5_MODI_OUT_SIPV6_31_0};
1548                 }
1549                 break;
1550         case RTE_FLOW_FIELD_IPV6_DST:
1551                 if (mask) {
1552                         if (data->offset < 32) {
1553                                 info[idx] = (struct field_modify_info){4, 0,
1554                                                 MLX5_MODI_OUT_DIPV6_127_96};
1555                                 mask[idx] = 0xffffffff;
1556                                 if (width < 32) {
1557                                         mask[idx] = mask[idx] << (32 - width);
1558                                         width = 0;
1559                                 } else {
1560                                         width -= 32;
1561                                 }
1562                                 if (!width)
1563                                         break;
1564                                 ++idx;
1565                         }
1566                         if (data->offset < 64) {
1567                                 info[idx] = (struct field_modify_info){4,
1568                                                 4 * idx,
1569                                                 MLX5_MODI_OUT_DIPV6_95_64};
1570                                 mask[idx] = 0xffffffff;
1571                                 if (width < 32) {
1572                                         mask[idx] = mask[idx] << (32 - width);
1573                                         width = 0;
1574                                 } else {
1575                                         width -= 32;
1576                                 }
1577                                 if (!width)
1578                                         break;
1579                                 ++idx;
1580                         }
1581                         if (data->offset < 96) {
1582                                 info[idx] = (struct field_modify_info){4,
1583                                                 8 * idx,
1584                                                 MLX5_MODI_OUT_DIPV6_63_32};
1585                                 mask[idx] = 0xffffffff;
1586                                 if (width < 32) {
1587                                         mask[idx] = mask[idx] << (32 - width);
1588                                         width = 0;
1589                                 } else {
1590                                         width -= 32;
1591                                 }
1592                                 if (!width)
1593                                         break;
1594                                 ++idx;
1595                         }
1596                         info[idx] = (struct field_modify_info){4, 12 * idx,
1597                                                 MLX5_MODI_OUT_DIPV6_31_0};
1598                         mask[idx] = 0xffffffff;
1599                         if (width < 32)
1600                                 mask[idx] = mask[idx] << (32 - width);
1601                 } else {
1602                         if (data->offset < 32)
1603                                 info[idx++] = (struct field_modify_info){4, 0,
1604                                                 MLX5_MODI_OUT_DIPV6_127_96};
1605                         if (data->offset < 64)
1606                                 info[idx++] = (struct field_modify_info){4, 0,
1607                                                 MLX5_MODI_OUT_DIPV6_95_64};
1608                         if (data->offset < 96)
1609                                 info[idx++] = (struct field_modify_info){4, 0,
1610                                                 MLX5_MODI_OUT_DIPV6_63_32};
1611                         if (data->offset < 128)
1612                                 info[idx++] = (struct field_modify_info){4, 0,
1613                                                 MLX5_MODI_OUT_DIPV6_31_0};
1614                 }
1615                 break;
1616         case RTE_FLOW_FIELD_TCP_PORT_SRC:
1617                 info[idx] = (struct field_modify_info){2, 0,
1618                                         MLX5_MODI_OUT_TCP_SPORT};
1619                 if (mask) {
1620                         mask[idx] = 0x0000ffff;
1621                         if (width < 16)
1622                                 mask[idx] = (mask[idx] << (16 - width)) &
1623                                                 0x0000ffff;
1624                 }
1625                 break;
1626         case RTE_FLOW_FIELD_TCP_PORT_DST:
1627                 info[idx] = (struct field_modify_info){2, 0,
1628                                         MLX5_MODI_OUT_TCP_DPORT};
1629                 if (mask) {
1630                         mask[idx] = 0x0000ffff;
1631                         if (width < 16)
1632                                 mask[idx] = (mask[idx] << (16 - width)) &
1633                                                 0x0000ffff;
1634                 }
1635                 break;
1636         case RTE_FLOW_FIELD_TCP_SEQ_NUM:
1637                 info[idx] = (struct field_modify_info){4, 0,
1638                                         MLX5_MODI_OUT_TCP_SEQ_NUM};
1639                 if (mask) {
1640                         mask[idx] = 0xffffffff;
1641                         if (width < 32)
1642                                 mask[idx] = (mask[idx] << (32 - width));
1643                 }
1644                 break;
1645         case RTE_FLOW_FIELD_TCP_ACK_NUM:
1646                 info[idx] = (struct field_modify_info){4, 0,
1647                                         MLX5_MODI_OUT_TCP_ACK_NUM};
1648                 if (mask) {
1649                         mask[idx] = 0xffffffff;
1650                         if (width < 32)
1651                                 mask[idx] = (mask[idx] << (32 - width));
1652                 }
1653                 break;
1654         case RTE_FLOW_FIELD_TCP_FLAGS:
1655                 info[idx] = (struct field_modify_info){1, 0,
1656                                         MLX5_MODI_OUT_TCP_FLAGS};
1657                 if (mask) {
1658                         mask[idx] = 0x0000003f;
1659                         if (width < 6)
1660                                 mask[idx] = (mask[idx] << (6 - width)) &
1661                                                 0x0000003f;
1662                 }
1663                 break;
1664         case RTE_FLOW_FIELD_UDP_PORT_SRC:
1665                 info[idx] = (struct field_modify_info){2, 0,
1666                                         MLX5_MODI_OUT_UDP_SPORT};
1667                 if (mask) {
1668                         mask[idx] = 0x0000ffff;
1669                         if (width < 16)
1670                                 mask[idx] = (mask[idx] << (16 - width)) &
1671                                                 0x0000ffff;
1672                 }
1673                 break;
1674         case RTE_FLOW_FIELD_UDP_PORT_DST:
1675                 info[idx] = (struct field_modify_info){2, 0,
1676                                         MLX5_MODI_OUT_UDP_DPORT};
1677                 if (mask) {
1678                         mask[idx] = 0x0000ffff;
1679                         if (width < 16)
1680                                 mask[idx] = (mask[idx] << (16 - width)) &
1681                                                 0x0000ffff;
1682                 }
1683                 break;
1684         case RTE_FLOW_FIELD_VXLAN_VNI:
1685                 /* not supported yet */
1686                 break;
1687         case RTE_FLOW_FIELD_GENEVE_VNI:
1688                 /* not supported yet*/
1689                 break;
1690         case RTE_FLOW_FIELD_GTP_TEID:
1691                 info[idx] = (struct field_modify_info){4, 0,
1692                                         MLX5_MODI_GTP_TEID};
1693                 if (mask) {
1694                         mask[idx] = 0xffffffff;
1695                         if (width < 32)
1696                                 mask[idx] = mask[idx] << (32 - width);
1697                 }
1698                 break;
1699         case RTE_FLOW_FIELD_TAG:
1700                 {
1701                         int reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG,
1702                                                    data->level, error);
1703                         if (reg < 0)
1704                                 return;
1705                         MLX5_ASSERT(reg != REG_NON);
1706                         MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1707                         info[idx] = (struct field_modify_info){4, 0,
1708                                                 reg_to_field[reg]};
1709                         if (mask) {
1710                                 mask[idx] = 0xffffffff;
1711                                 if (width < 32)
1712                                         mask[idx] = mask[idx] << (32 - width);
1713                         }
1714                 }
1715                 break;
1716         case RTE_FLOW_FIELD_MARK:
1717                 {
1718                         int reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK,
1719                                                        0, error);
1720                         if (reg < 0)
1721                                 return;
1722                         MLX5_ASSERT(reg != REG_NON);
1723                         MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1724                         info[idx] = (struct field_modify_info){4, 0,
1725                                                 reg_to_field[reg]};
1726                         if (mask) {
1727                                 mask[idx] = 0xffffffff;
1728                                 if (width < 32)
1729                                         mask[idx] = mask[idx] << (32 - width);
1730                         }
1731                 }
1732                 break;
1733         case RTE_FLOW_FIELD_META:
1734                 {
1735                         int reg = flow_dv_get_metadata_reg(dev, attr, error);
1736                         if (reg < 0)
1737                                 return;
1738                         MLX5_ASSERT(reg != REG_NON);
1739                         MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1740                         info[idx] = (struct field_modify_info){4, 0,
1741                                                 reg_to_field[reg]};
1742                         if (mask) {
1743                                 mask[idx] = 0xffffffff;
1744                                 if (width < 32)
1745                                         mask[idx] = mask[idx] << (32 - width);
1746                         }
1747                 }
1748                 break;
1749         case RTE_FLOW_FIELD_POINTER:
1750                 for (idx = 0; idx < MLX5_ACT_MAX_MOD_FIELDS; idx++) {
1751                         if (mask[idx]) {
1752                                 memcpy(&value[idx],
1753                                         (void *)(uintptr_t)data->value, 32);
1754                                 value[idx] = RTE_BE32(value[idx]);
1755                                 break;
1756                         }
1757                 }
1758                 break;
1759         case RTE_FLOW_FIELD_VALUE:
1760                 for (idx = 0; idx < MLX5_ACT_MAX_MOD_FIELDS; idx++) {
1761                         if (mask[idx]) {
1762                                 value[idx] = RTE_BE32((uint32_t)data->value);
1763                                 break;
1764                         }
1765                 }
1766                 break;
1767         default:
1768                 MLX5_ASSERT(false);
1769                 break;
1770         }
1771 }
1772
1773 /**
1774  * Convert modify_field action to DV specification.
1775  *
1776  * @param[in] dev
1777  *   Pointer to the rte_eth_dev structure.
1778  * @param[in,out] resource
1779  *   Pointer to the modify-header resource.
1780  * @param[in] action
1781  *   Pointer to action specification.
1782  * @param[in] attr
1783  *   Attributes of flow that includes this item.
1784  * @param[out] error
1785  *   Pointer to the error structure.
1786  *
1787  * @return
1788  *   0 on success, a negative errno value otherwise and rte_errno is set.
1789  */
1790 static int
1791 flow_dv_convert_action_modify_field
1792                         (struct rte_eth_dev *dev,
1793                          struct mlx5_flow_dv_modify_hdr_resource *resource,
1794                          const struct rte_flow_action *action,
1795                          const struct rte_flow_attr *attr,
1796                          struct rte_flow_error *error)
1797 {
1798         const struct rte_flow_action_modify_field *conf =
1799                 (const struct rte_flow_action_modify_field *)(action->conf);
1800         struct rte_flow_item item;
1801         struct field_modify_info field[MLX5_ACT_MAX_MOD_FIELDS] = {
1802                                                                 {0, 0, 0} };
1803         struct field_modify_info dcopy[MLX5_ACT_MAX_MOD_FIELDS] = {
1804                                                                 {0, 0, 0} };
1805         uint32_t mask[MLX5_ACT_MAX_MOD_FIELDS] = {0, 0, 0, 0, 0};
1806         uint32_t value[MLX5_ACT_MAX_MOD_FIELDS] = {0, 0, 0, 0, 0};
1807         uint32_t type;
1808
1809         if (conf->src.field == RTE_FLOW_FIELD_POINTER ||
1810                 conf->src.field == RTE_FLOW_FIELD_VALUE) {
1811                 type = MLX5_MODIFICATION_TYPE_SET;
1812                 /** For SET fill the destination field (field) first. */
1813                 mlx5_flow_field_id_to_modify_info(&conf->dst, field, mask,
1814                                           value, conf->width, dev, attr, error);
1815                 /** Then copy immediate value from source as per mask. */
1816                 mlx5_flow_field_id_to_modify_info(&conf->src, dcopy, mask,
1817                                           value, conf->width, dev, attr, error);
1818                 item.spec = &value;
1819         } else {
1820                 type = MLX5_MODIFICATION_TYPE_COPY;
1821                 /** For COPY fill the destination field (dcopy) without mask. */
1822                 mlx5_flow_field_id_to_modify_info(&conf->dst, dcopy, NULL,
1823                                           value, conf->width, dev, attr, error);
1824                 /** Then construct the source field (field) with mask. */
1825                 mlx5_flow_field_id_to_modify_info(&conf->src, field, mask,
1826                                           value, conf->width, dev, attr, error);
1827         }
1828         item.mask = &mask;
1829         return flow_dv_convert_modify_action(&item,
1830                         field, dcopy, resource, type, error);
1831 }
1832
1833 /**
1834  * Validate MARK item.
1835  *
1836  * @param[in] dev
1837  *   Pointer to the rte_eth_dev structure.
1838  * @param[in] item
1839  *   Item specification.
1840  * @param[in] attr
1841  *   Attributes of flow that includes this item.
1842  * @param[out] error
1843  *   Pointer to error structure.
1844  *
1845  * @return
1846  *   0 on success, a negative errno value otherwise and rte_errno is set.
1847  */
1848 static int
1849 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1850                            const struct rte_flow_item *item,
1851                            const struct rte_flow_attr *attr __rte_unused,
1852                            struct rte_flow_error *error)
1853 {
1854         struct mlx5_priv *priv = dev->data->dev_private;
1855         struct mlx5_dev_config *config = &priv->config;
1856         const struct rte_flow_item_mark *spec = item->spec;
1857         const struct rte_flow_item_mark *mask = item->mask;
1858         const struct rte_flow_item_mark nic_mask = {
1859                 .id = priv->sh->dv_mark_mask,
1860         };
1861         int ret;
1862
1863         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1864                 return rte_flow_error_set(error, ENOTSUP,
1865                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1866                                           "extended metadata feature"
1867                                           " isn't enabled");
1868         if (!mlx5_flow_ext_mreg_supported(dev))
1869                 return rte_flow_error_set(error, ENOTSUP,
1870                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1871                                           "extended metadata register"
1872                                           " isn't supported");
1873         if (!nic_mask.id)
1874                 return rte_flow_error_set(error, ENOTSUP,
1875                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1876                                           "extended metadata register"
1877                                           " isn't available");
1878         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1879         if (ret < 0)
1880                 return ret;
1881         if (!spec)
1882                 return rte_flow_error_set(error, EINVAL,
1883                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1884                                           item->spec,
1885                                           "data cannot be empty");
1886         if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1887                 return rte_flow_error_set(error, EINVAL,
1888                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1889                                           &spec->id,
1890                                           "mark id exceeds the limit");
1891         if (!mask)
1892                 mask = &nic_mask;
1893         if (!mask->id)
1894                 return rte_flow_error_set(error, EINVAL,
1895                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1896                                         "mask cannot be zero");
1897
1898         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1899                                         (const uint8_t *)&nic_mask,
1900                                         sizeof(struct rte_flow_item_mark),
1901                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1902         if (ret < 0)
1903                 return ret;
1904         return 0;
1905 }
1906
1907 /**
1908  * Validate META item.
1909  *
1910  * @param[in] dev
1911  *   Pointer to the rte_eth_dev structure.
1912  * @param[in] item
1913  *   Item specification.
1914  * @param[in] attr
1915  *   Attributes of flow that includes this item.
1916  * @param[out] error
1917  *   Pointer to error structure.
1918  *
1919  * @return
1920  *   0 on success, a negative errno value otherwise and rte_errno is set.
1921  */
1922 static int
1923 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1924                            const struct rte_flow_item *item,
1925                            const struct rte_flow_attr *attr,
1926                            struct rte_flow_error *error)
1927 {
1928         struct mlx5_priv *priv = dev->data->dev_private;
1929         struct mlx5_dev_config *config = &priv->config;
1930         const struct rte_flow_item_meta *spec = item->spec;
1931         const struct rte_flow_item_meta *mask = item->mask;
1932         struct rte_flow_item_meta nic_mask = {
1933                 .data = UINT32_MAX
1934         };
1935         int reg;
1936         int ret;
1937
1938         if (!spec)
1939                 return rte_flow_error_set(error, EINVAL,
1940                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1941                                           item->spec,
1942                                           "data cannot be empty");
1943         if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1944                 if (!mlx5_flow_ext_mreg_supported(dev))
1945                         return rte_flow_error_set(error, ENOTSUP,
1946                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1947                                           "extended metadata register"
1948                                           " isn't supported");
1949                 reg = flow_dv_get_metadata_reg(dev, attr, error);
1950                 if (reg < 0)
1951                         return reg;
1952                 if (reg == REG_NON)
1953                         return rte_flow_error_set(error, ENOTSUP,
1954                                         RTE_FLOW_ERROR_TYPE_ITEM, item,
1955                                         "unavalable extended metadata register");
1956                 if (reg == REG_B)
1957                         return rte_flow_error_set(error, ENOTSUP,
1958                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1959                                           "match on reg_b "
1960                                           "isn't supported");
1961                 if (reg != REG_A)
1962                         nic_mask.data = priv->sh->dv_meta_mask;
1963         } else if (attr->transfer) {
1964                 return rte_flow_error_set(error, ENOTSUP,
1965                                         RTE_FLOW_ERROR_TYPE_ITEM, item,
1966                                         "extended metadata feature "
1967                                         "should be enabled when "
1968                                         "meta item is requested "
1969                                         "with e-switch mode ");
1970         }
1971         if (!mask)
1972                 mask = &rte_flow_item_meta_mask;
1973         if (!mask->data)
1974                 return rte_flow_error_set(error, EINVAL,
1975                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1976                                         "mask cannot be zero");
1977
1978         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1979                                         (const uint8_t *)&nic_mask,
1980                                         sizeof(struct rte_flow_item_meta),
1981                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1982         return ret;
1983 }
1984
1985 /**
1986  * Validate TAG item.
1987  *
1988  * @param[in] dev
1989  *   Pointer to the rte_eth_dev structure.
1990  * @param[in] item
1991  *   Item specification.
1992  * @param[in] attr
1993  *   Attributes of flow that includes this item.
1994  * @param[out] error
1995  *   Pointer to error structure.
1996  *
1997  * @return
1998  *   0 on success, a negative errno value otherwise and rte_errno is set.
1999  */
2000 static int
2001 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
2002                           const struct rte_flow_item *item,
2003                           const struct rte_flow_attr *attr __rte_unused,
2004                           struct rte_flow_error *error)
2005 {
2006         const struct rte_flow_item_tag *spec = item->spec;
2007         const struct rte_flow_item_tag *mask = item->mask;
2008         const struct rte_flow_item_tag nic_mask = {
2009                 .data = RTE_BE32(UINT32_MAX),
2010                 .index = 0xff,
2011         };
2012         int ret;
2013
2014         if (!mlx5_flow_ext_mreg_supported(dev))
2015                 return rte_flow_error_set(error, ENOTSUP,
2016                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2017                                           "extensive metadata register"
2018                                           " isn't supported");
2019         if (!spec)
2020                 return rte_flow_error_set(error, EINVAL,
2021                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
2022                                           item->spec,
2023                                           "data cannot be empty");
2024         if (!mask)
2025                 mask = &rte_flow_item_tag_mask;
2026         if (!mask->data)
2027                 return rte_flow_error_set(error, EINVAL,
2028                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2029                                         "mask cannot be zero");
2030
2031         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2032                                         (const uint8_t *)&nic_mask,
2033                                         sizeof(struct rte_flow_item_tag),
2034                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2035         if (ret < 0)
2036                 return ret;
2037         if (mask->index != 0xff)
2038                 return rte_flow_error_set(error, EINVAL,
2039                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2040                                           "partial mask for tag index"
2041                                           " is not supported");
2042         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
2043         if (ret < 0)
2044                 return ret;
2045         MLX5_ASSERT(ret != REG_NON);
2046         return 0;
2047 }
2048
2049 /**
2050  * Validate vport item.
2051  *
2052  * @param[in] dev
2053  *   Pointer to the rte_eth_dev structure.
2054  * @param[in] item
2055  *   Item specification.
2056  * @param[in] attr
2057  *   Attributes of flow that includes this item.
2058  * @param[in] item_flags
2059  *   Bit-fields that holds the items detected until now.
2060  * @param[out] error
2061  *   Pointer to error structure.
2062  *
2063  * @return
2064  *   0 on success, a negative errno value otherwise and rte_errno is set.
2065  */
2066 static int
2067 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
2068                               const struct rte_flow_item *item,
2069                               const struct rte_flow_attr *attr,
2070                               uint64_t item_flags,
2071                               struct rte_flow_error *error)
2072 {
2073         const struct rte_flow_item_port_id *spec = item->spec;
2074         const struct rte_flow_item_port_id *mask = item->mask;
2075         const struct rte_flow_item_port_id switch_mask = {
2076                         .id = 0xffffffff,
2077         };
2078         struct mlx5_priv *esw_priv;
2079         struct mlx5_priv *dev_priv;
2080         int ret;
2081
2082         if (!attr->transfer)
2083                 return rte_flow_error_set(error, EINVAL,
2084                                           RTE_FLOW_ERROR_TYPE_ITEM,
2085                                           NULL,
2086                                           "match on port id is valid only"
2087                                           " when transfer flag is enabled");
2088         if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
2089                 return rte_flow_error_set(error, ENOTSUP,
2090                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2091                                           "multiple source ports are not"
2092                                           " supported");
2093         if (!mask)
2094                 mask = &switch_mask;
2095         if (mask->id != 0xffffffff)
2096                 return rte_flow_error_set(error, ENOTSUP,
2097                                            RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2098                                            mask,
2099                                            "no support for partial mask on"
2100                                            " \"id\" field");
2101         ret = mlx5_flow_item_acceptable
2102                                 (item, (const uint8_t *)mask,
2103                                  (const uint8_t *)&rte_flow_item_port_id_mask,
2104                                  sizeof(struct rte_flow_item_port_id),
2105                                  MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2106         if (ret)
2107                 return ret;
2108         if (!spec)
2109                 return 0;
2110         esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
2111         if (!esw_priv)
2112                 return rte_flow_error_set(error, rte_errno,
2113                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
2114                                           "failed to obtain E-Switch info for"
2115                                           " port");
2116         dev_priv = mlx5_dev_to_eswitch_info(dev);
2117         if (!dev_priv)
2118                 return rte_flow_error_set(error, rte_errno,
2119                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2120                                           NULL,
2121                                           "failed to obtain E-Switch info");
2122         if (esw_priv->domain_id != dev_priv->domain_id)
2123                 return rte_flow_error_set(error, EINVAL,
2124                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
2125                                           "cannot match on a port from a"
2126                                           " different E-Switch");
2127         return 0;
2128 }
2129
2130 /**
2131  * Validate VLAN item.
2132  *
2133  * @param[in] item
2134  *   Item specification.
2135  * @param[in] item_flags
2136  *   Bit-fields that holds the items detected until now.
2137  * @param[in] dev
2138  *   Ethernet device flow is being created on.
2139  * @param[out] error
2140  *   Pointer to error structure.
2141  *
2142  * @return
2143  *   0 on success, a negative errno value otherwise and rte_errno is set.
2144  */
2145 static int
2146 flow_dv_validate_item_vlan(const struct rte_flow_item *item,
2147                            uint64_t item_flags,
2148                            struct rte_eth_dev *dev,
2149                            struct rte_flow_error *error)
2150 {
2151         const struct rte_flow_item_vlan *mask = item->mask;
2152         const struct rte_flow_item_vlan nic_mask = {
2153                 .tci = RTE_BE16(UINT16_MAX),
2154                 .inner_type = RTE_BE16(UINT16_MAX),
2155                 .has_more_vlan = 1,
2156         };
2157         const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2158         int ret;
2159         const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 |
2160                                         MLX5_FLOW_LAYER_INNER_L4) :
2161                                        (MLX5_FLOW_LAYER_OUTER_L3 |
2162                                         MLX5_FLOW_LAYER_OUTER_L4);
2163         const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
2164                                         MLX5_FLOW_LAYER_OUTER_VLAN;
2165
2166         if (item_flags & vlanm)
2167                 return rte_flow_error_set(error, EINVAL,
2168                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2169                                           "multiple VLAN layers not supported");
2170         else if ((item_flags & l34m) != 0)
2171                 return rte_flow_error_set(error, EINVAL,
2172                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2173                                           "VLAN cannot follow L3/L4 layer");
2174         if (!mask)
2175                 mask = &rte_flow_item_vlan_mask;
2176         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2177                                         (const uint8_t *)&nic_mask,
2178                                         sizeof(struct rte_flow_item_vlan),
2179                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2180         if (ret)
2181                 return ret;
2182         if (!tunnel && mask->tci != RTE_BE16(0x0fff)) {
2183                 struct mlx5_priv *priv = dev->data->dev_private;
2184
2185                 if (priv->vmwa_context) {
2186                         /*
2187                          * Non-NULL context means we have a virtual machine
2188                          * and SR-IOV enabled, we have to create VLAN interface
2189                          * to make hypervisor to setup E-Switch vport
2190                          * context correctly. We avoid creating the multiple
2191                          * VLAN interfaces, so we cannot support VLAN tag mask.
2192                          */
2193                         return rte_flow_error_set(error, EINVAL,
2194                                                   RTE_FLOW_ERROR_TYPE_ITEM,
2195                                                   item,
2196                                                   "VLAN tag mask is not"
2197                                                   " supported in virtual"
2198                                                   " environment");
2199                 }
2200         }
2201         return 0;
2202 }
2203
2204 /*
2205  * GTP flags are contained in 1 byte of the format:
2206  * -------------------------------------------
2207  * | bit   | 0 - 2   | 3  | 4   | 5 | 6 | 7  |
2208  * |-----------------------------------------|
2209  * | value | Version | PT | Res | E | S | PN |
2210  * -------------------------------------------
2211  *
2212  * Matching is supported only for GTP flags E, S, PN.
2213  */
2214 #define MLX5_GTP_FLAGS_MASK     0x07
2215
2216 /**
2217  * Validate GTP item.
2218  *
2219  * @param[in] dev
2220  *   Pointer to the rte_eth_dev structure.
2221  * @param[in] item
2222  *   Item specification.
2223  * @param[in] item_flags
2224  *   Bit-fields that holds the items detected until now.
2225  * @param[out] error
2226  *   Pointer to error structure.
2227  *
2228  * @return
2229  *   0 on success, a negative errno value otherwise and rte_errno is set.
2230  */
2231 static int
2232 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
2233                           const struct rte_flow_item *item,
2234                           uint64_t item_flags,
2235                           struct rte_flow_error *error)
2236 {
2237         struct mlx5_priv *priv = dev->data->dev_private;
2238         const struct rte_flow_item_gtp *spec = item->spec;
2239         const struct rte_flow_item_gtp *mask = item->mask;
2240         const struct rte_flow_item_gtp nic_mask = {
2241                 .v_pt_rsv_flags = MLX5_GTP_FLAGS_MASK,
2242                 .msg_type = 0xff,
2243                 .teid = RTE_BE32(0xffffffff),
2244         };
2245
2246         if (!priv->config.hca_attr.tunnel_stateless_gtp)
2247                 return rte_flow_error_set(error, ENOTSUP,
2248                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2249                                           "GTP support is not enabled");
2250         if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
2251                 return rte_flow_error_set(error, ENOTSUP,
2252                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2253                                           "multiple tunnel layers not"
2254                                           " supported");
2255         if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
2256                 return rte_flow_error_set(error, EINVAL,
2257                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2258                                           "no outer UDP layer found");
2259         if (!mask)
2260                 mask = &rte_flow_item_gtp_mask;
2261         if (spec && spec->v_pt_rsv_flags & ~MLX5_GTP_FLAGS_MASK)
2262                 return rte_flow_error_set(error, ENOTSUP,
2263                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2264                                           "Match is supported for GTP"
2265                                           " flags only");
2266         return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2267                                          (const uint8_t *)&nic_mask,
2268                                          sizeof(struct rte_flow_item_gtp),
2269                                          MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2270 }
2271
2272 /**
2273  * Validate GTP PSC item.
2274  *
2275  * @param[in] item
2276  *   Item specification.
2277  * @param[in] last_item
2278  *   Previous validated item in the pattern items.
2279  * @param[in] gtp_item
2280  *   Previous GTP item specification.
2281  * @param[in] attr
2282  *   Pointer to flow attributes.
2283  * @param[out] error
2284  *   Pointer to error structure.
2285  *
2286  * @return
2287  *   0 on success, a negative errno value otherwise and rte_errno is set.
2288  */
2289 static int
2290 flow_dv_validate_item_gtp_psc(const struct rte_flow_item *item,
2291                               uint64_t last_item,
2292                               const struct rte_flow_item *gtp_item,
2293                               const struct rte_flow_attr *attr,
2294                               struct rte_flow_error *error)
2295 {
2296         const struct rte_flow_item_gtp *gtp_spec;
2297         const struct rte_flow_item_gtp *gtp_mask;
2298         const struct rte_flow_item_gtp_psc *spec;
2299         const struct rte_flow_item_gtp_psc *mask;
2300         const struct rte_flow_item_gtp_psc nic_mask = {
2301                 .pdu_type = 0xFF,
2302                 .qfi = 0xFF,
2303         };
2304
2305         if (!gtp_item || !(last_item & MLX5_FLOW_LAYER_GTP))
2306                 return rte_flow_error_set
2307                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2308                          "GTP PSC item must be preceded with GTP item");
2309         gtp_spec = gtp_item->spec;
2310         gtp_mask = gtp_item->mask ? gtp_item->mask : &rte_flow_item_gtp_mask;
2311         /* GTP spec and E flag is requested to match zero. */
2312         if (gtp_spec &&
2313                 (gtp_mask->v_pt_rsv_flags &
2314                 ~gtp_spec->v_pt_rsv_flags & MLX5_GTP_EXT_HEADER_FLAG))
2315                 return rte_flow_error_set
2316                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2317                          "GTP E flag must be 1 to match GTP PSC");
2318         /* Check the flow is not created in group zero. */
2319         if (!attr->transfer && !attr->group)
2320                 return rte_flow_error_set
2321                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2322                          "GTP PSC is not supported for group 0");
2323         /* GTP spec is here and E flag is requested to match zero. */
2324         if (!item->spec)
2325                 return 0;
2326         spec = item->spec;
2327         mask = item->mask ? item->mask : &rte_flow_item_gtp_psc_mask;
2328         if (spec->pdu_type > MLX5_GTP_EXT_MAX_PDU_TYPE)
2329                 return rte_flow_error_set
2330                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2331                          "PDU type should be smaller than 16");
2332         return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2333                                          (const uint8_t *)&nic_mask,
2334                                          sizeof(struct rte_flow_item_gtp_psc),
2335                                          MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2336 }
2337
2338 /**
2339  * Validate IPV4 item.
2340  * Use existing validation function mlx5_flow_validate_item_ipv4(), and
2341  * add specific validation of fragment_offset field,
2342  *
2343  * @param[in] item
2344  *   Item specification.
2345  * @param[in] item_flags
2346  *   Bit-fields that holds the items detected until now.
2347  * @param[out] error
2348  *   Pointer to error structure.
2349  *
2350  * @return
2351  *   0 on success, a negative errno value otherwise and rte_errno is set.
2352  */
2353 static int
2354 flow_dv_validate_item_ipv4(const struct rte_flow_item *item,
2355                            uint64_t item_flags,
2356                            uint64_t last_item,
2357                            uint16_t ether_type,
2358                            struct rte_flow_error *error)
2359 {
2360         int ret;
2361         const struct rte_flow_item_ipv4 *spec = item->spec;
2362         const struct rte_flow_item_ipv4 *last = item->last;
2363         const struct rte_flow_item_ipv4 *mask = item->mask;
2364         rte_be16_t fragment_offset_spec = 0;
2365         rte_be16_t fragment_offset_last = 0;
2366         const struct rte_flow_item_ipv4 nic_ipv4_mask = {
2367                 .hdr = {
2368                         .src_addr = RTE_BE32(0xffffffff),
2369                         .dst_addr = RTE_BE32(0xffffffff),
2370                         .type_of_service = 0xff,
2371                         .fragment_offset = RTE_BE16(0xffff),
2372                         .next_proto_id = 0xff,
2373                         .time_to_live = 0xff,
2374                 },
2375         };
2376
2377         ret = mlx5_flow_validate_item_ipv4(item, item_flags, last_item,
2378                                            ether_type, &nic_ipv4_mask,
2379                                            MLX5_ITEM_RANGE_ACCEPTED, error);
2380         if (ret < 0)
2381                 return ret;
2382         if (spec && mask)
2383                 fragment_offset_spec = spec->hdr.fragment_offset &
2384                                        mask->hdr.fragment_offset;
2385         if (!fragment_offset_spec)
2386                 return 0;
2387         /*
2388          * spec and mask are valid, enforce using full mask to make sure the
2389          * complete value is used correctly.
2390          */
2391         if ((mask->hdr.fragment_offset & RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2392                         != RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2393                 return rte_flow_error_set(error, EINVAL,
2394                                           RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2395                                           item, "must use full mask for"
2396                                           " fragment_offset");
2397         /*
2398          * Match on fragment_offset 0x2000 means MF is 1 and frag-offset is 0,
2399          * indicating this is 1st fragment of fragmented packet.
2400          * This is not yet supported in MLX5, return appropriate error message.
2401          */
2402         if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG))
2403                 return rte_flow_error_set(error, ENOTSUP,
2404                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2405                                           "match on first fragment not "
2406                                           "supported");
2407         if (fragment_offset_spec && !last)
2408                 return rte_flow_error_set(error, ENOTSUP,
2409                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2410                                           "specified value not supported");
2411         /* spec and last are valid, validate the specified range. */
2412         fragment_offset_last = last->hdr.fragment_offset &
2413                                mask->hdr.fragment_offset;
2414         /*
2415          * Match on fragment_offset spec 0x2001 and last 0x3fff
2416          * means MF is 1 and frag-offset is > 0.
2417          * This packet is fragment 2nd and onward, excluding last.
2418          * This is not yet supported in MLX5, return appropriate
2419          * error message.
2420          */
2421         if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG + 1) &&
2422             fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2423                 return rte_flow_error_set(error, ENOTSUP,
2424                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2425                                           last, "match on following "
2426                                           "fragments not supported");
2427         /*
2428          * Match on fragment_offset spec 0x0001 and last 0x1fff
2429          * means MF is 0 and frag-offset is > 0.
2430          * This packet is last fragment of fragmented packet.
2431          * This is not yet supported in MLX5, return appropriate
2432          * error message.
2433          */
2434         if (fragment_offset_spec == RTE_BE16(1) &&
2435             fragment_offset_last == RTE_BE16(RTE_IPV4_HDR_OFFSET_MASK))
2436                 return rte_flow_error_set(error, ENOTSUP,
2437                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2438                                           last, "match on last "
2439                                           "fragment not supported");
2440         /*
2441          * Match on fragment_offset spec 0x0001 and last 0x3fff
2442          * means MF and/or frag-offset is not 0.
2443          * This is a fragmented packet.
2444          * Other range values are invalid and rejected.
2445          */
2446         if (!(fragment_offset_spec == RTE_BE16(1) &&
2447               fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK)))
2448                 return rte_flow_error_set(error, ENOTSUP,
2449                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2450                                           "specified range not supported");
2451         return 0;
2452 }
2453
2454 /**
2455  * Validate IPV6 fragment extension item.
2456  *
2457  * @param[in] item
2458  *   Item specification.
2459  * @param[in] item_flags
2460  *   Bit-fields that holds the items detected until now.
2461  * @param[out] error
2462  *   Pointer to error structure.
2463  *
2464  * @return
2465  *   0 on success, a negative errno value otherwise and rte_errno is set.
2466  */
2467 static int
2468 flow_dv_validate_item_ipv6_frag_ext(const struct rte_flow_item *item,
2469                                     uint64_t item_flags,
2470                                     struct rte_flow_error *error)
2471 {
2472         const struct rte_flow_item_ipv6_frag_ext *spec = item->spec;
2473         const struct rte_flow_item_ipv6_frag_ext *last = item->last;
2474         const struct rte_flow_item_ipv6_frag_ext *mask = item->mask;
2475         rte_be16_t frag_data_spec = 0;
2476         rte_be16_t frag_data_last = 0;
2477         const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2478         const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 :
2479                                       MLX5_FLOW_LAYER_OUTER_L4;
2480         int ret = 0;
2481         struct rte_flow_item_ipv6_frag_ext nic_mask = {
2482                 .hdr = {
2483                         .next_header = 0xff,
2484                         .frag_data = RTE_BE16(0xffff),
2485                 },
2486         };
2487
2488         if (item_flags & l4m)
2489                 return rte_flow_error_set(error, EINVAL,
2490                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2491                                           "ipv6 fragment extension item cannot "
2492                                           "follow L4 item.");
2493         if ((tunnel && !(item_flags & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
2494             (!tunnel && !(item_flags & MLX5_FLOW_LAYER_OUTER_L3_IPV6)))
2495                 return rte_flow_error_set(error, EINVAL,
2496                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2497                                           "ipv6 fragment extension item must "
2498                                           "follow ipv6 item");
2499         if (spec && mask)
2500                 frag_data_spec = spec->hdr.frag_data & mask->hdr.frag_data;
2501         if (!frag_data_spec)
2502                 return 0;
2503         /*
2504          * spec and mask are valid, enforce using full mask to make sure the
2505          * complete value is used correctly.
2506          */
2507         if ((mask->hdr.frag_data & RTE_BE16(RTE_IPV6_FRAG_USED_MASK)) !=
2508                                 RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2509                 return rte_flow_error_set(error, EINVAL,
2510                                           RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2511                                           item, "must use full mask for"
2512                                           " frag_data");
2513         /*
2514          * Match on frag_data 0x00001 means M is 1 and frag-offset is 0.
2515          * This is 1st fragment of fragmented packet.
2516          */
2517         if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_MF_MASK))
2518                 return rte_flow_error_set(error, ENOTSUP,
2519                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2520                                           "match on first fragment not "
2521                                           "supported");
2522         if (frag_data_spec && !last)
2523                 return rte_flow_error_set(error, EINVAL,
2524                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2525                                           "specified value not supported");
2526         ret = mlx5_flow_item_acceptable
2527                                 (item, (const uint8_t *)mask,
2528                                  (const uint8_t *)&nic_mask,
2529                                  sizeof(struct rte_flow_item_ipv6_frag_ext),
2530                                  MLX5_ITEM_RANGE_ACCEPTED, error);
2531         if (ret)
2532                 return ret;
2533         /* spec and last are valid, validate the specified range. */
2534         frag_data_last = last->hdr.frag_data & mask->hdr.frag_data;
2535         /*
2536          * Match on frag_data spec 0x0009 and last 0xfff9
2537          * means M is 1 and frag-offset is > 0.
2538          * This packet is fragment 2nd and onward, excluding last.
2539          * This is not yet supported in MLX5, return appropriate
2540          * error message.
2541          */
2542         if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN |
2543                                        RTE_IPV6_EHDR_MF_MASK) &&
2544             frag_data_last == RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2545                 return rte_flow_error_set(error, ENOTSUP,
2546                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2547                                           last, "match on following "
2548                                           "fragments not supported");
2549         /*
2550          * Match on frag_data spec 0x0008 and last 0xfff8
2551          * means M is 0 and frag-offset is > 0.
2552          * This packet is last fragment of fragmented packet.
2553          * This is not yet supported in MLX5, return appropriate
2554          * error message.
2555          */
2556         if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN) &&
2557             frag_data_last == RTE_BE16(RTE_IPV6_EHDR_FO_MASK))
2558                 return rte_flow_error_set(error, ENOTSUP,
2559                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2560                                           last, "match on last "
2561                                           "fragment not supported");
2562         /* Other range values are invalid and rejected. */
2563         return rte_flow_error_set(error, EINVAL,
2564                                   RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2565                                   "specified range not supported");
2566 }
2567
2568 /**
2569  * Validate the pop VLAN action.
2570  *
2571  * @param[in] dev
2572  *   Pointer to the rte_eth_dev structure.
2573  * @param[in] action_flags
2574  *   Holds the actions detected until now.
2575  * @param[in] action
2576  *   Pointer to the pop vlan action.
2577  * @param[in] item_flags
2578  *   The items found in this flow rule.
2579  * @param[in] attr
2580  *   Pointer to flow attributes.
2581  * @param[out] error
2582  *   Pointer to error structure.
2583  *
2584  * @return
2585  *   0 on success, a negative errno value otherwise and rte_errno is set.
2586  */
2587 static int
2588 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
2589                                  uint64_t action_flags,
2590                                  const struct rte_flow_action *action,
2591                                  uint64_t item_flags,
2592                                  const struct rte_flow_attr *attr,
2593                                  struct rte_flow_error *error)
2594 {
2595         const struct mlx5_priv *priv = dev->data->dev_private;
2596
2597         (void)action;
2598         (void)attr;
2599         if (!priv->sh->pop_vlan_action)
2600                 return rte_flow_error_set(error, ENOTSUP,
2601                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2602                                           NULL,
2603                                           "pop vlan action is not supported");
2604         if (attr->egress)
2605                 return rte_flow_error_set(error, ENOTSUP,
2606                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2607                                           NULL,
2608                                           "pop vlan action not supported for "
2609                                           "egress");
2610         if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
2611                 return rte_flow_error_set(error, ENOTSUP,
2612                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2613                                           "no support for multiple VLAN "
2614                                           "actions");
2615         /* Pop VLAN with preceding Decap requires inner header with VLAN. */
2616         if ((action_flags & MLX5_FLOW_ACTION_DECAP) &&
2617             !(item_flags & MLX5_FLOW_LAYER_INNER_VLAN))
2618                 return rte_flow_error_set(error, ENOTSUP,
2619                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2620                                           NULL,
2621                                           "cannot pop vlan after decap without "
2622                                           "match on inner vlan in the flow");
2623         /* Pop VLAN without preceding Decap requires outer header with VLAN. */
2624         if (!(action_flags & MLX5_FLOW_ACTION_DECAP) &&
2625             !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2626                 return rte_flow_error_set(error, ENOTSUP,
2627                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2628                                           NULL,
2629                                           "cannot pop vlan without a "
2630                                           "match on (outer) vlan in the flow");
2631         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2632                 return rte_flow_error_set(error, EINVAL,
2633                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2634                                           "wrong action order, port_id should "
2635                                           "be after pop VLAN action");
2636         if (!attr->transfer && priv->representor)
2637                 return rte_flow_error_set(error, ENOTSUP,
2638                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2639                                           "pop vlan action for VF representor "
2640                                           "not supported on NIC table");
2641         return 0;
2642 }
2643
2644 /**
2645  * Get VLAN default info from vlan match info.
2646  *
2647  * @param[in] items
2648  *   the list of item specifications.
2649  * @param[out] vlan
2650  *   pointer VLAN info to fill to.
2651  *
2652  * @return
2653  *   0 on success, a negative errno value otherwise and rte_errno is set.
2654  */
2655 static void
2656 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
2657                                   struct rte_vlan_hdr *vlan)
2658 {
2659         const struct rte_flow_item_vlan nic_mask = {
2660                 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
2661                                 MLX5DV_FLOW_VLAN_VID_MASK),
2662                 .inner_type = RTE_BE16(0xffff),
2663         };
2664
2665         if (items == NULL)
2666                 return;
2667         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2668                 int type = items->type;
2669
2670                 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
2671                     type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
2672                         break;
2673         }
2674         if (items->type != RTE_FLOW_ITEM_TYPE_END) {
2675                 const struct rte_flow_item_vlan *vlan_m = items->mask;
2676                 const struct rte_flow_item_vlan *vlan_v = items->spec;
2677
2678                 /* If VLAN item in pattern doesn't contain data, return here. */
2679                 if (!vlan_v)
2680                         return;
2681                 if (!vlan_m)
2682                         vlan_m = &nic_mask;
2683                 /* Only full match values are accepted */
2684                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
2685                      MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
2686                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
2687                         vlan->vlan_tci |=
2688                                 rte_be_to_cpu_16(vlan_v->tci &
2689                                                  MLX5DV_FLOW_VLAN_PCP_MASK_BE);
2690                 }
2691                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
2692                      MLX5DV_FLOW_VLAN_VID_MASK_BE) {
2693                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
2694                         vlan->vlan_tci |=
2695                                 rte_be_to_cpu_16(vlan_v->tci &
2696                                                  MLX5DV_FLOW_VLAN_VID_MASK_BE);
2697                 }
2698                 if (vlan_m->inner_type == nic_mask.inner_type)
2699                         vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
2700                                                            vlan_m->inner_type);
2701         }
2702 }
2703
2704 /**
2705  * Validate the push VLAN action.
2706  *
2707  * @param[in] dev
2708  *   Pointer to the rte_eth_dev structure.
2709  * @param[in] action_flags
2710  *   Holds the actions detected until now.
2711  * @param[in] item_flags
2712  *   The items found in this flow rule.
2713  * @param[in] action
2714  *   Pointer to the action structure.
2715  * @param[in] attr
2716  *   Pointer to flow attributes
2717  * @param[out] error
2718  *   Pointer to error structure.
2719  *
2720  * @return
2721  *   0 on success, a negative errno value otherwise and rte_errno is set.
2722  */
2723 static int
2724 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
2725                                   uint64_t action_flags,
2726                                   const struct rte_flow_item_vlan *vlan_m,
2727                                   const struct rte_flow_action *action,
2728                                   const struct rte_flow_attr *attr,
2729                                   struct rte_flow_error *error)
2730 {
2731         const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
2732         const struct mlx5_priv *priv = dev->data->dev_private;
2733
2734         if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
2735             push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
2736                 return rte_flow_error_set(error, EINVAL,
2737                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2738                                           "invalid vlan ethertype");
2739         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2740                 return rte_flow_error_set(error, EINVAL,
2741                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2742                                           "wrong action order, port_id should "
2743                                           "be after push VLAN");
2744         if (!attr->transfer && priv->representor)
2745                 return rte_flow_error_set(error, ENOTSUP,
2746                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2747                                           "push vlan action for VF representor "
2748                                           "not supported on NIC table");
2749         if (vlan_m &&
2750             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
2751             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
2752                 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
2753             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
2754             !(mlx5_flow_find_action
2755                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
2756                 return rte_flow_error_set(error, EINVAL,
2757                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2758                                           "not full match mask on VLAN PCP and "
2759                                           "there is no of_set_vlan_pcp action, "
2760                                           "push VLAN action cannot figure out "
2761                                           "PCP value");
2762         if (vlan_m &&
2763             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
2764             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
2765                 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
2766             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
2767             !(mlx5_flow_find_action
2768                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
2769                 return rte_flow_error_set(error, EINVAL,
2770                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2771                                           "not full match mask on VLAN VID and "
2772                                           "there is no of_set_vlan_vid action, "
2773                                           "push VLAN action cannot figure out "
2774                                           "VID value");
2775         (void)attr;
2776         return 0;
2777 }
2778
2779 /**
2780  * Validate the set VLAN PCP.
2781  *
2782  * @param[in] action_flags
2783  *   Holds the actions detected until now.
2784  * @param[in] actions
2785  *   Pointer to the list of actions remaining in the flow rule.
2786  * @param[out] error
2787  *   Pointer to error structure.
2788  *
2789  * @return
2790  *   0 on success, a negative errno value otherwise and rte_errno is set.
2791  */
2792 static int
2793 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
2794                                      const struct rte_flow_action actions[],
2795                                      struct rte_flow_error *error)
2796 {
2797         const struct rte_flow_action *action = actions;
2798         const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
2799
2800         if (conf->vlan_pcp > 7)
2801                 return rte_flow_error_set(error, EINVAL,
2802                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2803                                           "VLAN PCP value is too big");
2804         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
2805                 return rte_flow_error_set(error, ENOTSUP,
2806                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2807                                           "set VLAN PCP action must follow "
2808                                           "the push VLAN action");
2809         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
2810                 return rte_flow_error_set(error, ENOTSUP,
2811                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2812                                           "Multiple VLAN PCP modification are "
2813                                           "not supported");
2814         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2815                 return rte_flow_error_set(error, EINVAL,
2816                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2817                                           "wrong action order, port_id should "
2818                                           "be after set VLAN PCP");
2819         return 0;
2820 }
2821
2822 /**
2823  * Validate the set VLAN VID.
2824  *
2825  * @param[in] item_flags
2826  *   Holds the items detected in this rule.
2827  * @param[in] action_flags
2828  *   Holds the actions detected until now.
2829  * @param[in] actions
2830  *   Pointer to the list of actions remaining in the flow rule.
2831  * @param[out] error
2832  *   Pointer to error structure.
2833  *
2834  * @return
2835  *   0 on success, a negative errno value otherwise and rte_errno is set.
2836  */
2837 static int
2838 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
2839                                      uint64_t action_flags,
2840                                      const struct rte_flow_action actions[],
2841                                      struct rte_flow_error *error)
2842 {
2843         const struct rte_flow_action *action = actions;
2844         const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
2845
2846         if (rte_be_to_cpu_16(conf->vlan_vid) > 0xFFE)
2847                 return rte_flow_error_set(error, EINVAL,
2848                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2849                                           "VLAN VID value is too big");
2850         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
2851             !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2852                 return rte_flow_error_set(error, ENOTSUP,
2853                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2854                                           "set VLAN VID action must follow push"
2855                                           " VLAN action or match on VLAN item");
2856         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
2857                 return rte_flow_error_set(error, ENOTSUP,
2858                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2859                                           "Multiple VLAN VID modifications are "
2860                                           "not supported");
2861         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2862                 return rte_flow_error_set(error, EINVAL,
2863                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2864                                           "wrong action order, port_id should "
2865                                           "be after set VLAN VID");
2866         return 0;
2867 }
2868
2869 /*
2870  * Validate the FLAG action.
2871  *
2872  * @param[in] dev
2873  *   Pointer to the rte_eth_dev structure.
2874  * @param[in] action_flags
2875  *   Holds the actions detected until now.
2876  * @param[in] attr
2877  *   Pointer to flow attributes
2878  * @param[out] error
2879  *   Pointer to error structure.
2880  *
2881  * @return
2882  *   0 on success, a negative errno value otherwise and rte_errno is set.
2883  */
2884 static int
2885 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
2886                              uint64_t action_flags,
2887                              const struct rte_flow_attr *attr,
2888                              struct rte_flow_error *error)
2889 {
2890         struct mlx5_priv *priv = dev->data->dev_private;
2891         struct mlx5_dev_config *config = &priv->config;
2892         int ret;
2893
2894         /* Fall back if no extended metadata register support. */
2895         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2896                 return mlx5_flow_validate_action_flag(action_flags, attr,
2897                                                       error);
2898         /* Extensive metadata mode requires registers. */
2899         if (!mlx5_flow_ext_mreg_supported(dev))
2900                 return rte_flow_error_set(error, ENOTSUP,
2901                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2902                                           "no metadata registers "
2903                                           "to support flag action");
2904         if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
2905                 return rte_flow_error_set(error, ENOTSUP,
2906                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2907                                           "extended metadata register"
2908                                           " isn't available");
2909         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2910         if (ret < 0)
2911                 return ret;
2912         MLX5_ASSERT(ret > 0);
2913         if (action_flags & MLX5_FLOW_ACTION_MARK)
2914                 return rte_flow_error_set(error, EINVAL,
2915                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2916                                           "can't mark and flag in same flow");
2917         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2918                 return rte_flow_error_set(error, EINVAL,
2919                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2920                                           "can't have 2 flag"
2921                                           " actions in same flow");
2922         return 0;
2923 }
2924
2925 /**
2926  * Validate MARK action.
2927  *
2928  * @param[in] dev
2929  *   Pointer to the rte_eth_dev structure.
2930  * @param[in] action
2931  *   Pointer to action.
2932  * @param[in] action_flags
2933  *   Holds the actions detected until now.
2934  * @param[in] attr
2935  *   Pointer to flow attributes
2936  * @param[out] error
2937  *   Pointer to error structure.
2938  *
2939  * @return
2940  *   0 on success, a negative errno value otherwise and rte_errno is set.
2941  */
2942 static int
2943 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
2944                              const struct rte_flow_action *action,
2945                              uint64_t action_flags,
2946                              const struct rte_flow_attr *attr,
2947                              struct rte_flow_error *error)
2948 {
2949         struct mlx5_priv *priv = dev->data->dev_private;
2950         struct mlx5_dev_config *config = &priv->config;
2951         const struct rte_flow_action_mark *mark = action->conf;
2952         int ret;
2953
2954         if (is_tunnel_offload_active(dev))
2955                 return rte_flow_error_set(error, ENOTSUP,
2956                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2957                                           "no mark action "
2958                                           "if tunnel offload active");
2959         /* Fall back if no extended metadata register support. */
2960         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2961                 return mlx5_flow_validate_action_mark(action, action_flags,
2962                                                       attr, error);
2963         /* Extensive metadata mode requires registers. */
2964         if (!mlx5_flow_ext_mreg_supported(dev))
2965                 return rte_flow_error_set(error, ENOTSUP,
2966                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2967                                           "no metadata registers "
2968                                           "to support mark action");
2969         if (!priv->sh->dv_mark_mask)
2970                 return rte_flow_error_set(error, ENOTSUP,
2971                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2972                                           "extended metadata register"
2973                                           " isn't available");
2974         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2975         if (ret < 0)
2976                 return ret;
2977         MLX5_ASSERT(ret > 0);
2978         if (!mark)
2979                 return rte_flow_error_set(error, EINVAL,
2980                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2981                                           "configuration cannot be null");
2982         if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
2983                 return rte_flow_error_set(error, EINVAL,
2984                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2985                                           &mark->id,
2986                                           "mark id exceeds the limit");
2987         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2988                 return rte_flow_error_set(error, EINVAL,
2989                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2990                                           "can't flag and mark in same flow");
2991         if (action_flags & MLX5_FLOW_ACTION_MARK)
2992                 return rte_flow_error_set(error, EINVAL,
2993                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2994                                           "can't have 2 mark actions in same"
2995                                           " flow");
2996         return 0;
2997 }
2998
2999 /**
3000  * Validate SET_META action.
3001  *
3002  * @param[in] dev
3003  *   Pointer to the rte_eth_dev structure.
3004  * @param[in] action
3005  *   Pointer to the action structure.
3006  * @param[in] action_flags
3007  *   Holds the actions detected until now.
3008  * @param[in] attr
3009  *   Pointer to flow attributes
3010  * @param[out] error
3011  *   Pointer to error structure.
3012  *
3013  * @return
3014  *   0 on success, a negative errno value otherwise and rte_errno is set.
3015  */
3016 static int
3017 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
3018                                  const struct rte_flow_action *action,
3019                                  uint64_t action_flags __rte_unused,
3020                                  const struct rte_flow_attr *attr,
3021                                  struct rte_flow_error *error)
3022 {
3023         const struct rte_flow_action_set_meta *conf;
3024         uint32_t nic_mask = UINT32_MAX;
3025         int reg;
3026
3027         if (!mlx5_flow_ext_mreg_supported(dev))
3028                 return rte_flow_error_set(error, ENOTSUP,
3029                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3030                                           "extended metadata register"
3031                                           " isn't supported");
3032         reg = flow_dv_get_metadata_reg(dev, attr, error);
3033         if (reg < 0)
3034                 return reg;
3035         if (reg == REG_NON)
3036                 return rte_flow_error_set(error, ENOTSUP,
3037                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3038                                           "unavalable extended metadata register");
3039         if (reg != REG_A && reg != REG_B) {
3040                 struct mlx5_priv *priv = dev->data->dev_private;
3041
3042                 nic_mask = priv->sh->dv_meta_mask;
3043         }
3044         if (!(action->conf))
3045                 return rte_flow_error_set(error, EINVAL,
3046                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3047                                           "configuration cannot be null");
3048         conf = (const struct rte_flow_action_set_meta *)action->conf;
3049         if (!conf->mask)
3050                 return rte_flow_error_set(error, EINVAL,
3051                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3052                                           "zero mask doesn't have any effect");
3053         if (conf->mask & ~nic_mask)
3054                 return rte_flow_error_set(error, EINVAL,
3055                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3056                                           "meta data must be within reg C0");
3057         return 0;
3058 }
3059
3060 /**
3061  * Validate SET_TAG action.
3062  *
3063  * @param[in] dev
3064  *   Pointer to the rte_eth_dev structure.
3065  * @param[in] action
3066  *   Pointer to the action structure.
3067  * @param[in] action_flags
3068  *   Holds the actions detected until now.
3069  * @param[in] attr
3070  *   Pointer to flow attributes
3071  * @param[out] error
3072  *   Pointer to error structure.
3073  *
3074  * @return
3075  *   0 on success, a negative errno value otherwise and rte_errno is set.
3076  */
3077 static int
3078 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
3079                                 const struct rte_flow_action *action,
3080                                 uint64_t action_flags,
3081                                 const struct rte_flow_attr *attr,
3082                                 struct rte_flow_error *error)
3083 {
3084         const struct rte_flow_action_set_tag *conf;
3085         const uint64_t terminal_action_flags =
3086                 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
3087                 MLX5_FLOW_ACTION_RSS;
3088         int ret;
3089
3090         if (!mlx5_flow_ext_mreg_supported(dev))
3091                 return rte_flow_error_set(error, ENOTSUP,
3092                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3093                                           "extensive metadata register"
3094                                           " isn't supported");
3095         if (!(action->conf))
3096                 return rte_flow_error_set(error, EINVAL,
3097                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3098                                           "configuration cannot be null");
3099         conf = (const struct rte_flow_action_set_tag *)action->conf;
3100         if (!conf->mask)
3101                 return rte_flow_error_set(error, EINVAL,
3102                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3103                                           "zero mask doesn't have any effect");
3104         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
3105         if (ret < 0)
3106                 return ret;
3107         if (!attr->transfer && attr->ingress &&
3108             (action_flags & terminal_action_flags))
3109                 return rte_flow_error_set(error, EINVAL,
3110                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3111                                           "set_tag has no effect"
3112                                           " with terminal actions");
3113         return 0;
3114 }
3115
3116 /**
3117  * Validate count action.
3118  *
3119  * @param[in] dev
3120  *   Pointer to rte_eth_dev structure.
3121  * @param[in] action
3122  *   Pointer to the action structure.
3123  * @param[in] action_flags
3124  *   Holds the actions detected until now.
3125  * @param[out] error
3126  *   Pointer to error structure.
3127  *
3128  * @return
3129  *   0 on success, a negative errno value otherwise and rte_errno is set.
3130  */
3131 static int
3132 flow_dv_validate_action_count(struct rte_eth_dev *dev,
3133                               const struct rte_flow_action *action,
3134                               uint64_t action_flags,
3135                               struct rte_flow_error *error)
3136 {
3137         struct mlx5_priv *priv = dev->data->dev_private;
3138         const struct rte_flow_action_count *count;
3139
3140         if (!priv->config.devx)
3141                 goto notsup_err;
3142         if (action_flags & MLX5_FLOW_ACTION_COUNT)
3143                 return rte_flow_error_set(error, EINVAL,
3144                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3145                                           "duplicate count actions set");
3146         count = (const struct rte_flow_action_count *)action->conf;
3147         if (count && count->shared && (action_flags & MLX5_FLOW_ACTION_AGE) &&
3148             !priv->sh->flow_hit_aso_en)
3149                 return rte_flow_error_set(error, EINVAL,
3150                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3151                                           "old age and shared count combination is not supported");
3152 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
3153         return 0;
3154 #endif
3155 notsup_err:
3156         return rte_flow_error_set
3157                       (error, ENOTSUP,
3158                        RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3159                        NULL,
3160                        "count action not supported");
3161 }
3162
3163 /**
3164  * Validate the L2 encap action.
3165  *
3166  * @param[in] dev
3167  *   Pointer to the rte_eth_dev structure.
3168  * @param[in] action_flags
3169  *   Holds the actions detected until now.
3170  * @param[in] action
3171  *   Pointer to the action structure.
3172  * @param[in] attr
3173  *   Pointer to flow attributes.
3174  * @param[out] error
3175  *   Pointer to error structure.
3176  *
3177  * @return
3178  *   0 on success, a negative errno value otherwise and rte_errno is set.
3179  */
3180 static int
3181 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
3182                                  uint64_t action_flags,
3183                                  const struct rte_flow_action *action,
3184                                  const struct rte_flow_attr *attr,
3185                                  struct rte_flow_error *error)
3186 {
3187         const struct mlx5_priv *priv = dev->data->dev_private;
3188
3189         if (!(action->conf))
3190                 return rte_flow_error_set(error, EINVAL,
3191                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3192                                           "configuration cannot be null");
3193         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3194                 return rte_flow_error_set(error, EINVAL,
3195                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3196                                           "can only have a single encap action "
3197                                           "in a flow");
3198         if (!attr->transfer && priv->representor)
3199                 return rte_flow_error_set(error, ENOTSUP,
3200                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3201                                           "encap action for VF representor "
3202                                           "not supported on NIC table");
3203         return 0;
3204 }
3205
3206 /**
3207  * Validate a decap action.
3208  *
3209  * @param[in] dev
3210  *   Pointer to the rte_eth_dev structure.
3211  * @param[in] action_flags
3212  *   Holds the actions detected until now.
3213  * @param[in] action
3214  *   Pointer to the action structure.
3215  * @param[in] item_flags
3216  *   Holds the items detected.
3217  * @param[in] attr
3218  *   Pointer to flow attributes
3219  * @param[out] error
3220  *   Pointer to error structure.
3221  *
3222  * @return
3223  *   0 on success, a negative errno value otherwise and rte_errno is set.
3224  */
3225 static int
3226 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
3227                               uint64_t action_flags,
3228                               const struct rte_flow_action *action,
3229                               const uint64_t item_flags,
3230                               const struct rte_flow_attr *attr,
3231                               struct rte_flow_error *error)
3232 {
3233         const struct mlx5_priv *priv = dev->data->dev_private;
3234
3235         if (priv->config.hca_attr.scatter_fcs_w_decap_disable &&
3236             !priv->config.decap_en)
3237                 return rte_flow_error_set(error, ENOTSUP,
3238                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3239                                           "decap is not enabled");
3240         if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
3241                 return rte_flow_error_set(error, ENOTSUP,
3242                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3243                                           action_flags &
3244                                           MLX5_FLOW_ACTION_DECAP ? "can only "
3245                                           "have a single decap action" : "decap "
3246                                           "after encap is not supported");
3247         if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
3248                 return rte_flow_error_set(error, EINVAL,
3249                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3250                                           "can't have decap action after"
3251                                           " modify action");
3252         if (attr->egress)
3253                 return rte_flow_error_set(error, ENOTSUP,
3254                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
3255                                           NULL,
3256                                           "decap action not supported for "
3257                                           "egress");
3258         if (!attr->transfer && priv->representor)
3259                 return rte_flow_error_set(error, ENOTSUP,
3260                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3261                                           "decap action for VF representor "
3262                                           "not supported on NIC table");
3263         if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_DECAP &&
3264             !(item_flags & MLX5_FLOW_LAYER_VXLAN))
3265                 return rte_flow_error_set(error, ENOTSUP,
3266                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3267                                 "VXLAN item should be present for VXLAN decap");
3268         return 0;
3269 }
3270
3271 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
3272
3273 /**
3274  * Validate the raw encap and decap actions.
3275  *
3276  * @param[in] dev
3277  *   Pointer to the rte_eth_dev structure.
3278  * @param[in] decap
3279  *   Pointer to the decap action.
3280  * @param[in] encap
3281  *   Pointer to the encap action.
3282  * @param[in] attr
3283  *   Pointer to flow attributes
3284  * @param[in/out] action_flags
3285  *   Holds the actions detected until now.
3286  * @param[out] actions_n
3287  *   pointer to the number of actions counter.
3288  * @param[in] action
3289  *   Pointer to the action structure.
3290  * @param[in] item_flags
3291  *   Holds the items detected.
3292  * @param[out] error
3293  *   Pointer to error structure.
3294  *
3295  * @return
3296  *   0 on success, a negative errno value otherwise and rte_errno is set.
3297  */
3298 static int
3299 flow_dv_validate_action_raw_encap_decap
3300         (struct rte_eth_dev *dev,
3301          const struct rte_flow_action_raw_decap *decap,
3302          const struct rte_flow_action_raw_encap *encap,
3303          const struct rte_flow_attr *attr, uint64_t *action_flags,
3304          int *actions_n, const struct rte_flow_action *action,
3305          uint64_t item_flags, struct rte_flow_error *error)
3306 {
3307         const struct mlx5_priv *priv = dev->data->dev_private;
3308         int ret;
3309
3310         if (encap && (!encap->size || !encap->data))
3311                 return rte_flow_error_set(error, EINVAL,
3312                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3313                                           "raw encap data cannot be empty");
3314         if (decap && encap) {
3315                 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
3316                     encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
3317                         /* L3 encap. */
3318                         decap = NULL;
3319                 else if (encap->size <=
3320                            MLX5_ENCAPSULATION_DECISION_SIZE &&
3321                            decap->size >
3322                            MLX5_ENCAPSULATION_DECISION_SIZE)
3323                         /* L3 decap. */
3324                         encap = NULL;
3325                 else if (encap->size >
3326                            MLX5_ENCAPSULATION_DECISION_SIZE &&
3327                            decap->size >
3328                            MLX5_ENCAPSULATION_DECISION_SIZE)
3329                         /* 2 L2 actions: encap and decap. */
3330                         ;
3331                 else
3332                         return rte_flow_error_set(error,
3333                                 ENOTSUP,
3334                                 RTE_FLOW_ERROR_TYPE_ACTION,
3335                                 NULL, "unsupported too small "
3336                                 "raw decap and too small raw "
3337                                 "encap combination");
3338         }
3339         if (decap) {
3340                 ret = flow_dv_validate_action_decap(dev, *action_flags, action,
3341                                                     item_flags, attr, error);
3342                 if (ret < 0)
3343                         return ret;
3344                 *action_flags |= MLX5_FLOW_ACTION_DECAP;
3345                 ++(*actions_n);
3346         }
3347         if (encap) {
3348                 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
3349                         return rte_flow_error_set(error, ENOTSUP,
3350                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3351                                                   NULL,
3352                                                   "small raw encap size");
3353                 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
3354                         return rte_flow_error_set(error, EINVAL,
3355                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3356                                                   NULL,
3357                                                   "more than one encap action");
3358                 if (!attr->transfer && priv->representor)
3359                         return rte_flow_error_set
3360                                         (error, ENOTSUP,
3361                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3362                                          "encap action for VF representor "
3363                                          "not supported on NIC table");
3364                 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
3365                 ++(*actions_n);
3366         }
3367         return 0;
3368 }
3369
3370 /**
3371  * Match encap_decap resource.
3372  *
3373  * @param list
3374  *   Pointer to the hash list.
3375  * @param entry
3376  *   Pointer to exist resource entry object.
3377  * @param key
3378  *   Key of the new entry.
3379  * @param ctx_cb
3380  *   Pointer to new encap_decap resource.
3381  *
3382  * @return
3383  *   0 on matching, none-zero otherwise.
3384  */
3385 int
3386 flow_dv_encap_decap_match_cb(struct mlx5_hlist *list __rte_unused,
3387                              struct mlx5_hlist_entry *entry,
3388                              uint64_t key __rte_unused, void *cb_ctx)
3389 {
3390         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3391         struct mlx5_flow_dv_encap_decap_resource *resource = ctx->data;
3392         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
3393
3394         cache_resource = container_of(entry,
3395                                       struct mlx5_flow_dv_encap_decap_resource,
3396                                       entry);
3397         if (resource->reformat_type == cache_resource->reformat_type &&
3398             resource->ft_type == cache_resource->ft_type &&
3399             resource->flags == cache_resource->flags &&
3400             resource->size == cache_resource->size &&
3401             !memcmp((const void *)resource->buf,
3402                     (const void *)cache_resource->buf,
3403                     resource->size))
3404                 return 0;
3405         return -1;
3406 }
3407
3408 /**
3409  * Allocate encap_decap resource.
3410  *
3411  * @param list
3412  *   Pointer to the hash list.
3413  * @param entry
3414  *   Pointer to exist resource entry object.
3415  * @param ctx_cb
3416  *   Pointer to new encap_decap resource.
3417  *
3418  * @return
3419  *   0 on matching, none-zero otherwise.
3420  */
3421 struct mlx5_hlist_entry *
3422 flow_dv_encap_decap_create_cb(struct mlx5_hlist *list,
3423                               uint64_t key __rte_unused,
3424                               void *cb_ctx)
3425 {
3426         struct mlx5_dev_ctx_shared *sh = list->ctx;
3427         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3428         struct mlx5dv_dr_domain *domain;
3429         struct mlx5_flow_dv_encap_decap_resource *resource = ctx->data;
3430         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
3431         uint32_t idx;
3432         int ret;
3433
3434         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3435                 domain = sh->fdb_domain;
3436         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3437                 domain = sh->rx_domain;
3438         else
3439                 domain = sh->tx_domain;
3440         /* Register new encap/decap resource. */
3441         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
3442                                        &idx);
3443         if (!cache_resource) {
3444                 rte_flow_error_set(ctx->error, ENOMEM,
3445                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3446                                    "cannot allocate resource memory");
3447                 return NULL;
3448         }
3449         *cache_resource = *resource;
3450         cache_resource->idx = idx;
3451         ret = mlx5_flow_os_create_flow_action_packet_reformat
3452                                         (sh->ctx, domain, cache_resource,
3453                                          &cache_resource->action);
3454         if (ret) {
3455                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);
3456                 rte_flow_error_set(ctx->error, ENOMEM,
3457                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3458                                    NULL, "cannot create action");
3459                 return NULL;
3460         }
3461
3462         return &cache_resource->entry;
3463 }
3464
3465 /**
3466  * Find existing encap/decap resource or create and register a new one.
3467  *
3468  * @param[in, out] dev
3469  *   Pointer to rte_eth_dev structure.
3470  * @param[in, out] resource
3471  *   Pointer to encap/decap resource.
3472  * @parm[in, out] dev_flow
3473  *   Pointer to the dev_flow.
3474  * @param[out] error
3475  *   pointer to error structure.
3476  *
3477  * @return
3478  *   0 on success otherwise -errno and errno is set.
3479  */
3480 static int
3481 flow_dv_encap_decap_resource_register
3482                         (struct rte_eth_dev *dev,
3483                          struct mlx5_flow_dv_encap_decap_resource *resource,
3484                          struct mlx5_flow *dev_flow,
3485                          struct rte_flow_error *error)
3486 {
3487         struct mlx5_priv *priv = dev->data->dev_private;
3488         struct mlx5_dev_ctx_shared *sh = priv->sh;
3489         struct mlx5_hlist_entry *entry;
3490         union {
3491                 struct {
3492                         uint32_t ft_type:8;
3493                         uint32_t refmt_type:8;
3494                         /*
3495                          * Header reformat actions can be shared between
3496                          * non-root tables. One bit to indicate non-root
3497                          * table or not.
3498                          */
3499                         uint32_t is_root:1;
3500                         uint32_t reserve:15;
3501                 };
3502                 uint32_t v32;
3503         } encap_decap_key = {
3504                 {
3505                         .ft_type = resource->ft_type,
3506                         .refmt_type = resource->reformat_type,
3507                         .is_root = !!dev_flow->dv.group,
3508                         .reserve = 0,
3509                 }
3510         };
3511         struct mlx5_flow_cb_ctx ctx = {
3512                 .error = error,
3513                 .data = resource,
3514         };
3515         uint64_t key64;
3516
3517         resource->flags = dev_flow->dv.group ? 0 : 1;
3518         key64 =  __rte_raw_cksum(&encap_decap_key.v32,
3519                                  sizeof(encap_decap_key.v32), 0);
3520         if (resource->reformat_type !=
3521             MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2 &&
3522             resource->size)
3523                 key64 = __rte_raw_cksum(resource->buf, resource->size, key64);
3524         entry = mlx5_hlist_register(sh->encaps_decaps, key64, &ctx);
3525         if (!entry)
3526                 return -rte_errno;
3527         resource = container_of(entry, typeof(*resource), entry);
3528         dev_flow->dv.encap_decap = resource;
3529         dev_flow->handle->dvh.rix_encap_decap = resource->idx;
3530         return 0;
3531 }
3532
3533 /**
3534  * Find existing table jump resource or create and register a new one.
3535  *
3536  * @param[in, out] dev
3537  *   Pointer to rte_eth_dev structure.
3538  * @param[in, out] tbl
3539  *   Pointer to flow table resource.
3540  * @parm[in, out] dev_flow
3541  *   Pointer to the dev_flow.
3542  * @param[out] error
3543  *   pointer to error structure.
3544  *
3545  * @return
3546  *   0 on success otherwise -errno and errno is set.
3547  */
3548 static int
3549 flow_dv_jump_tbl_resource_register
3550                         (struct rte_eth_dev *dev __rte_unused,
3551                          struct mlx5_flow_tbl_resource *tbl,
3552                          struct mlx5_flow *dev_flow,
3553                          struct rte_flow_error *error __rte_unused)
3554 {
3555         struct mlx5_flow_tbl_data_entry *tbl_data =
3556                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
3557
3558         MLX5_ASSERT(tbl);
3559         MLX5_ASSERT(tbl_data->jump.action);
3560         dev_flow->handle->rix_jump = tbl_data->idx;
3561         dev_flow->dv.jump = &tbl_data->jump;
3562         return 0;
3563 }
3564
3565 int
3566 flow_dv_port_id_match_cb(struct mlx5_cache_list *list __rte_unused,
3567                          struct mlx5_cache_entry *entry, void *cb_ctx)
3568 {
3569         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3570         struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3571         struct mlx5_flow_dv_port_id_action_resource *res =
3572                         container_of(entry, typeof(*res), entry);
3573
3574         return ref->port_id != res->port_id;
3575 }
3576
3577 struct mlx5_cache_entry *
3578 flow_dv_port_id_create_cb(struct mlx5_cache_list *list,
3579                           struct mlx5_cache_entry *entry __rte_unused,
3580                           void *cb_ctx)
3581 {
3582         struct mlx5_dev_ctx_shared *sh = list->ctx;
3583         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3584         struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3585         struct mlx5_flow_dv_port_id_action_resource *cache;
3586         uint32_t idx;
3587         int ret;
3588
3589         /* Register new port id action resource. */
3590         cache = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID], &idx);
3591         if (!cache) {
3592                 rte_flow_error_set(ctx->error, ENOMEM,
3593                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3594                                    "cannot allocate port_id action cache memory");
3595                 return NULL;
3596         }
3597         *cache = *ref;
3598         ret = mlx5_flow_os_create_flow_action_dest_port(sh->fdb_domain,
3599                                                         ref->port_id,
3600                                                         &cache->action);
3601         if (ret) {
3602                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], idx);
3603                 rte_flow_error_set(ctx->error, ENOMEM,
3604                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3605                                    "cannot create action");
3606                 return NULL;
3607         }
3608         return &cache->entry;
3609 }
3610
3611 /**
3612  * Find existing table port ID resource or create and register a new one.
3613  *
3614  * @param[in, out] dev
3615  *   Pointer to rte_eth_dev structure.
3616  * @param[in, out] resource
3617  *   Pointer to port ID action resource.
3618  * @parm[in, out] dev_flow
3619  *   Pointer to the dev_flow.
3620  * @param[out] error
3621  *   pointer to error structure.
3622  *
3623  * @return
3624  *   0 on success otherwise -errno and errno is set.
3625  */
3626 static int
3627 flow_dv_port_id_action_resource_register
3628                         (struct rte_eth_dev *dev,
3629                          struct mlx5_flow_dv_port_id_action_resource *resource,
3630                          struct mlx5_flow *dev_flow,
3631                          struct rte_flow_error *error)
3632 {
3633         struct mlx5_priv *priv = dev->data->dev_private;
3634         struct mlx5_cache_entry *entry;
3635         struct mlx5_flow_dv_port_id_action_resource *cache;
3636         struct mlx5_flow_cb_ctx ctx = {
3637                 .error = error,
3638                 .data = resource,
3639         };
3640
3641         entry = mlx5_cache_register(&priv->sh->port_id_action_list, &ctx);
3642         if (!entry)
3643                 return -rte_errno;
3644         cache = container_of(entry, typeof(*cache), entry);
3645         dev_flow->dv.port_id_action = cache;
3646         dev_flow->handle->rix_port_id_action = cache->idx;
3647         return 0;
3648 }
3649
3650 int
3651 flow_dv_push_vlan_match_cb(struct mlx5_cache_list *list __rte_unused,
3652                          struct mlx5_cache_entry *entry, void *cb_ctx)
3653 {
3654         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3655         struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3656         struct mlx5_flow_dv_push_vlan_action_resource *res =
3657                         container_of(entry, typeof(*res), entry);
3658
3659         return ref->vlan_tag != res->vlan_tag || ref->ft_type != res->ft_type;
3660 }
3661
3662 struct mlx5_cache_entry *
3663 flow_dv_push_vlan_create_cb(struct mlx5_cache_list *list,
3664                           struct mlx5_cache_entry *entry __rte_unused,
3665                           void *cb_ctx)
3666 {
3667         struct mlx5_dev_ctx_shared *sh = list->ctx;
3668         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3669         struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3670         struct mlx5_flow_dv_push_vlan_action_resource *cache;
3671         struct mlx5dv_dr_domain *domain;
3672         uint32_t idx;
3673         int ret;
3674
3675         /* Register new port id action resource. */
3676         cache = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN], &idx);
3677         if (!cache) {
3678                 rte_flow_error_set(ctx->error, ENOMEM,
3679                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3680                                    "cannot allocate push_vlan action cache memory");
3681                 return NULL;
3682         }
3683         *cache = *ref;
3684         if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3685                 domain = sh->fdb_domain;
3686         else if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3687                 domain = sh->rx_domain;
3688         else
3689                 domain = sh->tx_domain;
3690         ret = mlx5_flow_os_create_flow_action_push_vlan(domain, ref->vlan_tag,
3691                                                         &cache->action);
3692         if (ret) {
3693                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
3694                 rte_flow_error_set(ctx->error, ENOMEM,
3695                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3696                                    "cannot create push vlan action");
3697                 return NULL;
3698         }
3699         return &cache->entry;
3700 }
3701
3702 /**
3703  * Find existing push vlan resource or create and register a new one.
3704  *
3705  * @param [in, out] dev
3706  *   Pointer to rte_eth_dev structure.
3707  * @param[in, out] resource
3708  *   Pointer to port ID action resource.
3709  * @parm[in, out] dev_flow
3710  *   Pointer to the dev_flow.
3711  * @param[out] error
3712  *   pointer to error structure.
3713  *
3714  * @return
3715  *   0 on success otherwise -errno and errno is set.
3716  */
3717 static int
3718 flow_dv_push_vlan_action_resource_register
3719                        (struct rte_eth_dev *dev,
3720                         struct mlx5_flow_dv_push_vlan_action_resource *resource,
3721                         struct mlx5_flow *dev_flow,
3722                         struct rte_flow_error *error)
3723 {
3724         struct mlx5_priv *priv = dev->data->dev_private;
3725         struct mlx5_flow_dv_push_vlan_action_resource *cache;
3726         struct mlx5_cache_entry *entry;
3727         struct mlx5_flow_cb_ctx ctx = {
3728                 .error = error,
3729                 .data = resource,
3730         };
3731
3732         entry = mlx5_cache_register(&priv->sh->push_vlan_action_list, &ctx);
3733         if (!entry)
3734                 return -rte_errno;
3735         cache = container_of(entry, typeof(*cache), entry);
3736
3737         dev_flow->handle->dvh.rix_push_vlan = cache->idx;
3738         dev_flow->dv.push_vlan_res = cache;
3739         return 0;
3740 }
3741
3742 /**
3743  * Get the size of specific rte_flow_item_type hdr size
3744  *
3745  * @param[in] item_type
3746  *   Tested rte_flow_item_type.
3747  *
3748  * @return
3749  *   sizeof struct item_type, 0 if void or irrelevant.
3750  */
3751 static size_t
3752 flow_dv_get_item_hdr_len(const enum rte_flow_item_type item_type)
3753 {
3754         size_t retval;
3755
3756         switch (item_type) {
3757         case RTE_FLOW_ITEM_TYPE_ETH:
3758                 retval = sizeof(struct rte_ether_hdr);
3759                 break;
3760         case RTE_FLOW_ITEM_TYPE_VLAN:
3761                 retval = sizeof(struct rte_vlan_hdr);
3762                 break;
3763         case RTE_FLOW_ITEM_TYPE_IPV4:
3764                 retval = sizeof(struct rte_ipv4_hdr);
3765                 break;
3766         case RTE_FLOW_ITEM_TYPE_IPV6:
3767                 retval = sizeof(struct rte_ipv6_hdr);
3768                 break;
3769         case RTE_FLOW_ITEM_TYPE_UDP:
3770                 retval = sizeof(struct rte_udp_hdr);
3771                 break;
3772         case RTE_FLOW_ITEM_TYPE_TCP:
3773                 retval = sizeof(struct rte_tcp_hdr);
3774                 break;
3775         case RTE_FLOW_ITEM_TYPE_VXLAN:
3776         case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3777                 retval = sizeof(struct rte_vxlan_hdr);
3778                 break;
3779         case RTE_FLOW_ITEM_TYPE_GRE:
3780         case RTE_FLOW_ITEM_TYPE_NVGRE:
3781                 retval = sizeof(struct rte_gre_hdr);
3782                 break;
3783         case RTE_FLOW_ITEM_TYPE_MPLS:
3784                 retval = sizeof(struct rte_mpls_hdr);
3785                 break;
3786         case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
3787         default:
3788                 retval = 0;
3789                 break;
3790         }
3791         return retval;
3792 }
3793
3794 #define MLX5_ENCAP_IPV4_VERSION         0x40
3795 #define MLX5_ENCAP_IPV4_IHL_MIN         0x05
3796 #define MLX5_ENCAP_IPV4_TTL_DEF         0x40
3797 #define MLX5_ENCAP_IPV6_VTC_FLOW        0x60000000
3798 #define MLX5_ENCAP_IPV6_HOP_LIMIT       0xff
3799 #define MLX5_ENCAP_VXLAN_FLAGS          0x08000000
3800 #define MLX5_ENCAP_VXLAN_GPE_FLAGS      0x04
3801
3802 /**
3803  * Convert the encap action data from list of rte_flow_item to raw buffer
3804  *
3805  * @param[in] items
3806  *   Pointer to rte_flow_item objects list.
3807  * @param[out] buf
3808  *   Pointer to the output buffer.
3809  * @param[out] size
3810  *   Pointer to the output buffer size.
3811  * @param[out] error
3812  *   Pointer to the error structure.
3813  *
3814  * @return
3815  *   0 on success, a negative errno value otherwise and rte_errno is set.
3816  */
3817 static int
3818 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
3819                            size_t *size, struct rte_flow_error *error)
3820 {
3821         struct rte_ether_hdr *eth = NULL;
3822         struct rte_vlan_hdr *vlan = NULL;
3823         struct rte_ipv4_hdr *ipv4 = NULL;
3824         struct rte_ipv6_hdr *ipv6 = NULL;
3825         struct rte_udp_hdr *udp = NULL;
3826         struct rte_vxlan_hdr *vxlan = NULL;
3827         struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
3828         struct rte_gre_hdr *gre = NULL;
3829         size_t len;
3830         size_t temp_size = 0;
3831
3832         if (!items)
3833                 return rte_flow_error_set(error, EINVAL,
3834                                           RTE_FLOW_ERROR_TYPE_ACTION,
3835                                           NULL, "invalid empty data");
3836         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
3837                 len = flow_dv_get_item_hdr_len(items->type);
3838                 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
3839                         return rte_flow_error_set(error, EINVAL,
3840                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3841                                                   (void *)items->type,
3842                                                   "items total size is too big"
3843                                                   " for encap action");
3844                 rte_memcpy((void *)&buf[temp_size], items->spec, len);
3845                 switch (items->type) {
3846                 case RTE_FLOW_ITEM_TYPE_ETH:
3847                         eth = (struct rte_ether_hdr *)&buf[temp_size];
3848                         break;
3849                 case RTE_FLOW_ITEM_TYPE_VLAN:
3850                         vlan = (struct rte_vlan_hdr *)&buf[temp_size];
3851                         if (!eth)
3852                                 return rte_flow_error_set(error, EINVAL,
3853                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3854                                                 (void *)items->type,
3855                                                 "eth header not found");
3856                         if (!eth->ether_type)
3857                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
3858                         break;
3859                 case RTE_FLOW_ITEM_TYPE_IPV4:
3860                         ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
3861                         if (!vlan && !eth)
3862                                 return rte_flow_error_set(error, EINVAL,
3863                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3864                                                 (void *)items->type,
3865                                                 "neither eth nor vlan"
3866                                                 " header found");
3867                         if (vlan && !vlan->eth_proto)
3868                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3869                         else if (eth && !eth->ether_type)
3870                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3871                         if (!ipv4->version_ihl)
3872                                 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
3873                                                     MLX5_ENCAP_IPV4_IHL_MIN;
3874                         if (!ipv4->time_to_live)
3875                                 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
3876                         break;
3877                 case RTE_FLOW_ITEM_TYPE_IPV6:
3878                         ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
3879                         if (!vlan && !eth)
3880                                 return rte_flow_error_set(error, EINVAL,
3881                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3882                                                 (void *)items->type,
3883                                                 "neither eth nor vlan"
3884                                                 " header found");
3885                         if (vlan && !vlan->eth_proto)
3886                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3887                         else if (eth && !eth->ether_type)
3888                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3889                         if (!ipv6->vtc_flow)
3890                                 ipv6->vtc_flow =
3891                                         RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
3892                         if (!ipv6->hop_limits)
3893                                 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
3894                         break;
3895                 case RTE_FLOW_ITEM_TYPE_UDP:
3896                         udp = (struct rte_udp_hdr *)&buf[temp_size];
3897                         if (!ipv4 && !ipv6)
3898                                 return rte_flow_error_set(error, EINVAL,
3899                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3900                                                 (void *)items->type,
3901                                                 "ip header not found");
3902                         if (ipv4 && !ipv4->next_proto_id)
3903                                 ipv4->next_proto_id = IPPROTO_UDP;
3904                         else if (ipv6 && !ipv6->proto)
3905                                 ipv6->proto = IPPROTO_UDP;
3906                         break;
3907                 case RTE_FLOW_ITEM_TYPE_VXLAN:
3908                         vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
3909                         if (!udp)
3910                                 return rte_flow_error_set(error, EINVAL,
3911                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3912                                                 (void *)items->type,
3913                                                 "udp header not found");
3914                         if (!udp->dst_port)
3915                                 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
3916                         if (!vxlan->vx_flags)
3917                                 vxlan->vx_flags =
3918                                         RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
3919                         break;
3920                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3921                         vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
3922                         if (!udp)
3923                                 return rte_flow_error_set(error, EINVAL,
3924                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3925                                                 (void *)items->type,
3926                                                 "udp header not found");
3927                         if (!vxlan_gpe->proto)
3928                                 return rte_flow_error_set(error, EINVAL,
3929                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3930                                                 (void *)items->type,
3931                                                 "next protocol not found");
3932                         if (!udp->dst_port)
3933                                 udp->dst_port =
3934                                         RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
3935                         if (!vxlan_gpe->vx_flags)
3936                                 vxlan_gpe->vx_flags =
3937                                                 MLX5_ENCAP_VXLAN_GPE_FLAGS;
3938                         break;
3939                 case RTE_FLOW_ITEM_TYPE_GRE:
3940                 case RTE_FLOW_ITEM_TYPE_NVGRE:
3941                         gre = (struct rte_gre_hdr *)&buf[temp_size];
3942                         if (!gre->proto)
3943                                 return rte_flow_error_set(error, EINVAL,
3944                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3945                                                 (void *)items->type,
3946                                                 "next protocol not found");
3947                         if (!ipv4 && !ipv6)
3948                                 return rte_flow_error_set(error, EINVAL,
3949                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3950                                                 (void *)items->type,
3951                                                 "ip header not found");
3952                         if (ipv4 && !ipv4->next_proto_id)
3953                                 ipv4->next_proto_id = IPPROTO_GRE;
3954                         else if (ipv6 && !ipv6->proto)
3955                                 ipv6->proto = IPPROTO_GRE;
3956                         break;
3957                 case RTE_FLOW_ITEM_TYPE_VOID:
3958                         break;
3959                 default:
3960                         return rte_flow_error_set(error, EINVAL,
3961                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3962                                                   (void *)items->type,
3963                                                   "unsupported item type");
3964                         break;
3965                 }
3966                 temp_size += len;
3967         }
3968         *size = temp_size;
3969         return 0;
3970 }
3971
3972 static int
3973 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
3974 {
3975         struct rte_ether_hdr *eth = NULL;
3976         struct rte_vlan_hdr *vlan = NULL;
3977         struct rte_ipv6_hdr *ipv6 = NULL;
3978         struct rte_udp_hdr *udp = NULL;
3979         char *next_hdr;
3980         uint16_t proto;
3981
3982         eth = (struct rte_ether_hdr *)data;
3983         next_hdr = (char *)(eth + 1);
3984         proto = RTE_BE16(eth->ether_type);
3985
3986         /* VLAN skipping */
3987         while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
3988                 vlan = (struct rte_vlan_hdr *)next_hdr;
3989                 proto = RTE_BE16(vlan->eth_proto);
3990                 next_hdr += sizeof(struct rte_vlan_hdr);
3991         }
3992
3993         /* HW calculates IPv4 csum. no need to proceed */
3994         if (proto == RTE_ETHER_TYPE_IPV4)
3995                 return 0;
3996
3997         /* non IPv4/IPv6 header. not supported */
3998         if (proto != RTE_ETHER_TYPE_IPV6) {
3999                 return rte_flow_error_set(error, ENOTSUP,
4000                                           RTE_FLOW_ERROR_TYPE_ACTION,
4001                                           NULL, "Cannot offload non IPv4/IPv6");
4002         }
4003
4004         ipv6 = (struct rte_ipv6_hdr *)next_hdr;
4005
4006         /* ignore non UDP */
4007         if (ipv6->proto != IPPROTO_UDP)
4008                 return 0;
4009
4010         udp = (struct rte_udp_hdr *)(ipv6 + 1);
4011         udp->dgram_cksum = 0;
4012
4013         return 0;
4014 }
4015
4016 /**
4017  * Convert L2 encap action to DV specification.
4018  *
4019  * @param[in] dev
4020  *   Pointer to rte_eth_dev structure.
4021  * @param[in] action
4022  *   Pointer to action structure.
4023  * @param[in, out] dev_flow
4024  *   Pointer to the mlx5_flow.
4025  * @param[in] transfer
4026  *   Mark if the flow is E-Switch flow.
4027  * @param[out] error
4028  *   Pointer to the error structure.
4029  *
4030  * @return
4031  *   0 on success, a negative errno value otherwise and rte_errno is set.
4032  */
4033 static int
4034 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
4035                                const struct rte_flow_action *action,
4036                                struct mlx5_flow *dev_flow,
4037                                uint8_t transfer,
4038                                struct rte_flow_error *error)
4039 {
4040         const struct rte_flow_item *encap_data;
4041         const struct rte_flow_action_raw_encap *raw_encap_data;
4042         struct mlx5_flow_dv_encap_decap_resource res = {
4043                 .reformat_type =
4044                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
4045                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
4046                                       MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
4047         };
4048
4049         if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
4050                 raw_encap_data =
4051                         (const struct rte_flow_action_raw_encap *)action->conf;
4052                 res.size = raw_encap_data->size;
4053                 memcpy(res.buf, raw_encap_data->data, res.size);
4054         } else {
4055                 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
4056                         encap_data =
4057                                 ((const struct rte_flow_action_vxlan_encap *)
4058                                                 action->conf)->definition;
4059                 else
4060                         encap_data =
4061                                 ((const struct rte_flow_action_nvgre_encap *)
4062                                                 action->conf)->definition;
4063                 if (flow_dv_convert_encap_data(encap_data, res.buf,
4064                                                &res.size, error))
4065                         return -rte_errno;
4066         }
4067         if (flow_dv_zero_encap_udp_csum(res.buf, error))
4068                 return -rte_errno;
4069         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4070                 return rte_flow_error_set(error, EINVAL,
4071                                           RTE_FLOW_ERROR_TYPE_ACTION,
4072                                           NULL, "can't create L2 encap action");
4073         return 0;
4074 }
4075
4076 /**
4077  * Convert L2 decap action to DV specification.
4078  *
4079  * @param[in] dev
4080  *   Pointer to rte_eth_dev structure.
4081  * @param[in, out] dev_flow
4082  *   Pointer to the mlx5_flow.
4083  * @param[in] transfer
4084  *   Mark if the flow is E-Switch flow.
4085  * @param[out] error
4086  *   Pointer to the error structure.
4087  *
4088  * @return
4089  *   0 on success, a negative errno value otherwise and rte_errno is set.
4090  */
4091 static int
4092 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
4093                                struct mlx5_flow *dev_flow,
4094                                uint8_t transfer,
4095                                struct rte_flow_error *error)
4096 {
4097         struct mlx5_flow_dv_encap_decap_resource res = {
4098                 .size = 0,
4099                 .reformat_type =
4100                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
4101                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
4102                                       MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
4103         };
4104
4105         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4106                 return rte_flow_error_set(error, EINVAL,
4107                                           RTE_FLOW_ERROR_TYPE_ACTION,
4108                                           NULL, "can't create L2 decap action");
4109         return 0;
4110 }
4111
4112 /**
4113  * Convert raw decap/encap (L3 tunnel) action to DV specification.
4114  *
4115  * @param[in] dev
4116  *   Pointer to rte_eth_dev structure.
4117  * @param[in] action
4118  *   Pointer to action structure.
4119  * @param[in, out] dev_flow
4120  *   Pointer to the mlx5_flow.
4121  * @param[in] attr
4122  *   Pointer to the flow attributes.
4123  * @param[out] error
4124  *   Pointer to the error structure.
4125  *
4126  * @return
4127  *   0 on success, a negative errno value otherwise and rte_errno is set.
4128  */
4129 static int
4130 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
4131                                 const struct rte_flow_action *action,
4132                                 struct mlx5_flow *dev_flow,
4133                                 const struct rte_flow_attr *attr,
4134                                 struct rte_flow_error *error)
4135 {
4136         const struct rte_flow_action_raw_encap *encap_data;
4137         struct mlx5_flow_dv_encap_decap_resource res;
4138
4139         memset(&res, 0, sizeof(res));
4140         encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
4141         res.size = encap_data->size;
4142         memcpy(res.buf, encap_data->data, res.size);
4143         res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
4144                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
4145                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
4146         if (attr->transfer)
4147                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
4148         else
4149                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
4150                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
4151         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4152                 return rte_flow_error_set(error, EINVAL,
4153                                           RTE_FLOW_ERROR_TYPE_ACTION,
4154                                           NULL, "can't create encap action");
4155         return 0;
4156 }
4157
4158 /**
4159  * Create action push VLAN.
4160  *
4161  * @param[in] dev
4162  *   Pointer to rte_eth_dev structure.
4163  * @param[in] attr
4164  *   Pointer to the flow attributes.
4165  * @param[in] vlan
4166  *   Pointer to the vlan to push to the Ethernet header.
4167  * @param[in, out] dev_flow
4168  *   Pointer to the mlx5_flow.
4169  * @param[out] error
4170  *   Pointer to the error structure.
4171  *
4172  * @return
4173  *   0 on success, a negative errno value otherwise and rte_errno is set.
4174  */
4175 static int
4176 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
4177                                 const struct rte_flow_attr *attr,
4178                                 const struct rte_vlan_hdr *vlan,
4179                                 struct mlx5_flow *dev_flow,
4180                                 struct rte_flow_error *error)
4181 {
4182         struct mlx5_flow_dv_push_vlan_action_resource res;
4183
4184         memset(&res, 0, sizeof(res));
4185         res.vlan_tag =
4186                 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
4187                                  vlan->vlan_tci);
4188         if (attr->transfer)
4189                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
4190         else
4191                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
4192                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
4193         return flow_dv_push_vlan_action_resource_register
4194                                             (dev, &res, dev_flow, error);
4195 }
4196
4197 /**
4198  * Validate the modify-header actions.
4199  *
4200  * @param[in] action_flags
4201  *   Holds the actions detected until now.
4202  * @param[in] action
4203  *   Pointer to the modify action.
4204  * @param[out] error
4205  *   Pointer to error structure.
4206  *
4207  * @return
4208  *   0 on success, a negative errno value otherwise and rte_errno is set.
4209  */
4210 static int
4211 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
4212                                    const struct rte_flow_action *action,
4213                                    struct rte_flow_error *error)
4214 {
4215         if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
4216                 return rte_flow_error_set(error, EINVAL,
4217                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4218                                           NULL, "action configuration not set");
4219         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
4220                 return rte_flow_error_set(error, EINVAL,
4221                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4222                                           "can't have encap action before"
4223                                           " modify action");
4224         return 0;
4225 }
4226
4227 /**
4228  * Validate the modify-header MAC address actions.
4229  *
4230  * @param[in] action_flags
4231  *   Holds the actions detected until now.
4232  * @param[in] action
4233  *   Pointer to the modify action.
4234  * @param[in] item_flags
4235  *   Holds the items detected.
4236  * @param[out] error
4237  *   Pointer to error structure.
4238  *
4239  * @return
4240  *   0 on success, a negative errno value otherwise and rte_errno is set.
4241  */
4242 static int
4243 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
4244                                    const struct rte_flow_action *action,
4245                                    const uint64_t item_flags,
4246                                    struct rte_flow_error *error)
4247 {
4248         int ret = 0;
4249
4250         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4251         if (!ret) {
4252                 if (!(item_flags & MLX5_FLOW_LAYER_L2))
4253                         return rte_flow_error_set(error, EINVAL,
4254                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4255                                                   NULL,
4256                                                   "no L2 item in pattern");
4257         }
4258         return ret;
4259 }
4260
4261 /**
4262  * Validate the modify-header IPv4 address actions.
4263  *
4264  * @param[in] action_flags
4265  *   Holds the actions detected until now.
4266  * @param[in] action
4267  *   Pointer to the modify action.
4268  * @param[in] item_flags
4269  *   Holds the items detected.
4270  * @param[out] error
4271  *   Pointer to error structure.
4272  *
4273  * @return
4274  *   0 on success, a negative errno value otherwise and rte_errno is set.
4275  */
4276 static int
4277 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
4278                                     const struct rte_flow_action *action,
4279                                     const uint64_t item_flags,
4280                                     struct rte_flow_error *error)
4281 {
4282         int ret = 0;
4283         uint64_t layer;
4284
4285         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4286         if (!ret) {
4287                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4288                                  MLX5_FLOW_LAYER_INNER_L3_IPV4 :
4289                                  MLX5_FLOW_LAYER_OUTER_L3_IPV4;
4290                 if (!(item_flags & layer))
4291                         return rte_flow_error_set(error, EINVAL,
4292                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4293                                                   NULL,
4294                                                   "no ipv4 item in pattern");
4295         }
4296         return ret;
4297 }
4298
4299 /**
4300  * Validate the modify-header IPv6 address actions.
4301  *
4302  * @param[in] action_flags
4303  *   Holds the actions detected until now.
4304  * @param[in] action
4305  *   Pointer to the modify action.
4306  * @param[in] item_flags
4307  *   Holds the items detected.
4308  * @param[out] error
4309  *   Pointer to error structure.
4310  *
4311  * @return
4312  *   0 on success, a negative errno value otherwise and rte_errno is set.
4313  */
4314 static int
4315 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
4316                                     const struct rte_flow_action *action,
4317                                     const uint64_t item_flags,
4318                                     struct rte_flow_error *error)
4319 {
4320         int ret = 0;
4321         uint64_t layer;
4322
4323         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4324         if (!ret) {
4325                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4326                                  MLX5_FLOW_LAYER_INNER_L3_IPV6 :
4327                                  MLX5_FLOW_LAYER_OUTER_L3_IPV6;
4328                 if (!(item_flags & layer))
4329                         return rte_flow_error_set(error, EINVAL,
4330                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4331                                                   NULL,
4332                                                   "no ipv6 item in pattern");
4333         }
4334         return ret;
4335 }
4336
4337 /**
4338  * Validate the modify-header TP actions.
4339  *
4340  * @param[in] action_flags
4341  *   Holds the actions detected until now.
4342  * @param[in] action
4343  *   Pointer to the modify action.
4344  * @param[in] item_flags
4345  *   Holds the items detected.
4346  * @param[out] error
4347  *   Pointer to error structure.
4348  *
4349  * @return
4350  *   0 on success, a negative errno value otherwise and rte_errno is set.
4351  */
4352 static int
4353 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
4354                                   const struct rte_flow_action *action,
4355                                   const uint64_t item_flags,
4356                                   struct rte_flow_error *error)
4357 {
4358         int ret = 0;
4359         uint64_t layer;
4360
4361         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4362         if (!ret) {
4363                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4364                                  MLX5_FLOW_LAYER_INNER_L4 :
4365                                  MLX5_FLOW_LAYER_OUTER_L4;
4366                 if (!(item_flags & layer))
4367                         return rte_flow_error_set(error, EINVAL,
4368                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4369                                                   NULL, "no transport layer "
4370                                                   "in pattern");
4371         }
4372         return ret;
4373 }
4374
4375 /**
4376  * Validate the modify-header actions of increment/decrement
4377  * TCP Sequence-number.
4378  *
4379  * @param[in] action_flags
4380  *   Holds the actions detected until now.
4381  * @param[in] action
4382  *   Pointer to the modify action.
4383  * @param[in] item_flags
4384  *   Holds the items detected.
4385  * @param[out] error
4386  *   Pointer to error structure.
4387  *
4388  * @return
4389  *   0 on success, a negative errno value otherwise and rte_errno is set.
4390  */
4391 static int
4392 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
4393                                        const struct rte_flow_action *action,
4394                                        const uint64_t item_flags,
4395                                        struct rte_flow_error *error)
4396 {
4397         int ret = 0;
4398         uint64_t layer;
4399
4400         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4401         if (!ret) {
4402                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4403                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
4404                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
4405                 if (!(item_flags & layer))
4406                         return rte_flow_error_set(error, EINVAL,
4407                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4408                                                   NULL, "no TCP item in"
4409                                                   " pattern");
4410                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
4411                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
4412                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
4413                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
4414                         return rte_flow_error_set(error, EINVAL,
4415                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4416                                                   NULL,
4417                                                   "cannot decrease and increase"
4418                                                   " TCP sequence number"
4419                                                   " at the same time");
4420         }
4421         return ret;
4422 }
4423
4424 /**
4425  * Validate the modify-header actions of increment/decrement
4426  * TCP Acknowledgment number.
4427  *
4428  * @param[in] action_flags
4429  *   Holds the actions detected until now.
4430  * @param[in] action
4431  *   Pointer to the modify action.
4432  * @param[in] item_flags
4433  *   Holds the items detected.
4434  * @param[out] error
4435  *   Pointer to error structure.
4436  *
4437  * @return
4438  *   0 on success, a negative errno value otherwise and rte_errno is set.
4439  */
4440 static int
4441 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
4442                                        const struct rte_flow_action *action,
4443                                        const uint64_t item_flags,
4444                                        struct rte_flow_error *error)
4445 {
4446         int ret = 0;
4447         uint64_t layer;
4448
4449         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4450         if (!ret) {
4451                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4452                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
4453                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
4454                 if (!(item_flags & layer))
4455                         return rte_flow_error_set(error, EINVAL,
4456                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4457                                                   NULL, "no TCP item in"
4458                                                   " pattern");
4459                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
4460                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
4461                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
4462                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
4463                         return rte_flow_error_set(error, EINVAL,
4464                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4465                                                   NULL,
4466                                                   "cannot decrease and increase"
4467                                                   " TCP acknowledgment number"
4468                                                   " at the same time");
4469         }
4470         return ret;
4471 }
4472
4473 /**
4474  * Validate the modify-header TTL actions.
4475  *
4476  * @param[in] action_flags
4477  *   Holds the actions detected until now.
4478  * @param[in] action
4479  *   Pointer to the modify action.
4480  * @param[in] item_flags
4481  *   Holds the items detected.
4482  * @param[out] error
4483  *   Pointer to error structure.
4484  *
4485  * @return
4486  *   0 on success, a negative errno value otherwise and rte_errno is set.
4487  */
4488 static int
4489 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
4490                                    const struct rte_flow_action *action,
4491                                    const uint64_t item_flags,
4492                                    struct rte_flow_error *error)
4493 {
4494         int ret = 0;
4495         uint64_t layer;
4496
4497         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4498         if (!ret) {
4499                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4500                                  MLX5_FLOW_LAYER_INNER_L3 :
4501                                  MLX5_FLOW_LAYER_OUTER_L3;
4502                 if (!(item_flags & layer))
4503                         return rte_flow_error_set(error, EINVAL,
4504                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4505                                                   NULL,
4506                                                   "no IP protocol in pattern");
4507         }
4508         return ret;
4509 }
4510
4511 static int
4512 mlx5_flow_item_field_width(enum rte_flow_field_id field)
4513 {
4514         switch (field) {
4515         case RTE_FLOW_FIELD_START:
4516                 return 32;
4517         case RTE_FLOW_FIELD_MAC_DST:
4518         case RTE_FLOW_FIELD_MAC_SRC:
4519                 return 48;
4520         case RTE_FLOW_FIELD_VLAN_TYPE:
4521                 return 16;
4522         case RTE_FLOW_FIELD_VLAN_ID:
4523                 return 12;
4524         case RTE_FLOW_FIELD_MAC_TYPE:
4525                 return 16;
4526         case RTE_FLOW_FIELD_IPV4_DSCP:
4527                 return 6;
4528         case RTE_FLOW_FIELD_IPV4_TTL:
4529                 return 8;
4530         case RTE_FLOW_FIELD_IPV4_SRC:
4531         case RTE_FLOW_FIELD_IPV4_DST:
4532                 return 32;
4533         case RTE_FLOW_FIELD_IPV6_DSCP:
4534                 return 6;
4535         case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
4536                 return 8;
4537         case RTE_FLOW_FIELD_IPV6_SRC:
4538         case RTE_FLOW_FIELD_IPV6_DST:
4539                 return 128;
4540         case RTE_FLOW_FIELD_TCP_PORT_SRC:
4541         case RTE_FLOW_FIELD_TCP_PORT_DST:
4542                 return 16;
4543         case RTE_FLOW_FIELD_TCP_SEQ_NUM:
4544         case RTE_FLOW_FIELD_TCP_ACK_NUM:
4545                 return 32;
4546         case RTE_FLOW_FIELD_TCP_FLAGS:
4547                 return 6;
4548         case RTE_FLOW_FIELD_UDP_PORT_SRC:
4549         case RTE_FLOW_FIELD_UDP_PORT_DST:
4550                 return 16;
4551         case RTE_FLOW_FIELD_VXLAN_VNI:
4552         case RTE_FLOW_FIELD_GENEVE_VNI:
4553                 return 24;
4554         case RTE_FLOW_FIELD_GTP_TEID:
4555         case RTE_FLOW_FIELD_TAG:
4556                 return 32;
4557         case RTE_FLOW_FIELD_MARK:
4558                 return 24;
4559         case RTE_FLOW_FIELD_META:
4560         case RTE_FLOW_FIELD_POINTER:
4561         case RTE_FLOW_FIELD_VALUE:
4562                 return 32;
4563         default:
4564                 MLX5_ASSERT(false);
4565         }
4566         return 0;
4567 }
4568
4569 /**
4570  * Validate the generic modify field actions.
4571  *
4572  * @param[in] action_flags
4573  *   Holds the actions detected until now.
4574  * @param[in] action
4575  *   Pointer to the modify action.
4576  * @param[in] item_flags
4577  *   Holds the items detected.
4578  * @param[out] error
4579  *   Pointer to error structure.
4580  *
4581  * @return
4582  *   Number of header fields to modify (0 or more) on success,
4583  *   a negative errno value otherwise and rte_errno is set.
4584  */
4585 static int
4586 flow_dv_validate_action_modify_field(const uint64_t action_flags,
4587                                    const struct rte_flow_action *action,
4588                                    struct rte_flow_error *error)
4589 {
4590         int ret = 0;
4591         const struct rte_flow_action_modify_field *action_modify_field =
4592                 action->conf;
4593         uint32_t dst_width =
4594                 mlx5_flow_item_field_width(action_modify_field->dst.field);
4595         uint32_t src_width =
4596                 mlx5_flow_item_field_width(action_modify_field->src.field);
4597
4598         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4599         if (ret)
4600                 return ret;
4601
4602         if (action_modify_field->dst.field != RTE_FLOW_FIELD_VALUE &&
4603             action_modify_field->dst.field != RTE_FLOW_FIELD_POINTER) {
4604                 if (action_modify_field->dst.offset >= dst_width ||
4605                     (action_modify_field->dst.offset % 32))
4606                         return rte_flow_error_set(error, EINVAL,
4607                                                 RTE_FLOW_ERROR_TYPE_ACTION,
4608                                                 NULL,
4609                                                 "destination offset is too big"
4610                                                 " or not aligned to 4 bytes");
4611                 if (action_modify_field->dst.level &&
4612                     action_modify_field->dst.field != RTE_FLOW_FIELD_TAG)
4613                         return rte_flow_error_set(error, EINVAL,
4614                                                 RTE_FLOW_ERROR_TYPE_ACTION,
4615                                                 NULL,
4616                                                 "cannot modify inner headers");
4617         }
4618         if (action_modify_field->src.field != RTE_FLOW_FIELD_VALUE &&
4619             action_modify_field->src.field != RTE_FLOW_FIELD_POINTER) {
4620                 if (action_modify_field->src.offset >= src_width ||
4621                     (action_modify_field->src.offset % 32))
4622                         return rte_flow_error_set(error, EINVAL,
4623                                                 RTE_FLOW_ERROR_TYPE_ACTION,
4624                                                 NULL,
4625                                                 "source offset is too big"
4626                                                 " or not aligned to 4 bytes");
4627                 if (action_modify_field->src.level &&
4628                     action_modify_field->src.field != RTE_FLOW_FIELD_TAG)
4629                         return rte_flow_error_set(error, EINVAL,
4630                                                 RTE_FLOW_ERROR_TYPE_ACTION,
4631                                                 NULL,
4632                                                 "cannot copy from inner headers");
4633         }
4634         if (action_modify_field->width == 0)
4635                 return rte_flow_error_set(error, EINVAL,
4636                                                 RTE_FLOW_ERROR_TYPE_ACTION,
4637                                                 NULL,
4638                                                 "width is required for modify action");
4639         if (action_modify_field->dst.field ==
4640             action_modify_field->src.field)
4641                 return rte_flow_error_set(error, EINVAL,
4642                                         RTE_FLOW_ERROR_TYPE_ACTION,
4643                                         NULL,
4644                                         "source and destination fields"
4645                                         " cannot be the same");
4646         if (action_modify_field->dst.field == RTE_FLOW_FIELD_VALUE ||
4647             action_modify_field->dst.field == RTE_FLOW_FIELD_POINTER)
4648                 return rte_flow_error_set(error, EINVAL,
4649                                         RTE_FLOW_ERROR_TYPE_ACTION,
4650                                         NULL,
4651                                         "immediate value or a pointer to it"
4652                                         " cannot be used as a destination");
4653         if (action_modify_field->dst.field == RTE_FLOW_FIELD_START ||
4654             action_modify_field->src.field == RTE_FLOW_FIELD_START)
4655                 return rte_flow_error_set(error, EINVAL,
4656                                 RTE_FLOW_ERROR_TYPE_ACTION,
4657                                 NULL,
4658                                 "modifications of an arbitrary"
4659                                 " place in a packet is not supported");
4660         if (action_modify_field->operation != RTE_FLOW_MODIFY_SET)
4661                 return rte_flow_error_set(error, EINVAL,
4662                                 RTE_FLOW_ERROR_TYPE_ACTION,
4663                                 NULL,
4664                                 "add and sub operations"
4665                                 " are not supported");
4666         return (action_modify_field->width / 32) +
4667                !!(action_modify_field->width % 32);
4668 }
4669
4670 /**
4671  * Validate jump action.
4672  *
4673  * @param[in] action
4674  *   Pointer to the jump action.
4675  * @param[in] action_flags
4676  *   Holds the actions detected until now.
4677  * @param[in] attributes
4678  *   Pointer to flow attributes
4679  * @param[in] external
4680  *   Action belongs to flow rule created by request external to PMD.
4681  * @param[out] error
4682  *   Pointer to error structure.
4683  *
4684  * @return
4685  *   0 on success, a negative errno value otherwise and rte_errno is set.
4686  */
4687 static int
4688 flow_dv_validate_action_jump(struct rte_eth_dev *dev,
4689                              const struct mlx5_flow_tunnel *tunnel,
4690                              const struct rte_flow_action *action,
4691                              uint64_t action_flags,
4692                              const struct rte_flow_attr *attributes,
4693                              bool external, struct rte_flow_error *error)
4694 {
4695         uint32_t target_group, table;
4696         int ret = 0;
4697         struct flow_grp_info grp_info = {
4698                 .external = !!external,
4699                 .transfer = !!attributes->transfer,
4700                 .fdb_def_rule = 1,
4701                 .std_tbl_fix = 0
4702         };
4703         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
4704                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4705                 return rte_flow_error_set(error, EINVAL,
4706                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4707                                           "can't have 2 fate actions in"
4708                                           " same flow");
4709         if (action_flags & MLX5_FLOW_ACTION_METER)
4710                 return rte_flow_error_set(error, ENOTSUP,
4711                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4712                                           "jump with meter not support");
4713         if (!action->conf)
4714                 return rte_flow_error_set(error, EINVAL,
4715                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4716                                           NULL, "action configuration not set");
4717         target_group =
4718                 ((const struct rte_flow_action_jump *)action->conf)->group;
4719         ret = mlx5_flow_group_to_table(dev, tunnel, target_group, &table,
4720                                        &grp_info, error);
4721         if (ret)
4722                 return ret;
4723         if (attributes->group == target_group &&
4724             !(action_flags & (MLX5_FLOW_ACTION_TUNNEL_SET |
4725                               MLX5_FLOW_ACTION_TUNNEL_MATCH)))
4726                 return rte_flow_error_set(error, EINVAL,
4727                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4728                                           "target group must be other than"
4729                                           " the current flow group");
4730         return 0;
4731 }
4732
4733 /*
4734  * Validate the port_id action.
4735  *
4736  * @param[in] dev
4737  *   Pointer to rte_eth_dev structure.
4738  * @param[in] action_flags
4739  *   Bit-fields that holds the actions detected until now.
4740  * @param[in] action
4741  *   Port_id RTE action structure.
4742  * @param[in] attr
4743  *   Attributes of flow that includes this action.
4744  * @param[out] error
4745  *   Pointer to error structure.
4746  *
4747  * @return
4748  *   0 on success, a negative errno value otherwise and rte_errno is set.
4749  */
4750 static int
4751 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
4752                                 uint64_t action_flags,
4753                                 const struct rte_flow_action *action,
4754                                 const struct rte_flow_attr *attr,
4755                                 struct rte_flow_error *error)
4756 {
4757         const struct rte_flow_action_port_id *port_id;
4758         struct mlx5_priv *act_priv;
4759         struct mlx5_priv *dev_priv;
4760         uint16_t port;
4761
4762         if (!attr->transfer)
4763                 return rte_flow_error_set(error, ENOTSUP,
4764                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4765                                           NULL,
4766                                           "port id action is valid in transfer"
4767                                           " mode only");
4768         if (!action || !action->conf)
4769                 return rte_flow_error_set(error, ENOTSUP,
4770                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4771                                           NULL,
4772                                           "port id action parameters must be"
4773                                           " specified");
4774         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
4775                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4776                 return rte_flow_error_set(error, EINVAL,
4777                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4778                                           "can have only one fate actions in"
4779                                           " a flow");
4780         dev_priv = mlx5_dev_to_eswitch_info(dev);
4781         if (!dev_priv)
4782                 return rte_flow_error_set(error, rte_errno,
4783                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4784                                           NULL,
4785                                           "failed to obtain E-Switch info");
4786         port_id = action->conf;
4787         port = port_id->original ? dev->data->port_id : port_id->id;
4788         act_priv = mlx5_port_to_eswitch_info(port, false);
4789         if (!act_priv)
4790                 return rte_flow_error_set
4791                                 (error, rte_errno,
4792                                  RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
4793                                  "failed to obtain E-Switch port id for port");
4794         if (act_priv->domain_id != dev_priv->domain_id)
4795                 return rte_flow_error_set
4796                                 (error, EINVAL,
4797                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4798                                  "port does not belong to"
4799                                  " E-Switch being configured");
4800         return 0;
4801 }
4802
4803 /**
4804  * Get the maximum number of modify header actions.
4805  *
4806  * @param dev
4807  *   Pointer to rte_eth_dev structure.
4808  * @param flags
4809  *   Flags bits to check if root level.
4810  *
4811  * @return
4812  *   Max number of modify header actions device can support.
4813  */
4814 static inline unsigned int
4815 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev __rte_unused,
4816                               uint64_t flags)
4817 {
4818         /*
4819          * There's no way to directly query the max capacity from FW.
4820          * The maximal value on root table should be assumed to be supported.
4821          */
4822         if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
4823                 return MLX5_MAX_MODIFY_NUM;
4824         else
4825                 return MLX5_ROOT_TBL_MODIFY_NUM;
4826 }
4827
4828 /**
4829  * Validate the meter action.
4830  *
4831  * @param[in] dev
4832  *   Pointer to rte_eth_dev structure.
4833  * @param[in] action_flags
4834  *   Bit-fields that holds the actions detected until now.
4835  * @param[in] action
4836  *   Pointer to the meter action.
4837  * @param[in] attr
4838  *   Attributes of flow that includes this action.
4839  * @param[out] error
4840  *   Pointer to error structure.
4841  *
4842  * @return
4843  *   0 on success, a negative errno value otherwise and rte_ernno is set.
4844  */
4845 static int
4846 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
4847                                 uint64_t action_flags,
4848                                 const struct rte_flow_action *action,
4849                                 const struct rte_flow_attr *attr,
4850                                 struct rte_flow_error *error)
4851 {
4852         struct mlx5_priv *priv = dev->data->dev_private;
4853         const struct rte_flow_action_meter *am = action->conf;
4854         struct mlx5_flow_meter *fm;
4855
4856         if (!am)
4857                 return rte_flow_error_set(error, EINVAL,
4858                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4859                                           "meter action conf is NULL");
4860
4861         if (action_flags & MLX5_FLOW_ACTION_METER)
4862                 return rte_flow_error_set(error, ENOTSUP,
4863                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4864                                           "meter chaining not support");
4865         if (action_flags & MLX5_FLOW_ACTION_JUMP)
4866                 return rte_flow_error_set(error, ENOTSUP,
4867                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4868                                           "meter with jump not support");
4869         if (!priv->mtr_en)
4870                 return rte_flow_error_set(error, ENOTSUP,
4871                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4872                                           NULL,
4873                                           "meter action not supported");
4874         fm = mlx5_flow_meter_find(priv, am->mtr_id);
4875         if (!fm)
4876                 return rte_flow_error_set(error, EINVAL,
4877                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4878                                           "Meter not found");
4879         if (fm->ref_cnt && (!(fm->transfer == attr->transfer ||
4880               (!fm->ingress && !attr->ingress && attr->egress) ||
4881               (!fm->egress && !attr->egress && attr->ingress))))
4882                 return rte_flow_error_set(error, EINVAL,
4883                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4884                                           "Flow attributes are either invalid "
4885                                           "or have a conflict with current "
4886                                           "meter attributes");
4887         return 0;
4888 }
4889
4890 /**
4891  * Validate the age action.
4892  *
4893  * @param[in] action_flags
4894  *   Holds the actions detected until now.
4895  * @param[in] action
4896  *   Pointer to the age action.
4897  * @param[in] dev
4898  *   Pointer to the Ethernet device structure.
4899  * @param[out] error
4900  *   Pointer to error structure.
4901  *
4902  * @return
4903  *   0 on success, a negative errno value otherwise and rte_errno is set.
4904  */
4905 static int
4906 flow_dv_validate_action_age(uint64_t action_flags,
4907                             const struct rte_flow_action *action,
4908                             struct rte_eth_dev *dev,
4909                             struct rte_flow_error *error)
4910 {
4911         struct mlx5_priv *priv = dev->data->dev_private;
4912         const struct rte_flow_action_age *age = action->conf;
4913
4914         if (!priv->config.devx || (priv->sh->cmng.counter_fallback &&
4915             !priv->sh->aso_age_mng))
4916                 return rte_flow_error_set(error, ENOTSUP,
4917                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4918                                           NULL,
4919                                           "age action not supported");
4920         if (!(action->conf))
4921                 return rte_flow_error_set(error, EINVAL,
4922                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4923                                           "configuration cannot be null");
4924         if (!(age->timeout))
4925                 return rte_flow_error_set(error, EINVAL,
4926                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4927                                           "invalid timeout value 0");
4928         if (action_flags & MLX5_FLOW_ACTION_AGE)
4929                 return rte_flow_error_set(error, EINVAL,
4930                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4931                                           "duplicate age actions set");
4932         return 0;
4933 }
4934
4935 /**
4936  * Validate the modify-header IPv4 DSCP actions.
4937  *
4938  * @param[in] action_flags
4939  *   Holds the actions detected until now.
4940  * @param[in] action
4941  *   Pointer to the modify action.
4942  * @param[in] item_flags
4943  *   Holds the items detected.
4944  * @param[out] error
4945  *   Pointer to error structure.
4946  *
4947  * @return
4948  *   0 on success, a negative errno value otherwise and rte_errno is set.
4949  */
4950 static int
4951 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
4952                                          const struct rte_flow_action *action,
4953                                          const uint64_t item_flags,
4954                                          struct rte_flow_error *error)
4955 {
4956         int ret = 0;
4957
4958         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4959         if (!ret) {
4960                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
4961                         return rte_flow_error_set(error, EINVAL,
4962                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4963                                                   NULL,
4964                                                   "no ipv4 item in pattern");
4965         }
4966         return ret;
4967 }
4968
4969 /**
4970  * Validate the modify-header IPv6 DSCP actions.
4971  *
4972  * @param[in] action_flags
4973  *   Holds the actions detected until now.
4974  * @param[in] action
4975  *   Pointer to the modify action.
4976  * @param[in] item_flags
4977  *   Holds the items detected.
4978  * @param[out] error
4979  *   Pointer to error structure.
4980  *
4981  * @return
4982  *   0 on success, a negative errno value otherwise and rte_errno is set.
4983  */
4984 static int
4985 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
4986                                          const struct rte_flow_action *action,
4987                                          const uint64_t item_flags,
4988                                          struct rte_flow_error *error)
4989 {
4990         int ret = 0;
4991
4992         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4993         if (!ret) {
4994                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
4995                         return rte_flow_error_set(error, EINVAL,
4996                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4997                                                   NULL,
4998                                                   "no ipv6 item in pattern");
4999         }
5000         return ret;
5001 }
5002
5003 /**
5004  * Match modify-header resource.
5005  *
5006  * @param list
5007  *   Pointer to the hash list.
5008  * @param entry
5009  *   Pointer to exist resource entry object.
5010  * @param key
5011  *   Key of the new entry.
5012  * @param ctx
5013  *   Pointer to new modify-header resource.
5014  *
5015  * @return
5016  *   0 on matching, non-zero otherwise.
5017  */
5018 int
5019 flow_dv_modify_match_cb(struct mlx5_hlist *list __rte_unused,
5020                         struct mlx5_hlist_entry *entry,
5021                         uint64_t key __rte_unused, void *cb_ctx)
5022 {
5023         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5024         struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5025         struct mlx5_flow_dv_modify_hdr_resource *resource =
5026                         container_of(entry, typeof(*resource), entry);
5027         uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
5028
5029         key_len += ref->actions_num * sizeof(ref->actions[0]);
5030         return ref->actions_num != resource->actions_num ||
5031                memcmp(&ref->ft_type, &resource->ft_type, key_len);
5032 }
5033
5034 struct mlx5_hlist_entry *
5035 flow_dv_modify_create_cb(struct mlx5_hlist *list, uint64_t key __rte_unused,
5036                          void *cb_ctx)
5037 {
5038         struct mlx5_dev_ctx_shared *sh = list->ctx;
5039         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5040         struct mlx5dv_dr_domain *ns;
5041         struct mlx5_flow_dv_modify_hdr_resource *entry;
5042         struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5043         int ret;
5044         uint32_t data_len = ref->actions_num * sizeof(ref->actions[0]);
5045         uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
5046
5047         entry = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*entry) + data_len, 0,
5048                             SOCKET_ID_ANY);
5049         if (!entry) {
5050                 rte_flow_error_set(ctx->error, ENOMEM,
5051                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5052                                    "cannot allocate resource memory");
5053                 return NULL;
5054         }
5055         rte_memcpy(&entry->ft_type,
5056                    RTE_PTR_ADD(ref, offsetof(typeof(*ref), ft_type)),
5057                    key_len + data_len);
5058         if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
5059                 ns = sh->fdb_domain;
5060         else if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
5061                 ns = sh->tx_domain;
5062         else
5063                 ns = sh->rx_domain;
5064         ret = mlx5_flow_os_create_flow_action_modify_header
5065                                         (sh->ctx, ns, entry,
5066                                          data_len, &entry->action);
5067         if (ret) {
5068                 mlx5_free(entry);
5069                 rte_flow_error_set(ctx->error, ENOMEM,
5070                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5071                                    NULL, "cannot create modification action");
5072                 return NULL;
5073         }
5074         return &entry->entry;
5075 }
5076
5077 /**
5078  * Validate the sample action.
5079  *
5080  * @param[in, out] action_flags
5081  *   Holds the actions detected until now.
5082  * @param[in] action
5083  *   Pointer to the sample action.
5084  * @param[in] dev
5085  *   Pointer to the Ethernet device structure.
5086  * @param[in] attr
5087  *   Attributes of flow that includes this action.
5088  * @param[in] item_flags
5089  *   Holds the items detected.
5090  * @param[in] rss
5091  *   Pointer to the RSS action.
5092  * @param[out] sample_rss
5093  *   Pointer to the RSS action in sample action list.
5094  * @param[out] count
5095  *   Pointer to the COUNT action in sample action list.
5096  * @param[out] fdb_mirror_limit
5097  *   Pointer to the FDB mirror limitation flag.
5098  * @param[out] error
5099  *   Pointer to error structure.
5100  *
5101  * @return
5102  *   0 on success, a negative errno value otherwise and rte_errno is set.
5103  */
5104 static int
5105 flow_dv_validate_action_sample(uint64_t *action_flags,
5106                                const struct rte_flow_action *action,
5107                                struct rte_eth_dev *dev,
5108                                const struct rte_flow_attr *attr,
5109                                uint64_t item_flags,
5110                                const struct rte_flow_action_rss *rss,
5111                                const struct rte_flow_action_rss **sample_rss,
5112                                const struct rte_flow_action_count **count,
5113                                int *fdb_mirror_limit,
5114                                struct rte_flow_error *error)
5115 {
5116         struct mlx5_priv *priv = dev->data->dev_private;
5117         struct mlx5_dev_config *dev_conf = &priv->config;
5118         const struct rte_flow_action_sample *sample = action->conf;
5119         const struct rte_flow_action *act;
5120         uint64_t sub_action_flags = 0;
5121         uint16_t queue_index = 0xFFFF;
5122         int actions_n = 0;
5123         int ret;
5124
5125         if (!sample)
5126                 return rte_flow_error_set(error, EINVAL,
5127                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
5128                                           "configuration cannot be NULL");
5129         if (sample->ratio == 0)
5130                 return rte_flow_error_set(error, EINVAL,
5131                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
5132                                           "ratio value starts from 1");
5133         if (!priv->config.devx || (sample->ratio > 0 && !priv->sampler_en))
5134                 return rte_flow_error_set(error, ENOTSUP,
5135                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5136                                           NULL,
5137                                           "sample action not supported");
5138         if (*action_flags & MLX5_FLOW_ACTION_SAMPLE)
5139                 return rte_flow_error_set(error, EINVAL,
5140                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5141                                           "Multiple sample actions not "
5142                                           "supported");
5143         if (*action_flags & MLX5_FLOW_ACTION_METER)
5144                 return rte_flow_error_set(error, EINVAL,
5145                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
5146                                           "wrong action order, meter should "
5147                                           "be after sample action");
5148         if (*action_flags & MLX5_FLOW_ACTION_JUMP)
5149                 return rte_flow_error_set(error, EINVAL,
5150                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
5151                                           "wrong action order, jump should "
5152                                           "be after sample action");
5153         act = sample->actions;
5154         for (; act->type != RTE_FLOW_ACTION_TYPE_END; act++) {
5155                 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
5156                         return rte_flow_error_set(error, ENOTSUP,
5157                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5158                                                   act, "too many actions");
5159                 switch (act->type) {
5160                 case RTE_FLOW_ACTION_TYPE_QUEUE:
5161                         ret = mlx5_flow_validate_action_queue(act,
5162                                                               sub_action_flags,
5163                                                               dev,
5164                                                               attr, error);
5165                         if (ret < 0)
5166                                 return ret;
5167                         queue_index = ((const struct rte_flow_action_queue *)
5168                                                         (act->conf))->index;
5169                         sub_action_flags |= MLX5_FLOW_ACTION_QUEUE;
5170                         ++actions_n;
5171                         break;
5172                 case RTE_FLOW_ACTION_TYPE_RSS:
5173                         *sample_rss = act->conf;
5174                         ret = mlx5_flow_validate_action_rss(act,
5175                                                             sub_action_flags,
5176                                                             dev, attr,
5177                                                             item_flags,
5178                                                             error);
5179                         if (ret < 0)
5180                                 return ret;
5181                         if (rss && *sample_rss &&
5182                             ((*sample_rss)->level != rss->level ||
5183                             (*sample_rss)->types != rss->types))
5184                                 return rte_flow_error_set(error, ENOTSUP,
5185                                         RTE_FLOW_ERROR_TYPE_ACTION,
5186                                         NULL,
5187                                         "Can't use the different RSS types "
5188                                         "or level in the same flow");
5189                         if (*sample_rss != NULL && (*sample_rss)->queue_num)
5190                                 queue_index = (*sample_rss)->queue[0];
5191                         sub_action_flags |= MLX5_FLOW_ACTION_RSS;
5192                         ++actions_n;
5193                         break;
5194                 case RTE_FLOW_ACTION_TYPE_MARK:
5195                         ret = flow_dv_validate_action_mark(dev, act,
5196                                                            sub_action_flags,
5197                                                            attr, error);
5198                         if (ret < 0)
5199                                 return ret;
5200                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY)
5201                                 sub_action_flags |= MLX5_FLOW_ACTION_MARK |
5202                                                 MLX5_FLOW_ACTION_MARK_EXT;
5203                         else
5204                                 sub_action_flags |= MLX5_FLOW_ACTION_MARK;
5205                         ++actions_n;
5206                         break;
5207                 case RTE_FLOW_ACTION_TYPE_COUNT:
5208                         ret = flow_dv_validate_action_count
5209                                 (dev, act,
5210                                  *action_flags | sub_action_flags,
5211                                  error);
5212                         if (ret < 0)
5213                                 return ret;
5214                         *count = act->conf;
5215                         sub_action_flags |= MLX5_FLOW_ACTION_COUNT;
5216                         *action_flags |= MLX5_FLOW_ACTION_COUNT;
5217                         ++actions_n;
5218                         break;
5219                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5220                         ret = flow_dv_validate_action_port_id(dev,
5221                                                               sub_action_flags,
5222                                                               act,
5223                                                               attr,
5224                                                               error);
5225                         if (ret)
5226                                 return ret;
5227                         sub_action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5228                         ++actions_n;
5229                         break;
5230                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5231                         ret = flow_dv_validate_action_raw_encap_decap
5232                                 (dev, NULL, act->conf, attr, &sub_action_flags,
5233                                  &actions_n, action, item_flags, error);
5234                         if (ret < 0)
5235                                 return ret;
5236                         ++actions_n;
5237                         break;
5238                 default:
5239                         return rte_flow_error_set(error, ENOTSUP,
5240                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5241                                                   NULL,
5242                                                   "Doesn't support optional "
5243                                                   "action");
5244                 }
5245         }
5246         if (attr->ingress && !attr->transfer) {
5247                 if (!(sub_action_flags & (MLX5_FLOW_ACTION_QUEUE |
5248                                           MLX5_FLOW_ACTION_RSS)))
5249                         return rte_flow_error_set(error, EINVAL,
5250                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5251                                                   NULL,
5252                                                   "Ingress must has a dest "
5253                                                   "QUEUE for Sample");
5254         } else if (attr->egress && !attr->transfer) {
5255                 return rte_flow_error_set(error, ENOTSUP,
5256                                           RTE_FLOW_ERROR_TYPE_ACTION,
5257                                           NULL,
5258                                           "Sample Only support Ingress "
5259                                           "or E-Switch");
5260         } else if (sample->actions->type != RTE_FLOW_ACTION_TYPE_END) {
5261                 MLX5_ASSERT(attr->transfer);
5262                 if (sample->ratio > 1)
5263                         return rte_flow_error_set(error, ENOTSUP,
5264                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5265                                                   NULL,
5266                                                   "E-Switch doesn't support "
5267                                                   "any optional action "
5268                                                   "for sampling");
5269                 if (sub_action_flags & MLX5_FLOW_ACTION_QUEUE)
5270                         return rte_flow_error_set(error, ENOTSUP,
5271                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5272                                                   NULL,
5273                                                   "unsupported action QUEUE");
5274                 if (sub_action_flags & MLX5_FLOW_ACTION_RSS)
5275                         return rte_flow_error_set(error, ENOTSUP,
5276                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5277                                                   NULL,
5278                                                   "unsupported action QUEUE");
5279                 if (!(sub_action_flags & MLX5_FLOW_ACTION_PORT_ID))
5280                         return rte_flow_error_set(error, EINVAL,
5281                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5282                                                   NULL,
5283                                                   "E-Switch must has a dest "
5284                                                   "port for mirroring");
5285                 if (!priv->config.hca_attr.reg_c_preserve &&
5286                      priv->representor_id != -1)
5287                         *fdb_mirror_limit = 1;
5288         }
5289         /* Continue validation for Xcap actions.*/
5290         if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) &&
5291             (queue_index == 0xFFFF ||
5292              mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
5293                 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
5294                      MLX5_FLOW_XCAP_ACTIONS)
5295                         return rte_flow_error_set(error, ENOTSUP,
5296                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5297                                                   NULL, "encap and decap "
5298                                                   "combination aren't "
5299                                                   "supported");
5300                 if (!attr->transfer && attr->ingress && (sub_action_flags &
5301                                                         MLX5_FLOW_ACTION_ENCAP))
5302                         return rte_flow_error_set(error, ENOTSUP,
5303                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5304                                                   NULL, "encap is not supported"
5305                                                   " for ingress traffic");
5306         }
5307         return 0;
5308 }
5309
5310 /**
5311  * Find existing modify-header resource or create and register a new one.
5312  *
5313  * @param dev[in, out]
5314  *   Pointer to rte_eth_dev structure.
5315  * @param[in, out] resource
5316  *   Pointer to modify-header resource.
5317  * @parm[in, out] dev_flow
5318  *   Pointer to the dev_flow.
5319  * @param[out] error
5320  *   pointer to error structure.
5321  *
5322  * @return
5323  *   0 on success otherwise -errno and errno is set.
5324  */
5325 static int
5326 flow_dv_modify_hdr_resource_register
5327                         (struct rte_eth_dev *dev,
5328                          struct mlx5_flow_dv_modify_hdr_resource *resource,
5329                          struct mlx5_flow *dev_flow,
5330                          struct rte_flow_error *error)
5331 {
5332         struct mlx5_priv *priv = dev->data->dev_private;
5333         struct mlx5_dev_ctx_shared *sh = priv->sh;
5334         uint32_t key_len = sizeof(*resource) -
5335                            offsetof(typeof(*resource), ft_type) +
5336                            resource->actions_num * sizeof(resource->actions[0]);
5337         struct mlx5_hlist_entry *entry;
5338         struct mlx5_flow_cb_ctx ctx = {
5339                 .error = error,
5340                 .data = resource,
5341         };
5342         uint64_t key64;
5343
5344         resource->flags = dev_flow->dv.group ? 0 :
5345                           MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
5346         if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
5347                                     resource->flags))
5348                 return rte_flow_error_set(error, EOVERFLOW,
5349                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5350                                           "too many modify header items");
5351         key64 = __rte_raw_cksum(&resource->ft_type, key_len, 0);
5352         entry = mlx5_hlist_register(sh->modify_cmds, key64, &ctx);
5353         if (!entry)
5354                 return -rte_errno;
5355         resource = container_of(entry, typeof(*resource), entry);
5356         dev_flow->handle->dvh.modify_hdr = resource;
5357         return 0;
5358 }
5359
5360 /**
5361  * Get DV flow counter by index.
5362  *
5363  * @param[in] dev
5364  *   Pointer to the Ethernet device structure.
5365  * @param[in] idx
5366  *   mlx5 flow counter index in the container.
5367  * @param[out] ppool
5368  *   mlx5 flow counter pool in the container,
5369  *
5370  * @return
5371  *   Pointer to the counter, NULL otherwise.
5372  */
5373 static struct mlx5_flow_counter *
5374 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
5375                            uint32_t idx,
5376                            struct mlx5_flow_counter_pool **ppool)
5377 {
5378         struct mlx5_priv *priv = dev->data->dev_private;
5379         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5380         struct mlx5_flow_counter_pool *pool;
5381
5382         /* Decrease to original index and clear shared bit. */
5383         idx = (idx - 1) & (MLX5_CNT_SHARED_OFFSET - 1);
5384         MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cmng->n);
5385         pool = cmng->pools[idx / MLX5_COUNTERS_PER_POOL];
5386         MLX5_ASSERT(pool);
5387         if (ppool)
5388                 *ppool = pool;
5389         return MLX5_POOL_GET_CNT(pool, idx % MLX5_COUNTERS_PER_POOL);
5390 }
5391
5392 /**
5393  * Check the devx counter belongs to the pool.
5394  *
5395  * @param[in] pool
5396  *   Pointer to the counter pool.
5397  * @param[in] id
5398  *   The counter devx ID.
5399  *
5400  * @return
5401  *   True if counter belongs to the pool, false otherwise.
5402  */
5403 static bool
5404 flow_dv_is_counter_in_pool(struct mlx5_flow_counter_pool *pool, int id)
5405 {
5406         int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
5407                    MLX5_COUNTERS_PER_POOL;
5408
5409         if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
5410                 return true;
5411         return false;
5412 }
5413
5414 /**
5415  * Get a pool by devx counter ID.
5416  *
5417  * @param[in] cmng
5418  *   Pointer to the counter management.
5419  * @param[in] id
5420  *   The counter devx ID.
5421  *
5422  * @return
5423  *   The counter pool pointer if exists, NULL otherwise,
5424  */
5425 static struct mlx5_flow_counter_pool *
5426 flow_dv_find_pool_by_id(struct mlx5_flow_counter_mng *cmng, int id)
5427 {
5428         uint32_t i;
5429         struct mlx5_flow_counter_pool *pool = NULL;
5430
5431         rte_spinlock_lock(&cmng->pool_update_sl);
5432         /* Check last used pool. */
5433         if (cmng->last_pool_idx != POOL_IDX_INVALID &&
5434             flow_dv_is_counter_in_pool(cmng->pools[cmng->last_pool_idx], id)) {
5435                 pool = cmng->pools[cmng->last_pool_idx];
5436                 goto out;
5437         }
5438         /* ID out of range means no suitable pool in the container. */
5439         if (id > cmng->max_id || id < cmng->min_id)
5440                 goto out;
5441         /*
5442          * Find the pool from the end of the container, since mostly counter
5443          * ID is sequence increasing, and the last pool should be the needed
5444          * one.
5445          */
5446         i = cmng->n_valid;
5447         while (i--) {
5448                 struct mlx5_flow_counter_pool *pool_tmp = cmng->pools[i];
5449
5450                 if (flow_dv_is_counter_in_pool(pool_tmp, id)) {
5451                         pool = pool_tmp;
5452                         break;
5453                 }
5454         }
5455 out:
5456         rte_spinlock_unlock(&cmng->pool_update_sl);
5457         return pool;
5458 }
5459
5460 /**
5461  * Resize a counter container.
5462  *
5463  * @param[in] dev
5464  *   Pointer to the Ethernet device structure.
5465  *
5466  * @return
5467  *   0 on success, otherwise negative errno value and rte_errno is set.
5468  */
5469 static int
5470 flow_dv_container_resize(struct rte_eth_dev *dev)
5471 {
5472         struct mlx5_priv *priv = dev->data->dev_private;
5473         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5474         void *old_pools = cmng->pools;
5475         uint32_t resize = cmng->n + MLX5_CNT_CONTAINER_RESIZE;
5476         uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
5477         void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
5478
5479         if (!pools) {
5480                 rte_errno = ENOMEM;
5481                 return -ENOMEM;
5482         }
5483         if (old_pools)
5484                 memcpy(pools, old_pools, cmng->n *
5485                                        sizeof(struct mlx5_flow_counter_pool *));
5486         cmng->n = resize;
5487         cmng->pools = pools;
5488         if (old_pools)
5489                 mlx5_free(old_pools);
5490         return 0;
5491 }
5492
5493 /**
5494  * Query a devx flow counter.
5495  *
5496  * @param[in] dev
5497  *   Pointer to the Ethernet device structure.
5498  * @param[in] cnt
5499  *   Index to the flow counter.
5500  * @param[out] pkts
5501  *   The statistics value of packets.
5502  * @param[out] bytes
5503  *   The statistics value of bytes.
5504  *
5505  * @return
5506  *   0 on success, otherwise a negative errno value and rte_errno is set.
5507  */
5508 static inline int
5509 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
5510                      uint64_t *bytes)
5511 {
5512         struct mlx5_priv *priv = dev->data->dev_private;
5513         struct mlx5_flow_counter_pool *pool = NULL;
5514         struct mlx5_flow_counter *cnt;
5515         int offset;
5516
5517         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
5518         MLX5_ASSERT(pool);
5519         if (priv->sh->cmng.counter_fallback)
5520                 return mlx5_devx_cmd_flow_counter_query(cnt->dcs_when_active, 0,
5521                                         0, pkts, bytes, 0, NULL, NULL, 0);
5522         rte_spinlock_lock(&pool->sl);
5523         if (!pool->raw) {
5524                 *pkts = 0;
5525                 *bytes = 0;
5526         } else {
5527                 offset = MLX5_CNT_ARRAY_IDX(pool, cnt);
5528                 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
5529                 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
5530         }
5531         rte_spinlock_unlock(&pool->sl);
5532         return 0;
5533 }
5534
5535 /**
5536  * Create and initialize a new counter pool.
5537  *
5538  * @param[in] dev
5539  *   Pointer to the Ethernet device structure.
5540  * @param[out] dcs
5541  *   The devX counter handle.
5542  * @param[in] age
5543  *   Whether the pool is for counter that was allocated for aging.
5544  * @param[in/out] cont_cur
5545  *   Pointer to the container pointer, it will be update in pool resize.
5546  *
5547  * @return
5548  *   The pool container pointer on success, NULL otherwise and rte_errno is set.
5549  */
5550 static struct mlx5_flow_counter_pool *
5551 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
5552                     uint32_t age)
5553 {
5554         struct mlx5_priv *priv = dev->data->dev_private;
5555         struct mlx5_flow_counter_pool *pool;
5556         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5557         bool fallback = priv->sh->cmng.counter_fallback;
5558         uint32_t size = sizeof(*pool);
5559
5560         size += MLX5_COUNTERS_PER_POOL * MLX5_CNT_SIZE;
5561         size += (!age ? 0 : MLX5_COUNTERS_PER_POOL * MLX5_AGE_SIZE);
5562         pool = mlx5_malloc(MLX5_MEM_ZERO, size, 0, SOCKET_ID_ANY);
5563         if (!pool) {
5564                 rte_errno = ENOMEM;
5565                 return NULL;
5566         }
5567         pool->raw = NULL;
5568         pool->is_aged = !!age;
5569         pool->query_gen = 0;
5570         pool->min_dcs = dcs;
5571         rte_spinlock_init(&pool->sl);
5572         rte_spinlock_init(&pool->csl);
5573         TAILQ_INIT(&pool->counters[0]);
5574         TAILQ_INIT(&pool->counters[1]);
5575         pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
5576         rte_spinlock_lock(&cmng->pool_update_sl);
5577         pool->index = cmng->n_valid;
5578         if (pool->index == cmng->n && flow_dv_container_resize(dev)) {
5579                 mlx5_free(pool);
5580                 rte_spinlock_unlock(&cmng->pool_update_sl);
5581                 return NULL;
5582         }
5583         cmng->pools[pool->index] = pool;
5584         cmng->n_valid++;
5585         if (unlikely(fallback)) {
5586                 int base = RTE_ALIGN_FLOOR(dcs->id, MLX5_COUNTERS_PER_POOL);
5587
5588                 if (base < cmng->min_id)
5589                         cmng->min_id = base;
5590                 if (base > cmng->max_id)
5591                         cmng->max_id = base + MLX5_COUNTERS_PER_POOL - 1;
5592                 cmng->last_pool_idx = pool->index;
5593         }
5594         rte_spinlock_unlock(&cmng->pool_update_sl);
5595         return pool;
5596 }
5597
5598 /**
5599  * Prepare a new counter and/or a new counter pool.
5600  *
5601  * @param[in] dev
5602  *   Pointer to the Ethernet device structure.
5603  * @param[out] cnt_free
5604  *   Where to put the pointer of a new counter.
5605  * @param[in] age
5606  *   Whether the pool is for counter that was allocated for aging.
5607  *
5608  * @return
5609  *   The counter pool pointer and @p cnt_free is set on success,
5610  *   NULL otherwise and rte_errno is set.
5611  */
5612 static struct mlx5_flow_counter_pool *
5613 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
5614                              struct mlx5_flow_counter **cnt_free,
5615                              uint32_t age)
5616 {
5617         struct mlx5_priv *priv = dev->data->dev_private;
5618         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5619         struct mlx5_flow_counter_pool *pool;
5620         struct mlx5_counters tmp_tq;
5621         struct mlx5_devx_obj *dcs = NULL;
5622         struct mlx5_flow_counter *cnt;
5623         enum mlx5_counter_type cnt_type =
5624                         age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
5625         bool fallback = priv->sh->cmng.counter_fallback;
5626         uint32_t i;
5627
5628         if (fallback) {
5629                 /* bulk_bitmap must be 0 for single counter allocation. */
5630                 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
5631                 if (!dcs)
5632                         return NULL;
5633                 pool = flow_dv_find_pool_by_id(cmng, dcs->id);
5634                 if (!pool) {
5635                         pool = flow_dv_pool_create(dev, dcs, age);
5636                         if (!pool) {
5637                                 mlx5_devx_cmd_destroy(dcs);
5638                                 return NULL;
5639                         }
5640                 }
5641                 i = dcs->id % MLX5_COUNTERS_PER_POOL;
5642                 cnt = MLX5_POOL_GET_CNT(pool, i);
5643                 cnt->pool = pool;
5644                 cnt->dcs_when_free = dcs;
5645                 *cnt_free = cnt;
5646                 return pool;
5647         }
5648         dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
5649         if (!dcs) {
5650                 rte_errno = ENODATA;
5651                 return NULL;
5652         }
5653         pool = flow_dv_pool_create(dev, dcs, age);
5654         if (!pool) {
5655                 mlx5_devx_cmd_destroy(dcs);
5656                 return NULL;
5657         }
5658         TAILQ_INIT(&tmp_tq);
5659         for (i = 1; i < MLX5_COUNTERS_PER_POOL; ++i) {
5660                 cnt = MLX5_POOL_GET_CNT(pool, i);
5661                 cnt->pool = pool;
5662                 TAILQ_INSERT_HEAD(&tmp_tq, cnt, next);
5663         }
5664         rte_spinlock_lock(&cmng->csl[cnt_type]);
5665         TAILQ_CONCAT(&cmng->counters[cnt_type], &tmp_tq, next);
5666         rte_spinlock_unlock(&cmng->csl[cnt_type]);
5667         *cnt_free = MLX5_POOL_GET_CNT(pool, 0);
5668         (*cnt_free)->pool = pool;
5669         return pool;
5670 }
5671
5672 /**
5673  * Allocate a flow counter.
5674  *
5675  * @param[in] dev
5676  *   Pointer to the Ethernet device structure.
5677  * @param[in] age
5678  *   Whether the counter was allocated for aging.
5679  *
5680  * @return
5681  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
5682  */
5683 static uint32_t
5684 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t age)
5685 {
5686         struct mlx5_priv *priv = dev->data->dev_private;
5687         struct mlx5_flow_counter_pool *pool = NULL;
5688         struct mlx5_flow_counter *cnt_free = NULL;
5689         bool fallback = priv->sh->cmng.counter_fallback;
5690         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5691         enum mlx5_counter_type cnt_type =
5692                         age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
5693         uint32_t cnt_idx;
5694
5695         if (!priv->config.devx) {
5696                 rte_errno = ENOTSUP;
5697                 return 0;
5698         }
5699         /* Get free counters from container. */
5700         rte_spinlock_lock(&cmng->csl[cnt_type]);
5701         cnt_free = TAILQ_FIRST(&cmng->counters[cnt_type]);
5702         if (cnt_free)
5703                 TAILQ_REMOVE(&cmng->counters[cnt_type], cnt_free, next);
5704         rte_spinlock_unlock(&cmng->csl[cnt_type]);
5705         if (!cnt_free && !flow_dv_counter_pool_prepare(dev, &cnt_free, age))
5706                 goto err;
5707         pool = cnt_free->pool;
5708         if (fallback)
5709                 cnt_free->dcs_when_active = cnt_free->dcs_when_free;
5710         /* Create a DV counter action only in the first time usage. */
5711         if (!cnt_free->action) {
5712                 uint16_t offset;
5713                 struct mlx5_devx_obj *dcs;
5714                 int ret;
5715
5716                 if (!fallback) {
5717                         offset = MLX5_CNT_ARRAY_IDX(pool, cnt_free);
5718                         dcs = pool->min_dcs;
5719                 } else {
5720                         offset = 0;
5721                         dcs = cnt_free->dcs_when_free;
5722                 }
5723                 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, offset,
5724                                                             &cnt_free->action);
5725                 if (ret) {
5726                         rte_errno = errno;
5727                         goto err;
5728                 }
5729         }
5730         cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
5731                                 MLX5_CNT_ARRAY_IDX(pool, cnt_free));
5732         /* Update the counter reset values. */
5733         if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
5734                                  &cnt_free->bytes))
5735                 goto err;
5736         if (!fallback && !priv->sh->cmng.query_thread_on)
5737                 /* Start the asynchronous batch query by the host thread. */
5738                 mlx5_set_query_alarm(priv->sh);
5739         return cnt_idx;
5740 err:
5741         if (cnt_free) {
5742                 cnt_free->pool = pool;
5743                 if (fallback)
5744                         cnt_free->dcs_when_free = cnt_free->dcs_when_active;
5745                 rte_spinlock_lock(&cmng->csl[cnt_type]);
5746                 TAILQ_INSERT_TAIL(&cmng->counters[cnt_type], cnt_free, next);
5747                 rte_spinlock_unlock(&cmng->csl[cnt_type]);
5748         }
5749         return 0;
5750 }
5751
5752 /**
5753  * Allocate a shared flow counter.
5754  *
5755  * @param[in] ctx
5756  *   Pointer to the shared counter configuration.
5757  * @param[in] data
5758  *   Pointer to save the allocated counter index.
5759  *
5760  * @return
5761  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
5762  */
5763
5764 static int32_t
5765 flow_dv_counter_alloc_shared_cb(void *ctx, union mlx5_l3t_data *data)
5766 {
5767         struct mlx5_shared_counter_conf *conf = ctx;
5768         struct rte_eth_dev *dev = conf->dev;
5769         struct mlx5_flow_counter *cnt;
5770
5771         data->dword = flow_dv_counter_alloc(dev, 0);
5772         data->dword |= MLX5_CNT_SHARED_OFFSET;
5773         cnt = flow_dv_counter_get_by_idx(dev, data->dword, NULL);
5774         cnt->shared_info.id = conf->id;
5775         return 0;
5776 }
5777
5778 /**
5779  * Get a shared flow counter.
5780  *
5781  * @param[in] dev
5782  *   Pointer to the Ethernet device structure.
5783  * @param[in] id
5784  *   Counter identifier.
5785  *
5786  * @return
5787  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
5788  */
5789 static uint32_t
5790 flow_dv_counter_get_shared(struct rte_eth_dev *dev, uint32_t id)
5791 {
5792         struct mlx5_priv *priv = dev->data->dev_private;
5793         struct mlx5_shared_counter_conf conf = {
5794                 .dev = dev,
5795                 .id = id,
5796         };
5797         union mlx5_l3t_data data = {
5798                 .dword = 0,
5799         };
5800
5801         mlx5_l3t_prepare_entry(priv->sh->cnt_id_tbl, id, &data,
5802                                flow_dv_counter_alloc_shared_cb, &conf);
5803         return data.dword;
5804 }
5805
5806 /**
5807  * Get age param from counter index.
5808  *
5809  * @param[in] dev
5810  *   Pointer to the Ethernet device structure.
5811  * @param[in] counter
5812  *   Index to the counter handler.
5813  *
5814  * @return
5815  *   The aging parameter specified for the counter index.
5816  */
5817 static struct mlx5_age_param*
5818 flow_dv_counter_idx_get_age(struct rte_eth_dev *dev,
5819                                 uint32_t counter)
5820 {
5821         struct mlx5_flow_counter *cnt;
5822         struct mlx5_flow_counter_pool *pool = NULL;
5823
5824         flow_dv_counter_get_by_idx(dev, counter, &pool);
5825         counter = (counter - 1) % MLX5_COUNTERS_PER_POOL;
5826         cnt = MLX5_POOL_GET_CNT(pool, counter);
5827         return MLX5_CNT_TO_AGE(cnt);
5828 }
5829
5830 /**
5831  * Remove a flow counter from aged counter list.
5832  *
5833  * @param[in] dev
5834  *   Pointer to the Ethernet device structure.
5835  * @param[in] counter
5836  *   Index to the counter handler.
5837  * @param[in] cnt
5838  *   Pointer to the counter handler.
5839  */
5840 static void
5841 flow_dv_counter_remove_from_age(struct rte_eth_dev *dev,
5842                                 uint32_t counter, struct mlx5_flow_counter *cnt)
5843 {
5844         struct mlx5_age_info *age_info;
5845         struct mlx5_age_param *age_param;
5846         struct mlx5_priv *priv = dev->data->dev_private;
5847         uint16_t expected = AGE_CANDIDATE;
5848
5849         age_info = GET_PORT_AGE_INFO(priv);
5850         age_param = flow_dv_counter_idx_get_age(dev, counter);
5851         if (!__atomic_compare_exchange_n(&age_param->state, &expected,
5852                                          AGE_FREE, false, __ATOMIC_RELAXED,
5853                                          __ATOMIC_RELAXED)) {
5854                 /**
5855                  * We need the lock even it is age timeout,
5856                  * since counter may still in process.
5857                  */
5858                 rte_spinlock_lock(&age_info->aged_sl);
5859                 TAILQ_REMOVE(&age_info->aged_counters, cnt, next);
5860                 rte_spinlock_unlock(&age_info->aged_sl);
5861                 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
5862         }
5863 }
5864
5865 /**
5866  * Release a flow counter.
5867  *
5868  * @param[in] dev
5869  *   Pointer to the Ethernet device structure.
5870  * @param[in] counter
5871  *   Index to the counter handler.
5872  */
5873 static void
5874 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t counter)
5875 {
5876         struct mlx5_priv *priv = dev->data->dev_private;
5877         struct mlx5_flow_counter_pool *pool = NULL;
5878         struct mlx5_flow_counter *cnt;
5879         enum mlx5_counter_type cnt_type;
5880
5881         if (!counter)
5882                 return;
5883         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
5884         MLX5_ASSERT(pool);
5885         if (IS_SHARED_CNT(counter) &&
5886             mlx5_l3t_clear_entry(priv->sh->cnt_id_tbl, cnt->shared_info.id))
5887                 return;
5888         if (pool->is_aged)
5889                 flow_dv_counter_remove_from_age(dev, counter, cnt);
5890         cnt->pool = pool;
5891         /*
5892          * Put the counter back to list to be updated in none fallback mode.
5893          * Currently, we are using two list alternately, while one is in query,
5894          * add the freed counter to the other list based on the pool query_gen
5895          * value. After query finishes, add counter the list to the global
5896          * container counter list. The list changes while query starts. In
5897          * this case, lock will not be needed as query callback and release
5898          * function both operate with the different list.
5899          *
5900          */
5901         if (!priv->sh->cmng.counter_fallback) {
5902                 rte_spinlock_lock(&pool->csl);
5903                 TAILQ_INSERT_TAIL(&pool->counters[pool->query_gen], cnt, next);
5904                 rte_spinlock_unlock(&pool->csl);
5905         } else {
5906                 cnt->dcs_when_free = cnt->dcs_when_active;
5907                 cnt_type = pool->is_aged ? MLX5_COUNTER_TYPE_AGE :
5908                                            MLX5_COUNTER_TYPE_ORIGIN;
5909                 rte_spinlock_lock(&priv->sh->cmng.csl[cnt_type]);
5910                 TAILQ_INSERT_TAIL(&priv->sh->cmng.counters[cnt_type],
5911                                   cnt, next);
5912                 rte_spinlock_unlock(&priv->sh->cmng.csl[cnt_type]);
5913         }
5914 }
5915
5916 /**
5917  * Verify the @p attributes will be correctly understood by the NIC and store
5918  * them in the @p flow if everything is correct.
5919  *
5920  * @param[in] dev
5921  *   Pointer to dev struct.
5922  * @param[in] attributes
5923  *   Pointer to flow attributes
5924  * @param[in] external
5925  *   This flow rule is created by request external to PMD.
5926  * @param[out] error
5927  *   Pointer to error structure.
5928  *
5929  * @return
5930  *   - 0 on success and non root table.
5931  *   - 1 on success and root table.
5932  *   - a negative errno value otherwise and rte_errno is set.
5933  */
5934 static int
5935 flow_dv_validate_attributes(struct rte_eth_dev *dev,
5936                             const struct mlx5_flow_tunnel *tunnel,
5937                             const struct rte_flow_attr *attributes,
5938                             const struct flow_grp_info *grp_info,
5939                             struct rte_flow_error *error)
5940 {
5941         struct mlx5_priv *priv = dev->data->dev_private;
5942         uint32_t lowest_priority = mlx5_get_lowest_priority(dev, attributes);
5943         int ret = 0;
5944
5945 #ifndef HAVE_MLX5DV_DR
5946         RTE_SET_USED(tunnel);
5947         RTE_SET_USED(grp_info);
5948         if (attributes->group)
5949                 return rte_flow_error_set(error, ENOTSUP,
5950                                           RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
5951                                           NULL,
5952                                           "groups are not supported");
5953 #else
5954         uint32_t table = 0;
5955
5956         ret = mlx5_flow_group_to_table(dev, tunnel, attributes->group, &table,
5957                                        grp_info, error);
5958         if (ret)
5959                 return ret;
5960         if (!table)
5961                 ret = MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
5962 #endif
5963         if (attributes->priority != MLX5_FLOW_LOWEST_PRIO_INDICATOR &&
5964             attributes->priority > lowest_priority)
5965                 return rte_flow_error_set(error, ENOTSUP,
5966                                           RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
5967                                           NULL,
5968                                           "priority out of range");
5969         if (attributes->transfer) {
5970                 if (!priv->config.dv_esw_en)
5971                         return rte_flow_error_set
5972                                 (error, ENOTSUP,
5973                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5974                                  "E-Switch dr is not supported");
5975                 if (!(priv->representor || priv->master))
5976                         return rte_flow_error_set
5977                                 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5978                                  NULL, "E-Switch configuration can only be"
5979                                  " done by a master or a representor device");
5980                 if (attributes->egress)
5981                         return rte_flow_error_set
5982                                 (error, ENOTSUP,
5983                                  RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
5984                                  "egress is not supported");
5985         }
5986         if (!(attributes->egress ^ attributes->ingress))
5987                 return rte_flow_error_set(error, ENOTSUP,
5988                                           RTE_FLOW_ERROR_TYPE_ATTR, NULL,
5989                                           "must specify exactly one of "
5990                                           "ingress or egress");
5991         return ret;
5992 }
5993
5994 /**
5995  * Internal validation function. For validating both actions and items.
5996  *
5997  * @param[in] dev
5998  *   Pointer to the rte_eth_dev structure.
5999  * @param[in] attr
6000  *   Pointer to the flow attributes.
6001  * @param[in] items
6002  *   Pointer to the list of items.
6003  * @param[in] actions
6004  *   Pointer to the list of actions.
6005  * @param[in] external
6006  *   This flow rule is created by request external to PMD.
6007  * @param[in] hairpin
6008  *   Number of hairpin TX actions, 0 means classic flow.
6009  * @param[out] error
6010  *   Pointer to the error structure.
6011  *
6012  * @return
6013  *   0 on success, a negative errno value otherwise and rte_errno is set.
6014  */
6015 static int
6016 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
6017                  const struct rte_flow_item items[],
6018                  const struct rte_flow_action actions[],
6019                  bool external, int hairpin, struct rte_flow_error *error)
6020 {
6021         int ret;
6022         uint64_t action_flags = 0;
6023         uint64_t item_flags = 0;
6024         uint64_t last_item = 0;
6025         uint8_t next_protocol = 0xff;
6026         uint16_t ether_type = 0;
6027         int actions_n = 0;
6028         uint8_t item_ipv6_proto = 0;
6029         int fdb_mirror_limit = 0;
6030         int modify_after_mirror = 0;
6031         const struct rte_flow_item *geneve_item = NULL;
6032         const struct rte_flow_item *gre_item = NULL;
6033         const struct rte_flow_item *gtp_item = NULL;
6034         const struct rte_flow_action_raw_decap *decap;
6035         const struct rte_flow_action_raw_encap *encap;
6036         const struct rte_flow_action_rss *rss = NULL;
6037         const struct rte_flow_action_rss *sample_rss = NULL;
6038         const struct rte_flow_action_count *count = NULL;
6039         const struct rte_flow_action_count *sample_count = NULL;
6040         const struct rte_flow_item_tcp nic_tcp_mask = {
6041                 .hdr = {
6042                         .tcp_flags = 0xFF,
6043                         .src_port = RTE_BE16(UINT16_MAX),
6044                         .dst_port = RTE_BE16(UINT16_MAX),
6045                 }
6046         };
6047         const struct rte_flow_item_ipv6 nic_ipv6_mask = {
6048                 .hdr = {
6049                         .src_addr =
6050                         "\xff\xff\xff\xff\xff\xff\xff\xff"
6051                         "\xff\xff\xff\xff\xff\xff\xff\xff",
6052                         .dst_addr =
6053                         "\xff\xff\xff\xff\xff\xff\xff\xff"
6054                         "\xff\xff\xff\xff\xff\xff\xff\xff",
6055                         .vtc_flow = RTE_BE32(0xffffffff),
6056                         .proto = 0xff,
6057                         .hop_limits = 0xff,
6058                 },
6059                 .has_frag_ext = 1,
6060         };
6061         const struct rte_flow_item_ecpri nic_ecpri_mask = {
6062                 .hdr = {
6063                         .common = {
6064                                 .u32 =
6065                                 RTE_BE32(((const struct rte_ecpri_common_hdr) {
6066                                         .type = 0xFF,
6067                                         }).u32),
6068                         },
6069                         .dummy[0] = 0xffffffff,
6070                 },
6071         };
6072         struct mlx5_priv *priv = dev->data->dev_private;
6073         struct mlx5_dev_config *dev_conf = &priv->config;
6074         uint16_t queue_index = 0xFFFF;
6075         const struct rte_flow_item_vlan *vlan_m = NULL;
6076         uint32_t rw_act_num = 0;
6077         uint64_t is_root;
6078         const struct mlx5_flow_tunnel *tunnel;
6079         struct flow_grp_info grp_info = {
6080                 .external = !!external,
6081                 .transfer = !!attr->transfer,
6082                 .fdb_def_rule = !!priv->fdb_def_rule,
6083         };
6084         const struct rte_eth_hairpin_conf *conf;
6085
6086         if (items == NULL)
6087                 return -1;
6088         if (is_flow_tunnel_match_rule(dev, attr, items, actions)) {
6089                 tunnel = flow_items_to_tunnel(items);
6090                 action_flags |= MLX5_FLOW_ACTION_TUNNEL_MATCH |
6091                                 MLX5_FLOW_ACTION_DECAP;
6092         } else if (is_flow_tunnel_steer_rule(dev, attr, items, actions)) {
6093                 tunnel = flow_actions_to_tunnel(actions);
6094                 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
6095         } else {
6096                 tunnel = NULL;
6097         }
6098         if (tunnel && priv->representor)
6099                 return rte_flow_error_set(error, ENOTSUP,
6100                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6101                                           "decap not supported "
6102                                           "for VF representor");
6103         grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
6104                                 (dev, tunnel, attr, items, actions);
6105         ret = flow_dv_validate_attributes(dev, tunnel, attr, &grp_info, error);
6106         if (ret < 0)
6107                 return ret;
6108         is_root = (uint64_t)ret;
6109         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
6110                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
6111                 int type = items->type;
6112
6113                 if (!mlx5_flow_os_item_supported(type))
6114                         return rte_flow_error_set(error, ENOTSUP,
6115                                                   RTE_FLOW_ERROR_TYPE_ITEM,
6116                                                   NULL, "item not supported");
6117                 switch (type) {
6118                 case MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL:
6119                         if (items[0].type != (typeof(items[0].type))
6120                                                 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL)
6121                                 return rte_flow_error_set
6122                                                 (error, EINVAL,
6123                                                 RTE_FLOW_ERROR_TYPE_ITEM,
6124                                                 NULL, "MLX5 private items "
6125                                                 "must be the first");
6126                         break;
6127                 case RTE_FLOW_ITEM_TYPE_VOID:
6128                         break;
6129                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
6130                         ret = flow_dv_validate_item_port_id
6131                                         (dev, items, attr, item_flags, error);
6132                         if (ret < 0)
6133                                 return ret;
6134                         last_item = MLX5_FLOW_ITEM_PORT_ID;
6135                         break;
6136                 case RTE_FLOW_ITEM_TYPE_ETH:
6137                         ret = mlx5_flow_validate_item_eth(items, item_flags,
6138                                                           true, error);
6139                         if (ret < 0)
6140                                 return ret;
6141                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
6142                                              MLX5_FLOW_LAYER_OUTER_L2;
6143                         if (items->mask != NULL && items->spec != NULL) {
6144                                 ether_type =
6145                                         ((const struct rte_flow_item_eth *)
6146                                          items->spec)->type;
6147                                 ether_type &=
6148                                         ((const struct rte_flow_item_eth *)
6149                                          items->mask)->type;
6150                                 ether_type = rte_be_to_cpu_16(ether_type);
6151                         } else {
6152                                 ether_type = 0;
6153                         }
6154                         break;
6155                 case RTE_FLOW_ITEM_TYPE_VLAN:
6156                         ret = flow_dv_validate_item_vlan(items, item_flags,
6157                                                          dev, error);
6158                         if (ret < 0)
6159                                 return ret;
6160                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
6161                                              MLX5_FLOW_LAYER_OUTER_VLAN;
6162                         if (items->mask != NULL && items->spec != NULL) {
6163                                 ether_type =
6164                                         ((const struct rte_flow_item_vlan *)
6165                                          items->spec)->inner_type;
6166                                 ether_type &=
6167                                         ((const struct rte_flow_item_vlan *)
6168                                          items->mask)->inner_type;
6169                                 ether_type = rte_be_to_cpu_16(ether_type);
6170                         } else {
6171                                 ether_type = 0;
6172                         }
6173                         /* Store outer VLAN mask for of_push_vlan action. */
6174                         if (!tunnel)
6175                                 vlan_m = items->mask;
6176                         break;
6177                 case RTE_FLOW_ITEM_TYPE_IPV4:
6178                         mlx5_flow_tunnel_ip_check(items, next_protocol,
6179                                                   &item_flags, &tunnel);
6180                         ret = flow_dv_validate_item_ipv4(items, item_flags,
6181                                                          last_item, ether_type,
6182                                                          error);
6183                         if (ret < 0)
6184                                 return ret;
6185                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
6186                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
6187                         if (items->mask != NULL &&
6188                             ((const struct rte_flow_item_ipv4 *)
6189                              items->mask)->hdr.next_proto_id) {
6190                                 next_protocol =
6191                                         ((const struct rte_flow_item_ipv4 *)
6192                                          (items->spec))->hdr.next_proto_id;
6193                                 next_protocol &=
6194                                         ((const struct rte_flow_item_ipv4 *)
6195                                          (items->mask))->hdr.next_proto_id;
6196                         } else {
6197                                 /* Reset for inner layer. */
6198                                 next_protocol = 0xff;
6199                         }
6200                         break;
6201                 case RTE_FLOW_ITEM_TYPE_IPV6:
6202                         mlx5_flow_tunnel_ip_check(items, next_protocol,
6203                                                   &item_flags, &tunnel);
6204                         ret = mlx5_flow_validate_item_ipv6(items, item_flags,
6205                                                            last_item,
6206                                                            ether_type,
6207                                                            &nic_ipv6_mask,
6208                                                            error);
6209                         if (ret < 0)
6210                                 return ret;
6211                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
6212                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
6213                         if (items->mask != NULL &&
6214                             ((const struct rte_flow_item_ipv6 *)
6215                              items->mask)->hdr.proto) {
6216                                 item_ipv6_proto =
6217                                         ((const struct rte_flow_item_ipv6 *)
6218                                          items->spec)->hdr.proto;
6219                                 next_protocol =
6220                                         ((const struct rte_flow_item_ipv6 *)
6221                                          items->spec)->hdr.proto;
6222                                 next_protocol &=
6223                                         ((const struct rte_flow_item_ipv6 *)
6224                                          items->mask)->hdr.proto;
6225                         } else {
6226                                 /* Reset for inner layer. */
6227                                 next_protocol = 0xff;
6228                         }
6229                         break;
6230                 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
6231                         ret = flow_dv_validate_item_ipv6_frag_ext(items,
6232                                                                   item_flags,
6233                                                                   error);
6234                         if (ret < 0)
6235                                 return ret;
6236                         last_item = tunnel ?
6237                                         MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
6238                                         MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
6239                         if (items->mask != NULL &&
6240                             ((const struct rte_flow_item_ipv6_frag_ext *)
6241                              items->mask)->hdr.next_header) {
6242                                 next_protocol =
6243                                 ((const struct rte_flow_item_ipv6_frag_ext *)
6244                                  items->spec)->hdr.next_header;
6245                                 next_protocol &=
6246                                 ((const struct rte_flow_item_ipv6_frag_ext *)
6247                                  items->mask)->hdr.next_header;
6248                         } else {
6249                                 /* Reset for inner layer. */
6250                                 next_protocol = 0xff;
6251                         }
6252                         break;
6253                 case RTE_FLOW_ITEM_TYPE_TCP:
6254                         ret = mlx5_flow_validate_item_tcp
6255                                                 (items, item_flags,
6256                                                  next_protocol,
6257                                                  &nic_tcp_mask,
6258                                                  error);
6259                         if (ret < 0)
6260                                 return ret;
6261                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
6262                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
6263                         break;
6264                 case RTE_FLOW_ITEM_TYPE_UDP:
6265                         ret = mlx5_flow_validate_item_udp(items, item_flags,
6266                                                           next_protocol,
6267                                                           error);
6268                         if (ret < 0)
6269                                 return ret;
6270                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
6271                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
6272                         break;
6273                 case RTE_FLOW_ITEM_TYPE_GRE:
6274                         ret = mlx5_flow_validate_item_gre(items, item_flags,
6275                                                           next_protocol, error);
6276                         if (ret < 0)
6277                                 return ret;
6278                         gre_item = items;
6279                         last_item = MLX5_FLOW_LAYER_GRE;
6280                         break;
6281                 case RTE_FLOW_ITEM_TYPE_NVGRE:
6282                         ret = mlx5_flow_validate_item_nvgre(items, item_flags,
6283                                                             next_protocol,
6284                                                             error);
6285                         if (ret < 0)
6286                                 return ret;
6287                         last_item = MLX5_FLOW_LAYER_NVGRE;
6288                         break;
6289                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
6290                         ret = mlx5_flow_validate_item_gre_key
6291                                 (items, item_flags, gre_item, error);
6292                         if (ret < 0)
6293                                 return ret;
6294                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
6295                         break;
6296                 case RTE_FLOW_ITEM_TYPE_VXLAN:
6297                         ret = mlx5_flow_validate_item_vxlan(items, item_flags,
6298                                                             error);
6299                         if (ret < 0)
6300                                 return ret;
6301                         last_item = MLX5_FLOW_LAYER_VXLAN;
6302                         break;
6303                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
6304                         ret = mlx5_flow_validate_item_vxlan_gpe(items,
6305                                                                 item_flags, dev,
6306                                                                 error);
6307                         if (ret < 0)
6308                                 return ret;
6309                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
6310                         break;
6311                 case RTE_FLOW_ITEM_TYPE_GENEVE:
6312                         ret = mlx5_flow_validate_item_geneve(items,
6313                                                              item_flags, dev,
6314                                                              error);
6315                         if (ret < 0)
6316                                 return ret;
6317                         geneve_item = items;
6318                         last_item = MLX5_FLOW_LAYER_GENEVE;
6319                         break;
6320                 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
6321                         ret = mlx5_flow_validate_item_geneve_opt(items,
6322                                                                  last_item,
6323                                                                  geneve_item,
6324                                                                  dev,
6325                                                                  error);
6326                         if (ret < 0)
6327                                 return ret;
6328                         last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
6329                         break;
6330                 case RTE_FLOW_ITEM_TYPE_MPLS:
6331                         ret = mlx5_flow_validate_item_mpls(dev, items,
6332                                                            item_flags,
6333                                                            last_item, error);
6334                         if (ret < 0)
6335                                 return ret;
6336                         last_item = MLX5_FLOW_LAYER_MPLS;
6337                         break;
6338
6339                 case RTE_FLOW_ITEM_TYPE_MARK:
6340                         ret = flow_dv_validate_item_mark(dev, items, attr,
6341                                                          error);
6342                         if (ret < 0)
6343                                 return ret;
6344                         last_item = MLX5_FLOW_ITEM_MARK;
6345                         break;
6346                 case RTE_FLOW_ITEM_TYPE_META:
6347                         ret = flow_dv_validate_item_meta(dev, items, attr,
6348                                                          error);
6349                         if (ret < 0)
6350                                 return ret;
6351                         last_item = MLX5_FLOW_ITEM_METADATA;
6352                         break;
6353                 case RTE_FLOW_ITEM_TYPE_ICMP:
6354                         ret = mlx5_flow_validate_item_icmp(items, item_flags,
6355                                                            next_protocol,
6356                                                            error);
6357                         if (ret < 0)
6358                                 return ret;
6359                         last_item = MLX5_FLOW_LAYER_ICMP;
6360                         break;
6361                 case RTE_FLOW_ITEM_TYPE_ICMP6:
6362                         ret = mlx5_flow_validate_item_icmp6(items, item_flags,
6363                                                             next_protocol,
6364                                                             error);
6365                         if (ret < 0)
6366                                 return ret;
6367                         item_ipv6_proto = IPPROTO_ICMPV6;
6368                         last_item = MLX5_FLOW_LAYER_ICMP6;
6369                         break;
6370                 case RTE_FLOW_ITEM_TYPE_TAG:
6371                         ret = flow_dv_validate_item_tag(dev, items,
6372                                                         attr, error);
6373                         if (ret < 0)
6374                                 return ret;
6375                         last_item = MLX5_FLOW_ITEM_TAG;
6376                         break;
6377                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
6378                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
6379                         break;
6380                 case RTE_FLOW_ITEM_TYPE_GTP:
6381                         ret = flow_dv_validate_item_gtp(dev, items, item_flags,
6382                                                         error);
6383                         if (ret < 0)
6384                                 return ret;
6385                         gtp_item = items;
6386                         last_item = MLX5_FLOW_LAYER_GTP;
6387                         break;
6388                 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
6389                         ret = flow_dv_validate_item_gtp_psc(items, last_item,
6390                                                             gtp_item, attr,
6391                                                             error);
6392                         if (ret < 0)
6393                                 return ret;
6394                         last_item = MLX5_FLOW_LAYER_GTP_PSC;
6395                         break;
6396                 case RTE_FLOW_ITEM_TYPE_ECPRI:
6397                         /* Capacity will be checked in the translate stage. */
6398                         ret = mlx5_flow_validate_item_ecpri(items, item_flags,
6399                                                             last_item,
6400                                                             ether_type,
6401                                                             &nic_ecpri_mask,
6402                                                             error);
6403                         if (ret < 0)
6404                                 return ret;
6405                         last_item = MLX5_FLOW_LAYER_ECPRI;
6406                         break;
6407                 default:
6408                         return rte_flow_error_set(error, ENOTSUP,
6409                                                   RTE_FLOW_ERROR_TYPE_ITEM,
6410                                                   NULL, "item not supported");
6411                 }
6412                 item_flags |= last_item;
6413         }
6414         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
6415                 int type = actions->type;
6416
6417                 if (!mlx5_flow_os_action_supported(type))
6418                         return rte_flow_error_set(error, ENOTSUP,
6419                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6420                                                   actions,
6421                                                   "action not supported");
6422                 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
6423                         return rte_flow_error_set(error, ENOTSUP,
6424                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6425                                                   actions, "too many actions");
6426                 switch (type) {
6427                 case RTE_FLOW_ACTION_TYPE_VOID:
6428                         break;
6429                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
6430                         ret = flow_dv_validate_action_port_id(dev,
6431                                                               action_flags,
6432                                                               actions,
6433                                                               attr,
6434                                                               error);
6435                         if (ret)
6436                                 return ret;
6437                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
6438                         ++actions_n;
6439                         break;
6440                 case RTE_FLOW_ACTION_TYPE_FLAG:
6441                         ret = flow_dv_validate_action_flag(dev, action_flags,
6442                                                            attr, error);
6443                         if (ret < 0)
6444                                 return ret;
6445                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
6446                                 /* Count all modify-header actions as one. */
6447                                 if (!(action_flags &
6448                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
6449                                         ++actions_n;
6450                                 action_flags |= MLX5_FLOW_ACTION_FLAG |
6451                                                 MLX5_FLOW_ACTION_MARK_EXT;
6452                                 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6453                                         modify_after_mirror = 1;
6454
6455                         } else {
6456                                 action_flags |= MLX5_FLOW_ACTION_FLAG;
6457                                 ++actions_n;
6458                         }
6459                         rw_act_num += MLX5_ACT_NUM_SET_MARK;
6460                         break;
6461                 case RTE_FLOW_ACTION_TYPE_MARK:
6462                         ret = flow_dv_validate_action_mark(dev, actions,
6463                                                            action_flags,
6464                                                            attr, error);
6465                         if (ret < 0)
6466                                 return ret;
6467                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
6468                                 /* Count all modify-header actions as one. */
6469                                 if (!(action_flags &
6470                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
6471                                         ++actions_n;
6472                                 action_flags |= MLX5_FLOW_ACTION_MARK |
6473                                                 MLX5_FLOW_ACTION_MARK_EXT;
6474                                 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6475                                         modify_after_mirror = 1;
6476                         } else {
6477                                 action_flags |= MLX5_FLOW_ACTION_MARK;
6478                                 ++actions_n;
6479                         }
6480                         rw_act_num += MLX5_ACT_NUM_SET_MARK;
6481                         break;
6482                 case RTE_FLOW_ACTION_TYPE_SET_META:
6483                         ret = flow_dv_validate_action_set_meta(dev, actions,
6484                                                                action_flags,
6485                                                                attr, error);
6486                         if (ret < 0)
6487                                 return ret;
6488                         /* Count all modify-header actions as one action. */
6489                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6490                                 ++actions_n;
6491                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6492                                 modify_after_mirror = 1;
6493                         action_flags |= MLX5_FLOW_ACTION_SET_META;
6494                         rw_act_num += MLX5_ACT_NUM_SET_META;
6495                         break;
6496                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
6497                         ret = flow_dv_validate_action_set_tag(dev, actions,
6498                                                               action_flags,
6499                                                               attr, error);
6500                         if (ret < 0)
6501                                 return ret;
6502                         /* Count all modify-header actions as one action. */
6503                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6504                                 ++actions_n;
6505                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6506                                 modify_after_mirror = 1;
6507                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
6508                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
6509                         break;
6510                 case RTE_FLOW_ACTION_TYPE_DROP:
6511                         ret = mlx5_flow_validate_action_drop(action_flags,
6512                                                              attr, error);
6513                         if (ret < 0)
6514                                 return ret;
6515                         action_flags |= MLX5_FLOW_ACTION_DROP;
6516                         ++actions_n;
6517                         break;
6518                 case RTE_FLOW_ACTION_TYPE_QUEUE:
6519                         ret = mlx5_flow_validate_action_queue(actions,
6520                                                               action_flags, dev,
6521                                                               attr, error);
6522                         if (ret < 0)
6523                                 return ret;
6524                         queue_index = ((const struct rte_flow_action_queue *)
6525                                                         (actions->conf))->index;
6526                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
6527                         ++actions_n;
6528                         break;
6529                 case RTE_FLOW_ACTION_TYPE_RSS:
6530                         rss = actions->conf;
6531                         ret = mlx5_flow_validate_action_rss(actions,
6532                                                             action_flags, dev,
6533                                                             attr, item_flags,
6534                                                             error);
6535                         if (ret < 0)
6536                                 return ret;
6537                         if (rss && sample_rss &&
6538                             (sample_rss->level != rss->level ||
6539                             sample_rss->types != rss->types))
6540                                 return rte_flow_error_set(error, ENOTSUP,
6541                                         RTE_FLOW_ERROR_TYPE_ACTION,
6542                                         NULL,
6543                                         "Can't use the different RSS types "
6544                                         "or level in the same flow");
6545                         if (rss != NULL && rss->queue_num)
6546                                 queue_index = rss->queue[0];
6547                         action_flags |= MLX5_FLOW_ACTION_RSS;
6548                         ++actions_n;
6549                         break;
6550                 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
6551                         ret =
6552                         mlx5_flow_validate_action_default_miss(action_flags,
6553                                         attr, error);
6554                         if (ret < 0)
6555                                 return ret;
6556                         action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
6557                         ++actions_n;
6558                         break;
6559                 case RTE_FLOW_ACTION_TYPE_COUNT:
6560                         ret = flow_dv_validate_action_count(dev, actions,
6561                                                             action_flags,
6562                                                             error);
6563                         if (ret < 0)
6564                                 return ret;
6565                         count = actions->conf;
6566                         action_flags |= MLX5_FLOW_ACTION_COUNT;
6567                         ++actions_n;
6568                         break;
6569                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
6570                         if (flow_dv_validate_action_pop_vlan(dev,
6571                                                              action_flags,
6572                                                              actions,
6573                                                              item_flags, attr,
6574                                                              error))
6575                                 return -rte_errno;
6576                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
6577                         ++actions_n;
6578                         break;
6579                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
6580                         ret = flow_dv_validate_action_push_vlan(dev,
6581                                                                 action_flags,
6582                                                                 vlan_m,
6583                                                                 actions, attr,
6584                                                                 error);
6585                         if (ret < 0)
6586                                 return ret;
6587                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
6588                         ++actions_n;
6589                         break;
6590                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
6591                         ret = flow_dv_validate_action_set_vlan_pcp
6592                                                 (action_flags, actions, error);
6593                         if (ret < 0)
6594                                 return ret;
6595                         /* Count PCP with push_vlan command. */
6596                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
6597                         break;
6598                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
6599                         ret = flow_dv_validate_action_set_vlan_vid
6600                                                 (item_flags, action_flags,
6601                                                  actions, error);
6602                         if (ret < 0)
6603                                 return ret;
6604                         /* Count VID with push_vlan command. */
6605                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
6606                         rw_act_num += MLX5_ACT_NUM_MDF_VID;
6607                         break;
6608                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
6609                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
6610                         ret = flow_dv_validate_action_l2_encap(dev,
6611                                                                action_flags,
6612                                                                actions, attr,
6613                                                                error);
6614                         if (ret < 0)
6615                                 return ret;
6616                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
6617                         ++actions_n;
6618                         break;
6619                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
6620                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
6621                         ret = flow_dv_validate_action_decap(dev, action_flags,
6622                                                             actions, item_flags,
6623                                                             attr, error);
6624                         if (ret < 0)
6625                                 return ret;
6626                         action_flags |= MLX5_FLOW_ACTION_DECAP;
6627                         ++actions_n;
6628                         break;
6629                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
6630                         ret = flow_dv_validate_action_raw_encap_decap
6631                                 (dev, NULL, actions->conf, attr, &action_flags,
6632                                  &actions_n, actions, item_flags, error);
6633                         if (ret < 0)
6634                                 return ret;
6635                         break;
6636                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
6637                         decap = actions->conf;
6638                         while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
6639                                 ;
6640                         if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
6641                                 encap = NULL;
6642                                 actions--;
6643                         } else {
6644                                 encap = actions->conf;
6645                         }
6646                         ret = flow_dv_validate_action_raw_encap_decap
6647                                            (dev,
6648                                             decap ? decap : &empty_decap, encap,
6649                                             attr, &action_flags, &actions_n,
6650                                             actions, item_flags, error);
6651                         if (ret < 0)
6652                                 return ret;
6653                         break;
6654                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
6655                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
6656                         ret = flow_dv_validate_action_modify_mac(action_flags,
6657                                                                  actions,
6658                                                                  item_flags,
6659                                                                  error);
6660                         if (ret < 0)
6661                                 return ret;
6662                         /* Count all modify-header actions as one action. */
6663                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6664                                 ++actions_n;
6665                         action_flags |= actions->type ==
6666                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
6667                                                 MLX5_FLOW_ACTION_SET_MAC_SRC :
6668                                                 MLX5_FLOW_ACTION_SET_MAC_DST;
6669                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6670                                 modify_after_mirror = 1;
6671                         /*
6672                          * Even if the source and destination MAC addresses have
6673                          * overlap in the header with 4B alignment, the convert
6674                          * function will handle them separately and 4 SW actions
6675                          * will be created. And 2 actions will be added each
6676                          * time no matter how many bytes of address will be set.
6677                          */
6678                         rw_act_num += MLX5_ACT_NUM_MDF_MAC;
6679                         break;
6680                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
6681                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
6682                         ret = flow_dv_validate_action_modify_ipv4(action_flags,
6683                                                                   actions,
6684                                                                   item_flags,
6685                                                                   error);
6686                         if (ret < 0)
6687                                 return ret;
6688                         /* Count all modify-header actions as one action. */
6689                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6690                                 ++actions_n;
6691                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6692                                 modify_after_mirror = 1;
6693                         action_flags |= actions->type ==
6694                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
6695                                                 MLX5_FLOW_ACTION_SET_IPV4_SRC :
6696                                                 MLX5_FLOW_ACTION_SET_IPV4_DST;
6697                         rw_act_num += MLX5_ACT_NUM_MDF_IPV4;
6698                         break;
6699                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
6700                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
6701                         ret = flow_dv_validate_action_modify_ipv6(action_flags,
6702                                                                   actions,
6703                                                                   item_flags,
6704                                                                   error);
6705                         if (ret < 0)
6706                                 return ret;
6707                         if (item_ipv6_proto == IPPROTO_ICMPV6)
6708                                 return rte_flow_error_set(error, ENOTSUP,
6709                                         RTE_FLOW_ERROR_TYPE_ACTION,
6710                                         actions,
6711                                         "Can't change header "
6712                                         "with ICMPv6 proto");
6713                         /* Count all modify-header actions as one action. */
6714                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6715                                 ++actions_n;
6716                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6717                                 modify_after_mirror = 1;
6718                         action_flags |= actions->type ==
6719                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
6720                                                 MLX5_FLOW_ACTION_SET_IPV6_SRC :
6721                                                 MLX5_FLOW_ACTION_SET_IPV6_DST;
6722                         rw_act_num += MLX5_ACT_NUM_MDF_IPV6;
6723                         break;
6724                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
6725                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
6726                         ret = flow_dv_validate_action_modify_tp(action_flags,
6727                                                                 actions,
6728                                                                 item_flags,
6729                                                                 error);
6730                         if (ret < 0)
6731                                 return ret;
6732                         /* Count all modify-header actions as one action. */
6733                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6734                                 ++actions_n;
6735                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6736                                 modify_after_mirror = 1;
6737                         action_flags |= actions->type ==
6738                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
6739                                                 MLX5_FLOW_ACTION_SET_TP_SRC :
6740                                                 MLX5_FLOW_ACTION_SET_TP_DST;
6741                         rw_act_num += MLX5_ACT_NUM_MDF_PORT;
6742                         break;
6743                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
6744                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
6745                         ret = flow_dv_validate_action_modify_ttl(action_flags,
6746                                                                  actions,
6747                                                                  item_flags,
6748                                                                  error);
6749                         if (ret < 0)
6750                                 return ret;
6751                         /* Count all modify-header actions as one action. */
6752                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6753                                 ++actions_n;
6754                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6755                                 modify_after_mirror = 1;
6756                         action_flags |= actions->type ==
6757                                         RTE_FLOW_ACTION_TYPE_SET_TTL ?
6758                                                 MLX5_FLOW_ACTION_SET_TTL :
6759                                                 MLX5_FLOW_ACTION_DEC_TTL;
6760                         rw_act_num += MLX5_ACT_NUM_MDF_TTL;
6761                         break;
6762                 case RTE_FLOW_ACTION_TYPE_JUMP:
6763                         ret = flow_dv_validate_action_jump(dev, tunnel, actions,
6764                                                            action_flags,
6765                                                            attr, external,
6766                                                            error);
6767                         if (ret)
6768                                 return ret;
6769                         if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) &&
6770                             fdb_mirror_limit)
6771                                 return rte_flow_error_set(error, EINVAL,
6772                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6773                                                   NULL,
6774                                                   "sample and jump action combination is not supported");
6775                         ++actions_n;
6776                         action_flags |= MLX5_FLOW_ACTION_JUMP;
6777                         break;
6778                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
6779                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
6780                         ret = flow_dv_validate_action_modify_tcp_seq
6781                                                                 (action_flags,
6782                                                                  actions,
6783                                                                  item_flags,
6784                                                                  error);
6785                         if (ret < 0)
6786                                 return ret;
6787                         /* Count all modify-header actions as one action. */
6788                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6789                                 ++actions_n;
6790                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6791                                 modify_after_mirror = 1;
6792                         action_flags |= actions->type ==
6793                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
6794                                                 MLX5_FLOW_ACTION_INC_TCP_SEQ :
6795                                                 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
6796                         rw_act_num += MLX5_ACT_NUM_MDF_TCPSEQ;
6797                         break;
6798                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
6799                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
6800                         ret = flow_dv_validate_action_modify_tcp_ack
6801                                                                 (action_flags,
6802                                                                  actions,
6803                                                                  item_flags,
6804                                                                  error);
6805                         if (ret < 0)
6806                                 return ret;
6807                         /* Count all modify-header actions as one action. */
6808                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6809                                 ++actions_n;
6810                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6811                                 modify_after_mirror = 1;
6812                         action_flags |= actions->type ==
6813                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
6814                                                 MLX5_FLOW_ACTION_INC_TCP_ACK :
6815                                                 MLX5_FLOW_ACTION_DEC_TCP_ACK;
6816                         rw_act_num += MLX5_ACT_NUM_MDF_TCPACK;
6817                         break;
6818                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
6819                         break;
6820                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
6821                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
6822                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
6823                         break;
6824                 case RTE_FLOW_ACTION_TYPE_METER:
6825                         ret = mlx5_flow_validate_action_meter(dev,
6826                                                               action_flags,
6827                                                               actions, attr,
6828                                                               error);
6829                         if (ret < 0)
6830                                 return ret;
6831                         action_flags |= MLX5_FLOW_ACTION_METER;
6832                         ++actions_n;
6833                         /* Meter action will add one more TAG action. */
6834                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
6835                         break;
6836                 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
6837                         if (!attr->transfer && !attr->group)
6838                                 return rte_flow_error_set(error, ENOTSUP,
6839                                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6840                                                                            NULL,
6841                           "Shared ASO age action is not supported for group 0");
6842                         action_flags |= MLX5_FLOW_ACTION_AGE;
6843                         ++actions_n;
6844                         break;
6845                 case RTE_FLOW_ACTION_TYPE_AGE:
6846                         ret = flow_dv_validate_action_age(action_flags,
6847                                                           actions, dev,
6848                                                           error);
6849                         if (ret < 0)
6850                                 return ret;
6851                         /*
6852                          * Validate the regular AGE action (using counter)
6853                          * mutual exclusion with share counter actions.
6854                          */
6855                         if (!priv->sh->flow_hit_aso_en) {
6856                                 if (count && count->shared)
6857                                         return rte_flow_error_set
6858                                                 (error, EINVAL,
6859                                                 RTE_FLOW_ERROR_TYPE_ACTION,
6860                                                 NULL,
6861                                                 "old age and shared count combination is not supported");
6862                                 if (sample_count)
6863                                         return rte_flow_error_set
6864                                                 (error, EINVAL,
6865                                                 RTE_FLOW_ERROR_TYPE_ACTION,
6866                                                 NULL,
6867                                                 "old age action and count must be in the same sub flow");
6868                         }
6869                         action_flags |= MLX5_FLOW_ACTION_AGE;
6870                         ++actions_n;
6871                         break;
6872                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
6873                         ret = flow_dv_validate_action_modify_ipv4_dscp
6874                                                          (action_flags,
6875                                                           actions,
6876                                                           item_flags,
6877                                                           error);
6878                         if (ret < 0)
6879                                 return ret;
6880                         /* Count all modify-header actions as one action. */
6881                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6882                                 ++actions_n;
6883                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6884                                 modify_after_mirror = 1;
6885                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
6886                         rw_act_num += MLX5_ACT_NUM_SET_DSCP;
6887                         break;
6888                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
6889                         ret = flow_dv_validate_action_modify_ipv6_dscp
6890                                                                 (action_flags,
6891                                                                  actions,
6892                                                                  item_flags,
6893                                                                  error);
6894                         if (ret < 0)
6895                                 return ret;
6896                         /* Count all modify-header actions as one action. */
6897                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6898                                 ++actions_n;
6899                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6900                                 modify_after_mirror = 1;
6901                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
6902                         rw_act_num += MLX5_ACT_NUM_SET_DSCP;
6903                         break;
6904                 case RTE_FLOW_ACTION_TYPE_SAMPLE:
6905                         ret = flow_dv_validate_action_sample(&action_flags,
6906                                                              actions, dev,
6907                                                              attr, item_flags,
6908                                                              rss, &sample_rss,
6909                                                              &sample_count,
6910                                                              &fdb_mirror_limit,
6911                                                              error);
6912                         if (ret < 0)
6913                                 return ret;
6914                         action_flags |= MLX5_FLOW_ACTION_SAMPLE;
6915                         ++actions_n;
6916                         break;
6917                 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
6918                         if (actions[0].type != (typeof(actions[0].type))
6919                                 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET)
6920                                 return rte_flow_error_set
6921                                                 (error, EINVAL,
6922                                                 RTE_FLOW_ERROR_TYPE_ACTION,
6923                                                 NULL, "MLX5 private action "
6924                                                 "must be the first");
6925
6926                         action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
6927                         break;
6928                 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
6929                         if (!attr->transfer && !attr->group)
6930                                 return rte_flow_error_set(error, ENOTSUP,
6931                                                 RTE_FLOW_ERROR_TYPE_ACTION,
6932                                                 NULL, "modify field action "
6933                                                 "is not supported for group 0");
6934                         ret = flow_dv_validate_action_modify_field(action_flags,
6935                                                                  actions,
6936                                                                  error);
6937                         if (ret < 0)
6938                                 return ret;
6939                         /* Count all modify-header actions as one action. */
6940                         if (!(action_flags & MLX5_FLOW_ACTION_MODIFY_FIELD))
6941                                 ++actions_n;
6942                         action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
6943                         rw_act_num += ret;
6944                         break;
6945                 default:
6946                         return rte_flow_error_set(error, ENOTSUP,
6947                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6948                                                   actions,
6949                                                   "action not supported");
6950                 }
6951         }
6952         /*
6953          * Validate actions in flow rules
6954          * - Explicit decap action is prohibited by the tunnel offload API.
6955          * - Drop action in tunnel steer rule is prohibited by the API.
6956          * - Application cannot use MARK action because it's value can mask
6957          *   tunnel default miss nitification.
6958          * - JUMP in tunnel match rule has no support in current PMD
6959          *   implementation.
6960          * - TAG & META are reserved for future uses.
6961          */
6962         if (action_flags & MLX5_FLOW_ACTION_TUNNEL_SET) {
6963                 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_DECAP    |
6964                                             MLX5_FLOW_ACTION_MARK     |
6965                                             MLX5_FLOW_ACTION_SET_TAG  |
6966                                             MLX5_FLOW_ACTION_SET_META |
6967                                             MLX5_FLOW_ACTION_DROP;
6968
6969                 if (action_flags & bad_actions_mask)
6970                         return rte_flow_error_set
6971                                         (error, EINVAL,
6972                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6973                                         "Invalid RTE action in tunnel "
6974                                         "set decap rule");
6975                 if (!(action_flags & MLX5_FLOW_ACTION_JUMP))
6976                         return rte_flow_error_set
6977                                         (error, EINVAL,
6978                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6979                                         "tunnel set decap rule must terminate "
6980                                         "with JUMP");
6981                 if (!attr->ingress)
6982                         return rte_flow_error_set
6983                                         (error, EINVAL,
6984                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6985                                         "tunnel flows for ingress traffic only");
6986         }
6987         if (action_flags & MLX5_FLOW_ACTION_TUNNEL_MATCH) {
6988                 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_JUMP    |
6989                                             MLX5_FLOW_ACTION_MARK    |
6990                                             MLX5_FLOW_ACTION_SET_TAG |
6991                                             MLX5_FLOW_ACTION_SET_META;
6992
6993                 if (action_flags & bad_actions_mask)
6994                         return rte_flow_error_set
6995                                         (error, EINVAL,
6996                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6997                                         "Invalid RTE action in tunnel "
6998                                         "set match rule");
6999         }
7000         /*
7001          * Validate the drop action mutual exclusion with other actions.
7002          * Drop action is mutually-exclusive with any other action, except for
7003          * Count action.
7004          * Drop action compatibility with tunnel offload was already validated.
7005          */
7006         if (action_flags & (MLX5_FLOW_ACTION_TUNNEL_MATCH |
7007                             MLX5_FLOW_ACTION_TUNNEL_MATCH));
7008         else if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
7009             (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
7010                 return rte_flow_error_set(error, EINVAL,
7011                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7012                                           "Drop action is mutually-exclusive "
7013                                           "with any other action, except for "
7014                                           "Count action");
7015         /* Eswitch has few restrictions on using items and actions */
7016         if (attr->transfer) {
7017                 if (!mlx5_flow_ext_mreg_supported(dev) &&
7018                     action_flags & MLX5_FLOW_ACTION_FLAG)
7019                         return rte_flow_error_set(error, ENOTSUP,
7020                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7021                                                   NULL,
7022                                                   "unsupported action FLAG");
7023                 if (!mlx5_flow_ext_mreg_supported(dev) &&
7024                     action_flags & MLX5_FLOW_ACTION_MARK)
7025                         return rte_flow_error_set(error, ENOTSUP,
7026                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7027                                                   NULL,
7028                                                   "unsupported action MARK");
7029                 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
7030                         return rte_flow_error_set(error, ENOTSUP,
7031                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7032                                                   NULL,
7033                                                   "unsupported action QUEUE");
7034                 if (action_flags & MLX5_FLOW_ACTION_RSS)
7035                         return rte_flow_error_set(error, ENOTSUP,
7036                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7037                                                   NULL,
7038                                                   "unsupported action RSS");
7039                 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
7040                         return rte_flow_error_set(error, EINVAL,
7041                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7042                                                   actions,
7043                                                   "no fate action is found");
7044         } else {
7045                 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
7046                         return rte_flow_error_set(error, EINVAL,
7047                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7048                                                   actions,
7049                                                   "no fate action is found");
7050         }
7051         /*
7052          * Continue validation for Xcap and VLAN actions.
7053          * If hairpin is working in explicit TX rule mode, there is no actions
7054          * splitting and the validation of hairpin ingress flow should be the
7055          * same as other standard flows.
7056          */
7057         if ((action_flags & (MLX5_FLOW_XCAP_ACTIONS |
7058                              MLX5_FLOW_VLAN_ACTIONS)) &&
7059             (queue_index == 0xFFFF ||
7060              mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN ||
7061              ((conf = mlx5_rxq_get_hairpin_conf(dev, queue_index)) != NULL &&
7062              conf->tx_explicit != 0))) {
7063                 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
7064                     MLX5_FLOW_XCAP_ACTIONS)
7065                         return rte_flow_error_set(error, ENOTSUP,
7066                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7067                                                   NULL, "encap and decap "
7068                                                   "combination aren't supported");
7069                 if (!attr->transfer && attr->ingress) {
7070                         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
7071                                 return rte_flow_error_set
7072                                                 (error, ENOTSUP,
7073                                                  RTE_FLOW_ERROR_TYPE_ACTION,
7074                                                  NULL, "encap is not supported"
7075                                                  " for ingress traffic");
7076                         else if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
7077                                 return rte_flow_error_set
7078                                                 (error, ENOTSUP,
7079                                                  RTE_FLOW_ERROR_TYPE_ACTION,
7080                                                  NULL, "push VLAN action not "
7081                                                  "supported for ingress");
7082                         else if ((action_flags & MLX5_FLOW_VLAN_ACTIONS) ==
7083                                         MLX5_FLOW_VLAN_ACTIONS)
7084                                 return rte_flow_error_set
7085                                                 (error, ENOTSUP,
7086                                                  RTE_FLOW_ERROR_TYPE_ACTION,
7087                                                  NULL, "no support for "
7088                                                  "multiple VLAN actions");
7089                 }
7090         }
7091         /*
7092          * Hairpin flow will add one more TAG action in TX implicit mode.
7093          * In TX explicit mode, there will be no hairpin flow ID.
7094          */
7095         if (hairpin > 0)
7096                 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7097         /* extra metadata enabled: one more TAG action will be add. */
7098         if (dev_conf->dv_flow_en &&
7099             dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
7100             mlx5_flow_ext_mreg_supported(dev))
7101                 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7102         if (rw_act_num >
7103                         flow_dv_modify_hdr_action_max(dev, is_root)) {
7104                 return rte_flow_error_set(error, ENOTSUP,
7105                                           RTE_FLOW_ERROR_TYPE_ACTION,
7106                                           NULL, "too many header modify"
7107                                           " actions to support");
7108         }
7109         /* Eswitch egress mirror and modify flow has limitation on CX5 */
7110         if (fdb_mirror_limit && modify_after_mirror)
7111                 return rte_flow_error_set(error, EINVAL,
7112                                 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7113                                 "sample before modify action is not supported");
7114         return 0;
7115 }
7116
7117 /**
7118  * Internal preparation function. Allocates the DV flow size,
7119  * this size is constant.
7120  *
7121  * @param[in] dev
7122  *   Pointer to the rte_eth_dev structure.
7123  * @param[in] attr
7124  *   Pointer to the flow attributes.
7125  * @param[in] items
7126  *   Pointer to the list of items.
7127  * @param[in] actions
7128  *   Pointer to the list of actions.
7129  * @param[out] error
7130  *   Pointer to the error structure.
7131  *
7132  * @return
7133  *   Pointer to mlx5_flow object on success,
7134  *   otherwise NULL and rte_errno is set.
7135  */
7136 static struct mlx5_flow *
7137 flow_dv_prepare(struct rte_eth_dev *dev,
7138                 const struct rte_flow_attr *attr __rte_unused,
7139                 const struct rte_flow_item items[] __rte_unused,
7140                 const struct rte_flow_action actions[] __rte_unused,
7141                 struct rte_flow_error *error)
7142 {
7143         uint32_t handle_idx = 0;
7144         struct mlx5_flow *dev_flow;
7145         struct mlx5_flow_handle *dev_handle;
7146         struct mlx5_priv *priv = dev->data->dev_private;
7147         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
7148
7149         MLX5_ASSERT(wks);
7150         /* In case of corrupting the memory. */
7151         if (wks->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
7152                 rte_flow_error_set(error, ENOSPC,
7153                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7154                                    "not free temporary device flow");
7155                 return NULL;
7156         }
7157         dev_handle = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
7158                                    &handle_idx);
7159         if (!dev_handle) {
7160                 rte_flow_error_set(error, ENOMEM,
7161                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7162                                    "not enough memory to create flow handle");
7163                 return NULL;
7164         }
7165         MLX5_ASSERT(wks->flow_idx < RTE_DIM(wks->flows));
7166         dev_flow = &wks->flows[wks->flow_idx++];
7167         memset(dev_flow, 0, sizeof(*dev_flow));
7168         dev_flow->handle = dev_handle;
7169         dev_flow->handle_idx = handle_idx;
7170         /*
7171          * In some old rdma-core releases, before continuing, a check of the
7172          * length of matching parameter will be done at first. It needs to use
7173          * the length without misc4 param. If the flow has misc4 support, then
7174          * the length needs to be adjusted accordingly. Each param member is
7175          * aligned with a 64B boundary naturally.
7176          */
7177         dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param) -
7178                                   MLX5_ST_SZ_BYTES(fte_match_set_misc4);
7179         dev_flow->ingress = attr->ingress;
7180         dev_flow->dv.transfer = attr->transfer;
7181         return dev_flow;
7182 }
7183
7184 #ifdef RTE_LIBRTE_MLX5_DEBUG
7185 /**
7186  * Sanity check for match mask and value. Similar to check_valid_spec() in
7187  * kernel driver. If unmasked bit is present in value, it returns failure.
7188  *
7189  * @param match_mask
7190  *   pointer to match mask buffer.
7191  * @param match_value
7192  *   pointer to match value buffer.
7193  *
7194  * @return
7195  *   0 if valid, -EINVAL otherwise.
7196  */
7197 static int
7198 flow_dv_check_valid_spec(void *match_mask, void *match_value)
7199 {
7200         uint8_t *m = match_mask;
7201         uint8_t *v = match_value;
7202         unsigned int i;
7203
7204         for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
7205                 if (v[i] & ~m[i]) {
7206                         DRV_LOG(ERR,
7207                                 "match_value differs from match_criteria"
7208                                 " %p[%u] != %p[%u]",
7209                                 match_value, i, match_mask, i);
7210                         return -EINVAL;
7211                 }
7212         }
7213         return 0;
7214 }
7215 #endif
7216
7217 /**
7218  * Add match of ip_version.
7219  *
7220  * @param[in] group
7221  *   Flow group.
7222  * @param[in] headers_v
7223  *   Values header pointer.
7224  * @param[in] headers_m
7225  *   Masks header pointer.
7226  * @param[in] ip_version
7227  *   The IP version to set.
7228  */
7229 static inline void
7230 flow_dv_set_match_ip_version(uint32_t group,
7231                              void *headers_v,
7232                              void *headers_m,
7233                              uint8_t ip_version)
7234 {
7235         if (group == 0)
7236                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
7237         else
7238                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version,
7239                          ip_version);
7240         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, ip_version);
7241         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, 0);
7242         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype, 0);
7243 }
7244
7245 /**
7246  * Add Ethernet item to matcher and to the value.
7247  *
7248  * @param[in, out] matcher
7249  *   Flow matcher.
7250  * @param[in, out] key
7251  *   Flow matcher value.
7252  * @param[in] item
7253  *   Flow pattern to translate.
7254  * @param[in] inner
7255  *   Item is inner pattern.
7256  */
7257 static void
7258 flow_dv_translate_item_eth(void *matcher, void *key,
7259                            const struct rte_flow_item *item, int inner,
7260                            uint32_t group)
7261 {
7262         const struct rte_flow_item_eth *eth_m = item->mask;
7263         const struct rte_flow_item_eth *eth_v = item->spec;
7264         const struct rte_flow_item_eth nic_mask = {
7265                 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
7266                 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
7267                 .type = RTE_BE16(0xffff),
7268                 .has_vlan = 0,
7269         };
7270         void *hdrs_m;
7271         void *hdrs_v;
7272         char *l24_v;
7273         unsigned int i;
7274
7275         if (!eth_v)
7276                 return;
7277         if (!eth_m)
7278                 eth_m = &nic_mask;
7279         if (inner) {
7280                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7281                                          inner_headers);
7282                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7283         } else {
7284                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7285                                          outer_headers);
7286                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7287         }
7288         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, dmac_47_16),
7289                &eth_m->dst, sizeof(eth_m->dst));
7290         /* The value must be in the range of the mask. */
7291         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, dmac_47_16);
7292         for (i = 0; i < sizeof(eth_m->dst); ++i)
7293                 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
7294         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, smac_47_16),
7295                &eth_m->src, sizeof(eth_m->src));
7296         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, smac_47_16);
7297         /* The value must be in the range of the mask. */
7298         for (i = 0; i < sizeof(eth_m->dst); ++i)
7299                 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
7300         /*
7301          * HW supports match on one Ethertype, the Ethertype following the last
7302          * VLAN tag of the packet (see PRM).
7303          * Set match on ethertype only if ETH header is not followed by VLAN.
7304          * HW is optimized for IPv4/IPv6. In such cases, avoid setting
7305          * ethertype, and use ip_version field instead.
7306          * eCPRI over Ether layer will use type value 0xAEFE.
7307          */
7308         if (eth_m->type == 0xFFFF) {
7309                 /* Set cvlan_tag mask for any single\multi\un-tagged case. */
7310                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
7311                 switch (eth_v->type) {
7312                 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
7313                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
7314                         return;
7315                 case RTE_BE16(RTE_ETHER_TYPE_QINQ):
7316                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
7317                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
7318                         return;
7319                 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
7320                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
7321                         return;
7322                 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
7323                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
7324                         return;
7325                 default:
7326                         break;
7327                 }
7328         }
7329         if (eth_m->has_vlan) {
7330                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
7331                 if (eth_v->has_vlan) {
7332                         /*
7333                          * Here, when also has_more_vlan field in VLAN item is
7334                          * not set, only single-tagged packets will be matched.
7335                          */
7336                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
7337                         return;
7338                 }
7339         }
7340         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
7341                  rte_be_to_cpu_16(eth_m->type));
7342         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, ethertype);
7343         *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
7344 }
7345
7346 /**
7347  * Add VLAN item to matcher and to the value.
7348  *
7349  * @param[in, out] dev_flow
7350  *   Flow descriptor.
7351  * @param[in, out] matcher
7352  *   Flow matcher.
7353  * @param[in, out] key
7354  *   Flow matcher value.
7355  * @param[in] item
7356  *   Flow pattern to translate.
7357  * @param[in] inner
7358  *   Item is inner pattern.
7359  */
7360 static void
7361 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
7362                             void *matcher, void *key,
7363                             const struct rte_flow_item *item,
7364                             int inner, uint32_t group)
7365 {
7366         const struct rte_flow_item_vlan *vlan_m = item->mask;
7367         const struct rte_flow_item_vlan *vlan_v = item->spec;
7368         void *hdrs_m;
7369         void *hdrs_v;
7370         uint16_t tci_m;
7371         uint16_t tci_v;
7372
7373         if (inner) {
7374                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7375                                          inner_headers);
7376                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7377         } else {
7378                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7379                                          outer_headers);
7380                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7381                 /*
7382                  * This is workaround, masks are not supported,
7383                  * and pre-validated.
7384                  */
7385                 if (vlan_v)
7386                         dev_flow->handle->vf_vlan.tag =
7387                                         rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
7388         }
7389         /*
7390          * When VLAN item exists in flow, mark packet as tagged,
7391          * even if TCI is not specified.
7392          */
7393         if (!MLX5_GET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag)) {
7394                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
7395                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
7396         }
7397         if (!vlan_v)
7398                 return;
7399         if (!vlan_m)
7400                 vlan_m = &rte_flow_item_vlan_mask;
7401         tci_m = rte_be_to_cpu_16(vlan_m->tci);
7402         tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
7403         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_vid, tci_m);
7404         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_vid, tci_v);
7405         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_cfi, tci_m >> 12);
7406         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_cfi, tci_v >> 12);
7407         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_prio, tci_m >> 13);
7408         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_prio, tci_v >> 13);
7409         /*
7410          * HW is optimized for IPv4/IPv6. In such cases, avoid setting
7411          * ethertype, and use ip_version field instead.
7412          */
7413         if (vlan_m->inner_type == 0xFFFF) {
7414                 switch (vlan_v->inner_type) {
7415                 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
7416                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
7417                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
7418                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
7419                         return;
7420                 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
7421                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
7422                         return;
7423                 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
7424                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
7425                         return;
7426                 default:
7427                         break;
7428                 }
7429         }
7430         if (vlan_m->has_more_vlan && vlan_v->has_more_vlan) {
7431                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
7432                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
7433                 /* Only one vlan_tag bit can be set. */
7434                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
7435                 return;
7436         }
7437         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
7438                  rte_be_to_cpu_16(vlan_m->inner_type));
7439         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, ethertype,
7440                  rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
7441 }
7442
7443 /**
7444  * Add IPV4 item to matcher and to the value.
7445  *
7446  * @param[in, out] matcher
7447  *   Flow matcher.
7448  * @param[in, out] key
7449  *   Flow matcher value.
7450  * @param[in] item
7451  *   Flow pattern to translate.
7452  * @param[in] inner
7453  *   Item is inner pattern.
7454  * @param[in] group
7455  *   The group to insert the rule.
7456  */
7457 static void
7458 flow_dv_translate_item_ipv4(void *matcher, void *key,
7459                             const struct rte_flow_item *item,
7460                             int inner, uint32_t group)
7461 {
7462         const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
7463         const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
7464         const struct rte_flow_item_ipv4 nic_mask = {
7465                 .hdr = {
7466                         .src_addr = RTE_BE32(0xffffffff),
7467                         .dst_addr = RTE_BE32(0xffffffff),
7468                         .type_of_service = 0xff,
7469                         .next_proto_id = 0xff,
7470                         .time_to_live = 0xff,
7471                 },
7472         };
7473         void *headers_m;
7474         void *headers_v;
7475         char *l24_m;
7476         char *l24_v;
7477         uint8_t tos;
7478
7479         if (inner) {
7480                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7481                                          inner_headers);
7482                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7483         } else {
7484                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7485                                          outer_headers);
7486                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7487         }
7488         flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
7489         if (!ipv4_v)
7490                 return;
7491         if (!ipv4_m)
7492                 ipv4_m = &nic_mask;
7493         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
7494                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
7495         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
7496                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
7497         *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
7498         *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
7499         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
7500                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
7501         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
7502                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
7503         *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
7504         *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
7505         tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
7506         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
7507                  ipv4_m->hdr.type_of_service);
7508         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
7509         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
7510                  ipv4_m->hdr.type_of_service >> 2);
7511         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
7512         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
7513                  ipv4_m->hdr.next_proto_id);
7514         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
7515                  ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
7516         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
7517                  ipv4_m->hdr.time_to_live);
7518         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
7519                  ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
7520         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
7521                  !!(ipv4_m->hdr.fragment_offset));
7522         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
7523                  !!(ipv4_v->hdr.fragment_offset & ipv4_m->hdr.fragment_offset));
7524 }
7525
7526 /**
7527  * Add IPV6 item to matcher and to the value.
7528  *
7529  * @param[in, out] matcher
7530  *   Flow matcher.
7531  * @param[in, out] key
7532  *   Flow matcher value.
7533  * @param[in] item
7534  *   Flow pattern to translate.
7535  * @param[in] inner
7536  *   Item is inner pattern.
7537  * @param[in] group
7538  *   The group to insert the rule.
7539  */
7540 static void
7541 flow_dv_translate_item_ipv6(void *matcher, void *key,
7542                             const struct rte_flow_item *item,
7543                             int inner, uint32_t group)
7544 {
7545         const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
7546         const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
7547         const struct rte_flow_item_ipv6 nic_mask = {
7548                 .hdr = {
7549                         .src_addr =
7550                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
7551                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
7552                         .dst_addr =
7553                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
7554                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
7555                         .vtc_flow = RTE_BE32(0xffffffff),
7556                         .proto = 0xff,
7557                         .hop_limits = 0xff,
7558                 },
7559         };
7560         void *headers_m;
7561         void *headers_v;
7562         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7563         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7564         char *l24_m;
7565         char *l24_v;
7566         uint32_t vtc_m;
7567         uint32_t vtc_v;
7568         int i;
7569         int size;
7570
7571         if (inner) {
7572                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7573                                          inner_headers);
7574                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7575         } else {
7576                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7577                                          outer_headers);
7578                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7579         }
7580         flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
7581         if (!ipv6_v)
7582                 return;
7583         if (!ipv6_m)
7584                 ipv6_m = &nic_mask;
7585         size = sizeof(ipv6_m->hdr.dst_addr);
7586         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
7587                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
7588         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
7589                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
7590         memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
7591         for (i = 0; i < size; ++i)
7592                 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
7593         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
7594                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
7595         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
7596                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
7597         memcpy(l24_m, ipv6_m->hdr.src_addr, size);
7598         for (i = 0; i < size; ++i)
7599                 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
7600         /* TOS. */
7601         vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
7602         vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
7603         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
7604         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
7605         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
7606         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
7607         /* Label. */
7608         if (inner) {
7609                 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
7610                          vtc_m);
7611                 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
7612                          vtc_v);
7613         } else {
7614                 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
7615                          vtc_m);
7616                 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
7617                          vtc_v);
7618         }
7619         /* Protocol. */
7620         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
7621                  ipv6_m->hdr.proto);
7622         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
7623                  ipv6_v->hdr.proto & ipv6_m->hdr.proto);
7624         /* Hop limit. */
7625         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
7626                  ipv6_m->hdr.hop_limits);
7627         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
7628                  ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
7629         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
7630                  !!(ipv6_m->has_frag_ext));
7631         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
7632                  !!(ipv6_v->has_frag_ext & ipv6_m->has_frag_ext));
7633 }
7634
7635 /**
7636  * Add IPV6 fragment extension item to matcher and to the value.
7637  *
7638  * @param[in, out] matcher
7639  *   Flow matcher.
7640  * @param[in, out] key
7641  *   Flow matcher value.
7642  * @param[in] item
7643  *   Flow pattern to translate.
7644  * @param[in] inner
7645  *   Item is inner pattern.
7646  */
7647 static void
7648 flow_dv_translate_item_ipv6_frag_ext(void *matcher, void *key,
7649                                      const struct rte_flow_item *item,
7650                                      int inner)
7651 {
7652         const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_m = item->mask;
7653         const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_v = item->spec;
7654         const struct rte_flow_item_ipv6_frag_ext nic_mask = {
7655                 .hdr = {
7656                         .next_header = 0xff,
7657                         .frag_data = RTE_BE16(0xffff),
7658                 },
7659         };
7660         void *headers_m;
7661         void *headers_v;
7662
7663         if (inner) {
7664                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7665                                          inner_headers);
7666                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7667         } else {
7668                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7669                                          outer_headers);
7670                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7671         }
7672         /* IPv6 fragment extension item exists, so packet is IP fragment. */
7673         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
7674         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 1);
7675         if (!ipv6_frag_ext_v)
7676                 return;
7677         if (!ipv6_frag_ext_m)
7678                 ipv6_frag_ext_m = &nic_mask;
7679         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
7680                  ipv6_frag_ext_m->hdr.next_header);
7681         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
7682                  ipv6_frag_ext_v->hdr.next_header &
7683                  ipv6_frag_ext_m->hdr.next_header);
7684 }
7685
7686 /**
7687  * Add TCP item to matcher and to the value.
7688  *
7689  * @param[in, out] matcher
7690  *   Flow matcher.
7691  * @param[in, out] key
7692  *   Flow matcher value.
7693  * @param[in] item
7694  *   Flow pattern to translate.
7695  * @param[in] inner
7696  *   Item is inner pattern.
7697  */
7698 static void
7699 flow_dv_translate_item_tcp(void *matcher, void *key,
7700                            const struct rte_flow_item *item,
7701                            int inner)
7702 {
7703         const struct rte_flow_item_tcp *tcp_m = item->mask;
7704         const struct rte_flow_item_tcp *tcp_v = item->spec;
7705         void *headers_m;
7706         void *headers_v;
7707
7708         if (inner) {
7709                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7710                                          inner_headers);
7711                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7712         } else {
7713                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7714                                          outer_headers);
7715                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7716         }
7717         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7718         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
7719         if (!tcp_v)
7720                 return;
7721         if (!tcp_m)
7722                 tcp_m = &rte_flow_item_tcp_mask;
7723         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
7724                  rte_be_to_cpu_16(tcp_m->hdr.src_port));
7725         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
7726                  rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
7727         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
7728                  rte_be_to_cpu_16(tcp_m->hdr.dst_port));
7729         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
7730                  rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
7731         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
7732                  tcp_m->hdr.tcp_flags);
7733         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
7734                  (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
7735 }
7736
7737 /**
7738  * Add UDP item to matcher and to the value.
7739  *
7740  * @param[in, out] matcher
7741  *   Flow matcher.
7742  * @param[in, out] key
7743  *   Flow matcher value.
7744  * @param[in] item
7745  *   Flow pattern to translate.
7746  * @param[in] inner
7747  *   Item is inner pattern.
7748  */
7749 static void
7750 flow_dv_translate_item_udp(void *matcher, void *key,
7751                            const struct rte_flow_item *item,
7752                            int inner)
7753 {
7754         const struct rte_flow_item_udp *udp_m = item->mask;
7755         const struct rte_flow_item_udp *udp_v = item->spec;
7756         void *headers_m;
7757         void *headers_v;
7758
7759         if (inner) {
7760                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7761                                          inner_headers);
7762                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7763         } else {
7764                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7765                                          outer_headers);
7766                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7767         }
7768         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7769         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
7770         if (!udp_v)
7771                 return;
7772         if (!udp_m)
7773                 udp_m = &rte_flow_item_udp_mask;
7774         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
7775                  rte_be_to_cpu_16(udp_m->hdr.src_port));
7776         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
7777                  rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
7778         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
7779                  rte_be_to_cpu_16(udp_m->hdr.dst_port));
7780         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
7781                  rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
7782 }
7783
7784 /**
7785  * Add GRE optional Key item to matcher and to the value.
7786  *
7787  * @param[in, out] matcher
7788  *   Flow matcher.
7789  * @param[in, out] key
7790  *   Flow matcher value.
7791  * @param[in] item
7792  *   Flow pattern to translate.
7793  * @param[in] inner
7794  *   Item is inner pattern.
7795  */
7796 static void
7797 flow_dv_translate_item_gre_key(void *matcher, void *key,
7798                                    const struct rte_flow_item *item)
7799 {
7800         const rte_be32_t *key_m = item->mask;
7801         const rte_be32_t *key_v = item->spec;
7802         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7803         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7804         rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
7805
7806         /* GRE K bit must be on and should already be validated */
7807         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
7808         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
7809         if (!key_v)
7810                 return;
7811         if (!key_m)
7812                 key_m = &gre_key_default_mask;
7813         MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
7814                  rte_be_to_cpu_32(*key_m) >> 8);
7815         MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
7816                  rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
7817         MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
7818                  rte_be_to_cpu_32(*key_m) & 0xFF);
7819         MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
7820                  rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
7821 }
7822
7823 /**
7824  * Add GRE item to matcher and to the value.
7825  *
7826  * @param[in, out] matcher
7827  *   Flow matcher.
7828  * @param[in, out] key
7829  *   Flow matcher value.
7830  * @param[in] item
7831  *   Flow pattern to translate.
7832  * @param[in] inner
7833  *   Item is inner pattern.
7834  */
7835 static void
7836 flow_dv_translate_item_gre(void *matcher, void *key,
7837                            const struct rte_flow_item *item,
7838                            int inner)
7839 {
7840         const struct rte_flow_item_gre *gre_m = item->mask;
7841         const struct rte_flow_item_gre *gre_v = item->spec;
7842         void *headers_m;
7843         void *headers_v;
7844         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7845         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7846         struct {
7847                 union {
7848                         __extension__
7849                         struct {
7850                                 uint16_t version:3;
7851                                 uint16_t rsvd0:9;
7852                                 uint16_t s_present:1;
7853                                 uint16_t k_present:1;
7854                                 uint16_t rsvd_bit1:1;
7855                                 uint16_t c_present:1;
7856                         };
7857                         uint16_t value;
7858                 };
7859         } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
7860
7861         if (inner) {
7862                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7863                                          inner_headers);
7864                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7865         } else {
7866                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7867                                          outer_headers);
7868                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7869         }
7870         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7871         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
7872         if (!gre_v)
7873                 return;
7874         if (!gre_m)
7875                 gre_m = &rte_flow_item_gre_mask;
7876         MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
7877                  rte_be_to_cpu_16(gre_m->protocol));
7878         MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
7879                  rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
7880         gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
7881         gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
7882         MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
7883                  gre_crks_rsvd0_ver_m.c_present);
7884         MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
7885                  gre_crks_rsvd0_ver_v.c_present &
7886                  gre_crks_rsvd0_ver_m.c_present);
7887         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
7888                  gre_crks_rsvd0_ver_m.k_present);
7889         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
7890                  gre_crks_rsvd0_ver_v.k_present &
7891                  gre_crks_rsvd0_ver_m.k_present);
7892         MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
7893                  gre_crks_rsvd0_ver_m.s_present);
7894         MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
7895                  gre_crks_rsvd0_ver_v.s_present &
7896                  gre_crks_rsvd0_ver_m.s_present);
7897 }
7898
7899 /**
7900  * Add NVGRE item to matcher and to the value.
7901  *
7902  * @param[in, out] matcher
7903  *   Flow matcher.
7904  * @param[in, out] key
7905  *   Flow matcher value.
7906  * @param[in] item
7907  *   Flow pattern to translate.
7908  * @param[in] inner
7909  *   Item is inner pattern.
7910  */
7911 static void
7912 flow_dv_translate_item_nvgre(void *matcher, void *key,
7913                              const struct rte_flow_item *item,
7914                              int inner)
7915 {
7916         const struct rte_flow_item_nvgre *nvgre_m = item->mask;
7917         const struct rte_flow_item_nvgre *nvgre_v = item->spec;
7918         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7919         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7920         const char *tni_flow_id_m;
7921         const char *tni_flow_id_v;
7922         char *gre_key_m;
7923         char *gre_key_v;
7924         int size;
7925         int i;
7926
7927         /* For NVGRE, GRE header fields must be set with defined values. */
7928         const struct rte_flow_item_gre gre_spec = {
7929                 .c_rsvd0_ver = RTE_BE16(0x2000),
7930                 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
7931         };
7932         const struct rte_flow_item_gre gre_mask = {
7933                 .c_rsvd0_ver = RTE_BE16(0xB000),
7934                 .protocol = RTE_BE16(UINT16_MAX),
7935         };
7936         const struct rte_flow_item gre_item = {
7937                 .spec = &gre_spec,
7938                 .mask = &gre_mask,
7939                 .last = NULL,
7940         };
7941         flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
7942         if (!nvgre_v)
7943                 return;
7944         if (!nvgre_m)
7945                 nvgre_m = &rte_flow_item_nvgre_mask;
7946         tni_flow_id_m = (const char *)nvgre_m->tni;
7947         tni_flow_id_v = (const char *)nvgre_v->tni;
7948         size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
7949         gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
7950         gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
7951         memcpy(gre_key_m, tni_flow_id_m, size);
7952         for (i = 0; i < size; ++i)
7953                 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
7954 }
7955
7956 /**
7957  * Add VXLAN item to matcher and to the value.
7958  *
7959  * @param[in, out] matcher
7960  *   Flow matcher.
7961  * @param[in, out] key
7962  *   Flow matcher value.
7963  * @param[in] item
7964  *   Flow pattern to translate.
7965  * @param[in] inner
7966  *   Item is inner pattern.
7967  */
7968 static void
7969 flow_dv_translate_item_vxlan(void *matcher, void *key,
7970                              const struct rte_flow_item *item,
7971                              int inner)
7972 {
7973         const struct rte_flow_item_vxlan *vxlan_m = item->mask;
7974         const struct rte_flow_item_vxlan *vxlan_v = item->spec;
7975         void *headers_m;
7976         void *headers_v;
7977         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7978         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7979         char *vni_m;
7980         char *vni_v;
7981         uint16_t dport;
7982         int size;
7983         int i;
7984
7985         if (inner) {
7986                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7987                                          inner_headers);
7988                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7989         } else {
7990                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7991                                          outer_headers);
7992                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7993         }
7994         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
7995                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
7996         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7997                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7998                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7999         }
8000         if (!vxlan_v)
8001                 return;
8002         if (!vxlan_m)
8003                 vxlan_m = &rte_flow_item_vxlan_mask;
8004         size = sizeof(vxlan_m->vni);
8005         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
8006         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
8007         memcpy(vni_m, vxlan_m->vni, size);
8008         for (i = 0; i < size; ++i)
8009                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
8010 }
8011
8012 /**
8013  * Add VXLAN-GPE item to matcher and to the value.
8014  *
8015  * @param[in, out] matcher
8016  *   Flow matcher.
8017  * @param[in, out] key
8018  *   Flow matcher value.
8019  * @param[in] item
8020  *   Flow pattern to translate.
8021  * @param[in] inner
8022  *   Item is inner pattern.
8023  */
8024
8025 static void
8026 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
8027                                  const struct rte_flow_item *item, int inner)
8028 {
8029         const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
8030         const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
8031         void *headers_m;
8032         void *headers_v;
8033         void *misc_m =
8034                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
8035         void *misc_v =
8036                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8037         char *vni_m;
8038         char *vni_v;
8039         uint16_t dport;
8040         int size;
8041         int i;
8042         uint8_t flags_m = 0xff;
8043         uint8_t flags_v = 0xc;
8044
8045         if (inner) {
8046                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8047                                          inner_headers);
8048                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8049         } else {
8050                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8051                                          outer_headers);
8052                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8053         }
8054         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
8055                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
8056         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8057                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8058                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8059         }
8060         if (!vxlan_v)
8061                 return;
8062         if (!vxlan_m)
8063                 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
8064         size = sizeof(vxlan_m->vni);
8065         vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
8066         vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
8067         memcpy(vni_m, vxlan_m->vni, size);
8068         for (i = 0; i < size; ++i)
8069                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
8070         if (vxlan_m->flags) {
8071                 flags_m = vxlan_m->flags;
8072                 flags_v = vxlan_v->flags;
8073         }
8074         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
8075         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
8076         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
8077                  vxlan_m->protocol);
8078         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
8079                  vxlan_v->protocol);
8080 }
8081
8082 /**
8083  * Add Geneve item to matcher and to the value.
8084  *
8085  * @param[in, out] matcher
8086  *   Flow matcher.
8087  * @param[in, out] key
8088  *   Flow matcher value.
8089  * @param[in] item
8090  *   Flow pattern to translate.
8091  * @param[in] inner
8092  *   Item is inner pattern.
8093  */
8094
8095 static void
8096 flow_dv_translate_item_geneve(void *matcher, void *key,
8097                               const struct rte_flow_item *item, int inner)
8098 {
8099         const struct rte_flow_item_geneve *geneve_m = item->mask;
8100         const struct rte_flow_item_geneve *geneve_v = item->spec;
8101         void *headers_m;
8102         void *headers_v;
8103         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8104         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8105         uint16_t dport;
8106         uint16_t gbhdr_m;
8107         uint16_t gbhdr_v;
8108         char *vni_m;
8109         char *vni_v;
8110         size_t size, i;
8111
8112         if (inner) {
8113                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8114                                          inner_headers);
8115                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8116         } else {
8117                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8118                                          outer_headers);
8119                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8120         }
8121         dport = MLX5_UDP_PORT_GENEVE;
8122         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8123                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8124                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8125         }
8126         if (!geneve_v)
8127                 return;
8128         if (!geneve_m)
8129                 geneve_m = &rte_flow_item_geneve_mask;
8130         size = sizeof(geneve_m->vni);
8131         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
8132         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
8133         memcpy(vni_m, geneve_m->vni, size);
8134         for (i = 0; i < size; ++i)
8135                 vni_v[i] = vni_m[i] & geneve_v->vni[i];
8136         MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
8137                  rte_be_to_cpu_16(geneve_m->protocol));
8138         MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
8139                  rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
8140         gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
8141         gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
8142         MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
8143                  MLX5_GENEVE_OAMF_VAL(gbhdr_m));
8144         MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
8145                  MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
8146         MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
8147                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
8148         MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
8149                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
8150                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
8151 }
8152
8153 /**
8154  * Create Geneve TLV option resource.
8155  *
8156  * @param dev[in, out]
8157  *   Pointer to rte_eth_dev structure.
8158  * @param[in, out] tag_be24
8159  *   Tag value in big endian then R-shift 8.
8160  * @parm[in, out] dev_flow
8161  *   Pointer to the dev_flow.
8162  * @param[out] error
8163  *   pointer to error structure.
8164  *
8165  * @return
8166  *   0 on success otherwise -errno and errno is set.
8167  */
8168
8169 int
8170 flow_dev_geneve_tlv_option_resource_register(struct rte_eth_dev *dev,
8171                                              const struct rte_flow_item *item,
8172                                              struct rte_flow_error *error)
8173 {
8174         struct mlx5_priv *priv = dev->data->dev_private;
8175         struct mlx5_dev_ctx_shared *sh = priv->sh;
8176         struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
8177                         sh->geneve_tlv_option_resource;
8178         struct mlx5_devx_obj *obj;
8179         const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
8180         int ret = 0;
8181
8182         if (!geneve_opt_v)
8183                 return -1;
8184         rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
8185         if (geneve_opt_resource != NULL) {
8186                 if (geneve_opt_resource->option_class ==
8187                         geneve_opt_v->option_class &&
8188                         geneve_opt_resource->option_type ==
8189                         geneve_opt_v->option_type &&
8190                         geneve_opt_resource->length ==
8191                         geneve_opt_v->option_len) {
8192                         /* We already have GENVE TLV option obj allocated. */
8193                         __atomic_fetch_add(&geneve_opt_resource->refcnt, 1,
8194                                            __ATOMIC_RELAXED);
8195                 } else {
8196                         ret = rte_flow_error_set(error, ENOMEM,
8197                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8198                                 "Only one GENEVE TLV option supported");
8199                         goto exit;
8200                 }
8201         } else {
8202                 /* Create a GENEVE TLV object and resource. */
8203                 obj = mlx5_devx_cmd_create_geneve_tlv_option(sh->ctx,
8204                                 geneve_opt_v->option_class,
8205                                 geneve_opt_v->option_type,
8206                                 geneve_opt_v->option_len);
8207                 if (!obj) {
8208                         ret = rte_flow_error_set(error, ENODATA,
8209                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8210                                 "Failed to create GENEVE TLV Devx object");
8211                         goto exit;
8212                 }
8213                 sh->geneve_tlv_option_resource =
8214                                 mlx5_malloc(MLX5_MEM_ZERO,
8215                                                 sizeof(*geneve_opt_resource),
8216                                                 0, SOCKET_ID_ANY);
8217                 if (!sh->geneve_tlv_option_resource) {
8218                         claim_zero(mlx5_devx_cmd_destroy(obj));
8219                         ret = rte_flow_error_set(error, ENOMEM,
8220                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8221                                 "GENEVE TLV object memory allocation failed");
8222                         goto exit;
8223                 }
8224                 geneve_opt_resource = sh->geneve_tlv_option_resource;
8225                 geneve_opt_resource->obj = obj;
8226                 geneve_opt_resource->option_class = geneve_opt_v->option_class;
8227                 geneve_opt_resource->option_type = geneve_opt_v->option_type;
8228                 geneve_opt_resource->length = geneve_opt_v->option_len;
8229                 __atomic_store_n(&geneve_opt_resource->refcnt, 1,
8230                                 __ATOMIC_RELAXED);
8231         }
8232 exit:
8233         rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
8234         return ret;
8235 }
8236
8237 /**
8238  * Add Geneve TLV option item to matcher.
8239  *
8240  * @param[in, out] dev
8241  *   Pointer to rte_eth_dev structure.
8242  * @param[in, out] matcher
8243  *   Flow matcher.
8244  * @param[in, out] key
8245  *   Flow matcher value.
8246  * @param[in] item
8247  *   Flow pattern to translate.
8248  * @param[out] error
8249  *   Pointer to error structure.
8250  */
8251 static int
8252 flow_dv_translate_item_geneve_opt(struct rte_eth_dev *dev, void *matcher,
8253                                   void *key, const struct rte_flow_item *item,
8254                                   struct rte_flow_error *error)
8255 {
8256         const struct rte_flow_item_geneve_opt *geneve_opt_m = item->mask;
8257         const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
8258         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8259         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8260         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8261                         misc_parameters_3);
8262         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8263         rte_be32_t opt_data_key = 0, opt_data_mask = 0;
8264         int ret = 0;
8265
8266         if (!geneve_opt_v)
8267                 return -1;
8268         if (!geneve_opt_m)
8269                 geneve_opt_m = &rte_flow_item_geneve_opt_mask;
8270         ret = flow_dev_geneve_tlv_option_resource_register(dev, item,
8271                                                            error);
8272         if (ret) {
8273                 DRV_LOG(ERR, "Failed to create geneve_tlv_obj");
8274                 return ret;
8275         }
8276         /*
8277          * Set the option length in GENEVE header if not requested.
8278          * The GENEVE TLV option length is expressed by the option length field
8279          * in the GENEVE header.
8280          * If the option length was not requested but the GENEVE TLV option item
8281          * is present we set the option length field implicitly.
8282          */
8283         if (!MLX5_GET16(fte_match_set_misc, misc_m, geneve_opt_len)) {
8284                 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
8285                          MLX5_GENEVE_OPTLEN_MASK);
8286                 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
8287                          geneve_opt_v->option_len + 1);
8288         }
8289         /* Set the data. */
8290         if (geneve_opt_v->data) {
8291                 memcpy(&opt_data_key, geneve_opt_v->data,
8292                         RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
8293                                 sizeof(opt_data_key)));
8294                 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
8295                                 sizeof(opt_data_key));
8296                 memcpy(&opt_data_mask, geneve_opt_m->data,
8297                         RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
8298                                 sizeof(opt_data_mask)));
8299                 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
8300                                 sizeof(opt_data_mask));
8301                 MLX5_SET(fte_match_set_misc3, misc3_m,
8302                                 geneve_tlv_option_0_data,
8303                                 rte_be_to_cpu_32(opt_data_mask));
8304                 MLX5_SET(fte_match_set_misc3, misc3_v,
8305                                 geneve_tlv_option_0_data,
8306                         rte_be_to_cpu_32(opt_data_key & opt_data_mask));
8307         }
8308         return ret;
8309 }
8310
8311 /**
8312  * Add MPLS item to matcher and to the value.
8313  *
8314  * @param[in, out] matcher
8315  *   Flow matcher.
8316  * @param[in, out] key
8317  *   Flow matcher value.
8318  * @param[in] item
8319  *   Flow pattern to translate.
8320  * @param[in] prev_layer
8321  *   The protocol layer indicated in previous item.
8322  * @param[in] inner
8323  *   Item is inner pattern.
8324  */
8325 static void
8326 flow_dv_translate_item_mpls(void *matcher, void *key,
8327                             const struct rte_flow_item *item,
8328                             uint64_t prev_layer,
8329                             int inner)
8330 {
8331         const uint32_t *in_mpls_m = item->mask;
8332         const uint32_t *in_mpls_v = item->spec;
8333         uint32_t *out_mpls_m = 0;
8334         uint32_t *out_mpls_v = 0;
8335         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8336         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8337         void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
8338                                      misc_parameters_2);
8339         void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
8340         void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
8341         void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8342
8343         switch (prev_layer) {
8344         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
8345                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
8346                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
8347                          MLX5_UDP_PORT_MPLS);
8348                 break;
8349         case MLX5_FLOW_LAYER_GRE:
8350                 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
8351                 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
8352                          RTE_ETHER_TYPE_MPLS);
8353                 break;
8354         default:
8355                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
8356                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8357                          IPPROTO_MPLS);
8358                 break;
8359         }
8360         if (!in_mpls_v)
8361                 return;
8362         if (!in_mpls_m)
8363                 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
8364         switch (prev_layer) {
8365         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
8366                 out_mpls_m =
8367                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
8368                                                  outer_first_mpls_over_udp);
8369                 out_mpls_v =
8370                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
8371                                                  outer_first_mpls_over_udp);
8372                 break;
8373         case MLX5_FLOW_LAYER_GRE:
8374                 out_mpls_m =
8375                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
8376                                                  outer_first_mpls_over_gre);
8377                 out_mpls_v =
8378                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
8379                                                  outer_first_mpls_over_gre);
8380                 break;
8381         default:
8382                 /* Inner MPLS not over GRE is not supported. */
8383                 if (!inner) {
8384                         out_mpls_m =
8385                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
8386                                                          misc2_m,
8387                                                          outer_first_mpls);
8388                         out_mpls_v =
8389                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
8390                                                          misc2_v,
8391                                                          outer_first_mpls);
8392                 }
8393                 break;
8394         }
8395         if (out_mpls_m && out_mpls_v) {
8396                 *out_mpls_m = *in_mpls_m;
8397                 *out_mpls_v = *in_mpls_v & *in_mpls_m;
8398         }
8399 }
8400
8401 /**
8402  * Add metadata register item to matcher
8403  *
8404  * @param[in, out] matcher
8405  *   Flow matcher.
8406  * @param[in, out] key
8407  *   Flow matcher value.
8408  * @param[in] reg_type
8409  *   Type of device metadata register
8410  * @param[in] value
8411  *   Register value
8412  * @param[in] mask
8413  *   Register mask
8414  */
8415 static void
8416 flow_dv_match_meta_reg(void *matcher, void *key,
8417                        enum modify_reg reg_type,
8418                        uint32_t data, uint32_t mask)
8419 {
8420         void *misc2_m =
8421                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
8422         void *misc2_v =
8423                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
8424         uint32_t temp;
8425
8426         data &= mask;
8427         switch (reg_type) {
8428         case REG_A:
8429                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
8430                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
8431                 break;
8432         case REG_B:
8433                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
8434                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
8435                 break;
8436         case REG_C_0:
8437                 /*
8438                  * The metadata register C0 field might be divided into
8439                  * source vport index and META item value, we should set
8440                  * this field according to specified mask, not as whole one.
8441                  */
8442                 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
8443                 temp |= mask;
8444                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
8445                 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
8446                 temp &= ~mask;
8447                 temp |= data;
8448                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
8449                 break;
8450         case REG_C_1:
8451                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
8452                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
8453                 break;
8454         case REG_C_2:
8455                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
8456                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
8457                 break;
8458         case REG_C_3:
8459                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
8460                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
8461                 break;
8462         case REG_C_4:
8463                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
8464                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
8465                 break;
8466         case REG_C_5:
8467                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
8468                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
8469                 break;
8470         case REG_C_6:
8471                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
8472                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
8473                 break;
8474         case REG_C_7:
8475                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
8476                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
8477                 break;
8478         default:
8479                 MLX5_ASSERT(false);
8480                 break;
8481         }
8482 }
8483
8484 /**
8485  * Add MARK item to matcher
8486  *
8487  * @param[in] dev
8488  *   The device to configure through.
8489  * @param[in, out] matcher
8490  *   Flow matcher.
8491  * @param[in, out] key
8492  *   Flow matcher value.
8493  * @param[in] item
8494  *   Flow pattern to translate.
8495  */
8496 static void
8497 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
8498                             void *matcher, void *key,
8499                             const struct rte_flow_item *item)
8500 {
8501         struct mlx5_priv *priv = dev->data->dev_private;
8502         const struct rte_flow_item_mark *mark;
8503         uint32_t value;
8504         uint32_t mask;
8505
8506         mark = item->mask ? (const void *)item->mask :
8507                             &rte_flow_item_mark_mask;
8508         mask = mark->id & priv->sh->dv_mark_mask;
8509         mark = (const void *)item->spec;
8510         MLX5_ASSERT(mark);
8511         value = mark->id & priv->sh->dv_mark_mask & mask;
8512         if (mask) {
8513                 enum modify_reg reg;
8514
8515                 /* Get the metadata register index for the mark. */
8516                 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
8517                 MLX5_ASSERT(reg > 0);
8518                 if (reg == REG_C_0) {
8519                         struct mlx5_priv *priv = dev->data->dev_private;
8520                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
8521                         uint32_t shl_c0 = rte_bsf32(msk_c0);
8522
8523                         mask &= msk_c0;
8524                         mask <<= shl_c0;
8525                         value <<= shl_c0;
8526                 }
8527                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
8528         }
8529 }
8530
8531 /**
8532  * Add META item to matcher
8533  *
8534  * @param[in] dev
8535  *   The devich to configure through.
8536  * @param[in, out] matcher
8537  *   Flow matcher.
8538  * @param[in, out] key
8539  *   Flow matcher value.
8540  * @param[in] attr
8541  *   Attributes of flow that includes this item.
8542  * @param[in] item
8543  *   Flow pattern to translate.
8544  */
8545 static void
8546 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
8547                             void *matcher, void *key,
8548                             const struct rte_flow_attr *attr,
8549                             const struct rte_flow_item *item)
8550 {
8551         const struct rte_flow_item_meta *meta_m;
8552         const struct rte_flow_item_meta *meta_v;
8553
8554         meta_m = (const void *)item->mask;
8555         if (!meta_m)
8556                 meta_m = &rte_flow_item_meta_mask;
8557         meta_v = (const void *)item->spec;
8558         if (meta_v) {
8559                 int reg;
8560                 uint32_t value = meta_v->data;
8561                 uint32_t mask = meta_m->data;
8562
8563                 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
8564                 if (reg < 0)
8565                         return;
8566                 MLX5_ASSERT(reg != REG_NON);
8567                 /*
8568                  * In datapath code there is no endianness
8569                  * coversions for perfromance reasons, all
8570                  * pattern conversions are done in rte_flow.
8571                  */
8572                 value = rte_cpu_to_be_32(value);
8573                 mask = rte_cpu_to_be_32(mask);
8574                 if (reg == REG_C_0) {
8575                         struct mlx5_priv *priv = dev->data->dev_private;
8576                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
8577                         uint32_t shl_c0 = rte_bsf32(msk_c0);
8578 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
8579                         uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
8580
8581                         value >>= shr_c0;
8582                         mask >>= shr_c0;
8583 #endif
8584                         value <<= shl_c0;
8585                         mask <<= shl_c0;
8586                         MLX5_ASSERT(msk_c0);
8587                         MLX5_ASSERT(!(~msk_c0 & mask));
8588                 }
8589                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
8590         }
8591 }
8592
8593 /**
8594  * Add vport metadata Reg C0 item to matcher
8595  *
8596  * @param[in, out] matcher
8597  *   Flow matcher.
8598  * @param[in, out] key
8599  *   Flow matcher value.
8600  * @param[in] reg
8601  *   Flow pattern to translate.
8602  */
8603 static void
8604 flow_dv_translate_item_meta_vport(void *matcher, void *key,
8605                                   uint32_t value, uint32_t mask)
8606 {
8607         flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
8608 }
8609
8610 /**
8611  * Add tag item to matcher
8612  *
8613  * @param[in] dev
8614  *   The devich to configure through.
8615  * @param[in, out] matcher
8616  *   Flow matcher.
8617  * @param[in, out] key
8618  *   Flow matcher value.
8619  * @param[in] item
8620  *   Flow pattern to translate.
8621  */
8622 static void
8623 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
8624                                 void *matcher, void *key,
8625                                 const struct rte_flow_item *item)
8626 {
8627         const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
8628         const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
8629         uint32_t mask, value;
8630
8631         MLX5_ASSERT(tag_v);
8632         value = tag_v->data;
8633         mask = tag_m ? tag_m->data : UINT32_MAX;
8634         if (tag_v->id == REG_C_0) {
8635                 struct mlx5_priv *priv = dev->data->dev_private;
8636                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
8637                 uint32_t shl_c0 = rte_bsf32(msk_c0);
8638
8639                 mask &= msk_c0;
8640                 mask <<= shl_c0;
8641                 value <<= shl_c0;
8642         }
8643         flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
8644 }
8645
8646 /**
8647  * Add TAG item to matcher
8648  *
8649  * @param[in] dev
8650  *   The devich to configure through.
8651  * @param[in, out] matcher
8652  *   Flow matcher.
8653  * @param[in, out] key
8654  *   Flow matcher value.
8655  * @param[in] item
8656  *   Flow pattern to translate.
8657  */
8658 static void
8659 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
8660                            void *matcher, void *key,
8661                            const struct rte_flow_item *item)
8662 {
8663         const struct rte_flow_item_tag *tag_v = item->spec;
8664         const struct rte_flow_item_tag *tag_m = item->mask;
8665         enum modify_reg reg;
8666
8667         MLX5_ASSERT(tag_v);
8668         tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
8669         /* Get the metadata register index for the tag. */
8670         reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
8671         MLX5_ASSERT(reg > 0);
8672         flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
8673 }
8674
8675 /**
8676  * Add source vport match to the specified matcher.
8677  *
8678  * @param[in, out] matcher
8679  *   Flow matcher.
8680  * @param[in, out] key
8681  *   Flow matcher value.
8682  * @param[in] port
8683  *   Source vport value to match
8684  * @param[in] mask
8685  *   Mask
8686  */
8687 static void
8688 flow_dv_translate_item_source_vport(void *matcher, void *key,
8689                                     int16_t port, uint16_t mask)
8690 {
8691         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8692         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8693
8694         MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
8695         MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
8696 }
8697
8698 /**
8699  * Translate port-id item to eswitch match on  port-id.
8700  *
8701  * @param[in] dev
8702  *   The devich to configure through.
8703  * @param[in, out] matcher
8704  *   Flow matcher.
8705  * @param[in, out] key
8706  *   Flow matcher value.
8707  * @param[in] item
8708  *   Flow pattern to translate.
8709  * @param[in]
8710  *   Flow attributes.
8711  *
8712  * @return
8713  *   0 on success, a negative errno value otherwise.
8714  */
8715 static int
8716 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
8717                                void *key, const struct rte_flow_item *item,
8718                                const struct rte_flow_attr *attr)
8719 {
8720         const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
8721         const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
8722         struct mlx5_priv *priv;
8723         uint16_t mask, id;
8724
8725         mask = pid_m ? pid_m->id : 0xffff;
8726         id = pid_v ? pid_v->id : dev->data->port_id;
8727         priv = mlx5_port_to_eswitch_info(id, item == NULL);
8728         if (!priv)
8729                 return -rte_errno;
8730         /*
8731          * Translate to vport field or to metadata, depending on mode.
8732          * Kernel can use either misc.source_port or half of C0 metadata
8733          * register.
8734          */
8735         if (priv->vport_meta_mask) {
8736                 /*
8737                  * Provide the hint for SW steering library
8738                  * to insert the flow into ingress domain and
8739                  * save the extra vport match.
8740                  */
8741                 if (mask == 0xffff && priv->vport_id == 0xffff &&
8742                     priv->pf_bond < 0 && attr->transfer)
8743                         flow_dv_translate_item_source_vport
8744                                 (matcher, key, priv->vport_id, mask);
8745                 /*
8746                  * We should always set the vport metadata register,
8747                  * otherwise the SW steering library can drop
8748                  * the rule if wire vport metadata value is not zero,
8749                  * it depends on kernel configuration.
8750                  */
8751                 flow_dv_translate_item_meta_vport(matcher, key,
8752                                                   priv->vport_meta_tag,
8753                                                   priv->vport_meta_mask);
8754         } else {
8755                 flow_dv_translate_item_source_vport(matcher, key,
8756                                                     priv->vport_id, mask);
8757         }
8758         return 0;
8759 }
8760
8761 /**
8762  * Add ICMP6 item to matcher and to the value.
8763  *
8764  * @param[in, out] matcher
8765  *   Flow matcher.
8766  * @param[in, out] key
8767  *   Flow matcher value.
8768  * @param[in] item
8769  *   Flow pattern to translate.
8770  * @param[in] inner
8771  *   Item is inner pattern.
8772  */
8773 static void
8774 flow_dv_translate_item_icmp6(void *matcher, void *key,
8775                               const struct rte_flow_item *item,
8776                               int inner)
8777 {
8778         const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
8779         const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
8780         void *headers_m;
8781         void *headers_v;
8782         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8783                                      misc_parameters_3);
8784         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8785         if (inner) {
8786                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8787                                          inner_headers);
8788                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8789         } else {
8790                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8791                                          outer_headers);
8792                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8793         }
8794         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
8795         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
8796         if (!icmp6_v)
8797                 return;
8798         if (!icmp6_m)
8799                 icmp6_m = &rte_flow_item_icmp6_mask;
8800         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
8801         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
8802                  icmp6_v->type & icmp6_m->type);
8803         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
8804         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
8805                  icmp6_v->code & icmp6_m->code);
8806 }
8807
8808 /**
8809  * Add ICMP item to matcher and to the value.
8810  *
8811  * @param[in, out] matcher
8812  *   Flow matcher.
8813  * @param[in, out] key
8814  *   Flow matcher value.
8815  * @param[in] item
8816  *   Flow pattern to translate.
8817  * @param[in] inner
8818  *   Item is inner pattern.
8819  */
8820 static void
8821 flow_dv_translate_item_icmp(void *matcher, void *key,
8822                             const struct rte_flow_item *item,
8823                             int inner)
8824 {
8825         const struct rte_flow_item_icmp *icmp_m = item->mask;
8826         const struct rte_flow_item_icmp *icmp_v = item->spec;
8827         uint32_t icmp_header_data_m = 0;
8828         uint32_t icmp_header_data_v = 0;
8829         void *headers_m;
8830         void *headers_v;
8831         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8832                                      misc_parameters_3);
8833         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8834         if (inner) {
8835                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8836                                          inner_headers);
8837                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8838         } else {
8839                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8840                                          outer_headers);
8841                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8842         }
8843         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
8844         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
8845         if (!icmp_v)
8846                 return;
8847         if (!icmp_m)
8848                 icmp_m = &rte_flow_item_icmp_mask;
8849         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
8850                  icmp_m->hdr.icmp_type);
8851         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
8852                  icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
8853         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
8854                  icmp_m->hdr.icmp_code);
8855         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
8856                  icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
8857         icmp_header_data_m = rte_be_to_cpu_16(icmp_m->hdr.icmp_seq_nb);
8858         icmp_header_data_m |= rte_be_to_cpu_16(icmp_m->hdr.icmp_ident) << 16;
8859         if (icmp_header_data_m) {
8860                 icmp_header_data_v = rte_be_to_cpu_16(icmp_v->hdr.icmp_seq_nb);
8861                 icmp_header_data_v |=
8862                          rte_be_to_cpu_16(icmp_v->hdr.icmp_ident) << 16;
8863                 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_header_data,
8864                          icmp_header_data_m);
8865                 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_header_data,
8866                          icmp_header_data_v & icmp_header_data_m);
8867         }
8868 }
8869
8870 /**
8871  * Add GTP item to matcher and to the value.
8872  *
8873  * @param[in, out] matcher
8874  *   Flow matcher.
8875  * @param[in, out] key
8876  *   Flow matcher value.
8877  * @param[in] item
8878  *   Flow pattern to translate.
8879  * @param[in] inner
8880  *   Item is inner pattern.
8881  */
8882 static void
8883 flow_dv_translate_item_gtp(void *matcher, void *key,
8884                            const struct rte_flow_item *item, int inner)
8885 {
8886         const struct rte_flow_item_gtp *gtp_m = item->mask;
8887         const struct rte_flow_item_gtp *gtp_v = item->spec;
8888         void *headers_m;
8889         void *headers_v;
8890         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8891                                      misc_parameters_3);
8892         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8893         uint16_t dport = RTE_GTPU_UDP_PORT;
8894
8895         if (inner) {
8896                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8897                                          inner_headers);
8898                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8899         } else {
8900                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8901                                          outer_headers);
8902                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8903         }
8904         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8905                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8906                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8907         }
8908         if (!gtp_v)
8909                 return;
8910         if (!gtp_m)
8911                 gtp_m = &rte_flow_item_gtp_mask;
8912         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags,
8913                  gtp_m->v_pt_rsv_flags);
8914         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags,
8915                  gtp_v->v_pt_rsv_flags & gtp_m->v_pt_rsv_flags);
8916         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
8917         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
8918                  gtp_v->msg_type & gtp_m->msg_type);
8919         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
8920                  rte_be_to_cpu_32(gtp_m->teid));
8921         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
8922                  rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
8923 }
8924
8925 /**
8926  * Add GTP PSC item to matcher.
8927  *
8928  * @param[in, out] matcher
8929  *   Flow matcher.
8930  * @param[in, out] key
8931  *   Flow matcher value.
8932  * @param[in] item
8933  *   Flow pattern to translate.
8934  */
8935 static int
8936 flow_dv_translate_item_gtp_psc(void *matcher, void *key,
8937                                const struct rte_flow_item *item)
8938 {
8939         const struct rte_flow_item_gtp_psc *gtp_psc_m = item->mask;
8940         const struct rte_flow_item_gtp_psc *gtp_psc_v = item->spec;
8941         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8942                         misc_parameters_3);
8943         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8944         union {
8945                 uint32_t w32;
8946                 struct {
8947                         uint16_t seq_num;
8948                         uint8_t npdu_num;
8949                         uint8_t next_ext_header_type;
8950                 };
8951         } dw_2;
8952         uint8_t gtp_flags;
8953
8954         /* Always set E-flag match on one, regardless of GTP item settings. */
8955         gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_m, gtpu_msg_flags);
8956         gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
8957         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags, gtp_flags);
8958         gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_v, gtpu_msg_flags);
8959         gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
8960         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags, gtp_flags);
8961         /*Set next extension header type. */
8962         dw_2.seq_num = 0;
8963         dw_2.npdu_num = 0;
8964         dw_2.next_ext_header_type = 0xff;
8965         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_dw_2,
8966                  rte_cpu_to_be_32(dw_2.w32));
8967         dw_2.seq_num = 0;
8968         dw_2.npdu_num = 0;
8969         dw_2.next_ext_header_type = 0x85;
8970         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_dw_2,
8971                  rte_cpu_to_be_32(dw_2.w32));
8972         if (gtp_psc_v) {
8973                 union {
8974                         uint32_t w32;
8975                         struct {
8976                                 uint8_t len;
8977                                 uint8_t type_flags;
8978                                 uint8_t qfi;
8979                                 uint8_t reserved;
8980                         };
8981                 } dw_0;
8982
8983                 /*Set extension header PDU type and Qos. */
8984                 if (!gtp_psc_m)
8985                         gtp_psc_m = &rte_flow_item_gtp_psc_mask;
8986                 dw_0.w32 = 0;
8987                 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_m->pdu_type);
8988                 dw_0.qfi = gtp_psc_m->qfi;
8989                 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_first_ext_dw_0,
8990                          rte_cpu_to_be_32(dw_0.w32));
8991                 dw_0.w32 = 0;
8992                 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_v->pdu_type &
8993                                                         gtp_psc_m->pdu_type);
8994                 dw_0.qfi = gtp_psc_v->qfi & gtp_psc_m->qfi;
8995                 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_first_ext_dw_0,
8996                          rte_cpu_to_be_32(dw_0.w32));
8997         }
8998         return 0;
8999 }
9000
9001 /**
9002  * Add eCPRI item to matcher and to the value.
9003  *
9004  * @param[in] dev
9005  *   The devich to configure through.
9006  * @param[in, out] matcher
9007  *   Flow matcher.
9008  * @param[in, out] key
9009  *   Flow matcher value.
9010  * @param[in] item
9011  *   Flow pattern to translate.
9012  * @param[in] samples
9013  *   Sample IDs to be used in the matching.
9014  */
9015 static void
9016 flow_dv_translate_item_ecpri(struct rte_eth_dev *dev, void *matcher,
9017                              void *key, const struct rte_flow_item *item)
9018 {
9019         struct mlx5_priv *priv = dev->data->dev_private;
9020         const struct rte_flow_item_ecpri *ecpri_m = item->mask;
9021         const struct rte_flow_item_ecpri *ecpri_v = item->spec;
9022         struct rte_ecpri_common_hdr common;
9023         void *misc4_m = MLX5_ADDR_OF(fte_match_param, matcher,
9024                                      misc_parameters_4);
9025         void *misc4_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_4);
9026         uint32_t *samples;
9027         void *dw_m;
9028         void *dw_v;
9029
9030         if (!ecpri_v)
9031                 return;
9032         if (!ecpri_m)
9033                 ecpri_m = &rte_flow_item_ecpri_mask;
9034         /*
9035          * Maximal four DW samples are supported in a single matching now.
9036          * Two are used now for a eCPRI matching:
9037          * 1. Type: one byte, mask should be 0x00ff0000 in network order
9038          * 2. ID of a message: one or two bytes, mask 0xffff0000 or 0xff000000
9039          *    if any.
9040          */
9041         if (!ecpri_m->hdr.common.u32)
9042                 return;
9043         samples = priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0].ids;
9044         /* Need to take the whole DW as the mask to fill the entry. */
9045         dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
9046                             prog_sample_field_value_0);
9047         dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
9048                             prog_sample_field_value_0);
9049         /* Already big endian (network order) in the header. */
9050         *(uint32_t *)dw_m = ecpri_m->hdr.common.u32;
9051         *(uint32_t *)dw_v = ecpri_v->hdr.common.u32 & ecpri_m->hdr.common.u32;
9052         /* Sample#0, used for matching type, offset 0. */
9053         MLX5_SET(fte_match_set_misc4, misc4_m,
9054                  prog_sample_field_id_0, samples[0]);
9055         /* It makes no sense to set the sample ID in the mask field. */
9056         MLX5_SET(fte_match_set_misc4, misc4_v,
9057                  prog_sample_field_id_0, samples[0]);
9058         /*
9059          * Checking if message body part needs to be matched.
9060          * Some wildcard rules only matching type field should be supported.
9061          */
9062         if (ecpri_m->hdr.dummy[0]) {
9063                 common.u32 = rte_be_to_cpu_32(ecpri_v->hdr.common.u32);
9064                 switch (common.type) {
9065                 case RTE_ECPRI_MSG_TYPE_IQ_DATA:
9066                 case RTE_ECPRI_MSG_TYPE_RTC_CTRL:
9067                 case RTE_ECPRI_MSG_TYPE_DLY_MSR:
9068                         dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
9069                                             prog_sample_field_value_1);
9070                         dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
9071                                             prog_sample_field_value_1);
9072                         *(uint32_t *)dw_m = ecpri_m->hdr.dummy[0];
9073                         *(uint32_t *)dw_v = ecpri_v->hdr.dummy[0] &
9074                                             ecpri_m->hdr.dummy[0];
9075                         /* Sample#1, to match message body, offset 4. */
9076                         MLX5_SET(fte_match_set_misc4, misc4_m,
9077                                  prog_sample_field_id_1, samples[1]);
9078                         MLX5_SET(fte_match_set_misc4, misc4_v,
9079                                  prog_sample_field_id_1, samples[1]);
9080                         break;
9081                 default:
9082                         /* Others, do not match any sample ID. */
9083                         break;
9084                 }
9085         }
9086 }
9087
9088 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
9089
9090 #define HEADER_IS_ZERO(match_criteria, headers)                              \
9091         !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers),     \
9092                  matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
9093
9094 /**
9095  * Calculate flow matcher enable bitmap.
9096  *
9097  * @param match_criteria
9098  *   Pointer to flow matcher criteria.
9099  *
9100  * @return
9101  *   Bitmap of enabled fields.
9102  */
9103 static uint8_t
9104 flow_dv_matcher_enable(uint32_t *match_criteria)
9105 {
9106         uint8_t match_criteria_enable;
9107
9108         match_criteria_enable =
9109                 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
9110                 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
9111         match_criteria_enable |=
9112                 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
9113                 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
9114         match_criteria_enable |=
9115                 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
9116                 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
9117         match_criteria_enable |=
9118                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
9119                 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
9120         match_criteria_enable |=
9121                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
9122                 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
9123         match_criteria_enable |=
9124                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_4)) <<
9125                 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT;
9126         return match_criteria_enable;
9127 }
9128
9129 struct mlx5_hlist_entry *
9130 flow_dv_tbl_create_cb(struct mlx5_hlist *list, uint64_t key64, void *cb_ctx)
9131 {
9132         struct mlx5_dev_ctx_shared *sh = list->ctx;
9133         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9134         struct rte_eth_dev *dev = ctx->dev;
9135         struct mlx5_flow_tbl_data_entry *tbl_data;
9136         struct mlx5_flow_tbl_tunnel_prm *tt_prm = ctx->data;
9137         struct rte_flow_error *error = ctx->error;
9138         union mlx5_flow_tbl_key key = { .v64 = key64 };
9139         struct mlx5_flow_tbl_resource *tbl;
9140         void *domain;
9141         uint32_t idx = 0;
9142         int ret;
9143
9144         tbl_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
9145         if (!tbl_data) {
9146                 rte_flow_error_set(error, ENOMEM,
9147                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9148                                    NULL,
9149                                    "cannot allocate flow table data entry");
9150                 return NULL;
9151         }
9152         tbl_data->idx = idx;
9153         tbl_data->tunnel = tt_prm->tunnel;
9154         tbl_data->group_id = tt_prm->group_id;
9155         tbl_data->external = !!tt_prm->external;
9156         tbl_data->tunnel_offload = is_tunnel_offload_active(dev);
9157         tbl_data->is_egress = !!key.direction;
9158         tbl_data->is_transfer = !!key.domain;
9159         tbl_data->dummy = !!key.dummy;
9160         tbl_data->table_id = key.table_id;
9161         tbl = &tbl_data->tbl;
9162         if (key.dummy)
9163                 return &tbl_data->entry;
9164         if (key.domain)
9165                 domain = sh->fdb_domain;
9166         else if (key.direction)
9167                 domain = sh->tx_domain;
9168         else
9169                 domain = sh->rx_domain;
9170         ret = mlx5_flow_os_create_flow_tbl(domain, key.table_id, &tbl->obj);
9171         if (ret) {
9172                 rte_flow_error_set(error, ENOMEM,
9173                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9174                                    NULL, "cannot create flow table object");
9175                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
9176                 return NULL;
9177         }
9178         if (key.table_id) {
9179                 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
9180                                         (tbl->obj, &tbl_data->jump.action);
9181                 if (ret) {
9182                         rte_flow_error_set(error, ENOMEM,
9183                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9184                                            NULL,
9185                                            "cannot create flow jump action");
9186                         mlx5_flow_os_destroy_flow_tbl(tbl->obj);
9187                         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
9188                         return NULL;
9189                 }
9190         }
9191         MKSTR(matcher_name, "%s_%s_%u_matcher_cache",
9192               key.domain ? "FDB" : "NIC", key.direction ? "egress" : "ingress",
9193               key.table_id);
9194         mlx5_cache_list_init(&tbl_data->matchers, matcher_name, 0, sh,
9195                              flow_dv_matcher_create_cb,
9196                              flow_dv_matcher_match_cb,
9197                              flow_dv_matcher_remove_cb);
9198         return &tbl_data->entry;
9199 }
9200
9201 int
9202 flow_dv_tbl_match_cb(struct mlx5_hlist *list __rte_unused,
9203                      struct mlx5_hlist_entry *entry, uint64_t key64,
9204                      void *cb_ctx __rte_unused)
9205 {
9206         struct mlx5_flow_tbl_data_entry *tbl_data =
9207                 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
9208         union mlx5_flow_tbl_key key = { .v64 = key64 };
9209
9210         return tbl_data->table_id != key.table_id ||
9211                tbl_data->dummy != key.dummy ||
9212                tbl_data->is_transfer != key.domain ||
9213                tbl_data->is_egress != key.direction;
9214 }
9215
9216 /**
9217  * Get a flow table.
9218  *
9219  * @param[in, out] dev
9220  *   Pointer to rte_eth_dev structure.
9221  * @param[in] table_id
9222  *   Table id to use.
9223  * @param[in] egress
9224  *   Direction of the table.
9225  * @param[in] transfer
9226  *   E-Switch or NIC flow.
9227  * @param[in] dummy
9228  *   Dummy entry for dv API.
9229  * @param[out] error
9230  *   pointer to error structure.
9231  *
9232  * @return
9233  *   Returns tables resource based on the index, NULL in case of failed.
9234  */
9235 struct mlx5_flow_tbl_resource *
9236 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
9237                          uint32_t table_id, uint8_t egress,
9238                          uint8_t transfer,
9239                          bool external,
9240                          const struct mlx5_flow_tunnel *tunnel,
9241                          uint32_t group_id, uint8_t dummy,
9242                          struct rte_flow_error *error)
9243 {
9244         struct mlx5_priv *priv = dev->data->dev_private;
9245         union mlx5_flow_tbl_key table_key = {
9246                 {
9247                         .table_id = table_id,
9248                         .dummy = dummy,
9249                         .domain = !!transfer,
9250                         .direction = !!egress,
9251                 }
9252         };
9253         struct mlx5_flow_tbl_tunnel_prm tt_prm = {
9254                 .tunnel = tunnel,
9255                 .group_id = group_id,
9256                 .external = external,
9257         };
9258         struct mlx5_flow_cb_ctx ctx = {
9259                 .dev = dev,
9260                 .error = error,
9261                 .data = &tt_prm,
9262         };
9263         struct mlx5_hlist_entry *entry;
9264         struct mlx5_flow_tbl_data_entry *tbl_data;
9265
9266         entry = mlx5_hlist_register(priv->sh->flow_tbls, table_key.v64, &ctx);
9267         if (!entry) {
9268                 rte_flow_error_set(error, ENOMEM,
9269                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9270                                    "cannot get table");
9271                 return NULL;
9272         }
9273         DRV_LOG(DEBUG, "Table_id %u tunnel %u group %u registered.",
9274                 table_id, tunnel ? tunnel->tunnel_id : 0, group_id);
9275         tbl_data = container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
9276         return &tbl_data->tbl;
9277 }
9278
9279 void
9280 flow_dv_tbl_remove_cb(struct mlx5_hlist *list,
9281                       struct mlx5_hlist_entry *entry)
9282 {
9283         struct mlx5_dev_ctx_shared *sh = list->ctx;
9284         struct mlx5_flow_tbl_data_entry *tbl_data =
9285                 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
9286
9287         MLX5_ASSERT(entry && sh);
9288         if (tbl_data->jump.action)
9289                 mlx5_flow_os_destroy_flow_action(tbl_data->jump.action);
9290         if (tbl_data->tbl.obj)
9291                 mlx5_flow_os_destroy_flow_tbl(tbl_data->tbl.obj);
9292         if (tbl_data->tunnel_offload && tbl_data->external) {
9293                 struct mlx5_hlist_entry *he;
9294                 struct mlx5_hlist *tunnel_grp_hash;
9295                 struct mlx5_flow_tunnel_hub *thub = sh->tunnel_hub;
9296                 union tunnel_tbl_key tunnel_key = {
9297                         .tunnel_id = tbl_data->tunnel ?
9298                                         tbl_data->tunnel->tunnel_id : 0,
9299                         .group = tbl_data->group_id
9300                 };
9301                 uint32_t table_id = tbl_data->table_id;
9302
9303                 tunnel_grp_hash = tbl_data->tunnel ?
9304                                         tbl_data->tunnel->groups :
9305                                         thub->groups;
9306                 he = mlx5_hlist_lookup(tunnel_grp_hash, tunnel_key.val, NULL);
9307                 if (he)
9308                         mlx5_hlist_unregister(tunnel_grp_hash, he);
9309                 DRV_LOG(DEBUG,
9310                         "Table_id %u tunnel %u group %u released.",
9311                         table_id,
9312                         tbl_data->tunnel ?
9313                         tbl_data->tunnel->tunnel_id : 0,
9314                         tbl_data->group_id);
9315         }
9316         mlx5_cache_list_destroy(&tbl_data->matchers);
9317         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], tbl_data->idx);
9318 }
9319
9320 /**
9321  * Release a flow table.
9322  *
9323  * @param[in] sh
9324  *   Pointer to device shared structure.
9325  * @param[in] tbl
9326  *   Table resource to be released.
9327  *
9328  * @return
9329  *   Returns 0 if table was released, else return 1;
9330  */
9331 static int
9332 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
9333                              struct mlx5_flow_tbl_resource *tbl)
9334 {
9335         struct mlx5_flow_tbl_data_entry *tbl_data =
9336                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
9337
9338         if (!tbl)
9339                 return 0;
9340         return mlx5_hlist_unregister(sh->flow_tbls, &tbl_data->entry);
9341 }
9342
9343 int
9344 flow_dv_matcher_match_cb(struct mlx5_cache_list *list __rte_unused,
9345                          struct mlx5_cache_entry *entry, void *cb_ctx)
9346 {
9347         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9348         struct mlx5_flow_dv_matcher *ref = ctx->data;
9349         struct mlx5_flow_dv_matcher *cur = container_of(entry, typeof(*cur),
9350                                                         entry);
9351
9352         return cur->crc != ref->crc ||
9353                cur->priority != ref->priority ||
9354                memcmp((const void *)cur->mask.buf,
9355                       (const void *)ref->mask.buf, ref->mask.size);
9356 }
9357
9358 struct mlx5_cache_entry *
9359 flow_dv_matcher_create_cb(struct mlx5_cache_list *list,
9360                           struct mlx5_cache_entry *entry __rte_unused,
9361                           void *cb_ctx)
9362 {
9363         struct mlx5_dev_ctx_shared *sh = list->ctx;
9364         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9365         struct mlx5_flow_dv_matcher *ref = ctx->data;
9366         struct mlx5_flow_dv_matcher *cache;
9367         struct mlx5dv_flow_matcher_attr dv_attr = {
9368                 .type = IBV_FLOW_ATTR_NORMAL,
9369                 .match_mask = (void *)&ref->mask,
9370         };
9371         struct mlx5_flow_tbl_data_entry *tbl = container_of(ref->tbl,
9372                                                             typeof(*tbl), tbl);
9373         int ret;
9374
9375         cache = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*cache), 0, SOCKET_ID_ANY);
9376         if (!cache) {
9377                 rte_flow_error_set(ctx->error, ENOMEM,
9378                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9379                                    "cannot create matcher");
9380                 return NULL;
9381         }
9382         *cache = *ref;
9383         dv_attr.match_criteria_enable =
9384                 flow_dv_matcher_enable(cache->mask.buf);
9385         dv_attr.priority = ref->priority;
9386         if (tbl->is_egress)
9387                 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
9388         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->tbl.obj,
9389                                                &cache->matcher_object);
9390         if (ret) {
9391                 mlx5_free(cache);
9392                 rte_flow_error_set(ctx->error, ENOMEM,
9393                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9394                                    "cannot create matcher");
9395                 return NULL;
9396         }
9397         return &cache->entry;
9398 }
9399
9400 /**
9401  * Register the flow matcher.
9402  *
9403  * @param[in, out] dev
9404  *   Pointer to rte_eth_dev structure.
9405  * @param[in, out] matcher
9406  *   Pointer to flow matcher.
9407  * @param[in, out] key
9408  *   Pointer to flow table key.
9409  * @parm[in, out] dev_flow
9410  *   Pointer to the dev_flow.
9411  * @param[out] error
9412  *   pointer to error structure.
9413  *
9414  * @return
9415  *   0 on success otherwise -errno and errno is set.
9416  */
9417 static int
9418 flow_dv_matcher_register(struct rte_eth_dev *dev,
9419                          struct mlx5_flow_dv_matcher *ref,
9420                          union mlx5_flow_tbl_key *key,
9421                          struct mlx5_flow *dev_flow,
9422                          const struct mlx5_flow_tunnel *tunnel,
9423                          uint32_t group_id,
9424                          struct rte_flow_error *error)
9425 {
9426         struct mlx5_cache_entry *entry;
9427         struct mlx5_flow_dv_matcher *cache;
9428         struct mlx5_flow_tbl_resource *tbl;
9429         struct mlx5_flow_tbl_data_entry *tbl_data;
9430         struct mlx5_flow_cb_ctx ctx = {
9431                 .error = error,
9432                 .data = ref,
9433         };
9434
9435         /**
9436          * tunnel offload API requires this registration for cases when
9437          * tunnel match rule was inserted before tunnel set rule.
9438          */
9439         tbl = flow_dv_tbl_resource_get(dev, key->table_id,
9440                                        key->direction, key->domain,
9441                                        dev_flow->external, tunnel,
9442                                        group_id, 0, error);
9443         if (!tbl)
9444                 return -rte_errno;      /* No need to refill the error info */
9445         tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
9446         ref->tbl = tbl;
9447         entry = mlx5_cache_register(&tbl_data->matchers, &ctx);
9448         if (!entry) {
9449                 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
9450                 return rte_flow_error_set(error, ENOMEM,
9451                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9452                                           "cannot allocate ref memory");
9453         }
9454         cache = container_of(entry, typeof(*cache), entry);
9455         dev_flow->handle->dvh.matcher = cache;
9456         return 0;
9457 }
9458
9459 struct mlx5_hlist_entry *
9460 flow_dv_tag_create_cb(struct mlx5_hlist *list, uint64_t key, void *ctx)
9461 {
9462         struct mlx5_dev_ctx_shared *sh = list->ctx;
9463         struct rte_flow_error *error = ctx;
9464         struct mlx5_flow_dv_tag_resource *entry;
9465         uint32_t idx = 0;
9466         int ret;
9467
9468         entry = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_TAG], &idx);
9469         if (!entry) {
9470                 rte_flow_error_set(error, ENOMEM,
9471                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9472                                    "cannot allocate resource memory");
9473                 return NULL;
9474         }
9475         entry->idx = idx;
9476         entry->tag_id = key;
9477         ret = mlx5_flow_os_create_flow_action_tag(key,
9478                                                   &entry->action);
9479         if (ret) {
9480                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], idx);
9481                 rte_flow_error_set(error, ENOMEM,
9482                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9483                                    NULL, "cannot create action");
9484                 return NULL;
9485         }
9486         return &entry->entry;
9487 }
9488
9489 int
9490 flow_dv_tag_match_cb(struct mlx5_hlist *list __rte_unused,
9491                      struct mlx5_hlist_entry *entry, uint64_t key,
9492                      void *cb_ctx __rte_unused)
9493 {
9494         struct mlx5_flow_dv_tag_resource *tag =
9495                 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
9496
9497         return key != tag->tag_id;
9498 }
9499
9500 /**
9501  * Find existing tag resource or create and register a new one.
9502  *
9503  * @param dev[in, out]
9504  *   Pointer to rte_eth_dev structure.
9505  * @param[in, out] tag_be24
9506  *   Tag value in big endian then R-shift 8.
9507  * @parm[in, out] dev_flow
9508  *   Pointer to the dev_flow.
9509  * @param[out] error
9510  *   pointer to error structure.
9511  *
9512  * @return
9513  *   0 on success otherwise -errno and errno is set.
9514  */
9515 static int
9516 flow_dv_tag_resource_register
9517                         (struct rte_eth_dev *dev,
9518                          uint32_t tag_be24,
9519                          struct mlx5_flow *dev_flow,
9520                          struct rte_flow_error *error)
9521 {
9522         struct mlx5_priv *priv = dev->data->dev_private;
9523         struct mlx5_flow_dv_tag_resource *cache_resource;
9524         struct mlx5_hlist_entry *entry;
9525
9526         entry = mlx5_hlist_register(priv->sh->tag_table, tag_be24, error);
9527         if (entry) {
9528                 cache_resource = container_of
9529                         (entry, struct mlx5_flow_dv_tag_resource, entry);
9530                 dev_flow->handle->dvh.rix_tag = cache_resource->idx;
9531                 dev_flow->dv.tag_resource = cache_resource;
9532                 return 0;
9533         }
9534         return -rte_errno;
9535 }
9536
9537 void
9538 flow_dv_tag_remove_cb(struct mlx5_hlist *list,
9539                       struct mlx5_hlist_entry *entry)
9540 {
9541         struct mlx5_dev_ctx_shared *sh = list->ctx;
9542         struct mlx5_flow_dv_tag_resource *tag =
9543                 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
9544
9545         MLX5_ASSERT(tag && sh && tag->action);
9546         claim_zero(mlx5_flow_os_destroy_flow_action(tag->action));
9547         DRV_LOG(DEBUG, "Tag %p: removed.", (void *)tag);
9548         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], tag->idx);
9549 }
9550
9551 /**
9552  * Release the tag.
9553  *
9554  * @param dev
9555  *   Pointer to Ethernet device.
9556  * @param tag_idx
9557  *   Tag index.
9558  *
9559  * @return
9560  *   1 while a reference on it exists, 0 when freed.
9561  */
9562 static int
9563 flow_dv_tag_release(struct rte_eth_dev *dev,
9564                     uint32_t tag_idx)
9565 {
9566         struct mlx5_priv *priv = dev->data->dev_private;
9567         struct mlx5_flow_dv_tag_resource *tag;
9568
9569         tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
9570         if (!tag)
9571                 return 0;
9572         DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
9573                 dev->data->port_id, (void *)tag, tag->entry.ref_cnt);
9574         return mlx5_hlist_unregister(priv->sh->tag_table, &tag->entry);
9575 }
9576
9577 /**
9578  * Translate port ID action to vport.
9579  *
9580  * @param[in] dev
9581  *   Pointer to rte_eth_dev structure.
9582  * @param[in] action
9583  *   Pointer to the port ID action.
9584  * @param[out] dst_port_id
9585  *   The target port ID.
9586  * @param[out] error
9587  *   Pointer to the error structure.
9588  *
9589  * @return
9590  *   0 on success, a negative errno value otherwise and rte_errno is set.
9591  */
9592 static int
9593 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
9594                                  const struct rte_flow_action *action,
9595                                  uint32_t *dst_port_id,
9596                                  struct rte_flow_error *error)
9597 {
9598         uint32_t port;
9599         struct mlx5_priv *priv;
9600         const struct rte_flow_action_port_id *conf =
9601                         (const struct rte_flow_action_port_id *)action->conf;
9602
9603         port = conf->original ? dev->data->port_id : conf->id;
9604         priv = mlx5_port_to_eswitch_info(port, false);
9605         if (!priv)
9606                 return rte_flow_error_set(error, -rte_errno,
9607                                           RTE_FLOW_ERROR_TYPE_ACTION,
9608                                           NULL,
9609                                           "No eswitch info was found for port");
9610 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
9611         /*
9612          * This parameter is transferred to
9613          * mlx5dv_dr_action_create_dest_ib_port().
9614          */
9615         *dst_port_id = priv->dev_port;
9616 #else
9617         /*
9618          * Legacy mode, no LAG configurations is supported.
9619          * This parameter is transferred to
9620          * mlx5dv_dr_action_create_dest_vport().
9621          */
9622         *dst_port_id = priv->vport_id;
9623 #endif
9624         return 0;
9625 }
9626
9627 /**
9628  * Create a counter with aging configuration.
9629  *
9630  * @param[in] dev
9631  *   Pointer to rte_eth_dev structure.
9632  * @param[out] count
9633  *   Pointer to the counter action configuration.
9634  * @param[in] age
9635  *   Pointer to the aging action configuration.
9636  *
9637  * @return
9638  *   Index to flow counter on success, 0 otherwise.
9639  */
9640 static uint32_t
9641 flow_dv_translate_create_counter(struct rte_eth_dev *dev,
9642                                 struct mlx5_flow *dev_flow,
9643                                 const struct rte_flow_action_count *count,
9644                                 const struct rte_flow_action_age *age)
9645 {
9646         uint32_t counter;
9647         struct mlx5_age_param *age_param;
9648
9649         if (count && count->shared)
9650                 counter = flow_dv_counter_get_shared(dev, count->id);
9651         else
9652                 counter = flow_dv_counter_alloc(dev, !!age);
9653         if (!counter || age == NULL)
9654                 return counter;
9655         age_param  = flow_dv_counter_idx_get_age(dev, counter);
9656         age_param->context = age->context ? age->context :
9657                 (void *)(uintptr_t)(dev_flow->flow_idx);
9658         age_param->timeout = age->timeout;
9659         age_param->port_id = dev->data->port_id;
9660         __atomic_store_n(&age_param->sec_since_last_hit, 0, __ATOMIC_RELAXED);
9661         __atomic_store_n(&age_param->state, AGE_CANDIDATE, __ATOMIC_RELAXED);
9662         return counter;
9663 }
9664
9665 /**
9666  * Add Tx queue matcher
9667  *
9668  * @param[in] dev
9669  *   Pointer to the dev struct.
9670  * @param[in, out] matcher
9671  *   Flow matcher.
9672  * @param[in, out] key
9673  *   Flow matcher value.
9674  * @param[in] item
9675  *   Flow pattern to translate.
9676  * @param[in] inner
9677  *   Item is inner pattern.
9678  */
9679 static void
9680 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
9681                                 void *matcher, void *key,
9682                                 const struct rte_flow_item *item)
9683 {
9684         const struct mlx5_rte_flow_item_tx_queue *queue_m;
9685         const struct mlx5_rte_flow_item_tx_queue *queue_v;
9686         void *misc_m =
9687                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
9688         void *misc_v =
9689                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
9690         struct mlx5_txq_ctrl *txq;
9691         uint32_t queue;
9692
9693
9694         queue_m = (const void *)item->mask;
9695         if (!queue_m)
9696                 return;
9697         queue_v = (const void *)item->spec;
9698         if (!queue_v)
9699                 return;
9700         txq = mlx5_txq_get(dev, queue_v->queue);
9701         if (!txq)
9702                 return;
9703         queue = txq->obj->sq->id;
9704         MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
9705         MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
9706                  queue & queue_m->queue);
9707         mlx5_txq_release(dev, queue_v->queue);
9708 }
9709
9710 /**
9711  * Set the hash fields according to the @p flow information.
9712  *
9713  * @param[in] dev_flow
9714  *   Pointer to the mlx5_flow.
9715  * @param[in] rss_desc
9716  *   Pointer to the mlx5_flow_rss_desc.
9717  */
9718 static void
9719 flow_dv_hashfields_set(struct mlx5_flow *dev_flow,
9720                        struct mlx5_flow_rss_desc *rss_desc)
9721 {
9722         uint64_t items = dev_flow->handle->layers;
9723         int rss_inner = 0;
9724         uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
9725
9726         dev_flow->hash_fields = 0;
9727 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
9728         if (rss_desc->level >= 2) {
9729                 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
9730                 rss_inner = 1;
9731         }
9732 #endif
9733         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
9734             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
9735                 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
9736                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
9737                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
9738                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
9739                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
9740                         else
9741                                 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
9742                 }
9743         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
9744                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
9745                 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
9746                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
9747                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
9748                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
9749                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
9750                         else
9751                                 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
9752                 }
9753         }
9754         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
9755             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
9756                 if (rss_types & ETH_RSS_UDP) {
9757                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
9758                                 dev_flow->hash_fields |=
9759                                                 IBV_RX_HASH_SRC_PORT_UDP;
9760                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
9761                                 dev_flow->hash_fields |=
9762                                                 IBV_RX_HASH_DST_PORT_UDP;
9763                         else
9764                                 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
9765                 }
9766         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
9767                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
9768                 if (rss_types & ETH_RSS_TCP) {
9769                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
9770                                 dev_flow->hash_fields |=
9771                                                 IBV_RX_HASH_SRC_PORT_TCP;
9772                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
9773                                 dev_flow->hash_fields |=
9774                                                 IBV_RX_HASH_DST_PORT_TCP;
9775                         else
9776                                 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
9777                 }
9778         }
9779 }
9780
9781 /**
9782  * Prepare an Rx Hash queue.
9783  *
9784  * @param dev
9785  *   Pointer to Ethernet device.
9786  * @param[in] dev_flow
9787  *   Pointer to the mlx5_flow.
9788  * @param[in] rss_desc
9789  *   Pointer to the mlx5_flow_rss_desc.
9790  * @param[out] hrxq_idx
9791  *   Hash Rx queue index.
9792  *
9793  * @return
9794  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
9795  */
9796 static struct mlx5_hrxq *
9797 flow_dv_hrxq_prepare(struct rte_eth_dev *dev,
9798                      struct mlx5_flow *dev_flow,
9799                      struct mlx5_flow_rss_desc *rss_desc,
9800                      uint32_t *hrxq_idx)
9801 {
9802         struct mlx5_priv *priv = dev->data->dev_private;
9803         struct mlx5_flow_handle *dh = dev_flow->handle;
9804         struct mlx5_hrxq *hrxq;
9805
9806         MLX5_ASSERT(rss_desc->queue_num);
9807         rss_desc->key_len = MLX5_RSS_HASH_KEY_LEN;
9808         rss_desc->hash_fields = dev_flow->hash_fields;
9809         rss_desc->tunnel = !!(dh->layers & MLX5_FLOW_LAYER_TUNNEL);
9810         rss_desc->shared_rss = 0;
9811         *hrxq_idx = mlx5_hrxq_get(dev, rss_desc);
9812         if (!*hrxq_idx)
9813                 return NULL;
9814         hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
9815                               *hrxq_idx);
9816         return hrxq;
9817 }
9818
9819 /**
9820  * Release sample sub action resource.
9821  *
9822  * @param[in, out] dev
9823  *   Pointer to rte_eth_dev structure.
9824  * @param[in] act_res
9825  *   Pointer to sample sub action resource.
9826  */
9827 static void
9828 flow_dv_sample_sub_actions_release(struct rte_eth_dev *dev,
9829                                    struct mlx5_flow_sub_actions_idx *act_res)
9830 {
9831         if (act_res->rix_hrxq) {
9832                 mlx5_hrxq_release(dev, act_res->rix_hrxq);
9833                 act_res->rix_hrxq = 0;
9834         }
9835         if (act_res->rix_encap_decap) {
9836                 flow_dv_encap_decap_resource_release(dev,
9837                                                      act_res->rix_encap_decap);
9838                 act_res->rix_encap_decap = 0;
9839         }
9840         if (act_res->rix_port_id_action) {
9841                 flow_dv_port_id_action_resource_release(dev,
9842                                                 act_res->rix_port_id_action);
9843                 act_res->rix_port_id_action = 0;
9844         }
9845         if (act_res->rix_tag) {
9846                 flow_dv_tag_release(dev, act_res->rix_tag);
9847                 act_res->rix_tag = 0;
9848         }
9849         if (act_res->rix_jump) {
9850                 flow_dv_jump_tbl_resource_release(dev, act_res->rix_jump);
9851                 act_res->rix_jump = 0;
9852         }
9853 }
9854
9855 int
9856 flow_dv_sample_match_cb(struct mlx5_cache_list *list __rte_unused,
9857                         struct mlx5_cache_entry *entry, void *cb_ctx)
9858 {
9859         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9860         struct rte_eth_dev *dev = ctx->dev;
9861         struct mlx5_flow_dv_sample_resource *resource = ctx->data;
9862         struct mlx5_flow_dv_sample_resource *cache_resource =
9863                         container_of(entry, typeof(*cache_resource), entry);
9864
9865         if (resource->ratio == cache_resource->ratio &&
9866             resource->ft_type == cache_resource->ft_type &&
9867             resource->ft_id == cache_resource->ft_id &&
9868             resource->set_action == cache_resource->set_action &&
9869             !memcmp((void *)&resource->sample_act,
9870                     (void *)&cache_resource->sample_act,
9871                     sizeof(struct mlx5_flow_sub_actions_list))) {
9872                 /*
9873                  * Existing sample action should release the prepared
9874                  * sub-actions reference counter.
9875                  */
9876                 flow_dv_sample_sub_actions_release(dev,
9877                                                 &resource->sample_idx);
9878                 return 0;
9879         }
9880         return 1;
9881 }
9882
9883 struct mlx5_cache_entry *
9884 flow_dv_sample_create_cb(struct mlx5_cache_list *list __rte_unused,
9885                          struct mlx5_cache_entry *entry __rte_unused,
9886                          void *cb_ctx)
9887 {
9888         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9889         struct rte_eth_dev *dev = ctx->dev;
9890         struct mlx5_flow_dv_sample_resource *resource = ctx->data;
9891         void **sample_dv_actions = resource->sub_actions;
9892         struct mlx5_flow_dv_sample_resource *cache_resource;
9893         struct mlx5dv_dr_flow_sampler_attr sampler_attr;
9894         struct mlx5_priv *priv = dev->data->dev_private;
9895         struct mlx5_dev_ctx_shared *sh = priv->sh;
9896         struct mlx5_flow_tbl_resource *tbl;
9897         uint32_t idx = 0;
9898         const uint32_t next_ft_step = 1;
9899         uint32_t next_ft_id = resource->ft_id + next_ft_step;
9900         uint8_t is_egress = 0;
9901         uint8_t is_transfer = 0;
9902         struct rte_flow_error *error = ctx->error;
9903
9904         /* Register new sample resource. */
9905         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_SAMPLE], &idx);
9906         if (!cache_resource) {
9907                 rte_flow_error_set(error, ENOMEM,
9908                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9909                                           NULL,
9910                                           "cannot allocate resource memory");
9911                 return NULL;
9912         }
9913         *cache_resource = *resource;
9914         /* Create normal path table level */
9915         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
9916                 is_transfer = 1;
9917         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
9918                 is_egress = 1;
9919         tbl = flow_dv_tbl_resource_get(dev, next_ft_id,
9920                                         is_egress, is_transfer,
9921                                         true, NULL, 0, 0, error);
9922         if (!tbl) {
9923                 rte_flow_error_set(error, ENOMEM,
9924                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9925                                           NULL,
9926                                           "fail to create normal path table "
9927                                           "for sample");
9928                 goto error;
9929         }
9930         cache_resource->normal_path_tbl = tbl;
9931         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB) {
9932                 if (!sh->default_miss_action) {
9933                         rte_flow_error_set(error, ENOMEM,
9934                                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9935                                                 NULL,
9936                                                 "default miss action was not "
9937                                                 "created");
9938                         goto error;
9939                 }
9940                 sample_dv_actions[resource->sample_act.actions_num++] =
9941                                                 sh->default_miss_action;
9942         }
9943         /* Create a DR sample action */
9944         sampler_attr.sample_ratio = cache_resource->ratio;
9945         sampler_attr.default_next_table = tbl->obj;
9946         sampler_attr.num_sample_actions = resource->sample_act.actions_num;
9947         sampler_attr.sample_actions = (struct mlx5dv_dr_action **)
9948                                                         &sample_dv_actions[0];
9949         sampler_attr.action = cache_resource->set_action;
9950         if (mlx5_os_flow_dr_create_flow_action_sampler
9951                         (&sampler_attr, &cache_resource->verbs_action)) {
9952                 rte_flow_error_set(error, ENOMEM,
9953                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9954                                         NULL, "cannot create sample action");
9955                 goto error;
9956         }
9957         cache_resource->idx = idx;
9958         cache_resource->dev = dev;
9959         return &cache_resource->entry;
9960 error:
9961         if (cache_resource->ft_type != MLX5DV_FLOW_TABLE_TYPE_FDB)
9962                 flow_dv_sample_sub_actions_release(dev,
9963                                                    &cache_resource->sample_idx);
9964         if (cache_resource->normal_path_tbl)
9965                 flow_dv_tbl_resource_release(MLX5_SH(dev),
9966                                 cache_resource->normal_path_tbl);
9967         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_SAMPLE], idx);
9968         return NULL;
9969
9970 }
9971
9972 /**
9973  * Find existing sample resource or create and register a new one.
9974  *
9975  * @param[in, out] dev
9976  *   Pointer to rte_eth_dev structure.
9977  * @param[in] resource
9978  *   Pointer to sample resource.
9979  * @parm[in, out] dev_flow
9980  *   Pointer to the dev_flow.
9981  * @param[out] error
9982  *   pointer to error structure.
9983  *
9984  * @return
9985  *   0 on success otherwise -errno and errno is set.
9986  */
9987 static int
9988 flow_dv_sample_resource_register(struct rte_eth_dev *dev,
9989                          struct mlx5_flow_dv_sample_resource *resource,
9990                          struct mlx5_flow *dev_flow,
9991                          struct rte_flow_error *error)
9992 {
9993         struct mlx5_flow_dv_sample_resource *cache_resource;
9994         struct mlx5_cache_entry *entry;
9995         struct mlx5_priv *priv = dev->data->dev_private;
9996         struct mlx5_flow_cb_ctx ctx = {
9997                 .dev = dev,
9998                 .error = error,
9999                 .data = resource,
10000         };
10001
10002         entry = mlx5_cache_register(&priv->sh->sample_action_list, &ctx);
10003         if (!entry)
10004                 return -rte_errno;
10005         cache_resource = container_of(entry, typeof(*cache_resource), entry);
10006         dev_flow->handle->dvh.rix_sample = cache_resource->idx;
10007         dev_flow->dv.sample_res = cache_resource;
10008         return 0;
10009 }
10010
10011 int
10012 flow_dv_dest_array_match_cb(struct mlx5_cache_list *list __rte_unused,
10013                             struct mlx5_cache_entry *entry, void *cb_ctx)
10014 {
10015         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10016         struct mlx5_flow_dv_dest_array_resource *resource = ctx->data;
10017         struct rte_eth_dev *dev = ctx->dev;
10018         struct mlx5_flow_dv_dest_array_resource *cache_resource =
10019                         container_of(entry, typeof(*cache_resource), entry);
10020         uint32_t idx = 0;
10021
10022         if (resource->num_of_dest == cache_resource->num_of_dest &&
10023             resource->ft_type == cache_resource->ft_type &&
10024             !memcmp((void *)cache_resource->sample_act,
10025                     (void *)resource->sample_act,
10026                    (resource->num_of_dest *
10027                    sizeof(struct mlx5_flow_sub_actions_list)))) {
10028                 /*
10029                  * Existing sample action should release the prepared
10030                  * sub-actions reference counter.
10031                  */
10032                 for (idx = 0; idx < resource->num_of_dest; idx++)
10033                         flow_dv_sample_sub_actions_release(dev,
10034                                         &resource->sample_idx[idx]);
10035                 return 0;
10036         }
10037         return 1;
10038 }
10039
10040 struct mlx5_cache_entry *
10041 flow_dv_dest_array_create_cb(struct mlx5_cache_list *list __rte_unused,
10042                          struct mlx5_cache_entry *entry __rte_unused,
10043                          void *cb_ctx)
10044 {
10045         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10046         struct rte_eth_dev *dev = ctx->dev;
10047         struct mlx5_flow_dv_dest_array_resource *cache_resource;
10048         struct mlx5_flow_dv_dest_array_resource *resource = ctx->data;
10049         struct mlx5dv_dr_action_dest_attr *dest_attr[MLX5_MAX_DEST_NUM] = { 0 };
10050         struct mlx5dv_dr_action_dest_reformat dest_reformat[MLX5_MAX_DEST_NUM];
10051         struct mlx5_priv *priv = dev->data->dev_private;
10052         struct mlx5_dev_ctx_shared *sh = priv->sh;
10053         struct mlx5_flow_sub_actions_list *sample_act;
10054         struct mlx5dv_dr_domain *domain;
10055         uint32_t idx = 0, res_idx = 0;
10056         struct rte_flow_error *error = ctx->error;
10057         uint64_t action_flags;
10058         int ret;
10059
10060         /* Register new destination array resource. */
10061         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
10062                                             &res_idx);
10063         if (!cache_resource) {
10064                 rte_flow_error_set(error, ENOMEM,
10065                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10066                                           NULL,
10067                                           "cannot allocate resource memory");
10068                 return NULL;
10069         }
10070         *cache_resource = *resource;
10071         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
10072                 domain = sh->fdb_domain;
10073         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
10074                 domain = sh->rx_domain;
10075         else
10076                 domain = sh->tx_domain;
10077         for (idx = 0; idx < resource->num_of_dest; idx++) {
10078                 dest_attr[idx] = (struct mlx5dv_dr_action_dest_attr *)
10079                                  mlx5_malloc(MLX5_MEM_ZERO,
10080                                  sizeof(struct mlx5dv_dr_action_dest_attr),
10081                                  0, SOCKET_ID_ANY);
10082                 if (!dest_attr[idx]) {
10083                         rte_flow_error_set(error, ENOMEM,
10084                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10085                                            NULL,
10086                                            "cannot allocate resource memory");
10087                         goto error;
10088                 }
10089                 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST;
10090                 sample_act = &resource->sample_act[idx];
10091                 action_flags = sample_act->action_flags;
10092                 switch (action_flags) {
10093                 case MLX5_FLOW_ACTION_QUEUE:
10094                         dest_attr[idx]->dest = sample_act->dr_queue_action;
10095                         break;
10096                 case (MLX5_FLOW_ACTION_PORT_ID | MLX5_FLOW_ACTION_ENCAP):
10097                         dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST_REFORMAT;
10098                         dest_attr[idx]->dest_reformat = &dest_reformat[idx];
10099                         dest_attr[idx]->dest_reformat->reformat =
10100                                         sample_act->dr_encap_action;
10101                         dest_attr[idx]->dest_reformat->dest =
10102                                         sample_act->dr_port_id_action;
10103                         break;
10104                 case MLX5_FLOW_ACTION_PORT_ID:
10105                         dest_attr[idx]->dest = sample_act->dr_port_id_action;
10106                         break;
10107                 case MLX5_FLOW_ACTION_JUMP:
10108                         dest_attr[idx]->dest = sample_act->dr_jump_action;
10109                         break;
10110                 default:
10111                         rte_flow_error_set(error, EINVAL,
10112                                            RTE_FLOW_ERROR_TYPE_ACTION,
10113                                            NULL,
10114                                            "unsupported actions type");
10115                         goto error;
10116                 }
10117         }
10118         /* create a dest array actioin */
10119         ret = mlx5_os_flow_dr_create_flow_action_dest_array
10120                                                 (domain,
10121                                                  cache_resource->num_of_dest,
10122                                                  dest_attr,
10123                                                  &cache_resource->action);
10124         if (ret) {
10125                 rte_flow_error_set(error, ENOMEM,
10126                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10127                                    NULL,
10128                                    "cannot create destination array action");
10129                 goto error;
10130         }
10131         cache_resource->idx = res_idx;
10132         cache_resource->dev = dev;
10133         for (idx = 0; idx < resource->num_of_dest; idx++)
10134                 mlx5_free(dest_attr[idx]);
10135         return &cache_resource->entry;
10136 error:
10137         for (idx = 0; idx < resource->num_of_dest; idx++) {
10138                 struct mlx5_flow_sub_actions_idx *act_res =
10139                                         &cache_resource->sample_idx[idx];
10140                 if (act_res->rix_hrxq &&
10141                     !mlx5_hrxq_release(dev,
10142                                 act_res->rix_hrxq))
10143                         act_res->rix_hrxq = 0;
10144                 if (act_res->rix_encap_decap &&
10145                         !flow_dv_encap_decap_resource_release(dev,
10146                                 act_res->rix_encap_decap))
10147                         act_res->rix_encap_decap = 0;
10148                 if (act_res->rix_port_id_action &&
10149                         !flow_dv_port_id_action_resource_release(dev,
10150                                 act_res->rix_port_id_action))
10151                         act_res->rix_port_id_action = 0;
10152                 if (act_res->rix_jump &&
10153                         !flow_dv_jump_tbl_resource_release(dev,
10154                                 act_res->rix_jump))
10155                         act_res->rix_jump = 0;
10156                 if (dest_attr[idx])
10157                         mlx5_free(dest_attr[idx]);
10158         }
10159
10160         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DEST_ARRAY], res_idx);
10161         return NULL;
10162 }
10163
10164 /**
10165  * Find existing destination array resource or create and register a new one.
10166  *
10167  * @param[in, out] dev
10168  *   Pointer to rte_eth_dev structure.
10169  * @param[in] resource
10170  *   Pointer to destination array resource.
10171  * @parm[in, out] dev_flow
10172  *   Pointer to the dev_flow.
10173  * @param[out] error
10174  *   pointer to error structure.
10175  *
10176  * @return
10177  *   0 on success otherwise -errno and errno is set.
10178  */
10179 static int
10180 flow_dv_dest_array_resource_register(struct rte_eth_dev *dev,
10181                          struct mlx5_flow_dv_dest_array_resource *resource,
10182                          struct mlx5_flow *dev_flow,
10183                          struct rte_flow_error *error)
10184 {
10185         struct mlx5_flow_dv_dest_array_resource *cache_resource;
10186         struct mlx5_priv *priv = dev->data->dev_private;
10187         struct mlx5_cache_entry *entry;
10188         struct mlx5_flow_cb_ctx ctx = {
10189                 .dev = dev,
10190                 .error = error,
10191                 .data = resource,
10192         };
10193
10194         entry = mlx5_cache_register(&priv->sh->dest_array_list, &ctx);
10195         if (!entry)
10196                 return -rte_errno;
10197         cache_resource = container_of(entry, typeof(*cache_resource), entry);
10198         dev_flow->handle->dvh.rix_dest_array = cache_resource->idx;
10199         dev_flow->dv.dest_array_res = cache_resource;
10200         return 0;
10201 }
10202
10203 /**
10204  * Convert Sample action to DV specification.
10205  *
10206  * @param[in] dev
10207  *   Pointer to rte_eth_dev structure.
10208  * @param[in] action
10209  *   Pointer to sample action structure.
10210  * @param[in, out] dev_flow
10211  *   Pointer to the mlx5_flow.
10212  * @param[in] attr
10213  *   Pointer to the flow attributes.
10214  * @param[in, out] num_of_dest
10215  *   Pointer to the num of destination.
10216  * @param[in, out] sample_actions
10217  *   Pointer to sample actions list.
10218  * @param[in, out] res
10219  *   Pointer to sample resource.
10220  * @param[out] error
10221  *   Pointer to the error structure.
10222  *
10223  * @return
10224  *   0 on success, a negative errno value otherwise and rte_errno is set.
10225  */
10226 static int
10227 flow_dv_translate_action_sample(struct rte_eth_dev *dev,
10228                                 const struct rte_flow_action_sample *action,
10229                                 struct mlx5_flow *dev_flow,
10230                                 const struct rte_flow_attr *attr,
10231                                 uint32_t *num_of_dest,
10232                                 void **sample_actions,
10233                                 struct mlx5_flow_dv_sample_resource *res,
10234                                 struct rte_flow_error *error)
10235 {
10236         struct mlx5_priv *priv = dev->data->dev_private;
10237         const struct rte_flow_action *sub_actions;
10238         struct mlx5_flow_sub_actions_list *sample_act;
10239         struct mlx5_flow_sub_actions_idx *sample_idx;
10240         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
10241         struct rte_flow *flow = dev_flow->flow;
10242         struct mlx5_flow_rss_desc *rss_desc;
10243         uint64_t action_flags = 0;
10244
10245         MLX5_ASSERT(wks);
10246         rss_desc = &wks->rss_desc;
10247         sample_act = &res->sample_act;
10248         sample_idx = &res->sample_idx;
10249         res->ratio = action->ratio;
10250         sub_actions = action->actions;
10251         for (; sub_actions->type != RTE_FLOW_ACTION_TYPE_END; sub_actions++) {
10252                 int type = sub_actions->type;
10253                 uint32_t pre_rix = 0;
10254                 void *pre_r;
10255                 switch (type) {
10256                 case RTE_FLOW_ACTION_TYPE_QUEUE:
10257                 {
10258                         const struct rte_flow_action_queue *queue;
10259                         struct mlx5_hrxq *hrxq;
10260                         uint32_t hrxq_idx;
10261
10262                         queue = sub_actions->conf;
10263                         rss_desc->queue_num = 1;
10264                         rss_desc->queue[0] = queue->index;
10265                         hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
10266                                                     rss_desc, &hrxq_idx);
10267                         if (!hrxq)
10268                                 return rte_flow_error_set
10269                                         (error, rte_errno,
10270                                          RTE_FLOW_ERROR_TYPE_ACTION,
10271                                          NULL,
10272                                          "cannot create fate queue");
10273                         sample_act->dr_queue_action = hrxq->action;
10274                         sample_idx->rix_hrxq = hrxq_idx;
10275                         sample_actions[sample_act->actions_num++] =
10276                                                 hrxq->action;
10277                         (*num_of_dest)++;
10278                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
10279                         if (action_flags & MLX5_FLOW_ACTION_MARK)
10280                                 dev_flow->handle->rix_hrxq = hrxq_idx;
10281                         dev_flow->handle->fate_action =
10282                                         MLX5_FLOW_FATE_QUEUE;
10283                         break;
10284                 }
10285                 case RTE_FLOW_ACTION_TYPE_RSS:
10286                 {
10287                         struct mlx5_hrxq *hrxq;
10288                         uint32_t hrxq_idx;
10289                         const struct rte_flow_action_rss *rss;
10290                         const uint8_t *rss_key;
10291
10292                         rss = sub_actions->conf;
10293                         memcpy(rss_desc->queue, rss->queue,
10294                                rss->queue_num * sizeof(uint16_t));
10295                         rss_desc->queue_num = rss->queue_num;
10296                         /* NULL RSS key indicates default RSS key. */
10297                         rss_key = !rss->key ? rss_hash_default_key : rss->key;
10298                         memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
10299                         /*
10300                          * rss->level and rss.types should be set in advance
10301                          * when expanding items for RSS.
10302                          */
10303                         flow_dv_hashfields_set(dev_flow, rss_desc);
10304                         hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
10305                                                     rss_desc, &hrxq_idx);
10306                         if (!hrxq)
10307                                 return rte_flow_error_set
10308                                         (error, rte_errno,
10309                                          RTE_FLOW_ERROR_TYPE_ACTION,
10310                                          NULL,
10311                                          "cannot create fate queue");
10312                         sample_act->dr_queue_action = hrxq->action;
10313                         sample_idx->rix_hrxq = hrxq_idx;
10314                         sample_actions[sample_act->actions_num++] =
10315                                                 hrxq->action;
10316                         (*num_of_dest)++;
10317                         action_flags |= MLX5_FLOW_ACTION_RSS;
10318                         if (action_flags & MLX5_FLOW_ACTION_MARK)
10319                                 dev_flow->handle->rix_hrxq = hrxq_idx;
10320                         dev_flow->handle->fate_action =
10321                                         MLX5_FLOW_FATE_QUEUE;
10322                         break;
10323                 }
10324                 case RTE_FLOW_ACTION_TYPE_MARK:
10325                 {
10326                         uint32_t tag_be = mlx5_flow_mark_set
10327                                 (((const struct rte_flow_action_mark *)
10328                                 (sub_actions->conf))->id);
10329
10330                         dev_flow->handle->mark = 1;
10331                         pre_rix = dev_flow->handle->dvh.rix_tag;
10332                         /* Save the mark resource before sample */
10333                         pre_r = dev_flow->dv.tag_resource;
10334                         if (flow_dv_tag_resource_register(dev, tag_be,
10335                                                   dev_flow, error))
10336                                 return -rte_errno;
10337                         MLX5_ASSERT(dev_flow->dv.tag_resource);
10338                         sample_act->dr_tag_action =
10339                                 dev_flow->dv.tag_resource->action;
10340                         sample_idx->rix_tag =
10341                                 dev_flow->handle->dvh.rix_tag;
10342                         sample_actions[sample_act->actions_num++] =
10343                                                 sample_act->dr_tag_action;
10344                         /* Recover the mark resource after sample */
10345                         dev_flow->dv.tag_resource = pre_r;
10346                         dev_flow->handle->dvh.rix_tag = pre_rix;
10347                         action_flags |= MLX5_FLOW_ACTION_MARK;
10348                         break;
10349                 }
10350                 case RTE_FLOW_ACTION_TYPE_COUNT:
10351                 {
10352                         if (!flow->counter) {
10353                                 flow->counter =
10354                                         flow_dv_translate_create_counter(dev,
10355                                                 dev_flow, sub_actions->conf,
10356                                                 0);
10357                                 if (!flow->counter)
10358                                         return rte_flow_error_set
10359                                                 (error, rte_errno,
10360                                                 RTE_FLOW_ERROR_TYPE_ACTION,
10361                                                 NULL,
10362                                                 "cannot create counter"
10363                                                 " object.");
10364                         }
10365                         sample_act->dr_cnt_action =
10366                                   (flow_dv_counter_get_by_idx(dev,
10367                                   flow->counter, NULL))->action;
10368                         sample_actions[sample_act->actions_num++] =
10369                                                 sample_act->dr_cnt_action;
10370                         action_flags |= MLX5_FLOW_ACTION_COUNT;
10371                         break;
10372                 }
10373                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
10374                 {
10375                         struct mlx5_flow_dv_port_id_action_resource
10376                                         port_id_resource;
10377                         uint32_t port_id = 0;
10378
10379                         memset(&port_id_resource, 0, sizeof(port_id_resource));
10380                         /* Save the port id resource before sample */
10381                         pre_rix = dev_flow->handle->rix_port_id_action;
10382                         pre_r = dev_flow->dv.port_id_action;
10383                         if (flow_dv_translate_action_port_id(dev, sub_actions,
10384                                                              &port_id, error))
10385                                 return -rte_errno;
10386                         port_id_resource.port_id = port_id;
10387                         if (flow_dv_port_id_action_resource_register
10388                             (dev, &port_id_resource, dev_flow, error))
10389                                 return -rte_errno;
10390                         sample_act->dr_port_id_action =
10391                                 dev_flow->dv.port_id_action->action;
10392                         sample_idx->rix_port_id_action =
10393                                 dev_flow->handle->rix_port_id_action;
10394                         sample_actions[sample_act->actions_num++] =
10395                                                 sample_act->dr_port_id_action;
10396                         /* Recover the port id resource after sample */
10397                         dev_flow->dv.port_id_action = pre_r;
10398                         dev_flow->handle->rix_port_id_action = pre_rix;
10399                         (*num_of_dest)++;
10400                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
10401                         break;
10402                 }
10403                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
10404                         /* Save the encap resource before sample */
10405                         pre_rix = dev_flow->handle->dvh.rix_encap_decap;
10406                         pre_r = dev_flow->dv.encap_decap;
10407                         if (flow_dv_create_action_l2_encap(dev, sub_actions,
10408                                                            dev_flow,
10409                                                            attr->transfer,
10410                                                            error))
10411                                 return -rte_errno;
10412                         sample_act->dr_encap_action =
10413                                 dev_flow->dv.encap_decap->action;
10414                         sample_idx->rix_encap_decap =
10415                                 dev_flow->handle->dvh.rix_encap_decap;
10416                         sample_actions[sample_act->actions_num++] =
10417                                                 sample_act->dr_encap_action;
10418                         /* Recover the encap resource after sample */
10419                         dev_flow->dv.encap_decap = pre_r;
10420                         dev_flow->handle->dvh.rix_encap_decap = pre_rix;
10421                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
10422                         break;
10423                 default:
10424                         return rte_flow_error_set(error, EINVAL,
10425                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10426                                 NULL,
10427                                 "Not support for sampler action");
10428                 }
10429         }
10430         sample_act->action_flags = action_flags;
10431         res->ft_id = dev_flow->dv.group;
10432         if (attr->transfer) {
10433                 union {
10434                         uint32_t action_in[MLX5_ST_SZ_DW(set_action_in)];
10435                         uint64_t set_action;
10436                 } action_ctx = { .set_action = 0 };
10437
10438                 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
10439                 MLX5_SET(set_action_in, action_ctx.action_in, action_type,
10440                          MLX5_MODIFICATION_TYPE_SET);
10441                 MLX5_SET(set_action_in, action_ctx.action_in, field,
10442                          MLX5_MODI_META_REG_C_0);
10443                 MLX5_SET(set_action_in, action_ctx.action_in, data,
10444                          priv->vport_meta_tag);
10445                 res->set_action = action_ctx.set_action;
10446         } else if (attr->ingress) {
10447                 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
10448         } else {
10449                 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_TX;
10450         }
10451         return 0;
10452 }
10453
10454 /**
10455  * Convert Sample action to DV specification.
10456  *
10457  * @param[in] dev
10458  *   Pointer to rte_eth_dev structure.
10459  * @param[in, out] dev_flow
10460  *   Pointer to the mlx5_flow.
10461  * @param[in] num_of_dest
10462  *   The num of destination.
10463  * @param[in, out] res
10464  *   Pointer to sample resource.
10465  * @param[in, out] mdest_res
10466  *   Pointer to destination array resource.
10467  * @param[in] sample_actions
10468  *   Pointer to sample path actions list.
10469  * @param[in] action_flags
10470  *   Holds the actions detected until now.
10471  * @param[out] error
10472  *   Pointer to the error structure.
10473  *
10474  * @return
10475  *   0 on success, a negative errno value otherwise and rte_errno is set.
10476  */
10477 static int
10478 flow_dv_create_action_sample(struct rte_eth_dev *dev,
10479                              struct mlx5_flow *dev_flow,
10480                              uint32_t num_of_dest,
10481                              struct mlx5_flow_dv_sample_resource *res,
10482                              struct mlx5_flow_dv_dest_array_resource *mdest_res,
10483                              void **sample_actions,
10484                              uint64_t action_flags,
10485                              struct rte_flow_error *error)
10486 {
10487         /* update normal path action resource into last index of array */
10488         uint32_t dest_index = MLX5_MAX_DEST_NUM - 1;
10489         struct mlx5_flow_sub_actions_list *sample_act =
10490                                         &mdest_res->sample_act[dest_index];
10491         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
10492         struct mlx5_flow_rss_desc *rss_desc;
10493         uint32_t normal_idx = 0;
10494         struct mlx5_hrxq *hrxq;
10495         uint32_t hrxq_idx;
10496
10497         MLX5_ASSERT(wks);
10498         rss_desc = &wks->rss_desc;
10499         if (num_of_dest > 1) {
10500                 if (sample_act->action_flags & MLX5_FLOW_ACTION_QUEUE) {
10501                         /* Handle QP action for mirroring */
10502                         hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
10503                                                     rss_desc, &hrxq_idx);
10504                         if (!hrxq)
10505                                 return rte_flow_error_set
10506                                      (error, rte_errno,
10507                                       RTE_FLOW_ERROR_TYPE_ACTION,
10508                                       NULL,
10509                                       "cannot create rx queue");
10510                         normal_idx++;
10511                         mdest_res->sample_idx[dest_index].rix_hrxq = hrxq_idx;
10512                         sample_act->dr_queue_action = hrxq->action;
10513                         if (action_flags & MLX5_FLOW_ACTION_MARK)
10514                                 dev_flow->handle->rix_hrxq = hrxq_idx;
10515                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
10516                 }
10517                 if (sample_act->action_flags & MLX5_FLOW_ACTION_ENCAP) {
10518                         normal_idx++;
10519                         mdest_res->sample_idx[dest_index].rix_encap_decap =
10520                                 dev_flow->handle->dvh.rix_encap_decap;
10521                         sample_act->dr_encap_action =
10522                                 dev_flow->dv.encap_decap->action;
10523                 }
10524                 if (sample_act->action_flags & MLX5_FLOW_ACTION_PORT_ID) {
10525                         normal_idx++;
10526                         mdest_res->sample_idx[dest_index].rix_port_id_action =
10527                                 dev_flow->handle->rix_port_id_action;
10528                         sample_act->dr_port_id_action =
10529                                 dev_flow->dv.port_id_action->action;
10530                 }
10531                 if (sample_act->action_flags & MLX5_FLOW_ACTION_JUMP) {
10532                         normal_idx++;
10533                         mdest_res->sample_idx[dest_index].rix_jump =
10534                                 dev_flow->handle->rix_jump;
10535                         sample_act->dr_jump_action =
10536                                 dev_flow->dv.jump->action;
10537                         dev_flow->handle->rix_jump = 0;
10538                 }
10539                 sample_act->actions_num = normal_idx;
10540                 /* update sample action resource into first index of array */
10541                 mdest_res->ft_type = res->ft_type;
10542                 memcpy(&mdest_res->sample_idx[0], &res->sample_idx,
10543                                 sizeof(struct mlx5_flow_sub_actions_idx));
10544                 memcpy(&mdest_res->sample_act[0], &res->sample_act,
10545                                 sizeof(struct mlx5_flow_sub_actions_list));
10546                 mdest_res->num_of_dest = num_of_dest;
10547                 if (flow_dv_dest_array_resource_register(dev, mdest_res,
10548                                                          dev_flow, error))
10549                         return rte_flow_error_set(error, EINVAL,
10550                                                   RTE_FLOW_ERROR_TYPE_ACTION,
10551                                                   NULL, "can't create sample "
10552                                                   "action");
10553         } else {
10554                 res->sub_actions = sample_actions;
10555                 if (flow_dv_sample_resource_register(dev, res, dev_flow, error))
10556                         return rte_flow_error_set(error, EINVAL,
10557                                                   RTE_FLOW_ERROR_TYPE_ACTION,
10558                                                   NULL,
10559                                                   "can't create sample action");
10560         }
10561         return 0;
10562 }
10563
10564 /**
10565  * Remove an ASO age action from age actions list.
10566  *
10567  * @param[in] dev
10568  *   Pointer to the Ethernet device structure.
10569  * @param[in] age
10570  *   Pointer to the aso age action handler.
10571  */
10572 static void
10573 flow_dv_aso_age_remove_from_age(struct rte_eth_dev *dev,
10574                                 struct mlx5_aso_age_action *age)
10575 {
10576         struct mlx5_age_info *age_info;
10577         struct mlx5_age_param *age_param = &age->age_params;
10578         struct mlx5_priv *priv = dev->data->dev_private;
10579         uint16_t expected = AGE_CANDIDATE;
10580
10581         age_info = GET_PORT_AGE_INFO(priv);
10582         if (!__atomic_compare_exchange_n(&age_param->state, &expected,
10583                                          AGE_FREE, false, __ATOMIC_RELAXED,
10584                                          __ATOMIC_RELAXED)) {
10585                 /**
10586                  * We need the lock even it is age timeout,
10587                  * since age action may still in process.
10588                  */
10589                 rte_spinlock_lock(&age_info->aged_sl);
10590                 LIST_REMOVE(age, next);
10591                 rte_spinlock_unlock(&age_info->aged_sl);
10592                 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
10593         }
10594 }
10595
10596 /**
10597  * Release an ASO age action.
10598  *
10599  * @param[in] dev
10600  *   Pointer to the Ethernet device structure.
10601  * @param[in] age_idx
10602  *   Index of ASO age action to release.
10603  * @param[in] flow
10604  *   True if the release operation is during flow destroy operation.
10605  *   False if the release operation is during action destroy operation.
10606  *
10607  * @return
10608  *   0 when age action was removed, otherwise the number of references.
10609  */
10610 static int
10611 flow_dv_aso_age_release(struct rte_eth_dev *dev, uint32_t age_idx)
10612 {
10613         struct mlx5_priv *priv = dev->data->dev_private;
10614         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
10615         struct mlx5_aso_age_action *age = flow_aso_age_get_by_idx(dev, age_idx);
10616         uint32_t ret = __atomic_sub_fetch(&age->refcnt, 1, __ATOMIC_RELAXED);
10617
10618         if (!ret) {
10619                 flow_dv_aso_age_remove_from_age(dev, age);
10620                 rte_spinlock_lock(&mng->free_sl);
10621                 LIST_INSERT_HEAD(&mng->free, age, next);
10622                 rte_spinlock_unlock(&mng->free_sl);
10623         }
10624         return ret;
10625 }
10626
10627 /**
10628  * Resize the ASO age pools array by MLX5_CNT_CONTAINER_RESIZE pools.
10629  *
10630  * @param[in] dev
10631  *   Pointer to the Ethernet device structure.
10632  *
10633  * @return
10634  *   0 on success, otherwise negative errno value and rte_errno is set.
10635  */
10636 static int
10637 flow_dv_aso_age_pools_resize(struct rte_eth_dev *dev)
10638 {
10639         struct mlx5_priv *priv = dev->data->dev_private;
10640         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
10641         void *old_pools = mng->pools;
10642         uint32_t resize = mng->n + MLX5_CNT_CONTAINER_RESIZE;
10643         uint32_t mem_size = sizeof(struct mlx5_aso_age_pool *) * resize;
10644         void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
10645
10646         if (!pools) {
10647                 rte_errno = ENOMEM;
10648                 return -ENOMEM;
10649         }
10650         if (old_pools) {
10651                 memcpy(pools, old_pools,
10652                        mng->n * sizeof(struct mlx5_flow_counter_pool *));
10653                 mlx5_free(old_pools);
10654         } else {
10655                 /* First ASO flow hit allocation - starting ASO data-path. */
10656                 int ret = mlx5_aso_queue_start(priv->sh);
10657
10658                 if (ret) {
10659                         mlx5_free(pools);
10660                         return ret;
10661                 }
10662         }
10663         mng->n = resize;
10664         mng->pools = pools;
10665         return 0;
10666 }
10667
10668 /**
10669  * Create and initialize a new ASO aging pool.
10670  *
10671  * @param[in] dev
10672  *   Pointer to the Ethernet device structure.
10673  * @param[out] age_free
10674  *   Where to put the pointer of a new age action.
10675  *
10676  * @return
10677  *   The age actions pool pointer and @p age_free is set on success,
10678  *   NULL otherwise and rte_errno is set.
10679  */
10680 static struct mlx5_aso_age_pool *
10681 flow_dv_age_pool_create(struct rte_eth_dev *dev,
10682                         struct mlx5_aso_age_action **age_free)
10683 {
10684         struct mlx5_priv *priv = dev->data->dev_private;
10685         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
10686         struct mlx5_aso_age_pool *pool = NULL;
10687         struct mlx5_devx_obj *obj = NULL;
10688         uint32_t i;
10689
10690         obj = mlx5_devx_cmd_create_flow_hit_aso_obj(priv->sh->ctx,
10691                                                     priv->sh->pdn);
10692         if (!obj) {
10693                 rte_errno = ENODATA;
10694                 DRV_LOG(ERR, "Failed to create flow_hit_aso_obj using DevX.");
10695                 return NULL;
10696         }
10697         pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
10698         if (!pool) {
10699                 claim_zero(mlx5_devx_cmd_destroy(obj));
10700                 rte_errno = ENOMEM;
10701                 return NULL;
10702         }
10703         pool->flow_hit_aso_obj = obj;
10704         pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
10705         rte_spinlock_lock(&mng->resize_sl);
10706         pool->index = mng->next;
10707         /* Resize pools array if there is no room for the new pool in it. */
10708         if (pool->index == mng->n && flow_dv_aso_age_pools_resize(dev)) {
10709                 claim_zero(mlx5_devx_cmd_destroy(obj));
10710                 mlx5_free(pool);
10711                 rte_spinlock_unlock(&mng->resize_sl);
10712                 return NULL;
10713         }
10714         mng->pools[pool->index] = pool;
10715         mng->next++;
10716         rte_spinlock_unlock(&mng->resize_sl);
10717         /* Assign the first action in the new pool, the rest go to free list. */
10718         *age_free = &pool->actions[0];
10719         for (i = 1; i < MLX5_ASO_AGE_ACTIONS_PER_POOL; i++) {
10720                 pool->actions[i].offset = i;
10721                 LIST_INSERT_HEAD(&mng->free, &pool->actions[i], next);
10722         }
10723         return pool;
10724 }
10725
10726 /**
10727  * Allocate a ASO aging bit.
10728  *
10729  * @param[in] dev
10730  *   Pointer to the Ethernet device structure.
10731  * @param[out] error
10732  *   Pointer to the error structure.
10733  *
10734  * @return
10735  *   Index to ASO age action on success, 0 otherwise and rte_errno is set.
10736  */
10737 static uint32_t
10738 flow_dv_aso_age_alloc(struct rte_eth_dev *dev, struct rte_flow_error *error)
10739 {
10740         struct mlx5_priv *priv = dev->data->dev_private;
10741         const struct mlx5_aso_age_pool *pool;
10742         struct mlx5_aso_age_action *age_free = NULL;
10743         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
10744
10745         MLX5_ASSERT(mng);
10746         /* Try to get the next free age action bit. */
10747         rte_spinlock_lock(&mng->free_sl);
10748         age_free = LIST_FIRST(&mng->free);
10749         if (age_free) {
10750                 LIST_REMOVE(age_free, next);
10751         } else if (!flow_dv_age_pool_create(dev, &age_free)) {
10752                 rte_spinlock_unlock(&mng->free_sl);
10753                 rte_flow_error_set(error, rte_errno, RTE_FLOW_ERROR_TYPE_ACTION,
10754                                    NULL, "failed to create ASO age pool");
10755                 return 0; /* 0 is an error. */
10756         }
10757         rte_spinlock_unlock(&mng->free_sl);
10758         pool = container_of
10759           ((const struct mlx5_aso_age_action (*)[MLX5_ASO_AGE_ACTIONS_PER_POOL])
10760                   (age_free - age_free->offset), const struct mlx5_aso_age_pool,
10761                                                                        actions);
10762         if (!age_free->dr_action) {
10763                 int reg_c = mlx5_flow_get_reg_id(dev, MLX5_ASO_FLOW_HIT, 0,
10764                                                  error);
10765
10766                 if (reg_c < 0) {
10767                         rte_flow_error_set(error, rte_errno,
10768                                            RTE_FLOW_ERROR_TYPE_ACTION,
10769                                            NULL, "failed to get reg_c "
10770                                            "for ASO flow hit");
10771                         return 0; /* 0 is an error. */
10772                 }
10773 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
10774                 age_free->dr_action = mlx5_glue->dv_create_flow_action_aso
10775                                 (priv->sh->rx_domain,
10776                                  pool->flow_hit_aso_obj->obj, age_free->offset,
10777                                  MLX5DV_DR_ACTION_FLAGS_ASO_FIRST_HIT_SET,
10778                                  (reg_c - REG_C_0));
10779 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
10780                 if (!age_free->dr_action) {
10781                         rte_errno = errno;
10782                         rte_spinlock_lock(&mng->free_sl);
10783                         LIST_INSERT_HEAD(&mng->free, age_free, next);
10784                         rte_spinlock_unlock(&mng->free_sl);
10785                         rte_flow_error_set(error, rte_errno,
10786                                            RTE_FLOW_ERROR_TYPE_ACTION,
10787                                            NULL, "failed to create ASO "
10788                                            "flow hit action");
10789                         return 0; /* 0 is an error. */
10790                 }
10791         }
10792         __atomic_store_n(&age_free->refcnt, 1, __ATOMIC_RELAXED);
10793         return pool->index | ((age_free->offset + 1) << 16);
10794 }
10795
10796 /**
10797  * Create a age action using ASO mechanism.
10798  *
10799  * @param[in] dev
10800  *   Pointer to rte_eth_dev structure.
10801  * @param[in] age
10802  *   Pointer to the aging action configuration.
10803  * @param[out] error
10804  *   Pointer to the error structure.
10805  *
10806  * @return
10807  *   Index to flow counter on success, 0 otherwise.
10808  */
10809 static uint32_t
10810 flow_dv_translate_create_aso_age(struct rte_eth_dev *dev,
10811                                  const struct rte_flow_action_age *age,
10812                                  struct rte_flow_error *error)
10813 {
10814         uint32_t age_idx = 0;
10815         struct mlx5_aso_age_action *aso_age;
10816
10817         age_idx = flow_dv_aso_age_alloc(dev, error);
10818         if (!age_idx)
10819                 return 0;
10820         aso_age = flow_aso_age_get_by_idx(dev, age_idx);
10821         aso_age->age_params.context = age->context;
10822         aso_age->age_params.timeout = age->timeout;
10823         aso_age->age_params.port_id = dev->data->port_id;
10824         __atomic_store_n(&aso_age->age_params.sec_since_last_hit, 0,
10825                          __ATOMIC_RELAXED);
10826         __atomic_store_n(&aso_age->age_params.state, AGE_CANDIDATE,
10827                          __ATOMIC_RELAXED);
10828         return age_idx;
10829 }
10830
10831 /**
10832  * Fill the flow with DV spec, lock free
10833  * (mutex should be acquired by caller).
10834  *
10835  * @param[in] dev
10836  *   Pointer to rte_eth_dev structure.
10837  * @param[in, out] dev_flow
10838  *   Pointer to the sub flow.
10839  * @param[in] attr
10840  *   Pointer to the flow attributes.
10841  * @param[in] items
10842  *   Pointer to the list of items.
10843  * @param[in] actions
10844  *   Pointer to the list of actions.
10845  * @param[out] error
10846  *   Pointer to the error structure.
10847  *
10848  * @return
10849  *   0 on success, a negative errno value otherwise and rte_errno is set.
10850  */
10851 static int
10852 flow_dv_translate(struct rte_eth_dev *dev,
10853                   struct mlx5_flow *dev_flow,
10854                   const struct rte_flow_attr *attr,
10855                   const struct rte_flow_item items[],
10856                   const struct rte_flow_action actions[],
10857                   struct rte_flow_error *error)
10858 {
10859         struct mlx5_priv *priv = dev->data->dev_private;
10860         struct mlx5_dev_config *dev_conf = &priv->config;
10861         struct rte_flow *flow = dev_flow->flow;
10862         struct mlx5_flow_handle *handle = dev_flow->handle;
10863         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
10864         struct mlx5_flow_rss_desc *rss_desc;
10865         uint64_t item_flags = 0;
10866         uint64_t last_item = 0;
10867         uint64_t action_flags = 0;
10868         struct mlx5_flow_dv_matcher matcher = {
10869                 .mask = {
10870                         .size = sizeof(matcher.mask.buf) -
10871                                 MLX5_ST_SZ_BYTES(fte_match_set_misc4),
10872                 },
10873         };
10874         int actions_n = 0;
10875         bool actions_end = false;
10876         union {
10877                 struct mlx5_flow_dv_modify_hdr_resource res;
10878                 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
10879                             sizeof(struct mlx5_modification_cmd) *
10880                             (MLX5_MAX_MODIFY_NUM + 1)];
10881         } mhdr_dummy;
10882         struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
10883         const struct rte_flow_action_count *count = NULL;
10884         const struct rte_flow_action_age *age = NULL;
10885         union flow_dv_attr flow_attr = { .attr = 0 };
10886         uint32_t tag_be;
10887         union mlx5_flow_tbl_key tbl_key;
10888         uint32_t modify_action_position = UINT32_MAX;
10889         void *match_mask = matcher.mask.buf;
10890         void *match_value = dev_flow->dv.value.buf;
10891         uint8_t next_protocol = 0xff;
10892         struct rte_vlan_hdr vlan = { 0 };
10893         struct mlx5_flow_dv_dest_array_resource mdest_res;
10894         struct mlx5_flow_dv_sample_resource sample_res;
10895         void *sample_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
10896         const struct rte_flow_action_sample *sample = NULL;
10897         struct mlx5_flow_sub_actions_list *sample_act;
10898         uint32_t sample_act_pos = UINT32_MAX;
10899         uint32_t num_of_dest = 0;
10900         int tmp_actions_n = 0;
10901         uint32_t table;
10902         int ret = 0;
10903         const struct mlx5_flow_tunnel *tunnel;
10904         struct flow_grp_info grp_info = {
10905                 .external = !!dev_flow->external,
10906                 .transfer = !!attr->transfer,
10907                 .fdb_def_rule = !!priv->fdb_def_rule,
10908                 .skip_scale = dev_flow->skip_scale &
10909                         (1 << MLX5_SCALE_FLOW_GROUP_BIT),
10910         };
10911
10912         if (!wks)
10913                 return rte_flow_error_set(error, ENOMEM,
10914                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10915                                           NULL,
10916                                           "failed to push flow workspace");
10917         rss_desc = &wks->rss_desc;
10918         memset(&mdest_res, 0, sizeof(struct mlx5_flow_dv_dest_array_resource));
10919         memset(&sample_res, 0, sizeof(struct mlx5_flow_dv_sample_resource));
10920         mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
10921                                            MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
10922         /* update normal path action resource into last index of array */
10923         sample_act = &mdest_res.sample_act[MLX5_MAX_DEST_NUM - 1];
10924         tunnel = is_flow_tunnel_match_rule(dev, attr, items, actions) ?
10925                  flow_items_to_tunnel(items) :
10926                  is_flow_tunnel_steer_rule(dev, attr, items, actions) ?
10927                  flow_actions_to_tunnel(actions) :
10928                  dev_flow->tunnel ? dev_flow->tunnel : NULL;
10929         mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
10930                                            MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
10931         grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
10932                                 (dev, tunnel, attr, items, actions);
10933         ret = mlx5_flow_group_to_table(dev, tunnel, attr->group, &table,
10934                                        &grp_info, error);
10935         if (ret)
10936                 return ret;
10937         dev_flow->dv.group = table;
10938         if (attr->transfer)
10939                 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
10940         /* number of actions must be set to 0 in case of dirty stack. */
10941         mhdr_res->actions_num = 0;
10942         if (is_flow_tunnel_match_rule(dev, attr, items, actions)) {
10943                 /*
10944                  * do not add decap action if match rule drops packet
10945                  * HW rejects rules with decap & drop
10946                  *
10947                  * if tunnel match rule was inserted before matching tunnel set
10948                  * rule flow table used in the match rule must be registered.
10949                  * current implementation handles that in the
10950                  * flow_dv_match_register() at the function end.
10951                  */
10952                 bool add_decap = true;
10953                 const struct rte_flow_action *ptr = actions;
10954
10955                 for (; ptr->type != RTE_FLOW_ACTION_TYPE_END; ptr++) {
10956                         if (ptr->type == RTE_FLOW_ACTION_TYPE_DROP) {
10957                                 add_decap = false;
10958                                 break;
10959                         }
10960                 }
10961                 if (add_decap) {
10962                         if (flow_dv_create_action_l2_decap(dev, dev_flow,
10963                                                            attr->transfer,
10964                                                            error))
10965                                 return -rte_errno;
10966                         dev_flow->dv.actions[actions_n++] =
10967                                         dev_flow->dv.encap_decap->action;
10968                         action_flags |= MLX5_FLOW_ACTION_DECAP;
10969                 }
10970         }
10971         for (; !actions_end ; actions++) {
10972                 const struct rte_flow_action_queue *queue;
10973                 const struct rte_flow_action_rss *rss;
10974                 const struct rte_flow_action *action = actions;
10975                 const uint8_t *rss_key;
10976                 const struct rte_flow_action_meter *mtr;
10977                 struct mlx5_flow_tbl_resource *tbl;
10978                 struct mlx5_aso_age_action *age_act;
10979                 uint32_t port_id = 0;
10980                 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
10981                 int action_type = actions->type;
10982                 const struct rte_flow_action *found_action = NULL;
10983                 struct mlx5_flow_meter *fm = NULL;
10984                 uint32_t jump_group = 0;
10985
10986                 if (!mlx5_flow_os_action_supported(action_type))
10987                         return rte_flow_error_set(error, ENOTSUP,
10988                                                   RTE_FLOW_ERROR_TYPE_ACTION,
10989                                                   actions,
10990                                                   "action not supported");
10991                 switch (action_type) {
10992                 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
10993                         action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
10994                         break;
10995                 case RTE_FLOW_ACTION_TYPE_VOID:
10996                         break;
10997                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
10998                         if (flow_dv_translate_action_port_id(dev, action,
10999                                                              &port_id, error))
11000                                 return -rte_errno;
11001                         port_id_resource.port_id = port_id;
11002                         MLX5_ASSERT(!handle->rix_port_id_action);
11003                         if (flow_dv_port_id_action_resource_register
11004                             (dev, &port_id_resource, dev_flow, error))
11005                                 return -rte_errno;
11006                         dev_flow->dv.actions[actions_n++] =
11007                                         dev_flow->dv.port_id_action->action;
11008                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
11009                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_PORT_ID;
11010                         sample_act->action_flags |= MLX5_FLOW_ACTION_PORT_ID;
11011                         num_of_dest++;
11012                         break;
11013                 case RTE_FLOW_ACTION_TYPE_FLAG:
11014                         action_flags |= MLX5_FLOW_ACTION_FLAG;
11015                         dev_flow->handle->mark = 1;
11016                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
11017                                 struct rte_flow_action_mark mark = {
11018                                         .id = MLX5_FLOW_MARK_DEFAULT,
11019                                 };
11020
11021                                 if (flow_dv_convert_action_mark(dev, &mark,
11022                                                                 mhdr_res,
11023                                                                 error))
11024                                         return -rte_errno;
11025                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
11026                                 break;
11027                         }
11028                         tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
11029                         /*
11030                          * Only one FLAG or MARK is supported per device flow
11031                          * right now. So the pointer to the tag resource must be
11032                          * zero before the register process.
11033                          */
11034                         MLX5_ASSERT(!handle->dvh.rix_tag);
11035                         if (flow_dv_tag_resource_register(dev, tag_be,
11036                                                           dev_flow, error))
11037                                 return -rte_errno;
11038                         MLX5_ASSERT(dev_flow->dv.tag_resource);
11039                         dev_flow->dv.actions[actions_n++] =
11040                                         dev_flow->dv.tag_resource->action;
11041                         break;
11042                 case RTE_FLOW_ACTION_TYPE_MARK:
11043                         action_flags |= MLX5_FLOW_ACTION_MARK;
11044                         dev_flow->handle->mark = 1;
11045                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
11046                                 const struct rte_flow_action_mark *mark =
11047                                         (const struct rte_flow_action_mark *)
11048                                                 actions->conf;
11049
11050                                 if (flow_dv_convert_action_mark(dev, mark,
11051                                                                 mhdr_res,
11052                                                                 error))
11053                                         return -rte_errno;
11054                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
11055                                 break;
11056                         }
11057                         /* Fall-through */
11058                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
11059                         /* Legacy (non-extensive) MARK action. */
11060                         tag_be = mlx5_flow_mark_set
11061                               (((const struct rte_flow_action_mark *)
11062                                (actions->conf))->id);
11063                         MLX5_ASSERT(!handle->dvh.rix_tag);
11064                         if (flow_dv_tag_resource_register(dev, tag_be,
11065                                                           dev_flow, error))
11066                                 return -rte_errno;
11067                         MLX5_ASSERT(dev_flow->dv.tag_resource);
11068                         dev_flow->dv.actions[actions_n++] =
11069                                         dev_flow->dv.tag_resource->action;
11070                         break;
11071                 case RTE_FLOW_ACTION_TYPE_SET_META:
11072                         if (flow_dv_convert_action_set_meta
11073                                 (dev, mhdr_res, attr,
11074                                  (const struct rte_flow_action_set_meta *)
11075                                   actions->conf, error))
11076                                 return -rte_errno;
11077                         action_flags |= MLX5_FLOW_ACTION_SET_META;
11078                         break;
11079                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
11080                         if (flow_dv_convert_action_set_tag
11081                                 (dev, mhdr_res,
11082                                  (const struct rte_flow_action_set_tag *)
11083                                   actions->conf, error))
11084                                 return -rte_errno;
11085                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
11086                         break;
11087                 case RTE_FLOW_ACTION_TYPE_DROP:
11088                         action_flags |= MLX5_FLOW_ACTION_DROP;
11089                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_DROP;
11090                         break;
11091                 case RTE_FLOW_ACTION_TYPE_QUEUE:
11092                         queue = actions->conf;
11093                         rss_desc->queue_num = 1;
11094                         rss_desc->queue[0] = queue->index;
11095                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
11096                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
11097                         sample_act->action_flags |= MLX5_FLOW_ACTION_QUEUE;
11098                         num_of_dest++;
11099                         break;
11100                 case RTE_FLOW_ACTION_TYPE_RSS:
11101                         rss = actions->conf;
11102                         memcpy(rss_desc->queue, rss->queue,
11103                                rss->queue_num * sizeof(uint16_t));
11104                         rss_desc->queue_num = rss->queue_num;
11105                         /* NULL RSS key indicates default RSS key. */
11106                         rss_key = !rss->key ? rss_hash_default_key : rss->key;
11107                         memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
11108                         /*
11109                          * rss->level and rss.types should be set in advance
11110                          * when expanding items for RSS.
11111                          */
11112                         action_flags |= MLX5_FLOW_ACTION_RSS;
11113                         dev_flow->handle->fate_action = rss_desc->shared_rss ?
11114                                 MLX5_FLOW_FATE_SHARED_RSS :
11115                                 MLX5_FLOW_FATE_QUEUE;
11116                         break;
11117                 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
11118                         flow->age = (uint32_t)(uintptr_t)(action->conf);
11119                         age_act = flow_aso_age_get_by_idx(dev, flow->age);
11120                         __atomic_fetch_add(&age_act->refcnt, 1,
11121                                            __ATOMIC_RELAXED);
11122                         dev_flow->dv.actions[actions_n++] = age_act->dr_action;
11123                         action_flags |= MLX5_FLOW_ACTION_AGE;
11124                         break;
11125                 case RTE_FLOW_ACTION_TYPE_AGE:
11126                         if (priv->sh->flow_hit_aso_en && attr->group) {
11127                                 /*
11128                                  * Create one shared age action, to be used
11129                                  * by all sub-flows.
11130                                  */
11131                                 if (!flow->age) {
11132                                         flow->age =
11133                                                 flow_dv_translate_create_aso_age
11134                                                         (dev, action->conf,
11135                                                          error);
11136                                         if (!flow->age)
11137                                                 return rte_flow_error_set
11138                                                 (error, rte_errno,
11139                                                  RTE_FLOW_ERROR_TYPE_ACTION,
11140                                                  NULL,
11141                                                  "can't create ASO age action");
11142                                 }
11143                                 dev_flow->dv.actions[actions_n++] =
11144                                           (flow_aso_age_get_by_idx
11145                                                 (dev, flow->age))->dr_action;
11146                                 action_flags |= MLX5_FLOW_ACTION_AGE;
11147                                 break;
11148                         }
11149                         /* Fall-through */
11150                 case RTE_FLOW_ACTION_TYPE_COUNT:
11151                         if (!dev_conf->devx) {
11152                                 return rte_flow_error_set
11153                                               (error, ENOTSUP,
11154                                                RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11155                                                NULL,
11156                                                "count action not supported");
11157                         }
11158                         /* Save information first, will apply later. */
11159                         if (actions->type == RTE_FLOW_ACTION_TYPE_COUNT)
11160                                 count = action->conf;
11161                         else
11162                                 age = action->conf;
11163                         action_flags |= MLX5_FLOW_ACTION_COUNT;
11164                         break;
11165                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
11166                         dev_flow->dv.actions[actions_n++] =
11167                                                 priv->sh->pop_vlan_action;
11168                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
11169                         break;
11170                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
11171                         if (!(action_flags &
11172                               MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
11173                                 flow_dev_get_vlan_info_from_items(items, &vlan);
11174                         vlan.eth_proto = rte_be_to_cpu_16
11175                              ((((const struct rte_flow_action_of_push_vlan *)
11176                                                    actions->conf)->ethertype));
11177                         found_action = mlx5_flow_find_action
11178                                         (actions + 1,
11179                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
11180                         if (found_action)
11181                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
11182                         found_action = mlx5_flow_find_action
11183                                         (actions + 1,
11184                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
11185                         if (found_action)
11186                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
11187                         if (flow_dv_create_action_push_vlan
11188                                             (dev, attr, &vlan, dev_flow, error))
11189                                 return -rte_errno;
11190                         dev_flow->dv.actions[actions_n++] =
11191                                         dev_flow->dv.push_vlan_res->action;
11192                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
11193                         break;
11194                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
11195                         /* of_vlan_push action handled this action */
11196                         MLX5_ASSERT(action_flags &
11197                                     MLX5_FLOW_ACTION_OF_PUSH_VLAN);
11198                         break;
11199                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
11200                         if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
11201                                 break;
11202                         flow_dev_get_vlan_info_from_items(items, &vlan);
11203                         mlx5_update_vlan_vid_pcp(actions, &vlan);
11204                         /* If no VLAN push - this is a modify header action */
11205                         if (flow_dv_convert_action_modify_vlan_vid
11206                                                 (mhdr_res, actions, error))
11207                                 return -rte_errno;
11208                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
11209                         break;
11210                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
11211                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
11212                         if (flow_dv_create_action_l2_encap(dev, actions,
11213                                                            dev_flow,
11214                                                            attr->transfer,
11215                                                            error))
11216                                 return -rte_errno;
11217                         dev_flow->dv.actions[actions_n++] =
11218                                         dev_flow->dv.encap_decap->action;
11219                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
11220                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
11221                                 sample_act->action_flags |=
11222                                                         MLX5_FLOW_ACTION_ENCAP;
11223                         break;
11224                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
11225                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
11226                         if (flow_dv_create_action_l2_decap(dev, dev_flow,
11227                                                            attr->transfer,
11228                                                            error))
11229                                 return -rte_errno;
11230                         dev_flow->dv.actions[actions_n++] =
11231                                         dev_flow->dv.encap_decap->action;
11232                         action_flags |= MLX5_FLOW_ACTION_DECAP;
11233                         break;
11234                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
11235                         /* Handle encap with preceding decap. */
11236                         if (action_flags & MLX5_FLOW_ACTION_DECAP) {
11237                                 if (flow_dv_create_action_raw_encap
11238                                         (dev, actions, dev_flow, attr, error))
11239                                         return -rte_errno;
11240                                 dev_flow->dv.actions[actions_n++] =
11241                                         dev_flow->dv.encap_decap->action;
11242                         } else {
11243                                 /* Handle encap without preceding decap. */
11244                                 if (flow_dv_create_action_l2_encap
11245                                     (dev, actions, dev_flow, attr->transfer,
11246                                      error))
11247                                         return -rte_errno;
11248                                 dev_flow->dv.actions[actions_n++] =
11249                                         dev_flow->dv.encap_decap->action;
11250                         }
11251                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
11252                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
11253                                 sample_act->action_flags |=
11254                                                         MLX5_FLOW_ACTION_ENCAP;
11255                         break;
11256                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
11257                         while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
11258                                 ;
11259                         if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
11260                                 if (flow_dv_create_action_l2_decap
11261                                     (dev, dev_flow, attr->transfer, error))
11262                                         return -rte_errno;
11263                                 dev_flow->dv.actions[actions_n++] =
11264                                         dev_flow->dv.encap_decap->action;
11265                         }
11266                         /* If decap is followed by encap, handle it at encap. */
11267                         action_flags |= MLX5_FLOW_ACTION_DECAP;
11268                         break;
11269                 case RTE_FLOW_ACTION_TYPE_JUMP:
11270                         jump_group = ((const struct rte_flow_action_jump *)
11271                                                         action->conf)->group;
11272                         grp_info.std_tbl_fix = 0;
11273                         if (dev_flow->skip_scale &
11274                                 (1 << MLX5_SCALE_JUMP_FLOW_GROUP_BIT))
11275                                 grp_info.skip_scale = 1;
11276                         else
11277                                 grp_info.skip_scale = 0;
11278                         ret = mlx5_flow_group_to_table(dev, tunnel,
11279                                                        jump_group,
11280                                                        &table,
11281                                                        &grp_info, error);
11282                         if (ret)
11283                                 return ret;
11284                         tbl = flow_dv_tbl_resource_get(dev, table, attr->egress,
11285                                                        attr->transfer,
11286                                                        !!dev_flow->external,
11287                                                        tunnel, jump_group, 0,
11288                                                        error);
11289                         if (!tbl)
11290                                 return rte_flow_error_set
11291                                                 (error, errno,
11292                                                  RTE_FLOW_ERROR_TYPE_ACTION,
11293                                                  NULL,
11294                                                  "cannot create jump action.");
11295                         if (flow_dv_jump_tbl_resource_register
11296                             (dev, tbl, dev_flow, error)) {
11297                                 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
11298                                 return rte_flow_error_set
11299                                                 (error, errno,
11300                                                  RTE_FLOW_ERROR_TYPE_ACTION,
11301                                                  NULL,
11302                                                  "cannot create jump action.");
11303                         }
11304                         dev_flow->dv.actions[actions_n++] =
11305                                         dev_flow->dv.jump->action;
11306                         action_flags |= MLX5_FLOW_ACTION_JUMP;
11307                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_JUMP;
11308                         sample_act->action_flags |= MLX5_FLOW_ACTION_JUMP;
11309                         num_of_dest++;
11310                         break;
11311                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
11312                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
11313                         if (flow_dv_convert_action_modify_mac
11314                                         (mhdr_res, actions, error))
11315                                 return -rte_errno;
11316                         action_flags |= actions->type ==
11317                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
11318                                         MLX5_FLOW_ACTION_SET_MAC_SRC :
11319                                         MLX5_FLOW_ACTION_SET_MAC_DST;
11320                         break;
11321                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
11322                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
11323                         if (flow_dv_convert_action_modify_ipv4
11324                                         (mhdr_res, actions, error))
11325                                 return -rte_errno;
11326                         action_flags |= actions->type ==
11327                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
11328                                         MLX5_FLOW_ACTION_SET_IPV4_SRC :
11329                                         MLX5_FLOW_ACTION_SET_IPV4_DST;
11330                         break;
11331                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
11332                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
11333                         if (flow_dv_convert_action_modify_ipv6
11334                                         (mhdr_res, actions, error))
11335                                 return -rte_errno;
11336                         action_flags |= actions->type ==
11337                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
11338                                         MLX5_FLOW_ACTION_SET_IPV6_SRC :
11339                                         MLX5_FLOW_ACTION_SET_IPV6_DST;
11340                         break;
11341                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
11342                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
11343                         if (flow_dv_convert_action_modify_tp
11344                                         (mhdr_res, actions, items,
11345                                          &flow_attr, dev_flow, !!(action_flags &
11346                                          MLX5_FLOW_ACTION_DECAP), error))
11347                                 return -rte_errno;
11348                         action_flags |= actions->type ==
11349                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
11350                                         MLX5_FLOW_ACTION_SET_TP_SRC :
11351                                         MLX5_FLOW_ACTION_SET_TP_DST;
11352                         break;
11353                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
11354                         if (flow_dv_convert_action_modify_dec_ttl
11355                                         (mhdr_res, items, &flow_attr, dev_flow,
11356                                          !!(action_flags &
11357                                          MLX5_FLOW_ACTION_DECAP), error))
11358                                 return -rte_errno;
11359                         action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
11360                         break;
11361                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
11362                         if (flow_dv_convert_action_modify_ttl
11363                                         (mhdr_res, actions, items, &flow_attr,
11364                                          dev_flow, !!(action_flags &
11365                                          MLX5_FLOW_ACTION_DECAP), error))
11366                                 return -rte_errno;
11367                         action_flags |= MLX5_FLOW_ACTION_SET_TTL;
11368                         break;
11369                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
11370                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
11371                         if (flow_dv_convert_action_modify_tcp_seq
11372                                         (mhdr_res, actions, error))
11373                                 return -rte_errno;
11374                         action_flags |= actions->type ==
11375                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
11376                                         MLX5_FLOW_ACTION_INC_TCP_SEQ :
11377                                         MLX5_FLOW_ACTION_DEC_TCP_SEQ;
11378                         break;
11379
11380                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
11381                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
11382                         if (flow_dv_convert_action_modify_tcp_ack
11383                                         (mhdr_res, actions, error))
11384                                 return -rte_errno;
11385                         action_flags |= actions->type ==
11386                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
11387                                         MLX5_FLOW_ACTION_INC_TCP_ACK :
11388                                         MLX5_FLOW_ACTION_DEC_TCP_ACK;
11389                         break;
11390                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
11391                         if (flow_dv_convert_action_set_reg
11392                                         (mhdr_res, actions, error))
11393                                 return -rte_errno;
11394                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
11395                         break;
11396                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
11397                         if (flow_dv_convert_action_copy_mreg
11398                                         (dev, mhdr_res, actions, error))
11399                                 return -rte_errno;
11400                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
11401                         break;
11402                 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
11403                         action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
11404                         dev_flow->handle->fate_action =
11405                                         MLX5_FLOW_FATE_DEFAULT_MISS;
11406                         break;
11407                 case RTE_FLOW_ACTION_TYPE_METER:
11408                         mtr = actions->conf;
11409                         if (!flow->meter) {
11410                                 fm = mlx5_flow_meter_attach(priv, mtr->mtr_id,
11411                                                             attr, error);
11412                                 if (!fm)
11413                                         return rte_flow_error_set(error,
11414                                                 rte_errno,
11415                                                 RTE_FLOW_ERROR_TYPE_ACTION,
11416                                                 NULL,
11417                                                 "meter not found "
11418                                                 "or invalid parameters");
11419                                 flow->meter = fm->idx;
11420                         }
11421                         /* Set the meter action. */
11422                         if (!fm) {
11423                                 fm = mlx5_ipool_get(priv->sh->ipool
11424                                                 [MLX5_IPOOL_MTR], flow->meter);
11425                                 if (!fm)
11426                                         return rte_flow_error_set(error,
11427                                                 rte_errno,
11428                                                 RTE_FLOW_ERROR_TYPE_ACTION,
11429                                                 NULL,
11430                                                 "meter not found "
11431                                                 "or invalid parameters");
11432                         }
11433                         dev_flow->dv.actions[actions_n++] =
11434                                 fm->mfts->meter_action;
11435                         action_flags |= MLX5_FLOW_ACTION_METER;
11436                         break;
11437                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
11438                         if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
11439                                                               actions, error))
11440                                 return -rte_errno;
11441                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
11442                         break;
11443                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
11444                         if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
11445                                                               actions, error))
11446                                 return -rte_errno;
11447                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
11448                         break;
11449                 case RTE_FLOW_ACTION_TYPE_SAMPLE:
11450                         sample_act_pos = actions_n;
11451                         sample = (const struct rte_flow_action_sample *)
11452                                  action->conf;
11453                         actions_n++;
11454                         action_flags |= MLX5_FLOW_ACTION_SAMPLE;
11455                         /* put encap action into group if work with port id */
11456                         if ((action_flags & MLX5_FLOW_ACTION_ENCAP) &&
11457                             (action_flags & MLX5_FLOW_ACTION_PORT_ID))
11458                                 sample_act->action_flags |=
11459                                                         MLX5_FLOW_ACTION_ENCAP;
11460                         break;
11461                 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
11462                         if (flow_dv_convert_action_modify_field
11463                                         (dev, mhdr_res, actions, attr, error))
11464                                 return -rte_errno;
11465                         action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
11466                         break;
11467                 case RTE_FLOW_ACTION_TYPE_END:
11468                         actions_end = true;
11469                         if (mhdr_res->actions_num) {
11470                                 /* create modify action if needed. */
11471                                 if (flow_dv_modify_hdr_resource_register
11472                                         (dev, mhdr_res, dev_flow, error))
11473                                         return -rte_errno;
11474                                 dev_flow->dv.actions[modify_action_position] =
11475                                         handle->dvh.modify_hdr->action;
11476                         }
11477                         if (action_flags & MLX5_FLOW_ACTION_COUNT) {
11478                                 /*
11479                                  * Create one count action, to be used
11480                                  * by all sub-flows.
11481                                  */
11482                                 if (!flow->counter) {
11483                                         flow->counter =
11484                                                 flow_dv_translate_create_counter
11485                                                         (dev, dev_flow, count,
11486                                                          age);
11487                                         if (!flow->counter)
11488                                                 return rte_flow_error_set
11489                                                 (error, rte_errno,
11490                                                  RTE_FLOW_ERROR_TYPE_ACTION,
11491                                                  NULL, "cannot create counter"
11492                                                  " object.");
11493                                 }
11494                                 dev_flow->dv.actions[actions_n] =
11495                                           (flow_dv_counter_get_by_idx(dev,
11496                                           flow->counter, NULL))->action;
11497                                 actions_n++;
11498                         }
11499                 default:
11500                         break;
11501                 }
11502                 if (mhdr_res->actions_num &&
11503                     modify_action_position == UINT32_MAX)
11504                         modify_action_position = actions_n++;
11505         }
11506         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
11507                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
11508                 int item_type = items->type;
11509
11510                 if (!mlx5_flow_os_item_supported(item_type))
11511                         return rte_flow_error_set(error, ENOTSUP,
11512                                                   RTE_FLOW_ERROR_TYPE_ITEM,
11513                                                   NULL, "item not supported");
11514                 switch (item_type) {
11515                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
11516                         flow_dv_translate_item_port_id
11517                                 (dev, match_mask, match_value, items, attr);
11518                         last_item = MLX5_FLOW_ITEM_PORT_ID;
11519                         break;
11520                 case RTE_FLOW_ITEM_TYPE_ETH:
11521                         flow_dv_translate_item_eth(match_mask, match_value,
11522                                                    items, tunnel,
11523                                                    dev_flow->dv.group);
11524                         matcher.priority = action_flags &
11525                                         MLX5_FLOW_ACTION_DEFAULT_MISS &&
11526                                         !dev_flow->external ?
11527                                         MLX5_PRIORITY_MAP_L3 :
11528                                         MLX5_PRIORITY_MAP_L2;
11529                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
11530                                              MLX5_FLOW_LAYER_OUTER_L2;
11531                         break;
11532                 case RTE_FLOW_ITEM_TYPE_VLAN:
11533                         flow_dv_translate_item_vlan(dev_flow,
11534                                                     match_mask, match_value,
11535                                                     items, tunnel,
11536                                                     dev_flow->dv.group);
11537                         matcher.priority = MLX5_PRIORITY_MAP_L2;
11538                         last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
11539                                               MLX5_FLOW_LAYER_INNER_VLAN) :
11540                                              (MLX5_FLOW_LAYER_OUTER_L2 |
11541                                               MLX5_FLOW_LAYER_OUTER_VLAN);
11542                         break;
11543                 case RTE_FLOW_ITEM_TYPE_IPV4:
11544                         mlx5_flow_tunnel_ip_check(items, next_protocol,
11545                                                   &item_flags, &tunnel);
11546                         flow_dv_translate_item_ipv4(match_mask, match_value,
11547                                                     items, tunnel,
11548                                                     dev_flow->dv.group);
11549                         matcher.priority = MLX5_PRIORITY_MAP_L3;
11550                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
11551                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
11552                         if (items->mask != NULL &&
11553                             ((const struct rte_flow_item_ipv4 *)
11554                              items->mask)->hdr.next_proto_id) {
11555                                 next_protocol =
11556                                         ((const struct rte_flow_item_ipv4 *)
11557                                          (items->spec))->hdr.next_proto_id;
11558                                 next_protocol &=
11559                                         ((const struct rte_flow_item_ipv4 *)
11560                                          (items->mask))->hdr.next_proto_id;
11561                         } else {
11562                                 /* Reset for inner layer. */
11563                                 next_protocol = 0xff;
11564                         }
11565                         break;
11566                 case RTE_FLOW_ITEM_TYPE_IPV6:
11567                         mlx5_flow_tunnel_ip_check(items, next_protocol,
11568                                                   &item_flags, &tunnel);
11569                         flow_dv_translate_item_ipv6(match_mask, match_value,
11570                                                     items, tunnel,
11571                                                     dev_flow->dv.group);
11572                         matcher.priority = MLX5_PRIORITY_MAP_L3;
11573                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
11574                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
11575                         if (items->mask != NULL &&
11576                             ((const struct rte_flow_item_ipv6 *)
11577                              items->mask)->hdr.proto) {
11578                                 next_protocol =
11579                                         ((const struct rte_flow_item_ipv6 *)
11580                                          items->spec)->hdr.proto;
11581                                 next_protocol &=
11582                                         ((const struct rte_flow_item_ipv6 *)
11583                                          items->mask)->hdr.proto;
11584                         } else {
11585                                 /* Reset for inner layer. */
11586                                 next_protocol = 0xff;
11587                         }
11588                         break;
11589                 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
11590                         flow_dv_translate_item_ipv6_frag_ext(match_mask,
11591                                                              match_value,
11592                                                              items, tunnel);
11593                         last_item = tunnel ?
11594                                         MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
11595                                         MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
11596                         if (items->mask != NULL &&
11597                             ((const struct rte_flow_item_ipv6_frag_ext *)
11598                              items->mask)->hdr.next_header) {
11599                                 next_protocol =
11600                                 ((const struct rte_flow_item_ipv6_frag_ext *)
11601                                  items->spec)->hdr.next_header;
11602                                 next_protocol &=
11603                                 ((const struct rte_flow_item_ipv6_frag_ext *)
11604                                  items->mask)->hdr.next_header;
11605                         } else {
11606                                 /* Reset for inner layer. */
11607                                 next_protocol = 0xff;
11608                         }
11609                         break;
11610                 case RTE_FLOW_ITEM_TYPE_TCP:
11611                         flow_dv_translate_item_tcp(match_mask, match_value,
11612                                                    items, tunnel);
11613                         matcher.priority = MLX5_PRIORITY_MAP_L4;
11614                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
11615                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
11616                         break;
11617                 case RTE_FLOW_ITEM_TYPE_UDP:
11618                         flow_dv_translate_item_udp(match_mask, match_value,
11619                                                    items, tunnel);
11620                         matcher.priority = MLX5_PRIORITY_MAP_L4;
11621                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
11622                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
11623                         break;
11624                 case RTE_FLOW_ITEM_TYPE_GRE:
11625                         flow_dv_translate_item_gre(match_mask, match_value,
11626                                                    items, tunnel);
11627                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11628                         last_item = MLX5_FLOW_LAYER_GRE;
11629                         break;
11630                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
11631                         flow_dv_translate_item_gre_key(match_mask,
11632                                                        match_value, items);
11633                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
11634                         break;
11635                 case RTE_FLOW_ITEM_TYPE_NVGRE:
11636                         flow_dv_translate_item_nvgre(match_mask, match_value,
11637                                                      items, tunnel);
11638                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11639                         last_item = MLX5_FLOW_LAYER_GRE;
11640                         break;
11641                 case RTE_FLOW_ITEM_TYPE_VXLAN:
11642                         flow_dv_translate_item_vxlan(match_mask, match_value,
11643                                                      items, tunnel);
11644                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11645                         last_item = MLX5_FLOW_LAYER_VXLAN;
11646                         break;
11647                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
11648                         flow_dv_translate_item_vxlan_gpe(match_mask,
11649                                                          match_value, items,
11650                                                          tunnel);
11651                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11652                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
11653                         break;
11654                 case RTE_FLOW_ITEM_TYPE_GENEVE:
11655                         flow_dv_translate_item_geneve(match_mask, match_value,
11656                                                       items, tunnel);
11657                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11658                         last_item = MLX5_FLOW_LAYER_GENEVE;
11659                         break;
11660                 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
11661                         ret = flow_dv_translate_item_geneve_opt(dev, match_mask,
11662                                                           match_value,
11663                                                           items, error);
11664                         if (ret)
11665                                 return rte_flow_error_set(error, -ret,
11666                                         RTE_FLOW_ERROR_TYPE_ITEM, NULL,
11667                                         "cannot create GENEVE TLV option");
11668                         flow->geneve_tlv_option = 1;
11669                         last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
11670                         break;
11671                 case RTE_FLOW_ITEM_TYPE_MPLS:
11672                         flow_dv_translate_item_mpls(match_mask, match_value,
11673                                                     items, last_item, tunnel);
11674                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11675                         last_item = MLX5_FLOW_LAYER_MPLS;
11676                         break;
11677                 case RTE_FLOW_ITEM_TYPE_MARK:
11678                         flow_dv_translate_item_mark(dev, match_mask,
11679                                                     match_value, items);
11680                         last_item = MLX5_FLOW_ITEM_MARK;
11681                         break;
11682                 case RTE_FLOW_ITEM_TYPE_META:
11683                         flow_dv_translate_item_meta(dev, match_mask,
11684                                                     match_value, attr, items);
11685                         last_item = MLX5_FLOW_ITEM_METADATA;
11686                         break;
11687                 case RTE_FLOW_ITEM_TYPE_ICMP:
11688                         flow_dv_translate_item_icmp(match_mask, match_value,
11689                                                     items, tunnel);
11690                         last_item = MLX5_FLOW_LAYER_ICMP;
11691                         break;
11692                 case RTE_FLOW_ITEM_TYPE_ICMP6:
11693                         flow_dv_translate_item_icmp6(match_mask, match_value,
11694                                                       items, tunnel);
11695                         last_item = MLX5_FLOW_LAYER_ICMP6;
11696                         break;
11697                 case RTE_FLOW_ITEM_TYPE_TAG:
11698                         flow_dv_translate_item_tag(dev, match_mask,
11699                                                    match_value, items);
11700                         last_item = MLX5_FLOW_ITEM_TAG;
11701                         break;
11702                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
11703                         flow_dv_translate_mlx5_item_tag(dev, match_mask,
11704                                                         match_value, items);
11705                         last_item = MLX5_FLOW_ITEM_TAG;
11706                         break;
11707                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
11708                         flow_dv_translate_item_tx_queue(dev, match_mask,
11709                                                         match_value,
11710                                                         items);
11711                         last_item = MLX5_FLOW_ITEM_TX_QUEUE;
11712                         break;
11713                 case RTE_FLOW_ITEM_TYPE_GTP:
11714                         flow_dv_translate_item_gtp(match_mask, match_value,
11715                                                    items, tunnel);
11716                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11717                         last_item = MLX5_FLOW_LAYER_GTP;
11718                         break;
11719                 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
11720                         ret = flow_dv_translate_item_gtp_psc(match_mask,
11721                                                           match_value,
11722                                                           items);
11723                         if (ret)
11724                                 return rte_flow_error_set(error, -ret,
11725                                         RTE_FLOW_ERROR_TYPE_ITEM, NULL,
11726                                         "cannot create GTP PSC item");
11727                         last_item = MLX5_FLOW_LAYER_GTP_PSC;
11728                         break;
11729                 case RTE_FLOW_ITEM_TYPE_ECPRI:
11730                         if (!mlx5_flex_parser_ecpri_exist(dev)) {
11731                                 /* Create it only the first time to be used. */
11732                                 ret = mlx5_flex_parser_ecpri_alloc(dev);
11733                                 if (ret)
11734                                         return rte_flow_error_set
11735                                                 (error, -ret,
11736                                                 RTE_FLOW_ERROR_TYPE_ITEM,
11737                                                 NULL,
11738                                                 "cannot create eCPRI parser");
11739                         }
11740                         /* Adjust the length matcher and device flow value. */
11741                         matcher.mask.size = MLX5_ST_SZ_BYTES(fte_match_param);
11742                         dev_flow->dv.value.size =
11743                                         MLX5_ST_SZ_BYTES(fte_match_param);
11744                         flow_dv_translate_item_ecpri(dev, match_mask,
11745                                                      match_value, items);
11746                         /* No other protocol should follow eCPRI layer. */
11747                         last_item = MLX5_FLOW_LAYER_ECPRI;
11748                         break;
11749                 default:
11750                         break;
11751                 }
11752                 item_flags |= last_item;
11753         }
11754         /*
11755          * When E-Switch mode is enabled, we have two cases where we need to
11756          * set the source port manually.
11757          * The first one, is in case of Nic steering rule, and the second is
11758          * E-Switch rule where no port_id item was found. In both cases
11759          * the source port is set according the current port in use.
11760          */
11761         if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
11762             (priv->representor || priv->master)) {
11763                 if (flow_dv_translate_item_port_id(dev, match_mask,
11764                                                    match_value, NULL, attr))
11765                         return -rte_errno;
11766         }
11767 #ifdef RTE_LIBRTE_MLX5_DEBUG
11768         MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
11769                                               dev_flow->dv.value.buf));
11770 #endif
11771         /*
11772          * Layers may be already initialized from prefix flow if this dev_flow
11773          * is the suffix flow.
11774          */
11775         handle->layers |= item_flags;
11776         if (action_flags & MLX5_FLOW_ACTION_RSS)
11777                 flow_dv_hashfields_set(dev_flow, rss_desc);
11778         /* If has RSS action in the sample action, the Sample/Mirror resource
11779          * should be registered after the hash filed be update.
11780          */
11781         if (action_flags & MLX5_FLOW_ACTION_SAMPLE) {
11782                 ret = flow_dv_translate_action_sample(dev,
11783                                                       sample,
11784                                                       dev_flow, attr,
11785                                                       &num_of_dest,
11786                                                       sample_actions,
11787                                                       &sample_res,
11788                                                       error);
11789                 if (ret < 0)
11790                         return ret;
11791                 ret = flow_dv_create_action_sample(dev,
11792                                                    dev_flow,
11793                                                    num_of_dest,
11794                                                    &sample_res,
11795                                                    &mdest_res,
11796                                                    sample_actions,
11797                                                    action_flags,
11798                                                    error);
11799                 if (ret < 0)
11800                         return rte_flow_error_set
11801                                                 (error, rte_errno,
11802                                                 RTE_FLOW_ERROR_TYPE_ACTION,
11803                                                 NULL,
11804                                                 "cannot create sample action");
11805                 if (num_of_dest > 1) {
11806                         dev_flow->dv.actions[sample_act_pos] =
11807                         dev_flow->dv.dest_array_res->action;
11808                 } else {
11809                         dev_flow->dv.actions[sample_act_pos] =
11810                         dev_flow->dv.sample_res->verbs_action;
11811                 }
11812         }
11813         /*
11814          * For multiple destination (sample action with ratio=1), the encap
11815          * action and port id action will be combined into group action.
11816          * So need remove the original these actions in the flow and only
11817          * use the sample action instead of.
11818          */
11819         if (num_of_dest > 1 &&
11820             (sample_act->dr_port_id_action || sample_act->dr_jump_action)) {
11821                 int i;
11822                 void *temp_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
11823
11824                 for (i = 0; i < actions_n; i++) {
11825                         if ((sample_act->dr_encap_action &&
11826                                 sample_act->dr_encap_action ==
11827                                 dev_flow->dv.actions[i]) ||
11828                                 (sample_act->dr_port_id_action &&
11829                                 sample_act->dr_port_id_action ==
11830                                 dev_flow->dv.actions[i]) ||
11831                                 (sample_act->dr_jump_action &&
11832                                 sample_act->dr_jump_action ==
11833                                 dev_flow->dv.actions[i]))
11834                                 continue;
11835                         temp_actions[tmp_actions_n++] = dev_flow->dv.actions[i];
11836                 }
11837                 memcpy((void *)dev_flow->dv.actions,
11838                                 (void *)temp_actions,
11839                                 tmp_actions_n * sizeof(void *));
11840                 actions_n = tmp_actions_n;
11841         }
11842         dev_flow->dv.actions_n = actions_n;
11843         dev_flow->act_flags = action_flags;
11844         /* Register matcher. */
11845         matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
11846                                     matcher.mask.size);
11847         matcher.priority = mlx5_get_matcher_priority(dev, attr,
11848                                         matcher.priority);
11849         /* reserved field no needs to be set to 0 here. */
11850         tbl_key.domain = attr->transfer;
11851         tbl_key.direction = attr->egress;
11852         tbl_key.table_id = dev_flow->dv.group;
11853         if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow,
11854                                      tunnel, attr->group, error))
11855                 return -rte_errno;
11856         return 0;
11857 }
11858
11859 /**
11860  * Set hash RX queue by hash fields (see enum ibv_rx_hash_fields)
11861  * and tunnel.
11862  *
11863  * @param[in, out] action
11864  *   Shred RSS action holding hash RX queue objects.
11865  * @param[in] hash_fields
11866  *   Defines combination of packet fields to participate in RX hash.
11867  * @param[in] tunnel
11868  *   Tunnel type
11869  * @param[in] hrxq_idx
11870  *   Hash RX queue index to set.
11871  *
11872  * @return
11873  *   0 on success, otherwise negative errno value.
11874  */
11875 static int
11876 __flow_dv_action_rss_hrxq_set(struct mlx5_shared_action_rss *action,
11877                               const uint64_t hash_fields,
11878                               const int tunnel,
11879                               uint32_t hrxq_idx)
11880 {
11881         uint32_t *hrxqs = tunnel ? action->hrxq : action->hrxq_tunnel;
11882
11883         switch (hash_fields & ~IBV_RX_HASH_INNER) {
11884         case MLX5_RSS_HASH_IPV4:
11885                 hrxqs[0] = hrxq_idx;
11886                 return 0;
11887         case MLX5_RSS_HASH_IPV4_TCP:
11888                 hrxqs[1] = hrxq_idx;
11889                 return 0;
11890         case MLX5_RSS_HASH_IPV4_UDP:
11891                 hrxqs[2] = hrxq_idx;
11892                 return 0;
11893         case MLX5_RSS_HASH_IPV6:
11894                 hrxqs[3] = hrxq_idx;
11895                 return 0;
11896         case MLX5_RSS_HASH_IPV6_TCP:
11897                 hrxqs[4] = hrxq_idx;
11898                 return 0;
11899         case MLX5_RSS_HASH_IPV6_UDP:
11900                 hrxqs[5] = hrxq_idx;
11901                 return 0;
11902         case MLX5_RSS_HASH_NONE:
11903                 hrxqs[6] = hrxq_idx;
11904                 return 0;
11905         default:
11906                 return -1;
11907         }
11908 }
11909
11910 /**
11911  * Look up for hash RX queue by hash fields (see enum ibv_rx_hash_fields)
11912  * and tunnel.
11913  *
11914  * @param[in] dev
11915  *   Pointer to the Ethernet device structure.
11916  * @param[in] idx
11917  *   Shared RSS action ID holding hash RX queue objects.
11918  * @param[in] hash_fields
11919  *   Defines combination of packet fields to participate in RX hash.
11920  * @param[in] tunnel
11921  *   Tunnel type
11922  *
11923  * @return
11924  *   Valid hash RX queue index, otherwise 0.
11925  */
11926 static uint32_t
11927 __flow_dv_action_rss_hrxq_lookup(struct rte_eth_dev *dev, uint32_t idx,
11928                                  const uint64_t hash_fields,
11929                                  const int tunnel)
11930 {
11931         struct mlx5_priv *priv = dev->data->dev_private;
11932         struct mlx5_shared_action_rss *shared_rss =
11933             mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
11934         const uint32_t *hrxqs = tunnel ? shared_rss->hrxq :
11935                                                         shared_rss->hrxq_tunnel;
11936
11937         switch (hash_fields & ~IBV_RX_HASH_INNER) {
11938         case MLX5_RSS_HASH_IPV4:
11939                 return hrxqs[0];
11940         case MLX5_RSS_HASH_IPV4_TCP:
11941                 return hrxqs[1];
11942         case MLX5_RSS_HASH_IPV4_UDP:
11943                 return hrxqs[2];
11944         case MLX5_RSS_HASH_IPV6:
11945                 return hrxqs[3];
11946         case MLX5_RSS_HASH_IPV6_TCP:
11947                 return hrxqs[4];
11948         case MLX5_RSS_HASH_IPV6_UDP:
11949                 return hrxqs[5];
11950         case MLX5_RSS_HASH_NONE:
11951                 return hrxqs[6];
11952         default:
11953                 return 0;
11954         }
11955 }
11956
11957 /**
11958  * Apply the flow to the NIC, lock free,
11959  * (mutex should be acquired by caller).
11960  *
11961  * @param[in] dev
11962  *   Pointer to the Ethernet device structure.
11963  * @param[in, out] flow
11964  *   Pointer to flow structure.
11965  * @param[out] error
11966  *   Pointer to error structure.
11967  *
11968  * @return
11969  *   0 on success, a negative errno value otherwise and rte_errno is set.
11970  */
11971 static int
11972 flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
11973               struct rte_flow_error *error)
11974 {
11975         struct mlx5_flow_dv_workspace *dv;
11976         struct mlx5_flow_handle *dh;
11977         struct mlx5_flow_handle_dv *dv_h;
11978         struct mlx5_flow *dev_flow;
11979         struct mlx5_priv *priv = dev->data->dev_private;
11980         uint32_t handle_idx;
11981         int n;
11982         int err;
11983         int idx;
11984         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
11985         struct mlx5_flow_rss_desc *rss_desc = &wks->rss_desc;
11986
11987         MLX5_ASSERT(wks);
11988         for (idx = wks->flow_idx - 1; idx >= 0; idx--) {
11989                 dev_flow = &wks->flows[idx];
11990                 dv = &dev_flow->dv;
11991                 dh = dev_flow->handle;
11992                 dv_h = &dh->dvh;
11993                 n = dv->actions_n;
11994                 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
11995                         if (dv->transfer) {
11996                                 dv->actions[n++] = priv->sh->esw_drop_action;
11997                         } else {
11998                                 MLX5_ASSERT(priv->drop_queue.hrxq);
11999                                 dv->actions[n++] =
12000                                                 priv->drop_queue.hrxq->action;
12001                         }
12002                 } else if ((dh->fate_action == MLX5_FLOW_FATE_QUEUE &&
12003                            !dv_h->rix_sample && !dv_h->rix_dest_array)) {
12004                         struct mlx5_hrxq *hrxq;
12005                         uint32_t hrxq_idx;
12006
12007                         hrxq = flow_dv_hrxq_prepare(dev, dev_flow, rss_desc,
12008                                                     &hrxq_idx);
12009                         if (!hrxq) {
12010                                 rte_flow_error_set
12011                                         (error, rte_errno,
12012                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12013                                          "cannot get hash queue");
12014                                 goto error;
12015                         }
12016                         dh->rix_hrxq = hrxq_idx;
12017                         dv->actions[n++] = hrxq->action;
12018                 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
12019                         struct mlx5_hrxq *hrxq = NULL;
12020                         uint32_t hrxq_idx;
12021
12022                         hrxq_idx = __flow_dv_action_rss_hrxq_lookup(dev,
12023                                                 rss_desc->shared_rss,
12024                                                 dev_flow->hash_fields,
12025                                                 !!(dh->layers &
12026                                                 MLX5_FLOW_LAYER_TUNNEL));
12027                         if (hrxq_idx)
12028                                 hrxq = mlx5_ipool_get
12029                                         (priv->sh->ipool[MLX5_IPOOL_HRXQ],
12030                                          hrxq_idx);
12031                         if (!hrxq) {
12032                                 rte_flow_error_set
12033                                         (error, rte_errno,
12034                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12035                                          "cannot get hash queue");
12036                                 goto error;
12037                         }
12038                         dh->rix_srss = rss_desc->shared_rss;
12039                         dv->actions[n++] = hrxq->action;
12040                 } else if (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS) {
12041                         if (!priv->sh->default_miss_action) {
12042                                 rte_flow_error_set
12043                                         (error, rte_errno,
12044                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12045                                          "default miss action not be created.");
12046                                 goto error;
12047                         }
12048                         dv->actions[n++] = priv->sh->default_miss_action;
12049                 }
12050                 err = mlx5_flow_os_create_flow(dv_h->matcher->matcher_object,
12051                                                (void *)&dv->value, n,
12052                                                dv->actions, &dh->drv_flow);
12053                 if (err) {
12054                         rte_flow_error_set(error, errno,
12055                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12056                                            NULL,
12057                                            "hardware refuses to create flow");
12058                         goto error;
12059                 }
12060                 if (priv->vmwa_context &&
12061                     dh->vf_vlan.tag && !dh->vf_vlan.created) {
12062                         /*
12063                          * The rule contains the VLAN pattern.
12064                          * For VF we are going to create VLAN
12065                          * interface to make hypervisor set correct
12066                          * e-Switch vport context.
12067                          */
12068                         mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
12069                 }
12070         }
12071         return 0;
12072 error:
12073         err = rte_errno; /* Save rte_errno before cleanup. */
12074         SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles,
12075                        handle_idx, dh, next) {
12076                 /* hrxq is union, don't clear it if the flag is not set. */
12077                 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE && dh->rix_hrxq) {
12078                         mlx5_hrxq_release(dev, dh->rix_hrxq);
12079                         dh->rix_hrxq = 0;
12080                 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
12081                         dh->rix_srss = 0;
12082                 }
12083                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
12084                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
12085         }
12086         rte_errno = err; /* Restore rte_errno. */
12087         return -rte_errno;
12088 }
12089
12090 void
12091 flow_dv_matcher_remove_cb(struct mlx5_cache_list *list __rte_unused,
12092                           struct mlx5_cache_entry *entry)
12093 {
12094         struct mlx5_flow_dv_matcher *cache = container_of(entry, typeof(*cache),
12095                                                           entry);
12096
12097         claim_zero(mlx5_flow_os_destroy_flow_matcher(cache->matcher_object));
12098         mlx5_free(cache);
12099 }
12100
12101 /**
12102  * Release the flow matcher.
12103  *
12104  * @param dev
12105  *   Pointer to Ethernet device.
12106  * @param port_id
12107  *   Index to port ID action resource.
12108  *
12109  * @return
12110  *   1 while a reference on it exists, 0 when freed.
12111  */
12112 static int
12113 flow_dv_matcher_release(struct rte_eth_dev *dev,
12114                         struct mlx5_flow_handle *handle)
12115 {
12116         struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
12117         struct mlx5_flow_tbl_data_entry *tbl = container_of(matcher->tbl,
12118                                                             typeof(*tbl), tbl);
12119         int ret;
12120
12121         MLX5_ASSERT(matcher->matcher_object);
12122         ret = mlx5_cache_unregister(&tbl->matchers, &matcher->entry);
12123         flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl->tbl);
12124         return ret;
12125 }
12126
12127 /**
12128  * Release encap_decap resource.
12129  *
12130  * @param list
12131  *   Pointer to the hash list.
12132  * @param entry
12133  *   Pointer to exist resource entry object.
12134  */
12135 void
12136 flow_dv_encap_decap_remove_cb(struct mlx5_hlist *list,
12137                               struct mlx5_hlist_entry *entry)
12138 {
12139         struct mlx5_dev_ctx_shared *sh = list->ctx;
12140         struct mlx5_flow_dv_encap_decap_resource *res =
12141                 container_of(entry, typeof(*res), entry);
12142
12143         claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
12144         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], res->idx);
12145 }
12146
12147 /**
12148  * Release an encap/decap resource.
12149  *
12150  * @param dev
12151  *   Pointer to Ethernet device.
12152  * @param encap_decap_idx
12153  *   Index of encap decap resource.
12154  *
12155  * @return
12156  *   1 while a reference on it exists, 0 when freed.
12157  */
12158 static int
12159 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
12160                                      uint32_t encap_decap_idx)
12161 {
12162         struct mlx5_priv *priv = dev->data->dev_private;
12163         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
12164
12165         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
12166                                         encap_decap_idx);
12167         if (!cache_resource)
12168                 return 0;
12169         MLX5_ASSERT(cache_resource->action);
12170         return mlx5_hlist_unregister(priv->sh->encaps_decaps,
12171                                      &cache_resource->entry);
12172 }
12173
12174 /**
12175  * Release an jump to table action resource.
12176  *
12177  * @param dev
12178  *   Pointer to Ethernet device.
12179  * @param rix_jump
12180  *   Index to the jump action resource.
12181  *
12182  * @return
12183  *   1 while a reference on it exists, 0 when freed.
12184  */
12185 static int
12186 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
12187                                   uint32_t rix_jump)
12188 {
12189         struct mlx5_priv *priv = dev->data->dev_private;
12190         struct mlx5_flow_tbl_data_entry *tbl_data;
12191
12192         tbl_data = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_JUMP],
12193                                   rix_jump);
12194         if (!tbl_data)
12195                 return 0;
12196         return flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl_data->tbl);
12197 }
12198
12199 void
12200 flow_dv_modify_remove_cb(struct mlx5_hlist *list __rte_unused,
12201                          struct mlx5_hlist_entry *entry)
12202 {
12203         struct mlx5_flow_dv_modify_hdr_resource *res =
12204                 container_of(entry, typeof(*res), entry);
12205
12206         claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
12207         mlx5_free(entry);
12208 }
12209
12210 /**
12211  * Release a modify-header resource.
12212  *
12213  * @param dev
12214  *   Pointer to Ethernet device.
12215  * @param handle
12216  *   Pointer to mlx5_flow_handle.
12217  *
12218  * @return
12219  *   1 while a reference on it exists, 0 when freed.
12220  */
12221 static int
12222 flow_dv_modify_hdr_resource_release(struct rte_eth_dev *dev,
12223                                     struct mlx5_flow_handle *handle)
12224 {
12225         struct mlx5_priv *priv = dev->data->dev_private;
12226         struct mlx5_flow_dv_modify_hdr_resource *entry = handle->dvh.modify_hdr;
12227
12228         MLX5_ASSERT(entry->action);
12229         return mlx5_hlist_unregister(priv->sh->modify_cmds, &entry->entry);
12230 }
12231
12232 void
12233 flow_dv_port_id_remove_cb(struct mlx5_cache_list *list,
12234                           struct mlx5_cache_entry *entry)
12235 {
12236         struct mlx5_dev_ctx_shared *sh = list->ctx;
12237         struct mlx5_flow_dv_port_id_action_resource *cache =
12238                         container_of(entry, typeof(*cache), entry);
12239
12240         claim_zero(mlx5_flow_os_destroy_flow_action(cache->action));
12241         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], cache->idx);
12242 }
12243
12244 /**
12245  * Release port ID action resource.
12246  *
12247  * @param dev
12248  *   Pointer to Ethernet device.
12249  * @param handle
12250  *   Pointer to mlx5_flow_handle.
12251  *
12252  * @return
12253  *   1 while a reference on it exists, 0 when freed.
12254  */
12255 static int
12256 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
12257                                         uint32_t port_id)
12258 {
12259         struct mlx5_priv *priv = dev->data->dev_private;
12260         struct mlx5_flow_dv_port_id_action_resource *cache;
12261
12262         cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID], port_id);
12263         if (!cache)
12264                 return 0;
12265         MLX5_ASSERT(cache->action);
12266         return mlx5_cache_unregister(&priv->sh->port_id_action_list,
12267                                      &cache->entry);
12268 }
12269
12270 /**
12271  * Release shared RSS action resource.
12272  *
12273  * @param dev
12274  *   Pointer to Ethernet device.
12275  * @param srss
12276  *   Shared RSS action index.
12277  */
12278 static void
12279 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss)
12280 {
12281         struct mlx5_priv *priv = dev->data->dev_private;
12282         struct mlx5_shared_action_rss *shared_rss;
12283
12284         shared_rss = mlx5_ipool_get
12285                         (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], srss);
12286         __atomic_sub_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
12287 }
12288
12289 void
12290 flow_dv_push_vlan_remove_cb(struct mlx5_cache_list *list,
12291                             struct mlx5_cache_entry *entry)
12292 {
12293         struct mlx5_dev_ctx_shared *sh = list->ctx;
12294         struct mlx5_flow_dv_push_vlan_action_resource *cache =
12295                         container_of(entry, typeof(*cache), entry);
12296
12297         claim_zero(mlx5_flow_os_destroy_flow_action(cache->action));
12298         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], cache->idx);
12299 }
12300
12301 /**
12302  * Release push vlan action resource.
12303  *
12304  * @param dev
12305  *   Pointer to Ethernet device.
12306  * @param handle
12307  *   Pointer to mlx5_flow_handle.
12308  *
12309  * @return
12310  *   1 while a reference on it exists, 0 when freed.
12311  */
12312 static int
12313 flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,
12314                                           struct mlx5_flow_handle *handle)
12315 {
12316         struct mlx5_priv *priv = dev->data->dev_private;
12317         struct mlx5_flow_dv_push_vlan_action_resource *cache;
12318         uint32_t idx = handle->dvh.rix_push_vlan;
12319
12320         cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
12321         if (!cache)
12322                 return 0;
12323         MLX5_ASSERT(cache->action);
12324         return mlx5_cache_unregister(&priv->sh->push_vlan_action_list,
12325                                      &cache->entry);
12326 }
12327
12328 /**
12329  * Release the fate resource.
12330  *
12331  * @param dev
12332  *   Pointer to Ethernet device.
12333  * @param handle
12334  *   Pointer to mlx5_flow_handle.
12335  */
12336 static void
12337 flow_dv_fate_resource_release(struct rte_eth_dev *dev,
12338                                struct mlx5_flow_handle *handle)
12339 {
12340         if (!handle->rix_fate)
12341                 return;
12342         switch (handle->fate_action) {
12343         case MLX5_FLOW_FATE_QUEUE:
12344                 mlx5_hrxq_release(dev, handle->rix_hrxq);
12345                 break;
12346         case MLX5_FLOW_FATE_JUMP:
12347                 flow_dv_jump_tbl_resource_release(dev, handle->rix_jump);
12348                 break;
12349         case MLX5_FLOW_FATE_PORT_ID:
12350                 flow_dv_port_id_action_resource_release(dev,
12351                                 handle->rix_port_id_action);
12352                 break;
12353         default:
12354                 DRV_LOG(DEBUG, "Incorrect fate action:%d", handle->fate_action);
12355                 break;
12356         }
12357         handle->rix_fate = 0;
12358 }
12359
12360 void
12361 flow_dv_sample_remove_cb(struct mlx5_cache_list *list __rte_unused,
12362                          struct mlx5_cache_entry *entry)
12363 {
12364         struct mlx5_flow_dv_sample_resource *cache_resource =
12365                         container_of(entry, typeof(*cache_resource), entry);
12366         struct rte_eth_dev *dev = cache_resource->dev;
12367         struct mlx5_priv *priv = dev->data->dev_private;
12368
12369         if (cache_resource->verbs_action)
12370                 claim_zero(mlx5_flow_os_destroy_flow_action
12371                                 (cache_resource->verbs_action));
12372         if (cache_resource->normal_path_tbl)
12373                 flow_dv_tbl_resource_release(MLX5_SH(dev),
12374                         cache_resource->normal_path_tbl);
12375         flow_dv_sample_sub_actions_release(dev,
12376                                 &cache_resource->sample_idx);
12377         mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
12378                         cache_resource->idx);
12379         DRV_LOG(DEBUG, "sample resource %p: removed",
12380                 (void *)cache_resource);
12381 }
12382
12383 /**
12384  * Release an sample resource.
12385  *
12386  * @param dev
12387  *   Pointer to Ethernet device.
12388  * @param handle
12389  *   Pointer to mlx5_flow_handle.
12390  *
12391  * @return
12392  *   1 while a reference on it exists, 0 when freed.
12393  */
12394 static int
12395 flow_dv_sample_resource_release(struct rte_eth_dev *dev,
12396                                      struct mlx5_flow_handle *handle)
12397 {
12398         struct mlx5_priv *priv = dev->data->dev_private;
12399         struct mlx5_flow_dv_sample_resource *cache_resource;
12400
12401         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
12402                          handle->dvh.rix_sample);
12403         if (!cache_resource)
12404                 return 0;
12405         MLX5_ASSERT(cache_resource->verbs_action);
12406         return mlx5_cache_unregister(&priv->sh->sample_action_list,
12407                                      &cache_resource->entry);
12408 }
12409
12410 void
12411 flow_dv_dest_array_remove_cb(struct mlx5_cache_list *list __rte_unused,
12412                              struct mlx5_cache_entry *entry)
12413 {
12414         struct mlx5_flow_dv_dest_array_resource *cache_resource =
12415                         container_of(entry, typeof(*cache_resource), entry);
12416         struct rte_eth_dev *dev = cache_resource->dev;
12417         struct mlx5_priv *priv = dev->data->dev_private;
12418         uint32_t i = 0;
12419
12420         MLX5_ASSERT(cache_resource->action);
12421         if (cache_resource->action)
12422                 claim_zero(mlx5_flow_os_destroy_flow_action
12423                                         (cache_resource->action));
12424         for (; i < cache_resource->num_of_dest; i++)
12425                 flow_dv_sample_sub_actions_release(dev,
12426                                 &cache_resource->sample_idx[i]);
12427         mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
12428                         cache_resource->idx);
12429         DRV_LOG(DEBUG, "destination array resource %p: removed",
12430                 (void *)cache_resource);
12431 }
12432
12433 /**
12434  * Release an destination array resource.
12435  *
12436  * @param dev
12437  *   Pointer to Ethernet device.
12438  * @param handle
12439  *   Pointer to mlx5_flow_handle.
12440  *
12441  * @return
12442  *   1 while a reference on it exists, 0 when freed.
12443  */
12444 static int
12445 flow_dv_dest_array_resource_release(struct rte_eth_dev *dev,
12446                                     struct mlx5_flow_handle *handle)
12447 {
12448         struct mlx5_priv *priv = dev->data->dev_private;
12449         struct mlx5_flow_dv_dest_array_resource *cache;
12450
12451         cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
12452                                handle->dvh.rix_dest_array);
12453         if (!cache)
12454                 return 0;
12455         MLX5_ASSERT(cache->action);
12456         return mlx5_cache_unregister(&priv->sh->dest_array_list,
12457                                      &cache->entry);
12458 }
12459
12460 static void
12461 flow_dv_geneve_tlv_option_resource_release(struct rte_eth_dev *dev)
12462 {
12463         struct mlx5_priv *priv = dev->data->dev_private;
12464         struct mlx5_dev_ctx_shared *sh = priv->sh;
12465         struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
12466                                 sh->geneve_tlv_option_resource;
12467         rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
12468         if (geneve_opt_resource) {
12469                 if (!(__atomic_sub_fetch(&geneve_opt_resource->refcnt, 1,
12470                                          __ATOMIC_RELAXED))) {
12471                         claim_zero(mlx5_devx_cmd_destroy
12472                                         (geneve_opt_resource->obj));
12473                         mlx5_free(sh->geneve_tlv_option_resource);
12474                         sh->geneve_tlv_option_resource = NULL;
12475                 }
12476         }
12477         rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
12478 }
12479
12480 /**
12481  * Remove the flow from the NIC but keeps it in memory.
12482  * Lock free, (mutex should be acquired by caller).
12483  *
12484  * @param[in] dev
12485  *   Pointer to Ethernet device.
12486  * @param[in, out] flow
12487  *   Pointer to flow structure.
12488  */
12489 static void
12490 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
12491 {
12492         struct mlx5_flow_handle *dh;
12493         uint32_t handle_idx;
12494         struct mlx5_priv *priv = dev->data->dev_private;
12495
12496         if (!flow)
12497                 return;
12498         handle_idx = flow->dev_handles;
12499         while (handle_idx) {
12500                 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
12501                                     handle_idx);
12502                 if (!dh)
12503                         return;
12504                 if (dh->drv_flow) {
12505                         claim_zero(mlx5_flow_os_destroy_flow(dh->drv_flow));
12506                         dh->drv_flow = NULL;
12507                 }
12508                 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE)
12509                         flow_dv_fate_resource_release(dev, dh);
12510                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
12511                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
12512                 handle_idx = dh->next.next;
12513         }
12514 }
12515
12516 /**
12517  * Remove the flow from the NIC and the memory.
12518  * Lock free, (mutex should be acquired by caller).
12519  *
12520  * @param[in] dev
12521  *   Pointer to the Ethernet device structure.
12522  * @param[in, out] flow
12523  *   Pointer to flow structure.
12524  */
12525 static void
12526 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
12527 {
12528         struct mlx5_flow_handle *dev_handle;
12529         struct mlx5_priv *priv = dev->data->dev_private;
12530         uint32_t srss = 0;
12531
12532         if (!flow)
12533                 return;
12534         flow_dv_remove(dev, flow);
12535         if (flow->counter) {
12536                 flow_dv_counter_free(dev, flow->counter);
12537                 flow->counter = 0;
12538         }
12539         if (flow->meter) {
12540                 struct mlx5_flow_meter *fm;
12541
12542                 fm = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MTR],
12543                                     flow->meter);
12544                 if (fm)
12545                         mlx5_flow_meter_detach(fm);
12546                 flow->meter = 0;
12547         }
12548         if (flow->age)
12549                 flow_dv_aso_age_release(dev, flow->age);
12550         if (flow->geneve_tlv_option) {
12551                 flow_dv_geneve_tlv_option_resource_release(dev);
12552                 flow->geneve_tlv_option = 0;
12553         }
12554         while (flow->dev_handles) {
12555                 uint32_t tmp_idx = flow->dev_handles;
12556
12557                 dev_handle = mlx5_ipool_get(priv->sh->ipool
12558                                             [MLX5_IPOOL_MLX5_FLOW], tmp_idx);
12559                 if (!dev_handle)
12560                         return;
12561                 flow->dev_handles = dev_handle->next.next;
12562                 if (dev_handle->dvh.matcher)
12563                         flow_dv_matcher_release(dev, dev_handle);
12564                 if (dev_handle->dvh.rix_sample)
12565                         flow_dv_sample_resource_release(dev, dev_handle);
12566                 if (dev_handle->dvh.rix_dest_array)
12567                         flow_dv_dest_array_resource_release(dev, dev_handle);
12568                 if (dev_handle->dvh.rix_encap_decap)
12569                         flow_dv_encap_decap_resource_release(dev,
12570                                 dev_handle->dvh.rix_encap_decap);
12571                 if (dev_handle->dvh.modify_hdr)
12572                         flow_dv_modify_hdr_resource_release(dev, dev_handle);
12573                 if (dev_handle->dvh.rix_push_vlan)
12574                         flow_dv_push_vlan_action_resource_release(dev,
12575                                                                   dev_handle);
12576                 if (dev_handle->dvh.rix_tag)
12577                         flow_dv_tag_release(dev,
12578                                             dev_handle->dvh.rix_tag);
12579                 if (dev_handle->fate_action != MLX5_FLOW_FATE_SHARED_RSS)
12580                         flow_dv_fate_resource_release(dev, dev_handle);
12581                 else if (!srss)
12582                         srss = dev_handle->rix_srss;
12583                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
12584                            tmp_idx);
12585         }
12586         if (srss)
12587                 flow_dv_shared_rss_action_release(dev, srss);
12588 }
12589
12590 /**
12591  * Release array of hash RX queue objects.
12592  * Helper function.
12593  *
12594  * @param[in] dev
12595  *   Pointer to the Ethernet device structure.
12596  * @param[in, out] hrxqs
12597  *   Array of hash RX queue objects.
12598  *
12599  * @return
12600  *   Total number of references to hash RX queue objects in *hrxqs* array
12601  *   after this operation.
12602  */
12603 static int
12604 __flow_dv_hrxqs_release(struct rte_eth_dev *dev,
12605                         uint32_t (*hrxqs)[MLX5_RSS_HASH_FIELDS_LEN])
12606 {
12607         size_t i;
12608         int remaining = 0;
12609
12610         for (i = 0; i < RTE_DIM(*hrxqs); i++) {
12611                 int ret = mlx5_hrxq_release(dev, (*hrxqs)[i]);
12612
12613                 if (!ret)
12614                         (*hrxqs)[i] = 0;
12615                 remaining += ret;
12616         }
12617         return remaining;
12618 }
12619
12620 /**
12621  * Release all hash RX queue objects representing shared RSS action.
12622  *
12623  * @param[in] dev
12624  *   Pointer to the Ethernet device structure.
12625  * @param[in, out] action
12626  *   Shared RSS action to remove hash RX queue objects from.
12627  *
12628  * @return
12629  *   Total number of references to hash RX queue objects stored in *action*
12630  *   after this operation.
12631  *   Expected to be 0 if no external references held.
12632  */
12633 static int
12634 __flow_dv_action_rss_hrxqs_release(struct rte_eth_dev *dev,
12635                                  struct mlx5_shared_action_rss *shared_rss)
12636 {
12637         return __flow_dv_hrxqs_release(dev, &shared_rss->hrxq) +
12638                 __flow_dv_hrxqs_release(dev, &shared_rss->hrxq_tunnel);
12639 }
12640
12641 /**
12642  * Setup shared RSS action.
12643  * Prepare set of hash RX queue objects sufficient to handle all valid
12644  * hash_fields combinations (see enum ibv_rx_hash_fields).
12645  *
12646  * @param[in] dev
12647  *   Pointer to the Ethernet device structure.
12648  * @param[in] action_idx
12649  *   Shared RSS action ipool index.
12650  * @param[in, out] action
12651  *   Partially initialized shared RSS action.
12652  * @param[out] error
12653  *   Perform verbose error reporting if not NULL. Initialized in case of
12654  *   error only.
12655  *
12656  * @return
12657  *   0 on success, otherwise negative errno value.
12658  */
12659 static int
12660 __flow_dv_action_rss_setup(struct rte_eth_dev *dev,
12661                            uint32_t action_idx,
12662                            struct mlx5_shared_action_rss *shared_rss,
12663                            struct rte_flow_error *error)
12664 {
12665         struct mlx5_flow_rss_desc rss_desc = { 0 };
12666         size_t i;
12667         int err;
12668
12669         if (mlx5_ind_table_obj_setup(dev, shared_rss->ind_tbl)) {
12670                 return rte_flow_error_set(error, rte_errno,
12671                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12672                                           "cannot setup indirection table");
12673         }
12674         memcpy(rss_desc.key, shared_rss->origin.key, MLX5_RSS_HASH_KEY_LEN);
12675         rss_desc.key_len = MLX5_RSS_HASH_KEY_LEN;
12676         rss_desc.const_q = shared_rss->origin.queue;
12677         rss_desc.queue_num = shared_rss->origin.queue_num;
12678         /* Set non-zero value to indicate a shared RSS. */
12679         rss_desc.shared_rss = action_idx;
12680         rss_desc.ind_tbl = shared_rss->ind_tbl;
12681         for (i = 0; i < MLX5_RSS_HASH_FIELDS_LEN; i++) {
12682                 uint32_t hrxq_idx;
12683                 uint64_t hash_fields = mlx5_rss_hash_fields[i];
12684                 int tunnel;
12685
12686                 for (tunnel = 0; tunnel < 2; tunnel++) {
12687                         rss_desc.tunnel = tunnel;
12688                         rss_desc.hash_fields = hash_fields;
12689                         hrxq_idx = mlx5_hrxq_get(dev, &rss_desc);
12690                         if (!hrxq_idx) {
12691                                 rte_flow_error_set
12692                                         (error, rte_errno,
12693                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12694                                          "cannot get hash queue");
12695                                 goto error_hrxq_new;
12696                         }
12697                         err = __flow_dv_action_rss_hrxq_set
12698                                 (shared_rss, hash_fields, tunnel, hrxq_idx);
12699                         MLX5_ASSERT(!err);
12700                 }
12701         }
12702         return 0;
12703 error_hrxq_new:
12704         err = rte_errno;
12705         __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
12706         if (!mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl, true))
12707                 shared_rss->ind_tbl = NULL;
12708         rte_errno = err;
12709         return -rte_errno;
12710 }
12711
12712 /**
12713  * Create shared RSS action.
12714  *
12715  * @param[in] dev
12716  *   Pointer to the Ethernet device structure.
12717  * @param[in] conf
12718  *   Shared action configuration.
12719  * @param[in] rss
12720  *   RSS action specification used to create shared action.
12721  * @param[out] error
12722  *   Perform verbose error reporting if not NULL. Initialized in case of
12723  *   error only.
12724  *
12725  * @return
12726  *   A valid shared action ID in case of success, 0 otherwise and
12727  *   rte_errno is set.
12728  */
12729 static uint32_t
12730 __flow_dv_action_rss_create(struct rte_eth_dev *dev,
12731                             const struct rte_flow_shared_action_conf *conf,
12732                             const struct rte_flow_action_rss *rss,
12733                             struct rte_flow_error *error)
12734 {
12735         struct mlx5_priv *priv = dev->data->dev_private;
12736         struct mlx5_shared_action_rss *shared_rss = NULL;
12737         void *queue = NULL;
12738         struct rte_flow_action_rss *origin;
12739         const uint8_t *rss_key;
12740         uint32_t queue_size = rss->queue_num * sizeof(uint16_t);
12741         uint32_t idx;
12742
12743         RTE_SET_USED(conf);
12744         queue = mlx5_malloc(0, RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
12745                             0, SOCKET_ID_ANY);
12746         shared_rss = mlx5_ipool_zmalloc
12747                          (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], &idx);
12748         if (!shared_rss || !queue) {
12749                 rte_flow_error_set(error, ENOMEM,
12750                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12751                                    "cannot allocate resource memory");
12752                 goto error_rss_init;
12753         }
12754         if (idx > (1u << MLX5_SHARED_ACTION_TYPE_OFFSET)) {
12755                 rte_flow_error_set(error, E2BIG,
12756                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12757                                    "rss action number out of range");
12758                 goto error_rss_init;
12759         }
12760         shared_rss->ind_tbl = mlx5_malloc(MLX5_MEM_ZERO,
12761                                           sizeof(*shared_rss->ind_tbl),
12762                                           0, SOCKET_ID_ANY);
12763         if (!shared_rss->ind_tbl) {
12764                 rte_flow_error_set(error, ENOMEM,
12765                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12766                                    "cannot allocate resource memory");
12767                 goto error_rss_init;
12768         }
12769         memcpy(queue, rss->queue, queue_size);
12770         shared_rss->ind_tbl->queues = queue;
12771         shared_rss->ind_tbl->queues_n = rss->queue_num;
12772         origin = &shared_rss->origin;
12773         origin->func = rss->func;
12774         origin->level = rss->level;
12775         /* RSS type 0 indicates default RSS type (ETH_RSS_IP). */
12776         origin->types = !rss->types ? ETH_RSS_IP : rss->types;
12777         /* NULL RSS key indicates default RSS key. */
12778         rss_key = !rss->key ? rss_hash_default_key : rss->key;
12779         memcpy(shared_rss->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
12780         origin->key = &shared_rss->key[0];
12781         origin->key_len = MLX5_RSS_HASH_KEY_LEN;
12782         origin->queue = queue;
12783         origin->queue_num = rss->queue_num;
12784         if (__flow_dv_action_rss_setup(dev, idx, shared_rss, error))
12785                 goto error_rss_init;
12786         rte_spinlock_init(&shared_rss->action_rss_sl);
12787         __atomic_add_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
12788         rte_spinlock_lock(&priv->shared_act_sl);
12789         ILIST_INSERT(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
12790                      &priv->rss_shared_actions, idx, shared_rss, next);
12791         rte_spinlock_unlock(&priv->shared_act_sl);
12792         return idx;
12793 error_rss_init:
12794         if (shared_rss) {
12795                 if (shared_rss->ind_tbl)
12796                         mlx5_free(shared_rss->ind_tbl);
12797                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
12798                                 idx);
12799         }
12800         if (queue)
12801                 mlx5_free(queue);
12802         return 0;
12803 }
12804
12805 /**
12806  * Destroy the shared RSS action.
12807  * Release related hash RX queue objects.
12808  *
12809  * @param[in] dev
12810  *   Pointer to the Ethernet device structure.
12811  * @param[in] idx
12812  *   The shared RSS action object ID to be removed.
12813  * @param[out] error
12814  *   Perform verbose error reporting if not NULL. Initialized in case of
12815  *   error only.
12816  *
12817  * @return
12818  *   0 on success, otherwise negative errno value.
12819  */
12820 static int
12821 __flow_dv_action_rss_release(struct rte_eth_dev *dev, uint32_t idx,
12822                              struct rte_flow_error *error)
12823 {
12824         struct mlx5_priv *priv = dev->data->dev_private;
12825         struct mlx5_shared_action_rss *shared_rss =
12826             mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
12827         uint32_t old_refcnt = 1;
12828         int remaining;
12829         uint16_t *queue = NULL;
12830
12831         if (!shared_rss)
12832                 return rte_flow_error_set(error, EINVAL,
12833                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12834                                           "invalid shared action");
12835         remaining = __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
12836         if (remaining)
12837                 return rte_flow_error_set(error, EBUSY,
12838                                           RTE_FLOW_ERROR_TYPE_ACTION,
12839                                           NULL,
12840                                           "shared rss hrxq has references");
12841         if (!__atomic_compare_exchange_n(&shared_rss->refcnt, &old_refcnt,
12842                                          0, 0, __ATOMIC_ACQUIRE,
12843                                          __ATOMIC_RELAXED))
12844                 return rte_flow_error_set(error, EBUSY,
12845                                           RTE_FLOW_ERROR_TYPE_ACTION,
12846                                           NULL,
12847                                           "shared rss has references");
12848         queue = shared_rss->ind_tbl->queues;
12849         remaining = mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl, true);
12850         if (remaining)
12851                 return rte_flow_error_set(error, EBUSY,
12852                                           RTE_FLOW_ERROR_TYPE_ACTION,
12853                                           NULL,
12854                                           "shared rss indirection table has"
12855                                           " references");
12856         mlx5_free(queue);
12857         rte_spinlock_lock(&priv->shared_act_sl);
12858         ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
12859                      &priv->rss_shared_actions, idx, shared_rss, next);
12860         rte_spinlock_unlock(&priv->shared_act_sl);
12861         mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
12862                         idx);
12863         return 0;
12864 }
12865
12866 /**
12867  * Create shared action, lock free,
12868  * (mutex should be acquired by caller).
12869  * Dispatcher for action type specific call.
12870  *
12871  * @param[in] dev
12872  *   Pointer to the Ethernet device structure.
12873  * @param[in] conf
12874  *   Shared action configuration.
12875  * @param[in] action
12876  *   Action specification used to create shared action.
12877  * @param[out] error
12878  *   Perform verbose error reporting if not NULL. Initialized in case of
12879  *   error only.
12880  *
12881  * @return
12882  *   A valid shared action handle in case of success, NULL otherwise and
12883  *   rte_errno is set.
12884  */
12885 static struct rte_flow_shared_action *
12886 flow_dv_action_create(struct rte_eth_dev *dev,
12887                       const struct rte_flow_shared_action_conf *conf,
12888                       const struct rte_flow_action *action,
12889                       struct rte_flow_error *err)
12890 {
12891         uint32_t idx = 0;
12892         uint32_t ret = 0;
12893
12894         switch (action->type) {
12895         case RTE_FLOW_ACTION_TYPE_RSS:
12896                 ret = __flow_dv_action_rss_create(dev, conf, action->conf, err);
12897                 idx = (MLX5_SHARED_ACTION_TYPE_RSS <<
12898                        MLX5_SHARED_ACTION_TYPE_OFFSET) | ret;
12899                 break;
12900         case RTE_FLOW_ACTION_TYPE_AGE:
12901                 ret = flow_dv_translate_create_aso_age(dev, action->conf, err);
12902                 idx = (MLX5_SHARED_ACTION_TYPE_AGE <<
12903                        MLX5_SHARED_ACTION_TYPE_OFFSET) | ret;
12904                 if (ret) {
12905                         struct mlx5_aso_age_action *aso_age =
12906                                               flow_aso_age_get_by_idx(dev, ret);
12907
12908                         if (!aso_age->age_params.context)
12909                                 aso_age->age_params.context =
12910                                                          (void *)(uintptr_t)idx;
12911                 }
12912                 break;
12913         default:
12914                 rte_flow_error_set(err, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION,
12915                                    NULL, "action type not supported");
12916                 break;
12917         }
12918         return ret ? (struct rte_flow_shared_action *)(uintptr_t)idx : NULL;
12919 }
12920
12921 /**
12922  * Destroy the shared action.
12923  * Release action related resources on the NIC and the memory.
12924  * Lock free, (mutex should be acquired by caller).
12925  * Dispatcher for action type specific call.
12926  *
12927  * @param[in] dev
12928  *   Pointer to the Ethernet device structure.
12929  * @param[in] action
12930  *   The shared action object to be removed.
12931  * @param[out] error
12932  *   Perform verbose error reporting if not NULL. Initialized in case of
12933  *   error only.
12934  *
12935  * @return
12936  *   0 on success, otherwise negative errno value.
12937  */
12938 static int
12939 flow_dv_action_destroy(struct rte_eth_dev *dev,
12940                        struct rte_flow_shared_action *action,
12941                        struct rte_flow_error *error)
12942 {
12943         uint32_t act_idx = (uint32_t)(uintptr_t)action;
12944         uint32_t type = act_idx >> MLX5_SHARED_ACTION_TYPE_OFFSET;
12945         uint32_t idx = act_idx & ((1u << MLX5_SHARED_ACTION_TYPE_OFFSET) - 1);
12946         int ret;
12947
12948         switch (type) {
12949         case MLX5_SHARED_ACTION_TYPE_RSS:
12950                 return __flow_dv_action_rss_release(dev, idx, error);
12951         case MLX5_SHARED_ACTION_TYPE_AGE:
12952                 ret = flow_dv_aso_age_release(dev, idx);
12953                 if (ret)
12954                         /*
12955                          * In this case, the last flow has a reference will
12956                          * actually release the age action.
12957                          */
12958                         DRV_LOG(DEBUG, "Shared age action %" PRIu32 " was"
12959                                 " released with references %d.", idx, ret);
12960                 return 0;
12961         default:
12962                 return rte_flow_error_set(error, ENOTSUP,
12963                                           RTE_FLOW_ERROR_TYPE_ACTION,
12964                                           NULL,
12965                                           "action type not supported");
12966         }
12967 }
12968
12969 /**
12970  * Updates in place shared RSS action configuration.
12971  *
12972  * @param[in] dev
12973  *   Pointer to the Ethernet device structure.
12974  * @param[in] idx
12975  *   The shared RSS action object ID to be updated.
12976  * @param[in] action_conf
12977  *   RSS action specification used to modify *shared_rss*.
12978  * @param[out] error
12979  *   Perform verbose error reporting if not NULL. Initialized in case of
12980  *   error only.
12981  *
12982  * @return
12983  *   0 on success, otherwise negative errno value.
12984  * @note: currently only support update of RSS queues.
12985  */
12986 static int
12987 __flow_dv_action_rss_update(struct rte_eth_dev *dev, uint32_t idx,
12988                             const struct rte_flow_action_rss *action_conf,
12989                             struct rte_flow_error *error)
12990 {
12991         struct mlx5_priv *priv = dev->data->dev_private;
12992         struct mlx5_shared_action_rss *shared_rss =
12993             mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
12994         int ret = 0;
12995         void *queue = NULL;
12996         uint16_t *queue_old = NULL;
12997         uint32_t queue_size = action_conf->queue_num * sizeof(uint16_t);
12998
12999         if (!shared_rss)
13000                 return rte_flow_error_set(error, EINVAL,
13001                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
13002                                           "invalid shared action to update");
13003         if (priv->obj_ops.ind_table_modify == NULL)
13004                 return rte_flow_error_set(error, ENOTSUP,
13005                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
13006                                           "cannot modify indirection table");
13007         queue = mlx5_malloc(MLX5_MEM_ZERO,
13008                             RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
13009                             0, SOCKET_ID_ANY);
13010         if (!queue)
13011                 return rte_flow_error_set(error, ENOMEM,
13012                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13013                                           NULL,
13014                                           "cannot allocate resource memory");
13015         memcpy(queue, action_conf->queue, queue_size);
13016         MLX5_ASSERT(shared_rss->ind_tbl);
13017         rte_spinlock_lock(&shared_rss->action_rss_sl);
13018         queue_old = shared_rss->ind_tbl->queues;
13019         ret = mlx5_ind_table_obj_modify(dev, shared_rss->ind_tbl,
13020                                         queue, action_conf->queue_num, true);
13021         if (ret) {
13022                 mlx5_free(queue);
13023                 ret = rte_flow_error_set(error, rte_errno,
13024                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
13025                                           "cannot update indirection table");
13026         } else {
13027                 mlx5_free(queue_old);
13028                 shared_rss->origin.queue = queue;
13029                 shared_rss->origin.queue_num = action_conf->queue_num;
13030         }
13031         rte_spinlock_unlock(&shared_rss->action_rss_sl);
13032         return ret;
13033 }
13034
13035 /**
13036  * Updates in place shared action configuration, lock free,
13037  * (mutex should be acquired by caller).
13038  *
13039  * @param[in] dev
13040  *   Pointer to the Ethernet device structure.
13041  * @param[in] action
13042  *   The shared action object to be updated.
13043  * @param[in] action_conf
13044  *   Action specification used to modify *action*.
13045  *   *action_conf* should be of type correlating with type of the *action*,
13046  *   otherwise considered as invalid.
13047  * @param[out] error
13048  *   Perform verbose error reporting if not NULL. Initialized in case of
13049  *   error only.
13050  *
13051  * @return
13052  *   0 on success, otherwise negative errno value.
13053  */
13054 static int
13055 flow_dv_action_update(struct rte_eth_dev *dev,
13056                         struct rte_flow_shared_action *action,
13057                         const void *action_conf,
13058                         struct rte_flow_error *err)
13059 {
13060         uint32_t act_idx = (uint32_t)(uintptr_t)action;
13061         uint32_t type = act_idx >> MLX5_SHARED_ACTION_TYPE_OFFSET;
13062         uint32_t idx = act_idx & ((1u << MLX5_SHARED_ACTION_TYPE_OFFSET) - 1);
13063
13064         switch (type) {
13065         case MLX5_SHARED_ACTION_TYPE_RSS:
13066                 return __flow_dv_action_rss_update(dev, idx, action_conf, err);
13067         default:
13068                 return rte_flow_error_set(err, ENOTSUP,
13069                                           RTE_FLOW_ERROR_TYPE_ACTION,
13070                                           NULL,
13071                                           "action type update not supported");
13072         }
13073 }
13074
13075 static int
13076 flow_dv_action_query(struct rte_eth_dev *dev,
13077                      const struct rte_flow_shared_action *action, void *data,
13078                      struct rte_flow_error *error)
13079 {
13080         struct mlx5_age_param *age_param;
13081         struct rte_flow_query_age *resp;
13082         uint32_t act_idx = (uint32_t)(uintptr_t)action;
13083         uint32_t type = act_idx >> MLX5_SHARED_ACTION_TYPE_OFFSET;
13084         uint32_t idx = act_idx & ((1u << MLX5_SHARED_ACTION_TYPE_OFFSET) - 1);
13085
13086         switch (type) {
13087         case MLX5_SHARED_ACTION_TYPE_AGE:
13088                 age_param = &flow_aso_age_get_by_idx(dev, idx)->age_params;
13089                 resp = data;
13090                 resp->aged = __atomic_load_n(&age_param->state,
13091                                               __ATOMIC_RELAXED) == AGE_TMOUT ?
13092                                                                           1 : 0;
13093                 resp->sec_since_last_hit_valid = !resp->aged;
13094                 if (resp->sec_since_last_hit_valid)
13095                         resp->sec_since_last_hit = __atomic_load_n
13096                              (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
13097                 return 0;
13098         default:
13099                 return rte_flow_error_set(error, ENOTSUP,
13100                                           RTE_FLOW_ERROR_TYPE_ACTION,
13101                                           NULL,
13102                                           "action type query not supported");
13103         }
13104 }
13105
13106 /**
13107  * Query a dv flow  rule for its statistics via devx.
13108  *
13109  * @param[in] dev
13110  *   Pointer to Ethernet device.
13111  * @param[in] flow
13112  *   Pointer to the sub flow.
13113  * @param[out] data
13114  *   data retrieved by the query.
13115  * @param[out] error
13116  *   Perform verbose error reporting if not NULL.
13117  *
13118  * @return
13119  *   0 on success, a negative errno value otherwise and rte_errno is set.
13120  */
13121 static int
13122 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
13123                     void *data, struct rte_flow_error *error)
13124 {
13125         struct mlx5_priv *priv = dev->data->dev_private;
13126         struct rte_flow_query_count *qc = data;
13127
13128         if (!priv->config.devx)
13129                 return rte_flow_error_set(error, ENOTSUP,
13130                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13131                                           NULL,
13132                                           "counters are not supported");
13133         if (flow->counter) {
13134                 uint64_t pkts, bytes;
13135                 struct mlx5_flow_counter *cnt;
13136
13137                 cnt = flow_dv_counter_get_by_idx(dev, flow->counter,
13138                                                  NULL);
13139                 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
13140                                                &bytes);
13141
13142                 if (err)
13143                         return rte_flow_error_set(error, -err,
13144                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13145                                         NULL, "cannot read counters");
13146                 qc->hits_set = 1;
13147                 qc->bytes_set = 1;
13148                 qc->hits = pkts - cnt->hits;
13149                 qc->bytes = bytes - cnt->bytes;
13150                 if (qc->reset) {
13151                         cnt->hits = pkts;
13152                         cnt->bytes = bytes;
13153                 }
13154                 return 0;
13155         }
13156         return rte_flow_error_set(error, EINVAL,
13157                                   RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13158                                   NULL,
13159                                   "counters are not available");
13160 }
13161
13162 /**
13163  * Query a flow rule AGE action for aging information.
13164  *
13165  * @param[in] dev
13166  *   Pointer to Ethernet device.
13167  * @param[in] flow
13168  *   Pointer to the sub flow.
13169  * @param[out] data
13170  *   data retrieved by the query.
13171  * @param[out] error
13172  *   Perform verbose error reporting if not NULL.
13173  *
13174  * @return
13175  *   0 on success, a negative errno value otherwise and rte_errno is set.
13176  */
13177 static int
13178 flow_dv_query_age(struct rte_eth_dev *dev, struct rte_flow *flow,
13179                   void *data, struct rte_flow_error *error)
13180 {
13181         struct rte_flow_query_age *resp = data;
13182         struct mlx5_age_param *age_param;
13183
13184         if (flow->age) {
13185                 struct mlx5_aso_age_action *act =
13186                                      flow_aso_age_get_by_idx(dev, flow->age);
13187
13188                 age_param = &act->age_params;
13189         } else if (flow->counter) {
13190                 age_param = flow_dv_counter_idx_get_age(dev, flow->counter);
13191
13192                 if (!age_param || !age_param->timeout)
13193                         return rte_flow_error_set
13194                                         (error, EINVAL,
13195                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13196                                          NULL, "cannot read age data");
13197         } else {
13198                 return rte_flow_error_set(error, EINVAL,
13199                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13200                                           NULL, "age data not available");
13201         }
13202         resp->aged = __atomic_load_n(&age_param->state, __ATOMIC_RELAXED) ==
13203                                      AGE_TMOUT ? 1 : 0;
13204         resp->sec_since_last_hit_valid = !resp->aged;
13205         if (resp->sec_since_last_hit_valid)
13206                 resp->sec_since_last_hit = __atomic_load_n
13207                              (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
13208         return 0;
13209 }
13210
13211 /**
13212  * Query a flow.
13213  *
13214  * @see rte_flow_query()
13215  * @see rte_flow_ops
13216  */
13217 static int
13218 flow_dv_query(struct rte_eth_dev *dev,
13219               struct rte_flow *flow __rte_unused,
13220               const struct rte_flow_action *actions __rte_unused,
13221               void *data __rte_unused,
13222               struct rte_flow_error *error __rte_unused)
13223 {
13224         int ret = -EINVAL;
13225
13226         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
13227                 switch (actions->type) {
13228                 case RTE_FLOW_ACTION_TYPE_VOID:
13229                         break;
13230                 case RTE_FLOW_ACTION_TYPE_COUNT:
13231                         ret = flow_dv_query_count(dev, flow, data, error);
13232                         break;
13233                 case RTE_FLOW_ACTION_TYPE_AGE:
13234                         ret = flow_dv_query_age(dev, flow, data, error);
13235                         break;
13236                 default:
13237                         return rte_flow_error_set(error, ENOTSUP,
13238                                                   RTE_FLOW_ERROR_TYPE_ACTION,
13239                                                   actions,
13240                                                   "action not supported");
13241                 }
13242         }
13243         return ret;
13244 }
13245
13246 /**
13247  * Destroy the meter table set.
13248  * Lock free, (mutex should be acquired by caller).
13249  *
13250  * @param[in] dev
13251  *   Pointer to Ethernet device.
13252  * @param[in] tbl
13253  *   Pointer to the meter table set.
13254  *
13255  * @return
13256  *   Always 0.
13257  */
13258 static int
13259 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
13260                         struct mlx5_meter_domains_infos *tbl)
13261 {
13262         struct mlx5_priv *priv = dev->data->dev_private;
13263         struct mlx5_meter_domains_infos *mtd =
13264                                 (struct mlx5_meter_domains_infos *)tbl;
13265
13266         if (!mtd || !priv->config.dv_flow_en)
13267                 return 0;
13268         if (mtd->ingress.policer_rules[RTE_MTR_DROPPED])
13269                 claim_zero(mlx5_flow_os_destroy_flow
13270                            (mtd->ingress.policer_rules[RTE_MTR_DROPPED]));
13271         if (mtd->egress.policer_rules[RTE_MTR_DROPPED])
13272                 claim_zero(mlx5_flow_os_destroy_flow
13273                            (mtd->egress.policer_rules[RTE_MTR_DROPPED]));
13274         if (mtd->transfer.policer_rules[RTE_MTR_DROPPED])
13275                 claim_zero(mlx5_flow_os_destroy_flow
13276                            (mtd->transfer.policer_rules[RTE_MTR_DROPPED]));
13277         if (mtd->egress.color_matcher)
13278                 claim_zero(mlx5_flow_os_destroy_flow_matcher
13279                            (mtd->egress.color_matcher));
13280         if (mtd->egress.any_matcher)
13281                 claim_zero(mlx5_flow_os_destroy_flow_matcher
13282                            (mtd->egress.any_matcher));
13283         if (mtd->egress.tbl)
13284                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->egress.tbl);
13285         if (mtd->egress.sfx_tbl)
13286                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->egress.sfx_tbl);
13287         if (mtd->ingress.color_matcher)
13288                 claim_zero(mlx5_flow_os_destroy_flow_matcher
13289                            (mtd->ingress.color_matcher));
13290         if (mtd->ingress.any_matcher)
13291                 claim_zero(mlx5_flow_os_destroy_flow_matcher
13292                            (mtd->ingress.any_matcher));
13293         if (mtd->ingress.tbl)
13294                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->ingress.tbl);
13295         if (mtd->ingress.sfx_tbl)
13296                 flow_dv_tbl_resource_release(MLX5_SH(dev),
13297                                              mtd->ingress.sfx_tbl);
13298         if (mtd->transfer.color_matcher)
13299                 claim_zero(mlx5_flow_os_destroy_flow_matcher
13300                            (mtd->transfer.color_matcher));
13301         if (mtd->transfer.any_matcher)
13302                 claim_zero(mlx5_flow_os_destroy_flow_matcher
13303                            (mtd->transfer.any_matcher));
13304         if (mtd->transfer.tbl)
13305                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->transfer.tbl);
13306         if (mtd->transfer.sfx_tbl)
13307                 flow_dv_tbl_resource_release(MLX5_SH(dev),
13308                                              mtd->transfer.sfx_tbl);
13309         if (mtd->drop_actn)
13310                 claim_zero(mlx5_flow_os_destroy_flow_action(mtd->drop_actn));
13311         mlx5_free(mtd);
13312         return 0;
13313 }
13314
13315 /* Number of meter flow actions, count and jump or count and drop. */
13316 #define METER_ACTIONS 2
13317
13318 /**
13319  * Create specify domain meter table and suffix table.
13320  *
13321  * @param[in] dev
13322  *   Pointer to Ethernet device.
13323  * @param[in,out] mtb
13324  *   Pointer to DV meter table set.
13325  * @param[in] egress
13326  *   Table attribute.
13327  * @param[in] transfer
13328  *   Table attribute.
13329  * @param[in] color_reg_c_idx
13330  *   Reg C index for color match.
13331  *
13332  * @return
13333  *   0 on success, -1 otherwise and rte_errno is set.
13334  */
13335 static int
13336 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
13337                            struct mlx5_meter_domains_infos *mtb,
13338                            uint8_t egress, uint8_t transfer,
13339                            uint32_t color_reg_c_idx)
13340 {
13341         struct mlx5_priv *priv = dev->data->dev_private;
13342         struct mlx5_dev_ctx_shared *sh = priv->sh;
13343         struct mlx5_flow_dv_match_params mask = {
13344                 .size = sizeof(mask.buf),
13345         };
13346         struct mlx5_flow_dv_match_params value = {
13347                 .size = sizeof(value.buf),
13348         };
13349         struct mlx5dv_flow_matcher_attr dv_attr = {
13350                 .type = IBV_FLOW_ATTR_NORMAL,
13351                 .priority = 0,
13352                 .match_criteria_enable = 0,
13353                 .match_mask = (void *)&mask,
13354         };
13355         void *actions[METER_ACTIONS];
13356         struct mlx5_meter_domain_info *dtb;
13357         struct rte_flow_error error;
13358         int i = 0;
13359         int ret;
13360
13361         if (transfer)
13362                 dtb = &mtb->transfer;
13363         else if (egress)
13364                 dtb = &mtb->egress;
13365         else
13366                 dtb = &mtb->ingress;
13367         /* Create the meter table with METER level. */
13368         dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
13369                                             egress, transfer, false, NULL, 0,
13370                                             0, &error);
13371         if (!dtb->tbl) {
13372                 DRV_LOG(ERR, "Failed to create meter policer table.");
13373                 return -1;
13374         }
13375         /* Create the meter suffix table with SUFFIX level. */
13376         dtb->sfx_tbl = flow_dv_tbl_resource_get(dev,
13377                                             MLX5_FLOW_TABLE_LEVEL_SUFFIX,
13378                                             egress, transfer, false, NULL, 0,
13379                                             0, &error);
13380         if (!dtb->sfx_tbl) {
13381                 DRV_LOG(ERR, "Failed to create meter suffix table.");
13382                 return -1;
13383         }
13384         /* Create matchers, Any and Color. */
13385         dv_attr.priority = 3;
13386         dv_attr.match_criteria_enable = 0;
13387         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, dtb->tbl->obj,
13388                                                &dtb->any_matcher);
13389         if (ret) {
13390                 DRV_LOG(ERR, "Failed to create meter"
13391                              " policer default matcher.");
13392                 goto error_exit;
13393         }
13394         dv_attr.priority = 0;
13395         dv_attr.match_criteria_enable =
13396                                 1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
13397         flow_dv_match_meta_reg(mask.buf, value.buf, color_reg_c_idx,
13398                                rte_col_2_mlx5_col(RTE_COLORS), UINT8_MAX);
13399         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, dtb->tbl->obj,
13400                                                &dtb->color_matcher);
13401         if (ret) {
13402                 DRV_LOG(ERR, "Failed to create meter policer color matcher.");
13403                 goto error_exit;
13404         }
13405         if (mtb->count_actns[RTE_MTR_DROPPED])
13406                 actions[i++] = mtb->count_actns[RTE_MTR_DROPPED];
13407         actions[i++] = mtb->drop_actn;
13408         /* Default rule: lowest priority, match any, actions: drop. */
13409         ret = mlx5_flow_os_create_flow(dtb->any_matcher, (void *)&value, i,
13410                                        actions,
13411                                        &dtb->policer_rules[RTE_MTR_DROPPED]);
13412         if (ret) {
13413                 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
13414                 goto error_exit;
13415         }
13416         return 0;
13417 error_exit:
13418         return -1;
13419 }
13420
13421 /**
13422  * Create the needed meter and suffix tables.
13423  * Lock free, (mutex should be acquired by caller).
13424  *
13425  * @param[in] dev
13426  *   Pointer to Ethernet device.
13427  * @param[in] fm
13428  *   Pointer to the flow meter.
13429  *
13430  * @return
13431  *   Pointer to table set on success, NULL otherwise and rte_errno is set.
13432  */
13433 static struct mlx5_meter_domains_infos *
13434 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev,
13435                        const struct mlx5_flow_meter *fm)
13436 {
13437         struct mlx5_priv *priv = dev->data->dev_private;
13438         struct mlx5_meter_domains_infos *mtb;
13439         int ret;
13440         int i;
13441
13442         if (!priv->mtr_en) {
13443                 rte_errno = ENOTSUP;
13444                 return NULL;
13445         }
13446         mtb = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mtb), 0, SOCKET_ID_ANY);
13447         if (!mtb) {
13448                 DRV_LOG(ERR, "Failed to allocate memory for meter.");
13449                 return NULL;
13450         }
13451         /* Create meter count actions */
13452         for (i = 0; i <= RTE_MTR_DROPPED; i++) {
13453                 struct mlx5_flow_counter *cnt;
13454                 if (!fm->policer_stats.cnt[i])
13455                         continue;
13456                 cnt = flow_dv_counter_get_by_idx(dev,
13457                       fm->policer_stats.cnt[i], NULL);
13458                 mtb->count_actns[i] = cnt->action;
13459         }
13460         /* Create drop action. */
13461         ret = mlx5_flow_os_create_flow_action_drop(&mtb->drop_actn);
13462         if (ret) {
13463                 DRV_LOG(ERR, "Failed to create drop action.");
13464                 goto error_exit;
13465         }
13466         /* Egress meter table. */
13467         ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0, priv->mtr_color_reg);
13468         if (ret) {
13469                 DRV_LOG(ERR, "Failed to prepare egress meter table.");
13470                 goto error_exit;
13471         }
13472         /* Ingress meter table. */
13473         ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0, priv->mtr_color_reg);
13474         if (ret) {
13475                 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
13476                 goto error_exit;
13477         }
13478         /* FDB meter table. */
13479         if (priv->config.dv_esw_en) {
13480                 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1,
13481                                                  priv->mtr_color_reg);
13482                 if (ret) {
13483                         DRV_LOG(ERR, "Failed to prepare fdb meter table.");
13484                         goto error_exit;
13485                 }
13486         }
13487         return mtb;
13488 error_exit:
13489         flow_dv_destroy_mtr_tbl(dev, mtb);
13490         return NULL;
13491 }
13492
13493 /**
13494  * Destroy domain policer rule.
13495  *
13496  * @param[in] dt
13497  *   Pointer to domain table.
13498  */
13499 static void
13500 flow_dv_destroy_domain_policer_rule(struct mlx5_meter_domain_info *dt)
13501 {
13502         int i;
13503
13504         for (i = 0; i < RTE_MTR_DROPPED; i++) {
13505                 if (dt->policer_rules[i]) {
13506                         claim_zero(mlx5_flow_os_destroy_flow
13507                                    (dt->policer_rules[i]));
13508                         dt->policer_rules[i] = NULL;
13509                 }
13510         }
13511         if (dt->jump_actn) {
13512                 claim_zero(mlx5_flow_os_destroy_flow_action(dt->jump_actn));
13513                 dt->jump_actn = NULL;
13514         }
13515 }
13516
13517 /**
13518  * Destroy policer rules.
13519  *
13520  * @param[in] dev
13521  *   Pointer to Ethernet device.
13522  * @param[in] fm
13523  *   Pointer to flow meter structure.
13524  * @param[in] attr
13525  *   Pointer to flow attributes.
13526  *
13527  * @return
13528  *   Always 0.
13529  */
13530 static int
13531 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev __rte_unused,
13532                               const struct mlx5_flow_meter *fm,
13533                               const struct rte_flow_attr *attr)
13534 {
13535         struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
13536
13537         if (!mtb)
13538                 return 0;
13539         if (attr->egress)
13540                 flow_dv_destroy_domain_policer_rule(&mtb->egress);
13541         if (attr->ingress)
13542                 flow_dv_destroy_domain_policer_rule(&mtb->ingress);
13543         if (attr->transfer)
13544                 flow_dv_destroy_domain_policer_rule(&mtb->transfer);
13545         return 0;
13546 }
13547
13548 /**
13549  * Create specify domain meter policer rule.
13550  *
13551  * @param[in] fm
13552  *   Pointer to flow meter structure.
13553  * @param[in] mtb
13554  *   Pointer to DV meter table set.
13555  * @param[in] mtr_reg_c
13556  *   Color match REG_C.
13557  *
13558  * @return
13559  *   0 on success, -1 otherwise.
13560  */
13561 static int
13562 flow_dv_create_policer_forward_rule(struct mlx5_flow_meter *fm,
13563                                     struct mlx5_meter_domain_info *dtb,
13564                                     uint8_t mtr_reg_c)
13565 {
13566         struct mlx5_flow_dv_match_params matcher = {
13567                 .size = sizeof(matcher.buf),
13568         };
13569         struct mlx5_flow_dv_match_params value = {
13570                 .size = sizeof(value.buf),
13571         };
13572         struct mlx5_meter_domains_infos *mtb = fm->mfts;
13573         void *actions[METER_ACTIONS];
13574         int i;
13575         int ret = 0;
13576
13577         /* Create jump action. */
13578         if (!dtb->jump_actn)
13579                 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
13580                                 (dtb->sfx_tbl->obj, &dtb->jump_actn);
13581         if (ret) {
13582                 DRV_LOG(ERR, "Failed to create policer jump action.");
13583                 goto error;
13584         }
13585         for (i = 0; i < RTE_MTR_DROPPED; i++) {
13586                 int j = 0;
13587
13588                 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_reg_c,
13589                                        rte_col_2_mlx5_col(i), UINT8_MAX);
13590                 if (mtb->count_actns[i])
13591                         actions[j++] = mtb->count_actns[i];
13592                 if (fm->action[i] == MTR_POLICER_ACTION_DROP)
13593                         actions[j++] = mtb->drop_actn;
13594                 else
13595                         actions[j++] = dtb->jump_actn;
13596                 ret = mlx5_flow_os_create_flow(dtb->color_matcher,
13597                                                (void *)&value, j, actions,
13598                                                &dtb->policer_rules[i]);
13599                 if (ret) {
13600                         DRV_LOG(ERR, "Failed to create policer rule.");
13601                         goto error;
13602                 }
13603         }
13604         return 0;
13605 error:
13606         rte_errno = errno;
13607         return -1;
13608 }
13609
13610 /**
13611  * Create policer rules.
13612  *
13613  * @param[in] dev
13614  *   Pointer to Ethernet device.
13615  * @param[in] fm
13616  *   Pointer to flow meter structure.
13617  * @param[in] attr
13618  *   Pointer to flow attributes.
13619  *
13620  * @return
13621  *   0 on success, -1 otherwise.
13622  */
13623 static int
13624 flow_dv_create_policer_rules(struct rte_eth_dev *dev,
13625                              struct mlx5_flow_meter *fm,
13626                              const struct rte_flow_attr *attr)
13627 {
13628         struct mlx5_priv *priv = dev->data->dev_private;
13629         struct mlx5_meter_domains_infos *mtb = fm->mfts;
13630         int ret;
13631
13632         if (attr->egress) {
13633                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->egress,
13634                                                 priv->mtr_color_reg);
13635                 if (ret) {
13636                         DRV_LOG(ERR, "Failed to create egress policer.");
13637                         goto error;
13638                 }
13639         }
13640         if (attr->ingress) {
13641                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->ingress,
13642                                                 priv->mtr_color_reg);
13643                 if (ret) {
13644                         DRV_LOG(ERR, "Failed to create ingress policer.");
13645                         goto error;
13646                 }
13647         }
13648         if (attr->transfer) {
13649                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->transfer,
13650                                                 priv->mtr_color_reg);
13651                 if (ret) {
13652                         DRV_LOG(ERR, "Failed to create transfer policer.");
13653                         goto error;
13654                 }
13655         }
13656         return 0;
13657 error:
13658         flow_dv_destroy_policer_rules(dev, fm, attr);
13659         return -1;
13660 }
13661
13662 /**
13663  * Validate the batch counter support in root table.
13664  *
13665  * Create a simple flow with invalid counter and drop action on root table to
13666  * validate if batch counter with offset on root table is supported or not.
13667  *
13668  * @param[in] dev
13669  *   Pointer to rte_eth_dev structure.
13670  *
13671  * @return
13672  *   0 on success, a negative errno value otherwise and rte_errno is set.
13673  */
13674 int
13675 mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev)
13676 {
13677         struct mlx5_priv *priv = dev->data->dev_private;
13678         struct mlx5_dev_ctx_shared *sh = priv->sh;
13679         struct mlx5_flow_dv_match_params mask = {
13680                 .size = sizeof(mask.buf),
13681         };
13682         struct mlx5_flow_dv_match_params value = {
13683                 .size = sizeof(value.buf),
13684         };
13685         struct mlx5dv_flow_matcher_attr dv_attr = {
13686                 .type = IBV_FLOW_ATTR_NORMAL,
13687                 .priority = 0,
13688                 .match_criteria_enable = 0,
13689                 .match_mask = (void *)&mask,
13690         };
13691         void *actions[2] = { 0 };
13692         struct mlx5_flow_tbl_resource *tbl = NULL;
13693         struct mlx5_devx_obj *dcs = NULL;
13694         void *matcher = NULL;
13695         void *flow = NULL;
13696         int ret = -1;
13697
13698         tbl = flow_dv_tbl_resource_get(dev, 0, 0, 0, false, NULL, 0, 0, NULL);
13699         if (!tbl)
13700                 goto err;
13701         dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
13702         if (!dcs)
13703                 goto err;
13704         ret = mlx5_flow_os_create_flow_action_count(dcs->obj, UINT16_MAX,
13705                                                     &actions[0]);
13706         if (ret)
13707                 goto err;
13708         actions[1] = priv->drop_queue.hrxq->action;
13709         dv_attr.match_criteria_enable = flow_dv_matcher_enable(mask.buf);
13710         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj,
13711                                                &matcher);
13712         if (ret)
13713                 goto err;
13714         ret = mlx5_flow_os_create_flow(matcher, (void *)&value, 2,
13715                                        actions, &flow);
13716 err:
13717         /*
13718          * If batch counter with offset is not supported, the driver will not
13719          * validate the invalid offset value, flow create should success.
13720          * In this case, it means batch counter is not supported in root table.
13721          *
13722          * Otherwise, if flow create is failed, counter offset is supported.
13723          */
13724         if (flow) {
13725                 DRV_LOG(INFO, "Batch counter is not supported in root "
13726                               "table. Switch to fallback mode.");
13727                 rte_errno = ENOTSUP;
13728                 ret = -rte_errno;
13729                 claim_zero(mlx5_flow_os_destroy_flow(flow));
13730         } else {
13731                 /* Check matcher to make sure validate fail at flow create. */
13732                 if (!matcher || (matcher && errno != EINVAL))
13733                         DRV_LOG(ERR, "Unexpected error in counter offset "
13734                                      "support detection");
13735                 ret = 0;
13736         }
13737         if (actions[0])
13738                 claim_zero(mlx5_flow_os_destroy_flow_action(actions[0]));
13739         if (matcher)
13740                 claim_zero(mlx5_flow_os_destroy_flow_matcher(matcher));
13741         if (tbl)
13742                 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
13743         if (dcs)
13744                 claim_zero(mlx5_devx_cmd_destroy(dcs));
13745         return ret;
13746 }
13747
13748 /**
13749  * Query a devx counter.
13750  *
13751  * @param[in] dev
13752  *   Pointer to the Ethernet device structure.
13753  * @param[in] cnt
13754  *   Index to the flow counter.
13755  * @param[in] clear
13756  *   Set to clear the counter statistics.
13757  * @param[out] pkts
13758  *   The statistics value of packets.
13759  * @param[out] bytes
13760  *   The statistics value of bytes.
13761  *
13762  * @return
13763  *   0 on success, otherwise return -1.
13764  */
13765 static int
13766 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
13767                       uint64_t *pkts, uint64_t *bytes)
13768 {
13769         struct mlx5_priv *priv = dev->data->dev_private;
13770         struct mlx5_flow_counter *cnt;
13771         uint64_t inn_pkts, inn_bytes;
13772         int ret;
13773
13774         if (!priv->config.devx)
13775                 return -1;
13776
13777         ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
13778         if (ret)
13779                 return -1;
13780         cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
13781         *pkts = inn_pkts - cnt->hits;
13782         *bytes = inn_bytes - cnt->bytes;
13783         if (clear) {
13784                 cnt->hits = inn_pkts;
13785                 cnt->bytes = inn_bytes;
13786         }
13787         return 0;
13788 }
13789
13790 /**
13791  * Get aged-out flows.
13792  *
13793  * @param[in] dev
13794  *   Pointer to the Ethernet device structure.
13795  * @param[in] context
13796  *   The address of an array of pointers to the aged-out flows contexts.
13797  * @param[in] nb_contexts
13798  *   The length of context array pointers.
13799  * @param[out] error
13800  *   Perform verbose error reporting if not NULL. Initialized in case of
13801  *   error only.
13802  *
13803  * @return
13804  *   how many contexts get in success, otherwise negative errno value.
13805  *   if nb_contexts is 0, return the amount of all aged contexts.
13806  *   if nb_contexts is not 0 , return the amount of aged flows reported
13807  *   in the context array.
13808  * @note: only stub for now
13809  */
13810 static int
13811 flow_get_aged_flows(struct rte_eth_dev *dev,
13812                     void **context,
13813                     uint32_t nb_contexts,
13814                     struct rte_flow_error *error)
13815 {
13816         struct mlx5_priv *priv = dev->data->dev_private;
13817         struct mlx5_age_info *age_info;
13818         struct mlx5_age_param *age_param;
13819         struct mlx5_flow_counter *counter;
13820         struct mlx5_aso_age_action *act;
13821         int nb_flows = 0;
13822
13823         if (nb_contexts && !context)
13824                 return rte_flow_error_set(error, EINVAL,
13825                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13826                                           NULL, "empty context");
13827         age_info = GET_PORT_AGE_INFO(priv);
13828         rte_spinlock_lock(&age_info->aged_sl);
13829         LIST_FOREACH(act, &age_info->aged_aso, next) {
13830                 nb_flows++;
13831                 if (nb_contexts) {
13832                         context[nb_flows - 1] =
13833                                                 act->age_params.context;
13834                         if (!(--nb_contexts))
13835                                 break;
13836                 }
13837         }
13838         TAILQ_FOREACH(counter, &age_info->aged_counters, next) {
13839                 nb_flows++;
13840                 if (nb_contexts) {
13841                         age_param = MLX5_CNT_TO_AGE(counter);
13842                         context[nb_flows - 1] = age_param->context;
13843                         if (!(--nb_contexts))
13844                                 break;
13845                 }
13846         }
13847         rte_spinlock_unlock(&age_info->aged_sl);
13848         MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
13849         return nb_flows;
13850 }
13851
13852 /*
13853  * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
13854  */
13855 static uint32_t
13856 flow_dv_counter_allocate(struct rte_eth_dev *dev)
13857 {
13858         return flow_dv_counter_alloc(dev, 0);
13859 }
13860
13861 /**
13862  * Validate shared action.
13863  * Dispatcher for action type specific validation.
13864  *
13865  * @param[in] dev
13866  *   Pointer to the Ethernet device structure.
13867  * @param[in] conf
13868  *   Shared action configuration.
13869  * @param[in] action
13870  *   The shared action object to validate.
13871  * @param[out] error
13872  *   Perform verbose error reporting if not NULL. Initialized in case of
13873  *   error only.
13874  *
13875  * @return
13876  *   0 on success, otherwise negative errno value.
13877  */
13878 static int
13879 flow_dv_action_validate(struct rte_eth_dev *dev,
13880                         const struct rte_flow_shared_action_conf *conf,
13881                         const struct rte_flow_action *action,
13882                         struct rte_flow_error *err)
13883 {
13884         struct mlx5_priv *priv = dev->data->dev_private;
13885
13886         RTE_SET_USED(conf);
13887         switch (action->type) {
13888         case RTE_FLOW_ACTION_TYPE_RSS:
13889                 /*
13890                  * priv->obj_ops is set according to driver capabilities.
13891                  * When DevX capabilities are
13892                  * sufficient, it is set to devx_obj_ops.
13893                  * Otherwise, it is set to ibv_obj_ops.
13894                  * ibv_obj_ops doesn't support ind_table_modify operation.
13895                  * In this case the shared RSS action can't be used.
13896                  */
13897                 if (priv->obj_ops.ind_table_modify == NULL)
13898                         return rte_flow_error_set
13899                                         (err, ENOTSUP,
13900                                          RTE_FLOW_ERROR_TYPE_ACTION,
13901                                          NULL,
13902                                          "shared RSS action not supported");
13903                 return mlx5_validate_action_rss(dev, action, err);
13904         case RTE_FLOW_ACTION_TYPE_AGE:
13905                 if (!priv->sh->aso_age_mng)
13906                         return rte_flow_error_set(err, ENOTSUP,
13907                                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13908                                                 NULL,
13909                                              "shared age action not supported");
13910                 return flow_dv_validate_action_age(0, action, dev, err);
13911         default:
13912                 return rte_flow_error_set(err, ENOTSUP,
13913                                           RTE_FLOW_ERROR_TYPE_ACTION,
13914                                           NULL,
13915                                           "action type not supported");
13916         }
13917 }
13918
13919 static int
13920 flow_dv_sync_domain(struct rte_eth_dev *dev, uint32_t domains, uint32_t flags)
13921 {
13922         struct mlx5_priv *priv = dev->data->dev_private;
13923         int ret = 0;
13924
13925         if ((domains & MLX5_DOMAIN_BIT_NIC_RX) && priv->sh->rx_domain != NULL) {
13926                 ret = mlx5_os_flow_dr_sync_domain(priv->sh->rx_domain,
13927                                                 flags);
13928                 if (ret != 0)
13929                         return ret;
13930         }
13931         if ((domains & MLX5_DOMAIN_BIT_NIC_TX) && priv->sh->tx_domain != NULL) {
13932                 ret = mlx5_os_flow_dr_sync_domain(priv->sh->tx_domain, flags);
13933                 if (ret != 0)
13934                         return ret;
13935         }
13936         if ((domains & MLX5_DOMAIN_BIT_FDB) && priv->sh->fdb_domain != NULL) {
13937                 ret = mlx5_os_flow_dr_sync_domain(priv->sh->fdb_domain, flags);
13938                 if (ret != 0)
13939                         return ret;
13940         }
13941         return 0;
13942 }
13943
13944 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
13945         .validate = flow_dv_validate,
13946         .prepare = flow_dv_prepare,
13947         .translate = flow_dv_translate,
13948         .apply = flow_dv_apply,
13949         .remove = flow_dv_remove,
13950         .destroy = flow_dv_destroy,
13951         .query = flow_dv_query,
13952         .create_mtr_tbls = flow_dv_create_mtr_tbl,
13953         .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
13954         .create_policer_rules = flow_dv_create_policer_rules,
13955         .destroy_policer_rules = flow_dv_destroy_policer_rules,
13956         .counter_alloc = flow_dv_counter_allocate,
13957         .counter_free = flow_dv_counter_free,
13958         .counter_query = flow_dv_counter_query,
13959         .get_aged_flows = flow_get_aged_flows,
13960         .action_validate = flow_dv_action_validate,
13961         .action_create = flow_dv_action_create,
13962         .action_destroy = flow_dv_action_destroy,
13963         .action_update = flow_dv_action_update,
13964         .action_query = flow_dv_action_query,
13965         .sync_domain = flow_dv_sync_domain,
13966 };
13967
13968 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */
13969