drivers/net/mlx5/mlx5_flow_dv.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2018 Mellanox Technologies, Ltd
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdalign.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10
  11 #include <rte_common.h>
  12 #include <rte_ether.h>
  13 #include <ethdev_driver.h>
  14 #include <rte_flow.h>
  15 #include <rte_flow_driver.h>
  16 #include <rte_malloc.h>
  17 #include <rte_cycles.h>
  18 #include <rte_ip.h>
  19 #include <rte_gre.h>
  20 #include <rte_vxlan.h>
  21 #include <rte_gtp.h>
  22 #include <rte_eal_paging.h>
  23 #include <rte_mpls.h>
  24
  25 #include <mlx5_glue.h>
  26 #include <mlx5_devx_cmds.h>
  27 #include <mlx5_prm.h>
  28 #include <mlx5_malloc.h>
  29
  30 #include "mlx5_defs.h"
  31 #include "mlx5.h"
  32 #include "mlx5_common_os.h"
  33 #include "mlx5_flow.h"
  34 #include "mlx5_flow_os.h"
  35 #include "mlx5_rxtx.h"
  36 #include "rte_pmd_mlx5.h"
  37
  38 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
  39
  40 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
  41 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
  42 #endif
  43
  44 #ifndef HAVE_MLX5DV_DR_ESWITCH
  45 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
  46 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
  47 #endif
  48 #endif
  49
  50 #ifndef HAVE_MLX5DV_DR
  51 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
  52 #endif
  53
  54 /* VLAN header definitions */
  55 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
  56 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
  57 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
  58 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
  59 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
  60
  61 union flow_dv_attr {
  62         struct {
  63                 uint32_t valid:1;
  64                 uint32_t ipv4:1;
  65                 uint32_t ipv6:1;
  66                 uint32_t tcp:1;
  67                 uint32_t udp:1;
  68                 uint32_t reserved:27;
  69         };
  70         uint32_t attr;
  71 };
  72
  73 static int
  74 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
  75                              struct mlx5_flow_tbl_resource *tbl);
  76
  77 static int
  78 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
  79                                      uint32_t encap_decap_idx);
  80
  81 static int
  82 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
  83                                         uint32_t port_id);
  84 static void
  85 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss);
  86
  87 static int
  88 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
  89                                   uint32_t rix_jump);
  90
  91 /**
  92  * Initialize flow attributes structure according to flow items' types.
  93  *
  94  * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
  95  * mode. For tunnel mode, the items to be modified are the outermost ones.
  96  *
  97  * @param[in] item
  98  *   Pointer to item specification.
  99  * @param[out] attr
 100  *   Pointer to flow attributes structure.
 101  * @param[in] dev_flow
 102  *   Pointer to the sub flow.
 103  * @param[in] tunnel_decap
 104  *   Whether action is after tunnel decapsulation.
 105  */
 106 static void
 107 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
 108                   struct mlx5_flow *dev_flow, bool tunnel_decap)
 109 {
 110         uint64_t layers = dev_flow->handle->layers;
 111
 112         /*
 113          * If layers is already initialized, it means this dev_flow is the
 114          * suffix flow, the layers flags is set by the prefix flow. Need to
 115          * use the layer flags from prefix flow as the suffix flow may not
 116          * have the user defined items as the flow is split.
 117          */
 118         if (layers) {
 119                 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
 120                         attr->ipv4 = 1;
 121                 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
 122                         attr->ipv6 = 1;
 123                 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
 124                         attr->tcp = 1;
 125                 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
 126                         attr->udp = 1;
 127                 attr->valid = 1;
 128                 return;
 129         }
 130         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
 131                 uint8_t next_protocol = 0xff;
 132                 switch (item->type) {
 133                 case RTE_FLOW_ITEM_TYPE_GRE:
 134                 case RTE_FLOW_ITEM_TYPE_NVGRE:
 135                 case RTE_FLOW_ITEM_TYPE_VXLAN:
 136                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
 137                 case RTE_FLOW_ITEM_TYPE_GENEVE:
 138                 case RTE_FLOW_ITEM_TYPE_MPLS:
 139                         if (tunnel_decap)
 140                                 attr->attr = 0;
 141                         break;
 142                 case RTE_FLOW_ITEM_TYPE_IPV4:
 143                         if (!attr->ipv6)
 144                                 attr->ipv4 = 1;
 145                         if (item->mask != NULL &&
 146                             ((const struct rte_flow_item_ipv4 *)
 147                             item->mask)->hdr.next_proto_id)
 148                                 next_protocol =
 149                                     ((const struct rte_flow_item_ipv4 *)
 150                                       (item->spec))->hdr.next_proto_id &
 151                                     ((const struct rte_flow_item_ipv4 *)
 152                                       (item->mask))->hdr.next_proto_id;
 153                         if ((next_protocol == IPPROTO_IPIP ||
 154                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 155                                 attr->attr = 0;
 156                         break;
 157                 case RTE_FLOW_ITEM_TYPE_IPV6:
 158                         if (!attr->ipv4)
 159                                 attr->ipv6 = 1;
 160                         if (item->mask != NULL &&
 161                             ((const struct rte_flow_item_ipv6 *)
 162                             item->mask)->hdr.proto)
 163                                 next_protocol =
 164                                     ((const struct rte_flow_item_ipv6 *)
 165                                       (item->spec))->hdr.proto &
 166                                     ((const struct rte_flow_item_ipv6 *)
 167                                       (item->mask))->hdr.proto;
 168                         if ((next_protocol == IPPROTO_IPIP ||
 169                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 170                                 attr->attr = 0;
 171                         break;
 172                 case RTE_FLOW_ITEM_TYPE_UDP:
 173                         if (!attr->tcp)
 174                                 attr->udp = 1;
 175                         break;
 176                 case RTE_FLOW_ITEM_TYPE_TCP:
 177                         if (!attr->udp)
 178                                 attr->tcp = 1;
 179                         break;
 180                 default:
 181                         break;
 182                 }
 183         }
 184         attr->valid = 1;
 185 }
 186
 187 /**
 188  * Convert rte_mtr_color to mlx5 color.
 189  *
 190  * @param[in] rcol
 191  *   rte_mtr_color.
 192  *
 193  * @return
 194  *   mlx5 color.
 195  */
 196 static int
 197 rte_col_2_mlx5_col(enum rte_color rcol)
 198 {
 199         switch (rcol) {
 200         case RTE_COLOR_GREEN:
 201                 return MLX5_FLOW_COLOR_GREEN;
 202         case RTE_COLOR_YELLOW:
 203                 return MLX5_FLOW_COLOR_YELLOW;
 204         case RTE_COLOR_RED:
 205                 return MLX5_FLOW_COLOR_RED;
 206         default:
 207                 break;
 208         }
 209         return MLX5_FLOW_COLOR_UNDEFINED;
 210 }
 211
 212 struct field_modify_info {
 213         uint32_t size; /* Size of field in protocol header, in bytes. */
 214         uint32_t offset; /* Offset of field in protocol header, in bytes. */
 215         enum mlx5_modification_field id;
 216 };
 217
 218 struct field_modify_info modify_eth[] = {
 219         {4,  0, MLX5_MODI_OUT_DMAC_47_16},
 220         {2,  4, MLX5_MODI_OUT_DMAC_15_0},
 221         {4,  6, MLX5_MODI_OUT_SMAC_47_16},
 222         {2, 10, MLX5_MODI_OUT_SMAC_15_0},
 223         {0, 0, 0},
 224 };
 225
 226 struct field_modify_info modify_vlan_out_first_vid[] = {
 227         /* Size in bits !!! */
 228         {12, 0, MLX5_MODI_OUT_FIRST_VID},
 229         {0, 0, 0},
 230 };
 231
 232 struct field_modify_info modify_ipv4[] = {
 233         {1,  1, MLX5_MODI_OUT_IP_DSCP},
 234         {1,  8, MLX5_MODI_OUT_IPV4_TTL},
 235         {4, 12, MLX5_MODI_OUT_SIPV4},
 236         {4, 16, MLX5_MODI_OUT_DIPV4},
 237         {0, 0, 0},
 238 };
 239
 240 struct field_modify_info modify_ipv6[] = {
 241         {1,  0, MLX5_MODI_OUT_IP_DSCP},
 242         {1,  7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
 243         {4,  8, MLX5_MODI_OUT_SIPV6_127_96},
 244         {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
 245         {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
 246         {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
 247         {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
 248         {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
 249         {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
 250         {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
 251         {0, 0, 0},
 252 };
 253
 254 struct field_modify_info modify_udp[] = {
 255         {2, 0, MLX5_MODI_OUT_UDP_SPORT},
 256         {2, 2, MLX5_MODI_OUT_UDP_DPORT},
 257         {0, 0, 0},
 258 };
 259
 260 struct field_modify_info modify_tcp[] = {
 261         {2, 0, MLX5_MODI_OUT_TCP_SPORT},
 262         {2, 2, MLX5_MODI_OUT_TCP_DPORT},
 263         {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
 264         {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
 265         {0, 0, 0},
 266 };
 267
 268 static void
 269 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
 270                           uint8_t next_protocol, uint64_t *item_flags,
 271                           int *tunnel)
 272 {
 273         MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
 274                     item->type == RTE_FLOW_ITEM_TYPE_IPV6);
 275         if (next_protocol == IPPROTO_IPIP) {
 276                 *item_flags |= MLX5_FLOW_LAYER_IPIP;
 277                 *tunnel = 1;
 278         }
 279         if (next_protocol == IPPROTO_IPV6) {
 280                 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
 281                 *tunnel = 1;
 282         }
 283 }
 284
 285 /* Update VLAN's VID/PCP based on input rte_flow_action.
 286  *
 287  * @param[in] action
 288  *   Pointer to struct rte_flow_action.
 289  * @param[out] vlan
 290  *   Pointer to struct rte_vlan_hdr.
 291  */
 292 static void
 293 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
 294                          struct rte_vlan_hdr *vlan)
 295 {
 296         uint16_t vlan_tci;
 297         if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
 298                 vlan_tci =
 299                     ((const struct rte_flow_action_of_set_vlan_pcp *)
 300                                                action->conf)->vlan_pcp;
 301                 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
 302                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
 303                 vlan->vlan_tci |= vlan_tci;
 304         } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
 305                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
 306                 vlan->vlan_tci |= rte_be_to_cpu_16
 307                     (((const struct rte_flow_action_of_set_vlan_vid *)
 308                                              action->conf)->vlan_vid);
 309         }
 310 }
 311
 312 /**
 313  * Fetch 1, 2, 3 or 4 byte field from the byte array
 314  * and return as unsigned integer in host-endian format.
 315  *
 316  * @param[in] data
 317  *   Pointer to data array.
 318  * @param[in] size
 319  *   Size of field to extract.
 320  *
 321  * @return
 322  *   converted field in host endian format.
 323  */
 324 static inline uint32_t
 325 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
 326 {
 327         uint32_t ret;
 328
 329         switch (size) {
 330         case 1:
 331                 ret = *data;
 332                 break;
 333         case 2:
 334                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 335                 break;
 336         case 3:
 337                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 338                 ret = (ret << 8) | *(data + sizeof(uint16_t));
 339                 break;
 340         case 4:
 341                 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
 342                 break;
 343         default:
 344                 MLX5_ASSERT(false);
 345                 ret = 0;
 346                 break;
 347         }
 348         return ret;
 349 }
 350
 351 /**
 352  * Convert modify-header action to DV specification.
 353  *
 354  * Data length of each action is determined by provided field description
 355  * and the item mask. Data bit offset and width of each action is determined
 356  * by provided item mask.
 357  *
 358  * @param[in] item
 359  *   Pointer to item specification.
 360  * @param[in] field
 361  *   Pointer to field modification information.
 362  *     For MLX5_MODIFICATION_TYPE_SET specifies destination field.
 363  *     For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
 364  *     For MLX5_MODIFICATION_TYPE_COPY specifies source field.
 365  * @param[in] dcopy
 366  *   Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
 367  *   Negative offset value sets the same offset as source offset.
 368  *   size field is ignored, value is taken from source field.
 369  * @param[in,out] resource
 370  *   Pointer to the modify-header resource.
 371  * @param[in] type
 372  *   Type of modification.
 373  * @param[out] error
 374  *   Pointer to the error structure.
 375  *
 376  * @return
 377  *   0 on success, a negative errno value otherwise and rte_errno is set.
 378  */
 379 static int
 380 flow_dv_convert_modify_action(struct rte_flow_item *item,
 381                               struct field_modify_info *field,
 382                               struct field_modify_info *dcopy,
 383                               struct mlx5_flow_dv_modify_hdr_resource *resource,
 384                               uint32_t type, struct rte_flow_error *error)
 385 {
 386         uint32_t i = resource->actions_num;
 387         struct mlx5_modification_cmd *actions = resource->actions;
 388
 389         /*
 390          * The item and mask are provided in big-endian format.
 391          * The fields should be presented as in big-endian format either.
 392          * Mask must be always present, it defines the actual field width.
 393          */
 394         MLX5_ASSERT(item->mask);
 395         MLX5_ASSERT(field->size);
 396         do {
 397                 unsigned int size_b;
 398                 unsigned int off_b;
 399                 uint32_t mask;
 400                 uint32_t data;
 401
 402                 if (i >= MLX5_MAX_MODIFY_NUM)
 403                         return rte_flow_error_set(error, EINVAL,
 404                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 405                                  "too many items to modify");
 406                 /* Fetch variable byte size mask from the array. */
 407                 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
 408                                            field->offset, field->size);
 409                 if (!mask) {
 410                         ++field;
 411                         continue;
 412                 }
 413                 /* Deduce actual data width in bits from mask value. */
 414                 off_b = rte_bsf32(mask);
 415                 size_b = sizeof(uint32_t) * CHAR_BIT -
 416                          off_b - __builtin_clz(mask);
 417                 MLX5_ASSERT(size_b);
 418                 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
 419                 actions[i] = (struct mlx5_modification_cmd) {
 420                         .action_type = type,
 421                         .field = field->id,
 422                         .offset = off_b,
 423                         .length = size_b,
 424                 };
 425                 /* Convert entire record to expected big-endian format. */
 426                 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 427                 if (type == MLX5_MODIFICATION_TYPE_COPY) {
 428                         MLX5_ASSERT(dcopy);
 429                         actions[i].dst_field = dcopy->id;
 430                         actions[i].dst_offset =
 431                                 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
 432                         /* Convert entire record to big-endian format. */
 433                         actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
 434                         ++dcopy;
 435                 } else {
 436                         MLX5_ASSERT(item->spec);
 437                         data = flow_dv_fetch_field((const uint8_t *)item->spec +
 438                                                    field->offset, field->size);
 439                         /* Shift out the trailing masked bits from data. */
 440                         data = (data & mask) >> off_b;
 441                         actions[i].data1 = rte_cpu_to_be_32(data);
 442                 }
 443                 ++i;
 444                 ++field;
 445         } while (field->size);
 446         if (resource->actions_num == i)
 447                 return rte_flow_error_set(error, EINVAL,
 448                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 449                                           "invalid modification flow item");
 450         resource->actions_num = i;
 451         return 0;
 452 }
 453
 454 /**
 455  * Convert modify-header set IPv4 address action to DV specification.
 456  *
 457  * @param[in,out] resource
 458  *   Pointer to the modify-header resource.
 459  * @param[in] action
 460  *   Pointer to action specification.
 461  * @param[out] error
 462  *   Pointer to the error structure.
 463  *
 464  * @return
 465  *   0 on success, a negative errno value otherwise and rte_errno is set.
 466  */
 467 static int
 468 flow_dv_convert_action_modify_ipv4
 469                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 470                          const struct rte_flow_action *action,
 471                          struct rte_flow_error *error)
 472 {
 473         const struct rte_flow_action_set_ipv4 *conf =
 474                 (const struct rte_flow_action_set_ipv4 *)(action->conf);
 475         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
 476         struct rte_flow_item_ipv4 ipv4;
 477         struct rte_flow_item_ipv4 ipv4_mask;
 478
 479         memset(&ipv4, 0, sizeof(ipv4));
 480         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 481         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
 482                 ipv4.hdr.src_addr = conf->ipv4_addr;
 483                 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
 484         } else {
 485                 ipv4.hdr.dst_addr = conf->ipv4_addr;
 486                 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
 487         }
 488         item.spec = &ipv4;
 489         item.mask = &ipv4_mask;
 490         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
 491                                              MLX5_MODIFICATION_TYPE_SET, error);
 492 }
 493
 494 /**
 495  * Convert modify-header set IPv6 address action to DV specification.
 496  *
 497  * @param[in,out] resource
 498  *   Pointer to the modify-header resource.
 499  * @param[in] action
 500  *   Pointer to action specification.
 501  * @param[out] error
 502  *   Pointer to the error structure.
 503  *
 504  * @return
 505  *   0 on success, a negative errno value otherwise and rte_errno is set.
 506  */
 507 static int
 508 flow_dv_convert_action_modify_ipv6
 509                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 510                          const struct rte_flow_action *action,
 511                          struct rte_flow_error *error)
 512 {
 513         const struct rte_flow_action_set_ipv6 *conf =
 514                 (const struct rte_flow_action_set_ipv6 *)(action->conf);
 515         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
 516         struct rte_flow_item_ipv6 ipv6;
 517         struct rte_flow_item_ipv6 ipv6_mask;
 518
 519         memset(&ipv6, 0, sizeof(ipv6));
 520         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 521         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
 522                 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
 523                        sizeof(ipv6.hdr.src_addr));
 524                 memcpy(&ipv6_mask.hdr.src_addr,
 525                        &rte_flow_item_ipv6_mask.hdr.src_addr,
 526                        sizeof(ipv6.hdr.src_addr));
 527         } else {
 528                 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
 529                        sizeof(ipv6.hdr.dst_addr));
 530                 memcpy(&ipv6_mask.hdr.dst_addr,
 531                        &rte_flow_item_ipv6_mask.hdr.dst_addr,
 532                        sizeof(ipv6.hdr.dst_addr));
 533         }
 534         item.spec = &ipv6;
 535         item.mask = &ipv6_mask;
 536         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
 537                                              MLX5_MODIFICATION_TYPE_SET, error);
 538 }
 539
 540 /**
 541  * Convert modify-header set MAC address action to DV specification.
 542  *
 543  * @param[in,out] resource
 544  *   Pointer to the modify-header resource.
 545  * @param[in] action
 546  *   Pointer to action specification.
 547  * @param[out] error
 548  *   Pointer to the error structure.
 549  *
 550  * @return
 551  *   0 on success, a negative errno value otherwise and rte_errno is set.
 552  */
 553 static int
 554 flow_dv_convert_action_modify_mac
 555                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 556                          const struct rte_flow_action *action,
 557                          struct rte_flow_error *error)
 558 {
 559         const struct rte_flow_action_set_mac *conf =
 560                 (const struct rte_flow_action_set_mac *)(action->conf);
 561         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
 562         struct rte_flow_item_eth eth;
 563         struct rte_flow_item_eth eth_mask;
 564
 565         memset(&eth, 0, sizeof(eth));
 566         memset(&eth_mask, 0, sizeof(eth_mask));
 567         if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
 568                 memcpy(&eth.src.addr_bytes, &conf->mac_addr,
 569                        sizeof(eth.src.addr_bytes));
 570                 memcpy(&eth_mask.src.addr_bytes,
 571                        &rte_flow_item_eth_mask.src.addr_bytes,
 572                        sizeof(eth_mask.src.addr_bytes));
 573         } else {
 574                 memcpy(&eth.dst.addr_bytes, &conf->mac_addr,
 575                        sizeof(eth.dst.addr_bytes));
 576                 memcpy(&eth_mask.dst.addr_bytes,
 577                        &rte_flow_item_eth_mask.dst.addr_bytes,
 578                        sizeof(eth_mask.dst.addr_bytes));
 579         }
 580         item.spec = &eth;
 581         item.mask = &eth_mask;
 582         return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
 583                                              MLX5_MODIFICATION_TYPE_SET, error);
 584 }
 585
 586 /**
 587  * Convert modify-header set VLAN VID action to DV specification.
 588  *
 589  * @param[in,out] resource
 590  *   Pointer to the modify-header resource.
 591  * @param[in] action
 592  *   Pointer to action specification.
 593  * @param[out] error
 594  *   Pointer to the error structure.
 595  *
 596  * @return
 597  *   0 on success, a negative errno value otherwise and rte_errno is set.
 598  */
 599 static int
 600 flow_dv_convert_action_modify_vlan_vid
 601                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 602                          const struct rte_flow_action *action,
 603                          struct rte_flow_error *error)
 604 {
 605         const struct rte_flow_action_of_set_vlan_vid *conf =
 606                 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
 607         int i = resource->actions_num;
 608         struct mlx5_modification_cmd *actions = resource->actions;
 609         struct field_modify_info *field = modify_vlan_out_first_vid;
 610
 611         if (i >= MLX5_MAX_MODIFY_NUM)
 612                 return rte_flow_error_set(error, EINVAL,
 613                          RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 614                          "too many items to modify");
 615         actions[i] = (struct mlx5_modification_cmd) {
 616                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 617                 .field = field->id,
 618                 .length = field->size,
 619                 .offset = field->offset,
 620         };
 621         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 622         actions[i].data1 = conf->vlan_vid;
 623         actions[i].data1 = actions[i].data1 << 16;
 624         resource->actions_num = ++i;
 625         return 0;
 626 }
 627
 628 /**
 629  * Convert modify-header set TP action to DV specification.
 630  *
 631  * @param[in,out] resource
 632  *   Pointer to the modify-header resource.
 633  * @param[in] action
 634  *   Pointer to action specification.
 635  * @param[in] items
 636  *   Pointer to rte_flow_item objects list.
 637  * @param[in] attr
 638  *   Pointer to flow attributes structure.
 639  * @param[in] dev_flow
 640  *   Pointer to the sub flow.
 641  * @param[in] tunnel_decap
 642  *   Whether action is after tunnel decapsulation.
 643  * @param[out] error
 644  *   Pointer to the error structure.
 645  *
 646  * @return
 647  *   0 on success, a negative errno value otherwise and rte_errno is set.
 648  */
 649 static int
 650 flow_dv_convert_action_modify_tp
 651                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 652                          const struct rte_flow_action *action,
 653                          const struct rte_flow_item *items,
 654                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 655                          bool tunnel_decap, struct rte_flow_error *error)
 656 {
 657         const struct rte_flow_action_set_tp *conf =
 658                 (const struct rte_flow_action_set_tp *)(action->conf);
 659         struct rte_flow_item item;
 660         struct rte_flow_item_udp udp;
 661         struct rte_flow_item_udp udp_mask;
 662         struct rte_flow_item_tcp tcp;
 663         struct rte_flow_item_tcp tcp_mask;
 664         struct field_modify_info *field;
 665
 666         if (!attr->valid)
 667                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 668         if (attr->udp) {
 669                 memset(&udp, 0, sizeof(udp));
 670                 memset(&udp_mask, 0, sizeof(udp_mask));
 671                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 672                         udp.hdr.src_port = conf->port;
 673                         udp_mask.hdr.src_port =
 674                                         rte_flow_item_udp_mask.hdr.src_port;
 675                 } else {
 676                         udp.hdr.dst_port = conf->port;
 677                         udp_mask.hdr.dst_port =
 678                                         rte_flow_item_udp_mask.hdr.dst_port;
 679                 }
 680                 item.type = RTE_FLOW_ITEM_TYPE_UDP;
 681                 item.spec = &udp;
 682                 item.mask = &udp_mask;
 683                 field = modify_udp;
 684         } else {
 685                 MLX5_ASSERT(attr->tcp);
 686                 memset(&tcp, 0, sizeof(tcp));
 687                 memset(&tcp_mask, 0, sizeof(tcp_mask));
 688                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 689                         tcp.hdr.src_port = conf->port;
 690                         tcp_mask.hdr.src_port =
 691                                         rte_flow_item_tcp_mask.hdr.src_port;
 692                 } else {
 693                         tcp.hdr.dst_port = conf->port;
 694                         tcp_mask.hdr.dst_port =
 695                                         rte_flow_item_tcp_mask.hdr.dst_port;
 696                 }
 697                 item.type = RTE_FLOW_ITEM_TYPE_TCP;
 698                 item.spec = &tcp;
 699                 item.mask = &tcp_mask;
 700                 field = modify_tcp;
 701         }
 702         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 703                                              MLX5_MODIFICATION_TYPE_SET, error);
 704 }
 705
 706 /**
 707  * Convert modify-header set TTL action to DV specification.
 708  *
 709  * @param[in,out] resource
 710  *   Pointer to the modify-header resource.
 711  * @param[in] action
 712  *   Pointer to action specification.
 713  * @param[in] items
 714  *   Pointer to rte_flow_item objects list.
 715  * @param[in] attr
 716  *   Pointer to flow attributes structure.
 717  * @param[in] dev_flow
 718  *   Pointer to the sub flow.
 719  * @param[in] tunnel_decap
 720  *   Whether action is after tunnel decapsulation.
 721  * @param[out] error
 722  *   Pointer to the error structure.
 723  *
 724  * @return
 725  *   0 on success, a negative errno value otherwise and rte_errno is set.
 726  */
 727 static int
 728 flow_dv_convert_action_modify_ttl
 729                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 730                          const struct rte_flow_action *action,
 731                          const struct rte_flow_item *items,
 732                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 733                          bool tunnel_decap, struct rte_flow_error *error)
 734 {
 735         const struct rte_flow_action_set_ttl *conf =
 736                 (const struct rte_flow_action_set_ttl *)(action->conf);
 737         struct rte_flow_item item;
 738         struct rte_flow_item_ipv4 ipv4;
 739         struct rte_flow_item_ipv4 ipv4_mask;
 740         struct rte_flow_item_ipv6 ipv6;
 741         struct rte_flow_item_ipv6 ipv6_mask;
 742         struct field_modify_info *field;
 743
 744         if (!attr->valid)
 745                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 746         if (attr->ipv4) {
 747                 memset(&ipv4, 0, sizeof(ipv4));
 748                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 749                 ipv4.hdr.time_to_live = conf->ttl_value;
 750                 ipv4_mask.hdr.time_to_live = 0xFF;
 751                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 752                 item.spec = &ipv4;
 753                 item.mask = &ipv4_mask;
 754                 field = modify_ipv4;
 755         } else {
 756                 MLX5_ASSERT(attr->ipv6);
 757                 memset(&ipv6, 0, sizeof(ipv6));
 758                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 759                 ipv6.hdr.hop_limits = conf->ttl_value;
 760                 ipv6_mask.hdr.hop_limits = 0xFF;
 761                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 762                 item.spec = &ipv6;
 763                 item.mask = &ipv6_mask;
 764                 field = modify_ipv6;
 765         }
 766         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 767                                              MLX5_MODIFICATION_TYPE_SET, error);
 768 }
 769
 770 /**
 771  * Convert modify-header decrement TTL action to DV specification.
 772  *
 773  * @param[in,out] resource
 774  *   Pointer to the modify-header resource.
 775  * @param[in] action
 776  *   Pointer to action specification.
 777  * @param[in] items
 778  *   Pointer to rte_flow_item objects list.
 779  * @param[in] attr
 780  *   Pointer to flow attributes structure.
 781  * @param[in] dev_flow
 782  *   Pointer to the sub flow.
 783  * @param[in] tunnel_decap
 784  *   Whether action is after tunnel decapsulation.
 785  * @param[out] error
 786  *   Pointer to the error structure.
 787  *
 788  * @return
 789  *   0 on success, a negative errno value otherwise and rte_errno is set.
 790  */
 791 static int
 792 flow_dv_convert_action_modify_dec_ttl
 793                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 794                          const struct rte_flow_item *items,
 795                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 796                          bool tunnel_decap, struct rte_flow_error *error)
 797 {
 798         struct rte_flow_item item;
 799         struct rte_flow_item_ipv4 ipv4;
 800         struct rte_flow_item_ipv4 ipv4_mask;
 801         struct rte_flow_item_ipv6 ipv6;
 802         struct rte_flow_item_ipv6 ipv6_mask;
 803         struct field_modify_info *field;
 804
 805         if (!attr->valid)
 806                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 807         if (attr->ipv4) {
 808                 memset(&ipv4, 0, sizeof(ipv4));
 809                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 810                 ipv4.hdr.time_to_live = 0xFF;
 811                 ipv4_mask.hdr.time_to_live = 0xFF;
 812                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 813                 item.spec = &ipv4;
 814                 item.mask = &ipv4_mask;
 815                 field = modify_ipv4;
 816         } else {
 817                 MLX5_ASSERT(attr->ipv6);
 818                 memset(&ipv6, 0, sizeof(ipv6));
 819                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 820                 ipv6.hdr.hop_limits = 0xFF;
 821                 ipv6_mask.hdr.hop_limits = 0xFF;
 822                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 823                 item.spec = &ipv6;
 824                 item.mask = &ipv6_mask;
 825                 field = modify_ipv6;
 826         }
 827         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 828                                              MLX5_MODIFICATION_TYPE_ADD, error);
 829 }
 830
 831 /**
 832  * Convert modify-header increment/decrement TCP Sequence number
 833  * to DV specification.
 834  *
 835  * @param[in,out] resource
 836  *   Pointer to the modify-header resource.
 837  * @param[in] action
 838  *   Pointer to action specification.
 839  * @param[out] error
 840  *   Pointer to the error structure.
 841  *
 842  * @return
 843  *   0 on success, a negative errno value otherwise and rte_errno is set.
 844  */
 845 static int
 846 flow_dv_convert_action_modify_tcp_seq
 847                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 848                          const struct rte_flow_action *action,
 849                          struct rte_flow_error *error)
 850 {
 851         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 852         uint64_t value = rte_be_to_cpu_32(*conf);
 853         struct rte_flow_item item;
 854         struct rte_flow_item_tcp tcp;
 855         struct rte_flow_item_tcp tcp_mask;
 856
 857         memset(&tcp, 0, sizeof(tcp));
 858         memset(&tcp_mask, 0, sizeof(tcp_mask));
 859         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
 860                 /*
 861                  * The HW has no decrement operation, only increment operation.
 862                  * To simulate decrement X from Y using increment operation
 863                  * we need to add UINT32_MAX X times to Y.
 864                  * Each adding of UINT32_MAX decrements Y by 1.
 865                  */
 866                 value *= UINT32_MAX;
 867         tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
 868         tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
 869         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 870         item.spec = &tcp;
 871         item.mask = &tcp_mask;
 872         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 873                                              MLX5_MODIFICATION_TYPE_ADD, error);
 874 }
 875
 876 /**
 877  * Convert modify-header increment/decrement TCP Acknowledgment number
 878  * to DV specification.
 879  *
 880  * @param[in,out] resource
 881  *   Pointer to the modify-header resource.
 882  * @param[in] action
 883  *   Pointer to action specification.
 884  * @param[out] error
 885  *   Pointer to the error structure.
 886  *
 887  * @return
 888  *   0 on success, a negative errno value otherwise and rte_errno is set.
 889  */
 890 static int
 891 flow_dv_convert_action_modify_tcp_ack
 892                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 893                          const struct rte_flow_action *action,
 894                          struct rte_flow_error *error)
 895 {
 896         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 897         uint64_t value = rte_be_to_cpu_32(*conf);
 898         struct rte_flow_item item;
 899         struct rte_flow_item_tcp tcp;
 900         struct rte_flow_item_tcp tcp_mask;
 901
 902         memset(&tcp, 0, sizeof(tcp));
 903         memset(&tcp_mask, 0, sizeof(tcp_mask));
 904         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
 905                 /*
 906                  * The HW has no decrement operation, only increment operation.
 907                  * To simulate decrement X from Y using increment operation
 908                  * we need to add UINT32_MAX X times to Y.
 909                  * Each adding of UINT32_MAX decrements Y by 1.
 910                  */
 911                 value *= UINT32_MAX;
 912         tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
 913         tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
 914         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 915         item.spec = &tcp;
 916         item.mask = &tcp_mask;
 917         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 918                                              MLX5_MODIFICATION_TYPE_ADD, error);
 919 }
 920
 921 static enum mlx5_modification_field reg_to_field[] = {
 922         [REG_NON] = MLX5_MODI_OUT_NONE,
 923         [REG_A] = MLX5_MODI_META_DATA_REG_A,
 924         [REG_B] = MLX5_MODI_META_DATA_REG_B,
 925         [REG_C_0] = MLX5_MODI_META_REG_C_0,
 926         [REG_C_1] = MLX5_MODI_META_REG_C_1,
 927         [REG_C_2] = MLX5_MODI_META_REG_C_2,
 928         [REG_C_3] = MLX5_MODI_META_REG_C_3,
 929         [REG_C_4] = MLX5_MODI_META_REG_C_4,
 930         [REG_C_5] = MLX5_MODI_META_REG_C_5,
 931         [REG_C_6] = MLX5_MODI_META_REG_C_6,
 932         [REG_C_7] = MLX5_MODI_META_REG_C_7,
 933 };
 934
 935 /**
 936  * Convert register set to DV specification.
 937  *
 938  * @param[in,out] resource
 939  *   Pointer to the modify-header resource.
 940  * @param[in] action
 941  *   Pointer to action specification.
 942  * @param[out] error
 943  *   Pointer to the error structure.
 944  *
 945  * @return
 946  *   0 on success, a negative errno value otherwise and rte_errno is set.
 947  */
 948 static int
 949 flow_dv_convert_action_set_reg
 950                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 951                          const struct rte_flow_action *action,
 952                          struct rte_flow_error *error)
 953 {
 954         const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
 955         struct mlx5_modification_cmd *actions = resource->actions;
 956         uint32_t i = resource->actions_num;
 957
 958         if (i >= MLX5_MAX_MODIFY_NUM)
 959                 return rte_flow_error_set(error, EINVAL,
 960                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 961                                           "too many items to modify");
 962         MLX5_ASSERT(conf->id != REG_NON);
 963         MLX5_ASSERT(conf->id < (enum modify_reg)RTE_DIM(reg_to_field));
 964         actions[i] = (struct mlx5_modification_cmd) {
 965                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 966                 .field = reg_to_field[conf->id],
 967         };
 968         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 969         actions[i].data1 = rte_cpu_to_be_32(conf->data);
 970         ++i;
 971         resource->actions_num = i;
 972         return 0;
 973 }
 974
 975 /**
 976  * Convert SET_TAG action to DV specification.
 977  *
 978  * @param[in] dev
 979  *   Pointer to the rte_eth_dev structure.
 980  * @param[in,out] resource
 981  *   Pointer to the modify-header resource.
 982  * @param[in] conf
 983  *   Pointer to action specification.
 984  * @param[out] error
 985  *   Pointer to the error structure.
 986  *
 987  * @return
 988  *   0 on success, a negative errno value otherwise and rte_errno is set.
 989  */
 990 static int
 991 flow_dv_convert_action_set_tag
 992                         (struct rte_eth_dev *dev,
 993                          struct mlx5_flow_dv_modify_hdr_resource *resource,
 994                          const struct rte_flow_action_set_tag *conf,
 995                          struct rte_flow_error *error)
 996 {
 997         rte_be32_t data = rte_cpu_to_be_32(conf->data);
 998         rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
 999         struct rte_flow_item item = {
1000                 .spec = &data,
1001                 .mask = &mask,
1002         };
1003         struct field_modify_info reg_c_x[] = {
1004                 [1] = {0, 0, 0},
1005         };
1006         enum mlx5_modification_field reg_type;
1007         int ret;
1008
1009         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1010         if (ret < 0)
1011                 return ret;
1012         MLX5_ASSERT(ret != REG_NON);
1013         MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1014         reg_type = reg_to_field[ret];
1015         MLX5_ASSERT(reg_type > 0);
1016         reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1017         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1018                                              MLX5_MODIFICATION_TYPE_SET, error);
1019 }
1020
1021 /**
1022  * Convert internal COPY_REG action to DV specification.
1023  *
1024  * @param[in] dev
1025  *   Pointer to the rte_eth_dev structure.
1026  * @param[in,out] res
1027  *   Pointer to the modify-header resource.
1028  * @param[in] action
1029  *   Pointer to action specification.
1030  * @param[out] error
1031  *   Pointer to the error structure.
1032  *
1033  * @return
1034  *   0 on success, a negative errno value otherwise and rte_errno is set.
1035  */
1036 static int
1037 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1038                                  struct mlx5_flow_dv_modify_hdr_resource *res,
1039                                  const struct rte_flow_action *action,
1040                                  struct rte_flow_error *error)
1041 {
1042         const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1043         rte_be32_t mask = RTE_BE32(UINT32_MAX);
1044         struct rte_flow_item item = {
1045                 .spec = NULL,
1046                 .mask = &mask,
1047         };
1048         struct field_modify_info reg_src[] = {
1049                 {4, 0, reg_to_field[conf->src]},
1050                 {0, 0, 0},
1051         };
1052         struct field_modify_info reg_dst = {
1053                 .offset = 0,
1054                 .id = reg_to_field[conf->dst],
1055         };
1056         /* Adjust reg_c[0] usage according to reported mask. */
1057         if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1058                 struct mlx5_priv *priv = dev->data->dev_private;
1059                 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1060
1061                 MLX5_ASSERT(reg_c0);
1062                 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1063                 if (conf->dst == REG_C_0) {
1064                         /* Copy to reg_c[0], within mask only. */
1065                         reg_dst.offset = rte_bsf32(reg_c0);
1066                         /*
1067                          * Mask is ignoring the enianness, because
1068                          * there is no conversion in datapath.
1069                          */
1070 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1071                         /* Copy from destination lower bits to reg_c[0]. */
1072                         mask = reg_c0 >> reg_dst.offset;
1073 #else
1074                         /* Copy from destination upper bits to reg_c[0]. */
1075                         mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1076                                           rte_fls_u32(reg_c0));
1077 #endif
1078                 } else {
1079                         mask = rte_cpu_to_be_32(reg_c0);
1080 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1081                         /* Copy from reg_c[0] to destination lower bits. */
1082                         reg_dst.offset = 0;
1083 #else
1084                         /* Copy from reg_c[0] to destination upper bits. */
1085                         reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1086                                          (rte_fls_u32(reg_c0) -
1087                                           rte_bsf32(reg_c0));
1088 #endif
1089                 }
1090         }
1091         return flow_dv_convert_modify_action(&item,
1092                                              reg_src, &reg_dst, res,
1093                                              MLX5_MODIFICATION_TYPE_COPY,
1094                                              error);
1095 }
1096
1097 /**
1098  * Convert MARK action to DV specification. This routine is used
1099  * in extensive metadata only and requires metadata register to be
1100  * handled. In legacy mode hardware tag resource is engaged.
1101  *
1102  * @param[in] dev
1103  *   Pointer to the rte_eth_dev structure.
1104  * @param[in] conf
1105  *   Pointer to MARK action specification.
1106  * @param[in,out] resource
1107  *   Pointer to the modify-header resource.
1108  * @param[out] error
1109  *   Pointer to the error structure.
1110  *
1111  * @return
1112  *   0 on success, a negative errno value otherwise and rte_errno is set.
1113  */
1114 static int
1115 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1116                             const struct rte_flow_action_mark *conf,
1117                             struct mlx5_flow_dv_modify_hdr_resource *resource,
1118                             struct rte_flow_error *error)
1119 {
1120         struct mlx5_priv *priv = dev->data->dev_private;
1121         rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1122                                            priv->sh->dv_mark_mask);
1123         rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1124         struct rte_flow_item item = {
1125                 .spec = &data,
1126                 .mask = &mask,
1127         };
1128         struct field_modify_info reg_c_x[] = {
1129                 [1] = {0, 0, 0},
1130         };
1131         int reg;
1132
1133         if (!mask)
1134                 return rte_flow_error_set(error, EINVAL,
1135                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1136                                           NULL, "zero mark action mask");
1137         reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1138         if (reg < 0)
1139                 return reg;
1140         MLX5_ASSERT(reg > 0);
1141         if (reg == REG_C_0) {
1142                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1143                 uint32_t shl_c0 = rte_bsf32(msk_c0);
1144
1145                 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1146                 mask = rte_cpu_to_be_32(mask) & msk_c0;
1147                 mask = rte_cpu_to_be_32(mask << shl_c0);
1148         }
1149         reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1150         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1151                                              MLX5_MODIFICATION_TYPE_SET, error);
1152 }
1153
1154 /**
1155  * Get metadata register index for specified steering domain.
1156  *
1157  * @param[in] dev
1158  *   Pointer to the rte_eth_dev structure.
1159  * @param[in] attr
1160  *   Attributes of flow to determine steering domain.
1161  * @param[out] error
1162  *   Pointer to the error structure.
1163  *
1164  * @return
1165  *   positive index on success, a negative errno value otherwise
1166  *   and rte_errno is set.
1167  */
1168 static enum modify_reg
1169 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1170                          const struct rte_flow_attr *attr,
1171                          struct rte_flow_error *error)
1172 {
1173         int reg =
1174                 mlx5_flow_get_reg_id(dev, attr->transfer ?
1175                                           MLX5_METADATA_FDB :
1176                                             attr->egress ?
1177                                             MLX5_METADATA_TX :
1178                                             MLX5_METADATA_RX, 0, error);
1179         if (reg < 0)
1180                 return rte_flow_error_set(error,
1181                                           ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1182                                           NULL, "unavailable "
1183                                           "metadata register");
1184         return reg;
1185 }
1186
1187 /**
1188  * Convert SET_META action to DV specification.
1189  *
1190  * @param[in] dev
1191  *   Pointer to the rte_eth_dev structure.
1192  * @param[in,out] resource
1193  *   Pointer to the modify-header resource.
1194  * @param[in] attr
1195  *   Attributes of flow that includes this item.
1196  * @param[in] conf
1197  *   Pointer to action specification.
1198  * @param[out] error
1199  *   Pointer to the error structure.
1200  *
1201  * @return
1202  *   0 on success, a negative errno value otherwise and rte_errno is set.
1203  */
1204 static int
1205 flow_dv_convert_action_set_meta
1206                         (struct rte_eth_dev *dev,
1207                          struct mlx5_flow_dv_modify_hdr_resource *resource,
1208                          const struct rte_flow_attr *attr,
1209                          const struct rte_flow_action_set_meta *conf,
1210                          struct rte_flow_error *error)
1211 {
1212         uint32_t data = conf->data;
1213         uint32_t mask = conf->mask;
1214         struct rte_flow_item item = {
1215                 .spec = &data,
1216                 .mask = &mask,
1217         };
1218         struct field_modify_info reg_c_x[] = {
1219                 [1] = {0, 0, 0},
1220         };
1221         int reg = flow_dv_get_metadata_reg(dev, attr, error);
1222
1223         if (reg < 0)
1224                 return reg;
1225         MLX5_ASSERT(reg != REG_NON);
1226         /*
1227          * In datapath code there is no endianness
1228          * coversions for perfromance reasons, all
1229          * pattern conversions are done in rte_flow.
1230          */
1231         if (reg == REG_C_0) {
1232                 struct mlx5_priv *priv = dev->data->dev_private;
1233                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1234                 uint32_t shl_c0;
1235
1236                 MLX5_ASSERT(msk_c0);
1237 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1238                 shl_c0 = rte_bsf32(msk_c0);
1239 #else
1240                 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1241 #endif
1242                 mask <<= shl_c0;
1243                 data <<= shl_c0;
1244                 MLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1245         }
1246         reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1247         /* The routine expects parameters in memory as big-endian ones. */
1248         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1249                                              MLX5_MODIFICATION_TYPE_SET, error);
1250 }
1251
1252 /**
1253  * Convert modify-header set IPv4 DSCP action to DV specification.
1254  *
1255  * @param[in,out] resource
1256  *   Pointer to the modify-header resource.
1257  * @param[in] action
1258  *   Pointer to action specification.
1259  * @param[out] error
1260  *   Pointer to the error structure.
1261  *
1262  * @return
1263  *   0 on success, a negative errno value otherwise and rte_errno is set.
1264  */
1265 static int
1266 flow_dv_convert_action_modify_ipv4_dscp
1267                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1268                          const struct rte_flow_action *action,
1269                          struct rte_flow_error *error)
1270 {
1271         const struct rte_flow_action_set_dscp *conf =
1272                 (const struct rte_flow_action_set_dscp *)(action->conf);
1273         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1274         struct rte_flow_item_ipv4 ipv4;
1275         struct rte_flow_item_ipv4 ipv4_mask;
1276
1277         memset(&ipv4, 0, sizeof(ipv4));
1278         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1279         ipv4.hdr.type_of_service = conf->dscp;
1280         ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1281         item.spec = &ipv4;
1282         item.mask = &ipv4_mask;
1283         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1284                                              MLX5_MODIFICATION_TYPE_SET, error);
1285 }
1286
1287 /**
1288  * Convert modify-header set IPv6 DSCP action to DV specification.
1289  *
1290  * @param[in,out] resource
1291  *   Pointer to the modify-header resource.
1292  * @param[in] action
1293  *   Pointer to action specification.
1294  * @param[out] error
1295  *   Pointer to the error structure.
1296  *
1297  * @return
1298  *   0 on success, a negative errno value otherwise and rte_errno is set.
1299  */
1300 static int
1301 flow_dv_convert_action_modify_ipv6_dscp
1302                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1303                          const struct rte_flow_action *action,
1304                          struct rte_flow_error *error)
1305 {
1306         const struct rte_flow_action_set_dscp *conf =
1307                 (const struct rte_flow_action_set_dscp *)(action->conf);
1308         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1309         struct rte_flow_item_ipv6 ipv6;
1310         struct rte_flow_item_ipv6 ipv6_mask;
1311
1312         memset(&ipv6, 0, sizeof(ipv6));
1313         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1314         /*
1315          * Even though the DSCP bits offset of IPv6 is not byte aligned,
1316          * rdma-core only accept the DSCP bits byte aligned start from
1317          * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1318          * bits in IPv6 case as rdma-core requires byte aligned value.
1319          */
1320         ipv6.hdr.vtc_flow = conf->dscp;
1321         ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1322         item.spec = &ipv6;
1323         item.mask = &ipv6_mask;
1324         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1325                                              MLX5_MODIFICATION_TYPE_SET, error);
1326 }
1327
1328 static void
1329 mlx5_flow_field_id_to_modify_info
1330                 (const struct rte_flow_action_modify_data *data,
1331                  struct field_modify_info *info,
1332                  uint32_t *mask, uint32_t *value, uint32_t width,
1333                  struct rte_eth_dev *dev,
1334                  const struct rte_flow_attr *attr,
1335                  struct rte_flow_error *error)
1336 {
1337         uint32_t idx = 0;
1338         switch (data->field) {
1339         case RTE_FLOW_FIELD_START:
1340                 /* not supported yet */
1341                 MLX5_ASSERT(false);
1342                 break;
1343         case RTE_FLOW_FIELD_MAC_DST:
1344                 if (mask) {
1345                         if (data->offset < 32) {
1346                                 info[idx] = (struct field_modify_info){4, 0,
1347                                                 MLX5_MODI_OUT_DMAC_47_16};
1348                                 if (width < 32) {
1349                                         mask[idx] =
1350                                                 rte_cpu_to_be_32(0xffffffff >>
1351                                                                  (32 - width));
1352                                         width = 0;
1353                                 } else {
1354                                         mask[idx] = RTE_BE32(0xffffffff);
1355                                         width -= 32;
1356                                 }
1357                                 if (!width)
1358                                         break;
1359                                 ++idx;
1360                         }
1361                         info[idx] = (struct field_modify_info){2, 4 * idx,
1362                                                 MLX5_MODI_OUT_DMAC_15_0};
1363                         mask[idx] = rte_cpu_to_be_32(0x0000ffff >>
1364                                                      (16 - width));
1365                 } else {
1366                         if (data->offset < 32)
1367                                 info[idx++] = (struct field_modify_info){4, 0,
1368                                                 MLX5_MODI_OUT_DMAC_47_16};
1369                         info[idx] = (struct field_modify_info){2, 0,
1370                                                 MLX5_MODI_OUT_DMAC_15_0};
1371                 }
1372                 break;
1373         case RTE_FLOW_FIELD_MAC_SRC:
1374                 if (mask) {
1375                         if (data->offset < 32) {
1376                                 info[idx] = (struct field_modify_info){4, 0,
1377                                                 MLX5_MODI_OUT_SMAC_47_16};
1378                                 if (width < 32) {
1379                                         mask[idx] =
1380                                                 rte_cpu_to_be_32(0xffffffff >>
1381                                                                 (32 - width));
1382                                         width = 0;
1383                                 } else {
1384                                         mask[idx] = RTE_BE32(0xffffffff);
1385                                         width -= 32;
1386                                 }
1387                                 if (!width)
1388                                         break;
1389                                 ++idx;
1390                         }
1391                         info[idx] = (struct field_modify_info){2, 4 * idx,
1392                                                 MLX5_MODI_OUT_SMAC_15_0};
1393                         mask[idx] = rte_cpu_to_be_32(0x0000ffff >>
1394                                                      (16 - width));
1395                 } else {
1396                         if (data->offset < 32)
1397                                 info[idx++] = (struct field_modify_info){4, 0,
1398                                                 MLX5_MODI_OUT_SMAC_47_16};
1399                         info[idx] = (struct field_modify_info){2, 0,
1400                                                 MLX5_MODI_OUT_SMAC_15_0};
1401                 }
1402                 break;
1403         case RTE_FLOW_FIELD_VLAN_TYPE:
1404                 /* not supported yet */
1405                 break;
1406         case RTE_FLOW_FIELD_VLAN_ID:
1407                 info[idx] = (struct field_modify_info){2, 0,
1408                                         MLX5_MODI_OUT_FIRST_VID};
1409                 if (mask)
1410                         mask[idx] = rte_cpu_to_be_32(0x00000fff >>
1411                                                      (12 - width));
1412                 break;
1413         case RTE_FLOW_FIELD_MAC_TYPE:
1414                 info[idx] = (struct field_modify_info){2, 0,
1415                                         MLX5_MODI_OUT_ETHERTYPE};
1416                 if (mask)
1417                         mask[idx] = rte_cpu_to_be_32(0x0000ffff >>
1418                                                      (16 - width));
1419                 break;
1420         case RTE_FLOW_FIELD_IPV4_DSCP:
1421                 info[idx] = (struct field_modify_info){1, 0,
1422                                         MLX5_MODI_OUT_IP_DSCP};
1423                 if (mask)
1424                         mask[idx] = rte_cpu_to_be_32(0x0000003f >>
1425                                                      (6 - width));
1426                 break;
1427         case RTE_FLOW_FIELD_IPV4_TTL:
1428                 info[idx] = (struct field_modify_info){1, 0,
1429                                         MLX5_MODI_OUT_IPV4_TTL};
1430                 if (mask)
1431                         mask[idx] = rte_cpu_to_be_32(0x000000ff >>
1432                                                      (8 - width));
1433                 break;
1434         case RTE_FLOW_FIELD_IPV4_SRC:
1435                 info[idx] = (struct field_modify_info){4, 0,
1436                                         MLX5_MODI_OUT_SIPV4};
1437                 if (mask)
1438                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1439                                                      (32 - width));
1440                 break;
1441         case RTE_FLOW_FIELD_IPV4_DST:
1442                 info[idx] = (struct field_modify_info){4, 0,
1443                                         MLX5_MODI_OUT_DIPV4};
1444                 if (mask)
1445                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1446                                                      (32 - width));
1447                 break;
1448         case RTE_FLOW_FIELD_IPV6_DSCP:
1449                 info[idx] = (struct field_modify_info){1, 0,
1450                                         MLX5_MODI_OUT_IP_DSCP};
1451                 if (mask)
1452                         mask[idx] = rte_cpu_to_be_32(0x0000003f >>
1453                                                      (6 - width));
1454                 break;
1455         case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
1456                 info[idx] = (struct field_modify_info){1, 0,
1457                                         MLX5_MODI_OUT_IPV6_HOPLIMIT};
1458                 if (mask)
1459                         mask[idx] = rte_cpu_to_be_32(0x000000ff >>
1460                                                      (8 - width));
1461                 break;
1462         case RTE_FLOW_FIELD_IPV6_SRC:
1463                 if (mask) {
1464                         if (data->offset < 32) {
1465                                 info[idx] = (struct field_modify_info){4,
1466                                                 4 * idx,
1467                                                 MLX5_MODI_OUT_SIPV6_31_0};
1468                                 if (width < 32) {
1469                                         mask[idx] =
1470                                                 rte_cpu_to_be_32(0xffffffff >>
1471                                                                  (32 - width));
1472                                         width = 0;
1473                                 } else {
1474                                         mask[idx] = RTE_BE32(0xffffffff);
1475                                         width -= 32;
1476                                 }
1477                                 if (!width)
1478                                         break;
1479                                 ++idx;
1480                         }
1481                         if (data->offset < 64) {
1482                                 info[idx] = (struct field_modify_info){4,
1483                                                 4 * idx,
1484                                                 MLX5_MODI_OUT_SIPV6_63_32};
1485                                 if (width < 32) {
1486                                         mask[idx] =
1487                                                 rte_cpu_to_be_32(0xffffffff >>
1488                                                                  (32 - width));
1489                                         width = 0;
1490                                 } else {
1491                                         mask[idx] = RTE_BE32(0xffffffff);
1492                                         width -= 32;
1493                                 }
1494                                 if (!width)
1495                                         break;
1496                                 ++idx;
1497                         }
1498                         if (data->offset < 96) {
1499                                 info[idx] = (struct field_modify_info){4,
1500                                                 4 * idx,
1501                                                 MLX5_MODI_OUT_SIPV6_95_64};
1502                                 if (width < 32) {
1503                                         mask[idx] =
1504                                                 rte_cpu_to_be_32(0xffffffff >>
1505                                                                  (32 - width));
1506                                         width = 0;
1507                                 } else {
1508                                         mask[idx] = RTE_BE32(0xffffffff);
1509                                         width -= 32;
1510                                 }
1511                                 if (!width)
1512                                         break;
1513                                 ++idx;
1514                         }
1515                         info[idx] = (struct field_modify_info){4, 4 * idx,
1516                                                 MLX5_MODI_OUT_SIPV6_127_96};
1517                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1518                                                      (32 - width));
1519                 } else {
1520                         if (data->offset < 32)
1521                                 info[idx++] = (struct field_modify_info){4, 0,
1522                                                 MLX5_MODI_OUT_SIPV6_31_0};
1523                         if (data->offset < 64)
1524                                 info[idx++] = (struct field_modify_info){4, 0,
1525                                                 MLX5_MODI_OUT_SIPV6_63_32};
1526                         if (data->offset < 96)
1527                                 info[idx++] = (struct field_modify_info){4, 0,
1528                                                 MLX5_MODI_OUT_SIPV6_95_64};
1529                         if (data->offset < 128)
1530                                 info[idx++] = (struct field_modify_info){4, 0,
1531                                                 MLX5_MODI_OUT_SIPV6_127_96};
1532                 }
1533                 break;
1534         case RTE_FLOW_FIELD_IPV6_DST:
1535                 if (mask) {
1536                         if (data->offset < 32) {
1537                                 info[idx] = (struct field_modify_info){4,
1538                                                 4 * idx,
1539                                                 MLX5_MODI_OUT_DIPV6_31_0};
1540                                 if (width < 32) {
1541                                         mask[idx] =
1542                                                 rte_cpu_to_be_32(0xffffffff >>
1543                                                                  (32 - width));
1544                                         width = 0;
1545                                 } else {
1546                                         mask[idx] = RTE_BE32(0xffffffff);
1547                                         width -= 32;
1548                                 }
1549                                 if (!width)
1550                                         break;
1551                                 ++idx;
1552                         }
1553                         if (data->offset < 64) {
1554                                 info[idx] = (struct field_modify_info){4,
1555                                                 4 * idx,
1556                                                 MLX5_MODI_OUT_DIPV6_63_32};
1557                                 if (width < 32) {
1558                                         mask[idx] =
1559                                                 rte_cpu_to_be_32(0xffffffff >>
1560                                                                  (32 - width));
1561                                         width = 0;
1562                                 } else {
1563                                         mask[idx] = RTE_BE32(0xffffffff);
1564                                         width -= 32;
1565                                 }
1566                                 if (!width)
1567                                         break;
1568                                 ++idx;
1569                         }
1570                         if (data->offset < 96) {
1571                                 info[idx] = (struct field_modify_info){4,
1572                                                 4 * idx,
1573                                                 MLX5_MODI_OUT_DIPV6_95_64};
1574                                 if (width < 32) {
1575                                         mask[idx] =
1576                                                 rte_cpu_to_be_32(0xffffffff >>
1577                                                                  (32 - width));
1578                                         width = 0;
1579                                 } else {
1580                                         mask[idx] = RTE_BE32(0xffffffff);
1581                                         width -= 32;
1582                                 }
1583                                 if (!width)
1584                                         break;
1585                                 ++idx;
1586                         }
1587                         info[idx] = (struct field_modify_info){4, 4 * idx,
1588                                                 MLX5_MODI_OUT_DIPV6_127_96};
1589                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1590                                                      (32 - width));
1591                 } else {
1592                         if (data->offset < 32)
1593                                 info[idx++] = (struct field_modify_info){4, 0,
1594                                                 MLX5_MODI_OUT_DIPV6_31_0};
1595                         if (data->offset < 64)
1596                                 info[idx++] = (struct field_modify_info){4, 0,
1597                                                 MLX5_MODI_OUT_DIPV6_63_32};
1598                         if (data->offset < 96)
1599                                 info[idx++] = (struct field_modify_info){4, 0,
1600                                                 MLX5_MODI_OUT_DIPV6_95_64};
1601                         if (data->offset < 128)
1602                                 info[idx++] = (struct field_modify_info){4, 0,
1603                                                 MLX5_MODI_OUT_DIPV6_127_96};
1604                 }
1605                 break;
1606         case RTE_FLOW_FIELD_TCP_PORT_SRC:
1607                 info[idx] = (struct field_modify_info){2, 0,
1608                                         MLX5_MODI_OUT_TCP_SPORT};
1609                 if (mask)
1610                         mask[idx] = rte_cpu_to_be_32(0x0000ffff >>
1611                                                      (16 - width));
1612                 break;
1613         case RTE_FLOW_FIELD_TCP_PORT_DST:
1614                 info[idx] = (struct field_modify_info){2, 0,
1615                                         MLX5_MODI_OUT_TCP_DPORT};
1616                 if (mask)
1617                         mask[idx] = rte_cpu_to_be_32(0x0000ffff >>
1618                                                      (16 - width));
1619                 break;
1620         case RTE_FLOW_FIELD_TCP_SEQ_NUM:
1621                 info[idx] = (struct field_modify_info){4, 0,
1622                                         MLX5_MODI_OUT_TCP_SEQ_NUM};
1623                 if (mask)
1624                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1625                                                      (32 - width));
1626                 break;
1627         case RTE_FLOW_FIELD_TCP_ACK_NUM:
1628                 info[idx] = (struct field_modify_info){4, 0,
1629                                         MLX5_MODI_OUT_TCP_ACK_NUM};
1630                 if (mask)
1631                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1632                                                      (32 - width));
1633                 break;
1634         case RTE_FLOW_FIELD_TCP_FLAGS:
1635                 info[idx] = (struct field_modify_info){1, 0,
1636                                         MLX5_MODI_OUT_TCP_FLAGS};
1637                 if (mask)
1638                         mask[idx] = rte_cpu_to_be_32(0x0000003f >>
1639                                                      (6 - width));
1640                 break;
1641         case RTE_FLOW_FIELD_UDP_PORT_SRC:
1642                 info[idx] = (struct field_modify_info){2, 0,
1643                                         MLX5_MODI_OUT_UDP_SPORT};
1644                 if (mask)
1645                         mask[idx] = rte_cpu_to_be_32(0x0000ffff >>
1646                                                      (16 - width));
1647                 break;
1648         case RTE_FLOW_FIELD_UDP_PORT_DST:
1649                 info[idx] = (struct field_modify_info){2, 0,
1650                                         MLX5_MODI_OUT_UDP_DPORT};
1651                 if (mask)
1652                         mask[idx] = rte_cpu_to_be_32(0x0000ffff >>
1653                                                      (16 - width));
1654                 break;
1655         case RTE_FLOW_FIELD_VXLAN_VNI:
1656                 /* not supported yet */
1657                 break;
1658         case RTE_FLOW_FIELD_GENEVE_VNI:
1659                 /* not supported yet*/
1660                 break;
1661         case RTE_FLOW_FIELD_GTP_TEID:
1662                 info[idx] = (struct field_modify_info){4, 0,
1663                                         MLX5_MODI_GTP_TEID};
1664                 if (mask)
1665                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1666                                                      (32 - width));
1667                 break;
1668         case RTE_FLOW_FIELD_TAG:
1669                 {
1670                         int reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG,
1671                                                    data->level, error);
1672                         if (reg < 0)
1673                                 return;
1674                         MLX5_ASSERT(reg != REG_NON);
1675                         MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1676                         info[idx] = (struct field_modify_info){4, 0,
1677                                                 reg_to_field[reg]};
1678                         if (mask)
1679                                 mask[idx] =
1680                                         rte_cpu_to_be_32(0xffffffff >>
1681                                                          (32 - width));
1682                 }
1683                 break;
1684         case RTE_FLOW_FIELD_MARK:
1685                 {
1686                         int reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK,
1687                                                        0, error);
1688                         if (reg < 0)
1689                                 return;
1690                         MLX5_ASSERT(reg != REG_NON);
1691                         MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1692                         info[idx] = (struct field_modify_info){4, 0,
1693                                                 reg_to_field[reg]};
1694                         if (mask)
1695                                 mask[idx] =
1696                                         rte_cpu_to_be_32(0xffffffff >>
1697                                                          (32 - width));
1698                 }
1699                 break;
1700         case RTE_FLOW_FIELD_META:
1701                 {
1702                         int reg = flow_dv_get_metadata_reg(dev, attr, error);
1703                         if (reg < 0)
1704                                 return;
1705                         MLX5_ASSERT(reg != REG_NON);
1706                         MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1707                         info[idx] = (struct field_modify_info){4, 0,
1708                                                 reg_to_field[reg]};
1709                         if (mask)
1710                                 mask[idx] =
1711                                         rte_cpu_to_be_32(0xffffffff >>
1712                                                          (32 - width));
1713                 }
1714                 break;
1715         case RTE_FLOW_FIELD_POINTER:
1716                 for (idx = 0; idx < MLX5_ACT_MAX_MOD_FIELDS; idx++) {
1717                         if (mask[idx]) {
1718                                 memcpy(&value[idx],
1719                                         (void *)(uintptr_t)data->value, 32);
1720                                 value[idx] = rte_cpu_to_be_32(value[idx]);
1721                                 break;
1722                         }
1723                 }
1724                 break;
1725         case RTE_FLOW_FIELD_VALUE:
1726                 for (idx = 0; idx < MLX5_ACT_MAX_MOD_FIELDS; idx++) {
1727                         if (mask[idx]) {
1728                                 value[idx] =
1729                                         rte_cpu_to_be_32((uint32_t)data->value);
1730                                 break;
1731                         }
1732                 }
1733                 break;
1734         default:
1735                 MLX5_ASSERT(false);
1736                 break;
1737         }
1738 }
1739
1740 /**
1741  * Convert modify_field action to DV specification.
1742  *
1743  * @param[in] dev
1744  *   Pointer to the rte_eth_dev structure.
1745  * @param[in,out] resource
1746  *   Pointer to the modify-header resource.
1747  * @param[in] action
1748  *   Pointer to action specification.
1749  * @param[in] attr
1750  *   Attributes of flow that includes this item.
1751  * @param[out] error
1752  *   Pointer to the error structure.
1753  *
1754  * @return
1755  *   0 on success, a negative errno value otherwise and rte_errno is set.
1756  */
1757 static int
1758 flow_dv_convert_action_modify_field
1759                         (struct rte_eth_dev *dev,
1760                          struct mlx5_flow_dv_modify_hdr_resource *resource,
1761                          const struct rte_flow_action *action,
1762                          const struct rte_flow_attr *attr,
1763                          struct rte_flow_error *error)
1764 {
1765         const struct rte_flow_action_modify_field *conf =
1766                 (const struct rte_flow_action_modify_field *)(action->conf);
1767         struct rte_flow_item item;
1768         struct field_modify_info field[MLX5_ACT_MAX_MOD_FIELDS] = {
1769                                                                 {0, 0, 0} };
1770         struct field_modify_info dcopy[MLX5_ACT_MAX_MOD_FIELDS] = {
1771                                                                 {0, 0, 0} };
1772         uint32_t mask[MLX5_ACT_MAX_MOD_FIELDS] = {0, 0, 0, 0, 0};
1773         uint32_t value[MLX5_ACT_MAX_MOD_FIELDS] = {0, 0, 0, 0, 0};
1774         uint32_t type;
1775
1776         if (conf->src.field == RTE_FLOW_FIELD_POINTER ||
1777                 conf->src.field == RTE_FLOW_FIELD_VALUE) {
1778                 type = MLX5_MODIFICATION_TYPE_SET;
1779                 /** For SET fill the destination field (field) first. */
1780                 mlx5_flow_field_id_to_modify_info(&conf->dst, field, mask,
1781                                           value, conf->width, dev, attr, error);
1782                 /** Then copy immediate value from source as per mask. */
1783                 mlx5_flow_field_id_to_modify_info(&conf->src, dcopy, mask,
1784                                           value, conf->width, dev, attr, error);
1785                 item.spec = &value;
1786         } else {
1787                 type = MLX5_MODIFICATION_TYPE_COPY;
1788                 /** For COPY fill the destination field (dcopy) without mask. */
1789                 mlx5_flow_field_id_to_modify_info(&conf->dst, dcopy, NULL,
1790                                           value, conf->width, dev, attr, error);
1791                 /** Then construct the source field (field) with mask. */
1792                 mlx5_flow_field_id_to_modify_info(&conf->src, field, mask,
1793                                           value, conf->width, dev, attr, error);
1794         }
1795         item.mask = &mask;
1796         return flow_dv_convert_modify_action(&item,
1797                         field, dcopy, resource, type, error);
1798 }
1799
1800 /**
1801  * Validate MARK item.
1802  *
1803  * @param[in] dev
1804  *   Pointer to the rte_eth_dev structure.
1805  * @param[in] item
1806  *   Item specification.
1807  * @param[in] attr
1808  *   Attributes of flow that includes this item.
1809  * @param[out] error
1810  *   Pointer to error structure.
1811  *
1812  * @return
1813  *   0 on success, a negative errno value otherwise and rte_errno is set.
1814  */
1815 static int
1816 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1817                            const struct rte_flow_item *item,
1818                            const struct rte_flow_attr *attr __rte_unused,
1819                            struct rte_flow_error *error)
1820 {
1821         struct mlx5_priv *priv = dev->data->dev_private;
1822         struct mlx5_dev_config *config = &priv->config;
1823         const struct rte_flow_item_mark *spec = item->spec;
1824         const struct rte_flow_item_mark *mask = item->mask;
1825         const struct rte_flow_item_mark nic_mask = {
1826                 .id = priv->sh->dv_mark_mask,
1827         };
1828         int ret;
1829
1830         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1831                 return rte_flow_error_set(error, ENOTSUP,
1832                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1833                                           "extended metadata feature"
1834                                           " isn't enabled");
1835         if (!mlx5_flow_ext_mreg_supported(dev))
1836                 return rte_flow_error_set(error, ENOTSUP,
1837                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1838                                           "extended metadata register"
1839                                           " isn't supported");
1840         if (!nic_mask.id)
1841                 return rte_flow_error_set(error, ENOTSUP,
1842                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1843                                           "extended metadata register"
1844                                           " isn't available");
1845         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1846         if (ret < 0)
1847                 return ret;
1848         if (!spec)
1849                 return rte_flow_error_set(error, EINVAL,
1850                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1851                                           item->spec,
1852                                           "data cannot be empty");
1853         if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1854                 return rte_flow_error_set(error, EINVAL,
1855                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1856                                           &spec->id,
1857                                           "mark id exceeds the limit");
1858         if (!mask)
1859                 mask = &nic_mask;
1860         if (!mask->id)
1861                 return rte_flow_error_set(error, EINVAL,
1862                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1863                                         "mask cannot be zero");
1864
1865         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1866                                         (const uint8_t *)&nic_mask,
1867                                         sizeof(struct rte_flow_item_mark),
1868                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1869         if (ret < 0)
1870                 return ret;
1871         return 0;
1872 }
1873
1874 /**
1875  * Validate META item.
1876  *
1877  * @param[in] dev
1878  *   Pointer to the rte_eth_dev structure.
1879  * @param[in] item
1880  *   Item specification.
1881  * @param[in] attr
1882  *   Attributes of flow that includes this item.
1883  * @param[out] error
1884  *   Pointer to error structure.
1885  *
1886  * @return
1887  *   0 on success, a negative errno value otherwise and rte_errno is set.
1888  */
1889 static int
1890 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1891                            const struct rte_flow_item *item,
1892                            const struct rte_flow_attr *attr,
1893                            struct rte_flow_error *error)
1894 {
1895         struct mlx5_priv *priv = dev->data->dev_private;
1896         struct mlx5_dev_config *config = &priv->config;
1897         const struct rte_flow_item_meta *spec = item->spec;
1898         const struct rte_flow_item_meta *mask = item->mask;
1899         struct rte_flow_item_meta nic_mask = {
1900                 .data = UINT32_MAX
1901         };
1902         int reg;
1903         int ret;
1904
1905         if (!spec)
1906                 return rte_flow_error_set(error, EINVAL,
1907                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1908                                           item->spec,
1909                                           "data cannot be empty");
1910         if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1911                 if (!mlx5_flow_ext_mreg_supported(dev))
1912                         return rte_flow_error_set(error, ENOTSUP,
1913                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1914                                           "extended metadata register"
1915                                           " isn't supported");
1916                 reg = flow_dv_get_metadata_reg(dev, attr, error);
1917                 if (reg < 0)
1918                         return reg;
1919                 if (reg == REG_NON)
1920                         return rte_flow_error_set(error, ENOTSUP,
1921                                         RTE_FLOW_ERROR_TYPE_ITEM, item,
1922                                         "unavalable extended metadata register");
1923                 if (reg == REG_B)
1924                         return rte_flow_error_set(error, ENOTSUP,
1925                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1926                                           "match on reg_b "
1927                                           "isn't supported");
1928                 if (reg != REG_A)
1929                         nic_mask.data = priv->sh->dv_meta_mask;
1930         } else {
1931                 if (attr->transfer)
1932                         return rte_flow_error_set(error, ENOTSUP,
1933                                         RTE_FLOW_ERROR_TYPE_ITEM, item,
1934                                         "extended metadata feature "
1935                                         "should be enabled when "
1936                                         "meta item is requested "
1937                                         "with e-switch mode ");
1938                 if (attr->ingress)
1939                         return rte_flow_error_set(error, ENOTSUP,
1940                                         RTE_FLOW_ERROR_TYPE_ITEM, item,
1941                                         "match on metadata for ingress "
1942                                         "is not supported in legacy "
1943                                         "metadata mode");
1944         }
1945         if (!mask)
1946                 mask = &rte_flow_item_meta_mask;
1947         if (!mask->data)
1948                 return rte_flow_error_set(error, EINVAL,
1949                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1950                                         "mask cannot be zero");
1951
1952         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1953                                         (const uint8_t *)&nic_mask,
1954                                         sizeof(struct rte_flow_item_meta),
1955                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1956         return ret;
1957 }
1958
1959 /**
1960  * Validate TAG item.
1961  *
1962  * @param[in] dev
1963  *   Pointer to the rte_eth_dev structure.
1964  * @param[in] item
1965  *   Item specification.
1966  * @param[in] attr
1967  *   Attributes of flow that includes this item.
1968  * @param[out] error
1969  *   Pointer to error structure.
1970  *
1971  * @return
1972  *   0 on success, a negative errno value otherwise and rte_errno is set.
1973  */
1974 static int
1975 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
1976                           const struct rte_flow_item *item,
1977                           const struct rte_flow_attr *attr __rte_unused,
1978                           struct rte_flow_error *error)
1979 {
1980         const struct rte_flow_item_tag *spec = item->spec;
1981         const struct rte_flow_item_tag *mask = item->mask;
1982         const struct rte_flow_item_tag nic_mask = {
1983                 .data = RTE_BE32(UINT32_MAX),
1984                 .index = 0xff,
1985         };
1986         int ret;
1987
1988         if (!mlx5_flow_ext_mreg_supported(dev))
1989                 return rte_flow_error_set(error, ENOTSUP,
1990                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1991                                           "extensive metadata register"
1992                                           " isn't supported");
1993         if (!spec)
1994                 return rte_flow_error_set(error, EINVAL,
1995                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1996                                           item->spec,
1997                                           "data cannot be empty");
1998         if (!mask)
1999                 mask = &rte_flow_item_tag_mask;
2000         if (!mask->data)
2001                 return rte_flow_error_set(error, EINVAL,
2002                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2003                                         "mask cannot be zero");
2004
2005         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2006                                         (const uint8_t *)&nic_mask,
2007                                         sizeof(struct rte_flow_item_tag),
2008                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2009         if (ret < 0)
2010                 return ret;
2011         if (mask->index != 0xff)
2012                 return rte_flow_error_set(error, EINVAL,
2013                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2014                                           "partial mask for tag index"
2015                                           " is not supported");
2016         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
2017         if (ret < 0)
2018                 return ret;
2019         MLX5_ASSERT(ret != REG_NON);
2020         return 0;
2021 }
2022
2023 /**
2024  * Validate vport item.
2025  *
2026  * @param[in] dev
2027  *   Pointer to the rte_eth_dev structure.
2028  * @param[in] item
2029  *   Item specification.
2030  * @param[in] attr
2031  *   Attributes of flow that includes this item.
2032  * @param[in] item_flags
2033  *   Bit-fields that holds the items detected until now.
2034  * @param[out] error
2035  *   Pointer to error structure.
2036  *
2037  * @return
2038  *   0 on success, a negative errno value otherwise and rte_errno is set.
2039  */
2040 static int
2041 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
2042                               const struct rte_flow_item *item,
2043                               const struct rte_flow_attr *attr,
2044                               uint64_t item_flags,
2045                               struct rte_flow_error *error)
2046 {
2047         const struct rte_flow_item_port_id *spec = item->spec;
2048         const struct rte_flow_item_port_id *mask = item->mask;
2049         const struct rte_flow_item_port_id switch_mask = {
2050                         .id = 0xffffffff,
2051         };
2052         struct mlx5_priv *esw_priv;
2053         struct mlx5_priv *dev_priv;
2054         int ret;
2055
2056         if (!attr->transfer)
2057                 return rte_flow_error_set(error, EINVAL,
2058                                           RTE_FLOW_ERROR_TYPE_ITEM,
2059                                           NULL,
2060                                           "match on port id is valid only"
2061                                           " when transfer flag is enabled");
2062         if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
2063                 return rte_flow_error_set(error, ENOTSUP,
2064                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2065                                           "multiple source ports are not"
2066                                           " supported");
2067         if (!mask)
2068                 mask = &switch_mask;
2069         if (mask->id != 0xffffffff)
2070                 return rte_flow_error_set(error, ENOTSUP,
2071                                            RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2072                                            mask,
2073                                            "no support for partial mask on"
2074                                            " \"id\" field");
2075         ret = mlx5_flow_item_acceptable
2076                                 (item, (const uint8_t *)mask,
2077                                  (const uint8_t *)&rte_flow_item_port_id_mask,
2078                                  sizeof(struct rte_flow_item_port_id),
2079                                  MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2080         if (ret)
2081                 return ret;
2082         if (!spec)
2083                 return 0;
2084         esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
2085         if (!esw_priv)
2086                 return rte_flow_error_set(error, rte_errno,
2087                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
2088                                           "failed to obtain E-Switch info for"
2089                                           " port");
2090         dev_priv = mlx5_dev_to_eswitch_info(dev);
2091         if (!dev_priv)
2092                 return rte_flow_error_set(error, rte_errno,
2093                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2094                                           NULL,
2095                                           "failed to obtain E-Switch info");
2096         if (esw_priv->domain_id != dev_priv->domain_id)
2097                 return rte_flow_error_set(error, EINVAL,
2098                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
2099                                           "cannot match on a port from a"
2100                                           " different E-Switch");
2101         return 0;
2102 }
2103
2104 /**
2105  * Validate VLAN item.
2106  *
2107  * @param[in] item
2108  *   Item specification.
2109  * @param[in] item_flags
2110  *   Bit-fields that holds the items detected until now.
2111  * @param[in] dev
2112  *   Ethernet device flow is being created on.
2113  * @param[out] error
2114  *   Pointer to error structure.
2115  *
2116  * @return
2117  *   0 on success, a negative errno value otherwise and rte_errno is set.
2118  */
2119 static int
2120 flow_dv_validate_item_vlan(const struct rte_flow_item *item,
2121                            uint64_t item_flags,
2122                            struct rte_eth_dev *dev,
2123                            struct rte_flow_error *error)
2124 {
2125         const struct rte_flow_item_vlan *mask = item->mask;
2126         const struct rte_flow_item_vlan nic_mask = {
2127                 .tci = RTE_BE16(UINT16_MAX),
2128                 .inner_type = RTE_BE16(UINT16_MAX),
2129                 .has_more_vlan = 1,
2130         };
2131         const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2132         int ret;
2133         const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 |
2134                                         MLX5_FLOW_LAYER_INNER_L4) :
2135                                        (MLX5_FLOW_LAYER_OUTER_L3 |
2136                                         MLX5_FLOW_LAYER_OUTER_L4);
2137         const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
2138                                         MLX5_FLOW_LAYER_OUTER_VLAN;
2139
2140         if (item_flags & vlanm)
2141                 return rte_flow_error_set(error, EINVAL,
2142                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2143                                           "multiple VLAN layers not supported");
2144         else if ((item_flags & l34m) != 0)
2145                 return rte_flow_error_set(error, EINVAL,
2146                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2147                                           "VLAN cannot follow L3/L4 layer");
2148         if (!mask)
2149                 mask = &rte_flow_item_vlan_mask;
2150         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2151                                         (const uint8_t *)&nic_mask,
2152                                         sizeof(struct rte_flow_item_vlan),
2153                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2154         if (ret)
2155                 return ret;
2156         if (!tunnel && mask->tci != RTE_BE16(0x0fff)) {
2157                 struct mlx5_priv *priv = dev->data->dev_private;
2158
2159                 if (priv->vmwa_context) {
2160                         /*
2161                          * Non-NULL context means we have a virtual machine
2162                          * and SR-IOV enabled, we have to create VLAN interface
2163                          * to make hypervisor to setup E-Switch vport
2164                          * context correctly. We avoid creating the multiple
2165                          * VLAN interfaces, so we cannot support VLAN tag mask.
2166                          */
2167                         return rte_flow_error_set(error, EINVAL,
2168                                                   RTE_FLOW_ERROR_TYPE_ITEM,
2169                                                   item,
2170                                                   "VLAN tag mask is not"
2171                                                   " supported in virtual"
2172                                                   " environment");
2173                 }
2174         }
2175         return 0;
2176 }
2177
2178 /*
2179  * GTP flags are contained in 1 byte of the format:
2180  * -------------------------------------------
2181  * | bit   | 0 - 2   | 3  | 4   | 5 | 6 | 7  |
2182  * |-----------------------------------------|
2183  * | value | Version | PT | Res | E | S | PN |
2184  * -------------------------------------------
2185  *
2186  * Matching is supported only for GTP flags E, S, PN.
2187  */
2188 #define MLX5_GTP_FLAGS_MASK     0x07
2189
2190 /**
2191  * Validate GTP item.
2192  *
2193  * @param[in] dev
2194  *   Pointer to the rte_eth_dev structure.
2195  * @param[in] item
2196  *   Item specification.
2197  * @param[in] item_flags
2198  *   Bit-fields that holds the items detected until now.
2199  * @param[out] error
2200  *   Pointer to error structure.
2201  *
2202  * @return
2203  *   0 on success, a negative errno value otherwise and rte_errno is set.
2204  */
2205 static int
2206 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
2207                           const struct rte_flow_item *item,
2208                           uint64_t item_flags,
2209                           struct rte_flow_error *error)
2210 {
2211         struct mlx5_priv *priv = dev->data->dev_private;
2212         const struct rte_flow_item_gtp *spec = item->spec;
2213         const struct rte_flow_item_gtp *mask = item->mask;
2214         const struct rte_flow_item_gtp nic_mask = {
2215                 .v_pt_rsv_flags = MLX5_GTP_FLAGS_MASK,
2216                 .msg_type = 0xff,
2217                 .teid = RTE_BE32(0xffffffff),
2218         };
2219
2220         if (!priv->config.hca_attr.tunnel_stateless_gtp)
2221                 return rte_flow_error_set(error, ENOTSUP,
2222                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2223                                           "GTP support is not enabled");
2224         if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
2225                 return rte_flow_error_set(error, ENOTSUP,
2226                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2227                                           "multiple tunnel layers not"
2228                                           " supported");
2229         if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
2230                 return rte_flow_error_set(error, EINVAL,
2231                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2232                                           "no outer UDP layer found");
2233         if (!mask)
2234                 mask = &rte_flow_item_gtp_mask;
2235         if (spec && spec->v_pt_rsv_flags & ~MLX5_GTP_FLAGS_MASK)
2236                 return rte_flow_error_set(error, ENOTSUP,
2237                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2238                                           "Match is supported for GTP"
2239                                           " flags only");
2240         return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2241                                          (const uint8_t *)&nic_mask,
2242                                          sizeof(struct rte_flow_item_gtp),
2243                                          MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2244 }
2245
2246 /**
2247  * Validate GTP PSC item.
2248  *
2249  * @param[in] item
2250  *   Item specification.
2251  * @param[in] last_item
2252  *   Previous validated item in the pattern items.
2253  * @param[in] gtp_item
2254  *   Previous GTP item specification.
2255  * @param[in] attr
2256  *   Pointer to flow attributes.
2257  * @param[out] error
2258  *   Pointer to error structure.
2259  *
2260  * @return
2261  *   0 on success, a negative errno value otherwise and rte_errno is set.
2262  */
2263 static int
2264 flow_dv_validate_item_gtp_psc(const struct rte_flow_item *item,
2265                               uint64_t last_item,
2266                               const struct rte_flow_item *gtp_item,
2267                               const struct rte_flow_attr *attr,
2268                               struct rte_flow_error *error)
2269 {
2270         const struct rte_flow_item_gtp *gtp_spec;
2271         const struct rte_flow_item_gtp *gtp_mask;
2272         const struct rte_flow_item_gtp_psc *spec;
2273         const struct rte_flow_item_gtp_psc *mask;
2274         const struct rte_flow_item_gtp_psc nic_mask = {
2275                 .pdu_type = 0xFF,
2276                 .qfi = 0xFF,
2277         };
2278
2279         if (!gtp_item || !(last_item & MLX5_FLOW_LAYER_GTP))
2280                 return rte_flow_error_set
2281                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2282                          "GTP PSC item must be preceded with GTP item");
2283         gtp_spec = gtp_item->spec;
2284         gtp_mask = gtp_item->mask ? gtp_item->mask : &rte_flow_item_gtp_mask;
2285         /* GTP spec and E flag is requested to match zero. */
2286         if (gtp_spec &&
2287                 (gtp_mask->v_pt_rsv_flags &
2288                 ~gtp_spec->v_pt_rsv_flags & MLX5_GTP_EXT_HEADER_FLAG))
2289                 return rte_flow_error_set
2290                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2291                          "GTP E flag must be 1 to match GTP PSC");
2292         /* Check the flow is not created in group zero. */
2293         if (!attr->transfer && !attr->group)
2294                 return rte_flow_error_set
2295                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2296                          "GTP PSC is not supported for group 0");
2297         /* GTP spec is here and E flag is requested to match zero. */
2298         if (!item->spec)
2299                 return 0;
2300         spec = item->spec;
2301         mask = item->mask ? item->mask : &rte_flow_item_gtp_psc_mask;
2302         if (spec->pdu_type > MLX5_GTP_EXT_MAX_PDU_TYPE)
2303                 return rte_flow_error_set
2304                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2305                          "PDU type should be smaller than 16");
2306         return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2307                                          (const uint8_t *)&nic_mask,
2308                                          sizeof(struct rte_flow_item_gtp_psc),
2309                                          MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2310 }
2311
2312 /**
2313  * Validate IPV4 item.
2314  * Use existing validation function mlx5_flow_validate_item_ipv4(), and
2315  * add specific validation of fragment_offset field,
2316  *
2317  * @param[in] item
2318  *   Item specification.
2319  * @param[in] item_flags
2320  *   Bit-fields that holds the items detected until now.
2321  * @param[out] error
2322  *   Pointer to error structure.
2323  *
2324  * @return
2325  *   0 on success, a negative errno value otherwise and rte_errno is set.
2326  */
2327 static int
2328 flow_dv_validate_item_ipv4(const struct rte_flow_item *item,
2329                            uint64_t item_flags,
2330                            uint64_t last_item,
2331                            uint16_t ether_type,
2332                            struct rte_flow_error *error)
2333 {
2334         int ret;
2335         const struct rte_flow_item_ipv4 *spec = item->spec;
2336         const struct rte_flow_item_ipv4 *last = item->last;
2337         const struct rte_flow_item_ipv4 *mask = item->mask;
2338         rte_be16_t fragment_offset_spec = 0;
2339         rte_be16_t fragment_offset_last = 0;
2340         const struct rte_flow_item_ipv4 nic_ipv4_mask = {
2341                 .hdr = {
2342                         .src_addr = RTE_BE32(0xffffffff),
2343                         .dst_addr = RTE_BE32(0xffffffff),
2344                         .type_of_service = 0xff,
2345                         .fragment_offset = RTE_BE16(0xffff),
2346                         .next_proto_id = 0xff,
2347                         .time_to_live = 0xff,
2348                 },
2349         };
2350
2351         ret = mlx5_flow_validate_item_ipv4(item, item_flags, last_item,
2352                                            ether_type, &nic_ipv4_mask,
2353                                            MLX5_ITEM_RANGE_ACCEPTED, error);
2354         if (ret < 0)
2355                 return ret;
2356         if (spec && mask)
2357                 fragment_offset_spec = spec->hdr.fragment_offset &
2358                                        mask->hdr.fragment_offset;
2359         if (!fragment_offset_spec)
2360                 return 0;
2361         /*
2362          * spec and mask are valid, enforce using full mask to make sure the
2363          * complete value is used correctly.
2364          */
2365         if ((mask->hdr.fragment_offset & RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2366                         != RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2367                 return rte_flow_error_set(error, EINVAL,
2368                                           RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2369                                           item, "must use full mask for"
2370                                           " fragment_offset");
2371         /*
2372          * Match on fragment_offset 0x2000 means MF is 1 and frag-offset is 0,
2373          * indicating this is 1st fragment of fragmented packet.
2374          * This is not yet supported in MLX5, return appropriate error message.
2375          */
2376         if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG))
2377                 return rte_flow_error_set(error, ENOTSUP,
2378                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2379                                           "match on first fragment not "
2380                                           "supported");
2381         if (fragment_offset_spec && !last)
2382                 return rte_flow_error_set(error, ENOTSUP,
2383                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2384                                           "specified value not supported");
2385         /* spec and last are valid, validate the specified range. */
2386         fragment_offset_last = last->hdr.fragment_offset &
2387                                mask->hdr.fragment_offset;
2388         /*
2389          * Match on fragment_offset spec 0x2001 and last 0x3fff
2390          * means MF is 1 and frag-offset is > 0.
2391          * This packet is fragment 2nd and onward, excluding last.
2392          * This is not yet supported in MLX5, return appropriate
2393          * error message.
2394          */
2395         if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG + 1) &&
2396             fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2397                 return rte_flow_error_set(error, ENOTSUP,
2398                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2399                                           last, "match on following "
2400                                           "fragments not supported");
2401         /*
2402          * Match on fragment_offset spec 0x0001 and last 0x1fff
2403          * means MF is 0 and frag-offset is > 0.
2404          * This packet is last fragment of fragmented packet.
2405          * This is not yet supported in MLX5, return appropriate
2406          * error message.
2407          */
2408         if (fragment_offset_spec == RTE_BE16(1) &&
2409             fragment_offset_last == RTE_BE16(RTE_IPV4_HDR_OFFSET_MASK))
2410                 return rte_flow_error_set(error, ENOTSUP,
2411                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2412                                           last, "match on last "
2413                                           "fragment not supported");
2414         /*
2415          * Match on fragment_offset spec 0x0001 and last 0x3fff
2416          * means MF and/or frag-offset is not 0.
2417          * This is a fragmented packet.
2418          * Other range values are invalid and rejected.
2419          */
2420         if (!(fragment_offset_spec == RTE_BE16(1) &&
2421               fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK)))
2422                 return rte_flow_error_set(error, ENOTSUP,
2423                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2424                                           "specified range not supported");
2425         return 0;
2426 }
2427
2428 /**
2429  * Validate IPV6 fragment extension item.
2430  *
2431  * @param[in] item
2432  *   Item specification.
2433  * @param[in] item_flags
2434  *   Bit-fields that holds the items detected until now.
2435  * @param[out] error
2436  *   Pointer to error structure.
2437  *
2438  * @return
2439  *   0 on success, a negative errno value otherwise and rte_errno is set.
2440  */
2441 static int
2442 flow_dv_validate_item_ipv6_frag_ext(const struct rte_flow_item *item,
2443                                     uint64_t item_flags,
2444                                     struct rte_flow_error *error)
2445 {
2446         const struct rte_flow_item_ipv6_frag_ext *spec = item->spec;
2447         const struct rte_flow_item_ipv6_frag_ext *last = item->last;
2448         const struct rte_flow_item_ipv6_frag_ext *mask = item->mask;
2449         rte_be16_t frag_data_spec = 0;
2450         rte_be16_t frag_data_last = 0;
2451         const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2452         const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 :
2453                                       MLX5_FLOW_LAYER_OUTER_L4;
2454         int ret = 0;
2455         struct rte_flow_item_ipv6_frag_ext nic_mask = {
2456                 .hdr = {
2457                         .next_header = 0xff,
2458                         .frag_data = RTE_BE16(0xffff),
2459                 },
2460         };
2461
2462         if (item_flags & l4m)
2463                 return rte_flow_error_set(error, EINVAL,
2464                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2465                                           "ipv6 fragment extension item cannot "
2466                                           "follow L4 item.");
2467         if ((tunnel && !(item_flags & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
2468             (!tunnel && !(item_flags & MLX5_FLOW_LAYER_OUTER_L3_IPV6)))
2469                 return rte_flow_error_set(error, EINVAL,
2470                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2471                                           "ipv6 fragment extension item must "
2472                                           "follow ipv6 item");
2473         if (spec && mask)
2474                 frag_data_spec = spec->hdr.frag_data & mask->hdr.frag_data;
2475         if (!frag_data_spec)
2476                 return 0;
2477         /*
2478          * spec and mask are valid, enforce using full mask to make sure the
2479          * complete value is used correctly.
2480          */
2481         if ((mask->hdr.frag_data & RTE_BE16(RTE_IPV6_FRAG_USED_MASK)) !=
2482                                 RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2483                 return rte_flow_error_set(error, EINVAL,
2484                                           RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2485                                           item, "must use full mask for"
2486                                           " frag_data");
2487         /*
2488          * Match on frag_data 0x00001 means M is 1 and frag-offset is 0.
2489          * This is 1st fragment of fragmented packet.
2490          */
2491         if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_MF_MASK))
2492                 return rte_flow_error_set(error, ENOTSUP,
2493                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2494                                           "match on first fragment not "
2495                                           "supported");
2496         if (frag_data_spec && !last)
2497                 return rte_flow_error_set(error, EINVAL,
2498                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2499                                           "specified value not supported");
2500         ret = mlx5_flow_item_acceptable
2501                                 (item, (const uint8_t *)mask,
2502                                  (const uint8_t *)&nic_mask,
2503                                  sizeof(struct rte_flow_item_ipv6_frag_ext),
2504                                  MLX5_ITEM_RANGE_ACCEPTED, error);
2505         if (ret)
2506                 return ret;
2507         /* spec and last are valid, validate the specified range. */
2508         frag_data_last = last->hdr.frag_data & mask->hdr.frag_data;
2509         /*
2510          * Match on frag_data spec 0x0009 and last 0xfff9
2511          * means M is 1 and frag-offset is > 0.
2512          * This packet is fragment 2nd and onward, excluding last.
2513          * This is not yet supported in MLX5, return appropriate
2514          * error message.
2515          */
2516         if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN |
2517                                        RTE_IPV6_EHDR_MF_MASK) &&
2518             frag_data_last == RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2519                 return rte_flow_error_set(error, ENOTSUP,
2520                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2521                                           last, "match on following "
2522                                           "fragments not supported");
2523         /*
2524          * Match on frag_data spec 0x0008 and last 0xfff8
2525          * means M is 0 and frag-offset is > 0.
2526          * This packet is last fragment of fragmented packet.
2527          * This is not yet supported in MLX5, return appropriate
2528          * error message.
2529          */
2530         if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN) &&
2531             frag_data_last == RTE_BE16(RTE_IPV6_EHDR_FO_MASK))
2532                 return rte_flow_error_set(error, ENOTSUP,
2533                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2534                                           last, "match on last "
2535                                           "fragment not supported");
2536         /* Other range values are invalid and rejected. */
2537         return rte_flow_error_set(error, EINVAL,
2538                                   RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2539                                   "specified range not supported");
2540 }
2541
2542 /**
2543  * Validate the pop VLAN action.
2544  *
2545  * @param[in] dev
2546  *   Pointer to the rte_eth_dev structure.
2547  * @param[in] action_flags
2548  *   Holds the actions detected until now.
2549  * @param[in] action
2550  *   Pointer to the pop vlan action.
2551  * @param[in] item_flags
2552  *   The items found in this flow rule.
2553  * @param[in] attr
2554  *   Pointer to flow attributes.
2555  * @param[out] error
2556  *   Pointer to error structure.
2557  *
2558  * @return
2559  *   0 on success, a negative errno value otherwise and rte_errno is set.
2560  */
2561 static int
2562 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
2563                                  uint64_t action_flags,
2564                                  const struct rte_flow_action *action,
2565                                  uint64_t item_flags,
2566                                  const struct rte_flow_attr *attr,
2567                                  struct rte_flow_error *error)
2568 {
2569         const struct mlx5_priv *priv = dev->data->dev_private;
2570
2571         (void)action;
2572         (void)attr;
2573         if (!priv->sh->pop_vlan_action)
2574                 return rte_flow_error_set(error, ENOTSUP,
2575                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2576                                           NULL,
2577                                           "pop vlan action is not supported");
2578         if (attr->egress)
2579                 return rte_flow_error_set(error, ENOTSUP,
2580                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2581                                           NULL,
2582                                           "pop vlan action not supported for "
2583                                           "egress");
2584         if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
2585                 return rte_flow_error_set(error, ENOTSUP,
2586                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2587                                           "no support for multiple VLAN "
2588                                           "actions");
2589         /* Pop VLAN with preceding Decap requires inner header with VLAN. */
2590         if ((action_flags & MLX5_FLOW_ACTION_DECAP) &&
2591             !(item_flags & MLX5_FLOW_LAYER_INNER_VLAN))
2592                 return rte_flow_error_set(error, ENOTSUP,
2593                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2594                                           NULL,
2595                                           "cannot pop vlan after decap without "
2596                                           "match on inner vlan in the flow");
2597         /* Pop VLAN without preceding Decap requires outer header with VLAN. */
2598         if (!(action_flags & MLX5_FLOW_ACTION_DECAP) &&
2599             !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2600                 return rte_flow_error_set(error, ENOTSUP,
2601                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2602                                           NULL,
2603                                           "cannot pop vlan without a "
2604                                           "match on (outer) vlan in the flow");
2605         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2606                 return rte_flow_error_set(error, EINVAL,
2607                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2608                                           "wrong action order, port_id should "
2609                                           "be after pop VLAN action");
2610         if (!attr->transfer && priv->representor)
2611                 return rte_flow_error_set(error, ENOTSUP,
2612                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2613                                           "pop vlan action for VF representor "
2614                                           "not supported on NIC table");
2615         return 0;
2616 }
2617
2618 /**
2619  * Get VLAN default info from vlan match info.
2620  *
2621  * @param[in] items
2622  *   the list of item specifications.
2623  * @param[out] vlan
2624  *   pointer VLAN info to fill to.
2625  *
2626  * @return
2627  *   0 on success, a negative errno value otherwise and rte_errno is set.
2628  */
2629 static void
2630 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
2631                                   struct rte_vlan_hdr *vlan)
2632 {
2633         const struct rte_flow_item_vlan nic_mask = {
2634                 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
2635                                 MLX5DV_FLOW_VLAN_VID_MASK),
2636                 .inner_type = RTE_BE16(0xffff),
2637         };
2638
2639         if (items == NULL)
2640                 return;
2641         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2642                 int type = items->type;
2643
2644                 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
2645                     type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
2646                         break;
2647         }
2648         if (items->type != RTE_FLOW_ITEM_TYPE_END) {
2649                 const struct rte_flow_item_vlan *vlan_m = items->mask;
2650                 const struct rte_flow_item_vlan *vlan_v = items->spec;
2651
2652                 /* If VLAN item in pattern doesn't contain data, return here. */
2653                 if (!vlan_v)
2654                         return;
2655                 if (!vlan_m)
2656                         vlan_m = &nic_mask;
2657                 /* Only full match values are accepted */
2658                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
2659                      MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
2660                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
2661                         vlan->vlan_tci |=
2662                                 rte_be_to_cpu_16(vlan_v->tci &
2663                                                  MLX5DV_FLOW_VLAN_PCP_MASK_BE);
2664                 }
2665                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
2666                      MLX5DV_FLOW_VLAN_VID_MASK_BE) {
2667                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
2668                         vlan->vlan_tci |=
2669                                 rte_be_to_cpu_16(vlan_v->tci &
2670                                                  MLX5DV_FLOW_VLAN_VID_MASK_BE);
2671                 }
2672                 if (vlan_m->inner_type == nic_mask.inner_type)
2673                         vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
2674                                                            vlan_m->inner_type);
2675         }
2676 }
2677
2678 /**
2679  * Validate the push VLAN action.
2680  *
2681  * @param[in] dev
2682  *   Pointer to the rte_eth_dev structure.
2683  * @param[in] action_flags
2684  *   Holds the actions detected until now.
2685  * @param[in] item_flags
2686  *   The items found in this flow rule.
2687  * @param[in] action
2688  *   Pointer to the action structure.
2689  * @param[in] attr
2690  *   Pointer to flow attributes
2691  * @param[out] error
2692  *   Pointer to error structure.
2693  *
2694  * @return
2695  *   0 on success, a negative errno value otherwise and rte_errno is set.
2696  */
2697 static int
2698 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
2699                                   uint64_t action_flags,
2700                                   const struct rte_flow_item_vlan *vlan_m,
2701                                   const struct rte_flow_action *action,
2702                                   const struct rte_flow_attr *attr,
2703                                   struct rte_flow_error *error)
2704 {
2705         const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
2706         const struct mlx5_priv *priv = dev->data->dev_private;
2707
2708         if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
2709             push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
2710                 return rte_flow_error_set(error, EINVAL,
2711                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2712                                           "invalid vlan ethertype");
2713         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2714                 return rte_flow_error_set(error, EINVAL,
2715                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2716                                           "wrong action order, port_id should "
2717                                           "be after push VLAN");
2718         if (!attr->transfer && priv->representor)
2719                 return rte_flow_error_set(error, ENOTSUP,
2720                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2721                                           "push vlan action for VF representor "
2722                                           "not supported on NIC table");
2723         if (vlan_m &&
2724             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
2725             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
2726                 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
2727             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
2728             !(mlx5_flow_find_action
2729                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
2730                 return rte_flow_error_set(error, EINVAL,
2731                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2732                                           "not full match mask on VLAN PCP and "
2733                                           "there is no of_set_vlan_pcp action, "
2734                                           "push VLAN action cannot figure out "
2735                                           "PCP value");
2736         if (vlan_m &&
2737             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
2738             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
2739                 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
2740             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
2741             !(mlx5_flow_find_action
2742                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
2743                 return rte_flow_error_set(error, EINVAL,
2744                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2745                                           "not full match mask on VLAN VID and "
2746                                           "there is no of_set_vlan_vid action, "
2747                                           "push VLAN action cannot figure out "
2748                                           "VID value");
2749         (void)attr;
2750         return 0;
2751 }
2752
2753 /**
2754  * Validate the set VLAN PCP.
2755  *
2756  * @param[in] action_flags
2757  *   Holds the actions detected until now.
2758  * @param[in] actions
2759  *   Pointer to the list of actions remaining in the flow rule.
2760  * @param[out] error
2761  *   Pointer to error structure.
2762  *
2763  * @return
2764  *   0 on success, a negative errno value otherwise and rte_errno is set.
2765  */
2766 static int
2767 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
2768                                      const struct rte_flow_action actions[],
2769                                      struct rte_flow_error *error)
2770 {
2771         const struct rte_flow_action *action = actions;
2772         const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
2773
2774         if (conf->vlan_pcp > 7)
2775                 return rte_flow_error_set(error, EINVAL,
2776                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2777                                           "VLAN PCP value is too big");
2778         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
2779                 return rte_flow_error_set(error, ENOTSUP,
2780                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2781                                           "set VLAN PCP action must follow "
2782                                           "the push VLAN action");
2783         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
2784                 return rte_flow_error_set(error, ENOTSUP,
2785                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2786                                           "Multiple VLAN PCP modification are "
2787                                           "not supported");
2788         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2789                 return rte_flow_error_set(error, EINVAL,
2790                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2791                                           "wrong action order, port_id should "
2792                                           "be after set VLAN PCP");
2793         return 0;
2794 }
2795
2796 /**
2797  * Validate the set VLAN VID.
2798  *
2799  * @param[in] item_flags
2800  *   Holds the items detected in this rule.
2801  * @param[in] action_flags
2802  *   Holds the actions detected until now.
2803  * @param[in] actions
2804  *   Pointer to the list of actions remaining in the flow rule.
2805  * @param[out] error
2806  *   Pointer to error structure.
2807  *
2808  * @return
2809  *   0 on success, a negative errno value otherwise and rte_errno is set.
2810  */
2811 static int
2812 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
2813                                      uint64_t action_flags,
2814                                      const struct rte_flow_action actions[],
2815                                      struct rte_flow_error *error)
2816 {
2817         const struct rte_flow_action *action = actions;
2818         const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
2819
2820         if (rte_be_to_cpu_16(conf->vlan_vid) > 0xFFE)
2821                 return rte_flow_error_set(error, EINVAL,
2822                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2823                                           "VLAN VID value is too big");
2824         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
2825             !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2826                 return rte_flow_error_set(error, ENOTSUP,
2827                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2828                                           "set VLAN VID action must follow push"
2829                                           " VLAN action or match on VLAN item");
2830         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
2831                 return rte_flow_error_set(error, ENOTSUP,
2832                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2833                                           "Multiple VLAN VID modifications are "
2834                                           "not supported");
2835         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2836                 return rte_flow_error_set(error, EINVAL,
2837                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2838                                           "wrong action order, port_id should "
2839                                           "be after set VLAN VID");
2840         return 0;
2841 }
2842
2843 /*
2844  * Validate the FLAG action.
2845  *
2846  * @param[in] dev
2847  *   Pointer to the rte_eth_dev structure.
2848  * @param[in] action_flags
2849  *   Holds the actions detected until now.
2850  * @param[in] attr
2851  *   Pointer to flow attributes
2852  * @param[out] error
2853  *   Pointer to error structure.
2854  *
2855  * @return
2856  *   0 on success, a negative errno value otherwise and rte_errno is set.
2857  */
2858 static int
2859 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
2860                              uint64_t action_flags,
2861                              const struct rte_flow_attr *attr,
2862                              struct rte_flow_error *error)
2863 {
2864         struct mlx5_priv *priv = dev->data->dev_private;
2865         struct mlx5_dev_config *config = &priv->config;
2866         int ret;
2867
2868         /* Fall back if no extended metadata register support. */
2869         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2870                 return mlx5_flow_validate_action_flag(action_flags, attr,
2871                                                       error);
2872         /* Extensive metadata mode requires registers. */
2873         if (!mlx5_flow_ext_mreg_supported(dev))
2874                 return rte_flow_error_set(error, ENOTSUP,
2875                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2876                                           "no metadata registers "
2877                                           "to support flag action");
2878         if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
2879                 return rte_flow_error_set(error, ENOTSUP,
2880                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2881                                           "extended metadata register"
2882                                           " isn't available");
2883         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2884         if (ret < 0)
2885                 return ret;
2886         MLX5_ASSERT(ret > 0);
2887         if (action_flags & MLX5_FLOW_ACTION_MARK)
2888                 return rte_flow_error_set(error, EINVAL,
2889                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2890                                           "can't mark and flag in same flow");
2891         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2892                 return rte_flow_error_set(error, EINVAL,
2893                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2894                                           "can't have 2 flag"
2895                                           " actions in same flow");
2896         return 0;
2897 }
2898
2899 /**
2900  * Validate MARK action.
2901  *
2902  * @param[in] dev
2903  *   Pointer to the rte_eth_dev structure.
2904  * @param[in] action
2905  *   Pointer to action.
2906  * @param[in] action_flags
2907  *   Holds the actions detected until now.
2908  * @param[in] attr
2909  *   Pointer to flow attributes
2910  * @param[out] error
2911  *   Pointer to error structure.
2912  *
2913  * @return
2914  *   0 on success, a negative errno value otherwise and rte_errno is set.
2915  */
2916 static int
2917 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
2918                              const struct rte_flow_action *action,
2919                              uint64_t action_flags,
2920                              const struct rte_flow_attr *attr,
2921                              struct rte_flow_error *error)
2922 {
2923         struct mlx5_priv *priv = dev->data->dev_private;
2924         struct mlx5_dev_config *config = &priv->config;
2925         const struct rte_flow_action_mark *mark = action->conf;
2926         int ret;
2927
2928         if (is_tunnel_offload_active(dev))
2929                 return rte_flow_error_set(error, ENOTSUP,
2930                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2931                                           "no mark action "
2932                                           "if tunnel offload active");
2933         /* Fall back if no extended metadata register support. */
2934         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2935                 return mlx5_flow_validate_action_mark(action, action_flags,
2936                                                       attr, error);
2937         /* Extensive metadata mode requires registers. */
2938         if (!mlx5_flow_ext_mreg_supported(dev))
2939                 return rte_flow_error_set(error, ENOTSUP,
2940                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2941                                           "no metadata registers "
2942                                           "to support mark action");
2943         if (!priv->sh->dv_mark_mask)
2944                 return rte_flow_error_set(error, ENOTSUP,
2945                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2946                                           "extended metadata register"
2947                                           " isn't available");
2948         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2949         if (ret < 0)
2950                 return ret;
2951         MLX5_ASSERT(ret > 0);
2952         if (!mark)
2953                 return rte_flow_error_set(error, EINVAL,
2954                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2955                                           "configuration cannot be null");
2956         if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
2957                 return rte_flow_error_set(error, EINVAL,
2958                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2959                                           &mark->id,
2960                                           "mark id exceeds the limit");
2961         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2962                 return rte_flow_error_set(error, EINVAL,
2963                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2964                                           "can't flag and mark in same flow");
2965         if (action_flags & MLX5_FLOW_ACTION_MARK)
2966                 return rte_flow_error_set(error, EINVAL,
2967                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2968                                           "can't have 2 mark actions in same"
2969                                           " flow");
2970         return 0;
2971 }
2972
2973 /**
2974  * Validate SET_META action.
2975  *
2976  * @param[in] dev
2977  *   Pointer to the rte_eth_dev structure.
2978  * @param[in] action
2979  *   Pointer to the action structure.
2980  * @param[in] action_flags
2981  *   Holds the actions detected until now.
2982  * @param[in] attr
2983  *   Pointer to flow attributes
2984  * @param[out] error
2985  *   Pointer to error structure.
2986  *
2987  * @return
2988  *   0 on success, a negative errno value otherwise and rte_errno is set.
2989  */
2990 static int
2991 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
2992                                  const struct rte_flow_action *action,
2993                                  uint64_t action_flags __rte_unused,
2994                                  const struct rte_flow_attr *attr,
2995                                  struct rte_flow_error *error)
2996 {
2997         const struct rte_flow_action_set_meta *conf;
2998         uint32_t nic_mask = UINT32_MAX;
2999         int reg;
3000
3001         if (!mlx5_flow_ext_mreg_supported(dev))
3002                 return rte_flow_error_set(error, ENOTSUP,
3003                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3004                                           "extended metadata register"
3005                                           " isn't supported");
3006         reg = flow_dv_get_metadata_reg(dev, attr, error);
3007         if (reg < 0)
3008                 return reg;
3009         if (reg == REG_NON)
3010                 return rte_flow_error_set(error, ENOTSUP,
3011                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3012                                           "unavalable extended metadata register");
3013         if (reg != REG_A && reg != REG_B) {
3014                 struct mlx5_priv *priv = dev->data->dev_private;
3015
3016                 nic_mask = priv->sh->dv_meta_mask;
3017         }
3018         if (!(action->conf))
3019                 return rte_flow_error_set(error, EINVAL,
3020                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3021                                           "configuration cannot be null");
3022         conf = (const struct rte_flow_action_set_meta *)action->conf;
3023         if (!conf->mask)
3024                 return rte_flow_error_set(error, EINVAL,
3025                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3026                                           "zero mask doesn't have any effect");
3027         if (conf->mask & ~nic_mask)
3028                 return rte_flow_error_set(error, EINVAL,
3029                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3030                                           "meta data must be within reg C0");
3031         return 0;
3032 }
3033
3034 /**
3035  * Validate SET_TAG action.
3036  *
3037  * @param[in] dev
3038  *   Pointer to the rte_eth_dev structure.
3039  * @param[in] action
3040  *   Pointer to the action structure.
3041  * @param[in] action_flags
3042  *   Holds the actions detected until now.
3043  * @param[in] attr
3044  *   Pointer to flow attributes
3045  * @param[out] error
3046  *   Pointer to error structure.
3047  *
3048  * @return
3049  *   0 on success, a negative errno value otherwise and rte_errno is set.
3050  */
3051 static int
3052 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
3053                                 const struct rte_flow_action *action,
3054                                 uint64_t action_flags,
3055                                 const struct rte_flow_attr *attr,
3056                                 struct rte_flow_error *error)
3057 {
3058         const struct rte_flow_action_set_tag *conf;
3059         const uint64_t terminal_action_flags =
3060                 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
3061                 MLX5_FLOW_ACTION_RSS;
3062         int ret;
3063
3064         if (!mlx5_flow_ext_mreg_supported(dev))
3065                 return rte_flow_error_set(error, ENOTSUP,
3066                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3067                                           "extensive metadata register"
3068                                           " isn't supported");
3069         if (!(action->conf))
3070                 return rte_flow_error_set(error, EINVAL,
3071                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3072                                           "configuration cannot be null");
3073         conf = (const struct rte_flow_action_set_tag *)action->conf;
3074         if (!conf->mask)
3075                 return rte_flow_error_set(error, EINVAL,
3076                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3077                                           "zero mask doesn't have any effect");
3078         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
3079         if (ret < 0)
3080                 return ret;
3081         if (!attr->transfer && attr->ingress &&
3082             (action_flags & terminal_action_flags))
3083                 return rte_flow_error_set(error, EINVAL,
3084                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3085                                           "set_tag has no effect"
3086                                           " with terminal actions");
3087         return 0;
3088 }
3089
3090 /**
3091  * Validate count action.
3092  *
3093  * @param[in] dev
3094  *   Pointer to rte_eth_dev structure.
3095  * @param[in] action
3096  *   Pointer to the action structure.
3097  * @param[in] action_flags
3098  *   Holds the actions detected until now.
3099  * @param[out] error
3100  *   Pointer to error structure.
3101  *
3102  * @return
3103  *   0 on success, a negative errno value otherwise and rte_errno is set.
3104  */
3105 static int
3106 flow_dv_validate_action_count(struct rte_eth_dev *dev,
3107                               const struct rte_flow_action *action,
3108                               uint64_t action_flags,
3109                               struct rte_flow_error *error)
3110 {
3111         struct mlx5_priv *priv = dev->data->dev_private;
3112         const struct rte_flow_action_count *count;
3113
3114         if (!priv->config.devx)
3115                 goto notsup_err;
3116         if (action_flags & MLX5_FLOW_ACTION_COUNT)
3117                 return rte_flow_error_set(error, EINVAL,
3118                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3119                                           "duplicate count actions set");
3120         count = (const struct rte_flow_action_count *)action->conf;
3121         if (count && count->shared && (action_flags & MLX5_FLOW_ACTION_AGE) &&
3122             !priv->sh->flow_hit_aso_en)
3123                 return rte_flow_error_set(error, EINVAL,
3124                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3125                                           "old age and shared count combination is not supported");
3126 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
3127         return 0;
3128 #endif
3129 notsup_err:
3130         return rte_flow_error_set
3131                       (error, ENOTSUP,
3132                        RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3133                        NULL,
3134                        "count action not supported");
3135 }
3136
3137 /**
3138  * Validate the L2 encap action.
3139  *
3140  * @param[in] dev
3141  *   Pointer to the rte_eth_dev structure.
3142  * @param[in] action_flags
3143  *   Holds the actions detected until now.
3144  * @param[in] action
3145  *   Pointer to the action structure.
3146  * @param[in] attr
3147  *   Pointer to flow attributes.
3148  * @param[out] error
3149  *   Pointer to error structure.
3150  *
3151  * @return
3152  *   0 on success, a negative errno value otherwise and rte_errno is set.
3153  */
3154 static int
3155 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
3156                                  uint64_t action_flags,
3157                                  const struct rte_flow_action *action,
3158                                  const struct rte_flow_attr *attr,
3159                                  struct rte_flow_error *error)
3160 {
3161         const struct mlx5_priv *priv = dev->data->dev_private;
3162
3163         if (!(action->conf))
3164                 return rte_flow_error_set(error, EINVAL,
3165                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3166                                           "configuration cannot be null");
3167         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3168                 return rte_flow_error_set(error, EINVAL,
3169                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3170                                           "can only have a single encap action "
3171                                           "in a flow");
3172         if (!attr->transfer && priv->representor)
3173                 return rte_flow_error_set(error, ENOTSUP,
3174                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3175                                           "encap action for VF representor "
3176                                           "not supported on NIC table");
3177         return 0;
3178 }
3179
3180 /**
3181  * Validate a decap action.
3182  *
3183  * @param[in] dev
3184  *   Pointer to the rte_eth_dev structure.
3185  * @param[in] action_flags
3186  *   Holds the actions detected until now.
3187  * @param[in] action
3188  *   Pointer to the action structure.
3189  * @param[in] item_flags
3190  *   Holds the items detected.
3191  * @param[in] attr
3192  *   Pointer to flow attributes
3193  * @param[out] error
3194  *   Pointer to error structure.
3195  *
3196  * @return
3197  *   0 on success, a negative errno value otherwise and rte_errno is set.
3198  */
3199 static int
3200 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
3201                               uint64_t action_flags,
3202                               const struct rte_flow_action *action,
3203                               const uint64_t item_flags,
3204                               const struct rte_flow_attr *attr,
3205                               struct rte_flow_error *error)
3206 {
3207         const struct mlx5_priv *priv = dev->data->dev_private;
3208
3209         if (priv->config.hca_attr.scatter_fcs_w_decap_disable &&
3210             !priv->config.decap_en)
3211                 return rte_flow_error_set(error, ENOTSUP,
3212                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3213                                           "decap is not enabled");
3214         if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
3215                 return rte_flow_error_set(error, ENOTSUP,
3216                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3217                                           action_flags &
3218                                           MLX5_FLOW_ACTION_DECAP ? "can only "
3219                                           "have a single decap action" : "decap "
3220                                           "after encap is not supported");
3221         if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
3222                 return rte_flow_error_set(error, EINVAL,
3223                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3224                                           "can't have decap action after"
3225                                           " modify action");
3226         if (attr->egress)
3227                 return rte_flow_error_set(error, ENOTSUP,
3228                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
3229                                           NULL,
3230                                           "decap action not supported for "
3231                                           "egress");
3232         if (!attr->transfer && priv->representor)
3233                 return rte_flow_error_set(error, ENOTSUP,
3234                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3235                                           "decap action for VF representor "
3236                                           "not supported on NIC table");
3237         if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_DECAP &&
3238             !(item_flags & MLX5_FLOW_LAYER_VXLAN))
3239                 return rte_flow_error_set(error, ENOTSUP,
3240                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3241                                 "VXLAN item should be present for VXLAN decap");
3242         return 0;
3243 }
3244
3245 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
3246
3247 /**
3248  * Validate the raw encap and decap actions.
3249  *
3250  * @param[in] dev
3251  *   Pointer to the rte_eth_dev structure.
3252  * @param[in] decap
3253  *   Pointer to the decap action.
3254  * @param[in] encap
3255  *   Pointer to the encap action.
3256  * @param[in] attr
3257  *   Pointer to flow attributes
3258  * @param[in/out] action_flags
3259  *   Holds the actions detected until now.
3260  * @param[out] actions_n
3261  *   pointer to the number of actions counter.
3262  * @param[in] action
3263  *   Pointer to the action structure.
3264  * @param[in] item_flags
3265  *   Holds the items detected.
3266  * @param[out] error
3267  *   Pointer to error structure.
3268  *
3269  * @return
3270  *   0 on success, a negative errno value otherwise and rte_errno is set.
3271  */
3272 static int
3273 flow_dv_validate_action_raw_encap_decap
3274         (struct rte_eth_dev *dev,
3275          const struct rte_flow_action_raw_decap *decap,
3276          const struct rte_flow_action_raw_encap *encap,
3277          const struct rte_flow_attr *attr, uint64_t *action_flags,
3278          int *actions_n, const struct rte_flow_action *action,
3279          uint64_t item_flags, struct rte_flow_error *error)
3280 {
3281         const struct mlx5_priv *priv = dev->data->dev_private;
3282         int ret;
3283
3284         if (encap && (!encap->size || !encap->data))
3285                 return rte_flow_error_set(error, EINVAL,
3286                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3287                                           "raw encap data cannot be empty");
3288         if (decap && encap) {
3289                 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
3290                     encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
3291                         /* L3 encap. */
3292                         decap = NULL;
3293                 else if (encap->size <=
3294                            MLX5_ENCAPSULATION_DECISION_SIZE &&
3295                            decap->size >
3296                            MLX5_ENCAPSULATION_DECISION_SIZE)
3297                         /* L3 decap. */
3298                         encap = NULL;
3299                 else if (encap->size >
3300                            MLX5_ENCAPSULATION_DECISION_SIZE &&
3301                            decap->size >
3302                            MLX5_ENCAPSULATION_DECISION_SIZE)
3303                         /* 2 L2 actions: encap and decap. */
3304                         ;
3305                 else
3306                         return rte_flow_error_set(error,
3307                                 ENOTSUP,
3308                                 RTE_FLOW_ERROR_TYPE_ACTION,
3309                                 NULL, "unsupported too small "
3310                                 "raw decap and too small raw "
3311                                 "encap combination");
3312         }
3313         if (decap) {
3314                 ret = flow_dv_validate_action_decap(dev, *action_flags, action,
3315                                                     item_flags, attr, error);
3316                 if (ret < 0)
3317                         return ret;
3318                 *action_flags |= MLX5_FLOW_ACTION_DECAP;
3319                 ++(*actions_n);
3320         }
3321         if (encap) {
3322                 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
3323                         return rte_flow_error_set(error, ENOTSUP,
3324                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3325                                                   NULL,
3326                                                   "small raw encap size");
3327                 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
3328                         return rte_flow_error_set(error, EINVAL,
3329                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3330                                                   NULL,
3331                                                   "more than one encap action");
3332                 if (!attr->transfer && priv->representor)
3333                         return rte_flow_error_set
3334                                         (error, ENOTSUP,
3335                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3336                                          "encap action for VF representor "
3337                                          "not supported on NIC table");
3338                 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
3339                 ++(*actions_n);
3340         }
3341         return 0;
3342 }
3343
3344 /**
3345  * Match encap_decap resource.
3346  *
3347  * @param list
3348  *   Pointer to the hash list.
3349  * @param entry
3350  *   Pointer to exist resource entry object.
3351  * @param key
3352  *   Key of the new entry.
3353  * @param ctx_cb
3354  *   Pointer to new encap_decap resource.
3355  *
3356  * @return
3357  *   0 on matching, none-zero otherwise.
3358  */
3359 int
3360 flow_dv_encap_decap_match_cb(struct mlx5_hlist *list __rte_unused,
3361                              struct mlx5_hlist_entry *entry,
3362                              uint64_t key __rte_unused, void *cb_ctx)
3363 {
3364         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3365         struct mlx5_flow_dv_encap_decap_resource *resource = ctx->data;
3366         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
3367
3368         cache_resource = container_of(entry,
3369                                       struct mlx5_flow_dv_encap_decap_resource,
3370                                       entry);
3371         if (resource->reformat_type == cache_resource->reformat_type &&
3372             resource->ft_type == cache_resource->ft_type &&
3373             resource->flags == cache_resource->flags &&
3374             resource->size == cache_resource->size &&
3375             !memcmp((const void *)resource->buf,
3376                     (const void *)cache_resource->buf,
3377                     resource->size))
3378                 return 0;
3379         return -1;
3380 }
3381
3382 /**
3383  * Allocate encap_decap resource.
3384  *
3385  * @param list
3386  *   Pointer to the hash list.
3387  * @param entry
3388  *   Pointer to exist resource entry object.
3389  * @param ctx_cb
3390  *   Pointer to new encap_decap resource.
3391  *
3392  * @return
3393  *   0 on matching, none-zero otherwise.
3394  */
3395 struct mlx5_hlist_entry *
3396 flow_dv_encap_decap_create_cb(struct mlx5_hlist *list,
3397                               uint64_t key __rte_unused,
3398                               void *cb_ctx)
3399 {
3400         struct mlx5_dev_ctx_shared *sh = list->ctx;
3401         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3402         struct mlx5dv_dr_domain *domain;
3403         struct mlx5_flow_dv_encap_decap_resource *resource = ctx->data;
3404         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
3405         uint32_t idx;
3406         int ret;
3407
3408         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3409                 domain = sh->fdb_domain;
3410         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3411                 domain = sh->rx_domain;
3412         else
3413                 domain = sh->tx_domain;
3414         /* Register new encap/decap resource. */
3415         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
3416                                        &idx);
3417         if (!cache_resource) {
3418                 rte_flow_error_set(ctx->error, ENOMEM,
3419                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3420                                    "cannot allocate resource memory");
3421                 return NULL;
3422         }
3423         *cache_resource = *resource;
3424         cache_resource->idx = idx;
3425         ret = mlx5_flow_os_create_flow_action_packet_reformat
3426                                         (sh->ctx, domain, cache_resource,
3427                                          &cache_resource->action);
3428         if (ret) {
3429                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);
3430                 rte_flow_error_set(ctx->error, ENOMEM,
3431                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3432                                    NULL, "cannot create action");
3433                 return NULL;
3434         }
3435
3436         return &cache_resource->entry;
3437 }
3438
3439 /**
3440  * Find existing encap/decap resource or create and register a new one.
3441  *
3442  * @param[in, out] dev
3443  *   Pointer to rte_eth_dev structure.
3444  * @param[in, out] resource
3445  *   Pointer to encap/decap resource.
3446  * @parm[in, out] dev_flow
3447  *   Pointer to the dev_flow.
3448  * @param[out] error
3449  *   pointer to error structure.
3450  *
3451  * @return
3452  *   0 on success otherwise -errno and errno is set.
3453  */
3454 static int
3455 flow_dv_encap_decap_resource_register
3456                         (struct rte_eth_dev *dev,
3457                          struct mlx5_flow_dv_encap_decap_resource *resource,
3458                          struct mlx5_flow *dev_flow,
3459                          struct rte_flow_error *error)
3460 {
3461         struct mlx5_priv *priv = dev->data->dev_private;
3462         struct mlx5_dev_ctx_shared *sh = priv->sh;
3463         struct mlx5_hlist_entry *entry;
3464         union {
3465                 struct {
3466                         uint32_t ft_type:8;
3467                         uint32_t refmt_type:8;
3468                         /*
3469                          * Header reformat actions can be shared between
3470                          * non-root tables. One bit to indicate non-root
3471                          * table or not.
3472                          */
3473                         uint32_t is_root:1;
3474                         uint32_t reserve:15;
3475                 };
3476                 uint32_t v32;
3477         } encap_decap_key = {
3478                 {
3479                         .ft_type = resource->ft_type,
3480                         .refmt_type = resource->reformat_type,
3481                         .is_root = !!dev_flow->dv.group,
3482                         .reserve = 0,
3483                 }
3484         };
3485         struct mlx5_flow_cb_ctx ctx = {
3486                 .error = error,
3487                 .data = resource,
3488         };
3489         uint64_t key64;
3490
3491         resource->flags = dev_flow->dv.group ? 0 : 1;
3492         key64 =  __rte_raw_cksum(&encap_decap_key.v32,
3493                                  sizeof(encap_decap_key.v32), 0);
3494         if (resource->reformat_type !=
3495             MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2 &&
3496             resource->size)
3497                 key64 = __rte_raw_cksum(resource->buf, resource->size, key64);
3498         entry = mlx5_hlist_register(sh->encaps_decaps, key64, &ctx);
3499         if (!entry)
3500                 return -rte_errno;
3501         resource = container_of(entry, typeof(*resource), entry);
3502         dev_flow->dv.encap_decap = resource;
3503         dev_flow->handle->dvh.rix_encap_decap = resource->idx;
3504         return 0;
3505 }
3506
3507 /**
3508  * Find existing table jump resource or create and register a new one.
3509  *
3510  * @param[in, out] dev
3511  *   Pointer to rte_eth_dev structure.
3512  * @param[in, out] tbl
3513  *   Pointer to flow table resource.
3514  * @parm[in, out] dev_flow
3515  *   Pointer to the dev_flow.
3516  * @param[out] error
3517  *   pointer to error structure.
3518  *
3519  * @return
3520  *   0 on success otherwise -errno and errno is set.
3521  */
3522 static int
3523 flow_dv_jump_tbl_resource_register
3524                         (struct rte_eth_dev *dev __rte_unused,
3525                          struct mlx5_flow_tbl_resource *tbl,
3526                          struct mlx5_flow *dev_flow,
3527                          struct rte_flow_error *error __rte_unused)
3528 {
3529         struct mlx5_flow_tbl_data_entry *tbl_data =
3530                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
3531
3532         MLX5_ASSERT(tbl);
3533         MLX5_ASSERT(tbl_data->jump.action);
3534         dev_flow->handle->rix_jump = tbl_data->idx;
3535         dev_flow->dv.jump = &tbl_data->jump;
3536         return 0;
3537 }
3538
3539 int
3540 flow_dv_port_id_match_cb(struct mlx5_cache_list *list __rte_unused,
3541                          struct mlx5_cache_entry *entry, void *cb_ctx)
3542 {
3543         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3544         struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3545         struct mlx5_flow_dv_port_id_action_resource *res =
3546                         container_of(entry, typeof(*res), entry);
3547
3548         return ref->port_id != res->port_id;
3549 }
3550
3551 struct mlx5_cache_entry *
3552 flow_dv_port_id_create_cb(struct mlx5_cache_list *list,
3553                           struct mlx5_cache_entry *entry __rte_unused,
3554                           void *cb_ctx)
3555 {
3556         struct mlx5_dev_ctx_shared *sh = list->ctx;
3557         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3558         struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3559         struct mlx5_flow_dv_port_id_action_resource *cache;
3560         uint32_t idx;
3561         int ret;
3562
3563         /* Register new port id action resource. */
3564         cache = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID], &idx);
3565         if (!cache) {
3566                 rte_flow_error_set(ctx->error, ENOMEM,
3567                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3568                                    "cannot allocate port_id action cache memory");
3569                 return NULL;
3570         }
3571         *cache = *ref;
3572         ret = mlx5_flow_os_create_flow_action_dest_port(sh->fdb_domain,
3573                                                         ref->port_id,
3574                                                         &cache->action);
3575         if (ret) {
3576                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], idx);
3577                 rte_flow_error_set(ctx->error, ENOMEM,
3578                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3579                                    "cannot create action");
3580                 return NULL;
3581         }
3582         cache->idx = idx;
3583         return &cache->entry;
3584 }
3585
3586 /**
3587  * Find existing table port ID resource or create and register a new one.
3588  *
3589  * @param[in, out] dev
3590  *   Pointer to rte_eth_dev structure.
3591  * @param[in, out] resource
3592  *   Pointer to port ID action resource.
3593  * @parm[in, out] dev_flow
3594  *   Pointer to the dev_flow.
3595  * @param[out] error
3596  *   pointer to error structure.
3597  *
3598  * @return
3599  *   0 on success otherwise -errno and errno is set.
3600  */
3601 static int
3602 flow_dv_port_id_action_resource_register
3603                         (struct rte_eth_dev *dev,
3604                          struct mlx5_flow_dv_port_id_action_resource *resource,
3605                          struct mlx5_flow *dev_flow,
3606                          struct rte_flow_error *error)
3607 {
3608         struct mlx5_priv *priv = dev->data->dev_private;
3609         struct mlx5_cache_entry *entry;
3610         struct mlx5_flow_dv_port_id_action_resource *cache;
3611         struct mlx5_flow_cb_ctx ctx = {
3612                 .error = error,
3613                 .data = resource,
3614         };
3615
3616         entry = mlx5_cache_register(&priv->sh->port_id_action_list, &ctx);
3617         if (!entry)
3618                 return -rte_errno;
3619         cache = container_of(entry, typeof(*cache), entry);
3620         dev_flow->dv.port_id_action = cache;
3621         dev_flow->handle->rix_port_id_action = cache->idx;
3622         return 0;
3623 }
3624
3625 int
3626 flow_dv_push_vlan_match_cb(struct mlx5_cache_list *list __rte_unused,
3627                          struct mlx5_cache_entry *entry, void *cb_ctx)
3628 {
3629         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3630         struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3631         struct mlx5_flow_dv_push_vlan_action_resource *res =
3632                         container_of(entry, typeof(*res), entry);
3633
3634         return ref->vlan_tag != res->vlan_tag || ref->ft_type != res->ft_type;
3635 }
3636
3637 struct mlx5_cache_entry *
3638 flow_dv_push_vlan_create_cb(struct mlx5_cache_list *list,
3639                           struct mlx5_cache_entry *entry __rte_unused,
3640                           void *cb_ctx)
3641 {
3642         struct mlx5_dev_ctx_shared *sh = list->ctx;
3643         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3644         struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3645         struct mlx5_flow_dv_push_vlan_action_resource *cache;
3646         struct mlx5dv_dr_domain *domain;
3647         uint32_t idx;
3648         int ret;
3649
3650         /* Register new port id action resource. */
3651         cache = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN], &idx);
3652         if (!cache) {
3653                 rte_flow_error_set(ctx->error, ENOMEM,
3654                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3655                                    "cannot allocate push_vlan action cache memory");
3656                 return NULL;
3657         }
3658         *cache = *ref;
3659         if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3660                 domain = sh->fdb_domain;
3661         else if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3662                 domain = sh->rx_domain;
3663         else
3664                 domain = sh->tx_domain;
3665         ret = mlx5_flow_os_create_flow_action_push_vlan(domain, ref->vlan_tag,
3666                                                         &cache->action);
3667         if (ret) {
3668                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
3669                 rte_flow_error_set(ctx->error, ENOMEM,
3670                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3671                                    "cannot create push vlan action");
3672                 return NULL;
3673         }
3674         cache->idx = idx;
3675         return &cache->entry;
3676 }
3677
3678 /**
3679  * Find existing push vlan resource or create and register a new one.
3680  *
3681  * @param [in, out] dev
3682  *   Pointer to rte_eth_dev structure.
3683  * @param[in, out] resource
3684  *   Pointer to port ID action resource.
3685  * @parm[in, out] dev_flow
3686  *   Pointer to the dev_flow.
3687  * @param[out] error
3688  *   pointer to error structure.
3689  *
3690  * @return
3691  *   0 on success otherwise -errno and errno is set.
3692  */
3693 static int
3694 flow_dv_push_vlan_action_resource_register
3695                        (struct rte_eth_dev *dev,
3696                         struct mlx5_flow_dv_push_vlan_action_resource *resource,
3697                         struct mlx5_flow *dev_flow,
3698                         struct rte_flow_error *error)
3699 {
3700         struct mlx5_priv *priv = dev->data->dev_private;
3701         struct mlx5_flow_dv_push_vlan_action_resource *cache;
3702         struct mlx5_cache_entry *entry;
3703         struct mlx5_flow_cb_ctx ctx = {
3704                 .error = error,
3705                 .data = resource,
3706         };
3707
3708         entry = mlx5_cache_register(&priv->sh->push_vlan_action_list, &ctx);
3709         if (!entry)
3710                 return -rte_errno;
3711         cache = container_of(entry, typeof(*cache), entry);
3712
3713         dev_flow->handle->dvh.rix_push_vlan = cache->idx;
3714         dev_flow->dv.push_vlan_res = cache;
3715         return 0;
3716 }
3717
3718 /**
3719  * Get the size of specific rte_flow_item_type hdr size
3720  *
3721  * @param[in] item_type
3722  *   Tested rte_flow_item_type.
3723  *
3724  * @return
3725  *   sizeof struct item_type, 0 if void or irrelevant.
3726  */
3727 static size_t
3728 flow_dv_get_item_hdr_len(const enum rte_flow_item_type item_type)
3729 {
3730         size_t retval;
3731
3732         switch (item_type) {
3733         case RTE_FLOW_ITEM_TYPE_ETH:
3734                 retval = sizeof(struct rte_ether_hdr);
3735                 break;
3736         case RTE_FLOW_ITEM_TYPE_VLAN:
3737                 retval = sizeof(struct rte_vlan_hdr);
3738                 break;
3739         case RTE_FLOW_ITEM_TYPE_IPV4:
3740                 retval = sizeof(struct rte_ipv4_hdr);
3741                 break;
3742         case RTE_FLOW_ITEM_TYPE_IPV6:
3743                 retval = sizeof(struct rte_ipv6_hdr);
3744                 break;
3745         case RTE_FLOW_ITEM_TYPE_UDP:
3746                 retval = sizeof(struct rte_udp_hdr);
3747                 break;
3748         case RTE_FLOW_ITEM_TYPE_TCP:
3749                 retval = sizeof(struct rte_tcp_hdr);
3750                 break;
3751         case RTE_FLOW_ITEM_TYPE_VXLAN:
3752         case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3753                 retval = sizeof(struct rte_vxlan_hdr);
3754                 break;
3755         case RTE_FLOW_ITEM_TYPE_GRE:
3756         case RTE_FLOW_ITEM_TYPE_NVGRE:
3757                 retval = sizeof(struct rte_gre_hdr);
3758                 break;
3759         case RTE_FLOW_ITEM_TYPE_MPLS:
3760                 retval = sizeof(struct rte_mpls_hdr);
3761                 break;
3762         case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
3763         default:
3764                 retval = 0;
3765                 break;
3766         }
3767         return retval;
3768 }
3769
3770 #define MLX5_ENCAP_IPV4_VERSION         0x40
3771 #define MLX5_ENCAP_IPV4_IHL_MIN         0x05
3772 #define MLX5_ENCAP_IPV4_TTL_DEF         0x40
3773 #define MLX5_ENCAP_IPV6_VTC_FLOW        0x60000000
3774 #define MLX5_ENCAP_IPV6_HOP_LIMIT       0xff
3775 #define MLX5_ENCAP_VXLAN_FLAGS          0x08000000
3776 #define MLX5_ENCAP_VXLAN_GPE_FLAGS      0x04
3777
3778 /**
3779  * Convert the encap action data from list of rte_flow_item to raw buffer
3780  *
3781  * @param[in] items
3782  *   Pointer to rte_flow_item objects list.
3783  * @param[out] buf
3784  *   Pointer to the output buffer.
3785  * @param[out] size
3786  *   Pointer to the output buffer size.
3787  * @param[out] error
3788  *   Pointer to the error structure.
3789  *
3790  * @return
3791  *   0 on success, a negative errno value otherwise and rte_errno is set.
3792  */
3793 static int
3794 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
3795                            size_t *size, struct rte_flow_error *error)
3796 {
3797         struct rte_ether_hdr *eth = NULL;
3798         struct rte_vlan_hdr *vlan = NULL;
3799         struct rte_ipv4_hdr *ipv4 = NULL;
3800         struct rte_ipv6_hdr *ipv6 = NULL;
3801         struct rte_udp_hdr *udp = NULL;
3802         struct rte_vxlan_hdr *vxlan = NULL;
3803         struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
3804         struct rte_gre_hdr *gre = NULL;
3805         size_t len;
3806         size_t temp_size = 0;
3807
3808         if (!items)
3809                 return rte_flow_error_set(error, EINVAL,
3810                                           RTE_FLOW_ERROR_TYPE_ACTION,
3811                                           NULL, "invalid empty data");
3812         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
3813                 len = flow_dv_get_item_hdr_len(items->type);
3814                 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
3815                         return rte_flow_error_set(error, EINVAL,
3816                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3817                                                   (void *)items->type,
3818                                                   "items total size is too big"
3819                                                   " for encap action");
3820                 rte_memcpy((void *)&buf[temp_size], items->spec, len);
3821                 switch (items->type) {
3822                 case RTE_FLOW_ITEM_TYPE_ETH:
3823                         eth = (struct rte_ether_hdr *)&buf[temp_size];
3824                         break;
3825                 case RTE_FLOW_ITEM_TYPE_VLAN:
3826                         vlan = (struct rte_vlan_hdr *)&buf[temp_size];
3827                         if (!eth)
3828                                 return rte_flow_error_set(error, EINVAL,
3829                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3830                                                 (void *)items->type,
3831                                                 "eth header not found");
3832                         if (!eth->ether_type)
3833                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
3834                         break;
3835                 case RTE_FLOW_ITEM_TYPE_IPV4:
3836                         ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
3837                         if (!vlan && !eth)
3838                                 return rte_flow_error_set(error, EINVAL,
3839                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3840                                                 (void *)items->type,
3841                                                 "neither eth nor vlan"
3842                                                 " header found");
3843                         if (vlan && !vlan->eth_proto)
3844                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3845                         else if (eth && !eth->ether_type)
3846                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3847                         if (!ipv4->version_ihl)
3848                                 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
3849                                                     MLX5_ENCAP_IPV4_IHL_MIN;
3850                         if (!ipv4->time_to_live)
3851                                 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
3852                         break;
3853                 case RTE_FLOW_ITEM_TYPE_IPV6:
3854                         ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
3855                         if (!vlan && !eth)
3856                                 return rte_flow_error_set(error, EINVAL,
3857                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3858                                                 (void *)items->type,
3859                                                 "neither eth nor vlan"
3860                                                 " header found");
3861                         if (vlan && !vlan->eth_proto)
3862                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3863                         else if (eth && !eth->ether_type)
3864                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3865                         if (!ipv6->vtc_flow)
3866                                 ipv6->vtc_flow =
3867                                         RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
3868                         if (!ipv6->hop_limits)
3869                                 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
3870                         break;
3871                 case RTE_FLOW_ITEM_TYPE_UDP:
3872                         udp = (struct rte_udp_hdr *)&buf[temp_size];
3873                         if (!ipv4 && !ipv6)
3874                                 return rte_flow_error_set(error, EINVAL,
3875                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3876                                                 (void *)items->type,
3877                                                 "ip header not found");
3878                         if (ipv4 && !ipv4->next_proto_id)
3879                                 ipv4->next_proto_id = IPPROTO_UDP;
3880                         else if (ipv6 && !ipv6->proto)
3881                                 ipv6->proto = IPPROTO_UDP;
3882                         break;
3883                 case RTE_FLOW_ITEM_TYPE_VXLAN:
3884                         vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
3885                         if (!udp)
3886                                 return rte_flow_error_set(error, EINVAL,
3887                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3888                                                 (void *)items->type,
3889                                                 "udp header not found");
3890                         if (!udp->dst_port)
3891                                 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
3892                         if (!vxlan->vx_flags)
3893                                 vxlan->vx_flags =
3894                                         RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
3895                         break;
3896                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3897                         vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
3898                         if (!udp)
3899                                 return rte_flow_error_set(error, EINVAL,
3900                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3901                                                 (void *)items->type,
3902                                                 "udp header not found");
3903                         if (!vxlan_gpe->proto)
3904                                 return rte_flow_error_set(error, EINVAL,
3905                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3906                                                 (void *)items->type,
3907                                                 "next protocol not found");
3908                         if (!udp->dst_port)
3909                                 udp->dst_port =
3910                                         RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
3911                         if (!vxlan_gpe->vx_flags)
3912                                 vxlan_gpe->vx_flags =
3913                                                 MLX5_ENCAP_VXLAN_GPE_FLAGS;
3914                         break;
3915                 case RTE_FLOW_ITEM_TYPE_GRE:
3916                 case RTE_FLOW_ITEM_TYPE_NVGRE:
3917                         gre = (struct rte_gre_hdr *)&buf[temp_size];
3918                         if (!gre->proto)
3919                                 return rte_flow_error_set(error, EINVAL,
3920                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3921                                                 (void *)items->type,
3922                                                 "next protocol not found");
3923                         if (!ipv4 && !ipv6)
3924                                 return rte_flow_error_set(error, EINVAL,
3925                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3926                                                 (void *)items->type,
3927                                                 "ip header not found");
3928                         if (ipv4 && !ipv4->next_proto_id)
3929                                 ipv4->next_proto_id = IPPROTO_GRE;
3930                         else if (ipv6 && !ipv6->proto)
3931                                 ipv6->proto = IPPROTO_GRE;
3932                         break;
3933                 case RTE_FLOW_ITEM_TYPE_VOID:
3934                         break;
3935                 default:
3936                         return rte_flow_error_set(error, EINVAL,
3937                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3938                                                   (void *)items->type,
3939                                                   "unsupported item type");
3940                         break;
3941                 }
3942                 temp_size += len;
3943         }
3944         *size = temp_size;
3945         return 0;
3946 }
3947
3948 static int
3949 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
3950 {
3951         struct rte_ether_hdr *eth = NULL;
3952         struct rte_vlan_hdr *vlan = NULL;
3953         struct rte_ipv6_hdr *ipv6 = NULL;
3954         struct rte_udp_hdr *udp = NULL;
3955         char *next_hdr;
3956         uint16_t proto;
3957
3958         eth = (struct rte_ether_hdr *)data;
3959         next_hdr = (char *)(eth + 1);
3960         proto = RTE_BE16(eth->ether_type);
3961
3962         /* VLAN skipping */
3963         while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
3964                 vlan = (struct rte_vlan_hdr *)next_hdr;
3965                 proto = RTE_BE16(vlan->eth_proto);
3966                 next_hdr += sizeof(struct rte_vlan_hdr);
3967         }
3968
3969         /* HW calculates IPv4 csum. no need to proceed */
3970         if (proto == RTE_ETHER_TYPE_IPV4)
3971                 return 0;
3972
3973         /* non IPv4/IPv6 header. not supported */
3974         if (proto != RTE_ETHER_TYPE_IPV6) {
3975                 return rte_flow_error_set(error, ENOTSUP,
3976                                           RTE_FLOW_ERROR_TYPE_ACTION,
3977                                           NULL, "Cannot offload non IPv4/IPv6");
3978         }
3979
3980         ipv6 = (struct rte_ipv6_hdr *)next_hdr;
3981
3982         /* ignore non UDP */
3983         if (ipv6->proto != IPPROTO_UDP)
3984                 return 0;
3985
3986         udp = (struct rte_udp_hdr *)(ipv6 + 1);
3987         udp->dgram_cksum = 0;
3988
3989         return 0;
3990 }
3991
3992 /**
3993  * Convert L2 encap action to DV specification.
3994  *
3995  * @param[in] dev
3996  *   Pointer to rte_eth_dev structure.
3997  * @param[in] action
3998  *   Pointer to action structure.
3999  * @param[in, out] dev_flow
4000  *   Pointer to the mlx5_flow.
4001  * @param[in] transfer
4002  *   Mark if the flow is E-Switch flow.
4003  * @param[out] error
4004  *   Pointer to the error structure.
4005  *
4006  * @return
4007  *   0 on success, a negative errno value otherwise and rte_errno is set.
4008  */
4009 static int
4010 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
4011                                const struct rte_flow_action *action,
4012                                struct mlx5_flow *dev_flow,
4013                                uint8_t transfer,
4014                                struct rte_flow_error *error)
4015 {
4016         const struct rte_flow_item *encap_data;
4017         const struct rte_flow_action_raw_encap *raw_encap_data;
4018         struct mlx5_flow_dv_encap_decap_resource res = {
4019                 .reformat_type =
4020                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
4021                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
4022                                       MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
4023         };
4024
4025         if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
4026                 raw_encap_data =
4027                         (const struct rte_flow_action_raw_encap *)action->conf;
4028                 res.size = raw_encap_data->size;
4029                 memcpy(res.buf, raw_encap_data->data, res.size);
4030         } else {
4031                 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
4032                         encap_data =
4033                                 ((const struct rte_flow_action_vxlan_encap *)
4034                                                 action->conf)->definition;
4035                 else
4036                         encap_data =
4037                                 ((const struct rte_flow_action_nvgre_encap *)
4038                                                 action->conf)->definition;
4039                 if (flow_dv_convert_encap_data(encap_data, res.buf,
4040                                                &res.size, error))
4041                         return -rte_errno;
4042         }
4043         if (flow_dv_zero_encap_udp_csum(res.buf, error))
4044                 return -rte_errno;
4045         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4046                 return rte_flow_error_set(error, EINVAL,
4047                                           RTE_FLOW_ERROR_TYPE_ACTION,
4048                                           NULL, "can't create L2 encap action");
4049         return 0;
4050 }
4051
4052 /**
4053  * Convert L2 decap action to DV specification.
4054  *
4055  * @param[in] dev
4056  *   Pointer to rte_eth_dev structure.
4057  * @param[in, out] dev_flow
4058  *   Pointer to the mlx5_flow.
4059  * @param[in] transfer
4060  *   Mark if the flow is E-Switch flow.
4061  * @param[out] error
4062  *   Pointer to the error structure.
4063  *
4064  * @return
4065  *   0 on success, a negative errno value otherwise and rte_errno is set.
4066  */
4067 static int
4068 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
4069                                struct mlx5_flow *dev_flow,
4070                                uint8_t transfer,
4071                                struct rte_flow_error *error)
4072 {
4073         struct mlx5_flow_dv_encap_decap_resource res = {
4074                 .size = 0,
4075                 .reformat_type =
4076                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
4077                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
4078                                       MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
4079         };
4080
4081         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4082                 return rte_flow_error_set(error, EINVAL,
4083                                           RTE_FLOW_ERROR_TYPE_ACTION,
4084                                           NULL, "can't create L2 decap action");
4085         return 0;
4086 }
4087
4088 /**
4089  * Convert raw decap/encap (L3 tunnel) action to DV specification.
4090  *
4091  * @param[in] dev
4092  *   Pointer to rte_eth_dev structure.
4093  * @param[in] action
4094  *   Pointer to action structure.
4095  * @param[in, out] dev_flow
4096  *   Pointer to the mlx5_flow.
4097  * @param[in] attr
4098  *   Pointer to the flow attributes.
4099  * @param[out] error
4100  *   Pointer to the error structure.
4101  *
4102  * @return
4103  *   0 on success, a negative errno value otherwise and rte_errno is set.
4104  */
4105 static int
4106 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
4107                                 const struct rte_flow_action *action,
4108                                 struct mlx5_flow *dev_flow,
4109                                 const struct rte_flow_attr *attr,
4110                                 struct rte_flow_error *error)
4111 {
4112         const struct rte_flow_action_raw_encap *encap_data;
4113         struct mlx5_flow_dv_encap_decap_resource res;
4114
4115         memset(&res, 0, sizeof(res));
4116         encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
4117         res.size = encap_data->size;
4118         memcpy(res.buf, encap_data->data, res.size);
4119         res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
4120                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
4121                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
4122         if (attr->transfer)
4123                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
4124         else
4125                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
4126                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
4127         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4128                 return rte_flow_error_set(error, EINVAL,
4129                                           RTE_FLOW_ERROR_TYPE_ACTION,
4130                                           NULL, "can't create encap action");
4131         return 0;
4132 }
4133
4134 /**
4135  * Create action push VLAN.
4136  *
4137  * @param[in] dev
4138  *   Pointer to rte_eth_dev structure.
4139  * @param[in] attr
4140  *   Pointer to the flow attributes.
4141  * @param[in] vlan
4142  *   Pointer to the vlan to push to the Ethernet header.
4143  * @param[in, out] dev_flow
4144  *   Pointer to the mlx5_flow.
4145  * @param[out] error
4146  *   Pointer to the error structure.
4147  *
4148  * @return
4149  *   0 on success, a negative errno value otherwise and rte_errno is set.
4150  */
4151 static int
4152 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
4153                                 const struct rte_flow_attr *attr,
4154                                 const struct rte_vlan_hdr *vlan,
4155                                 struct mlx5_flow *dev_flow,
4156                                 struct rte_flow_error *error)
4157 {
4158         struct mlx5_flow_dv_push_vlan_action_resource res;
4159
4160         memset(&res, 0, sizeof(res));
4161         res.vlan_tag =
4162                 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
4163                                  vlan->vlan_tci);
4164         if (attr->transfer)
4165                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
4166         else
4167                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
4168                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
4169         return flow_dv_push_vlan_action_resource_register
4170                                             (dev, &res, dev_flow, error);
4171 }
4172
4173 /**
4174  * Validate the modify-header actions.
4175  *
4176  * @param[in] action_flags
4177  *   Holds the actions detected until now.
4178  * @param[in] action
4179  *   Pointer to the modify action.
4180  * @param[out] error
4181  *   Pointer to error structure.
4182  *
4183  * @return
4184  *   0 on success, a negative errno value otherwise and rte_errno is set.
4185  */
4186 static int
4187 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
4188                                    const struct rte_flow_action *action,
4189                                    struct rte_flow_error *error)
4190 {
4191         if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
4192                 return rte_flow_error_set(error, EINVAL,
4193                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4194                                           NULL, "action configuration not set");
4195         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
4196                 return rte_flow_error_set(error, EINVAL,
4197                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4198                                           "can't have encap action before"
4199                                           " modify action");
4200         return 0;
4201 }
4202
4203 /**
4204  * Validate the modify-header MAC address actions.
4205  *
4206  * @param[in] action_flags
4207  *   Holds the actions detected until now.
4208  * @param[in] action
4209  *   Pointer to the modify action.
4210  * @param[in] item_flags
4211  *   Holds the items detected.
4212  * @param[out] error
4213  *   Pointer to error structure.
4214  *
4215  * @return
4216  *   0 on success, a negative errno value otherwise and rte_errno is set.
4217  */
4218 static int
4219 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
4220                                    const struct rte_flow_action *action,
4221                                    const uint64_t item_flags,
4222                                    struct rte_flow_error *error)
4223 {
4224         int ret = 0;
4225
4226         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4227         if (!ret) {
4228                 if (!(item_flags & MLX5_FLOW_LAYER_L2))
4229                         return rte_flow_error_set(error, EINVAL,
4230                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4231                                                   NULL,
4232                                                   "no L2 item in pattern");
4233         }
4234         return ret;
4235 }
4236
4237 /**
4238  * Validate the modify-header IPv4 address actions.
4239  *
4240  * @param[in] action_flags
4241  *   Holds the actions detected until now.
4242  * @param[in] action
4243  *   Pointer to the modify action.
4244  * @param[in] item_flags
4245  *   Holds the items detected.
4246  * @param[out] error
4247  *   Pointer to error structure.
4248  *
4249  * @return
4250  *   0 on success, a negative errno value otherwise and rte_errno is set.
4251  */
4252 static int
4253 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
4254                                     const struct rte_flow_action *action,
4255                                     const uint64_t item_flags,
4256                                     struct rte_flow_error *error)
4257 {
4258         int ret = 0;
4259         uint64_t layer;
4260
4261         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4262         if (!ret) {
4263                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4264                                  MLX5_FLOW_LAYER_INNER_L3_IPV4 :
4265                                  MLX5_FLOW_LAYER_OUTER_L3_IPV4;
4266                 if (!(item_flags & layer))
4267                         return rte_flow_error_set(error, EINVAL,
4268                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4269                                                   NULL,
4270                                                   "no ipv4 item in pattern");
4271         }
4272         return ret;
4273 }
4274
4275 /**
4276  * Validate the modify-header IPv6 address actions.
4277  *
4278  * @param[in] action_flags
4279  *   Holds the actions detected until now.
4280  * @param[in] action
4281  *   Pointer to the modify action.
4282  * @param[in] item_flags
4283  *   Holds the items detected.
4284  * @param[out] error
4285  *   Pointer to error structure.
4286  *
4287  * @return
4288  *   0 on success, a negative errno value otherwise and rte_errno is set.
4289  */
4290 static int
4291 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
4292                                     const struct rte_flow_action *action,
4293                                     const uint64_t item_flags,
4294                                     struct rte_flow_error *error)
4295 {
4296         int ret = 0;
4297         uint64_t layer;
4298
4299         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4300         if (!ret) {
4301                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4302                                  MLX5_FLOW_LAYER_INNER_L3_IPV6 :
4303                                  MLX5_FLOW_LAYER_OUTER_L3_IPV6;
4304                 if (!(item_flags & layer))
4305                         return rte_flow_error_set(error, EINVAL,
4306                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4307                                                   NULL,
4308                                                   "no ipv6 item in pattern");
4309         }
4310         return ret;
4311 }
4312
4313 /**
4314  * Validate the modify-header TP actions.
4315  *
4316  * @param[in] action_flags
4317  *   Holds the actions detected until now.
4318  * @param[in] action
4319  *   Pointer to the modify action.
4320  * @param[in] item_flags
4321  *   Holds the items detected.
4322  * @param[out] error
4323  *   Pointer to error structure.
4324  *
4325  * @return
4326  *   0 on success, a negative errno value otherwise and rte_errno is set.
4327  */
4328 static int
4329 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
4330                                   const struct rte_flow_action *action,
4331                                   const uint64_t item_flags,
4332                                   struct rte_flow_error *error)
4333 {
4334         int ret = 0;
4335         uint64_t layer;
4336
4337         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4338         if (!ret) {
4339                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4340                                  MLX5_FLOW_LAYER_INNER_L4 :
4341                                  MLX5_FLOW_LAYER_OUTER_L4;
4342                 if (!(item_flags & layer))
4343                         return rte_flow_error_set(error, EINVAL,
4344                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4345                                                   NULL, "no transport layer "
4346                                                   "in pattern");
4347         }
4348         return ret;
4349 }
4350
4351 /**
4352  * Validate the modify-header actions of increment/decrement
4353  * TCP Sequence-number.
4354  *
4355  * @param[in] action_flags
4356  *   Holds the actions detected until now.
4357  * @param[in] action
4358  *   Pointer to the modify action.
4359  * @param[in] item_flags
4360  *   Holds the items detected.
4361  * @param[out] error
4362  *   Pointer to error structure.
4363  *
4364  * @return
4365  *   0 on success, a negative errno value otherwise and rte_errno is set.
4366  */
4367 static int
4368 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
4369                                        const struct rte_flow_action *action,
4370                                        const uint64_t item_flags,
4371                                        struct rte_flow_error *error)
4372 {
4373         int ret = 0;
4374         uint64_t layer;
4375
4376         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4377         if (!ret) {
4378                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4379                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
4380                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
4381                 if (!(item_flags & layer))
4382                         return rte_flow_error_set(error, EINVAL,
4383                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4384                                                   NULL, "no TCP item in"
4385                                                   " pattern");
4386                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
4387                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
4388                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
4389                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
4390                         return rte_flow_error_set(error, EINVAL,
4391                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4392                                                   NULL,
4393                                                   "cannot decrease and increase"
4394                                                   " TCP sequence number"
4395                                                   " at the same time");
4396         }
4397         return ret;
4398 }
4399
4400 /**
4401  * Validate the modify-header actions of increment/decrement
4402  * TCP Acknowledgment number.
4403  *
4404  * @param[in] action_flags
4405  *   Holds the actions detected until now.
4406  * @param[in] action
4407  *   Pointer to the modify action.
4408  * @param[in] item_flags
4409  *   Holds the items detected.
4410  * @param[out] error
4411  *   Pointer to error structure.
4412  *
4413  * @return
4414  *   0 on success, a negative errno value otherwise and rte_errno is set.
4415  */
4416 static int
4417 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
4418                                        const struct rte_flow_action *action,
4419                                        const uint64_t item_flags,
4420                                        struct rte_flow_error *error)
4421 {
4422         int ret = 0;
4423         uint64_t layer;
4424
4425         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4426         if (!ret) {
4427                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4428                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
4429                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
4430                 if (!(item_flags & layer))
4431                         return rte_flow_error_set(error, EINVAL,
4432                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4433                                                   NULL, "no TCP item in"
4434                                                   " pattern");
4435                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
4436                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
4437                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
4438                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
4439                         return rte_flow_error_set(error, EINVAL,
4440                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4441                                                   NULL,
4442                                                   "cannot decrease and increase"
4443                                                   " TCP acknowledgment number"
4444                                                   " at the same time");
4445         }
4446         return ret;
4447 }
4448
4449 /**
4450  * Validate the modify-header TTL actions.
4451  *
4452  * @param[in] action_flags
4453  *   Holds the actions detected until now.
4454  * @param[in] action
4455  *   Pointer to the modify action.
4456  * @param[in] item_flags
4457  *   Holds the items detected.
4458  * @param[out] error
4459  *   Pointer to error structure.
4460  *
4461  * @return
4462  *   0 on success, a negative errno value otherwise and rte_errno is set.
4463  */
4464 static int
4465 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
4466                                    const struct rte_flow_action *action,
4467                                    const uint64_t item_flags,
4468                                    struct rte_flow_error *error)
4469 {
4470         int ret = 0;
4471         uint64_t layer;
4472
4473         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4474         if (!ret) {
4475                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4476                                  MLX5_FLOW_LAYER_INNER_L3 :
4477                                  MLX5_FLOW_LAYER_OUTER_L3;
4478                 if (!(item_flags & layer))
4479                         return rte_flow_error_set(error, EINVAL,
4480                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4481                                                   NULL,
4482                                                   "no IP protocol in pattern");
4483         }
4484         return ret;
4485 }
4486
4487 static int
4488 mlx5_flow_item_field_width(enum rte_flow_field_id field)
4489 {
4490         switch (field) {
4491         case RTE_FLOW_FIELD_START:
4492                 return 32;
4493         case RTE_FLOW_FIELD_MAC_DST:
4494         case RTE_FLOW_FIELD_MAC_SRC:
4495                 return 48;
4496         case RTE_FLOW_FIELD_VLAN_TYPE:
4497                 return 16;
4498         case RTE_FLOW_FIELD_VLAN_ID:
4499                 return 12;
4500         case RTE_FLOW_FIELD_MAC_TYPE:
4501                 return 16;
4502         case RTE_FLOW_FIELD_IPV4_DSCP:
4503                 return 6;
4504         case RTE_FLOW_FIELD_IPV4_TTL:
4505                 return 8;
4506         case RTE_FLOW_FIELD_IPV4_SRC:
4507         case RTE_FLOW_FIELD_IPV4_DST:
4508                 return 32;
4509         case RTE_FLOW_FIELD_IPV6_DSCP:
4510                 return 6;
4511         case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
4512                 return 8;
4513         case RTE_FLOW_FIELD_IPV6_SRC:
4514         case RTE_FLOW_FIELD_IPV6_DST:
4515                 return 128;
4516         case RTE_FLOW_FIELD_TCP_PORT_SRC:
4517         case RTE_FLOW_FIELD_TCP_PORT_DST:
4518                 return 16;
4519         case RTE_FLOW_FIELD_TCP_SEQ_NUM:
4520         case RTE_FLOW_FIELD_TCP_ACK_NUM:
4521                 return 32;
4522         case RTE_FLOW_FIELD_TCP_FLAGS:
4523                 return 6;
4524         case RTE_FLOW_FIELD_UDP_PORT_SRC:
4525         case RTE_FLOW_FIELD_UDP_PORT_DST:
4526                 return 16;
4527         case RTE_FLOW_FIELD_VXLAN_VNI:
4528         case RTE_FLOW_FIELD_GENEVE_VNI:
4529                 return 24;
4530         case RTE_FLOW_FIELD_GTP_TEID:
4531         case RTE_FLOW_FIELD_TAG:
4532                 return 32;
4533         case RTE_FLOW_FIELD_MARK:
4534                 return 24;
4535         case RTE_FLOW_FIELD_META:
4536         case RTE_FLOW_FIELD_POINTER:
4537         case RTE_FLOW_FIELD_VALUE:
4538                 return 32;
4539         default:
4540                 MLX5_ASSERT(false);
4541         }
4542         return 0;
4543 }
4544
4545 /**
4546  * Validate the generic modify field actions.
4547  * @param[in] dev
4548  *   Pointer to the rte_eth_dev structure.
4549  * @param[in] action_flags
4550  *   Holds the actions detected until now.
4551  * @param[in] action
4552  *   Pointer to the modify action.
4553  * @param[in] attr
4554  *   Pointer to the flow attributes.
4555  * @param[out] error
4556  *   Pointer to error structure.
4557  *
4558  * @return
4559  *   Number of header fields to modify (0 or more) on success,
4560  *   a negative errno value otherwise and rte_errno is set.
4561  */
4562 static int
4563 flow_dv_validate_action_modify_field(struct rte_eth_dev *dev,
4564                                    const uint64_t action_flags,
4565                                    const struct rte_flow_action *action,
4566                                    const struct rte_flow_attr *attr,
4567                                    struct rte_flow_error *error)
4568 {
4569         int ret = 0;
4570         struct mlx5_priv *priv = dev->data->dev_private;
4571         struct mlx5_dev_config *config = &priv->config;
4572         const struct rte_flow_action_modify_field *action_modify_field =
4573                 action->conf;
4574         uint32_t dst_width =
4575                 mlx5_flow_item_field_width(action_modify_field->dst.field);
4576         uint32_t src_width =
4577                 mlx5_flow_item_field_width(action_modify_field->src.field);
4578
4579         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4580         if (ret)
4581                 return ret;
4582
4583         if (action_modify_field->width == 0)
4584                 return rte_flow_error_set(error, EINVAL,
4585                                 RTE_FLOW_ERROR_TYPE_ACTION, action,
4586                                 "no bits are requested to be modified");
4587         else if (action_modify_field->width > dst_width ||
4588                  action_modify_field->width > src_width)
4589                 return rte_flow_error_set(error, EINVAL,
4590                                 RTE_FLOW_ERROR_TYPE_ACTION, action,
4591                                 "cannot modify more bits than"
4592                                 " the width of a field");
4593         if (action_modify_field->dst.field != RTE_FLOW_FIELD_VALUE &&
4594             action_modify_field->dst.field != RTE_FLOW_FIELD_POINTER) {
4595                 if ((action_modify_field->dst.offset +
4596                      action_modify_field->width > dst_width) ||
4597                     (action_modify_field->dst.offset % 32))
4598                         return rte_flow_error_set(error, EINVAL,
4599                                         RTE_FLOW_ERROR_TYPE_ACTION, action,
4600                                         "destination offset is too big"
4601                                         " or not aligned to 4 bytes");
4602                 if (action_modify_field->dst.level &&
4603                     action_modify_field->dst.field != RTE_FLOW_FIELD_TAG)
4604                         return rte_flow_error_set(error, ENOTSUP,
4605                                         RTE_FLOW_ERROR_TYPE_ACTION, action,
4606                                         "inner header fields modification"
4607                                         " is not supported");
4608         }
4609         if (action_modify_field->src.field != RTE_FLOW_FIELD_VALUE &&
4610             action_modify_field->src.field != RTE_FLOW_FIELD_POINTER) {
4611                 if (!attr->transfer && !attr->group)
4612                         return rte_flow_error_set(error, ENOTSUP,
4613                                         RTE_FLOW_ERROR_TYPE_ACTION, action,
4614                                         "modify field action is not"
4615                                         " supported for group 0");
4616                 if ((action_modify_field->src.offset +
4617                      action_modify_field->width > src_width) ||
4618                     (action_modify_field->src.offset % 32))
4619                         return rte_flow_error_set(error, EINVAL,
4620                                         RTE_FLOW_ERROR_TYPE_ACTION, action,
4621                                         "source offset is too big"
4622                                         " or not aligned to 4 bytes");
4623                 if (action_modify_field->src.level &&
4624                     action_modify_field->src.field != RTE_FLOW_FIELD_TAG)
4625                         return rte_flow_error_set(error, ENOTSUP,
4626                                         RTE_FLOW_ERROR_TYPE_ACTION, action,
4627                                         "inner header fields modification"
4628                                         " is not supported");
4629         }
4630         if (action_modify_field->dst.field ==
4631             action_modify_field->src.field)
4632                 return rte_flow_error_set(error, EINVAL,
4633                                 RTE_FLOW_ERROR_TYPE_ACTION, action,
4634                                 "source and destination fields"
4635                                 " cannot be the same");
4636         if (action_modify_field->dst.field == RTE_FLOW_FIELD_VALUE ||
4637             action_modify_field->dst.field == RTE_FLOW_FIELD_POINTER)
4638                 return rte_flow_error_set(error, EINVAL,
4639                                 RTE_FLOW_ERROR_TYPE_ACTION, action,
4640                                 "immediate value or a pointer to it"
4641                                 " cannot be used as a destination");
4642         if (action_modify_field->dst.field == RTE_FLOW_FIELD_START ||
4643             action_modify_field->src.field == RTE_FLOW_FIELD_START)
4644                 return rte_flow_error_set(error, ENOTSUP,
4645                                 RTE_FLOW_ERROR_TYPE_ACTION, action,
4646                                 "modifications of an arbitrary"
4647                                 " place in a packet is not supported");
4648         if (action_modify_field->dst.field == RTE_FLOW_FIELD_VLAN_TYPE ||
4649             action_modify_field->src.field == RTE_FLOW_FIELD_VLAN_TYPE)
4650                 return rte_flow_error_set(error, ENOTSUP,
4651                                 RTE_FLOW_ERROR_TYPE_ACTION, action,
4652                                 "modifications of the 802.1Q Tag"
4653                                 " Identifier is not supported");
4654         if (action_modify_field->dst.field == RTE_FLOW_FIELD_VXLAN_VNI ||
4655             action_modify_field->src.field == RTE_FLOW_FIELD_VXLAN_VNI)
4656                 return rte_flow_error_set(error, ENOTSUP,
4657                                 RTE_FLOW_ERROR_TYPE_ACTION, action,
4658                                 "modifications of the VXLAN Network"
4659                                 " Identifier is not supported");
4660         if (action_modify_field->dst.field == RTE_FLOW_FIELD_GENEVE_VNI ||
4661             action_modify_field->src.field == RTE_FLOW_FIELD_GENEVE_VNI)
4662                 return rte_flow_error_set(error, ENOTSUP,
4663                                 RTE_FLOW_ERROR_TYPE_ACTION, action,
4664                                 "modifications of the GENEVE Network"
4665                                 " Identifier is not supported");
4666         if (action_modify_field->dst.field == RTE_FLOW_FIELD_MARK ||
4667             action_modify_field->src.field == RTE_FLOW_FIELD_MARK ||
4668             action_modify_field->dst.field == RTE_FLOW_FIELD_META ||
4669             action_modify_field->src.field == RTE_FLOW_FIELD_META) {
4670                 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY ||
4671                     !mlx5_flow_ext_mreg_supported(dev))
4672                         return rte_flow_error_set(error, ENOTSUP,
4673                                         RTE_FLOW_ERROR_TYPE_ACTION, action,
4674                                         "cannot modify mark or metadata without"
4675                                         " extended metadata register support");
4676         }
4677         if (action_modify_field->operation != RTE_FLOW_MODIFY_SET)
4678                 return rte_flow_error_set(error, ENOTSUP,
4679                                 RTE_FLOW_ERROR_TYPE_ACTION, action,
4680                                 "add and sub operations"
4681                                 " are not supported");
4682         return (action_modify_field->width / 32) +
4683                !!(action_modify_field->width % 32);
4684 }
4685
4686 /**
4687  * Validate jump action.
4688  *
4689  * @param[in] action
4690  *   Pointer to the jump action.
4691  * @param[in] action_flags
4692  *   Holds the actions detected until now.
4693  * @param[in] attributes
4694  *   Pointer to flow attributes
4695  * @param[in] external
4696  *   Action belongs to flow rule created by request external to PMD.
4697  * @param[out] error
4698  *   Pointer to error structure.
4699  *
4700  * @return
4701  *   0 on success, a negative errno value otherwise and rte_errno is set.
4702  */
4703 static int
4704 flow_dv_validate_action_jump(struct rte_eth_dev *dev,
4705                              const struct mlx5_flow_tunnel *tunnel,
4706                              const struct rte_flow_action *action,
4707                              uint64_t action_flags,
4708                              const struct rte_flow_attr *attributes,
4709                              bool external, struct rte_flow_error *error)
4710 {
4711         uint32_t target_group, table;
4712         int ret = 0;
4713         struct flow_grp_info grp_info = {
4714                 .external = !!external,
4715                 .transfer = !!attributes->transfer,
4716                 .fdb_def_rule = 1,
4717                 .std_tbl_fix = 0
4718         };
4719         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
4720                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4721                 return rte_flow_error_set(error, EINVAL,
4722                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4723                                           "can't have 2 fate actions in"
4724                                           " same flow");
4725         if (action_flags & MLX5_FLOW_ACTION_METER)
4726                 return rte_flow_error_set(error, ENOTSUP,
4727                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4728                                           "jump with meter not support");
4729         if (!action->conf)
4730                 return rte_flow_error_set(error, EINVAL,
4731                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4732                                           NULL, "action configuration not set");
4733         target_group =
4734                 ((const struct rte_flow_action_jump *)action->conf)->group;
4735         ret = mlx5_flow_group_to_table(dev, tunnel, target_group, &table,
4736                                        &grp_info, error);
4737         if (ret)
4738                 return ret;
4739         if (attributes->group == target_group &&
4740             !(action_flags & (MLX5_FLOW_ACTION_TUNNEL_SET |
4741                               MLX5_FLOW_ACTION_TUNNEL_MATCH)))
4742                 return rte_flow_error_set(error, EINVAL,
4743                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4744                                           "target group must be other than"
4745                                           " the current flow group");
4746         return 0;
4747 }
4748
4749 /*
4750  * Validate the port_id action.
4751  *
4752  * @param[in] dev
4753  *   Pointer to rte_eth_dev structure.
4754  * @param[in] action_flags
4755  *   Bit-fields that holds the actions detected until now.
4756  * @param[in] action
4757  *   Port_id RTE action structure.
4758  * @param[in] attr
4759  *   Attributes of flow that includes this action.
4760  * @param[out] error
4761  *   Pointer to error structure.
4762  *
4763  * @return
4764  *   0 on success, a negative errno value otherwise and rte_errno is set.
4765  */
4766 static int
4767 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
4768                                 uint64_t action_flags,
4769                                 const struct rte_flow_action *action,
4770                                 const struct rte_flow_attr *attr,
4771                                 struct rte_flow_error *error)
4772 {
4773         const struct rte_flow_action_port_id *port_id;
4774         struct mlx5_priv *act_priv;
4775         struct mlx5_priv *dev_priv;
4776         uint16_t port;
4777
4778         if (!attr->transfer)
4779                 return rte_flow_error_set(error, ENOTSUP,
4780                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4781                                           NULL,
4782                                           "port id action is valid in transfer"
4783                                           " mode only");
4784         if (!action || !action->conf)
4785                 return rte_flow_error_set(error, ENOTSUP,
4786                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4787                                           NULL,
4788                                           "port id action parameters must be"
4789                                           " specified");
4790         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
4791                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4792                 return rte_flow_error_set(error, EINVAL,
4793                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4794                                           "can have only one fate actions in"
4795                                           " a flow");
4796         dev_priv = mlx5_dev_to_eswitch_info(dev);
4797         if (!dev_priv)
4798                 return rte_flow_error_set(error, rte_errno,
4799                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4800                                           NULL,
4801                                           "failed to obtain E-Switch info");
4802         port_id = action->conf;
4803         port = port_id->original ? dev->data->port_id : port_id->id;
4804         act_priv = mlx5_port_to_eswitch_info(port, false);
4805         if (!act_priv)
4806                 return rte_flow_error_set
4807                                 (error, rte_errno,
4808                                  RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
4809                                  "failed to obtain E-Switch port id for port");
4810         if (act_priv->domain_id != dev_priv->domain_id)
4811                 return rte_flow_error_set
4812                                 (error, EINVAL,
4813                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4814                                  "port does not belong to"
4815                                  " E-Switch being configured");
4816         return 0;
4817 }
4818
4819 /**
4820  * Get the maximum number of modify header actions.
4821  *
4822  * @param dev
4823  *   Pointer to rte_eth_dev structure.
4824  * @param flags
4825  *   Flags bits to check if root level.
4826  *
4827  * @return
4828  *   Max number of modify header actions device can support.
4829  */
4830 static inline unsigned int
4831 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev __rte_unused,
4832                               uint64_t flags)
4833 {
4834         /*
4835          * There's no way to directly query the max capacity from FW.
4836          * The maximal value on root table should be assumed to be supported.
4837          */
4838         if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
4839                 return MLX5_MAX_MODIFY_NUM;
4840         else
4841                 return MLX5_ROOT_TBL_MODIFY_NUM;
4842 }
4843
4844 /**
4845  * Validate the meter action.
4846  *
4847  * @param[in] dev
4848  *   Pointer to rte_eth_dev structure.
4849  * @param[in] action_flags
4850  *   Bit-fields that holds the actions detected until now.
4851  * @param[in] action
4852  *   Pointer to the meter action.
4853  * @param[in] attr
4854  *   Attributes of flow that includes this action.
4855  * @param[out] error
4856  *   Pointer to error structure.
4857  *
4858  * @return
4859  *   0 on success, a negative errno value otherwise and rte_ernno is set.
4860  */
4861 static int
4862 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
4863                                 uint64_t action_flags,
4864                                 const struct rte_flow_action *action,
4865                                 const struct rte_flow_attr *attr,
4866                                 struct rte_flow_error *error)
4867 {
4868         struct mlx5_priv *priv = dev->data->dev_private;
4869         const struct rte_flow_action_meter *am = action->conf;
4870         struct mlx5_flow_meter *fm;
4871
4872         if (!am)
4873                 return rte_flow_error_set(error, EINVAL,
4874                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4875                                           "meter action conf is NULL");
4876
4877         if (action_flags & MLX5_FLOW_ACTION_METER)
4878                 return rte_flow_error_set(error, ENOTSUP,
4879                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4880                                           "meter chaining not support");
4881         if (action_flags & MLX5_FLOW_ACTION_JUMP)
4882                 return rte_flow_error_set(error, ENOTSUP,
4883                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4884                                           "meter with jump not support");
4885         if (!priv->mtr_en)
4886                 return rte_flow_error_set(error, ENOTSUP,
4887                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4888                                           NULL,
4889                                           "meter action not supported");
4890         fm = mlx5_flow_meter_find(priv, am->mtr_id);
4891         if (!fm)
4892                 return rte_flow_error_set(error, EINVAL,
4893                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4894                                           "Meter not found");
4895         if (fm->ref_cnt && (!(fm->transfer == attr->transfer ||
4896               (!fm->ingress && !attr->ingress && attr->egress) ||
4897               (!fm->egress && !attr->egress && attr->ingress))))
4898                 return rte_flow_error_set(error, EINVAL,
4899                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4900                                           "Flow attributes are either invalid "
4901                                           "or have a conflict with current "
4902                                           "meter attributes");
4903         return 0;
4904 }
4905
4906 /**
4907  * Validate the age action.
4908  *
4909  * @param[in] action_flags
4910  *   Holds the actions detected until now.
4911  * @param[in] action
4912  *   Pointer to the age action.
4913  * @param[in] dev
4914  *   Pointer to the Ethernet device structure.
4915  * @param[out] error
4916  *   Pointer to error structure.
4917  *
4918  * @return
4919  *   0 on success, a negative errno value otherwise and rte_errno is set.
4920  */
4921 static int
4922 flow_dv_validate_action_age(uint64_t action_flags,
4923                             const struct rte_flow_action *action,
4924                             struct rte_eth_dev *dev,
4925                             struct rte_flow_error *error)
4926 {
4927         struct mlx5_priv *priv = dev->data->dev_private;
4928         const struct rte_flow_action_age *age = action->conf;
4929
4930         if (!priv->config.devx || (priv->sh->cmng.counter_fallback &&
4931             !priv->sh->aso_age_mng))
4932                 return rte_flow_error_set(error, ENOTSUP,
4933                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4934                                           NULL,
4935                                           "age action not supported");
4936         if (!(action->conf))
4937                 return rte_flow_error_set(error, EINVAL,
4938                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4939                                           "configuration cannot be null");
4940         if (!(age->timeout))
4941                 return rte_flow_error_set(error, EINVAL,
4942                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4943                                           "invalid timeout value 0");
4944         if (action_flags & MLX5_FLOW_ACTION_AGE)
4945                 return rte_flow_error_set(error, EINVAL,
4946                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4947                                           "duplicate age actions set");
4948         return 0;
4949 }
4950
4951 /**
4952  * Validate the modify-header IPv4 DSCP actions.
4953  *
4954  * @param[in] action_flags
4955  *   Holds the actions detected until now.
4956  * @param[in] action
4957  *   Pointer to the modify action.
4958  * @param[in] item_flags
4959  *   Holds the items detected.
4960  * @param[out] error
4961  *   Pointer to error structure.
4962  *
4963  * @return
4964  *   0 on success, a negative errno value otherwise and rte_errno is set.
4965  */
4966 static int
4967 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
4968                                          const struct rte_flow_action *action,
4969                                          const uint64_t item_flags,
4970                                          struct rte_flow_error *error)
4971 {
4972         int ret = 0;
4973
4974         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4975         if (!ret) {
4976                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
4977                         return rte_flow_error_set(error, EINVAL,
4978                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4979                                                   NULL,
4980                                                   "no ipv4 item in pattern");
4981         }
4982         return ret;
4983 }
4984
4985 /**
4986  * Validate the modify-header IPv6 DSCP actions.
4987  *
4988  * @param[in] action_flags
4989  *   Holds the actions detected until now.
4990  * @param[in] action
4991  *   Pointer to the modify action.
4992  * @param[in] item_flags
4993  *   Holds the items detected.
4994  * @param[out] error
4995  *   Pointer to error structure.
4996  *
4997  * @return
4998  *   0 on success, a negative errno value otherwise and rte_errno is set.
4999  */
5000 static int
5001 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
5002                                          const struct rte_flow_action *action,
5003                                          const uint64_t item_flags,
5004                                          struct rte_flow_error *error)
5005 {
5006         int ret = 0;
5007
5008         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
5009         if (!ret) {
5010                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
5011                         return rte_flow_error_set(error, EINVAL,
5012                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5013                                                   NULL,
5014                                                   "no ipv6 item in pattern");
5015         }
5016         return ret;
5017 }
5018
5019 /**
5020  * Match modify-header resource.
5021  *
5022  * @param list
5023  *   Pointer to the hash list.
5024  * @param entry
5025  *   Pointer to exist resource entry object.
5026  * @param key
5027  *   Key of the new entry.
5028  * @param ctx
5029  *   Pointer to new modify-header resource.
5030  *
5031  * @return
5032  *   0 on matching, non-zero otherwise.
5033  */
5034 int
5035 flow_dv_modify_match_cb(struct mlx5_hlist *list __rte_unused,
5036                         struct mlx5_hlist_entry *entry,
5037                         uint64_t key __rte_unused, void *cb_ctx)
5038 {
5039         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5040         struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5041         struct mlx5_flow_dv_modify_hdr_resource *resource =
5042                         container_of(entry, typeof(*resource), entry);
5043         uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
5044
5045         key_len += ref->actions_num * sizeof(ref->actions[0]);
5046         return ref->actions_num != resource->actions_num ||
5047                memcmp(&ref->ft_type, &resource->ft_type, key_len);
5048 }
5049
5050 struct mlx5_hlist_entry *
5051 flow_dv_modify_create_cb(struct mlx5_hlist *list, uint64_t key __rte_unused,
5052                          void *cb_ctx)
5053 {
5054         struct mlx5_dev_ctx_shared *sh = list->ctx;
5055         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5056         struct mlx5dv_dr_domain *ns;
5057         struct mlx5_flow_dv_modify_hdr_resource *entry;
5058         struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5059         int ret;
5060         uint32_t data_len = ref->actions_num * sizeof(ref->actions[0]);
5061         uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
5062
5063         entry = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*entry) + data_len, 0,
5064                             SOCKET_ID_ANY);
5065         if (!entry) {
5066                 rte_flow_error_set(ctx->error, ENOMEM,
5067                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5068                                    "cannot allocate resource memory");
5069                 return NULL;
5070         }
5071         rte_memcpy(&entry->ft_type,
5072                    RTE_PTR_ADD(ref, offsetof(typeof(*ref), ft_type)),
5073                    key_len + data_len);
5074         if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
5075                 ns = sh->fdb_domain;
5076         else if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
5077                 ns = sh->tx_domain;
5078         else
5079                 ns = sh->rx_domain;
5080         ret = mlx5_flow_os_create_flow_action_modify_header
5081                                         (sh->ctx, ns, entry,
5082                                          data_len, &entry->action);
5083         if (ret) {
5084                 mlx5_free(entry);
5085                 rte_flow_error_set(ctx->error, ENOMEM,
5086                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5087                                    NULL, "cannot create modification action");
5088                 return NULL;
5089         }
5090         return &entry->entry;
5091 }
5092
5093 /**
5094  * Validate the sample action.
5095  *
5096  * @param[in, out] action_flags
5097  *   Holds the actions detected until now.
5098  * @param[in] action
5099  *   Pointer to the sample action.
5100  * @param[in] dev
5101  *   Pointer to the Ethernet device structure.
5102  * @param[in] attr
5103  *   Attributes of flow that includes this action.
5104  * @param[in] item_flags
5105  *   Holds the items detected.
5106  * @param[in] rss
5107  *   Pointer to the RSS action.
5108  * @param[out] sample_rss
5109  *   Pointer to the RSS action in sample action list.
5110  * @param[out] count
5111  *   Pointer to the COUNT action in sample action list.
5112  * @param[out] fdb_mirror_limit
5113  *   Pointer to the FDB mirror limitation flag.
5114  * @param[out] error
5115  *   Pointer to error structure.
5116  *
5117  * @return
5118  *   0 on success, a negative errno value otherwise and rte_errno is set.
5119  */
5120 static int
5121 flow_dv_validate_action_sample(uint64_t *action_flags,
5122                                const struct rte_flow_action *action,
5123                                struct rte_eth_dev *dev,
5124                                const struct rte_flow_attr *attr,
5125                                uint64_t item_flags,
5126                                const struct rte_flow_action_rss *rss,
5127                                const struct rte_flow_action_rss **sample_rss,
5128                                const struct rte_flow_action_count **count,
5129                                int *fdb_mirror_limit,
5130                                struct rte_flow_error *error)
5131 {
5132         struct mlx5_priv *priv = dev->data->dev_private;
5133         struct mlx5_dev_config *dev_conf = &priv->config;
5134         const struct rte_flow_action_sample *sample = action->conf;
5135         const struct rte_flow_action *act;
5136         uint64_t sub_action_flags = 0;
5137         uint16_t queue_index = 0xFFFF;
5138         int actions_n = 0;
5139         int ret;
5140
5141         if (!sample)
5142                 return rte_flow_error_set(error, EINVAL,
5143                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
5144                                           "configuration cannot be NULL");
5145         if (sample->ratio == 0)
5146                 return rte_flow_error_set(error, EINVAL,
5147                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
5148                                           "ratio value starts from 1");
5149         if (!priv->config.devx || (sample->ratio > 0 && !priv->sampler_en))
5150                 return rte_flow_error_set(error, ENOTSUP,
5151                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5152                                           NULL,
5153                                           "sample action not supported");
5154         if (*action_flags & MLX5_FLOW_ACTION_SAMPLE)
5155                 return rte_flow_error_set(error, EINVAL,
5156                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5157                                           "Multiple sample actions not "
5158                                           "supported");
5159         if (*action_flags & MLX5_FLOW_ACTION_METER)
5160                 return rte_flow_error_set(error, EINVAL,
5161                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
5162                                           "wrong action order, meter should "
5163                                           "be after sample action");
5164         if (*action_flags & MLX5_FLOW_ACTION_JUMP)
5165                 return rte_flow_error_set(error, EINVAL,
5166                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
5167                                           "wrong action order, jump should "
5168                                           "be after sample action");
5169         act = sample->actions;
5170         for (; act->type != RTE_FLOW_ACTION_TYPE_END; act++) {
5171                 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
5172                         return rte_flow_error_set(error, ENOTSUP,
5173                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5174                                                   act, "too many actions");
5175                 switch (act->type) {
5176                 case RTE_FLOW_ACTION_TYPE_QUEUE:
5177                         ret = mlx5_flow_validate_action_queue(act,
5178                                                               sub_action_flags,
5179                                                               dev,
5180                                                               attr, error);
5181                         if (ret < 0)
5182                                 return ret;
5183                         queue_index = ((const struct rte_flow_action_queue *)
5184                                                         (act->conf))->index;
5185                         sub_action_flags |= MLX5_FLOW_ACTION_QUEUE;
5186                         ++actions_n;
5187                         break;
5188                 case RTE_FLOW_ACTION_TYPE_RSS:
5189                         *sample_rss = act->conf;
5190                         ret = mlx5_flow_validate_action_rss(act,
5191                                                             sub_action_flags,
5192                                                             dev, attr,
5193                                                             item_flags,
5194                                                             error);
5195                         if (ret < 0)
5196                                 return ret;
5197                         if (rss && *sample_rss &&
5198                             ((*sample_rss)->level != rss->level ||
5199                             (*sample_rss)->types != rss->types))
5200                                 return rte_flow_error_set(error, ENOTSUP,
5201                                         RTE_FLOW_ERROR_TYPE_ACTION,
5202                                         NULL,
5203                                         "Can't use the different RSS types "
5204                                         "or level in the same flow");
5205                         if (*sample_rss != NULL && (*sample_rss)->queue_num)
5206                                 queue_index = (*sample_rss)->queue[0];
5207                         sub_action_flags |= MLX5_FLOW_ACTION_RSS;
5208                         ++actions_n;
5209                         break;
5210                 case RTE_FLOW_ACTION_TYPE_MARK:
5211                         ret = flow_dv_validate_action_mark(dev, act,
5212                                                            sub_action_flags,
5213                                                            attr, error);
5214                         if (ret < 0)
5215                                 return ret;
5216                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY)
5217                                 sub_action_flags |= MLX5_FLOW_ACTION_MARK |
5218                                                 MLX5_FLOW_ACTION_MARK_EXT;
5219                         else
5220                                 sub_action_flags |= MLX5_FLOW_ACTION_MARK;
5221                         ++actions_n;
5222                         break;
5223                 case RTE_FLOW_ACTION_TYPE_COUNT:
5224                         ret = flow_dv_validate_action_count
5225                                 (dev, act,
5226                                  *action_flags | sub_action_flags,
5227                                  error);
5228                         if (ret < 0)
5229                                 return ret;
5230                         *count = act->conf;
5231                         sub_action_flags |= MLX5_FLOW_ACTION_COUNT;
5232                         *action_flags |= MLX5_FLOW_ACTION_COUNT;
5233                         ++actions_n;
5234                         break;
5235                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5236                         ret = flow_dv_validate_action_port_id(dev,
5237                                                               sub_action_flags,
5238                                                               act,
5239                                                               attr,
5240                                                               error);
5241                         if (ret)
5242                                 return ret;
5243                         sub_action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5244                         ++actions_n;
5245                         break;
5246                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5247                         ret = flow_dv_validate_action_raw_encap_decap
5248                                 (dev, NULL, act->conf, attr, &sub_action_flags,
5249                                  &actions_n, action, item_flags, error);
5250                         if (ret < 0)
5251                                 return ret;
5252                         ++actions_n;
5253                         break;
5254                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5255                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5256                         ret = flow_dv_validate_action_l2_encap(dev,
5257                                                                sub_action_flags,
5258                                                                act, attr,
5259                                                                error);
5260                         if (ret < 0)
5261                                 return ret;
5262                         sub_action_flags |= MLX5_FLOW_ACTION_ENCAP;
5263                         ++actions_n;
5264                         break;
5265                 default:
5266                         return rte_flow_error_set(error, ENOTSUP,
5267                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5268                                                   NULL,
5269                                                   "Doesn't support optional "
5270                                                   "action");
5271                 }
5272         }
5273         if (attr->ingress && !attr->transfer) {
5274                 if (!(sub_action_flags & (MLX5_FLOW_ACTION_QUEUE |
5275                                           MLX5_FLOW_ACTION_RSS)))
5276                         return rte_flow_error_set(error, EINVAL,
5277                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5278                                                   NULL,
5279                                                   "Ingress must has a dest "
5280                                                   "QUEUE for Sample");
5281         } else if (attr->egress && !attr->transfer) {
5282                 return rte_flow_error_set(error, ENOTSUP,
5283                                           RTE_FLOW_ERROR_TYPE_ACTION,
5284                                           NULL,
5285                                           "Sample Only support Ingress "
5286                                           "or E-Switch");
5287         } else if (sample->actions->type != RTE_FLOW_ACTION_TYPE_END) {
5288                 MLX5_ASSERT(attr->transfer);
5289                 if (sample->ratio > 1)
5290                         return rte_flow_error_set(error, ENOTSUP,
5291                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5292                                                   NULL,
5293                                                   "E-Switch doesn't support "
5294                                                   "any optional action "
5295                                                   "for sampling");
5296                 if (sub_action_flags & MLX5_FLOW_ACTION_QUEUE)
5297                         return rte_flow_error_set(error, ENOTSUP,
5298                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5299                                                   NULL,
5300                                                   "unsupported action QUEUE");
5301                 if (sub_action_flags & MLX5_FLOW_ACTION_RSS)
5302                         return rte_flow_error_set(error, ENOTSUP,
5303                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5304                                                   NULL,
5305                                                   "unsupported action QUEUE");
5306                 if (!(sub_action_flags & MLX5_FLOW_ACTION_PORT_ID))
5307                         return rte_flow_error_set(error, EINVAL,
5308                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5309                                                   NULL,
5310                                                   "E-Switch must has a dest "
5311                                                   "port for mirroring");
5312                 if (!priv->config.hca_attr.reg_c_preserve &&
5313                      priv->representor_id != -1)
5314                         *fdb_mirror_limit = 1;
5315         }
5316         /* Continue validation for Xcap actions.*/
5317         if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) &&
5318             (queue_index == 0xFFFF ||
5319              mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
5320                 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
5321                      MLX5_FLOW_XCAP_ACTIONS)
5322                         return rte_flow_error_set(error, ENOTSUP,
5323                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5324                                                   NULL, "encap and decap "
5325                                                   "combination aren't "
5326                                                   "supported");
5327                 if (!attr->transfer && attr->ingress && (sub_action_flags &
5328                                                         MLX5_FLOW_ACTION_ENCAP))
5329                         return rte_flow_error_set(error, ENOTSUP,
5330                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5331                                                   NULL, "encap is not supported"
5332                                                   " for ingress traffic");
5333         }
5334         return 0;
5335 }
5336
5337 /**
5338  * Find existing modify-header resource or create and register a new one.
5339  *
5340  * @param dev[in, out]
5341  *   Pointer to rte_eth_dev structure.
5342  * @param[in, out] resource
5343  *   Pointer to modify-header resource.
5344  * @parm[in, out] dev_flow
5345  *   Pointer to the dev_flow.
5346  * @param[out] error
5347  *   pointer to error structure.
5348  *
5349  * @return
5350  *   0 on success otherwise -errno and errno is set.
5351  */
5352 static int
5353 flow_dv_modify_hdr_resource_register
5354                         (struct rte_eth_dev *dev,
5355                          struct mlx5_flow_dv_modify_hdr_resource *resource,
5356                          struct mlx5_flow *dev_flow,
5357                          struct rte_flow_error *error)
5358 {
5359         struct mlx5_priv *priv = dev->data->dev_private;
5360         struct mlx5_dev_ctx_shared *sh = priv->sh;
5361         uint32_t key_len = sizeof(*resource) -
5362                            offsetof(typeof(*resource), ft_type) +
5363                            resource->actions_num * sizeof(resource->actions[0]);
5364         struct mlx5_hlist_entry *entry;
5365         struct mlx5_flow_cb_ctx ctx = {
5366                 .error = error,
5367                 .data = resource,
5368         };
5369         uint64_t key64;
5370
5371         resource->flags = dev_flow->dv.group ? 0 :
5372                           MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
5373         if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
5374                                     resource->flags))
5375                 return rte_flow_error_set(error, EOVERFLOW,
5376                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5377                                           "too many modify header items");
5378         key64 = __rte_raw_cksum(&resource->ft_type, key_len, 0);
5379         entry = mlx5_hlist_register(sh->modify_cmds, key64, &ctx);
5380         if (!entry)
5381                 return -rte_errno;
5382         resource = container_of(entry, typeof(*resource), entry);
5383         dev_flow->handle->dvh.modify_hdr = resource;
5384         return 0;
5385 }
5386
5387 /**
5388  * Get DV flow counter by index.
5389  *
5390  * @param[in] dev
5391  *   Pointer to the Ethernet device structure.
5392  * @param[in] idx
5393  *   mlx5 flow counter index in the container.
5394  * @param[out] ppool
5395  *   mlx5 flow counter pool in the container,
5396  *
5397  * @return
5398  *   Pointer to the counter, NULL otherwise.
5399  */
5400 static struct mlx5_flow_counter *
5401 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
5402                            uint32_t idx,
5403                            struct mlx5_flow_counter_pool **ppool)
5404 {
5405         struct mlx5_priv *priv = dev->data->dev_private;
5406         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5407         struct mlx5_flow_counter_pool *pool;
5408
5409         /* Decrease to original index and clear shared bit. */
5410         idx = (idx - 1) & (MLX5_CNT_SHARED_OFFSET - 1);
5411         MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cmng->n);
5412         pool = cmng->pools[idx / MLX5_COUNTERS_PER_POOL];
5413         MLX5_ASSERT(pool);
5414         if (ppool)
5415                 *ppool = pool;
5416         return MLX5_POOL_GET_CNT(pool, idx % MLX5_COUNTERS_PER_POOL);
5417 }
5418
5419 /**
5420  * Check the devx counter belongs to the pool.
5421  *
5422  * @param[in] pool
5423  *   Pointer to the counter pool.
5424  * @param[in] id
5425  *   The counter devx ID.
5426  *
5427  * @return
5428  *   True if counter belongs to the pool, false otherwise.
5429  */
5430 static bool
5431 flow_dv_is_counter_in_pool(struct mlx5_flow_counter_pool *pool, int id)
5432 {
5433         int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
5434                    MLX5_COUNTERS_PER_POOL;
5435
5436         if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
5437                 return true;
5438         return false;
5439 }
5440
5441 /**
5442  * Get a pool by devx counter ID.
5443  *
5444  * @param[in] cmng
5445  *   Pointer to the counter management.
5446  * @param[in] id
5447  *   The counter devx ID.
5448  *
5449  * @return
5450  *   The counter pool pointer if exists, NULL otherwise,
5451  */
5452 static struct mlx5_flow_counter_pool *
5453 flow_dv_find_pool_by_id(struct mlx5_flow_counter_mng *cmng, int id)
5454 {
5455         uint32_t i;
5456         struct mlx5_flow_counter_pool *pool = NULL;
5457
5458         rte_spinlock_lock(&cmng->pool_update_sl);
5459         /* Check last used pool. */
5460         if (cmng->last_pool_idx != POOL_IDX_INVALID &&
5461             flow_dv_is_counter_in_pool(cmng->pools[cmng->last_pool_idx], id)) {
5462                 pool = cmng->pools[cmng->last_pool_idx];
5463                 goto out;
5464         }
5465         /* ID out of range means no suitable pool in the container. */
5466         if (id > cmng->max_id || id < cmng->min_id)
5467                 goto out;
5468         /*
5469          * Find the pool from the end of the container, since mostly counter
5470          * ID is sequence increasing, and the last pool should be the needed
5471          * one.
5472          */
5473         i = cmng->n_valid;
5474         while (i--) {
5475                 struct mlx5_flow_counter_pool *pool_tmp = cmng->pools[i];
5476
5477                 if (flow_dv_is_counter_in_pool(pool_tmp, id)) {
5478                         pool = pool_tmp;
5479                         break;
5480                 }
5481         }
5482 out:
5483         rte_spinlock_unlock(&cmng->pool_update_sl);
5484         return pool;
5485 }
5486
5487 /**
5488  * Resize a counter container.
5489  *
5490  * @param[in] dev
5491  *   Pointer to the Ethernet device structure.
5492  *
5493  * @return
5494  *   0 on success, otherwise negative errno value and rte_errno is set.
5495  */
5496 static int
5497 flow_dv_container_resize(struct rte_eth_dev *dev)
5498 {
5499         struct mlx5_priv *priv = dev->data->dev_private;
5500         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5501         void *old_pools = cmng->pools;
5502         uint32_t resize = cmng->n + MLX5_CNT_CONTAINER_RESIZE;
5503         uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
5504         void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
5505
5506         if (!pools) {
5507                 rte_errno = ENOMEM;
5508                 return -ENOMEM;
5509         }
5510         if (old_pools)
5511                 memcpy(pools, old_pools, cmng->n *
5512                                        sizeof(struct mlx5_flow_counter_pool *));
5513         cmng->n = resize;
5514         cmng->pools = pools;
5515         if (old_pools)
5516                 mlx5_free(old_pools);
5517         return 0;
5518 }
5519
5520 /**
5521  * Query a devx flow counter.
5522  *
5523  * @param[in] dev
5524  *   Pointer to the Ethernet device structure.
5525  * @param[in] cnt
5526  *   Index to the flow counter.
5527  * @param[out] pkts
5528  *   The statistics value of packets.
5529  * @param[out] bytes
5530  *   The statistics value of bytes.
5531  *
5532  * @return
5533  *   0 on success, otherwise a negative errno value and rte_errno is set.
5534  */
5535 static inline int
5536 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
5537                      uint64_t *bytes)
5538 {
5539         struct mlx5_priv *priv = dev->data->dev_private;
5540         struct mlx5_flow_counter_pool *pool = NULL;
5541         struct mlx5_flow_counter *cnt;
5542         int offset;
5543
5544         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
5545         MLX5_ASSERT(pool);
5546         if (priv->sh->cmng.counter_fallback)
5547                 return mlx5_devx_cmd_flow_counter_query(cnt->dcs_when_active, 0,
5548                                         0, pkts, bytes, 0, NULL, NULL, 0);
5549         rte_spinlock_lock(&pool->sl);
5550         if (!pool->raw) {
5551                 *pkts = 0;
5552                 *bytes = 0;
5553         } else {
5554                 offset = MLX5_CNT_ARRAY_IDX(pool, cnt);
5555                 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
5556                 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
5557         }
5558         rte_spinlock_unlock(&pool->sl);
5559         return 0;
5560 }
5561
5562 /**
5563  * Create and initialize a new counter pool.
5564  *
5565  * @param[in] dev
5566  *   Pointer to the Ethernet device structure.
5567  * @param[out] dcs
5568  *   The devX counter handle.
5569  * @param[in] age
5570  *   Whether the pool is for counter that was allocated for aging.
5571  * @param[in/out] cont_cur
5572  *   Pointer to the container pointer, it will be update in pool resize.
5573  *
5574  * @return
5575  *   The pool container pointer on success, NULL otherwise and rte_errno is set.
5576  */
5577 static struct mlx5_flow_counter_pool *
5578 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
5579                     uint32_t age)
5580 {
5581         struct mlx5_priv *priv = dev->data->dev_private;
5582         struct mlx5_flow_counter_pool *pool;
5583         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5584         bool fallback = priv->sh->cmng.counter_fallback;
5585         uint32_t size = sizeof(*pool);
5586
5587         size += MLX5_COUNTERS_PER_POOL * MLX5_CNT_SIZE;
5588         size += (!age ? 0 : MLX5_COUNTERS_PER_POOL * MLX5_AGE_SIZE);
5589         pool = mlx5_malloc(MLX5_MEM_ZERO, size, 0, SOCKET_ID_ANY);
5590         if (!pool) {
5591                 rte_errno = ENOMEM;
5592                 return NULL;
5593         }
5594         pool->raw = NULL;
5595         pool->is_aged = !!age;
5596         pool->query_gen = 0;
5597         pool->min_dcs = dcs;
5598         rte_spinlock_init(&pool->sl);
5599         rte_spinlock_init(&pool->csl);
5600         TAILQ_INIT(&pool->counters[0]);
5601         TAILQ_INIT(&pool->counters[1]);
5602         pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
5603         rte_spinlock_lock(&cmng->pool_update_sl);
5604         pool->index = cmng->n_valid;
5605         if (pool->index == cmng->n && flow_dv_container_resize(dev)) {
5606                 mlx5_free(pool);
5607                 rte_spinlock_unlock(&cmng->pool_update_sl);
5608                 return NULL;
5609         }
5610         cmng->pools[pool->index] = pool;
5611         cmng->n_valid++;
5612         if (unlikely(fallback)) {
5613                 int base = RTE_ALIGN_FLOOR(dcs->id, MLX5_COUNTERS_PER_POOL);
5614
5615                 if (base < cmng->min_id)
5616                         cmng->min_id = base;
5617                 if (base > cmng->max_id)
5618                         cmng->max_id = base + MLX5_COUNTERS_PER_POOL - 1;
5619                 cmng->last_pool_idx = pool->index;
5620         }
5621         rte_spinlock_unlock(&cmng->pool_update_sl);
5622         return pool;
5623 }
5624
5625 /**
5626  * Prepare a new counter and/or a new counter pool.
5627  *
5628  * @param[in] dev
5629  *   Pointer to the Ethernet device structure.
5630  * @param[out] cnt_free
5631  *   Where to put the pointer of a new counter.
5632  * @param[in] age
5633  *   Whether the pool is for counter that was allocated for aging.
5634  *
5635  * @return
5636  *   The counter pool pointer and @p cnt_free is set on success,
5637  *   NULL otherwise and rte_errno is set.
5638  */
5639 static struct mlx5_flow_counter_pool *
5640 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
5641                              struct mlx5_flow_counter **cnt_free,
5642                              uint32_t age)
5643 {
5644         struct mlx5_priv *priv = dev->data->dev_private;
5645         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5646         struct mlx5_flow_counter_pool *pool;
5647         struct mlx5_counters tmp_tq;
5648         struct mlx5_devx_obj *dcs = NULL;
5649         struct mlx5_flow_counter *cnt;
5650         enum mlx5_counter_type cnt_type =
5651                         age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
5652         bool fallback = priv->sh->cmng.counter_fallback;
5653         uint32_t i;
5654
5655         if (fallback) {
5656                 /* bulk_bitmap must be 0 for single counter allocation. */
5657                 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
5658                 if (!dcs)
5659                         return NULL;
5660                 pool = flow_dv_find_pool_by_id(cmng, dcs->id);
5661                 if (!pool) {
5662                         pool = flow_dv_pool_create(dev, dcs, age);
5663                         if (!pool) {
5664                                 mlx5_devx_cmd_destroy(dcs);
5665                                 return NULL;
5666                         }
5667                 }
5668                 i = dcs->id % MLX5_COUNTERS_PER_POOL;
5669                 cnt = MLX5_POOL_GET_CNT(pool, i);
5670                 cnt->pool = pool;
5671                 cnt->dcs_when_free = dcs;
5672                 *cnt_free = cnt;
5673                 return pool;
5674         }
5675         dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
5676         if (!dcs) {
5677                 rte_errno = ENODATA;
5678                 return NULL;
5679         }
5680         pool = flow_dv_pool_create(dev, dcs, age);
5681         if (!pool) {
5682                 mlx5_devx_cmd_destroy(dcs);
5683                 return NULL;
5684         }
5685         TAILQ_INIT(&tmp_tq);
5686         for (i = 1; i < MLX5_COUNTERS_PER_POOL; ++i) {
5687                 cnt = MLX5_POOL_GET_CNT(pool, i);
5688                 cnt->pool = pool;
5689                 TAILQ_INSERT_HEAD(&tmp_tq, cnt, next);
5690         }
5691         rte_spinlock_lock(&cmng->csl[cnt_type]);
5692         TAILQ_CONCAT(&cmng->counters[cnt_type], &tmp_tq, next);
5693         rte_spinlock_unlock(&cmng->csl[cnt_type]);
5694         *cnt_free = MLX5_POOL_GET_CNT(pool, 0);
5695         (*cnt_free)->pool = pool;
5696         return pool;
5697 }
5698
5699 /**
5700  * Allocate a flow counter.
5701  *
5702  * @param[in] dev
5703  *   Pointer to the Ethernet device structure.
5704  * @param[in] age
5705  *   Whether the counter was allocated for aging.
5706  *
5707  * @return
5708  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
5709  */
5710 static uint32_t
5711 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t age)
5712 {
5713         struct mlx5_priv *priv = dev->data->dev_private;
5714         struct mlx5_flow_counter_pool *pool = NULL;
5715         struct mlx5_flow_counter *cnt_free = NULL;
5716         bool fallback = priv->sh->cmng.counter_fallback;
5717         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5718         enum mlx5_counter_type cnt_type =
5719                         age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
5720         uint32_t cnt_idx;
5721
5722         if (!priv->config.devx) {
5723                 rte_errno = ENOTSUP;
5724                 return 0;
5725         }
5726         /* Get free counters from container. */
5727         rte_spinlock_lock(&cmng->csl[cnt_type]);
5728         cnt_free = TAILQ_FIRST(&cmng->counters[cnt_type]);
5729         if (cnt_free)
5730                 TAILQ_REMOVE(&cmng->counters[cnt_type], cnt_free, next);
5731         rte_spinlock_unlock(&cmng->csl[cnt_type]);
5732         if (!cnt_free && !flow_dv_counter_pool_prepare(dev, &cnt_free, age))
5733                 goto err;
5734         pool = cnt_free->pool;
5735         if (fallback)
5736                 cnt_free->dcs_when_active = cnt_free->dcs_when_free;
5737         /* Create a DV counter action only in the first time usage. */
5738         if (!cnt_free->action) {
5739                 uint16_t offset;
5740                 struct mlx5_devx_obj *dcs;
5741                 int ret;
5742
5743                 if (!fallback) {
5744                         offset = MLX5_CNT_ARRAY_IDX(pool, cnt_free);
5745                         dcs = pool->min_dcs;
5746                 } else {
5747                         offset = 0;
5748                         dcs = cnt_free->dcs_when_free;
5749                 }
5750                 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, offset,
5751                                                             &cnt_free->action);
5752                 if (ret) {
5753                         rte_errno = errno;
5754                         goto err;
5755                 }
5756         }
5757         cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
5758                                 MLX5_CNT_ARRAY_IDX(pool, cnt_free));
5759         /* Update the counter reset values. */
5760         if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
5761                                  &cnt_free->bytes))
5762                 goto err;
5763         if (!fallback && !priv->sh->cmng.query_thread_on)
5764                 /* Start the asynchronous batch query by the host thread. */
5765                 mlx5_set_query_alarm(priv->sh);
5766         return cnt_idx;
5767 err:
5768         if (cnt_free) {
5769                 cnt_free->pool = pool;
5770                 if (fallback)
5771                         cnt_free->dcs_when_free = cnt_free->dcs_when_active;
5772                 rte_spinlock_lock(&cmng->csl[cnt_type]);
5773                 TAILQ_INSERT_TAIL(&cmng->counters[cnt_type], cnt_free, next);
5774                 rte_spinlock_unlock(&cmng->csl[cnt_type]);
5775         }
5776         return 0;
5777 }
5778
5779 /**
5780  * Allocate a shared flow counter.
5781  *
5782  * @param[in] ctx
5783  *   Pointer to the shared counter configuration.
5784  * @param[in] data
5785  *   Pointer to save the allocated counter index.
5786  *
5787  * @return
5788  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
5789  */
5790
5791 static int32_t
5792 flow_dv_counter_alloc_shared_cb(void *ctx, union mlx5_l3t_data *data)
5793 {
5794         struct mlx5_shared_counter_conf *conf = ctx;
5795         struct rte_eth_dev *dev = conf->dev;
5796         struct mlx5_flow_counter *cnt;
5797
5798         data->dword = flow_dv_counter_alloc(dev, 0);
5799         data->dword |= MLX5_CNT_SHARED_OFFSET;
5800         cnt = flow_dv_counter_get_by_idx(dev, data->dword, NULL);
5801         cnt->shared_info.id = conf->id;
5802         return 0;
5803 }
5804
5805 /**
5806  * Get a shared flow counter.
5807  *
5808  * @param[in] dev
5809  *   Pointer to the Ethernet device structure.
5810  * @param[in] id
5811  *   Counter identifier.
5812  *
5813  * @return
5814  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
5815  */
5816 static uint32_t
5817 flow_dv_counter_get_shared(struct rte_eth_dev *dev, uint32_t id)
5818 {
5819         struct mlx5_priv *priv = dev->data->dev_private;
5820         struct mlx5_shared_counter_conf conf = {
5821                 .dev = dev,
5822                 .id = id,
5823         };
5824         union mlx5_l3t_data data = {
5825                 .dword = 0,
5826         };
5827
5828         mlx5_l3t_prepare_entry(priv->sh->cnt_id_tbl, id, &data,
5829                                flow_dv_counter_alloc_shared_cb, &conf);
5830         return data.dword;
5831 }
5832
5833 /**
5834  * Get age param from counter index.
5835  *
5836  * @param[in] dev
5837  *   Pointer to the Ethernet device structure.
5838  * @param[in] counter
5839  *   Index to the counter handler.
5840  *
5841  * @return
5842  *   The aging parameter specified for the counter index.
5843  */
5844 static struct mlx5_age_param*
5845 flow_dv_counter_idx_get_age(struct rte_eth_dev *dev,
5846                                 uint32_t counter)
5847 {
5848         struct mlx5_flow_counter *cnt;
5849         struct mlx5_flow_counter_pool *pool = NULL;
5850
5851         flow_dv_counter_get_by_idx(dev, counter, &pool);
5852         counter = (counter - 1) % MLX5_COUNTERS_PER_POOL;
5853         cnt = MLX5_POOL_GET_CNT(pool, counter);
5854         return MLX5_CNT_TO_AGE(cnt);
5855 }
5856
5857 /**
5858  * Remove a flow counter from aged counter list.
5859  *
5860  * @param[in] dev
5861  *   Pointer to the Ethernet device structure.
5862  * @param[in] counter
5863  *   Index to the counter handler.
5864  * @param[in] cnt
5865  *   Pointer to the counter handler.
5866  */
5867 static void
5868 flow_dv_counter_remove_from_age(struct rte_eth_dev *dev,
5869                                 uint32_t counter, struct mlx5_flow_counter *cnt)
5870 {
5871         struct mlx5_age_info *age_info;
5872         struct mlx5_age_param *age_param;
5873         struct mlx5_priv *priv = dev->data->dev_private;
5874         uint16_t expected = AGE_CANDIDATE;
5875
5876         age_info = GET_PORT_AGE_INFO(priv);
5877         age_param = flow_dv_counter_idx_get_age(dev, counter);
5878         if (!__atomic_compare_exchange_n(&age_param->state, &expected,
5879                                          AGE_FREE, false, __ATOMIC_RELAXED,
5880                                          __ATOMIC_RELAXED)) {
5881                 /**
5882                  * We need the lock even it is age timeout,
5883                  * since counter may still in process.
5884                  */
5885                 rte_spinlock_lock(&age_info->aged_sl);
5886                 TAILQ_REMOVE(&age_info->aged_counters, cnt, next);
5887                 rte_spinlock_unlock(&age_info->aged_sl);
5888                 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
5889         }
5890 }
5891
5892 /**
5893  * Release a flow counter.
5894  *
5895  * @param[in] dev
5896  *   Pointer to the Ethernet device structure.
5897  * @param[in] counter
5898  *   Index to the counter handler.
5899  */
5900 static void
5901 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t counter)
5902 {
5903         struct mlx5_priv *priv = dev->data->dev_private;
5904         struct mlx5_flow_counter_pool *pool = NULL;
5905         struct mlx5_flow_counter *cnt;
5906         enum mlx5_counter_type cnt_type;
5907
5908         if (!counter)
5909                 return;
5910         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
5911         MLX5_ASSERT(pool);
5912         if (IS_SHARED_CNT(counter) &&
5913             mlx5_l3t_clear_entry(priv->sh->cnt_id_tbl, cnt->shared_info.id))
5914                 return;
5915         if (pool->is_aged)
5916                 flow_dv_counter_remove_from_age(dev, counter, cnt);
5917         cnt->pool = pool;
5918         /*
5919          * Put the counter back to list to be updated in none fallback mode.
5920          * Currently, we are using two list alternately, while one is in query,
5921          * add the freed counter to the other list based on the pool query_gen
5922          * value. After query finishes, add counter the list to the global
5923          * container counter list. The list changes while query starts. In
5924          * this case, lock will not be needed as query callback and release
5925          * function both operate with the different list.
5926          *
5927          */
5928         if (!priv->sh->cmng.counter_fallback) {
5929                 rte_spinlock_lock(&pool->csl);
5930                 TAILQ_INSERT_TAIL(&pool->counters[pool->query_gen], cnt, next);
5931                 rte_spinlock_unlock(&pool->csl);
5932         } else {
5933                 cnt->dcs_when_free = cnt->dcs_when_active;
5934                 cnt_type = pool->is_aged ? MLX5_COUNTER_TYPE_AGE :
5935                                            MLX5_COUNTER_TYPE_ORIGIN;
5936                 rte_spinlock_lock(&priv->sh->cmng.csl[cnt_type]);
5937                 TAILQ_INSERT_TAIL(&priv->sh->cmng.counters[cnt_type],
5938                                   cnt, next);
5939                 rte_spinlock_unlock(&priv->sh->cmng.csl[cnt_type]);
5940         }
5941 }
5942
5943 /**
5944  * Verify the @p attributes will be correctly understood by the NIC and store
5945  * them in the @p flow if everything is correct.
5946  *
5947  * @param[in] dev
5948  *   Pointer to dev struct.
5949  * @param[in] attributes
5950  *   Pointer to flow attributes
5951  * @param[in] external
5952  *   This flow rule is created by request external to PMD.
5953  * @param[out] error
5954  *   Pointer to error structure.
5955  *
5956  * @return
5957  *   - 0 on success and non root table.
5958  *   - 1 on success and root table.
5959  *   - a negative errno value otherwise and rte_errno is set.
5960  */
5961 static int
5962 flow_dv_validate_attributes(struct rte_eth_dev *dev,
5963                             const struct mlx5_flow_tunnel *tunnel,
5964                             const struct rte_flow_attr *attributes,
5965                             const struct flow_grp_info *grp_info,
5966                             struct rte_flow_error *error)
5967 {
5968         struct mlx5_priv *priv = dev->data->dev_private;
5969         uint32_t lowest_priority = mlx5_get_lowest_priority(dev, attributes);
5970         int ret = 0;
5971
5972 #ifndef HAVE_MLX5DV_DR
5973         RTE_SET_USED(tunnel);
5974         RTE_SET_USED(grp_info);
5975         if (attributes->group)
5976                 return rte_flow_error_set(error, ENOTSUP,
5977                                           RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
5978                                           NULL,
5979                                           "groups are not supported");
5980 #else
5981         uint32_t table = 0;
5982
5983         ret = mlx5_flow_group_to_table(dev, tunnel, attributes->group, &table,
5984                                        grp_info, error);
5985         if (ret)
5986                 return ret;
5987         if (!table)
5988                 ret = MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
5989 #endif
5990         if (attributes->priority != MLX5_FLOW_LOWEST_PRIO_INDICATOR &&
5991             attributes->priority > lowest_priority)
5992                 return rte_flow_error_set(error, ENOTSUP,
5993                                           RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
5994                                           NULL,
5995                                           "priority out of range");
5996         if (attributes->transfer) {
5997                 if (!priv->config.dv_esw_en)
5998                         return rte_flow_error_set
5999                                 (error, ENOTSUP,
6000                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6001                                  "E-Switch dr is not supported");
6002                 if (!(priv->representor || priv->master))
6003                         return rte_flow_error_set
6004                                 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6005                                  NULL, "E-Switch configuration can only be"
6006                                  " done by a master or a representor device");
6007                 if (attributes->egress)
6008                         return rte_flow_error_set
6009                                 (error, ENOTSUP,
6010                                  RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
6011                                  "egress is not supported");
6012         }
6013         if (!(attributes->egress ^ attributes->ingress))
6014                 return rte_flow_error_set(error, ENOTSUP,
6015                                           RTE_FLOW_ERROR_TYPE_ATTR, NULL,
6016                                           "must specify exactly one of "
6017                                           "ingress or egress");
6018         return ret;
6019 }
6020
6021 /**
6022  * Internal validation function. For validating both actions and items.
6023  *
6024  * @param[in] dev
6025  *   Pointer to the rte_eth_dev structure.
6026  * @param[in] attr
6027  *   Pointer to the flow attributes.
6028  * @param[in] items
6029  *   Pointer to the list of items.
6030  * @param[in] actions
6031  *   Pointer to the list of actions.
6032  * @param[in] external
6033  *   This flow rule is created by request external to PMD.
6034  * @param[in] hairpin
6035  *   Number of hairpin TX actions, 0 means classic flow.
6036  * @param[out] error
6037  *   Pointer to the error structure.
6038  *
6039  * @return
6040  *   0 on success, a negative errno value otherwise and rte_errno is set.
6041  */
6042 static int
6043 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
6044                  const struct rte_flow_item items[],
6045                  const struct rte_flow_action actions[],
6046                  bool external, int hairpin, struct rte_flow_error *error)
6047 {
6048         int ret;
6049         uint64_t action_flags = 0;
6050         uint64_t item_flags = 0;
6051         uint64_t last_item = 0;
6052         uint8_t next_protocol = 0xff;
6053         uint16_t ether_type = 0;
6054         int actions_n = 0;
6055         uint8_t item_ipv6_proto = 0;
6056         int fdb_mirror_limit = 0;
6057         int modify_after_mirror = 0;
6058         const struct rte_flow_item *geneve_item = NULL;
6059         const struct rte_flow_item *gre_item = NULL;
6060         const struct rte_flow_item *gtp_item = NULL;
6061         const struct rte_flow_action_raw_decap *decap;
6062         const struct rte_flow_action_raw_encap *encap;
6063         const struct rte_flow_action_rss *rss = NULL;
6064         const struct rte_flow_action_rss *sample_rss = NULL;
6065         const struct rte_flow_action_count *count = NULL;
6066         const struct rte_flow_action_count *sample_count = NULL;
6067         const struct rte_flow_item_tcp nic_tcp_mask = {
6068                 .hdr = {
6069                         .tcp_flags = 0xFF,
6070                         .src_port = RTE_BE16(UINT16_MAX),
6071                         .dst_port = RTE_BE16(UINT16_MAX),
6072                 }
6073         };
6074         const struct rte_flow_item_ipv6 nic_ipv6_mask = {
6075                 .hdr = {
6076                         .src_addr =
6077                         "\xff\xff\xff\xff\xff\xff\xff\xff"
6078                         "\xff\xff\xff\xff\xff\xff\xff\xff",
6079                         .dst_addr =
6080                         "\xff\xff\xff\xff\xff\xff\xff\xff"
6081                         "\xff\xff\xff\xff\xff\xff\xff\xff",
6082                         .vtc_flow = RTE_BE32(0xffffffff),
6083                         .proto = 0xff,
6084                         .hop_limits = 0xff,
6085                 },
6086                 .has_frag_ext = 1,
6087         };
6088         const struct rte_flow_item_ecpri nic_ecpri_mask = {
6089                 .hdr = {
6090                         .common = {
6091                                 .u32 =
6092                                 RTE_BE32(((const struct rte_ecpri_common_hdr) {
6093                                         .type = 0xFF,
6094                                         }).u32),
6095                         },
6096                         .dummy[0] = 0xffffffff,
6097                 },
6098         };
6099         struct mlx5_priv *priv = dev->data->dev_private;
6100         struct mlx5_dev_config *dev_conf = &priv->config;
6101         uint16_t queue_index = 0xFFFF;
6102         const struct rte_flow_item_vlan *vlan_m = NULL;
6103         uint32_t rw_act_num = 0;
6104         uint64_t is_root;
6105         const struct mlx5_flow_tunnel *tunnel;
6106         struct flow_grp_info grp_info = {
6107                 .external = !!external,
6108                 .transfer = !!attr->transfer,
6109                 .fdb_def_rule = !!priv->fdb_def_rule,
6110         };
6111         const struct rte_eth_hairpin_conf *conf;
6112
6113         if (items == NULL)
6114                 return -1;
6115         if (is_flow_tunnel_match_rule(dev, attr, items, actions)) {
6116                 tunnel = flow_items_to_tunnel(items);
6117                 action_flags |= MLX5_FLOW_ACTION_TUNNEL_MATCH |
6118                                 MLX5_FLOW_ACTION_DECAP;
6119         } else if (is_flow_tunnel_steer_rule(dev, attr, items, actions)) {
6120                 tunnel = flow_actions_to_tunnel(actions);
6121                 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
6122         } else {
6123                 tunnel = NULL;
6124         }
6125         if (tunnel && priv->representor)
6126                 return rte_flow_error_set(error, ENOTSUP,
6127                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6128                                           "decap not supported "
6129                                           "for VF representor");
6130         grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
6131                                 (dev, tunnel, attr, items, actions);
6132         ret = flow_dv_validate_attributes(dev, tunnel, attr, &grp_info, error);
6133         if (ret < 0)
6134                 return ret;
6135         is_root = (uint64_t)ret;
6136         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
6137                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
6138                 int type = items->type;
6139
6140                 if (!mlx5_flow_os_item_supported(type))
6141                         return rte_flow_error_set(error, ENOTSUP,
6142                                                   RTE_FLOW_ERROR_TYPE_ITEM,
6143                                                   NULL, "item not supported");
6144                 switch (type) {
6145                 case MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL:
6146                         if (items[0].type != (typeof(items[0].type))
6147                                                 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL)
6148                                 return rte_flow_error_set
6149                                                 (error, EINVAL,
6150                                                 RTE_FLOW_ERROR_TYPE_ITEM,
6151                                                 NULL, "MLX5 private items "
6152                                                 "must be the first");
6153                         break;
6154                 case RTE_FLOW_ITEM_TYPE_VOID:
6155                         break;
6156                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
6157                         ret = flow_dv_validate_item_port_id
6158                                         (dev, items, attr, item_flags, error);
6159                         if (ret < 0)
6160                                 return ret;
6161                         last_item = MLX5_FLOW_ITEM_PORT_ID;
6162                         break;
6163                 case RTE_FLOW_ITEM_TYPE_ETH:
6164                         ret = mlx5_flow_validate_item_eth(items, item_flags,
6165                                                           true, error);
6166                         if (ret < 0)
6167                                 return ret;
6168                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
6169                                              MLX5_FLOW_LAYER_OUTER_L2;
6170                         if (items->mask != NULL && items->spec != NULL) {
6171                                 ether_type =
6172                                         ((const struct rte_flow_item_eth *)
6173                                          items->spec)->type;
6174                                 ether_type &=
6175                                         ((const struct rte_flow_item_eth *)
6176                                          items->mask)->type;
6177                                 ether_type = rte_be_to_cpu_16(ether_type);
6178                         } else {
6179                                 ether_type = 0;
6180                         }
6181                         break;
6182                 case RTE_FLOW_ITEM_TYPE_VLAN:
6183                         ret = flow_dv_validate_item_vlan(items, item_flags,
6184                                                          dev, error);
6185                         if (ret < 0)
6186                                 return ret;
6187                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
6188                                              MLX5_FLOW_LAYER_OUTER_VLAN;
6189                         if (items->mask != NULL && items->spec != NULL) {
6190                                 ether_type =
6191                                         ((const struct rte_flow_item_vlan *)
6192                                          items->spec)->inner_type;
6193                                 ether_type &=
6194                                         ((const struct rte_flow_item_vlan *)
6195                                          items->mask)->inner_type;
6196                                 ether_type = rte_be_to_cpu_16(ether_type);
6197                         } else {
6198                                 ether_type = 0;
6199                         }
6200                         /* Store outer VLAN mask for of_push_vlan action. */
6201                         if (!tunnel)
6202                                 vlan_m = items->mask;
6203                         break;
6204                 case RTE_FLOW_ITEM_TYPE_IPV4:
6205                         mlx5_flow_tunnel_ip_check(items, next_protocol,
6206                                                   &item_flags, &tunnel);
6207                         ret = flow_dv_validate_item_ipv4(items, item_flags,
6208                                                          last_item, ether_type,
6209                                                          error);
6210                         if (ret < 0)
6211                                 return ret;
6212                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
6213                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
6214                         if (items->mask != NULL &&
6215                             ((const struct rte_flow_item_ipv4 *)
6216                              items->mask)->hdr.next_proto_id) {
6217                                 next_protocol =
6218                                         ((const struct rte_flow_item_ipv4 *)
6219                                          (items->spec))->hdr.next_proto_id;
6220                                 next_protocol &=
6221                                         ((const struct rte_flow_item_ipv4 *)
6222                                          (items->mask))->hdr.next_proto_id;
6223                         } else {
6224                                 /* Reset for inner layer. */
6225                                 next_protocol = 0xff;
6226                         }
6227                         break;
6228                 case RTE_FLOW_ITEM_TYPE_IPV6:
6229                         mlx5_flow_tunnel_ip_check(items, next_protocol,
6230                                                   &item_flags, &tunnel);
6231                         ret = mlx5_flow_validate_item_ipv6(items, item_flags,
6232                                                            last_item,
6233                                                            ether_type,
6234                                                            &nic_ipv6_mask,
6235                                                            error);
6236                         if (ret < 0)
6237                                 return ret;
6238                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
6239                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
6240                         if (items->mask != NULL &&
6241                             ((const struct rte_flow_item_ipv6 *)
6242                              items->mask)->hdr.proto) {
6243                                 item_ipv6_proto =
6244                                         ((const struct rte_flow_item_ipv6 *)
6245                                          items->spec)->hdr.proto;
6246                                 next_protocol =
6247                                         ((const struct rte_flow_item_ipv6 *)
6248                                          items->spec)->hdr.proto;
6249                                 next_protocol &=
6250                                         ((const struct rte_flow_item_ipv6 *)
6251                                          items->mask)->hdr.proto;
6252                         } else {
6253                                 /* Reset for inner layer. */
6254                                 next_protocol = 0xff;
6255                         }
6256                         break;
6257                 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
6258                         ret = flow_dv_validate_item_ipv6_frag_ext(items,
6259                                                                   item_flags,
6260                                                                   error);
6261                         if (ret < 0)
6262                                 return ret;
6263                         last_item = tunnel ?
6264                                         MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
6265                                         MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
6266                         if (items->mask != NULL &&
6267                             ((const struct rte_flow_item_ipv6_frag_ext *)
6268                              items->mask)->hdr.next_header) {
6269                                 next_protocol =
6270                                 ((const struct rte_flow_item_ipv6_frag_ext *)
6271                                  items->spec)->hdr.next_header;
6272                                 next_protocol &=
6273                                 ((const struct rte_flow_item_ipv6_frag_ext *)
6274                                  items->mask)->hdr.next_header;
6275                         } else {
6276                                 /* Reset for inner layer. */
6277                                 next_protocol = 0xff;
6278                         }
6279                         break;
6280                 case RTE_FLOW_ITEM_TYPE_TCP:
6281                         ret = mlx5_flow_validate_item_tcp
6282                                                 (items, item_flags,
6283                                                  next_protocol,
6284                                                  &nic_tcp_mask,
6285                                                  error);
6286                         if (ret < 0)
6287                                 return ret;
6288                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
6289                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
6290                         break;
6291                 case RTE_FLOW_ITEM_TYPE_UDP:
6292                         ret = mlx5_flow_validate_item_udp(items, item_flags,
6293                                                           next_protocol,
6294                                                           error);
6295                         if (ret < 0)
6296                                 return ret;
6297                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
6298                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
6299                         break;
6300                 case RTE_FLOW_ITEM_TYPE_GRE:
6301                         ret = mlx5_flow_validate_item_gre(items, item_flags,
6302                                                           next_protocol, error);
6303                         if (ret < 0)
6304                                 return ret;
6305                         gre_item = items;
6306                         last_item = MLX5_FLOW_LAYER_GRE;
6307                         break;
6308                 case RTE_FLOW_ITEM_TYPE_NVGRE:
6309                         ret = mlx5_flow_validate_item_nvgre(items, item_flags,
6310                                                             next_protocol,
6311                                                             error);
6312                         if (ret < 0)
6313                                 return ret;
6314                         last_item = MLX5_FLOW_LAYER_NVGRE;
6315                         break;
6316                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
6317                         ret = mlx5_flow_validate_item_gre_key
6318                                 (items, item_flags, gre_item, error);
6319                         if (ret < 0)
6320                                 return ret;
6321                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
6322                         break;
6323                 case RTE_FLOW_ITEM_TYPE_VXLAN:
6324                         ret = mlx5_flow_validate_item_vxlan(items, item_flags,
6325                                                             error);
6326                         if (ret < 0)
6327                                 return ret;
6328                         last_item = MLX5_FLOW_LAYER_VXLAN;
6329                         break;
6330                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
6331                         ret = mlx5_flow_validate_item_vxlan_gpe(items,
6332                                                                 item_flags, dev,
6333                                                                 error);
6334                         if (ret < 0)
6335                                 return ret;
6336                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
6337                         break;
6338                 case RTE_FLOW_ITEM_TYPE_GENEVE:
6339                         ret = mlx5_flow_validate_item_geneve(items,
6340                                                              item_flags, dev,
6341                                                              error);
6342                         if (ret < 0)
6343                                 return ret;
6344                         geneve_item = items;
6345                         last_item = MLX5_FLOW_LAYER_GENEVE;
6346                         break;
6347                 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
6348                         ret = mlx5_flow_validate_item_geneve_opt(items,
6349                                                                  last_item,
6350                                                                  geneve_item,
6351                                                                  dev,
6352                                                                  error);
6353                         if (ret < 0)
6354                                 return ret;
6355                         last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
6356                         break;
6357                 case RTE_FLOW_ITEM_TYPE_MPLS:
6358                         ret = mlx5_flow_validate_item_mpls(dev, items,
6359                                                            item_flags,
6360                                                            last_item, error);
6361                         if (ret < 0)
6362                                 return ret;
6363                         last_item = MLX5_FLOW_LAYER_MPLS;
6364                         break;
6365
6366                 case RTE_FLOW_ITEM_TYPE_MARK:
6367                         ret = flow_dv_validate_item_mark(dev, items, attr,
6368                                                          error);
6369                         if (ret < 0)
6370                                 return ret;
6371                         last_item = MLX5_FLOW_ITEM_MARK;
6372                         break;
6373                 case RTE_FLOW_ITEM_TYPE_META:
6374                         ret = flow_dv_validate_item_meta(dev, items, attr,
6375                                                          error);
6376                         if (ret < 0)
6377                                 return ret;
6378                         last_item = MLX5_FLOW_ITEM_METADATA;
6379                         break;
6380                 case RTE_FLOW_ITEM_TYPE_ICMP:
6381                         ret = mlx5_flow_validate_item_icmp(items, item_flags,
6382                                                            next_protocol,
6383                                                            error);
6384                         if (ret < 0)
6385                                 return ret;
6386                         last_item = MLX5_FLOW_LAYER_ICMP;
6387                         break;
6388                 case RTE_FLOW_ITEM_TYPE_ICMP6:
6389                         ret = mlx5_flow_validate_item_icmp6(items, item_flags,
6390                                                             next_protocol,
6391                                                             error);
6392                         if (ret < 0)
6393                                 return ret;
6394                         item_ipv6_proto = IPPROTO_ICMPV6;
6395                         last_item = MLX5_FLOW_LAYER_ICMP6;
6396                         break;
6397                 case RTE_FLOW_ITEM_TYPE_TAG:
6398                         ret = flow_dv_validate_item_tag(dev, items,
6399                                                         attr, error);
6400                         if (ret < 0)
6401                                 return ret;
6402                         last_item = MLX5_FLOW_ITEM_TAG;
6403                         break;
6404                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
6405                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
6406                         break;
6407                 case RTE_FLOW_ITEM_TYPE_GTP:
6408                         ret = flow_dv_validate_item_gtp(dev, items, item_flags,
6409                                                         error);
6410                         if (ret < 0)
6411                                 return ret;
6412                         gtp_item = items;
6413                         last_item = MLX5_FLOW_LAYER_GTP;
6414                         break;
6415                 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
6416                         ret = flow_dv_validate_item_gtp_psc(items, last_item,
6417                                                             gtp_item, attr,
6418                                                             error);
6419                         if (ret < 0)
6420                                 return ret;
6421                         last_item = MLX5_FLOW_LAYER_GTP_PSC;
6422                         break;
6423                 case RTE_FLOW_ITEM_TYPE_ECPRI:
6424                         /* Capacity will be checked in the translate stage. */
6425                         ret = mlx5_flow_validate_item_ecpri(items, item_flags,
6426                                                             last_item,
6427                                                             ether_type,
6428                                                             &nic_ecpri_mask,
6429                                                             error);
6430                         if (ret < 0)
6431                                 return ret;
6432                         last_item = MLX5_FLOW_LAYER_ECPRI;
6433                         break;
6434                 default:
6435                         return rte_flow_error_set(error, ENOTSUP,
6436                                                   RTE_FLOW_ERROR_TYPE_ITEM,
6437                                                   NULL, "item not supported");
6438                 }
6439                 item_flags |= last_item;
6440         }
6441         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
6442                 int type = actions->type;
6443
6444                 if (!mlx5_flow_os_action_supported(type))
6445                         return rte_flow_error_set(error, ENOTSUP,
6446                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6447                                                   actions,
6448                                                   "action not supported");
6449                 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
6450                         return rte_flow_error_set(error, ENOTSUP,
6451                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6452                                                   actions, "too many actions");
6453                 switch (type) {
6454                 case RTE_FLOW_ACTION_TYPE_VOID:
6455                         break;
6456                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
6457                         ret = flow_dv_validate_action_port_id(dev,
6458                                                               action_flags,
6459                                                               actions,
6460                                                               attr,
6461                                                               error);
6462                         if (ret)
6463                                 return ret;
6464                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
6465                         ++actions_n;
6466                         break;
6467                 case RTE_FLOW_ACTION_TYPE_FLAG:
6468                         ret = flow_dv_validate_action_flag(dev, action_flags,
6469                                                            attr, error);
6470                         if (ret < 0)
6471                                 return ret;
6472                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
6473                                 /* Count all modify-header actions as one. */
6474                                 if (!(action_flags &
6475                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
6476                                         ++actions_n;
6477                                 action_flags |= MLX5_FLOW_ACTION_FLAG |
6478                                                 MLX5_FLOW_ACTION_MARK_EXT;
6479                                 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6480                                         modify_after_mirror = 1;
6481
6482                         } else {
6483                                 action_flags |= MLX5_FLOW_ACTION_FLAG;
6484                                 ++actions_n;
6485                         }
6486                         rw_act_num += MLX5_ACT_NUM_SET_MARK;
6487                         break;
6488                 case RTE_FLOW_ACTION_TYPE_MARK:
6489                         ret = flow_dv_validate_action_mark(dev, actions,
6490                                                            action_flags,
6491                                                            attr, error);
6492                         if (ret < 0)
6493                                 return ret;
6494                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
6495                                 /* Count all modify-header actions as one. */
6496                                 if (!(action_flags &
6497                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
6498                                         ++actions_n;
6499                                 action_flags |= MLX5_FLOW_ACTION_MARK |
6500                                                 MLX5_FLOW_ACTION_MARK_EXT;
6501                                 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6502                                         modify_after_mirror = 1;
6503                         } else {
6504                                 action_flags |= MLX5_FLOW_ACTION_MARK;
6505                                 ++actions_n;
6506                         }
6507                         rw_act_num += MLX5_ACT_NUM_SET_MARK;
6508                         break;
6509                 case RTE_FLOW_ACTION_TYPE_SET_META:
6510                         ret = flow_dv_validate_action_set_meta(dev, actions,
6511                                                                action_flags,
6512                                                                attr, error);
6513                         if (ret < 0)
6514                                 return ret;
6515                         /* Count all modify-header actions as one action. */
6516                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6517                                 ++actions_n;
6518                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6519                                 modify_after_mirror = 1;
6520                         action_flags |= MLX5_FLOW_ACTION_SET_META;
6521                         rw_act_num += MLX5_ACT_NUM_SET_META;
6522                         break;
6523                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
6524                         ret = flow_dv_validate_action_set_tag(dev, actions,
6525                                                               action_flags,
6526                                                               attr, error);
6527                         if (ret < 0)
6528                                 return ret;
6529                         /* Count all modify-header actions as one action. */
6530                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6531                                 ++actions_n;
6532                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6533                                 modify_after_mirror = 1;
6534                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
6535                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
6536                         break;
6537                 case RTE_FLOW_ACTION_TYPE_DROP:
6538                         ret = mlx5_flow_validate_action_drop(action_flags,
6539                                                              attr, error);
6540                         if (ret < 0)
6541                                 return ret;
6542                         action_flags |= MLX5_FLOW_ACTION_DROP;
6543                         ++actions_n;
6544                         break;
6545                 case RTE_FLOW_ACTION_TYPE_QUEUE:
6546                         ret = mlx5_flow_validate_action_queue(actions,
6547                                                               action_flags, dev,
6548                                                               attr, error);
6549                         if (ret < 0)
6550                                 return ret;
6551                         queue_index = ((const struct rte_flow_action_queue *)
6552                                                         (actions->conf))->index;
6553                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
6554                         ++actions_n;
6555                         break;
6556                 case RTE_FLOW_ACTION_TYPE_RSS:
6557                         rss = actions->conf;
6558                         ret = mlx5_flow_validate_action_rss(actions,
6559                                                             action_flags, dev,
6560                                                             attr, item_flags,
6561                                                             error);
6562                         if (ret < 0)
6563                                 return ret;
6564                         if (rss && sample_rss &&
6565                             (sample_rss->level != rss->level ||
6566                             sample_rss->types != rss->types))
6567                                 return rte_flow_error_set(error, ENOTSUP,
6568                                         RTE_FLOW_ERROR_TYPE_ACTION,
6569                                         NULL,
6570                                         "Can't use the different RSS types "
6571                                         "or level in the same flow");
6572                         if (rss != NULL && rss->queue_num)
6573                                 queue_index = rss->queue[0];
6574                         action_flags |= MLX5_FLOW_ACTION_RSS;
6575                         ++actions_n;
6576                         break;
6577                 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
6578                         ret =
6579                         mlx5_flow_validate_action_default_miss(action_flags,
6580                                         attr, error);
6581                         if (ret < 0)
6582                                 return ret;
6583                         action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
6584                         ++actions_n;
6585                         break;
6586                 case RTE_FLOW_ACTION_TYPE_COUNT:
6587                         ret = flow_dv_validate_action_count(dev, actions,
6588                                                             action_flags,
6589                                                             error);
6590                         if (ret < 0)
6591                                 return ret;
6592                         count = actions->conf;
6593                         action_flags |= MLX5_FLOW_ACTION_COUNT;
6594                         ++actions_n;
6595                         break;
6596                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
6597                         if (flow_dv_validate_action_pop_vlan(dev,
6598                                                              action_flags,
6599                                                              actions,
6600                                                              item_flags, attr,
6601                                                              error))
6602                                 return -rte_errno;
6603                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
6604                         ++actions_n;
6605                         break;
6606                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
6607                         ret = flow_dv_validate_action_push_vlan(dev,
6608                                                                 action_flags,
6609                                                                 vlan_m,
6610                                                                 actions, attr,
6611                                                                 error);
6612                         if (ret < 0)
6613                                 return ret;
6614                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
6615                         ++actions_n;
6616                         break;
6617                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
6618                         ret = flow_dv_validate_action_set_vlan_pcp
6619                                                 (action_flags, actions, error);
6620                         if (ret < 0)
6621                                 return ret;
6622                         /* Count PCP with push_vlan command. */
6623                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
6624                         break;
6625                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
6626                         ret = flow_dv_validate_action_set_vlan_vid
6627                                                 (item_flags, action_flags,
6628                                                  actions, error);
6629                         if (ret < 0)
6630                                 return ret;
6631                         /* Count VID with push_vlan command. */
6632                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
6633                         rw_act_num += MLX5_ACT_NUM_MDF_VID;
6634                         break;
6635                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
6636                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
6637                         ret = flow_dv_validate_action_l2_encap(dev,
6638                                                                action_flags,
6639                                                                actions, attr,
6640                                                                error);
6641                         if (ret < 0)
6642                                 return ret;
6643                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
6644                         ++actions_n;
6645                         break;
6646                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
6647                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
6648                         ret = flow_dv_validate_action_decap(dev, action_flags,
6649                                                             actions, item_flags,
6650                                                             attr, error);
6651                         if (ret < 0)
6652                                 return ret;
6653                         action_flags |= MLX5_FLOW_ACTION_DECAP;
6654                         ++actions_n;
6655                         break;
6656                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
6657                         ret = flow_dv_validate_action_raw_encap_decap
6658                                 (dev, NULL, actions->conf, attr, &action_flags,
6659                                  &actions_n, actions, item_flags, error);
6660                         if (ret < 0)
6661                                 return ret;
6662                         break;
6663                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
6664                         decap = actions->conf;
6665                         while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
6666                                 ;
6667                         if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
6668                                 encap = NULL;
6669                                 actions--;
6670                         } else {
6671                                 encap = actions->conf;
6672                         }
6673                         ret = flow_dv_validate_action_raw_encap_decap
6674                                            (dev,
6675                                             decap ? decap : &empty_decap, encap,
6676                                             attr, &action_flags, &actions_n,
6677                                             actions, item_flags, error);
6678                         if (ret < 0)
6679                                 return ret;
6680                         break;
6681                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
6682                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
6683                         ret = flow_dv_validate_action_modify_mac(action_flags,
6684                                                                  actions,
6685                                                                  item_flags,
6686                                                                  error);
6687                         if (ret < 0)
6688                                 return ret;
6689                         /* Count all modify-header actions as one action. */
6690                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6691                                 ++actions_n;
6692                         action_flags |= actions->type ==
6693                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
6694                                                 MLX5_FLOW_ACTION_SET_MAC_SRC :
6695                                                 MLX5_FLOW_ACTION_SET_MAC_DST;
6696                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6697                                 modify_after_mirror = 1;
6698                         /*
6699                          * Even if the source and destination MAC addresses have
6700                          * overlap in the header with 4B alignment, the convert
6701                          * function will handle them separately and 4 SW actions
6702                          * will be created. And 2 actions will be added each
6703                          * time no matter how many bytes of address will be set.
6704                          */
6705                         rw_act_num += MLX5_ACT_NUM_MDF_MAC;
6706                         break;
6707                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
6708                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
6709                         ret = flow_dv_validate_action_modify_ipv4(action_flags,
6710                                                                   actions,
6711                                                                   item_flags,
6712                                                                   error);
6713                         if (ret < 0)
6714                                 return ret;
6715                         /* Count all modify-header actions as one action. */
6716                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6717                                 ++actions_n;
6718                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6719                                 modify_after_mirror = 1;
6720                         action_flags |= actions->type ==
6721                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
6722                                                 MLX5_FLOW_ACTION_SET_IPV4_SRC :
6723                                                 MLX5_FLOW_ACTION_SET_IPV4_DST;
6724                         rw_act_num += MLX5_ACT_NUM_MDF_IPV4;
6725                         break;
6726                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
6727                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
6728                         ret = flow_dv_validate_action_modify_ipv6(action_flags,
6729                                                                   actions,
6730                                                                   item_flags,
6731                                                                   error);
6732                         if (ret < 0)
6733                                 return ret;
6734                         if (item_ipv6_proto == IPPROTO_ICMPV6)
6735                                 return rte_flow_error_set(error, ENOTSUP,
6736                                         RTE_FLOW_ERROR_TYPE_ACTION,
6737                                         actions,
6738                                         "Can't change header "
6739                                         "with ICMPv6 proto");
6740                         /* Count all modify-header actions as one action. */
6741                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6742                                 ++actions_n;
6743                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6744                                 modify_after_mirror = 1;
6745                         action_flags |= actions->type ==
6746                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
6747                                                 MLX5_FLOW_ACTION_SET_IPV6_SRC :
6748                                                 MLX5_FLOW_ACTION_SET_IPV6_DST;
6749                         rw_act_num += MLX5_ACT_NUM_MDF_IPV6;
6750                         break;
6751                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
6752                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
6753                         ret = flow_dv_validate_action_modify_tp(action_flags,
6754                                                                 actions,
6755                                                                 item_flags,
6756                                                                 error);
6757                         if (ret < 0)
6758                                 return ret;
6759                         /* Count all modify-header actions as one action. */
6760                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6761                                 ++actions_n;
6762                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6763                                 modify_after_mirror = 1;
6764                         action_flags |= actions->type ==
6765                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
6766                                                 MLX5_FLOW_ACTION_SET_TP_SRC :
6767                                                 MLX5_FLOW_ACTION_SET_TP_DST;
6768                         rw_act_num += MLX5_ACT_NUM_MDF_PORT;
6769                         break;
6770                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
6771                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
6772                         ret = flow_dv_validate_action_modify_ttl(action_flags,
6773                                                                  actions,
6774                                                                  item_flags,
6775                                                                  error);
6776                         if (ret < 0)
6777                                 return ret;
6778                         /* Count all modify-header actions as one action. */
6779                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6780                                 ++actions_n;
6781                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6782                                 modify_after_mirror = 1;
6783                         action_flags |= actions->type ==
6784                                         RTE_FLOW_ACTION_TYPE_SET_TTL ?
6785                                                 MLX5_FLOW_ACTION_SET_TTL :
6786                                                 MLX5_FLOW_ACTION_DEC_TTL;
6787                         rw_act_num += MLX5_ACT_NUM_MDF_TTL;
6788                         break;
6789                 case RTE_FLOW_ACTION_TYPE_JUMP:
6790                         ret = flow_dv_validate_action_jump(dev, tunnel, actions,
6791                                                            action_flags,
6792                                                            attr, external,
6793                                                            error);
6794                         if (ret)
6795                                 return ret;
6796                         if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) &&
6797                             fdb_mirror_limit)
6798                                 return rte_flow_error_set(error, EINVAL,
6799                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6800                                                   NULL,
6801                                                   "sample and jump action combination is not supported");
6802                         ++actions_n;
6803                         action_flags |= MLX5_FLOW_ACTION_JUMP;
6804                         break;
6805                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
6806                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
6807                         ret = flow_dv_validate_action_modify_tcp_seq
6808                                                                 (action_flags,
6809                                                                  actions,
6810                                                                  item_flags,
6811                                                                  error);
6812                         if (ret < 0)
6813                                 return ret;
6814                         /* Count all modify-header actions as one action. */
6815                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6816                                 ++actions_n;
6817                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6818                                 modify_after_mirror = 1;
6819                         action_flags |= actions->type ==
6820                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
6821                                                 MLX5_FLOW_ACTION_INC_TCP_SEQ :
6822                                                 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
6823                         rw_act_num += MLX5_ACT_NUM_MDF_TCPSEQ;
6824                         break;
6825                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
6826                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
6827                         ret = flow_dv_validate_action_modify_tcp_ack
6828                                                                 (action_flags,
6829                                                                  actions,
6830                                                                  item_flags,
6831                                                                  error);
6832                         if (ret < 0)
6833                                 return ret;
6834                         /* Count all modify-header actions as one action. */
6835                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6836                                 ++actions_n;
6837                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6838                                 modify_after_mirror = 1;
6839                         action_flags |= actions->type ==
6840                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
6841                                                 MLX5_FLOW_ACTION_INC_TCP_ACK :
6842                                                 MLX5_FLOW_ACTION_DEC_TCP_ACK;
6843                         rw_act_num += MLX5_ACT_NUM_MDF_TCPACK;
6844                         break;
6845                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
6846                         break;
6847                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
6848                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
6849                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
6850                         break;
6851                 case RTE_FLOW_ACTION_TYPE_METER:
6852                         ret = mlx5_flow_validate_action_meter(dev,
6853                                                               action_flags,
6854                                                               actions, attr,
6855                                                               error);
6856                         if (ret < 0)
6857                                 return ret;
6858                         action_flags |= MLX5_FLOW_ACTION_METER;
6859                         ++actions_n;
6860                         /* Meter action will add one more TAG action. */
6861                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
6862                         break;
6863                 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
6864                         if (!attr->transfer && !attr->group)
6865                                 return rte_flow_error_set(error, ENOTSUP,
6866                                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6867                                                                            NULL,
6868                           "Shared ASO age action is not supported for group 0");
6869                         action_flags |= MLX5_FLOW_ACTION_AGE;
6870                         ++actions_n;
6871                         break;
6872                 case RTE_FLOW_ACTION_TYPE_AGE:
6873                         ret = flow_dv_validate_action_age(action_flags,
6874                                                           actions, dev,
6875                                                           error);
6876                         if (ret < 0)
6877                                 return ret;
6878                         /*
6879                          * Validate the regular AGE action (using counter)
6880                          * mutual exclusion with share counter actions.
6881                          */
6882                         if (!priv->sh->flow_hit_aso_en) {
6883                                 if (count && count->shared)
6884                                         return rte_flow_error_set
6885                                                 (error, EINVAL,
6886                                                 RTE_FLOW_ERROR_TYPE_ACTION,
6887                                                 NULL,
6888                                                 "old age and shared count combination is not supported");
6889                                 if (sample_count)
6890                                         return rte_flow_error_set
6891                                                 (error, EINVAL,
6892                                                 RTE_FLOW_ERROR_TYPE_ACTION,
6893                                                 NULL,
6894                                                 "old age action and count must be in the same sub flow");
6895                         }
6896                         action_flags |= MLX5_FLOW_ACTION_AGE;
6897                         ++actions_n;
6898                         break;
6899                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
6900                         ret = flow_dv_validate_action_modify_ipv4_dscp
6901                                                          (action_flags,
6902                                                           actions,
6903                                                           item_flags,
6904                                                           error);
6905                         if (ret < 0)
6906                                 return ret;
6907                         /* Count all modify-header actions as one action. */
6908                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6909                                 ++actions_n;
6910                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6911                                 modify_after_mirror = 1;
6912                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
6913                         rw_act_num += MLX5_ACT_NUM_SET_DSCP;
6914                         break;
6915                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
6916                         ret = flow_dv_validate_action_modify_ipv6_dscp
6917                                                                 (action_flags,
6918                                                                  actions,
6919                                                                  item_flags,
6920                                                                  error);
6921                         if (ret < 0)
6922                                 return ret;
6923                         /* Count all modify-header actions as one action. */
6924                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6925                                 ++actions_n;
6926                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6927                                 modify_after_mirror = 1;
6928                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
6929                         rw_act_num += MLX5_ACT_NUM_SET_DSCP;
6930                         break;
6931                 case RTE_FLOW_ACTION_TYPE_SAMPLE:
6932                         ret = flow_dv_validate_action_sample(&action_flags,
6933                                                              actions, dev,
6934                                                              attr, item_flags,
6935                                                              rss, &sample_rss,
6936                                                              &sample_count,
6937                                                              &fdb_mirror_limit,
6938                                                              error);
6939                         if (ret < 0)
6940                                 return ret;
6941                         action_flags |= MLX5_FLOW_ACTION_SAMPLE;
6942                         ++actions_n;
6943                         break;
6944                 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
6945                         if (actions[0].type != (typeof(actions[0].type))
6946                                 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET)
6947                                 return rte_flow_error_set
6948                                                 (error, EINVAL,
6949                                                 RTE_FLOW_ERROR_TYPE_ACTION,
6950                                                 NULL, "MLX5 private action "
6951                                                 "must be the first");
6952
6953                         action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
6954                         break;
6955                 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
6956                         ret = flow_dv_validate_action_modify_field(dev,
6957                                                                    action_flags,
6958                                                                    actions,
6959                                                                    attr,
6960                                                                    error);
6961                         if (ret < 0)
6962                                 return ret;
6963                         /* Count all modify-header actions as one action. */
6964                         if (!(action_flags & MLX5_FLOW_ACTION_MODIFY_FIELD))
6965                                 ++actions_n;
6966                         action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
6967                         rw_act_num += ret;
6968                         break;
6969                 default:
6970                         return rte_flow_error_set(error, ENOTSUP,
6971                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6972                                                   actions,
6973                                                   "action not supported");
6974                 }
6975         }
6976         /*
6977          * Validate actions in flow rules
6978          * - Explicit decap action is prohibited by the tunnel offload API.
6979          * - Drop action in tunnel steer rule is prohibited by the API.
6980          * - Application cannot use MARK action because it's value can mask
6981          *   tunnel default miss nitification.
6982          * - JUMP in tunnel match rule has no support in current PMD
6983          *   implementation.
6984          * - TAG & META are reserved for future uses.
6985          */
6986         if (action_flags & MLX5_FLOW_ACTION_TUNNEL_SET) {
6987                 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_DECAP    |
6988                                             MLX5_FLOW_ACTION_MARK     |
6989                                             MLX5_FLOW_ACTION_SET_TAG  |
6990                                             MLX5_FLOW_ACTION_SET_META |
6991                                             MLX5_FLOW_ACTION_DROP;
6992
6993                 if (action_flags & bad_actions_mask)
6994                         return rte_flow_error_set
6995                                         (error, EINVAL,
6996                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6997                                         "Invalid RTE action in tunnel "
6998                                         "set decap rule");
6999                 if (!(action_flags & MLX5_FLOW_ACTION_JUMP))
7000                         return rte_flow_error_set
7001                                         (error, EINVAL,
7002                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7003                                         "tunnel set decap rule must terminate "
7004                                         "with JUMP");
7005                 if (!attr->ingress)
7006                         return rte_flow_error_set
7007                                         (error, EINVAL,
7008                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7009                                         "tunnel flows for ingress traffic only");
7010         }
7011         if (action_flags & MLX5_FLOW_ACTION_TUNNEL_MATCH) {
7012                 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_JUMP    |
7013                                             MLX5_FLOW_ACTION_MARK    |
7014                                             MLX5_FLOW_ACTION_SET_TAG |
7015                                             MLX5_FLOW_ACTION_SET_META;
7016
7017                 if (action_flags & bad_actions_mask)
7018                         return rte_flow_error_set
7019                                         (error, EINVAL,
7020                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7021                                         "Invalid RTE action in tunnel "
7022                                         "set match rule");
7023         }
7024         /*
7025          * Validate the drop action mutual exclusion with other actions.
7026          * Drop action is mutually-exclusive with any other action, except for
7027          * Count action.
7028          * Drop action compatibility with tunnel offload was already validated.
7029          */
7030         if (action_flags & (MLX5_FLOW_ACTION_TUNNEL_MATCH |
7031                             MLX5_FLOW_ACTION_TUNNEL_MATCH));
7032         else if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
7033             (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
7034                 return rte_flow_error_set(error, EINVAL,
7035                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7036                                           "Drop action is mutually-exclusive "
7037                                           "with any other action, except for "
7038                                           "Count action");
7039         /* Eswitch has few restrictions on using items and actions */
7040         if (attr->transfer) {
7041                 if (!mlx5_flow_ext_mreg_supported(dev) &&
7042                     action_flags & MLX5_FLOW_ACTION_FLAG)
7043                         return rte_flow_error_set(error, ENOTSUP,
7044                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7045                                                   NULL,
7046                                                   "unsupported action FLAG");
7047                 if (!mlx5_flow_ext_mreg_supported(dev) &&
7048                     action_flags & MLX5_FLOW_ACTION_MARK)
7049                         return rte_flow_error_set(error, ENOTSUP,
7050                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7051                                                   NULL,
7052                                                   "unsupported action MARK");
7053                 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
7054                         return rte_flow_error_set(error, ENOTSUP,
7055                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7056                                                   NULL,
7057                                                   "unsupported action QUEUE");
7058                 if (action_flags & MLX5_FLOW_ACTION_RSS)
7059                         return rte_flow_error_set(error, ENOTSUP,
7060                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7061                                                   NULL,
7062                                                   "unsupported action RSS");
7063                 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
7064                         return rte_flow_error_set(error, EINVAL,
7065                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7066                                                   actions,
7067                                                   "no fate action is found");
7068         } else {
7069                 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
7070                         return rte_flow_error_set(error, EINVAL,
7071                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7072                                                   actions,
7073                                                   "no fate action is found");
7074         }
7075         /*
7076          * Continue validation for Xcap and VLAN actions.
7077          * If hairpin is working in explicit TX rule mode, there is no actions
7078          * splitting and the validation of hairpin ingress flow should be the
7079          * same as other standard flows.
7080          */
7081         if ((action_flags & (MLX5_FLOW_XCAP_ACTIONS |
7082                              MLX5_FLOW_VLAN_ACTIONS)) &&
7083             (queue_index == 0xFFFF ||
7084              mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN ||
7085              ((conf = mlx5_rxq_get_hairpin_conf(dev, queue_index)) != NULL &&
7086              conf->tx_explicit != 0))) {
7087                 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
7088                     MLX5_FLOW_XCAP_ACTIONS)
7089                         return rte_flow_error_set(error, ENOTSUP,
7090                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7091                                                   NULL, "encap and decap "
7092                                                   "combination aren't supported");
7093                 if (!attr->transfer && attr->ingress) {
7094                         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
7095                                 return rte_flow_error_set
7096                                                 (error, ENOTSUP,
7097                                                  RTE_FLOW_ERROR_TYPE_ACTION,
7098                                                  NULL, "encap is not supported"
7099                                                  " for ingress traffic");
7100                         else if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
7101                                 return rte_flow_error_set
7102                                                 (error, ENOTSUP,
7103                                                  RTE_FLOW_ERROR_TYPE_ACTION,
7104                                                  NULL, "push VLAN action not "
7105                                                  "supported for ingress");
7106                         else if ((action_flags & MLX5_FLOW_VLAN_ACTIONS) ==
7107                                         MLX5_FLOW_VLAN_ACTIONS)
7108                                 return rte_flow_error_set
7109                                                 (error, ENOTSUP,
7110                                                  RTE_FLOW_ERROR_TYPE_ACTION,
7111                                                  NULL, "no support for "
7112                                                  "multiple VLAN actions");
7113                 }
7114         }
7115         /*
7116          * Hairpin flow will add one more TAG action in TX implicit mode.
7117          * In TX explicit mode, there will be no hairpin flow ID.
7118          */
7119         if (hairpin > 0)
7120                 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7121         /* extra metadata enabled: one more TAG action will be add. */
7122         if (dev_conf->dv_flow_en &&
7123             dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
7124             mlx5_flow_ext_mreg_supported(dev))
7125                 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7126         if (rw_act_num >
7127                         flow_dv_modify_hdr_action_max(dev, is_root)) {
7128                 return rte_flow_error_set(error, ENOTSUP,
7129                                           RTE_FLOW_ERROR_TYPE_ACTION,
7130                                           NULL, "too many header modify"
7131                                           " actions to support");
7132         }
7133         /* Eswitch egress mirror and modify flow has limitation on CX5 */
7134         if (fdb_mirror_limit && modify_after_mirror)
7135                 return rte_flow_error_set(error, EINVAL,
7136                                 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7137                                 "sample before modify action is not supported");
7138         return 0;
7139 }
7140
7141 /**
7142  * Internal preparation function. Allocates the DV flow size,
7143  * this size is constant.
7144  *
7145  * @param[in] dev
7146  *   Pointer to the rte_eth_dev structure.
7147  * @param[in] attr
7148  *   Pointer to the flow attributes.
7149  * @param[in] items
7150  *   Pointer to the list of items.
7151  * @param[in] actions
7152  *   Pointer to the list of actions.
7153  * @param[out] error
7154  *   Pointer to the error structure.
7155  *
7156  * @return
7157  *   Pointer to mlx5_flow object on success,
7158  *   otherwise NULL and rte_errno is set.
7159  */
7160 static struct mlx5_flow *
7161 flow_dv_prepare(struct rte_eth_dev *dev,
7162                 const struct rte_flow_attr *attr __rte_unused,
7163                 const struct rte_flow_item items[] __rte_unused,
7164                 const struct rte_flow_action actions[] __rte_unused,
7165                 struct rte_flow_error *error)
7166 {
7167         uint32_t handle_idx = 0;
7168         struct mlx5_flow *dev_flow;
7169         struct mlx5_flow_handle *dev_handle;
7170         struct mlx5_priv *priv = dev->data->dev_private;
7171         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
7172
7173         MLX5_ASSERT(wks);
7174         /* In case of corrupting the memory. */
7175         if (wks->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
7176                 rte_flow_error_set(error, ENOSPC,
7177                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7178                                    "not free temporary device flow");
7179                 return NULL;
7180         }
7181         dev_handle = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
7182                                    &handle_idx);
7183         if (!dev_handle) {
7184                 rte_flow_error_set(error, ENOMEM,
7185                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7186                                    "not enough memory to create flow handle");
7187                 return NULL;
7188         }
7189         MLX5_ASSERT(wks->flow_idx < RTE_DIM(wks->flows));
7190         dev_flow = &wks->flows[wks->flow_idx++];
7191         memset(dev_flow, 0, sizeof(*dev_flow));
7192         dev_flow->handle = dev_handle;
7193         dev_flow->handle_idx = handle_idx;
7194         /*
7195          * In some old rdma-core releases, before continuing, a check of the
7196          * length of matching parameter will be done at first. It needs to use
7197          * the length without misc4 param. If the flow has misc4 support, then
7198          * the length needs to be adjusted accordingly. Each param member is
7199          * aligned with a 64B boundary naturally.
7200          */
7201         dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param) -
7202                                   MLX5_ST_SZ_BYTES(fte_match_set_misc4);
7203         dev_flow->ingress = attr->ingress;
7204         dev_flow->dv.transfer = attr->transfer;
7205         return dev_flow;
7206 }
7207
7208 #ifdef RTE_LIBRTE_MLX5_DEBUG
7209 /**
7210  * Sanity check for match mask and value. Similar to check_valid_spec() in
7211  * kernel driver. If unmasked bit is present in value, it returns failure.
7212  *
7213  * @param match_mask
7214  *   pointer to match mask buffer.
7215  * @param match_value
7216  *   pointer to match value buffer.
7217  *
7218  * @return
7219  *   0 if valid, -EINVAL otherwise.
7220  */
7221 static int
7222 flow_dv_check_valid_spec(void *match_mask, void *match_value)
7223 {
7224         uint8_t *m = match_mask;
7225         uint8_t *v = match_value;
7226         unsigned int i;
7227
7228         for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
7229                 if (v[i] & ~m[i]) {
7230                         DRV_LOG(ERR,
7231                                 "match_value differs from match_criteria"
7232                                 " %p[%u] != %p[%u]",
7233                                 match_value, i, match_mask, i);
7234                         return -EINVAL;
7235                 }
7236         }
7237         return 0;
7238 }
7239 #endif
7240
7241 /**
7242  * Add match of ip_version.
7243  *
7244  * @param[in] group
7245  *   Flow group.
7246  * @param[in] headers_v
7247  *   Values header pointer.
7248  * @param[in] headers_m
7249  *   Masks header pointer.
7250  * @param[in] ip_version
7251  *   The IP version to set.
7252  */
7253 static inline void
7254 flow_dv_set_match_ip_version(uint32_t group,
7255                              void *headers_v,
7256                              void *headers_m,
7257                              uint8_t ip_version)
7258 {
7259         if (group == 0)
7260                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
7261         else
7262                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version,
7263                          ip_version);
7264         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, ip_version);
7265         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, 0);
7266         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype, 0);
7267 }
7268
7269 /**
7270  * Add Ethernet item to matcher and to the value.
7271  *
7272  * @param[in, out] matcher
7273  *   Flow matcher.
7274  * @param[in, out] key
7275  *   Flow matcher value.
7276  * @param[in] item
7277  *   Flow pattern to translate.
7278  * @param[in] inner
7279  *   Item is inner pattern.
7280  */
7281 static void
7282 flow_dv_translate_item_eth(void *matcher, void *key,
7283                            const struct rte_flow_item *item, int inner,
7284                            uint32_t group)
7285 {
7286         const struct rte_flow_item_eth *eth_m = item->mask;
7287         const struct rte_flow_item_eth *eth_v = item->spec;
7288         const struct rte_flow_item_eth nic_mask = {
7289                 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
7290                 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
7291                 .type = RTE_BE16(0xffff),
7292                 .has_vlan = 0,
7293         };
7294         void *hdrs_m;
7295         void *hdrs_v;
7296         char *l24_v;
7297         unsigned int i;
7298
7299         if (!eth_v)
7300                 return;
7301         if (!eth_m)
7302                 eth_m = &nic_mask;
7303         if (inner) {
7304                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7305                                          inner_headers);
7306                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7307         } else {
7308                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7309                                          outer_headers);
7310                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7311         }
7312         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, dmac_47_16),
7313                &eth_m->dst, sizeof(eth_m->dst));
7314         /* The value must be in the range of the mask. */
7315         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, dmac_47_16);
7316         for (i = 0; i < sizeof(eth_m->dst); ++i)
7317                 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
7318         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, smac_47_16),
7319                &eth_m->src, sizeof(eth_m->src));
7320         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, smac_47_16);
7321         /* The value must be in the range of the mask. */
7322         for (i = 0; i < sizeof(eth_m->dst); ++i)
7323                 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
7324         /*
7325          * HW supports match on one Ethertype, the Ethertype following the last
7326          * VLAN tag of the packet (see PRM).
7327          * Set match on ethertype only if ETH header is not followed by VLAN.
7328          * HW is optimized for IPv4/IPv6. In such cases, avoid setting
7329          * ethertype, and use ip_version field instead.
7330          * eCPRI over Ether layer will use type value 0xAEFE.
7331          */
7332         if (eth_m->type == 0xFFFF) {
7333                 /* Set cvlan_tag mask for any single\multi\un-tagged case. */
7334                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
7335                 switch (eth_v->type) {
7336                 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
7337                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
7338                         return;
7339                 case RTE_BE16(RTE_ETHER_TYPE_QINQ):
7340                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
7341                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
7342                         return;
7343                 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
7344                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
7345                         return;
7346                 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
7347                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
7348                         return;
7349                 default:
7350                         break;
7351                 }
7352         }
7353         if (eth_m->has_vlan) {
7354                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
7355                 if (eth_v->has_vlan) {
7356                         /*
7357                          * Here, when also has_more_vlan field in VLAN item is
7358                          * not set, only single-tagged packets will be matched.
7359                          */
7360                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
7361                         return;
7362                 }
7363         }
7364         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
7365                  rte_be_to_cpu_16(eth_m->type));
7366         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, ethertype);
7367         *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
7368 }
7369
7370 /**
7371  * Add VLAN item to matcher and to the value.
7372  *
7373  * @param[in, out] dev_flow
7374  *   Flow descriptor.
7375  * @param[in, out] matcher
7376  *   Flow matcher.
7377  * @param[in, out] key
7378  *   Flow matcher value.
7379  * @param[in] item
7380  *   Flow pattern to translate.
7381  * @param[in] inner
7382  *   Item is inner pattern.
7383  */
7384 static void
7385 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
7386                             void *matcher, void *key,
7387                             const struct rte_flow_item *item,
7388                             int inner, uint32_t group)
7389 {
7390         const struct rte_flow_item_vlan *vlan_m = item->mask;
7391         const struct rte_flow_item_vlan *vlan_v = item->spec;
7392         void *hdrs_m;
7393         void *hdrs_v;
7394         uint16_t tci_m;
7395         uint16_t tci_v;
7396
7397         if (inner) {
7398                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7399                                          inner_headers);
7400                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7401         } else {
7402                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7403                                          outer_headers);
7404                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7405                 /*
7406                  * This is workaround, masks are not supported,
7407                  * and pre-validated.
7408                  */
7409                 if (vlan_v)
7410                         dev_flow->handle->vf_vlan.tag =
7411                                         rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
7412         }
7413         /*
7414          * When VLAN item exists in flow, mark packet as tagged,
7415          * even if TCI is not specified.
7416          */
7417         if (!MLX5_GET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag)) {
7418                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
7419                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
7420         }
7421         if (!vlan_v)
7422                 return;
7423         if (!vlan_m)
7424                 vlan_m = &rte_flow_item_vlan_mask;
7425         tci_m = rte_be_to_cpu_16(vlan_m->tci);
7426         tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
7427         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_vid, tci_m);
7428         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_vid, tci_v);
7429         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_cfi, tci_m >> 12);
7430         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_cfi, tci_v >> 12);
7431         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_prio, tci_m >> 13);
7432         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_prio, tci_v >> 13);
7433         /*
7434          * HW is optimized for IPv4/IPv6. In such cases, avoid setting
7435          * ethertype, and use ip_version field instead.
7436          */
7437         if (vlan_m->inner_type == 0xFFFF) {
7438                 switch (vlan_v->inner_type) {
7439                 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
7440                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
7441                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
7442                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
7443                         return;
7444                 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
7445                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
7446                         return;
7447                 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
7448                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
7449                         return;
7450                 default:
7451                         break;
7452                 }
7453         }
7454         if (vlan_m->has_more_vlan && vlan_v->has_more_vlan) {
7455                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
7456                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
7457                 /* Only one vlan_tag bit can be set. */
7458                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
7459                 return;
7460         }
7461         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
7462                  rte_be_to_cpu_16(vlan_m->inner_type));
7463         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, ethertype,
7464                  rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
7465 }
7466
7467 /**
7468  * Add IPV4 item to matcher and to the value.
7469  *
7470  * @param[in, out] matcher
7471  *   Flow matcher.
7472  * @param[in, out] key
7473  *   Flow matcher value.
7474  * @param[in] item
7475  *   Flow pattern to translate.
7476  * @param[in] inner
7477  *   Item is inner pattern.
7478  * @param[in] group
7479  *   The group to insert the rule.
7480  */
7481 static void
7482 flow_dv_translate_item_ipv4(void *matcher, void *key,
7483                             const struct rte_flow_item *item,
7484                             int inner, uint32_t group)
7485 {
7486         const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
7487         const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
7488         const struct rte_flow_item_ipv4 nic_mask = {
7489                 .hdr = {
7490                         .src_addr = RTE_BE32(0xffffffff),
7491                         .dst_addr = RTE_BE32(0xffffffff),
7492                         .type_of_service = 0xff,
7493                         .next_proto_id = 0xff,
7494                         .time_to_live = 0xff,
7495                 },
7496         };
7497         void *headers_m;
7498         void *headers_v;
7499         char *l24_m;
7500         char *l24_v;
7501         uint8_t tos;
7502
7503         if (inner) {
7504                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7505                                          inner_headers);
7506                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7507         } else {
7508                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7509                                          outer_headers);
7510                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7511         }
7512         flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
7513         if (!ipv4_v)
7514                 return;
7515         if (!ipv4_m)
7516                 ipv4_m = &nic_mask;
7517         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
7518                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
7519         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
7520                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
7521         *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
7522         *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
7523         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
7524                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
7525         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
7526                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
7527         *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
7528         *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
7529         tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
7530         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
7531                  ipv4_m->hdr.type_of_service);
7532         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
7533         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
7534                  ipv4_m->hdr.type_of_service >> 2);
7535         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
7536         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
7537                  ipv4_m->hdr.next_proto_id);
7538         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
7539                  ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
7540         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
7541                  ipv4_m->hdr.time_to_live);
7542         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
7543                  ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
7544         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
7545                  !!(ipv4_m->hdr.fragment_offset));
7546         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
7547                  !!(ipv4_v->hdr.fragment_offset & ipv4_m->hdr.fragment_offset));
7548 }
7549
7550 /**
7551  * Add IPV6 item to matcher and to the value.
7552  *
7553  * @param[in, out] matcher
7554  *   Flow matcher.
7555  * @param[in, out] key
7556  *   Flow matcher value.
7557  * @param[in] item
7558  *   Flow pattern to translate.
7559  * @param[in] inner
7560  *   Item is inner pattern.
7561  * @param[in] group
7562  *   The group to insert the rule.
7563  */
7564 static void
7565 flow_dv_translate_item_ipv6(void *matcher, void *key,
7566                             const struct rte_flow_item *item,
7567                             int inner, uint32_t group)
7568 {
7569         const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
7570         const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
7571         const struct rte_flow_item_ipv6 nic_mask = {
7572                 .hdr = {
7573                         .src_addr =
7574                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
7575                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
7576                         .dst_addr =
7577                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
7578                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
7579                         .vtc_flow = RTE_BE32(0xffffffff),
7580                         .proto = 0xff,
7581                         .hop_limits = 0xff,
7582                 },
7583         };
7584         void *headers_m;
7585         void *headers_v;
7586         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7587         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7588         char *l24_m;
7589         char *l24_v;
7590         uint32_t vtc_m;
7591         uint32_t vtc_v;
7592         int i;
7593         int size;
7594
7595         if (inner) {
7596                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7597                                          inner_headers);
7598                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7599         } else {
7600                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7601                                          outer_headers);
7602                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7603         }
7604         flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
7605         if (!ipv6_v)
7606                 return;
7607         if (!ipv6_m)
7608                 ipv6_m = &nic_mask;
7609         size = sizeof(ipv6_m->hdr.dst_addr);
7610         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
7611                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
7612         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
7613                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
7614         memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
7615         for (i = 0; i < size; ++i)
7616                 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
7617         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
7618                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
7619         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
7620                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
7621         memcpy(l24_m, ipv6_m->hdr.src_addr, size);
7622         for (i = 0; i < size; ++i)
7623                 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
7624         /* TOS. */
7625         vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
7626         vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
7627         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
7628         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
7629         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
7630         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
7631         /* Label. */
7632         if (inner) {
7633                 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
7634                          vtc_m);
7635                 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
7636                          vtc_v);
7637         } else {
7638                 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
7639                          vtc_m);
7640                 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
7641                          vtc_v);
7642         }
7643         /* Protocol. */
7644         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
7645                  ipv6_m->hdr.proto);
7646         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
7647                  ipv6_v->hdr.proto & ipv6_m->hdr.proto);
7648         /* Hop limit. */
7649         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
7650                  ipv6_m->hdr.hop_limits);
7651         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
7652                  ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
7653         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
7654                  !!(ipv6_m->has_frag_ext));
7655         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
7656                  !!(ipv6_v->has_frag_ext & ipv6_m->has_frag_ext));
7657 }
7658
7659 /**
7660  * Add IPV6 fragment extension item to matcher and to the value.
7661  *
7662  * @param[in, out] matcher
7663  *   Flow matcher.
7664  * @param[in, out] key
7665  *   Flow matcher value.
7666  * @param[in] item
7667  *   Flow pattern to translate.
7668  * @param[in] inner
7669  *   Item is inner pattern.
7670  */
7671 static void
7672 flow_dv_translate_item_ipv6_frag_ext(void *matcher, void *key,
7673                                      const struct rte_flow_item *item,
7674                                      int inner)
7675 {
7676         const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_m = item->mask;
7677         const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_v = item->spec;
7678         const struct rte_flow_item_ipv6_frag_ext nic_mask = {
7679                 .hdr = {
7680                         .next_header = 0xff,
7681                         .frag_data = RTE_BE16(0xffff),
7682                 },
7683         };
7684         void *headers_m;
7685         void *headers_v;
7686
7687         if (inner) {
7688                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7689                                          inner_headers);
7690                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7691         } else {
7692                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7693                                          outer_headers);
7694                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7695         }
7696         /* IPv6 fragment extension item exists, so packet is IP fragment. */
7697         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
7698         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 1);
7699         if (!ipv6_frag_ext_v)
7700                 return;
7701         if (!ipv6_frag_ext_m)
7702                 ipv6_frag_ext_m = &nic_mask;
7703         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
7704                  ipv6_frag_ext_m->hdr.next_header);
7705         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
7706                  ipv6_frag_ext_v->hdr.next_header &
7707                  ipv6_frag_ext_m->hdr.next_header);
7708 }
7709
7710 /**
7711  * Add TCP item to matcher and to the value.
7712  *
7713  * @param[in, out] matcher
7714  *   Flow matcher.
7715  * @param[in, out] key
7716  *   Flow matcher value.
7717  * @param[in] item
7718  *   Flow pattern to translate.
7719  * @param[in] inner
7720  *   Item is inner pattern.
7721  */
7722 static void
7723 flow_dv_translate_item_tcp(void *matcher, void *key,
7724                            const struct rte_flow_item *item,
7725                            int inner)
7726 {
7727         const struct rte_flow_item_tcp *tcp_m = item->mask;
7728         const struct rte_flow_item_tcp *tcp_v = item->spec;
7729         void *headers_m;
7730         void *headers_v;
7731
7732         if (inner) {
7733                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7734                                          inner_headers);
7735                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7736         } else {
7737                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7738                                          outer_headers);
7739                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7740         }
7741         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7742         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
7743         if (!tcp_v)
7744                 return;
7745         if (!tcp_m)
7746                 tcp_m = &rte_flow_item_tcp_mask;
7747         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
7748                  rte_be_to_cpu_16(tcp_m->hdr.src_port));
7749         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
7750                  rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
7751         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
7752                  rte_be_to_cpu_16(tcp_m->hdr.dst_port));
7753         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
7754                  rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
7755         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
7756                  tcp_m->hdr.tcp_flags);
7757         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
7758                  (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
7759 }
7760
7761 /**
7762  * Add UDP item to matcher and to the value.
7763  *
7764  * @param[in, out] matcher
7765  *   Flow matcher.
7766  * @param[in, out] key
7767  *   Flow matcher value.
7768  * @param[in] item
7769  *   Flow pattern to translate.
7770  * @param[in] inner
7771  *   Item is inner pattern.
7772  */
7773 static void
7774 flow_dv_translate_item_udp(void *matcher, void *key,
7775                            const struct rte_flow_item *item,
7776                            int inner)
7777 {
7778         const struct rte_flow_item_udp *udp_m = item->mask;
7779         const struct rte_flow_item_udp *udp_v = item->spec;
7780         void *headers_m;
7781         void *headers_v;
7782
7783         if (inner) {
7784                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7785                                          inner_headers);
7786                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7787         } else {
7788                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7789                                          outer_headers);
7790                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7791         }
7792         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7793         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
7794         if (!udp_v)
7795                 return;
7796         if (!udp_m)
7797                 udp_m = &rte_flow_item_udp_mask;
7798         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
7799                  rte_be_to_cpu_16(udp_m->hdr.src_port));
7800         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
7801                  rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
7802         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
7803                  rte_be_to_cpu_16(udp_m->hdr.dst_port));
7804         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
7805                  rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
7806 }
7807
7808 /**
7809  * Add GRE optional Key item to matcher and to the value.
7810  *
7811  * @param[in, out] matcher
7812  *   Flow matcher.
7813  * @param[in, out] key
7814  *   Flow matcher value.
7815  * @param[in] item
7816  *   Flow pattern to translate.
7817  * @param[in] inner
7818  *   Item is inner pattern.
7819  */
7820 static void
7821 flow_dv_translate_item_gre_key(void *matcher, void *key,
7822                                    const struct rte_flow_item *item)
7823 {
7824         const rte_be32_t *key_m = item->mask;
7825         const rte_be32_t *key_v = item->spec;
7826         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7827         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7828         rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
7829
7830         /* GRE K bit must be on and should already be validated */
7831         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
7832         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
7833         if (!key_v)
7834                 return;
7835         if (!key_m)
7836                 key_m = &gre_key_default_mask;
7837         MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
7838                  rte_be_to_cpu_32(*key_m) >> 8);
7839         MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
7840                  rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
7841         MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
7842                  rte_be_to_cpu_32(*key_m) & 0xFF);
7843         MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
7844                  rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
7845 }
7846
7847 /**
7848  * Add GRE item to matcher and to the value.
7849  *
7850  * @param[in, out] matcher
7851  *   Flow matcher.
7852  * @param[in, out] key
7853  *   Flow matcher value.
7854  * @param[in] item
7855  *   Flow pattern to translate.
7856  * @param[in] inner
7857  *   Item is inner pattern.
7858  */
7859 static void
7860 flow_dv_translate_item_gre(void *matcher, void *key,
7861                            const struct rte_flow_item *item,
7862                            int inner)
7863 {
7864         const struct rte_flow_item_gre *gre_m = item->mask;
7865         const struct rte_flow_item_gre *gre_v = item->spec;
7866         void *headers_m;
7867         void *headers_v;
7868         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7869         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7870         struct {
7871                 union {
7872                         __extension__
7873                         struct {
7874                                 uint16_t version:3;
7875                                 uint16_t rsvd0:9;
7876                                 uint16_t s_present:1;
7877                                 uint16_t k_present:1;
7878                                 uint16_t rsvd_bit1:1;
7879                                 uint16_t c_present:1;
7880                         };
7881                         uint16_t value;
7882                 };
7883         } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
7884
7885         if (inner) {
7886                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7887                                          inner_headers);
7888                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7889         } else {
7890                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7891                                          outer_headers);
7892                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7893         }
7894         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7895         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
7896         if (!gre_v)
7897                 return;
7898         if (!gre_m)
7899                 gre_m = &rte_flow_item_gre_mask;
7900         MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
7901                  rte_be_to_cpu_16(gre_m->protocol));
7902         MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
7903                  rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
7904         gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
7905         gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
7906         MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
7907                  gre_crks_rsvd0_ver_m.c_present);
7908         MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
7909                  gre_crks_rsvd0_ver_v.c_present &
7910                  gre_crks_rsvd0_ver_m.c_present);
7911         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
7912                  gre_crks_rsvd0_ver_m.k_present);
7913         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
7914                  gre_crks_rsvd0_ver_v.k_present &
7915                  gre_crks_rsvd0_ver_m.k_present);
7916         MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
7917                  gre_crks_rsvd0_ver_m.s_present);
7918         MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
7919                  gre_crks_rsvd0_ver_v.s_present &
7920                  gre_crks_rsvd0_ver_m.s_present);
7921 }
7922
7923 /**
7924  * Add NVGRE item to matcher and to the value.
7925  *
7926  * @param[in, out] matcher
7927  *   Flow matcher.
7928  * @param[in, out] key
7929  *   Flow matcher value.
7930  * @param[in] item
7931  *   Flow pattern to translate.
7932  * @param[in] inner
7933  *   Item is inner pattern.
7934  */
7935 static void
7936 flow_dv_translate_item_nvgre(void *matcher, void *key,
7937                              const struct rte_flow_item *item,
7938                              int inner)
7939 {
7940         const struct rte_flow_item_nvgre *nvgre_m = item->mask;
7941         const struct rte_flow_item_nvgre *nvgre_v = item->spec;
7942         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7943         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7944         const char *tni_flow_id_m;
7945         const char *tni_flow_id_v;
7946         char *gre_key_m;
7947         char *gre_key_v;
7948         int size;
7949         int i;
7950
7951         /* For NVGRE, GRE header fields must be set with defined values. */
7952         const struct rte_flow_item_gre gre_spec = {
7953                 .c_rsvd0_ver = RTE_BE16(0x2000),
7954                 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
7955         };
7956         const struct rte_flow_item_gre gre_mask = {
7957                 .c_rsvd0_ver = RTE_BE16(0xB000),
7958                 .protocol = RTE_BE16(UINT16_MAX),
7959         };
7960         const struct rte_flow_item gre_item = {
7961                 .spec = &gre_spec,
7962                 .mask = &gre_mask,
7963                 .last = NULL,
7964         };
7965         flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
7966         if (!nvgre_v)
7967                 return;
7968         if (!nvgre_m)
7969                 nvgre_m = &rte_flow_item_nvgre_mask;
7970         tni_flow_id_m = (const char *)nvgre_m->tni;
7971         tni_flow_id_v = (const char *)nvgre_v->tni;
7972         size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
7973         gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
7974         gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
7975         memcpy(gre_key_m, tni_flow_id_m, size);
7976         for (i = 0; i < size; ++i)
7977                 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
7978 }
7979
7980 /**
7981  * Add VXLAN item to matcher and to the value.
7982  *
7983  * @param[in, out] matcher
7984  *   Flow matcher.
7985  * @param[in, out] key
7986  *   Flow matcher value.
7987  * @param[in] item
7988  *   Flow pattern to translate.
7989  * @param[in] inner
7990  *   Item is inner pattern.
7991  */
7992 static void
7993 flow_dv_translate_item_vxlan(void *matcher, void *key,
7994                              const struct rte_flow_item *item,
7995                              int inner)
7996 {
7997         const struct rte_flow_item_vxlan *vxlan_m = item->mask;
7998         const struct rte_flow_item_vxlan *vxlan_v = item->spec;
7999         void *headers_m;
8000         void *headers_v;
8001         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8002         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8003         char *vni_m;
8004         char *vni_v;
8005         uint16_t dport;
8006         int size;
8007         int i;
8008
8009         if (inner) {
8010                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8011                                          inner_headers);
8012                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8013         } else {
8014                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8015                                          outer_headers);
8016                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8017         }
8018         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
8019                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
8020         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8021                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8022                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8023         }
8024         if (!vxlan_v)
8025                 return;
8026         if (!vxlan_m)
8027                 vxlan_m = &rte_flow_item_vxlan_mask;
8028         size = sizeof(vxlan_m->vni);
8029         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
8030         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
8031         memcpy(vni_m, vxlan_m->vni, size);
8032         for (i = 0; i < size; ++i)
8033                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
8034 }
8035
8036 /**
8037  * Add VXLAN-GPE item to matcher and to the value.
8038  *
8039  * @param[in, out] matcher
8040  *   Flow matcher.
8041  * @param[in, out] key
8042  *   Flow matcher value.
8043  * @param[in] item
8044  *   Flow pattern to translate.
8045  * @param[in] inner
8046  *   Item is inner pattern.
8047  */
8048
8049 static void
8050 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
8051                                  const struct rte_flow_item *item, int inner)
8052 {
8053         const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
8054         const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
8055         void *headers_m;
8056         void *headers_v;
8057         void *misc_m =
8058                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
8059         void *misc_v =
8060                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8061         char *vni_m;
8062         char *vni_v;
8063         uint16_t dport;
8064         int size;
8065         int i;
8066         uint8_t flags_m = 0xff;
8067         uint8_t flags_v = 0xc;
8068
8069         if (inner) {
8070                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8071                                          inner_headers);
8072                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8073         } else {
8074                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8075                                          outer_headers);
8076                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8077         }
8078         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
8079                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
8080         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8081                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8082                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8083         }
8084         if (!vxlan_v)
8085                 return;
8086         if (!vxlan_m)
8087                 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
8088         size = sizeof(vxlan_m->vni);
8089         vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
8090         vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
8091         memcpy(vni_m, vxlan_m->vni, size);
8092         for (i = 0; i < size; ++i)
8093                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
8094         if (vxlan_m->flags) {
8095                 flags_m = vxlan_m->flags;
8096                 flags_v = vxlan_v->flags;
8097         }
8098         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
8099         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
8100         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
8101                  vxlan_m->protocol);
8102         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
8103                  vxlan_v->protocol);
8104 }
8105
8106 /**
8107  * Add Geneve item to matcher and to the value.
8108  *
8109  * @param[in, out] matcher
8110  *   Flow matcher.
8111  * @param[in, out] key
8112  *   Flow matcher value.
8113  * @param[in] item
8114  *   Flow pattern to translate.
8115  * @param[in] inner
8116  *   Item is inner pattern.
8117  */
8118
8119 static void
8120 flow_dv_translate_item_geneve(void *matcher, void *key,
8121                               const struct rte_flow_item *item, int inner)
8122 {
8123         const struct rte_flow_item_geneve *geneve_m = item->mask;
8124         const struct rte_flow_item_geneve *geneve_v = item->spec;
8125         void *headers_m;
8126         void *headers_v;
8127         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8128         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8129         uint16_t dport;
8130         uint16_t gbhdr_m;
8131         uint16_t gbhdr_v;
8132         char *vni_m;
8133         char *vni_v;
8134         size_t size, i;
8135
8136         if (inner) {
8137                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8138                                          inner_headers);
8139                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8140         } else {
8141                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8142                                          outer_headers);
8143                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8144         }
8145         dport = MLX5_UDP_PORT_GENEVE;
8146         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8147                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8148                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8149         }
8150         if (!geneve_v)
8151                 return;
8152         if (!geneve_m)
8153                 geneve_m = &rte_flow_item_geneve_mask;
8154         size = sizeof(geneve_m->vni);
8155         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
8156         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
8157         memcpy(vni_m, geneve_m->vni, size);
8158         for (i = 0; i < size; ++i)
8159                 vni_v[i] = vni_m[i] & geneve_v->vni[i];
8160         MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
8161                  rte_be_to_cpu_16(geneve_m->protocol));
8162         MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
8163                  rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
8164         gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
8165         gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
8166         MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
8167                  MLX5_GENEVE_OAMF_VAL(gbhdr_m));
8168         MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
8169                  MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
8170         MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
8171                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
8172         MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
8173                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
8174                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
8175 }
8176
8177 /**
8178  * Create Geneve TLV option resource.
8179  *
8180  * @param dev[in, out]
8181  *   Pointer to rte_eth_dev structure.
8182  * @param[in, out] tag_be24
8183  *   Tag value in big endian then R-shift 8.
8184  * @parm[in, out] dev_flow
8185  *   Pointer to the dev_flow.
8186  * @param[out] error
8187  *   pointer to error structure.
8188  *
8189  * @return
8190  *   0 on success otherwise -errno and errno is set.
8191  */
8192
8193 int
8194 flow_dev_geneve_tlv_option_resource_register(struct rte_eth_dev *dev,
8195                                              const struct rte_flow_item *item,
8196                                              struct rte_flow_error *error)
8197 {
8198         struct mlx5_priv *priv = dev->data->dev_private;
8199         struct mlx5_dev_ctx_shared *sh = priv->sh;
8200         struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
8201                         sh->geneve_tlv_option_resource;
8202         struct mlx5_devx_obj *obj;
8203         const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
8204         int ret = 0;
8205
8206         if (!geneve_opt_v)
8207                 return -1;
8208         rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
8209         if (geneve_opt_resource != NULL) {
8210                 if (geneve_opt_resource->option_class ==
8211                         geneve_opt_v->option_class &&
8212                         geneve_opt_resource->option_type ==
8213                         geneve_opt_v->option_type &&
8214                         geneve_opt_resource->length ==
8215                         geneve_opt_v->option_len) {
8216                         /* We already have GENVE TLV option obj allocated. */
8217                         __atomic_fetch_add(&geneve_opt_resource->refcnt, 1,
8218                                            __ATOMIC_RELAXED);
8219                 } else {
8220                         ret = rte_flow_error_set(error, ENOMEM,
8221                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8222                                 "Only one GENEVE TLV option supported");
8223                         goto exit;
8224                 }
8225         } else {
8226                 /* Create a GENEVE TLV object and resource. */
8227                 obj = mlx5_devx_cmd_create_geneve_tlv_option(sh->ctx,
8228                                 geneve_opt_v->option_class,
8229                                 geneve_opt_v->option_type,
8230                                 geneve_opt_v->option_len);
8231                 if (!obj) {
8232                         ret = rte_flow_error_set(error, ENODATA,
8233                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8234                                 "Failed to create GENEVE TLV Devx object");
8235                         goto exit;
8236                 }
8237                 sh->geneve_tlv_option_resource =
8238                                 mlx5_malloc(MLX5_MEM_ZERO,
8239                                                 sizeof(*geneve_opt_resource),
8240                                                 0, SOCKET_ID_ANY);
8241                 if (!sh->geneve_tlv_option_resource) {
8242                         claim_zero(mlx5_devx_cmd_destroy(obj));
8243                         ret = rte_flow_error_set(error, ENOMEM,
8244                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8245                                 "GENEVE TLV object memory allocation failed");
8246                         goto exit;
8247                 }
8248                 geneve_opt_resource = sh->geneve_tlv_option_resource;
8249                 geneve_opt_resource->obj = obj;
8250                 geneve_opt_resource->option_class = geneve_opt_v->option_class;
8251                 geneve_opt_resource->option_type = geneve_opt_v->option_type;
8252                 geneve_opt_resource->length = geneve_opt_v->option_len;
8253                 __atomic_store_n(&geneve_opt_resource->refcnt, 1,
8254                                 __ATOMIC_RELAXED);
8255         }
8256 exit:
8257         rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
8258         return ret;
8259 }
8260
8261 /**
8262  * Add Geneve TLV option item to matcher.
8263  *
8264  * @param[in, out] dev
8265  *   Pointer to rte_eth_dev structure.
8266  * @param[in, out] matcher
8267  *   Flow matcher.
8268  * @param[in, out] key
8269  *   Flow matcher value.
8270  * @param[in] item
8271  *   Flow pattern to translate.
8272  * @param[out] error
8273  *   Pointer to error structure.
8274  */
8275 static int
8276 flow_dv_translate_item_geneve_opt(struct rte_eth_dev *dev, void *matcher,
8277                                   void *key, const struct rte_flow_item *item,
8278                                   struct rte_flow_error *error)
8279 {
8280         const struct rte_flow_item_geneve_opt *geneve_opt_m = item->mask;
8281         const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
8282         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8283         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8284         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8285                         misc_parameters_3);
8286         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8287         rte_be32_t opt_data_key = 0, opt_data_mask = 0;
8288         int ret = 0;
8289
8290         if (!geneve_opt_v)
8291                 return -1;
8292         if (!geneve_opt_m)
8293                 geneve_opt_m = &rte_flow_item_geneve_opt_mask;
8294         ret = flow_dev_geneve_tlv_option_resource_register(dev, item,
8295                                                            error);
8296         if (ret) {
8297                 DRV_LOG(ERR, "Failed to create geneve_tlv_obj");
8298                 return ret;
8299         }
8300         /*
8301          * Set the option length in GENEVE header if not requested.
8302          * The GENEVE TLV option length is expressed by the option length field
8303          * in the GENEVE header.
8304          * If the option length was not requested but the GENEVE TLV option item
8305          * is present we set the option length field implicitly.
8306          */
8307         if (!MLX5_GET16(fte_match_set_misc, misc_m, geneve_opt_len)) {
8308                 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
8309                          MLX5_GENEVE_OPTLEN_MASK);
8310                 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
8311                          geneve_opt_v->option_len + 1);
8312         }
8313         /* Set the data. */
8314         if (geneve_opt_v->data) {
8315                 memcpy(&opt_data_key, geneve_opt_v->data,
8316                         RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
8317                                 sizeof(opt_data_key)));
8318                 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
8319                                 sizeof(opt_data_key));
8320                 memcpy(&opt_data_mask, geneve_opt_m->data,
8321                         RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
8322                                 sizeof(opt_data_mask)));
8323                 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
8324                                 sizeof(opt_data_mask));
8325                 MLX5_SET(fte_match_set_misc3, misc3_m,
8326                                 geneve_tlv_option_0_data,
8327                                 rte_be_to_cpu_32(opt_data_mask));
8328                 MLX5_SET(fte_match_set_misc3, misc3_v,
8329                                 geneve_tlv_option_0_data,
8330                         rte_be_to_cpu_32(opt_data_key & opt_data_mask));
8331         }
8332         return ret;
8333 }
8334
8335 /**
8336  * Add MPLS item to matcher and to the value.
8337  *
8338  * @param[in, out] matcher
8339  *   Flow matcher.
8340  * @param[in, out] key
8341  *   Flow matcher value.
8342  * @param[in] item
8343  *   Flow pattern to translate.
8344  * @param[in] prev_layer
8345  *   The protocol layer indicated in previous item.
8346  * @param[in] inner
8347  *   Item is inner pattern.
8348  */
8349 static void
8350 flow_dv_translate_item_mpls(void *matcher, void *key,
8351                             const struct rte_flow_item *item,
8352                             uint64_t prev_layer,
8353                             int inner)
8354 {
8355         const uint32_t *in_mpls_m = item->mask;
8356         const uint32_t *in_mpls_v = item->spec;
8357         uint32_t *out_mpls_m = 0;
8358         uint32_t *out_mpls_v = 0;
8359         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8360         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8361         void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
8362                                      misc_parameters_2);
8363         void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
8364         void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
8365         void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8366
8367         switch (prev_layer) {
8368         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
8369                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
8370                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
8371                          MLX5_UDP_PORT_MPLS);
8372                 break;
8373         case MLX5_FLOW_LAYER_GRE:
8374                 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
8375                 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
8376                          RTE_ETHER_TYPE_MPLS);
8377                 break;
8378         default:
8379                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
8380                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8381                          IPPROTO_MPLS);
8382                 break;
8383         }
8384         if (!in_mpls_v)
8385                 return;
8386         if (!in_mpls_m)
8387                 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
8388         switch (prev_layer) {
8389         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
8390                 out_mpls_m =
8391                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
8392                                                  outer_first_mpls_over_udp);
8393                 out_mpls_v =
8394                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
8395                                                  outer_first_mpls_over_udp);
8396                 break;
8397         case MLX5_FLOW_LAYER_GRE:
8398                 out_mpls_m =
8399                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
8400                                                  outer_first_mpls_over_gre);
8401                 out_mpls_v =
8402                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
8403                                                  outer_first_mpls_over_gre);
8404                 break;
8405         default:
8406                 /* Inner MPLS not over GRE is not supported. */
8407                 if (!inner) {
8408                         out_mpls_m =
8409                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
8410                                                          misc2_m,
8411                                                          outer_first_mpls);
8412                         out_mpls_v =
8413                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
8414                                                          misc2_v,
8415                                                          outer_first_mpls);
8416                 }
8417                 break;
8418         }
8419         if (out_mpls_m && out_mpls_v) {
8420                 *out_mpls_m = *in_mpls_m;
8421                 *out_mpls_v = *in_mpls_v & *in_mpls_m;
8422         }
8423 }
8424
8425 /**
8426  * Add metadata register item to matcher
8427  *
8428  * @param[in, out] matcher
8429  *   Flow matcher.
8430  * @param[in, out] key
8431  *   Flow matcher value.
8432  * @param[in] reg_type
8433  *   Type of device metadata register
8434  * @param[in] value
8435  *   Register value
8436  * @param[in] mask
8437  *   Register mask
8438  */
8439 static void
8440 flow_dv_match_meta_reg(void *matcher, void *key,
8441                        enum modify_reg reg_type,
8442                        uint32_t data, uint32_t mask)
8443 {
8444         void *misc2_m =
8445                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
8446         void *misc2_v =
8447                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
8448         uint32_t temp;
8449
8450         data &= mask;
8451         switch (reg_type) {
8452         case REG_A:
8453                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
8454                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
8455                 break;
8456         case REG_B:
8457                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
8458                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
8459                 break;
8460         case REG_C_0:
8461                 /*
8462                  * The metadata register C0 field might be divided into
8463                  * source vport index and META item value, we should set
8464                  * this field according to specified mask, not as whole one.
8465                  */
8466                 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
8467                 temp |= mask;
8468                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
8469                 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
8470                 temp &= ~mask;
8471                 temp |= data;
8472                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
8473                 break;
8474         case REG_C_1:
8475                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
8476                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
8477                 break;
8478         case REG_C_2:
8479                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
8480                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
8481                 break;
8482         case REG_C_3:
8483                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
8484                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
8485                 break;
8486         case REG_C_4:
8487                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
8488                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
8489                 break;
8490         case REG_C_5:
8491                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
8492                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
8493                 break;
8494         case REG_C_6:
8495                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
8496                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
8497                 break;
8498         case REG_C_7:
8499                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
8500                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
8501                 break;
8502         default:
8503                 MLX5_ASSERT(false);
8504                 break;
8505         }
8506 }
8507
8508 /**
8509  * Add MARK item to matcher
8510  *
8511  * @param[in] dev
8512  *   The device to configure through.
8513  * @param[in, out] matcher
8514  *   Flow matcher.
8515  * @param[in, out] key
8516  *   Flow matcher value.
8517  * @param[in] item
8518  *   Flow pattern to translate.
8519  */
8520 static void
8521 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
8522                             void *matcher, void *key,
8523                             const struct rte_flow_item *item)
8524 {
8525         struct mlx5_priv *priv = dev->data->dev_private;
8526         const struct rte_flow_item_mark *mark;
8527         uint32_t value;
8528         uint32_t mask;
8529
8530         mark = item->mask ? (const void *)item->mask :
8531                             &rte_flow_item_mark_mask;
8532         mask = mark->id & priv->sh->dv_mark_mask;
8533         mark = (const void *)item->spec;
8534         MLX5_ASSERT(mark);
8535         value = mark->id & priv->sh->dv_mark_mask & mask;
8536         if (mask) {
8537                 enum modify_reg reg;
8538
8539                 /* Get the metadata register index for the mark. */
8540                 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
8541                 MLX5_ASSERT(reg > 0);
8542                 if (reg == REG_C_0) {
8543                         struct mlx5_priv *priv = dev->data->dev_private;
8544                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
8545                         uint32_t shl_c0 = rte_bsf32(msk_c0);
8546
8547                         mask &= msk_c0;
8548                         mask <<= shl_c0;
8549                         value <<= shl_c0;
8550                 }
8551                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
8552         }
8553 }
8554
8555 /**
8556  * Add META item to matcher
8557  *
8558  * @param[in] dev
8559  *   The devich to configure through.
8560  * @param[in, out] matcher
8561  *   Flow matcher.
8562  * @param[in, out] key
8563  *   Flow matcher value.
8564  * @param[in] attr
8565  *   Attributes of flow that includes this item.
8566  * @param[in] item
8567  *   Flow pattern to translate.
8568  */
8569 static void
8570 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
8571                             void *matcher, void *key,
8572                             const struct rte_flow_attr *attr,
8573                             const struct rte_flow_item *item)
8574 {
8575         const struct rte_flow_item_meta *meta_m;
8576         const struct rte_flow_item_meta *meta_v;
8577
8578         meta_m = (const void *)item->mask;
8579         if (!meta_m)
8580                 meta_m = &rte_flow_item_meta_mask;
8581         meta_v = (const void *)item->spec;
8582         if (meta_v) {
8583                 int reg;
8584                 uint32_t value = meta_v->data;
8585                 uint32_t mask = meta_m->data;
8586
8587                 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
8588                 if (reg < 0)
8589                         return;
8590                 MLX5_ASSERT(reg != REG_NON);
8591                 /*
8592                  * In datapath code there is no endianness
8593                  * coversions for perfromance reasons, all
8594                  * pattern conversions are done in rte_flow.
8595                  */
8596                 value = rte_cpu_to_be_32(value);
8597                 mask = rte_cpu_to_be_32(mask);
8598                 if (reg == REG_C_0) {
8599                         struct mlx5_priv *priv = dev->data->dev_private;
8600                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
8601                         uint32_t shl_c0 = rte_bsf32(msk_c0);
8602 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
8603                         uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
8604
8605                         value >>= shr_c0;
8606                         mask >>= shr_c0;
8607 #endif
8608                         value <<= shl_c0;
8609                         mask <<= shl_c0;
8610                         MLX5_ASSERT(msk_c0);
8611                         MLX5_ASSERT(!(~msk_c0 & mask));
8612                 }
8613                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
8614         }
8615 }
8616
8617 /**
8618  * Add vport metadata Reg C0 item to matcher
8619  *
8620  * @param[in, out] matcher
8621  *   Flow matcher.
8622  * @param[in, out] key
8623  *   Flow matcher value.
8624  * @param[in] reg
8625  *   Flow pattern to translate.
8626  */
8627 static void
8628 flow_dv_translate_item_meta_vport(void *matcher, void *key,
8629                                   uint32_t value, uint32_t mask)
8630 {
8631         flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
8632 }
8633
8634 /**
8635  * Add tag item to matcher
8636  *
8637  * @param[in] dev
8638  *   The devich to configure through.
8639  * @param[in, out] matcher
8640  *   Flow matcher.
8641  * @param[in, out] key
8642  *   Flow matcher value.
8643  * @param[in] item
8644  *   Flow pattern to translate.
8645  */
8646 static void
8647 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
8648                                 void *matcher, void *key,
8649                                 const struct rte_flow_item *item)
8650 {
8651         const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
8652         const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
8653         uint32_t mask, value;
8654
8655         MLX5_ASSERT(tag_v);
8656         value = tag_v->data;
8657         mask = tag_m ? tag_m->data : UINT32_MAX;
8658         if (tag_v->id == REG_C_0) {
8659                 struct mlx5_priv *priv = dev->data->dev_private;
8660                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
8661                 uint32_t shl_c0 = rte_bsf32(msk_c0);
8662
8663                 mask &= msk_c0;
8664                 mask <<= shl_c0;
8665                 value <<= shl_c0;
8666         }
8667         flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
8668 }
8669
8670 /**
8671  * Add TAG item to matcher
8672  *
8673  * @param[in] dev
8674  *   The devich to configure through.
8675  * @param[in, out] matcher
8676  *   Flow matcher.
8677  * @param[in, out] key
8678  *   Flow matcher value.
8679  * @param[in] item
8680  *   Flow pattern to translate.
8681  */
8682 static void
8683 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
8684                            void *matcher, void *key,
8685                            const struct rte_flow_item *item)
8686 {
8687         const struct rte_flow_item_tag *tag_v = item->spec;
8688         const struct rte_flow_item_tag *tag_m = item->mask;
8689         enum modify_reg reg;
8690
8691         MLX5_ASSERT(tag_v);
8692         tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
8693         /* Get the metadata register index for the tag. */
8694         reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
8695         MLX5_ASSERT(reg > 0);
8696         flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
8697 }
8698
8699 /**
8700  * Add source vport match to the specified matcher.
8701  *
8702  * @param[in, out] matcher
8703  *   Flow matcher.
8704  * @param[in, out] key
8705  *   Flow matcher value.
8706  * @param[in] port
8707  *   Source vport value to match
8708  * @param[in] mask
8709  *   Mask
8710  */
8711 static void
8712 flow_dv_translate_item_source_vport(void *matcher, void *key,
8713                                     int16_t port, uint16_t mask)
8714 {
8715         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8716         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8717
8718         MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
8719         MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
8720 }
8721
8722 /**
8723  * Translate port-id item to eswitch match on  port-id.
8724  *
8725  * @param[in] dev
8726  *   The devich to configure through.
8727  * @param[in, out] matcher
8728  *   Flow matcher.
8729  * @param[in, out] key
8730  *   Flow matcher value.
8731  * @param[in] item
8732  *   Flow pattern to translate.
8733  * @param[in]
8734  *   Flow attributes.
8735  *
8736  * @return
8737  *   0 on success, a negative errno value otherwise.
8738  */
8739 static int
8740 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
8741                                void *key, const struct rte_flow_item *item,
8742                                const struct rte_flow_attr *attr)
8743 {
8744         const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
8745         const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
8746         struct mlx5_priv *priv;
8747         uint16_t mask, id;
8748
8749         mask = pid_m ? pid_m->id : 0xffff;
8750         id = pid_v ? pid_v->id : dev->data->port_id;
8751         priv = mlx5_port_to_eswitch_info(id, item == NULL);
8752         if (!priv)
8753                 return -rte_errno;
8754         /*
8755          * Translate to vport field or to metadata, depending on mode.
8756          * Kernel can use either misc.source_port or half of C0 metadata
8757          * register.
8758          */
8759         if (priv->vport_meta_mask) {
8760                 /*
8761                  * Provide the hint for SW steering library
8762                  * to insert the flow into ingress domain and
8763                  * save the extra vport match.
8764                  */
8765                 if (mask == 0xffff && priv->vport_id == 0xffff &&
8766                     priv->pf_bond < 0 && attr->transfer)
8767                         flow_dv_translate_item_source_vport
8768                                 (matcher, key, priv->vport_id, mask);
8769                 /*
8770                  * We should always set the vport metadata register,
8771                  * otherwise the SW steering library can drop
8772                  * the rule if wire vport metadata value is not zero,
8773                  * it depends on kernel configuration.
8774                  */
8775                 flow_dv_translate_item_meta_vport(matcher, key,
8776                                                   priv->vport_meta_tag,
8777                                                   priv->vport_meta_mask);
8778         } else {
8779                 flow_dv_translate_item_source_vport(matcher, key,
8780                                                     priv->vport_id, mask);
8781         }
8782         return 0;
8783 }
8784
8785 /**
8786  * Add ICMP6 item to matcher and to the value.
8787  *
8788  * @param[in, out] matcher
8789  *   Flow matcher.
8790  * @param[in, out] key
8791  *   Flow matcher value.
8792  * @param[in] item
8793  *   Flow pattern to translate.
8794  * @param[in] inner
8795  *   Item is inner pattern.
8796  */
8797 static void
8798 flow_dv_translate_item_icmp6(void *matcher, void *key,
8799                               const struct rte_flow_item *item,
8800                               int inner)
8801 {
8802         const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
8803         const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
8804         void *headers_m;
8805         void *headers_v;
8806         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8807                                      misc_parameters_3);
8808         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8809         if (inner) {
8810                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8811                                          inner_headers);
8812                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8813         } else {
8814                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8815                                          outer_headers);
8816                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8817         }
8818         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
8819         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
8820         if (!icmp6_v)
8821                 return;
8822         if (!icmp6_m)
8823                 icmp6_m = &rte_flow_item_icmp6_mask;
8824         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
8825         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
8826                  icmp6_v->type & icmp6_m->type);
8827         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
8828         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
8829                  icmp6_v->code & icmp6_m->code);
8830 }
8831
8832 /**
8833  * Add ICMP item to matcher and to the value.
8834  *
8835  * @param[in, out] matcher
8836  *   Flow matcher.
8837  * @param[in, out] key
8838  *   Flow matcher value.
8839  * @param[in] item
8840  *   Flow pattern to translate.
8841  * @param[in] inner
8842  *   Item is inner pattern.
8843  */
8844 static void
8845 flow_dv_translate_item_icmp(void *matcher, void *key,
8846                             const struct rte_flow_item *item,
8847                             int inner)
8848 {
8849         const struct rte_flow_item_icmp *icmp_m = item->mask;
8850         const struct rte_flow_item_icmp *icmp_v = item->spec;
8851         uint32_t icmp_header_data_m = 0;
8852         uint32_t icmp_header_data_v = 0;
8853         void *headers_m;
8854         void *headers_v;
8855         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8856                                      misc_parameters_3);
8857         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8858         if (inner) {
8859                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8860                                          inner_headers);
8861                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8862         } else {
8863                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8864                                          outer_headers);
8865                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8866         }
8867         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
8868         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
8869         if (!icmp_v)
8870                 return;
8871         if (!icmp_m)
8872                 icmp_m = &rte_flow_item_icmp_mask;
8873         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
8874                  icmp_m->hdr.icmp_type);
8875         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
8876                  icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
8877         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
8878                  icmp_m->hdr.icmp_code);
8879         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
8880                  icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
8881         icmp_header_data_m = rte_be_to_cpu_16(icmp_m->hdr.icmp_seq_nb);
8882         icmp_header_data_m |= rte_be_to_cpu_16(icmp_m->hdr.icmp_ident) << 16;
8883         if (icmp_header_data_m) {
8884                 icmp_header_data_v = rte_be_to_cpu_16(icmp_v->hdr.icmp_seq_nb);
8885                 icmp_header_data_v |=
8886                          rte_be_to_cpu_16(icmp_v->hdr.icmp_ident) << 16;
8887                 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_header_data,
8888                          icmp_header_data_m);
8889                 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_header_data,
8890                          icmp_header_data_v & icmp_header_data_m);
8891         }
8892 }
8893
8894 /**
8895  * Add GTP item to matcher and to the value.
8896  *
8897  * @param[in, out] matcher
8898  *   Flow matcher.
8899  * @param[in, out] key
8900  *   Flow matcher value.
8901  * @param[in] item
8902  *   Flow pattern to translate.
8903  * @param[in] inner
8904  *   Item is inner pattern.
8905  */
8906 static void
8907 flow_dv_translate_item_gtp(void *matcher, void *key,
8908                            const struct rte_flow_item *item, int inner)
8909 {
8910         const struct rte_flow_item_gtp *gtp_m = item->mask;
8911         const struct rte_flow_item_gtp *gtp_v = item->spec;
8912         void *headers_m;
8913         void *headers_v;
8914         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8915                                      misc_parameters_3);
8916         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8917         uint16_t dport = RTE_GTPU_UDP_PORT;
8918
8919         if (inner) {
8920                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8921                                          inner_headers);
8922                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8923         } else {
8924                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8925                                          outer_headers);
8926                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8927         }
8928         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8929                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8930                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8931         }
8932         if (!gtp_v)
8933                 return;
8934         if (!gtp_m)
8935                 gtp_m = &rte_flow_item_gtp_mask;
8936         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags,
8937                  gtp_m->v_pt_rsv_flags);
8938         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags,
8939                  gtp_v->v_pt_rsv_flags & gtp_m->v_pt_rsv_flags);
8940         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
8941         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
8942                  gtp_v->msg_type & gtp_m->msg_type);
8943         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
8944                  rte_be_to_cpu_32(gtp_m->teid));
8945         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
8946                  rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
8947 }
8948
8949 /**
8950  * Add GTP PSC item to matcher.
8951  *
8952  * @param[in, out] matcher
8953  *   Flow matcher.
8954  * @param[in, out] key
8955  *   Flow matcher value.
8956  * @param[in] item
8957  *   Flow pattern to translate.
8958  */
8959 static int
8960 flow_dv_translate_item_gtp_psc(void *matcher, void *key,
8961                                const struct rte_flow_item *item)
8962 {
8963         const struct rte_flow_item_gtp_psc *gtp_psc_m = item->mask;
8964         const struct rte_flow_item_gtp_psc *gtp_psc_v = item->spec;
8965         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8966                         misc_parameters_3);
8967         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8968         union {
8969                 uint32_t w32;
8970                 struct {
8971                         uint16_t seq_num;
8972                         uint8_t npdu_num;
8973                         uint8_t next_ext_header_type;
8974                 };
8975         } dw_2;
8976         uint8_t gtp_flags;
8977
8978         /* Always set E-flag match on one, regardless of GTP item settings. */
8979         gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_m, gtpu_msg_flags);
8980         gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
8981         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags, gtp_flags);
8982         gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_v, gtpu_msg_flags);
8983         gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
8984         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags, gtp_flags);
8985         /*Set next extension header type. */
8986         dw_2.seq_num = 0;
8987         dw_2.npdu_num = 0;
8988         dw_2.next_ext_header_type = 0xff;
8989         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_dw_2,
8990                  rte_cpu_to_be_32(dw_2.w32));
8991         dw_2.seq_num = 0;
8992         dw_2.npdu_num = 0;
8993         dw_2.next_ext_header_type = 0x85;
8994         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_dw_2,
8995                  rte_cpu_to_be_32(dw_2.w32));
8996         if (gtp_psc_v) {
8997                 union {
8998                         uint32_t w32;
8999                         struct {
9000                                 uint8_t len;
9001                                 uint8_t type_flags;
9002                                 uint8_t qfi;
9003                                 uint8_t reserved;
9004                         };
9005                 } dw_0;
9006
9007                 /*Set extension header PDU type and Qos. */
9008                 if (!gtp_psc_m)
9009                         gtp_psc_m = &rte_flow_item_gtp_psc_mask;
9010                 dw_0.w32 = 0;
9011                 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_m->pdu_type);
9012                 dw_0.qfi = gtp_psc_m->qfi;
9013                 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_first_ext_dw_0,
9014                          rte_cpu_to_be_32(dw_0.w32));
9015                 dw_0.w32 = 0;
9016                 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_v->pdu_type &
9017                                                         gtp_psc_m->pdu_type);
9018                 dw_0.qfi = gtp_psc_v->qfi & gtp_psc_m->qfi;
9019                 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_first_ext_dw_0,
9020                          rte_cpu_to_be_32(dw_0.w32));
9021         }
9022         return 0;
9023 }
9024
9025 /**
9026  * Add eCPRI item to matcher and to the value.
9027  *
9028  * @param[in] dev
9029  *   The devich to configure through.
9030  * @param[in, out] matcher
9031  *   Flow matcher.
9032  * @param[in, out] key
9033  *   Flow matcher value.
9034  * @param[in] item
9035  *   Flow pattern to translate.
9036  * @param[in] samples
9037  *   Sample IDs to be used in the matching.
9038  */
9039 static void
9040 flow_dv_translate_item_ecpri(struct rte_eth_dev *dev, void *matcher,
9041                              void *key, const struct rte_flow_item *item)
9042 {
9043         struct mlx5_priv *priv = dev->data->dev_private;
9044         const struct rte_flow_item_ecpri *ecpri_m = item->mask;
9045         const struct rte_flow_item_ecpri *ecpri_v = item->spec;
9046         struct rte_ecpri_common_hdr common;
9047         void *misc4_m = MLX5_ADDR_OF(fte_match_param, matcher,
9048                                      misc_parameters_4);
9049         void *misc4_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_4);
9050         uint32_t *samples;
9051         void *dw_m;
9052         void *dw_v;
9053
9054         if (!ecpri_v)
9055                 return;
9056         if (!ecpri_m)
9057                 ecpri_m = &rte_flow_item_ecpri_mask;
9058         /*
9059          * Maximal four DW samples are supported in a single matching now.
9060          * Two are used now for a eCPRI matching:
9061          * 1. Type: one byte, mask should be 0x00ff0000 in network order
9062          * 2. ID of a message: one or two bytes, mask 0xffff0000 or 0xff000000
9063          *    if any.
9064          */
9065         if (!ecpri_m->hdr.common.u32)
9066                 return;
9067         samples = priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0].ids;
9068         /* Need to take the whole DW as the mask to fill the entry. */
9069         dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
9070                             prog_sample_field_value_0);
9071         dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
9072                             prog_sample_field_value_0);
9073         /* Already big endian (network order) in the header. */
9074         *(uint32_t *)dw_m = ecpri_m->hdr.common.u32;
9075         *(uint32_t *)dw_v = ecpri_v->hdr.common.u32 & ecpri_m->hdr.common.u32;
9076         /* Sample#0, used for matching type, offset 0. */
9077         MLX5_SET(fte_match_set_misc4, misc4_m,
9078                  prog_sample_field_id_0, samples[0]);
9079         /* It makes no sense to set the sample ID in the mask field. */
9080         MLX5_SET(fte_match_set_misc4, misc4_v,
9081                  prog_sample_field_id_0, samples[0]);
9082         /*
9083          * Checking if message body part needs to be matched.
9084          * Some wildcard rules only matching type field should be supported.
9085          */
9086         if (ecpri_m->hdr.dummy[0]) {
9087                 common.u32 = rte_be_to_cpu_32(ecpri_v->hdr.common.u32);
9088                 switch (common.type) {
9089                 case RTE_ECPRI_MSG_TYPE_IQ_DATA:
9090                 case RTE_ECPRI_MSG_TYPE_RTC_CTRL:
9091                 case RTE_ECPRI_MSG_TYPE_DLY_MSR:
9092                         dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
9093                                             prog_sample_field_value_1);
9094                         dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
9095                                             prog_sample_field_value_1);
9096                         *(uint32_t *)dw_m = ecpri_m->hdr.dummy[0];
9097                         *(uint32_t *)dw_v = ecpri_v->hdr.dummy[0] &
9098                                             ecpri_m->hdr.dummy[0];
9099                         /* Sample#1, to match message body, offset 4. */
9100                         MLX5_SET(fte_match_set_misc4, misc4_m,
9101                                  prog_sample_field_id_1, samples[1]);
9102                         MLX5_SET(fte_match_set_misc4, misc4_v,
9103                                  prog_sample_field_id_1, samples[1]);
9104                         break;
9105                 default:
9106                         /* Others, do not match any sample ID. */
9107                         break;
9108                 }
9109         }
9110 }
9111
9112 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
9113
9114 #define HEADER_IS_ZERO(match_criteria, headers)                              \
9115         !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers),     \
9116                  matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
9117
9118 /**
9119  * Calculate flow matcher enable bitmap.
9120  *
9121  * @param match_criteria
9122  *   Pointer to flow matcher criteria.
9123  *
9124  * @return
9125  *   Bitmap of enabled fields.
9126  */
9127 static uint8_t
9128 flow_dv_matcher_enable(uint32_t *match_criteria)
9129 {
9130         uint8_t match_criteria_enable;
9131
9132         match_criteria_enable =
9133                 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
9134                 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
9135         match_criteria_enable |=
9136                 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
9137                 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
9138         match_criteria_enable |=
9139                 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
9140                 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
9141         match_criteria_enable |=
9142                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
9143                 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
9144         match_criteria_enable |=
9145                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
9146                 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
9147         match_criteria_enable |=
9148                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_4)) <<
9149                 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT;
9150         return match_criteria_enable;
9151 }
9152
9153 struct mlx5_hlist_entry *
9154 flow_dv_tbl_create_cb(struct mlx5_hlist *list, uint64_t key64, void *cb_ctx)
9155 {
9156         struct mlx5_dev_ctx_shared *sh = list->ctx;
9157         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9158         struct rte_eth_dev *dev = ctx->dev;
9159         struct mlx5_flow_tbl_data_entry *tbl_data;
9160         struct mlx5_flow_tbl_tunnel_prm *tt_prm = ctx->data;
9161         struct rte_flow_error *error = ctx->error;
9162         union mlx5_flow_tbl_key key = { .v64 = key64 };
9163         struct mlx5_flow_tbl_resource *tbl;
9164         void *domain;
9165         uint32_t idx = 0;
9166         int ret;
9167
9168         tbl_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
9169         if (!tbl_data) {
9170                 rte_flow_error_set(error, ENOMEM,
9171                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9172                                    NULL,
9173                                    "cannot allocate flow table data entry");
9174                 return NULL;
9175         }
9176         tbl_data->idx = idx;
9177         tbl_data->tunnel = tt_prm->tunnel;
9178         tbl_data->group_id = tt_prm->group_id;
9179         tbl_data->external = !!tt_prm->external;
9180         tbl_data->tunnel_offload = is_tunnel_offload_active(dev);
9181         tbl_data->is_egress = !!key.direction;
9182         tbl_data->is_transfer = !!key.domain;
9183         tbl_data->dummy = !!key.dummy;
9184         tbl_data->table_id = key.table_id;
9185         tbl = &tbl_data->tbl;
9186         if (key.dummy)
9187                 return &tbl_data->entry;
9188         if (key.domain)
9189                 domain = sh->fdb_domain;
9190         else if (key.direction)
9191                 domain = sh->tx_domain;
9192         else
9193                 domain = sh->rx_domain;
9194         ret = mlx5_flow_os_create_flow_tbl(domain, key.table_id, &tbl->obj);
9195         if (ret) {
9196                 rte_flow_error_set(error, ENOMEM,
9197                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9198                                    NULL, "cannot create flow table object");
9199                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
9200                 return NULL;
9201         }
9202         if (key.table_id) {
9203                 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
9204                                         (tbl->obj, &tbl_data->jump.action);
9205                 if (ret) {
9206                         rte_flow_error_set(error, ENOMEM,
9207                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9208                                            NULL,
9209                                            "cannot create flow jump action");
9210                         mlx5_flow_os_destroy_flow_tbl(tbl->obj);
9211                         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
9212                         return NULL;
9213                 }
9214         }
9215         MKSTR(matcher_name, "%s_%s_%u_matcher_cache",
9216               key.domain ? "FDB" : "NIC", key.direction ? "egress" : "ingress",
9217               key.table_id);
9218         mlx5_cache_list_init(&tbl_data->matchers, matcher_name, 0, sh,
9219                              flow_dv_matcher_create_cb,
9220                              flow_dv_matcher_match_cb,
9221                              flow_dv_matcher_remove_cb);
9222         return &tbl_data->entry;
9223 }
9224
9225 int
9226 flow_dv_tbl_match_cb(struct mlx5_hlist *list __rte_unused,
9227                      struct mlx5_hlist_entry *entry, uint64_t key64,
9228                      void *cb_ctx __rte_unused)
9229 {
9230         struct mlx5_flow_tbl_data_entry *tbl_data =
9231                 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
9232         union mlx5_flow_tbl_key key = { .v64 = key64 };
9233
9234         return tbl_data->table_id != key.table_id ||
9235                tbl_data->dummy != key.dummy ||
9236                tbl_data->is_transfer != key.domain ||
9237                tbl_data->is_egress != key.direction;
9238 }
9239
9240 /**
9241  * Get a flow table.
9242  *
9243  * @param[in, out] dev
9244  *   Pointer to rte_eth_dev structure.
9245  * @param[in] table_id
9246  *   Table id to use.
9247  * @param[in] egress
9248  *   Direction of the table.
9249  * @param[in] transfer
9250  *   E-Switch or NIC flow.
9251  * @param[in] dummy
9252  *   Dummy entry for dv API.
9253  * @param[out] error
9254  *   pointer to error structure.
9255  *
9256  * @return
9257  *   Returns tables resource based on the index, NULL in case of failed.
9258  */
9259 struct mlx5_flow_tbl_resource *
9260 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
9261                          uint32_t table_id, uint8_t egress,
9262                          uint8_t transfer,
9263                          bool external,
9264                          const struct mlx5_flow_tunnel *tunnel,
9265                          uint32_t group_id, uint8_t dummy,
9266                          struct rte_flow_error *error)
9267 {
9268         struct mlx5_priv *priv = dev->data->dev_private;
9269         union mlx5_flow_tbl_key table_key = {
9270                 {
9271                         .table_id = table_id,
9272                         .dummy = dummy,
9273                         .domain = !!transfer,
9274                         .direction = !!egress,
9275                 }
9276         };
9277         struct mlx5_flow_tbl_tunnel_prm tt_prm = {
9278                 .tunnel = tunnel,
9279                 .group_id = group_id,
9280                 .external = external,
9281         };
9282         struct mlx5_flow_cb_ctx ctx = {
9283                 .dev = dev,
9284                 .error = error,
9285                 .data = &tt_prm,
9286         };
9287         struct mlx5_hlist_entry *entry;
9288         struct mlx5_flow_tbl_data_entry *tbl_data;
9289
9290         entry = mlx5_hlist_register(priv->sh->flow_tbls, table_key.v64, &ctx);
9291         if (!entry) {
9292                 rte_flow_error_set(error, ENOMEM,
9293                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9294                                    "cannot get table");
9295                 return NULL;
9296         }
9297         DRV_LOG(DEBUG, "Table_id %u tunnel %u group %u registered.",
9298                 table_id, tunnel ? tunnel->tunnel_id : 0, group_id);
9299         tbl_data = container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
9300         return &tbl_data->tbl;
9301 }
9302
9303 void
9304 flow_dv_tbl_remove_cb(struct mlx5_hlist *list,
9305                       struct mlx5_hlist_entry *entry)
9306 {
9307         struct mlx5_dev_ctx_shared *sh = list->ctx;
9308         struct mlx5_flow_tbl_data_entry *tbl_data =
9309                 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
9310
9311         MLX5_ASSERT(entry && sh);
9312         if (tbl_data->jump.action)
9313                 mlx5_flow_os_destroy_flow_action(tbl_data->jump.action);
9314         if (tbl_data->tbl.obj)
9315                 mlx5_flow_os_destroy_flow_tbl(tbl_data->tbl.obj);
9316         if (tbl_data->tunnel_offload && tbl_data->external) {
9317                 struct mlx5_hlist_entry *he;
9318                 struct mlx5_hlist *tunnel_grp_hash;
9319                 struct mlx5_flow_tunnel_hub *thub = sh->tunnel_hub;
9320                 union tunnel_tbl_key tunnel_key = {
9321                         .tunnel_id = tbl_data->tunnel ?
9322                                         tbl_data->tunnel->tunnel_id : 0,
9323                         .group = tbl_data->group_id
9324                 };
9325                 uint32_t table_id = tbl_data->table_id;
9326
9327                 tunnel_grp_hash = tbl_data->tunnel ?
9328                                         tbl_data->tunnel->groups :
9329                                         thub->groups;
9330                 he = mlx5_hlist_lookup(tunnel_grp_hash, tunnel_key.val, NULL);
9331                 if (he)
9332                         mlx5_hlist_unregister(tunnel_grp_hash, he);
9333                 DRV_LOG(DEBUG,
9334                         "Table_id %u tunnel %u group %u released.",
9335                         table_id,
9336                         tbl_data->tunnel ?
9337                         tbl_data->tunnel->tunnel_id : 0,
9338                         tbl_data->group_id);
9339         }
9340         mlx5_cache_list_destroy(&tbl_data->matchers);
9341         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], tbl_data->idx);
9342 }
9343
9344 /**
9345  * Release a flow table.
9346  *
9347  * @param[in] sh
9348  *   Pointer to device shared structure.
9349  * @param[in] tbl
9350  *   Table resource to be released.
9351  *
9352  * @return
9353  *   Returns 0 if table was released, else return 1;
9354  */
9355 static int
9356 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
9357                              struct mlx5_flow_tbl_resource *tbl)
9358 {
9359         struct mlx5_flow_tbl_data_entry *tbl_data =
9360                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
9361
9362         if (!tbl)
9363                 return 0;
9364         return mlx5_hlist_unregister(sh->flow_tbls, &tbl_data->entry);
9365 }
9366
9367 int
9368 flow_dv_matcher_match_cb(struct mlx5_cache_list *list __rte_unused,
9369                          struct mlx5_cache_entry *entry, void *cb_ctx)
9370 {
9371         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9372         struct mlx5_flow_dv_matcher *ref = ctx->data;
9373         struct mlx5_flow_dv_matcher *cur = container_of(entry, typeof(*cur),
9374                                                         entry);
9375
9376         return cur->crc != ref->crc ||
9377                cur->priority != ref->priority ||
9378                memcmp((const void *)cur->mask.buf,
9379                       (const void *)ref->mask.buf, ref->mask.size);
9380 }
9381
9382 struct mlx5_cache_entry *
9383 flow_dv_matcher_create_cb(struct mlx5_cache_list *list,
9384                           struct mlx5_cache_entry *entry __rte_unused,
9385                           void *cb_ctx)
9386 {
9387         struct mlx5_dev_ctx_shared *sh = list->ctx;
9388         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9389         struct mlx5_flow_dv_matcher *ref = ctx->data;
9390         struct mlx5_flow_dv_matcher *cache;
9391         struct mlx5dv_flow_matcher_attr dv_attr = {
9392                 .type = IBV_FLOW_ATTR_NORMAL,
9393                 .match_mask = (void *)&ref->mask,
9394         };
9395         struct mlx5_flow_tbl_data_entry *tbl = container_of(ref->tbl,
9396                                                             typeof(*tbl), tbl);
9397         int ret;
9398
9399         cache = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*cache), 0, SOCKET_ID_ANY);
9400         if (!cache) {
9401                 rte_flow_error_set(ctx->error, ENOMEM,
9402                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9403                                    "cannot create matcher");
9404                 return NULL;
9405         }
9406         *cache = *ref;
9407         dv_attr.match_criteria_enable =
9408                 flow_dv_matcher_enable(cache->mask.buf);
9409         dv_attr.priority = ref->priority;
9410         if (tbl->is_egress)
9411                 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
9412         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->tbl.obj,
9413                                                &cache->matcher_object);
9414         if (ret) {
9415                 mlx5_free(cache);
9416                 rte_flow_error_set(ctx->error, ENOMEM,
9417                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9418                                    "cannot create matcher");
9419                 return NULL;
9420         }
9421         return &cache->entry;
9422 }
9423
9424 /**
9425  * Register the flow matcher.
9426  *
9427  * @param[in, out] dev
9428  *   Pointer to rte_eth_dev structure.
9429  * @param[in, out] matcher
9430  *   Pointer to flow matcher.
9431  * @param[in, out] key
9432  *   Pointer to flow table key.
9433  * @parm[in, out] dev_flow
9434  *   Pointer to the dev_flow.
9435  * @param[out] error
9436  *   pointer to error structure.
9437  *
9438  * @return
9439  *   0 on success otherwise -errno and errno is set.
9440  */
9441 static int
9442 flow_dv_matcher_register(struct rte_eth_dev *dev,
9443                          struct mlx5_flow_dv_matcher *ref,
9444                          union mlx5_flow_tbl_key *key,
9445                          struct mlx5_flow *dev_flow,
9446                          const struct mlx5_flow_tunnel *tunnel,
9447                          uint32_t group_id,
9448                          struct rte_flow_error *error)
9449 {
9450         struct mlx5_cache_entry *entry;
9451         struct mlx5_flow_dv_matcher *cache;
9452         struct mlx5_flow_tbl_resource *tbl;
9453         struct mlx5_flow_tbl_data_entry *tbl_data;
9454         struct mlx5_flow_cb_ctx ctx = {
9455                 .error = error,
9456                 .data = ref,
9457         };
9458
9459         /**
9460          * tunnel offload API requires this registration for cases when
9461          * tunnel match rule was inserted before tunnel set rule.
9462          */
9463         tbl = flow_dv_tbl_resource_get(dev, key->table_id,
9464                                        key->direction, key->domain,
9465                                        dev_flow->external, tunnel,
9466                                        group_id, 0, error);
9467         if (!tbl)
9468                 return -rte_errno;      /* No need to refill the error info */
9469         tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
9470         ref->tbl = tbl;
9471         entry = mlx5_cache_register(&tbl_data->matchers, &ctx);
9472         if (!entry) {
9473                 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
9474                 return rte_flow_error_set(error, ENOMEM,
9475                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9476                                           "cannot allocate ref memory");
9477         }
9478         cache = container_of(entry, typeof(*cache), entry);
9479         dev_flow->handle->dvh.matcher = cache;
9480         return 0;
9481 }
9482
9483 struct mlx5_hlist_entry *
9484 flow_dv_tag_create_cb(struct mlx5_hlist *list, uint64_t key, void *ctx)
9485 {
9486         struct mlx5_dev_ctx_shared *sh = list->ctx;
9487         struct rte_flow_error *error = ctx;
9488         struct mlx5_flow_dv_tag_resource *entry;
9489         uint32_t idx = 0;
9490         int ret;
9491
9492         entry = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_TAG], &idx);
9493         if (!entry) {
9494                 rte_flow_error_set(error, ENOMEM,
9495                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9496                                    "cannot allocate resource memory");
9497                 return NULL;
9498         }
9499         entry->idx = idx;
9500         entry->tag_id = key;
9501         ret = mlx5_flow_os_create_flow_action_tag(key,
9502                                                   &entry->action);
9503         if (ret) {
9504                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], idx);
9505                 rte_flow_error_set(error, ENOMEM,
9506                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9507                                    NULL, "cannot create action");
9508                 return NULL;
9509         }
9510         return &entry->entry;
9511 }
9512
9513 int
9514 flow_dv_tag_match_cb(struct mlx5_hlist *list __rte_unused,
9515                      struct mlx5_hlist_entry *entry, uint64_t key,
9516                      void *cb_ctx __rte_unused)
9517 {
9518         struct mlx5_flow_dv_tag_resource *tag =
9519                 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
9520
9521         return key != tag->tag_id;
9522 }
9523
9524 /**
9525  * Find existing tag resource or create and register a new one.
9526  *
9527  * @param dev[in, out]
9528  *   Pointer to rte_eth_dev structure.
9529  * @param[in, out] tag_be24
9530  *   Tag value in big endian then R-shift 8.
9531  * @parm[in, out] dev_flow
9532  *   Pointer to the dev_flow.
9533  * @param[out] error
9534  *   pointer to error structure.
9535  *
9536  * @return
9537  *   0 on success otherwise -errno and errno is set.
9538  */
9539 static int
9540 flow_dv_tag_resource_register
9541                         (struct rte_eth_dev *dev,
9542                          uint32_t tag_be24,
9543                          struct mlx5_flow *dev_flow,
9544                          struct rte_flow_error *error)
9545 {
9546         struct mlx5_priv *priv = dev->data->dev_private;
9547         struct mlx5_flow_dv_tag_resource *cache_resource;
9548         struct mlx5_hlist_entry *entry;
9549
9550         entry = mlx5_hlist_register(priv->sh->tag_table, tag_be24, error);
9551         if (entry) {
9552                 cache_resource = container_of
9553                         (entry, struct mlx5_flow_dv_tag_resource, entry);
9554                 dev_flow->handle->dvh.rix_tag = cache_resource->idx;
9555                 dev_flow->dv.tag_resource = cache_resource;
9556                 return 0;
9557         }
9558         return -rte_errno;
9559 }
9560
9561 void
9562 flow_dv_tag_remove_cb(struct mlx5_hlist *list,
9563                       struct mlx5_hlist_entry *entry)
9564 {
9565         struct mlx5_dev_ctx_shared *sh = list->ctx;
9566         struct mlx5_flow_dv_tag_resource *tag =
9567                 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
9568
9569         MLX5_ASSERT(tag && sh && tag->action);
9570         claim_zero(mlx5_flow_os_destroy_flow_action(tag->action));
9571         DRV_LOG(DEBUG, "Tag %p: removed.", (void *)tag);
9572         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], tag->idx);
9573 }
9574
9575 /**
9576  * Release the tag.
9577  *
9578  * @param dev
9579  *   Pointer to Ethernet device.
9580  * @param tag_idx
9581  *   Tag index.
9582  *
9583  * @return
9584  *   1 while a reference on it exists, 0 when freed.
9585  */
9586 static int
9587 flow_dv_tag_release(struct rte_eth_dev *dev,
9588                     uint32_t tag_idx)
9589 {
9590         struct mlx5_priv *priv = dev->data->dev_private;
9591         struct mlx5_flow_dv_tag_resource *tag;
9592
9593         tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
9594         if (!tag)
9595                 return 0;
9596         DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
9597                 dev->data->port_id, (void *)tag, tag->entry.ref_cnt);
9598         return mlx5_hlist_unregister(priv->sh->tag_table, &tag->entry);
9599 }
9600
9601 /**
9602  * Translate port ID action to vport.
9603  *
9604  * @param[in] dev
9605  *   Pointer to rte_eth_dev structure.
9606  * @param[in] action
9607  *   Pointer to the port ID action.
9608  * @param[out] dst_port_id
9609  *   The target port ID.
9610  * @param[out] error
9611  *   Pointer to the error structure.
9612  *
9613  * @return
9614  *   0 on success, a negative errno value otherwise and rte_errno is set.
9615  */
9616 static int
9617 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
9618                                  const struct rte_flow_action *action,
9619                                  uint32_t *dst_port_id,
9620                                  struct rte_flow_error *error)
9621 {
9622         uint32_t port;
9623         struct mlx5_priv *priv;
9624         const struct rte_flow_action_port_id *conf =
9625                         (const struct rte_flow_action_port_id *)action->conf;
9626
9627         port = conf->original ? dev->data->port_id : conf->id;
9628         priv = mlx5_port_to_eswitch_info(port, false);
9629         if (!priv)
9630                 return rte_flow_error_set(error, -rte_errno,
9631                                           RTE_FLOW_ERROR_TYPE_ACTION,
9632                                           NULL,
9633                                           "No eswitch info was found for port");
9634 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
9635         /*
9636          * This parameter is transferred to
9637          * mlx5dv_dr_action_create_dest_ib_port().
9638          */
9639         *dst_port_id = priv->dev_port;
9640 #else
9641         /*
9642          * Legacy mode, no LAG configurations is supported.
9643          * This parameter is transferred to
9644          * mlx5dv_dr_action_create_dest_vport().
9645          */
9646         *dst_port_id = priv->vport_id;
9647 #endif
9648         return 0;
9649 }
9650
9651 /**
9652  * Create a counter with aging configuration.
9653  *
9654  * @param[in] dev
9655  *   Pointer to rte_eth_dev structure.
9656  * @param[out] count
9657  *   Pointer to the counter action configuration.
9658  * @param[in] age
9659  *   Pointer to the aging action configuration.
9660  *
9661  * @return
9662  *   Index to flow counter on success, 0 otherwise.
9663  */
9664 static uint32_t
9665 flow_dv_translate_create_counter(struct rte_eth_dev *dev,
9666                                 struct mlx5_flow *dev_flow,
9667                                 const struct rte_flow_action_count *count,
9668                                 const struct rte_flow_action_age *age)
9669 {
9670         uint32_t counter;
9671         struct mlx5_age_param *age_param;
9672
9673         if (count && count->shared)
9674                 counter = flow_dv_counter_get_shared(dev, count->id);
9675         else
9676                 counter = flow_dv_counter_alloc(dev, !!age);
9677         if (!counter || age == NULL)
9678                 return counter;
9679         age_param  = flow_dv_counter_idx_get_age(dev, counter);
9680         age_param->context = age->context ? age->context :
9681                 (void *)(uintptr_t)(dev_flow->flow_idx);
9682         age_param->timeout = age->timeout;
9683         age_param->port_id = dev->data->port_id;
9684         __atomic_store_n(&age_param->sec_since_last_hit, 0, __ATOMIC_RELAXED);
9685         __atomic_store_n(&age_param->state, AGE_CANDIDATE, __ATOMIC_RELAXED);
9686         return counter;
9687 }
9688
9689 /**
9690  * Add Tx queue matcher
9691  *
9692  * @param[in] dev
9693  *   Pointer to the dev struct.
9694  * @param[in, out] matcher
9695  *   Flow matcher.
9696  * @param[in, out] key
9697  *   Flow matcher value.
9698  * @param[in] item
9699  *   Flow pattern to translate.
9700  * @param[in] inner
9701  *   Item is inner pattern.
9702  */
9703 static void
9704 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
9705                                 void *matcher, void *key,
9706                                 const struct rte_flow_item *item)
9707 {
9708         const struct mlx5_rte_flow_item_tx_queue *queue_m;
9709         const struct mlx5_rte_flow_item_tx_queue *queue_v;
9710         void *misc_m =
9711                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
9712         void *misc_v =
9713                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
9714         struct mlx5_txq_ctrl *txq;
9715         uint32_t queue;
9716
9717
9718         queue_m = (const void *)item->mask;
9719         if (!queue_m)
9720                 return;
9721         queue_v = (const void *)item->spec;
9722         if (!queue_v)
9723                 return;
9724         txq = mlx5_txq_get(dev, queue_v->queue);
9725         if (!txq)
9726                 return;
9727         queue = txq->obj->sq->id;
9728         MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
9729         MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
9730                  queue & queue_m->queue);
9731         mlx5_txq_release(dev, queue_v->queue);
9732 }
9733
9734 /**
9735  * Set the hash fields according to the @p flow information.
9736  *
9737  * @param[in] dev_flow
9738  *   Pointer to the mlx5_flow.
9739  * @param[in] rss_desc
9740  *   Pointer to the mlx5_flow_rss_desc.
9741  */
9742 static void
9743 flow_dv_hashfields_set(struct mlx5_flow *dev_flow,
9744                        struct mlx5_flow_rss_desc *rss_desc)
9745 {
9746         uint64_t items = dev_flow->handle->layers;
9747         int rss_inner = 0;
9748         uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
9749
9750         dev_flow->hash_fields = 0;
9751 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
9752         if (rss_desc->level >= 2) {
9753                 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
9754                 rss_inner = 1;
9755         }
9756 #endif
9757         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
9758             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
9759                 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
9760                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
9761                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
9762                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
9763                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
9764                         else
9765                                 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
9766                 }
9767         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
9768                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
9769                 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
9770                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
9771                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
9772                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
9773                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
9774                         else
9775                                 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
9776                 }
9777         }
9778         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
9779             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
9780                 if (rss_types & ETH_RSS_UDP) {
9781                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
9782                                 dev_flow->hash_fields |=
9783                                                 IBV_RX_HASH_SRC_PORT_UDP;
9784                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
9785                                 dev_flow->hash_fields |=
9786                                                 IBV_RX_HASH_DST_PORT_UDP;
9787                         else
9788                                 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
9789                 }
9790         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
9791                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
9792                 if (rss_types & ETH_RSS_TCP) {
9793                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
9794                                 dev_flow->hash_fields |=
9795                                                 IBV_RX_HASH_SRC_PORT_TCP;
9796                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
9797                                 dev_flow->hash_fields |=
9798                                                 IBV_RX_HASH_DST_PORT_TCP;
9799                         else
9800                                 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
9801                 }
9802         }
9803 }
9804
9805 /**
9806  * Prepare an Rx Hash queue.
9807  *
9808  * @param dev
9809  *   Pointer to Ethernet device.
9810  * @param[in] dev_flow
9811  *   Pointer to the mlx5_flow.
9812  * @param[in] rss_desc
9813  *   Pointer to the mlx5_flow_rss_desc.
9814  * @param[out] hrxq_idx
9815  *   Hash Rx queue index.
9816  *
9817  * @return
9818  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
9819  */
9820 static struct mlx5_hrxq *
9821 flow_dv_hrxq_prepare(struct rte_eth_dev *dev,
9822                      struct mlx5_flow *dev_flow,
9823                      struct mlx5_flow_rss_desc *rss_desc,
9824                      uint32_t *hrxq_idx)
9825 {
9826         struct mlx5_priv *priv = dev->data->dev_private;
9827         struct mlx5_flow_handle *dh = dev_flow->handle;
9828         struct mlx5_hrxq *hrxq;
9829
9830         MLX5_ASSERT(rss_desc->queue_num);
9831         rss_desc->key_len = MLX5_RSS_HASH_KEY_LEN;
9832         rss_desc->hash_fields = dev_flow->hash_fields;
9833         rss_desc->tunnel = !!(dh->layers & MLX5_FLOW_LAYER_TUNNEL);
9834         rss_desc->shared_rss = 0;
9835         *hrxq_idx = mlx5_hrxq_get(dev, rss_desc);
9836         if (!*hrxq_idx)
9837                 return NULL;
9838         hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
9839                               *hrxq_idx);
9840         return hrxq;
9841 }
9842
9843 /**
9844  * Release sample sub action resource.
9845  *
9846  * @param[in, out] dev
9847  *   Pointer to rte_eth_dev structure.
9848  * @param[in] act_res
9849  *   Pointer to sample sub action resource.
9850  */
9851 static void
9852 flow_dv_sample_sub_actions_release(struct rte_eth_dev *dev,
9853                                    struct mlx5_flow_sub_actions_idx *act_res)
9854 {
9855         if (act_res->rix_hrxq) {
9856                 mlx5_hrxq_release(dev, act_res->rix_hrxq);
9857                 act_res->rix_hrxq = 0;
9858         }
9859         if (act_res->rix_encap_decap) {
9860                 flow_dv_encap_decap_resource_release(dev,
9861                                                      act_res->rix_encap_decap);
9862                 act_res->rix_encap_decap = 0;
9863         }
9864         if (act_res->rix_port_id_action) {
9865                 flow_dv_port_id_action_resource_release(dev,
9866                                                 act_res->rix_port_id_action);
9867                 act_res->rix_port_id_action = 0;
9868         }
9869         if (act_res->rix_tag) {
9870                 flow_dv_tag_release(dev, act_res->rix_tag);
9871                 act_res->rix_tag = 0;
9872         }
9873         if (act_res->rix_jump) {
9874                 flow_dv_jump_tbl_resource_release(dev, act_res->rix_jump);
9875                 act_res->rix_jump = 0;
9876         }
9877 }
9878
9879 int
9880 flow_dv_sample_match_cb(struct mlx5_cache_list *list __rte_unused,
9881                         struct mlx5_cache_entry *entry, void *cb_ctx)
9882 {
9883         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9884         struct rte_eth_dev *dev = ctx->dev;
9885         struct mlx5_flow_dv_sample_resource *resource = ctx->data;
9886         struct mlx5_flow_dv_sample_resource *cache_resource =
9887                         container_of(entry, typeof(*cache_resource), entry);
9888
9889         if (resource->ratio == cache_resource->ratio &&
9890             resource->ft_type == cache_resource->ft_type &&
9891             resource->ft_id == cache_resource->ft_id &&
9892             resource->set_action == cache_resource->set_action &&
9893             !memcmp((void *)&resource->sample_act,
9894                     (void *)&cache_resource->sample_act,
9895                     sizeof(struct mlx5_flow_sub_actions_list))) {
9896                 /*
9897                  * Existing sample action should release the prepared
9898                  * sub-actions reference counter.
9899                  */
9900                 flow_dv_sample_sub_actions_release(dev,
9901                                                 &resource->sample_idx);
9902                 return 0;
9903         }
9904         return 1;
9905 }
9906
9907 struct mlx5_cache_entry *
9908 flow_dv_sample_create_cb(struct mlx5_cache_list *list __rte_unused,
9909                          struct mlx5_cache_entry *entry __rte_unused,
9910                          void *cb_ctx)
9911 {
9912         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9913         struct rte_eth_dev *dev = ctx->dev;
9914         struct mlx5_flow_dv_sample_resource *resource = ctx->data;
9915         void **sample_dv_actions = resource->sub_actions;
9916         struct mlx5_flow_dv_sample_resource *cache_resource;
9917         struct mlx5dv_dr_flow_sampler_attr sampler_attr;
9918         struct mlx5_priv *priv = dev->data->dev_private;
9919         struct mlx5_dev_ctx_shared *sh = priv->sh;
9920         struct mlx5_flow_tbl_resource *tbl;
9921         uint32_t idx = 0;
9922         const uint32_t next_ft_step = 1;
9923         uint32_t next_ft_id = resource->ft_id + next_ft_step;
9924         uint8_t is_egress = 0;
9925         uint8_t is_transfer = 0;
9926         struct rte_flow_error *error = ctx->error;
9927
9928         /* Register new sample resource. */
9929         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_SAMPLE], &idx);
9930         if (!cache_resource) {
9931                 rte_flow_error_set(error, ENOMEM,
9932                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9933                                           NULL,
9934                                           "cannot allocate resource memory");
9935                 return NULL;
9936         }
9937         *cache_resource = *resource;
9938         /* Create normal path table level */
9939         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
9940                 is_transfer = 1;
9941         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
9942                 is_egress = 1;
9943         tbl = flow_dv_tbl_resource_get(dev, next_ft_id,
9944                                         is_egress, is_transfer,
9945                                         true, NULL, 0, 0, error);
9946         if (!tbl) {
9947                 rte_flow_error_set(error, ENOMEM,
9948                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9949                                           NULL,
9950                                           "fail to create normal path table "
9951                                           "for sample");
9952                 goto error;
9953         }
9954         cache_resource->normal_path_tbl = tbl;
9955         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB) {
9956                 if (!sh->default_miss_action) {
9957                         rte_flow_error_set(error, ENOMEM,
9958                                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9959                                                 NULL,
9960                                                 "default miss action was not "
9961                                                 "created");
9962                         goto error;
9963                 }
9964                 sample_dv_actions[resource->sample_act.actions_num++] =
9965                                                 sh->default_miss_action;
9966         }
9967         /* Create a DR sample action */
9968         sampler_attr.sample_ratio = cache_resource->ratio;
9969         sampler_attr.default_next_table = tbl->obj;
9970         sampler_attr.num_sample_actions = resource->sample_act.actions_num;
9971         sampler_attr.sample_actions = (struct mlx5dv_dr_action **)
9972                                                         &sample_dv_actions[0];
9973         sampler_attr.action = cache_resource->set_action;
9974         if (mlx5_os_flow_dr_create_flow_action_sampler
9975                         (&sampler_attr, &cache_resource->verbs_action)) {
9976                 rte_flow_error_set(error, ENOMEM,
9977                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9978                                         NULL, "cannot create sample action");
9979                 goto error;
9980         }
9981         cache_resource->idx = idx;
9982         cache_resource->dev = dev;
9983         return &cache_resource->entry;
9984 error:
9985         if (cache_resource->ft_type != MLX5DV_FLOW_TABLE_TYPE_FDB)
9986                 flow_dv_sample_sub_actions_release(dev,
9987                                                    &cache_resource->sample_idx);
9988         if (cache_resource->normal_path_tbl)
9989                 flow_dv_tbl_resource_release(MLX5_SH(dev),
9990                                 cache_resource->normal_path_tbl);
9991         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_SAMPLE], idx);
9992         return NULL;
9993
9994 }
9995
9996 /**
9997  * Find existing sample resource or create and register a new one.
9998  *
9999  * @param[in, out] dev
10000  *   Pointer to rte_eth_dev structure.
10001  * @param[in] resource
10002  *   Pointer to sample resource.
10003  * @parm[in, out] dev_flow
10004  *   Pointer to the dev_flow.
10005  * @param[out] error
10006  *   pointer to error structure.
10007  *
10008  * @return
10009  *   0 on success otherwise -errno and errno is set.
10010  */
10011 static int
10012 flow_dv_sample_resource_register(struct rte_eth_dev *dev,
10013                          struct mlx5_flow_dv_sample_resource *resource,
10014                          struct mlx5_flow *dev_flow,
10015                          struct rte_flow_error *error)
10016 {
10017         struct mlx5_flow_dv_sample_resource *cache_resource;
10018         struct mlx5_cache_entry *entry;
10019         struct mlx5_priv *priv = dev->data->dev_private;
10020         struct mlx5_flow_cb_ctx ctx = {
10021                 .dev = dev,
10022                 .error = error,
10023                 .data = resource,
10024         };
10025
10026         entry = mlx5_cache_register(&priv->sh->sample_action_list, &ctx);
10027         if (!entry)
10028                 return -rte_errno;
10029         cache_resource = container_of(entry, typeof(*cache_resource), entry);
10030         dev_flow->handle->dvh.rix_sample = cache_resource->idx;
10031         dev_flow->dv.sample_res = cache_resource;
10032         return 0;
10033 }
10034
10035 int
10036 flow_dv_dest_array_match_cb(struct mlx5_cache_list *list __rte_unused,
10037                             struct mlx5_cache_entry *entry, void *cb_ctx)
10038 {
10039         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10040         struct mlx5_flow_dv_dest_array_resource *resource = ctx->data;
10041         struct rte_eth_dev *dev = ctx->dev;
10042         struct mlx5_flow_dv_dest_array_resource *cache_resource =
10043                         container_of(entry, typeof(*cache_resource), entry);
10044         uint32_t idx = 0;
10045
10046         if (resource->num_of_dest == cache_resource->num_of_dest &&
10047             resource->ft_type == cache_resource->ft_type &&
10048             !memcmp((void *)cache_resource->sample_act,
10049                     (void *)resource->sample_act,
10050                    (resource->num_of_dest *
10051                    sizeof(struct mlx5_flow_sub_actions_list)))) {
10052                 /*
10053                  * Existing sample action should release the prepared
10054                  * sub-actions reference counter.
10055                  */
10056                 for (idx = 0; idx < resource->num_of_dest; idx++)
10057                         flow_dv_sample_sub_actions_release(dev,
10058                                         &resource->sample_idx[idx]);
10059                 return 0;
10060         }
10061         return 1;
10062 }
10063
10064 struct mlx5_cache_entry *
10065 flow_dv_dest_array_create_cb(struct mlx5_cache_list *list __rte_unused,
10066                          struct mlx5_cache_entry *entry __rte_unused,
10067                          void *cb_ctx)
10068 {
10069         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10070         struct rte_eth_dev *dev = ctx->dev;
10071         struct mlx5_flow_dv_dest_array_resource *cache_resource;
10072         struct mlx5_flow_dv_dest_array_resource *resource = ctx->data;
10073         struct mlx5dv_dr_action_dest_attr *dest_attr[MLX5_MAX_DEST_NUM] = { 0 };
10074         struct mlx5dv_dr_action_dest_reformat dest_reformat[MLX5_MAX_DEST_NUM];
10075         struct mlx5_priv *priv = dev->data->dev_private;
10076         struct mlx5_dev_ctx_shared *sh = priv->sh;
10077         struct mlx5_flow_sub_actions_list *sample_act;
10078         struct mlx5dv_dr_domain *domain;
10079         uint32_t idx = 0, res_idx = 0;
10080         struct rte_flow_error *error = ctx->error;
10081         uint64_t action_flags;
10082         int ret;
10083
10084         /* Register new destination array resource. */
10085         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
10086                                             &res_idx);
10087         if (!cache_resource) {
10088                 rte_flow_error_set(error, ENOMEM,
10089                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10090                                           NULL,
10091                                           "cannot allocate resource memory");
10092                 return NULL;
10093         }
10094         *cache_resource = *resource;
10095         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
10096                 domain = sh->fdb_domain;
10097         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
10098                 domain = sh->rx_domain;
10099         else
10100                 domain = sh->tx_domain;
10101         for (idx = 0; idx < resource->num_of_dest; idx++) {
10102                 dest_attr[idx] = (struct mlx5dv_dr_action_dest_attr *)
10103                                  mlx5_malloc(MLX5_MEM_ZERO,
10104                                  sizeof(struct mlx5dv_dr_action_dest_attr),
10105                                  0, SOCKET_ID_ANY);
10106                 if (!dest_attr[idx]) {
10107                         rte_flow_error_set(error, ENOMEM,
10108                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10109                                            NULL,
10110                                            "cannot allocate resource memory");
10111                         goto error;
10112                 }
10113                 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST;
10114                 sample_act = &resource->sample_act[idx];
10115                 action_flags = sample_act->action_flags;
10116                 switch (action_flags) {
10117                 case MLX5_FLOW_ACTION_QUEUE:
10118                         dest_attr[idx]->dest = sample_act->dr_queue_action;
10119                         break;
10120                 case (MLX5_FLOW_ACTION_PORT_ID | MLX5_FLOW_ACTION_ENCAP):
10121                         dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST_REFORMAT;
10122                         dest_attr[idx]->dest_reformat = &dest_reformat[idx];
10123                         dest_attr[idx]->dest_reformat->reformat =
10124                                         sample_act->dr_encap_action;
10125                         dest_attr[idx]->dest_reformat->dest =
10126                                         sample_act->dr_port_id_action;
10127                         break;
10128                 case MLX5_FLOW_ACTION_PORT_ID:
10129                         dest_attr[idx]->dest = sample_act->dr_port_id_action;
10130                         break;
10131                 case MLX5_FLOW_ACTION_JUMP:
10132                         dest_attr[idx]->dest = sample_act->dr_jump_action;
10133                         break;
10134                 default:
10135                         rte_flow_error_set(error, EINVAL,
10136                                            RTE_FLOW_ERROR_TYPE_ACTION,
10137                                            NULL,
10138                                            "unsupported actions type");
10139                         goto error;
10140                 }
10141         }
10142         /* create a dest array actioin */
10143         ret = mlx5_os_flow_dr_create_flow_action_dest_array
10144                                                 (domain,
10145                                                  cache_resource->num_of_dest,
10146                                                  dest_attr,
10147                                                  &cache_resource->action);
10148         if (ret) {
10149                 rte_flow_error_set(error, ENOMEM,
10150                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10151                                    NULL,
10152                                    "cannot create destination array action");
10153                 goto error;
10154         }
10155         cache_resource->idx = res_idx;
10156         cache_resource->dev = dev;
10157         for (idx = 0; idx < resource->num_of_dest; idx++)
10158                 mlx5_free(dest_attr[idx]);
10159         return &cache_resource->entry;
10160 error:
10161         for (idx = 0; idx < resource->num_of_dest; idx++) {
10162                 struct mlx5_flow_sub_actions_idx *act_res =
10163                                         &cache_resource->sample_idx[idx];
10164                 if (act_res->rix_hrxq &&
10165                     !mlx5_hrxq_release(dev,
10166                                 act_res->rix_hrxq))
10167                         act_res->rix_hrxq = 0;
10168                 if (act_res->rix_encap_decap &&
10169                         !flow_dv_encap_decap_resource_release(dev,
10170                                 act_res->rix_encap_decap))
10171                         act_res->rix_encap_decap = 0;
10172                 if (act_res->rix_port_id_action &&
10173                         !flow_dv_port_id_action_resource_release(dev,
10174                                 act_res->rix_port_id_action))
10175                         act_res->rix_port_id_action = 0;
10176                 if (act_res->rix_jump &&
10177                         !flow_dv_jump_tbl_resource_release(dev,
10178                                 act_res->rix_jump))
10179                         act_res->rix_jump = 0;
10180                 if (dest_attr[idx])
10181                         mlx5_free(dest_attr[idx]);
10182         }
10183
10184         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DEST_ARRAY], res_idx);
10185         return NULL;
10186 }
10187
10188 /**
10189  * Find existing destination array resource or create and register a new one.
10190  *
10191  * @param[in, out] dev
10192  *   Pointer to rte_eth_dev structure.
10193  * @param[in] resource
10194  *   Pointer to destination array resource.
10195  * @parm[in, out] dev_flow
10196  *   Pointer to the dev_flow.
10197  * @param[out] error
10198  *   pointer to error structure.
10199  *
10200  * @return
10201  *   0 on success otherwise -errno and errno is set.
10202  */
10203 static int
10204 flow_dv_dest_array_resource_register(struct rte_eth_dev *dev,
10205                          struct mlx5_flow_dv_dest_array_resource *resource,
10206                          struct mlx5_flow *dev_flow,
10207                          struct rte_flow_error *error)
10208 {
10209         struct mlx5_flow_dv_dest_array_resource *cache_resource;
10210         struct mlx5_priv *priv = dev->data->dev_private;
10211         struct mlx5_cache_entry *entry;
10212         struct mlx5_flow_cb_ctx ctx = {
10213                 .dev = dev,
10214                 .error = error,
10215                 .data = resource,
10216         };
10217
10218         entry = mlx5_cache_register(&priv->sh->dest_array_list, &ctx);
10219         if (!entry)
10220                 return -rte_errno;
10221         cache_resource = container_of(entry, typeof(*cache_resource), entry);
10222         dev_flow->handle->dvh.rix_dest_array = cache_resource->idx;
10223         dev_flow->dv.dest_array_res = cache_resource;
10224         return 0;
10225 }
10226
10227 /**
10228  * Convert Sample action to DV specification.
10229  *
10230  * @param[in] dev
10231  *   Pointer to rte_eth_dev structure.
10232  * @param[in] action
10233  *   Pointer to sample action structure.
10234  * @param[in, out] dev_flow
10235  *   Pointer to the mlx5_flow.
10236  * @param[in] attr
10237  *   Pointer to the flow attributes.
10238  * @param[in, out] num_of_dest
10239  *   Pointer to the num of destination.
10240  * @param[in, out] sample_actions
10241  *   Pointer to sample actions list.
10242  * @param[in, out] res
10243  *   Pointer to sample resource.
10244  * @param[out] error
10245  *   Pointer to the error structure.
10246  *
10247  * @return
10248  *   0 on success, a negative errno value otherwise and rte_errno is set.
10249  */
10250 static int
10251 flow_dv_translate_action_sample(struct rte_eth_dev *dev,
10252                                 const struct rte_flow_action_sample *action,
10253                                 struct mlx5_flow *dev_flow,
10254                                 const struct rte_flow_attr *attr,
10255                                 uint32_t *num_of_dest,
10256                                 void **sample_actions,
10257                                 struct mlx5_flow_dv_sample_resource *res,
10258                                 struct rte_flow_error *error)
10259 {
10260         struct mlx5_priv *priv = dev->data->dev_private;
10261         const struct rte_flow_action *sub_actions;
10262         struct mlx5_flow_sub_actions_list *sample_act;
10263         struct mlx5_flow_sub_actions_idx *sample_idx;
10264         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
10265         struct rte_flow *flow = dev_flow->flow;
10266         struct mlx5_flow_rss_desc *rss_desc;
10267         uint64_t action_flags = 0;
10268
10269         MLX5_ASSERT(wks);
10270         rss_desc = &wks->rss_desc;
10271         sample_act = &res->sample_act;
10272         sample_idx = &res->sample_idx;
10273         res->ratio = action->ratio;
10274         sub_actions = action->actions;
10275         for (; sub_actions->type != RTE_FLOW_ACTION_TYPE_END; sub_actions++) {
10276                 int type = sub_actions->type;
10277                 uint32_t pre_rix = 0;
10278                 void *pre_r;
10279                 switch (type) {
10280                 case RTE_FLOW_ACTION_TYPE_QUEUE:
10281                 {
10282                         const struct rte_flow_action_queue *queue;
10283                         struct mlx5_hrxq *hrxq;
10284                         uint32_t hrxq_idx;
10285
10286                         queue = sub_actions->conf;
10287                         rss_desc->queue_num = 1;
10288                         rss_desc->queue[0] = queue->index;
10289                         hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
10290                                                     rss_desc, &hrxq_idx);
10291                         if (!hrxq)
10292                                 return rte_flow_error_set
10293                                         (error, rte_errno,
10294                                          RTE_FLOW_ERROR_TYPE_ACTION,
10295                                          NULL,
10296                                          "cannot create fate queue");
10297                         sample_act->dr_queue_action = hrxq->action;
10298                         sample_idx->rix_hrxq = hrxq_idx;
10299                         sample_actions[sample_act->actions_num++] =
10300                                                 hrxq->action;
10301                         (*num_of_dest)++;
10302                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
10303                         if (action_flags & MLX5_FLOW_ACTION_MARK)
10304                                 dev_flow->handle->rix_hrxq = hrxq_idx;
10305                         dev_flow->handle->fate_action =
10306                                         MLX5_FLOW_FATE_QUEUE;
10307                         break;
10308                 }
10309                 case RTE_FLOW_ACTION_TYPE_RSS:
10310                 {
10311                         struct mlx5_hrxq *hrxq;
10312                         uint32_t hrxq_idx;
10313                         const struct rte_flow_action_rss *rss;
10314                         const uint8_t *rss_key;
10315
10316                         rss = sub_actions->conf;
10317                         memcpy(rss_desc->queue, rss->queue,
10318                                rss->queue_num * sizeof(uint16_t));
10319                         rss_desc->queue_num = rss->queue_num;
10320                         /* NULL RSS key indicates default RSS key. */
10321                         rss_key = !rss->key ? rss_hash_default_key : rss->key;
10322                         memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
10323                         /*
10324                          * rss->level and rss.types should be set in advance
10325                          * when expanding items for RSS.
10326                          */
10327                         flow_dv_hashfields_set(dev_flow, rss_desc);
10328                         hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
10329                                                     rss_desc, &hrxq_idx);
10330                         if (!hrxq)
10331                                 return rte_flow_error_set
10332                                         (error, rte_errno,
10333                                          RTE_FLOW_ERROR_TYPE_ACTION,
10334                                          NULL,
10335                                          "cannot create fate queue");
10336                         sample_act->dr_queue_action = hrxq->action;
10337                         sample_idx->rix_hrxq = hrxq_idx;
10338                         sample_actions[sample_act->actions_num++] =
10339                                                 hrxq->action;
10340                         (*num_of_dest)++;
10341                         action_flags |= MLX5_FLOW_ACTION_RSS;
10342                         if (action_flags & MLX5_FLOW_ACTION_MARK)
10343                                 dev_flow->handle->rix_hrxq = hrxq_idx;
10344                         dev_flow->handle->fate_action =
10345                                         MLX5_FLOW_FATE_QUEUE;
10346                         break;
10347                 }
10348                 case RTE_FLOW_ACTION_TYPE_MARK:
10349                 {
10350                         uint32_t tag_be = mlx5_flow_mark_set
10351                                 (((const struct rte_flow_action_mark *)
10352                                 (sub_actions->conf))->id);
10353
10354                         dev_flow->handle->mark = 1;
10355                         pre_rix = dev_flow->handle->dvh.rix_tag;
10356                         /* Save the mark resource before sample */
10357                         pre_r = dev_flow->dv.tag_resource;
10358                         if (flow_dv_tag_resource_register(dev, tag_be,
10359                                                   dev_flow, error))
10360                                 return -rte_errno;
10361                         MLX5_ASSERT(dev_flow->dv.tag_resource);
10362                         sample_act->dr_tag_action =
10363                                 dev_flow->dv.tag_resource->action;
10364                         sample_idx->rix_tag =
10365                                 dev_flow->handle->dvh.rix_tag;
10366                         sample_actions[sample_act->actions_num++] =
10367                                                 sample_act->dr_tag_action;
10368                         /* Recover the mark resource after sample */
10369                         dev_flow->dv.tag_resource = pre_r;
10370                         dev_flow->handle->dvh.rix_tag = pre_rix;
10371                         action_flags |= MLX5_FLOW_ACTION_MARK;
10372                         break;
10373                 }
10374                 case RTE_FLOW_ACTION_TYPE_COUNT:
10375                 {
10376                         if (!flow->counter) {
10377                                 flow->counter =
10378                                         flow_dv_translate_create_counter(dev,
10379                                                 dev_flow, sub_actions->conf,
10380                                                 0);
10381                                 if (!flow->counter)
10382                                         return rte_flow_error_set
10383                                                 (error, rte_errno,
10384                                                 RTE_FLOW_ERROR_TYPE_ACTION,
10385                                                 NULL,
10386                                                 "cannot create counter"
10387                                                 " object.");
10388                         }
10389                         sample_act->dr_cnt_action =
10390                                   (flow_dv_counter_get_by_idx(dev,
10391                                   flow->counter, NULL))->action;
10392                         sample_actions[sample_act->actions_num++] =
10393                                                 sample_act->dr_cnt_action;
10394                         action_flags |= MLX5_FLOW_ACTION_COUNT;
10395                         break;
10396                 }
10397                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
10398                 {
10399                         struct mlx5_flow_dv_port_id_action_resource
10400                                         port_id_resource;
10401                         uint32_t port_id = 0;
10402
10403                         memset(&port_id_resource, 0, sizeof(port_id_resource));
10404                         /* Save the port id resource before sample */
10405                         pre_rix = dev_flow->handle->rix_port_id_action;
10406                         pre_r = dev_flow->dv.port_id_action;
10407                         if (flow_dv_translate_action_port_id(dev, sub_actions,
10408                                                              &port_id, error))
10409                                 return -rte_errno;
10410                         port_id_resource.port_id = port_id;
10411                         if (flow_dv_port_id_action_resource_register
10412                             (dev, &port_id_resource, dev_flow, error))
10413                                 return -rte_errno;
10414                         sample_act->dr_port_id_action =
10415                                 dev_flow->dv.port_id_action->action;
10416                         sample_idx->rix_port_id_action =
10417                                 dev_flow->handle->rix_port_id_action;
10418                         sample_actions[sample_act->actions_num++] =
10419                                                 sample_act->dr_port_id_action;
10420                         /* Recover the port id resource after sample */
10421                         dev_flow->dv.port_id_action = pre_r;
10422                         dev_flow->handle->rix_port_id_action = pre_rix;
10423                         (*num_of_dest)++;
10424                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
10425                         break;
10426                 }
10427                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
10428                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
10429                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
10430                         /* Save the encap resource before sample */
10431                         pre_rix = dev_flow->handle->dvh.rix_encap_decap;
10432                         pre_r = dev_flow->dv.encap_decap;
10433                         if (flow_dv_create_action_l2_encap(dev, sub_actions,
10434                                                            dev_flow,
10435                                                            attr->transfer,
10436                                                            error))
10437                                 return -rte_errno;
10438                         sample_act->dr_encap_action =
10439                                 dev_flow->dv.encap_decap->action;
10440                         sample_idx->rix_encap_decap =
10441                                 dev_flow->handle->dvh.rix_encap_decap;
10442                         sample_actions[sample_act->actions_num++] =
10443                                                 sample_act->dr_encap_action;
10444                         /* Recover the encap resource after sample */
10445                         dev_flow->dv.encap_decap = pre_r;
10446                         dev_flow->handle->dvh.rix_encap_decap = pre_rix;
10447                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
10448                         break;
10449                 default:
10450                         return rte_flow_error_set(error, EINVAL,
10451                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10452                                 NULL,
10453                                 "Not support for sampler action");
10454                 }
10455         }
10456         sample_act->action_flags = action_flags;
10457         res->ft_id = dev_flow->dv.group;
10458         if (attr->transfer) {
10459                 union {
10460                         uint32_t action_in[MLX5_ST_SZ_DW(set_action_in)];
10461                         uint64_t set_action;
10462                 } action_ctx = { .set_action = 0 };
10463
10464                 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
10465                 MLX5_SET(set_action_in, action_ctx.action_in, action_type,
10466                          MLX5_MODIFICATION_TYPE_SET);
10467                 MLX5_SET(set_action_in, action_ctx.action_in, field,
10468                          MLX5_MODI_META_REG_C_0);
10469                 MLX5_SET(set_action_in, action_ctx.action_in, data,
10470                          priv->vport_meta_tag);
10471                 res->set_action = action_ctx.set_action;
10472         } else if (attr->ingress) {
10473                 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
10474         } else {
10475                 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_TX;
10476         }
10477         return 0;
10478 }
10479
10480 /**
10481  * Convert Sample action to DV specification.
10482  *
10483  * @param[in] dev
10484  *   Pointer to rte_eth_dev structure.
10485  * @param[in, out] dev_flow
10486  *   Pointer to the mlx5_flow.
10487  * @param[in] num_of_dest
10488  *   The num of destination.
10489  * @param[in, out] res
10490  *   Pointer to sample resource.
10491  * @param[in, out] mdest_res
10492  *   Pointer to destination array resource.
10493  * @param[in] sample_actions
10494  *   Pointer to sample path actions list.
10495  * @param[in] action_flags
10496  *   Holds the actions detected until now.
10497  * @param[out] error
10498  *   Pointer to the error structure.
10499  *
10500  * @return
10501  *   0 on success, a negative errno value otherwise and rte_errno is set.
10502  */
10503 static int
10504 flow_dv_create_action_sample(struct rte_eth_dev *dev,
10505                              struct mlx5_flow *dev_flow,
10506                              uint32_t num_of_dest,
10507                              struct mlx5_flow_dv_sample_resource *res,
10508                              struct mlx5_flow_dv_dest_array_resource *mdest_res,
10509                              void **sample_actions,
10510                              uint64_t action_flags,
10511                              struct rte_flow_error *error)
10512 {
10513         /* update normal path action resource into last index of array */
10514         uint32_t dest_index = MLX5_MAX_DEST_NUM - 1;
10515         struct mlx5_flow_sub_actions_list *sample_act =
10516                                         &mdest_res->sample_act[dest_index];
10517         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
10518         struct mlx5_flow_rss_desc *rss_desc;
10519         uint32_t normal_idx = 0;
10520         struct mlx5_hrxq *hrxq;
10521         uint32_t hrxq_idx;
10522
10523         MLX5_ASSERT(wks);
10524         rss_desc = &wks->rss_desc;
10525         if (num_of_dest > 1) {
10526                 if (sample_act->action_flags & MLX5_FLOW_ACTION_QUEUE) {
10527                         /* Handle QP action for mirroring */
10528                         hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
10529                                                     rss_desc, &hrxq_idx);
10530                         if (!hrxq)
10531                                 return rte_flow_error_set
10532                                      (error, rte_errno,
10533                                       RTE_FLOW_ERROR_TYPE_ACTION,
10534                                       NULL,
10535                                       "cannot create rx queue");
10536                         normal_idx++;
10537                         mdest_res->sample_idx[dest_index].rix_hrxq = hrxq_idx;
10538                         sample_act->dr_queue_action = hrxq->action;
10539                         if (action_flags & MLX5_FLOW_ACTION_MARK)
10540                                 dev_flow->handle->rix_hrxq = hrxq_idx;
10541                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
10542                 }
10543                 if (sample_act->action_flags & MLX5_FLOW_ACTION_ENCAP) {
10544                         normal_idx++;
10545                         mdest_res->sample_idx[dest_index].rix_encap_decap =
10546                                 dev_flow->handle->dvh.rix_encap_decap;
10547                         sample_act->dr_encap_action =
10548                                 dev_flow->dv.encap_decap->action;
10549                 }
10550                 if (sample_act->action_flags & MLX5_FLOW_ACTION_PORT_ID) {
10551                         normal_idx++;
10552                         mdest_res->sample_idx[dest_index].rix_port_id_action =
10553                                 dev_flow->handle->rix_port_id_action;
10554                         sample_act->dr_port_id_action =
10555                                 dev_flow->dv.port_id_action->action;
10556                 }
10557                 if (sample_act->action_flags & MLX5_FLOW_ACTION_JUMP) {
10558                         normal_idx++;
10559                         mdest_res->sample_idx[dest_index].rix_jump =
10560                                 dev_flow->handle->rix_jump;
10561                         sample_act->dr_jump_action =
10562                                 dev_flow->dv.jump->action;
10563                         dev_flow->handle->rix_jump = 0;
10564                 }
10565                 sample_act->actions_num = normal_idx;
10566                 /* update sample action resource into first index of array */
10567                 mdest_res->ft_type = res->ft_type;
10568                 memcpy(&mdest_res->sample_idx[0], &res->sample_idx,
10569                                 sizeof(struct mlx5_flow_sub_actions_idx));
10570                 memcpy(&mdest_res->sample_act[0], &res->sample_act,
10571                                 sizeof(struct mlx5_flow_sub_actions_list));
10572                 mdest_res->num_of_dest = num_of_dest;
10573                 if (flow_dv_dest_array_resource_register(dev, mdest_res,
10574                                                          dev_flow, error))
10575                         return rte_flow_error_set(error, EINVAL,
10576                                                   RTE_FLOW_ERROR_TYPE_ACTION,
10577                                                   NULL, "can't create sample "
10578                                                   "action");
10579         } else {
10580                 res->sub_actions = sample_actions;
10581                 if (flow_dv_sample_resource_register(dev, res, dev_flow, error))
10582                         return rte_flow_error_set(error, EINVAL,
10583                                                   RTE_FLOW_ERROR_TYPE_ACTION,
10584                                                   NULL,
10585                                                   "can't create sample action");
10586         }
10587         return 0;
10588 }
10589
10590 /**
10591  * Remove an ASO age action from age actions list.
10592  *
10593  * @param[in] dev
10594  *   Pointer to the Ethernet device structure.
10595  * @param[in] age
10596  *   Pointer to the aso age action handler.
10597  */
10598 static void
10599 flow_dv_aso_age_remove_from_age(struct rte_eth_dev *dev,
10600                                 struct mlx5_aso_age_action *age)
10601 {
10602         struct mlx5_age_info *age_info;
10603         struct mlx5_age_param *age_param = &age->age_params;
10604         struct mlx5_priv *priv = dev->data->dev_private;
10605         uint16_t expected = AGE_CANDIDATE;
10606
10607         age_info = GET_PORT_AGE_INFO(priv);
10608         if (!__atomic_compare_exchange_n(&age_param->state, &expected,
10609                                          AGE_FREE, false, __ATOMIC_RELAXED,
10610                                          __ATOMIC_RELAXED)) {
10611                 /**
10612                  * We need the lock even it is age timeout,
10613                  * since age action may still in process.
10614                  */
10615                 rte_spinlock_lock(&age_info->aged_sl);
10616                 LIST_REMOVE(age, next);
10617                 rte_spinlock_unlock(&age_info->aged_sl);
10618                 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
10619         }
10620 }
10621
10622 /**
10623  * Release an ASO age action.
10624  *
10625  * @param[in] dev
10626  *   Pointer to the Ethernet device structure.
10627  * @param[in] age_idx
10628  *   Index of ASO age action to release.
10629  * @param[in] flow
10630  *   True if the release operation is during flow destroy operation.
10631  *   False if the release operation is during action destroy operation.
10632  *
10633  * @return
10634  *   0 when age action was removed, otherwise the number of references.
10635  */
10636 static int
10637 flow_dv_aso_age_release(struct rte_eth_dev *dev, uint32_t age_idx)
10638 {
10639         struct mlx5_priv *priv = dev->data->dev_private;
10640         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
10641         struct mlx5_aso_age_action *age = flow_aso_age_get_by_idx(dev, age_idx);
10642         uint32_t ret = __atomic_sub_fetch(&age->refcnt, 1, __ATOMIC_RELAXED);
10643
10644         if (!ret) {
10645                 flow_dv_aso_age_remove_from_age(dev, age);
10646                 rte_spinlock_lock(&mng->free_sl);
10647                 LIST_INSERT_HEAD(&mng->free, age, next);
10648                 rte_spinlock_unlock(&mng->free_sl);
10649         }
10650         return ret;
10651 }
10652
10653 /**
10654  * Resize the ASO age pools array by MLX5_CNT_CONTAINER_RESIZE pools.
10655  *
10656  * @param[in] dev
10657  *   Pointer to the Ethernet device structure.
10658  *
10659  * @return
10660  *   0 on success, otherwise negative errno value and rte_errno is set.
10661  */
10662 static int
10663 flow_dv_aso_age_pools_resize(struct rte_eth_dev *dev)
10664 {
10665         struct mlx5_priv *priv = dev->data->dev_private;
10666         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
10667         void *old_pools = mng->pools;
10668         uint32_t resize = mng->n + MLX5_CNT_CONTAINER_RESIZE;
10669         uint32_t mem_size = sizeof(struct mlx5_aso_age_pool *) * resize;
10670         void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
10671
10672         if (!pools) {
10673                 rte_errno = ENOMEM;
10674                 return -ENOMEM;
10675         }
10676         if (old_pools) {
10677                 memcpy(pools, old_pools,
10678                        mng->n * sizeof(struct mlx5_flow_counter_pool *));
10679                 mlx5_free(old_pools);
10680         } else {
10681                 /* First ASO flow hit allocation - starting ASO data-path. */
10682                 int ret = mlx5_aso_queue_start(priv->sh);
10683
10684                 if (ret) {
10685                         mlx5_free(pools);
10686                         return ret;
10687                 }
10688         }
10689         mng->n = resize;
10690         mng->pools = pools;
10691         return 0;
10692 }
10693
10694 /**
10695  * Create and initialize a new ASO aging pool.
10696  *
10697  * @param[in] dev
10698  *   Pointer to the Ethernet device structure.
10699  * @param[out] age_free
10700  *   Where to put the pointer of a new age action.
10701  *
10702  * @return
10703  *   The age actions pool pointer and @p age_free is set on success,
10704  *   NULL otherwise and rte_errno is set.
10705  */
10706 static struct mlx5_aso_age_pool *
10707 flow_dv_age_pool_create(struct rte_eth_dev *dev,
10708                         struct mlx5_aso_age_action **age_free)
10709 {
10710         struct mlx5_priv *priv = dev->data->dev_private;
10711         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
10712         struct mlx5_aso_age_pool *pool = NULL;
10713         struct mlx5_devx_obj *obj = NULL;
10714         uint32_t i;
10715
10716         obj = mlx5_devx_cmd_create_flow_hit_aso_obj(priv->sh->ctx,
10717                                                     priv->sh->pdn);
10718         if (!obj) {
10719                 rte_errno = ENODATA;
10720                 DRV_LOG(ERR, "Failed to create flow_hit_aso_obj using DevX.");
10721                 return NULL;
10722         }
10723         pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
10724         if (!pool) {
10725                 claim_zero(mlx5_devx_cmd_destroy(obj));
10726                 rte_errno = ENOMEM;
10727                 return NULL;
10728         }
10729         pool->flow_hit_aso_obj = obj;
10730         pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
10731         rte_spinlock_lock(&mng->resize_sl);
10732         pool->index = mng->next;
10733         /* Resize pools array if there is no room for the new pool in it. */
10734         if (pool->index == mng->n && flow_dv_aso_age_pools_resize(dev)) {
10735                 claim_zero(mlx5_devx_cmd_destroy(obj));
10736                 mlx5_free(pool);
10737                 rte_spinlock_unlock(&mng->resize_sl);
10738                 return NULL;
10739         }
10740         mng->pools[pool->index] = pool;
10741         mng->next++;
10742         rte_spinlock_unlock(&mng->resize_sl);
10743         /* Assign the first action in the new pool, the rest go to free list. */
10744         *age_free = &pool->actions[0];
10745         for (i = 1; i < MLX5_ASO_AGE_ACTIONS_PER_POOL; i++) {
10746                 pool->actions[i].offset = i;
10747                 LIST_INSERT_HEAD(&mng->free, &pool->actions[i], next);
10748         }
10749         return pool;
10750 }
10751
10752 /**
10753  * Allocate a ASO aging bit.
10754  *
10755  * @param[in] dev
10756  *   Pointer to the Ethernet device structure.
10757  * @param[out] error
10758  *   Pointer to the error structure.
10759  *
10760  * @return
10761  *   Index to ASO age action on success, 0 otherwise and rte_errno is set.
10762  */
10763 static uint32_t
10764 flow_dv_aso_age_alloc(struct rte_eth_dev *dev, struct rte_flow_error *error)
10765 {
10766         struct mlx5_priv *priv = dev->data->dev_private;
10767         const struct mlx5_aso_age_pool *pool;
10768         struct mlx5_aso_age_action *age_free = NULL;
10769         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
10770
10771         MLX5_ASSERT(mng);
10772         /* Try to get the next free age action bit. */
10773         rte_spinlock_lock(&mng->free_sl);
10774         age_free = LIST_FIRST(&mng->free);
10775         if (age_free) {
10776                 LIST_REMOVE(age_free, next);
10777         } else if (!flow_dv_age_pool_create(dev, &age_free)) {
10778                 rte_spinlock_unlock(&mng->free_sl);
10779                 rte_flow_error_set(error, rte_errno, RTE_FLOW_ERROR_TYPE_ACTION,
10780                                    NULL, "failed to create ASO age pool");
10781                 return 0; /* 0 is an error. */
10782         }
10783         rte_spinlock_unlock(&mng->free_sl);
10784         pool = container_of
10785           ((const struct mlx5_aso_age_action (*)[MLX5_ASO_AGE_ACTIONS_PER_POOL])
10786                   (age_free - age_free->offset), const struct mlx5_aso_age_pool,
10787                                                                        actions);
10788         if (!age_free->dr_action) {
10789                 int reg_c = mlx5_flow_get_reg_id(dev, MLX5_ASO_FLOW_HIT, 0,
10790                                                  error);
10791
10792                 if (reg_c < 0) {
10793                         rte_flow_error_set(error, rte_errno,
10794                                            RTE_FLOW_ERROR_TYPE_ACTION,
10795                                            NULL, "failed to get reg_c "
10796                                            "for ASO flow hit");
10797                         return 0; /* 0 is an error. */
10798                 }
10799 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
10800                 age_free->dr_action = mlx5_glue->dv_create_flow_action_aso
10801                                 (priv->sh->rx_domain,
10802                                  pool->flow_hit_aso_obj->obj, age_free->offset,
10803                                  MLX5DV_DR_ACTION_FLAGS_ASO_FIRST_HIT_SET,
10804                                  (reg_c - REG_C_0));
10805 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
10806                 if (!age_free->dr_action) {
10807                         rte_errno = errno;
10808                         rte_spinlock_lock(&mng->free_sl);
10809                         LIST_INSERT_HEAD(&mng->free, age_free, next);
10810                         rte_spinlock_unlock(&mng->free_sl);
10811                         rte_flow_error_set(error, rte_errno,
10812                                            RTE_FLOW_ERROR_TYPE_ACTION,
10813                                            NULL, "failed to create ASO "
10814                                            "flow hit action");
10815                         return 0; /* 0 is an error. */
10816                 }
10817         }
10818         __atomic_store_n(&age_free->refcnt, 1, __ATOMIC_RELAXED);
10819         return pool->index | ((age_free->offset + 1) << 16);
10820 }
10821
10822 /**
10823  * Create a age action using ASO mechanism.
10824  *
10825  * @param[in] dev
10826  *   Pointer to rte_eth_dev structure.
10827  * @param[in] age
10828  *   Pointer to the aging action configuration.
10829  * @param[out] error
10830  *   Pointer to the error structure.
10831  *
10832  * @return
10833  *   Index to flow counter on success, 0 otherwise.
10834  */
10835 static uint32_t
10836 flow_dv_translate_create_aso_age(struct rte_eth_dev *dev,
10837                                  const struct rte_flow_action_age *age,
10838                                  struct rte_flow_error *error)
10839 {
10840         uint32_t age_idx = 0;
10841         struct mlx5_aso_age_action *aso_age;
10842
10843         age_idx = flow_dv_aso_age_alloc(dev, error);
10844         if (!age_idx)
10845                 return 0;
10846         aso_age = flow_aso_age_get_by_idx(dev, age_idx);
10847         aso_age->age_params.context = age->context;
10848         aso_age->age_params.timeout = age->timeout;
10849         aso_age->age_params.port_id = dev->data->port_id;
10850         __atomic_store_n(&aso_age->age_params.sec_since_last_hit, 0,
10851                          __ATOMIC_RELAXED);
10852         __atomic_store_n(&aso_age->age_params.state, AGE_CANDIDATE,
10853                          __ATOMIC_RELAXED);
10854         return age_idx;
10855 }
10856
10857 /**
10858  * Fill the flow with DV spec, lock free
10859  * (mutex should be acquired by caller).
10860  *
10861  * @param[in] dev
10862  *   Pointer to rte_eth_dev structure.
10863  * @param[in, out] dev_flow
10864  *   Pointer to the sub flow.
10865  * @param[in] attr
10866  *   Pointer to the flow attributes.
10867  * @param[in] items
10868  *   Pointer to the list of items.
10869  * @param[in] actions
10870  *   Pointer to the list of actions.
10871  * @param[out] error
10872  *   Pointer to the error structure.
10873  *
10874  * @return
10875  *   0 on success, a negative errno value otherwise and rte_errno is set.
10876  */
10877 static int
10878 flow_dv_translate(struct rte_eth_dev *dev,
10879                   struct mlx5_flow *dev_flow,
10880                   const struct rte_flow_attr *attr,
10881                   const struct rte_flow_item items[],
10882                   const struct rte_flow_action actions[],
10883                   struct rte_flow_error *error)
10884 {
10885         struct mlx5_priv *priv = dev->data->dev_private;
10886         struct mlx5_dev_config *dev_conf = &priv->config;
10887         struct rte_flow *flow = dev_flow->flow;
10888         struct mlx5_flow_handle *handle = dev_flow->handle;
10889         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
10890         struct mlx5_flow_rss_desc *rss_desc;
10891         uint64_t item_flags = 0;
10892         uint64_t last_item = 0;
10893         uint64_t action_flags = 0;
10894         struct mlx5_flow_dv_matcher matcher = {
10895                 .mask = {
10896                         .size = sizeof(matcher.mask.buf) -
10897                                 MLX5_ST_SZ_BYTES(fte_match_set_misc4),
10898                 },
10899         };
10900         int actions_n = 0;
10901         bool actions_end = false;
10902         union {
10903                 struct mlx5_flow_dv_modify_hdr_resource res;
10904                 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
10905                             sizeof(struct mlx5_modification_cmd) *
10906                             (MLX5_MAX_MODIFY_NUM + 1)];
10907         } mhdr_dummy;
10908         struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
10909         const struct rte_flow_action_count *count = NULL;
10910         const struct rte_flow_action_age *age = NULL;
10911         union flow_dv_attr flow_attr = { .attr = 0 };
10912         uint32_t tag_be;
10913         union mlx5_flow_tbl_key tbl_key;
10914         uint32_t modify_action_position = UINT32_MAX;
10915         void *match_mask = matcher.mask.buf;
10916         void *match_value = dev_flow->dv.value.buf;
10917         uint8_t next_protocol = 0xff;
10918         struct rte_vlan_hdr vlan = { 0 };
10919         struct mlx5_flow_dv_dest_array_resource mdest_res;
10920         struct mlx5_flow_dv_sample_resource sample_res;
10921         void *sample_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
10922         const struct rte_flow_action_sample *sample = NULL;
10923         struct mlx5_flow_sub_actions_list *sample_act;
10924         uint32_t sample_act_pos = UINT32_MAX;
10925         uint32_t num_of_dest = 0;
10926         int tmp_actions_n = 0;
10927         uint32_t table;
10928         int ret = 0;
10929         const struct mlx5_flow_tunnel *tunnel;
10930         struct flow_grp_info grp_info = {
10931                 .external = !!dev_flow->external,
10932                 .transfer = !!attr->transfer,
10933                 .fdb_def_rule = !!priv->fdb_def_rule,
10934                 .skip_scale = dev_flow->skip_scale &
10935                         (1 << MLX5_SCALE_FLOW_GROUP_BIT),
10936         };
10937
10938         if (!wks)
10939                 return rte_flow_error_set(error, ENOMEM,
10940                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10941                                           NULL,
10942                                           "failed to push flow workspace");
10943         rss_desc = &wks->rss_desc;
10944         memset(&mdest_res, 0, sizeof(struct mlx5_flow_dv_dest_array_resource));
10945         memset(&sample_res, 0, sizeof(struct mlx5_flow_dv_sample_resource));
10946         mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
10947                                            MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
10948         /* update normal path action resource into last index of array */
10949         sample_act = &mdest_res.sample_act[MLX5_MAX_DEST_NUM - 1];
10950         tunnel = is_flow_tunnel_match_rule(dev, attr, items, actions) ?
10951                  flow_items_to_tunnel(items) :
10952                  is_flow_tunnel_steer_rule(dev, attr, items, actions) ?
10953                  flow_actions_to_tunnel(actions) :
10954                  dev_flow->tunnel ? dev_flow->tunnel : NULL;
10955         mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
10956                                            MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
10957         grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
10958                                 (dev, tunnel, attr, items, actions);
10959         ret = mlx5_flow_group_to_table(dev, tunnel, attr->group, &table,
10960                                        &grp_info, error);
10961         if (ret)
10962                 return ret;
10963         dev_flow->dv.group = table;
10964         if (attr->transfer)
10965                 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
10966         /* number of actions must be set to 0 in case of dirty stack. */
10967         mhdr_res->actions_num = 0;
10968         if (is_flow_tunnel_match_rule(dev, attr, items, actions)) {
10969                 /*
10970                  * do not add decap action if match rule drops packet
10971                  * HW rejects rules with decap & drop
10972                  *
10973                  * if tunnel match rule was inserted before matching tunnel set
10974                  * rule flow table used in the match rule must be registered.
10975                  * current implementation handles that in the
10976                  * flow_dv_match_register() at the function end.
10977                  */
10978                 bool add_decap = true;
10979                 const struct rte_flow_action *ptr = actions;
10980
10981                 for (; ptr->type != RTE_FLOW_ACTION_TYPE_END; ptr++) {
10982                         if (ptr->type == RTE_FLOW_ACTION_TYPE_DROP) {
10983                                 add_decap = false;
10984                                 break;
10985                         }
10986                 }
10987                 if (add_decap) {
10988                         if (flow_dv_create_action_l2_decap(dev, dev_flow,
10989                                                            attr->transfer,
10990                                                            error))
10991                                 return -rte_errno;
10992                         dev_flow->dv.actions[actions_n++] =
10993                                         dev_flow->dv.encap_decap->action;
10994                         action_flags |= MLX5_FLOW_ACTION_DECAP;
10995                 }
10996         }
10997         for (; !actions_end ; actions++) {
10998                 const struct rte_flow_action_queue *queue;
10999                 const struct rte_flow_action_rss *rss;
11000                 const struct rte_flow_action *action = actions;
11001                 const uint8_t *rss_key;
11002                 const struct rte_flow_action_meter *mtr;
11003                 struct mlx5_flow_tbl_resource *tbl;
11004                 struct mlx5_aso_age_action *age_act;
11005                 uint32_t port_id = 0;
11006                 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
11007                 int action_type = actions->type;
11008                 const struct rte_flow_action *found_action = NULL;
11009                 struct mlx5_flow_meter *fm = NULL;
11010                 uint32_t jump_group = 0;
11011
11012                 if (!mlx5_flow_os_action_supported(action_type))
11013                         return rte_flow_error_set(error, ENOTSUP,
11014                                                   RTE_FLOW_ERROR_TYPE_ACTION,
11015                                                   actions,
11016                                                   "action not supported");
11017                 switch (action_type) {
11018                 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
11019                         action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
11020                         break;
11021                 case RTE_FLOW_ACTION_TYPE_VOID:
11022                         break;
11023                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
11024                         if (flow_dv_translate_action_port_id(dev, action,
11025                                                              &port_id, error))
11026                                 return -rte_errno;
11027                         port_id_resource.port_id = port_id;
11028                         MLX5_ASSERT(!handle->rix_port_id_action);
11029                         if (flow_dv_port_id_action_resource_register
11030                             (dev, &port_id_resource, dev_flow, error))
11031                                 return -rte_errno;
11032                         dev_flow->dv.actions[actions_n++] =
11033                                         dev_flow->dv.port_id_action->action;
11034                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
11035                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_PORT_ID;
11036                         sample_act->action_flags |= MLX5_FLOW_ACTION_PORT_ID;
11037                         num_of_dest++;
11038                         break;
11039                 case RTE_FLOW_ACTION_TYPE_FLAG:
11040                         action_flags |= MLX5_FLOW_ACTION_FLAG;
11041                         dev_flow->handle->mark = 1;
11042                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
11043                                 struct rte_flow_action_mark mark = {
11044                                         .id = MLX5_FLOW_MARK_DEFAULT,
11045                                 };
11046
11047                                 if (flow_dv_convert_action_mark(dev, &mark,
11048                                                                 mhdr_res,
11049                                                                 error))
11050                                         return -rte_errno;
11051                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
11052                                 break;
11053                         }
11054                         tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
11055                         /*
11056                          * Only one FLAG or MARK is supported per device flow
11057                          * right now. So the pointer to the tag resource must be
11058                          * zero before the register process.
11059                          */
11060                         MLX5_ASSERT(!handle->dvh.rix_tag);
11061                         if (flow_dv_tag_resource_register(dev, tag_be,
11062                                                           dev_flow, error))
11063                                 return -rte_errno;
11064                         MLX5_ASSERT(dev_flow->dv.tag_resource);
11065                         dev_flow->dv.actions[actions_n++] =
11066                                         dev_flow->dv.tag_resource->action;
11067                         break;
11068                 case RTE_FLOW_ACTION_TYPE_MARK:
11069                         action_flags |= MLX5_FLOW_ACTION_MARK;
11070                         dev_flow->handle->mark = 1;
11071                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
11072                                 const struct rte_flow_action_mark *mark =
11073                                         (const struct rte_flow_action_mark *)
11074                                                 actions->conf;
11075
11076                                 if (flow_dv_convert_action_mark(dev, mark,
11077                                                                 mhdr_res,
11078                                                                 error))
11079                                         return -rte_errno;
11080                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
11081                                 break;
11082                         }
11083                         /* Fall-through */
11084                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
11085                         /* Legacy (non-extensive) MARK action. */
11086                         tag_be = mlx5_flow_mark_set
11087                               (((const struct rte_flow_action_mark *)
11088                                (actions->conf))->id);
11089                         MLX5_ASSERT(!handle->dvh.rix_tag);
11090                         if (flow_dv_tag_resource_register(dev, tag_be,
11091                                                           dev_flow, error))
11092                                 return -rte_errno;
11093                         MLX5_ASSERT(dev_flow->dv.tag_resource);
11094                         dev_flow->dv.actions[actions_n++] =
11095                                         dev_flow->dv.tag_resource->action;
11096                         break;
11097                 case RTE_FLOW_ACTION_TYPE_SET_META:
11098                         if (flow_dv_convert_action_set_meta
11099                                 (dev, mhdr_res, attr,
11100                                  (const struct rte_flow_action_set_meta *)
11101                                   actions->conf, error))
11102                                 return -rte_errno;
11103                         action_flags |= MLX5_FLOW_ACTION_SET_META;
11104                         break;
11105                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
11106                         if (flow_dv_convert_action_set_tag
11107                                 (dev, mhdr_res,
11108                                  (const struct rte_flow_action_set_tag *)
11109                                   actions->conf, error))
11110                                 return -rte_errno;
11111                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
11112                         break;
11113                 case RTE_FLOW_ACTION_TYPE_DROP:
11114                         action_flags |= MLX5_FLOW_ACTION_DROP;
11115                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_DROP;
11116                         break;
11117                 case RTE_FLOW_ACTION_TYPE_QUEUE:
11118                         queue = actions->conf;
11119                         rss_desc->queue_num = 1;
11120                         rss_desc->queue[0] = queue->index;
11121                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
11122                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
11123                         sample_act->action_flags |= MLX5_FLOW_ACTION_QUEUE;
11124                         num_of_dest++;
11125                         break;
11126                 case RTE_FLOW_ACTION_TYPE_RSS:
11127                         rss = actions->conf;
11128                         memcpy(rss_desc->queue, rss->queue,
11129                                rss->queue_num * sizeof(uint16_t));
11130                         rss_desc->queue_num = rss->queue_num;
11131                         /* NULL RSS key indicates default RSS key. */
11132                         rss_key = !rss->key ? rss_hash_default_key : rss->key;
11133                         memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
11134                         /*
11135                          * rss->level and rss.types should be set in advance
11136                          * when expanding items for RSS.
11137                          */
11138                         action_flags |= MLX5_FLOW_ACTION_RSS;
11139                         dev_flow->handle->fate_action = rss_desc->shared_rss ?
11140                                 MLX5_FLOW_FATE_SHARED_RSS :
11141                                 MLX5_FLOW_FATE_QUEUE;
11142                         break;
11143                 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
11144                         flow->age = (uint32_t)(uintptr_t)(action->conf);
11145                         age_act = flow_aso_age_get_by_idx(dev, flow->age);
11146                         __atomic_fetch_add(&age_act->refcnt, 1,
11147                                            __ATOMIC_RELAXED);
11148                         dev_flow->dv.actions[actions_n++] = age_act->dr_action;
11149                         action_flags |= MLX5_FLOW_ACTION_AGE;
11150                         break;
11151                 case RTE_FLOW_ACTION_TYPE_AGE:
11152                         if (priv->sh->flow_hit_aso_en && attr->group) {
11153                                 /*
11154                                  * Create one shared age action, to be used
11155                                  * by all sub-flows.
11156                                  */
11157                                 if (!flow->age) {
11158                                         flow->age =
11159                                                 flow_dv_translate_create_aso_age
11160                                                         (dev, action->conf,
11161                                                          error);
11162                                         if (!flow->age)
11163                                                 return rte_flow_error_set
11164                                                 (error, rte_errno,
11165                                                  RTE_FLOW_ERROR_TYPE_ACTION,
11166                                                  NULL,
11167                                                  "can't create ASO age action");
11168                                 }
11169                                 dev_flow->dv.actions[actions_n++] =
11170                                           (flow_aso_age_get_by_idx
11171                                                 (dev, flow->age))->dr_action;
11172                                 action_flags |= MLX5_FLOW_ACTION_AGE;
11173                                 break;
11174                         }
11175                         /* Fall-through */
11176                 case RTE_FLOW_ACTION_TYPE_COUNT:
11177                         if (!dev_conf->devx) {
11178                                 return rte_flow_error_set
11179                                               (error, ENOTSUP,
11180                                                RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11181                                                NULL,
11182                                                "count action not supported");
11183                         }
11184                         /* Save information first, will apply later. */
11185                         if (actions->type == RTE_FLOW_ACTION_TYPE_COUNT)
11186                                 count = action->conf;
11187                         else
11188                                 age = action->conf;
11189                         action_flags |= MLX5_FLOW_ACTION_COUNT;
11190                         break;
11191                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
11192                         dev_flow->dv.actions[actions_n++] =
11193                                                 priv->sh->pop_vlan_action;
11194                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
11195                         break;
11196                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
11197                         if (!(action_flags &
11198                               MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
11199                                 flow_dev_get_vlan_info_from_items(items, &vlan);
11200                         vlan.eth_proto = rte_be_to_cpu_16
11201                              ((((const struct rte_flow_action_of_push_vlan *)
11202                                                    actions->conf)->ethertype));
11203                         found_action = mlx5_flow_find_action
11204                                         (actions + 1,
11205                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
11206                         if (found_action)
11207                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
11208                         found_action = mlx5_flow_find_action
11209                                         (actions + 1,
11210                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
11211                         if (found_action)
11212                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
11213                         if (flow_dv_create_action_push_vlan
11214                                             (dev, attr, &vlan, dev_flow, error))
11215                                 return -rte_errno;
11216                         dev_flow->dv.actions[actions_n++] =
11217                                         dev_flow->dv.push_vlan_res->action;
11218                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
11219                         break;
11220                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
11221                         /* of_vlan_push action handled this action */
11222                         MLX5_ASSERT(action_flags &
11223                                     MLX5_FLOW_ACTION_OF_PUSH_VLAN);
11224                         break;
11225                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
11226                         if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
11227                                 break;
11228                         flow_dev_get_vlan_info_from_items(items, &vlan);
11229                         mlx5_update_vlan_vid_pcp(actions, &vlan);
11230                         /* If no VLAN push - this is a modify header action */
11231                         if (flow_dv_convert_action_modify_vlan_vid
11232                                                 (mhdr_res, actions, error))
11233                                 return -rte_errno;
11234                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
11235                         break;
11236                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
11237                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
11238                         if (flow_dv_create_action_l2_encap(dev, actions,
11239                                                            dev_flow,
11240                                                            attr->transfer,
11241                                                            error))
11242                                 return -rte_errno;
11243                         dev_flow->dv.actions[actions_n++] =
11244                                         dev_flow->dv.encap_decap->action;
11245                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
11246                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
11247                                 sample_act->action_flags |=
11248                                                         MLX5_FLOW_ACTION_ENCAP;
11249                         break;
11250                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
11251                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
11252                         if (flow_dv_create_action_l2_decap(dev, dev_flow,
11253                                                            attr->transfer,
11254                                                            error))
11255                                 return -rte_errno;
11256                         dev_flow->dv.actions[actions_n++] =
11257                                         dev_flow->dv.encap_decap->action;
11258                         action_flags |= MLX5_FLOW_ACTION_DECAP;
11259                         break;
11260                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
11261                         /* Handle encap with preceding decap. */
11262                         if (action_flags & MLX5_FLOW_ACTION_DECAP) {
11263                                 if (flow_dv_create_action_raw_encap
11264                                         (dev, actions, dev_flow, attr, error))
11265                                         return -rte_errno;
11266                                 dev_flow->dv.actions[actions_n++] =
11267                                         dev_flow->dv.encap_decap->action;
11268                         } else {
11269                                 /* Handle encap without preceding decap. */
11270                                 if (flow_dv_create_action_l2_encap
11271                                     (dev, actions, dev_flow, attr->transfer,
11272                                      error))
11273                                         return -rte_errno;
11274                                 dev_flow->dv.actions[actions_n++] =
11275                                         dev_flow->dv.encap_decap->action;
11276                         }
11277                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
11278                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
11279                                 sample_act->action_flags |=
11280                                                         MLX5_FLOW_ACTION_ENCAP;
11281                         break;
11282                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
11283                         while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
11284                                 ;
11285                         if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
11286                                 if (flow_dv_create_action_l2_decap
11287                                     (dev, dev_flow, attr->transfer, error))
11288                                         return -rte_errno;
11289                                 dev_flow->dv.actions[actions_n++] =
11290                                         dev_flow->dv.encap_decap->action;
11291                         }
11292                         /* If decap is followed by encap, handle it at encap. */
11293                         action_flags |= MLX5_FLOW_ACTION_DECAP;
11294                         break;
11295                 case RTE_FLOW_ACTION_TYPE_JUMP:
11296                         jump_group = ((const struct rte_flow_action_jump *)
11297                                                         action->conf)->group;
11298                         grp_info.std_tbl_fix = 0;
11299                         if (dev_flow->skip_scale &
11300                                 (1 << MLX5_SCALE_JUMP_FLOW_GROUP_BIT))
11301                                 grp_info.skip_scale = 1;
11302                         else
11303                                 grp_info.skip_scale = 0;
11304                         ret = mlx5_flow_group_to_table(dev, tunnel,
11305                                                        jump_group,
11306                                                        &table,
11307                                                        &grp_info, error);
11308                         if (ret)
11309                                 return ret;
11310                         tbl = flow_dv_tbl_resource_get(dev, table, attr->egress,
11311                                                        attr->transfer,
11312                                                        !!dev_flow->external,
11313                                                        tunnel, jump_group, 0,
11314                                                        error);
11315                         if (!tbl)
11316                                 return rte_flow_error_set
11317                                                 (error, errno,
11318                                                  RTE_FLOW_ERROR_TYPE_ACTION,
11319                                                  NULL,
11320                                                  "cannot create jump action.");
11321                         if (flow_dv_jump_tbl_resource_register
11322                             (dev, tbl, dev_flow, error)) {
11323                                 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
11324                                 return rte_flow_error_set
11325                                                 (error, errno,
11326                                                  RTE_FLOW_ERROR_TYPE_ACTION,
11327                                                  NULL,
11328                                                  "cannot create jump action.");
11329                         }
11330                         dev_flow->dv.actions[actions_n++] =
11331                                         dev_flow->dv.jump->action;
11332                         action_flags |= MLX5_FLOW_ACTION_JUMP;
11333                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_JUMP;
11334                         sample_act->action_flags |= MLX5_FLOW_ACTION_JUMP;
11335                         num_of_dest++;
11336                         break;
11337                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
11338                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
11339                         if (flow_dv_convert_action_modify_mac
11340                                         (mhdr_res, actions, error))
11341                                 return -rte_errno;
11342                         action_flags |= actions->type ==
11343                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
11344                                         MLX5_FLOW_ACTION_SET_MAC_SRC :
11345                                         MLX5_FLOW_ACTION_SET_MAC_DST;
11346                         break;
11347                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
11348                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
11349                         if (flow_dv_convert_action_modify_ipv4
11350                                         (mhdr_res, actions, error))
11351                                 return -rte_errno;
11352                         action_flags |= actions->type ==
11353                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
11354                                         MLX5_FLOW_ACTION_SET_IPV4_SRC :
11355                                         MLX5_FLOW_ACTION_SET_IPV4_DST;
11356                         break;
11357                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
11358                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
11359                         if (flow_dv_convert_action_modify_ipv6
11360                                         (mhdr_res, actions, error))
11361                                 return -rte_errno;
11362                         action_flags |= actions->type ==
11363                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
11364                                         MLX5_FLOW_ACTION_SET_IPV6_SRC :
11365                                         MLX5_FLOW_ACTION_SET_IPV6_DST;
11366                         break;
11367                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
11368                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
11369                         if (flow_dv_convert_action_modify_tp
11370                                         (mhdr_res, actions, items,
11371                                          &flow_attr, dev_flow, !!(action_flags &
11372                                          MLX5_FLOW_ACTION_DECAP), error))
11373                                 return -rte_errno;
11374                         action_flags |= actions->type ==
11375                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
11376                                         MLX5_FLOW_ACTION_SET_TP_SRC :
11377                                         MLX5_FLOW_ACTION_SET_TP_DST;
11378                         break;
11379                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
11380                         if (flow_dv_convert_action_modify_dec_ttl
11381                                         (mhdr_res, items, &flow_attr, dev_flow,
11382                                          !!(action_flags &
11383                                          MLX5_FLOW_ACTION_DECAP), error))
11384                                 return -rte_errno;
11385                         action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
11386                         break;
11387                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
11388                         if (flow_dv_convert_action_modify_ttl
11389                                         (mhdr_res, actions, items, &flow_attr,
11390                                          dev_flow, !!(action_flags &
11391                                          MLX5_FLOW_ACTION_DECAP), error))
11392                                 return -rte_errno;
11393                         action_flags |= MLX5_FLOW_ACTION_SET_TTL;
11394                         break;
11395                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
11396                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
11397                         if (flow_dv_convert_action_modify_tcp_seq
11398                                         (mhdr_res, actions, error))
11399                                 return -rte_errno;
11400                         action_flags |= actions->type ==
11401                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
11402                                         MLX5_FLOW_ACTION_INC_TCP_SEQ :
11403                                         MLX5_FLOW_ACTION_DEC_TCP_SEQ;
11404                         break;
11405
11406                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
11407                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
11408                         if (flow_dv_convert_action_modify_tcp_ack
11409                                         (mhdr_res, actions, error))
11410                                 return -rte_errno;
11411                         action_flags |= actions->type ==
11412                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
11413                                         MLX5_FLOW_ACTION_INC_TCP_ACK :
11414                                         MLX5_FLOW_ACTION_DEC_TCP_ACK;
11415                         break;
11416                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
11417                         if (flow_dv_convert_action_set_reg
11418                                         (mhdr_res, actions, error))
11419                                 return -rte_errno;
11420                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
11421                         break;
11422                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
11423                         if (flow_dv_convert_action_copy_mreg
11424                                         (dev, mhdr_res, actions, error))
11425                                 return -rte_errno;
11426                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
11427                         break;
11428                 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
11429                         action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
11430                         dev_flow->handle->fate_action =
11431                                         MLX5_FLOW_FATE_DEFAULT_MISS;
11432                         break;
11433                 case RTE_FLOW_ACTION_TYPE_METER:
11434                         mtr = actions->conf;
11435                         if (!flow->meter) {
11436                                 fm = mlx5_flow_meter_attach(priv, mtr->mtr_id,
11437                                                             attr, error);
11438                                 if (!fm)
11439                                         return rte_flow_error_set(error,
11440                                                 rte_errno,
11441                                                 RTE_FLOW_ERROR_TYPE_ACTION,
11442                                                 NULL,
11443                                                 "meter not found "
11444                                                 "or invalid parameters");
11445                                 flow->meter = fm->idx;
11446                         }
11447                         /* Set the meter action. */
11448                         if (!fm) {
11449                                 fm = mlx5_ipool_get(priv->sh->ipool
11450                                                 [MLX5_IPOOL_MTR], flow->meter);
11451                                 if (!fm)
11452                                         return rte_flow_error_set(error,
11453                                                 rte_errno,
11454                                                 RTE_FLOW_ERROR_TYPE_ACTION,
11455                                                 NULL,
11456                                                 "meter not found "
11457                                                 "or invalid parameters");
11458                         }
11459                         dev_flow->dv.actions[actions_n++] =
11460                                 fm->mfts->meter_action;
11461                         action_flags |= MLX5_FLOW_ACTION_METER;
11462                         break;
11463                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
11464                         if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
11465                                                               actions, error))
11466                                 return -rte_errno;
11467                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
11468                         break;
11469                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
11470                         if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
11471                                                               actions, error))
11472                                 return -rte_errno;
11473                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
11474                         break;
11475                 case RTE_FLOW_ACTION_TYPE_SAMPLE:
11476                         sample_act_pos = actions_n;
11477                         sample = (const struct rte_flow_action_sample *)
11478                                  action->conf;
11479                         actions_n++;
11480                         action_flags |= MLX5_FLOW_ACTION_SAMPLE;
11481                         /* put encap action into group if work with port id */
11482                         if ((action_flags & MLX5_FLOW_ACTION_ENCAP) &&
11483                             (action_flags & MLX5_FLOW_ACTION_PORT_ID))
11484                                 sample_act->action_flags |=
11485                                                         MLX5_FLOW_ACTION_ENCAP;
11486                         break;
11487                 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
11488                         if (flow_dv_convert_action_modify_field
11489                                         (dev, mhdr_res, actions, attr, error))
11490                                 return -rte_errno;
11491                         action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
11492                         break;
11493                 case RTE_FLOW_ACTION_TYPE_END:
11494                         actions_end = true;
11495                         if (mhdr_res->actions_num) {
11496                                 /* create modify action if needed. */
11497                                 if (flow_dv_modify_hdr_resource_register
11498                                         (dev, mhdr_res, dev_flow, error))
11499                                         return -rte_errno;
11500                                 dev_flow->dv.actions[modify_action_position] =
11501                                         handle->dvh.modify_hdr->action;
11502                         }
11503                         if (action_flags & MLX5_FLOW_ACTION_COUNT) {
11504                                 /*
11505                                  * Create one count action, to be used
11506                                  * by all sub-flows.
11507                                  */
11508                                 if (!flow->counter) {
11509                                         flow->counter =
11510                                                 flow_dv_translate_create_counter
11511                                                         (dev, dev_flow, count,
11512                                                          age);
11513                                         if (!flow->counter)
11514                                                 return rte_flow_error_set
11515                                                 (error, rte_errno,
11516                                                  RTE_FLOW_ERROR_TYPE_ACTION,
11517                                                  NULL, "cannot create counter"
11518                                                  " object.");
11519                                 }
11520                                 dev_flow->dv.actions[actions_n] =
11521                                           (flow_dv_counter_get_by_idx(dev,
11522                                           flow->counter, NULL))->action;
11523                                 actions_n++;
11524                         }
11525                 default:
11526                         break;
11527                 }
11528                 if (mhdr_res->actions_num &&
11529                     modify_action_position == UINT32_MAX)
11530                         modify_action_position = actions_n++;
11531         }
11532         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
11533                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
11534                 int item_type = items->type;
11535
11536                 if (!mlx5_flow_os_item_supported(item_type))
11537                         return rte_flow_error_set(error, ENOTSUP,
11538                                                   RTE_FLOW_ERROR_TYPE_ITEM,
11539                                                   NULL, "item not supported");
11540                 switch (item_type) {
11541                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
11542                         flow_dv_translate_item_port_id
11543                                 (dev, match_mask, match_value, items, attr);
11544                         last_item = MLX5_FLOW_ITEM_PORT_ID;
11545                         break;
11546                 case RTE_FLOW_ITEM_TYPE_ETH:
11547                         flow_dv_translate_item_eth(match_mask, match_value,
11548                                                    items, tunnel,
11549                                                    dev_flow->dv.group);
11550                         matcher.priority = action_flags &
11551                                         MLX5_FLOW_ACTION_DEFAULT_MISS &&
11552                                         !dev_flow->external ?
11553                                         MLX5_PRIORITY_MAP_L3 :
11554                                         MLX5_PRIORITY_MAP_L2;
11555                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
11556                                              MLX5_FLOW_LAYER_OUTER_L2;
11557                         break;
11558                 case RTE_FLOW_ITEM_TYPE_VLAN:
11559                         flow_dv_translate_item_vlan(dev_flow,
11560                                                     match_mask, match_value,
11561                                                     items, tunnel,
11562                                                     dev_flow->dv.group);
11563                         matcher.priority = MLX5_PRIORITY_MAP_L2;
11564                         last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
11565                                               MLX5_FLOW_LAYER_INNER_VLAN) :
11566                                              (MLX5_FLOW_LAYER_OUTER_L2 |
11567                                               MLX5_FLOW_LAYER_OUTER_VLAN);
11568                         break;
11569                 case RTE_FLOW_ITEM_TYPE_IPV4:
11570                         mlx5_flow_tunnel_ip_check(items, next_protocol,
11571                                                   &item_flags, &tunnel);
11572                         flow_dv_translate_item_ipv4(match_mask, match_value,
11573                                                     items, tunnel,
11574                                                     dev_flow->dv.group);
11575                         matcher.priority = MLX5_PRIORITY_MAP_L3;
11576                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
11577                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
11578                         if (items->mask != NULL &&
11579                             ((const struct rte_flow_item_ipv4 *)
11580                              items->mask)->hdr.next_proto_id) {
11581                                 next_protocol =
11582                                         ((const struct rte_flow_item_ipv4 *)
11583                                          (items->spec))->hdr.next_proto_id;
11584                                 next_protocol &=
11585                                         ((const struct rte_flow_item_ipv4 *)
11586                                          (items->mask))->hdr.next_proto_id;
11587                         } else {
11588                                 /* Reset for inner layer. */
11589                                 next_protocol = 0xff;
11590                         }
11591                         break;
11592                 case RTE_FLOW_ITEM_TYPE_IPV6:
11593                         mlx5_flow_tunnel_ip_check(items, next_protocol,
11594                                                   &item_flags, &tunnel);
11595                         flow_dv_translate_item_ipv6(match_mask, match_value,
11596                                                     items, tunnel,
11597                                                     dev_flow->dv.group);
11598                         matcher.priority = MLX5_PRIORITY_MAP_L3;
11599                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
11600                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
11601                         if (items->mask != NULL &&
11602                             ((const struct rte_flow_item_ipv6 *)
11603                              items->mask)->hdr.proto) {
11604                                 next_protocol =
11605                                         ((const struct rte_flow_item_ipv6 *)
11606                                          items->spec)->hdr.proto;
11607                                 next_protocol &=
11608                                         ((const struct rte_flow_item_ipv6 *)
11609                                          items->mask)->hdr.proto;
11610                         } else {
11611                                 /* Reset for inner layer. */
11612                                 next_protocol = 0xff;
11613                         }
11614                         break;
11615                 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
11616                         flow_dv_translate_item_ipv6_frag_ext(match_mask,
11617                                                              match_value,
11618                                                              items, tunnel);
11619                         last_item = tunnel ?
11620                                         MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
11621                                         MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
11622                         if (items->mask != NULL &&
11623                             ((const struct rte_flow_item_ipv6_frag_ext *)
11624                              items->mask)->hdr.next_header) {
11625                                 next_protocol =
11626                                 ((const struct rte_flow_item_ipv6_frag_ext *)
11627                                  items->spec)->hdr.next_header;
11628                                 next_protocol &=
11629                                 ((const struct rte_flow_item_ipv6_frag_ext *)
11630                                  items->mask)->hdr.next_header;
11631                         } else {
11632                                 /* Reset for inner layer. */
11633                                 next_protocol = 0xff;
11634                         }
11635                         break;
11636                 case RTE_FLOW_ITEM_TYPE_TCP:
11637                         flow_dv_translate_item_tcp(match_mask, match_value,
11638                                                    items, tunnel);
11639                         matcher.priority = MLX5_PRIORITY_MAP_L4;
11640                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
11641                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
11642                         break;
11643                 case RTE_FLOW_ITEM_TYPE_UDP:
11644                         flow_dv_translate_item_udp(match_mask, match_value,
11645                                                    items, tunnel);
11646                         matcher.priority = MLX5_PRIORITY_MAP_L4;
11647                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
11648                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
11649                         break;
11650                 case RTE_FLOW_ITEM_TYPE_GRE:
11651                         flow_dv_translate_item_gre(match_mask, match_value,
11652                                                    items, tunnel);
11653                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11654                         last_item = MLX5_FLOW_LAYER_GRE;
11655                         break;
11656                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
11657                         flow_dv_translate_item_gre_key(match_mask,
11658                                                        match_value, items);
11659                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
11660                         break;
11661                 case RTE_FLOW_ITEM_TYPE_NVGRE:
11662                         flow_dv_translate_item_nvgre(match_mask, match_value,
11663                                                      items, tunnel);
11664                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11665                         last_item = MLX5_FLOW_LAYER_GRE;
11666                         break;
11667                 case RTE_FLOW_ITEM_TYPE_VXLAN:
11668                         flow_dv_translate_item_vxlan(match_mask, match_value,
11669                                                      items, tunnel);
11670                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11671                         last_item = MLX5_FLOW_LAYER_VXLAN;
11672                         break;
11673                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
11674                         flow_dv_translate_item_vxlan_gpe(match_mask,
11675                                                          match_value, items,
11676                                                          tunnel);
11677                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11678                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
11679                         break;
11680                 case RTE_FLOW_ITEM_TYPE_GENEVE:
11681                         flow_dv_translate_item_geneve(match_mask, match_value,
11682                                                       items, tunnel);
11683                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11684                         last_item = MLX5_FLOW_LAYER_GENEVE;
11685                         break;
11686                 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
11687                         ret = flow_dv_translate_item_geneve_opt(dev, match_mask,
11688                                                           match_value,
11689                                                           items, error);
11690                         if (ret)
11691                                 return rte_flow_error_set(error, -ret,
11692                                         RTE_FLOW_ERROR_TYPE_ITEM, NULL,
11693                                         "cannot create GENEVE TLV option");
11694                         flow->geneve_tlv_option = 1;
11695                         last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
11696                         break;
11697                 case RTE_FLOW_ITEM_TYPE_MPLS:
11698                         flow_dv_translate_item_mpls(match_mask, match_value,
11699                                                     items, last_item, tunnel);
11700                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11701                         last_item = MLX5_FLOW_LAYER_MPLS;
11702                         break;
11703                 case RTE_FLOW_ITEM_TYPE_MARK:
11704                         flow_dv_translate_item_mark(dev, match_mask,
11705                                                     match_value, items);
11706                         last_item = MLX5_FLOW_ITEM_MARK;
11707                         break;
11708                 case RTE_FLOW_ITEM_TYPE_META:
11709                         flow_dv_translate_item_meta(dev, match_mask,
11710                                                     match_value, attr, items);
11711                         last_item = MLX5_FLOW_ITEM_METADATA;
11712                         break;
11713                 case RTE_FLOW_ITEM_TYPE_ICMP:
11714                         flow_dv_translate_item_icmp(match_mask, match_value,
11715                                                     items, tunnel);
11716                         last_item = MLX5_FLOW_LAYER_ICMP;
11717                         break;
11718                 case RTE_FLOW_ITEM_TYPE_ICMP6:
11719                         flow_dv_translate_item_icmp6(match_mask, match_value,
11720                                                       items, tunnel);
11721                         last_item = MLX5_FLOW_LAYER_ICMP6;
11722                         break;
11723                 case RTE_FLOW_ITEM_TYPE_TAG:
11724                         flow_dv_translate_item_tag(dev, match_mask,
11725                                                    match_value, items);
11726                         last_item = MLX5_FLOW_ITEM_TAG;
11727                         break;
11728                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
11729                         flow_dv_translate_mlx5_item_tag(dev, match_mask,
11730                                                         match_value, items);
11731                         last_item = MLX5_FLOW_ITEM_TAG;
11732                         break;
11733                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
11734                         flow_dv_translate_item_tx_queue(dev, match_mask,
11735                                                         match_value,
11736                                                         items);
11737                         last_item = MLX5_FLOW_ITEM_TX_QUEUE;
11738                         break;
11739                 case RTE_FLOW_ITEM_TYPE_GTP:
11740                         flow_dv_translate_item_gtp(match_mask, match_value,
11741                                                    items, tunnel);
11742                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11743                         last_item = MLX5_FLOW_LAYER_GTP;
11744                         break;
11745                 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
11746                         ret = flow_dv_translate_item_gtp_psc(match_mask,
11747                                                           match_value,
11748                                                           items);
11749                         if (ret)
11750                                 return rte_flow_error_set(error, -ret,
11751                                         RTE_FLOW_ERROR_TYPE_ITEM, NULL,
11752                                         "cannot create GTP PSC item");
11753                         last_item = MLX5_FLOW_LAYER_GTP_PSC;
11754                         break;
11755                 case RTE_FLOW_ITEM_TYPE_ECPRI:
11756                         if (!mlx5_flex_parser_ecpri_exist(dev)) {
11757                                 /* Create it only the first time to be used. */
11758                                 ret = mlx5_flex_parser_ecpri_alloc(dev);
11759                                 if (ret)
11760                                         return rte_flow_error_set
11761                                                 (error, -ret,
11762                                                 RTE_FLOW_ERROR_TYPE_ITEM,
11763                                                 NULL,
11764                                                 "cannot create eCPRI parser");
11765                         }
11766                         /* Adjust the length matcher and device flow value. */
11767                         matcher.mask.size = MLX5_ST_SZ_BYTES(fte_match_param);
11768                         dev_flow->dv.value.size =
11769                                         MLX5_ST_SZ_BYTES(fte_match_param);
11770                         flow_dv_translate_item_ecpri(dev, match_mask,
11771                                                      match_value, items);
11772                         /* No other protocol should follow eCPRI layer. */
11773                         last_item = MLX5_FLOW_LAYER_ECPRI;
11774                         break;
11775                 default:
11776                         break;
11777                 }
11778                 item_flags |= last_item;
11779         }
11780         /*
11781          * When E-Switch mode is enabled, we have two cases where we need to
11782          * set the source port manually.
11783          * The first one, is in case of Nic steering rule, and the second is
11784          * E-Switch rule where no port_id item was found. In both cases
11785          * the source port is set according the current port in use.
11786          */
11787         if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
11788             (priv->representor || priv->master)) {
11789                 if (flow_dv_translate_item_port_id(dev, match_mask,
11790                                                    match_value, NULL, attr))
11791                         return -rte_errno;
11792         }
11793 #ifdef RTE_LIBRTE_MLX5_DEBUG
11794         MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
11795                                               dev_flow->dv.value.buf));
11796 #endif
11797         /*
11798          * Layers may be already initialized from prefix flow if this dev_flow
11799          * is the suffix flow.
11800          */
11801         handle->layers |= item_flags;
11802         if (action_flags & MLX5_FLOW_ACTION_RSS)
11803                 flow_dv_hashfields_set(dev_flow, rss_desc);
11804         /* If has RSS action in the sample action, the Sample/Mirror resource
11805          * should be registered after the hash filed be update.
11806          */
11807         if (action_flags & MLX5_FLOW_ACTION_SAMPLE) {
11808                 ret = flow_dv_translate_action_sample(dev,
11809                                                       sample,
11810                                                       dev_flow, attr,
11811                                                       &num_of_dest,
11812                                                       sample_actions,
11813                                                       &sample_res,
11814                                                       error);
11815                 if (ret < 0)
11816                         return ret;
11817                 ret = flow_dv_create_action_sample(dev,
11818                                                    dev_flow,
11819                                                    num_of_dest,
11820                                                    &sample_res,
11821                                                    &mdest_res,
11822                                                    sample_actions,
11823                                                    action_flags,
11824                                                    error);
11825                 if (ret < 0)
11826                         return rte_flow_error_set
11827                                                 (error, rte_errno,
11828                                                 RTE_FLOW_ERROR_TYPE_ACTION,
11829                                                 NULL,
11830                                                 "cannot create sample action");
11831                 if (num_of_dest > 1) {
11832                         dev_flow->dv.actions[sample_act_pos] =
11833                         dev_flow->dv.dest_array_res->action;
11834                 } else {
11835                         dev_flow->dv.actions[sample_act_pos] =
11836                         dev_flow->dv.sample_res->verbs_action;
11837                 }
11838         }
11839         /*
11840          * For multiple destination (sample action with ratio=1), the encap
11841          * action and port id action will be combined into group action.
11842          * So need remove the original these actions in the flow and only
11843          * use the sample action instead of.
11844          */
11845         if (num_of_dest > 1 &&
11846             (sample_act->dr_port_id_action || sample_act->dr_jump_action)) {
11847                 int i;
11848                 void *temp_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
11849
11850                 for (i = 0; i < actions_n; i++) {
11851                         if ((sample_act->dr_encap_action &&
11852                                 sample_act->dr_encap_action ==
11853                                 dev_flow->dv.actions[i]) ||
11854                                 (sample_act->dr_port_id_action &&
11855                                 sample_act->dr_port_id_action ==
11856                                 dev_flow->dv.actions[i]) ||
11857                                 (sample_act->dr_jump_action &&
11858                                 sample_act->dr_jump_action ==
11859                                 dev_flow->dv.actions[i]))
11860                                 continue;
11861                         temp_actions[tmp_actions_n++] = dev_flow->dv.actions[i];
11862                 }
11863                 memcpy((void *)dev_flow->dv.actions,
11864                                 (void *)temp_actions,
11865                                 tmp_actions_n * sizeof(void *));
11866                 actions_n = tmp_actions_n;
11867         }
11868         dev_flow->dv.actions_n = actions_n;
11869         dev_flow->act_flags = action_flags;
11870         /* Register matcher. */
11871         matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
11872                                     matcher.mask.size);
11873         matcher.priority = mlx5_get_matcher_priority(dev, attr,
11874                                         matcher.priority);
11875         /* reserved field no needs to be set to 0 here. */
11876         tbl_key.domain = attr->transfer;
11877         tbl_key.direction = attr->egress;
11878         tbl_key.table_id = dev_flow->dv.group;
11879         if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow,
11880                                      tunnel, attr->group, error))
11881                 return -rte_errno;
11882         return 0;
11883 }
11884
11885 /**
11886  * Set hash RX queue by hash fields (see enum ibv_rx_hash_fields)
11887  * and tunnel.
11888  *
11889  * @param[in, out] action
11890  *   Shred RSS action holding hash RX queue objects.
11891  * @param[in] hash_fields
11892  *   Defines combination of packet fields to participate in RX hash.
11893  * @param[in] tunnel
11894  *   Tunnel type
11895  * @param[in] hrxq_idx
11896  *   Hash RX queue index to set.
11897  *
11898  * @return
11899  *   0 on success, otherwise negative errno value.
11900  */
11901 static int
11902 __flow_dv_action_rss_hrxq_set(struct mlx5_shared_action_rss *action,
11903                               const uint64_t hash_fields,
11904                               uint32_t hrxq_idx)
11905 {
11906         uint32_t *hrxqs = action->hrxq;
11907
11908         switch (hash_fields & ~IBV_RX_HASH_INNER) {
11909         case MLX5_RSS_HASH_IPV4:
11910                 /* fall-through. */
11911         case MLX5_RSS_HASH_IPV4_DST_ONLY:
11912                 /* fall-through. */
11913         case MLX5_RSS_HASH_IPV4_SRC_ONLY:
11914                 hrxqs[0] = hrxq_idx;
11915                 return 0;
11916         case MLX5_RSS_HASH_IPV4_TCP:
11917                 /* fall-through. */
11918         case MLX5_RSS_HASH_IPV4_TCP_DST_ONLY:
11919                 /* fall-through. */
11920         case MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY:
11921                 hrxqs[1] = hrxq_idx;
11922                 return 0;
11923         case MLX5_RSS_HASH_IPV4_UDP:
11924                 /* fall-through. */
11925         case MLX5_RSS_HASH_IPV4_UDP_DST_ONLY:
11926                 /* fall-through. */
11927         case MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY:
11928                 hrxqs[2] = hrxq_idx;
11929                 return 0;
11930         case MLX5_RSS_HASH_IPV6:
11931                 /* fall-through. */
11932         case MLX5_RSS_HASH_IPV6_DST_ONLY:
11933                 /* fall-through. */
11934         case MLX5_RSS_HASH_IPV6_SRC_ONLY:
11935                 hrxqs[3] = hrxq_idx;
11936                 return 0;
11937         case MLX5_RSS_HASH_IPV6_TCP:
11938                 /* fall-through. */
11939         case MLX5_RSS_HASH_IPV6_TCP_DST_ONLY:
11940                 /* fall-through. */
11941         case MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY:
11942                 hrxqs[4] = hrxq_idx;
11943                 return 0;
11944         case MLX5_RSS_HASH_IPV6_UDP:
11945                 /* fall-through. */
11946         case MLX5_RSS_HASH_IPV6_UDP_DST_ONLY:
11947                 /* fall-through. */
11948         case MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY:
11949                 hrxqs[5] = hrxq_idx;
11950                 return 0;
11951         case MLX5_RSS_HASH_NONE:
11952                 hrxqs[6] = hrxq_idx;
11953                 return 0;
11954         default:
11955                 return -1;
11956         }
11957 }
11958
11959 /**
11960  * Look up for hash RX queue by hash fields (see enum ibv_rx_hash_fields)
11961  * and tunnel.
11962  *
11963  * @param[in] dev
11964  *   Pointer to the Ethernet device structure.
11965  * @param[in] idx
11966  *   Shared RSS action ID holding hash RX queue objects.
11967  * @param[in] hash_fields
11968  *   Defines combination of packet fields to participate in RX hash.
11969  * @param[in] tunnel
11970  *   Tunnel type
11971  *
11972  * @return
11973  *   Valid hash RX queue index, otherwise 0.
11974  */
11975 static uint32_t
11976 __flow_dv_action_rss_hrxq_lookup(struct rte_eth_dev *dev, uint32_t idx,
11977                                  const uint64_t hash_fields)
11978 {
11979         struct mlx5_priv *priv = dev->data->dev_private;
11980         struct mlx5_shared_action_rss *shared_rss =
11981             mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
11982         const uint32_t *hrxqs = shared_rss->hrxq;
11983
11984         switch (hash_fields & ~IBV_RX_HASH_INNER) {
11985         case MLX5_RSS_HASH_IPV4:
11986                 /* fall-through. */
11987         case MLX5_RSS_HASH_IPV4_DST_ONLY:
11988                 /* fall-through. */
11989         case MLX5_RSS_HASH_IPV4_SRC_ONLY:
11990                 return hrxqs[0];
11991         case MLX5_RSS_HASH_IPV4_TCP:
11992                 /* fall-through. */
11993         case MLX5_RSS_HASH_IPV4_TCP_DST_ONLY:
11994                 /* fall-through. */
11995         case MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY:
11996                 return hrxqs[1];
11997         case MLX5_RSS_HASH_IPV4_UDP:
11998                 /* fall-through. */
11999         case MLX5_RSS_HASH_IPV4_UDP_DST_ONLY:
12000                 /* fall-through. */
12001         case MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY:
12002                 return hrxqs[2];
12003         case MLX5_RSS_HASH_IPV6:
12004                 /* fall-through. */
12005         case MLX5_RSS_HASH_IPV6_DST_ONLY:
12006                 /* fall-through. */
12007         case MLX5_RSS_HASH_IPV6_SRC_ONLY:
12008                 return hrxqs[3];
12009         case MLX5_RSS_HASH_IPV6_TCP:
12010                 /* fall-through. */
12011         case MLX5_RSS_HASH_IPV6_TCP_DST_ONLY:
12012                 /* fall-through. */
12013         case MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY:
12014                 return hrxqs[4];
12015         case MLX5_RSS_HASH_IPV6_UDP:
12016                 /* fall-through. */
12017         case MLX5_RSS_HASH_IPV6_UDP_DST_ONLY:
12018                 /* fall-through. */
12019         case MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY:
12020                 return hrxqs[5];
12021         case MLX5_RSS_HASH_NONE:
12022                 return hrxqs[6];
12023         default:
12024                 return 0;
12025         }
12026
12027 }
12028
12029 /**
12030  * Apply the flow to the NIC, lock free,
12031  * (mutex should be acquired by caller).
12032  *
12033  * @param[in] dev
12034  *   Pointer to the Ethernet device structure.
12035  * @param[in, out] flow
12036  *   Pointer to flow structure.
12037  * @param[out] error
12038  *   Pointer to error structure.
12039  *
12040  * @return
12041  *   0 on success, a negative errno value otherwise and rte_errno is set.
12042  */
12043 static int
12044 flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
12045               struct rte_flow_error *error)
12046 {
12047         struct mlx5_flow_dv_workspace *dv;
12048         struct mlx5_flow_handle *dh;
12049         struct mlx5_flow_handle_dv *dv_h;
12050         struct mlx5_flow *dev_flow;
12051         struct mlx5_priv *priv = dev->data->dev_private;
12052         uint32_t handle_idx;
12053         int n;
12054         int err;
12055         int idx;
12056         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
12057         struct mlx5_flow_rss_desc *rss_desc = &wks->rss_desc;
12058
12059         MLX5_ASSERT(wks);
12060         for (idx = wks->flow_idx - 1; idx >= 0; idx--) {
12061                 dev_flow = &wks->flows[idx];
12062                 dv = &dev_flow->dv;
12063                 dh = dev_flow->handle;
12064                 dv_h = &dh->dvh;
12065                 n = dv->actions_n;
12066                 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
12067                         if (dv->transfer) {
12068                                 MLX5_ASSERT(priv->sh->dr_drop_action);
12069                                 dv->actions[n++] = priv->sh->dr_drop_action;
12070                         } else {
12071 #ifdef HAVE_MLX5DV_DR
12072                                 /* DR supports drop action placeholder. */
12073                                 MLX5_ASSERT(priv->sh->dr_drop_action);
12074                                 dv->actions[n++] = priv->sh->dr_drop_action;
12075 #else
12076                                 /* For DV we use the explicit drop queue. */
12077                                 MLX5_ASSERT(priv->drop_queue.hrxq);
12078                                 dv->actions[n++] =
12079                                                 priv->drop_queue.hrxq->action;
12080 #endif
12081                         }
12082                 } else if ((dh->fate_action == MLX5_FLOW_FATE_QUEUE &&
12083                            !dv_h->rix_sample && !dv_h->rix_dest_array)) {
12084                         struct mlx5_hrxq *hrxq;
12085                         uint32_t hrxq_idx;
12086
12087                         hrxq = flow_dv_hrxq_prepare(dev, dev_flow, rss_desc,
12088                                                     &hrxq_idx);
12089                         if (!hrxq) {
12090                                 rte_flow_error_set
12091                                         (error, rte_errno,
12092                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12093                                          "cannot get hash queue");
12094                                 goto error;
12095                         }
12096                         dh->rix_hrxq = hrxq_idx;
12097                         dv->actions[n++] = hrxq->action;
12098                 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
12099                         struct mlx5_hrxq *hrxq = NULL;
12100                         uint32_t hrxq_idx;
12101
12102                         hrxq_idx = __flow_dv_action_rss_hrxq_lookup(dev,
12103                                                 rss_desc->shared_rss,
12104                                                 dev_flow->hash_fields);
12105                         if (hrxq_idx)
12106                                 hrxq = mlx5_ipool_get
12107                                         (priv->sh->ipool[MLX5_IPOOL_HRXQ],
12108                                          hrxq_idx);
12109                         if (!hrxq) {
12110                                 rte_flow_error_set
12111                                         (error, rte_errno,
12112                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12113                                          "cannot get hash queue");
12114                                 goto error;
12115                         }
12116                         dh->rix_srss = rss_desc->shared_rss;
12117                         dv->actions[n++] = hrxq->action;
12118                 } else if (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS) {
12119                         if (!priv->sh->default_miss_action) {
12120                                 rte_flow_error_set
12121                                         (error, rte_errno,
12122                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12123                                          "default miss action not be created.");
12124                                 goto error;
12125                         }
12126                         dv->actions[n++] = priv->sh->default_miss_action;
12127                 }
12128                 err = mlx5_flow_os_create_flow(dv_h->matcher->matcher_object,
12129                                                (void *)&dv->value, n,
12130                                                dv->actions, &dh->drv_flow);
12131                 if (err) {
12132                         rte_flow_error_set(error, errno,
12133                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12134                                            NULL,
12135                                            "hardware refuses to create flow");
12136                         goto error;
12137                 }
12138                 if (priv->vmwa_context &&
12139                     dh->vf_vlan.tag && !dh->vf_vlan.created) {
12140                         /*
12141                          * The rule contains the VLAN pattern.
12142                          * For VF we are going to create VLAN
12143                          * interface to make hypervisor set correct
12144                          * e-Switch vport context.
12145                          */
12146                         mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
12147                 }
12148         }
12149         return 0;
12150 error:
12151         err = rte_errno; /* Save rte_errno before cleanup. */
12152         SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles,
12153                        handle_idx, dh, next) {
12154                 /* hrxq is union, don't clear it if the flag is not set. */
12155                 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE && dh->rix_hrxq) {
12156                         mlx5_hrxq_release(dev, dh->rix_hrxq);
12157                         dh->rix_hrxq = 0;
12158                 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
12159                         dh->rix_srss = 0;
12160                 }
12161                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
12162                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
12163         }
12164         rte_errno = err; /* Restore rte_errno. */
12165         return -rte_errno;
12166 }
12167
12168 void
12169 flow_dv_matcher_remove_cb(struct mlx5_cache_list *list __rte_unused,
12170                           struct mlx5_cache_entry *entry)
12171 {
12172         struct mlx5_flow_dv_matcher *cache = container_of(entry, typeof(*cache),
12173                                                           entry);
12174
12175         claim_zero(mlx5_flow_os_destroy_flow_matcher(cache->matcher_object));
12176         mlx5_free(cache);
12177 }
12178
12179 /**
12180  * Release the flow matcher.
12181  *
12182  * @param dev
12183  *   Pointer to Ethernet device.
12184  * @param port_id
12185  *   Index to port ID action resource.
12186  *
12187  * @return
12188  *   1 while a reference on it exists, 0 when freed.
12189  */
12190 static int
12191 flow_dv_matcher_release(struct rte_eth_dev *dev,
12192                         struct mlx5_flow_handle *handle)
12193 {
12194         struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
12195         struct mlx5_flow_tbl_data_entry *tbl = container_of(matcher->tbl,
12196                                                             typeof(*tbl), tbl);
12197         int ret;
12198
12199         MLX5_ASSERT(matcher->matcher_object);
12200         ret = mlx5_cache_unregister(&tbl->matchers, &matcher->entry);
12201         flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl->tbl);
12202         return ret;
12203 }
12204
12205 /**
12206  * Release encap_decap resource.
12207  *
12208  * @param list
12209  *   Pointer to the hash list.
12210  * @param entry
12211  *   Pointer to exist resource entry object.
12212  */
12213 void
12214 flow_dv_encap_decap_remove_cb(struct mlx5_hlist *list,
12215                               struct mlx5_hlist_entry *entry)
12216 {
12217         struct mlx5_dev_ctx_shared *sh = list->ctx;
12218         struct mlx5_flow_dv_encap_decap_resource *res =
12219                 container_of(entry, typeof(*res), entry);
12220
12221         claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
12222         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], res->idx);
12223 }
12224
12225 /**
12226  * Release an encap/decap resource.
12227  *
12228  * @param dev
12229  *   Pointer to Ethernet device.
12230  * @param encap_decap_idx
12231  *   Index of encap decap resource.
12232  *
12233  * @return
12234  *   1 while a reference on it exists, 0 when freed.
12235  */
12236 static int
12237 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
12238                                      uint32_t encap_decap_idx)
12239 {
12240         struct mlx5_priv *priv = dev->data->dev_private;
12241         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
12242
12243         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
12244                                         encap_decap_idx);
12245         if (!cache_resource)
12246                 return 0;
12247         MLX5_ASSERT(cache_resource->action);
12248         return mlx5_hlist_unregister(priv->sh->encaps_decaps,
12249                                      &cache_resource->entry);
12250 }
12251
12252 /**
12253  * Release an jump to table action resource.
12254  *
12255  * @param dev
12256  *   Pointer to Ethernet device.
12257  * @param rix_jump
12258  *   Index to the jump action resource.
12259  *
12260  * @return
12261  *   1 while a reference on it exists, 0 when freed.
12262  */
12263 static int
12264 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
12265                                   uint32_t rix_jump)
12266 {
12267         struct mlx5_priv *priv = dev->data->dev_private;
12268         struct mlx5_flow_tbl_data_entry *tbl_data;
12269
12270         tbl_data = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_JUMP],
12271                                   rix_jump);
12272         if (!tbl_data)
12273                 return 0;
12274         return flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl_data->tbl);
12275 }
12276
12277 void
12278 flow_dv_modify_remove_cb(struct mlx5_hlist *list __rte_unused,
12279                          struct mlx5_hlist_entry *entry)
12280 {
12281         struct mlx5_flow_dv_modify_hdr_resource *res =
12282                 container_of(entry, typeof(*res), entry);
12283
12284         claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
12285         mlx5_free(entry);
12286 }
12287
12288 /**
12289  * Release a modify-header resource.
12290  *
12291  * @param dev
12292  *   Pointer to Ethernet device.
12293  * @param handle
12294  *   Pointer to mlx5_flow_handle.
12295  *
12296  * @return
12297  *   1 while a reference on it exists, 0 when freed.
12298  */
12299 static int
12300 flow_dv_modify_hdr_resource_release(struct rte_eth_dev *dev,
12301                                     struct mlx5_flow_handle *handle)
12302 {
12303         struct mlx5_priv *priv = dev->data->dev_private;
12304         struct mlx5_flow_dv_modify_hdr_resource *entry = handle->dvh.modify_hdr;
12305
12306         MLX5_ASSERT(entry->action);
12307         return mlx5_hlist_unregister(priv->sh->modify_cmds, &entry->entry);
12308 }
12309
12310 void
12311 flow_dv_port_id_remove_cb(struct mlx5_cache_list *list,
12312                           struct mlx5_cache_entry *entry)
12313 {
12314         struct mlx5_dev_ctx_shared *sh = list->ctx;
12315         struct mlx5_flow_dv_port_id_action_resource *cache =
12316                         container_of(entry, typeof(*cache), entry);
12317
12318         claim_zero(mlx5_flow_os_destroy_flow_action(cache->action));
12319         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], cache->idx);
12320 }
12321
12322 /**
12323  * Release port ID action resource.
12324  *
12325  * @param dev
12326  *   Pointer to Ethernet device.
12327  * @param handle
12328  *   Pointer to mlx5_flow_handle.
12329  *
12330  * @return
12331  *   1 while a reference on it exists, 0 when freed.
12332  */
12333 static int
12334 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
12335                                         uint32_t port_id)
12336 {
12337         struct mlx5_priv *priv = dev->data->dev_private;
12338         struct mlx5_flow_dv_port_id_action_resource *cache;
12339
12340         cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID], port_id);
12341         if (!cache)
12342                 return 0;
12343         MLX5_ASSERT(cache->action);
12344         return mlx5_cache_unregister(&priv->sh->port_id_action_list,
12345                                      &cache->entry);
12346 }
12347
12348 /**
12349  * Release shared RSS action resource.
12350  *
12351  * @param dev
12352  *   Pointer to Ethernet device.
12353  * @param srss
12354  *   Shared RSS action index.
12355  */
12356 static void
12357 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss)
12358 {
12359         struct mlx5_priv *priv = dev->data->dev_private;
12360         struct mlx5_shared_action_rss *shared_rss;
12361
12362         shared_rss = mlx5_ipool_get
12363                         (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], srss);
12364         __atomic_sub_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
12365 }
12366
12367 void
12368 flow_dv_push_vlan_remove_cb(struct mlx5_cache_list *list,
12369                             struct mlx5_cache_entry *entry)
12370 {
12371         struct mlx5_dev_ctx_shared *sh = list->ctx;
12372         struct mlx5_flow_dv_push_vlan_action_resource *cache =
12373                         container_of(entry, typeof(*cache), entry);
12374
12375         claim_zero(mlx5_flow_os_destroy_flow_action(cache->action));
12376         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], cache->idx);
12377 }
12378
12379 /**
12380  * Release push vlan action resource.
12381  *
12382  * @param dev
12383  *   Pointer to Ethernet device.
12384  * @param handle
12385  *   Pointer to mlx5_flow_handle.
12386  *
12387  * @return
12388  *   1 while a reference on it exists, 0 when freed.
12389  */
12390 static int
12391 flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,
12392                                           struct mlx5_flow_handle *handle)
12393 {
12394         struct mlx5_priv *priv = dev->data->dev_private;
12395         struct mlx5_flow_dv_push_vlan_action_resource *cache;
12396         uint32_t idx = handle->dvh.rix_push_vlan;
12397
12398         cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
12399         if (!cache)
12400                 return 0;
12401         MLX5_ASSERT(cache->action);
12402         return mlx5_cache_unregister(&priv->sh->push_vlan_action_list,
12403                                      &cache->entry);
12404 }
12405
12406 /**
12407  * Release the fate resource.
12408  *
12409  * @param dev
12410  *   Pointer to Ethernet device.
12411  * @param handle
12412  *   Pointer to mlx5_flow_handle.
12413  */
12414 static void
12415 flow_dv_fate_resource_release(struct rte_eth_dev *dev,
12416                                struct mlx5_flow_handle *handle)
12417 {
12418         if (!handle->rix_fate)
12419                 return;
12420         switch (handle->fate_action) {
12421         case MLX5_FLOW_FATE_QUEUE:
12422                 mlx5_hrxq_release(dev, handle->rix_hrxq);
12423                 break;
12424         case MLX5_FLOW_FATE_JUMP:
12425                 flow_dv_jump_tbl_resource_release(dev, handle->rix_jump);
12426                 break;
12427         case MLX5_FLOW_FATE_PORT_ID:
12428                 flow_dv_port_id_action_resource_release(dev,
12429                                 handle->rix_port_id_action);
12430                 break;
12431         default:
12432                 DRV_LOG(DEBUG, "Incorrect fate action:%d", handle->fate_action);
12433                 break;
12434         }
12435         handle->rix_fate = 0;
12436 }
12437
12438 void
12439 flow_dv_sample_remove_cb(struct mlx5_cache_list *list __rte_unused,
12440                          struct mlx5_cache_entry *entry)
12441 {
12442         struct mlx5_flow_dv_sample_resource *cache_resource =
12443                         container_of(entry, typeof(*cache_resource), entry);
12444         struct rte_eth_dev *dev = cache_resource->dev;
12445         struct mlx5_priv *priv = dev->data->dev_private;
12446
12447         if (cache_resource->verbs_action)
12448                 claim_zero(mlx5_flow_os_destroy_flow_action
12449                                 (cache_resource->verbs_action));
12450         if (cache_resource->normal_path_tbl)
12451                 flow_dv_tbl_resource_release(MLX5_SH(dev),
12452                         cache_resource->normal_path_tbl);
12453         flow_dv_sample_sub_actions_release(dev,
12454                                 &cache_resource->sample_idx);
12455         mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
12456                         cache_resource->idx);
12457         DRV_LOG(DEBUG, "sample resource %p: removed",
12458                 (void *)cache_resource);
12459 }
12460
12461 /**
12462  * Release an sample resource.
12463  *
12464  * @param dev
12465  *   Pointer to Ethernet device.
12466  * @param handle
12467  *   Pointer to mlx5_flow_handle.
12468  *
12469  * @return
12470  *   1 while a reference on it exists, 0 when freed.
12471  */
12472 static int
12473 flow_dv_sample_resource_release(struct rte_eth_dev *dev,
12474                                      struct mlx5_flow_handle *handle)
12475 {
12476         struct mlx5_priv *priv = dev->data->dev_private;
12477         struct mlx5_flow_dv_sample_resource *cache_resource;
12478
12479         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
12480                          handle->dvh.rix_sample);
12481         if (!cache_resource)
12482                 return 0;
12483         MLX5_ASSERT(cache_resource->verbs_action);
12484         return mlx5_cache_unregister(&priv->sh->sample_action_list,
12485                                      &cache_resource->entry);
12486 }
12487
12488 void
12489 flow_dv_dest_array_remove_cb(struct mlx5_cache_list *list __rte_unused,
12490                              struct mlx5_cache_entry *entry)
12491 {
12492         struct mlx5_flow_dv_dest_array_resource *cache_resource =
12493                         container_of(entry, typeof(*cache_resource), entry);
12494         struct rte_eth_dev *dev = cache_resource->dev;
12495         struct mlx5_priv *priv = dev->data->dev_private;
12496         uint32_t i = 0;
12497
12498         MLX5_ASSERT(cache_resource->action);
12499         if (cache_resource->action)
12500                 claim_zero(mlx5_flow_os_destroy_flow_action
12501                                         (cache_resource->action));
12502         for (; i < cache_resource->num_of_dest; i++)
12503                 flow_dv_sample_sub_actions_release(dev,
12504                                 &cache_resource->sample_idx[i]);
12505         mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
12506                         cache_resource->idx);
12507         DRV_LOG(DEBUG, "destination array resource %p: removed",
12508                 (void *)cache_resource);
12509 }
12510
12511 /**
12512  * Release an destination array resource.
12513  *
12514  * @param dev
12515  *   Pointer to Ethernet device.
12516  * @param handle
12517  *   Pointer to mlx5_flow_handle.
12518  *
12519  * @return
12520  *   1 while a reference on it exists, 0 when freed.
12521  */
12522 static int
12523 flow_dv_dest_array_resource_release(struct rte_eth_dev *dev,
12524                                     struct mlx5_flow_handle *handle)
12525 {
12526         struct mlx5_priv *priv = dev->data->dev_private;
12527         struct mlx5_flow_dv_dest_array_resource *cache;
12528
12529         cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
12530                                handle->dvh.rix_dest_array);
12531         if (!cache)
12532                 return 0;
12533         MLX5_ASSERT(cache->action);
12534         return mlx5_cache_unregister(&priv->sh->dest_array_list,
12535                                      &cache->entry);
12536 }
12537
12538 static void
12539 flow_dv_geneve_tlv_option_resource_release(struct rte_eth_dev *dev)
12540 {
12541         struct mlx5_priv *priv = dev->data->dev_private;
12542         struct mlx5_dev_ctx_shared *sh = priv->sh;
12543         struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
12544                                 sh->geneve_tlv_option_resource;
12545         rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
12546         if (geneve_opt_resource) {
12547                 if (!(__atomic_sub_fetch(&geneve_opt_resource->refcnt, 1,
12548                                          __ATOMIC_RELAXED))) {
12549                         claim_zero(mlx5_devx_cmd_destroy
12550                                         (geneve_opt_resource->obj));
12551                         mlx5_free(sh->geneve_tlv_option_resource);
12552                         sh->geneve_tlv_option_resource = NULL;
12553                 }
12554         }
12555         rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
12556 }
12557
12558 /**
12559  * Remove the flow from the NIC but keeps it in memory.
12560  * Lock free, (mutex should be acquired by caller).
12561  *
12562  * @param[in] dev
12563  *   Pointer to Ethernet device.
12564  * @param[in, out] flow
12565  *   Pointer to flow structure.
12566  */
12567 static void
12568 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
12569 {
12570         struct mlx5_flow_handle *dh;
12571         uint32_t handle_idx;
12572         struct mlx5_priv *priv = dev->data->dev_private;
12573
12574         if (!flow)
12575                 return;
12576         handle_idx = flow->dev_handles;
12577         while (handle_idx) {
12578                 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
12579                                     handle_idx);
12580                 if (!dh)
12581                         return;
12582                 if (dh->drv_flow) {
12583                         claim_zero(mlx5_flow_os_destroy_flow(dh->drv_flow));
12584                         dh->drv_flow = NULL;
12585                 }
12586                 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE)
12587                         flow_dv_fate_resource_release(dev, dh);
12588                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
12589                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
12590                 handle_idx = dh->next.next;
12591         }
12592 }
12593
12594 /**
12595  * Remove the flow from the NIC and the memory.
12596  * Lock free, (mutex should be acquired by caller).
12597  *
12598  * @param[in] dev
12599  *   Pointer to the Ethernet device structure.
12600  * @param[in, out] flow
12601  *   Pointer to flow structure.
12602  */
12603 static void
12604 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
12605 {
12606         struct mlx5_flow_handle *dev_handle;
12607         struct mlx5_priv *priv = dev->data->dev_private;
12608         uint32_t srss = 0;
12609
12610         if (!flow)
12611                 return;
12612         flow_dv_remove(dev, flow);
12613         if (flow->counter) {
12614                 flow_dv_counter_free(dev, flow->counter);
12615                 flow->counter = 0;
12616         }
12617         if (flow->meter) {
12618                 struct mlx5_flow_meter *fm;
12619
12620                 fm = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MTR],
12621                                     flow->meter);
12622                 if (fm)
12623                         mlx5_flow_meter_detach(fm);
12624                 flow->meter = 0;
12625         }
12626         if (flow->age)
12627                 flow_dv_aso_age_release(dev, flow->age);
12628         if (flow->geneve_tlv_option) {
12629                 flow_dv_geneve_tlv_option_resource_release(dev);
12630                 flow->geneve_tlv_option = 0;
12631         }
12632         while (flow->dev_handles) {
12633                 uint32_t tmp_idx = flow->dev_handles;
12634
12635                 dev_handle = mlx5_ipool_get(priv->sh->ipool
12636                                             [MLX5_IPOOL_MLX5_FLOW], tmp_idx);
12637                 if (!dev_handle)
12638                         return;
12639                 flow->dev_handles = dev_handle->next.next;
12640                 if (dev_handle->dvh.matcher)
12641                         flow_dv_matcher_release(dev, dev_handle);
12642                 if (dev_handle->dvh.rix_sample)
12643                         flow_dv_sample_resource_release(dev, dev_handle);
12644                 if (dev_handle->dvh.rix_dest_array)
12645                         flow_dv_dest_array_resource_release(dev, dev_handle);
12646                 if (dev_handle->dvh.rix_encap_decap)
12647                         flow_dv_encap_decap_resource_release(dev,
12648                                 dev_handle->dvh.rix_encap_decap);
12649                 if (dev_handle->dvh.modify_hdr)
12650                         flow_dv_modify_hdr_resource_release(dev, dev_handle);
12651                 if (dev_handle->dvh.rix_push_vlan)
12652                         flow_dv_push_vlan_action_resource_release(dev,
12653                                                                   dev_handle);
12654                 if (dev_handle->dvh.rix_tag)
12655                         flow_dv_tag_release(dev,
12656                                             dev_handle->dvh.rix_tag);
12657                 if (dev_handle->fate_action != MLX5_FLOW_FATE_SHARED_RSS)
12658                         flow_dv_fate_resource_release(dev, dev_handle);
12659                 else if (!srss)
12660                         srss = dev_handle->rix_srss;
12661                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
12662                            tmp_idx);
12663         }
12664         if (srss)
12665                 flow_dv_shared_rss_action_release(dev, srss);
12666 }
12667
12668 /**
12669  * Release array of hash RX queue objects.
12670  * Helper function.
12671  *
12672  * @param[in] dev
12673  *   Pointer to the Ethernet device structure.
12674  * @param[in, out] hrxqs
12675  *   Array of hash RX queue objects.
12676  *
12677  * @return
12678  *   Total number of references to hash RX queue objects in *hrxqs* array
12679  *   after this operation.
12680  */
12681 static int
12682 __flow_dv_hrxqs_release(struct rte_eth_dev *dev,
12683                         uint32_t (*hrxqs)[MLX5_RSS_HASH_FIELDS_LEN])
12684 {
12685         size_t i;
12686         int remaining = 0;
12687
12688         for (i = 0; i < RTE_DIM(*hrxqs); i++) {
12689                 int ret = mlx5_hrxq_release(dev, (*hrxqs)[i]);
12690
12691                 if (!ret)
12692                         (*hrxqs)[i] = 0;
12693                 remaining += ret;
12694         }
12695         return remaining;
12696 }
12697
12698 /**
12699  * Release all hash RX queue objects representing shared RSS action.
12700  *
12701  * @param[in] dev
12702  *   Pointer to the Ethernet device structure.
12703  * @param[in, out] action
12704  *   Shared RSS action to remove hash RX queue objects from.
12705  *
12706  * @return
12707  *   Total number of references to hash RX queue objects stored in *action*
12708  *   after this operation.
12709  *   Expected to be 0 if no external references held.
12710  */
12711 static int
12712 __flow_dv_action_rss_hrxqs_release(struct rte_eth_dev *dev,
12713                                  struct mlx5_shared_action_rss *shared_rss)
12714 {
12715         return __flow_dv_hrxqs_release(dev, &shared_rss->hrxq);
12716 }
12717
12718 /**
12719  * Adjust L3/L4 hash value of pre-created shared RSS hrxq according to
12720  * user input.
12721  *
12722  * Only one hash value is available for one L3+L4 combination:
12723  * for example:
12724  * MLX5_RSS_HASH_IPV4, MLX5_RSS_HASH_IPV4_SRC_ONLY, and
12725  * MLX5_RSS_HASH_IPV4_DST_ONLY are mutually exclusive so they can share
12726  * same slot in mlx5_rss_hash_fields.
12727  *
12728  * @param[in] rss
12729  *   Pointer to the shared action RSS conf.
12730  * @param[in, out] hash_field
12731  *   hash_field variable needed to be adjusted.
12732  *
12733  * @return
12734  *   void
12735  */
12736 static void
12737 __flow_dv_action_rss_l34_hash_adjust(struct mlx5_shared_action_rss *rss,
12738                                      uint64_t *hash_field)
12739 {
12740         uint64_t rss_types = rss->origin.types;
12741
12742         switch (*hash_field & ~IBV_RX_HASH_INNER) {
12743         case MLX5_RSS_HASH_IPV4:
12744                 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
12745                         *hash_field &= ~MLX5_RSS_HASH_IPV4;
12746                         if (rss_types & ETH_RSS_L3_DST_ONLY)
12747                                 *hash_field |= IBV_RX_HASH_DST_IPV4;
12748                         else if (rss_types & ETH_RSS_L3_SRC_ONLY)
12749                                 *hash_field |= IBV_RX_HASH_SRC_IPV4;
12750                         else
12751                                 *hash_field |= MLX5_RSS_HASH_IPV4;
12752                 }
12753                 return;
12754         case MLX5_RSS_HASH_IPV6:
12755                 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
12756                         *hash_field &= ~MLX5_RSS_HASH_IPV6;
12757                         if (rss_types & ETH_RSS_L3_DST_ONLY)
12758                                 *hash_field |= IBV_RX_HASH_DST_IPV6;
12759                         else if (rss_types & ETH_RSS_L3_SRC_ONLY)
12760                                 *hash_field |= IBV_RX_HASH_SRC_IPV6;
12761                         else
12762                                 *hash_field |= MLX5_RSS_HASH_IPV6;
12763                 }
12764                 return;
12765         case MLX5_RSS_HASH_IPV4_UDP:
12766                 /* fall-through. */
12767         case MLX5_RSS_HASH_IPV6_UDP:
12768                 if (rss_types & ETH_RSS_UDP) {
12769                         *hash_field &= ~MLX5_UDP_IBV_RX_HASH;
12770                         if (rss_types & ETH_RSS_L4_DST_ONLY)
12771                                 *hash_field |= IBV_RX_HASH_DST_PORT_UDP;
12772                         else if (rss_types & ETH_RSS_L4_SRC_ONLY)
12773                                 *hash_field |= IBV_RX_HASH_SRC_PORT_UDP;
12774                         else
12775                                 *hash_field |= MLX5_UDP_IBV_RX_HASH;
12776                 }
12777                 return;
12778         case MLX5_RSS_HASH_IPV4_TCP:
12779                 /* fall-through. */
12780         case MLX5_RSS_HASH_IPV6_TCP:
12781                 if (rss_types & ETH_RSS_TCP) {
12782                         *hash_field &= ~MLX5_TCP_IBV_RX_HASH;
12783                         if (rss_types & ETH_RSS_L4_DST_ONLY)
12784                                 *hash_field |= IBV_RX_HASH_DST_PORT_TCP;
12785                         else if (rss_types & ETH_RSS_L4_SRC_ONLY)
12786                                 *hash_field |= IBV_RX_HASH_SRC_PORT_TCP;
12787                         else
12788                                 *hash_field |= MLX5_TCP_IBV_RX_HASH;
12789                 }
12790                 return;
12791         default:
12792                 return;
12793         }
12794 }
12795
12796 /**
12797  * Setup shared RSS action.
12798  * Prepare set of hash RX queue objects sufficient to handle all valid
12799  * hash_fields combinations (see enum ibv_rx_hash_fields).
12800  *
12801  * @param[in] dev
12802  *   Pointer to the Ethernet device structure.
12803  * @param[in] action_idx
12804  *   Shared RSS action ipool index.
12805  * @param[in, out] action
12806  *   Partially initialized shared RSS action.
12807  * @param[out] error
12808  *   Perform verbose error reporting if not NULL. Initialized in case of
12809  *   error only.
12810  *
12811  * @return
12812  *   0 on success, otherwise negative errno value.
12813  */
12814 static int
12815 __flow_dv_action_rss_setup(struct rte_eth_dev *dev,
12816                            uint32_t action_idx,
12817                            struct mlx5_shared_action_rss *shared_rss,
12818                            struct rte_flow_error *error)
12819 {
12820         struct mlx5_flow_rss_desc rss_desc = { 0 };
12821         size_t i;
12822         int err;
12823
12824         if (mlx5_ind_table_obj_setup(dev, shared_rss->ind_tbl)) {
12825                 return rte_flow_error_set(error, rte_errno,
12826                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12827                                           "cannot setup indirection table");
12828         }
12829         memcpy(rss_desc.key, shared_rss->origin.key, MLX5_RSS_HASH_KEY_LEN);
12830         rss_desc.key_len = MLX5_RSS_HASH_KEY_LEN;
12831         rss_desc.const_q = shared_rss->origin.queue;
12832         rss_desc.queue_num = shared_rss->origin.queue_num;
12833         /* Set non-zero value to indicate a shared RSS. */
12834         rss_desc.shared_rss = action_idx;
12835         rss_desc.ind_tbl = shared_rss->ind_tbl;
12836         for (i = 0; i < MLX5_RSS_HASH_FIELDS_LEN; i++) {
12837                 uint32_t hrxq_idx;
12838                 uint64_t hash_fields = mlx5_rss_hash_fields[i];
12839                 int tunnel = 0;
12840
12841                 __flow_dv_action_rss_l34_hash_adjust(shared_rss, &hash_fields);
12842                 if (shared_rss->origin.level > 1) {
12843                         hash_fields |= IBV_RX_HASH_INNER;
12844                         tunnel = 1;
12845                 }
12846                 rss_desc.tunnel = tunnel;
12847                 rss_desc.hash_fields = hash_fields;
12848                 hrxq_idx = mlx5_hrxq_get(dev, &rss_desc);
12849                 if (!hrxq_idx) {
12850                         rte_flow_error_set
12851                                 (error, rte_errno,
12852                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12853                                  "cannot get hash queue");
12854                         goto error_hrxq_new;
12855                 }
12856                 err = __flow_dv_action_rss_hrxq_set
12857                         (shared_rss, hash_fields, hrxq_idx);
12858                 MLX5_ASSERT(!err);
12859         }
12860         return 0;
12861 error_hrxq_new:
12862         err = rte_errno;
12863         __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
12864         if (!mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl, true))
12865                 shared_rss->ind_tbl = NULL;
12866         rte_errno = err;
12867         return -rte_errno;
12868 }
12869
12870 /**
12871  * Create shared RSS action.
12872  *
12873  * @param[in] dev
12874  *   Pointer to the Ethernet device structure.
12875  * @param[in] conf
12876  *   Shared action configuration.
12877  * @param[in] rss
12878  *   RSS action specification used to create shared action.
12879  * @param[out] error
12880  *   Perform verbose error reporting if not NULL. Initialized in case of
12881  *   error only.
12882  *
12883  * @return
12884  *   A valid shared action ID in case of success, 0 otherwise and
12885  *   rte_errno is set.
12886  */
12887 static uint32_t
12888 __flow_dv_action_rss_create(struct rte_eth_dev *dev,
12889                             const struct rte_flow_shared_action_conf *conf,
12890                             const struct rte_flow_action_rss *rss,
12891                             struct rte_flow_error *error)
12892 {
12893         struct mlx5_priv *priv = dev->data->dev_private;
12894         struct mlx5_shared_action_rss *shared_rss = NULL;
12895         void *queue = NULL;
12896         struct rte_flow_action_rss *origin;
12897         const uint8_t *rss_key;
12898         uint32_t queue_size = rss->queue_num * sizeof(uint16_t);
12899         uint32_t idx;
12900
12901         RTE_SET_USED(conf);
12902         queue = mlx5_malloc(0, RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
12903                             0, SOCKET_ID_ANY);
12904         shared_rss = mlx5_ipool_zmalloc
12905                          (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], &idx);
12906         if (!shared_rss || !queue) {
12907                 rte_flow_error_set(error, ENOMEM,
12908                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12909                                    "cannot allocate resource memory");
12910                 goto error_rss_init;
12911         }
12912         if (idx > (1u << MLX5_SHARED_ACTION_TYPE_OFFSET)) {
12913                 rte_flow_error_set(error, E2BIG,
12914                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12915                                    "rss action number out of range");
12916                 goto error_rss_init;
12917         }
12918         shared_rss->ind_tbl = mlx5_malloc(MLX5_MEM_ZERO,
12919                                           sizeof(*shared_rss->ind_tbl),
12920                                           0, SOCKET_ID_ANY);
12921         if (!shared_rss->ind_tbl) {
12922                 rte_flow_error_set(error, ENOMEM,
12923                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12924                                    "cannot allocate resource memory");
12925                 goto error_rss_init;
12926         }
12927         memcpy(queue, rss->queue, queue_size);
12928         shared_rss->ind_tbl->queues = queue;
12929         shared_rss->ind_tbl->queues_n = rss->queue_num;
12930         origin = &shared_rss->origin;
12931         origin->func = rss->func;
12932         origin->level = rss->level;
12933         /* RSS type 0 indicates default RSS type (ETH_RSS_IP). */
12934         origin->types = !rss->types ? ETH_RSS_IP : rss->types;
12935         /* NULL RSS key indicates default RSS key. */
12936         rss_key = !rss->key ? rss_hash_default_key : rss->key;
12937         memcpy(shared_rss->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
12938         origin->key = &shared_rss->key[0];
12939         origin->key_len = MLX5_RSS_HASH_KEY_LEN;
12940         origin->queue = queue;
12941         origin->queue_num = rss->queue_num;
12942         if (__flow_dv_action_rss_setup(dev, idx, shared_rss, error))
12943                 goto error_rss_init;
12944         rte_spinlock_init(&shared_rss->action_rss_sl);
12945         __atomic_add_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
12946         rte_spinlock_lock(&priv->shared_act_sl);
12947         ILIST_INSERT(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
12948                      &priv->rss_shared_actions, idx, shared_rss, next);
12949         rte_spinlock_unlock(&priv->shared_act_sl);
12950         return idx;
12951 error_rss_init:
12952         if (shared_rss) {
12953                 if (shared_rss->ind_tbl)
12954                         mlx5_free(shared_rss->ind_tbl);
12955                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
12956                                 idx);
12957         }
12958         if (queue)
12959                 mlx5_free(queue);
12960         return 0;
12961 }
12962
12963 /**
12964  * Destroy the shared RSS action.
12965  * Release related hash RX queue objects.
12966  *
12967  * @param[in] dev
12968  *   Pointer to the Ethernet device structure.
12969  * @param[in] idx
12970  *   The shared RSS action object ID to be removed.
12971  * @param[out] error
12972  *   Perform verbose error reporting if not NULL. Initialized in case of
12973  *   error only.
12974  *
12975  * @return
12976  *   0 on success, otherwise negative errno value.
12977  */
12978 static int
12979 __flow_dv_action_rss_release(struct rte_eth_dev *dev, uint32_t idx,
12980                              struct rte_flow_error *error)
12981 {
12982         struct mlx5_priv *priv = dev->data->dev_private;
12983         struct mlx5_shared_action_rss *shared_rss =
12984             mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
12985         uint32_t old_refcnt = 1;
12986         int remaining;
12987         uint16_t *queue = NULL;
12988
12989         if (!shared_rss)
12990                 return rte_flow_error_set(error, EINVAL,
12991                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12992                                           "invalid shared action");
12993         remaining = __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
12994         if (remaining)
12995                 return rte_flow_error_set(error, EBUSY,
12996                                           RTE_FLOW_ERROR_TYPE_ACTION,
12997                                           NULL,
12998                                           "shared rss hrxq has references");
12999         if (!__atomic_compare_exchange_n(&shared_rss->refcnt, &old_refcnt,
13000                                          0, 0, __ATOMIC_ACQUIRE,
13001                                          __ATOMIC_RELAXED))
13002                 return rte_flow_error_set(error, EBUSY,
13003                                           RTE_FLOW_ERROR_TYPE_ACTION,
13004                                           NULL,
13005                                           "shared rss has references");
13006         queue = shared_rss->ind_tbl->queues;
13007         remaining = mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl, true);
13008         if (remaining)
13009                 return rte_flow_error_set(error, EBUSY,
13010                                           RTE_FLOW_ERROR_TYPE_ACTION,
13011                                           NULL,
13012                                           "shared rss indirection table has"
13013                                           " references");
13014         mlx5_free(queue);
13015         rte_spinlock_lock(&priv->shared_act_sl);
13016         ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
13017                      &priv->rss_shared_actions, idx, shared_rss, next);
13018         rte_spinlock_unlock(&priv->shared_act_sl);
13019         mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
13020                         idx);
13021         return 0;
13022 }
13023
13024 /**
13025  * Create shared action, lock free,
13026  * (mutex should be acquired by caller).
13027  * Dispatcher for action type specific call.
13028  *
13029  * @param[in] dev
13030  *   Pointer to the Ethernet device structure.
13031  * @param[in] conf
13032  *   Shared action configuration.
13033  * @param[in] action
13034  *   Action specification used to create shared action.
13035  * @param[out] error
13036  *   Perform verbose error reporting if not NULL. Initialized in case of
13037  *   error only.
13038  *
13039  * @return
13040  *   A valid shared action handle in case of success, NULL otherwise and
13041  *   rte_errno is set.
13042  */
13043 static struct rte_flow_shared_action *
13044 flow_dv_action_create(struct rte_eth_dev *dev,
13045                       const struct rte_flow_shared_action_conf *conf,
13046                       const struct rte_flow_action *action,
13047                       struct rte_flow_error *err)
13048 {
13049         uint32_t idx = 0;
13050         uint32_t ret = 0;
13051
13052         switch (action->type) {
13053         case RTE_FLOW_ACTION_TYPE_RSS:
13054                 ret = __flow_dv_action_rss_create(dev, conf, action->conf, err);
13055                 idx = (MLX5_SHARED_ACTION_TYPE_RSS <<
13056                        MLX5_SHARED_ACTION_TYPE_OFFSET) | ret;
13057                 break;
13058         case RTE_FLOW_ACTION_TYPE_AGE:
13059                 ret = flow_dv_translate_create_aso_age(dev, action->conf, err);
13060                 idx = (MLX5_SHARED_ACTION_TYPE_AGE <<
13061                        MLX5_SHARED_ACTION_TYPE_OFFSET) | ret;
13062                 if (ret) {
13063                         struct mlx5_aso_age_action *aso_age =
13064                                               flow_aso_age_get_by_idx(dev, ret);
13065
13066                         if (!aso_age->age_params.context)
13067                                 aso_age->age_params.context =
13068                                                          (void *)(uintptr_t)idx;
13069                 }
13070                 break;
13071         default:
13072                 rte_flow_error_set(err, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION,
13073                                    NULL, "action type not supported");
13074                 break;
13075         }
13076         return ret ? (struct rte_flow_shared_action *)(uintptr_t)idx : NULL;
13077 }
13078
13079 /**
13080  * Destroy the shared action.
13081  * Release action related resources on the NIC and the memory.
13082  * Lock free, (mutex should be acquired by caller).
13083  * Dispatcher for action type specific call.
13084  *
13085  * @param[in] dev
13086  *   Pointer to the Ethernet device structure.
13087  * @param[in] action
13088  *   The shared action object to be removed.
13089  * @param[out] error
13090  *   Perform verbose error reporting if not NULL. Initialized in case of
13091  *   error only.
13092  *
13093  * @return
13094  *   0 on success, otherwise negative errno value.
13095  */
13096 static int
13097 flow_dv_action_destroy(struct rte_eth_dev *dev,
13098                        struct rte_flow_shared_action *action,
13099                        struct rte_flow_error *error)
13100 {
13101         uint32_t act_idx = (uint32_t)(uintptr_t)action;
13102         uint32_t type = act_idx >> MLX5_SHARED_ACTION_TYPE_OFFSET;
13103         uint32_t idx = act_idx & ((1u << MLX5_SHARED_ACTION_TYPE_OFFSET) - 1);
13104         int ret;
13105
13106         switch (type) {
13107         case MLX5_SHARED_ACTION_TYPE_RSS:
13108                 return __flow_dv_action_rss_release(dev, idx, error);
13109         case MLX5_SHARED_ACTION_TYPE_AGE:
13110                 ret = flow_dv_aso_age_release(dev, idx);
13111                 if (ret)
13112                         /*
13113                          * In this case, the last flow has a reference will
13114                          * actually release the age action.
13115                          */
13116                         DRV_LOG(DEBUG, "Shared age action %" PRIu32 " was"
13117                                 " released with references %d.", idx, ret);
13118                 return 0;
13119         default:
13120                 return rte_flow_error_set(error, ENOTSUP,
13121                                           RTE_FLOW_ERROR_TYPE_ACTION,
13122                                           NULL,
13123                                           "action type not supported");
13124         }
13125 }
13126
13127 /**
13128  * Updates in place shared RSS action configuration.
13129  *
13130  * @param[in] dev
13131  *   Pointer to the Ethernet device structure.
13132  * @param[in] idx
13133  *   The shared RSS action object ID to be updated.
13134  * @param[in] action_conf
13135  *   RSS action specification used to modify *shared_rss*.
13136  * @param[out] error
13137  *   Perform verbose error reporting if not NULL. Initialized in case of
13138  *   error only.
13139  *
13140  * @return
13141  *   0 on success, otherwise negative errno value.
13142  * @note: currently only support update of RSS queues.
13143  */
13144 static int
13145 __flow_dv_action_rss_update(struct rte_eth_dev *dev, uint32_t idx,
13146                             const struct rte_flow_action_rss *action_conf,
13147                             struct rte_flow_error *error)
13148 {
13149         struct mlx5_priv *priv = dev->data->dev_private;
13150         struct mlx5_shared_action_rss *shared_rss =
13151             mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
13152         int ret = 0;
13153         void *queue = NULL;
13154         uint16_t *queue_old = NULL;
13155         uint32_t queue_size = action_conf->queue_num * sizeof(uint16_t);
13156
13157         if (!shared_rss)
13158                 return rte_flow_error_set(error, EINVAL,
13159                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
13160                                           "invalid shared action to update");
13161         if (priv->obj_ops.ind_table_modify == NULL)
13162                 return rte_flow_error_set(error, ENOTSUP,
13163                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
13164                                           "cannot modify indirection table");
13165         queue = mlx5_malloc(MLX5_MEM_ZERO,
13166                             RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
13167                             0, SOCKET_ID_ANY);
13168         if (!queue)
13169                 return rte_flow_error_set(error, ENOMEM,
13170                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13171                                           NULL,
13172                                           "cannot allocate resource memory");
13173         memcpy(queue, action_conf->queue, queue_size);
13174         MLX5_ASSERT(shared_rss->ind_tbl);
13175         rte_spinlock_lock(&shared_rss->action_rss_sl);
13176         queue_old = shared_rss->ind_tbl->queues;
13177         ret = mlx5_ind_table_obj_modify(dev, shared_rss->ind_tbl,
13178                                         queue, action_conf->queue_num, true);
13179         if (ret) {
13180                 mlx5_free(queue);
13181                 ret = rte_flow_error_set(error, rte_errno,
13182                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
13183                                           "cannot update indirection table");
13184         } else {
13185                 mlx5_free(queue_old);
13186                 shared_rss->origin.queue = queue;
13187                 shared_rss->origin.queue_num = action_conf->queue_num;
13188         }
13189         rte_spinlock_unlock(&shared_rss->action_rss_sl);
13190         return ret;
13191 }
13192
13193 /**
13194  * Updates in place shared action configuration, lock free,
13195  * (mutex should be acquired by caller).
13196  *
13197  * @param[in] dev
13198  *   Pointer to the Ethernet device structure.
13199  * @param[in] action
13200  *   The shared action object to be updated.
13201  * @param[in] action_conf
13202  *   Action specification used to modify *action*.
13203  *   *action_conf* should be of type correlating with type of the *action*,
13204  *   otherwise considered as invalid.
13205  * @param[out] error
13206  *   Perform verbose error reporting if not NULL. Initialized in case of
13207  *   error only.
13208  *
13209  * @return
13210  *   0 on success, otherwise negative errno value.
13211  */
13212 static int
13213 flow_dv_action_update(struct rte_eth_dev *dev,
13214                         struct rte_flow_shared_action *action,
13215                         const void *action_conf,
13216                         struct rte_flow_error *err)
13217 {
13218         uint32_t act_idx = (uint32_t)(uintptr_t)action;
13219         uint32_t type = act_idx >> MLX5_SHARED_ACTION_TYPE_OFFSET;
13220         uint32_t idx = act_idx & ((1u << MLX5_SHARED_ACTION_TYPE_OFFSET) - 1);
13221
13222         switch (type) {
13223         case MLX5_SHARED_ACTION_TYPE_RSS:
13224                 return __flow_dv_action_rss_update(dev, idx, action_conf, err);
13225         default:
13226                 return rte_flow_error_set(err, ENOTSUP,
13227                                           RTE_FLOW_ERROR_TYPE_ACTION,
13228                                           NULL,
13229                                           "action type update not supported");
13230         }
13231 }
13232
13233 static int
13234 flow_dv_action_query(struct rte_eth_dev *dev,
13235                      const struct rte_flow_shared_action *action, void *data,
13236                      struct rte_flow_error *error)
13237 {
13238         struct mlx5_age_param *age_param;
13239         struct rte_flow_query_age *resp;
13240         uint32_t act_idx = (uint32_t)(uintptr_t)action;
13241         uint32_t type = act_idx >> MLX5_SHARED_ACTION_TYPE_OFFSET;
13242         uint32_t idx = act_idx & ((1u << MLX5_SHARED_ACTION_TYPE_OFFSET) - 1);
13243
13244         switch (type) {
13245         case MLX5_SHARED_ACTION_TYPE_AGE:
13246                 age_param = &flow_aso_age_get_by_idx(dev, idx)->age_params;
13247                 resp = data;
13248                 resp->aged = __atomic_load_n(&age_param->state,
13249                                               __ATOMIC_RELAXED) == AGE_TMOUT ?
13250                                                                           1 : 0;
13251                 resp->sec_since_last_hit_valid = !resp->aged;
13252                 if (resp->sec_since_last_hit_valid)
13253                         resp->sec_since_last_hit = __atomic_load_n
13254                              (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
13255                 return 0;
13256         default:
13257                 return rte_flow_error_set(error, ENOTSUP,
13258                                           RTE_FLOW_ERROR_TYPE_ACTION,
13259                                           NULL,
13260                                           "action type query not supported");
13261         }
13262 }
13263
13264 /**
13265  * Query a dv flow  rule for its statistics via devx.
13266  *
13267  * @param[in] dev
13268  *   Pointer to Ethernet device.
13269  * @param[in] flow
13270  *   Pointer to the sub flow.
13271  * @param[out] data
13272  *   data retrieved by the query.
13273  * @param[out] error
13274  *   Perform verbose error reporting if not NULL.
13275  *
13276  * @return
13277  *   0 on success, a negative errno value otherwise and rte_errno is set.
13278  */
13279 static int
13280 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
13281                     void *data, struct rte_flow_error *error)
13282 {
13283         struct mlx5_priv *priv = dev->data->dev_private;
13284         struct rte_flow_query_count *qc = data;
13285
13286         if (!priv->config.devx)
13287                 return rte_flow_error_set(error, ENOTSUP,
13288                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13289                                           NULL,
13290                                           "counters are not supported");
13291         if (flow->counter) {
13292                 uint64_t pkts, bytes;
13293                 struct mlx5_flow_counter *cnt;
13294
13295                 cnt = flow_dv_counter_get_by_idx(dev, flow->counter,
13296                                                  NULL);
13297                 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
13298                                                &bytes);
13299
13300                 if (err)
13301                         return rte_flow_error_set(error, -err,
13302                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13303                                         NULL, "cannot read counters");
13304                 qc->hits_set = 1;
13305                 qc->bytes_set = 1;
13306                 qc->hits = pkts - cnt->hits;
13307                 qc->bytes = bytes - cnt->bytes;
13308                 if (qc->reset) {
13309                         cnt->hits = pkts;
13310                         cnt->bytes = bytes;
13311                 }
13312                 return 0;
13313         }
13314         return rte_flow_error_set(error, EINVAL,
13315                                   RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13316                                   NULL,
13317                                   "counters are not available");
13318 }
13319
13320 /**
13321  * Query a flow rule AGE action for aging information.
13322  *
13323  * @param[in] dev
13324  *   Pointer to Ethernet device.
13325  * @param[in] flow
13326  *   Pointer to the sub flow.
13327  * @param[out] data
13328  *   data retrieved by the query.
13329  * @param[out] error
13330  *   Perform verbose error reporting if not NULL.
13331  *
13332  * @return
13333  *   0 on success, a negative errno value otherwise and rte_errno is set.
13334  */
13335 static int
13336 flow_dv_query_age(struct rte_eth_dev *dev, struct rte_flow *flow,
13337                   void *data, struct rte_flow_error *error)
13338 {
13339         struct rte_flow_query_age *resp = data;
13340         struct mlx5_age_param *age_param;
13341
13342         if (flow->age) {
13343                 struct mlx5_aso_age_action *act =
13344                                      flow_aso_age_get_by_idx(dev, flow->age);
13345
13346                 age_param = &act->age_params;
13347         } else if (flow->counter) {
13348                 age_param = flow_dv_counter_idx_get_age(dev, flow->counter);
13349
13350                 if (!age_param || !age_param->timeout)
13351                         return rte_flow_error_set
13352                                         (error, EINVAL,
13353                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13354                                          NULL, "cannot read age data");
13355         } else {
13356                 return rte_flow_error_set(error, EINVAL,
13357                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13358                                           NULL, "age data not available");
13359         }
13360         resp->aged = __atomic_load_n(&age_param->state, __ATOMIC_RELAXED) ==
13361                                      AGE_TMOUT ? 1 : 0;
13362         resp->sec_since_last_hit_valid = !resp->aged;
13363         if (resp->sec_since_last_hit_valid)
13364                 resp->sec_since_last_hit = __atomic_load_n
13365                              (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
13366         return 0;
13367 }
13368
13369 /**
13370  * Query a flow.
13371  *
13372  * @see rte_flow_query()
13373  * @see rte_flow_ops
13374  */
13375 static int
13376 flow_dv_query(struct rte_eth_dev *dev,
13377               struct rte_flow *flow __rte_unused,
13378               const struct rte_flow_action *actions __rte_unused,
13379               void *data __rte_unused,
13380               struct rte_flow_error *error __rte_unused)
13381 {
13382         int ret = -EINVAL;
13383
13384         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
13385                 switch (actions->type) {
13386                 case RTE_FLOW_ACTION_TYPE_VOID:
13387                         break;
13388                 case RTE_FLOW_ACTION_TYPE_COUNT:
13389                         ret = flow_dv_query_count(dev, flow, data, error);
13390                         break;
13391                 case RTE_FLOW_ACTION_TYPE_AGE:
13392                         ret = flow_dv_query_age(dev, flow, data, error);
13393                         break;
13394                 default:
13395                         return rte_flow_error_set(error, ENOTSUP,
13396                                                   RTE_FLOW_ERROR_TYPE_ACTION,
13397                                                   actions,
13398                                                   "action not supported");
13399                 }
13400         }
13401         return ret;
13402 }
13403
13404 /**
13405  * Destroy the meter table set.
13406  * Lock free, (mutex should be acquired by caller).
13407  *
13408  * @param[in] dev
13409  *   Pointer to Ethernet device.
13410  * @param[in] tbl
13411  *   Pointer to the meter table set.
13412  *
13413  * @return
13414  *   Always 0.
13415  */
13416 static int
13417 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
13418                         struct mlx5_meter_domains_infos *tbl)
13419 {
13420         struct mlx5_priv *priv = dev->data->dev_private;
13421         struct mlx5_meter_domains_infos *mtd =
13422                                 (struct mlx5_meter_domains_infos *)tbl;
13423
13424         if (!mtd || !priv->config.dv_flow_en)
13425                 return 0;
13426         if (mtd->ingress.policer_rules[RTE_MTR_DROPPED])
13427                 claim_zero(mlx5_flow_os_destroy_flow
13428                            (mtd->ingress.policer_rules[RTE_MTR_DROPPED]));
13429         if (mtd->egress.policer_rules[RTE_MTR_DROPPED])
13430                 claim_zero(mlx5_flow_os_destroy_flow
13431                            (mtd->egress.policer_rules[RTE_MTR_DROPPED]));
13432         if (mtd->transfer.policer_rules[RTE_MTR_DROPPED])
13433                 claim_zero(mlx5_flow_os_destroy_flow
13434                            (mtd->transfer.policer_rules[RTE_MTR_DROPPED]));
13435         if (mtd->egress.color_matcher)
13436                 claim_zero(mlx5_flow_os_destroy_flow_matcher
13437                            (mtd->egress.color_matcher));
13438         if (mtd->egress.any_matcher)
13439                 claim_zero(mlx5_flow_os_destroy_flow_matcher
13440                            (mtd->egress.any_matcher));
13441         if (mtd->egress.tbl)
13442                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->egress.tbl);
13443         if (mtd->egress.sfx_tbl)
13444                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->egress.sfx_tbl);
13445         if (mtd->ingress.color_matcher)
13446                 claim_zero(mlx5_flow_os_destroy_flow_matcher
13447                            (mtd->ingress.color_matcher));
13448         if (mtd->ingress.any_matcher)
13449                 claim_zero(mlx5_flow_os_destroy_flow_matcher
13450                            (mtd->ingress.any_matcher));
13451         if (mtd->ingress.tbl)
13452                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->ingress.tbl);
13453         if (mtd->ingress.sfx_tbl)
13454                 flow_dv_tbl_resource_release(MLX5_SH(dev),
13455                                              mtd->ingress.sfx_tbl);
13456         if (mtd->transfer.color_matcher)
13457                 claim_zero(mlx5_flow_os_destroy_flow_matcher
13458                            (mtd->transfer.color_matcher));
13459         if (mtd->transfer.any_matcher)
13460                 claim_zero(mlx5_flow_os_destroy_flow_matcher
13461                            (mtd->transfer.any_matcher));
13462         if (mtd->transfer.tbl)
13463                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->transfer.tbl);
13464         if (mtd->transfer.sfx_tbl)
13465                 flow_dv_tbl_resource_release(MLX5_SH(dev),
13466                                              mtd->transfer.sfx_tbl);
13467         if (mtd->drop_actn)
13468                 claim_zero(mlx5_flow_os_destroy_flow_action(mtd->drop_actn));
13469         mlx5_free(mtd);
13470         return 0;
13471 }
13472
13473 /* Number of meter flow actions, count and jump or count and drop. */
13474 #define METER_ACTIONS 2
13475
13476 /**
13477  * Create specify domain meter table and suffix table.
13478  *
13479  * @param[in] dev
13480  *   Pointer to Ethernet device.
13481  * @param[in,out] mtb
13482  *   Pointer to DV meter table set.
13483  * @param[in] egress
13484  *   Table attribute.
13485  * @param[in] transfer
13486  *   Table attribute.
13487  * @param[in] color_reg_c_idx
13488  *   Reg C index for color match.
13489  *
13490  * @return
13491  *   0 on success, -1 otherwise and rte_errno is set.
13492  */
13493 static int
13494 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
13495                            struct mlx5_meter_domains_infos *mtb,
13496                            uint8_t egress, uint8_t transfer,
13497                            uint32_t color_reg_c_idx)
13498 {
13499         struct mlx5_priv *priv = dev->data->dev_private;
13500         struct mlx5_dev_ctx_shared *sh = priv->sh;
13501         struct mlx5_flow_dv_match_params mask = {
13502                 .size = sizeof(mask.buf),
13503         };
13504         struct mlx5_flow_dv_match_params value = {
13505                 .size = sizeof(value.buf),
13506         };
13507         struct mlx5dv_flow_matcher_attr dv_attr = {
13508                 .type = IBV_FLOW_ATTR_NORMAL,
13509                 .priority = 0,
13510                 .match_criteria_enable = 0,
13511                 .match_mask = (void *)&mask,
13512         };
13513         void *actions[METER_ACTIONS];
13514         struct mlx5_meter_domain_info *dtb;
13515         struct rte_flow_error error;
13516         int i = 0;
13517         int ret;
13518
13519         if (transfer)
13520                 dtb = &mtb->transfer;
13521         else if (egress)
13522                 dtb = &mtb->egress;
13523         else
13524                 dtb = &mtb->ingress;
13525         /* Create the meter table with METER level. */
13526         dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
13527                                             egress, transfer, false, NULL, 0,
13528                                             0, &error);
13529         if (!dtb->tbl) {
13530                 DRV_LOG(ERR, "Failed to create meter policer table.");
13531                 return -1;
13532         }
13533         /* Create the meter suffix table with SUFFIX level. */
13534         dtb->sfx_tbl = flow_dv_tbl_resource_get(dev,
13535                                             MLX5_FLOW_TABLE_LEVEL_SUFFIX,
13536                                             egress, transfer, false, NULL, 0,
13537                                             0, &error);
13538         if (!dtb->sfx_tbl) {
13539                 DRV_LOG(ERR, "Failed to create meter suffix table.");
13540                 return -1;
13541         }
13542         /* Create matchers, Any and Color. */
13543         dv_attr.priority = 3;
13544         dv_attr.match_criteria_enable = 0;
13545         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, dtb->tbl->obj,
13546                                                &dtb->any_matcher);
13547         if (ret) {
13548                 DRV_LOG(ERR, "Failed to create meter"
13549                              " policer default matcher.");
13550                 goto error_exit;
13551         }
13552         dv_attr.priority = 0;
13553         dv_attr.match_criteria_enable =
13554                                 1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
13555         flow_dv_match_meta_reg(mask.buf, value.buf, color_reg_c_idx,
13556                                rte_col_2_mlx5_col(RTE_COLORS), UINT8_MAX);
13557         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, dtb->tbl->obj,
13558                                                &dtb->color_matcher);
13559         if (ret) {
13560                 DRV_LOG(ERR, "Failed to create meter policer color matcher.");
13561                 goto error_exit;
13562         }
13563         if (mtb->count_actns[RTE_MTR_DROPPED])
13564                 actions[i++] = mtb->count_actns[RTE_MTR_DROPPED];
13565         actions[i++] = mtb->drop_actn;
13566         /* Default rule: lowest priority, match any, actions: drop. */
13567         ret = mlx5_flow_os_create_flow(dtb->any_matcher, (void *)&value, i,
13568                                        actions,
13569                                        &dtb->policer_rules[RTE_MTR_DROPPED]);
13570         if (ret) {
13571                 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
13572                 goto error_exit;
13573         }
13574         return 0;
13575 error_exit:
13576         return -1;
13577 }
13578
13579 /**
13580  * Create the needed meter and suffix tables.
13581  * Lock free, (mutex should be acquired by caller).
13582  *
13583  * @param[in] dev
13584  *   Pointer to Ethernet device.
13585  * @param[in] fm
13586  *   Pointer to the flow meter.
13587  *
13588  * @return
13589  *   Pointer to table set on success, NULL otherwise and rte_errno is set.
13590  */
13591 static struct mlx5_meter_domains_infos *
13592 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev,
13593                        const struct mlx5_flow_meter *fm)
13594 {
13595         struct mlx5_priv *priv = dev->data->dev_private;
13596         struct mlx5_meter_domains_infos *mtb;
13597         int ret;
13598         int i;
13599
13600         if (!priv->mtr_en) {
13601                 rte_errno = ENOTSUP;
13602                 return NULL;
13603         }
13604         mtb = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mtb), 0, SOCKET_ID_ANY);
13605         if (!mtb) {
13606                 DRV_LOG(ERR, "Failed to allocate memory for meter.");
13607                 return NULL;
13608         }
13609         /* Create meter count actions */
13610         for (i = 0; i <= RTE_MTR_DROPPED; i++) {
13611                 struct mlx5_flow_counter *cnt;
13612                 if (!fm->policer_stats.cnt[i])
13613                         continue;
13614                 cnt = flow_dv_counter_get_by_idx(dev,
13615                       fm->policer_stats.cnt[i], NULL);
13616                 mtb->count_actns[i] = cnt->action;
13617         }
13618         /* Create drop action. */
13619         ret = mlx5_flow_os_create_flow_action_drop(&mtb->drop_actn);
13620         if (ret) {
13621                 DRV_LOG(ERR, "Failed to create drop action.");
13622                 goto error_exit;
13623         }
13624         /* Egress meter table. */
13625         ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0, priv->mtr_color_reg);
13626         if (ret) {
13627                 DRV_LOG(ERR, "Failed to prepare egress meter table.");
13628                 goto error_exit;
13629         }
13630         /* Ingress meter table. */
13631         ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0, priv->mtr_color_reg);
13632         if (ret) {
13633                 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
13634                 goto error_exit;
13635         }
13636         /* FDB meter table. */
13637         if (priv->config.dv_esw_en) {
13638                 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1,
13639                                                  priv->mtr_color_reg);
13640                 if (ret) {
13641                         DRV_LOG(ERR, "Failed to prepare fdb meter table.");
13642                         goto error_exit;
13643                 }
13644         }
13645         return mtb;
13646 error_exit:
13647         flow_dv_destroy_mtr_tbl(dev, mtb);
13648         return NULL;
13649 }
13650
13651 /**
13652  * Destroy domain policer rule.
13653  *
13654  * @param[in] dt
13655  *   Pointer to domain table.
13656  */
13657 static void
13658 flow_dv_destroy_domain_policer_rule(struct mlx5_meter_domain_info *dt)
13659 {
13660         int i;
13661
13662         for (i = 0; i < RTE_MTR_DROPPED; i++) {
13663                 if (dt->policer_rules[i]) {
13664                         claim_zero(mlx5_flow_os_destroy_flow
13665                                    (dt->policer_rules[i]));
13666                         dt->policer_rules[i] = NULL;
13667                 }
13668         }
13669         if (dt->jump_actn) {
13670                 claim_zero(mlx5_flow_os_destroy_flow_action(dt->jump_actn));
13671                 dt->jump_actn = NULL;
13672         }
13673 }
13674
13675 /**
13676  * Destroy policer rules.
13677  *
13678  * @param[in] dev
13679  *   Pointer to Ethernet device.
13680  * @param[in] fm
13681  *   Pointer to flow meter structure.
13682  * @param[in] attr
13683  *   Pointer to flow attributes.
13684  *
13685  * @return
13686  *   Always 0.
13687  */
13688 static int
13689 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev __rte_unused,
13690                               const struct mlx5_flow_meter *fm,
13691                               const struct rte_flow_attr *attr)
13692 {
13693         struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
13694
13695         if (!mtb)
13696                 return 0;
13697         if (attr->egress)
13698                 flow_dv_destroy_domain_policer_rule(&mtb->egress);
13699         if (attr->ingress)
13700                 flow_dv_destroy_domain_policer_rule(&mtb->ingress);
13701         if (attr->transfer)
13702                 flow_dv_destroy_domain_policer_rule(&mtb->transfer);
13703         return 0;
13704 }
13705
13706 /**
13707  * Create specify domain meter policer rule.
13708  *
13709  * @param[in] fm
13710  *   Pointer to flow meter structure.
13711  * @param[in] mtb
13712  *   Pointer to DV meter table set.
13713  * @param[in] mtr_reg_c
13714  *   Color match REG_C.
13715  *
13716  * @return
13717  *   0 on success, -1 otherwise.
13718  */
13719 static int
13720 flow_dv_create_policer_forward_rule(struct mlx5_flow_meter *fm,
13721                                     struct mlx5_meter_domain_info *dtb,
13722                                     uint8_t mtr_reg_c)
13723 {
13724         struct mlx5_flow_dv_match_params matcher = {
13725                 .size = sizeof(matcher.buf),
13726         };
13727         struct mlx5_flow_dv_match_params value = {
13728                 .size = sizeof(value.buf),
13729         };
13730         struct mlx5_meter_domains_infos *mtb = fm->mfts;
13731         void *actions[METER_ACTIONS];
13732         int i;
13733         int ret = 0;
13734
13735         /* Create jump action. */
13736         if (!dtb->jump_actn)
13737                 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
13738                                 (dtb->sfx_tbl->obj, &dtb->jump_actn);
13739         if (ret) {
13740                 DRV_LOG(ERR, "Failed to create policer jump action.");
13741                 goto error;
13742         }
13743         for (i = 0; i < RTE_MTR_DROPPED; i++) {
13744                 int j = 0;
13745
13746                 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_reg_c,
13747                                        rte_col_2_mlx5_col(i), UINT8_MAX);
13748                 if (mtb->count_actns[i])
13749                         actions[j++] = mtb->count_actns[i];
13750                 if (fm->action[i] == MTR_POLICER_ACTION_DROP)
13751                         actions[j++] = mtb->drop_actn;
13752                 else
13753                         actions[j++] = dtb->jump_actn;
13754                 ret = mlx5_flow_os_create_flow(dtb->color_matcher,
13755                                                (void *)&value, j, actions,
13756                                                &dtb->policer_rules[i]);
13757                 if (ret) {
13758                         DRV_LOG(ERR, "Failed to create policer rule.");
13759                         goto error;
13760                 }
13761         }
13762         return 0;
13763 error:
13764         rte_errno = errno;
13765         return -1;
13766 }
13767
13768 /**
13769  * Create policer rules.
13770  *
13771  * @param[in] dev
13772  *   Pointer to Ethernet device.
13773  * @param[in] fm
13774  *   Pointer to flow meter structure.
13775  * @param[in] attr
13776  *   Pointer to flow attributes.
13777  *
13778  * @return
13779  *   0 on success, -1 otherwise.
13780  */
13781 static int
13782 flow_dv_create_policer_rules(struct rte_eth_dev *dev,
13783                              struct mlx5_flow_meter *fm,
13784                              const struct rte_flow_attr *attr)
13785 {
13786         struct mlx5_priv *priv = dev->data->dev_private;
13787         struct mlx5_meter_domains_infos *mtb = fm->mfts;
13788         int ret;
13789
13790         if (attr->egress) {
13791                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->egress,
13792                                                 priv->mtr_color_reg);
13793                 if (ret) {
13794                         DRV_LOG(ERR, "Failed to create egress policer.");
13795                         goto error;
13796                 }
13797         }
13798         if (attr->ingress) {
13799                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->ingress,
13800                                                 priv->mtr_color_reg);
13801                 if (ret) {
13802                         DRV_LOG(ERR, "Failed to create ingress policer.");
13803                         goto error;
13804                 }
13805         }
13806         if (attr->transfer) {
13807                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->transfer,
13808                                                 priv->mtr_color_reg);
13809                 if (ret) {
13810                         DRV_LOG(ERR, "Failed to create transfer policer.");
13811                         goto error;
13812                 }
13813         }
13814         return 0;
13815 error:
13816         flow_dv_destroy_policer_rules(dev, fm, attr);
13817         return -1;
13818 }
13819
13820 /**
13821  * Validate the batch counter support in root table.
13822  *
13823  * Create a simple flow with invalid counter and drop action on root table to
13824  * validate if batch counter with offset on root table is supported or not.
13825  *
13826  * @param[in] dev
13827  *   Pointer to rte_eth_dev structure.
13828  *
13829  * @return
13830  *   0 on success, a negative errno value otherwise and rte_errno is set.
13831  */
13832 int
13833 mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev)
13834 {
13835         struct mlx5_priv *priv = dev->data->dev_private;
13836         struct mlx5_dev_ctx_shared *sh = priv->sh;
13837         struct mlx5_flow_dv_match_params mask = {
13838                 .size = sizeof(mask.buf),
13839         };
13840         struct mlx5_flow_dv_match_params value = {
13841                 .size = sizeof(value.buf),
13842         };
13843         struct mlx5dv_flow_matcher_attr dv_attr = {
13844                 .type = IBV_FLOW_ATTR_NORMAL,
13845                 .priority = 0,
13846                 .match_criteria_enable = 0,
13847                 .match_mask = (void *)&mask,
13848         };
13849         void *actions[2] = { 0 };
13850         struct mlx5_flow_tbl_resource *tbl = NULL;
13851         struct mlx5_devx_obj *dcs = NULL;
13852         void *matcher = NULL;
13853         void *flow = NULL;
13854         int ret = -1;
13855
13856         tbl = flow_dv_tbl_resource_get(dev, 0, 0, 0, false, NULL, 0, 0, NULL);
13857         if (!tbl)
13858                 goto err;
13859         dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
13860         if (!dcs)
13861                 goto err;
13862         ret = mlx5_flow_os_create_flow_action_count(dcs->obj, UINT16_MAX,
13863                                                     &actions[0]);
13864         if (ret)
13865                 goto err;
13866         actions[1] = sh->dr_drop_action ? sh->dr_drop_action :
13867                                           priv->drop_queue.hrxq->action;
13868         dv_attr.match_criteria_enable = flow_dv_matcher_enable(mask.buf);
13869         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj,
13870                                                &matcher);
13871         if (ret)
13872                 goto err;
13873         ret = mlx5_flow_os_create_flow(matcher, (void *)&value, 2,
13874                                        actions, &flow);
13875 err:
13876         /*
13877          * If batch counter with offset is not supported, the driver will not
13878          * validate the invalid offset value, flow create should success.
13879          * In this case, it means batch counter is not supported in root table.
13880          *
13881          * Otherwise, if flow create is failed, counter offset is supported.
13882          */
13883         if (flow) {
13884                 DRV_LOG(INFO, "Batch counter is not supported in root "
13885                               "table. Switch to fallback mode.");
13886                 rte_errno = ENOTSUP;
13887                 ret = -rte_errno;
13888                 claim_zero(mlx5_flow_os_destroy_flow(flow));
13889         } else {
13890                 /* Check matcher to make sure validate fail at flow create. */
13891                 if (!matcher || (matcher && errno != EINVAL))
13892                         DRV_LOG(ERR, "Unexpected error in counter offset "
13893                                      "support detection");
13894                 ret = 0;
13895         }
13896         if (actions[0])
13897                 claim_zero(mlx5_flow_os_destroy_flow_action(actions[0]));
13898         if (matcher)
13899                 claim_zero(mlx5_flow_os_destroy_flow_matcher(matcher));
13900         if (tbl)
13901                 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
13902         if (dcs)
13903                 claim_zero(mlx5_devx_cmd_destroy(dcs));
13904         return ret;
13905 }
13906
13907 /**
13908  * Query a devx counter.
13909  *
13910  * @param[in] dev
13911  *   Pointer to the Ethernet device structure.
13912  * @param[in] cnt
13913  *   Index to the flow counter.
13914  * @param[in] clear
13915  *   Set to clear the counter statistics.
13916  * @param[out] pkts
13917  *   The statistics value of packets.
13918  * @param[out] bytes
13919  *   The statistics value of bytes.
13920  *
13921  * @return
13922  *   0 on success, otherwise return -1.
13923  */
13924 static int
13925 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
13926                       uint64_t *pkts, uint64_t *bytes)
13927 {
13928         struct mlx5_priv *priv = dev->data->dev_private;
13929         struct mlx5_flow_counter *cnt;
13930         uint64_t inn_pkts, inn_bytes;
13931         int ret;
13932
13933         if (!priv->config.devx)
13934                 return -1;
13935
13936         ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
13937         if (ret)
13938                 return -1;
13939         cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
13940         *pkts = inn_pkts - cnt->hits;
13941         *bytes = inn_bytes - cnt->bytes;
13942         if (clear) {
13943                 cnt->hits = inn_pkts;
13944                 cnt->bytes = inn_bytes;
13945         }
13946         return 0;
13947 }
13948
13949 /**
13950  * Get aged-out flows.
13951  *
13952  * @param[in] dev
13953  *   Pointer to the Ethernet device structure.
13954  * @param[in] context
13955  *   The address of an array of pointers to the aged-out flows contexts.
13956  * @param[in] nb_contexts
13957  *   The length of context array pointers.
13958  * @param[out] error
13959  *   Perform verbose error reporting if not NULL. Initialized in case of
13960  *   error only.
13961  *
13962  * @return
13963  *   how many contexts get in success, otherwise negative errno value.
13964  *   if nb_contexts is 0, return the amount of all aged contexts.
13965  *   if nb_contexts is not 0 , return the amount of aged flows reported
13966  *   in the context array.
13967  * @note: only stub for now
13968  */
13969 static int
13970 flow_get_aged_flows(struct rte_eth_dev *dev,
13971                     void **context,
13972                     uint32_t nb_contexts,
13973                     struct rte_flow_error *error)
13974 {
13975         struct mlx5_priv *priv = dev->data->dev_private;
13976         struct mlx5_age_info *age_info;
13977         struct mlx5_age_param *age_param;
13978         struct mlx5_flow_counter *counter;
13979         struct mlx5_aso_age_action *act;
13980         int nb_flows = 0;
13981
13982         if (nb_contexts && !context)
13983                 return rte_flow_error_set(error, EINVAL,
13984                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13985                                           NULL, "empty context");
13986         age_info = GET_PORT_AGE_INFO(priv);
13987         rte_spinlock_lock(&age_info->aged_sl);
13988         LIST_FOREACH(act, &age_info->aged_aso, next) {
13989                 nb_flows++;
13990                 if (nb_contexts) {
13991                         context[nb_flows - 1] =
13992                                                 act->age_params.context;
13993                         if (!(--nb_contexts))
13994                                 break;
13995                 }
13996         }
13997         TAILQ_FOREACH(counter, &age_info->aged_counters, next) {
13998                 nb_flows++;
13999                 if (nb_contexts) {
14000                         age_param = MLX5_CNT_TO_AGE(counter);
14001                         context[nb_flows - 1] = age_param->context;
14002                         if (!(--nb_contexts))
14003                                 break;
14004                 }
14005         }
14006         rte_spinlock_unlock(&age_info->aged_sl);
14007         MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
14008         return nb_flows;
14009 }
14010
14011 /*
14012  * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
14013  */
14014 static uint32_t
14015 flow_dv_counter_allocate(struct rte_eth_dev *dev)
14016 {
14017         return flow_dv_counter_alloc(dev, 0);
14018 }
14019
14020 /**
14021  * Validate shared action.
14022  * Dispatcher for action type specific validation.
14023  *
14024  * @param[in] dev
14025  *   Pointer to the Ethernet device structure.
14026  * @param[in] conf
14027  *   Shared action configuration.
14028  * @param[in] action
14029  *   The shared action object to validate.
14030  * @param[out] error
14031  *   Perform verbose error reporting if not NULL. Initialized in case of
14032  *   error only.
14033  *
14034  * @return
14035  *   0 on success, otherwise negative errno value.
14036  */
14037 static int
14038 flow_dv_action_validate(struct rte_eth_dev *dev,
14039                         const struct rte_flow_shared_action_conf *conf,
14040                         const struct rte_flow_action *action,
14041                         struct rte_flow_error *err)
14042 {
14043         struct mlx5_priv *priv = dev->data->dev_private;
14044
14045         RTE_SET_USED(conf);
14046         switch (action->type) {
14047         case RTE_FLOW_ACTION_TYPE_RSS:
14048                 /*
14049                  * priv->obj_ops is set according to driver capabilities.
14050                  * When DevX capabilities are
14051                  * sufficient, it is set to devx_obj_ops.
14052                  * Otherwise, it is set to ibv_obj_ops.
14053                  * ibv_obj_ops doesn't support ind_table_modify operation.
14054                  * In this case the shared RSS action can't be used.
14055                  */
14056                 if (priv->obj_ops.ind_table_modify == NULL)
14057                         return rte_flow_error_set
14058                                         (err, ENOTSUP,
14059                                          RTE_FLOW_ERROR_TYPE_ACTION,
14060                                          NULL,
14061                                          "shared RSS action not supported");
14062                 return mlx5_validate_action_rss(dev, action, err);
14063         case RTE_FLOW_ACTION_TYPE_AGE:
14064                 if (!priv->sh->aso_age_mng)
14065                         return rte_flow_error_set(err, ENOTSUP,
14066                                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
14067                                                 NULL,
14068                                              "shared age action not supported");
14069                 return flow_dv_validate_action_age(0, action, dev, err);
14070         default:
14071                 return rte_flow_error_set(err, ENOTSUP,
14072                                           RTE_FLOW_ERROR_TYPE_ACTION,
14073                                           NULL,
14074                                           "action type not supported");
14075         }
14076 }
14077
14078 static int
14079 flow_dv_sync_domain(struct rte_eth_dev *dev, uint32_t domains, uint32_t flags)
14080 {
14081         struct mlx5_priv *priv = dev->data->dev_private;
14082         int ret = 0;
14083
14084         if ((domains & MLX5_DOMAIN_BIT_NIC_RX) && priv->sh->rx_domain != NULL) {
14085                 ret = mlx5_os_flow_dr_sync_domain(priv->sh->rx_domain,
14086                                                 flags);
14087                 if (ret != 0)
14088                         return ret;
14089         }
14090         if ((domains & MLX5_DOMAIN_BIT_NIC_TX) && priv->sh->tx_domain != NULL) {
14091                 ret = mlx5_os_flow_dr_sync_domain(priv->sh->tx_domain, flags);
14092                 if (ret != 0)
14093                         return ret;
14094         }
14095         if ((domains & MLX5_DOMAIN_BIT_FDB) && priv->sh->fdb_domain != NULL) {
14096                 ret = mlx5_os_flow_dr_sync_domain(priv->sh->fdb_domain, flags);
14097                 if (ret != 0)
14098                         return ret;
14099         }
14100         return 0;
14101 }
14102
14103 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
14104         .validate = flow_dv_validate,
14105         .prepare = flow_dv_prepare,
14106         .translate = flow_dv_translate,
14107         .apply = flow_dv_apply,
14108         .remove = flow_dv_remove,
14109         .destroy = flow_dv_destroy,
14110         .query = flow_dv_query,
14111         .create_mtr_tbls = flow_dv_create_mtr_tbl,
14112         .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
14113         .create_policer_rules = flow_dv_create_policer_rules,
14114         .destroy_policer_rules = flow_dv_destroy_policer_rules,
14115         .counter_alloc = flow_dv_counter_allocate,
14116         .counter_free = flow_dv_counter_free,
14117         .counter_query = flow_dv_counter_query,
14118         .get_aged_flows = flow_get_aged_flows,
14119         .action_validate = flow_dv_action_validate,
14120         .action_create = flow_dv_action_create,
14121         .action_destroy = flow_dv_action_destroy,
14122         .action_update = flow_dv_action_update,
14123         .action_query = flow_dv_action_query,
14124         .sync_domain = flow_dv_sync_domain,
14125 };
14126
14127 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */
14128