drivers/net/mlx5/mlx5_flow_dv.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2018 Mellanox Technologies, Ltd
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdalign.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10
  11 #include <rte_common.h>
  12 #include <rte_ether.h>
  13 #include <ethdev_driver.h>
  14 #include <rte_flow.h>
  15 #include <rte_flow_driver.h>
  16 #include <rte_malloc.h>
  17 #include <rte_cycles.h>
  18 #include <rte_ip.h>
  19 #include <rte_gre.h>
  20 #include <rte_vxlan.h>
  21 #include <rte_gtp.h>
  22 #include <rte_eal_paging.h>
  23 #include <rte_mpls.h>
  24
  25 #include <mlx5_glue.h>
  26 #include <mlx5_devx_cmds.h>
  27 #include <mlx5_prm.h>
  28 #include <mlx5_malloc.h>
  29
  30 #include "mlx5_defs.h"
  31 #include "mlx5.h"
  32 #include "mlx5_common_os.h"
  33 #include "mlx5_flow.h"
  34 #include "mlx5_flow_os.h"
  35 #include "mlx5_rxtx.h"
  36 #include "rte_pmd_mlx5.h"
  37
  38 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
  39
  40 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
  41 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
  42 #endif
  43
  44 #ifndef HAVE_MLX5DV_DR_ESWITCH
  45 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
  46 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
  47 #endif
  48 #endif
  49
  50 #ifndef HAVE_MLX5DV_DR
  51 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
  52 #endif
  53
  54 /* VLAN header definitions */
  55 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
  56 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
  57 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
  58 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
  59 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
  60
  61 union flow_dv_attr {
  62         struct {
  63                 uint32_t valid:1;
  64                 uint32_t ipv4:1;
  65                 uint32_t ipv6:1;
  66                 uint32_t tcp:1;
  67                 uint32_t udp:1;
  68                 uint32_t reserved:27;
  69         };
  70         uint32_t attr;
  71 };
  72
  73 static int
  74 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
  75                              struct mlx5_flow_tbl_resource *tbl);
  76
  77 static int
  78 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
  79                                      uint32_t encap_decap_idx);
  80
  81 static int
  82 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
  83                                         uint32_t port_id);
  84 static void
  85 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss);
  86
  87 static int
  88 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
  89                                   uint32_t rix_jump);
  90
  91 /**
  92  * Initialize flow attributes structure according to flow items' types.
  93  *
  94  * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
  95  * mode. For tunnel mode, the items to be modified are the outermost ones.
  96  *
  97  * @param[in] item
  98  *   Pointer to item specification.
  99  * @param[out] attr
 100  *   Pointer to flow attributes structure.
 101  * @param[in] dev_flow
 102  *   Pointer to the sub flow.
 103  * @param[in] tunnel_decap
 104  *   Whether action is after tunnel decapsulation.
 105  */
 106 static void
 107 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
 108                   struct mlx5_flow *dev_flow, bool tunnel_decap)
 109 {
 110         uint64_t layers = dev_flow->handle->layers;
 111
 112         /*
 113          * If layers is already initialized, it means this dev_flow is the
 114          * suffix flow, the layers flags is set by the prefix flow. Need to
 115          * use the layer flags from prefix flow as the suffix flow may not
 116          * have the user defined items as the flow is split.
 117          */
 118         if (layers) {
 119                 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
 120                         attr->ipv4 = 1;
 121                 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
 122                         attr->ipv6 = 1;
 123                 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
 124                         attr->tcp = 1;
 125                 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
 126                         attr->udp = 1;
 127                 attr->valid = 1;
 128                 return;
 129         }
 130         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
 131                 uint8_t next_protocol = 0xff;
 132                 switch (item->type) {
 133                 case RTE_FLOW_ITEM_TYPE_GRE:
 134                 case RTE_FLOW_ITEM_TYPE_NVGRE:
 135                 case RTE_FLOW_ITEM_TYPE_VXLAN:
 136                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
 137                 case RTE_FLOW_ITEM_TYPE_GENEVE:
 138                 case RTE_FLOW_ITEM_TYPE_MPLS:
 139                         if (tunnel_decap)
 140                                 attr->attr = 0;
 141                         break;
 142                 case RTE_FLOW_ITEM_TYPE_IPV4:
 143                         if (!attr->ipv6)
 144                                 attr->ipv4 = 1;
 145                         if (item->mask != NULL &&
 146                             ((const struct rte_flow_item_ipv4 *)
 147                             item->mask)->hdr.next_proto_id)
 148                                 next_protocol =
 149                                     ((const struct rte_flow_item_ipv4 *)
 150                                       (item->spec))->hdr.next_proto_id &
 151                                     ((const struct rte_flow_item_ipv4 *)
 152                                       (item->mask))->hdr.next_proto_id;
 153                         if ((next_protocol == IPPROTO_IPIP ||
 154                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 155                                 attr->attr = 0;
 156                         break;
 157                 case RTE_FLOW_ITEM_TYPE_IPV6:
 158                         if (!attr->ipv4)
 159                                 attr->ipv6 = 1;
 160                         if (item->mask != NULL &&
 161                             ((const struct rte_flow_item_ipv6 *)
 162                             item->mask)->hdr.proto)
 163                                 next_protocol =
 164                                     ((const struct rte_flow_item_ipv6 *)
 165                                       (item->spec))->hdr.proto &
 166                                     ((const struct rte_flow_item_ipv6 *)
 167                                       (item->mask))->hdr.proto;
 168                         if ((next_protocol == IPPROTO_IPIP ||
 169                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 170                                 attr->attr = 0;
 171                         break;
 172                 case RTE_FLOW_ITEM_TYPE_UDP:
 173                         if (!attr->tcp)
 174                                 attr->udp = 1;
 175                         break;
 176                 case RTE_FLOW_ITEM_TYPE_TCP:
 177                         if (!attr->udp)
 178                                 attr->tcp = 1;
 179                         break;
 180                 default:
 181                         break;
 182                 }
 183         }
 184         attr->valid = 1;
 185 }
 186
 187 /**
 188  * Convert rte_mtr_color to mlx5 color.
 189  *
 190  * @param[in] rcol
 191  *   rte_mtr_color.
 192  *
 193  * @return
 194  *   mlx5 color.
 195  */
 196 static int
 197 rte_col_2_mlx5_col(enum rte_color rcol)
 198 {
 199         switch (rcol) {
 200         case RTE_COLOR_GREEN:
 201                 return MLX5_FLOW_COLOR_GREEN;
 202         case RTE_COLOR_YELLOW:
 203                 return MLX5_FLOW_COLOR_YELLOW;
 204         case RTE_COLOR_RED:
 205                 return MLX5_FLOW_COLOR_RED;
 206         default:
 207                 break;
 208         }
 209         return MLX5_FLOW_COLOR_UNDEFINED;
 210 }
 211
 212 struct field_modify_info {
 213         uint32_t size; /* Size of field in protocol header, in bytes. */
 214         uint32_t offset; /* Offset of field in protocol header, in bytes. */
 215         enum mlx5_modification_field id;
 216 };
 217
 218 struct field_modify_info modify_eth[] = {
 219         {4,  0, MLX5_MODI_OUT_DMAC_47_16},
 220         {2,  4, MLX5_MODI_OUT_DMAC_15_0},
 221         {4,  6, MLX5_MODI_OUT_SMAC_47_16},
 222         {2, 10, MLX5_MODI_OUT_SMAC_15_0},
 223         {0, 0, 0},
 224 };
 225
 226 struct field_modify_info modify_vlan_out_first_vid[] = {
 227         /* Size in bits !!! */
 228         {12, 0, MLX5_MODI_OUT_FIRST_VID},
 229         {0, 0, 0},
 230 };
 231
 232 struct field_modify_info modify_ipv4[] = {
 233         {1,  1, MLX5_MODI_OUT_IP_DSCP},
 234         {1,  8, MLX5_MODI_OUT_IPV4_TTL},
 235         {4, 12, MLX5_MODI_OUT_SIPV4},
 236         {4, 16, MLX5_MODI_OUT_DIPV4},
 237         {0, 0, 0},
 238 };
 239
 240 struct field_modify_info modify_ipv6[] = {
 241         {1,  0, MLX5_MODI_OUT_IP_DSCP},
 242         {1,  7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
 243         {4,  8, MLX5_MODI_OUT_SIPV6_127_96},
 244         {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
 245         {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
 246         {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
 247         {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
 248         {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
 249         {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
 250         {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
 251         {0, 0, 0},
 252 };
 253
 254 struct field_modify_info modify_udp[] = {
 255         {2, 0, MLX5_MODI_OUT_UDP_SPORT},
 256         {2, 2, MLX5_MODI_OUT_UDP_DPORT},
 257         {0, 0, 0},
 258 };
 259
 260 struct field_modify_info modify_tcp[] = {
 261         {2, 0, MLX5_MODI_OUT_TCP_SPORT},
 262         {2, 2, MLX5_MODI_OUT_TCP_DPORT},
 263         {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
 264         {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
 265         {0, 0, 0},
 266 };
 267
 268 static void
 269 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
 270                           uint8_t next_protocol, uint64_t *item_flags,
 271                           int *tunnel)
 272 {
 273         MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
 274                     item->type == RTE_FLOW_ITEM_TYPE_IPV6);
 275         if (next_protocol == IPPROTO_IPIP) {
 276                 *item_flags |= MLX5_FLOW_LAYER_IPIP;
 277                 *tunnel = 1;
 278         }
 279         if (next_protocol == IPPROTO_IPV6) {
 280                 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
 281                 *tunnel = 1;
 282         }
 283 }
 284
 285 /* Update VLAN's VID/PCP based on input rte_flow_action.
 286  *
 287  * @param[in] action
 288  *   Pointer to struct rte_flow_action.
 289  * @param[out] vlan
 290  *   Pointer to struct rte_vlan_hdr.
 291  */
 292 static void
 293 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
 294                          struct rte_vlan_hdr *vlan)
 295 {
 296         uint16_t vlan_tci;
 297         if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
 298                 vlan_tci =
 299                     ((const struct rte_flow_action_of_set_vlan_pcp *)
 300                                                action->conf)->vlan_pcp;
 301                 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
 302                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
 303                 vlan->vlan_tci |= vlan_tci;
 304         } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
 305                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
 306                 vlan->vlan_tci |= rte_be_to_cpu_16
 307                     (((const struct rte_flow_action_of_set_vlan_vid *)
 308                                              action->conf)->vlan_vid);
 309         }
 310 }
 311
 312 /**
 313  * Fetch 1, 2, 3 or 4 byte field from the byte array
 314  * and return as unsigned integer in host-endian format.
 315  *
 316  * @param[in] data
 317  *   Pointer to data array.
 318  * @param[in] size
 319  *   Size of field to extract.
 320  *
 321  * @return
 322  *   converted field in host endian format.
 323  */
 324 static inline uint32_t
 325 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
 326 {
 327         uint32_t ret;
 328
 329         switch (size) {
 330         case 1:
 331                 ret = *data;
 332                 break;
 333         case 2:
 334                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 335                 break;
 336         case 3:
 337                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 338                 ret = (ret << 8) | *(data + sizeof(uint16_t));
 339                 break;
 340         case 4:
 341                 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
 342                 break;
 343         default:
 344                 MLX5_ASSERT(false);
 345                 ret = 0;
 346                 break;
 347         }
 348         return ret;
 349 }
 350
 351 /**
 352  * Convert modify-header action to DV specification.
 353  *
 354  * Data length of each action is determined by provided field description
 355  * and the item mask. Data bit offset and width of each action is determined
 356  * by provided item mask.
 357  *
 358  * @param[in] item
 359  *   Pointer to item specification.
 360  * @param[in] field
 361  *   Pointer to field modification information.
 362  *     For MLX5_MODIFICATION_TYPE_SET specifies destination field.
 363  *     For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
 364  *     For MLX5_MODIFICATION_TYPE_COPY specifies source field.
 365  * @param[in] dcopy
 366  *   Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
 367  *   Negative offset value sets the same offset as source offset.
 368  *   size field is ignored, value is taken from source field.
 369  * @param[in,out] resource
 370  *   Pointer to the modify-header resource.
 371  * @param[in] type
 372  *   Type of modification.
 373  * @param[out] error
 374  *   Pointer to the error structure.
 375  *
 376  * @return
 377  *   0 on success, a negative errno value otherwise and rte_errno is set.
 378  */
 379 static int
 380 flow_dv_convert_modify_action(struct rte_flow_item *item,
 381                               struct field_modify_info *field,
 382                               struct field_modify_info *dcopy,
 383                               struct mlx5_flow_dv_modify_hdr_resource *resource,
 384                               uint32_t type, struct rte_flow_error *error)
 385 {
 386         uint32_t i = resource->actions_num;
 387         struct mlx5_modification_cmd *actions = resource->actions;
 388
 389         /*
 390          * The item and mask are provided in big-endian format.
 391          * The fields should be presented as in big-endian format either.
 392          * Mask must be always present, it defines the actual field width.
 393          */
 394         MLX5_ASSERT(item->mask);
 395         MLX5_ASSERT(field->size);
 396         do {
 397                 unsigned int size_b;
 398                 unsigned int off_b;
 399                 uint32_t mask;
 400                 uint32_t data;
 401
 402                 if (i >= MLX5_MAX_MODIFY_NUM)
 403                         return rte_flow_error_set(error, EINVAL,
 404                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 405                                  "too many items to modify");
 406                 /* Fetch variable byte size mask from the array. */
 407                 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
 408                                            field->offset, field->size);
 409                 if (!mask) {
 410                         ++field;
 411                         continue;
 412                 }
 413                 /* Deduce actual data width in bits from mask value. */
 414                 off_b = rte_bsf32(mask);
 415                 size_b = sizeof(uint32_t) * CHAR_BIT -
 416                          off_b - __builtin_clz(mask);
 417                 MLX5_ASSERT(size_b);
 418                 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
 419                 actions[i] = (struct mlx5_modification_cmd) {
 420                         .action_type = type,
 421                         .field = field->id,
 422                         .offset = off_b,
 423                         .length = size_b,
 424                 };
 425                 /* Convert entire record to expected big-endian format. */
 426                 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 427                 if (type == MLX5_MODIFICATION_TYPE_COPY) {
 428                         MLX5_ASSERT(dcopy);
 429                         actions[i].dst_field = dcopy->id;
 430                         actions[i].dst_offset =
 431                                 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
 432                         /* Convert entire record to big-endian format. */
 433                         actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
 434                         ++dcopy;
 435                 } else {
 436                         MLX5_ASSERT(item->spec);
 437                         data = flow_dv_fetch_field((const uint8_t *)item->spec +
 438                                                    field->offset, field->size);
 439                         /* Shift out the trailing masked bits from data. */
 440                         data = (data & mask) >> off_b;
 441                         actions[i].data1 = rte_cpu_to_be_32(data);
 442                 }
 443                 ++i;
 444                 ++field;
 445         } while (field->size);
 446         if (resource->actions_num == i)
 447                 return rte_flow_error_set(error, EINVAL,
 448                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 449                                           "invalid modification flow item");
 450         resource->actions_num = i;
 451         return 0;
 452 }
 453
 454 /**
 455  * Convert modify-header set IPv4 address action to DV specification.
 456  *
 457  * @param[in,out] resource
 458  *   Pointer to the modify-header resource.
 459  * @param[in] action
 460  *   Pointer to action specification.
 461  * @param[out] error
 462  *   Pointer to the error structure.
 463  *
 464  * @return
 465  *   0 on success, a negative errno value otherwise and rte_errno is set.
 466  */
 467 static int
 468 flow_dv_convert_action_modify_ipv4
 469                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 470                          const struct rte_flow_action *action,
 471                          struct rte_flow_error *error)
 472 {
 473         const struct rte_flow_action_set_ipv4 *conf =
 474                 (const struct rte_flow_action_set_ipv4 *)(action->conf);
 475         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
 476         struct rte_flow_item_ipv4 ipv4;
 477         struct rte_flow_item_ipv4 ipv4_mask;
 478
 479         memset(&ipv4, 0, sizeof(ipv4));
 480         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 481         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
 482                 ipv4.hdr.src_addr = conf->ipv4_addr;
 483                 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
 484         } else {
 485                 ipv4.hdr.dst_addr = conf->ipv4_addr;
 486                 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
 487         }
 488         item.spec = &ipv4;
 489         item.mask = &ipv4_mask;
 490         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
 491                                              MLX5_MODIFICATION_TYPE_SET, error);
 492 }
 493
 494 /**
 495  * Convert modify-header set IPv6 address action to DV specification.
 496  *
 497  * @param[in,out] resource
 498  *   Pointer to the modify-header resource.
 499  * @param[in] action
 500  *   Pointer to action specification.
 501  * @param[out] error
 502  *   Pointer to the error structure.
 503  *
 504  * @return
 505  *   0 on success, a negative errno value otherwise and rte_errno is set.
 506  */
 507 static int
 508 flow_dv_convert_action_modify_ipv6
 509                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 510                          const struct rte_flow_action *action,
 511                          struct rte_flow_error *error)
 512 {
 513         const struct rte_flow_action_set_ipv6 *conf =
 514                 (const struct rte_flow_action_set_ipv6 *)(action->conf);
 515         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
 516         struct rte_flow_item_ipv6 ipv6;
 517         struct rte_flow_item_ipv6 ipv6_mask;
 518
 519         memset(&ipv6, 0, sizeof(ipv6));
 520         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 521         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
 522                 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
 523                        sizeof(ipv6.hdr.src_addr));
 524                 memcpy(&ipv6_mask.hdr.src_addr,
 525                        &rte_flow_item_ipv6_mask.hdr.src_addr,
 526                        sizeof(ipv6.hdr.src_addr));
 527         } else {
 528                 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
 529                        sizeof(ipv6.hdr.dst_addr));
 530                 memcpy(&ipv6_mask.hdr.dst_addr,
 531                        &rte_flow_item_ipv6_mask.hdr.dst_addr,
 532                        sizeof(ipv6.hdr.dst_addr));
 533         }
 534         item.spec = &ipv6;
 535         item.mask = &ipv6_mask;
 536         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
 537                                              MLX5_MODIFICATION_TYPE_SET, error);
 538 }
 539
 540 /**
 541  * Convert modify-header set MAC address action to DV specification.
 542  *
 543  * @param[in,out] resource
 544  *   Pointer to the modify-header resource.
 545  * @param[in] action
 546  *   Pointer to action specification.
 547  * @param[out] error
 548  *   Pointer to the error structure.
 549  *
 550  * @return
 551  *   0 on success, a negative errno value otherwise and rte_errno is set.
 552  */
 553 static int
 554 flow_dv_convert_action_modify_mac
 555                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 556                          const struct rte_flow_action *action,
 557                          struct rte_flow_error *error)
 558 {
 559         const struct rte_flow_action_set_mac *conf =
 560                 (const struct rte_flow_action_set_mac *)(action->conf);
 561         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
 562         struct rte_flow_item_eth eth;
 563         struct rte_flow_item_eth eth_mask;
 564
 565         memset(&eth, 0, sizeof(eth));
 566         memset(&eth_mask, 0, sizeof(eth_mask));
 567         if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
 568                 memcpy(&eth.src.addr_bytes, &conf->mac_addr,
 569                        sizeof(eth.src.addr_bytes));
 570                 memcpy(&eth_mask.src.addr_bytes,
 571                        &rte_flow_item_eth_mask.src.addr_bytes,
 572                        sizeof(eth_mask.src.addr_bytes));
 573         } else {
 574                 memcpy(&eth.dst.addr_bytes, &conf->mac_addr,
 575                        sizeof(eth.dst.addr_bytes));
 576                 memcpy(&eth_mask.dst.addr_bytes,
 577                        &rte_flow_item_eth_mask.dst.addr_bytes,
 578                        sizeof(eth_mask.dst.addr_bytes));
 579         }
 580         item.spec = &eth;
 581         item.mask = &eth_mask;
 582         return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
 583                                              MLX5_MODIFICATION_TYPE_SET, error);
 584 }
 585
 586 /**
 587  * Convert modify-header set VLAN VID action to DV specification.
 588  *
 589  * @param[in,out] resource
 590  *   Pointer to the modify-header resource.
 591  * @param[in] action
 592  *   Pointer to action specification.
 593  * @param[out] error
 594  *   Pointer to the error structure.
 595  *
 596  * @return
 597  *   0 on success, a negative errno value otherwise and rte_errno is set.
 598  */
 599 static int
 600 flow_dv_convert_action_modify_vlan_vid
 601                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 602                          const struct rte_flow_action *action,
 603                          struct rte_flow_error *error)
 604 {
 605         const struct rte_flow_action_of_set_vlan_vid *conf =
 606                 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
 607         int i = resource->actions_num;
 608         struct mlx5_modification_cmd *actions = resource->actions;
 609         struct field_modify_info *field = modify_vlan_out_first_vid;
 610
 611         if (i >= MLX5_MAX_MODIFY_NUM)
 612                 return rte_flow_error_set(error, EINVAL,
 613                          RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 614                          "too many items to modify");
 615         actions[i] = (struct mlx5_modification_cmd) {
 616                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 617                 .field = field->id,
 618                 .length = field->size,
 619                 .offset = field->offset,
 620         };
 621         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 622         actions[i].data1 = conf->vlan_vid;
 623         actions[i].data1 = actions[i].data1 << 16;
 624         resource->actions_num = ++i;
 625         return 0;
 626 }
 627
 628 /**
 629  * Convert modify-header set TP action to DV specification.
 630  *
 631  * @param[in,out] resource
 632  *   Pointer to the modify-header resource.
 633  * @param[in] action
 634  *   Pointer to action specification.
 635  * @param[in] items
 636  *   Pointer to rte_flow_item objects list.
 637  * @param[in] attr
 638  *   Pointer to flow attributes structure.
 639  * @param[in] dev_flow
 640  *   Pointer to the sub flow.
 641  * @param[in] tunnel_decap
 642  *   Whether action is after tunnel decapsulation.
 643  * @param[out] error
 644  *   Pointer to the error structure.
 645  *
 646  * @return
 647  *   0 on success, a negative errno value otherwise and rte_errno is set.
 648  */
 649 static int
 650 flow_dv_convert_action_modify_tp
 651                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 652                          const struct rte_flow_action *action,
 653                          const struct rte_flow_item *items,
 654                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 655                          bool tunnel_decap, struct rte_flow_error *error)
 656 {
 657         const struct rte_flow_action_set_tp *conf =
 658                 (const struct rte_flow_action_set_tp *)(action->conf);
 659         struct rte_flow_item item;
 660         struct rte_flow_item_udp udp;
 661         struct rte_flow_item_udp udp_mask;
 662         struct rte_flow_item_tcp tcp;
 663         struct rte_flow_item_tcp tcp_mask;
 664         struct field_modify_info *field;
 665
 666         if (!attr->valid)
 667                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 668         if (attr->udp) {
 669                 memset(&udp, 0, sizeof(udp));
 670                 memset(&udp_mask, 0, sizeof(udp_mask));
 671                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 672                         udp.hdr.src_port = conf->port;
 673                         udp_mask.hdr.src_port =
 674                                         rte_flow_item_udp_mask.hdr.src_port;
 675                 } else {
 676                         udp.hdr.dst_port = conf->port;
 677                         udp_mask.hdr.dst_port =
 678                                         rte_flow_item_udp_mask.hdr.dst_port;
 679                 }
 680                 item.type = RTE_FLOW_ITEM_TYPE_UDP;
 681                 item.spec = &udp;
 682                 item.mask = &udp_mask;
 683                 field = modify_udp;
 684         } else {
 685                 MLX5_ASSERT(attr->tcp);
 686                 memset(&tcp, 0, sizeof(tcp));
 687                 memset(&tcp_mask, 0, sizeof(tcp_mask));
 688                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 689                         tcp.hdr.src_port = conf->port;
 690                         tcp_mask.hdr.src_port =
 691                                         rte_flow_item_tcp_mask.hdr.src_port;
 692                 } else {
 693                         tcp.hdr.dst_port = conf->port;
 694                         tcp_mask.hdr.dst_port =
 695                                         rte_flow_item_tcp_mask.hdr.dst_port;
 696                 }
 697                 item.type = RTE_FLOW_ITEM_TYPE_TCP;
 698                 item.spec = &tcp;
 699                 item.mask = &tcp_mask;
 700                 field = modify_tcp;
 701         }
 702         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 703                                              MLX5_MODIFICATION_TYPE_SET, error);
 704 }
 705
 706 /**
 707  * Convert modify-header set TTL action to DV specification.
 708  *
 709  * @param[in,out] resource
 710  *   Pointer to the modify-header resource.
 711  * @param[in] action
 712  *   Pointer to action specification.
 713  * @param[in] items
 714  *   Pointer to rte_flow_item objects list.
 715  * @param[in] attr
 716  *   Pointer to flow attributes structure.
 717  * @param[in] dev_flow
 718  *   Pointer to the sub flow.
 719  * @param[in] tunnel_decap
 720  *   Whether action is after tunnel decapsulation.
 721  * @param[out] error
 722  *   Pointer to the error structure.
 723  *
 724  * @return
 725  *   0 on success, a negative errno value otherwise and rte_errno is set.
 726  */
 727 static int
 728 flow_dv_convert_action_modify_ttl
 729                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 730                          const struct rte_flow_action *action,
 731                          const struct rte_flow_item *items,
 732                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 733                          bool tunnel_decap, struct rte_flow_error *error)
 734 {
 735         const struct rte_flow_action_set_ttl *conf =
 736                 (const struct rte_flow_action_set_ttl *)(action->conf);
 737         struct rte_flow_item item;
 738         struct rte_flow_item_ipv4 ipv4;
 739         struct rte_flow_item_ipv4 ipv4_mask;
 740         struct rte_flow_item_ipv6 ipv6;
 741         struct rte_flow_item_ipv6 ipv6_mask;
 742         struct field_modify_info *field;
 743
 744         if (!attr->valid)
 745                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 746         if (attr->ipv4) {
 747                 memset(&ipv4, 0, sizeof(ipv4));
 748                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 749                 ipv4.hdr.time_to_live = conf->ttl_value;
 750                 ipv4_mask.hdr.time_to_live = 0xFF;
 751                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 752                 item.spec = &ipv4;
 753                 item.mask = &ipv4_mask;
 754                 field = modify_ipv4;
 755         } else {
 756                 MLX5_ASSERT(attr->ipv6);
 757                 memset(&ipv6, 0, sizeof(ipv6));
 758                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 759                 ipv6.hdr.hop_limits = conf->ttl_value;
 760                 ipv6_mask.hdr.hop_limits = 0xFF;
 761                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 762                 item.spec = &ipv6;
 763                 item.mask = &ipv6_mask;
 764                 field = modify_ipv6;
 765         }
 766         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 767                                              MLX5_MODIFICATION_TYPE_SET, error);
 768 }
 769
 770 /**
 771  * Convert modify-header decrement TTL action to DV specification.
 772  *
 773  * @param[in,out] resource
 774  *   Pointer to the modify-header resource.
 775  * @param[in] action
 776  *   Pointer to action specification.
 777  * @param[in] items
 778  *   Pointer to rte_flow_item objects list.
 779  * @param[in] attr
 780  *   Pointer to flow attributes structure.
 781  * @param[in] dev_flow
 782  *   Pointer to the sub flow.
 783  * @param[in] tunnel_decap
 784  *   Whether action is after tunnel decapsulation.
 785  * @param[out] error
 786  *   Pointer to the error structure.
 787  *
 788  * @return
 789  *   0 on success, a negative errno value otherwise and rte_errno is set.
 790  */
 791 static int
 792 flow_dv_convert_action_modify_dec_ttl
 793                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 794                          const struct rte_flow_item *items,
 795                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 796                          bool tunnel_decap, struct rte_flow_error *error)
 797 {
 798         struct rte_flow_item item;
 799         struct rte_flow_item_ipv4 ipv4;
 800         struct rte_flow_item_ipv4 ipv4_mask;
 801         struct rte_flow_item_ipv6 ipv6;
 802         struct rte_flow_item_ipv6 ipv6_mask;
 803         struct field_modify_info *field;
 804
 805         if (!attr->valid)
 806                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 807         if (attr->ipv4) {
 808                 memset(&ipv4, 0, sizeof(ipv4));
 809                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 810                 ipv4.hdr.time_to_live = 0xFF;
 811                 ipv4_mask.hdr.time_to_live = 0xFF;
 812                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 813                 item.spec = &ipv4;
 814                 item.mask = &ipv4_mask;
 815                 field = modify_ipv4;
 816         } else {
 817                 MLX5_ASSERT(attr->ipv6);
 818                 memset(&ipv6, 0, sizeof(ipv6));
 819                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 820                 ipv6.hdr.hop_limits = 0xFF;
 821                 ipv6_mask.hdr.hop_limits = 0xFF;
 822                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 823                 item.spec = &ipv6;
 824                 item.mask = &ipv6_mask;
 825                 field = modify_ipv6;
 826         }
 827         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 828                                              MLX5_MODIFICATION_TYPE_ADD, error);
 829 }
 830
 831 /**
 832  * Convert modify-header increment/decrement TCP Sequence number
 833  * to DV specification.
 834  *
 835  * @param[in,out] resource
 836  *   Pointer to the modify-header resource.
 837  * @param[in] action
 838  *   Pointer to action specification.
 839  * @param[out] error
 840  *   Pointer to the error structure.
 841  *
 842  * @return
 843  *   0 on success, a negative errno value otherwise and rte_errno is set.
 844  */
 845 static int
 846 flow_dv_convert_action_modify_tcp_seq
 847                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 848                          const struct rte_flow_action *action,
 849                          struct rte_flow_error *error)
 850 {
 851         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 852         uint64_t value = rte_be_to_cpu_32(*conf);
 853         struct rte_flow_item item;
 854         struct rte_flow_item_tcp tcp;
 855         struct rte_flow_item_tcp tcp_mask;
 856
 857         memset(&tcp, 0, sizeof(tcp));
 858         memset(&tcp_mask, 0, sizeof(tcp_mask));
 859         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
 860                 /*
 861                  * The HW has no decrement operation, only increment operation.
 862                  * To simulate decrement X from Y using increment operation
 863                  * we need to add UINT32_MAX X times to Y.
 864                  * Each adding of UINT32_MAX decrements Y by 1.
 865                  */
 866                 value *= UINT32_MAX;
 867         tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
 868         tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
 869         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 870         item.spec = &tcp;
 871         item.mask = &tcp_mask;
 872         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 873                                              MLX5_MODIFICATION_TYPE_ADD, error);
 874 }
 875
 876 /**
 877  * Convert modify-header increment/decrement TCP Acknowledgment number
 878  * to DV specification.
 879  *
 880  * @param[in,out] resource
 881  *   Pointer to the modify-header resource.
 882  * @param[in] action
 883  *   Pointer to action specification.
 884  * @param[out] error
 885  *   Pointer to the error structure.
 886  *
 887  * @return
 888  *   0 on success, a negative errno value otherwise and rte_errno is set.
 889  */
 890 static int
 891 flow_dv_convert_action_modify_tcp_ack
 892                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 893                          const struct rte_flow_action *action,
 894                          struct rte_flow_error *error)
 895 {
 896         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 897         uint64_t value = rte_be_to_cpu_32(*conf);
 898         struct rte_flow_item item;
 899         struct rte_flow_item_tcp tcp;
 900         struct rte_flow_item_tcp tcp_mask;
 901
 902         memset(&tcp, 0, sizeof(tcp));
 903         memset(&tcp_mask, 0, sizeof(tcp_mask));
 904         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
 905                 /*
 906                  * The HW has no decrement operation, only increment operation.
 907                  * To simulate decrement X from Y using increment operation
 908                  * we need to add UINT32_MAX X times to Y.
 909                  * Each adding of UINT32_MAX decrements Y by 1.
 910                  */
 911                 value *= UINT32_MAX;
 912         tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
 913         tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
 914         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 915         item.spec = &tcp;
 916         item.mask = &tcp_mask;
 917         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 918                                              MLX5_MODIFICATION_TYPE_ADD, error);
 919 }
 920
 921 static enum mlx5_modification_field reg_to_field[] = {
 922         [REG_NON] = MLX5_MODI_OUT_NONE,
 923         [REG_A] = MLX5_MODI_META_DATA_REG_A,
 924         [REG_B] = MLX5_MODI_META_DATA_REG_B,
 925         [REG_C_0] = MLX5_MODI_META_REG_C_0,
 926         [REG_C_1] = MLX5_MODI_META_REG_C_1,
 927         [REG_C_2] = MLX5_MODI_META_REG_C_2,
 928         [REG_C_3] = MLX5_MODI_META_REG_C_3,
 929         [REG_C_4] = MLX5_MODI_META_REG_C_4,
 930         [REG_C_5] = MLX5_MODI_META_REG_C_5,
 931         [REG_C_6] = MLX5_MODI_META_REG_C_6,
 932         [REG_C_7] = MLX5_MODI_META_REG_C_7,
 933 };
 934
 935 /**
 936  * Convert register set to DV specification.
 937  *
 938  * @param[in,out] resource
 939  *   Pointer to the modify-header resource.
 940  * @param[in] action
 941  *   Pointer to action specification.
 942  * @param[out] error
 943  *   Pointer to the error structure.
 944  *
 945  * @return
 946  *   0 on success, a negative errno value otherwise and rte_errno is set.
 947  */
 948 static int
 949 flow_dv_convert_action_set_reg
 950                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 951                          const struct rte_flow_action *action,
 952                          struct rte_flow_error *error)
 953 {
 954         const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
 955         struct mlx5_modification_cmd *actions = resource->actions;
 956         uint32_t i = resource->actions_num;
 957
 958         if (i >= MLX5_MAX_MODIFY_NUM)
 959                 return rte_flow_error_set(error, EINVAL,
 960                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 961                                           "too many items to modify");
 962         MLX5_ASSERT(conf->id != REG_NON);
 963         MLX5_ASSERT(conf->id < (enum modify_reg)RTE_DIM(reg_to_field));
 964         actions[i] = (struct mlx5_modification_cmd) {
 965                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 966                 .field = reg_to_field[conf->id],
 967         };
 968         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 969         actions[i].data1 = rte_cpu_to_be_32(conf->data);
 970         ++i;
 971         resource->actions_num = i;
 972         return 0;
 973 }
 974
 975 /**
 976  * Convert SET_TAG action to DV specification.
 977  *
 978  * @param[in] dev
 979  *   Pointer to the rte_eth_dev structure.
 980  * @param[in,out] resource
 981  *   Pointer to the modify-header resource.
 982  * @param[in] conf
 983  *   Pointer to action specification.
 984  * @param[out] error
 985  *   Pointer to the error structure.
 986  *
 987  * @return
 988  *   0 on success, a negative errno value otherwise and rte_errno is set.
 989  */
 990 static int
 991 flow_dv_convert_action_set_tag
 992                         (struct rte_eth_dev *dev,
 993                          struct mlx5_flow_dv_modify_hdr_resource *resource,
 994                          const struct rte_flow_action_set_tag *conf,
 995                          struct rte_flow_error *error)
 996 {
 997         rte_be32_t data = rte_cpu_to_be_32(conf->data);
 998         rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
 999         struct rte_flow_item item = {
1000                 .spec = &data,
1001                 .mask = &mask,
1002         };
1003         struct field_modify_info reg_c_x[] = {
1004                 [1] = {0, 0, 0},
1005         };
1006         enum mlx5_modification_field reg_type;
1007         int ret;
1008
1009         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1010         if (ret < 0)
1011                 return ret;
1012         MLX5_ASSERT(ret != REG_NON);
1013         MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1014         reg_type = reg_to_field[ret];
1015         MLX5_ASSERT(reg_type > 0);
1016         reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1017         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1018                                              MLX5_MODIFICATION_TYPE_SET, error);
1019 }
1020
1021 /**
1022  * Convert internal COPY_REG action to DV specification.
1023  *
1024  * @param[in] dev
1025  *   Pointer to the rte_eth_dev structure.
1026  * @param[in,out] res
1027  *   Pointer to the modify-header resource.
1028  * @param[in] action
1029  *   Pointer to action specification.
1030  * @param[out] error
1031  *   Pointer to the error structure.
1032  *
1033  * @return
1034  *   0 on success, a negative errno value otherwise and rte_errno is set.
1035  */
1036 static int
1037 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1038                                  struct mlx5_flow_dv_modify_hdr_resource *res,
1039                                  const struct rte_flow_action *action,
1040                                  struct rte_flow_error *error)
1041 {
1042         const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1043         rte_be32_t mask = RTE_BE32(UINT32_MAX);
1044         struct rte_flow_item item = {
1045                 .spec = NULL,
1046                 .mask = &mask,
1047         };
1048         struct field_modify_info reg_src[] = {
1049                 {4, 0, reg_to_field[conf->src]},
1050                 {0, 0, 0},
1051         };
1052         struct field_modify_info reg_dst = {
1053                 .offset = 0,
1054                 .id = reg_to_field[conf->dst],
1055         };
1056         /* Adjust reg_c[0] usage according to reported mask. */
1057         if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1058                 struct mlx5_priv *priv = dev->data->dev_private;
1059                 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1060
1061                 MLX5_ASSERT(reg_c0);
1062                 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1063                 if (conf->dst == REG_C_0) {
1064                         /* Copy to reg_c[0], within mask only. */
1065                         reg_dst.offset = rte_bsf32(reg_c0);
1066                         /*
1067                          * Mask is ignoring the enianness, because
1068                          * there is no conversion in datapath.
1069                          */
1070 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1071                         /* Copy from destination lower bits to reg_c[0]. */
1072                         mask = reg_c0 >> reg_dst.offset;
1073 #else
1074                         /* Copy from destination upper bits to reg_c[0]. */
1075                         mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1076                                           rte_fls_u32(reg_c0));
1077 #endif
1078                 } else {
1079                         mask = rte_cpu_to_be_32(reg_c0);
1080 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1081                         /* Copy from reg_c[0] to destination lower bits. */
1082                         reg_dst.offset = 0;
1083 #else
1084                         /* Copy from reg_c[0] to destination upper bits. */
1085                         reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1086                                          (rte_fls_u32(reg_c0) -
1087                                           rte_bsf32(reg_c0));
1088 #endif
1089                 }
1090         }
1091         return flow_dv_convert_modify_action(&item,
1092                                              reg_src, &reg_dst, res,
1093                                              MLX5_MODIFICATION_TYPE_COPY,
1094                                              error);
1095 }
1096
1097 /**
1098  * Convert MARK action to DV specification. This routine is used
1099  * in extensive metadata only and requires metadata register to be
1100  * handled. In legacy mode hardware tag resource is engaged.
1101  *
1102  * @param[in] dev
1103  *   Pointer to the rte_eth_dev structure.
1104  * @param[in] conf
1105  *   Pointer to MARK action specification.
1106  * @param[in,out] resource
1107  *   Pointer to the modify-header resource.
1108  * @param[out] error
1109  *   Pointer to the error structure.
1110  *
1111  * @return
1112  *   0 on success, a negative errno value otherwise and rte_errno is set.
1113  */
1114 static int
1115 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1116                             const struct rte_flow_action_mark *conf,
1117                             struct mlx5_flow_dv_modify_hdr_resource *resource,
1118                             struct rte_flow_error *error)
1119 {
1120         struct mlx5_priv *priv = dev->data->dev_private;
1121         rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1122                                            priv->sh->dv_mark_mask);
1123         rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1124         struct rte_flow_item item = {
1125                 .spec = &data,
1126                 .mask = &mask,
1127         };
1128         struct field_modify_info reg_c_x[] = {
1129                 [1] = {0, 0, 0},
1130         };
1131         int reg;
1132
1133         if (!mask)
1134                 return rte_flow_error_set(error, EINVAL,
1135                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1136                                           NULL, "zero mark action mask");
1137         reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1138         if (reg < 0)
1139                 return reg;
1140         MLX5_ASSERT(reg > 0);
1141         if (reg == REG_C_0) {
1142                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1143                 uint32_t shl_c0 = rte_bsf32(msk_c0);
1144
1145                 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1146                 mask = rte_cpu_to_be_32(mask) & msk_c0;
1147                 mask = rte_cpu_to_be_32(mask << shl_c0);
1148         }
1149         reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1150         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1151                                              MLX5_MODIFICATION_TYPE_SET, error);
1152 }
1153
1154 /**
1155  * Get metadata register index for specified steering domain.
1156  *
1157  * @param[in] dev
1158  *   Pointer to the rte_eth_dev structure.
1159  * @param[in] attr
1160  *   Attributes of flow to determine steering domain.
1161  * @param[out] error
1162  *   Pointer to the error structure.
1163  *
1164  * @return
1165  *   positive index on success, a negative errno value otherwise
1166  *   and rte_errno is set.
1167  */
1168 static enum modify_reg
1169 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1170                          const struct rte_flow_attr *attr,
1171                          struct rte_flow_error *error)
1172 {
1173         int reg =
1174                 mlx5_flow_get_reg_id(dev, attr->transfer ?
1175                                           MLX5_METADATA_FDB :
1176                                             attr->egress ?
1177                                             MLX5_METADATA_TX :
1178                                             MLX5_METADATA_RX, 0, error);
1179         if (reg < 0)
1180                 return rte_flow_error_set(error,
1181                                           ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1182                                           NULL, "unavailable "
1183                                           "metadata register");
1184         return reg;
1185 }
1186
1187 /**
1188  * Convert SET_META action to DV specification.
1189  *
1190  * @param[in] dev
1191  *   Pointer to the rte_eth_dev structure.
1192  * @param[in,out] resource
1193  *   Pointer to the modify-header resource.
1194  * @param[in] attr
1195  *   Attributes of flow that includes this item.
1196  * @param[in] conf
1197  *   Pointer to action specification.
1198  * @param[out] error
1199  *   Pointer to the error structure.
1200  *
1201  * @return
1202  *   0 on success, a negative errno value otherwise and rte_errno is set.
1203  */
1204 static int
1205 flow_dv_convert_action_set_meta
1206                         (struct rte_eth_dev *dev,
1207                          struct mlx5_flow_dv_modify_hdr_resource *resource,
1208                          const struct rte_flow_attr *attr,
1209                          const struct rte_flow_action_set_meta *conf,
1210                          struct rte_flow_error *error)
1211 {
1212         uint32_t data = conf->data;
1213         uint32_t mask = conf->mask;
1214         struct rte_flow_item item = {
1215                 .spec = &data,
1216                 .mask = &mask,
1217         };
1218         struct field_modify_info reg_c_x[] = {
1219                 [1] = {0, 0, 0},
1220         };
1221         int reg = flow_dv_get_metadata_reg(dev, attr, error);
1222
1223         if (reg < 0)
1224                 return reg;
1225         MLX5_ASSERT(reg != REG_NON);
1226         /*
1227          * In datapath code there is no endianness
1228          * coversions for perfromance reasons, all
1229          * pattern conversions are done in rte_flow.
1230          */
1231         if (reg == REG_C_0) {
1232                 struct mlx5_priv *priv = dev->data->dev_private;
1233                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1234                 uint32_t shl_c0;
1235
1236                 MLX5_ASSERT(msk_c0);
1237 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1238                 shl_c0 = rte_bsf32(msk_c0);
1239 #else
1240                 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1241 #endif
1242                 mask <<= shl_c0;
1243                 data <<= shl_c0;
1244                 MLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1245         }
1246         reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1247         /* The routine expects parameters in memory as big-endian ones. */
1248         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1249                                              MLX5_MODIFICATION_TYPE_SET, error);
1250 }
1251
1252 /**
1253  * Convert modify-header set IPv4 DSCP action to DV specification.
1254  *
1255  * @param[in,out] resource
1256  *   Pointer to the modify-header resource.
1257  * @param[in] action
1258  *   Pointer to action specification.
1259  * @param[out] error
1260  *   Pointer to the error structure.
1261  *
1262  * @return
1263  *   0 on success, a negative errno value otherwise and rte_errno is set.
1264  */
1265 static int
1266 flow_dv_convert_action_modify_ipv4_dscp
1267                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1268                          const struct rte_flow_action *action,
1269                          struct rte_flow_error *error)
1270 {
1271         const struct rte_flow_action_set_dscp *conf =
1272                 (const struct rte_flow_action_set_dscp *)(action->conf);
1273         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1274         struct rte_flow_item_ipv4 ipv4;
1275         struct rte_flow_item_ipv4 ipv4_mask;
1276
1277         memset(&ipv4, 0, sizeof(ipv4));
1278         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1279         ipv4.hdr.type_of_service = conf->dscp;
1280         ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1281         item.spec = &ipv4;
1282         item.mask = &ipv4_mask;
1283         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1284                                              MLX5_MODIFICATION_TYPE_SET, error);
1285 }
1286
1287 /**
1288  * Convert modify-header set IPv6 DSCP action to DV specification.
1289  *
1290  * @param[in,out] resource
1291  *   Pointer to the modify-header resource.
1292  * @param[in] action
1293  *   Pointer to action specification.
1294  * @param[out] error
1295  *   Pointer to the error structure.
1296  *
1297  * @return
1298  *   0 on success, a negative errno value otherwise and rte_errno is set.
1299  */
1300 static int
1301 flow_dv_convert_action_modify_ipv6_dscp
1302                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1303                          const struct rte_flow_action *action,
1304                          struct rte_flow_error *error)
1305 {
1306         const struct rte_flow_action_set_dscp *conf =
1307                 (const struct rte_flow_action_set_dscp *)(action->conf);
1308         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1309         struct rte_flow_item_ipv6 ipv6;
1310         struct rte_flow_item_ipv6 ipv6_mask;
1311
1312         memset(&ipv6, 0, sizeof(ipv6));
1313         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1314         /*
1315          * Even though the DSCP bits offset of IPv6 is not byte aligned,
1316          * rdma-core only accept the DSCP bits byte aligned start from
1317          * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1318          * bits in IPv6 case as rdma-core requires byte aligned value.
1319          */
1320         ipv6.hdr.vtc_flow = conf->dscp;
1321         ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1322         item.spec = &ipv6;
1323         item.mask = &ipv6_mask;
1324         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1325                                              MLX5_MODIFICATION_TYPE_SET, error);
1326 }
1327
1328 static void
1329 mlx5_flow_field_id_to_modify_info
1330                 (const struct rte_flow_action_modify_data *data,
1331                  struct field_modify_info *info,
1332                  uint32_t *mask, uint32_t *value, uint32_t width,
1333                  struct rte_eth_dev *dev,
1334                  const struct rte_flow_attr *attr,
1335                  struct rte_flow_error *error)
1336 {
1337         uint32_t idx = 0;
1338         switch (data->field) {
1339         case RTE_FLOW_FIELD_START:
1340                 /* not supported yet */
1341                 MLX5_ASSERT(false);
1342                 break;
1343         case RTE_FLOW_FIELD_MAC_DST:
1344                 if (mask) {
1345                         if (data->offset < 32) {
1346                                 info[idx] = (struct field_modify_info){4, 0,
1347                                                 MLX5_MODI_OUT_DMAC_47_16};
1348                                 if (width < 32) {
1349                                         mask[idx] =
1350                                                 rte_cpu_to_be_32(0xffffffff >>
1351                                                                  (32 - width));
1352                                         width = 0;
1353                                 } else {
1354                                         mask[idx] = RTE_BE32(0xffffffff);
1355                                         width -= 32;
1356                                 }
1357                                 if (!width)
1358                                         break;
1359                                 ++idx;
1360                         }
1361                         info[idx] = (struct field_modify_info){2, 4 * idx,
1362                                                 MLX5_MODI_OUT_DMAC_15_0};
1363                         mask[idx] = rte_cpu_to_be_32(0x0000ffff >>
1364                                                      (16 - width));
1365                 } else {
1366                         if (data->offset < 32)
1367                                 info[idx++] = (struct field_modify_info){4, 0,
1368                                                 MLX5_MODI_OUT_DMAC_47_16};
1369                         info[idx] = (struct field_modify_info){2, 0,
1370                                                 MLX5_MODI_OUT_DMAC_15_0};
1371                 }
1372                 break;
1373         case RTE_FLOW_FIELD_MAC_SRC:
1374                 if (mask) {
1375                         if (data->offset < 32) {
1376                                 info[idx] = (struct field_modify_info){4, 0,
1377                                                 MLX5_MODI_OUT_SMAC_47_16};
1378                                 if (width < 32) {
1379                                         mask[idx] =
1380                                                 rte_cpu_to_be_32(0xffffffff >>
1381                                                                 (32 - width));
1382                                         width = 0;
1383                                 } else {
1384                                         mask[idx] = RTE_BE32(0xffffffff);
1385                                         width -= 32;
1386                                 }
1387                                 if (!width)
1388                                         break;
1389                                 ++idx;
1390                         }
1391                         info[idx] = (struct field_modify_info){2, 4 * idx,
1392                                                 MLX5_MODI_OUT_SMAC_15_0};
1393                         mask[idx] = rte_cpu_to_be_32(0x0000ffff >>
1394                                                      (16 - width));
1395                 } else {
1396                         if (data->offset < 32)
1397                                 info[idx++] = (struct field_modify_info){4, 0,
1398                                                 MLX5_MODI_OUT_SMAC_47_16};
1399                         info[idx] = (struct field_modify_info){2, 0,
1400                                                 MLX5_MODI_OUT_SMAC_15_0};
1401                 }
1402                 break;
1403         case RTE_FLOW_FIELD_VLAN_TYPE:
1404                 /* not supported yet */
1405                 break;
1406         case RTE_FLOW_FIELD_VLAN_ID:
1407                 info[idx] = (struct field_modify_info){2, 0,
1408                                         MLX5_MODI_OUT_FIRST_VID};
1409                 if (mask)
1410                         mask[idx] = rte_cpu_to_be_32(0x00000fff >>
1411                                                      (12 - width));
1412                 break;
1413         case RTE_FLOW_FIELD_MAC_TYPE:
1414                 info[idx] = (struct field_modify_info){2, 0,
1415                                         MLX5_MODI_OUT_ETHERTYPE};
1416                 if (mask)
1417                         mask[idx] = rte_cpu_to_be_32(0x0000ffff >>
1418                                                      (16 - width));
1419                 break;
1420         case RTE_FLOW_FIELD_IPV4_DSCP:
1421                 info[idx] = (struct field_modify_info){1, 0,
1422                                         MLX5_MODI_OUT_IP_DSCP};
1423                 if (mask)
1424                         mask[idx] = rte_cpu_to_be_32(0x0000003f >>
1425                                                      (6 - width));
1426                 break;
1427         case RTE_FLOW_FIELD_IPV4_TTL:
1428                 info[idx] = (struct field_modify_info){1, 0,
1429                                         MLX5_MODI_OUT_IPV4_TTL};
1430                 if (mask)
1431                         mask[idx] = rte_cpu_to_be_32(0x000000ff >>
1432                                                      (8 - width));
1433                 break;
1434         case RTE_FLOW_FIELD_IPV4_SRC:
1435                 info[idx] = (struct field_modify_info){4, 0,
1436                                         MLX5_MODI_OUT_SIPV4};
1437                 if (mask)
1438                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1439                                                      (32 - width));
1440                 break;
1441         case RTE_FLOW_FIELD_IPV4_DST:
1442                 info[idx] = (struct field_modify_info){4, 0,
1443                                         MLX5_MODI_OUT_DIPV4};
1444                 if (mask)
1445                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1446                                                      (32 - width));
1447                 break;
1448         case RTE_FLOW_FIELD_IPV6_DSCP:
1449                 info[idx] = (struct field_modify_info){1, 0,
1450                                         MLX5_MODI_OUT_IP_DSCP};
1451                 if (mask)
1452                         mask[idx] = rte_cpu_to_be_32(0x0000003f >>
1453                                                      (6 - width));
1454                 break;
1455         case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
1456                 info[idx] = (struct field_modify_info){1, 0,
1457                                         MLX5_MODI_OUT_IPV6_HOPLIMIT};
1458                 if (mask)
1459                         mask[idx] = rte_cpu_to_be_32(0x000000ff >>
1460                                                      (8 - width));
1461                 break;
1462         case RTE_FLOW_FIELD_IPV6_SRC:
1463                 if (mask) {
1464                         if (data->offset < 32) {
1465                                 info[idx] = (struct field_modify_info){4, 0,
1466                                                 MLX5_MODI_OUT_SIPV6_127_96};
1467                                 if (width < 32) {
1468                                         mask[idx] =
1469                                                 rte_cpu_to_be_32(0xffffffff >>
1470                                                                  (32 - width));
1471                                         width = 0;
1472                                 } else {
1473                                         mask[idx] = RTE_BE32(0xffffffff);
1474                                         width -= 32;
1475                                 }
1476                                 if (!width)
1477                                         break;
1478                                 ++idx;
1479                         }
1480                         if (data->offset < 64) {
1481                                 info[idx] = (struct field_modify_info){4,
1482                                                 4 * idx,
1483                                                 MLX5_MODI_OUT_SIPV6_95_64};
1484                                 if (width < 32) {
1485                                         mask[idx] =
1486                                                 rte_cpu_to_be_32(0xffffffff >>
1487                                                                  (32 - width));
1488                                         width = 0;
1489                                 } else {
1490                                         mask[idx] = RTE_BE32(0xffffffff);
1491                                         width -= 32;
1492                                 }
1493                                 if (!width)
1494                                         break;
1495                                 ++idx;
1496                         }
1497                         if (data->offset < 96) {
1498                                 info[idx] = (struct field_modify_info){4,
1499                                                 8 * idx,
1500                                                 MLX5_MODI_OUT_SIPV6_63_32};
1501                                 if (width < 32) {
1502                                         mask[idx] =
1503                                                 rte_cpu_to_be_32(0xffffffff >>
1504                                                                  (32 - width));
1505                                         width = 0;
1506                                 } else {
1507                                         mask[idx] = RTE_BE32(0xffffffff);
1508                                         width -= 32;
1509                                 }
1510                                 if (!width)
1511                                         break;
1512                                 ++idx;
1513                         }
1514                         info[idx] = (struct field_modify_info){4, 12 * idx,
1515                                                 MLX5_MODI_OUT_SIPV6_31_0};
1516                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1517                                                      (32 - width));
1518                 } else {
1519                         if (data->offset < 32)
1520                                 info[idx++] = (struct field_modify_info){4, 0,
1521                                                 MLX5_MODI_OUT_SIPV6_127_96};
1522                         if (data->offset < 64)
1523                                 info[idx++] = (struct field_modify_info){4, 0,
1524                                                 MLX5_MODI_OUT_SIPV6_95_64};
1525                         if (data->offset < 96)
1526                                 info[idx++] = (struct field_modify_info){4, 0,
1527                                                 MLX5_MODI_OUT_SIPV6_63_32};
1528                         if (data->offset < 128)
1529                                 info[idx++] = (struct field_modify_info){4, 0,
1530                                                 MLX5_MODI_OUT_SIPV6_31_0};
1531                 }
1532                 break;
1533         case RTE_FLOW_FIELD_IPV6_DST:
1534                 if (mask) {
1535                         if (data->offset < 32) {
1536                                 info[idx] = (struct field_modify_info){4, 0,
1537                                                 MLX5_MODI_OUT_DIPV6_127_96};
1538                                 if (width < 32) {
1539                                         mask[idx] =
1540                                                 rte_cpu_to_be_32(0xffffffff >>
1541                                                                  (32 - width));
1542                                         width = 0;
1543                                 } else {
1544                                         mask[idx] = RTE_BE32(0xffffffff);
1545                                         width -= 32;
1546                                 }
1547                                 if (!width)
1548                                         break;
1549                                 ++idx;
1550                         }
1551                         if (data->offset < 64) {
1552                                 info[idx] = (struct field_modify_info){4,
1553                                                 4 * idx,
1554                                                 MLX5_MODI_OUT_DIPV6_95_64};
1555                                 if (width < 32) {
1556                                         mask[idx] =
1557                                                 rte_cpu_to_be_32(0xffffffff >>
1558                                                                  (32 - width));
1559                                         width = 0;
1560                                 } else {
1561                                         mask[idx] = RTE_BE32(0xffffffff);
1562                                         width -= 32;
1563                                 }
1564                                 if (!width)
1565                                         break;
1566                                 ++idx;
1567                         }
1568                         if (data->offset < 96) {
1569                                 info[idx] = (struct field_modify_info){4,
1570                                                 8 * idx,
1571                                                 MLX5_MODI_OUT_DIPV6_63_32};
1572                                 if (width < 32) {
1573                                         mask[idx] =
1574                                                 rte_cpu_to_be_32(0xffffffff >>
1575                                                                  (32 - width));
1576                                         width = 0;
1577                                 } else {
1578                                         mask[idx] = RTE_BE32(0xffffffff);
1579                                         width -= 32;
1580                                 }
1581                                 if (!width)
1582                                         break;
1583                                 ++idx;
1584                         }
1585                         info[idx] = (struct field_modify_info){4, 12 * idx,
1586                                                 MLX5_MODI_OUT_DIPV6_31_0};
1587                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1588                                                      (32 - width));
1589                 } else {
1590                         if (data->offset < 32)
1591                                 info[idx++] = (struct field_modify_info){4, 0,
1592                                                 MLX5_MODI_OUT_DIPV6_127_96};
1593                         if (data->offset < 64)
1594                                 info[idx++] = (struct field_modify_info){4, 0,
1595                                                 MLX5_MODI_OUT_DIPV6_95_64};
1596                         if (data->offset < 96)
1597                                 info[idx++] = (struct field_modify_info){4, 0,
1598                                                 MLX5_MODI_OUT_DIPV6_63_32};
1599                         if (data->offset < 128)
1600                                 info[idx++] = (struct field_modify_info){4, 0,
1601                                                 MLX5_MODI_OUT_DIPV6_31_0};
1602                 }
1603                 break;
1604         case RTE_FLOW_FIELD_TCP_PORT_SRC:
1605                 info[idx] = (struct field_modify_info){2, 0,
1606                                         MLX5_MODI_OUT_TCP_SPORT};
1607                 if (mask)
1608                         mask[idx] = rte_cpu_to_be_32(0x0000ffff >>
1609                                                      (16 - width));
1610                 break;
1611         case RTE_FLOW_FIELD_TCP_PORT_DST:
1612                 info[idx] = (struct field_modify_info){2, 0,
1613                                         MLX5_MODI_OUT_TCP_DPORT};
1614                 if (mask)
1615                         mask[idx] = rte_cpu_to_be_32(0x0000ffff >>
1616                                                      (16 - width));
1617                 break;
1618         case RTE_FLOW_FIELD_TCP_SEQ_NUM:
1619                 info[idx] = (struct field_modify_info){4, 0,
1620                                         MLX5_MODI_OUT_TCP_SEQ_NUM};
1621                 if (mask)
1622                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1623                                                      (32 - width));
1624                 break;
1625         case RTE_FLOW_FIELD_TCP_ACK_NUM:
1626                 info[idx] = (struct field_modify_info){4, 0,
1627                                         MLX5_MODI_OUT_TCP_ACK_NUM};
1628                 if (mask)
1629                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1630                                                      (32 - width));
1631                 break;
1632         case RTE_FLOW_FIELD_TCP_FLAGS:
1633                 info[idx] = (struct field_modify_info){1, 0,
1634                                         MLX5_MODI_OUT_TCP_FLAGS};
1635                 if (mask)
1636                         mask[idx] = rte_cpu_to_be_32(0x0000003f >>
1637                                                      (6 - width));
1638                 break;
1639         case RTE_FLOW_FIELD_UDP_PORT_SRC:
1640                 info[idx] = (struct field_modify_info){2, 0,
1641                                         MLX5_MODI_OUT_UDP_SPORT};
1642                 if (mask)
1643                         mask[idx] = rte_cpu_to_be_32(0x0000ffff >>
1644                                                      (16 - width));
1645                 break;
1646         case RTE_FLOW_FIELD_UDP_PORT_DST:
1647                 info[idx] = (struct field_modify_info){2, 0,
1648                                         MLX5_MODI_OUT_UDP_DPORT};
1649                 if (mask)
1650                         mask[idx] = rte_cpu_to_be_32(0x0000ffff >>
1651                                                      (16 - width));
1652                 break;
1653         case RTE_FLOW_FIELD_VXLAN_VNI:
1654                 /* not supported yet */
1655                 break;
1656         case RTE_FLOW_FIELD_GENEVE_VNI:
1657                 /* not supported yet*/
1658                 break;
1659         case RTE_FLOW_FIELD_GTP_TEID:
1660                 info[idx] = (struct field_modify_info){4, 0,
1661                                         MLX5_MODI_GTP_TEID};
1662                 if (mask)
1663                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1664                                                      (32 - width));
1665                 break;
1666         case RTE_FLOW_FIELD_TAG:
1667                 {
1668                         int reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG,
1669                                                    data->level, error);
1670                         if (reg < 0)
1671                                 return;
1672                         MLX5_ASSERT(reg != REG_NON);
1673                         MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1674                         info[idx] = (struct field_modify_info){4, 0,
1675                                                 reg_to_field[reg]};
1676                         if (mask)
1677                                 mask[idx] =
1678                                         rte_cpu_to_be_32(0xffffffff >>
1679                                                          (32 - width));
1680                 }
1681                 break;
1682         case RTE_FLOW_FIELD_MARK:
1683                 {
1684                         int reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK,
1685                                                        0, error);
1686                         if (reg < 0)
1687                                 return;
1688                         MLX5_ASSERT(reg != REG_NON);
1689                         MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1690                         info[idx] = (struct field_modify_info){4, 0,
1691                                                 reg_to_field[reg]};
1692                         if (mask)
1693                                 mask[idx] =
1694                                         rte_cpu_to_be_32(0xffffffff >>
1695                                                          (32 - width));
1696                 }
1697                 break;
1698         case RTE_FLOW_FIELD_META:
1699                 {
1700                         int reg = flow_dv_get_metadata_reg(dev, attr, error);
1701                         if (reg < 0)
1702                                 return;
1703                         MLX5_ASSERT(reg != REG_NON);
1704                         MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1705                         info[idx] = (struct field_modify_info){4, 0,
1706                                                 reg_to_field[reg]};
1707                         if (mask)
1708                                 mask[idx] =
1709                                         rte_cpu_to_be_32(0xffffffff >>
1710                                                          (32 - width));
1711                 }
1712                 break;
1713         case RTE_FLOW_FIELD_POINTER:
1714                 for (idx = 0; idx < MLX5_ACT_MAX_MOD_FIELDS; idx++) {
1715                         if (mask[idx]) {
1716                                 memcpy(&value[idx],
1717                                         (void *)(uintptr_t)data->value, 32);
1718                                 value[idx] = rte_cpu_to_be_32(value[idx]);
1719                                 break;
1720                         }
1721                 }
1722                 break;
1723         case RTE_FLOW_FIELD_VALUE:
1724                 for (idx = 0; idx < MLX5_ACT_MAX_MOD_FIELDS; idx++) {
1725                         if (mask[idx]) {
1726                                 value[idx] =
1727                                         rte_cpu_to_be_32((uint32_t)data->value);
1728                                 break;
1729                         }
1730                 }
1731                 break;
1732         default:
1733                 MLX5_ASSERT(false);
1734                 break;
1735         }
1736 }
1737
1738 /**
1739  * Convert modify_field action to DV specification.
1740  *
1741  * @param[in] dev
1742  *   Pointer to the rte_eth_dev structure.
1743  * @param[in,out] resource
1744  *   Pointer to the modify-header resource.
1745  * @param[in] action
1746  *   Pointer to action specification.
1747  * @param[in] attr
1748  *   Attributes of flow that includes this item.
1749  * @param[out] error
1750  *   Pointer to the error structure.
1751  *
1752  * @return
1753  *   0 on success, a negative errno value otherwise and rte_errno is set.
1754  */
1755 static int
1756 flow_dv_convert_action_modify_field
1757                         (struct rte_eth_dev *dev,
1758                          struct mlx5_flow_dv_modify_hdr_resource *resource,
1759                          const struct rte_flow_action *action,
1760                          const struct rte_flow_attr *attr,
1761                          struct rte_flow_error *error)
1762 {
1763         const struct rte_flow_action_modify_field *conf =
1764                 (const struct rte_flow_action_modify_field *)(action->conf);
1765         struct rte_flow_item item;
1766         struct field_modify_info field[MLX5_ACT_MAX_MOD_FIELDS] = {
1767                                                                 {0, 0, 0} };
1768         struct field_modify_info dcopy[MLX5_ACT_MAX_MOD_FIELDS] = {
1769                                                                 {0, 0, 0} };
1770         uint32_t mask[MLX5_ACT_MAX_MOD_FIELDS] = {0, 0, 0, 0, 0};
1771         uint32_t value[MLX5_ACT_MAX_MOD_FIELDS] = {0, 0, 0, 0, 0};
1772         uint32_t type;
1773
1774         if (conf->src.field == RTE_FLOW_FIELD_POINTER ||
1775                 conf->src.field == RTE_FLOW_FIELD_VALUE) {
1776                 type = MLX5_MODIFICATION_TYPE_SET;
1777                 /** For SET fill the destination field (field) first. */
1778                 mlx5_flow_field_id_to_modify_info(&conf->dst, field, mask,
1779                                           value, conf->width, dev, attr, error);
1780                 /** Then copy immediate value from source as per mask. */
1781                 mlx5_flow_field_id_to_modify_info(&conf->src, dcopy, mask,
1782                                           value, conf->width, dev, attr, error);
1783                 item.spec = &value;
1784         } else {
1785                 type = MLX5_MODIFICATION_TYPE_COPY;
1786                 /** For COPY fill the destination field (dcopy) without mask. */
1787                 mlx5_flow_field_id_to_modify_info(&conf->dst, dcopy, NULL,
1788                                           value, conf->width, dev, attr, error);
1789                 /** Then construct the source field (field) with mask. */
1790                 mlx5_flow_field_id_to_modify_info(&conf->src, field, mask,
1791                                           value, conf->width, dev, attr, error);
1792         }
1793         item.mask = &mask;
1794         return flow_dv_convert_modify_action(&item,
1795                         field, dcopy, resource, type, error);
1796 }
1797
1798 /**
1799  * Validate MARK item.
1800  *
1801  * @param[in] dev
1802  *   Pointer to the rte_eth_dev structure.
1803  * @param[in] item
1804  *   Item specification.
1805  * @param[in] attr
1806  *   Attributes of flow that includes this item.
1807  * @param[out] error
1808  *   Pointer to error structure.
1809  *
1810  * @return
1811  *   0 on success, a negative errno value otherwise and rte_errno is set.
1812  */
1813 static int
1814 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1815                            const struct rte_flow_item *item,
1816                            const struct rte_flow_attr *attr __rte_unused,
1817                            struct rte_flow_error *error)
1818 {
1819         struct mlx5_priv *priv = dev->data->dev_private;
1820         struct mlx5_dev_config *config = &priv->config;
1821         const struct rte_flow_item_mark *spec = item->spec;
1822         const struct rte_flow_item_mark *mask = item->mask;
1823         const struct rte_flow_item_mark nic_mask = {
1824                 .id = priv->sh->dv_mark_mask,
1825         };
1826         int ret;
1827
1828         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1829                 return rte_flow_error_set(error, ENOTSUP,
1830                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1831                                           "extended metadata feature"
1832                                           " isn't enabled");
1833         if (!mlx5_flow_ext_mreg_supported(dev))
1834                 return rte_flow_error_set(error, ENOTSUP,
1835                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1836                                           "extended metadata register"
1837                                           " isn't supported");
1838         if (!nic_mask.id)
1839                 return rte_flow_error_set(error, ENOTSUP,
1840                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1841                                           "extended metadata register"
1842                                           " isn't available");
1843         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1844         if (ret < 0)
1845                 return ret;
1846         if (!spec)
1847                 return rte_flow_error_set(error, EINVAL,
1848                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1849                                           item->spec,
1850                                           "data cannot be empty");
1851         if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1852                 return rte_flow_error_set(error, EINVAL,
1853                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1854                                           &spec->id,
1855                                           "mark id exceeds the limit");
1856         if (!mask)
1857                 mask = &nic_mask;
1858         if (!mask->id)
1859                 return rte_flow_error_set(error, EINVAL,
1860                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1861                                         "mask cannot be zero");
1862
1863         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1864                                         (const uint8_t *)&nic_mask,
1865                                         sizeof(struct rte_flow_item_mark),
1866                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1867         if (ret < 0)
1868                 return ret;
1869         return 0;
1870 }
1871
1872 /**
1873  * Validate META item.
1874  *
1875  * @param[in] dev
1876  *   Pointer to the rte_eth_dev structure.
1877  * @param[in] item
1878  *   Item specification.
1879  * @param[in] attr
1880  *   Attributes of flow that includes this item.
1881  * @param[out] error
1882  *   Pointer to error structure.
1883  *
1884  * @return
1885  *   0 on success, a negative errno value otherwise and rte_errno is set.
1886  */
1887 static int
1888 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1889                            const struct rte_flow_item *item,
1890                            const struct rte_flow_attr *attr,
1891                            struct rte_flow_error *error)
1892 {
1893         struct mlx5_priv *priv = dev->data->dev_private;
1894         struct mlx5_dev_config *config = &priv->config;
1895         const struct rte_flow_item_meta *spec = item->spec;
1896         const struct rte_flow_item_meta *mask = item->mask;
1897         struct rte_flow_item_meta nic_mask = {
1898                 .data = UINT32_MAX
1899         };
1900         int reg;
1901         int ret;
1902
1903         if (!spec)
1904                 return rte_flow_error_set(error, EINVAL,
1905                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1906                                           item->spec,
1907                                           "data cannot be empty");
1908         if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1909                 if (!mlx5_flow_ext_mreg_supported(dev))
1910                         return rte_flow_error_set(error, ENOTSUP,
1911                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1912                                           "extended metadata register"
1913                                           " isn't supported");
1914                 reg = flow_dv_get_metadata_reg(dev, attr, error);
1915                 if (reg < 0)
1916                         return reg;
1917                 if (reg == REG_NON)
1918                         return rte_flow_error_set(error, ENOTSUP,
1919                                         RTE_FLOW_ERROR_TYPE_ITEM, item,
1920                                         "unavalable extended metadata register");
1921                 if (reg == REG_B)
1922                         return rte_flow_error_set(error, ENOTSUP,
1923                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1924                                           "match on reg_b "
1925                                           "isn't supported");
1926                 if (reg != REG_A)
1927                         nic_mask.data = priv->sh->dv_meta_mask;
1928         } else {
1929                 if (attr->transfer)
1930                         return rte_flow_error_set(error, ENOTSUP,
1931                                         RTE_FLOW_ERROR_TYPE_ITEM, item,
1932                                         "extended metadata feature "
1933                                         "should be enabled when "
1934                                         "meta item is requested "
1935                                         "with e-switch mode ");
1936                 if (attr->ingress)
1937                         return rte_flow_error_set(error, ENOTSUP,
1938                                         RTE_FLOW_ERROR_TYPE_ITEM, item,
1939                                         "match on metadata for ingress "
1940                                         "is not supported in legacy "
1941                                         "metadata mode");
1942         }
1943         if (!mask)
1944                 mask = &rte_flow_item_meta_mask;
1945         if (!mask->data)
1946                 return rte_flow_error_set(error, EINVAL,
1947                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1948                                         "mask cannot be zero");
1949
1950         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1951                                         (const uint8_t *)&nic_mask,
1952                                         sizeof(struct rte_flow_item_meta),
1953                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1954         return ret;
1955 }
1956
1957 /**
1958  * Validate TAG item.
1959  *
1960  * @param[in] dev
1961  *   Pointer to the rte_eth_dev structure.
1962  * @param[in] item
1963  *   Item specification.
1964  * @param[in] attr
1965  *   Attributes of flow that includes this item.
1966  * @param[out] error
1967  *   Pointer to error structure.
1968  *
1969  * @return
1970  *   0 on success, a negative errno value otherwise and rte_errno is set.
1971  */
1972 static int
1973 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
1974                           const struct rte_flow_item *item,
1975                           const struct rte_flow_attr *attr __rte_unused,
1976                           struct rte_flow_error *error)
1977 {
1978         const struct rte_flow_item_tag *spec = item->spec;
1979         const struct rte_flow_item_tag *mask = item->mask;
1980         const struct rte_flow_item_tag nic_mask = {
1981                 .data = RTE_BE32(UINT32_MAX),
1982                 .index = 0xff,
1983         };
1984         int ret;
1985
1986         if (!mlx5_flow_ext_mreg_supported(dev))
1987                 return rte_flow_error_set(error, ENOTSUP,
1988                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1989                                           "extensive metadata register"
1990                                           " isn't supported");
1991         if (!spec)
1992                 return rte_flow_error_set(error, EINVAL,
1993                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1994                                           item->spec,
1995                                           "data cannot be empty");
1996         if (!mask)
1997                 mask = &rte_flow_item_tag_mask;
1998         if (!mask->data)
1999                 return rte_flow_error_set(error, EINVAL,
2000                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2001                                         "mask cannot be zero");
2002
2003         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2004                                         (const uint8_t *)&nic_mask,
2005                                         sizeof(struct rte_flow_item_tag),
2006                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2007         if (ret < 0)
2008                 return ret;
2009         if (mask->index != 0xff)
2010                 return rte_flow_error_set(error, EINVAL,
2011                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2012                                           "partial mask for tag index"
2013                                           " is not supported");
2014         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
2015         if (ret < 0)
2016                 return ret;
2017         MLX5_ASSERT(ret != REG_NON);
2018         return 0;
2019 }
2020
2021 /**
2022  * Validate vport item.
2023  *
2024  * @param[in] dev
2025  *   Pointer to the rte_eth_dev structure.
2026  * @param[in] item
2027  *   Item specification.
2028  * @param[in] attr
2029  *   Attributes of flow that includes this item.
2030  * @param[in] item_flags
2031  *   Bit-fields that holds the items detected until now.
2032  * @param[out] error
2033  *   Pointer to error structure.
2034  *
2035  * @return
2036  *   0 on success, a negative errno value otherwise and rte_errno is set.
2037  */
2038 static int
2039 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
2040                               const struct rte_flow_item *item,
2041                               const struct rte_flow_attr *attr,
2042                               uint64_t item_flags,
2043                               struct rte_flow_error *error)
2044 {
2045         const struct rte_flow_item_port_id *spec = item->spec;
2046         const struct rte_flow_item_port_id *mask = item->mask;
2047         const struct rte_flow_item_port_id switch_mask = {
2048                         .id = 0xffffffff,
2049         };
2050         struct mlx5_priv *esw_priv;
2051         struct mlx5_priv *dev_priv;
2052         int ret;
2053
2054         if (!attr->transfer)
2055                 return rte_flow_error_set(error, EINVAL,
2056                                           RTE_FLOW_ERROR_TYPE_ITEM,
2057                                           NULL,
2058                                           "match on port id is valid only"
2059                                           " when transfer flag is enabled");
2060         if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
2061                 return rte_flow_error_set(error, ENOTSUP,
2062                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2063                                           "multiple source ports are not"
2064                                           " supported");
2065         if (!mask)
2066                 mask = &switch_mask;
2067         if (mask->id != 0xffffffff)
2068                 return rte_flow_error_set(error, ENOTSUP,
2069                                            RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2070                                            mask,
2071                                            "no support for partial mask on"
2072                                            " \"id\" field");
2073         ret = mlx5_flow_item_acceptable
2074                                 (item, (const uint8_t *)mask,
2075                                  (const uint8_t *)&rte_flow_item_port_id_mask,
2076                                  sizeof(struct rte_flow_item_port_id),
2077                                  MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2078         if (ret)
2079                 return ret;
2080         if (!spec)
2081                 return 0;
2082         esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
2083         if (!esw_priv)
2084                 return rte_flow_error_set(error, rte_errno,
2085                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
2086                                           "failed to obtain E-Switch info for"
2087                                           " port");
2088         dev_priv = mlx5_dev_to_eswitch_info(dev);
2089         if (!dev_priv)
2090                 return rte_flow_error_set(error, rte_errno,
2091                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2092                                           NULL,
2093                                           "failed to obtain E-Switch info");
2094         if (esw_priv->domain_id != dev_priv->domain_id)
2095                 return rte_flow_error_set(error, EINVAL,
2096                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
2097                                           "cannot match on a port from a"
2098                                           " different E-Switch");
2099         return 0;
2100 }
2101
2102 /**
2103  * Validate VLAN item.
2104  *
2105  * @param[in] item
2106  *   Item specification.
2107  * @param[in] item_flags
2108  *   Bit-fields that holds the items detected until now.
2109  * @param[in] dev
2110  *   Ethernet device flow is being created on.
2111  * @param[out] error
2112  *   Pointer to error structure.
2113  *
2114  * @return
2115  *   0 on success, a negative errno value otherwise and rte_errno is set.
2116  */
2117 static int
2118 flow_dv_validate_item_vlan(const struct rte_flow_item *item,
2119                            uint64_t item_flags,
2120                            struct rte_eth_dev *dev,
2121                            struct rte_flow_error *error)
2122 {
2123         const struct rte_flow_item_vlan *mask = item->mask;
2124         const struct rte_flow_item_vlan nic_mask = {
2125                 .tci = RTE_BE16(UINT16_MAX),
2126                 .inner_type = RTE_BE16(UINT16_MAX),
2127                 .has_more_vlan = 1,
2128         };
2129         const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2130         int ret;
2131         const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 |
2132                                         MLX5_FLOW_LAYER_INNER_L4) :
2133                                        (MLX5_FLOW_LAYER_OUTER_L3 |
2134                                         MLX5_FLOW_LAYER_OUTER_L4);
2135         const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
2136                                         MLX5_FLOW_LAYER_OUTER_VLAN;
2137
2138         if (item_flags & vlanm)
2139                 return rte_flow_error_set(error, EINVAL,
2140                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2141                                           "multiple VLAN layers not supported");
2142         else if ((item_flags & l34m) != 0)
2143                 return rte_flow_error_set(error, EINVAL,
2144                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2145                                           "VLAN cannot follow L3/L4 layer");
2146         if (!mask)
2147                 mask = &rte_flow_item_vlan_mask;
2148         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2149                                         (const uint8_t *)&nic_mask,
2150                                         sizeof(struct rte_flow_item_vlan),
2151                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2152         if (ret)
2153                 return ret;
2154         if (!tunnel && mask->tci != RTE_BE16(0x0fff)) {
2155                 struct mlx5_priv *priv = dev->data->dev_private;
2156
2157                 if (priv->vmwa_context) {
2158                         /*
2159                          * Non-NULL context means we have a virtual machine
2160                          * and SR-IOV enabled, we have to create VLAN interface
2161                          * to make hypervisor to setup E-Switch vport
2162                          * context correctly. We avoid creating the multiple
2163                          * VLAN interfaces, so we cannot support VLAN tag mask.
2164                          */
2165                         return rte_flow_error_set(error, EINVAL,
2166                                                   RTE_FLOW_ERROR_TYPE_ITEM,
2167                                                   item,
2168                                                   "VLAN tag mask is not"
2169                                                   " supported in virtual"
2170                                                   " environment");
2171                 }
2172         }
2173         return 0;
2174 }
2175
2176 /*
2177  * GTP flags are contained in 1 byte of the format:
2178  * -------------------------------------------
2179  * | bit   | 0 - 2   | 3  | 4   | 5 | 6 | 7  |
2180  * |-----------------------------------------|
2181  * | value | Version | PT | Res | E | S | PN |
2182  * -------------------------------------------
2183  *
2184  * Matching is supported only for GTP flags E, S, PN.
2185  */
2186 #define MLX5_GTP_FLAGS_MASK     0x07
2187
2188 /**
2189  * Validate GTP item.
2190  *
2191  * @param[in] dev
2192  *   Pointer to the rte_eth_dev structure.
2193  * @param[in] item
2194  *   Item specification.
2195  * @param[in] item_flags
2196  *   Bit-fields that holds the items detected until now.
2197  * @param[out] error
2198  *   Pointer to error structure.
2199  *
2200  * @return
2201  *   0 on success, a negative errno value otherwise and rte_errno is set.
2202  */
2203 static int
2204 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
2205                           const struct rte_flow_item *item,
2206                           uint64_t item_flags,
2207                           struct rte_flow_error *error)
2208 {
2209         struct mlx5_priv *priv = dev->data->dev_private;
2210         const struct rte_flow_item_gtp *spec = item->spec;
2211         const struct rte_flow_item_gtp *mask = item->mask;
2212         const struct rte_flow_item_gtp nic_mask = {
2213                 .v_pt_rsv_flags = MLX5_GTP_FLAGS_MASK,
2214                 .msg_type = 0xff,
2215                 .teid = RTE_BE32(0xffffffff),
2216         };
2217
2218         if (!priv->config.hca_attr.tunnel_stateless_gtp)
2219                 return rte_flow_error_set(error, ENOTSUP,
2220                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2221                                           "GTP support is not enabled");
2222         if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
2223                 return rte_flow_error_set(error, ENOTSUP,
2224                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2225                                           "multiple tunnel layers not"
2226                                           " supported");
2227         if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
2228                 return rte_flow_error_set(error, EINVAL,
2229                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2230                                           "no outer UDP layer found");
2231         if (!mask)
2232                 mask = &rte_flow_item_gtp_mask;
2233         if (spec && spec->v_pt_rsv_flags & ~MLX5_GTP_FLAGS_MASK)
2234                 return rte_flow_error_set(error, ENOTSUP,
2235                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2236                                           "Match is supported for GTP"
2237                                           " flags only");
2238         return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2239                                          (const uint8_t *)&nic_mask,
2240                                          sizeof(struct rte_flow_item_gtp),
2241                                          MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2242 }
2243
2244 /**
2245  * Validate GTP PSC item.
2246  *
2247  * @param[in] item
2248  *   Item specification.
2249  * @param[in] last_item
2250  *   Previous validated item in the pattern items.
2251  * @param[in] gtp_item
2252  *   Previous GTP item specification.
2253  * @param[in] attr
2254  *   Pointer to flow attributes.
2255  * @param[out] error
2256  *   Pointer to error structure.
2257  *
2258  * @return
2259  *   0 on success, a negative errno value otherwise and rte_errno is set.
2260  */
2261 static int
2262 flow_dv_validate_item_gtp_psc(const struct rte_flow_item *item,
2263                               uint64_t last_item,
2264                               const struct rte_flow_item *gtp_item,
2265                               const struct rte_flow_attr *attr,
2266                               struct rte_flow_error *error)
2267 {
2268         const struct rte_flow_item_gtp *gtp_spec;
2269         const struct rte_flow_item_gtp *gtp_mask;
2270         const struct rte_flow_item_gtp_psc *spec;
2271         const struct rte_flow_item_gtp_psc *mask;
2272         const struct rte_flow_item_gtp_psc nic_mask = {
2273                 .pdu_type = 0xFF,
2274                 .qfi = 0xFF,
2275         };
2276
2277         if (!gtp_item || !(last_item & MLX5_FLOW_LAYER_GTP))
2278                 return rte_flow_error_set
2279                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2280                          "GTP PSC item must be preceded with GTP item");
2281         gtp_spec = gtp_item->spec;
2282         gtp_mask = gtp_item->mask ? gtp_item->mask : &rte_flow_item_gtp_mask;
2283         /* GTP spec and E flag is requested to match zero. */
2284         if (gtp_spec &&
2285                 (gtp_mask->v_pt_rsv_flags &
2286                 ~gtp_spec->v_pt_rsv_flags & MLX5_GTP_EXT_HEADER_FLAG))
2287                 return rte_flow_error_set
2288                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2289                          "GTP E flag must be 1 to match GTP PSC");
2290         /* Check the flow is not created in group zero. */
2291         if (!attr->transfer && !attr->group)
2292                 return rte_flow_error_set
2293                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2294                          "GTP PSC is not supported for group 0");
2295         /* GTP spec is here and E flag is requested to match zero. */
2296         if (!item->spec)
2297                 return 0;
2298         spec = item->spec;
2299         mask = item->mask ? item->mask : &rte_flow_item_gtp_psc_mask;
2300         if (spec->pdu_type > MLX5_GTP_EXT_MAX_PDU_TYPE)
2301                 return rte_flow_error_set
2302                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2303                          "PDU type should be smaller than 16");
2304         return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2305                                          (const uint8_t *)&nic_mask,
2306                                          sizeof(struct rte_flow_item_gtp_psc),
2307                                          MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2308 }
2309
2310 /**
2311  * Validate IPV4 item.
2312  * Use existing validation function mlx5_flow_validate_item_ipv4(), and
2313  * add specific validation of fragment_offset field,
2314  *
2315  * @param[in] item
2316  *   Item specification.
2317  * @param[in] item_flags
2318  *   Bit-fields that holds the items detected until now.
2319  * @param[out] error
2320  *   Pointer to error structure.
2321  *
2322  * @return
2323  *   0 on success, a negative errno value otherwise and rte_errno is set.
2324  */
2325 static int
2326 flow_dv_validate_item_ipv4(const struct rte_flow_item *item,
2327                            uint64_t item_flags,
2328                            uint64_t last_item,
2329                            uint16_t ether_type,
2330                            struct rte_flow_error *error)
2331 {
2332         int ret;
2333         const struct rte_flow_item_ipv4 *spec = item->spec;
2334         const struct rte_flow_item_ipv4 *last = item->last;
2335         const struct rte_flow_item_ipv4 *mask = item->mask;
2336         rte_be16_t fragment_offset_spec = 0;
2337         rte_be16_t fragment_offset_last = 0;
2338         const struct rte_flow_item_ipv4 nic_ipv4_mask = {
2339                 .hdr = {
2340                         .src_addr = RTE_BE32(0xffffffff),
2341                         .dst_addr = RTE_BE32(0xffffffff),
2342                         .type_of_service = 0xff,
2343                         .fragment_offset = RTE_BE16(0xffff),
2344                         .next_proto_id = 0xff,
2345                         .time_to_live = 0xff,
2346                 },
2347         };
2348
2349         ret = mlx5_flow_validate_item_ipv4(item, item_flags, last_item,
2350                                            ether_type, &nic_ipv4_mask,
2351                                            MLX5_ITEM_RANGE_ACCEPTED, error);
2352         if (ret < 0)
2353                 return ret;
2354         if (spec && mask)
2355                 fragment_offset_spec = spec->hdr.fragment_offset &
2356                                        mask->hdr.fragment_offset;
2357         if (!fragment_offset_spec)
2358                 return 0;
2359         /*
2360          * spec and mask are valid, enforce using full mask to make sure the
2361          * complete value is used correctly.
2362          */
2363         if ((mask->hdr.fragment_offset & RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2364                         != RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2365                 return rte_flow_error_set(error, EINVAL,
2366                                           RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2367                                           item, "must use full mask for"
2368                                           " fragment_offset");
2369         /*
2370          * Match on fragment_offset 0x2000 means MF is 1 and frag-offset is 0,
2371          * indicating this is 1st fragment of fragmented packet.
2372          * This is not yet supported in MLX5, return appropriate error message.
2373          */
2374         if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG))
2375                 return rte_flow_error_set(error, ENOTSUP,
2376                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2377                                           "match on first fragment not "
2378                                           "supported");
2379         if (fragment_offset_spec && !last)
2380                 return rte_flow_error_set(error, ENOTSUP,
2381                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2382                                           "specified value not supported");
2383         /* spec and last are valid, validate the specified range. */
2384         fragment_offset_last = last->hdr.fragment_offset &
2385                                mask->hdr.fragment_offset;
2386         /*
2387          * Match on fragment_offset spec 0x2001 and last 0x3fff
2388          * means MF is 1 and frag-offset is > 0.
2389          * This packet is fragment 2nd and onward, excluding last.
2390          * This is not yet supported in MLX5, return appropriate
2391          * error message.
2392          */
2393         if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG + 1) &&
2394             fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2395                 return rte_flow_error_set(error, ENOTSUP,
2396                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2397                                           last, "match on following "
2398                                           "fragments not supported");
2399         /*
2400          * Match on fragment_offset spec 0x0001 and last 0x1fff
2401          * means MF is 0 and frag-offset is > 0.
2402          * This packet is last fragment of fragmented packet.
2403          * This is not yet supported in MLX5, return appropriate
2404          * error message.
2405          */
2406         if (fragment_offset_spec == RTE_BE16(1) &&
2407             fragment_offset_last == RTE_BE16(RTE_IPV4_HDR_OFFSET_MASK))
2408                 return rte_flow_error_set(error, ENOTSUP,
2409                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2410                                           last, "match on last "
2411                                           "fragment not supported");
2412         /*
2413          * Match on fragment_offset spec 0x0001 and last 0x3fff
2414          * means MF and/or frag-offset is not 0.
2415          * This is a fragmented packet.
2416          * Other range values are invalid and rejected.
2417          */
2418         if (!(fragment_offset_spec == RTE_BE16(1) &&
2419               fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK)))
2420                 return rte_flow_error_set(error, ENOTSUP,
2421                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2422                                           "specified range not supported");
2423         return 0;
2424 }
2425
2426 /**
2427  * Validate IPV6 fragment extension item.
2428  *
2429  * @param[in] item
2430  *   Item specification.
2431  * @param[in] item_flags
2432  *   Bit-fields that holds the items detected until now.
2433  * @param[out] error
2434  *   Pointer to error structure.
2435  *
2436  * @return
2437  *   0 on success, a negative errno value otherwise and rte_errno is set.
2438  */
2439 static int
2440 flow_dv_validate_item_ipv6_frag_ext(const struct rte_flow_item *item,
2441                                     uint64_t item_flags,
2442                                     struct rte_flow_error *error)
2443 {
2444         const struct rte_flow_item_ipv6_frag_ext *spec = item->spec;
2445         const struct rte_flow_item_ipv6_frag_ext *last = item->last;
2446         const struct rte_flow_item_ipv6_frag_ext *mask = item->mask;
2447         rte_be16_t frag_data_spec = 0;
2448         rte_be16_t frag_data_last = 0;
2449         const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2450         const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 :
2451                                       MLX5_FLOW_LAYER_OUTER_L4;
2452         int ret = 0;
2453         struct rte_flow_item_ipv6_frag_ext nic_mask = {
2454                 .hdr = {
2455                         .next_header = 0xff,
2456                         .frag_data = RTE_BE16(0xffff),
2457                 },
2458         };
2459
2460         if (item_flags & l4m)
2461                 return rte_flow_error_set(error, EINVAL,
2462                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2463                                           "ipv6 fragment extension item cannot "
2464                                           "follow L4 item.");
2465         if ((tunnel && !(item_flags & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
2466             (!tunnel && !(item_flags & MLX5_FLOW_LAYER_OUTER_L3_IPV6)))
2467                 return rte_flow_error_set(error, EINVAL,
2468                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2469                                           "ipv6 fragment extension item must "
2470                                           "follow ipv6 item");
2471         if (spec && mask)
2472                 frag_data_spec = spec->hdr.frag_data & mask->hdr.frag_data;
2473         if (!frag_data_spec)
2474                 return 0;
2475         /*
2476          * spec and mask are valid, enforce using full mask to make sure the
2477          * complete value is used correctly.
2478          */
2479         if ((mask->hdr.frag_data & RTE_BE16(RTE_IPV6_FRAG_USED_MASK)) !=
2480                                 RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2481                 return rte_flow_error_set(error, EINVAL,
2482                                           RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2483                                           item, "must use full mask for"
2484                                           " frag_data");
2485         /*
2486          * Match on frag_data 0x00001 means M is 1 and frag-offset is 0.
2487          * This is 1st fragment of fragmented packet.
2488          */
2489         if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_MF_MASK))
2490                 return rte_flow_error_set(error, ENOTSUP,
2491                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2492                                           "match on first fragment not "
2493                                           "supported");
2494         if (frag_data_spec && !last)
2495                 return rte_flow_error_set(error, EINVAL,
2496                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2497                                           "specified value not supported");
2498         ret = mlx5_flow_item_acceptable
2499                                 (item, (const uint8_t *)mask,
2500                                  (const uint8_t *)&nic_mask,
2501                                  sizeof(struct rte_flow_item_ipv6_frag_ext),
2502                                  MLX5_ITEM_RANGE_ACCEPTED, error);
2503         if (ret)
2504                 return ret;
2505         /* spec and last are valid, validate the specified range. */
2506         frag_data_last = last->hdr.frag_data & mask->hdr.frag_data;
2507         /*
2508          * Match on frag_data spec 0x0009 and last 0xfff9
2509          * means M is 1 and frag-offset is > 0.
2510          * This packet is fragment 2nd and onward, excluding last.
2511          * This is not yet supported in MLX5, return appropriate
2512          * error message.
2513          */
2514         if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN |
2515                                        RTE_IPV6_EHDR_MF_MASK) &&
2516             frag_data_last == RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2517                 return rte_flow_error_set(error, ENOTSUP,
2518                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2519                                           last, "match on following "
2520                                           "fragments not supported");
2521         /*
2522          * Match on frag_data spec 0x0008 and last 0xfff8
2523          * means M is 0 and frag-offset is > 0.
2524          * This packet is last fragment of fragmented packet.
2525          * This is not yet supported in MLX5, return appropriate
2526          * error message.
2527          */
2528         if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN) &&
2529             frag_data_last == RTE_BE16(RTE_IPV6_EHDR_FO_MASK))
2530                 return rte_flow_error_set(error, ENOTSUP,
2531                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2532                                           last, "match on last "
2533                                           "fragment not supported");
2534         /* Other range values are invalid and rejected. */
2535         return rte_flow_error_set(error, EINVAL,
2536                                   RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2537                                   "specified range not supported");
2538 }
2539
2540 /**
2541  * Validate the pop VLAN action.
2542  *
2543  * @param[in] dev
2544  *   Pointer to the rte_eth_dev structure.
2545  * @param[in] action_flags
2546  *   Holds the actions detected until now.
2547  * @param[in] action
2548  *   Pointer to the pop vlan action.
2549  * @param[in] item_flags
2550  *   The items found in this flow rule.
2551  * @param[in] attr
2552  *   Pointer to flow attributes.
2553  * @param[out] error
2554  *   Pointer to error structure.
2555  *
2556  * @return
2557  *   0 on success, a negative errno value otherwise and rte_errno is set.
2558  */
2559 static int
2560 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
2561                                  uint64_t action_flags,
2562                                  const struct rte_flow_action *action,
2563                                  uint64_t item_flags,
2564                                  const struct rte_flow_attr *attr,
2565                                  struct rte_flow_error *error)
2566 {
2567         const struct mlx5_priv *priv = dev->data->dev_private;
2568
2569         (void)action;
2570         (void)attr;
2571         if (!priv->sh->pop_vlan_action)
2572                 return rte_flow_error_set(error, ENOTSUP,
2573                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2574                                           NULL,
2575                                           "pop vlan action is not supported");
2576         if (attr->egress)
2577                 return rte_flow_error_set(error, ENOTSUP,
2578                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2579                                           NULL,
2580                                           "pop vlan action not supported for "
2581                                           "egress");
2582         if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
2583                 return rte_flow_error_set(error, ENOTSUP,
2584                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2585                                           "no support for multiple VLAN "
2586                                           "actions");
2587         /* Pop VLAN with preceding Decap requires inner header with VLAN. */
2588         if ((action_flags & MLX5_FLOW_ACTION_DECAP) &&
2589             !(item_flags & MLX5_FLOW_LAYER_INNER_VLAN))
2590                 return rte_flow_error_set(error, ENOTSUP,
2591                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2592                                           NULL,
2593                                           "cannot pop vlan after decap without "
2594                                           "match on inner vlan in the flow");
2595         /* Pop VLAN without preceding Decap requires outer header with VLAN. */
2596         if (!(action_flags & MLX5_FLOW_ACTION_DECAP) &&
2597             !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2598                 return rte_flow_error_set(error, ENOTSUP,
2599                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2600                                           NULL,
2601                                           "cannot pop vlan without a "
2602                                           "match on (outer) vlan in the flow");
2603         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2604                 return rte_flow_error_set(error, EINVAL,
2605                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2606                                           "wrong action order, port_id should "
2607                                           "be after pop VLAN action");
2608         if (!attr->transfer && priv->representor)
2609                 return rte_flow_error_set(error, ENOTSUP,
2610                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2611                                           "pop vlan action for VF representor "
2612                                           "not supported on NIC table");
2613         return 0;
2614 }
2615
2616 /**
2617  * Get VLAN default info from vlan match info.
2618  *
2619  * @param[in] items
2620  *   the list of item specifications.
2621  * @param[out] vlan
2622  *   pointer VLAN info to fill to.
2623  *
2624  * @return
2625  *   0 on success, a negative errno value otherwise and rte_errno is set.
2626  */
2627 static void
2628 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
2629                                   struct rte_vlan_hdr *vlan)
2630 {
2631         const struct rte_flow_item_vlan nic_mask = {
2632                 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
2633                                 MLX5DV_FLOW_VLAN_VID_MASK),
2634                 .inner_type = RTE_BE16(0xffff),
2635         };
2636
2637         if (items == NULL)
2638                 return;
2639         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2640                 int type = items->type;
2641
2642                 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
2643                     type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
2644                         break;
2645         }
2646         if (items->type != RTE_FLOW_ITEM_TYPE_END) {
2647                 const struct rte_flow_item_vlan *vlan_m = items->mask;
2648                 const struct rte_flow_item_vlan *vlan_v = items->spec;
2649
2650                 /* If VLAN item in pattern doesn't contain data, return here. */
2651                 if (!vlan_v)
2652                         return;
2653                 if (!vlan_m)
2654                         vlan_m = &nic_mask;
2655                 /* Only full match values are accepted */
2656                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
2657                      MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
2658                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
2659                         vlan->vlan_tci |=
2660                                 rte_be_to_cpu_16(vlan_v->tci &
2661                                                  MLX5DV_FLOW_VLAN_PCP_MASK_BE);
2662                 }
2663                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
2664                      MLX5DV_FLOW_VLAN_VID_MASK_BE) {
2665                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
2666                         vlan->vlan_tci |=
2667                                 rte_be_to_cpu_16(vlan_v->tci &
2668                                                  MLX5DV_FLOW_VLAN_VID_MASK_BE);
2669                 }
2670                 if (vlan_m->inner_type == nic_mask.inner_type)
2671                         vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
2672                                                            vlan_m->inner_type);
2673         }
2674 }
2675
2676 /**
2677  * Validate the push VLAN action.
2678  *
2679  * @param[in] dev
2680  *   Pointer to the rte_eth_dev structure.
2681  * @param[in] action_flags
2682  *   Holds the actions detected until now.
2683  * @param[in] item_flags
2684  *   The items found in this flow rule.
2685  * @param[in] action
2686  *   Pointer to the action structure.
2687  * @param[in] attr
2688  *   Pointer to flow attributes
2689  * @param[out] error
2690  *   Pointer to error structure.
2691  *
2692  * @return
2693  *   0 on success, a negative errno value otherwise and rte_errno is set.
2694  */
2695 static int
2696 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
2697                                   uint64_t action_flags,
2698                                   const struct rte_flow_item_vlan *vlan_m,
2699                                   const struct rte_flow_action *action,
2700                                   const struct rte_flow_attr *attr,
2701                                   struct rte_flow_error *error)
2702 {
2703         const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
2704         const struct mlx5_priv *priv = dev->data->dev_private;
2705
2706         if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
2707             push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
2708                 return rte_flow_error_set(error, EINVAL,
2709                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2710                                           "invalid vlan ethertype");
2711         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2712                 return rte_flow_error_set(error, EINVAL,
2713                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2714                                           "wrong action order, port_id should "
2715                                           "be after push VLAN");
2716         if (!attr->transfer && priv->representor)
2717                 return rte_flow_error_set(error, ENOTSUP,
2718                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2719                                           "push vlan action for VF representor "
2720                                           "not supported on NIC table");
2721         if (vlan_m &&
2722             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
2723             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
2724                 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
2725             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
2726             !(mlx5_flow_find_action
2727                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
2728                 return rte_flow_error_set(error, EINVAL,
2729                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2730                                           "not full match mask on VLAN PCP and "
2731                                           "there is no of_set_vlan_pcp action, "
2732                                           "push VLAN action cannot figure out "
2733                                           "PCP value");
2734         if (vlan_m &&
2735             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
2736             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
2737                 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
2738             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
2739             !(mlx5_flow_find_action
2740                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
2741                 return rte_flow_error_set(error, EINVAL,
2742                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2743                                           "not full match mask on VLAN VID and "
2744                                           "there is no of_set_vlan_vid action, "
2745                                           "push VLAN action cannot figure out "
2746                                           "VID value");
2747         (void)attr;
2748         return 0;
2749 }
2750
2751 /**
2752  * Validate the set VLAN PCP.
2753  *
2754  * @param[in] action_flags
2755  *   Holds the actions detected until now.
2756  * @param[in] actions
2757  *   Pointer to the list of actions remaining in the flow rule.
2758  * @param[out] error
2759  *   Pointer to error structure.
2760  *
2761  * @return
2762  *   0 on success, a negative errno value otherwise and rte_errno is set.
2763  */
2764 static int
2765 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
2766                                      const struct rte_flow_action actions[],
2767                                      struct rte_flow_error *error)
2768 {
2769         const struct rte_flow_action *action = actions;
2770         const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
2771
2772         if (conf->vlan_pcp > 7)
2773                 return rte_flow_error_set(error, EINVAL,
2774                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2775                                           "VLAN PCP value is too big");
2776         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
2777                 return rte_flow_error_set(error, ENOTSUP,
2778                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2779                                           "set VLAN PCP action must follow "
2780                                           "the push VLAN action");
2781         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
2782                 return rte_flow_error_set(error, ENOTSUP,
2783                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2784                                           "Multiple VLAN PCP modification are "
2785                                           "not supported");
2786         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2787                 return rte_flow_error_set(error, EINVAL,
2788                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2789                                           "wrong action order, port_id should "
2790                                           "be after set VLAN PCP");
2791         return 0;
2792 }
2793
2794 /**
2795  * Validate the set VLAN VID.
2796  *
2797  * @param[in] item_flags
2798  *   Holds the items detected in this rule.
2799  * @param[in] action_flags
2800  *   Holds the actions detected until now.
2801  * @param[in] actions
2802  *   Pointer to the list of actions remaining in the flow rule.
2803  * @param[out] error
2804  *   Pointer to error structure.
2805  *
2806  * @return
2807  *   0 on success, a negative errno value otherwise and rte_errno is set.
2808  */
2809 static int
2810 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
2811                                      uint64_t action_flags,
2812                                      const struct rte_flow_action actions[],
2813                                      struct rte_flow_error *error)
2814 {
2815         const struct rte_flow_action *action = actions;
2816         const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
2817
2818         if (rte_be_to_cpu_16(conf->vlan_vid) > 0xFFE)
2819                 return rte_flow_error_set(error, EINVAL,
2820                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2821                                           "VLAN VID value is too big");
2822         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
2823             !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2824                 return rte_flow_error_set(error, ENOTSUP,
2825                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2826                                           "set VLAN VID action must follow push"
2827                                           " VLAN action or match on VLAN item");
2828         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
2829                 return rte_flow_error_set(error, ENOTSUP,
2830                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2831                                           "Multiple VLAN VID modifications are "
2832                                           "not supported");
2833         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2834                 return rte_flow_error_set(error, EINVAL,
2835                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2836                                           "wrong action order, port_id should "
2837                                           "be after set VLAN VID");
2838         return 0;
2839 }
2840
2841 /*
2842  * Validate the FLAG action.
2843  *
2844  * @param[in] dev
2845  *   Pointer to the rte_eth_dev structure.
2846  * @param[in] action_flags
2847  *   Holds the actions detected until now.
2848  * @param[in] attr
2849  *   Pointer to flow attributes
2850  * @param[out] error
2851  *   Pointer to error structure.
2852  *
2853  * @return
2854  *   0 on success, a negative errno value otherwise and rte_errno is set.
2855  */
2856 static int
2857 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
2858                              uint64_t action_flags,
2859                              const struct rte_flow_attr *attr,
2860                              struct rte_flow_error *error)
2861 {
2862         struct mlx5_priv *priv = dev->data->dev_private;
2863         struct mlx5_dev_config *config = &priv->config;
2864         int ret;
2865
2866         /* Fall back if no extended metadata register support. */
2867         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2868                 return mlx5_flow_validate_action_flag(action_flags, attr,
2869                                                       error);
2870         /* Extensive metadata mode requires registers. */
2871         if (!mlx5_flow_ext_mreg_supported(dev))
2872                 return rte_flow_error_set(error, ENOTSUP,
2873                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2874                                           "no metadata registers "
2875                                           "to support flag action");
2876         if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
2877                 return rte_flow_error_set(error, ENOTSUP,
2878                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2879                                           "extended metadata register"
2880                                           " isn't available");
2881         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2882         if (ret < 0)
2883                 return ret;
2884         MLX5_ASSERT(ret > 0);
2885         if (action_flags & MLX5_FLOW_ACTION_MARK)
2886                 return rte_flow_error_set(error, EINVAL,
2887                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2888                                           "can't mark and flag in same flow");
2889         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2890                 return rte_flow_error_set(error, EINVAL,
2891                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2892                                           "can't have 2 flag"
2893                                           " actions in same flow");
2894         return 0;
2895 }
2896
2897 /**
2898  * Validate MARK action.
2899  *
2900  * @param[in] dev
2901  *   Pointer to the rte_eth_dev structure.
2902  * @param[in] action
2903  *   Pointer to action.
2904  * @param[in] action_flags
2905  *   Holds the actions detected until now.
2906  * @param[in] attr
2907  *   Pointer to flow attributes
2908  * @param[out] error
2909  *   Pointer to error structure.
2910  *
2911  * @return
2912  *   0 on success, a negative errno value otherwise and rte_errno is set.
2913  */
2914 static int
2915 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
2916                              const struct rte_flow_action *action,
2917                              uint64_t action_flags,
2918                              const struct rte_flow_attr *attr,
2919                              struct rte_flow_error *error)
2920 {
2921         struct mlx5_priv *priv = dev->data->dev_private;
2922         struct mlx5_dev_config *config = &priv->config;
2923         const struct rte_flow_action_mark *mark = action->conf;
2924         int ret;
2925
2926         if (is_tunnel_offload_active(dev))
2927                 return rte_flow_error_set(error, ENOTSUP,
2928                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2929                                           "no mark action "
2930                                           "if tunnel offload active");
2931         /* Fall back if no extended metadata register support. */
2932         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2933                 return mlx5_flow_validate_action_mark(action, action_flags,
2934                                                       attr, error);
2935         /* Extensive metadata mode requires registers. */
2936         if (!mlx5_flow_ext_mreg_supported(dev))
2937                 return rte_flow_error_set(error, ENOTSUP,
2938                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2939                                           "no metadata registers "
2940                                           "to support mark action");
2941         if (!priv->sh->dv_mark_mask)
2942                 return rte_flow_error_set(error, ENOTSUP,
2943                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2944                                           "extended metadata register"
2945                                           " isn't available");
2946         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2947         if (ret < 0)
2948                 return ret;
2949         MLX5_ASSERT(ret > 0);
2950         if (!mark)
2951                 return rte_flow_error_set(error, EINVAL,
2952                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2953                                           "configuration cannot be null");
2954         if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
2955                 return rte_flow_error_set(error, EINVAL,
2956                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2957                                           &mark->id,
2958                                           "mark id exceeds the limit");
2959         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2960                 return rte_flow_error_set(error, EINVAL,
2961                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2962                                           "can't flag and mark in same flow");
2963         if (action_flags & MLX5_FLOW_ACTION_MARK)
2964                 return rte_flow_error_set(error, EINVAL,
2965                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2966                                           "can't have 2 mark actions in same"
2967                                           " flow");
2968         return 0;
2969 }
2970
2971 /**
2972  * Validate SET_META action.
2973  *
2974  * @param[in] dev
2975  *   Pointer to the rte_eth_dev structure.
2976  * @param[in] action
2977  *   Pointer to the action structure.
2978  * @param[in] action_flags
2979  *   Holds the actions detected until now.
2980  * @param[in] attr
2981  *   Pointer to flow attributes
2982  * @param[out] error
2983  *   Pointer to error structure.
2984  *
2985  * @return
2986  *   0 on success, a negative errno value otherwise and rte_errno is set.
2987  */
2988 static int
2989 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
2990                                  const struct rte_flow_action *action,
2991                                  uint64_t action_flags __rte_unused,
2992                                  const struct rte_flow_attr *attr,
2993                                  struct rte_flow_error *error)
2994 {
2995         const struct rte_flow_action_set_meta *conf;
2996         uint32_t nic_mask = UINT32_MAX;
2997         int reg;
2998
2999         if (!mlx5_flow_ext_mreg_supported(dev))
3000                 return rte_flow_error_set(error, ENOTSUP,
3001                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3002                                           "extended metadata register"
3003                                           " isn't supported");
3004         reg = flow_dv_get_metadata_reg(dev, attr, error);
3005         if (reg < 0)
3006                 return reg;
3007         if (reg == REG_NON)
3008                 return rte_flow_error_set(error, ENOTSUP,
3009                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3010                                           "unavalable extended metadata register");
3011         if (reg != REG_A && reg != REG_B) {
3012                 struct mlx5_priv *priv = dev->data->dev_private;
3013
3014                 nic_mask = priv->sh->dv_meta_mask;
3015         }
3016         if (!(action->conf))
3017                 return rte_flow_error_set(error, EINVAL,
3018                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3019                                           "configuration cannot be null");
3020         conf = (const struct rte_flow_action_set_meta *)action->conf;
3021         if (!conf->mask)
3022                 return rte_flow_error_set(error, EINVAL,
3023                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3024                                           "zero mask doesn't have any effect");
3025         if (conf->mask & ~nic_mask)
3026                 return rte_flow_error_set(error, EINVAL,
3027                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3028                                           "meta data must be within reg C0");
3029         return 0;
3030 }
3031
3032 /**
3033  * Validate SET_TAG action.
3034  *
3035  * @param[in] dev
3036  *   Pointer to the rte_eth_dev structure.
3037  * @param[in] action
3038  *   Pointer to the action structure.
3039  * @param[in] action_flags
3040  *   Holds the actions detected until now.
3041  * @param[in] attr
3042  *   Pointer to flow attributes
3043  * @param[out] error
3044  *   Pointer to error structure.
3045  *
3046  * @return
3047  *   0 on success, a negative errno value otherwise and rte_errno is set.
3048  */
3049 static int
3050 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
3051                                 const struct rte_flow_action *action,
3052                                 uint64_t action_flags,
3053                                 const struct rte_flow_attr *attr,
3054                                 struct rte_flow_error *error)
3055 {
3056         const struct rte_flow_action_set_tag *conf;
3057         const uint64_t terminal_action_flags =
3058                 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
3059                 MLX5_FLOW_ACTION_RSS;
3060         int ret;
3061
3062         if (!mlx5_flow_ext_mreg_supported(dev))
3063                 return rte_flow_error_set(error, ENOTSUP,
3064                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3065                                           "extensive metadata register"
3066                                           " isn't supported");
3067         if (!(action->conf))
3068                 return rte_flow_error_set(error, EINVAL,
3069                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3070                                           "configuration cannot be null");
3071         conf = (const struct rte_flow_action_set_tag *)action->conf;
3072         if (!conf->mask)
3073                 return rte_flow_error_set(error, EINVAL,
3074                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3075                                           "zero mask doesn't have any effect");
3076         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
3077         if (ret < 0)
3078                 return ret;
3079         if (!attr->transfer && attr->ingress &&
3080             (action_flags & terminal_action_flags))
3081                 return rte_flow_error_set(error, EINVAL,
3082                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3083                                           "set_tag has no effect"
3084                                           " with terminal actions");
3085         return 0;
3086 }
3087
3088 /**
3089  * Validate count action.
3090  *
3091  * @param[in] dev
3092  *   Pointer to rte_eth_dev structure.
3093  * @param[in] action
3094  *   Pointer to the action structure.
3095  * @param[in] action_flags
3096  *   Holds the actions detected until now.
3097  * @param[out] error
3098  *   Pointer to error structure.
3099  *
3100  * @return
3101  *   0 on success, a negative errno value otherwise and rte_errno is set.
3102  */
3103 static int
3104 flow_dv_validate_action_count(struct rte_eth_dev *dev,
3105                               const struct rte_flow_action *action,
3106                               uint64_t action_flags,
3107                               struct rte_flow_error *error)
3108 {
3109         struct mlx5_priv *priv = dev->data->dev_private;
3110         const struct rte_flow_action_count *count;
3111
3112         if (!priv->config.devx)
3113                 goto notsup_err;
3114         if (action_flags & MLX5_FLOW_ACTION_COUNT)
3115                 return rte_flow_error_set(error, EINVAL,
3116                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3117                                           "duplicate count actions set");
3118         count = (const struct rte_flow_action_count *)action->conf;
3119         if (count && count->shared && (action_flags & MLX5_FLOW_ACTION_AGE) &&
3120             !priv->sh->flow_hit_aso_en)
3121                 return rte_flow_error_set(error, EINVAL,
3122                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3123                                           "old age and shared count combination is not supported");
3124 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
3125         return 0;
3126 #endif
3127 notsup_err:
3128         return rte_flow_error_set
3129                       (error, ENOTSUP,
3130                        RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3131                        NULL,
3132                        "count action not supported");
3133 }
3134
3135 /**
3136  * Validate the L2 encap action.
3137  *
3138  * @param[in] dev
3139  *   Pointer to the rte_eth_dev structure.
3140  * @param[in] action_flags
3141  *   Holds the actions detected until now.
3142  * @param[in] action
3143  *   Pointer to the action structure.
3144  * @param[in] attr
3145  *   Pointer to flow attributes.
3146  * @param[out] error
3147  *   Pointer to error structure.
3148  *
3149  * @return
3150  *   0 on success, a negative errno value otherwise and rte_errno is set.
3151  */
3152 static int
3153 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
3154                                  uint64_t action_flags,
3155                                  const struct rte_flow_action *action,
3156                                  const struct rte_flow_attr *attr,
3157                                  struct rte_flow_error *error)
3158 {
3159         const struct mlx5_priv *priv = dev->data->dev_private;
3160
3161         if (!(action->conf))
3162                 return rte_flow_error_set(error, EINVAL,
3163                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3164                                           "configuration cannot be null");
3165         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3166                 return rte_flow_error_set(error, EINVAL,
3167                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3168                                           "can only have a single encap action "
3169                                           "in a flow");
3170         if (!attr->transfer && priv->representor)
3171                 return rte_flow_error_set(error, ENOTSUP,
3172                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3173                                           "encap action for VF representor "
3174                                           "not supported on NIC table");
3175         return 0;
3176 }
3177
3178 /**
3179  * Validate a decap action.
3180  *
3181  * @param[in] dev
3182  *   Pointer to the rte_eth_dev structure.
3183  * @param[in] action_flags
3184  *   Holds the actions detected until now.
3185  * @param[in] action
3186  *   Pointer to the action structure.
3187  * @param[in] item_flags
3188  *   Holds the items detected.
3189  * @param[in] attr
3190  *   Pointer to flow attributes
3191  * @param[out] error
3192  *   Pointer to error structure.
3193  *
3194  * @return
3195  *   0 on success, a negative errno value otherwise and rte_errno is set.
3196  */
3197 static int
3198 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
3199                               uint64_t action_flags,
3200                               const struct rte_flow_action *action,
3201                               const uint64_t item_flags,
3202                               const struct rte_flow_attr *attr,
3203                               struct rte_flow_error *error)
3204 {
3205         const struct mlx5_priv *priv = dev->data->dev_private;
3206
3207         if (priv->config.hca_attr.scatter_fcs_w_decap_disable &&
3208             !priv->config.decap_en)
3209                 return rte_flow_error_set(error, ENOTSUP,
3210                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3211                                           "decap is not enabled");
3212         if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
3213                 return rte_flow_error_set(error, ENOTSUP,
3214                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3215                                           action_flags &
3216                                           MLX5_FLOW_ACTION_DECAP ? "can only "
3217                                           "have a single decap action" : "decap "
3218                                           "after encap is not supported");
3219         if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
3220                 return rte_flow_error_set(error, EINVAL,
3221                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3222                                           "can't have decap action after"
3223                                           " modify action");
3224         if (attr->egress)
3225                 return rte_flow_error_set(error, ENOTSUP,
3226                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
3227                                           NULL,
3228                                           "decap action not supported for "
3229                                           "egress");
3230         if (!attr->transfer && priv->representor)
3231                 return rte_flow_error_set(error, ENOTSUP,
3232                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3233                                           "decap action for VF representor "
3234                                           "not supported on NIC table");
3235         if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_DECAP &&
3236             !(item_flags & MLX5_FLOW_LAYER_VXLAN))
3237                 return rte_flow_error_set(error, ENOTSUP,
3238                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3239                                 "VXLAN item should be present for VXLAN decap");
3240         return 0;
3241 }
3242
3243 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
3244
3245 /**
3246  * Validate the raw encap and decap actions.
3247  *
3248  * @param[in] dev
3249  *   Pointer to the rte_eth_dev structure.
3250  * @param[in] decap
3251  *   Pointer to the decap action.
3252  * @param[in] encap
3253  *   Pointer to the encap action.
3254  * @param[in] attr
3255  *   Pointer to flow attributes
3256  * @param[in/out] action_flags
3257  *   Holds the actions detected until now.
3258  * @param[out] actions_n
3259  *   pointer to the number of actions counter.
3260  * @param[in] action
3261  *   Pointer to the action structure.
3262  * @param[in] item_flags
3263  *   Holds the items detected.
3264  * @param[out] error
3265  *   Pointer to error structure.
3266  *
3267  * @return
3268  *   0 on success, a negative errno value otherwise and rte_errno is set.
3269  */
3270 static int
3271 flow_dv_validate_action_raw_encap_decap
3272         (struct rte_eth_dev *dev,
3273          const struct rte_flow_action_raw_decap *decap,
3274          const struct rte_flow_action_raw_encap *encap,
3275          const struct rte_flow_attr *attr, uint64_t *action_flags,
3276          int *actions_n, const struct rte_flow_action *action,
3277          uint64_t item_flags, struct rte_flow_error *error)
3278 {
3279         const struct mlx5_priv *priv = dev->data->dev_private;
3280         int ret;
3281
3282         if (encap && (!encap->size || !encap->data))
3283                 return rte_flow_error_set(error, EINVAL,
3284                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3285                                           "raw encap data cannot be empty");
3286         if (decap && encap) {
3287                 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
3288                     encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
3289                         /* L3 encap. */
3290                         decap = NULL;
3291                 else if (encap->size <=
3292                            MLX5_ENCAPSULATION_DECISION_SIZE &&
3293                            decap->size >
3294                            MLX5_ENCAPSULATION_DECISION_SIZE)
3295                         /* L3 decap. */
3296                         encap = NULL;
3297                 else if (encap->size >
3298                            MLX5_ENCAPSULATION_DECISION_SIZE &&
3299                            decap->size >
3300                            MLX5_ENCAPSULATION_DECISION_SIZE)
3301                         /* 2 L2 actions: encap and decap. */
3302                         ;
3303                 else
3304                         return rte_flow_error_set(error,
3305                                 ENOTSUP,
3306                                 RTE_FLOW_ERROR_TYPE_ACTION,
3307                                 NULL, "unsupported too small "
3308                                 "raw decap and too small raw "
3309                                 "encap combination");
3310         }
3311         if (decap) {
3312                 ret = flow_dv_validate_action_decap(dev, *action_flags, action,
3313                                                     item_flags, attr, error);
3314                 if (ret < 0)
3315                         return ret;
3316                 *action_flags |= MLX5_FLOW_ACTION_DECAP;
3317                 ++(*actions_n);
3318         }
3319         if (encap) {
3320                 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
3321                         return rte_flow_error_set(error, ENOTSUP,
3322                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3323                                                   NULL,
3324                                                   "small raw encap size");
3325                 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
3326                         return rte_flow_error_set(error, EINVAL,
3327                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3328                                                   NULL,
3329                                                   "more than one encap action");
3330                 if (!attr->transfer && priv->representor)
3331                         return rte_flow_error_set
3332                                         (error, ENOTSUP,
3333                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3334                                          "encap action for VF representor "
3335                                          "not supported on NIC table");
3336                 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
3337                 ++(*actions_n);
3338         }
3339         return 0;
3340 }
3341
3342 /**
3343  * Match encap_decap resource.
3344  *
3345  * @param list
3346  *   Pointer to the hash list.
3347  * @param entry
3348  *   Pointer to exist resource entry object.
3349  * @param key
3350  *   Key of the new entry.
3351  * @param ctx_cb
3352  *   Pointer to new encap_decap resource.
3353  *
3354  * @return
3355  *   0 on matching, none-zero otherwise.
3356  */
3357 int
3358 flow_dv_encap_decap_match_cb(struct mlx5_hlist *list __rte_unused,
3359                              struct mlx5_hlist_entry *entry,
3360                              uint64_t key __rte_unused, void *cb_ctx)
3361 {
3362         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3363         struct mlx5_flow_dv_encap_decap_resource *resource = ctx->data;
3364         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
3365
3366         cache_resource = container_of(entry,
3367                                       struct mlx5_flow_dv_encap_decap_resource,
3368                                       entry);
3369         if (resource->reformat_type == cache_resource->reformat_type &&
3370             resource->ft_type == cache_resource->ft_type &&
3371             resource->flags == cache_resource->flags &&
3372             resource->size == cache_resource->size &&
3373             !memcmp((const void *)resource->buf,
3374                     (const void *)cache_resource->buf,
3375                     resource->size))
3376                 return 0;
3377         return -1;
3378 }
3379
3380 /**
3381  * Allocate encap_decap resource.
3382  *
3383  * @param list
3384  *   Pointer to the hash list.
3385  * @param entry
3386  *   Pointer to exist resource entry object.
3387  * @param ctx_cb
3388  *   Pointer to new encap_decap resource.
3389  *
3390  * @return
3391  *   0 on matching, none-zero otherwise.
3392  */
3393 struct mlx5_hlist_entry *
3394 flow_dv_encap_decap_create_cb(struct mlx5_hlist *list,
3395                               uint64_t key __rte_unused,
3396                               void *cb_ctx)
3397 {
3398         struct mlx5_dev_ctx_shared *sh = list->ctx;
3399         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3400         struct mlx5dv_dr_domain *domain;
3401         struct mlx5_flow_dv_encap_decap_resource *resource = ctx->data;
3402         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
3403         uint32_t idx;
3404         int ret;
3405
3406         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3407                 domain = sh->fdb_domain;
3408         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3409                 domain = sh->rx_domain;
3410         else
3411                 domain = sh->tx_domain;
3412         /* Register new encap/decap resource. */
3413         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
3414                                        &idx);
3415         if (!cache_resource) {
3416                 rte_flow_error_set(ctx->error, ENOMEM,
3417                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3418                                    "cannot allocate resource memory");
3419                 return NULL;
3420         }
3421         *cache_resource = *resource;
3422         cache_resource->idx = idx;
3423         ret = mlx5_flow_os_create_flow_action_packet_reformat
3424                                         (sh->ctx, domain, cache_resource,
3425                                          &cache_resource->action);
3426         if (ret) {
3427                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);
3428                 rte_flow_error_set(ctx->error, ENOMEM,
3429                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3430                                    NULL, "cannot create action");
3431                 return NULL;
3432         }
3433
3434         return &cache_resource->entry;
3435 }
3436
3437 /**
3438  * Find existing encap/decap resource or create and register a new one.
3439  *
3440  * @param[in, out] dev
3441  *   Pointer to rte_eth_dev structure.
3442  * @param[in, out] resource
3443  *   Pointer to encap/decap resource.
3444  * @parm[in, out] dev_flow
3445  *   Pointer to the dev_flow.
3446  * @param[out] error
3447  *   pointer to error structure.
3448  *
3449  * @return
3450  *   0 on success otherwise -errno and errno is set.
3451  */
3452 static int
3453 flow_dv_encap_decap_resource_register
3454                         (struct rte_eth_dev *dev,
3455                          struct mlx5_flow_dv_encap_decap_resource *resource,
3456                          struct mlx5_flow *dev_flow,
3457                          struct rte_flow_error *error)
3458 {
3459         struct mlx5_priv *priv = dev->data->dev_private;
3460         struct mlx5_dev_ctx_shared *sh = priv->sh;
3461         struct mlx5_hlist_entry *entry;
3462         union {
3463                 struct {
3464                         uint32_t ft_type:8;
3465                         uint32_t refmt_type:8;
3466                         /*
3467                          * Header reformat actions can be shared between
3468                          * non-root tables. One bit to indicate non-root
3469                          * table or not.
3470                          */
3471                         uint32_t is_root:1;
3472                         uint32_t reserve:15;
3473                 };
3474                 uint32_t v32;
3475         } encap_decap_key = {
3476                 {
3477                         .ft_type = resource->ft_type,
3478                         .refmt_type = resource->reformat_type,
3479                         .is_root = !!dev_flow->dv.group,
3480                         .reserve = 0,
3481                 }
3482         };
3483         struct mlx5_flow_cb_ctx ctx = {
3484                 .error = error,
3485                 .data = resource,
3486         };
3487         uint64_t key64;
3488
3489         resource->flags = dev_flow->dv.group ? 0 : 1;
3490         key64 =  __rte_raw_cksum(&encap_decap_key.v32,
3491                                  sizeof(encap_decap_key.v32), 0);
3492         if (resource->reformat_type !=
3493             MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2 &&
3494             resource->size)
3495                 key64 = __rte_raw_cksum(resource->buf, resource->size, key64);
3496         entry = mlx5_hlist_register(sh->encaps_decaps, key64, &ctx);
3497         if (!entry)
3498                 return -rte_errno;
3499         resource = container_of(entry, typeof(*resource), entry);
3500         dev_flow->dv.encap_decap = resource;
3501         dev_flow->handle->dvh.rix_encap_decap = resource->idx;
3502         return 0;
3503 }
3504
3505 /**
3506  * Find existing table jump resource or create and register a new one.
3507  *
3508  * @param[in, out] dev
3509  *   Pointer to rte_eth_dev structure.
3510  * @param[in, out] tbl
3511  *   Pointer to flow table resource.
3512  * @parm[in, out] dev_flow
3513  *   Pointer to the dev_flow.
3514  * @param[out] error
3515  *   pointer to error structure.
3516  *
3517  * @return
3518  *   0 on success otherwise -errno and errno is set.
3519  */
3520 static int
3521 flow_dv_jump_tbl_resource_register
3522                         (struct rte_eth_dev *dev __rte_unused,
3523                          struct mlx5_flow_tbl_resource *tbl,
3524                          struct mlx5_flow *dev_flow,
3525                          struct rte_flow_error *error __rte_unused)
3526 {
3527         struct mlx5_flow_tbl_data_entry *tbl_data =
3528                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
3529
3530         MLX5_ASSERT(tbl);
3531         MLX5_ASSERT(tbl_data->jump.action);
3532         dev_flow->handle->rix_jump = tbl_data->idx;
3533         dev_flow->dv.jump = &tbl_data->jump;
3534         return 0;
3535 }
3536
3537 int
3538 flow_dv_port_id_match_cb(struct mlx5_cache_list *list __rte_unused,
3539                          struct mlx5_cache_entry *entry, void *cb_ctx)
3540 {
3541         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3542         struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3543         struct mlx5_flow_dv_port_id_action_resource *res =
3544                         container_of(entry, typeof(*res), entry);
3545
3546         return ref->port_id != res->port_id;
3547 }
3548
3549 struct mlx5_cache_entry *
3550 flow_dv_port_id_create_cb(struct mlx5_cache_list *list,
3551                           struct mlx5_cache_entry *entry __rte_unused,
3552                           void *cb_ctx)
3553 {
3554         struct mlx5_dev_ctx_shared *sh = list->ctx;
3555         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3556         struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3557         struct mlx5_flow_dv_port_id_action_resource *cache;
3558         uint32_t idx;
3559         int ret;
3560
3561         /* Register new port id action resource. */
3562         cache = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID], &idx);
3563         if (!cache) {
3564                 rte_flow_error_set(ctx->error, ENOMEM,
3565                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3566                                    "cannot allocate port_id action cache memory");
3567                 return NULL;
3568         }
3569         *cache = *ref;
3570         ret = mlx5_flow_os_create_flow_action_dest_port(sh->fdb_domain,
3571                                                         ref->port_id,
3572                                                         &cache->action);
3573         if (ret) {
3574                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], idx);
3575                 rte_flow_error_set(ctx->error, ENOMEM,
3576                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3577                                    "cannot create action");
3578                 return NULL;
3579         }
3580         cache->idx = idx;
3581         return &cache->entry;
3582 }
3583
3584 /**
3585  * Find existing table port ID resource or create and register a new one.
3586  *
3587  * @param[in, out] dev
3588  *   Pointer to rte_eth_dev structure.
3589  * @param[in, out] resource
3590  *   Pointer to port ID action resource.
3591  * @parm[in, out] dev_flow
3592  *   Pointer to the dev_flow.
3593  * @param[out] error
3594  *   pointer to error structure.
3595  *
3596  * @return
3597  *   0 on success otherwise -errno and errno is set.
3598  */
3599 static int
3600 flow_dv_port_id_action_resource_register
3601                         (struct rte_eth_dev *dev,
3602                          struct mlx5_flow_dv_port_id_action_resource *resource,
3603                          struct mlx5_flow *dev_flow,
3604                          struct rte_flow_error *error)
3605 {
3606         struct mlx5_priv *priv = dev->data->dev_private;
3607         struct mlx5_cache_entry *entry;
3608         struct mlx5_flow_dv_port_id_action_resource *cache;
3609         struct mlx5_flow_cb_ctx ctx = {
3610                 .error = error,
3611                 .data = resource,
3612         };
3613
3614         entry = mlx5_cache_register(&priv->sh->port_id_action_list, &ctx);
3615         if (!entry)
3616                 return -rte_errno;
3617         cache = container_of(entry, typeof(*cache), entry);
3618         dev_flow->dv.port_id_action = cache;
3619         dev_flow->handle->rix_port_id_action = cache->idx;
3620         return 0;
3621 }
3622
3623 int
3624 flow_dv_push_vlan_match_cb(struct mlx5_cache_list *list __rte_unused,
3625                          struct mlx5_cache_entry *entry, void *cb_ctx)
3626 {
3627         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3628         struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3629         struct mlx5_flow_dv_push_vlan_action_resource *res =
3630                         container_of(entry, typeof(*res), entry);
3631
3632         return ref->vlan_tag != res->vlan_tag || ref->ft_type != res->ft_type;
3633 }
3634
3635 struct mlx5_cache_entry *
3636 flow_dv_push_vlan_create_cb(struct mlx5_cache_list *list,
3637                           struct mlx5_cache_entry *entry __rte_unused,
3638                           void *cb_ctx)
3639 {
3640         struct mlx5_dev_ctx_shared *sh = list->ctx;
3641         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3642         struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3643         struct mlx5_flow_dv_push_vlan_action_resource *cache;
3644         struct mlx5dv_dr_domain *domain;
3645         uint32_t idx;
3646         int ret;
3647
3648         /* Register new port id action resource. */
3649         cache = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN], &idx);
3650         if (!cache) {
3651                 rte_flow_error_set(ctx->error, ENOMEM,
3652                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3653                                    "cannot allocate push_vlan action cache memory");
3654                 return NULL;
3655         }
3656         *cache = *ref;
3657         if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3658                 domain = sh->fdb_domain;
3659         else if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3660                 domain = sh->rx_domain;
3661         else
3662                 domain = sh->tx_domain;
3663         ret = mlx5_flow_os_create_flow_action_push_vlan(domain, ref->vlan_tag,
3664                                                         &cache->action);
3665         if (ret) {
3666                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
3667                 rte_flow_error_set(ctx->error, ENOMEM,
3668                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3669                                    "cannot create push vlan action");
3670                 return NULL;
3671         }
3672         cache->idx = idx;
3673         return &cache->entry;
3674 }
3675
3676 /**
3677  * Find existing push vlan resource or create and register a new one.
3678  *
3679  * @param [in, out] dev
3680  *   Pointer to rte_eth_dev structure.
3681  * @param[in, out] resource
3682  *   Pointer to port ID action resource.
3683  * @parm[in, out] dev_flow
3684  *   Pointer to the dev_flow.
3685  * @param[out] error
3686  *   pointer to error structure.
3687  *
3688  * @return
3689  *   0 on success otherwise -errno and errno is set.
3690  */
3691 static int
3692 flow_dv_push_vlan_action_resource_register
3693                        (struct rte_eth_dev *dev,
3694                         struct mlx5_flow_dv_push_vlan_action_resource *resource,
3695                         struct mlx5_flow *dev_flow,
3696                         struct rte_flow_error *error)
3697 {
3698         struct mlx5_priv *priv = dev->data->dev_private;
3699         struct mlx5_flow_dv_push_vlan_action_resource *cache;
3700         struct mlx5_cache_entry *entry;
3701         struct mlx5_flow_cb_ctx ctx = {
3702                 .error = error,
3703                 .data = resource,
3704         };
3705
3706         entry = mlx5_cache_register(&priv->sh->push_vlan_action_list, &ctx);
3707         if (!entry)
3708                 return -rte_errno;
3709         cache = container_of(entry, typeof(*cache), entry);
3710
3711         dev_flow->handle->dvh.rix_push_vlan = cache->idx;
3712         dev_flow->dv.push_vlan_res = cache;
3713         return 0;
3714 }
3715
3716 /**
3717  * Get the size of specific rte_flow_item_type hdr size
3718  *
3719  * @param[in] item_type
3720  *   Tested rte_flow_item_type.
3721  *
3722  * @return
3723  *   sizeof struct item_type, 0 if void or irrelevant.
3724  */
3725 static size_t
3726 flow_dv_get_item_hdr_len(const enum rte_flow_item_type item_type)
3727 {
3728         size_t retval;
3729
3730         switch (item_type) {
3731         case RTE_FLOW_ITEM_TYPE_ETH:
3732                 retval = sizeof(struct rte_ether_hdr);
3733                 break;
3734         case RTE_FLOW_ITEM_TYPE_VLAN:
3735                 retval = sizeof(struct rte_vlan_hdr);
3736                 break;
3737         case RTE_FLOW_ITEM_TYPE_IPV4:
3738                 retval = sizeof(struct rte_ipv4_hdr);
3739                 break;
3740         case RTE_FLOW_ITEM_TYPE_IPV6:
3741                 retval = sizeof(struct rte_ipv6_hdr);
3742                 break;
3743         case RTE_FLOW_ITEM_TYPE_UDP:
3744                 retval = sizeof(struct rte_udp_hdr);
3745                 break;
3746         case RTE_FLOW_ITEM_TYPE_TCP:
3747                 retval = sizeof(struct rte_tcp_hdr);
3748                 break;
3749         case RTE_FLOW_ITEM_TYPE_VXLAN:
3750         case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3751                 retval = sizeof(struct rte_vxlan_hdr);
3752                 break;
3753         case RTE_FLOW_ITEM_TYPE_GRE:
3754         case RTE_FLOW_ITEM_TYPE_NVGRE:
3755                 retval = sizeof(struct rte_gre_hdr);
3756                 break;
3757         case RTE_FLOW_ITEM_TYPE_MPLS:
3758                 retval = sizeof(struct rte_mpls_hdr);
3759                 break;
3760         case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
3761         default:
3762                 retval = 0;
3763                 break;
3764         }
3765         return retval;
3766 }
3767
3768 #define MLX5_ENCAP_IPV4_VERSION         0x40
3769 #define MLX5_ENCAP_IPV4_IHL_MIN         0x05
3770 #define MLX5_ENCAP_IPV4_TTL_DEF         0x40
3771 #define MLX5_ENCAP_IPV6_VTC_FLOW        0x60000000
3772 #define MLX5_ENCAP_IPV6_HOP_LIMIT       0xff
3773 #define MLX5_ENCAP_VXLAN_FLAGS          0x08000000
3774 #define MLX5_ENCAP_VXLAN_GPE_FLAGS      0x04
3775
3776 /**
3777  * Convert the encap action data from list of rte_flow_item to raw buffer
3778  *
3779  * @param[in] items
3780  *   Pointer to rte_flow_item objects list.
3781  * @param[out] buf
3782  *   Pointer to the output buffer.
3783  * @param[out] size
3784  *   Pointer to the output buffer size.
3785  * @param[out] error
3786  *   Pointer to the error structure.
3787  *
3788  * @return
3789  *   0 on success, a negative errno value otherwise and rte_errno is set.
3790  */
3791 static int
3792 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
3793                            size_t *size, struct rte_flow_error *error)
3794 {
3795         struct rte_ether_hdr *eth = NULL;
3796         struct rte_vlan_hdr *vlan = NULL;
3797         struct rte_ipv4_hdr *ipv4 = NULL;
3798         struct rte_ipv6_hdr *ipv6 = NULL;
3799         struct rte_udp_hdr *udp = NULL;
3800         struct rte_vxlan_hdr *vxlan = NULL;
3801         struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
3802         struct rte_gre_hdr *gre = NULL;
3803         size_t len;
3804         size_t temp_size = 0;
3805
3806         if (!items)
3807                 return rte_flow_error_set(error, EINVAL,
3808                                           RTE_FLOW_ERROR_TYPE_ACTION,
3809                                           NULL, "invalid empty data");
3810         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
3811                 len = flow_dv_get_item_hdr_len(items->type);
3812                 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
3813                         return rte_flow_error_set(error, EINVAL,
3814                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3815                                                   (void *)items->type,
3816                                                   "items total size is too big"
3817                                                   " for encap action");
3818                 rte_memcpy((void *)&buf[temp_size], items->spec, len);
3819                 switch (items->type) {
3820                 case RTE_FLOW_ITEM_TYPE_ETH:
3821                         eth = (struct rte_ether_hdr *)&buf[temp_size];
3822                         break;
3823                 case RTE_FLOW_ITEM_TYPE_VLAN:
3824                         vlan = (struct rte_vlan_hdr *)&buf[temp_size];
3825                         if (!eth)
3826                                 return rte_flow_error_set(error, EINVAL,
3827                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3828                                                 (void *)items->type,
3829                                                 "eth header not found");
3830                         if (!eth->ether_type)
3831                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
3832                         break;
3833                 case RTE_FLOW_ITEM_TYPE_IPV4:
3834                         ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
3835                         if (!vlan && !eth)
3836                                 return rte_flow_error_set(error, EINVAL,
3837                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3838                                                 (void *)items->type,
3839                                                 "neither eth nor vlan"
3840                                                 " header found");
3841                         if (vlan && !vlan->eth_proto)
3842                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3843                         else if (eth && !eth->ether_type)
3844                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3845                         if (!ipv4->version_ihl)
3846                                 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
3847                                                     MLX5_ENCAP_IPV4_IHL_MIN;
3848                         if (!ipv4->time_to_live)
3849                                 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
3850                         break;
3851                 case RTE_FLOW_ITEM_TYPE_IPV6:
3852                         ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
3853                         if (!vlan && !eth)
3854                                 return rte_flow_error_set(error, EINVAL,
3855                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3856                                                 (void *)items->type,
3857                                                 "neither eth nor vlan"
3858                                                 " header found");
3859                         if (vlan && !vlan->eth_proto)
3860                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3861                         else if (eth && !eth->ether_type)
3862                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3863                         if (!ipv6->vtc_flow)
3864                                 ipv6->vtc_flow =
3865                                         RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
3866                         if (!ipv6->hop_limits)
3867                                 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
3868                         break;
3869                 case RTE_FLOW_ITEM_TYPE_UDP:
3870                         udp = (struct rte_udp_hdr *)&buf[temp_size];
3871                         if (!ipv4 && !ipv6)
3872                                 return rte_flow_error_set(error, EINVAL,
3873                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3874                                                 (void *)items->type,
3875                                                 "ip header not found");
3876                         if (ipv4 && !ipv4->next_proto_id)
3877                                 ipv4->next_proto_id = IPPROTO_UDP;
3878                         else if (ipv6 && !ipv6->proto)
3879                                 ipv6->proto = IPPROTO_UDP;
3880                         break;
3881                 case RTE_FLOW_ITEM_TYPE_VXLAN:
3882                         vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
3883                         if (!udp)
3884                                 return rte_flow_error_set(error, EINVAL,
3885                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3886                                                 (void *)items->type,
3887                                                 "udp header not found");
3888                         if (!udp->dst_port)
3889                                 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
3890                         if (!vxlan->vx_flags)
3891                                 vxlan->vx_flags =
3892                                         RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
3893                         break;
3894                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3895                         vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
3896                         if (!udp)
3897                                 return rte_flow_error_set(error, EINVAL,
3898                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3899                                                 (void *)items->type,
3900                                                 "udp header not found");
3901                         if (!vxlan_gpe->proto)
3902                                 return rte_flow_error_set(error, EINVAL,
3903                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3904                                                 (void *)items->type,
3905                                                 "next protocol not found");
3906                         if (!udp->dst_port)
3907                                 udp->dst_port =
3908                                         RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
3909                         if (!vxlan_gpe->vx_flags)
3910                                 vxlan_gpe->vx_flags =
3911                                                 MLX5_ENCAP_VXLAN_GPE_FLAGS;
3912                         break;
3913                 case RTE_FLOW_ITEM_TYPE_GRE:
3914                 case RTE_FLOW_ITEM_TYPE_NVGRE:
3915                         gre = (struct rte_gre_hdr *)&buf[temp_size];
3916                         if (!gre->proto)
3917                                 return rte_flow_error_set(error, EINVAL,
3918                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3919                                                 (void *)items->type,
3920                                                 "next protocol not found");
3921                         if (!ipv4 && !ipv6)
3922                                 return rte_flow_error_set(error, EINVAL,
3923                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3924                                                 (void *)items->type,
3925                                                 "ip header not found");
3926                         if (ipv4 && !ipv4->next_proto_id)
3927                                 ipv4->next_proto_id = IPPROTO_GRE;
3928                         else if (ipv6 && !ipv6->proto)
3929                                 ipv6->proto = IPPROTO_GRE;
3930                         break;
3931                 case RTE_FLOW_ITEM_TYPE_VOID:
3932                         break;
3933                 default:
3934                         return rte_flow_error_set(error, EINVAL,
3935                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3936                                                   (void *)items->type,
3937                                                   "unsupported item type");
3938                         break;
3939                 }
3940                 temp_size += len;
3941         }
3942         *size = temp_size;
3943         return 0;
3944 }
3945
3946 static int
3947 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
3948 {
3949         struct rte_ether_hdr *eth = NULL;
3950         struct rte_vlan_hdr *vlan = NULL;
3951         struct rte_ipv6_hdr *ipv6 = NULL;
3952         struct rte_udp_hdr *udp = NULL;
3953         char *next_hdr;
3954         uint16_t proto;
3955
3956         eth = (struct rte_ether_hdr *)data;
3957         next_hdr = (char *)(eth + 1);
3958         proto = RTE_BE16(eth->ether_type);
3959
3960         /* VLAN skipping */
3961         while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
3962                 vlan = (struct rte_vlan_hdr *)next_hdr;
3963                 proto = RTE_BE16(vlan->eth_proto);
3964                 next_hdr += sizeof(struct rte_vlan_hdr);
3965         }
3966
3967         /* HW calculates IPv4 csum. no need to proceed */
3968         if (proto == RTE_ETHER_TYPE_IPV4)
3969                 return 0;
3970
3971         /* non IPv4/IPv6 header. not supported */
3972         if (proto != RTE_ETHER_TYPE_IPV6) {
3973                 return rte_flow_error_set(error, ENOTSUP,
3974                                           RTE_FLOW_ERROR_TYPE_ACTION,
3975                                           NULL, "Cannot offload non IPv4/IPv6");
3976         }
3977
3978         ipv6 = (struct rte_ipv6_hdr *)next_hdr;
3979
3980         /* ignore non UDP */
3981         if (ipv6->proto != IPPROTO_UDP)
3982                 return 0;
3983
3984         udp = (struct rte_udp_hdr *)(ipv6 + 1);
3985         udp->dgram_cksum = 0;
3986
3987         return 0;
3988 }
3989
3990 /**
3991  * Convert L2 encap action to DV specification.
3992  *
3993  * @param[in] dev
3994  *   Pointer to rte_eth_dev structure.
3995  * @param[in] action
3996  *   Pointer to action structure.
3997  * @param[in, out] dev_flow
3998  *   Pointer to the mlx5_flow.
3999  * @param[in] transfer
4000  *   Mark if the flow is E-Switch flow.
4001  * @param[out] error
4002  *   Pointer to the error structure.
4003  *
4004  * @return
4005  *   0 on success, a negative errno value otherwise and rte_errno is set.
4006  */
4007 static int
4008 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
4009                                const struct rte_flow_action *action,
4010                                struct mlx5_flow *dev_flow,
4011                                uint8_t transfer,
4012                                struct rte_flow_error *error)
4013 {
4014         const struct rte_flow_item *encap_data;
4015         const struct rte_flow_action_raw_encap *raw_encap_data;
4016         struct mlx5_flow_dv_encap_decap_resource res = {
4017                 .reformat_type =
4018                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
4019                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
4020                                       MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
4021         };
4022
4023         if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
4024                 raw_encap_data =
4025                         (const struct rte_flow_action_raw_encap *)action->conf;
4026                 res.size = raw_encap_data->size;
4027                 memcpy(res.buf, raw_encap_data->data, res.size);
4028         } else {
4029                 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
4030                         encap_data =
4031                                 ((const struct rte_flow_action_vxlan_encap *)
4032                                                 action->conf)->definition;
4033                 else
4034                         encap_data =
4035                                 ((const struct rte_flow_action_nvgre_encap *)
4036                                                 action->conf)->definition;
4037                 if (flow_dv_convert_encap_data(encap_data, res.buf,
4038                                                &res.size, error))
4039                         return -rte_errno;
4040         }
4041         if (flow_dv_zero_encap_udp_csum(res.buf, error))
4042                 return -rte_errno;
4043         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4044                 return rte_flow_error_set(error, EINVAL,
4045                                           RTE_FLOW_ERROR_TYPE_ACTION,
4046                                           NULL, "can't create L2 encap action");
4047         return 0;
4048 }
4049
4050 /**
4051  * Convert L2 decap action to DV specification.
4052  *
4053  * @param[in] dev
4054  *   Pointer to rte_eth_dev structure.
4055  * @param[in, out] dev_flow
4056  *   Pointer to the mlx5_flow.
4057  * @param[in] transfer
4058  *   Mark if the flow is E-Switch flow.
4059  * @param[out] error
4060  *   Pointer to the error structure.
4061  *
4062  * @return
4063  *   0 on success, a negative errno value otherwise and rte_errno is set.
4064  */
4065 static int
4066 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
4067                                struct mlx5_flow *dev_flow,
4068                                uint8_t transfer,
4069                                struct rte_flow_error *error)
4070 {
4071         struct mlx5_flow_dv_encap_decap_resource res = {
4072                 .size = 0,
4073                 .reformat_type =
4074                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
4075                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
4076                                       MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
4077         };
4078
4079         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4080                 return rte_flow_error_set(error, EINVAL,
4081                                           RTE_FLOW_ERROR_TYPE_ACTION,
4082                                           NULL, "can't create L2 decap action");
4083         return 0;
4084 }
4085
4086 /**
4087  * Convert raw decap/encap (L3 tunnel) action to DV specification.
4088  *
4089  * @param[in] dev
4090  *   Pointer to rte_eth_dev structure.
4091  * @param[in] action
4092  *   Pointer to action structure.
4093  * @param[in, out] dev_flow
4094  *   Pointer to the mlx5_flow.
4095  * @param[in] attr
4096  *   Pointer to the flow attributes.
4097  * @param[out] error
4098  *   Pointer to the error structure.
4099  *
4100  * @return
4101  *   0 on success, a negative errno value otherwise and rte_errno is set.
4102  */
4103 static int
4104 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
4105                                 const struct rte_flow_action *action,
4106                                 struct mlx5_flow *dev_flow,
4107                                 const struct rte_flow_attr *attr,
4108                                 struct rte_flow_error *error)
4109 {
4110         const struct rte_flow_action_raw_encap *encap_data;
4111         struct mlx5_flow_dv_encap_decap_resource res;
4112
4113         memset(&res, 0, sizeof(res));
4114         encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
4115         res.size = encap_data->size;
4116         memcpy(res.buf, encap_data->data, res.size);
4117         res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
4118                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
4119                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
4120         if (attr->transfer)
4121                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
4122         else
4123                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
4124                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
4125         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4126                 return rte_flow_error_set(error, EINVAL,
4127                                           RTE_FLOW_ERROR_TYPE_ACTION,
4128                                           NULL, "can't create encap action");
4129         return 0;
4130 }
4131
4132 /**
4133  * Create action push VLAN.
4134  *
4135  * @param[in] dev
4136  *   Pointer to rte_eth_dev structure.
4137  * @param[in] attr
4138  *   Pointer to the flow attributes.
4139  * @param[in] vlan
4140  *   Pointer to the vlan to push to the Ethernet header.
4141  * @param[in, out] dev_flow
4142  *   Pointer to the mlx5_flow.
4143  * @param[out] error
4144  *   Pointer to the error structure.
4145  *
4146  * @return
4147  *   0 on success, a negative errno value otherwise and rte_errno is set.
4148  */
4149 static int
4150 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
4151                                 const struct rte_flow_attr *attr,
4152                                 const struct rte_vlan_hdr *vlan,
4153                                 struct mlx5_flow *dev_flow,
4154                                 struct rte_flow_error *error)
4155 {
4156         struct mlx5_flow_dv_push_vlan_action_resource res;
4157
4158         memset(&res, 0, sizeof(res));
4159         res.vlan_tag =
4160                 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
4161                                  vlan->vlan_tci);
4162         if (attr->transfer)
4163                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
4164         else
4165                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
4166                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
4167         return flow_dv_push_vlan_action_resource_register
4168                                             (dev, &res, dev_flow, error);
4169 }
4170
4171 /**
4172  * Validate the modify-header actions.
4173  *
4174  * @param[in] action_flags
4175  *   Holds the actions detected until now.
4176  * @param[in] action
4177  *   Pointer to the modify action.
4178  * @param[out] error
4179  *   Pointer to error structure.
4180  *
4181  * @return
4182  *   0 on success, a negative errno value otherwise and rte_errno is set.
4183  */
4184 static int
4185 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
4186                                    const struct rte_flow_action *action,
4187                                    struct rte_flow_error *error)
4188 {
4189         if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
4190                 return rte_flow_error_set(error, EINVAL,
4191                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4192                                           NULL, "action configuration not set");
4193         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
4194                 return rte_flow_error_set(error, EINVAL,
4195                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4196                                           "can't have encap action before"
4197                                           " modify action");
4198         return 0;
4199 }
4200
4201 /**
4202  * Validate the modify-header MAC address actions.
4203  *
4204  * @param[in] action_flags
4205  *   Holds the actions detected until now.
4206  * @param[in] action
4207  *   Pointer to the modify action.
4208  * @param[in] item_flags
4209  *   Holds the items detected.
4210  * @param[out] error
4211  *   Pointer to error structure.
4212  *
4213  * @return
4214  *   0 on success, a negative errno value otherwise and rte_errno is set.
4215  */
4216 static int
4217 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
4218                                    const struct rte_flow_action *action,
4219                                    const uint64_t item_flags,
4220                                    struct rte_flow_error *error)
4221 {
4222         int ret = 0;
4223
4224         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4225         if (!ret) {
4226                 if (!(item_flags & MLX5_FLOW_LAYER_L2))
4227                         return rte_flow_error_set(error, EINVAL,
4228                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4229                                                   NULL,
4230                                                   "no L2 item in pattern");
4231         }
4232         return ret;
4233 }
4234
4235 /**
4236  * Validate the modify-header IPv4 address actions.
4237  *
4238  * @param[in] action_flags
4239  *   Holds the actions detected until now.
4240  * @param[in] action
4241  *   Pointer to the modify action.
4242  * @param[in] item_flags
4243  *   Holds the items detected.
4244  * @param[out] error
4245  *   Pointer to error structure.
4246  *
4247  * @return
4248  *   0 on success, a negative errno value otherwise and rte_errno is set.
4249  */
4250 static int
4251 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
4252                                     const struct rte_flow_action *action,
4253                                     const uint64_t item_flags,
4254                                     struct rte_flow_error *error)
4255 {
4256         int ret = 0;
4257         uint64_t layer;
4258
4259         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4260         if (!ret) {
4261                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4262                                  MLX5_FLOW_LAYER_INNER_L3_IPV4 :
4263                                  MLX5_FLOW_LAYER_OUTER_L3_IPV4;
4264                 if (!(item_flags & layer))
4265                         return rte_flow_error_set(error, EINVAL,
4266                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4267                                                   NULL,
4268                                                   "no ipv4 item in pattern");
4269         }
4270         return ret;
4271 }
4272
4273 /**
4274  * Validate the modify-header IPv6 address actions.
4275  *
4276  * @param[in] action_flags
4277  *   Holds the actions detected until now.
4278  * @param[in] action
4279  *   Pointer to the modify action.
4280  * @param[in] item_flags
4281  *   Holds the items detected.
4282  * @param[out] error
4283  *   Pointer to error structure.
4284  *
4285  * @return
4286  *   0 on success, a negative errno value otherwise and rte_errno is set.
4287  */
4288 static int
4289 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
4290                                     const struct rte_flow_action *action,
4291                                     const uint64_t item_flags,
4292                                     struct rte_flow_error *error)
4293 {
4294         int ret = 0;
4295         uint64_t layer;
4296
4297         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4298         if (!ret) {
4299                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4300                                  MLX5_FLOW_LAYER_INNER_L3_IPV6 :
4301                                  MLX5_FLOW_LAYER_OUTER_L3_IPV6;
4302                 if (!(item_flags & layer))
4303                         return rte_flow_error_set(error, EINVAL,
4304                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4305                                                   NULL,
4306                                                   "no ipv6 item in pattern");
4307         }
4308         return ret;
4309 }
4310
4311 /**
4312  * Validate the modify-header TP actions.
4313  *
4314  * @param[in] action_flags
4315  *   Holds the actions detected until now.
4316  * @param[in] action
4317  *   Pointer to the modify action.
4318  * @param[in] item_flags
4319  *   Holds the items detected.
4320  * @param[out] error
4321  *   Pointer to error structure.
4322  *
4323  * @return
4324  *   0 on success, a negative errno value otherwise and rte_errno is set.
4325  */
4326 static int
4327 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
4328                                   const struct rte_flow_action *action,
4329                                   const uint64_t item_flags,
4330                                   struct rte_flow_error *error)
4331 {
4332         int ret = 0;
4333         uint64_t layer;
4334
4335         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4336         if (!ret) {
4337                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4338                                  MLX5_FLOW_LAYER_INNER_L4 :
4339                                  MLX5_FLOW_LAYER_OUTER_L4;
4340                 if (!(item_flags & layer))
4341                         return rte_flow_error_set(error, EINVAL,
4342                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4343                                                   NULL, "no transport layer "
4344                                                   "in pattern");
4345         }
4346         return ret;
4347 }
4348
4349 /**
4350  * Validate the modify-header actions of increment/decrement
4351  * TCP Sequence-number.
4352  *
4353  * @param[in] action_flags
4354  *   Holds the actions detected until now.
4355  * @param[in] action
4356  *   Pointer to the modify action.
4357  * @param[in] item_flags
4358  *   Holds the items detected.
4359  * @param[out] error
4360  *   Pointer to error structure.
4361  *
4362  * @return
4363  *   0 on success, a negative errno value otherwise and rte_errno is set.
4364  */
4365 static int
4366 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
4367                                        const struct rte_flow_action *action,
4368                                        const uint64_t item_flags,
4369                                        struct rte_flow_error *error)
4370 {
4371         int ret = 0;
4372         uint64_t layer;
4373
4374         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4375         if (!ret) {
4376                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4377                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
4378                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
4379                 if (!(item_flags & layer))
4380                         return rte_flow_error_set(error, EINVAL,
4381                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4382                                                   NULL, "no TCP item in"
4383                                                   " pattern");
4384                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
4385                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
4386                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
4387                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
4388                         return rte_flow_error_set(error, EINVAL,
4389                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4390                                                   NULL,
4391                                                   "cannot decrease and increase"
4392                                                   " TCP sequence number"
4393                                                   " at the same time");
4394         }
4395         return ret;
4396 }
4397
4398 /**
4399  * Validate the modify-header actions of increment/decrement
4400  * TCP Acknowledgment number.
4401  *
4402  * @param[in] action_flags
4403  *   Holds the actions detected until now.
4404  * @param[in] action
4405  *   Pointer to the modify action.
4406  * @param[in] item_flags
4407  *   Holds the items detected.
4408  * @param[out] error
4409  *   Pointer to error structure.
4410  *
4411  * @return
4412  *   0 on success, a negative errno value otherwise and rte_errno is set.
4413  */
4414 static int
4415 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
4416                                        const struct rte_flow_action *action,
4417                                        const uint64_t item_flags,
4418                                        struct rte_flow_error *error)
4419 {
4420         int ret = 0;
4421         uint64_t layer;
4422
4423         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4424         if (!ret) {
4425                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4426                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
4427                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
4428                 if (!(item_flags & layer))
4429                         return rte_flow_error_set(error, EINVAL,
4430                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4431                                                   NULL, "no TCP item in"
4432                                                   " pattern");
4433                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
4434                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
4435                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
4436                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
4437                         return rte_flow_error_set(error, EINVAL,
4438                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4439                                                   NULL,
4440                                                   "cannot decrease and increase"
4441                                                   " TCP acknowledgment number"
4442                                                   " at the same time");
4443         }
4444         return ret;
4445 }
4446
4447 /**
4448  * Validate the modify-header TTL actions.
4449  *
4450  * @param[in] action_flags
4451  *   Holds the actions detected until now.
4452  * @param[in] action
4453  *   Pointer to the modify action.
4454  * @param[in] item_flags
4455  *   Holds the items detected.
4456  * @param[out] error
4457  *   Pointer to error structure.
4458  *
4459  * @return
4460  *   0 on success, a negative errno value otherwise and rte_errno is set.
4461  */
4462 static int
4463 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
4464                                    const struct rte_flow_action *action,
4465                                    const uint64_t item_flags,
4466                                    struct rte_flow_error *error)
4467 {
4468         int ret = 0;
4469         uint64_t layer;
4470
4471         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4472         if (!ret) {
4473                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4474                                  MLX5_FLOW_LAYER_INNER_L3 :
4475                                  MLX5_FLOW_LAYER_OUTER_L3;
4476                 if (!(item_flags & layer))
4477                         return rte_flow_error_set(error, EINVAL,
4478                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4479                                                   NULL,
4480                                                   "no IP protocol in pattern");
4481         }
4482         return ret;
4483 }
4484
4485 static int
4486 mlx5_flow_item_field_width(enum rte_flow_field_id field)
4487 {
4488         switch (field) {
4489         case RTE_FLOW_FIELD_START:
4490                 return 32;
4491         case RTE_FLOW_FIELD_MAC_DST:
4492         case RTE_FLOW_FIELD_MAC_SRC:
4493                 return 48;
4494         case RTE_FLOW_FIELD_VLAN_TYPE:
4495                 return 16;
4496         case RTE_FLOW_FIELD_VLAN_ID:
4497                 return 12;
4498         case RTE_FLOW_FIELD_MAC_TYPE:
4499                 return 16;
4500         case RTE_FLOW_FIELD_IPV4_DSCP:
4501                 return 6;
4502         case RTE_FLOW_FIELD_IPV4_TTL:
4503                 return 8;
4504         case RTE_FLOW_FIELD_IPV4_SRC:
4505         case RTE_FLOW_FIELD_IPV4_DST:
4506                 return 32;
4507         case RTE_FLOW_FIELD_IPV6_DSCP:
4508                 return 6;
4509         case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
4510                 return 8;
4511         case RTE_FLOW_FIELD_IPV6_SRC:
4512         case RTE_FLOW_FIELD_IPV6_DST:
4513                 return 128;
4514         case RTE_FLOW_FIELD_TCP_PORT_SRC:
4515         case RTE_FLOW_FIELD_TCP_PORT_DST:
4516                 return 16;
4517         case RTE_FLOW_FIELD_TCP_SEQ_NUM:
4518         case RTE_FLOW_FIELD_TCP_ACK_NUM:
4519                 return 32;
4520         case RTE_FLOW_FIELD_TCP_FLAGS:
4521                 return 6;
4522         case RTE_FLOW_FIELD_UDP_PORT_SRC:
4523         case RTE_FLOW_FIELD_UDP_PORT_DST:
4524                 return 16;
4525         case RTE_FLOW_FIELD_VXLAN_VNI:
4526         case RTE_FLOW_FIELD_GENEVE_VNI:
4527                 return 24;
4528         case RTE_FLOW_FIELD_GTP_TEID:
4529         case RTE_FLOW_FIELD_TAG:
4530                 return 32;
4531         case RTE_FLOW_FIELD_MARK:
4532                 return 24;
4533         case RTE_FLOW_FIELD_META:
4534         case RTE_FLOW_FIELD_POINTER:
4535         case RTE_FLOW_FIELD_VALUE:
4536                 return 32;
4537         default:
4538                 MLX5_ASSERT(false);
4539         }
4540         return 0;
4541 }
4542
4543 /**
4544  * Validate the generic modify field actions.
4545  *
4546  * @param[in] action_flags
4547  *   Holds the actions detected until now.
4548  * @param[in] action
4549  *   Pointer to the modify action.
4550  * @param[in] item_flags
4551  *   Holds the items detected.
4552  * @param[out] error
4553  *   Pointer to error structure.
4554  *
4555  * @return
4556  *   Number of header fields to modify (0 or more) on success,
4557  *   a negative errno value otherwise and rte_errno is set.
4558  */
4559 static int
4560 flow_dv_validate_action_modify_field(const uint64_t action_flags,
4561                                    const struct rte_flow_action *action,
4562                                    struct rte_flow_error *error)
4563 {
4564         int ret = 0;
4565         const struct rte_flow_action_modify_field *action_modify_field =
4566                 action->conf;
4567         uint32_t dst_width =
4568                 mlx5_flow_item_field_width(action_modify_field->dst.field);
4569         uint32_t src_width =
4570                 mlx5_flow_item_field_width(action_modify_field->src.field);
4571
4572         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4573         if (ret)
4574                 return ret;
4575
4576         if (action_modify_field->width == 0)
4577                 return rte_flow_error_set(error, EINVAL,
4578                                         RTE_FLOW_ERROR_TYPE_ACTION,
4579                                         NULL,
4580                                         "no bits are requested to be modified");
4581         else if (action_modify_field->width > dst_width ||
4582                  action_modify_field->width > src_width)
4583                 return rte_flow_error_set(error, EINVAL,
4584                                         RTE_FLOW_ERROR_TYPE_ACTION,
4585                                         NULL,
4586                                         "cannot modify more bits than"
4587                                         " the width of a field");
4588         if (action_modify_field->dst.field != RTE_FLOW_FIELD_VALUE &&
4589             action_modify_field->dst.field != RTE_FLOW_FIELD_POINTER) {
4590                 if ((action_modify_field->dst.offset +
4591                      action_modify_field->width > dst_width) ||
4592                     (action_modify_field->dst.offset % 32))
4593                         return rte_flow_error_set(error, EINVAL,
4594                                                 RTE_FLOW_ERROR_TYPE_ACTION,
4595                                                 NULL,
4596                                                 "destination offset is too big"
4597                                                 " or not aligned to 4 bytes");
4598                 if (action_modify_field->dst.level &&
4599                     action_modify_field->dst.field != RTE_FLOW_FIELD_TAG)
4600                         return rte_flow_error_set(error, EINVAL,
4601                                                 RTE_FLOW_ERROR_TYPE_ACTION,
4602                                                 NULL,
4603                                                 "cannot modify inner headers");
4604         }
4605         if (action_modify_field->src.field != RTE_FLOW_FIELD_VALUE &&
4606             action_modify_field->src.field != RTE_FLOW_FIELD_POINTER) {
4607                 if ((action_modify_field->src.offset +
4608                      action_modify_field->width > src_width) ||
4609                     (action_modify_field->src.offset % 32))
4610                         return rte_flow_error_set(error, EINVAL,
4611                                                 RTE_FLOW_ERROR_TYPE_ACTION,
4612                                                 NULL,
4613                                                 "source offset is too big"
4614                                                 " or not aligned to 4 bytes");
4615                 if (action_modify_field->src.level &&
4616                     action_modify_field->src.field != RTE_FLOW_FIELD_TAG)
4617                         return rte_flow_error_set(error, EINVAL,
4618                                                 RTE_FLOW_ERROR_TYPE_ACTION,
4619                                                 NULL,
4620                                                 "cannot copy from inner headers");
4621         }
4622         if (action_modify_field->dst.field ==
4623             action_modify_field->src.field)
4624                 return rte_flow_error_set(error, EINVAL,
4625                                         RTE_FLOW_ERROR_TYPE_ACTION,
4626                                         NULL,
4627                                         "source and destination fields"
4628                                         " cannot be the same");
4629         if (action_modify_field->dst.field == RTE_FLOW_FIELD_VALUE ||
4630             action_modify_field->dst.field == RTE_FLOW_FIELD_POINTER)
4631                 return rte_flow_error_set(error, EINVAL,
4632                                         RTE_FLOW_ERROR_TYPE_ACTION,
4633                                         NULL,
4634                                         "immediate value or a pointer to it"
4635                                         " cannot be used as a destination");
4636         if (action_modify_field->dst.field == RTE_FLOW_FIELD_START ||
4637             action_modify_field->src.field == RTE_FLOW_FIELD_START)
4638                 return rte_flow_error_set(error, EINVAL,
4639                                 RTE_FLOW_ERROR_TYPE_ACTION,
4640                                 NULL,
4641                                 "modifications of an arbitrary"
4642                                 " place in a packet is not supported");
4643         if (action_modify_field->operation != RTE_FLOW_MODIFY_SET)
4644                 return rte_flow_error_set(error, EINVAL,
4645                                 RTE_FLOW_ERROR_TYPE_ACTION,
4646                                 NULL,
4647                                 "add and sub operations"
4648                                 " are not supported");
4649         return (action_modify_field->width / 32) +
4650                !!(action_modify_field->width % 32);
4651 }
4652
4653 /**
4654  * Validate jump action.
4655  *
4656  * @param[in] action
4657  *   Pointer to the jump action.
4658  * @param[in] action_flags
4659  *   Holds the actions detected until now.
4660  * @param[in] attributes
4661  *   Pointer to flow attributes
4662  * @param[in] external
4663  *   Action belongs to flow rule created by request external to PMD.
4664  * @param[out] error
4665  *   Pointer to error structure.
4666  *
4667  * @return
4668  *   0 on success, a negative errno value otherwise and rte_errno is set.
4669  */
4670 static int
4671 flow_dv_validate_action_jump(struct rte_eth_dev *dev,
4672                              const struct mlx5_flow_tunnel *tunnel,
4673                              const struct rte_flow_action *action,
4674                              uint64_t action_flags,
4675                              const struct rte_flow_attr *attributes,
4676                              bool external, struct rte_flow_error *error)
4677 {
4678         uint32_t target_group, table;
4679         int ret = 0;
4680         struct flow_grp_info grp_info = {
4681                 .external = !!external,
4682                 .transfer = !!attributes->transfer,
4683                 .fdb_def_rule = 1,
4684                 .std_tbl_fix = 0
4685         };
4686         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
4687                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4688                 return rte_flow_error_set(error, EINVAL,
4689                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4690                                           "can't have 2 fate actions in"
4691                                           " same flow");
4692         if (action_flags & MLX5_FLOW_ACTION_METER)
4693                 return rte_flow_error_set(error, ENOTSUP,
4694                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4695                                           "jump with meter not support");
4696         if (!action->conf)
4697                 return rte_flow_error_set(error, EINVAL,
4698                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4699                                           NULL, "action configuration not set");
4700         target_group =
4701                 ((const struct rte_flow_action_jump *)action->conf)->group;
4702         ret = mlx5_flow_group_to_table(dev, tunnel, target_group, &table,
4703                                        &grp_info, error);
4704         if (ret)
4705                 return ret;
4706         if (attributes->group == target_group &&
4707             !(action_flags & (MLX5_FLOW_ACTION_TUNNEL_SET |
4708                               MLX5_FLOW_ACTION_TUNNEL_MATCH)))
4709                 return rte_flow_error_set(error, EINVAL,
4710                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4711                                           "target group must be other than"
4712                                           " the current flow group");
4713         return 0;
4714 }
4715
4716 /*
4717  * Validate the port_id action.
4718  *
4719  * @param[in] dev
4720  *   Pointer to rte_eth_dev structure.
4721  * @param[in] action_flags
4722  *   Bit-fields that holds the actions detected until now.
4723  * @param[in] action
4724  *   Port_id RTE action structure.
4725  * @param[in] attr
4726  *   Attributes of flow that includes this action.
4727  * @param[out] error
4728  *   Pointer to error structure.
4729  *
4730  * @return
4731  *   0 on success, a negative errno value otherwise and rte_errno is set.
4732  */
4733 static int
4734 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
4735                                 uint64_t action_flags,
4736                                 const struct rte_flow_action *action,
4737                                 const struct rte_flow_attr *attr,
4738                                 struct rte_flow_error *error)
4739 {
4740         const struct rte_flow_action_port_id *port_id;
4741         struct mlx5_priv *act_priv;
4742         struct mlx5_priv *dev_priv;
4743         uint16_t port;
4744
4745         if (!attr->transfer)
4746                 return rte_flow_error_set(error, ENOTSUP,
4747                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4748                                           NULL,
4749                                           "port id action is valid in transfer"
4750                                           " mode only");
4751         if (!action || !action->conf)
4752                 return rte_flow_error_set(error, ENOTSUP,
4753                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4754                                           NULL,
4755                                           "port id action parameters must be"
4756                                           " specified");
4757         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
4758                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4759                 return rte_flow_error_set(error, EINVAL,
4760                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4761                                           "can have only one fate actions in"
4762                                           " a flow");
4763         dev_priv = mlx5_dev_to_eswitch_info(dev);
4764         if (!dev_priv)
4765                 return rte_flow_error_set(error, rte_errno,
4766                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4767                                           NULL,
4768                                           "failed to obtain E-Switch info");
4769         port_id = action->conf;
4770         port = port_id->original ? dev->data->port_id : port_id->id;
4771         act_priv = mlx5_port_to_eswitch_info(port, false);
4772         if (!act_priv)
4773                 return rte_flow_error_set
4774                                 (error, rte_errno,
4775                                  RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
4776                                  "failed to obtain E-Switch port id for port");
4777         if (act_priv->domain_id != dev_priv->domain_id)
4778                 return rte_flow_error_set
4779                                 (error, EINVAL,
4780                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4781                                  "port does not belong to"
4782                                  " E-Switch being configured");
4783         return 0;
4784 }
4785
4786 /**
4787  * Get the maximum number of modify header actions.
4788  *
4789  * @param dev
4790  *   Pointer to rte_eth_dev structure.
4791  * @param flags
4792  *   Flags bits to check if root level.
4793  *
4794  * @return
4795  *   Max number of modify header actions device can support.
4796  */
4797 static inline unsigned int
4798 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev __rte_unused,
4799                               uint64_t flags)
4800 {
4801         /*
4802          * There's no way to directly query the max capacity from FW.
4803          * The maximal value on root table should be assumed to be supported.
4804          */
4805         if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
4806                 return MLX5_MAX_MODIFY_NUM;
4807         else
4808                 return MLX5_ROOT_TBL_MODIFY_NUM;
4809 }
4810
4811 /**
4812  * Validate the meter action.
4813  *
4814  * @param[in] dev
4815  *   Pointer to rte_eth_dev structure.
4816  * @param[in] action_flags
4817  *   Bit-fields that holds the actions detected until now.
4818  * @param[in] action
4819  *   Pointer to the meter action.
4820  * @param[in] attr
4821  *   Attributes of flow that includes this action.
4822  * @param[out] error
4823  *   Pointer to error structure.
4824  *
4825  * @return
4826  *   0 on success, a negative errno value otherwise and rte_ernno is set.
4827  */
4828 static int
4829 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
4830                                 uint64_t action_flags,
4831                                 const struct rte_flow_action *action,
4832                                 const struct rte_flow_attr *attr,
4833                                 struct rte_flow_error *error)
4834 {
4835         struct mlx5_priv *priv = dev->data->dev_private;
4836         const struct rte_flow_action_meter *am = action->conf;
4837         struct mlx5_flow_meter *fm;
4838
4839         if (!am)
4840                 return rte_flow_error_set(error, EINVAL,
4841                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4842                                           "meter action conf is NULL");
4843
4844         if (action_flags & MLX5_FLOW_ACTION_METER)
4845                 return rte_flow_error_set(error, ENOTSUP,
4846                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4847                                           "meter chaining not support");
4848         if (action_flags & MLX5_FLOW_ACTION_JUMP)
4849                 return rte_flow_error_set(error, ENOTSUP,
4850                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4851                                           "meter with jump not support");
4852         if (!priv->mtr_en)
4853                 return rte_flow_error_set(error, ENOTSUP,
4854                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4855                                           NULL,
4856                                           "meter action not supported");
4857         fm = mlx5_flow_meter_find(priv, am->mtr_id);
4858         if (!fm)
4859                 return rte_flow_error_set(error, EINVAL,
4860                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4861                                           "Meter not found");
4862         if (fm->ref_cnt && (!(fm->transfer == attr->transfer ||
4863               (!fm->ingress && !attr->ingress && attr->egress) ||
4864               (!fm->egress && !attr->egress && attr->ingress))))
4865                 return rte_flow_error_set(error, EINVAL,
4866                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4867                                           "Flow attributes are either invalid "
4868                                           "or have a conflict with current "
4869                                           "meter attributes");
4870         return 0;
4871 }
4872
4873 /**
4874  * Validate the age action.
4875  *
4876  * @param[in] action_flags
4877  *   Holds the actions detected until now.
4878  * @param[in] action
4879  *   Pointer to the age action.
4880  * @param[in] dev
4881  *   Pointer to the Ethernet device structure.
4882  * @param[out] error
4883  *   Pointer to error structure.
4884  *
4885  * @return
4886  *   0 on success, a negative errno value otherwise and rte_errno is set.
4887  */
4888 static int
4889 flow_dv_validate_action_age(uint64_t action_flags,
4890                             const struct rte_flow_action *action,
4891                             struct rte_eth_dev *dev,
4892                             struct rte_flow_error *error)
4893 {
4894         struct mlx5_priv *priv = dev->data->dev_private;
4895         const struct rte_flow_action_age *age = action->conf;
4896
4897         if (!priv->config.devx || (priv->sh->cmng.counter_fallback &&
4898             !priv->sh->aso_age_mng))
4899                 return rte_flow_error_set(error, ENOTSUP,
4900                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4901                                           NULL,
4902                                           "age action not supported");
4903         if (!(action->conf))
4904                 return rte_flow_error_set(error, EINVAL,
4905                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4906                                           "configuration cannot be null");
4907         if (!(age->timeout))
4908                 return rte_flow_error_set(error, EINVAL,
4909                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4910                                           "invalid timeout value 0");
4911         if (action_flags & MLX5_FLOW_ACTION_AGE)
4912                 return rte_flow_error_set(error, EINVAL,
4913                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4914                                           "duplicate age actions set");
4915         return 0;
4916 }
4917
4918 /**
4919  * Validate the modify-header IPv4 DSCP actions.
4920  *
4921  * @param[in] action_flags
4922  *   Holds the actions detected until now.
4923  * @param[in] action
4924  *   Pointer to the modify action.
4925  * @param[in] item_flags
4926  *   Holds the items detected.
4927  * @param[out] error
4928  *   Pointer to error structure.
4929  *
4930  * @return
4931  *   0 on success, a negative errno value otherwise and rte_errno is set.
4932  */
4933 static int
4934 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
4935                                          const struct rte_flow_action *action,
4936                                          const uint64_t item_flags,
4937                                          struct rte_flow_error *error)
4938 {
4939         int ret = 0;
4940
4941         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4942         if (!ret) {
4943                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
4944                         return rte_flow_error_set(error, EINVAL,
4945                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4946                                                   NULL,
4947                                                   "no ipv4 item in pattern");
4948         }
4949         return ret;
4950 }
4951
4952 /**
4953  * Validate the modify-header IPv6 DSCP actions.
4954  *
4955  * @param[in] action_flags
4956  *   Holds the actions detected until now.
4957  * @param[in] action
4958  *   Pointer to the modify action.
4959  * @param[in] item_flags
4960  *   Holds the items detected.
4961  * @param[out] error
4962  *   Pointer to error structure.
4963  *
4964  * @return
4965  *   0 on success, a negative errno value otherwise and rte_errno is set.
4966  */
4967 static int
4968 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
4969                                          const struct rte_flow_action *action,
4970                                          const uint64_t item_flags,
4971                                          struct rte_flow_error *error)
4972 {
4973         int ret = 0;
4974
4975         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4976         if (!ret) {
4977                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
4978                         return rte_flow_error_set(error, EINVAL,
4979                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4980                                                   NULL,
4981                                                   "no ipv6 item in pattern");
4982         }
4983         return ret;
4984 }
4985
4986 /**
4987  * Match modify-header resource.
4988  *
4989  * @param list
4990  *   Pointer to the hash list.
4991  * @param entry
4992  *   Pointer to exist resource entry object.
4993  * @param key
4994  *   Key of the new entry.
4995  * @param ctx
4996  *   Pointer to new modify-header resource.
4997  *
4998  * @return
4999  *   0 on matching, non-zero otherwise.
5000  */
5001 int
5002 flow_dv_modify_match_cb(struct mlx5_hlist *list __rte_unused,
5003                         struct mlx5_hlist_entry *entry,
5004                         uint64_t key __rte_unused, void *cb_ctx)
5005 {
5006         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5007         struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5008         struct mlx5_flow_dv_modify_hdr_resource *resource =
5009                         container_of(entry, typeof(*resource), entry);
5010         uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
5011
5012         key_len += ref->actions_num * sizeof(ref->actions[0]);
5013         return ref->actions_num != resource->actions_num ||
5014                memcmp(&ref->ft_type, &resource->ft_type, key_len);
5015 }
5016
5017 struct mlx5_hlist_entry *
5018 flow_dv_modify_create_cb(struct mlx5_hlist *list, uint64_t key __rte_unused,
5019                          void *cb_ctx)
5020 {
5021         struct mlx5_dev_ctx_shared *sh = list->ctx;
5022         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5023         struct mlx5dv_dr_domain *ns;
5024         struct mlx5_flow_dv_modify_hdr_resource *entry;
5025         struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5026         int ret;
5027         uint32_t data_len = ref->actions_num * sizeof(ref->actions[0]);
5028         uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
5029
5030         entry = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*entry) + data_len, 0,
5031                             SOCKET_ID_ANY);
5032         if (!entry) {
5033                 rte_flow_error_set(ctx->error, ENOMEM,
5034                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5035                                    "cannot allocate resource memory");
5036                 return NULL;
5037         }
5038         rte_memcpy(&entry->ft_type,
5039                    RTE_PTR_ADD(ref, offsetof(typeof(*ref), ft_type)),
5040                    key_len + data_len);
5041         if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
5042                 ns = sh->fdb_domain;
5043         else if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
5044                 ns = sh->tx_domain;
5045         else
5046                 ns = sh->rx_domain;
5047         ret = mlx5_flow_os_create_flow_action_modify_header
5048                                         (sh->ctx, ns, entry,
5049                                          data_len, &entry->action);
5050         if (ret) {
5051                 mlx5_free(entry);
5052                 rte_flow_error_set(ctx->error, ENOMEM,
5053                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5054                                    NULL, "cannot create modification action");
5055                 return NULL;
5056         }
5057         return &entry->entry;
5058 }
5059
5060 /**
5061  * Validate the sample action.
5062  *
5063  * @param[in, out] action_flags
5064  *   Holds the actions detected until now.
5065  * @param[in] action
5066  *   Pointer to the sample action.
5067  * @param[in] dev
5068  *   Pointer to the Ethernet device structure.
5069  * @param[in] attr
5070  *   Attributes of flow that includes this action.
5071  * @param[in] item_flags
5072  *   Holds the items detected.
5073  * @param[in] rss
5074  *   Pointer to the RSS action.
5075  * @param[out] sample_rss
5076  *   Pointer to the RSS action in sample action list.
5077  * @param[out] count
5078  *   Pointer to the COUNT action in sample action list.
5079  * @param[out] fdb_mirror_limit
5080  *   Pointer to the FDB mirror limitation flag.
5081  * @param[out] error
5082  *   Pointer to error structure.
5083  *
5084  * @return
5085  *   0 on success, a negative errno value otherwise and rte_errno is set.
5086  */
5087 static int
5088 flow_dv_validate_action_sample(uint64_t *action_flags,
5089                                const struct rte_flow_action *action,
5090                                struct rte_eth_dev *dev,
5091                                const struct rte_flow_attr *attr,
5092                                uint64_t item_flags,
5093                                const struct rte_flow_action_rss *rss,
5094                                const struct rte_flow_action_rss **sample_rss,
5095                                const struct rte_flow_action_count **count,
5096                                int *fdb_mirror_limit,
5097                                struct rte_flow_error *error)
5098 {
5099         struct mlx5_priv *priv = dev->data->dev_private;
5100         struct mlx5_dev_config *dev_conf = &priv->config;
5101         const struct rte_flow_action_sample *sample = action->conf;
5102         const struct rte_flow_action *act;
5103         uint64_t sub_action_flags = 0;
5104         uint16_t queue_index = 0xFFFF;
5105         int actions_n = 0;
5106         int ret;
5107
5108         if (!sample)
5109                 return rte_flow_error_set(error, EINVAL,
5110                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
5111                                           "configuration cannot be NULL");
5112         if (sample->ratio == 0)
5113                 return rte_flow_error_set(error, EINVAL,
5114                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
5115                                           "ratio value starts from 1");
5116         if (!priv->config.devx || (sample->ratio > 0 && !priv->sampler_en))
5117                 return rte_flow_error_set(error, ENOTSUP,
5118                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5119                                           NULL,
5120                                           "sample action not supported");
5121         if (*action_flags & MLX5_FLOW_ACTION_SAMPLE)
5122                 return rte_flow_error_set(error, EINVAL,
5123                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5124                                           "Multiple sample actions not "
5125                                           "supported");
5126         if (*action_flags & MLX5_FLOW_ACTION_METER)
5127                 return rte_flow_error_set(error, EINVAL,
5128                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
5129                                           "wrong action order, meter should "
5130                                           "be after sample action");
5131         if (*action_flags & MLX5_FLOW_ACTION_JUMP)
5132                 return rte_flow_error_set(error, EINVAL,
5133                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
5134                                           "wrong action order, jump should "
5135                                           "be after sample action");
5136         act = sample->actions;
5137         for (; act->type != RTE_FLOW_ACTION_TYPE_END; act++) {
5138                 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
5139                         return rte_flow_error_set(error, ENOTSUP,
5140                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5141                                                   act, "too many actions");
5142                 switch (act->type) {
5143                 case RTE_FLOW_ACTION_TYPE_QUEUE:
5144                         ret = mlx5_flow_validate_action_queue(act,
5145                                                               sub_action_flags,
5146                                                               dev,
5147                                                               attr, error);
5148                         if (ret < 0)
5149                                 return ret;
5150                         queue_index = ((const struct rte_flow_action_queue *)
5151                                                         (act->conf))->index;
5152                         sub_action_flags |= MLX5_FLOW_ACTION_QUEUE;
5153                         ++actions_n;
5154                         break;
5155                 case RTE_FLOW_ACTION_TYPE_RSS:
5156                         *sample_rss = act->conf;
5157                         ret = mlx5_flow_validate_action_rss(act,
5158                                                             sub_action_flags,
5159                                                             dev, attr,
5160                                                             item_flags,
5161                                                             error);
5162                         if (ret < 0)
5163                                 return ret;
5164                         if (rss && *sample_rss &&
5165                             ((*sample_rss)->level != rss->level ||
5166                             (*sample_rss)->types != rss->types))
5167                                 return rte_flow_error_set(error, ENOTSUP,
5168                                         RTE_FLOW_ERROR_TYPE_ACTION,
5169                                         NULL,
5170                                         "Can't use the different RSS types "
5171                                         "or level in the same flow");
5172                         if (*sample_rss != NULL && (*sample_rss)->queue_num)
5173                                 queue_index = (*sample_rss)->queue[0];
5174                         sub_action_flags |= MLX5_FLOW_ACTION_RSS;
5175                         ++actions_n;
5176                         break;
5177                 case RTE_FLOW_ACTION_TYPE_MARK:
5178                         ret = flow_dv_validate_action_mark(dev, act,
5179                                                            sub_action_flags,
5180                                                            attr, error);
5181                         if (ret < 0)
5182                                 return ret;
5183                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY)
5184                                 sub_action_flags |= MLX5_FLOW_ACTION_MARK |
5185                                                 MLX5_FLOW_ACTION_MARK_EXT;
5186                         else
5187                                 sub_action_flags |= MLX5_FLOW_ACTION_MARK;
5188                         ++actions_n;
5189                         break;
5190                 case RTE_FLOW_ACTION_TYPE_COUNT:
5191                         ret = flow_dv_validate_action_count
5192                                 (dev, act,
5193                                  *action_flags | sub_action_flags,
5194                                  error);
5195                         if (ret < 0)
5196                                 return ret;
5197                         *count = act->conf;
5198                         sub_action_flags |= MLX5_FLOW_ACTION_COUNT;
5199                         *action_flags |= MLX5_FLOW_ACTION_COUNT;
5200                         ++actions_n;
5201                         break;
5202                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5203                         ret = flow_dv_validate_action_port_id(dev,
5204                                                               sub_action_flags,
5205                                                               act,
5206                                                               attr,
5207                                                               error);
5208                         if (ret)
5209                                 return ret;
5210                         sub_action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5211                         ++actions_n;
5212                         break;
5213                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5214                         ret = flow_dv_validate_action_raw_encap_decap
5215                                 (dev, NULL, act->conf, attr, &sub_action_flags,
5216                                  &actions_n, action, item_flags, error);
5217                         if (ret < 0)
5218                                 return ret;
5219                         ++actions_n;
5220                         break;
5221                 default:
5222                         return rte_flow_error_set(error, ENOTSUP,
5223                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5224                                                   NULL,
5225                                                   "Doesn't support optional "
5226                                                   "action");
5227                 }
5228         }
5229         if (attr->ingress && !attr->transfer) {
5230                 if (!(sub_action_flags & (MLX5_FLOW_ACTION_QUEUE |
5231                                           MLX5_FLOW_ACTION_RSS)))
5232                         return rte_flow_error_set(error, EINVAL,
5233                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5234                                                   NULL,
5235                                                   "Ingress must has a dest "
5236                                                   "QUEUE for Sample");
5237         } else if (attr->egress && !attr->transfer) {
5238                 return rte_flow_error_set(error, ENOTSUP,
5239                                           RTE_FLOW_ERROR_TYPE_ACTION,
5240                                           NULL,
5241                                           "Sample Only support Ingress "
5242                                           "or E-Switch");
5243         } else if (sample->actions->type != RTE_FLOW_ACTION_TYPE_END) {
5244                 MLX5_ASSERT(attr->transfer);
5245                 if (sample->ratio > 1)
5246                         return rte_flow_error_set(error, ENOTSUP,
5247                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5248                                                   NULL,
5249                                                   "E-Switch doesn't support "
5250                                                   "any optional action "
5251                                                   "for sampling");
5252                 if (sub_action_flags & MLX5_FLOW_ACTION_QUEUE)
5253                         return rte_flow_error_set(error, ENOTSUP,
5254                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5255                                                   NULL,
5256                                                   "unsupported action QUEUE");
5257                 if (sub_action_flags & MLX5_FLOW_ACTION_RSS)
5258                         return rte_flow_error_set(error, ENOTSUP,
5259                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5260                                                   NULL,
5261                                                   "unsupported action QUEUE");
5262                 if (!(sub_action_flags & MLX5_FLOW_ACTION_PORT_ID))
5263                         return rte_flow_error_set(error, EINVAL,
5264                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5265                                                   NULL,
5266                                                   "E-Switch must has a dest "
5267                                                   "port for mirroring");
5268                 if (!priv->config.hca_attr.reg_c_preserve &&
5269                      priv->representor_id != -1)
5270                         *fdb_mirror_limit = 1;
5271         }
5272         /* Continue validation for Xcap actions.*/
5273         if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) &&
5274             (queue_index == 0xFFFF ||
5275              mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
5276                 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
5277                      MLX5_FLOW_XCAP_ACTIONS)
5278                         return rte_flow_error_set(error, ENOTSUP,
5279                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5280                                                   NULL, "encap and decap "
5281                                                   "combination aren't "
5282                                                   "supported");
5283                 if (!attr->transfer && attr->ingress && (sub_action_flags &
5284                                                         MLX5_FLOW_ACTION_ENCAP))
5285                         return rte_flow_error_set(error, ENOTSUP,
5286                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5287                                                   NULL, "encap is not supported"
5288                                                   " for ingress traffic");
5289         }
5290         return 0;
5291 }
5292
5293 /**
5294  * Find existing modify-header resource or create and register a new one.
5295  *
5296  * @param dev[in, out]
5297  *   Pointer to rte_eth_dev structure.
5298  * @param[in, out] resource
5299  *   Pointer to modify-header resource.
5300  * @parm[in, out] dev_flow
5301  *   Pointer to the dev_flow.
5302  * @param[out] error
5303  *   pointer to error structure.
5304  *
5305  * @return
5306  *   0 on success otherwise -errno and errno is set.
5307  */
5308 static int
5309 flow_dv_modify_hdr_resource_register
5310                         (struct rte_eth_dev *dev,
5311                          struct mlx5_flow_dv_modify_hdr_resource *resource,
5312                          struct mlx5_flow *dev_flow,
5313                          struct rte_flow_error *error)
5314 {
5315         struct mlx5_priv *priv = dev->data->dev_private;
5316         struct mlx5_dev_ctx_shared *sh = priv->sh;
5317         uint32_t key_len = sizeof(*resource) -
5318                            offsetof(typeof(*resource), ft_type) +
5319                            resource->actions_num * sizeof(resource->actions[0]);
5320         struct mlx5_hlist_entry *entry;
5321         struct mlx5_flow_cb_ctx ctx = {
5322                 .error = error,
5323                 .data = resource,
5324         };
5325         uint64_t key64;
5326
5327         resource->flags = dev_flow->dv.group ? 0 :
5328                           MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
5329         if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
5330                                     resource->flags))
5331                 return rte_flow_error_set(error, EOVERFLOW,
5332                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5333                                           "too many modify header items");
5334         key64 = __rte_raw_cksum(&resource->ft_type, key_len, 0);
5335         entry = mlx5_hlist_register(sh->modify_cmds, key64, &ctx);
5336         if (!entry)
5337                 return -rte_errno;
5338         resource = container_of(entry, typeof(*resource), entry);
5339         dev_flow->handle->dvh.modify_hdr = resource;
5340         return 0;
5341 }
5342
5343 /**
5344  * Get DV flow counter by index.
5345  *
5346  * @param[in] dev
5347  *   Pointer to the Ethernet device structure.
5348  * @param[in] idx
5349  *   mlx5 flow counter index in the container.
5350  * @param[out] ppool
5351  *   mlx5 flow counter pool in the container,
5352  *
5353  * @return
5354  *   Pointer to the counter, NULL otherwise.
5355  */
5356 static struct mlx5_flow_counter *
5357 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
5358                            uint32_t idx,
5359                            struct mlx5_flow_counter_pool **ppool)
5360 {
5361         struct mlx5_priv *priv = dev->data->dev_private;
5362         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5363         struct mlx5_flow_counter_pool *pool;
5364
5365         /* Decrease to original index and clear shared bit. */
5366         idx = (idx - 1) & (MLX5_CNT_SHARED_OFFSET - 1);
5367         MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cmng->n);
5368         pool = cmng->pools[idx / MLX5_COUNTERS_PER_POOL];
5369         MLX5_ASSERT(pool);
5370         if (ppool)
5371                 *ppool = pool;
5372         return MLX5_POOL_GET_CNT(pool, idx % MLX5_COUNTERS_PER_POOL);
5373 }
5374
5375 /**
5376  * Check the devx counter belongs to the pool.
5377  *
5378  * @param[in] pool
5379  *   Pointer to the counter pool.
5380  * @param[in] id
5381  *   The counter devx ID.
5382  *
5383  * @return
5384  *   True if counter belongs to the pool, false otherwise.
5385  */
5386 static bool
5387 flow_dv_is_counter_in_pool(struct mlx5_flow_counter_pool *pool, int id)
5388 {
5389         int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
5390                    MLX5_COUNTERS_PER_POOL;
5391
5392         if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
5393                 return true;
5394         return false;
5395 }
5396
5397 /**
5398  * Get a pool by devx counter ID.
5399  *
5400  * @param[in] cmng
5401  *   Pointer to the counter management.
5402  * @param[in] id
5403  *   The counter devx ID.
5404  *
5405  * @return
5406  *   The counter pool pointer if exists, NULL otherwise,
5407  */
5408 static struct mlx5_flow_counter_pool *
5409 flow_dv_find_pool_by_id(struct mlx5_flow_counter_mng *cmng, int id)
5410 {
5411         uint32_t i;
5412         struct mlx5_flow_counter_pool *pool = NULL;
5413
5414         rte_spinlock_lock(&cmng->pool_update_sl);
5415         /* Check last used pool. */
5416         if (cmng->last_pool_idx != POOL_IDX_INVALID &&
5417             flow_dv_is_counter_in_pool(cmng->pools[cmng->last_pool_idx], id)) {
5418                 pool = cmng->pools[cmng->last_pool_idx];
5419                 goto out;
5420         }
5421         /* ID out of range means no suitable pool in the container. */
5422         if (id > cmng->max_id || id < cmng->min_id)
5423                 goto out;
5424         /*
5425          * Find the pool from the end of the container, since mostly counter
5426          * ID is sequence increasing, and the last pool should be the needed
5427          * one.
5428          */
5429         i = cmng->n_valid;
5430         while (i--) {
5431                 struct mlx5_flow_counter_pool *pool_tmp = cmng->pools[i];
5432
5433                 if (flow_dv_is_counter_in_pool(pool_tmp, id)) {
5434                         pool = pool_tmp;
5435                         break;
5436                 }
5437         }
5438 out:
5439         rte_spinlock_unlock(&cmng->pool_update_sl);
5440         return pool;
5441 }
5442
5443 /**
5444  * Resize a counter container.
5445  *
5446  * @param[in] dev
5447  *   Pointer to the Ethernet device structure.
5448  *
5449  * @return
5450  *   0 on success, otherwise negative errno value and rte_errno is set.
5451  */
5452 static int
5453 flow_dv_container_resize(struct rte_eth_dev *dev)
5454 {
5455         struct mlx5_priv *priv = dev->data->dev_private;
5456         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5457         void *old_pools = cmng->pools;
5458         uint32_t resize = cmng->n + MLX5_CNT_CONTAINER_RESIZE;
5459         uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
5460         void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
5461
5462         if (!pools) {
5463                 rte_errno = ENOMEM;
5464                 return -ENOMEM;
5465         }
5466         if (old_pools)
5467                 memcpy(pools, old_pools, cmng->n *
5468                                        sizeof(struct mlx5_flow_counter_pool *));
5469         cmng->n = resize;
5470         cmng->pools = pools;
5471         if (old_pools)
5472                 mlx5_free(old_pools);
5473         return 0;
5474 }
5475
5476 /**
5477  * Query a devx flow counter.
5478  *
5479  * @param[in] dev
5480  *   Pointer to the Ethernet device structure.
5481  * @param[in] cnt
5482  *   Index to the flow counter.
5483  * @param[out] pkts
5484  *   The statistics value of packets.
5485  * @param[out] bytes
5486  *   The statistics value of bytes.
5487  *
5488  * @return
5489  *   0 on success, otherwise a negative errno value and rte_errno is set.
5490  */
5491 static inline int
5492 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
5493                      uint64_t *bytes)
5494 {
5495         struct mlx5_priv *priv = dev->data->dev_private;
5496         struct mlx5_flow_counter_pool *pool = NULL;
5497         struct mlx5_flow_counter *cnt;
5498         int offset;
5499
5500         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
5501         MLX5_ASSERT(pool);
5502         if (priv->sh->cmng.counter_fallback)
5503                 return mlx5_devx_cmd_flow_counter_query(cnt->dcs_when_active, 0,
5504                                         0, pkts, bytes, 0, NULL, NULL, 0);
5505         rte_spinlock_lock(&pool->sl);
5506         if (!pool->raw) {
5507                 *pkts = 0;
5508                 *bytes = 0;
5509         } else {
5510                 offset = MLX5_CNT_ARRAY_IDX(pool, cnt);
5511                 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
5512                 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
5513         }
5514         rte_spinlock_unlock(&pool->sl);
5515         return 0;
5516 }
5517
5518 /**
5519  * Create and initialize a new counter pool.
5520  *
5521  * @param[in] dev
5522  *   Pointer to the Ethernet device structure.
5523  * @param[out] dcs
5524  *   The devX counter handle.
5525  * @param[in] age
5526  *   Whether the pool is for counter that was allocated for aging.
5527  * @param[in/out] cont_cur
5528  *   Pointer to the container pointer, it will be update in pool resize.
5529  *
5530  * @return
5531  *   The pool container pointer on success, NULL otherwise and rte_errno is set.
5532  */
5533 static struct mlx5_flow_counter_pool *
5534 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
5535                     uint32_t age)
5536 {
5537         struct mlx5_priv *priv = dev->data->dev_private;
5538         struct mlx5_flow_counter_pool *pool;
5539         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5540         bool fallback = priv->sh->cmng.counter_fallback;
5541         uint32_t size = sizeof(*pool);
5542
5543         size += MLX5_COUNTERS_PER_POOL * MLX5_CNT_SIZE;
5544         size += (!age ? 0 : MLX5_COUNTERS_PER_POOL * MLX5_AGE_SIZE);
5545         pool = mlx5_malloc(MLX5_MEM_ZERO, size, 0, SOCKET_ID_ANY);
5546         if (!pool) {
5547                 rte_errno = ENOMEM;
5548                 return NULL;
5549         }
5550         pool->raw = NULL;
5551         pool->is_aged = !!age;
5552         pool->query_gen = 0;
5553         pool->min_dcs = dcs;
5554         rte_spinlock_init(&pool->sl);
5555         rte_spinlock_init(&pool->csl);
5556         TAILQ_INIT(&pool->counters[0]);
5557         TAILQ_INIT(&pool->counters[1]);
5558         pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
5559         rte_spinlock_lock(&cmng->pool_update_sl);
5560         pool->index = cmng->n_valid;
5561         if (pool->index == cmng->n && flow_dv_container_resize(dev)) {
5562                 mlx5_free(pool);
5563                 rte_spinlock_unlock(&cmng->pool_update_sl);
5564                 return NULL;
5565         }
5566         cmng->pools[pool->index] = pool;
5567         cmng->n_valid++;
5568         if (unlikely(fallback)) {
5569                 int base = RTE_ALIGN_FLOOR(dcs->id, MLX5_COUNTERS_PER_POOL);
5570
5571                 if (base < cmng->min_id)
5572                         cmng->min_id = base;
5573                 if (base > cmng->max_id)
5574                         cmng->max_id = base + MLX5_COUNTERS_PER_POOL - 1;
5575                 cmng->last_pool_idx = pool->index;
5576         }
5577         rte_spinlock_unlock(&cmng->pool_update_sl);
5578         return pool;
5579 }
5580
5581 /**
5582  * Prepare a new counter and/or a new counter pool.
5583  *
5584  * @param[in] dev
5585  *   Pointer to the Ethernet device structure.
5586  * @param[out] cnt_free
5587  *   Where to put the pointer of a new counter.
5588  * @param[in] age
5589  *   Whether the pool is for counter that was allocated for aging.
5590  *
5591  * @return
5592  *   The counter pool pointer and @p cnt_free is set on success,
5593  *   NULL otherwise and rte_errno is set.
5594  */
5595 static struct mlx5_flow_counter_pool *
5596 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
5597                              struct mlx5_flow_counter **cnt_free,
5598                              uint32_t age)
5599 {
5600         struct mlx5_priv *priv = dev->data->dev_private;
5601         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5602         struct mlx5_flow_counter_pool *pool;
5603         struct mlx5_counters tmp_tq;
5604         struct mlx5_devx_obj *dcs = NULL;
5605         struct mlx5_flow_counter *cnt;
5606         enum mlx5_counter_type cnt_type =
5607                         age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
5608         bool fallback = priv->sh->cmng.counter_fallback;
5609         uint32_t i;
5610
5611         if (fallback) {
5612                 /* bulk_bitmap must be 0 for single counter allocation. */
5613                 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
5614                 if (!dcs)
5615                         return NULL;
5616                 pool = flow_dv_find_pool_by_id(cmng, dcs->id);
5617                 if (!pool) {
5618                         pool = flow_dv_pool_create(dev, dcs, age);
5619                         if (!pool) {
5620                                 mlx5_devx_cmd_destroy(dcs);
5621                                 return NULL;
5622                         }
5623                 }
5624                 i = dcs->id % MLX5_COUNTERS_PER_POOL;
5625                 cnt = MLX5_POOL_GET_CNT(pool, i);
5626                 cnt->pool = pool;
5627                 cnt->dcs_when_free = dcs;
5628                 *cnt_free = cnt;
5629                 return pool;
5630         }
5631         dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
5632         if (!dcs) {
5633                 rte_errno = ENODATA;
5634                 return NULL;
5635         }
5636         pool = flow_dv_pool_create(dev, dcs, age);
5637         if (!pool) {
5638                 mlx5_devx_cmd_destroy(dcs);
5639                 return NULL;
5640         }
5641         TAILQ_INIT(&tmp_tq);
5642         for (i = 1; i < MLX5_COUNTERS_PER_POOL; ++i) {
5643                 cnt = MLX5_POOL_GET_CNT(pool, i);
5644                 cnt->pool = pool;
5645                 TAILQ_INSERT_HEAD(&tmp_tq, cnt, next);
5646         }
5647         rte_spinlock_lock(&cmng->csl[cnt_type]);
5648         TAILQ_CONCAT(&cmng->counters[cnt_type], &tmp_tq, next);
5649         rte_spinlock_unlock(&cmng->csl[cnt_type]);
5650         *cnt_free = MLX5_POOL_GET_CNT(pool, 0);
5651         (*cnt_free)->pool = pool;
5652         return pool;
5653 }
5654
5655 /**
5656  * Allocate a flow counter.
5657  *
5658  * @param[in] dev
5659  *   Pointer to the Ethernet device structure.
5660  * @param[in] age
5661  *   Whether the counter was allocated for aging.
5662  *
5663  * @return
5664  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
5665  */
5666 static uint32_t
5667 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t age)
5668 {
5669         struct mlx5_priv *priv = dev->data->dev_private;
5670         struct mlx5_flow_counter_pool *pool = NULL;
5671         struct mlx5_flow_counter *cnt_free = NULL;
5672         bool fallback = priv->sh->cmng.counter_fallback;
5673         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5674         enum mlx5_counter_type cnt_type =
5675                         age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
5676         uint32_t cnt_idx;
5677
5678         if (!priv->config.devx) {
5679                 rte_errno = ENOTSUP;
5680                 return 0;
5681         }
5682         /* Get free counters from container. */
5683         rte_spinlock_lock(&cmng->csl[cnt_type]);
5684         cnt_free = TAILQ_FIRST(&cmng->counters[cnt_type]);
5685         if (cnt_free)
5686                 TAILQ_REMOVE(&cmng->counters[cnt_type], cnt_free, next);
5687         rte_spinlock_unlock(&cmng->csl[cnt_type]);
5688         if (!cnt_free && !flow_dv_counter_pool_prepare(dev, &cnt_free, age))
5689                 goto err;
5690         pool = cnt_free->pool;
5691         if (fallback)
5692                 cnt_free->dcs_when_active = cnt_free->dcs_when_free;
5693         /* Create a DV counter action only in the first time usage. */
5694         if (!cnt_free->action) {
5695                 uint16_t offset;
5696                 struct mlx5_devx_obj *dcs;
5697                 int ret;
5698
5699                 if (!fallback) {
5700                         offset = MLX5_CNT_ARRAY_IDX(pool, cnt_free);
5701                         dcs = pool->min_dcs;
5702                 } else {
5703                         offset = 0;
5704                         dcs = cnt_free->dcs_when_free;
5705                 }
5706                 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, offset,
5707                                                             &cnt_free->action);
5708                 if (ret) {
5709                         rte_errno = errno;
5710                         goto err;
5711                 }
5712         }
5713         cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
5714                                 MLX5_CNT_ARRAY_IDX(pool, cnt_free));
5715         /* Update the counter reset values. */
5716         if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
5717                                  &cnt_free->bytes))
5718                 goto err;
5719         if (!fallback && !priv->sh->cmng.query_thread_on)
5720                 /* Start the asynchronous batch query by the host thread. */
5721                 mlx5_set_query_alarm(priv->sh);
5722         return cnt_idx;
5723 err:
5724         if (cnt_free) {
5725                 cnt_free->pool = pool;
5726                 if (fallback)
5727                         cnt_free->dcs_when_free = cnt_free->dcs_when_active;
5728                 rte_spinlock_lock(&cmng->csl[cnt_type]);
5729                 TAILQ_INSERT_TAIL(&cmng->counters[cnt_type], cnt_free, next);
5730                 rte_spinlock_unlock(&cmng->csl[cnt_type]);
5731         }
5732         return 0;
5733 }
5734
5735 /**
5736  * Allocate a shared flow counter.
5737  *
5738  * @param[in] ctx
5739  *   Pointer to the shared counter configuration.
5740  * @param[in] data
5741  *   Pointer to save the allocated counter index.
5742  *
5743  * @return
5744  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
5745  */
5746
5747 static int32_t
5748 flow_dv_counter_alloc_shared_cb(void *ctx, union mlx5_l3t_data *data)
5749 {
5750         struct mlx5_shared_counter_conf *conf = ctx;
5751         struct rte_eth_dev *dev = conf->dev;
5752         struct mlx5_flow_counter *cnt;
5753
5754         data->dword = flow_dv_counter_alloc(dev, 0);
5755         data->dword |= MLX5_CNT_SHARED_OFFSET;
5756         cnt = flow_dv_counter_get_by_idx(dev, data->dword, NULL);
5757         cnt->shared_info.id = conf->id;
5758         return 0;
5759 }
5760
5761 /**
5762  * Get a shared flow counter.
5763  *
5764  * @param[in] dev
5765  *   Pointer to the Ethernet device structure.
5766  * @param[in] id
5767  *   Counter identifier.
5768  *
5769  * @return
5770  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
5771  */
5772 static uint32_t
5773 flow_dv_counter_get_shared(struct rte_eth_dev *dev, uint32_t id)
5774 {
5775         struct mlx5_priv *priv = dev->data->dev_private;
5776         struct mlx5_shared_counter_conf conf = {
5777                 .dev = dev,
5778                 .id = id,
5779         };
5780         union mlx5_l3t_data data = {
5781                 .dword = 0,
5782         };
5783
5784         mlx5_l3t_prepare_entry(priv->sh->cnt_id_tbl, id, &data,
5785                                flow_dv_counter_alloc_shared_cb, &conf);
5786         return data.dword;
5787 }
5788
5789 /**
5790  * Get age param from counter index.
5791  *
5792  * @param[in] dev
5793  *   Pointer to the Ethernet device structure.
5794  * @param[in] counter
5795  *   Index to the counter handler.
5796  *
5797  * @return
5798  *   The aging parameter specified for the counter index.
5799  */
5800 static struct mlx5_age_param*
5801 flow_dv_counter_idx_get_age(struct rte_eth_dev *dev,
5802                                 uint32_t counter)
5803 {
5804         struct mlx5_flow_counter *cnt;
5805         struct mlx5_flow_counter_pool *pool = NULL;
5806
5807         flow_dv_counter_get_by_idx(dev, counter, &pool);
5808         counter = (counter - 1) % MLX5_COUNTERS_PER_POOL;
5809         cnt = MLX5_POOL_GET_CNT(pool, counter);
5810         return MLX5_CNT_TO_AGE(cnt);
5811 }
5812
5813 /**
5814  * Remove a flow counter from aged counter list.
5815  *
5816  * @param[in] dev
5817  *   Pointer to the Ethernet device structure.
5818  * @param[in] counter
5819  *   Index to the counter handler.
5820  * @param[in] cnt
5821  *   Pointer to the counter handler.
5822  */
5823 static void
5824 flow_dv_counter_remove_from_age(struct rte_eth_dev *dev,
5825                                 uint32_t counter, struct mlx5_flow_counter *cnt)
5826 {
5827         struct mlx5_age_info *age_info;
5828         struct mlx5_age_param *age_param;
5829         struct mlx5_priv *priv = dev->data->dev_private;
5830         uint16_t expected = AGE_CANDIDATE;
5831
5832         age_info = GET_PORT_AGE_INFO(priv);
5833         age_param = flow_dv_counter_idx_get_age(dev, counter);
5834         if (!__atomic_compare_exchange_n(&age_param->state, &expected,
5835                                          AGE_FREE, false, __ATOMIC_RELAXED,
5836                                          __ATOMIC_RELAXED)) {
5837                 /**
5838                  * We need the lock even it is age timeout,
5839                  * since counter may still in process.
5840                  */
5841                 rte_spinlock_lock(&age_info->aged_sl);
5842                 TAILQ_REMOVE(&age_info->aged_counters, cnt, next);
5843                 rte_spinlock_unlock(&age_info->aged_sl);
5844                 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
5845         }
5846 }
5847
5848 /**
5849  * Release a flow counter.
5850  *
5851  * @param[in] dev
5852  *   Pointer to the Ethernet device structure.
5853  * @param[in] counter
5854  *   Index to the counter handler.
5855  */
5856 static void
5857 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t counter)
5858 {
5859         struct mlx5_priv *priv = dev->data->dev_private;
5860         struct mlx5_flow_counter_pool *pool = NULL;
5861         struct mlx5_flow_counter *cnt;
5862         enum mlx5_counter_type cnt_type;
5863
5864         if (!counter)
5865                 return;
5866         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
5867         MLX5_ASSERT(pool);
5868         if (IS_SHARED_CNT(counter) &&
5869             mlx5_l3t_clear_entry(priv->sh->cnt_id_tbl, cnt->shared_info.id))
5870                 return;
5871         if (pool->is_aged)
5872                 flow_dv_counter_remove_from_age(dev, counter, cnt);
5873         cnt->pool = pool;
5874         /*
5875          * Put the counter back to list to be updated in none fallback mode.
5876          * Currently, we are using two list alternately, while one is in query,
5877          * add the freed counter to the other list based on the pool query_gen
5878          * value. After query finishes, add counter the list to the global
5879          * container counter list. The list changes while query starts. In
5880          * this case, lock will not be needed as query callback and release
5881          * function both operate with the different list.
5882          *
5883          */
5884         if (!priv->sh->cmng.counter_fallback) {
5885                 rte_spinlock_lock(&pool->csl);
5886                 TAILQ_INSERT_TAIL(&pool->counters[pool->query_gen], cnt, next);
5887                 rte_spinlock_unlock(&pool->csl);
5888         } else {
5889                 cnt->dcs_when_free = cnt->dcs_when_active;
5890                 cnt_type = pool->is_aged ? MLX5_COUNTER_TYPE_AGE :
5891                                            MLX5_COUNTER_TYPE_ORIGIN;
5892                 rte_spinlock_lock(&priv->sh->cmng.csl[cnt_type]);
5893                 TAILQ_INSERT_TAIL(&priv->sh->cmng.counters[cnt_type],
5894                                   cnt, next);
5895                 rte_spinlock_unlock(&priv->sh->cmng.csl[cnt_type]);
5896         }
5897 }
5898
5899 /**
5900  * Verify the @p attributes will be correctly understood by the NIC and store
5901  * them in the @p flow if everything is correct.
5902  *
5903  * @param[in] dev
5904  *   Pointer to dev struct.
5905  * @param[in] attributes
5906  *   Pointer to flow attributes
5907  * @param[in] external
5908  *   This flow rule is created by request external to PMD.
5909  * @param[out] error
5910  *   Pointer to error structure.
5911  *
5912  * @return
5913  *   - 0 on success and non root table.
5914  *   - 1 on success and root table.
5915  *   - a negative errno value otherwise and rte_errno is set.
5916  */
5917 static int
5918 flow_dv_validate_attributes(struct rte_eth_dev *dev,
5919                             const struct mlx5_flow_tunnel *tunnel,
5920                             const struct rte_flow_attr *attributes,
5921                             const struct flow_grp_info *grp_info,
5922                             struct rte_flow_error *error)
5923 {
5924         struct mlx5_priv *priv = dev->data->dev_private;
5925         uint32_t lowest_priority = mlx5_get_lowest_priority(dev, attributes);
5926         int ret = 0;
5927
5928 #ifndef HAVE_MLX5DV_DR
5929         RTE_SET_USED(tunnel);
5930         RTE_SET_USED(grp_info);
5931         if (attributes->group)
5932                 return rte_flow_error_set(error, ENOTSUP,
5933                                           RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
5934                                           NULL,
5935                                           "groups are not supported");
5936 #else
5937         uint32_t table = 0;
5938
5939         ret = mlx5_flow_group_to_table(dev, tunnel, attributes->group, &table,
5940                                        grp_info, error);
5941         if (ret)
5942                 return ret;
5943         if (!table)
5944                 ret = MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
5945 #endif
5946         if (attributes->priority != MLX5_FLOW_LOWEST_PRIO_INDICATOR &&
5947             attributes->priority > lowest_priority)
5948                 return rte_flow_error_set(error, ENOTSUP,
5949                                           RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
5950                                           NULL,
5951                                           "priority out of range");
5952         if (attributes->transfer) {
5953                 if (!priv->config.dv_esw_en)
5954                         return rte_flow_error_set
5955                                 (error, ENOTSUP,
5956                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5957                                  "E-Switch dr is not supported");
5958                 if (!(priv->representor || priv->master))
5959                         return rte_flow_error_set
5960                                 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5961                                  NULL, "E-Switch configuration can only be"
5962                                  " done by a master or a representor device");
5963                 if (attributes->egress)
5964                         return rte_flow_error_set
5965                                 (error, ENOTSUP,
5966                                  RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
5967                                  "egress is not supported");
5968         }
5969         if (!(attributes->egress ^ attributes->ingress))
5970                 return rte_flow_error_set(error, ENOTSUP,
5971                                           RTE_FLOW_ERROR_TYPE_ATTR, NULL,
5972                                           "must specify exactly one of "
5973                                           "ingress or egress");
5974         return ret;
5975 }
5976
5977 /**
5978  * Internal validation function. For validating both actions and items.
5979  *
5980  * @param[in] dev
5981  *   Pointer to the rte_eth_dev structure.
5982  * @param[in] attr
5983  *   Pointer to the flow attributes.
5984  * @param[in] items
5985  *   Pointer to the list of items.
5986  * @param[in] actions
5987  *   Pointer to the list of actions.
5988  * @param[in] external
5989  *   This flow rule is created by request external to PMD.
5990  * @param[in] hairpin
5991  *   Number of hairpin TX actions, 0 means classic flow.
5992  * @param[out] error
5993  *   Pointer to the error structure.
5994  *
5995  * @return
5996  *   0 on success, a negative errno value otherwise and rte_errno is set.
5997  */
5998 static int
5999 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
6000                  const struct rte_flow_item items[],
6001                  const struct rte_flow_action actions[],
6002                  bool external, int hairpin, struct rte_flow_error *error)
6003 {
6004         int ret;
6005         uint64_t action_flags = 0;
6006         uint64_t item_flags = 0;
6007         uint64_t last_item = 0;
6008         uint8_t next_protocol = 0xff;
6009         uint16_t ether_type = 0;
6010         int actions_n = 0;
6011         uint8_t item_ipv6_proto = 0;
6012         int fdb_mirror_limit = 0;
6013         int modify_after_mirror = 0;
6014         const struct rte_flow_item *geneve_item = NULL;
6015         const struct rte_flow_item *gre_item = NULL;
6016         const struct rte_flow_item *gtp_item = NULL;
6017         const struct rte_flow_action_raw_decap *decap;
6018         const struct rte_flow_action_raw_encap *encap;
6019         const struct rte_flow_action_rss *rss = NULL;
6020         const struct rte_flow_action_rss *sample_rss = NULL;
6021         const struct rte_flow_action_count *count = NULL;
6022         const struct rte_flow_action_count *sample_count = NULL;
6023         const struct rte_flow_item_tcp nic_tcp_mask = {
6024                 .hdr = {
6025                         .tcp_flags = 0xFF,
6026                         .src_port = RTE_BE16(UINT16_MAX),
6027                         .dst_port = RTE_BE16(UINT16_MAX),
6028                 }
6029         };
6030         const struct rte_flow_item_ipv6 nic_ipv6_mask = {
6031                 .hdr = {
6032                         .src_addr =
6033                         "\xff\xff\xff\xff\xff\xff\xff\xff"
6034                         "\xff\xff\xff\xff\xff\xff\xff\xff",
6035                         .dst_addr =
6036                         "\xff\xff\xff\xff\xff\xff\xff\xff"
6037                         "\xff\xff\xff\xff\xff\xff\xff\xff",
6038                         .vtc_flow = RTE_BE32(0xffffffff),
6039                         .proto = 0xff,
6040                         .hop_limits = 0xff,
6041                 },
6042                 .has_frag_ext = 1,
6043         };
6044         const struct rte_flow_item_ecpri nic_ecpri_mask = {
6045                 .hdr = {
6046                         .common = {
6047                                 .u32 =
6048                                 RTE_BE32(((const struct rte_ecpri_common_hdr) {
6049                                         .type = 0xFF,
6050                                         }).u32),
6051                         },
6052                         .dummy[0] = 0xffffffff,
6053                 },
6054         };
6055         struct mlx5_priv *priv = dev->data->dev_private;
6056         struct mlx5_dev_config *dev_conf = &priv->config;
6057         uint16_t queue_index = 0xFFFF;
6058         const struct rte_flow_item_vlan *vlan_m = NULL;
6059         uint32_t rw_act_num = 0;
6060         uint64_t is_root;
6061         const struct mlx5_flow_tunnel *tunnel;
6062         struct flow_grp_info grp_info = {
6063                 .external = !!external,
6064                 .transfer = !!attr->transfer,
6065                 .fdb_def_rule = !!priv->fdb_def_rule,
6066         };
6067         const struct rte_eth_hairpin_conf *conf;
6068
6069         if (items == NULL)
6070                 return -1;
6071         if (is_flow_tunnel_match_rule(dev, attr, items, actions)) {
6072                 tunnel = flow_items_to_tunnel(items);
6073                 action_flags |= MLX5_FLOW_ACTION_TUNNEL_MATCH |
6074                                 MLX5_FLOW_ACTION_DECAP;
6075         } else if (is_flow_tunnel_steer_rule(dev, attr, items, actions)) {
6076                 tunnel = flow_actions_to_tunnel(actions);
6077                 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
6078         } else {
6079                 tunnel = NULL;
6080         }
6081         if (tunnel && priv->representor)
6082                 return rte_flow_error_set(error, ENOTSUP,
6083                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6084                                           "decap not supported "
6085                                           "for VF representor");
6086         grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
6087                                 (dev, tunnel, attr, items, actions);
6088         ret = flow_dv_validate_attributes(dev, tunnel, attr, &grp_info, error);
6089         if (ret < 0)
6090                 return ret;
6091         is_root = (uint64_t)ret;
6092         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
6093                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
6094                 int type = items->type;
6095
6096                 if (!mlx5_flow_os_item_supported(type))
6097                         return rte_flow_error_set(error, ENOTSUP,
6098                                                   RTE_FLOW_ERROR_TYPE_ITEM,
6099                                                   NULL, "item not supported");
6100                 switch (type) {
6101                 case MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL:
6102                         if (items[0].type != (typeof(items[0].type))
6103                                                 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL)
6104                                 return rte_flow_error_set
6105                                                 (error, EINVAL,
6106                                                 RTE_FLOW_ERROR_TYPE_ITEM,
6107                                                 NULL, "MLX5 private items "
6108                                                 "must be the first");
6109                         break;
6110                 case RTE_FLOW_ITEM_TYPE_VOID:
6111                         break;
6112                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
6113                         ret = flow_dv_validate_item_port_id
6114                                         (dev, items, attr, item_flags, error);
6115                         if (ret < 0)
6116                                 return ret;
6117                         last_item = MLX5_FLOW_ITEM_PORT_ID;
6118                         break;
6119                 case RTE_FLOW_ITEM_TYPE_ETH:
6120                         ret = mlx5_flow_validate_item_eth(items, item_flags,
6121                                                           true, error);
6122                         if (ret < 0)
6123                                 return ret;
6124                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
6125                                              MLX5_FLOW_LAYER_OUTER_L2;
6126                         if (items->mask != NULL && items->spec != NULL) {
6127                                 ether_type =
6128                                         ((const struct rte_flow_item_eth *)
6129                                          items->spec)->type;
6130                                 ether_type &=
6131                                         ((const struct rte_flow_item_eth *)
6132                                          items->mask)->type;
6133                                 ether_type = rte_be_to_cpu_16(ether_type);
6134                         } else {
6135                                 ether_type = 0;
6136                         }
6137                         break;
6138                 case RTE_FLOW_ITEM_TYPE_VLAN:
6139                         ret = flow_dv_validate_item_vlan(items, item_flags,
6140                                                          dev, error);
6141                         if (ret < 0)
6142                                 return ret;
6143                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
6144                                              MLX5_FLOW_LAYER_OUTER_VLAN;
6145                         if (items->mask != NULL && items->spec != NULL) {
6146                                 ether_type =
6147                                         ((const struct rte_flow_item_vlan *)
6148                                          items->spec)->inner_type;
6149                                 ether_type &=
6150                                         ((const struct rte_flow_item_vlan *)
6151                                          items->mask)->inner_type;
6152                                 ether_type = rte_be_to_cpu_16(ether_type);
6153                         } else {
6154                                 ether_type = 0;
6155                         }
6156                         /* Store outer VLAN mask for of_push_vlan action. */
6157                         if (!tunnel)
6158                                 vlan_m = items->mask;
6159                         break;
6160                 case RTE_FLOW_ITEM_TYPE_IPV4:
6161                         mlx5_flow_tunnel_ip_check(items, next_protocol,
6162                                                   &item_flags, &tunnel);
6163                         ret = flow_dv_validate_item_ipv4(items, item_flags,
6164                                                          last_item, ether_type,
6165                                                          error);
6166                         if (ret < 0)
6167                                 return ret;
6168                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
6169                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
6170                         if (items->mask != NULL &&
6171                             ((const struct rte_flow_item_ipv4 *)
6172                              items->mask)->hdr.next_proto_id) {
6173                                 next_protocol =
6174                                         ((const struct rte_flow_item_ipv4 *)
6175                                          (items->spec))->hdr.next_proto_id;
6176                                 next_protocol &=
6177                                         ((const struct rte_flow_item_ipv4 *)
6178                                          (items->mask))->hdr.next_proto_id;
6179                         } else {
6180                                 /* Reset for inner layer. */
6181                                 next_protocol = 0xff;
6182                         }
6183                         break;
6184                 case RTE_FLOW_ITEM_TYPE_IPV6:
6185                         mlx5_flow_tunnel_ip_check(items, next_protocol,
6186                                                   &item_flags, &tunnel);
6187                         ret = mlx5_flow_validate_item_ipv6(items, item_flags,
6188                                                            last_item,
6189                                                            ether_type,
6190                                                            &nic_ipv6_mask,
6191                                                            error);
6192                         if (ret < 0)
6193                                 return ret;
6194                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
6195                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
6196                         if (items->mask != NULL &&
6197                             ((const struct rte_flow_item_ipv6 *)
6198                              items->mask)->hdr.proto) {
6199                                 item_ipv6_proto =
6200                                         ((const struct rte_flow_item_ipv6 *)
6201                                          items->spec)->hdr.proto;
6202                                 next_protocol =
6203                                         ((const struct rte_flow_item_ipv6 *)
6204                                          items->spec)->hdr.proto;
6205                                 next_protocol &=
6206                                         ((const struct rte_flow_item_ipv6 *)
6207                                          items->mask)->hdr.proto;
6208                         } else {
6209                                 /* Reset for inner layer. */
6210                                 next_protocol = 0xff;
6211                         }
6212                         break;
6213                 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
6214                         ret = flow_dv_validate_item_ipv6_frag_ext(items,
6215                                                                   item_flags,
6216                                                                   error);
6217                         if (ret < 0)
6218                                 return ret;
6219                         last_item = tunnel ?
6220                                         MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
6221                                         MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
6222                         if (items->mask != NULL &&
6223                             ((const struct rte_flow_item_ipv6_frag_ext *)
6224                              items->mask)->hdr.next_header) {
6225                                 next_protocol =
6226                                 ((const struct rte_flow_item_ipv6_frag_ext *)
6227                                  items->spec)->hdr.next_header;
6228                                 next_protocol &=
6229                                 ((const struct rte_flow_item_ipv6_frag_ext *)
6230                                  items->mask)->hdr.next_header;
6231                         } else {
6232                                 /* Reset for inner layer. */
6233                                 next_protocol = 0xff;
6234                         }
6235                         break;
6236                 case RTE_FLOW_ITEM_TYPE_TCP:
6237                         ret = mlx5_flow_validate_item_tcp
6238                                                 (items, item_flags,
6239                                                  next_protocol,
6240                                                  &nic_tcp_mask,
6241                                                  error);
6242                         if (ret < 0)
6243                                 return ret;
6244                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
6245                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
6246                         break;
6247                 case RTE_FLOW_ITEM_TYPE_UDP:
6248                         ret = mlx5_flow_validate_item_udp(items, item_flags,
6249                                                           next_protocol,
6250                                                           error);
6251                         if (ret < 0)
6252                                 return ret;
6253                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
6254                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
6255                         break;
6256                 case RTE_FLOW_ITEM_TYPE_GRE:
6257                         ret = mlx5_flow_validate_item_gre(items, item_flags,
6258                                                           next_protocol, error);
6259                         if (ret < 0)
6260                                 return ret;
6261                         gre_item = items;
6262                         last_item = MLX5_FLOW_LAYER_GRE;
6263                         break;
6264                 case RTE_FLOW_ITEM_TYPE_NVGRE:
6265                         ret = mlx5_flow_validate_item_nvgre(items, item_flags,
6266                                                             next_protocol,
6267                                                             error);
6268                         if (ret < 0)
6269                                 return ret;
6270                         last_item = MLX5_FLOW_LAYER_NVGRE;
6271                         break;
6272                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
6273                         ret = mlx5_flow_validate_item_gre_key
6274                                 (items, item_flags, gre_item, error);
6275                         if (ret < 0)
6276                                 return ret;
6277                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
6278                         break;
6279                 case RTE_FLOW_ITEM_TYPE_VXLAN:
6280                         ret = mlx5_flow_validate_item_vxlan(items, item_flags,
6281                                                             error);
6282                         if (ret < 0)
6283                                 return ret;
6284                         last_item = MLX5_FLOW_LAYER_VXLAN;
6285                         break;
6286                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
6287                         ret = mlx5_flow_validate_item_vxlan_gpe(items,
6288                                                                 item_flags, dev,
6289                                                                 error);
6290                         if (ret < 0)
6291                                 return ret;
6292                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
6293                         break;
6294                 case RTE_FLOW_ITEM_TYPE_GENEVE:
6295                         ret = mlx5_flow_validate_item_geneve(items,
6296                                                              item_flags, dev,
6297                                                              error);
6298                         if (ret < 0)
6299                                 return ret;
6300                         geneve_item = items;
6301                         last_item = MLX5_FLOW_LAYER_GENEVE;
6302                         break;
6303                 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
6304                         ret = mlx5_flow_validate_item_geneve_opt(items,
6305                                                                  last_item,
6306                                                                  geneve_item,
6307                                                                  dev,
6308                                                                  error);
6309                         if (ret < 0)
6310                                 return ret;
6311                         last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
6312                         break;
6313                 case RTE_FLOW_ITEM_TYPE_MPLS:
6314                         ret = mlx5_flow_validate_item_mpls(dev, items,
6315                                                            item_flags,
6316                                                            last_item, error);
6317                         if (ret < 0)
6318                                 return ret;
6319                         last_item = MLX5_FLOW_LAYER_MPLS;
6320                         break;
6321
6322                 case RTE_FLOW_ITEM_TYPE_MARK:
6323                         ret = flow_dv_validate_item_mark(dev, items, attr,
6324                                                          error);
6325                         if (ret < 0)
6326                                 return ret;
6327                         last_item = MLX5_FLOW_ITEM_MARK;
6328                         break;
6329                 case RTE_FLOW_ITEM_TYPE_META:
6330                         ret = flow_dv_validate_item_meta(dev, items, attr,
6331                                                          error);
6332                         if (ret < 0)
6333                                 return ret;
6334                         last_item = MLX5_FLOW_ITEM_METADATA;
6335                         break;
6336                 case RTE_FLOW_ITEM_TYPE_ICMP:
6337                         ret = mlx5_flow_validate_item_icmp(items, item_flags,
6338                                                            next_protocol,
6339                                                            error);
6340                         if (ret < 0)
6341                                 return ret;
6342                         last_item = MLX5_FLOW_LAYER_ICMP;
6343                         break;
6344                 case RTE_FLOW_ITEM_TYPE_ICMP6:
6345                         ret = mlx5_flow_validate_item_icmp6(items, item_flags,
6346                                                             next_protocol,
6347                                                             error);
6348                         if (ret < 0)
6349                                 return ret;
6350                         item_ipv6_proto = IPPROTO_ICMPV6;
6351                         last_item = MLX5_FLOW_LAYER_ICMP6;
6352                         break;
6353                 case RTE_FLOW_ITEM_TYPE_TAG:
6354                         ret = flow_dv_validate_item_tag(dev, items,
6355                                                         attr, error);
6356                         if (ret < 0)
6357                                 return ret;
6358                         last_item = MLX5_FLOW_ITEM_TAG;
6359                         break;
6360                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
6361                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
6362                         break;
6363                 case RTE_FLOW_ITEM_TYPE_GTP:
6364                         ret = flow_dv_validate_item_gtp(dev, items, item_flags,
6365                                                         error);
6366                         if (ret < 0)
6367                                 return ret;
6368                         gtp_item = items;
6369                         last_item = MLX5_FLOW_LAYER_GTP;
6370                         break;
6371                 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
6372                         ret = flow_dv_validate_item_gtp_psc(items, last_item,
6373                                                             gtp_item, attr,
6374                                                             error);
6375                         if (ret < 0)
6376                                 return ret;
6377                         last_item = MLX5_FLOW_LAYER_GTP_PSC;
6378                         break;
6379                 case RTE_FLOW_ITEM_TYPE_ECPRI:
6380                         /* Capacity will be checked in the translate stage. */
6381                         ret = mlx5_flow_validate_item_ecpri(items, item_flags,
6382                                                             last_item,
6383                                                             ether_type,
6384                                                             &nic_ecpri_mask,
6385                                                             error);
6386                         if (ret < 0)
6387                                 return ret;
6388                         last_item = MLX5_FLOW_LAYER_ECPRI;
6389                         break;
6390                 default:
6391                         return rte_flow_error_set(error, ENOTSUP,
6392                                                   RTE_FLOW_ERROR_TYPE_ITEM,
6393                                                   NULL, "item not supported");
6394                 }
6395                 item_flags |= last_item;
6396         }
6397         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
6398                 int type = actions->type;
6399
6400                 if (!mlx5_flow_os_action_supported(type))
6401                         return rte_flow_error_set(error, ENOTSUP,
6402                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6403                                                   actions,
6404                                                   "action not supported");
6405                 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
6406                         return rte_flow_error_set(error, ENOTSUP,
6407                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6408                                                   actions, "too many actions");
6409                 switch (type) {
6410                 case RTE_FLOW_ACTION_TYPE_VOID:
6411                         break;
6412                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
6413                         ret = flow_dv_validate_action_port_id(dev,
6414                                                               action_flags,
6415                                                               actions,
6416                                                               attr,
6417                                                               error);
6418                         if (ret)
6419                                 return ret;
6420                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
6421                         ++actions_n;
6422                         break;
6423                 case RTE_FLOW_ACTION_TYPE_FLAG:
6424                         ret = flow_dv_validate_action_flag(dev, action_flags,
6425                                                            attr, error);
6426                         if (ret < 0)
6427                                 return ret;
6428                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
6429                                 /* Count all modify-header actions as one. */
6430                                 if (!(action_flags &
6431                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
6432                                         ++actions_n;
6433                                 action_flags |= MLX5_FLOW_ACTION_FLAG |
6434                                                 MLX5_FLOW_ACTION_MARK_EXT;
6435                                 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6436                                         modify_after_mirror = 1;
6437
6438                         } else {
6439                                 action_flags |= MLX5_FLOW_ACTION_FLAG;
6440                                 ++actions_n;
6441                         }
6442                         rw_act_num += MLX5_ACT_NUM_SET_MARK;
6443                         break;
6444                 case RTE_FLOW_ACTION_TYPE_MARK:
6445                         ret = flow_dv_validate_action_mark(dev, actions,
6446                                                            action_flags,
6447                                                            attr, error);
6448                         if (ret < 0)
6449                                 return ret;
6450                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
6451                                 /* Count all modify-header actions as one. */
6452                                 if (!(action_flags &
6453                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
6454                                         ++actions_n;
6455                                 action_flags |= MLX5_FLOW_ACTION_MARK |
6456                                                 MLX5_FLOW_ACTION_MARK_EXT;
6457                                 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6458                                         modify_after_mirror = 1;
6459                         } else {
6460                                 action_flags |= MLX5_FLOW_ACTION_MARK;
6461                                 ++actions_n;
6462                         }
6463                         rw_act_num += MLX5_ACT_NUM_SET_MARK;
6464                         break;
6465                 case RTE_FLOW_ACTION_TYPE_SET_META:
6466                         ret = flow_dv_validate_action_set_meta(dev, actions,
6467                                                                action_flags,
6468                                                                attr, error);
6469                         if (ret < 0)
6470                                 return ret;
6471                         /* Count all modify-header actions as one action. */
6472                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6473                                 ++actions_n;
6474                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6475                                 modify_after_mirror = 1;
6476                         action_flags |= MLX5_FLOW_ACTION_SET_META;
6477                         rw_act_num += MLX5_ACT_NUM_SET_META;
6478                         break;
6479                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
6480                         ret = flow_dv_validate_action_set_tag(dev, actions,
6481                                                               action_flags,
6482                                                               attr, error);
6483                         if (ret < 0)
6484                                 return ret;
6485                         /* Count all modify-header actions as one action. */
6486                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6487                                 ++actions_n;
6488                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6489                                 modify_after_mirror = 1;
6490                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
6491                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
6492                         break;
6493                 case RTE_FLOW_ACTION_TYPE_DROP:
6494                         ret = mlx5_flow_validate_action_drop(action_flags,
6495                                                              attr, error);
6496                         if (ret < 0)
6497                                 return ret;
6498                         action_flags |= MLX5_FLOW_ACTION_DROP;
6499                         ++actions_n;
6500                         break;
6501                 case RTE_FLOW_ACTION_TYPE_QUEUE:
6502                         ret = mlx5_flow_validate_action_queue(actions,
6503                                                               action_flags, dev,
6504                                                               attr, error);
6505                         if (ret < 0)
6506                                 return ret;
6507                         queue_index = ((const struct rte_flow_action_queue *)
6508                                                         (actions->conf))->index;
6509                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
6510                         ++actions_n;
6511                         break;
6512                 case RTE_FLOW_ACTION_TYPE_RSS:
6513                         rss = actions->conf;
6514                         ret = mlx5_flow_validate_action_rss(actions,
6515                                                             action_flags, dev,
6516                                                             attr, item_flags,
6517                                                             error);
6518                         if (ret < 0)
6519                                 return ret;
6520                         if (rss && sample_rss &&
6521                             (sample_rss->level != rss->level ||
6522                             sample_rss->types != rss->types))
6523                                 return rte_flow_error_set(error, ENOTSUP,
6524                                         RTE_FLOW_ERROR_TYPE_ACTION,
6525                                         NULL,
6526                                         "Can't use the different RSS types "
6527                                         "or level in the same flow");
6528                         if (rss != NULL && rss->queue_num)
6529                                 queue_index = rss->queue[0];
6530                         action_flags |= MLX5_FLOW_ACTION_RSS;
6531                         ++actions_n;
6532                         break;
6533                 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
6534                         ret =
6535                         mlx5_flow_validate_action_default_miss(action_flags,
6536                                         attr, error);
6537                         if (ret < 0)
6538                                 return ret;
6539                         action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
6540                         ++actions_n;
6541                         break;
6542                 case RTE_FLOW_ACTION_TYPE_COUNT:
6543                         ret = flow_dv_validate_action_count(dev, actions,
6544                                                             action_flags,
6545                                                             error);
6546                         if (ret < 0)
6547                                 return ret;
6548                         count = actions->conf;
6549                         action_flags |= MLX5_FLOW_ACTION_COUNT;
6550                         ++actions_n;
6551                         break;
6552                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
6553                         if (flow_dv_validate_action_pop_vlan(dev,
6554                                                              action_flags,
6555                                                              actions,
6556                                                              item_flags, attr,
6557                                                              error))
6558                                 return -rte_errno;
6559                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
6560                         ++actions_n;
6561                         break;
6562                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
6563                         ret = flow_dv_validate_action_push_vlan(dev,
6564                                                                 action_flags,
6565                                                                 vlan_m,
6566                                                                 actions, attr,
6567                                                                 error);
6568                         if (ret < 0)
6569                                 return ret;
6570                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
6571                         ++actions_n;
6572                         break;
6573                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
6574                         ret = flow_dv_validate_action_set_vlan_pcp
6575                                                 (action_flags, actions, error);
6576                         if (ret < 0)
6577                                 return ret;
6578                         /* Count PCP with push_vlan command. */
6579                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
6580                         break;
6581                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
6582                         ret = flow_dv_validate_action_set_vlan_vid
6583                                                 (item_flags, action_flags,
6584                                                  actions, error);
6585                         if (ret < 0)
6586                                 return ret;
6587                         /* Count VID with push_vlan command. */
6588                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
6589                         rw_act_num += MLX5_ACT_NUM_MDF_VID;
6590                         break;
6591                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
6592                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
6593                         ret = flow_dv_validate_action_l2_encap(dev,
6594                                                                action_flags,
6595                                                                actions, attr,
6596                                                                error);
6597                         if (ret < 0)
6598                                 return ret;
6599                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
6600                         ++actions_n;
6601                         break;
6602                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
6603                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
6604                         ret = flow_dv_validate_action_decap(dev, action_flags,
6605                                                             actions, item_flags,
6606                                                             attr, error);
6607                         if (ret < 0)
6608                                 return ret;
6609                         action_flags |= MLX5_FLOW_ACTION_DECAP;
6610                         ++actions_n;
6611                         break;
6612                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
6613                         ret = flow_dv_validate_action_raw_encap_decap
6614                                 (dev, NULL, actions->conf, attr, &action_flags,
6615                                  &actions_n, actions, item_flags, error);
6616                         if (ret < 0)
6617                                 return ret;
6618                         break;
6619                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
6620                         decap = actions->conf;
6621                         while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
6622                                 ;
6623                         if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
6624                                 encap = NULL;
6625                                 actions--;
6626                         } else {
6627                                 encap = actions->conf;
6628                         }
6629                         ret = flow_dv_validate_action_raw_encap_decap
6630                                            (dev,
6631                                             decap ? decap : &empty_decap, encap,
6632                                             attr, &action_flags, &actions_n,
6633                                             actions, item_flags, error);
6634                         if (ret < 0)
6635                                 return ret;
6636                         break;
6637                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
6638                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
6639                         ret = flow_dv_validate_action_modify_mac(action_flags,
6640                                                                  actions,
6641                                                                  item_flags,
6642                                                                  error);
6643                         if (ret < 0)
6644                                 return ret;
6645                         /* Count all modify-header actions as one action. */
6646                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6647                                 ++actions_n;
6648                         action_flags |= actions->type ==
6649                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
6650                                                 MLX5_FLOW_ACTION_SET_MAC_SRC :
6651                                                 MLX5_FLOW_ACTION_SET_MAC_DST;
6652                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6653                                 modify_after_mirror = 1;
6654                         /*
6655                          * Even if the source and destination MAC addresses have
6656                          * overlap in the header with 4B alignment, the convert
6657                          * function will handle them separately and 4 SW actions
6658                          * will be created. And 2 actions will be added each
6659                          * time no matter how many bytes of address will be set.
6660                          */
6661                         rw_act_num += MLX5_ACT_NUM_MDF_MAC;
6662                         break;
6663                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
6664                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
6665                         ret = flow_dv_validate_action_modify_ipv4(action_flags,
6666                                                                   actions,
6667                                                                   item_flags,
6668                                                                   error);
6669                         if (ret < 0)
6670                                 return ret;
6671                         /* Count all modify-header actions as one action. */
6672                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6673                                 ++actions_n;
6674                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6675                                 modify_after_mirror = 1;
6676                         action_flags |= actions->type ==
6677                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
6678                                                 MLX5_FLOW_ACTION_SET_IPV4_SRC :
6679                                                 MLX5_FLOW_ACTION_SET_IPV4_DST;
6680                         rw_act_num += MLX5_ACT_NUM_MDF_IPV4;
6681                         break;
6682                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
6683                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
6684                         ret = flow_dv_validate_action_modify_ipv6(action_flags,
6685                                                                   actions,
6686                                                                   item_flags,
6687                                                                   error);
6688                         if (ret < 0)
6689                                 return ret;
6690                         if (item_ipv6_proto == IPPROTO_ICMPV6)
6691                                 return rte_flow_error_set(error, ENOTSUP,
6692                                         RTE_FLOW_ERROR_TYPE_ACTION,
6693                                         actions,
6694                                         "Can't change header "
6695                                         "with ICMPv6 proto");
6696                         /* Count all modify-header actions as one action. */
6697                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6698                                 ++actions_n;
6699                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6700                                 modify_after_mirror = 1;
6701                         action_flags |= actions->type ==
6702                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
6703                                                 MLX5_FLOW_ACTION_SET_IPV6_SRC :
6704                                                 MLX5_FLOW_ACTION_SET_IPV6_DST;
6705                         rw_act_num += MLX5_ACT_NUM_MDF_IPV6;
6706                         break;
6707                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
6708                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
6709                         ret = flow_dv_validate_action_modify_tp(action_flags,
6710                                                                 actions,
6711                                                                 item_flags,
6712                                                                 error);
6713                         if (ret < 0)
6714                                 return ret;
6715                         /* Count all modify-header actions as one action. */
6716                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6717                                 ++actions_n;
6718                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6719                                 modify_after_mirror = 1;
6720                         action_flags |= actions->type ==
6721                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
6722                                                 MLX5_FLOW_ACTION_SET_TP_SRC :
6723                                                 MLX5_FLOW_ACTION_SET_TP_DST;
6724                         rw_act_num += MLX5_ACT_NUM_MDF_PORT;
6725                         break;
6726                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
6727                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
6728                         ret = flow_dv_validate_action_modify_ttl(action_flags,
6729                                                                  actions,
6730                                                                  item_flags,
6731                                                                  error);
6732                         if (ret < 0)
6733                                 return ret;
6734                         /* Count all modify-header actions as one action. */
6735                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6736                                 ++actions_n;
6737                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6738                                 modify_after_mirror = 1;
6739                         action_flags |= actions->type ==
6740                                         RTE_FLOW_ACTION_TYPE_SET_TTL ?
6741                                                 MLX5_FLOW_ACTION_SET_TTL :
6742                                                 MLX5_FLOW_ACTION_DEC_TTL;
6743                         rw_act_num += MLX5_ACT_NUM_MDF_TTL;
6744                         break;
6745                 case RTE_FLOW_ACTION_TYPE_JUMP:
6746                         ret = flow_dv_validate_action_jump(dev, tunnel, actions,
6747                                                            action_flags,
6748                                                            attr, external,
6749                                                            error);
6750                         if (ret)
6751                                 return ret;
6752                         if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) &&
6753                             fdb_mirror_limit)
6754                                 return rte_flow_error_set(error, EINVAL,
6755                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6756                                                   NULL,
6757                                                   "sample and jump action combination is not supported");
6758                         ++actions_n;
6759                         action_flags |= MLX5_FLOW_ACTION_JUMP;
6760                         break;
6761                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
6762                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
6763                         ret = flow_dv_validate_action_modify_tcp_seq
6764                                                                 (action_flags,
6765                                                                  actions,
6766                                                                  item_flags,
6767                                                                  error);
6768                         if (ret < 0)
6769                                 return ret;
6770                         /* Count all modify-header actions as one action. */
6771                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6772                                 ++actions_n;
6773                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6774                                 modify_after_mirror = 1;
6775                         action_flags |= actions->type ==
6776                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
6777                                                 MLX5_FLOW_ACTION_INC_TCP_SEQ :
6778                                                 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
6779                         rw_act_num += MLX5_ACT_NUM_MDF_TCPSEQ;
6780                         break;
6781                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
6782                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
6783                         ret = flow_dv_validate_action_modify_tcp_ack
6784                                                                 (action_flags,
6785                                                                  actions,
6786                                                                  item_flags,
6787                                                                  error);
6788                         if (ret < 0)
6789                                 return ret;
6790                         /* Count all modify-header actions as one action. */
6791                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6792                                 ++actions_n;
6793                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6794                                 modify_after_mirror = 1;
6795                         action_flags |= actions->type ==
6796                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
6797                                                 MLX5_FLOW_ACTION_INC_TCP_ACK :
6798                                                 MLX5_FLOW_ACTION_DEC_TCP_ACK;
6799                         rw_act_num += MLX5_ACT_NUM_MDF_TCPACK;
6800                         break;
6801                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
6802                         break;
6803                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
6804                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
6805                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
6806                         break;
6807                 case RTE_FLOW_ACTION_TYPE_METER:
6808                         ret = mlx5_flow_validate_action_meter(dev,
6809                                                               action_flags,
6810                                                               actions, attr,
6811                                                               error);
6812                         if (ret < 0)
6813                                 return ret;
6814                         action_flags |= MLX5_FLOW_ACTION_METER;
6815                         ++actions_n;
6816                         /* Meter action will add one more TAG action. */
6817                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
6818                         break;
6819                 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
6820                         if (!attr->transfer && !attr->group)
6821                                 return rte_flow_error_set(error, ENOTSUP,
6822                                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6823                                                                            NULL,
6824                           "Shared ASO age action is not supported for group 0");
6825                         action_flags |= MLX5_FLOW_ACTION_AGE;
6826                         ++actions_n;
6827                         break;
6828                 case RTE_FLOW_ACTION_TYPE_AGE:
6829                         ret = flow_dv_validate_action_age(action_flags,
6830                                                           actions, dev,
6831                                                           error);
6832                         if (ret < 0)
6833                                 return ret;
6834                         /*
6835                          * Validate the regular AGE action (using counter)
6836                          * mutual exclusion with share counter actions.
6837                          */
6838                         if (!priv->sh->flow_hit_aso_en) {
6839                                 if (count && count->shared)
6840                                         return rte_flow_error_set
6841                                                 (error, EINVAL,
6842                                                 RTE_FLOW_ERROR_TYPE_ACTION,
6843                                                 NULL,
6844                                                 "old age and shared count combination is not supported");
6845                                 if (sample_count)
6846                                         return rte_flow_error_set
6847                                                 (error, EINVAL,
6848                                                 RTE_FLOW_ERROR_TYPE_ACTION,
6849                                                 NULL,
6850                                                 "old age action and count must be in the same sub flow");
6851                         }
6852                         action_flags |= MLX5_FLOW_ACTION_AGE;
6853                         ++actions_n;
6854                         break;
6855                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
6856                         ret = flow_dv_validate_action_modify_ipv4_dscp
6857                                                          (action_flags,
6858                                                           actions,
6859                                                           item_flags,
6860                                                           error);
6861                         if (ret < 0)
6862                                 return ret;
6863                         /* Count all modify-header actions as one action. */
6864                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6865                                 ++actions_n;
6866                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6867                                 modify_after_mirror = 1;
6868                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
6869                         rw_act_num += MLX5_ACT_NUM_SET_DSCP;
6870                         break;
6871                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
6872                         ret = flow_dv_validate_action_modify_ipv6_dscp
6873                                                                 (action_flags,
6874                                                                  actions,
6875                                                                  item_flags,
6876                                                                  error);
6877                         if (ret < 0)
6878                                 return ret;
6879                         /* Count all modify-header actions as one action. */
6880                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6881                                 ++actions_n;
6882                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6883                                 modify_after_mirror = 1;
6884                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
6885                         rw_act_num += MLX5_ACT_NUM_SET_DSCP;
6886                         break;
6887                 case RTE_FLOW_ACTION_TYPE_SAMPLE:
6888                         ret = flow_dv_validate_action_sample(&action_flags,
6889                                                              actions, dev,
6890                                                              attr, item_flags,
6891                                                              rss, &sample_rss,
6892                                                              &sample_count,
6893                                                              &fdb_mirror_limit,
6894                                                              error);
6895                         if (ret < 0)
6896                                 return ret;
6897                         action_flags |= MLX5_FLOW_ACTION_SAMPLE;
6898                         ++actions_n;
6899                         break;
6900                 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
6901                         if (actions[0].type != (typeof(actions[0].type))
6902                                 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET)
6903                                 return rte_flow_error_set
6904                                                 (error, EINVAL,
6905                                                 RTE_FLOW_ERROR_TYPE_ACTION,
6906                                                 NULL, "MLX5 private action "
6907                                                 "must be the first");
6908
6909                         action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
6910                         break;
6911                 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
6912                         if (!attr->transfer && !attr->group)
6913                                 return rte_flow_error_set(error, ENOTSUP,
6914                                                 RTE_FLOW_ERROR_TYPE_ACTION,
6915                                                 NULL, "modify field action "
6916                                                 "is not supported for group 0");
6917                         ret = flow_dv_validate_action_modify_field(action_flags,
6918                                                                  actions,
6919                                                                  error);
6920                         if (ret < 0)
6921                                 return ret;
6922                         /* Count all modify-header actions as one action. */
6923                         if (!(action_flags & MLX5_FLOW_ACTION_MODIFY_FIELD))
6924                                 ++actions_n;
6925                         action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
6926                         rw_act_num += ret;
6927                         break;
6928                 default:
6929                         return rte_flow_error_set(error, ENOTSUP,
6930                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6931                                                   actions,
6932                                                   "action not supported");
6933                 }
6934         }
6935         /*
6936          * Validate actions in flow rules
6937          * - Explicit decap action is prohibited by the tunnel offload API.
6938          * - Drop action in tunnel steer rule is prohibited by the API.
6939          * - Application cannot use MARK action because it's value can mask
6940          *   tunnel default miss nitification.
6941          * - JUMP in tunnel match rule has no support in current PMD
6942          *   implementation.
6943          * - TAG & META are reserved for future uses.
6944          */
6945         if (action_flags & MLX5_FLOW_ACTION_TUNNEL_SET) {
6946                 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_DECAP    |
6947                                             MLX5_FLOW_ACTION_MARK     |
6948                                             MLX5_FLOW_ACTION_SET_TAG  |
6949                                             MLX5_FLOW_ACTION_SET_META |
6950                                             MLX5_FLOW_ACTION_DROP;
6951
6952                 if (action_flags & bad_actions_mask)
6953                         return rte_flow_error_set
6954                                         (error, EINVAL,
6955                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6956                                         "Invalid RTE action in tunnel "
6957                                         "set decap rule");
6958                 if (!(action_flags & MLX5_FLOW_ACTION_JUMP))
6959                         return rte_flow_error_set
6960                                         (error, EINVAL,
6961                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6962                                         "tunnel set decap rule must terminate "
6963                                         "with JUMP");
6964                 if (!attr->ingress)
6965                         return rte_flow_error_set
6966                                         (error, EINVAL,
6967                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6968                                         "tunnel flows for ingress traffic only");
6969         }
6970         if (action_flags & MLX5_FLOW_ACTION_TUNNEL_MATCH) {
6971                 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_JUMP    |
6972                                             MLX5_FLOW_ACTION_MARK    |
6973                                             MLX5_FLOW_ACTION_SET_TAG |
6974                                             MLX5_FLOW_ACTION_SET_META;
6975
6976                 if (action_flags & bad_actions_mask)
6977                         return rte_flow_error_set
6978                                         (error, EINVAL,
6979                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6980                                         "Invalid RTE action in tunnel "
6981                                         "set match rule");
6982         }
6983         /*
6984          * Validate the drop action mutual exclusion with other actions.
6985          * Drop action is mutually-exclusive with any other action, except for
6986          * Count action.
6987          * Drop action compatibility with tunnel offload was already validated.
6988          */
6989         if (action_flags & (MLX5_FLOW_ACTION_TUNNEL_MATCH |
6990                             MLX5_FLOW_ACTION_TUNNEL_MATCH));
6991         else if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
6992             (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
6993                 return rte_flow_error_set(error, EINVAL,
6994                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6995                                           "Drop action is mutually-exclusive "
6996                                           "with any other action, except for "
6997                                           "Count action");
6998         /* Eswitch has few restrictions on using items and actions */
6999         if (attr->transfer) {
7000                 if (!mlx5_flow_ext_mreg_supported(dev) &&
7001                     action_flags & MLX5_FLOW_ACTION_FLAG)
7002                         return rte_flow_error_set(error, ENOTSUP,
7003                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7004                                                   NULL,
7005                                                   "unsupported action FLAG");
7006                 if (!mlx5_flow_ext_mreg_supported(dev) &&
7007                     action_flags & MLX5_FLOW_ACTION_MARK)
7008                         return rte_flow_error_set(error, ENOTSUP,
7009                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7010                                                   NULL,
7011                                                   "unsupported action MARK");
7012                 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
7013                         return rte_flow_error_set(error, ENOTSUP,
7014                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7015                                                   NULL,
7016                                                   "unsupported action QUEUE");
7017                 if (action_flags & MLX5_FLOW_ACTION_RSS)
7018                         return rte_flow_error_set(error, ENOTSUP,
7019                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7020                                                   NULL,
7021                                                   "unsupported action RSS");
7022                 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
7023                         return rte_flow_error_set(error, EINVAL,
7024                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7025                                                   actions,
7026                                                   "no fate action is found");
7027         } else {
7028                 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
7029                         return rte_flow_error_set(error, EINVAL,
7030                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7031                                                   actions,
7032                                                   "no fate action is found");
7033         }
7034         /*
7035          * Continue validation for Xcap and VLAN actions.
7036          * If hairpin is working in explicit TX rule mode, there is no actions
7037          * splitting and the validation of hairpin ingress flow should be the
7038          * same as other standard flows.
7039          */
7040         if ((action_flags & (MLX5_FLOW_XCAP_ACTIONS |
7041                              MLX5_FLOW_VLAN_ACTIONS)) &&
7042             (queue_index == 0xFFFF ||
7043              mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN ||
7044              ((conf = mlx5_rxq_get_hairpin_conf(dev, queue_index)) != NULL &&
7045              conf->tx_explicit != 0))) {
7046                 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
7047                     MLX5_FLOW_XCAP_ACTIONS)
7048                         return rte_flow_error_set(error, ENOTSUP,
7049                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7050                                                   NULL, "encap and decap "
7051                                                   "combination aren't supported");
7052                 if (!attr->transfer && attr->ingress) {
7053                         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
7054                                 return rte_flow_error_set
7055                                                 (error, ENOTSUP,
7056                                                  RTE_FLOW_ERROR_TYPE_ACTION,
7057                                                  NULL, "encap is not supported"
7058                                                  " for ingress traffic");
7059                         else if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
7060                                 return rte_flow_error_set
7061                                                 (error, ENOTSUP,
7062                                                  RTE_FLOW_ERROR_TYPE_ACTION,
7063                                                  NULL, "push VLAN action not "
7064                                                  "supported for ingress");
7065                         else if ((action_flags & MLX5_FLOW_VLAN_ACTIONS) ==
7066                                         MLX5_FLOW_VLAN_ACTIONS)
7067                                 return rte_flow_error_set
7068                                                 (error, ENOTSUP,
7069                                                  RTE_FLOW_ERROR_TYPE_ACTION,
7070                                                  NULL, "no support for "
7071                                                  "multiple VLAN actions");
7072                 }
7073         }
7074         /*
7075          * Hairpin flow will add one more TAG action in TX implicit mode.
7076          * In TX explicit mode, there will be no hairpin flow ID.
7077          */
7078         if (hairpin > 0)
7079                 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7080         /* extra metadata enabled: one more TAG action will be add. */
7081         if (dev_conf->dv_flow_en &&
7082             dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
7083             mlx5_flow_ext_mreg_supported(dev))
7084                 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7085         if (rw_act_num >
7086                         flow_dv_modify_hdr_action_max(dev, is_root)) {
7087                 return rte_flow_error_set(error, ENOTSUP,
7088                                           RTE_FLOW_ERROR_TYPE_ACTION,
7089                                           NULL, "too many header modify"
7090                                           " actions to support");
7091         }
7092         /* Eswitch egress mirror and modify flow has limitation on CX5 */
7093         if (fdb_mirror_limit && modify_after_mirror)
7094                 return rte_flow_error_set(error, EINVAL,
7095                                 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7096                                 "sample before modify action is not supported");
7097         return 0;
7098 }
7099
7100 /**
7101  * Internal preparation function. Allocates the DV flow size,
7102  * this size is constant.
7103  *
7104  * @param[in] dev
7105  *   Pointer to the rte_eth_dev structure.
7106  * @param[in] attr
7107  *   Pointer to the flow attributes.
7108  * @param[in] items
7109  *   Pointer to the list of items.
7110  * @param[in] actions
7111  *   Pointer to the list of actions.
7112  * @param[out] error
7113  *   Pointer to the error structure.
7114  *
7115  * @return
7116  *   Pointer to mlx5_flow object on success,
7117  *   otherwise NULL and rte_errno is set.
7118  */
7119 static struct mlx5_flow *
7120 flow_dv_prepare(struct rte_eth_dev *dev,
7121                 const struct rte_flow_attr *attr __rte_unused,
7122                 const struct rte_flow_item items[] __rte_unused,
7123                 const struct rte_flow_action actions[] __rte_unused,
7124                 struct rte_flow_error *error)
7125 {
7126         uint32_t handle_idx = 0;
7127         struct mlx5_flow *dev_flow;
7128         struct mlx5_flow_handle *dev_handle;
7129         struct mlx5_priv *priv = dev->data->dev_private;
7130         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
7131
7132         MLX5_ASSERT(wks);
7133         /* In case of corrupting the memory. */
7134         if (wks->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
7135                 rte_flow_error_set(error, ENOSPC,
7136                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7137                                    "not free temporary device flow");
7138                 return NULL;
7139         }
7140         dev_handle = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
7141                                    &handle_idx);
7142         if (!dev_handle) {
7143                 rte_flow_error_set(error, ENOMEM,
7144                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7145                                    "not enough memory to create flow handle");
7146                 return NULL;
7147         }
7148         MLX5_ASSERT(wks->flow_idx < RTE_DIM(wks->flows));
7149         dev_flow = &wks->flows[wks->flow_idx++];
7150         memset(dev_flow, 0, sizeof(*dev_flow));
7151         dev_flow->handle = dev_handle;
7152         dev_flow->handle_idx = handle_idx;
7153         /*
7154          * In some old rdma-core releases, before continuing, a check of the
7155          * length of matching parameter will be done at first. It needs to use
7156          * the length without misc4 param. If the flow has misc4 support, then
7157          * the length needs to be adjusted accordingly. Each param member is
7158          * aligned with a 64B boundary naturally.
7159          */
7160         dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param) -
7161                                   MLX5_ST_SZ_BYTES(fte_match_set_misc4);
7162         dev_flow->ingress = attr->ingress;
7163         dev_flow->dv.transfer = attr->transfer;
7164         return dev_flow;
7165 }
7166
7167 #ifdef RTE_LIBRTE_MLX5_DEBUG
7168 /**
7169  * Sanity check for match mask and value. Similar to check_valid_spec() in
7170  * kernel driver. If unmasked bit is present in value, it returns failure.
7171  *
7172  * @param match_mask
7173  *   pointer to match mask buffer.
7174  * @param match_value
7175  *   pointer to match value buffer.
7176  *
7177  * @return
7178  *   0 if valid, -EINVAL otherwise.
7179  */
7180 static int
7181 flow_dv_check_valid_spec(void *match_mask, void *match_value)
7182 {
7183         uint8_t *m = match_mask;
7184         uint8_t *v = match_value;
7185         unsigned int i;
7186
7187         for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
7188                 if (v[i] & ~m[i]) {
7189                         DRV_LOG(ERR,
7190                                 "match_value differs from match_criteria"
7191                                 " %p[%u] != %p[%u]",
7192                                 match_value, i, match_mask, i);
7193                         return -EINVAL;
7194                 }
7195         }
7196         return 0;
7197 }
7198 #endif
7199
7200 /**
7201  * Add match of ip_version.
7202  *
7203  * @param[in] group
7204  *   Flow group.
7205  * @param[in] headers_v
7206  *   Values header pointer.
7207  * @param[in] headers_m
7208  *   Masks header pointer.
7209  * @param[in] ip_version
7210  *   The IP version to set.
7211  */
7212 static inline void
7213 flow_dv_set_match_ip_version(uint32_t group,
7214                              void *headers_v,
7215                              void *headers_m,
7216                              uint8_t ip_version)
7217 {
7218         if (group == 0)
7219                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
7220         else
7221                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version,
7222                          ip_version);
7223         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, ip_version);
7224         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, 0);
7225         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype, 0);
7226 }
7227
7228 /**
7229  * Add Ethernet item to matcher and to the value.
7230  *
7231  * @param[in, out] matcher
7232  *   Flow matcher.
7233  * @param[in, out] key
7234  *   Flow matcher value.
7235  * @param[in] item
7236  *   Flow pattern to translate.
7237  * @param[in] inner
7238  *   Item is inner pattern.
7239  */
7240 static void
7241 flow_dv_translate_item_eth(void *matcher, void *key,
7242                            const struct rte_flow_item *item, int inner,
7243                            uint32_t group)
7244 {
7245         const struct rte_flow_item_eth *eth_m = item->mask;
7246         const struct rte_flow_item_eth *eth_v = item->spec;
7247         const struct rte_flow_item_eth nic_mask = {
7248                 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
7249                 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
7250                 .type = RTE_BE16(0xffff),
7251                 .has_vlan = 0,
7252         };
7253         void *hdrs_m;
7254         void *hdrs_v;
7255         char *l24_v;
7256         unsigned int i;
7257
7258         if (!eth_v)
7259                 return;
7260         if (!eth_m)
7261                 eth_m = &nic_mask;
7262         if (inner) {
7263                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7264                                          inner_headers);
7265                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7266         } else {
7267                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7268                                          outer_headers);
7269                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7270         }
7271         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, dmac_47_16),
7272                &eth_m->dst, sizeof(eth_m->dst));
7273         /* The value must be in the range of the mask. */
7274         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, dmac_47_16);
7275         for (i = 0; i < sizeof(eth_m->dst); ++i)
7276                 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
7277         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, smac_47_16),
7278                &eth_m->src, sizeof(eth_m->src));
7279         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, smac_47_16);
7280         /* The value must be in the range of the mask. */
7281         for (i = 0; i < sizeof(eth_m->dst); ++i)
7282                 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
7283         /*
7284          * HW supports match on one Ethertype, the Ethertype following the last
7285          * VLAN tag of the packet (see PRM).
7286          * Set match on ethertype only if ETH header is not followed by VLAN.
7287          * HW is optimized for IPv4/IPv6. In such cases, avoid setting
7288          * ethertype, and use ip_version field instead.
7289          * eCPRI over Ether layer will use type value 0xAEFE.
7290          */
7291         if (eth_m->type == 0xFFFF) {
7292                 /* Set cvlan_tag mask for any single\multi\un-tagged case. */
7293                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
7294                 switch (eth_v->type) {
7295                 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
7296                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
7297                         return;
7298                 case RTE_BE16(RTE_ETHER_TYPE_QINQ):
7299                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
7300                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
7301                         return;
7302                 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
7303                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
7304                         return;
7305                 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
7306                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
7307                         return;
7308                 default:
7309                         break;
7310                 }
7311         }
7312         if (eth_m->has_vlan) {
7313                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
7314                 if (eth_v->has_vlan) {
7315                         /*
7316                          * Here, when also has_more_vlan field in VLAN item is
7317                          * not set, only single-tagged packets will be matched.
7318                          */
7319                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
7320                         return;
7321                 }
7322         }
7323         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
7324                  rte_be_to_cpu_16(eth_m->type));
7325         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, ethertype);
7326         *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
7327 }
7328
7329 /**
7330  * Add VLAN item to matcher and to the value.
7331  *
7332  * @param[in, out] dev_flow
7333  *   Flow descriptor.
7334  * @param[in, out] matcher
7335  *   Flow matcher.
7336  * @param[in, out] key
7337  *   Flow matcher value.
7338  * @param[in] item
7339  *   Flow pattern to translate.
7340  * @param[in] inner
7341  *   Item is inner pattern.
7342  */
7343 static void
7344 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
7345                             void *matcher, void *key,
7346                             const struct rte_flow_item *item,
7347                             int inner, uint32_t group)
7348 {
7349         const struct rte_flow_item_vlan *vlan_m = item->mask;
7350         const struct rte_flow_item_vlan *vlan_v = item->spec;
7351         void *hdrs_m;
7352         void *hdrs_v;
7353         uint16_t tci_m;
7354         uint16_t tci_v;
7355
7356         if (inner) {
7357                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7358                                          inner_headers);
7359                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7360         } else {
7361                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7362                                          outer_headers);
7363                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7364                 /*
7365                  * This is workaround, masks are not supported,
7366                  * and pre-validated.
7367                  */
7368                 if (vlan_v)
7369                         dev_flow->handle->vf_vlan.tag =
7370                                         rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
7371         }
7372         /*
7373          * When VLAN item exists in flow, mark packet as tagged,
7374          * even if TCI is not specified.
7375          */
7376         if (!MLX5_GET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag)) {
7377                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
7378                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
7379         }
7380         if (!vlan_v)
7381                 return;
7382         if (!vlan_m)
7383                 vlan_m = &rte_flow_item_vlan_mask;
7384         tci_m = rte_be_to_cpu_16(vlan_m->tci);
7385         tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
7386         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_vid, tci_m);
7387         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_vid, tci_v);
7388         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_cfi, tci_m >> 12);
7389         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_cfi, tci_v >> 12);
7390         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_prio, tci_m >> 13);
7391         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_prio, tci_v >> 13);
7392         /*
7393          * HW is optimized for IPv4/IPv6. In such cases, avoid setting
7394          * ethertype, and use ip_version field instead.
7395          */
7396         if (vlan_m->inner_type == 0xFFFF) {
7397                 switch (vlan_v->inner_type) {
7398                 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
7399                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
7400                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
7401                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
7402                         return;
7403                 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
7404                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
7405                         return;
7406                 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
7407                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
7408                         return;
7409                 default:
7410                         break;
7411                 }
7412         }
7413         if (vlan_m->has_more_vlan && vlan_v->has_more_vlan) {
7414                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
7415                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
7416                 /* Only one vlan_tag bit can be set. */
7417                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
7418                 return;
7419         }
7420         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
7421                  rte_be_to_cpu_16(vlan_m->inner_type));
7422         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, ethertype,
7423                  rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
7424 }
7425
7426 /**
7427  * Add IPV4 item to matcher and to the value.
7428  *
7429  * @param[in, out] matcher
7430  *   Flow matcher.
7431  * @param[in, out] key
7432  *   Flow matcher value.
7433  * @param[in] item
7434  *   Flow pattern to translate.
7435  * @param[in] inner
7436  *   Item is inner pattern.
7437  * @param[in] group
7438  *   The group to insert the rule.
7439  */
7440 static void
7441 flow_dv_translate_item_ipv4(void *matcher, void *key,
7442                             const struct rte_flow_item *item,
7443                             int inner, uint32_t group)
7444 {
7445         const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
7446         const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
7447         const struct rte_flow_item_ipv4 nic_mask = {
7448                 .hdr = {
7449                         .src_addr = RTE_BE32(0xffffffff),
7450                         .dst_addr = RTE_BE32(0xffffffff),
7451                         .type_of_service = 0xff,
7452                         .next_proto_id = 0xff,
7453                         .time_to_live = 0xff,
7454                 },
7455         };
7456         void *headers_m;
7457         void *headers_v;
7458         char *l24_m;
7459         char *l24_v;
7460         uint8_t tos;
7461
7462         if (inner) {
7463                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7464                                          inner_headers);
7465                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7466         } else {
7467                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7468                                          outer_headers);
7469                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7470         }
7471         flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
7472         if (!ipv4_v)
7473                 return;
7474         if (!ipv4_m)
7475                 ipv4_m = &nic_mask;
7476         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
7477                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
7478         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
7479                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
7480         *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
7481         *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
7482         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
7483                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
7484         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
7485                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
7486         *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
7487         *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
7488         tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
7489         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
7490                  ipv4_m->hdr.type_of_service);
7491         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
7492         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
7493                  ipv4_m->hdr.type_of_service >> 2);
7494         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
7495         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
7496                  ipv4_m->hdr.next_proto_id);
7497         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
7498                  ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
7499         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
7500                  ipv4_m->hdr.time_to_live);
7501         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
7502                  ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
7503         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
7504                  !!(ipv4_m->hdr.fragment_offset));
7505         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
7506                  !!(ipv4_v->hdr.fragment_offset & ipv4_m->hdr.fragment_offset));
7507 }
7508
7509 /**
7510  * Add IPV6 item to matcher and to the value.
7511  *
7512  * @param[in, out] matcher
7513  *   Flow matcher.
7514  * @param[in, out] key
7515  *   Flow matcher value.
7516  * @param[in] item
7517  *   Flow pattern to translate.
7518  * @param[in] inner
7519  *   Item is inner pattern.
7520  * @param[in] group
7521  *   The group to insert the rule.
7522  */
7523 static void
7524 flow_dv_translate_item_ipv6(void *matcher, void *key,
7525                             const struct rte_flow_item *item,
7526                             int inner, uint32_t group)
7527 {
7528         const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
7529         const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
7530         const struct rte_flow_item_ipv6 nic_mask = {
7531                 .hdr = {
7532                         .src_addr =
7533                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
7534                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
7535                         .dst_addr =
7536                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
7537                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
7538                         .vtc_flow = RTE_BE32(0xffffffff),
7539                         .proto = 0xff,
7540                         .hop_limits = 0xff,
7541                 },
7542         };
7543         void *headers_m;
7544         void *headers_v;
7545         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7546         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7547         char *l24_m;
7548         char *l24_v;
7549         uint32_t vtc_m;
7550         uint32_t vtc_v;
7551         int i;
7552         int size;
7553
7554         if (inner) {
7555                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7556                                          inner_headers);
7557                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7558         } else {
7559                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7560                                          outer_headers);
7561                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7562         }
7563         flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
7564         if (!ipv6_v)
7565                 return;
7566         if (!ipv6_m)
7567                 ipv6_m = &nic_mask;
7568         size = sizeof(ipv6_m->hdr.dst_addr);
7569         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
7570                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
7571         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
7572                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
7573         memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
7574         for (i = 0; i < size; ++i)
7575                 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
7576         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
7577                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
7578         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
7579                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
7580         memcpy(l24_m, ipv6_m->hdr.src_addr, size);
7581         for (i = 0; i < size; ++i)
7582                 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
7583         /* TOS. */
7584         vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
7585         vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
7586         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
7587         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
7588         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
7589         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
7590         /* Label. */
7591         if (inner) {
7592                 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
7593                          vtc_m);
7594                 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
7595                          vtc_v);
7596         } else {
7597                 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
7598                          vtc_m);
7599                 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
7600                          vtc_v);
7601         }
7602         /* Protocol. */
7603         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
7604                  ipv6_m->hdr.proto);
7605         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
7606                  ipv6_v->hdr.proto & ipv6_m->hdr.proto);
7607         /* Hop limit. */
7608         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
7609                  ipv6_m->hdr.hop_limits);
7610         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
7611                  ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
7612         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
7613                  !!(ipv6_m->has_frag_ext));
7614         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
7615                  !!(ipv6_v->has_frag_ext & ipv6_m->has_frag_ext));
7616 }
7617
7618 /**
7619  * Add IPV6 fragment extension item to matcher and to the value.
7620  *
7621  * @param[in, out] matcher
7622  *   Flow matcher.
7623  * @param[in, out] key
7624  *   Flow matcher value.
7625  * @param[in] item
7626  *   Flow pattern to translate.
7627  * @param[in] inner
7628  *   Item is inner pattern.
7629  */
7630 static void
7631 flow_dv_translate_item_ipv6_frag_ext(void *matcher, void *key,
7632                                      const struct rte_flow_item *item,
7633                                      int inner)
7634 {
7635         const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_m = item->mask;
7636         const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_v = item->spec;
7637         const struct rte_flow_item_ipv6_frag_ext nic_mask = {
7638                 .hdr = {
7639                         .next_header = 0xff,
7640                         .frag_data = RTE_BE16(0xffff),
7641                 },
7642         };
7643         void *headers_m;
7644         void *headers_v;
7645
7646         if (inner) {
7647                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7648                                          inner_headers);
7649                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7650         } else {
7651                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7652                                          outer_headers);
7653                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7654         }
7655         /* IPv6 fragment extension item exists, so packet is IP fragment. */
7656         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
7657         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 1);
7658         if (!ipv6_frag_ext_v)
7659                 return;
7660         if (!ipv6_frag_ext_m)
7661                 ipv6_frag_ext_m = &nic_mask;
7662         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
7663                  ipv6_frag_ext_m->hdr.next_header);
7664         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
7665                  ipv6_frag_ext_v->hdr.next_header &
7666                  ipv6_frag_ext_m->hdr.next_header);
7667 }
7668
7669 /**
7670  * Add TCP item to matcher and to the value.
7671  *
7672  * @param[in, out] matcher
7673  *   Flow matcher.
7674  * @param[in, out] key
7675  *   Flow matcher value.
7676  * @param[in] item
7677  *   Flow pattern to translate.
7678  * @param[in] inner
7679  *   Item is inner pattern.
7680  */
7681 static void
7682 flow_dv_translate_item_tcp(void *matcher, void *key,
7683                            const struct rte_flow_item *item,
7684                            int inner)
7685 {
7686         const struct rte_flow_item_tcp *tcp_m = item->mask;
7687         const struct rte_flow_item_tcp *tcp_v = item->spec;
7688         void *headers_m;
7689         void *headers_v;
7690
7691         if (inner) {
7692                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7693                                          inner_headers);
7694                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7695         } else {
7696                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7697                                          outer_headers);
7698                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7699         }
7700         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7701         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
7702         if (!tcp_v)
7703                 return;
7704         if (!tcp_m)
7705                 tcp_m = &rte_flow_item_tcp_mask;
7706         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
7707                  rte_be_to_cpu_16(tcp_m->hdr.src_port));
7708         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
7709                  rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
7710         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
7711                  rte_be_to_cpu_16(tcp_m->hdr.dst_port));
7712         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
7713                  rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
7714         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
7715                  tcp_m->hdr.tcp_flags);
7716         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
7717                  (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
7718 }
7719
7720 /**
7721  * Add UDP item to matcher and to the value.
7722  *
7723  * @param[in, out] matcher
7724  *   Flow matcher.
7725  * @param[in, out] key
7726  *   Flow matcher value.
7727  * @param[in] item
7728  *   Flow pattern to translate.
7729  * @param[in] inner
7730  *   Item is inner pattern.
7731  */
7732 static void
7733 flow_dv_translate_item_udp(void *matcher, void *key,
7734                            const struct rte_flow_item *item,
7735                            int inner)
7736 {
7737         const struct rte_flow_item_udp *udp_m = item->mask;
7738         const struct rte_flow_item_udp *udp_v = item->spec;
7739         void *headers_m;
7740         void *headers_v;
7741
7742         if (inner) {
7743                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7744                                          inner_headers);
7745                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7746         } else {
7747                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7748                                          outer_headers);
7749                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7750         }
7751         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7752         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
7753         if (!udp_v)
7754                 return;
7755         if (!udp_m)
7756                 udp_m = &rte_flow_item_udp_mask;
7757         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
7758                  rte_be_to_cpu_16(udp_m->hdr.src_port));
7759         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
7760                  rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
7761         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
7762                  rte_be_to_cpu_16(udp_m->hdr.dst_port));
7763         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
7764                  rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
7765 }
7766
7767 /**
7768  * Add GRE optional Key item to matcher and to the value.
7769  *
7770  * @param[in, out] matcher
7771  *   Flow matcher.
7772  * @param[in, out] key
7773  *   Flow matcher value.
7774  * @param[in] item
7775  *   Flow pattern to translate.
7776  * @param[in] inner
7777  *   Item is inner pattern.
7778  */
7779 static void
7780 flow_dv_translate_item_gre_key(void *matcher, void *key,
7781                                    const struct rte_flow_item *item)
7782 {
7783         const rte_be32_t *key_m = item->mask;
7784         const rte_be32_t *key_v = item->spec;
7785         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7786         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7787         rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
7788
7789         /* GRE K bit must be on and should already be validated */
7790         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
7791         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
7792         if (!key_v)
7793                 return;
7794         if (!key_m)
7795                 key_m = &gre_key_default_mask;
7796         MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
7797                  rte_be_to_cpu_32(*key_m) >> 8);
7798         MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
7799                  rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
7800         MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
7801                  rte_be_to_cpu_32(*key_m) & 0xFF);
7802         MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
7803                  rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
7804 }
7805
7806 /**
7807  * Add GRE item to matcher and to the value.
7808  *
7809  * @param[in, out] matcher
7810  *   Flow matcher.
7811  * @param[in, out] key
7812  *   Flow matcher value.
7813  * @param[in] item
7814  *   Flow pattern to translate.
7815  * @param[in] inner
7816  *   Item is inner pattern.
7817  */
7818 static void
7819 flow_dv_translate_item_gre(void *matcher, void *key,
7820                            const struct rte_flow_item *item,
7821                            int inner)
7822 {
7823         const struct rte_flow_item_gre *gre_m = item->mask;
7824         const struct rte_flow_item_gre *gre_v = item->spec;
7825         void *headers_m;
7826         void *headers_v;
7827         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7828         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7829         struct {
7830                 union {
7831                         __extension__
7832                         struct {
7833                                 uint16_t version:3;
7834                                 uint16_t rsvd0:9;
7835                                 uint16_t s_present:1;
7836                                 uint16_t k_present:1;
7837                                 uint16_t rsvd_bit1:1;
7838                                 uint16_t c_present:1;
7839                         };
7840                         uint16_t value;
7841                 };
7842         } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
7843
7844         if (inner) {
7845                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7846                                          inner_headers);
7847                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7848         } else {
7849                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7850                                          outer_headers);
7851                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7852         }
7853         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7854         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
7855         if (!gre_v)
7856                 return;
7857         if (!gre_m)
7858                 gre_m = &rte_flow_item_gre_mask;
7859         MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
7860                  rte_be_to_cpu_16(gre_m->protocol));
7861         MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
7862                  rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
7863         gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
7864         gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
7865         MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
7866                  gre_crks_rsvd0_ver_m.c_present);
7867         MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
7868                  gre_crks_rsvd0_ver_v.c_present &
7869                  gre_crks_rsvd0_ver_m.c_present);
7870         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
7871                  gre_crks_rsvd0_ver_m.k_present);
7872         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
7873                  gre_crks_rsvd0_ver_v.k_present &
7874                  gre_crks_rsvd0_ver_m.k_present);
7875         MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
7876                  gre_crks_rsvd0_ver_m.s_present);
7877         MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
7878                  gre_crks_rsvd0_ver_v.s_present &
7879                  gre_crks_rsvd0_ver_m.s_present);
7880 }
7881
7882 /**
7883  * Add NVGRE item to matcher and to the value.
7884  *
7885  * @param[in, out] matcher
7886  *   Flow matcher.
7887  * @param[in, out] key
7888  *   Flow matcher value.
7889  * @param[in] item
7890  *   Flow pattern to translate.
7891  * @param[in] inner
7892  *   Item is inner pattern.
7893  */
7894 static void
7895 flow_dv_translate_item_nvgre(void *matcher, void *key,
7896                              const struct rte_flow_item *item,
7897                              int inner)
7898 {
7899         const struct rte_flow_item_nvgre *nvgre_m = item->mask;
7900         const struct rte_flow_item_nvgre *nvgre_v = item->spec;
7901         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7902         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7903         const char *tni_flow_id_m;
7904         const char *tni_flow_id_v;
7905         char *gre_key_m;
7906         char *gre_key_v;
7907         int size;
7908         int i;
7909
7910         /* For NVGRE, GRE header fields must be set with defined values. */
7911         const struct rte_flow_item_gre gre_spec = {
7912                 .c_rsvd0_ver = RTE_BE16(0x2000),
7913                 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
7914         };
7915         const struct rte_flow_item_gre gre_mask = {
7916                 .c_rsvd0_ver = RTE_BE16(0xB000),
7917                 .protocol = RTE_BE16(UINT16_MAX),
7918         };
7919         const struct rte_flow_item gre_item = {
7920                 .spec = &gre_spec,
7921                 .mask = &gre_mask,
7922                 .last = NULL,
7923         };
7924         flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
7925         if (!nvgre_v)
7926                 return;
7927         if (!nvgre_m)
7928                 nvgre_m = &rte_flow_item_nvgre_mask;
7929         tni_flow_id_m = (const char *)nvgre_m->tni;
7930         tni_flow_id_v = (const char *)nvgre_v->tni;
7931         size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
7932         gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
7933         gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
7934         memcpy(gre_key_m, tni_flow_id_m, size);
7935         for (i = 0; i < size; ++i)
7936                 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
7937 }
7938
7939 /**
7940  * Add VXLAN item to matcher and to the value.
7941  *
7942  * @param[in, out] matcher
7943  *   Flow matcher.
7944  * @param[in, out] key
7945  *   Flow matcher value.
7946  * @param[in] item
7947  *   Flow pattern to translate.
7948  * @param[in] inner
7949  *   Item is inner pattern.
7950  */
7951 static void
7952 flow_dv_translate_item_vxlan(void *matcher, void *key,
7953                              const struct rte_flow_item *item,
7954                              int inner)
7955 {
7956         const struct rte_flow_item_vxlan *vxlan_m = item->mask;
7957         const struct rte_flow_item_vxlan *vxlan_v = item->spec;
7958         void *headers_m;
7959         void *headers_v;
7960         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7961         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7962         char *vni_m;
7963         char *vni_v;
7964         uint16_t dport;
7965         int size;
7966         int i;
7967
7968         if (inner) {
7969                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7970                                          inner_headers);
7971                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7972         } else {
7973                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7974                                          outer_headers);
7975                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7976         }
7977         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
7978                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
7979         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7980                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7981                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7982         }
7983         if (!vxlan_v)
7984                 return;
7985         if (!vxlan_m)
7986                 vxlan_m = &rte_flow_item_vxlan_mask;
7987         size = sizeof(vxlan_m->vni);
7988         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
7989         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
7990         memcpy(vni_m, vxlan_m->vni, size);
7991         for (i = 0; i < size; ++i)
7992                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
7993 }
7994
7995 /**
7996  * Add VXLAN-GPE item to matcher and to the value.
7997  *
7998  * @param[in, out] matcher
7999  *   Flow matcher.
8000  * @param[in, out] key
8001  *   Flow matcher value.
8002  * @param[in] item
8003  *   Flow pattern to translate.
8004  * @param[in] inner
8005  *   Item is inner pattern.
8006  */
8007
8008 static void
8009 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
8010                                  const struct rte_flow_item *item, int inner)
8011 {
8012         const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
8013         const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
8014         void *headers_m;
8015         void *headers_v;
8016         void *misc_m =
8017                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
8018         void *misc_v =
8019                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8020         char *vni_m;
8021         char *vni_v;
8022         uint16_t dport;
8023         int size;
8024         int i;
8025         uint8_t flags_m = 0xff;
8026         uint8_t flags_v = 0xc;
8027
8028         if (inner) {
8029                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8030                                          inner_headers);
8031                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8032         } else {
8033                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8034                                          outer_headers);
8035                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8036         }
8037         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
8038                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
8039         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8040                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8041                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8042         }
8043         if (!vxlan_v)
8044                 return;
8045         if (!vxlan_m)
8046                 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
8047         size = sizeof(vxlan_m->vni);
8048         vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
8049         vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
8050         memcpy(vni_m, vxlan_m->vni, size);
8051         for (i = 0; i < size; ++i)
8052                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
8053         if (vxlan_m->flags) {
8054                 flags_m = vxlan_m->flags;
8055                 flags_v = vxlan_v->flags;
8056         }
8057         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
8058         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
8059         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
8060                  vxlan_m->protocol);
8061         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
8062                  vxlan_v->protocol);
8063 }
8064
8065 /**
8066  * Add Geneve item to matcher and to the value.
8067  *
8068  * @param[in, out] matcher
8069  *   Flow matcher.
8070  * @param[in, out] key
8071  *   Flow matcher value.
8072  * @param[in] item
8073  *   Flow pattern to translate.
8074  * @param[in] inner
8075  *   Item is inner pattern.
8076  */
8077
8078 static void
8079 flow_dv_translate_item_geneve(void *matcher, void *key,
8080                               const struct rte_flow_item *item, int inner)
8081 {
8082         const struct rte_flow_item_geneve *geneve_m = item->mask;
8083         const struct rte_flow_item_geneve *geneve_v = item->spec;
8084         void *headers_m;
8085         void *headers_v;
8086         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8087         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8088         uint16_t dport;
8089         uint16_t gbhdr_m;
8090         uint16_t gbhdr_v;
8091         char *vni_m;
8092         char *vni_v;
8093         size_t size, i;
8094
8095         if (inner) {
8096                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8097                                          inner_headers);
8098                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8099         } else {
8100                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8101                                          outer_headers);
8102                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8103         }
8104         dport = MLX5_UDP_PORT_GENEVE;
8105         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8106                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8107                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8108         }
8109         if (!geneve_v)
8110                 return;
8111         if (!geneve_m)
8112                 geneve_m = &rte_flow_item_geneve_mask;
8113         size = sizeof(geneve_m->vni);
8114         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
8115         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
8116         memcpy(vni_m, geneve_m->vni, size);
8117         for (i = 0; i < size; ++i)
8118                 vni_v[i] = vni_m[i] & geneve_v->vni[i];
8119         MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
8120                  rte_be_to_cpu_16(geneve_m->protocol));
8121         MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
8122                  rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
8123         gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
8124         gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
8125         MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
8126                  MLX5_GENEVE_OAMF_VAL(gbhdr_m));
8127         MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
8128                  MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
8129         MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
8130                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
8131         MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
8132                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
8133                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
8134 }
8135
8136 /**
8137  * Create Geneve TLV option resource.
8138  *
8139  * @param dev[in, out]
8140  *   Pointer to rte_eth_dev structure.
8141  * @param[in, out] tag_be24
8142  *   Tag value in big endian then R-shift 8.
8143  * @parm[in, out] dev_flow
8144  *   Pointer to the dev_flow.
8145  * @param[out] error
8146  *   pointer to error structure.
8147  *
8148  * @return
8149  *   0 on success otherwise -errno and errno is set.
8150  */
8151
8152 int
8153 flow_dev_geneve_tlv_option_resource_register(struct rte_eth_dev *dev,
8154                                              const struct rte_flow_item *item,
8155                                              struct rte_flow_error *error)
8156 {
8157         struct mlx5_priv *priv = dev->data->dev_private;
8158         struct mlx5_dev_ctx_shared *sh = priv->sh;
8159         struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
8160                         sh->geneve_tlv_option_resource;
8161         struct mlx5_devx_obj *obj;
8162         const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
8163         int ret = 0;
8164
8165         if (!geneve_opt_v)
8166                 return -1;
8167         rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
8168         if (geneve_opt_resource != NULL) {
8169                 if (geneve_opt_resource->option_class ==
8170                         geneve_opt_v->option_class &&
8171                         geneve_opt_resource->option_type ==
8172                         geneve_opt_v->option_type &&
8173                         geneve_opt_resource->length ==
8174                         geneve_opt_v->option_len) {
8175                         /* We already have GENVE TLV option obj allocated. */
8176                         __atomic_fetch_add(&geneve_opt_resource->refcnt, 1,
8177                                            __ATOMIC_RELAXED);
8178                 } else {
8179                         ret = rte_flow_error_set(error, ENOMEM,
8180                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8181                                 "Only one GENEVE TLV option supported");
8182                         goto exit;
8183                 }
8184         } else {
8185                 /* Create a GENEVE TLV object and resource. */
8186                 obj = mlx5_devx_cmd_create_geneve_tlv_option(sh->ctx,
8187                                 geneve_opt_v->option_class,
8188                                 geneve_opt_v->option_type,
8189                                 geneve_opt_v->option_len);
8190                 if (!obj) {
8191                         ret = rte_flow_error_set(error, ENODATA,
8192                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8193                                 "Failed to create GENEVE TLV Devx object");
8194                         goto exit;
8195                 }
8196                 sh->geneve_tlv_option_resource =
8197                                 mlx5_malloc(MLX5_MEM_ZERO,
8198                                                 sizeof(*geneve_opt_resource),
8199                                                 0, SOCKET_ID_ANY);
8200                 if (!sh->geneve_tlv_option_resource) {
8201                         claim_zero(mlx5_devx_cmd_destroy(obj));
8202                         ret = rte_flow_error_set(error, ENOMEM,
8203                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8204                                 "GENEVE TLV object memory allocation failed");
8205                         goto exit;
8206                 }
8207                 geneve_opt_resource = sh->geneve_tlv_option_resource;
8208                 geneve_opt_resource->obj = obj;
8209                 geneve_opt_resource->option_class = geneve_opt_v->option_class;
8210                 geneve_opt_resource->option_type = geneve_opt_v->option_type;
8211                 geneve_opt_resource->length = geneve_opt_v->option_len;
8212                 __atomic_store_n(&geneve_opt_resource->refcnt, 1,
8213                                 __ATOMIC_RELAXED);
8214         }
8215 exit:
8216         rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
8217         return ret;
8218 }
8219
8220 /**
8221  * Add Geneve TLV option item to matcher.
8222  *
8223  * @param[in, out] dev
8224  *   Pointer to rte_eth_dev structure.
8225  * @param[in, out] matcher
8226  *   Flow matcher.
8227  * @param[in, out] key
8228  *   Flow matcher value.
8229  * @param[in] item
8230  *   Flow pattern to translate.
8231  * @param[out] error
8232  *   Pointer to error structure.
8233  */
8234 static int
8235 flow_dv_translate_item_geneve_opt(struct rte_eth_dev *dev, void *matcher,
8236                                   void *key, const struct rte_flow_item *item,
8237                                   struct rte_flow_error *error)
8238 {
8239         const struct rte_flow_item_geneve_opt *geneve_opt_m = item->mask;
8240         const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
8241         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8242         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8243         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8244                         misc_parameters_3);
8245         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8246         rte_be32_t opt_data_key = 0, opt_data_mask = 0;
8247         int ret = 0;
8248
8249         if (!geneve_opt_v)
8250                 return -1;
8251         if (!geneve_opt_m)
8252                 geneve_opt_m = &rte_flow_item_geneve_opt_mask;
8253         ret = flow_dev_geneve_tlv_option_resource_register(dev, item,
8254                                                            error);
8255         if (ret) {
8256                 DRV_LOG(ERR, "Failed to create geneve_tlv_obj");
8257                 return ret;
8258         }
8259         /*
8260          * Set the option length in GENEVE header if not requested.
8261          * The GENEVE TLV option length is expressed by the option length field
8262          * in the GENEVE header.
8263          * If the option length was not requested but the GENEVE TLV option item
8264          * is present we set the option length field implicitly.
8265          */
8266         if (!MLX5_GET16(fte_match_set_misc, misc_m, geneve_opt_len)) {
8267                 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
8268                          MLX5_GENEVE_OPTLEN_MASK);
8269                 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
8270                          geneve_opt_v->option_len + 1);
8271         }
8272         /* Set the data. */
8273         if (geneve_opt_v->data) {
8274                 memcpy(&opt_data_key, geneve_opt_v->data,
8275                         RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
8276                                 sizeof(opt_data_key)));
8277                 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
8278                                 sizeof(opt_data_key));
8279                 memcpy(&opt_data_mask, geneve_opt_m->data,
8280                         RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
8281                                 sizeof(opt_data_mask)));
8282                 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
8283                                 sizeof(opt_data_mask));
8284                 MLX5_SET(fte_match_set_misc3, misc3_m,
8285                                 geneve_tlv_option_0_data,
8286                                 rte_be_to_cpu_32(opt_data_mask));
8287                 MLX5_SET(fte_match_set_misc3, misc3_v,
8288                                 geneve_tlv_option_0_data,
8289                         rte_be_to_cpu_32(opt_data_key & opt_data_mask));
8290         }
8291         return ret;
8292 }
8293
8294 /**
8295  * Add MPLS item to matcher and to the value.
8296  *
8297  * @param[in, out] matcher
8298  *   Flow matcher.
8299  * @param[in, out] key
8300  *   Flow matcher value.
8301  * @param[in] item
8302  *   Flow pattern to translate.
8303  * @param[in] prev_layer
8304  *   The protocol layer indicated in previous item.
8305  * @param[in] inner
8306  *   Item is inner pattern.
8307  */
8308 static void
8309 flow_dv_translate_item_mpls(void *matcher, void *key,
8310                             const struct rte_flow_item *item,
8311                             uint64_t prev_layer,
8312                             int inner)
8313 {
8314         const uint32_t *in_mpls_m = item->mask;
8315         const uint32_t *in_mpls_v = item->spec;
8316         uint32_t *out_mpls_m = 0;
8317         uint32_t *out_mpls_v = 0;
8318         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8319         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8320         void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
8321                                      misc_parameters_2);
8322         void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
8323         void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
8324         void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8325
8326         switch (prev_layer) {
8327         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
8328                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
8329                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
8330                          MLX5_UDP_PORT_MPLS);
8331                 break;
8332         case MLX5_FLOW_LAYER_GRE:
8333                 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
8334                 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
8335                          RTE_ETHER_TYPE_MPLS);
8336                 break;
8337         default:
8338                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
8339                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8340                          IPPROTO_MPLS);
8341                 break;
8342         }
8343         if (!in_mpls_v)
8344                 return;
8345         if (!in_mpls_m)
8346                 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
8347         switch (prev_layer) {
8348         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
8349                 out_mpls_m =
8350                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
8351                                                  outer_first_mpls_over_udp);
8352                 out_mpls_v =
8353                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
8354                                                  outer_first_mpls_over_udp);
8355                 break;
8356         case MLX5_FLOW_LAYER_GRE:
8357                 out_mpls_m =
8358                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
8359                                                  outer_first_mpls_over_gre);
8360                 out_mpls_v =
8361                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
8362                                                  outer_first_mpls_over_gre);
8363                 break;
8364         default:
8365                 /* Inner MPLS not over GRE is not supported. */
8366                 if (!inner) {
8367                         out_mpls_m =
8368                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
8369                                                          misc2_m,
8370                                                          outer_first_mpls);
8371                         out_mpls_v =
8372                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
8373                                                          misc2_v,
8374                                                          outer_first_mpls);
8375                 }
8376                 break;
8377         }
8378         if (out_mpls_m && out_mpls_v) {
8379                 *out_mpls_m = *in_mpls_m;
8380                 *out_mpls_v = *in_mpls_v & *in_mpls_m;
8381         }
8382 }
8383
8384 /**
8385  * Add metadata register item to matcher
8386  *
8387  * @param[in, out] matcher
8388  *   Flow matcher.
8389  * @param[in, out] key
8390  *   Flow matcher value.
8391  * @param[in] reg_type
8392  *   Type of device metadata register
8393  * @param[in] value
8394  *   Register value
8395  * @param[in] mask
8396  *   Register mask
8397  */
8398 static void
8399 flow_dv_match_meta_reg(void *matcher, void *key,
8400                        enum modify_reg reg_type,
8401                        uint32_t data, uint32_t mask)
8402 {
8403         void *misc2_m =
8404                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
8405         void *misc2_v =
8406                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
8407         uint32_t temp;
8408
8409         data &= mask;
8410         switch (reg_type) {
8411         case REG_A:
8412                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
8413                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
8414                 break;
8415         case REG_B:
8416                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
8417                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
8418                 break;
8419         case REG_C_0:
8420                 /*
8421                  * The metadata register C0 field might be divided into
8422                  * source vport index and META item value, we should set
8423                  * this field according to specified mask, not as whole one.
8424                  */
8425                 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
8426                 temp |= mask;
8427                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
8428                 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
8429                 temp &= ~mask;
8430                 temp |= data;
8431                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
8432                 break;
8433         case REG_C_1:
8434                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
8435                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
8436                 break;
8437         case REG_C_2:
8438                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
8439                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
8440                 break;
8441         case REG_C_3:
8442                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
8443                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
8444                 break;
8445         case REG_C_4:
8446                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
8447                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
8448                 break;
8449         case REG_C_5:
8450                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
8451                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
8452                 break;
8453         case REG_C_6:
8454                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
8455                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
8456                 break;
8457         case REG_C_7:
8458                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
8459                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
8460                 break;
8461         default:
8462                 MLX5_ASSERT(false);
8463                 break;
8464         }
8465 }
8466
8467 /**
8468  * Add MARK item to matcher
8469  *
8470  * @param[in] dev
8471  *   The device to configure through.
8472  * @param[in, out] matcher
8473  *   Flow matcher.
8474  * @param[in, out] key
8475  *   Flow matcher value.
8476  * @param[in] item
8477  *   Flow pattern to translate.
8478  */
8479 static void
8480 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
8481                             void *matcher, void *key,
8482                             const struct rte_flow_item *item)
8483 {
8484         struct mlx5_priv *priv = dev->data->dev_private;
8485         const struct rte_flow_item_mark *mark;
8486         uint32_t value;
8487         uint32_t mask;
8488
8489         mark = item->mask ? (const void *)item->mask :
8490                             &rte_flow_item_mark_mask;
8491         mask = mark->id & priv->sh->dv_mark_mask;
8492         mark = (const void *)item->spec;
8493         MLX5_ASSERT(mark);
8494         value = mark->id & priv->sh->dv_mark_mask & mask;
8495         if (mask) {
8496                 enum modify_reg reg;
8497
8498                 /* Get the metadata register index for the mark. */
8499                 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
8500                 MLX5_ASSERT(reg > 0);
8501                 if (reg == REG_C_0) {
8502                         struct mlx5_priv *priv = dev->data->dev_private;
8503                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
8504                         uint32_t shl_c0 = rte_bsf32(msk_c0);
8505
8506                         mask &= msk_c0;
8507                         mask <<= shl_c0;
8508                         value <<= shl_c0;
8509                 }
8510                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
8511         }
8512 }
8513
8514 /**
8515  * Add META item to matcher
8516  *
8517  * @param[in] dev
8518  *   The devich to configure through.
8519  * @param[in, out] matcher
8520  *   Flow matcher.
8521  * @param[in, out] key
8522  *   Flow matcher value.
8523  * @param[in] attr
8524  *   Attributes of flow that includes this item.
8525  * @param[in] item
8526  *   Flow pattern to translate.
8527  */
8528 static void
8529 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
8530                             void *matcher, void *key,
8531                             const struct rte_flow_attr *attr,
8532                             const struct rte_flow_item *item)
8533 {
8534         const struct rte_flow_item_meta *meta_m;
8535         const struct rte_flow_item_meta *meta_v;
8536
8537         meta_m = (const void *)item->mask;
8538         if (!meta_m)
8539                 meta_m = &rte_flow_item_meta_mask;
8540         meta_v = (const void *)item->spec;
8541         if (meta_v) {
8542                 int reg;
8543                 uint32_t value = meta_v->data;
8544                 uint32_t mask = meta_m->data;
8545
8546                 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
8547                 if (reg < 0)
8548                         return;
8549                 MLX5_ASSERT(reg != REG_NON);
8550                 /*
8551                  * In datapath code there is no endianness
8552                  * coversions for perfromance reasons, all
8553                  * pattern conversions are done in rte_flow.
8554                  */
8555                 value = rte_cpu_to_be_32(value);
8556                 mask = rte_cpu_to_be_32(mask);
8557                 if (reg == REG_C_0) {
8558                         struct mlx5_priv *priv = dev->data->dev_private;
8559                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
8560                         uint32_t shl_c0 = rte_bsf32(msk_c0);
8561 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
8562                         uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
8563
8564                         value >>= shr_c0;
8565                         mask >>= shr_c0;
8566 #endif
8567                         value <<= shl_c0;
8568                         mask <<= shl_c0;
8569                         MLX5_ASSERT(msk_c0);
8570                         MLX5_ASSERT(!(~msk_c0 & mask));
8571                 }
8572                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
8573         }
8574 }
8575
8576 /**
8577  * Add vport metadata Reg C0 item to matcher
8578  *
8579  * @param[in, out] matcher
8580  *   Flow matcher.
8581  * @param[in, out] key
8582  *   Flow matcher value.
8583  * @param[in] reg
8584  *   Flow pattern to translate.
8585  */
8586 static void
8587 flow_dv_translate_item_meta_vport(void *matcher, void *key,
8588                                   uint32_t value, uint32_t mask)
8589 {
8590         flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
8591 }
8592
8593 /**
8594  * Add tag item to matcher
8595  *
8596  * @param[in] dev
8597  *   The devich to configure through.
8598  * @param[in, out] matcher
8599  *   Flow matcher.
8600  * @param[in, out] key
8601  *   Flow matcher value.
8602  * @param[in] item
8603  *   Flow pattern to translate.
8604  */
8605 static void
8606 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
8607                                 void *matcher, void *key,
8608                                 const struct rte_flow_item *item)
8609 {
8610         const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
8611         const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
8612         uint32_t mask, value;
8613
8614         MLX5_ASSERT(tag_v);
8615         value = tag_v->data;
8616         mask = tag_m ? tag_m->data : UINT32_MAX;
8617         if (tag_v->id == REG_C_0) {
8618                 struct mlx5_priv *priv = dev->data->dev_private;
8619                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
8620                 uint32_t shl_c0 = rte_bsf32(msk_c0);
8621
8622                 mask &= msk_c0;
8623                 mask <<= shl_c0;
8624                 value <<= shl_c0;
8625         }
8626         flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
8627 }
8628
8629 /**
8630  * Add TAG item to matcher
8631  *
8632  * @param[in] dev
8633  *   The devich to configure through.
8634  * @param[in, out] matcher
8635  *   Flow matcher.
8636  * @param[in, out] key
8637  *   Flow matcher value.
8638  * @param[in] item
8639  *   Flow pattern to translate.
8640  */
8641 static void
8642 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
8643                            void *matcher, void *key,
8644                            const struct rte_flow_item *item)
8645 {
8646         const struct rte_flow_item_tag *tag_v = item->spec;
8647         const struct rte_flow_item_tag *tag_m = item->mask;
8648         enum modify_reg reg;
8649
8650         MLX5_ASSERT(tag_v);
8651         tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
8652         /* Get the metadata register index for the tag. */
8653         reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
8654         MLX5_ASSERT(reg > 0);
8655         flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
8656 }
8657
8658 /**
8659  * Add source vport match to the specified matcher.
8660  *
8661  * @param[in, out] matcher
8662  *   Flow matcher.
8663  * @param[in, out] key
8664  *   Flow matcher value.
8665  * @param[in] port
8666  *   Source vport value to match
8667  * @param[in] mask
8668  *   Mask
8669  */
8670 static void
8671 flow_dv_translate_item_source_vport(void *matcher, void *key,
8672                                     int16_t port, uint16_t mask)
8673 {
8674         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8675         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8676
8677         MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
8678         MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
8679 }
8680
8681 /**
8682  * Translate port-id item to eswitch match on  port-id.
8683  *
8684  * @param[in] dev
8685  *   The devich to configure through.
8686  * @param[in, out] matcher
8687  *   Flow matcher.
8688  * @param[in, out] key
8689  *   Flow matcher value.
8690  * @param[in] item
8691  *   Flow pattern to translate.
8692  * @param[in]
8693  *   Flow attributes.
8694  *
8695  * @return
8696  *   0 on success, a negative errno value otherwise.
8697  */
8698 static int
8699 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
8700                                void *key, const struct rte_flow_item *item,
8701                                const struct rte_flow_attr *attr)
8702 {
8703         const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
8704         const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
8705         struct mlx5_priv *priv;
8706         uint16_t mask, id;
8707
8708         mask = pid_m ? pid_m->id : 0xffff;
8709         id = pid_v ? pid_v->id : dev->data->port_id;
8710         priv = mlx5_port_to_eswitch_info(id, item == NULL);
8711         if (!priv)
8712                 return -rte_errno;
8713         /*
8714          * Translate to vport field or to metadata, depending on mode.
8715          * Kernel can use either misc.source_port or half of C0 metadata
8716          * register.
8717          */
8718         if (priv->vport_meta_mask) {
8719                 /*
8720                  * Provide the hint for SW steering library
8721                  * to insert the flow into ingress domain and
8722                  * save the extra vport match.
8723                  */
8724                 if (mask == 0xffff && priv->vport_id == 0xffff &&
8725                     priv->pf_bond < 0 && attr->transfer)
8726                         flow_dv_translate_item_source_vport
8727                                 (matcher, key, priv->vport_id, mask);
8728                 /*
8729                  * We should always set the vport metadata register,
8730                  * otherwise the SW steering library can drop
8731                  * the rule if wire vport metadata value is not zero,
8732                  * it depends on kernel configuration.
8733                  */
8734                 flow_dv_translate_item_meta_vport(matcher, key,
8735                                                   priv->vport_meta_tag,
8736                                                   priv->vport_meta_mask);
8737         } else {
8738                 flow_dv_translate_item_source_vport(matcher, key,
8739                                                     priv->vport_id, mask);
8740         }
8741         return 0;
8742 }
8743
8744 /**
8745  * Add ICMP6 item to matcher and to the value.
8746  *
8747  * @param[in, out] matcher
8748  *   Flow matcher.
8749  * @param[in, out] key
8750  *   Flow matcher value.
8751  * @param[in] item
8752  *   Flow pattern to translate.
8753  * @param[in] inner
8754  *   Item is inner pattern.
8755  */
8756 static void
8757 flow_dv_translate_item_icmp6(void *matcher, void *key,
8758                               const struct rte_flow_item *item,
8759                               int inner)
8760 {
8761         const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
8762         const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
8763         void *headers_m;
8764         void *headers_v;
8765         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8766                                      misc_parameters_3);
8767         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8768         if (inner) {
8769                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8770                                          inner_headers);
8771                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8772         } else {
8773                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8774                                          outer_headers);
8775                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8776         }
8777         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
8778         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
8779         if (!icmp6_v)
8780                 return;
8781         if (!icmp6_m)
8782                 icmp6_m = &rte_flow_item_icmp6_mask;
8783         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
8784         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
8785                  icmp6_v->type & icmp6_m->type);
8786         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
8787         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
8788                  icmp6_v->code & icmp6_m->code);
8789 }
8790
8791 /**
8792  * Add ICMP item to matcher and to the value.
8793  *
8794  * @param[in, out] matcher
8795  *   Flow matcher.
8796  * @param[in, out] key
8797  *   Flow matcher value.
8798  * @param[in] item
8799  *   Flow pattern to translate.
8800  * @param[in] inner
8801  *   Item is inner pattern.
8802  */
8803 static void
8804 flow_dv_translate_item_icmp(void *matcher, void *key,
8805                             const struct rte_flow_item *item,
8806                             int inner)
8807 {
8808         const struct rte_flow_item_icmp *icmp_m = item->mask;
8809         const struct rte_flow_item_icmp *icmp_v = item->spec;
8810         uint32_t icmp_header_data_m = 0;
8811         uint32_t icmp_header_data_v = 0;
8812         void *headers_m;
8813         void *headers_v;
8814         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8815                                      misc_parameters_3);
8816         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8817         if (inner) {
8818                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8819                                          inner_headers);
8820                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8821         } else {
8822                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8823                                          outer_headers);
8824                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8825         }
8826         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
8827         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
8828         if (!icmp_v)
8829                 return;
8830         if (!icmp_m)
8831                 icmp_m = &rte_flow_item_icmp_mask;
8832         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
8833                  icmp_m->hdr.icmp_type);
8834         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
8835                  icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
8836         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
8837                  icmp_m->hdr.icmp_code);
8838         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
8839                  icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
8840         icmp_header_data_m = rte_be_to_cpu_16(icmp_m->hdr.icmp_seq_nb);
8841         icmp_header_data_m |= rte_be_to_cpu_16(icmp_m->hdr.icmp_ident) << 16;
8842         if (icmp_header_data_m) {
8843                 icmp_header_data_v = rte_be_to_cpu_16(icmp_v->hdr.icmp_seq_nb);
8844                 icmp_header_data_v |=
8845                          rte_be_to_cpu_16(icmp_v->hdr.icmp_ident) << 16;
8846                 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_header_data,
8847                          icmp_header_data_m);
8848                 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_header_data,
8849                          icmp_header_data_v & icmp_header_data_m);
8850         }
8851 }
8852
8853 /**
8854  * Add GTP item to matcher and to the value.
8855  *
8856  * @param[in, out] matcher
8857  *   Flow matcher.
8858  * @param[in, out] key
8859  *   Flow matcher value.
8860  * @param[in] item
8861  *   Flow pattern to translate.
8862  * @param[in] inner
8863  *   Item is inner pattern.
8864  */
8865 static void
8866 flow_dv_translate_item_gtp(void *matcher, void *key,
8867                            const struct rte_flow_item *item, int inner)
8868 {
8869         const struct rte_flow_item_gtp *gtp_m = item->mask;
8870         const struct rte_flow_item_gtp *gtp_v = item->spec;
8871         void *headers_m;
8872         void *headers_v;
8873         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8874                                      misc_parameters_3);
8875         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8876         uint16_t dport = RTE_GTPU_UDP_PORT;
8877
8878         if (inner) {
8879                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8880                                          inner_headers);
8881                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8882         } else {
8883                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8884                                          outer_headers);
8885                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8886         }
8887         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8888                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8889                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8890         }
8891         if (!gtp_v)
8892                 return;
8893         if (!gtp_m)
8894                 gtp_m = &rte_flow_item_gtp_mask;
8895         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags,
8896                  gtp_m->v_pt_rsv_flags);
8897         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags,
8898                  gtp_v->v_pt_rsv_flags & gtp_m->v_pt_rsv_flags);
8899         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
8900         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
8901                  gtp_v->msg_type & gtp_m->msg_type);
8902         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
8903                  rte_be_to_cpu_32(gtp_m->teid));
8904         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
8905                  rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
8906 }
8907
8908 /**
8909  * Add GTP PSC item to matcher.
8910  *
8911  * @param[in, out] matcher
8912  *   Flow matcher.
8913  * @param[in, out] key
8914  *   Flow matcher value.
8915  * @param[in] item
8916  *   Flow pattern to translate.
8917  */
8918 static int
8919 flow_dv_translate_item_gtp_psc(void *matcher, void *key,
8920                                const struct rte_flow_item *item)
8921 {
8922         const struct rte_flow_item_gtp_psc *gtp_psc_m = item->mask;
8923         const struct rte_flow_item_gtp_psc *gtp_psc_v = item->spec;
8924         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8925                         misc_parameters_3);
8926         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8927         union {
8928                 uint32_t w32;
8929                 struct {
8930                         uint16_t seq_num;
8931                         uint8_t npdu_num;
8932                         uint8_t next_ext_header_type;
8933                 };
8934         } dw_2;
8935         uint8_t gtp_flags;
8936
8937         /* Always set E-flag match on one, regardless of GTP item settings. */
8938         gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_m, gtpu_msg_flags);
8939         gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
8940         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags, gtp_flags);
8941         gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_v, gtpu_msg_flags);
8942         gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
8943         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags, gtp_flags);
8944         /*Set next extension header type. */
8945         dw_2.seq_num = 0;
8946         dw_2.npdu_num = 0;
8947         dw_2.next_ext_header_type = 0xff;
8948         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_dw_2,
8949                  rte_cpu_to_be_32(dw_2.w32));
8950         dw_2.seq_num = 0;
8951         dw_2.npdu_num = 0;
8952         dw_2.next_ext_header_type = 0x85;
8953         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_dw_2,
8954                  rte_cpu_to_be_32(dw_2.w32));
8955         if (gtp_psc_v) {
8956                 union {
8957                         uint32_t w32;
8958                         struct {
8959                                 uint8_t len;
8960                                 uint8_t type_flags;
8961                                 uint8_t qfi;
8962                                 uint8_t reserved;
8963                         };
8964                 } dw_0;
8965
8966                 /*Set extension header PDU type and Qos. */
8967                 if (!gtp_psc_m)
8968                         gtp_psc_m = &rte_flow_item_gtp_psc_mask;
8969                 dw_0.w32 = 0;
8970                 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_m->pdu_type);
8971                 dw_0.qfi = gtp_psc_m->qfi;
8972                 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_first_ext_dw_0,
8973                          rte_cpu_to_be_32(dw_0.w32));
8974                 dw_0.w32 = 0;
8975                 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_v->pdu_type &
8976                                                         gtp_psc_m->pdu_type);
8977                 dw_0.qfi = gtp_psc_v->qfi & gtp_psc_m->qfi;
8978                 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_first_ext_dw_0,
8979                          rte_cpu_to_be_32(dw_0.w32));
8980         }
8981         return 0;
8982 }
8983
8984 /**
8985  * Add eCPRI item to matcher and to the value.
8986  *
8987  * @param[in] dev
8988  *   The devich to configure through.
8989  * @param[in, out] matcher
8990  *   Flow matcher.
8991  * @param[in, out] key
8992  *   Flow matcher value.
8993  * @param[in] item
8994  *   Flow pattern to translate.
8995  * @param[in] samples
8996  *   Sample IDs to be used in the matching.
8997  */
8998 static void
8999 flow_dv_translate_item_ecpri(struct rte_eth_dev *dev, void *matcher,
9000                              void *key, const struct rte_flow_item *item)
9001 {
9002         struct mlx5_priv *priv = dev->data->dev_private;
9003         const struct rte_flow_item_ecpri *ecpri_m = item->mask;
9004         const struct rte_flow_item_ecpri *ecpri_v = item->spec;
9005         struct rte_ecpri_common_hdr common;
9006         void *misc4_m = MLX5_ADDR_OF(fte_match_param, matcher,
9007                                      misc_parameters_4);
9008         void *misc4_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_4);
9009         uint32_t *samples;
9010         void *dw_m;
9011         void *dw_v;
9012
9013         if (!ecpri_v)
9014                 return;
9015         if (!ecpri_m)
9016                 ecpri_m = &rte_flow_item_ecpri_mask;
9017         /*
9018          * Maximal four DW samples are supported in a single matching now.
9019          * Two are used now for a eCPRI matching:
9020          * 1. Type: one byte, mask should be 0x00ff0000 in network order
9021          * 2. ID of a message: one or two bytes, mask 0xffff0000 or 0xff000000
9022          *    if any.
9023          */
9024         if (!ecpri_m->hdr.common.u32)
9025                 return;
9026         samples = priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0].ids;
9027         /* Need to take the whole DW as the mask to fill the entry. */
9028         dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
9029                             prog_sample_field_value_0);
9030         dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
9031                             prog_sample_field_value_0);
9032         /* Already big endian (network order) in the header. */
9033         *(uint32_t *)dw_m = ecpri_m->hdr.common.u32;
9034         *(uint32_t *)dw_v = ecpri_v->hdr.common.u32 & ecpri_m->hdr.common.u32;
9035         /* Sample#0, used for matching type, offset 0. */
9036         MLX5_SET(fte_match_set_misc4, misc4_m,
9037                  prog_sample_field_id_0, samples[0]);
9038         /* It makes no sense to set the sample ID in the mask field. */
9039         MLX5_SET(fte_match_set_misc4, misc4_v,
9040                  prog_sample_field_id_0, samples[0]);
9041         /*
9042          * Checking if message body part needs to be matched.
9043          * Some wildcard rules only matching type field should be supported.
9044          */
9045         if (ecpri_m->hdr.dummy[0]) {
9046                 common.u32 = rte_be_to_cpu_32(ecpri_v->hdr.common.u32);
9047                 switch (common.type) {
9048                 case RTE_ECPRI_MSG_TYPE_IQ_DATA:
9049                 case RTE_ECPRI_MSG_TYPE_RTC_CTRL:
9050                 case RTE_ECPRI_MSG_TYPE_DLY_MSR:
9051                         dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
9052                                             prog_sample_field_value_1);
9053                         dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
9054                                             prog_sample_field_value_1);
9055                         *(uint32_t *)dw_m = ecpri_m->hdr.dummy[0];
9056                         *(uint32_t *)dw_v = ecpri_v->hdr.dummy[0] &
9057                                             ecpri_m->hdr.dummy[0];
9058                         /* Sample#1, to match message body, offset 4. */
9059                         MLX5_SET(fte_match_set_misc4, misc4_m,
9060                                  prog_sample_field_id_1, samples[1]);
9061                         MLX5_SET(fte_match_set_misc4, misc4_v,
9062                                  prog_sample_field_id_1, samples[1]);
9063                         break;
9064                 default:
9065                         /* Others, do not match any sample ID. */
9066                         break;
9067                 }
9068         }
9069 }
9070
9071 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
9072
9073 #define HEADER_IS_ZERO(match_criteria, headers)                              \
9074         !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers),     \
9075                  matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
9076
9077 /**
9078  * Calculate flow matcher enable bitmap.
9079  *
9080  * @param match_criteria
9081  *   Pointer to flow matcher criteria.
9082  *
9083  * @return
9084  *   Bitmap of enabled fields.
9085  */
9086 static uint8_t
9087 flow_dv_matcher_enable(uint32_t *match_criteria)
9088 {
9089         uint8_t match_criteria_enable;
9090
9091         match_criteria_enable =
9092                 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
9093                 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
9094         match_criteria_enable |=
9095                 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
9096                 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
9097         match_criteria_enable |=
9098                 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
9099                 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
9100         match_criteria_enable |=
9101                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
9102                 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
9103         match_criteria_enable |=
9104                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
9105                 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
9106         match_criteria_enable |=
9107                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_4)) <<
9108                 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT;
9109         return match_criteria_enable;
9110 }
9111
9112 struct mlx5_hlist_entry *
9113 flow_dv_tbl_create_cb(struct mlx5_hlist *list, uint64_t key64, void *cb_ctx)
9114 {
9115         struct mlx5_dev_ctx_shared *sh = list->ctx;
9116         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9117         struct rte_eth_dev *dev = ctx->dev;
9118         struct mlx5_flow_tbl_data_entry *tbl_data;
9119         struct mlx5_flow_tbl_tunnel_prm *tt_prm = ctx->data;
9120         struct rte_flow_error *error = ctx->error;
9121         union mlx5_flow_tbl_key key = { .v64 = key64 };
9122         struct mlx5_flow_tbl_resource *tbl;
9123         void *domain;
9124         uint32_t idx = 0;
9125         int ret;
9126
9127         tbl_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
9128         if (!tbl_data) {
9129                 rte_flow_error_set(error, ENOMEM,
9130                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9131                                    NULL,
9132                                    "cannot allocate flow table data entry");
9133                 return NULL;
9134         }
9135         tbl_data->idx = idx;
9136         tbl_data->tunnel = tt_prm->tunnel;
9137         tbl_data->group_id = tt_prm->group_id;
9138         tbl_data->external = !!tt_prm->external;
9139         tbl_data->tunnel_offload = is_tunnel_offload_active(dev);
9140         tbl_data->is_egress = !!key.direction;
9141         tbl_data->is_transfer = !!key.domain;
9142         tbl_data->dummy = !!key.dummy;
9143         tbl_data->table_id = key.table_id;
9144         tbl = &tbl_data->tbl;
9145         if (key.dummy)
9146                 return &tbl_data->entry;
9147         if (key.domain)
9148                 domain = sh->fdb_domain;
9149         else if (key.direction)
9150                 domain = sh->tx_domain;
9151         else
9152                 domain = sh->rx_domain;
9153         ret = mlx5_flow_os_create_flow_tbl(domain, key.table_id, &tbl->obj);
9154         if (ret) {
9155                 rte_flow_error_set(error, ENOMEM,
9156                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9157                                    NULL, "cannot create flow table object");
9158                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
9159                 return NULL;
9160         }
9161         if (key.table_id) {
9162                 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
9163                                         (tbl->obj, &tbl_data->jump.action);
9164                 if (ret) {
9165                         rte_flow_error_set(error, ENOMEM,
9166                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9167                                            NULL,
9168                                            "cannot create flow jump action");
9169                         mlx5_flow_os_destroy_flow_tbl(tbl->obj);
9170                         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
9171                         return NULL;
9172                 }
9173         }
9174         MKSTR(matcher_name, "%s_%s_%u_matcher_cache",
9175               key.domain ? "FDB" : "NIC", key.direction ? "egress" : "ingress",
9176               key.table_id);
9177         mlx5_cache_list_init(&tbl_data->matchers, matcher_name, 0, sh,
9178                              flow_dv_matcher_create_cb,
9179                              flow_dv_matcher_match_cb,
9180                              flow_dv_matcher_remove_cb);
9181         return &tbl_data->entry;
9182 }
9183
9184 int
9185 flow_dv_tbl_match_cb(struct mlx5_hlist *list __rte_unused,
9186                      struct mlx5_hlist_entry *entry, uint64_t key64,
9187                      void *cb_ctx __rte_unused)
9188 {
9189         struct mlx5_flow_tbl_data_entry *tbl_data =
9190                 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
9191         union mlx5_flow_tbl_key key = { .v64 = key64 };
9192
9193         return tbl_data->table_id != key.table_id ||
9194                tbl_data->dummy != key.dummy ||
9195                tbl_data->is_transfer != key.domain ||
9196                tbl_data->is_egress != key.direction;
9197 }
9198
9199 /**
9200  * Get a flow table.
9201  *
9202  * @param[in, out] dev
9203  *   Pointer to rte_eth_dev structure.
9204  * @param[in] table_id
9205  *   Table id to use.
9206  * @param[in] egress
9207  *   Direction of the table.
9208  * @param[in] transfer
9209  *   E-Switch or NIC flow.
9210  * @param[in] dummy
9211  *   Dummy entry for dv API.
9212  * @param[out] error
9213  *   pointer to error structure.
9214  *
9215  * @return
9216  *   Returns tables resource based on the index, NULL in case of failed.
9217  */
9218 struct mlx5_flow_tbl_resource *
9219 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
9220                          uint32_t table_id, uint8_t egress,
9221                          uint8_t transfer,
9222                          bool external,
9223                          const struct mlx5_flow_tunnel *tunnel,
9224                          uint32_t group_id, uint8_t dummy,
9225                          struct rte_flow_error *error)
9226 {
9227         struct mlx5_priv *priv = dev->data->dev_private;
9228         union mlx5_flow_tbl_key table_key = {
9229                 {
9230                         .table_id = table_id,
9231                         .dummy = dummy,
9232                         .domain = !!transfer,
9233                         .direction = !!egress,
9234                 }
9235         };
9236         struct mlx5_flow_tbl_tunnel_prm tt_prm = {
9237                 .tunnel = tunnel,
9238                 .group_id = group_id,
9239                 .external = external,
9240         };
9241         struct mlx5_flow_cb_ctx ctx = {
9242                 .dev = dev,
9243                 .error = error,
9244                 .data = &tt_prm,
9245         };
9246         struct mlx5_hlist_entry *entry;
9247         struct mlx5_flow_tbl_data_entry *tbl_data;
9248
9249         entry = mlx5_hlist_register(priv->sh->flow_tbls, table_key.v64, &ctx);
9250         if (!entry) {
9251                 rte_flow_error_set(error, ENOMEM,
9252                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9253                                    "cannot get table");
9254                 return NULL;
9255         }
9256         DRV_LOG(DEBUG, "Table_id %u tunnel %u group %u registered.",
9257                 table_id, tunnel ? tunnel->tunnel_id : 0, group_id);
9258         tbl_data = container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
9259         return &tbl_data->tbl;
9260 }
9261
9262 void
9263 flow_dv_tbl_remove_cb(struct mlx5_hlist *list,
9264                       struct mlx5_hlist_entry *entry)
9265 {
9266         struct mlx5_dev_ctx_shared *sh = list->ctx;
9267         struct mlx5_flow_tbl_data_entry *tbl_data =
9268                 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
9269
9270         MLX5_ASSERT(entry && sh);
9271         if (tbl_data->jump.action)
9272                 mlx5_flow_os_destroy_flow_action(tbl_data->jump.action);
9273         if (tbl_data->tbl.obj)
9274                 mlx5_flow_os_destroy_flow_tbl(tbl_data->tbl.obj);
9275         if (tbl_data->tunnel_offload && tbl_data->external) {
9276                 struct mlx5_hlist_entry *he;
9277                 struct mlx5_hlist *tunnel_grp_hash;
9278                 struct mlx5_flow_tunnel_hub *thub = sh->tunnel_hub;
9279                 union tunnel_tbl_key tunnel_key = {
9280                         .tunnel_id = tbl_data->tunnel ?
9281                                         tbl_data->tunnel->tunnel_id : 0,
9282                         .group = tbl_data->group_id
9283                 };
9284                 uint32_t table_id = tbl_data->table_id;
9285
9286                 tunnel_grp_hash = tbl_data->tunnel ?
9287                                         tbl_data->tunnel->groups :
9288                                         thub->groups;
9289                 he = mlx5_hlist_lookup(tunnel_grp_hash, tunnel_key.val, NULL);
9290                 if (he)
9291                         mlx5_hlist_unregister(tunnel_grp_hash, he);
9292                 DRV_LOG(DEBUG,
9293                         "Table_id %u tunnel %u group %u released.",
9294                         table_id,
9295                         tbl_data->tunnel ?
9296                         tbl_data->tunnel->tunnel_id : 0,
9297                         tbl_data->group_id);
9298         }
9299         mlx5_cache_list_destroy(&tbl_data->matchers);
9300         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], tbl_data->idx);
9301 }
9302
9303 /**
9304  * Release a flow table.
9305  *
9306  * @param[in] sh
9307  *   Pointer to device shared structure.
9308  * @param[in] tbl
9309  *   Table resource to be released.
9310  *
9311  * @return
9312  *   Returns 0 if table was released, else return 1;
9313  */
9314 static int
9315 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
9316                              struct mlx5_flow_tbl_resource *tbl)
9317 {
9318         struct mlx5_flow_tbl_data_entry *tbl_data =
9319                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
9320
9321         if (!tbl)
9322                 return 0;
9323         return mlx5_hlist_unregister(sh->flow_tbls, &tbl_data->entry);
9324 }
9325
9326 int
9327 flow_dv_matcher_match_cb(struct mlx5_cache_list *list __rte_unused,
9328                          struct mlx5_cache_entry *entry, void *cb_ctx)
9329 {
9330         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9331         struct mlx5_flow_dv_matcher *ref = ctx->data;
9332         struct mlx5_flow_dv_matcher *cur = container_of(entry, typeof(*cur),
9333                                                         entry);
9334
9335         return cur->crc != ref->crc ||
9336                cur->priority != ref->priority ||
9337                memcmp((const void *)cur->mask.buf,
9338                       (const void *)ref->mask.buf, ref->mask.size);
9339 }
9340
9341 struct mlx5_cache_entry *
9342 flow_dv_matcher_create_cb(struct mlx5_cache_list *list,
9343                           struct mlx5_cache_entry *entry __rte_unused,
9344                           void *cb_ctx)
9345 {
9346         struct mlx5_dev_ctx_shared *sh = list->ctx;
9347         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9348         struct mlx5_flow_dv_matcher *ref = ctx->data;
9349         struct mlx5_flow_dv_matcher *cache;
9350         struct mlx5dv_flow_matcher_attr dv_attr = {
9351                 .type = IBV_FLOW_ATTR_NORMAL,
9352                 .match_mask = (void *)&ref->mask,
9353         };
9354         struct mlx5_flow_tbl_data_entry *tbl = container_of(ref->tbl,
9355                                                             typeof(*tbl), tbl);
9356         int ret;
9357
9358         cache = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*cache), 0, SOCKET_ID_ANY);
9359         if (!cache) {
9360                 rte_flow_error_set(ctx->error, ENOMEM,
9361                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9362                                    "cannot create matcher");
9363                 return NULL;
9364         }
9365         *cache = *ref;
9366         dv_attr.match_criteria_enable =
9367                 flow_dv_matcher_enable(cache->mask.buf);
9368         dv_attr.priority = ref->priority;
9369         if (tbl->is_egress)
9370                 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
9371         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->tbl.obj,
9372                                                &cache->matcher_object);
9373         if (ret) {
9374                 mlx5_free(cache);
9375                 rte_flow_error_set(ctx->error, ENOMEM,
9376                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9377                                    "cannot create matcher");
9378                 return NULL;
9379         }
9380         return &cache->entry;
9381 }
9382
9383 /**
9384  * Register the flow matcher.
9385  *
9386  * @param[in, out] dev
9387  *   Pointer to rte_eth_dev structure.
9388  * @param[in, out] matcher
9389  *   Pointer to flow matcher.
9390  * @param[in, out] key
9391  *   Pointer to flow table key.
9392  * @parm[in, out] dev_flow
9393  *   Pointer to the dev_flow.
9394  * @param[out] error
9395  *   pointer to error structure.
9396  *
9397  * @return
9398  *   0 on success otherwise -errno and errno is set.
9399  */
9400 static int
9401 flow_dv_matcher_register(struct rte_eth_dev *dev,
9402                          struct mlx5_flow_dv_matcher *ref,
9403                          union mlx5_flow_tbl_key *key,
9404                          struct mlx5_flow *dev_flow,
9405                          const struct mlx5_flow_tunnel *tunnel,
9406                          uint32_t group_id,
9407                          struct rte_flow_error *error)
9408 {
9409         struct mlx5_cache_entry *entry;
9410         struct mlx5_flow_dv_matcher *cache;
9411         struct mlx5_flow_tbl_resource *tbl;
9412         struct mlx5_flow_tbl_data_entry *tbl_data;
9413         struct mlx5_flow_cb_ctx ctx = {
9414                 .error = error,
9415                 .data = ref,
9416         };
9417
9418         /**
9419          * tunnel offload API requires this registration for cases when
9420          * tunnel match rule was inserted before tunnel set rule.
9421          */
9422         tbl = flow_dv_tbl_resource_get(dev, key->table_id,
9423                                        key->direction, key->domain,
9424                                        dev_flow->external, tunnel,
9425                                        group_id, 0, error);
9426         if (!tbl)
9427                 return -rte_errno;      /* No need to refill the error info */
9428         tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
9429         ref->tbl = tbl;
9430         entry = mlx5_cache_register(&tbl_data->matchers, &ctx);
9431         if (!entry) {
9432                 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
9433                 return rte_flow_error_set(error, ENOMEM,
9434                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9435                                           "cannot allocate ref memory");
9436         }
9437         cache = container_of(entry, typeof(*cache), entry);
9438         dev_flow->handle->dvh.matcher = cache;
9439         return 0;
9440 }
9441
9442 struct mlx5_hlist_entry *
9443 flow_dv_tag_create_cb(struct mlx5_hlist *list, uint64_t key, void *ctx)
9444 {
9445         struct mlx5_dev_ctx_shared *sh = list->ctx;
9446         struct rte_flow_error *error = ctx;
9447         struct mlx5_flow_dv_tag_resource *entry;
9448         uint32_t idx = 0;
9449         int ret;
9450
9451         entry = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_TAG], &idx);
9452         if (!entry) {
9453                 rte_flow_error_set(error, ENOMEM,
9454                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9455                                    "cannot allocate resource memory");
9456                 return NULL;
9457         }
9458         entry->idx = idx;
9459         entry->tag_id = key;
9460         ret = mlx5_flow_os_create_flow_action_tag(key,
9461                                                   &entry->action);
9462         if (ret) {
9463                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], idx);
9464                 rte_flow_error_set(error, ENOMEM,
9465                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9466                                    NULL, "cannot create action");
9467                 return NULL;
9468         }
9469         return &entry->entry;
9470 }
9471
9472 int
9473 flow_dv_tag_match_cb(struct mlx5_hlist *list __rte_unused,
9474                      struct mlx5_hlist_entry *entry, uint64_t key,
9475                      void *cb_ctx __rte_unused)
9476 {
9477         struct mlx5_flow_dv_tag_resource *tag =
9478                 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
9479
9480         return key != tag->tag_id;
9481 }
9482
9483 /**
9484  * Find existing tag resource or create and register a new one.
9485  *
9486  * @param dev[in, out]
9487  *   Pointer to rte_eth_dev structure.
9488  * @param[in, out] tag_be24
9489  *   Tag value in big endian then R-shift 8.
9490  * @parm[in, out] dev_flow
9491  *   Pointer to the dev_flow.
9492  * @param[out] error
9493  *   pointer to error structure.
9494  *
9495  * @return
9496  *   0 on success otherwise -errno and errno is set.
9497  */
9498 static int
9499 flow_dv_tag_resource_register
9500                         (struct rte_eth_dev *dev,
9501                          uint32_t tag_be24,
9502                          struct mlx5_flow *dev_flow,
9503                          struct rte_flow_error *error)
9504 {
9505         struct mlx5_priv *priv = dev->data->dev_private;
9506         struct mlx5_flow_dv_tag_resource *cache_resource;
9507         struct mlx5_hlist_entry *entry;
9508
9509         entry = mlx5_hlist_register(priv->sh->tag_table, tag_be24, error);
9510         if (entry) {
9511                 cache_resource = container_of
9512                         (entry, struct mlx5_flow_dv_tag_resource, entry);
9513                 dev_flow->handle->dvh.rix_tag = cache_resource->idx;
9514                 dev_flow->dv.tag_resource = cache_resource;
9515                 return 0;
9516         }
9517         return -rte_errno;
9518 }
9519
9520 void
9521 flow_dv_tag_remove_cb(struct mlx5_hlist *list,
9522                       struct mlx5_hlist_entry *entry)
9523 {
9524         struct mlx5_dev_ctx_shared *sh = list->ctx;
9525         struct mlx5_flow_dv_tag_resource *tag =
9526                 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
9527
9528         MLX5_ASSERT(tag && sh && tag->action);
9529         claim_zero(mlx5_flow_os_destroy_flow_action(tag->action));
9530         DRV_LOG(DEBUG, "Tag %p: removed.", (void *)tag);
9531         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], tag->idx);
9532 }
9533
9534 /**
9535  * Release the tag.
9536  *
9537  * @param dev
9538  *   Pointer to Ethernet device.
9539  * @param tag_idx
9540  *   Tag index.
9541  *
9542  * @return
9543  *   1 while a reference on it exists, 0 when freed.
9544  */
9545 static int
9546 flow_dv_tag_release(struct rte_eth_dev *dev,
9547                     uint32_t tag_idx)
9548 {
9549         struct mlx5_priv *priv = dev->data->dev_private;
9550         struct mlx5_flow_dv_tag_resource *tag;
9551
9552         tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
9553         if (!tag)
9554                 return 0;
9555         DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
9556                 dev->data->port_id, (void *)tag, tag->entry.ref_cnt);
9557         return mlx5_hlist_unregister(priv->sh->tag_table, &tag->entry);
9558 }
9559
9560 /**
9561  * Translate port ID action to vport.
9562  *
9563  * @param[in] dev
9564  *   Pointer to rte_eth_dev structure.
9565  * @param[in] action
9566  *   Pointer to the port ID action.
9567  * @param[out] dst_port_id
9568  *   The target port ID.
9569  * @param[out] error
9570  *   Pointer to the error structure.
9571  *
9572  * @return
9573  *   0 on success, a negative errno value otherwise and rte_errno is set.
9574  */
9575 static int
9576 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
9577                                  const struct rte_flow_action *action,
9578                                  uint32_t *dst_port_id,
9579                                  struct rte_flow_error *error)
9580 {
9581         uint32_t port;
9582         struct mlx5_priv *priv;
9583         const struct rte_flow_action_port_id *conf =
9584                         (const struct rte_flow_action_port_id *)action->conf;
9585
9586         port = conf->original ? dev->data->port_id : conf->id;
9587         priv = mlx5_port_to_eswitch_info(port, false);
9588         if (!priv)
9589                 return rte_flow_error_set(error, -rte_errno,
9590                                           RTE_FLOW_ERROR_TYPE_ACTION,
9591                                           NULL,
9592                                           "No eswitch info was found for port");
9593 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
9594         /*
9595          * This parameter is transferred to
9596          * mlx5dv_dr_action_create_dest_ib_port().
9597          */
9598         *dst_port_id = priv->dev_port;
9599 #else
9600         /*
9601          * Legacy mode, no LAG configurations is supported.
9602          * This parameter is transferred to
9603          * mlx5dv_dr_action_create_dest_vport().
9604          */
9605         *dst_port_id = priv->vport_id;
9606 #endif
9607         return 0;
9608 }
9609
9610 /**
9611  * Create a counter with aging configuration.
9612  *
9613  * @param[in] dev
9614  *   Pointer to rte_eth_dev structure.
9615  * @param[out] count
9616  *   Pointer to the counter action configuration.
9617  * @param[in] age
9618  *   Pointer to the aging action configuration.
9619  *
9620  * @return
9621  *   Index to flow counter on success, 0 otherwise.
9622  */
9623 static uint32_t
9624 flow_dv_translate_create_counter(struct rte_eth_dev *dev,
9625                                 struct mlx5_flow *dev_flow,
9626                                 const struct rte_flow_action_count *count,
9627                                 const struct rte_flow_action_age *age)
9628 {
9629         uint32_t counter;
9630         struct mlx5_age_param *age_param;
9631
9632         if (count && count->shared)
9633                 counter = flow_dv_counter_get_shared(dev, count->id);
9634         else
9635                 counter = flow_dv_counter_alloc(dev, !!age);
9636         if (!counter || age == NULL)
9637                 return counter;
9638         age_param  = flow_dv_counter_idx_get_age(dev, counter);
9639         age_param->context = age->context ? age->context :
9640                 (void *)(uintptr_t)(dev_flow->flow_idx);
9641         age_param->timeout = age->timeout;
9642         age_param->port_id = dev->data->port_id;
9643         __atomic_store_n(&age_param->sec_since_last_hit, 0, __ATOMIC_RELAXED);
9644         __atomic_store_n(&age_param->state, AGE_CANDIDATE, __ATOMIC_RELAXED);
9645         return counter;
9646 }
9647
9648 /**
9649  * Add Tx queue matcher
9650  *
9651  * @param[in] dev
9652  *   Pointer to the dev struct.
9653  * @param[in, out] matcher
9654  *   Flow matcher.
9655  * @param[in, out] key
9656  *   Flow matcher value.
9657  * @param[in] item
9658  *   Flow pattern to translate.
9659  * @param[in] inner
9660  *   Item is inner pattern.
9661  */
9662 static void
9663 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
9664                                 void *matcher, void *key,
9665                                 const struct rte_flow_item *item)
9666 {
9667         const struct mlx5_rte_flow_item_tx_queue *queue_m;
9668         const struct mlx5_rte_flow_item_tx_queue *queue_v;
9669         void *misc_m =
9670                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
9671         void *misc_v =
9672                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
9673         struct mlx5_txq_ctrl *txq;
9674         uint32_t queue;
9675
9676
9677         queue_m = (const void *)item->mask;
9678         if (!queue_m)
9679                 return;
9680         queue_v = (const void *)item->spec;
9681         if (!queue_v)
9682                 return;
9683         txq = mlx5_txq_get(dev, queue_v->queue);
9684         if (!txq)
9685                 return;
9686         queue = txq->obj->sq->id;
9687         MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
9688         MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
9689                  queue & queue_m->queue);
9690         mlx5_txq_release(dev, queue_v->queue);
9691 }
9692
9693 /**
9694  * Set the hash fields according to the @p flow information.
9695  *
9696  * @param[in] dev_flow
9697  *   Pointer to the mlx5_flow.
9698  * @param[in] rss_desc
9699  *   Pointer to the mlx5_flow_rss_desc.
9700  */
9701 static void
9702 flow_dv_hashfields_set(struct mlx5_flow *dev_flow,
9703                        struct mlx5_flow_rss_desc *rss_desc)
9704 {
9705         uint64_t items = dev_flow->handle->layers;
9706         int rss_inner = 0;
9707         uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
9708
9709         dev_flow->hash_fields = 0;
9710 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
9711         if (rss_desc->level >= 2) {
9712                 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
9713                 rss_inner = 1;
9714         }
9715 #endif
9716         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
9717             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
9718                 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
9719                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
9720                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
9721                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
9722                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
9723                         else
9724                                 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
9725                 }
9726         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
9727                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
9728                 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
9729                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
9730                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
9731                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
9732                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
9733                         else
9734                                 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
9735                 }
9736         }
9737         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
9738             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
9739                 if (rss_types & ETH_RSS_UDP) {
9740                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
9741                                 dev_flow->hash_fields |=
9742                                                 IBV_RX_HASH_SRC_PORT_UDP;
9743                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
9744                                 dev_flow->hash_fields |=
9745                                                 IBV_RX_HASH_DST_PORT_UDP;
9746                         else
9747                                 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
9748                 }
9749         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
9750                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
9751                 if (rss_types & ETH_RSS_TCP) {
9752                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
9753                                 dev_flow->hash_fields |=
9754                                                 IBV_RX_HASH_SRC_PORT_TCP;
9755                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
9756                                 dev_flow->hash_fields |=
9757                                                 IBV_RX_HASH_DST_PORT_TCP;
9758                         else
9759                                 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
9760                 }
9761         }
9762 }
9763
9764 /**
9765  * Prepare an Rx Hash queue.
9766  *
9767  * @param dev
9768  *   Pointer to Ethernet device.
9769  * @param[in] dev_flow
9770  *   Pointer to the mlx5_flow.
9771  * @param[in] rss_desc
9772  *   Pointer to the mlx5_flow_rss_desc.
9773  * @param[out] hrxq_idx
9774  *   Hash Rx queue index.
9775  *
9776  * @return
9777  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
9778  */
9779 static struct mlx5_hrxq *
9780 flow_dv_hrxq_prepare(struct rte_eth_dev *dev,
9781                      struct mlx5_flow *dev_flow,
9782                      struct mlx5_flow_rss_desc *rss_desc,
9783                      uint32_t *hrxq_idx)
9784 {
9785         struct mlx5_priv *priv = dev->data->dev_private;
9786         struct mlx5_flow_handle *dh = dev_flow->handle;
9787         struct mlx5_hrxq *hrxq;
9788
9789         MLX5_ASSERT(rss_desc->queue_num);
9790         rss_desc->key_len = MLX5_RSS_HASH_KEY_LEN;
9791         rss_desc->hash_fields = dev_flow->hash_fields;
9792         rss_desc->tunnel = !!(dh->layers & MLX5_FLOW_LAYER_TUNNEL);
9793         rss_desc->shared_rss = 0;
9794         *hrxq_idx = mlx5_hrxq_get(dev, rss_desc);
9795         if (!*hrxq_idx)
9796                 return NULL;
9797         hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
9798                               *hrxq_idx);
9799         return hrxq;
9800 }
9801
9802 /**
9803  * Release sample sub action resource.
9804  *
9805  * @param[in, out] dev
9806  *   Pointer to rte_eth_dev structure.
9807  * @param[in] act_res
9808  *   Pointer to sample sub action resource.
9809  */
9810 static void
9811 flow_dv_sample_sub_actions_release(struct rte_eth_dev *dev,
9812                                    struct mlx5_flow_sub_actions_idx *act_res)
9813 {
9814         if (act_res->rix_hrxq) {
9815                 mlx5_hrxq_release(dev, act_res->rix_hrxq);
9816                 act_res->rix_hrxq = 0;
9817         }
9818         if (act_res->rix_encap_decap) {
9819                 flow_dv_encap_decap_resource_release(dev,
9820                                                      act_res->rix_encap_decap);
9821                 act_res->rix_encap_decap = 0;
9822         }
9823         if (act_res->rix_port_id_action) {
9824                 flow_dv_port_id_action_resource_release(dev,
9825                                                 act_res->rix_port_id_action);
9826                 act_res->rix_port_id_action = 0;
9827         }
9828         if (act_res->rix_tag) {
9829                 flow_dv_tag_release(dev, act_res->rix_tag);
9830                 act_res->rix_tag = 0;
9831         }
9832         if (act_res->rix_jump) {
9833                 flow_dv_jump_tbl_resource_release(dev, act_res->rix_jump);
9834                 act_res->rix_jump = 0;
9835         }
9836 }
9837
9838 int
9839 flow_dv_sample_match_cb(struct mlx5_cache_list *list __rte_unused,
9840                         struct mlx5_cache_entry *entry, void *cb_ctx)
9841 {
9842         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9843         struct rte_eth_dev *dev = ctx->dev;
9844         struct mlx5_flow_dv_sample_resource *resource = ctx->data;
9845         struct mlx5_flow_dv_sample_resource *cache_resource =
9846                         container_of(entry, typeof(*cache_resource), entry);
9847
9848         if (resource->ratio == cache_resource->ratio &&
9849             resource->ft_type == cache_resource->ft_type &&
9850             resource->ft_id == cache_resource->ft_id &&
9851             resource->set_action == cache_resource->set_action &&
9852             !memcmp((void *)&resource->sample_act,
9853                     (void *)&cache_resource->sample_act,
9854                     sizeof(struct mlx5_flow_sub_actions_list))) {
9855                 /*
9856                  * Existing sample action should release the prepared
9857                  * sub-actions reference counter.
9858                  */
9859                 flow_dv_sample_sub_actions_release(dev,
9860                                                 &resource->sample_idx);
9861                 return 0;
9862         }
9863         return 1;
9864 }
9865
9866 struct mlx5_cache_entry *
9867 flow_dv_sample_create_cb(struct mlx5_cache_list *list __rte_unused,
9868                          struct mlx5_cache_entry *entry __rte_unused,
9869                          void *cb_ctx)
9870 {
9871         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9872         struct rte_eth_dev *dev = ctx->dev;
9873         struct mlx5_flow_dv_sample_resource *resource = ctx->data;
9874         void **sample_dv_actions = resource->sub_actions;
9875         struct mlx5_flow_dv_sample_resource *cache_resource;
9876         struct mlx5dv_dr_flow_sampler_attr sampler_attr;
9877         struct mlx5_priv *priv = dev->data->dev_private;
9878         struct mlx5_dev_ctx_shared *sh = priv->sh;
9879         struct mlx5_flow_tbl_resource *tbl;
9880         uint32_t idx = 0;
9881         const uint32_t next_ft_step = 1;
9882         uint32_t next_ft_id = resource->ft_id + next_ft_step;
9883         uint8_t is_egress = 0;
9884         uint8_t is_transfer = 0;
9885         struct rte_flow_error *error = ctx->error;
9886
9887         /* Register new sample resource. */
9888         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_SAMPLE], &idx);
9889         if (!cache_resource) {
9890                 rte_flow_error_set(error, ENOMEM,
9891                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9892                                           NULL,
9893                                           "cannot allocate resource memory");
9894                 return NULL;
9895         }
9896         *cache_resource = *resource;
9897         /* Create normal path table level */
9898         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
9899                 is_transfer = 1;
9900         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
9901                 is_egress = 1;
9902         tbl = flow_dv_tbl_resource_get(dev, next_ft_id,
9903                                         is_egress, is_transfer,
9904                                         true, NULL, 0, 0, error);
9905         if (!tbl) {
9906                 rte_flow_error_set(error, ENOMEM,
9907                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9908                                           NULL,
9909                                           "fail to create normal path table "
9910                                           "for sample");
9911                 goto error;
9912         }
9913         cache_resource->normal_path_tbl = tbl;
9914         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB) {
9915                 if (!sh->default_miss_action) {
9916                         rte_flow_error_set(error, ENOMEM,
9917                                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9918                                                 NULL,
9919                                                 "default miss action was not "
9920                                                 "created");
9921                         goto error;
9922                 }
9923                 sample_dv_actions[resource->sample_act.actions_num++] =
9924                                                 sh->default_miss_action;
9925         }
9926         /* Create a DR sample action */
9927         sampler_attr.sample_ratio = cache_resource->ratio;
9928         sampler_attr.default_next_table = tbl->obj;
9929         sampler_attr.num_sample_actions = resource->sample_act.actions_num;
9930         sampler_attr.sample_actions = (struct mlx5dv_dr_action **)
9931                                                         &sample_dv_actions[0];
9932         sampler_attr.action = cache_resource->set_action;
9933         if (mlx5_os_flow_dr_create_flow_action_sampler
9934                         (&sampler_attr, &cache_resource->verbs_action)) {
9935                 rte_flow_error_set(error, ENOMEM,
9936                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9937                                         NULL, "cannot create sample action");
9938                 goto error;
9939         }
9940         cache_resource->idx = idx;
9941         cache_resource->dev = dev;
9942         return &cache_resource->entry;
9943 error:
9944         if (cache_resource->ft_type != MLX5DV_FLOW_TABLE_TYPE_FDB)
9945                 flow_dv_sample_sub_actions_release(dev,
9946                                                    &cache_resource->sample_idx);
9947         if (cache_resource->normal_path_tbl)
9948                 flow_dv_tbl_resource_release(MLX5_SH(dev),
9949                                 cache_resource->normal_path_tbl);
9950         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_SAMPLE], idx);
9951         return NULL;
9952
9953 }
9954
9955 /**
9956  * Find existing sample resource or create and register a new one.
9957  *
9958  * @param[in, out] dev
9959  *   Pointer to rte_eth_dev structure.
9960  * @param[in] resource
9961  *   Pointer to sample resource.
9962  * @parm[in, out] dev_flow
9963  *   Pointer to the dev_flow.
9964  * @param[out] error
9965  *   pointer to error structure.
9966  *
9967  * @return
9968  *   0 on success otherwise -errno and errno is set.
9969  */
9970 static int
9971 flow_dv_sample_resource_register(struct rte_eth_dev *dev,
9972                          struct mlx5_flow_dv_sample_resource *resource,
9973                          struct mlx5_flow *dev_flow,
9974                          struct rte_flow_error *error)
9975 {
9976         struct mlx5_flow_dv_sample_resource *cache_resource;
9977         struct mlx5_cache_entry *entry;
9978         struct mlx5_priv *priv = dev->data->dev_private;
9979         struct mlx5_flow_cb_ctx ctx = {
9980                 .dev = dev,
9981                 .error = error,
9982                 .data = resource,
9983         };
9984
9985         entry = mlx5_cache_register(&priv->sh->sample_action_list, &ctx);
9986         if (!entry)
9987                 return -rte_errno;
9988         cache_resource = container_of(entry, typeof(*cache_resource), entry);
9989         dev_flow->handle->dvh.rix_sample = cache_resource->idx;
9990         dev_flow->dv.sample_res = cache_resource;
9991         return 0;
9992 }
9993
9994 int
9995 flow_dv_dest_array_match_cb(struct mlx5_cache_list *list __rte_unused,
9996                             struct mlx5_cache_entry *entry, void *cb_ctx)
9997 {
9998         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9999         struct mlx5_flow_dv_dest_array_resource *resource = ctx->data;
10000         struct rte_eth_dev *dev = ctx->dev;
10001         struct mlx5_flow_dv_dest_array_resource *cache_resource =
10002                         container_of(entry, typeof(*cache_resource), entry);
10003         uint32_t idx = 0;
10004
10005         if (resource->num_of_dest == cache_resource->num_of_dest &&
10006             resource->ft_type == cache_resource->ft_type &&
10007             !memcmp((void *)cache_resource->sample_act,
10008                     (void *)resource->sample_act,
10009                    (resource->num_of_dest *
10010                    sizeof(struct mlx5_flow_sub_actions_list)))) {
10011                 /*
10012                  * Existing sample action should release the prepared
10013                  * sub-actions reference counter.
10014                  */
10015                 for (idx = 0; idx < resource->num_of_dest; idx++)
10016                         flow_dv_sample_sub_actions_release(dev,
10017                                         &resource->sample_idx[idx]);
10018                 return 0;
10019         }
10020         return 1;
10021 }
10022
10023 struct mlx5_cache_entry *
10024 flow_dv_dest_array_create_cb(struct mlx5_cache_list *list __rte_unused,
10025                          struct mlx5_cache_entry *entry __rte_unused,
10026                          void *cb_ctx)
10027 {
10028         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10029         struct rte_eth_dev *dev = ctx->dev;
10030         struct mlx5_flow_dv_dest_array_resource *cache_resource;
10031         struct mlx5_flow_dv_dest_array_resource *resource = ctx->data;
10032         struct mlx5dv_dr_action_dest_attr *dest_attr[MLX5_MAX_DEST_NUM] = { 0 };
10033         struct mlx5dv_dr_action_dest_reformat dest_reformat[MLX5_MAX_DEST_NUM];
10034         struct mlx5_priv *priv = dev->data->dev_private;
10035         struct mlx5_dev_ctx_shared *sh = priv->sh;
10036         struct mlx5_flow_sub_actions_list *sample_act;
10037         struct mlx5dv_dr_domain *domain;
10038         uint32_t idx = 0, res_idx = 0;
10039         struct rte_flow_error *error = ctx->error;
10040         uint64_t action_flags;
10041         int ret;
10042
10043         /* Register new destination array resource. */
10044         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
10045                                             &res_idx);
10046         if (!cache_resource) {
10047                 rte_flow_error_set(error, ENOMEM,
10048                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10049                                           NULL,
10050                                           "cannot allocate resource memory");
10051                 return NULL;
10052         }
10053         *cache_resource = *resource;
10054         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
10055                 domain = sh->fdb_domain;
10056         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
10057                 domain = sh->rx_domain;
10058         else
10059                 domain = sh->tx_domain;
10060         for (idx = 0; idx < resource->num_of_dest; idx++) {
10061                 dest_attr[idx] = (struct mlx5dv_dr_action_dest_attr *)
10062                                  mlx5_malloc(MLX5_MEM_ZERO,
10063                                  sizeof(struct mlx5dv_dr_action_dest_attr),
10064                                  0, SOCKET_ID_ANY);
10065                 if (!dest_attr[idx]) {
10066                         rte_flow_error_set(error, ENOMEM,
10067                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10068                                            NULL,
10069                                            "cannot allocate resource memory");
10070                         goto error;
10071                 }
10072                 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST;
10073                 sample_act = &resource->sample_act[idx];
10074                 action_flags = sample_act->action_flags;
10075                 switch (action_flags) {
10076                 case MLX5_FLOW_ACTION_QUEUE:
10077                         dest_attr[idx]->dest = sample_act->dr_queue_action;
10078                         break;
10079                 case (MLX5_FLOW_ACTION_PORT_ID | MLX5_FLOW_ACTION_ENCAP):
10080                         dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST_REFORMAT;
10081                         dest_attr[idx]->dest_reformat = &dest_reformat[idx];
10082                         dest_attr[idx]->dest_reformat->reformat =
10083                                         sample_act->dr_encap_action;
10084                         dest_attr[idx]->dest_reformat->dest =
10085                                         sample_act->dr_port_id_action;
10086                         break;
10087                 case MLX5_FLOW_ACTION_PORT_ID:
10088                         dest_attr[idx]->dest = sample_act->dr_port_id_action;
10089                         break;
10090                 case MLX5_FLOW_ACTION_JUMP:
10091                         dest_attr[idx]->dest = sample_act->dr_jump_action;
10092                         break;
10093                 default:
10094                         rte_flow_error_set(error, EINVAL,
10095                                            RTE_FLOW_ERROR_TYPE_ACTION,
10096                                            NULL,
10097                                            "unsupported actions type");
10098                         goto error;
10099                 }
10100         }
10101         /* create a dest array actioin */
10102         ret = mlx5_os_flow_dr_create_flow_action_dest_array
10103                                                 (domain,
10104                                                  cache_resource->num_of_dest,
10105                                                  dest_attr,
10106                                                  &cache_resource->action);
10107         if (ret) {
10108                 rte_flow_error_set(error, ENOMEM,
10109                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10110                                    NULL,
10111                                    "cannot create destination array action");
10112                 goto error;
10113         }
10114         cache_resource->idx = res_idx;
10115         cache_resource->dev = dev;
10116         for (idx = 0; idx < resource->num_of_dest; idx++)
10117                 mlx5_free(dest_attr[idx]);
10118         return &cache_resource->entry;
10119 error:
10120         for (idx = 0; idx < resource->num_of_dest; idx++) {
10121                 struct mlx5_flow_sub_actions_idx *act_res =
10122                                         &cache_resource->sample_idx[idx];
10123                 if (act_res->rix_hrxq &&
10124                     !mlx5_hrxq_release(dev,
10125                                 act_res->rix_hrxq))
10126                         act_res->rix_hrxq = 0;
10127                 if (act_res->rix_encap_decap &&
10128                         !flow_dv_encap_decap_resource_release(dev,
10129                                 act_res->rix_encap_decap))
10130                         act_res->rix_encap_decap = 0;
10131                 if (act_res->rix_port_id_action &&
10132                         !flow_dv_port_id_action_resource_release(dev,
10133                                 act_res->rix_port_id_action))
10134                         act_res->rix_port_id_action = 0;
10135                 if (act_res->rix_jump &&
10136                         !flow_dv_jump_tbl_resource_release(dev,
10137                                 act_res->rix_jump))
10138                         act_res->rix_jump = 0;
10139                 if (dest_attr[idx])
10140                         mlx5_free(dest_attr[idx]);
10141         }
10142
10143         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DEST_ARRAY], res_idx);
10144         return NULL;
10145 }
10146
10147 /**
10148  * Find existing destination array resource or create and register a new one.
10149  *
10150  * @param[in, out] dev
10151  *   Pointer to rte_eth_dev structure.
10152  * @param[in] resource
10153  *   Pointer to destination array resource.
10154  * @parm[in, out] dev_flow
10155  *   Pointer to the dev_flow.
10156  * @param[out] error
10157  *   pointer to error structure.
10158  *
10159  * @return
10160  *   0 on success otherwise -errno and errno is set.
10161  */
10162 static int
10163 flow_dv_dest_array_resource_register(struct rte_eth_dev *dev,
10164                          struct mlx5_flow_dv_dest_array_resource *resource,
10165                          struct mlx5_flow *dev_flow,
10166                          struct rte_flow_error *error)
10167 {
10168         struct mlx5_flow_dv_dest_array_resource *cache_resource;
10169         struct mlx5_priv *priv = dev->data->dev_private;
10170         struct mlx5_cache_entry *entry;
10171         struct mlx5_flow_cb_ctx ctx = {
10172                 .dev = dev,
10173                 .error = error,
10174                 .data = resource,
10175         };
10176
10177         entry = mlx5_cache_register(&priv->sh->dest_array_list, &ctx);
10178         if (!entry)
10179                 return -rte_errno;
10180         cache_resource = container_of(entry, typeof(*cache_resource), entry);
10181         dev_flow->handle->dvh.rix_dest_array = cache_resource->idx;
10182         dev_flow->dv.dest_array_res = cache_resource;
10183         return 0;
10184 }
10185
10186 /**
10187  * Convert Sample action to DV specification.
10188  *
10189  * @param[in] dev
10190  *   Pointer to rte_eth_dev structure.
10191  * @param[in] action
10192  *   Pointer to sample action structure.
10193  * @param[in, out] dev_flow
10194  *   Pointer to the mlx5_flow.
10195  * @param[in] attr
10196  *   Pointer to the flow attributes.
10197  * @param[in, out] num_of_dest
10198  *   Pointer to the num of destination.
10199  * @param[in, out] sample_actions
10200  *   Pointer to sample actions list.
10201  * @param[in, out] res
10202  *   Pointer to sample resource.
10203  * @param[out] error
10204  *   Pointer to the error structure.
10205  *
10206  * @return
10207  *   0 on success, a negative errno value otherwise and rte_errno is set.
10208  */
10209 static int
10210 flow_dv_translate_action_sample(struct rte_eth_dev *dev,
10211                                 const struct rte_flow_action_sample *action,
10212                                 struct mlx5_flow *dev_flow,
10213                                 const struct rte_flow_attr *attr,
10214                                 uint32_t *num_of_dest,
10215                                 void **sample_actions,
10216                                 struct mlx5_flow_dv_sample_resource *res,
10217                                 struct rte_flow_error *error)
10218 {
10219         struct mlx5_priv *priv = dev->data->dev_private;
10220         const struct rte_flow_action *sub_actions;
10221         struct mlx5_flow_sub_actions_list *sample_act;
10222         struct mlx5_flow_sub_actions_idx *sample_idx;
10223         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
10224         struct rte_flow *flow = dev_flow->flow;
10225         struct mlx5_flow_rss_desc *rss_desc;
10226         uint64_t action_flags = 0;
10227
10228         MLX5_ASSERT(wks);
10229         rss_desc = &wks->rss_desc;
10230         sample_act = &res->sample_act;
10231         sample_idx = &res->sample_idx;
10232         res->ratio = action->ratio;
10233         sub_actions = action->actions;
10234         for (; sub_actions->type != RTE_FLOW_ACTION_TYPE_END; sub_actions++) {
10235                 int type = sub_actions->type;
10236                 uint32_t pre_rix = 0;
10237                 void *pre_r;
10238                 switch (type) {
10239                 case RTE_FLOW_ACTION_TYPE_QUEUE:
10240                 {
10241                         const struct rte_flow_action_queue *queue;
10242                         struct mlx5_hrxq *hrxq;
10243                         uint32_t hrxq_idx;
10244
10245                         queue = sub_actions->conf;
10246                         rss_desc->queue_num = 1;
10247                         rss_desc->queue[0] = queue->index;
10248                         hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
10249                                                     rss_desc, &hrxq_idx);
10250                         if (!hrxq)
10251                                 return rte_flow_error_set
10252                                         (error, rte_errno,
10253                                          RTE_FLOW_ERROR_TYPE_ACTION,
10254                                          NULL,
10255                                          "cannot create fate queue");
10256                         sample_act->dr_queue_action = hrxq->action;
10257                         sample_idx->rix_hrxq = hrxq_idx;
10258                         sample_actions[sample_act->actions_num++] =
10259                                                 hrxq->action;
10260                         (*num_of_dest)++;
10261                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
10262                         if (action_flags & MLX5_FLOW_ACTION_MARK)
10263                                 dev_flow->handle->rix_hrxq = hrxq_idx;
10264                         dev_flow->handle->fate_action =
10265                                         MLX5_FLOW_FATE_QUEUE;
10266                         break;
10267                 }
10268                 case RTE_FLOW_ACTION_TYPE_RSS:
10269                 {
10270                         struct mlx5_hrxq *hrxq;
10271                         uint32_t hrxq_idx;
10272                         const struct rte_flow_action_rss *rss;
10273                         const uint8_t *rss_key;
10274
10275                         rss = sub_actions->conf;
10276                         memcpy(rss_desc->queue, rss->queue,
10277                                rss->queue_num * sizeof(uint16_t));
10278                         rss_desc->queue_num = rss->queue_num;
10279                         /* NULL RSS key indicates default RSS key. */
10280                         rss_key = !rss->key ? rss_hash_default_key : rss->key;
10281                         memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
10282                         /*
10283                          * rss->level and rss.types should be set in advance
10284                          * when expanding items for RSS.
10285                          */
10286                         flow_dv_hashfields_set(dev_flow, rss_desc);
10287                         hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
10288                                                     rss_desc, &hrxq_idx);
10289                         if (!hrxq)
10290                                 return rte_flow_error_set
10291                                         (error, rte_errno,
10292                                          RTE_FLOW_ERROR_TYPE_ACTION,
10293                                          NULL,
10294                                          "cannot create fate queue");
10295                         sample_act->dr_queue_action = hrxq->action;
10296                         sample_idx->rix_hrxq = hrxq_idx;
10297                         sample_actions[sample_act->actions_num++] =
10298                                                 hrxq->action;
10299                         (*num_of_dest)++;
10300                         action_flags |= MLX5_FLOW_ACTION_RSS;
10301                         if (action_flags & MLX5_FLOW_ACTION_MARK)
10302                                 dev_flow->handle->rix_hrxq = hrxq_idx;
10303                         dev_flow->handle->fate_action =
10304                                         MLX5_FLOW_FATE_QUEUE;
10305                         break;
10306                 }
10307                 case RTE_FLOW_ACTION_TYPE_MARK:
10308                 {
10309                         uint32_t tag_be = mlx5_flow_mark_set
10310                                 (((const struct rte_flow_action_mark *)
10311                                 (sub_actions->conf))->id);
10312
10313                         dev_flow->handle->mark = 1;
10314                         pre_rix = dev_flow->handle->dvh.rix_tag;
10315                         /* Save the mark resource before sample */
10316                         pre_r = dev_flow->dv.tag_resource;
10317                         if (flow_dv_tag_resource_register(dev, tag_be,
10318                                                   dev_flow, error))
10319                                 return -rte_errno;
10320                         MLX5_ASSERT(dev_flow->dv.tag_resource);
10321                         sample_act->dr_tag_action =
10322                                 dev_flow->dv.tag_resource->action;
10323                         sample_idx->rix_tag =
10324                                 dev_flow->handle->dvh.rix_tag;
10325                         sample_actions[sample_act->actions_num++] =
10326                                                 sample_act->dr_tag_action;
10327                         /* Recover the mark resource after sample */
10328                         dev_flow->dv.tag_resource = pre_r;
10329                         dev_flow->handle->dvh.rix_tag = pre_rix;
10330                         action_flags |= MLX5_FLOW_ACTION_MARK;
10331                         break;
10332                 }
10333                 case RTE_FLOW_ACTION_TYPE_COUNT:
10334                 {
10335                         if (!flow->counter) {
10336                                 flow->counter =
10337                                         flow_dv_translate_create_counter(dev,
10338                                                 dev_flow, sub_actions->conf,
10339                                                 0);
10340                                 if (!flow->counter)
10341                                         return rte_flow_error_set
10342                                                 (error, rte_errno,
10343                                                 RTE_FLOW_ERROR_TYPE_ACTION,
10344                                                 NULL,
10345                                                 "cannot create counter"
10346                                                 " object.");
10347                         }
10348                         sample_act->dr_cnt_action =
10349                                   (flow_dv_counter_get_by_idx(dev,
10350                                   flow->counter, NULL))->action;
10351                         sample_actions[sample_act->actions_num++] =
10352                                                 sample_act->dr_cnt_action;
10353                         action_flags |= MLX5_FLOW_ACTION_COUNT;
10354                         break;
10355                 }
10356                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
10357                 {
10358                         struct mlx5_flow_dv_port_id_action_resource
10359                                         port_id_resource;
10360                         uint32_t port_id = 0;
10361
10362                         memset(&port_id_resource, 0, sizeof(port_id_resource));
10363                         /* Save the port id resource before sample */
10364                         pre_rix = dev_flow->handle->rix_port_id_action;
10365                         pre_r = dev_flow->dv.port_id_action;
10366                         if (flow_dv_translate_action_port_id(dev, sub_actions,
10367                                                              &port_id, error))
10368                                 return -rte_errno;
10369                         port_id_resource.port_id = port_id;
10370                         if (flow_dv_port_id_action_resource_register
10371                             (dev, &port_id_resource, dev_flow, error))
10372                                 return -rte_errno;
10373                         sample_act->dr_port_id_action =
10374                                 dev_flow->dv.port_id_action->action;
10375                         sample_idx->rix_port_id_action =
10376                                 dev_flow->handle->rix_port_id_action;
10377                         sample_actions[sample_act->actions_num++] =
10378                                                 sample_act->dr_port_id_action;
10379                         /* Recover the port id resource after sample */
10380                         dev_flow->dv.port_id_action = pre_r;
10381                         dev_flow->handle->rix_port_id_action = pre_rix;
10382                         (*num_of_dest)++;
10383                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
10384                         break;
10385                 }
10386                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
10387                         /* Save the encap resource before sample */
10388                         pre_rix = dev_flow->handle->dvh.rix_encap_decap;
10389                         pre_r = dev_flow->dv.encap_decap;
10390                         if (flow_dv_create_action_l2_encap(dev, sub_actions,
10391                                                            dev_flow,
10392                                                            attr->transfer,
10393                                                            error))
10394                                 return -rte_errno;
10395                         sample_act->dr_encap_action =
10396                                 dev_flow->dv.encap_decap->action;
10397                         sample_idx->rix_encap_decap =
10398                                 dev_flow->handle->dvh.rix_encap_decap;
10399                         sample_actions[sample_act->actions_num++] =
10400                                                 sample_act->dr_encap_action;
10401                         /* Recover the encap resource after sample */
10402                         dev_flow->dv.encap_decap = pre_r;
10403                         dev_flow->handle->dvh.rix_encap_decap = pre_rix;
10404                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
10405                         break;
10406                 default:
10407                         return rte_flow_error_set(error, EINVAL,
10408                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10409                                 NULL,
10410                                 "Not support for sampler action");
10411                 }
10412         }
10413         sample_act->action_flags = action_flags;
10414         res->ft_id = dev_flow->dv.group;
10415         if (attr->transfer) {
10416                 union {
10417                         uint32_t action_in[MLX5_ST_SZ_DW(set_action_in)];
10418                         uint64_t set_action;
10419                 } action_ctx = { .set_action = 0 };
10420
10421                 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
10422                 MLX5_SET(set_action_in, action_ctx.action_in, action_type,
10423                          MLX5_MODIFICATION_TYPE_SET);
10424                 MLX5_SET(set_action_in, action_ctx.action_in, field,
10425                          MLX5_MODI_META_REG_C_0);
10426                 MLX5_SET(set_action_in, action_ctx.action_in, data,
10427                          priv->vport_meta_tag);
10428                 res->set_action = action_ctx.set_action;
10429         } else if (attr->ingress) {
10430                 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
10431         } else {
10432                 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_TX;
10433         }
10434         return 0;
10435 }
10436
10437 /**
10438  * Convert Sample action to DV specification.
10439  *
10440  * @param[in] dev
10441  *   Pointer to rte_eth_dev structure.
10442  * @param[in, out] dev_flow
10443  *   Pointer to the mlx5_flow.
10444  * @param[in] num_of_dest
10445  *   The num of destination.
10446  * @param[in, out] res
10447  *   Pointer to sample resource.
10448  * @param[in, out] mdest_res
10449  *   Pointer to destination array resource.
10450  * @param[in] sample_actions
10451  *   Pointer to sample path actions list.
10452  * @param[in] action_flags
10453  *   Holds the actions detected until now.
10454  * @param[out] error
10455  *   Pointer to the error structure.
10456  *
10457  * @return
10458  *   0 on success, a negative errno value otherwise and rte_errno is set.
10459  */
10460 static int
10461 flow_dv_create_action_sample(struct rte_eth_dev *dev,
10462                              struct mlx5_flow *dev_flow,
10463                              uint32_t num_of_dest,
10464                              struct mlx5_flow_dv_sample_resource *res,
10465                              struct mlx5_flow_dv_dest_array_resource *mdest_res,
10466                              void **sample_actions,
10467                              uint64_t action_flags,
10468                              struct rte_flow_error *error)
10469 {
10470         /* update normal path action resource into last index of array */
10471         uint32_t dest_index = MLX5_MAX_DEST_NUM - 1;
10472         struct mlx5_flow_sub_actions_list *sample_act =
10473                                         &mdest_res->sample_act[dest_index];
10474         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
10475         struct mlx5_flow_rss_desc *rss_desc;
10476         uint32_t normal_idx = 0;
10477         struct mlx5_hrxq *hrxq;
10478         uint32_t hrxq_idx;
10479
10480         MLX5_ASSERT(wks);
10481         rss_desc = &wks->rss_desc;
10482         if (num_of_dest > 1) {
10483                 if (sample_act->action_flags & MLX5_FLOW_ACTION_QUEUE) {
10484                         /* Handle QP action for mirroring */
10485                         hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
10486                                                     rss_desc, &hrxq_idx);
10487                         if (!hrxq)
10488                                 return rte_flow_error_set
10489                                      (error, rte_errno,
10490                                       RTE_FLOW_ERROR_TYPE_ACTION,
10491                                       NULL,
10492                                       "cannot create rx queue");
10493                         normal_idx++;
10494                         mdest_res->sample_idx[dest_index].rix_hrxq = hrxq_idx;
10495                         sample_act->dr_queue_action = hrxq->action;
10496                         if (action_flags & MLX5_FLOW_ACTION_MARK)
10497                                 dev_flow->handle->rix_hrxq = hrxq_idx;
10498                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
10499                 }
10500                 if (sample_act->action_flags & MLX5_FLOW_ACTION_ENCAP) {
10501                         normal_idx++;
10502                         mdest_res->sample_idx[dest_index].rix_encap_decap =
10503                                 dev_flow->handle->dvh.rix_encap_decap;
10504                         sample_act->dr_encap_action =
10505                                 dev_flow->dv.encap_decap->action;
10506                 }
10507                 if (sample_act->action_flags & MLX5_FLOW_ACTION_PORT_ID) {
10508                         normal_idx++;
10509                         mdest_res->sample_idx[dest_index].rix_port_id_action =
10510                                 dev_flow->handle->rix_port_id_action;
10511                         sample_act->dr_port_id_action =
10512                                 dev_flow->dv.port_id_action->action;
10513                 }
10514                 if (sample_act->action_flags & MLX5_FLOW_ACTION_JUMP) {
10515                         normal_idx++;
10516                         mdest_res->sample_idx[dest_index].rix_jump =
10517                                 dev_flow->handle->rix_jump;
10518                         sample_act->dr_jump_action =
10519                                 dev_flow->dv.jump->action;
10520                         dev_flow->handle->rix_jump = 0;
10521                 }
10522                 sample_act->actions_num = normal_idx;
10523                 /* update sample action resource into first index of array */
10524                 mdest_res->ft_type = res->ft_type;
10525                 memcpy(&mdest_res->sample_idx[0], &res->sample_idx,
10526                                 sizeof(struct mlx5_flow_sub_actions_idx));
10527                 memcpy(&mdest_res->sample_act[0], &res->sample_act,
10528                                 sizeof(struct mlx5_flow_sub_actions_list));
10529                 mdest_res->num_of_dest = num_of_dest;
10530                 if (flow_dv_dest_array_resource_register(dev, mdest_res,
10531                                                          dev_flow, error))
10532                         return rte_flow_error_set(error, EINVAL,
10533                                                   RTE_FLOW_ERROR_TYPE_ACTION,
10534                                                   NULL, "can't create sample "
10535                                                   "action");
10536         } else {
10537                 res->sub_actions = sample_actions;
10538                 if (flow_dv_sample_resource_register(dev, res, dev_flow, error))
10539                         return rte_flow_error_set(error, EINVAL,
10540                                                   RTE_FLOW_ERROR_TYPE_ACTION,
10541                                                   NULL,
10542                                                   "can't create sample action");
10543         }
10544         return 0;
10545 }
10546
10547 /**
10548  * Remove an ASO age action from age actions list.
10549  *
10550  * @param[in] dev
10551  *   Pointer to the Ethernet device structure.
10552  * @param[in] age
10553  *   Pointer to the aso age action handler.
10554  */
10555 static void
10556 flow_dv_aso_age_remove_from_age(struct rte_eth_dev *dev,
10557                                 struct mlx5_aso_age_action *age)
10558 {
10559         struct mlx5_age_info *age_info;
10560         struct mlx5_age_param *age_param = &age->age_params;
10561         struct mlx5_priv *priv = dev->data->dev_private;
10562         uint16_t expected = AGE_CANDIDATE;
10563
10564         age_info = GET_PORT_AGE_INFO(priv);
10565         if (!__atomic_compare_exchange_n(&age_param->state, &expected,
10566                                          AGE_FREE, false, __ATOMIC_RELAXED,
10567                                          __ATOMIC_RELAXED)) {
10568                 /**
10569                  * We need the lock even it is age timeout,
10570                  * since age action may still in process.
10571                  */
10572                 rte_spinlock_lock(&age_info->aged_sl);
10573                 LIST_REMOVE(age, next);
10574                 rte_spinlock_unlock(&age_info->aged_sl);
10575                 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
10576         }
10577 }
10578
10579 /**
10580  * Release an ASO age action.
10581  *
10582  * @param[in] dev
10583  *   Pointer to the Ethernet device structure.
10584  * @param[in] age_idx
10585  *   Index of ASO age action to release.
10586  * @param[in] flow
10587  *   True if the release operation is during flow destroy operation.
10588  *   False if the release operation is during action destroy operation.
10589  *
10590  * @return
10591  *   0 when age action was removed, otherwise the number of references.
10592  */
10593 static int
10594 flow_dv_aso_age_release(struct rte_eth_dev *dev, uint32_t age_idx)
10595 {
10596         struct mlx5_priv *priv = dev->data->dev_private;
10597         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
10598         struct mlx5_aso_age_action *age = flow_aso_age_get_by_idx(dev, age_idx);
10599         uint32_t ret = __atomic_sub_fetch(&age->refcnt, 1, __ATOMIC_RELAXED);
10600
10601         if (!ret) {
10602                 flow_dv_aso_age_remove_from_age(dev, age);
10603                 rte_spinlock_lock(&mng->free_sl);
10604                 LIST_INSERT_HEAD(&mng->free, age, next);
10605                 rte_spinlock_unlock(&mng->free_sl);
10606         }
10607         return ret;
10608 }
10609
10610 /**
10611  * Resize the ASO age pools array by MLX5_CNT_CONTAINER_RESIZE pools.
10612  *
10613  * @param[in] dev
10614  *   Pointer to the Ethernet device structure.
10615  *
10616  * @return
10617  *   0 on success, otherwise negative errno value and rte_errno is set.
10618  */
10619 static int
10620 flow_dv_aso_age_pools_resize(struct rte_eth_dev *dev)
10621 {
10622         struct mlx5_priv *priv = dev->data->dev_private;
10623         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
10624         void *old_pools = mng->pools;
10625         uint32_t resize = mng->n + MLX5_CNT_CONTAINER_RESIZE;
10626         uint32_t mem_size = sizeof(struct mlx5_aso_age_pool *) * resize;
10627         void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
10628
10629         if (!pools) {
10630                 rte_errno = ENOMEM;
10631                 return -ENOMEM;
10632         }
10633         if (old_pools) {
10634                 memcpy(pools, old_pools,
10635                        mng->n * sizeof(struct mlx5_flow_counter_pool *));
10636                 mlx5_free(old_pools);
10637         } else {
10638                 /* First ASO flow hit allocation - starting ASO data-path. */
10639                 int ret = mlx5_aso_queue_start(priv->sh);
10640
10641                 if (ret) {
10642                         mlx5_free(pools);
10643                         return ret;
10644                 }
10645         }
10646         mng->n = resize;
10647         mng->pools = pools;
10648         return 0;
10649 }
10650
10651 /**
10652  * Create and initialize a new ASO aging pool.
10653  *
10654  * @param[in] dev
10655  *   Pointer to the Ethernet device structure.
10656  * @param[out] age_free
10657  *   Where to put the pointer of a new age action.
10658  *
10659  * @return
10660  *   The age actions pool pointer and @p age_free is set on success,
10661  *   NULL otherwise and rte_errno is set.
10662  */
10663 static struct mlx5_aso_age_pool *
10664 flow_dv_age_pool_create(struct rte_eth_dev *dev,
10665                         struct mlx5_aso_age_action **age_free)
10666 {
10667         struct mlx5_priv *priv = dev->data->dev_private;
10668         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
10669         struct mlx5_aso_age_pool *pool = NULL;
10670         struct mlx5_devx_obj *obj = NULL;
10671         uint32_t i;
10672
10673         obj = mlx5_devx_cmd_create_flow_hit_aso_obj(priv->sh->ctx,
10674                                                     priv->sh->pdn);
10675         if (!obj) {
10676                 rte_errno = ENODATA;
10677                 DRV_LOG(ERR, "Failed to create flow_hit_aso_obj using DevX.");
10678                 return NULL;
10679         }
10680         pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
10681         if (!pool) {
10682                 claim_zero(mlx5_devx_cmd_destroy(obj));
10683                 rte_errno = ENOMEM;
10684                 return NULL;
10685         }
10686         pool->flow_hit_aso_obj = obj;
10687         pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
10688         rte_spinlock_lock(&mng->resize_sl);
10689         pool->index = mng->next;
10690         /* Resize pools array if there is no room for the new pool in it. */
10691         if (pool->index == mng->n && flow_dv_aso_age_pools_resize(dev)) {
10692                 claim_zero(mlx5_devx_cmd_destroy(obj));
10693                 mlx5_free(pool);
10694                 rte_spinlock_unlock(&mng->resize_sl);
10695                 return NULL;
10696         }
10697         mng->pools[pool->index] = pool;
10698         mng->next++;
10699         rte_spinlock_unlock(&mng->resize_sl);
10700         /* Assign the first action in the new pool, the rest go to free list. */
10701         *age_free = &pool->actions[0];
10702         for (i = 1; i < MLX5_ASO_AGE_ACTIONS_PER_POOL; i++) {
10703                 pool->actions[i].offset = i;
10704                 LIST_INSERT_HEAD(&mng->free, &pool->actions[i], next);
10705         }
10706         return pool;
10707 }
10708
10709 /**
10710  * Allocate a ASO aging bit.
10711  *
10712  * @param[in] dev
10713  *   Pointer to the Ethernet device structure.
10714  * @param[out] error
10715  *   Pointer to the error structure.
10716  *
10717  * @return
10718  *   Index to ASO age action on success, 0 otherwise and rte_errno is set.
10719  */
10720 static uint32_t
10721 flow_dv_aso_age_alloc(struct rte_eth_dev *dev, struct rte_flow_error *error)
10722 {
10723         struct mlx5_priv *priv = dev->data->dev_private;
10724         const struct mlx5_aso_age_pool *pool;
10725         struct mlx5_aso_age_action *age_free = NULL;
10726         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
10727
10728         MLX5_ASSERT(mng);
10729         /* Try to get the next free age action bit. */
10730         rte_spinlock_lock(&mng->free_sl);
10731         age_free = LIST_FIRST(&mng->free);
10732         if (age_free) {
10733                 LIST_REMOVE(age_free, next);
10734         } else if (!flow_dv_age_pool_create(dev, &age_free)) {
10735                 rte_spinlock_unlock(&mng->free_sl);
10736                 rte_flow_error_set(error, rte_errno, RTE_FLOW_ERROR_TYPE_ACTION,
10737                                    NULL, "failed to create ASO age pool");
10738                 return 0; /* 0 is an error. */
10739         }
10740         rte_spinlock_unlock(&mng->free_sl);
10741         pool = container_of
10742           ((const struct mlx5_aso_age_action (*)[MLX5_ASO_AGE_ACTIONS_PER_POOL])
10743                   (age_free - age_free->offset), const struct mlx5_aso_age_pool,
10744                                                                        actions);
10745         if (!age_free->dr_action) {
10746                 int reg_c = mlx5_flow_get_reg_id(dev, MLX5_ASO_FLOW_HIT, 0,
10747                                                  error);
10748
10749                 if (reg_c < 0) {
10750                         rte_flow_error_set(error, rte_errno,
10751                                            RTE_FLOW_ERROR_TYPE_ACTION,
10752                                            NULL, "failed to get reg_c "
10753                                            "for ASO flow hit");
10754                         return 0; /* 0 is an error. */
10755                 }
10756 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
10757                 age_free->dr_action = mlx5_glue->dv_create_flow_action_aso
10758                                 (priv->sh->rx_domain,
10759                                  pool->flow_hit_aso_obj->obj, age_free->offset,
10760                                  MLX5DV_DR_ACTION_FLAGS_ASO_FIRST_HIT_SET,
10761                                  (reg_c - REG_C_0));
10762 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
10763                 if (!age_free->dr_action) {
10764                         rte_errno = errno;
10765                         rte_spinlock_lock(&mng->free_sl);
10766                         LIST_INSERT_HEAD(&mng->free, age_free, next);
10767                         rte_spinlock_unlock(&mng->free_sl);
10768                         rte_flow_error_set(error, rte_errno,
10769                                            RTE_FLOW_ERROR_TYPE_ACTION,
10770                                            NULL, "failed to create ASO "
10771                                            "flow hit action");
10772                         return 0; /* 0 is an error. */
10773                 }
10774         }
10775         __atomic_store_n(&age_free->refcnt, 1, __ATOMIC_RELAXED);
10776         return pool->index | ((age_free->offset + 1) << 16);
10777 }
10778
10779 /**
10780  * Create a age action using ASO mechanism.
10781  *
10782  * @param[in] dev
10783  *   Pointer to rte_eth_dev structure.
10784  * @param[in] age
10785  *   Pointer to the aging action configuration.
10786  * @param[out] error
10787  *   Pointer to the error structure.
10788  *
10789  * @return
10790  *   Index to flow counter on success, 0 otherwise.
10791  */
10792 static uint32_t
10793 flow_dv_translate_create_aso_age(struct rte_eth_dev *dev,
10794                                  const struct rte_flow_action_age *age,
10795                                  struct rte_flow_error *error)
10796 {
10797         uint32_t age_idx = 0;
10798         struct mlx5_aso_age_action *aso_age;
10799
10800         age_idx = flow_dv_aso_age_alloc(dev, error);
10801         if (!age_idx)
10802                 return 0;
10803         aso_age = flow_aso_age_get_by_idx(dev, age_idx);
10804         aso_age->age_params.context = age->context;
10805         aso_age->age_params.timeout = age->timeout;
10806         aso_age->age_params.port_id = dev->data->port_id;
10807         __atomic_store_n(&aso_age->age_params.sec_since_last_hit, 0,
10808                          __ATOMIC_RELAXED);
10809         __atomic_store_n(&aso_age->age_params.state, AGE_CANDIDATE,
10810                          __ATOMIC_RELAXED);
10811         return age_idx;
10812 }
10813
10814 /**
10815  * Fill the flow with DV spec, lock free
10816  * (mutex should be acquired by caller).
10817  *
10818  * @param[in] dev
10819  *   Pointer to rte_eth_dev structure.
10820  * @param[in, out] dev_flow
10821  *   Pointer to the sub flow.
10822  * @param[in] attr
10823  *   Pointer to the flow attributes.
10824  * @param[in] items
10825  *   Pointer to the list of items.
10826  * @param[in] actions
10827  *   Pointer to the list of actions.
10828  * @param[out] error
10829  *   Pointer to the error structure.
10830  *
10831  * @return
10832  *   0 on success, a negative errno value otherwise and rte_errno is set.
10833  */
10834 static int
10835 flow_dv_translate(struct rte_eth_dev *dev,
10836                   struct mlx5_flow *dev_flow,
10837                   const struct rte_flow_attr *attr,
10838                   const struct rte_flow_item items[],
10839                   const struct rte_flow_action actions[],
10840                   struct rte_flow_error *error)
10841 {
10842         struct mlx5_priv *priv = dev->data->dev_private;
10843         struct mlx5_dev_config *dev_conf = &priv->config;
10844         struct rte_flow *flow = dev_flow->flow;
10845         struct mlx5_flow_handle *handle = dev_flow->handle;
10846         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
10847         struct mlx5_flow_rss_desc *rss_desc;
10848         uint64_t item_flags = 0;
10849         uint64_t last_item = 0;
10850         uint64_t action_flags = 0;
10851         struct mlx5_flow_dv_matcher matcher = {
10852                 .mask = {
10853                         .size = sizeof(matcher.mask.buf) -
10854                                 MLX5_ST_SZ_BYTES(fte_match_set_misc4),
10855                 },
10856         };
10857         int actions_n = 0;
10858         bool actions_end = false;
10859         union {
10860                 struct mlx5_flow_dv_modify_hdr_resource res;
10861                 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
10862                             sizeof(struct mlx5_modification_cmd) *
10863                             (MLX5_MAX_MODIFY_NUM + 1)];
10864         } mhdr_dummy;
10865         struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
10866         const struct rte_flow_action_count *count = NULL;
10867         const struct rte_flow_action_age *age = NULL;
10868         union flow_dv_attr flow_attr = { .attr = 0 };
10869         uint32_t tag_be;
10870         union mlx5_flow_tbl_key tbl_key;
10871         uint32_t modify_action_position = UINT32_MAX;
10872         void *match_mask = matcher.mask.buf;
10873         void *match_value = dev_flow->dv.value.buf;
10874         uint8_t next_protocol = 0xff;
10875         struct rte_vlan_hdr vlan = { 0 };
10876         struct mlx5_flow_dv_dest_array_resource mdest_res;
10877         struct mlx5_flow_dv_sample_resource sample_res;
10878         void *sample_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
10879         const struct rte_flow_action_sample *sample = NULL;
10880         struct mlx5_flow_sub_actions_list *sample_act;
10881         uint32_t sample_act_pos = UINT32_MAX;
10882         uint32_t num_of_dest = 0;
10883         int tmp_actions_n = 0;
10884         uint32_t table;
10885         int ret = 0;
10886         const struct mlx5_flow_tunnel *tunnel;
10887         struct flow_grp_info grp_info = {
10888                 .external = !!dev_flow->external,
10889                 .transfer = !!attr->transfer,
10890                 .fdb_def_rule = !!priv->fdb_def_rule,
10891                 .skip_scale = dev_flow->skip_scale &
10892                         (1 << MLX5_SCALE_FLOW_GROUP_BIT),
10893         };
10894
10895         if (!wks)
10896                 return rte_flow_error_set(error, ENOMEM,
10897                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10898                                           NULL,
10899                                           "failed to push flow workspace");
10900         rss_desc = &wks->rss_desc;
10901         memset(&mdest_res, 0, sizeof(struct mlx5_flow_dv_dest_array_resource));
10902         memset(&sample_res, 0, sizeof(struct mlx5_flow_dv_sample_resource));
10903         mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
10904                                            MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
10905         /* update normal path action resource into last index of array */
10906         sample_act = &mdest_res.sample_act[MLX5_MAX_DEST_NUM - 1];
10907         tunnel = is_flow_tunnel_match_rule(dev, attr, items, actions) ?
10908                  flow_items_to_tunnel(items) :
10909                  is_flow_tunnel_steer_rule(dev, attr, items, actions) ?
10910                  flow_actions_to_tunnel(actions) :
10911                  dev_flow->tunnel ? dev_flow->tunnel : NULL;
10912         mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
10913                                            MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
10914         grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
10915                                 (dev, tunnel, attr, items, actions);
10916         ret = mlx5_flow_group_to_table(dev, tunnel, attr->group, &table,
10917                                        &grp_info, error);
10918         if (ret)
10919                 return ret;
10920         dev_flow->dv.group = table;
10921         if (attr->transfer)
10922                 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
10923         /* number of actions must be set to 0 in case of dirty stack. */
10924         mhdr_res->actions_num = 0;
10925         if (is_flow_tunnel_match_rule(dev, attr, items, actions)) {
10926                 /*
10927                  * do not add decap action if match rule drops packet
10928                  * HW rejects rules with decap & drop
10929                  *
10930                  * if tunnel match rule was inserted before matching tunnel set
10931                  * rule flow table used in the match rule must be registered.
10932                  * current implementation handles that in the
10933                  * flow_dv_match_register() at the function end.
10934                  */
10935                 bool add_decap = true;
10936                 const struct rte_flow_action *ptr = actions;
10937
10938                 for (; ptr->type != RTE_FLOW_ACTION_TYPE_END; ptr++) {
10939                         if (ptr->type == RTE_FLOW_ACTION_TYPE_DROP) {
10940                                 add_decap = false;
10941                                 break;
10942                         }
10943                 }
10944                 if (add_decap) {
10945                         if (flow_dv_create_action_l2_decap(dev, dev_flow,
10946                                                            attr->transfer,
10947                                                            error))
10948                                 return -rte_errno;
10949                         dev_flow->dv.actions[actions_n++] =
10950                                         dev_flow->dv.encap_decap->action;
10951                         action_flags |= MLX5_FLOW_ACTION_DECAP;
10952                 }
10953         }
10954         for (; !actions_end ; actions++) {
10955                 const struct rte_flow_action_queue *queue;
10956                 const struct rte_flow_action_rss *rss;
10957                 const struct rte_flow_action *action = actions;
10958                 const uint8_t *rss_key;
10959                 const struct rte_flow_action_meter *mtr;
10960                 struct mlx5_flow_tbl_resource *tbl;
10961                 struct mlx5_aso_age_action *age_act;
10962                 uint32_t port_id = 0;
10963                 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
10964                 int action_type = actions->type;
10965                 const struct rte_flow_action *found_action = NULL;
10966                 struct mlx5_flow_meter *fm = NULL;
10967                 uint32_t jump_group = 0;
10968
10969                 if (!mlx5_flow_os_action_supported(action_type))
10970                         return rte_flow_error_set(error, ENOTSUP,
10971                                                   RTE_FLOW_ERROR_TYPE_ACTION,
10972                                                   actions,
10973                                                   "action not supported");
10974                 switch (action_type) {
10975                 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
10976                         action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
10977                         break;
10978                 case RTE_FLOW_ACTION_TYPE_VOID:
10979                         break;
10980                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
10981                         if (flow_dv_translate_action_port_id(dev, action,
10982                                                              &port_id, error))
10983                                 return -rte_errno;
10984                         port_id_resource.port_id = port_id;
10985                         MLX5_ASSERT(!handle->rix_port_id_action);
10986                         if (flow_dv_port_id_action_resource_register
10987                             (dev, &port_id_resource, dev_flow, error))
10988                                 return -rte_errno;
10989                         dev_flow->dv.actions[actions_n++] =
10990                                         dev_flow->dv.port_id_action->action;
10991                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
10992                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_PORT_ID;
10993                         sample_act->action_flags |= MLX5_FLOW_ACTION_PORT_ID;
10994                         num_of_dest++;
10995                         break;
10996                 case RTE_FLOW_ACTION_TYPE_FLAG:
10997                         action_flags |= MLX5_FLOW_ACTION_FLAG;
10998                         dev_flow->handle->mark = 1;
10999                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
11000                                 struct rte_flow_action_mark mark = {
11001                                         .id = MLX5_FLOW_MARK_DEFAULT,
11002                                 };
11003
11004                                 if (flow_dv_convert_action_mark(dev, &mark,
11005                                                                 mhdr_res,
11006                                                                 error))
11007                                         return -rte_errno;
11008                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
11009                                 break;
11010                         }
11011                         tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
11012                         /*
11013                          * Only one FLAG or MARK is supported per device flow
11014                          * right now. So the pointer to the tag resource must be
11015                          * zero before the register process.
11016                          */
11017                         MLX5_ASSERT(!handle->dvh.rix_tag);
11018                         if (flow_dv_tag_resource_register(dev, tag_be,
11019                                                           dev_flow, error))
11020                                 return -rte_errno;
11021                         MLX5_ASSERT(dev_flow->dv.tag_resource);
11022                         dev_flow->dv.actions[actions_n++] =
11023                                         dev_flow->dv.tag_resource->action;
11024                         break;
11025                 case RTE_FLOW_ACTION_TYPE_MARK:
11026                         action_flags |= MLX5_FLOW_ACTION_MARK;
11027                         dev_flow->handle->mark = 1;
11028                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
11029                                 const struct rte_flow_action_mark *mark =
11030                                         (const struct rte_flow_action_mark *)
11031                                                 actions->conf;
11032
11033                                 if (flow_dv_convert_action_mark(dev, mark,
11034                                                                 mhdr_res,
11035                                                                 error))
11036                                         return -rte_errno;
11037                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
11038                                 break;
11039                         }
11040                         /* Fall-through */
11041                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
11042                         /* Legacy (non-extensive) MARK action. */
11043                         tag_be = mlx5_flow_mark_set
11044                               (((const struct rte_flow_action_mark *)
11045                                (actions->conf))->id);
11046                         MLX5_ASSERT(!handle->dvh.rix_tag);
11047                         if (flow_dv_tag_resource_register(dev, tag_be,
11048                                                           dev_flow, error))
11049                                 return -rte_errno;
11050                         MLX5_ASSERT(dev_flow->dv.tag_resource);
11051                         dev_flow->dv.actions[actions_n++] =
11052                                         dev_flow->dv.tag_resource->action;
11053                         break;
11054                 case RTE_FLOW_ACTION_TYPE_SET_META:
11055                         if (flow_dv_convert_action_set_meta
11056                                 (dev, mhdr_res, attr,
11057                                  (const struct rte_flow_action_set_meta *)
11058                                   actions->conf, error))
11059                                 return -rte_errno;
11060                         action_flags |= MLX5_FLOW_ACTION_SET_META;
11061                         break;
11062                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
11063                         if (flow_dv_convert_action_set_tag
11064                                 (dev, mhdr_res,
11065                                  (const struct rte_flow_action_set_tag *)
11066                                   actions->conf, error))
11067                                 return -rte_errno;
11068                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
11069                         break;
11070                 case RTE_FLOW_ACTION_TYPE_DROP:
11071                         action_flags |= MLX5_FLOW_ACTION_DROP;
11072                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_DROP;
11073                         break;
11074                 case RTE_FLOW_ACTION_TYPE_QUEUE:
11075                         queue = actions->conf;
11076                         rss_desc->queue_num = 1;
11077                         rss_desc->queue[0] = queue->index;
11078                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
11079                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
11080                         sample_act->action_flags |= MLX5_FLOW_ACTION_QUEUE;
11081                         num_of_dest++;
11082                         break;
11083                 case RTE_FLOW_ACTION_TYPE_RSS:
11084                         rss = actions->conf;
11085                         memcpy(rss_desc->queue, rss->queue,
11086                                rss->queue_num * sizeof(uint16_t));
11087                         rss_desc->queue_num = rss->queue_num;
11088                         /* NULL RSS key indicates default RSS key. */
11089                         rss_key = !rss->key ? rss_hash_default_key : rss->key;
11090                         memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
11091                         /*
11092                          * rss->level and rss.types should be set in advance
11093                          * when expanding items for RSS.
11094                          */
11095                         action_flags |= MLX5_FLOW_ACTION_RSS;
11096                         dev_flow->handle->fate_action = rss_desc->shared_rss ?
11097                                 MLX5_FLOW_FATE_SHARED_RSS :
11098                                 MLX5_FLOW_FATE_QUEUE;
11099                         break;
11100                 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
11101                         flow->age = (uint32_t)(uintptr_t)(action->conf);
11102                         age_act = flow_aso_age_get_by_idx(dev, flow->age);
11103                         __atomic_fetch_add(&age_act->refcnt, 1,
11104                                            __ATOMIC_RELAXED);
11105                         dev_flow->dv.actions[actions_n++] = age_act->dr_action;
11106                         action_flags |= MLX5_FLOW_ACTION_AGE;
11107                         break;
11108                 case RTE_FLOW_ACTION_TYPE_AGE:
11109                         if (priv->sh->flow_hit_aso_en && attr->group) {
11110                                 /*
11111                                  * Create one shared age action, to be used
11112                                  * by all sub-flows.
11113                                  */
11114                                 if (!flow->age) {
11115                                         flow->age =
11116                                                 flow_dv_translate_create_aso_age
11117                                                         (dev, action->conf,
11118                                                          error);
11119                                         if (!flow->age)
11120                                                 return rte_flow_error_set
11121                                                 (error, rte_errno,
11122                                                  RTE_FLOW_ERROR_TYPE_ACTION,
11123                                                  NULL,
11124                                                  "can't create ASO age action");
11125                                 }
11126                                 dev_flow->dv.actions[actions_n++] =
11127                                           (flow_aso_age_get_by_idx
11128                                                 (dev, flow->age))->dr_action;
11129                                 action_flags |= MLX5_FLOW_ACTION_AGE;
11130                                 break;
11131                         }
11132                         /* Fall-through */
11133                 case RTE_FLOW_ACTION_TYPE_COUNT:
11134                         if (!dev_conf->devx) {
11135                                 return rte_flow_error_set
11136                                               (error, ENOTSUP,
11137                                                RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11138                                                NULL,
11139                                                "count action not supported");
11140                         }
11141                         /* Save information first, will apply later. */
11142                         if (actions->type == RTE_FLOW_ACTION_TYPE_COUNT)
11143                                 count = action->conf;
11144                         else
11145                                 age = action->conf;
11146                         action_flags |= MLX5_FLOW_ACTION_COUNT;
11147                         break;
11148                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
11149                         dev_flow->dv.actions[actions_n++] =
11150                                                 priv->sh->pop_vlan_action;
11151                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
11152                         break;
11153                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
11154                         if (!(action_flags &
11155                               MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
11156                                 flow_dev_get_vlan_info_from_items(items, &vlan);
11157                         vlan.eth_proto = rte_be_to_cpu_16
11158                              ((((const struct rte_flow_action_of_push_vlan *)
11159                                                    actions->conf)->ethertype));
11160                         found_action = mlx5_flow_find_action
11161                                         (actions + 1,
11162                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
11163                         if (found_action)
11164                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
11165                         found_action = mlx5_flow_find_action
11166                                         (actions + 1,
11167                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
11168                         if (found_action)
11169                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
11170                         if (flow_dv_create_action_push_vlan
11171                                             (dev, attr, &vlan, dev_flow, error))
11172                                 return -rte_errno;
11173                         dev_flow->dv.actions[actions_n++] =
11174                                         dev_flow->dv.push_vlan_res->action;
11175                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
11176                         break;
11177                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
11178                         /* of_vlan_push action handled this action */
11179                         MLX5_ASSERT(action_flags &
11180                                     MLX5_FLOW_ACTION_OF_PUSH_VLAN);
11181                         break;
11182                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
11183                         if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
11184                                 break;
11185                         flow_dev_get_vlan_info_from_items(items, &vlan);
11186                         mlx5_update_vlan_vid_pcp(actions, &vlan);
11187                         /* If no VLAN push - this is a modify header action */
11188                         if (flow_dv_convert_action_modify_vlan_vid
11189                                                 (mhdr_res, actions, error))
11190                                 return -rte_errno;
11191                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
11192                         break;
11193                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
11194                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
11195                         if (flow_dv_create_action_l2_encap(dev, actions,
11196                                                            dev_flow,
11197                                                            attr->transfer,
11198                                                            error))
11199                                 return -rte_errno;
11200                         dev_flow->dv.actions[actions_n++] =
11201                                         dev_flow->dv.encap_decap->action;
11202                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
11203                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
11204                                 sample_act->action_flags |=
11205                                                         MLX5_FLOW_ACTION_ENCAP;
11206                         break;
11207                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
11208                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
11209                         if (flow_dv_create_action_l2_decap(dev, dev_flow,
11210                                                            attr->transfer,
11211                                                            error))
11212                                 return -rte_errno;
11213                         dev_flow->dv.actions[actions_n++] =
11214                                         dev_flow->dv.encap_decap->action;
11215                         action_flags |= MLX5_FLOW_ACTION_DECAP;
11216                         break;
11217                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
11218                         /* Handle encap with preceding decap. */
11219                         if (action_flags & MLX5_FLOW_ACTION_DECAP) {
11220                                 if (flow_dv_create_action_raw_encap
11221                                         (dev, actions, dev_flow, attr, error))
11222                                         return -rte_errno;
11223                                 dev_flow->dv.actions[actions_n++] =
11224                                         dev_flow->dv.encap_decap->action;
11225                         } else {
11226                                 /* Handle encap without preceding decap. */
11227                                 if (flow_dv_create_action_l2_encap
11228                                     (dev, actions, dev_flow, attr->transfer,
11229                                      error))
11230                                         return -rte_errno;
11231                                 dev_flow->dv.actions[actions_n++] =
11232                                         dev_flow->dv.encap_decap->action;
11233                         }
11234                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
11235                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
11236                                 sample_act->action_flags |=
11237                                                         MLX5_FLOW_ACTION_ENCAP;
11238                         break;
11239                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
11240                         while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
11241                                 ;
11242                         if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
11243                                 if (flow_dv_create_action_l2_decap
11244                                     (dev, dev_flow, attr->transfer, error))
11245                                         return -rte_errno;
11246                                 dev_flow->dv.actions[actions_n++] =
11247                                         dev_flow->dv.encap_decap->action;
11248                         }
11249                         /* If decap is followed by encap, handle it at encap. */
11250                         action_flags |= MLX5_FLOW_ACTION_DECAP;
11251                         break;
11252                 case RTE_FLOW_ACTION_TYPE_JUMP:
11253                         jump_group = ((const struct rte_flow_action_jump *)
11254                                                         action->conf)->group;
11255                         grp_info.std_tbl_fix = 0;
11256                         if (dev_flow->skip_scale &
11257                                 (1 << MLX5_SCALE_JUMP_FLOW_GROUP_BIT))
11258                                 grp_info.skip_scale = 1;
11259                         else
11260                                 grp_info.skip_scale = 0;
11261                         ret = mlx5_flow_group_to_table(dev, tunnel,
11262                                                        jump_group,
11263                                                        &table,
11264                                                        &grp_info, error);
11265                         if (ret)
11266                                 return ret;
11267                         tbl = flow_dv_tbl_resource_get(dev, table, attr->egress,
11268                                                        attr->transfer,
11269                                                        !!dev_flow->external,
11270                                                        tunnel, jump_group, 0,
11271                                                        error);
11272                         if (!tbl)
11273                                 return rte_flow_error_set
11274                                                 (error, errno,
11275                                                  RTE_FLOW_ERROR_TYPE_ACTION,
11276                                                  NULL,
11277                                                  "cannot create jump action.");
11278                         if (flow_dv_jump_tbl_resource_register
11279                             (dev, tbl, dev_flow, error)) {
11280                                 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
11281                                 return rte_flow_error_set
11282                                                 (error, errno,
11283                                                  RTE_FLOW_ERROR_TYPE_ACTION,
11284                                                  NULL,
11285                                                  "cannot create jump action.");
11286                         }
11287                         dev_flow->dv.actions[actions_n++] =
11288                                         dev_flow->dv.jump->action;
11289                         action_flags |= MLX5_FLOW_ACTION_JUMP;
11290                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_JUMP;
11291                         sample_act->action_flags |= MLX5_FLOW_ACTION_JUMP;
11292                         num_of_dest++;
11293                         break;
11294                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
11295                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
11296                         if (flow_dv_convert_action_modify_mac
11297                                         (mhdr_res, actions, error))
11298                                 return -rte_errno;
11299                         action_flags |= actions->type ==
11300                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
11301                                         MLX5_FLOW_ACTION_SET_MAC_SRC :
11302                                         MLX5_FLOW_ACTION_SET_MAC_DST;
11303                         break;
11304                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
11305                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
11306                         if (flow_dv_convert_action_modify_ipv4
11307                                         (mhdr_res, actions, error))
11308                                 return -rte_errno;
11309                         action_flags |= actions->type ==
11310                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
11311                                         MLX5_FLOW_ACTION_SET_IPV4_SRC :
11312                                         MLX5_FLOW_ACTION_SET_IPV4_DST;
11313                         break;
11314                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
11315                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
11316                         if (flow_dv_convert_action_modify_ipv6
11317                                         (mhdr_res, actions, error))
11318                                 return -rte_errno;
11319                         action_flags |= actions->type ==
11320                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
11321                                         MLX5_FLOW_ACTION_SET_IPV6_SRC :
11322                                         MLX5_FLOW_ACTION_SET_IPV6_DST;
11323                         break;
11324                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
11325                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
11326                         if (flow_dv_convert_action_modify_tp
11327                                         (mhdr_res, actions, items,
11328                                          &flow_attr, dev_flow, !!(action_flags &
11329                                          MLX5_FLOW_ACTION_DECAP), error))
11330                                 return -rte_errno;
11331                         action_flags |= actions->type ==
11332                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
11333                                         MLX5_FLOW_ACTION_SET_TP_SRC :
11334                                         MLX5_FLOW_ACTION_SET_TP_DST;
11335                         break;
11336                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
11337                         if (flow_dv_convert_action_modify_dec_ttl
11338                                         (mhdr_res, items, &flow_attr, dev_flow,
11339                                          !!(action_flags &
11340                                          MLX5_FLOW_ACTION_DECAP), error))
11341                                 return -rte_errno;
11342                         action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
11343                         break;
11344                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
11345                         if (flow_dv_convert_action_modify_ttl
11346                                         (mhdr_res, actions, items, &flow_attr,
11347                                          dev_flow, !!(action_flags &
11348                                          MLX5_FLOW_ACTION_DECAP), error))
11349                                 return -rte_errno;
11350                         action_flags |= MLX5_FLOW_ACTION_SET_TTL;
11351                         break;
11352                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
11353                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
11354                         if (flow_dv_convert_action_modify_tcp_seq
11355                                         (mhdr_res, actions, error))
11356                                 return -rte_errno;
11357                         action_flags |= actions->type ==
11358                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
11359                                         MLX5_FLOW_ACTION_INC_TCP_SEQ :
11360                                         MLX5_FLOW_ACTION_DEC_TCP_SEQ;
11361                         break;
11362
11363                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
11364                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
11365                         if (flow_dv_convert_action_modify_tcp_ack
11366                                         (mhdr_res, actions, error))
11367                                 return -rte_errno;
11368                         action_flags |= actions->type ==
11369                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
11370                                         MLX5_FLOW_ACTION_INC_TCP_ACK :
11371                                         MLX5_FLOW_ACTION_DEC_TCP_ACK;
11372                         break;
11373                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
11374                         if (flow_dv_convert_action_set_reg
11375                                         (mhdr_res, actions, error))
11376                                 return -rte_errno;
11377                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
11378                         break;
11379                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
11380                         if (flow_dv_convert_action_copy_mreg
11381                                         (dev, mhdr_res, actions, error))
11382                                 return -rte_errno;
11383                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
11384                         break;
11385                 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
11386                         action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
11387                         dev_flow->handle->fate_action =
11388                                         MLX5_FLOW_FATE_DEFAULT_MISS;
11389                         break;
11390                 case RTE_FLOW_ACTION_TYPE_METER:
11391                         mtr = actions->conf;
11392                         if (!flow->meter) {
11393                                 fm = mlx5_flow_meter_attach(priv, mtr->mtr_id,
11394                                                             attr, error);
11395                                 if (!fm)
11396                                         return rte_flow_error_set(error,
11397                                                 rte_errno,
11398                                                 RTE_FLOW_ERROR_TYPE_ACTION,
11399                                                 NULL,
11400                                                 "meter not found "
11401                                                 "or invalid parameters");
11402                                 flow->meter = fm->idx;
11403                         }
11404                         /* Set the meter action. */
11405                         if (!fm) {
11406                                 fm = mlx5_ipool_get(priv->sh->ipool
11407                                                 [MLX5_IPOOL_MTR], flow->meter);
11408                                 if (!fm)
11409                                         return rte_flow_error_set(error,
11410                                                 rte_errno,
11411                                                 RTE_FLOW_ERROR_TYPE_ACTION,
11412                                                 NULL,
11413                                                 "meter not found "
11414                                                 "or invalid parameters");
11415                         }
11416                         dev_flow->dv.actions[actions_n++] =
11417                                 fm->mfts->meter_action;
11418                         action_flags |= MLX5_FLOW_ACTION_METER;
11419                         break;
11420                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
11421                         if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
11422                                                               actions, error))
11423                                 return -rte_errno;
11424                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
11425                         break;
11426                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
11427                         if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
11428                                                               actions, error))
11429                                 return -rte_errno;
11430                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
11431                         break;
11432                 case RTE_FLOW_ACTION_TYPE_SAMPLE:
11433                         sample_act_pos = actions_n;
11434                         sample = (const struct rte_flow_action_sample *)
11435                                  action->conf;
11436                         actions_n++;
11437                         action_flags |= MLX5_FLOW_ACTION_SAMPLE;
11438                         /* put encap action into group if work with port id */
11439                         if ((action_flags & MLX5_FLOW_ACTION_ENCAP) &&
11440                             (action_flags & MLX5_FLOW_ACTION_PORT_ID))
11441                                 sample_act->action_flags |=
11442                                                         MLX5_FLOW_ACTION_ENCAP;
11443                         break;
11444                 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
11445                         if (flow_dv_convert_action_modify_field
11446                                         (dev, mhdr_res, actions, attr, error))
11447                                 return -rte_errno;
11448                         action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
11449                         break;
11450                 case RTE_FLOW_ACTION_TYPE_END:
11451                         actions_end = true;
11452                         if (mhdr_res->actions_num) {
11453                                 /* create modify action if needed. */
11454                                 if (flow_dv_modify_hdr_resource_register
11455                                         (dev, mhdr_res, dev_flow, error))
11456                                         return -rte_errno;
11457                                 dev_flow->dv.actions[modify_action_position] =
11458                                         handle->dvh.modify_hdr->action;
11459                         }
11460                         if (action_flags & MLX5_FLOW_ACTION_COUNT) {
11461                                 /*
11462                                  * Create one count action, to be used
11463                                  * by all sub-flows.
11464                                  */
11465                                 if (!flow->counter) {
11466                                         flow->counter =
11467                                                 flow_dv_translate_create_counter
11468                                                         (dev, dev_flow, count,
11469                                                          age);
11470                                         if (!flow->counter)
11471                                                 return rte_flow_error_set
11472                                                 (error, rte_errno,
11473                                                  RTE_FLOW_ERROR_TYPE_ACTION,
11474                                                  NULL, "cannot create counter"
11475                                                  " object.");
11476                                 }
11477                                 dev_flow->dv.actions[actions_n] =
11478                                           (flow_dv_counter_get_by_idx(dev,
11479                                           flow->counter, NULL))->action;
11480                                 actions_n++;
11481                         }
11482                 default:
11483                         break;
11484                 }
11485                 if (mhdr_res->actions_num &&
11486                     modify_action_position == UINT32_MAX)
11487                         modify_action_position = actions_n++;
11488         }
11489         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
11490                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
11491                 int item_type = items->type;
11492
11493                 if (!mlx5_flow_os_item_supported(item_type))
11494                         return rte_flow_error_set(error, ENOTSUP,
11495                                                   RTE_FLOW_ERROR_TYPE_ITEM,
11496                                                   NULL, "item not supported");
11497                 switch (item_type) {
11498                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
11499                         flow_dv_translate_item_port_id
11500                                 (dev, match_mask, match_value, items, attr);
11501                         last_item = MLX5_FLOW_ITEM_PORT_ID;
11502                         break;
11503                 case RTE_FLOW_ITEM_TYPE_ETH:
11504                         flow_dv_translate_item_eth(match_mask, match_value,
11505                                                    items, tunnel,
11506                                                    dev_flow->dv.group);
11507                         matcher.priority = action_flags &
11508                                         MLX5_FLOW_ACTION_DEFAULT_MISS &&
11509                                         !dev_flow->external ?
11510                                         MLX5_PRIORITY_MAP_L3 :
11511                                         MLX5_PRIORITY_MAP_L2;
11512                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
11513                                              MLX5_FLOW_LAYER_OUTER_L2;
11514                         break;
11515                 case RTE_FLOW_ITEM_TYPE_VLAN:
11516                         flow_dv_translate_item_vlan(dev_flow,
11517                                                     match_mask, match_value,
11518                                                     items, tunnel,
11519                                                     dev_flow->dv.group);
11520                         matcher.priority = MLX5_PRIORITY_MAP_L2;
11521                         last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
11522                                               MLX5_FLOW_LAYER_INNER_VLAN) :
11523                                              (MLX5_FLOW_LAYER_OUTER_L2 |
11524                                               MLX5_FLOW_LAYER_OUTER_VLAN);
11525                         break;
11526                 case RTE_FLOW_ITEM_TYPE_IPV4:
11527                         mlx5_flow_tunnel_ip_check(items, next_protocol,
11528                                                   &item_flags, &tunnel);
11529                         flow_dv_translate_item_ipv4(match_mask, match_value,
11530                                                     items, tunnel,
11531                                                     dev_flow->dv.group);
11532                         matcher.priority = MLX5_PRIORITY_MAP_L3;
11533                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
11534                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
11535                         if (items->mask != NULL &&
11536                             ((const struct rte_flow_item_ipv4 *)
11537                              items->mask)->hdr.next_proto_id) {
11538                                 next_protocol =
11539                                         ((const struct rte_flow_item_ipv4 *)
11540                                          (items->spec))->hdr.next_proto_id;
11541                                 next_protocol &=
11542                                         ((const struct rte_flow_item_ipv4 *)
11543                                          (items->mask))->hdr.next_proto_id;
11544                         } else {
11545                                 /* Reset for inner layer. */
11546                                 next_protocol = 0xff;
11547                         }
11548                         break;
11549                 case RTE_FLOW_ITEM_TYPE_IPV6:
11550                         mlx5_flow_tunnel_ip_check(items, next_protocol,
11551                                                   &item_flags, &tunnel);
11552                         flow_dv_translate_item_ipv6(match_mask, match_value,
11553                                                     items, tunnel,
11554                                                     dev_flow->dv.group);
11555                         matcher.priority = MLX5_PRIORITY_MAP_L3;
11556                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
11557                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
11558                         if (items->mask != NULL &&
11559                             ((const struct rte_flow_item_ipv6 *)
11560                              items->mask)->hdr.proto) {
11561                                 next_protocol =
11562                                         ((const struct rte_flow_item_ipv6 *)
11563                                          items->spec)->hdr.proto;
11564                                 next_protocol &=
11565                                         ((const struct rte_flow_item_ipv6 *)
11566                                          items->mask)->hdr.proto;
11567                         } else {
11568                                 /* Reset for inner layer. */
11569                                 next_protocol = 0xff;
11570                         }
11571                         break;
11572                 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
11573                         flow_dv_translate_item_ipv6_frag_ext(match_mask,
11574                                                              match_value,
11575                                                              items, tunnel);
11576                         last_item = tunnel ?
11577                                         MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
11578                                         MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
11579                         if (items->mask != NULL &&
11580                             ((const struct rte_flow_item_ipv6_frag_ext *)
11581                              items->mask)->hdr.next_header) {
11582                                 next_protocol =
11583                                 ((const struct rte_flow_item_ipv6_frag_ext *)
11584                                  items->spec)->hdr.next_header;
11585                                 next_protocol &=
11586                                 ((const struct rte_flow_item_ipv6_frag_ext *)
11587                                  items->mask)->hdr.next_header;
11588                         } else {
11589                                 /* Reset for inner layer. */
11590                                 next_protocol = 0xff;
11591                         }
11592                         break;
11593                 case RTE_FLOW_ITEM_TYPE_TCP:
11594                         flow_dv_translate_item_tcp(match_mask, match_value,
11595                                                    items, tunnel);
11596                         matcher.priority = MLX5_PRIORITY_MAP_L4;
11597                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
11598                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
11599                         break;
11600                 case RTE_FLOW_ITEM_TYPE_UDP:
11601                         flow_dv_translate_item_udp(match_mask, match_value,
11602                                                    items, tunnel);
11603                         matcher.priority = MLX5_PRIORITY_MAP_L4;
11604                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
11605                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
11606                         break;
11607                 case RTE_FLOW_ITEM_TYPE_GRE:
11608                         flow_dv_translate_item_gre(match_mask, match_value,
11609                                                    items, tunnel);
11610                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11611                         last_item = MLX5_FLOW_LAYER_GRE;
11612                         break;
11613                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
11614                         flow_dv_translate_item_gre_key(match_mask,
11615                                                        match_value, items);
11616                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
11617                         break;
11618                 case RTE_FLOW_ITEM_TYPE_NVGRE:
11619                         flow_dv_translate_item_nvgre(match_mask, match_value,
11620                                                      items, tunnel);
11621                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11622                         last_item = MLX5_FLOW_LAYER_GRE;
11623                         break;
11624                 case RTE_FLOW_ITEM_TYPE_VXLAN:
11625                         flow_dv_translate_item_vxlan(match_mask, match_value,
11626                                                      items, tunnel);
11627                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11628                         last_item = MLX5_FLOW_LAYER_VXLAN;
11629                         break;
11630                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
11631                         flow_dv_translate_item_vxlan_gpe(match_mask,
11632                                                          match_value, items,
11633                                                          tunnel);
11634                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11635                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
11636                         break;
11637                 case RTE_FLOW_ITEM_TYPE_GENEVE:
11638                         flow_dv_translate_item_geneve(match_mask, match_value,
11639                                                       items, tunnel);
11640                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11641                         last_item = MLX5_FLOW_LAYER_GENEVE;
11642                         break;
11643                 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
11644                         ret = flow_dv_translate_item_geneve_opt(dev, match_mask,
11645                                                           match_value,
11646                                                           items, error);
11647                         if (ret)
11648                                 return rte_flow_error_set(error, -ret,
11649                                         RTE_FLOW_ERROR_TYPE_ITEM, NULL,
11650                                         "cannot create GENEVE TLV option");
11651                         flow->geneve_tlv_option = 1;
11652                         last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
11653                         break;
11654                 case RTE_FLOW_ITEM_TYPE_MPLS:
11655                         flow_dv_translate_item_mpls(match_mask, match_value,
11656                                                     items, last_item, tunnel);
11657                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11658                         last_item = MLX5_FLOW_LAYER_MPLS;
11659                         break;
11660                 case RTE_FLOW_ITEM_TYPE_MARK:
11661                         flow_dv_translate_item_mark(dev, match_mask,
11662                                                     match_value, items);
11663                         last_item = MLX5_FLOW_ITEM_MARK;
11664                         break;
11665                 case RTE_FLOW_ITEM_TYPE_META:
11666                         flow_dv_translate_item_meta(dev, match_mask,
11667                                                     match_value, attr, items);
11668                         last_item = MLX5_FLOW_ITEM_METADATA;
11669                         break;
11670                 case RTE_FLOW_ITEM_TYPE_ICMP:
11671                         flow_dv_translate_item_icmp(match_mask, match_value,
11672                                                     items, tunnel);
11673                         last_item = MLX5_FLOW_LAYER_ICMP;
11674                         break;
11675                 case RTE_FLOW_ITEM_TYPE_ICMP6:
11676                         flow_dv_translate_item_icmp6(match_mask, match_value,
11677                                                       items, tunnel);
11678                         last_item = MLX5_FLOW_LAYER_ICMP6;
11679                         break;
11680                 case RTE_FLOW_ITEM_TYPE_TAG:
11681                         flow_dv_translate_item_tag(dev, match_mask,
11682                                                    match_value, items);
11683                         last_item = MLX5_FLOW_ITEM_TAG;
11684                         break;
11685                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
11686                         flow_dv_translate_mlx5_item_tag(dev, match_mask,
11687                                                         match_value, items);
11688                         last_item = MLX5_FLOW_ITEM_TAG;
11689                         break;
11690                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
11691                         flow_dv_translate_item_tx_queue(dev, match_mask,
11692                                                         match_value,
11693                                                         items);
11694                         last_item = MLX5_FLOW_ITEM_TX_QUEUE;
11695                         break;
11696                 case RTE_FLOW_ITEM_TYPE_GTP:
11697                         flow_dv_translate_item_gtp(match_mask, match_value,
11698                                                    items, tunnel);
11699                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11700                         last_item = MLX5_FLOW_LAYER_GTP;
11701                         break;
11702                 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
11703                         ret = flow_dv_translate_item_gtp_psc(match_mask,
11704                                                           match_value,
11705                                                           items);
11706                         if (ret)
11707                                 return rte_flow_error_set(error, -ret,
11708                                         RTE_FLOW_ERROR_TYPE_ITEM, NULL,
11709                                         "cannot create GTP PSC item");
11710                         last_item = MLX5_FLOW_LAYER_GTP_PSC;
11711                         break;
11712                 case RTE_FLOW_ITEM_TYPE_ECPRI:
11713                         if (!mlx5_flex_parser_ecpri_exist(dev)) {
11714                                 /* Create it only the first time to be used. */
11715                                 ret = mlx5_flex_parser_ecpri_alloc(dev);
11716                                 if (ret)
11717                                         return rte_flow_error_set
11718                                                 (error, -ret,
11719                                                 RTE_FLOW_ERROR_TYPE_ITEM,
11720                                                 NULL,
11721                                                 "cannot create eCPRI parser");
11722                         }
11723                         /* Adjust the length matcher and device flow value. */
11724                         matcher.mask.size = MLX5_ST_SZ_BYTES(fte_match_param);
11725                         dev_flow->dv.value.size =
11726                                         MLX5_ST_SZ_BYTES(fte_match_param);
11727                         flow_dv_translate_item_ecpri(dev, match_mask,
11728                                                      match_value, items);
11729                         /* No other protocol should follow eCPRI layer. */
11730                         last_item = MLX5_FLOW_LAYER_ECPRI;
11731                         break;
11732                 default:
11733                         break;
11734                 }
11735                 item_flags |= last_item;
11736         }
11737         /*
11738          * When E-Switch mode is enabled, we have two cases where we need to
11739          * set the source port manually.
11740          * The first one, is in case of Nic steering rule, and the second is
11741          * E-Switch rule where no port_id item was found. In both cases
11742          * the source port is set according the current port in use.
11743          */
11744         if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
11745             (priv->representor || priv->master)) {
11746                 if (flow_dv_translate_item_port_id(dev, match_mask,
11747                                                    match_value, NULL, attr))
11748                         return -rte_errno;
11749         }
11750 #ifdef RTE_LIBRTE_MLX5_DEBUG
11751         MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
11752                                               dev_flow->dv.value.buf));
11753 #endif
11754         /*
11755          * Layers may be already initialized from prefix flow if this dev_flow
11756          * is the suffix flow.
11757          */
11758         handle->layers |= item_flags;
11759         if (action_flags & MLX5_FLOW_ACTION_RSS)
11760                 flow_dv_hashfields_set(dev_flow, rss_desc);
11761         /* If has RSS action in the sample action, the Sample/Mirror resource
11762          * should be registered after the hash filed be update.
11763          */
11764         if (action_flags & MLX5_FLOW_ACTION_SAMPLE) {
11765                 ret = flow_dv_translate_action_sample(dev,
11766                                                       sample,
11767                                                       dev_flow, attr,
11768                                                       &num_of_dest,
11769                                                       sample_actions,
11770                                                       &sample_res,
11771                                                       error);
11772                 if (ret < 0)
11773                         return ret;
11774                 ret = flow_dv_create_action_sample(dev,
11775                                                    dev_flow,
11776                                                    num_of_dest,
11777                                                    &sample_res,
11778                                                    &mdest_res,
11779                                                    sample_actions,
11780                                                    action_flags,
11781                                                    error);
11782                 if (ret < 0)
11783                         return rte_flow_error_set
11784                                                 (error, rte_errno,
11785                                                 RTE_FLOW_ERROR_TYPE_ACTION,
11786                                                 NULL,
11787                                                 "cannot create sample action");
11788                 if (num_of_dest > 1) {
11789                         dev_flow->dv.actions[sample_act_pos] =
11790                         dev_flow->dv.dest_array_res->action;
11791                 } else {
11792                         dev_flow->dv.actions[sample_act_pos] =
11793                         dev_flow->dv.sample_res->verbs_action;
11794                 }
11795         }
11796         /*
11797          * For multiple destination (sample action with ratio=1), the encap
11798          * action and port id action will be combined into group action.
11799          * So need remove the original these actions in the flow and only
11800          * use the sample action instead of.
11801          */
11802         if (num_of_dest > 1 &&
11803             (sample_act->dr_port_id_action || sample_act->dr_jump_action)) {
11804                 int i;
11805                 void *temp_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
11806
11807                 for (i = 0; i < actions_n; i++) {
11808                         if ((sample_act->dr_encap_action &&
11809                                 sample_act->dr_encap_action ==
11810                                 dev_flow->dv.actions[i]) ||
11811                                 (sample_act->dr_port_id_action &&
11812                                 sample_act->dr_port_id_action ==
11813                                 dev_flow->dv.actions[i]) ||
11814                                 (sample_act->dr_jump_action &&
11815                                 sample_act->dr_jump_action ==
11816                                 dev_flow->dv.actions[i]))
11817                                 continue;
11818                         temp_actions[tmp_actions_n++] = dev_flow->dv.actions[i];
11819                 }
11820                 memcpy((void *)dev_flow->dv.actions,
11821                                 (void *)temp_actions,
11822                                 tmp_actions_n * sizeof(void *));
11823                 actions_n = tmp_actions_n;
11824         }
11825         dev_flow->dv.actions_n = actions_n;
11826         dev_flow->act_flags = action_flags;
11827         /* Register matcher. */
11828         matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
11829                                     matcher.mask.size);
11830         matcher.priority = mlx5_get_matcher_priority(dev, attr,
11831                                         matcher.priority);
11832         /* reserved field no needs to be set to 0 here. */
11833         tbl_key.domain = attr->transfer;
11834         tbl_key.direction = attr->egress;
11835         tbl_key.table_id = dev_flow->dv.group;
11836         if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow,
11837                                      tunnel, attr->group, error))
11838                 return -rte_errno;
11839         return 0;
11840 }
11841
11842 /**
11843  * Set hash RX queue by hash fields (see enum ibv_rx_hash_fields)
11844  * and tunnel.
11845  *
11846  * @param[in, out] action
11847  *   Shred RSS action holding hash RX queue objects.
11848  * @param[in] hash_fields
11849  *   Defines combination of packet fields to participate in RX hash.
11850  * @param[in] tunnel
11851  *   Tunnel type
11852  * @param[in] hrxq_idx
11853  *   Hash RX queue index to set.
11854  *
11855  * @return
11856  *   0 on success, otherwise negative errno value.
11857  */
11858 static int
11859 __flow_dv_action_rss_hrxq_set(struct mlx5_shared_action_rss *action,
11860                               const uint64_t hash_fields,
11861                               const int tunnel,
11862                               uint32_t hrxq_idx)
11863 {
11864         uint32_t *hrxqs = tunnel ? action->hrxq : action->hrxq_tunnel;
11865
11866         switch (hash_fields & ~IBV_RX_HASH_INNER) {
11867         case MLX5_RSS_HASH_IPV4:
11868                 hrxqs[0] = hrxq_idx;
11869                 return 0;
11870         case MLX5_RSS_HASH_IPV4_TCP:
11871                 hrxqs[1] = hrxq_idx;
11872                 return 0;
11873         case MLX5_RSS_HASH_IPV4_UDP:
11874                 hrxqs[2] = hrxq_idx;
11875                 return 0;
11876         case MLX5_RSS_HASH_IPV6:
11877                 hrxqs[3] = hrxq_idx;
11878                 return 0;
11879         case MLX5_RSS_HASH_IPV6_TCP:
11880                 hrxqs[4] = hrxq_idx;
11881                 return 0;
11882         case MLX5_RSS_HASH_IPV6_UDP:
11883                 hrxqs[5] = hrxq_idx;
11884                 return 0;
11885         case MLX5_RSS_HASH_NONE:
11886                 hrxqs[6] = hrxq_idx;
11887                 return 0;
11888         default:
11889                 return -1;
11890         }
11891 }
11892
11893 /**
11894  * Look up for hash RX queue by hash fields (see enum ibv_rx_hash_fields)
11895  * and tunnel.
11896  *
11897  * @param[in] dev
11898  *   Pointer to the Ethernet device structure.
11899  * @param[in] idx
11900  *   Shared RSS action ID holding hash RX queue objects.
11901  * @param[in] hash_fields
11902  *   Defines combination of packet fields to participate in RX hash.
11903  * @param[in] tunnel
11904  *   Tunnel type
11905  *
11906  * @return
11907  *   Valid hash RX queue index, otherwise 0.
11908  */
11909 static uint32_t
11910 __flow_dv_action_rss_hrxq_lookup(struct rte_eth_dev *dev, uint32_t idx,
11911                                  const uint64_t hash_fields,
11912                                  const int tunnel)
11913 {
11914         struct mlx5_priv *priv = dev->data->dev_private;
11915         struct mlx5_shared_action_rss *shared_rss =
11916             mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
11917         const uint32_t *hrxqs = tunnel ? shared_rss->hrxq :
11918                                                         shared_rss->hrxq_tunnel;
11919
11920         switch (hash_fields & ~IBV_RX_HASH_INNER) {
11921         case MLX5_RSS_HASH_IPV4:
11922                 return hrxqs[0];
11923         case MLX5_RSS_HASH_IPV4_TCP:
11924                 return hrxqs[1];
11925         case MLX5_RSS_HASH_IPV4_UDP:
11926                 return hrxqs[2];
11927         case MLX5_RSS_HASH_IPV6:
11928                 return hrxqs[3];
11929         case MLX5_RSS_HASH_IPV6_TCP:
11930                 return hrxqs[4];
11931         case MLX5_RSS_HASH_IPV6_UDP:
11932                 return hrxqs[5];
11933         case MLX5_RSS_HASH_NONE:
11934                 return hrxqs[6];
11935         default:
11936                 return 0;
11937         }
11938 }
11939
11940 /**
11941  * Apply the flow to the NIC, lock free,
11942  * (mutex should be acquired by caller).
11943  *
11944  * @param[in] dev
11945  *   Pointer to the Ethernet device structure.
11946  * @param[in, out] flow
11947  *   Pointer to flow structure.
11948  * @param[out] error
11949  *   Pointer to error structure.
11950  *
11951  * @return
11952  *   0 on success, a negative errno value otherwise and rte_errno is set.
11953  */
11954 static int
11955 flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
11956               struct rte_flow_error *error)
11957 {
11958         struct mlx5_flow_dv_workspace *dv;
11959         struct mlx5_flow_handle *dh;
11960         struct mlx5_flow_handle_dv *dv_h;
11961         struct mlx5_flow *dev_flow;
11962         struct mlx5_priv *priv = dev->data->dev_private;
11963         uint32_t handle_idx;
11964         int n;
11965         int err;
11966         int idx;
11967         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
11968         struct mlx5_flow_rss_desc *rss_desc = &wks->rss_desc;
11969
11970         MLX5_ASSERT(wks);
11971         for (idx = wks->flow_idx - 1; idx >= 0; idx--) {
11972                 dev_flow = &wks->flows[idx];
11973                 dv = &dev_flow->dv;
11974                 dh = dev_flow->handle;
11975                 dv_h = &dh->dvh;
11976                 n = dv->actions_n;
11977                 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
11978                         if (dv->transfer) {
11979                                 dv->actions[n++] = priv->sh->esw_drop_action;
11980                         } else {
11981                                 MLX5_ASSERT(priv->drop_queue.hrxq);
11982                                 dv->actions[n++] =
11983                                                 priv->drop_queue.hrxq->action;
11984                         }
11985                 } else if ((dh->fate_action == MLX5_FLOW_FATE_QUEUE &&
11986                            !dv_h->rix_sample && !dv_h->rix_dest_array)) {
11987                         struct mlx5_hrxq *hrxq;
11988                         uint32_t hrxq_idx;
11989
11990                         hrxq = flow_dv_hrxq_prepare(dev, dev_flow, rss_desc,
11991                                                     &hrxq_idx);
11992                         if (!hrxq) {
11993                                 rte_flow_error_set
11994                                         (error, rte_errno,
11995                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11996                                          "cannot get hash queue");
11997                                 goto error;
11998                         }
11999                         dh->rix_hrxq = hrxq_idx;
12000                         dv->actions[n++] = hrxq->action;
12001                 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
12002                         struct mlx5_hrxq *hrxq = NULL;
12003                         uint32_t hrxq_idx;
12004
12005                         hrxq_idx = __flow_dv_action_rss_hrxq_lookup(dev,
12006                                                 rss_desc->shared_rss,
12007                                                 dev_flow->hash_fields,
12008                                                 !!(dh->layers &
12009                                                 MLX5_FLOW_LAYER_TUNNEL));
12010                         if (hrxq_idx)
12011                                 hrxq = mlx5_ipool_get
12012                                         (priv->sh->ipool[MLX5_IPOOL_HRXQ],
12013                                          hrxq_idx);
12014                         if (!hrxq) {
12015                                 rte_flow_error_set
12016                                         (error, rte_errno,
12017                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12018                                          "cannot get hash queue");
12019                                 goto error;
12020                         }
12021                         dh->rix_srss = rss_desc->shared_rss;
12022                         dv->actions[n++] = hrxq->action;
12023                 } else if (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS) {
12024                         if (!priv->sh->default_miss_action) {
12025                                 rte_flow_error_set
12026                                         (error, rte_errno,
12027                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12028                                          "default miss action not be created.");
12029                                 goto error;
12030                         }
12031                         dv->actions[n++] = priv->sh->default_miss_action;
12032                 }
12033                 err = mlx5_flow_os_create_flow(dv_h->matcher->matcher_object,
12034                                                (void *)&dv->value, n,
12035                                                dv->actions, &dh->drv_flow);
12036                 if (err) {
12037                         rte_flow_error_set(error, errno,
12038                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12039                                            NULL,
12040                                            "hardware refuses to create flow");
12041                         goto error;
12042                 }
12043                 if (priv->vmwa_context &&
12044                     dh->vf_vlan.tag && !dh->vf_vlan.created) {
12045                         /*
12046                          * The rule contains the VLAN pattern.
12047                          * For VF we are going to create VLAN
12048                          * interface to make hypervisor set correct
12049                          * e-Switch vport context.
12050                          */
12051                         mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
12052                 }
12053         }
12054         return 0;
12055 error:
12056         err = rte_errno; /* Save rte_errno before cleanup. */
12057         SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles,
12058                        handle_idx, dh, next) {
12059                 /* hrxq is union, don't clear it if the flag is not set. */
12060                 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE && dh->rix_hrxq) {
12061                         mlx5_hrxq_release(dev, dh->rix_hrxq);
12062                         dh->rix_hrxq = 0;
12063                 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
12064                         dh->rix_srss = 0;
12065                 }
12066                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
12067                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
12068         }
12069         rte_errno = err; /* Restore rte_errno. */
12070         return -rte_errno;
12071 }
12072
12073 void
12074 flow_dv_matcher_remove_cb(struct mlx5_cache_list *list __rte_unused,
12075                           struct mlx5_cache_entry *entry)
12076 {
12077         struct mlx5_flow_dv_matcher *cache = container_of(entry, typeof(*cache),
12078                                                           entry);
12079
12080         claim_zero(mlx5_flow_os_destroy_flow_matcher(cache->matcher_object));
12081         mlx5_free(cache);
12082 }
12083
12084 /**
12085  * Release the flow matcher.
12086  *
12087  * @param dev
12088  *   Pointer to Ethernet device.
12089  * @param port_id
12090  *   Index to port ID action resource.
12091  *
12092  * @return
12093  *   1 while a reference on it exists, 0 when freed.
12094  */
12095 static int
12096 flow_dv_matcher_release(struct rte_eth_dev *dev,
12097                         struct mlx5_flow_handle *handle)
12098 {
12099         struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
12100         struct mlx5_flow_tbl_data_entry *tbl = container_of(matcher->tbl,
12101                                                             typeof(*tbl), tbl);
12102         int ret;
12103
12104         MLX5_ASSERT(matcher->matcher_object);
12105         ret = mlx5_cache_unregister(&tbl->matchers, &matcher->entry);
12106         flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl->tbl);
12107         return ret;
12108 }
12109
12110 /**
12111  * Release encap_decap resource.
12112  *
12113  * @param list
12114  *   Pointer to the hash list.
12115  * @param entry
12116  *   Pointer to exist resource entry object.
12117  */
12118 void
12119 flow_dv_encap_decap_remove_cb(struct mlx5_hlist *list,
12120                               struct mlx5_hlist_entry *entry)
12121 {
12122         struct mlx5_dev_ctx_shared *sh = list->ctx;
12123         struct mlx5_flow_dv_encap_decap_resource *res =
12124                 container_of(entry, typeof(*res), entry);
12125
12126         claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
12127         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], res->idx);
12128 }
12129
12130 /**
12131  * Release an encap/decap resource.
12132  *
12133  * @param dev
12134  *   Pointer to Ethernet device.
12135  * @param encap_decap_idx
12136  *   Index of encap decap resource.
12137  *
12138  * @return
12139  *   1 while a reference on it exists, 0 when freed.
12140  */
12141 static int
12142 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
12143                                      uint32_t encap_decap_idx)
12144 {
12145         struct mlx5_priv *priv = dev->data->dev_private;
12146         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
12147
12148         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
12149                                         encap_decap_idx);
12150         if (!cache_resource)
12151                 return 0;
12152         MLX5_ASSERT(cache_resource->action);
12153         return mlx5_hlist_unregister(priv->sh->encaps_decaps,
12154                                      &cache_resource->entry);
12155 }
12156
12157 /**
12158  * Release an jump to table action resource.
12159  *
12160  * @param dev
12161  *   Pointer to Ethernet device.
12162  * @param rix_jump
12163  *   Index to the jump action resource.
12164  *
12165  * @return
12166  *   1 while a reference on it exists, 0 when freed.
12167  */
12168 static int
12169 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
12170                                   uint32_t rix_jump)
12171 {
12172         struct mlx5_priv *priv = dev->data->dev_private;
12173         struct mlx5_flow_tbl_data_entry *tbl_data;
12174
12175         tbl_data = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_JUMP],
12176                                   rix_jump);
12177         if (!tbl_data)
12178                 return 0;
12179         return flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl_data->tbl);
12180 }
12181
12182 void
12183 flow_dv_modify_remove_cb(struct mlx5_hlist *list __rte_unused,
12184                          struct mlx5_hlist_entry *entry)
12185 {
12186         struct mlx5_flow_dv_modify_hdr_resource *res =
12187                 container_of(entry, typeof(*res), entry);
12188
12189         claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
12190         mlx5_free(entry);
12191 }
12192
12193 /**
12194  * Release a modify-header resource.
12195  *
12196  * @param dev
12197  *   Pointer to Ethernet device.
12198  * @param handle
12199  *   Pointer to mlx5_flow_handle.
12200  *
12201  * @return
12202  *   1 while a reference on it exists, 0 when freed.
12203  */
12204 static int
12205 flow_dv_modify_hdr_resource_release(struct rte_eth_dev *dev,
12206                                     struct mlx5_flow_handle *handle)
12207 {
12208         struct mlx5_priv *priv = dev->data->dev_private;
12209         struct mlx5_flow_dv_modify_hdr_resource *entry = handle->dvh.modify_hdr;
12210
12211         MLX5_ASSERT(entry->action);
12212         return mlx5_hlist_unregister(priv->sh->modify_cmds, &entry->entry);
12213 }
12214
12215 void
12216 flow_dv_port_id_remove_cb(struct mlx5_cache_list *list,
12217                           struct mlx5_cache_entry *entry)
12218 {
12219         struct mlx5_dev_ctx_shared *sh = list->ctx;
12220         struct mlx5_flow_dv_port_id_action_resource *cache =
12221                         container_of(entry, typeof(*cache), entry);
12222
12223         claim_zero(mlx5_flow_os_destroy_flow_action(cache->action));
12224         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], cache->idx);
12225 }
12226
12227 /**
12228  * Release port ID action resource.
12229  *
12230  * @param dev
12231  *   Pointer to Ethernet device.
12232  * @param handle
12233  *   Pointer to mlx5_flow_handle.
12234  *
12235  * @return
12236  *   1 while a reference on it exists, 0 when freed.
12237  */
12238 static int
12239 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
12240                                         uint32_t port_id)
12241 {
12242         struct mlx5_priv *priv = dev->data->dev_private;
12243         struct mlx5_flow_dv_port_id_action_resource *cache;
12244
12245         cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID], port_id);
12246         if (!cache)
12247                 return 0;
12248         MLX5_ASSERT(cache->action);
12249         return mlx5_cache_unregister(&priv->sh->port_id_action_list,
12250                                      &cache->entry);
12251 }
12252
12253 /**
12254  * Release shared RSS action resource.
12255  *
12256  * @param dev
12257  *   Pointer to Ethernet device.
12258  * @param srss
12259  *   Shared RSS action index.
12260  */
12261 static void
12262 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss)
12263 {
12264         struct mlx5_priv *priv = dev->data->dev_private;
12265         struct mlx5_shared_action_rss *shared_rss;
12266
12267         shared_rss = mlx5_ipool_get
12268                         (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], srss);
12269         __atomic_sub_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
12270 }
12271
12272 void
12273 flow_dv_push_vlan_remove_cb(struct mlx5_cache_list *list,
12274                             struct mlx5_cache_entry *entry)
12275 {
12276         struct mlx5_dev_ctx_shared *sh = list->ctx;
12277         struct mlx5_flow_dv_push_vlan_action_resource *cache =
12278                         container_of(entry, typeof(*cache), entry);
12279
12280         claim_zero(mlx5_flow_os_destroy_flow_action(cache->action));
12281         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], cache->idx);
12282 }
12283
12284 /**
12285  * Release push vlan action resource.
12286  *
12287  * @param dev
12288  *   Pointer to Ethernet device.
12289  * @param handle
12290  *   Pointer to mlx5_flow_handle.
12291  *
12292  * @return
12293  *   1 while a reference on it exists, 0 when freed.
12294  */
12295 static int
12296 flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,
12297                                           struct mlx5_flow_handle *handle)
12298 {
12299         struct mlx5_priv *priv = dev->data->dev_private;
12300         struct mlx5_flow_dv_push_vlan_action_resource *cache;
12301         uint32_t idx = handle->dvh.rix_push_vlan;
12302
12303         cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
12304         if (!cache)
12305                 return 0;
12306         MLX5_ASSERT(cache->action);
12307         return mlx5_cache_unregister(&priv->sh->push_vlan_action_list,
12308                                      &cache->entry);
12309 }
12310
12311 /**
12312  * Release the fate resource.
12313  *
12314  * @param dev
12315  *   Pointer to Ethernet device.
12316  * @param handle
12317  *   Pointer to mlx5_flow_handle.
12318  */
12319 static void
12320 flow_dv_fate_resource_release(struct rte_eth_dev *dev,
12321                                struct mlx5_flow_handle *handle)
12322 {
12323         if (!handle->rix_fate)
12324                 return;
12325         switch (handle->fate_action) {
12326         case MLX5_FLOW_FATE_QUEUE:
12327                 mlx5_hrxq_release(dev, handle->rix_hrxq);
12328                 break;
12329         case MLX5_FLOW_FATE_JUMP:
12330                 flow_dv_jump_tbl_resource_release(dev, handle->rix_jump);
12331                 break;
12332         case MLX5_FLOW_FATE_PORT_ID:
12333                 flow_dv_port_id_action_resource_release(dev,
12334                                 handle->rix_port_id_action);
12335                 break;
12336         default:
12337                 DRV_LOG(DEBUG, "Incorrect fate action:%d", handle->fate_action);
12338                 break;
12339         }
12340         handle->rix_fate = 0;
12341 }
12342
12343 void
12344 flow_dv_sample_remove_cb(struct mlx5_cache_list *list __rte_unused,
12345                          struct mlx5_cache_entry *entry)
12346 {
12347         struct mlx5_flow_dv_sample_resource *cache_resource =
12348                         container_of(entry, typeof(*cache_resource), entry);
12349         struct rte_eth_dev *dev = cache_resource->dev;
12350         struct mlx5_priv *priv = dev->data->dev_private;
12351
12352         if (cache_resource->verbs_action)
12353                 claim_zero(mlx5_flow_os_destroy_flow_action
12354                                 (cache_resource->verbs_action));
12355         if (cache_resource->normal_path_tbl)
12356                 flow_dv_tbl_resource_release(MLX5_SH(dev),
12357                         cache_resource->normal_path_tbl);
12358         flow_dv_sample_sub_actions_release(dev,
12359                                 &cache_resource->sample_idx);
12360         mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
12361                         cache_resource->idx);
12362         DRV_LOG(DEBUG, "sample resource %p: removed",
12363                 (void *)cache_resource);
12364 }
12365
12366 /**
12367  * Release an sample resource.
12368  *
12369  * @param dev
12370  *   Pointer to Ethernet device.
12371  * @param handle
12372  *   Pointer to mlx5_flow_handle.
12373  *
12374  * @return
12375  *   1 while a reference on it exists, 0 when freed.
12376  */
12377 static int
12378 flow_dv_sample_resource_release(struct rte_eth_dev *dev,
12379                                      struct mlx5_flow_handle *handle)
12380 {
12381         struct mlx5_priv *priv = dev->data->dev_private;
12382         struct mlx5_flow_dv_sample_resource *cache_resource;
12383
12384         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
12385                          handle->dvh.rix_sample);
12386         if (!cache_resource)
12387                 return 0;
12388         MLX5_ASSERT(cache_resource->verbs_action);
12389         return mlx5_cache_unregister(&priv->sh->sample_action_list,
12390                                      &cache_resource->entry);
12391 }
12392
12393 void
12394 flow_dv_dest_array_remove_cb(struct mlx5_cache_list *list __rte_unused,
12395                              struct mlx5_cache_entry *entry)
12396 {
12397         struct mlx5_flow_dv_dest_array_resource *cache_resource =
12398                         container_of(entry, typeof(*cache_resource), entry);
12399         struct rte_eth_dev *dev = cache_resource->dev;
12400         struct mlx5_priv *priv = dev->data->dev_private;
12401         uint32_t i = 0;
12402
12403         MLX5_ASSERT(cache_resource->action);
12404         if (cache_resource->action)
12405                 claim_zero(mlx5_flow_os_destroy_flow_action
12406                                         (cache_resource->action));
12407         for (; i < cache_resource->num_of_dest; i++)
12408                 flow_dv_sample_sub_actions_release(dev,
12409                                 &cache_resource->sample_idx[i]);
12410         mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
12411                         cache_resource->idx);
12412         DRV_LOG(DEBUG, "destination array resource %p: removed",
12413                 (void *)cache_resource);
12414 }
12415
12416 /**
12417  * Release an destination array resource.
12418  *
12419  * @param dev
12420  *   Pointer to Ethernet device.
12421  * @param handle
12422  *   Pointer to mlx5_flow_handle.
12423  *
12424  * @return
12425  *   1 while a reference on it exists, 0 when freed.
12426  */
12427 static int
12428 flow_dv_dest_array_resource_release(struct rte_eth_dev *dev,
12429                                     struct mlx5_flow_handle *handle)
12430 {
12431         struct mlx5_priv *priv = dev->data->dev_private;
12432         struct mlx5_flow_dv_dest_array_resource *cache;
12433
12434         cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
12435                                handle->dvh.rix_dest_array);
12436         if (!cache)
12437                 return 0;
12438         MLX5_ASSERT(cache->action);
12439         return mlx5_cache_unregister(&priv->sh->dest_array_list,
12440                                      &cache->entry);
12441 }
12442
12443 static void
12444 flow_dv_geneve_tlv_option_resource_release(struct rte_eth_dev *dev)
12445 {
12446         struct mlx5_priv *priv = dev->data->dev_private;
12447         struct mlx5_dev_ctx_shared *sh = priv->sh;
12448         struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
12449                                 sh->geneve_tlv_option_resource;
12450         rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
12451         if (geneve_opt_resource) {
12452                 if (!(__atomic_sub_fetch(&geneve_opt_resource->refcnt, 1,
12453                                          __ATOMIC_RELAXED))) {
12454                         claim_zero(mlx5_devx_cmd_destroy
12455                                         (geneve_opt_resource->obj));
12456                         mlx5_free(sh->geneve_tlv_option_resource);
12457                         sh->geneve_tlv_option_resource = NULL;
12458                 }
12459         }
12460         rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
12461 }
12462
12463 /**
12464  * Remove the flow from the NIC but keeps it in memory.
12465  * Lock free, (mutex should be acquired by caller).
12466  *
12467  * @param[in] dev
12468  *   Pointer to Ethernet device.
12469  * @param[in, out] flow
12470  *   Pointer to flow structure.
12471  */
12472 static void
12473 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
12474 {
12475         struct mlx5_flow_handle *dh;
12476         uint32_t handle_idx;
12477         struct mlx5_priv *priv = dev->data->dev_private;
12478
12479         if (!flow)
12480                 return;
12481         handle_idx = flow->dev_handles;
12482         while (handle_idx) {
12483                 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
12484                                     handle_idx);
12485                 if (!dh)
12486                         return;
12487                 if (dh->drv_flow) {
12488                         claim_zero(mlx5_flow_os_destroy_flow(dh->drv_flow));
12489                         dh->drv_flow = NULL;
12490                 }
12491                 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE)
12492                         flow_dv_fate_resource_release(dev, dh);
12493                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
12494                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
12495                 handle_idx = dh->next.next;
12496         }
12497 }
12498
12499 /**
12500  * Remove the flow from the NIC and the memory.
12501  * Lock free, (mutex should be acquired by caller).
12502  *
12503  * @param[in] dev
12504  *   Pointer to the Ethernet device structure.
12505  * @param[in, out] flow
12506  *   Pointer to flow structure.
12507  */
12508 static void
12509 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
12510 {
12511         struct mlx5_flow_handle *dev_handle;
12512         struct mlx5_priv *priv = dev->data->dev_private;
12513         uint32_t srss = 0;
12514
12515         if (!flow)
12516                 return;
12517         flow_dv_remove(dev, flow);
12518         if (flow->counter) {
12519                 flow_dv_counter_free(dev, flow->counter);
12520                 flow->counter = 0;
12521         }
12522         if (flow->meter) {
12523                 struct mlx5_flow_meter *fm;
12524
12525                 fm = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MTR],
12526                                     flow->meter);
12527                 if (fm)
12528                         mlx5_flow_meter_detach(fm);
12529                 flow->meter = 0;
12530         }
12531         if (flow->age)
12532                 flow_dv_aso_age_release(dev, flow->age);
12533         if (flow->geneve_tlv_option) {
12534                 flow_dv_geneve_tlv_option_resource_release(dev);
12535                 flow->geneve_tlv_option = 0;
12536         }
12537         while (flow->dev_handles) {
12538                 uint32_t tmp_idx = flow->dev_handles;
12539
12540                 dev_handle = mlx5_ipool_get(priv->sh->ipool
12541                                             [MLX5_IPOOL_MLX5_FLOW], tmp_idx);
12542                 if (!dev_handle)
12543                         return;
12544                 flow->dev_handles = dev_handle->next.next;
12545                 if (dev_handle->dvh.matcher)
12546                         flow_dv_matcher_release(dev, dev_handle);
12547                 if (dev_handle->dvh.rix_sample)
12548                         flow_dv_sample_resource_release(dev, dev_handle);
12549                 if (dev_handle->dvh.rix_dest_array)
12550                         flow_dv_dest_array_resource_release(dev, dev_handle);
12551                 if (dev_handle->dvh.rix_encap_decap)
12552                         flow_dv_encap_decap_resource_release(dev,
12553                                 dev_handle->dvh.rix_encap_decap);
12554                 if (dev_handle->dvh.modify_hdr)
12555                         flow_dv_modify_hdr_resource_release(dev, dev_handle);
12556                 if (dev_handle->dvh.rix_push_vlan)
12557                         flow_dv_push_vlan_action_resource_release(dev,
12558                                                                   dev_handle);
12559                 if (dev_handle->dvh.rix_tag)
12560                         flow_dv_tag_release(dev,
12561                                             dev_handle->dvh.rix_tag);
12562                 if (dev_handle->fate_action != MLX5_FLOW_FATE_SHARED_RSS)
12563                         flow_dv_fate_resource_release(dev, dev_handle);
12564                 else if (!srss)
12565                         srss = dev_handle->rix_srss;
12566                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
12567                            tmp_idx);
12568         }
12569         if (srss)
12570                 flow_dv_shared_rss_action_release(dev, srss);
12571 }
12572
12573 /**
12574  * Release array of hash RX queue objects.
12575  * Helper function.
12576  *
12577  * @param[in] dev
12578  *   Pointer to the Ethernet device structure.
12579  * @param[in, out] hrxqs
12580  *   Array of hash RX queue objects.
12581  *
12582  * @return
12583  *   Total number of references to hash RX queue objects in *hrxqs* array
12584  *   after this operation.
12585  */
12586 static int
12587 __flow_dv_hrxqs_release(struct rte_eth_dev *dev,
12588                         uint32_t (*hrxqs)[MLX5_RSS_HASH_FIELDS_LEN])
12589 {
12590         size_t i;
12591         int remaining = 0;
12592
12593         for (i = 0; i < RTE_DIM(*hrxqs); i++) {
12594                 int ret = mlx5_hrxq_release(dev, (*hrxqs)[i]);
12595
12596                 if (!ret)
12597                         (*hrxqs)[i] = 0;
12598                 remaining += ret;
12599         }
12600         return remaining;
12601 }
12602
12603 /**
12604  * Release all hash RX queue objects representing shared RSS action.
12605  *
12606  * @param[in] dev
12607  *   Pointer to the Ethernet device structure.
12608  * @param[in, out] action
12609  *   Shared RSS action to remove hash RX queue objects from.
12610  *
12611  * @return
12612  *   Total number of references to hash RX queue objects stored in *action*
12613  *   after this operation.
12614  *   Expected to be 0 if no external references held.
12615  */
12616 static int
12617 __flow_dv_action_rss_hrxqs_release(struct rte_eth_dev *dev,
12618                                  struct mlx5_shared_action_rss *shared_rss)
12619 {
12620         return __flow_dv_hrxqs_release(dev, &shared_rss->hrxq) +
12621                 __flow_dv_hrxqs_release(dev, &shared_rss->hrxq_tunnel);
12622 }
12623
12624 /**
12625  * Setup shared RSS action.
12626  * Prepare set of hash RX queue objects sufficient to handle all valid
12627  * hash_fields combinations (see enum ibv_rx_hash_fields).
12628  *
12629  * @param[in] dev
12630  *   Pointer to the Ethernet device structure.
12631  * @param[in] action_idx
12632  *   Shared RSS action ipool index.
12633  * @param[in, out] action
12634  *   Partially initialized shared RSS action.
12635  * @param[out] error
12636  *   Perform verbose error reporting if not NULL. Initialized in case of
12637  *   error only.
12638  *
12639  * @return
12640  *   0 on success, otherwise negative errno value.
12641  */
12642 static int
12643 __flow_dv_action_rss_setup(struct rte_eth_dev *dev,
12644                            uint32_t action_idx,
12645                            struct mlx5_shared_action_rss *shared_rss,
12646                            struct rte_flow_error *error)
12647 {
12648         struct mlx5_flow_rss_desc rss_desc = { 0 };
12649         size_t i;
12650         int err;
12651
12652         if (mlx5_ind_table_obj_setup(dev, shared_rss->ind_tbl)) {
12653                 return rte_flow_error_set(error, rte_errno,
12654                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12655                                           "cannot setup indirection table");
12656         }
12657         memcpy(rss_desc.key, shared_rss->origin.key, MLX5_RSS_HASH_KEY_LEN);
12658         rss_desc.key_len = MLX5_RSS_HASH_KEY_LEN;
12659         rss_desc.const_q = shared_rss->origin.queue;
12660         rss_desc.queue_num = shared_rss->origin.queue_num;
12661         /* Set non-zero value to indicate a shared RSS. */
12662         rss_desc.shared_rss = action_idx;
12663         rss_desc.ind_tbl = shared_rss->ind_tbl;
12664         for (i = 0; i < MLX5_RSS_HASH_FIELDS_LEN; i++) {
12665                 uint32_t hrxq_idx;
12666                 uint64_t hash_fields = mlx5_rss_hash_fields[i];
12667                 int tunnel;
12668
12669                 for (tunnel = 0; tunnel < 2; tunnel++) {
12670                         rss_desc.tunnel = tunnel;
12671                         rss_desc.hash_fields = hash_fields;
12672                         hrxq_idx = mlx5_hrxq_get(dev, &rss_desc);
12673                         if (!hrxq_idx) {
12674                                 rte_flow_error_set
12675                                         (error, rte_errno,
12676                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12677                                          "cannot get hash queue");
12678                                 goto error_hrxq_new;
12679                         }
12680                         err = __flow_dv_action_rss_hrxq_set
12681                                 (shared_rss, hash_fields, tunnel, hrxq_idx);
12682                         MLX5_ASSERT(!err);
12683                 }
12684         }
12685         return 0;
12686 error_hrxq_new:
12687         err = rte_errno;
12688         __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
12689         if (!mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl, true))
12690                 shared_rss->ind_tbl = NULL;
12691         rte_errno = err;
12692         return -rte_errno;
12693 }
12694
12695 /**
12696  * Create shared RSS action.
12697  *
12698  * @param[in] dev
12699  *   Pointer to the Ethernet device structure.
12700  * @param[in] conf
12701  *   Shared action configuration.
12702  * @param[in] rss
12703  *   RSS action specification used to create shared action.
12704  * @param[out] error
12705  *   Perform verbose error reporting if not NULL. Initialized in case of
12706  *   error only.
12707  *
12708  * @return
12709  *   A valid shared action ID in case of success, 0 otherwise and
12710  *   rte_errno is set.
12711  */
12712 static uint32_t
12713 __flow_dv_action_rss_create(struct rte_eth_dev *dev,
12714                             const struct rte_flow_shared_action_conf *conf,
12715                             const struct rte_flow_action_rss *rss,
12716                             struct rte_flow_error *error)
12717 {
12718         struct mlx5_priv *priv = dev->data->dev_private;
12719         struct mlx5_shared_action_rss *shared_rss = NULL;
12720         void *queue = NULL;
12721         struct rte_flow_action_rss *origin;
12722         const uint8_t *rss_key;
12723         uint32_t queue_size = rss->queue_num * sizeof(uint16_t);
12724         uint32_t idx;
12725
12726         RTE_SET_USED(conf);
12727         queue = mlx5_malloc(0, RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
12728                             0, SOCKET_ID_ANY);
12729         shared_rss = mlx5_ipool_zmalloc
12730                          (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], &idx);
12731         if (!shared_rss || !queue) {
12732                 rte_flow_error_set(error, ENOMEM,
12733                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12734                                    "cannot allocate resource memory");
12735                 goto error_rss_init;
12736         }
12737         if (idx > (1u << MLX5_SHARED_ACTION_TYPE_OFFSET)) {
12738                 rte_flow_error_set(error, E2BIG,
12739                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12740                                    "rss action number out of range");
12741                 goto error_rss_init;
12742         }
12743         shared_rss->ind_tbl = mlx5_malloc(MLX5_MEM_ZERO,
12744                                           sizeof(*shared_rss->ind_tbl),
12745                                           0, SOCKET_ID_ANY);
12746         if (!shared_rss->ind_tbl) {
12747                 rte_flow_error_set(error, ENOMEM,
12748                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12749                                    "cannot allocate resource memory");
12750                 goto error_rss_init;
12751         }
12752         memcpy(queue, rss->queue, queue_size);
12753         shared_rss->ind_tbl->queues = queue;
12754         shared_rss->ind_tbl->queues_n = rss->queue_num;
12755         origin = &shared_rss->origin;
12756         origin->func = rss->func;
12757         origin->level = rss->level;
12758         /* RSS type 0 indicates default RSS type (ETH_RSS_IP). */
12759         origin->types = !rss->types ? ETH_RSS_IP : rss->types;
12760         /* NULL RSS key indicates default RSS key. */
12761         rss_key = !rss->key ? rss_hash_default_key : rss->key;
12762         memcpy(shared_rss->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
12763         origin->key = &shared_rss->key[0];
12764         origin->key_len = MLX5_RSS_HASH_KEY_LEN;
12765         origin->queue = queue;
12766         origin->queue_num = rss->queue_num;
12767         if (__flow_dv_action_rss_setup(dev, idx, shared_rss, error))
12768                 goto error_rss_init;
12769         rte_spinlock_init(&shared_rss->action_rss_sl);
12770         __atomic_add_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
12771         rte_spinlock_lock(&priv->shared_act_sl);
12772         ILIST_INSERT(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
12773                      &priv->rss_shared_actions, idx, shared_rss, next);
12774         rte_spinlock_unlock(&priv->shared_act_sl);
12775         return idx;
12776 error_rss_init:
12777         if (shared_rss) {
12778                 if (shared_rss->ind_tbl)
12779                         mlx5_free(shared_rss->ind_tbl);
12780                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
12781                                 idx);
12782         }
12783         if (queue)
12784                 mlx5_free(queue);
12785         return 0;
12786 }
12787
12788 /**
12789  * Destroy the shared RSS action.
12790  * Release related hash RX queue objects.
12791  *
12792  * @param[in] dev
12793  *   Pointer to the Ethernet device structure.
12794  * @param[in] idx
12795  *   The shared RSS action object ID to be removed.
12796  * @param[out] error
12797  *   Perform verbose error reporting if not NULL. Initialized in case of
12798  *   error only.
12799  *
12800  * @return
12801  *   0 on success, otherwise negative errno value.
12802  */
12803 static int
12804 __flow_dv_action_rss_release(struct rte_eth_dev *dev, uint32_t idx,
12805                              struct rte_flow_error *error)
12806 {
12807         struct mlx5_priv *priv = dev->data->dev_private;
12808         struct mlx5_shared_action_rss *shared_rss =
12809             mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
12810         uint32_t old_refcnt = 1;
12811         int remaining;
12812         uint16_t *queue = NULL;
12813
12814         if (!shared_rss)
12815                 return rte_flow_error_set(error, EINVAL,
12816                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12817                                           "invalid shared action");
12818         remaining = __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
12819         if (remaining)
12820                 return rte_flow_error_set(error, EBUSY,
12821                                           RTE_FLOW_ERROR_TYPE_ACTION,
12822                                           NULL,
12823                                           "shared rss hrxq has references");
12824         if (!__atomic_compare_exchange_n(&shared_rss->refcnt, &old_refcnt,
12825                                          0, 0, __ATOMIC_ACQUIRE,
12826                                          __ATOMIC_RELAXED))
12827                 return rte_flow_error_set(error, EBUSY,
12828                                           RTE_FLOW_ERROR_TYPE_ACTION,
12829                                           NULL,
12830                                           "shared rss has references");
12831         queue = shared_rss->ind_tbl->queues;
12832         remaining = mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl, true);
12833         if (remaining)
12834                 return rte_flow_error_set(error, EBUSY,
12835                                           RTE_FLOW_ERROR_TYPE_ACTION,
12836                                           NULL,
12837                                           "shared rss indirection table has"
12838                                           " references");
12839         mlx5_free(queue);
12840         rte_spinlock_lock(&priv->shared_act_sl);
12841         ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
12842                      &priv->rss_shared_actions, idx, shared_rss, next);
12843         rte_spinlock_unlock(&priv->shared_act_sl);
12844         mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
12845                         idx);
12846         return 0;
12847 }
12848
12849 /**
12850  * Create shared action, lock free,
12851  * (mutex should be acquired by caller).
12852  * Dispatcher for action type specific call.
12853  *
12854  * @param[in] dev
12855  *   Pointer to the Ethernet device structure.
12856  * @param[in] conf
12857  *   Shared action configuration.
12858  * @param[in] action
12859  *   Action specification used to create shared action.
12860  * @param[out] error
12861  *   Perform verbose error reporting if not NULL. Initialized in case of
12862  *   error only.
12863  *
12864  * @return
12865  *   A valid shared action handle in case of success, NULL otherwise and
12866  *   rte_errno is set.
12867  */
12868 static struct rte_flow_shared_action *
12869 flow_dv_action_create(struct rte_eth_dev *dev,
12870                       const struct rte_flow_shared_action_conf *conf,
12871                       const struct rte_flow_action *action,
12872                       struct rte_flow_error *err)
12873 {
12874         uint32_t idx = 0;
12875         uint32_t ret = 0;
12876
12877         switch (action->type) {
12878         case RTE_FLOW_ACTION_TYPE_RSS:
12879                 ret = __flow_dv_action_rss_create(dev, conf, action->conf, err);
12880                 idx = (MLX5_SHARED_ACTION_TYPE_RSS <<
12881                        MLX5_SHARED_ACTION_TYPE_OFFSET) | ret;
12882                 break;
12883         case RTE_FLOW_ACTION_TYPE_AGE:
12884                 ret = flow_dv_translate_create_aso_age(dev, action->conf, err);
12885                 idx = (MLX5_SHARED_ACTION_TYPE_AGE <<
12886                        MLX5_SHARED_ACTION_TYPE_OFFSET) | ret;
12887                 if (ret) {
12888                         struct mlx5_aso_age_action *aso_age =
12889                                               flow_aso_age_get_by_idx(dev, ret);
12890
12891                         if (!aso_age->age_params.context)
12892                                 aso_age->age_params.context =
12893                                                          (void *)(uintptr_t)idx;
12894                 }
12895                 break;
12896         default:
12897                 rte_flow_error_set(err, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION,
12898                                    NULL, "action type not supported");
12899                 break;
12900         }
12901         return ret ? (struct rte_flow_shared_action *)(uintptr_t)idx : NULL;
12902 }
12903
12904 /**
12905  * Destroy the shared action.
12906  * Release action related resources on the NIC and the memory.
12907  * Lock free, (mutex should be acquired by caller).
12908  * Dispatcher for action type specific call.
12909  *
12910  * @param[in] dev
12911  *   Pointer to the Ethernet device structure.
12912  * @param[in] action
12913  *   The shared action object to be removed.
12914  * @param[out] error
12915  *   Perform verbose error reporting if not NULL. Initialized in case of
12916  *   error only.
12917  *
12918  * @return
12919  *   0 on success, otherwise negative errno value.
12920  */
12921 static int
12922 flow_dv_action_destroy(struct rte_eth_dev *dev,
12923                        struct rte_flow_shared_action *action,
12924                        struct rte_flow_error *error)
12925 {
12926         uint32_t act_idx = (uint32_t)(uintptr_t)action;
12927         uint32_t type = act_idx >> MLX5_SHARED_ACTION_TYPE_OFFSET;
12928         uint32_t idx = act_idx & ((1u << MLX5_SHARED_ACTION_TYPE_OFFSET) - 1);
12929         int ret;
12930
12931         switch (type) {
12932         case MLX5_SHARED_ACTION_TYPE_RSS:
12933                 return __flow_dv_action_rss_release(dev, idx, error);
12934         case MLX5_SHARED_ACTION_TYPE_AGE:
12935                 ret = flow_dv_aso_age_release(dev, idx);
12936                 if (ret)
12937                         /*
12938                          * In this case, the last flow has a reference will
12939                          * actually release the age action.
12940                          */
12941                         DRV_LOG(DEBUG, "Shared age action %" PRIu32 " was"
12942                                 " released with references %d.", idx, ret);
12943                 return 0;
12944         default:
12945                 return rte_flow_error_set(error, ENOTSUP,
12946                                           RTE_FLOW_ERROR_TYPE_ACTION,
12947                                           NULL,
12948                                           "action type not supported");
12949         }
12950 }
12951
12952 /**
12953  * Updates in place shared RSS action configuration.
12954  *
12955  * @param[in] dev
12956  *   Pointer to the Ethernet device structure.
12957  * @param[in] idx
12958  *   The shared RSS action object ID to be updated.
12959  * @param[in] action_conf
12960  *   RSS action specification used to modify *shared_rss*.
12961  * @param[out] error
12962  *   Perform verbose error reporting if not NULL. Initialized in case of
12963  *   error only.
12964  *
12965  * @return
12966  *   0 on success, otherwise negative errno value.
12967  * @note: currently only support update of RSS queues.
12968  */
12969 static int
12970 __flow_dv_action_rss_update(struct rte_eth_dev *dev, uint32_t idx,
12971                             const struct rte_flow_action_rss *action_conf,
12972                             struct rte_flow_error *error)
12973 {
12974         struct mlx5_priv *priv = dev->data->dev_private;
12975         struct mlx5_shared_action_rss *shared_rss =
12976             mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
12977         int ret = 0;
12978         void *queue = NULL;
12979         uint16_t *queue_old = NULL;
12980         uint32_t queue_size = action_conf->queue_num * sizeof(uint16_t);
12981
12982         if (!shared_rss)
12983                 return rte_flow_error_set(error, EINVAL,
12984                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12985                                           "invalid shared action to update");
12986         if (priv->obj_ops.ind_table_modify == NULL)
12987                 return rte_flow_error_set(error, ENOTSUP,
12988                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12989                                           "cannot modify indirection table");
12990         queue = mlx5_malloc(MLX5_MEM_ZERO,
12991                             RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
12992                             0, SOCKET_ID_ANY);
12993         if (!queue)
12994                 return rte_flow_error_set(error, ENOMEM,
12995                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12996                                           NULL,
12997                                           "cannot allocate resource memory");
12998         memcpy(queue, action_conf->queue, queue_size);
12999         MLX5_ASSERT(shared_rss->ind_tbl);
13000         rte_spinlock_lock(&shared_rss->action_rss_sl);
13001         queue_old = shared_rss->ind_tbl->queues;
13002         ret = mlx5_ind_table_obj_modify(dev, shared_rss->ind_tbl,
13003                                         queue, action_conf->queue_num, true);
13004         if (ret) {
13005                 mlx5_free(queue);
13006                 ret = rte_flow_error_set(error, rte_errno,
13007                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
13008                                           "cannot update indirection table");
13009         } else {
13010                 mlx5_free(queue_old);
13011                 shared_rss->origin.queue = queue;
13012                 shared_rss->origin.queue_num = action_conf->queue_num;
13013         }
13014         rte_spinlock_unlock(&shared_rss->action_rss_sl);
13015         return ret;
13016 }
13017
13018 /**
13019  * Updates in place shared action configuration, lock free,
13020  * (mutex should be acquired by caller).
13021  *
13022  * @param[in] dev
13023  *   Pointer to the Ethernet device structure.
13024  * @param[in] action
13025  *   The shared action object to be updated.
13026  * @param[in] action_conf
13027  *   Action specification used to modify *action*.
13028  *   *action_conf* should be of type correlating with type of the *action*,
13029  *   otherwise considered as invalid.
13030  * @param[out] error
13031  *   Perform verbose error reporting if not NULL. Initialized in case of
13032  *   error only.
13033  *
13034  * @return
13035  *   0 on success, otherwise negative errno value.
13036  */
13037 static int
13038 flow_dv_action_update(struct rte_eth_dev *dev,
13039                         struct rte_flow_shared_action *action,
13040                         const void *action_conf,
13041                         struct rte_flow_error *err)
13042 {
13043         uint32_t act_idx = (uint32_t)(uintptr_t)action;
13044         uint32_t type = act_idx >> MLX5_SHARED_ACTION_TYPE_OFFSET;
13045         uint32_t idx = act_idx & ((1u << MLX5_SHARED_ACTION_TYPE_OFFSET) - 1);
13046
13047         switch (type) {
13048         case MLX5_SHARED_ACTION_TYPE_RSS:
13049                 return __flow_dv_action_rss_update(dev, idx, action_conf, err);
13050         default:
13051                 return rte_flow_error_set(err, ENOTSUP,
13052                                           RTE_FLOW_ERROR_TYPE_ACTION,
13053                                           NULL,
13054                                           "action type update not supported");
13055         }
13056 }
13057
13058 static int
13059 flow_dv_action_query(struct rte_eth_dev *dev,
13060                      const struct rte_flow_shared_action *action, void *data,
13061                      struct rte_flow_error *error)
13062 {
13063         struct mlx5_age_param *age_param;
13064         struct rte_flow_query_age *resp;
13065         uint32_t act_idx = (uint32_t)(uintptr_t)action;
13066         uint32_t type = act_idx >> MLX5_SHARED_ACTION_TYPE_OFFSET;
13067         uint32_t idx = act_idx & ((1u << MLX5_SHARED_ACTION_TYPE_OFFSET) - 1);
13068
13069         switch (type) {
13070         case MLX5_SHARED_ACTION_TYPE_AGE:
13071                 age_param = &flow_aso_age_get_by_idx(dev, idx)->age_params;
13072                 resp = data;
13073                 resp->aged = __atomic_load_n(&age_param->state,
13074                                               __ATOMIC_RELAXED) == AGE_TMOUT ?
13075                                                                           1 : 0;
13076                 resp->sec_since_last_hit_valid = !resp->aged;
13077                 if (resp->sec_since_last_hit_valid)
13078                         resp->sec_since_last_hit = __atomic_load_n
13079                              (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
13080                 return 0;
13081         default:
13082                 return rte_flow_error_set(error, ENOTSUP,
13083                                           RTE_FLOW_ERROR_TYPE_ACTION,
13084                                           NULL,
13085                                           "action type query not supported");
13086         }
13087 }
13088
13089 /**
13090  * Query a dv flow  rule for its statistics via devx.
13091  *
13092  * @param[in] dev
13093  *   Pointer to Ethernet device.
13094  * @param[in] flow
13095  *   Pointer to the sub flow.
13096  * @param[out] data
13097  *   data retrieved by the query.
13098  * @param[out] error
13099  *   Perform verbose error reporting if not NULL.
13100  *
13101  * @return
13102  *   0 on success, a negative errno value otherwise and rte_errno is set.
13103  */
13104 static int
13105 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
13106                     void *data, struct rte_flow_error *error)
13107 {
13108         struct mlx5_priv *priv = dev->data->dev_private;
13109         struct rte_flow_query_count *qc = data;
13110
13111         if (!priv->config.devx)
13112                 return rte_flow_error_set(error, ENOTSUP,
13113                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13114                                           NULL,
13115                                           "counters are not supported");
13116         if (flow->counter) {
13117                 uint64_t pkts, bytes;
13118                 struct mlx5_flow_counter *cnt;
13119
13120                 cnt = flow_dv_counter_get_by_idx(dev, flow->counter,
13121                                                  NULL);
13122                 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
13123                                                &bytes);
13124
13125                 if (err)
13126                         return rte_flow_error_set(error, -err,
13127                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13128                                         NULL, "cannot read counters");
13129                 qc->hits_set = 1;
13130                 qc->bytes_set = 1;
13131                 qc->hits = pkts - cnt->hits;
13132                 qc->bytes = bytes - cnt->bytes;
13133                 if (qc->reset) {
13134                         cnt->hits = pkts;
13135                         cnt->bytes = bytes;
13136                 }
13137                 return 0;
13138         }
13139         return rte_flow_error_set(error, EINVAL,
13140                                   RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13141                                   NULL,
13142                                   "counters are not available");
13143 }
13144
13145 /**
13146  * Query a flow rule AGE action for aging information.
13147  *
13148  * @param[in] dev
13149  *   Pointer to Ethernet device.
13150  * @param[in] flow
13151  *   Pointer to the sub flow.
13152  * @param[out] data
13153  *   data retrieved by the query.
13154  * @param[out] error
13155  *   Perform verbose error reporting if not NULL.
13156  *
13157  * @return
13158  *   0 on success, a negative errno value otherwise and rte_errno is set.
13159  */
13160 static int
13161 flow_dv_query_age(struct rte_eth_dev *dev, struct rte_flow *flow,
13162                   void *data, struct rte_flow_error *error)
13163 {
13164         struct rte_flow_query_age *resp = data;
13165         struct mlx5_age_param *age_param;
13166
13167         if (flow->age) {
13168                 struct mlx5_aso_age_action *act =
13169                                      flow_aso_age_get_by_idx(dev, flow->age);
13170
13171                 age_param = &act->age_params;
13172         } else if (flow->counter) {
13173                 age_param = flow_dv_counter_idx_get_age(dev, flow->counter);
13174
13175                 if (!age_param || !age_param->timeout)
13176                         return rte_flow_error_set
13177                                         (error, EINVAL,
13178                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13179                                          NULL, "cannot read age data");
13180         } else {
13181                 return rte_flow_error_set(error, EINVAL,
13182                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13183                                           NULL, "age data not available");
13184         }
13185         resp->aged = __atomic_load_n(&age_param->state, __ATOMIC_RELAXED) ==
13186                                      AGE_TMOUT ? 1 : 0;
13187         resp->sec_since_last_hit_valid = !resp->aged;
13188         if (resp->sec_since_last_hit_valid)
13189                 resp->sec_since_last_hit = __atomic_load_n
13190                              (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
13191         return 0;
13192 }
13193
13194 /**
13195  * Query a flow.
13196  *
13197  * @see rte_flow_query()
13198  * @see rte_flow_ops
13199  */
13200 static int
13201 flow_dv_query(struct rte_eth_dev *dev,
13202               struct rte_flow *flow __rte_unused,
13203               const struct rte_flow_action *actions __rte_unused,
13204               void *data __rte_unused,
13205               struct rte_flow_error *error __rte_unused)
13206 {
13207         int ret = -EINVAL;
13208
13209         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
13210                 switch (actions->type) {
13211                 case RTE_FLOW_ACTION_TYPE_VOID:
13212                         break;
13213                 case RTE_FLOW_ACTION_TYPE_COUNT:
13214                         ret = flow_dv_query_count(dev, flow, data, error);
13215                         break;
13216                 case RTE_FLOW_ACTION_TYPE_AGE:
13217                         ret = flow_dv_query_age(dev, flow, data, error);
13218                         break;
13219                 default:
13220                         return rte_flow_error_set(error, ENOTSUP,
13221                                                   RTE_FLOW_ERROR_TYPE_ACTION,
13222                                                   actions,
13223                                                   "action not supported");
13224                 }
13225         }
13226         return ret;
13227 }
13228
13229 /**
13230  * Destroy the meter table set.
13231  * Lock free, (mutex should be acquired by caller).
13232  *
13233  * @param[in] dev
13234  *   Pointer to Ethernet device.
13235  * @param[in] tbl
13236  *   Pointer to the meter table set.
13237  *
13238  * @return
13239  *   Always 0.
13240  */
13241 static int
13242 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
13243                         struct mlx5_meter_domains_infos *tbl)
13244 {
13245         struct mlx5_priv *priv = dev->data->dev_private;
13246         struct mlx5_meter_domains_infos *mtd =
13247                                 (struct mlx5_meter_domains_infos *)tbl;
13248
13249         if (!mtd || !priv->config.dv_flow_en)
13250                 return 0;
13251         if (mtd->ingress.policer_rules[RTE_MTR_DROPPED])
13252                 claim_zero(mlx5_flow_os_destroy_flow
13253                            (mtd->ingress.policer_rules[RTE_MTR_DROPPED]));
13254         if (mtd->egress.policer_rules[RTE_MTR_DROPPED])
13255                 claim_zero(mlx5_flow_os_destroy_flow
13256                            (mtd->egress.policer_rules[RTE_MTR_DROPPED]));
13257         if (mtd->transfer.policer_rules[RTE_MTR_DROPPED])
13258                 claim_zero(mlx5_flow_os_destroy_flow
13259                            (mtd->transfer.policer_rules[RTE_MTR_DROPPED]));
13260         if (mtd->egress.color_matcher)
13261                 claim_zero(mlx5_flow_os_destroy_flow_matcher
13262                            (mtd->egress.color_matcher));
13263         if (mtd->egress.any_matcher)
13264                 claim_zero(mlx5_flow_os_destroy_flow_matcher
13265                            (mtd->egress.any_matcher));
13266         if (mtd->egress.tbl)
13267                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->egress.tbl);
13268         if (mtd->egress.sfx_tbl)
13269                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->egress.sfx_tbl);
13270         if (mtd->ingress.color_matcher)
13271                 claim_zero(mlx5_flow_os_destroy_flow_matcher
13272                            (mtd->ingress.color_matcher));
13273         if (mtd->ingress.any_matcher)
13274                 claim_zero(mlx5_flow_os_destroy_flow_matcher
13275                            (mtd->ingress.any_matcher));
13276         if (mtd->ingress.tbl)
13277                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->ingress.tbl);
13278         if (mtd->ingress.sfx_tbl)
13279                 flow_dv_tbl_resource_release(MLX5_SH(dev),
13280                                              mtd->ingress.sfx_tbl);
13281         if (mtd->transfer.color_matcher)
13282                 claim_zero(mlx5_flow_os_destroy_flow_matcher
13283                            (mtd->transfer.color_matcher));
13284         if (mtd->transfer.any_matcher)
13285                 claim_zero(mlx5_flow_os_destroy_flow_matcher
13286                            (mtd->transfer.any_matcher));
13287         if (mtd->transfer.tbl)
13288                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->transfer.tbl);
13289         if (mtd->transfer.sfx_tbl)
13290                 flow_dv_tbl_resource_release(MLX5_SH(dev),
13291                                              mtd->transfer.sfx_tbl);
13292         if (mtd->drop_actn)
13293                 claim_zero(mlx5_flow_os_destroy_flow_action(mtd->drop_actn));
13294         mlx5_free(mtd);
13295         return 0;
13296 }
13297
13298 /* Number of meter flow actions, count and jump or count and drop. */
13299 #define METER_ACTIONS 2
13300
13301 /**
13302  * Create specify domain meter table and suffix table.
13303  *
13304  * @param[in] dev
13305  *   Pointer to Ethernet device.
13306  * @param[in,out] mtb
13307  *   Pointer to DV meter table set.
13308  * @param[in] egress
13309  *   Table attribute.
13310  * @param[in] transfer
13311  *   Table attribute.
13312  * @param[in] color_reg_c_idx
13313  *   Reg C index for color match.
13314  *
13315  * @return
13316  *   0 on success, -1 otherwise and rte_errno is set.
13317  */
13318 static int
13319 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
13320                            struct mlx5_meter_domains_infos *mtb,
13321                            uint8_t egress, uint8_t transfer,
13322                            uint32_t color_reg_c_idx)
13323 {
13324         struct mlx5_priv *priv = dev->data->dev_private;
13325         struct mlx5_dev_ctx_shared *sh = priv->sh;
13326         struct mlx5_flow_dv_match_params mask = {
13327                 .size = sizeof(mask.buf),
13328         };
13329         struct mlx5_flow_dv_match_params value = {
13330                 .size = sizeof(value.buf),
13331         };
13332         struct mlx5dv_flow_matcher_attr dv_attr = {
13333                 .type = IBV_FLOW_ATTR_NORMAL,
13334                 .priority = 0,
13335                 .match_criteria_enable = 0,
13336                 .match_mask = (void *)&mask,
13337         };
13338         void *actions[METER_ACTIONS];
13339         struct mlx5_meter_domain_info *dtb;
13340         struct rte_flow_error error;
13341         int i = 0;
13342         int ret;
13343
13344         if (transfer)
13345                 dtb = &mtb->transfer;
13346         else if (egress)
13347                 dtb = &mtb->egress;
13348         else
13349                 dtb = &mtb->ingress;
13350         /* Create the meter table with METER level. */
13351         dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
13352                                             egress, transfer, false, NULL, 0,
13353                                             0, &error);
13354         if (!dtb->tbl) {
13355                 DRV_LOG(ERR, "Failed to create meter policer table.");
13356                 return -1;
13357         }
13358         /* Create the meter suffix table with SUFFIX level. */
13359         dtb->sfx_tbl = flow_dv_tbl_resource_get(dev,
13360                                             MLX5_FLOW_TABLE_LEVEL_SUFFIX,
13361                                             egress, transfer, false, NULL, 0,
13362                                             0, &error);
13363         if (!dtb->sfx_tbl) {
13364                 DRV_LOG(ERR, "Failed to create meter suffix table.");
13365                 return -1;
13366         }
13367         /* Create matchers, Any and Color. */
13368         dv_attr.priority = 3;
13369         dv_attr.match_criteria_enable = 0;
13370         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, dtb->tbl->obj,
13371                                                &dtb->any_matcher);
13372         if (ret) {
13373                 DRV_LOG(ERR, "Failed to create meter"
13374                              " policer default matcher.");
13375                 goto error_exit;
13376         }
13377         dv_attr.priority = 0;
13378         dv_attr.match_criteria_enable =
13379                                 1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
13380         flow_dv_match_meta_reg(mask.buf, value.buf, color_reg_c_idx,
13381                                rte_col_2_mlx5_col(RTE_COLORS), UINT8_MAX);
13382         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, dtb->tbl->obj,
13383                                                &dtb->color_matcher);
13384         if (ret) {
13385                 DRV_LOG(ERR, "Failed to create meter policer color matcher.");
13386                 goto error_exit;
13387         }
13388         if (mtb->count_actns[RTE_MTR_DROPPED])
13389                 actions[i++] = mtb->count_actns[RTE_MTR_DROPPED];
13390         actions[i++] = mtb->drop_actn;
13391         /* Default rule: lowest priority, match any, actions: drop. */
13392         ret = mlx5_flow_os_create_flow(dtb->any_matcher, (void *)&value, i,
13393                                        actions,
13394                                        &dtb->policer_rules[RTE_MTR_DROPPED]);
13395         if (ret) {
13396                 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
13397                 goto error_exit;
13398         }
13399         return 0;
13400 error_exit:
13401         return -1;
13402 }
13403
13404 /**
13405  * Create the needed meter and suffix tables.
13406  * Lock free, (mutex should be acquired by caller).
13407  *
13408  * @param[in] dev
13409  *   Pointer to Ethernet device.
13410  * @param[in] fm
13411  *   Pointer to the flow meter.
13412  *
13413  * @return
13414  *   Pointer to table set on success, NULL otherwise and rte_errno is set.
13415  */
13416 static struct mlx5_meter_domains_infos *
13417 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev,
13418                        const struct mlx5_flow_meter *fm)
13419 {
13420         struct mlx5_priv *priv = dev->data->dev_private;
13421         struct mlx5_meter_domains_infos *mtb;
13422         int ret;
13423         int i;
13424
13425         if (!priv->mtr_en) {
13426                 rte_errno = ENOTSUP;
13427                 return NULL;
13428         }
13429         mtb = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mtb), 0, SOCKET_ID_ANY);
13430         if (!mtb) {
13431                 DRV_LOG(ERR, "Failed to allocate memory for meter.");
13432                 return NULL;
13433         }
13434         /* Create meter count actions */
13435         for (i = 0; i <= RTE_MTR_DROPPED; i++) {
13436                 struct mlx5_flow_counter *cnt;
13437                 if (!fm->policer_stats.cnt[i])
13438                         continue;
13439                 cnt = flow_dv_counter_get_by_idx(dev,
13440                       fm->policer_stats.cnt[i], NULL);
13441                 mtb->count_actns[i] = cnt->action;
13442         }
13443         /* Create drop action. */
13444         ret = mlx5_flow_os_create_flow_action_drop(&mtb->drop_actn);
13445         if (ret) {
13446                 DRV_LOG(ERR, "Failed to create drop action.");
13447                 goto error_exit;
13448         }
13449         /* Egress meter table. */
13450         ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0, priv->mtr_color_reg);
13451         if (ret) {
13452                 DRV_LOG(ERR, "Failed to prepare egress meter table.");
13453                 goto error_exit;
13454         }
13455         /* Ingress meter table. */
13456         ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0, priv->mtr_color_reg);
13457         if (ret) {
13458                 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
13459                 goto error_exit;
13460         }
13461         /* FDB meter table. */
13462         if (priv->config.dv_esw_en) {
13463                 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1,
13464                                                  priv->mtr_color_reg);
13465                 if (ret) {
13466                         DRV_LOG(ERR, "Failed to prepare fdb meter table.");
13467                         goto error_exit;
13468                 }
13469         }
13470         return mtb;
13471 error_exit:
13472         flow_dv_destroy_mtr_tbl(dev, mtb);
13473         return NULL;
13474 }
13475
13476 /**
13477  * Destroy domain policer rule.
13478  *
13479  * @param[in] dt
13480  *   Pointer to domain table.
13481  */
13482 static void
13483 flow_dv_destroy_domain_policer_rule(struct mlx5_meter_domain_info *dt)
13484 {
13485         int i;
13486
13487         for (i = 0; i < RTE_MTR_DROPPED; i++) {
13488                 if (dt->policer_rules[i]) {
13489                         claim_zero(mlx5_flow_os_destroy_flow
13490                                    (dt->policer_rules[i]));
13491                         dt->policer_rules[i] = NULL;
13492                 }
13493         }
13494         if (dt->jump_actn) {
13495                 claim_zero(mlx5_flow_os_destroy_flow_action(dt->jump_actn));
13496                 dt->jump_actn = NULL;
13497         }
13498 }
13499
13500 /**
13501  * Destroy policer rules.
13502  *
13503  * @param[in] dev
13504  *   Pointer to Ethernet device.
13505  * @param[in] fm
13506  *   Pointer to flow meter structure.
13507  * @param[in] attr
13508  *   Pointer to flow attributes.
13509  *
13510  * @return
13511  *   Always 0.
13512  */
13513 static int
13514 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev __rte_unused,
13515                               const struct mlx5_flow_meter *fm,
13516                               const struct rte_flow_attr *attr)
13517 {
13518         struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
13519
13520         if (!mtb)
13521                 return 0;
13522         if (attr->egress)
13523                 flow_dv_destroy_domain_policer_rule(&mtb->egress);
13524         if (attr->ingress)
13525                 flow_dv_destroy_domain_policer_rule(&mtb->ingress);
13526         if (attr->transfer)
13527                 flow_dv_destroy_domain_policer_rule(&mtb->transfer);
13528         return 0;
13529 }
13530
13531 /**
13532  * Create specify domain meter policer rule.
13533  *
13534  * @param[in] fm
13535  *   Pointer to flow meter structure.
13536  * @param[in] mtb
13537  *   Pointer to DV meter table set.
13538  * @param[in] mtr_reg_c
13539  *   Color match REG_C.
13540  *
13541  * @return
13542  *   0 on success, -1 otherwise.
13543  */
13544 static int
13545 flow_dv_create_policer_forward_rule(struct mlx5_flow_meter *fm,
13546                                     struct mlx5_meter_domain_info *dtb,
13547                                     uint8_t mtr_reg_c)
13548 {
13549         struct mlx5_flow_dv_match_params matcher = {
13550                 .size = sizeof(matcher.buf),
13551         };
13552         struct mlx5_flow_dv_match_params value = {
13553                 .size = sizeof(value.buf),
13554         };
13555         struct mlx5_meter_domains_infos *mtb = fm->mfts;
13556         void *actions[METER_ACTIONS];
13557         int i;
13558         int ret = 0;
13559
13560         /* Create jump action. */
13561         if (!dtb->jump_actn)
13562                 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
13563                                 (dtb->sfx_tbl->obj, &dtb->jump_actn);
13564         if (ret) {
13565                 DRV_LOG(ERR, "Failed to create policer jump action.");
13566                 goto error;
13567         }
13568         for (i = 0; i < RTE_MTR_DROPPED; i++) {
13569                 int j = 0;
13570
13571                 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_reg_c,
13572                                        rte_col_2_mlx5_col(i), UINT8_MAX);
13573                 if (mtb->count_actns[i])
13574                         actions[j++] = mtb->count_actns[i];
13575                 if (fm->action[i] == MTR_POLICER_ACTION_DROP)
13576                         actions[j++] = mtb->drop_actn;
13577                 else
13578                         actions[j++] = dtb->jump_actn;
13579                 ret = mlx5_flow_os_create_flow(dtb->color_matcher,
13580                                                (void *)&value, j, actions,
13581                                                &dtb->policer_rules[i]);
13582                 if (ret) {
13583                         DRV_LOG(ERR, "Failed to create policer rule.");
13584                         goto error;
13585                 }
13586         }
13587         return 0;
13588 error:
13589         rte_errno = errno;
13590         return -1;
13591 }
13592
13593 /**
13594  * Create policer rules.
13595  *
13596  * @param[in] dev
13597  *   Pointer to Ethernet device.
13598  * @param[in] fm
13599  *   Pointer to flow meter structure.
13600  * @param[in] attr
13601  *   Pointer to flow attributes.
13602  *
13603  * @return
13604  *   0 on success, -1 otherwise.
13605  */
13606 static int
13607 flow_dv_create_policer_rules(struct rte_eth_dev *dev,
13608                              struct mlx5_flow_meter *fm,
13609                              const struct rte_flow_attr *attr)
13610 {
13611         struct mlx5_priv *priv = dev->data->dev_private;
13612         struct mlx5_meter_domains_infos *mtb = fm->mfts;
13613         int ret;
13614
13615         if (attr->egress) {
13616                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->egress,
13617                                                 priv->mtr_color_reg);
13618                 if (ret) {
13619                         DRV_LOG(ERR, "Failed to create egress policer.");
13620                         goto error;
13621                 }
13622         }
13623         if (attr->ingress) {
13624                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->ingress,
13625                                                 priv->mtr_color_reg);
13626                 if (ret) {
13627                         DRV_LOG(ERR, "Failed to create ingress policer.");
13628                         goto error;
13629                 }
13630         }
13631         if (attr->transfer) {
13632                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->transfer,
13633                                                 priv->mtr_color_reg);
13634                 if (ret) {
13635                         DRV_LOG(ERR, "Failed to create transfer policer.");
13636                         goto error;
13637                 }
13638         }
13639         return 0;
13640 error:
13641         flow_dv_destroy_policer_rules(dev, fm, attr);
13642         return -1;
13643 }
13644
13645 /**
13646  * Validate the batch counter support in root table.
13647  *
13648  * Create a simple flow with invalid counter and drop action on root table to
13649  * validate if batch counter with offset on root table is supported or not.
13650  *
13651  * @param[in] dev
13652  *   Pointer to rte_eth_dev structure.
13653  *
13654  * @return
13655  *   0 on success, a negative errno value otherwise and rte_errno is set.
13656  */
13657 int
13658 mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev)
13659 {
13660         struct mlx5_priv *priv = dev->data->dev_private;
13661         struct mlx5_dev_ctx_shared *sh = priv->sh;
13662         struct mlx5_flow_dv_match_params mask = {
13663                 .size = sizeof(mask.buf),
13664         };
13665         struct mlx5_flow_dv_match_params value = {
13666                 .size = sizeof(value.buf),
13667         };
13668         struct mlx5dv_flow_matcher_attr dv_attr = {
13669                 .type = IBV_FLOW_ATTR_NORMAL,
13670                 .priority = 0,
13671                 .match_criteria_enable = 0,
13672                 .match_mask = (void *)&mask,
13673         };
13674         void *actions[2] = { 0 };
13675         struct mlx5_flow_tbl_resource *tbl = NULL;
13676         struct mlx5_devx_obj *dcs = NULL;
13677         void *matcher = NULL;
13678         void *flow = NULL;
13679         int ret = -1;
13680
13681         tbl = flow_dv_tbl_resource_get(dev, 0, 0, 0, false, NULL, 0, 0, NULL);
13682         if (!tbl)
13683                 goto err;
13684         dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
13685         if (!dcs)
13686                 goto err;
13687         ret = mlx5_flow_os_create_flow_action_count(dcs->obj, UINT16_MAX,
13688                                                     &actions[0]);
13689         if (ret)
13690                 goto err;
13691         actions[1] = priv->drop_queue.hrxq->action;
13692         dv_attr.match_criteria_enable = flow_dv_matcher_enable(mask.buf);
13693         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj,
13694                                                &matcher);
13695         if (ret)
13696                 goto err;
13697         ret = mlx5_flow_os_create_flow(matcher, (void *)&value, 2,
13698                                        actions, &flow);
13699 err:
13700         /*
13701          * If batch counter with offset is not supported, the driver will not
13702          * validate the invalid offset value, flow create should success.
13703          * In this case, it means batch counter is not supported in root table.
13704          *
13705          * Otherwise, if flow create is failed, counter offset is supported.
13706          */
13707         if (flow) {
13708                 DRV_LOG(INFO, "Batch counter is not supported in root "
13709                               "table. Switch to fallback mode.");
13710                 rte_errno = ENOTSUP;
13711                 ret = -rte_errno;
13712                 claim_zero(mlx5_flow_os_destroy_flow(flow));
13713         } else {
13714                 /* Check matcher to make sure validate fail at flow create. */
13715                 if (!matcher || (matcher && errno != EINVAL))
13716                         DRV_LOG(ERR, "Unexpected error in counter offset "
13717                                      "support detection");
13718                 ret = 0;
13719         }
13720         if (actions[0])
13721                 claim_zero(mlx5_flow_os_destroy_flow_action(actions[0]));
13722         if (matcher)
13723                 claim_zero(mlx5_flow_os_destroy_flow_matcher(matcher));
13724         if (tbl)
13725                 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
13726         if (dcs)
13727                 claim_zero(mlx5_devx_cmd_destroy(dcs));
13728         return ret;
13729 }
13730
13731 /**
13732  * Query a devx counter.
13733  *
13734  * @param[in] dev
13735  *   Pointer to the Ethernet device structure.
13736  * @param[in] cnt
13737  *   Index to the flow counter.
13738  * @param[in] clear
13739  *   Set to clear the counter statistics.
13740  * @param[out] pkts
13741  *   The statistics value of packets.
13742  * @param[out] bytes
13743  *   The statistics value of bytes.
13744  *
13745  * @return
13746  *   0 on success, otherwise return -1.
13747  */
13748 static int
13749 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
13750                       uint64_t *pkts, uint64_t *bytes)
13751 {
13752         struct mlx5_priv *priv = dev->data->dev_private;
13753         struct mlx5_flow_counter *cnt;
13754         uint64_t inn_pkts, inn_bytes;
13755         int ret;
13756
13757         if (!priv->config.devx)
13758                 return -1;
13759
13760         ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
13761         if (ret)
13762                 return -1;
13763         cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
13764         *pkts = inn_pkts - cnt->hits;
13765         *bytes = inn_bytes - cnt->bytes;
13766         if (clear) {
13767                 cnt->hits = inn_pkts;
13768                 cnt->bytes = inn_bytes;
13769         }
13770         return 0;
13771 }
13772
13773 /**
13774  * Get aged-out flows.
13775  *
13776  * @param[in] dev
13777  *   Pointer to the Ethernet device structure.
13778  * @param[in] context
13779  *   The address of an array of pointers to the aged-out flows contexts.
13780  * @param[in] nb_contexts
13781  *   The length of context array pointers.
13782  * @param[out] error
13783  *   Perform verbose error reporting if not NULL. Initialized in case of
13784  *   error only.
13785  *
13786  * @return
13787  *   how many contexts get in success, otherwise negative errno value.
13788  *   if nb_contexts is 0, return the amount of all aged contexts.
13789  *   if nb_contexts is not 0 , return the amount of aged flows reported
13790  *   in the context array.
13791  * @note: only stub for now
13792  */
13793 static int
13794 flow_get_aged_flows(struct rte_eth_dev *dev,
13795                     void **context,
13796                     uint32_t nb_contexts,
13797                     struct rte_flow_error *error)
13798 {
13799         struct mlx5_priv *priv = dev->data->dev_private;
13800         struct mlx5_age_info *age_info;
13801         struct mlx5_age_param *age_param;
13802         struct mlx5_flow_counter *counter;
13803         struct mlx5_aso_age_action *act;
13804         int nb_flows = 0;
13805
13806         if (nb_contexts && !context)
13807                 return rte_flow_error_set(error, EINVAL,
13808                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13809                                           NULL, "empty context");
13810         age_info = GET_PORT_AGE_INFO(priv);
13811         rte_spinlock_lock(&age_info->aged_sl);
13812         LIST_FOREACH(act, &age_info->aged_aso, next) {
13813                 nb_flows++;
13814                 if (nb_contexts) {
13815                         context[nb_flows - 1] =
13816                                                 act->age_params.context;
13817                         if (!(--nb_contexts))
13818                                 break;
13819                 }
13820         }
13821         TAILQ_FOREACH(counter, &age_info->aged_counters, next) {
13822                 nb_flows++;
13823                 if (nb_contexts) {
13824                         age_param = MLX5_CNT_TO_AGE(counter);
13825                         context[nb_flows - 1] = age_param->context;
13826                         if (!(--nb_contexts))
13827                                 break;
13828                 }
13829         }
13830         rte_spinlock_unlock(&age_info->aged_sl);
13831         MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
13832         return nb_flows;
13833 }
13834
13835 /*
13836  * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
13837  */
13838 static uint32_t
13839 flow_dv_counter_allocate(struct rte_eth_dev *dev)
13840 {
13841         return flow_dv_counter_alloc(dev, 0);
13842 }
13843
13844 /**
13845  * Validate shared action.
13846  * Dispatcher for action type specific validation.
13847  *
13848  * @param[in] dev
13849  *   Pointer to the Ethernet device structure.
13850  * @param[in] conf
13851  *   Shared action configuration.
13852  * @param[in] action
13853  *   The shared action object to validate.
13854  * @param[out] error
13855  *   Perform verbose error reporting if not NULL. Initialized in case of
13856  *   error only.
13857  *
13858  * @return
13859  *   0 on success, otherwise negative errno value.
13860  */
13861 static int
13862 flow_dv_action_validate(struct rte_eth_dev *dev,
13863                         const struct rte_flow_shared_action_conf *conf,
13864                         const struct rte_flow_action *action,
13865                         struct rte_flow_error *err)
13866 {
13867         struct mlx5_priv *priv = dev->data->dev_private;
13868
13869         RTE_SET_USED(conf);
13870         switch (action->type) {
13871         case RTE_FLOW_ACTION_TYPE_RSS:
13872                 /*
13873                  * priv->obj_ops is set according to driver capabilities.
13874                  * When DevX capabilities are
13875                  * sufficient, it is set to devx_obj_ops.
13876                  * Otherwise, it is set to ibv_obj_ops.
13877                  * ibv_obj_ops doesn't support ind_table_modify operation.
13878                  * In this case the shared RSS action can't be used.
13879                  */
13880                 if (priv->obj_ops.ind_table_modify == NULL)
13881                         return rte_flow_error_set
13882                                         (err, ENOTSUP,
13883                                          RTE_FLOW_ERROR_TYPE_ACTION,
13884                                          NULL,
13885                                          "shared RSS action not supported");
13886                 return mlx5_validate_action_rss(dev, action, err);
13887         case RTE_FLOW_ACTION_TYPE_AGE:
13888                 if (!priv->sh->aso_age_mng)
13889                         return rte_flow_error_set(err, ENOTSUP,
13890                                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13891                                                 NULL,
13892                                              "shared age action not supported");
13893                 return flow_dv_validate_action_age(0, action, dev, err);
13894         default:
13895                 return rte_flow_error_set(err, ENOTSUP,
13896                                           RTE_FLOW_ERROR_TYPE_ACTION,
13897                                           NULL,
13898                                           "action type not supported");
13899         }
13900 }
13901
13902 static int
13903 flow_dv_sync_domain(struct rte_eth_dev *dev, uint32_t domains, uint32_t flags)
13904 {
13905         struct mlx5_priv *priv = dev->data->dev_private;
13906         int ret = 0;
13907
13908         if ((domains & MLX5_DOMAIN_BIT_NIC_RX) && priv->sh->rx_domain != NULL) {
13909                 ret = mlx5_os_flow_dr_sync_domain(priv->sh->rx_domain,
13910                                                 flags);
13911                 if (ret != 0)
13912                         return ret;
13913         }
13914         if ((domains & MLX5_DOMAIN_BIT_NIC_TX) && priv->sh->tx_domain != NULL) {
13915                 ret = mlx5_os_flow_dr_sync_domain(priv->sh->tx_domain, flags);
13916                 if (ret != 0)
13917                         return ret;
13918         }
13919         if ((domains & MLX5_DOMAIN_BIT_FDB) && priv->sh->fdb_domain != NULL) {
13920                 ret = mlx5_os_flow_dr_sync_domain(priv->sh->fdb_domain, flags);
13921                 if (ret != 0)
13922                         return ret;
13923         }
13924         return 0;
13925 }
13926
13927 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
13928         .validate = flow_dv_validate,
13929         .prepare = flow_dv_prepare,
13930         .translate = flow_dv_translate,
13931         .apply = flow_dv_apply,
13932         .remove = flow_dv_remove,
13933         .destroy = flow_dv_destroy,
13934         .query = flow_dv_query,
13935         .create_mtr_tbls = flow_dv_create_mtr_tbl,
13936         .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
13937         .create_policer_rules = flow_dv_create_policer_rules,
13938         .destroy_policer_rules = flow_dv_destroy_policer_rules,
13939         .counter_alloc = flow_dv_counter_allocate,
13940         .counter_free = flow_dv_counter_free,
13941         .counter_query = flow_dv_counter_query,
13942         .get_aged_flows = flow_get_aged_flows,
13943         .action_validate = flow_dv_action_validate,
13944         .action_create = flow_dv_action_create,
13945         .action_destroy = flow_dv_action_destroy,
13946         .action_update = flow_dv_action_update,
13947         .action_query = flow_dv_action_query,
13948         .sync_domain = flow_dv_sync_domain,
13949 };
13950
13951 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */
13952