drivers/net/mlx5/mlx5_flow_dv.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2018 Mellanox Technologies, Ltd
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdalign.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10
  11 #include <rte_common.h>
  12 #include <rte_ether.h>
  13 #include <ethdev_driver.h>
  14 #include <rte_flow.h>
  15 #include <rte_flow_driver.h>
  16 #include <rte_malloc.h>
  17 #include <rte_cycles.h>
  18 #include <rte_ip.h>
  19 #include <rte_gre.h>
  20 #include <rte_vxlan.h>
  21 #include <rte_gtp.h>
  22 #include <rte_eal_paging.h>
  23 #include <rte_mpls.h>
  24
  25 #include <mlx5_glue.h>
  26 #include <mlx5_devx_cmds.h>
  27 #include <mlx5_prm.h>
  28 #include <mlx5_malloc.h>
  29
  30 #include "mlx5_defs.h"
  31 #include "mlx5.h"
  32 #include "mlx5_common_os.h"
  33 #include "mlx5_flow.h"
  34 #include "mlx5_flow_os.h"
  35 #include "mlx5_rxtx.h"
  36 #include "rte_pmd_mlx5.h"
  37
  38 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
  39
  40 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
  41 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
  42 #endif
  43
  44 #ifndef HAVE_MLX5DV_DR_ESWITCH
  45 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
  46 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
  47 #endif
  48 #endif
  49
  50 #ifndef HAVE_MLX5DV_DR
  51 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
  52 #endif
  53
  54 /* VLAN header definitions */
  55 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
  56 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
  57 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
  58 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
  59 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
  60
  61 union flow_dv_attr {
  62         struct {
  63                 uint32_t valid:1;
  64                 uint32_t ipv4:1;
  65                 uint32_t ipv6:1;
  66                 uint32_t tcp:1;
  67                 uint32_t udp:1;
  68                 uint32_t reserved:27;
  69         };
  70         uint32_t attr;
  71 };
  72
  73 static int
  74 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
  75                              struct mlx5_flow_tbl_resource *tbl);
  76
  77 static int
  78 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
  79                                      uint32_t encap_decap_idx);
  80
  81 static int
  82 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
  83                                         uint32_t port_id);
  84 static void
  85 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss);
  86
  87 static int
  88 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
  89                                   uint32_t rix_jump);
  90
  91 /**
  92  * Initialize flow attributes structure according to flow items' types.
  93  *
  94  * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
  95  * mode. For tunnel mode, the items to be modified are the outermost ones.
  96  *
  97  * @param[in] item
  98  *   Pointer to item specification.
  99  * @param[out] attr
 100  *   Pointer to flow attributes structure.
 101  * @param[in] dev_flow
 102  *   Pointer to the sub flow.
 103  * @param[in] tunnel_decap
 104  *   Whether action is after tunnel decapsulation.
 105  */
 106 static void
 107 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
 108                   struct mlx5_flow *dev_flow, bool tunnel_decap)
 109 {
 110         uint64_t layers = dev_flow->handle->layers;
 111
 112         /*
 113          * If layers is already initialized, it means this dev_flow is the
 114          * suffix flow, the layers flags is set by the prefix flow. Need to
 115          * use the layer flags from prefix flow as the suffix flow may not
 116          * have the user defined items as the flow is split.
 117          */
 118         if (layers) {
 119                 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
 120                         attr->ipv4 = 1;
 121                 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
 122                         attr->ipv6 = 1;
 123                 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
 124                         attr->tcp = 1;
 125                 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
 126                         attr->udp = 1;
 127                 attr->valid = 1;
 128                 return;
 129         }
 130         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
 131                 uint8_t next_protocol = 0xff;
 132                 switch (item->type) {
 133                 case RTE_FLOW_ITEM_TYPE_GRE:
 134                 case RTE_FLOW_ITEM_TYPE_NVGRE:
 135                 case RTE_FLOW_ITEM_TYPE_VXLAN:
 136                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
 137                 case RTE_FLOW_ITEM_TYPE_GENEVE:
 138                 case RTE_FLOW_ITEM_TYPE_MPLS:
 139                         if (tunnel_decap)
 140                                 attr->attr = 0;
 141                         break;
 142                 case RTE_FLOW_ITEM_TYPE_IPV4:
 143                         if (!attr->ipv6)
 144                                 attr->ipv4 = 1;
 145                         if (item->mask != NULL &&
 146                             ((const struct rte_flow_item_ipv4 *)
 147                             item->mask)->hdr.next_proto_id)
 148                                 next_protocol =
 149                                     ((const struct rte_flow_item_ipv4 *)
 150                                       (item->spec))->hdr.next_proto_id &
 151                                     ((const struct rte_flow_item_ipv4 *)
 152                                       (item->mask))->hdr.next_proto_id;
 153                         if ((next_protocol == IPPROTO_IPIP ||
 154                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 155                                 attr->attr = 0;
 156                         break;
 157                 case RTE_FLOW_ITEM_TYPE_IPV6:
 158                         if (!attr->ipv4)
 159                                 attr->ipv6 = 1;
 160                         if (item->mask != NULL &&
 161                             ((const struct rte_flow_item_ipv6 *)
 162                             item->mask)->hdr.proto)
 163                                 next_protocol =
 164                                     ((const struct rte_flow_item_ipv6 *)
 165                                       (item->spec))->hdr.proto &
 166                                     ((const struct rte_flow_item_ipv6 *)
 167                                       (item->mask))->hdr.proto;
 168                         if ((next_protocol == IPPROTO_IPIP ||
 169                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 170                                 attr->attr = 0;
 171                         break;
 172                 case RTE_FLOW_ITEM_TYPE_UDP:
 173                         if (!attr->tcp)
 174                                 attr->udp = 1;
 175                         break;
 176                 case RTE_FLOW_ITEM_TYPE_TCP:
 177                         if (!attr->udp)
 178                                 attr->tcp = 1;
 179                         break;
 180                 default:
 181                         break;
 182                 }
 183         }
 184         attr->valid = 1;
 185 }
 186
 187 /**
 188  * Convert rte_mtr_color to mlx5 color.
 189  *
 190  * @param[in] rcol
 191  *   rte_mtr_color.
 192  *
 193  * @return
 194  *   mlx5 color.
 195  */
 196 static int
 197 rte_col_2_mlx5_col(enum rte_color rcol)
 198 {
 199         switch (rcol) {
 200         case RTE_COLOR_GREEN:
 201                 return MLX5_FLOW_COLOR_GREEN;
 202         case RTE_COLOR_YELLOW:
 203                 return MLX5_FLOW_COLOR_YELLOW;
 204         case RTE_COLOR_RED:
 205                 return MLX5_FLOW_COLOR_RED;
 206         default:
 207                 break;
 208         }
 209         return MLX5_FLOW_COLOR_UNDEFINED;
 210 }
 211
 212 struct field_modify_info {
 213         uint32_t size; /* Size of field in protocol header, in bytes. */
 214         uint32_t offset; /* Offset of field in protocol header, in bytes. */
 215         enum mlx5_modification_field id;
 216 };
 217
 218 struct field_modify_info modify_eth[] = {
 219         {4,  0, MLX5_MODI_OUT_DMAC_47_16},
 220         {2,  4, MLX5_MODI_OUT_DMAC_15_0},
 221         {4,  6, MLX5_MODI_OUT_SMAC_47_16},
 222         {2, 10, MLX5_MODI_OUT_SMAC_15_0},
 223         {0, 0, 0},
 224 };
 225
 226 struct field_modify_info modify_vlan_out_first_vid[] = {
 227         /* Size in bits !!! */
 228         {12, 0, MLX5_MODI_OUT_FIRST_VID},
 229         {0, 0, 0},
 230 };
 231
 232 struct field_modify_info modify_ipv4[] = {
 233         {1,  1, MLX5_MODI_OUT_IP_DSCP},
 234         {1,  8, MLX5_MODI_OUT_IPV4_TTL},
 235         {4, 12, MLX5_MODI_OUT_SIPV4},
 236         {4, 16, MLX5_MODI_OUT_DIPV4},
 237         {0, 0, 0},
 238 };
 239
 240 struct field_modify_info modify_ipv6[] = {
 241         {1,  0, MLX5_MODI_OUT_IP_DSCP},
 242         {1,  7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
 243         {4,  8, MLX5_MODI_OUT_SIPV6_127_96},
 244         {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
 245         {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
 246         {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
 247         {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
 248         {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
 249         {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
 250         {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
 251         {0, 0, 0},
 252 };
 253
 254 struct field_modify_info modify_udp[] = {
 255         {2, 0, MLX5_MODI_OUT_UDP_SPORT},
 256         {2, 2, MLX5_MODI_OUT_UDP_DPORT},
 257         {0, 0, 0},
 258 };
 259
 260 struct field_modify_info modify_tcp[] = {
 261         {2, 0, MLX5_MODI_OUT_TCP_SPORT},
 262         {2, 2, MLX5_MODI_OUT_TCP_DPORT},
 263         {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
 264         {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
 265         {0, 0, 0},
 266 };
 267
 268 static void
 269 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
 270                           uint8_t next_protocol, uint64_t *item_flags,
 271                           int *tunnel)
 272 {
 273         MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
 274                     item->type == RTE_FLOW_ITEM_TYPE_IPV6);
 275         if (next_protocol == IPPROTO_IPIP) {
 276                 *item_flags |= MLX5_FLOW_LAYER_IPIP;
 277                 *tunnel = 1;
 278         }
 279         if (next_protocol == IPPROTO_IPV6) {
 280                 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
 281                 *tunnel = 1;
 282         }
 283 }
 284
 285 /* Update VLAN's VID/PCP based on input rte_flow_action.
 286  *
 287  * @param[in] action
 288  *   Pointer to struct rte_flow_action.
 289  * @param[out] vlan
 290  *   Pointer to struct rte_vlan_hdr.
 291  */
 292 static void
 293 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
 294                          struct rte_vlan_hdr *vlan)
 295 {
 296         uint16_t vlan_tci;
 297         if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
 298                 vlan_tci =
 299                     ((const struct rte_flow_action_of_set_vlan_pcp *)
 300                                                action->conf)->vlan_pcp;
 301                 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
 302                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
 303                 vlan->vlan_tci |= vlan_tci;
 304         } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
 305                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
 306                 vlan->vlan_tci |= rte_be_to_cpu_16
 307                     (((const struct rte_flow_action_of_set_vlan_vid *)
 308                                              action->conf)->vlan_vid);
 309         }
 310 }
 311
 312 /**
 313  * Fetch 1, 2, 3 or 4 byte field from the byte array
 314  * and return as unsigned integer in host-endian format.
 315  *
 316  * @param[in] data
 317  *   Pointer to data array.
 318  * @param[in] size
 319  *   Size of field to extract.
 320  *
 321  * @return
 322  *   converted field in host endian format.
 323  */
 324 static inline uint32_t
 325 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
 326 {
 327         uint32_t ret;
 328
 329         switch (size) {
 330         case 1:
 331                 ret = *data;
 332                 break;
 333         case 2:
 334                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 335                 break;
 336         case 3:
 337                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 338                 ret = (ret << 8) | *(data + sizeof(uint16_t));
 339                 break;
 340         case 4:
 341                 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
 342                 break;
 343         default:
 344                 MLX5_ASSERT(false);
 345                 ret = 0;
 346                 break;
 347         }
 348         return ret;
 349 }
 350
 351 /**
 352  * Convert modify-header action to DV specification.
 353  *
 354  * Data length of each action is determined by provided field description
 355  * and the item mask. Data bit offset and width of each action is determined
 356  * by provided item mask.
 357  *
 358  * @param[in] item
 359  *   Pointer to item specification.
 360  * @param[in] field
 361  *   Pointer to field modification information.
 362  *     For MLX5_MODIFICATION_TYPE_SET specifies destination field.
 363  *     For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
 364  *     For MLX5_MODIFICATION_TYPE_COPY specifies source field.
 365  * @param[in] dcopy
 366  *   Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
 367  *   Negative offset value sets the same offset as source offset.
 368  *   size field is ignored, value is taken from source field.
 369  * @param[in,out] resource
 370  *   Pointer to the modify-header resource.
 371  * @param[in] type
 372  *   Type of modification.
 373  * @param[out] error
 374  *   Pointer to the error structure.
 375  *
 376  * @return
 377  *   0 on success, a negative errno value otherwise and rte_errno is set.
 378  */
 379 static int
 380 flow_dv_convert_modify_action(struct rte_flow_item *item,
 381                               struct field_modify_info *field,
 382                               struct field_modify_info *dcopy,
 383                               struct mlx5_flow_dv_modify_hdr_resource *resource,
 384                               uint32_t type, struct rte_flow_error *error)
 385 {
 386         uint32_t i = resource->actions_num;
 387         struct mlx5_modification_cmd *actions = resource->actions;
 388
 389         /*
 390          * The item and mask are provided in big-endian format.
 391          * The fields should be presented as in big-endian format either.
 392          * Mask must be always present, it defines the actual field width.
 393          */
 394         MLX5_ASSERT(item->mask);
 395         MLX5_ASSERT(field->size);
 396         do {
 397                 unsigned int size_b;
 398                 unsigned int off_b;
 399                 uint32_t mask;
 400                 uint32_t data;
 401
 402                 if (i >= MLX5_MAX_MODIFY_NUM)
 403                         return rte_flow_error_set(error, EINVAL,
 404                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 405                                  "too many items to modify");
 406                 /* Fetch variable byte size mask from the array. */
 407                 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
 408                                            field->offset, field->size);
 409                 if (!mask) {
 410                         ++field;
 411                         continue;
 412                 }
 413                 /* Deduce actual data width in bits from mask value. */
 414                 off_b = rte_bsf32(mask);
 415                 size_b = sizeof(uint32_t) * CHAR_BIT -
 416                          off_b - __builtin_clz(mask);
 417                 MLX5_ASSERT(size_b);
 418                 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
 419                 actions[i] = (struct mlx5_modification_cmd) {
 420                         .action_type = type,
 421                         .field = field->id,
 422                         .offset = off_b,
 423                         .length = size_b,
 424                 };
 425                 /* Convert entire record to expected big-endian format. */
 426                 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 427                 if (type == MLX5_MODIFICATION_TYPE_COPY) {
 428                         MLX5_ASSERT(dcopy);
 429                         actions[i].dst_field = dcopy->id;
 430                         actions[i].dst_offset =
 431                                 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
 432                         /* Convert entire record to big-endian format. */
 433                         actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
 434                 } else {
 435                         MLX5_ASSERT(item->spec);
 436                         data = flow_dv_fetch_field((const uint8_t *)item->spec +
 437                                                    field->offset, field->size);
 438                         /* Shift out the trailing masked bits from data. */
 439                         data = (data & mask) >> off_b;
 440                         actions[i].data1 = rte_cpu_to_be_32(data);
 441                 }
 442                 ++i;
 443                 ++field;
 444         } while (field->size);
 445         if (resource->actions_num == i)
 446                 return rte_flow_error_set(error, EINVAL,
 447                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 448                                           "invalid modification flow item");
 449         resource->actions_num = i;
 450         return 0;
 451 }
 452
 453 /**
 454  * Convert modify-header set IPv4 address action to DV specification.
 455  *
 456  * @param[in,out] resource
 457  *   Pointer to the modify-header resource.
 458  * @param[in] action
 459  *   Pointer to action specification.
 460  * @param[out] error
 461  *   Pointer to the error structure.
 462  *
 463  * @return
 464  *   0 on success, a negative errno value otherwise and rte_errno is set.
 465  */
 466 static int
 467 flow_dv_convert_action_modify_ipv4
 468                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 469                          const struct rte_flow_action *action,
 470                          struct rte_flow_error *error)
 471 {
 472         const struct rte_flow_action_set_ipv4 *conf =
 473                 (const struct rte_flow_action_set_ipv4 *)(action->conf);
 474         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
 475         struct rte_flow_item_ipv4 ipv4;
 476         struct rte_flow_item_ipv4 ipv4_mask;
 477
 478         memset(&ipv4, 0, sizeof(ipv4));
 479         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 480         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
 481                 ipv4.hdr.src_addr = conf->ipv4_addr;
 482                 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
 483         } else {
 484                 ipv4.hdr.dst_addr = conf->ipv4_addr;
 485                 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
 486         }
 487         item.spec = &ipv4;
 488         item.mask = &ipv4_mask;
 489         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
 490                                              MLX5_MODIFICATION_TYPE_SET, error);
 491 }
 492
 493 /**
 494  * Convert modify-header set IPv6 address action to DV specification.
 495  *
 496  * @param[in,out] resource
 497  *   Pointer to the modify-header resource.
 498  * @param[in] action
 499  *   Pointer to action specification.
 500  * @param[out] error
 501  *   Pointer to the error structure.
 502  *
 503  * @return
 504  *   0 on success, a negative errno value otherwise and rte_errno is set.
 505  */
 506 static int
 507 flow_dv_convert_action_modify_ipv6
 508                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 509                          const struct rte_flow_action *action,
 510                          struct rte_flow_error *error)
 511 {
 512         const struct rte_flow_action_set_ipv6 *conf =
 513                 (const struct rte_flow_action_set_ipv6 *)(action->conf);
 514         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
 515         struct rte_flow_item_ipv6 ipv6;
 516         struct rte_flow_item_ipv6 ipv6_mask;
 517
 518         memset(&ipv6, 0, sizeof(ipv6));
 519         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 520         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
 521                 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
 522                        sizeof(ipv6.hdr.src_addr));
 523                 memcpy(&ipv6_mask.hdr.src_addr,
 524                        &rte_flow_item_ipv6_mask.hdr.src_addr,
 525                        sizeof(ipv6.hdr.src_addr));
 526         } else {
 527                 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
 528                        sizeof(ipv6.hdr.dst_addr));
 529                 memcpy(&ipv6_mask.hdr.dst_addr,
 530                        &rte_flow_item_ipv6_mask.hdr.dst_addr,
 531                        sizeof(ipv6.hdr.dst_addr));
 532         }
 533         item.spec = &ipv6;
 534         item.mask = &ipv6_mask;
 535         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
 536                                              MLX5_MODIFICATION_TYPE_SET, error);
 537 }
 538
 539 /**
 540  * Convert modify-header set MAC address action to DV specification.
 541  *
 542  * @param[in,out] resource
 543  *   Pointer to the modify-header resource.
 544  * @param[in] action
 545  *   Pointer to action specification.
 546  * @param[out] error
 547  *   Pointer to the error structure.
 548  *
 549  * @return
 550  *   0 on success, a negative errno value otherwise and rte_errno is set.
 551  */
 552 static int
 553 flow_dv_convert_action_modify_mac
 554                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 555                          const struct rte_flow_action *action,
 556                          struct rte_flow_error *error)
 557 {
 558         const struct rte_flow_action_set_mac *conf =
 559                 (const struct rte_flow_action_set_mac *)(action->conf);
 560         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
 561         struct rte_flow_item_eth eth;
 562         struct rte_flow_item_eth eth_mask;
 563
 564         memset(&eth, 0, sizeof(eth));
 565         memset(&eth_mask, 0, sizeof(eth_mask));
 566         if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
 567                 memcpy(&eth.src.addr_bytes, &conf->mac_addr,
 568                        sizeof(eth.src.addr_bytes));
 569                 memcpy(&eth_mask.src.addr_bytes,
 570                        &rte_flow_item_eth_mask.src.addr_bytes,
 571                        sizeof(eth_mask.src.addr_bytes));
 572         } else {
 573                 memcpy(&eth.dst.addr_bytes, &conf->mac_addr,
 574                        sizeof(eth.dst.addr_bytes));
 575                 memcpy(&eth_mask.dst.addr_bytes,
 576                        &rte_flow_item_eth_mask.dst.addr_bytes,
 577                        sizeof(eth_mask.dst.addr_bytes));
 578         }
 579         item.spec = &eth;
 580         item.mask = &eth_mask;
 581         return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
 582                                              MLX5_MODIFICATION_TYPE_SET, error);
 583 }
 584
 585 /**
 586  * Convert modify-header set VLAN VID action to DV specification.
 587  *
 588  * @param[in,out] resource
 589  *   Pointer to the modify-header resource.
 590  * @param[in] action
 591  *   Pointer to action specification.
 592  * @param[out] error
 593  *   Pointer to the error structure.
 594  *
 595  * @return
 596  *   0 on success, a negative errno value otherwise and rte_errno is set.
 597  */
 598 static int
 599 flow_dv_convert_action_modify_vlan_vid
 600                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 601                          const struct rte_flow_action *action,
 602                          struct rte_flow_error *error)
 603 {
 604         const struct rte_flow_action_of_set_vlan_vid *conf =
 605                 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
 606         int i = resource->actions_num;
 607         struct mlx5_modification_cmd *actions = resource->actions;
 608         struct field_modify_info *field = modify_vlan_out_first_vid;
 609
 610         if (i >= MLX5_MAX_MODIFY_NUM)
 611                 return rte_flow_error_set(error, EINVAL,
 612                          RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 613                          "too many items to modify");
 614         actions[i] = (struct mlx5_modification_cmd) {
 615                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 616                 .field = field->id,
 617                 .length = field->size,
 618                 .offset = field->offset,
 619         };
 620         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 621         actions[i].data1 = conf->vlan_vid;
 622         actions[i].data1 = actions[i].data1 << 16;
 623         resource->actions_num = ++i;
 624         return 0;
 625 }
 626
 627 /**
 628  * Convert modify-header set TP action to DV specification.
 629  *
 630  * @param[in,out] resource
 631  *   Pointer to the modify-header resource.
 632  * @param[in] action
 633  *   Pointer to action specification.
 634  * @param[in] items
 635  *   Pointer to rte_flow_item objects list.
 636  * @param[in] attr
 637  *   Pointer to flow attributes structure.
 638  * @param[in] dev_flow
 639  *   Pointer to the sub flow.
 640  * @param[in] tunnel_decap
 641  *   Whether action is after tunnel decapsulation.
 642  * @param[out] error
 643  *   Pointer to the error structure.
 644  *
 645  * @return
 646  *   0 on success, a negative errno value otherwise and rte_errno is set.
 647  */
 648 static int
 649 flow_dv_convert_action_modify_tp
 650                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 651                          const struct rte_flow_action *action,
 652                          const struct rte_flow_item *items,
 653                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 654                          bool tunnel_decap, struct rte_flow_error *error)
 655 {
 656         const struct rte_flow_action_set_tp *conf =
 657                 (const struct rte_flow_action_set_tp *)(action->conf);
 658         struct rte_flow_item item;
 659         struct rte_flow_item_udp udp;
 660         struct rte_flow_item_udp udp_mask;
 661         struct rte_flow_item_tcp tcp;
 662         struct rte_flow_item_tcp tcp_mask;
 663         struct field_modify_info *field;
 664
 665         if (!attr->valid)
 666                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 667         if (attr->udp) {
 668                 memset(&udp, 0, sizeof(udp));
 669                 memset(&udp_mask, 0, sizeof(udp_mask));
 670                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 671                         udp.hdr.src_port = conf->port;
 672                         udp_mask.hdr.src_port =
 673                                         rte_flow_item_udp_mask.hdr.src_port;
 674                 } else {
 675                         udp.hdr.dst_port = conf->port;
 676                         udp_mask.hdr.dst_port =
 677                                         rte_flow_item_udp_mask.hdr.dst_port;
 678                 }
 679                 item.type = RTE_FLOW_ITEM_TYPE_UDP;
 680                 item.spec = &udp;
 681                 item.mask = &udp_mask;
 682                 field = modify_udp;
 683         } else {
 684                 MLX5_ASSERT(attr->tcp);
 685                 memset(&tcp, 0, sizeof(tcp));
 686                 memset(&tcp_mask, 0, sizeof(tcp_mask));
 687                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 688                         tcp.hdr.src_port = conf->port;
 689                         tcp_mask.hdr.src_port =
 690                                         rte_flow_item_tcp_mask.hdr.src_port;
 691                 } else {
 692                         tcp.hdr.dst_port = conf->port;
 693                         tcp_mask.hdr.dst_port =
 694                                         rte_flow_item_tcp_mask.hdr.dst_port;
 695                 }
 696                 item.type = RTE_FLOW_ITEM_TYPE_TCP;
 697                 item.spec = &tcp;
 698                 item.mask = &tcp_mask;
 699                 field = modify_tcp;
 700         }
 701         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 702                                              MLX5_MODIFICATION_TYPE_SET, error);
 703 }
 704
 705 /**
 706  * Convert modify-header set TTL action to DV specification.
 707  *
 708  * @param[in,out] resource
 709  *   Pointer to the modify-header resource.
 710  * @param[in] action
 711  *   Pointer to action specification.
 712  * @param[in] items
 713  *   Pointer to rte_flow_item objects list.
 714  * @param[in] attr
 715  *   Pointer to flow attributes structure.
 716  * @param[in] dev_flow
 717  *   Pointer to the sub flow.
 718  * @param[in] tunnel_decap
 719  *   Whether action is after tunnel decapsulation.
 720  * @param[out] error
 721  *   Pointer to the error structure.
 722  *
 723  * @return
 724  *   0 on success, a negative errno value otherwise and rte_errno is set.
 725  */
 726 static int
 727 flow_dv_convert_action_modify_ttl
 728                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 729                          const struct rte_flow_action *action,
 730                          const struct rte_flow_item *items,
 731                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 732                          bool tunnel_decap, struct rte_flow_error *error)
 733 {
 734         const struct rte_flow_action_set_ttl *conf =
 735                 (const struct rte_flow_action_set_ttl *)(action->conf);
 736         struct rte_flow_item item;
 737         struct rte_flow_item_ipv4 ipv4;
 738         struct rte_flow_item_ipv4 ipv4_mask;
 739         struct rte_flow_item_ipv6 ipv6;
 740         struct rte_flow_item_ipv6 ipv6_mask;
 741         struct field_modify_info *field;
 742
 743         if (!attr->valid)
 744                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 745         if (attr->ipv4) {
 746                 memset(&ipv4, 0, sizeof(ipv4));
 747                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 748                 ipv4.hdr.time_to_live = conf->ttl_value;
 749                 ipv4_mask.hdr.time_to_live = 0xFF;
 750                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 751                 item.spec = &ipv4;
 752                 item.mask = &ipv4_mask;
 753                 field = modify_ipv4;
 754         } else {
 755                 MLX5_ASSERT(attr->ipv6);
 756                 memset(&ipv6, 0, sizeof(ipv6));
 757                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 758                 ipv6.hdr.hop_limits = conf->ttl_value;
 759                 ipv6_mask.hdr.hop_limits = 0xFF;
 760                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 761                 item.spec = &ipv6;
 762                 item.mask = &ipv6_mask;
 763                 field = modify_ipv6;
 764         }
 765         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 766                                              MLX5_MODIFICATION_TYPE_SET, error);
 767 }
 768
 769 /**
 770  * Convert modify-header decrement TTL action to DV specification.
 771  *
 772  * @param[in,out] resource
 773  *   Pointer to the modify-header resource.
 774  * @param[in] action
 775  *   Pointer to action specification.
 776  * @param[in] items
 777  *   Pointer to rte_flow_item objects list.
 778  * @param[in] attr
 779  *   Pointer to flow attributes structure.
 780  * @param[in] dev_flow
 781  *   Pointer to the sub flow.
 782  * @param[in] tunnel_decap
 783  *   Whether action is after tunnel decapsulation.
 784  * @param[out] error
 785  *   Pointer to the error structure.
 786  *
 787  * @return
 788  *   0 on success, a negative errno value otherwise and rte_errno is set.
 789  */
 790 static int
 791 flow_dv_convert_action_modify_dec_ttl
 792                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 793                          const struct rte_flow_item *items,
 794                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 795                          bool tunnel_decap, struct rte_flow_error *error)
 796 {
 797         struct rte_flow_item item;
 798         struct rte_flow_item_ipv4 ipv4;
 799         struct rte_flow_item_ipv4 ipv4_mask;
 800         struct rte_flow_item_ipv6 ipv6;
 801         struct rte_flow_item_ipv6 ipv6_mask;
 802         struct field_modify_info *field;
 803
 804         if (!attr->valid)
 805                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 806         if (attr->ipv4) {
 807                 memset(&ipv4, 0, sizeof(ipv4));
 808                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 809                 ipv4.hdr.time_to_live = 0xFF;
 810                 ipv4_mask.hdr.time_to_live = 0xFF;
 811                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 812                 item.spec = &ipv4;
 813                 item.mask = &ipv4_mask;
 814                 field = modify_ipv4;
 815         } else {
 816                 MLX5_ASSERT(attr->ipv6);
 817                 memset(&ipv6, 0, sizeof(ipv6));
 818                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 819                 ipv6.hdr.hop_limits = 0xFF;
 820                 ipv6_mask.hdr.hop_limits = 0xFF;
 821                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 822                 item.spec = &ipv6;
 823                 item.mask = &ipv6_mask;
 824                 field = modify_ipv6;
 825         }
 826         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 827                                              MLX5_MODIFICATION_TYPE_ADD, error);
 828 }
 829
 830 /**
 831  * Convert modify-header increment/decrement TCP Sequence number
 832  * to DV specification.
 833  *
 834  * @param[in,out] resource
 835  *   Pointer to the modify-header resource.
 836  * @param[in] action
 837  *   Pointer to action specification.
 838  * @param[out] error
 839  *   Pointer to the error structure.
 840  *
 841  * @return
 842  *   0 on success, a negative errno value otherwise and rte_errno is set.
 843  */
 844 static int
 845 flow_dv_convert_action_modify_tcp_seq
 846                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 847                          const struct rte_flow_action *action,
 848                          struct rte_flow_error *error)
 849 {
 850         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 851         uint64_t value = rte_be_to_cpu_32(*conf);
 852         struct rte_flow_item item;
 853         struct rte_flow_item_tcp tcp;
 854         struct rte_flow_item_tcp tcp_mask;
 855
 856         memset(&tcp, 0, sizeof(tcp));
 857         memset(&tcp_mask, 0, sizeof(tcp_mask));
 858         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
 859                 /*
 860                  * The HW has no decrement operation, only increment operation.
 861                  * To simulate decrement X from Y using increment operation
 862                  * we need to add UINT32_MAX X times to Y.
 863                  * Each adding of UINT32_MAX decrements Y by 1.
 864                  */
 865                 value *= UINT32_MAX;
 866         tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
 867         tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
 868         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 869         item.spec = &tcp;
 870         item.mask = &tcp_mask;
 871         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 872                                              MLX5_MODIFICATION_TYPE_ADD, error);
 873 }
 874
 875 /**
 876  * Convert modify-header increment/decrement TCP Acknowledgment number
 877  * to DV specification.
 878  *
 879  * @param[in,out] resource
 880  *   Pointer to the modify-header resource.
 881  * @param[in] action
 882  *   Pointer to action specification.
 883  * @param[out] error
 884  *   Pointer to the error structure.
 885  *
 886  * @return
 887  *   0 on success, a negative errno value otherwise and rte_errno is set.
 888  */
 889 static int
 890 flow_dv_convert_action_modify_tcp_ack
 891                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 892                          const struct rte_flow_action *action,
 893                          struct rte_flow_error *error)
 894 {
 895         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 896         uint64_t value = rte_be_to_cpu_32(*conf);
 897         struct rte_flow_item item;
 898         struct rte_flow_item_tcp tcp;
 899         struct rte_flow_item_tcp tcp_mask;
 900
 901         memset(&tcp, 0, sizeof(tcp));
 902         memset(&tcp_mask, 0, sizeof(tcp_mask));
 903         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
 904                 /*
 905                  * The HW has no decrement operation, only increment operation.
 906                  * To simulate decrement X from Y using increment operation
 907                  * we need to add UINT32_MAX X times to Y.
 908                  * Each adding of UINT32_MAX decrements Y by 1.
 909                  */
 910                 value *= UINT32_MAX;
 911         tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
 912         tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
 913         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 914         item.spec = &tcp;
 915         item.mask = &tcp_mask;
 916         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 917                                              MLX5_MODIFICATION_TYPE_ADD, error);
 918 }
 919
 920 static enum mlx5_modification_field reg_to_field[] = {
 921         [REG_NON] = MLX5_MODI_OUT_NONE,
 922         [REG_A] = MLX5_MODI_META_DATA_REG_A,
 923         [REG_B] = MLX5_MODI_META_DATA_REG_B,
 924         [REG_C_0] = MLX5_MODI_META_REG_C_0,
 925         [REG_C_1] = MLX5_MODI_META_REG_C_1,
 926         [REG_C_2] = MLX5_MODI_META_REG_C_2,
 927         [REG_C_3] = MLX5_MODI_META_REG_C_3,
 928         [REG_C_4] = MLX5_MODI_META_REG_C_4,
 929         [REG_C_5] = MLX5_MODI_META_REG_C_5,
 930         [REG_C_6] = MLX5_MODI_META_REG_C_6,
 931         [REG_C_7] = MLX5_MODI_META_REG_C_7,
 932 };
 933
 934 /**
 935  * Convert register set to DV specification.
 936  *
 937  * @param[in,out] resource
 938  *   Pointer to the modify-header resource.
 939  * @param[in] action
 940  *   Pointer to action specification.
 941  * @param[out] error
 942  *   Pointer to the error structure.
 943  *
 944  * @return
 945  *   0 on success, a negative errno value otherwise and rte_errno is set.
 946  */
 947 static int
 948 flow_dv_convert_action_set_reg
 949                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 950                          const struct rte_flow_action *action,
 951                          struct rte_flow_error *error)
 952 {
 953         const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
 954         struct mlx5_modification_cmd *actions = resource->actions;
 955         uint32_t i = resource->actions_num;
 956
 957         if (i >= MLX5_MAX_MODIFY_NUM)
 958                 return rte_flow_error_set(error, EINVAL,
 959                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 960                                           "too many items to modify");
 961         MLX5_ASSERT(conf->id != REG_NON);
 962         MLX5_ASSERT(conf->id < (enum modify_reg)RTE_DIM(reg_to_field));
 963         actions[i] = (struct mlx5_modification_cmd) {
 964                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 965                 .field = reg_to_field[conf->id],
 966         };
 967         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 968         actions[i].data1 = rte_cpu_to_be_32(conf->data);
 969         ++i;
 970         resource->actions_num = i;
 971         return 0;
 972 }
 973
 974 /**
 975  * Convert SET_TAG action to DV specification.
 976  *
 977  * @param[in] dev
 978  *   Pointer to the rte_eth_dev structure.
 979  * @param[in,out] resource
 980  *   Pointer to the modify-header resource.
 981  * @param[in] conf
 982  *   Pointer to action specification.
 983  * @param[out] error
 984  *   Pointer to the error structure.
 985  *
 986  * @return
 987  *   0 on success, a negative errno value otherwise and rte_errno is set.
 988  */
 989 static int
 990 flow_dv_convert_action_set_tag
 991                         (struct rte_eth_dev *dev,
 992                          struct mlx5_flow_dv_modify_hdr_resource *resource,
 993                          const struct rte_flow_action_set_tag *conf,
 994                          struct rte_flow_error *error)
 995 {
 996         rte_be32_t data = rte_cpu_to_be_32(conf->data);
 997         rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
 998         struct rte_flow_item item = {
 999                 .spec = &data,
1000                 .mask = &mask,
1001         };
1002         struct field_modify_info reg_c_x[] = {
1003                 [1] = {0, 0, 0},
1004         };
1005         enum mlx5_modification_field reg_type;
1006         int ret;
1007
1008         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1009         if (ret < 0)
1010                 return ret;
1011         MLX5_ASSERT(ret != REG_NON);
1012         MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1013         reg_type = reg_to_field[ret];
1014         MLX5_ASSERT(reg_type > 0);
1015         reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1016         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1017                                              MLX5_MODIFICATION_TYPE_SET, error);
1018 }
1019
1020 /**
1021  * Convert internal COPY_REG action to DV specification.
1022  *
1023  * @param[in] dev
1024  *   Pointer to the rte_eth_dev structure.
1025  * @param[in,out] res
1026  *   Pointer to the modify-header resource.
1027  * @param[in] action
1028  *   Pointer to action specification.
1029  * @param[out] error
1030  *   Pointer to the error structure.
1031  *
1032  * @return
1033  *   0 on success, a negative errno value otherwise and rte_errno is set.
1034  */
1035 static int
1036 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1037                                  struct mlx5_flow_dv_modify_hdr_resource *res,
1038                                  const struct rte_flow_action *action,
1039                                  struct rte_flow_error *error)
1040 {
1041         const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1042         rte_be32_t mask = RTE_BE32(UINT32_MAX);
1043         struct rte_flow_item item = {
1044                 .spec = NULL,
1045                 .mask = &mask,
1046         };
1047         struct field_modify_info reg_src[] = {
1048                 {4, 0, reg_to_field[conf->src]},
1049                 {0, 0, 0},
1050         };
1051         struct field_modify_info reg_dst = {
1052                 .offset = 0,
1053                 .id = reg_to_field[conf->dst],
1054         };
1055         /* Adjust reg_c[0] usage according to reported mask. */
1056         if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1057                 struct mlx5_priv *priv = dev->data->dev_private;
1058                 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1059
1060                 MLX5_ASSERT(reg_c0);
1061                 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1062                 if (conf->dst == REG_C_0) {
1063                         /* Copy to reg_c[0], within mask only. */
1064                         reg_dst.offset = rte_bsf32(reg_c0);
1065                         /*
1066                          * Mask is ignoring the enianness, because
1067                          * there is no conversion in datapath.
1068                          */
1069 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1070                         /* Copy from destination lower bits to reg_c[0]. */
1071                         mask = reg_c0 >> reg_dst.offset;
1072 #else
1073                         /* Copy from destination upper bits to reg_c[0]. */
1074                         mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1075                                           rte_fls_u32(reg_c0));
1076 #endif
1077                 } else {
1078                         mask = rte_cpu_to_be_32(reg_c0);
1079 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1080                         /* Copy from reg_c[0] to destination lower bits. */
1081                         reg_dst.offset = 0;
1082 #else
1083                         /* Copy from reg_c[0] to destination upper bits. */
1084                         reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1085                                          (rte_fls_u32(reg_c0) -
1086                                           rte_bsf32(reg_c0));
1087 #endif
1088                 }
1089         }
1090         return flow_dv_convert_modify_action(&item,
1091                                              reg_src, &reg_dst, res,
1092                                              MLX5_MODIFICATION_TYPE_COPY,
1093                                              error);
1094 }
1095
1096 /**
1097  * Convert MARK action to DV specification. This routine is used
1098  * in extensive metadata only and requires metadata register to be
1099  * handled. In legacy mode hardware tag resource is engaged.
1100  *
1101  * @param[in] dev
1102  *   Pointer to the rte_eth_dev structure.
1103  * @param[in] conf
1104  *   Pointer to MARK action specification.
1105  * @param[in,out] resource
1106  *   Pointer to the modify-header resource.
1107  * @param[out] error
1108  *   Pointer to the error structure.
1109  *
1110  * @return
1111  *   0 on success, a negative errno value otherwise and rte_errno is set.
1112  */
1113 static int
1114 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1115                             const struct rte_flow_action_mark *conf,
1116                             struct mlx5_flow_dv_modify_hdr_resource *resource,
1117                             struct rte_flow_error *error)
1118 {
1119         struct mlx5_priv *priv = dev->data->dev_private;
1120         rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1121                                            priv->sh->dv_mark_mask);
1122         rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1123         struct rte_flow_item item = {
1124                 .spec = &data,
1125                 .mask = &mask,
1126         };
1127         struct field_modify_info reg_c_x[] = {
1128                 [1] = {0, 0, 0},
1129         };
1130         int reg;
1131
1132         if (!mask)
1133                 return rte_flow_error_set(error, EINVAL,
1134                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1135                                           NULL, "zero mark action mask");
1136         reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1137         if (reg < 0)
1138                 return reg;
1139         MLX5_ASSERT(reg > 0);
1140         if (reg == REG_C_0) {
1141                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1142                 uint32_t shl_c0 = rte_bsf32(msk_c0);
1143
1144                 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1145                 mask = rte_cpu_to_be_32(mask) & msk_c0;
1146                 mask = rte_cpu_to_be_32(mask << shl_c0);
1147         }
1148         reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1149         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1150                                              MLX5_MODIFICATION_TYPE_SET, error);
1151 }
1152
1153 /**
1154  * Get metadata register index for specified steering domain.
1155  *
1156  * @param[in] dev
1157  *   Pointer to the rte_eth_dev structure.
1158  * @param[in] attr
1159  *   Attributes of flow to determine steering domain.
1160  * @param[out] error
1161  *   Pointer to the error structure.
1162  *
1163  * @return
1164  *   positive index on success, a negative errno value otherwise
1165  *   and rte_errno is set.
1166  */
1167 static enum modify_reg
1168 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1169                          const struct rte_flow_attr *attr,
1170                          struct rte_flow_error *error)
1171 {
1172         int reg =
1173                 mlx5_flow_get_reg_id(dev, attr->transfer ?
1174                                           MLX5_METADATA_FDB :
1175                                             attr->egress ?
1176                                             MLX5_METADATA_TX :
1177                                             MLX5_METADATA_RX, 0, error);
1178         if (reg < 0)
1179                 return rte_flow_error_set(error,
1180                                           ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1181                                           NULL, "unavailable "
1182                                           "metadata register");
1183         return reg;
1184 }
1185
1186 /**
1187  * Convert SET_META action to DV specification.
1188  *
1189  * @param[in] dev
1190  *   Pointer to the rte_eth_dev structure.
1191  * @param[in,out] resource
1192  *   Pointer to the modify-header resource.
1193  * @param[in] attr
1194  *   Attributes of flow that includes this item.
1195  * @param[in] conf
1196  *   Pointer to action specification.
1197  * @param[out] error
1198  *   Pointer to the error structure.
1199  *
1200  * @return
1201  *   0 on success, a negative errno value otherwise and rte_errno is set.
1202  */
1203 static int
1204 flow_dv_convert_action_set_meta
1205                         (struct rte_eth_dev *dev,
1206                          struct mlx5_flow_dv_modify_hdr_resource *resource,
1207                          const struct rte_flow_attr *attr,
1208                          const struct rte_flow_action_set_meta *conf,
1209                          struct rte_flow_error *error)
1210 {
1211         uint32_t data = conf->data;
1212         uint32_t mask = conf->mask;
1213         struct rte_flow_item item = {
1214                 .spec = &data,
1215                 .mask = &mask,
1216         };
1217         struct field_modify_info reg_c_x[] = {
1218                 [1] = {0, 0, 0},
1219         };
1220         int reg = flow_dv_get_metadata_reg(dev, attr, error);
1221
1222         if (reg < 0)
1223                 return reg;
1224         MLX5_ASSERT(reg != REG_NON);
1225         /*
1226          * In datapath code there is no endianness
1227          * coversions for perfromance reasons, all
1228          * pattern conversions are done in rte_flow.
1229          */
1230         if (reg == REG_C_0) {
1231                 struct mlx5_priv *priv = dev->data->dev_private;
1232                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1233                 uint32_t shl_c0;
1234
1235                 MLX5_ASSERT(msk_c0);
1236 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1237                 shl_c0 = rte_bsf32(msk_c0);
1238 #else
1239                 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1240 #endif
1241                 mask <<= shl_c0;
1242                 data <<= shl_c0;
1243                 MLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1244         }
1245         reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1246         /* The routine expects parameters in memory as big-endian ones. */
1247         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1248                                              MLX5_MODIFICATION_TYPE_SET, error);
1249 }
1250
1251 /**
1252  * Convert modify-header set IPv4 DSCP action to DV specification.
1253  *
1254  * @param[in,out] resource
1255  *   Pointer to the modify-header resource.
1256  * @param[in] action
1257  *   Pointer to action specification.
1258  * @param[out] error
1259  *   Pointer to the error structure.
1260  *
1261  * @return
1262  *   0 on success, a negative errno value otherwise and rte_errno is set.
1263  */
1264 static int
1265 flow_dv_convert_action_modify_ipv4_dscp
1266                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1267                          const struct rte_flow_action *action,
1268                          struct rte_flow_error *error)
1269 {
1270         const struct rte_flow_action_set_dscp *conf =
1271                 (const struct rte_flow_action_set_dscp *)(action->conf);
1272         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1273         struct rte_flow_item_ipv4 ipv4;
1274         struct rte_flow_item_ipv4 ipv4_mask;
1275
1276         memset(&ipv4, 0, sizeof(ipv4));
1277         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1278         ipv4.hdr.type_of_service = conf->dscp;
1279         ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1280         item.spec = &ipv4;
1281         item.mask = &ipv4_mask;
1282         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1283                                              MLX5_MODIFICATION_TYPE_SET, error);
1284 }
1285
1286 /**
1287  * Convert modify-header set IPv6 DSCP action to DV specification.
1288  *
1289  * @param[in,out] resource
1290  *   Pointer to the modify-header resource.
1291  * @param[in] action
1292  *   Pointer to action specification.
1293  * @param[out] error
1294  *   Pointer to the error structure.
1295  *
1296  * @return
1297  *   0 on success, a negative errno value otherwise and rte_errno is set.
1298  */
1299 static int
1300 flow_dv_convert_action_modify_ipv6_dscp
1301                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1302                          const struct rte_flow_action *action,
1303                          struct rte_flow_error *error)
1304 {
1305         const struct rte_flow_action_set_dscp *conf =
1306                 (const struct rte_flow_action_set_dscp *)(action->conf);
1307         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1308         struct rte_flow_item_ipv6 ipv6;
1309         struct rte_flow_item_ipv6 ipv6_mask;
1310
1311         memset(&ipv6, 0, sizeof(ipv6));
1312         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1313         /*
1314          * Even though the DSCP bits offset of IPv6 is not byte aligned,
1315          * rdma-core only accept the DSCP bits byte aligned start from
1316          * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1317          * bits in IPv6 case as rdma-core requires byte aligned value.
1318          */
1319         ipv6.hdr.vtc_flow = conf->dscp;
1320         ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1321         item.spec = &ipv6;
1322         item.mask = &ipv6_mask;
1323         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1324                                              MLX5_MODIFICATION_TYPE_SET, error);
1325 }
1326
1327 /**
1328  * Validate MARK item.
1329  *
1330  * @param[in] dev
1331  *   Pointer to the rte_eth_dev structure.
1332  * @param[in] item
1333  *   Item specification.
1334  * @param[in] attr
1335  *   Attributes of flow that includes this item.
1336  * @param[out] error
1337  *   Pointer to error structure.
1338  *
1339  * @return
1340  *   0 on success, a negative errno value otherwise and rte_errno is set.
1341  */
1342 static int
1343 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1344                            const struct rte_flow_item *item,
1345                            const struct rte_flow_attr *attr __rte_unused,
1346                            struct rte_flow_error *error)
1347 {
1348         struct mlx5_priv *priv = dev->data->dev_private;
1349         struct mlx5_dev_config *config = &priv->config;
1350         const struct rte_flow_item_mark *spec = item->spec;
1351         const struct rte_flow_item_mark *mask = item->mask;
1352         const struct rte_flow_item_mark nic_mask = {
1353                 .id = priv->sh->dv_mark_mask,
1354         };
1355         int ret;
1356
1357         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1358                 return rte_flow_error_set(error, ENOTSUP,
1359                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1360                                           "extended metadata feature"
1361                                           " isn't enabled");
1362         if (!mlx5_flow_ext_mreg_supported(dev))
1363                 return rte_flow_error_set(error, ENOTSUP,
1364                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1365                                           "extended metadata register"
1366                                           " isn't supported");
1367         if (!nic_mask.id)
1368                 return rte_flow_error_set(error, ENOTSUP,
1369                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1370                                           "extended metadata register"
1371                                           " isn't available");
1372         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1373         if (ret < 0)
1374                 return ret;
1375         if (!spec)
1376                 return rte_flow_error_set(error, EINVAL,
1377                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1378                                           item->spec,
1379                                           "data cannot be empty");
1380         if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1381                 return rte_flow_error_set(error, EINVAL,
1382                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1383                                           &spec->id,
1384                                           "mark id exceeds the limit");
1385         if (!mask)
1386                 mask = &nic_mask;
1387         if (!mask->id)
1388                 return rte_flow_error_set(error, EINVAL,
1389                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1390                                         "mask cannot be zero");
1391
1392         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1393                                         (const uint8_t *)&nic_mask,
1394                                         sizeof(struct rte_flow_item_mark),
1395                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1396         if (ret < 0)
1397                 return ret;
1398         return 0;
1399 }
1400
1401 /**
1402  * Validate META item.
1403  *
1404  * @param[in] dev
1405  *   Pointer to the rte_eth_dev structure.
1406  * @param[in] item
1407  *   Item specification.
1408  * @param[in] attr
1409  *   Attributes of flow that includes this item.
1410  * @param[out] error
1411  *   Pointer to error structure.
1412  *
1413  * @return
1414  *   0 on success, a negative errno value otherwise and rte_errno is set.
1415  */
1416 static int
1417 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1418                            const struct rte_flow_item *item,
1419                            const struct rte_flow_attr *attr,
1420                            struct rte_flow_error *error)
1421 {
1422         struct mlx5_priv *priv = dev->data->dev_private;
1423         struct mlx5_dev_config *config = &priv->config;
1424         const struct rte_flow_item_meta *spec = item->spec;
1425         const struct rte_flow_item_meta *mask = item->mask;
1426         struct rte_flow_item_meta nic_mask = {
1427                 .data = UINT32_MAX
1428         };
1429         int reg;
1430         int ret;
1431
1432         if (!spec)
1433                 return rte_flow_error_set(error, EINVAL,
1434                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1435                                           item->spec,
1436                                           "data cannot be empty");
1437         if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1438                 if (!mlx5_flow_ext_mreg_supported(dev))
1439                         return rte_flow_error_set(error, ENOTSUP,
1440                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1441                                           "extended metadata register"
1442                                           " isn't supported");
1443                 reg = flow_dv_get_metadata_reg(dev, attr, error);
1444                 if (reg < 0)
1445                         return reg;
1446                 if (reg == REG_NON)
1447                         return rte_flow_error_set(error, ENOTSUP,
1448                                         RTE_FLOW_ERROR_TYPE_ITEM, item,
1449                                         "unavalable extended metadata register");
1450                 if (reg == REG_B)
1451                         return rte_flow_error_set(error, ENOTSUP,
1452                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1453                                           "match on reg_b "
1454                                           "isn't supported");
1455                 if (reg != REG_A)
1456                         nic_mask.data = priv->sh->dv_meta_mask;
1457         } else if (attr->transfer) {
1458                 return rte_flow_error_set(error, ENOTSUP,
1459                                         RTE_FLOW_ERROR_TYPE_ITEM, item,
1460                                         "extended metadata feature "
1461                                         "should be enabled when "
1462                                         "meta item is requested "
1463                                         "with e-switch mode ");
1464         }
1465         if (!mask)
1466                 mask = &rte_flow_item_meta_mask;
1467         if (!mask->data)
1468                 return rte_flow_error_set(error, EINVAL,
1469                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1470                                         "mask cannot be zero");
1471
1472         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1473                                         (const uint8_t *)&nic_mask,
1474                                         sizeof(struct rte_flow_item_meta),
1475                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1476         return ret;
1477 }
1478
1479 /**
1480  * Validate TAG item.
1481  *
1482  * @param[in] dev
1483  *   Pointer to the rte_eth_dev structure.
1484  * @param[in] item
1485  *   Item specification.
1486  * @param[in] attr
1487  *   Attributes of flow that includes this item.
1488  * @param[out] error
1489  *   Pointer to error structure.
1490  *
1491  * @return
1492  *   0 on success, a negative errno value otherwise and rte_errno is set.
1493  */
1494 static int
1495 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
1496                           const struct rte_flow_item *item,
1497                           const struct rte_flow_attr *attr __rte_unused,
1498                           struct rte_flow_error *error)
1499 {
1500         const struct rte_flow_item_tag *spec = item->spec;
1501         const struct rte_flow_item_tag *mask = item->mask;
1502         const struct rte_flow_item_tag nic_mask = {
1503                 .data = RTE_BE32(UINT32_MAX),
1504                 .index = 0xff,
1505         };
1506         int ret;
1507
1508         if (!mlx5_flow_ext_mreg_supported(dev))
1509                 return rte_flow_error_set(error, ENOTSUP,
1510                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1511                                           "extensive metadata register"
1512                                           " isn't supported");
1513         if (!spec)
1514                 return rte_flow_error_set(error, EINVAL,
1515                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1516                                           item->spec,
1517                                           "data cannot be empty");
1518         if (!mask)
1519                 mask = &rte_flow_item_tag_mask;
1520         if (!mask->data)
1521                 return rte_flow_error_set(error, EINVAL,
1522                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1523                                         "mask cannot be zero");
1524
1525         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1526                                         (const uint8_t *)&nic_mask,
1527                                         sizeof(struct rte_flow_item_tag),
1528                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1529         if (ret < 0)
1530                 return ret;
1531         if (mask->index != 0xff)
1532                 return rte_flow_error_set(error, EINVAL,
1533                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1534                                           "partial mask for tag index"
1535                                           " is not supported");
1536         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
1537         if (ret < 0)
1538                 return ret;
1539         MLX5_ASSERT(ret != REG_NON);
1540         return 0;
1541 }
1542
1543 /**
1544  * Validate vport item.
1545  *
1546  * @param[in] dev
1547  *   Pointer to the rte_eth_dev structure.
1548  * @param[in] item
1549  *   Item specification.
1550  * @param[in] attr
1551  *   Attributes of flow that includes this item.
1552  * @param[in] item_flags
1553  *   Bit-fields that holds the items detected until now.
1554  * @param[out] error
1555  *   Pointer to error structure.
1556  *
1557  * @return
1558  *   0 on success, a negative errno value otherwise and rte_errno is set.
1559  */
1560 static int
1561 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
1562                               const struct rte_flow_item *item,
1563                               const struct rte_flow_attr *attr,
1564                               uint64_t item_flags,
1565                               struct rte_flow_error *error)
1566 {
1567         const struct rte_flow_item_port_id *spec = item->spec;
1568         const struct rte_flow_item_port_id *mask = item->mask;
1569         const struct rte_flow_item_port_id switch_mask = {
1570                         .id = 0xffffffff,
1571         };
1572         struct mlx5_priv *esw_priv;
1573         struct mlx5_priv *dev_priv;
1574         int ret;
1575
1576         if (!attr->transfer)
1577                 return rte_flow_error_set(error, EINVAL,
1578                                           RTE_FLOW_ERROR_TYPE_ITEM,
1579                                           NULL,
1580                                           "match on port id is valid only"
1581                                           " when transfer flag is enabled");
1582         if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
1583                 return rte_flow_error_set(error, ENOTSUP,
1584                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1585                                           "multiple source ports are not"
1586                                           " supported");
1587         if (!mask)
1588                 mask = &switch_mask;
1589         if (mask->id != 0xffffffff)
1590                 return rte_flow_error_set(error, ENOTSUP,
1591                                            RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1592                                            mask,
1593                                            "no support for partial mask on"
1594                                            " \"id\" field");
1595         ret = mlx5_flow_item_acceptable
1596                                 (item, (const uint8_t *)mask,
1597                                  (const uint8_t *)&rte_flow_item_port_id_mask,
1598                                  sizeof(struct rte_flow_item_port_id),
1599                                  MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1600         if (ret)
1601                 return ret;
1602         if (!spec)
1603                 return 0;
1604         esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
1605         if (!esw_priv)
1606                 return rte_flow_error_set(error, rte_errno,
1607                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1608                                           "failed to obtain E-Switch info for"
1609                                           " port");
1610         dev_priv = mlx5_dev_to_eswitch_info(dev);
1611         if (!dev_priv)
1612                 return rte_flow_error_set(error, rte_errno,
1613                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1614                                           NULL,
1615                                           "failed to obtain E-Switch info");
1616         if (esw_priv->domain_id != dev_priv->domain_id)
1617                 return rte_flow_error_set(error, EINVAL,
1618                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1619                                           "cannot match on a port from a"
1620                                           " different E-Switch");
1621         return 0;
1622 }
1623
1624 /**
1625  * Validate VLAN item.
1626  *
1627  * @param[in] item
1628  *   Item specification.
1629  * @param[in] item_flags
1630  *   Bit-fields that holds the items detected until now.
1631  * @param[in] dev
1632  *   Ethernet device flow is being created on.
1633  * @param[out] error
1634  *   Pointer to error structure.
1635  *
1636  * @return
1637  *   0 on success, a negative errno value otherwise and rte_errno is set.
1638  */
1639 static int
1640 flow_dv_validate_item_vlan(const struct rte_flow_item *item,
1641                            uint64_t item_flags,
1642                            struct rte_eth_dev *dev,
1643                            struct rte_flow_error *error)
1644 {
1645         const struct rte_flow_item_vlan *mask = item->mask;
1646         const struct rte_flow_item_vlan nic_mask = {
1647                 .tci = RTE_BE16(UINT16_MAX),
1648                 .inner_type = RTE_BE16(UINT16_MAX),
1649                 .has_more_vlan = 1,
1650         };
1651         const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
1652         int ret;
1653         const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 |
1654                                         MLX5_FLOW_LAYER_INNER_L4) :
1655                                        (MLX5_FLOW_LAYER_OUTER_L3 |
1656                                         MLX5_FLOW_LAYER_OUTER_L4);
1657         const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
1658                                         MLX5_FLOW_LAYER_OUTER_VLAN;
1659
1660         if (item_flags & vlanm)
1661                 return rte_flow_error_set(error, EINVAL,
1662                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1663                                           "multiple VLAN layers not supported");
1664         else if ((item_flags & l34m) != 0)
1665                 return rte_flow_error_set(error, EINVAL,
1666                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1667                                           "VLAN cannot follow L3/L4 layer");
1668         if (!mask)
1669                 mask = &rte_flow_item_vlan_mask;
1670         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1671                                         (const uint8_t *)&nic_mask,
1672                                         sizeof(struct rte_flow_item_vlan),
1673                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1674         if (ret)
1675                 return ret;
1676         if (!tunnel && mask->tci != RTE_BE16(0x0fff)) {
1677                 struct mlx5_priv *priv = dev->data->dev_private;
1678
1679                 if (priv->vmwa_context) {
1680                         /*
1681                          * Non-NULL context means we have a virtual machine
1682                          * and SR-IOV enabled, we have to create VLAN interface
1683                          * to make hypervisor to setup E-Switch vport
1684                          * context correctly. We avoid creating the multiple
1685                          * VLAN interfaces, so we cannot support VLAN tag mask.
1686                          */
1687                         return rte_flow_error_set(error, EINVAL,
1688                                                   RTE_FLOW_ERROR_TYPE_ITEM,
1689                                                   item,
1690                                                   "VLAN tag mask is not"
1691                                                   " supported in virtual"
1692                                                   " environment");
1693                 }
1694         }
1695         return 0;
1696 }
1697
1698 /*
1699  * GTP flags are contained in 1 byte of the format:
1700  * -------------------------------------------
1701  * | bit   | 0 - 2   | 3  | 4   | 5 | 6 | 7  |
1702  * |-----------------------------------------|
1703  * | value | Version | PT | Res | E | S | PN |
1704  * -------------------------------------------
1705  *
1706  * Matching is supported only for GTP flags E, S, PN.
1707  */
1708 #define MLX5_GTP_FLAGS_MASK     0x07
1709
1710 /**
1711  * Validate GTP item.
1712  *
1713  * @param[in] dev
1714  *   Pointer to the rte_eth_dev structure.
1715  * @param[in] item
1716  *   Item specification.
1717  * @param[in] item_flags
1718  *   Bit-fields that holds the items detected until now.
1719  * @param[out] error
1720  *   Pointer to error structure.
1721  *
1722  * @return
1723  *   0 on success, a negative errno value otherwise and rte_errno is set.
1724  */
1725 static int
1726 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
1727                           const struct rte_flow_item *item,
1728                           uint64_t item_flags,
1729                           struct rte_flow_error *error)
1730 {
1731         struct mlx5_priv *priv = dev->data->dev_private;
1732         const struct rte_flow_item_gtp *spec = item->spec;
1733         const struct rte_flow_item_gtp *mask = item->mask;
1734         const struct rte_flow_item_gtp nic_mask = {
1735                 .v_pt_rsv_flags = MLX5_GTP_FLAGS_MASK,
1736                 .msg_type = 0xff,
1737                 .teid = RTE_BE32(0xffffffff),
1738         };
1739
1740         if (!priv->config.hca_attr.tunnel_stateless_gtp)
1741                 return rte_flow_error_set(error, ENOTSUP,
1742                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1743                                           "GTP support is not enabled");
1744         if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
1745                 return rte_flow_error_set(error, ENOTSUP,
1746                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1747                                           "multiple tunnel layers not"
1748                                           " supported");
1749         if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
1750                 return rte_flow_error_set(error, EINVAL,
1751                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1752                                           "no outer UDP layer found");
1753         if (!mask)
1754                 mask = &rte_flow_item_gtp_mask;
1755         if (spec && spec->v_pt_rsv_flags & ~MLX5_GTP_FLAGS_MASK)
1756                 return rte_flow_error_set(error, ENOTSUP,
1757                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1758                                           "Match is supported for GTP"
1759                                           " flags only");
1760         return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1761                                          (const uint8_t *)&nic_mask,
1762                                          sizeof(struct rte_flow_item_gtp),
1763                                          MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1764 }
1765
1766 /**
1767  * Validate GTP PSC item.
1768  *
1769  * @param[in] item
1770  *   Item specification.
1771  * @param[in] last_item
1772  *   Previous validated item in the pattern items.
1773  * @param[in] gtp_item
1774  *   Previous GTP item specification.
1775  * @param[in] attr
1776  *   Pointer to flow attributes.
1777  * @param[out] error
1778  *   Pointer to error structure.
1779  *
1780  * @return
1781  *   0 on success, a negative errno value otherwise and rte_errno is set.
1782  */
1783 static int
1784 flow_dv_validate_item_gtp_psc(const struct rte_flow_item *item,
1785                               uint64_t last_item,
1786                               const struct rte_flow_item *gtp_item,
1787                               const struct rte_flow_attr *attr,
1788                               struct rte_flow_error *error)
1789 {
1790         const struct rte_flow_item_gtp *gtp_spec;
1791         const struct rte_flow_item_gtp *gtp_mask;
1792         const struct rte_flow_item_gtp_psc *spec;
1793         const struct rte_flow_item_gtp_psc *mask;
1794         const struct rte_flow_item_gtp_psc nic_mask = {
1795                 .pdu_type = 0xFF,
1796                 .qfi = 0xFF,
1797         };
1798
1799         if (!gtp_item || !(last_item & MLX5_FLOW_LAYER_GTP))
1800                 return rte_flow_error_set
1801                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
1802                          "GTP PSC item must be preceded with GTP item");
1803         gtp_spec = gtp_item->spec;
1804         gtp_mask = gtp_item->mask ? gtp_item->mask : &rte_flow_item_gtp_mask;
1805         /* GTP spec and E flag is requested to match zero. */
1806         if (gtp_spec &&
1807                 (gtp_mask->v_pt_rsv_flags &
1808                 ~gtp_spec->v_pt_rsv_flags & MLX5_GTP_EXT_HEADER_FLAG))
1809                 return rte_flow_error_set
1810                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
1811                          "GTP E flag must be 1 to match GTP PSC");
1812         /* Check the flow is not created in group zero. */
1813         if (!attr->transfer && !attr->group)
1814                 return rte_flow_error_set
1815                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1816                          "GTP PSC is not supported for group 0");
1817         /* GTP spec is here and E flag is requested to match zero. */
1818         if (!item->spec)
1819                 return 0;
1820         spec = item->spec;
1821         mask = item->mask ? item->mask : &rte_flow_item_gtp_psc_mask;
1822         if (spec->pdu_type > MLX5_GTP_EXT_MAX_PDU_TYPE)
1823                 return rte_flow_error_set
1824                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
1825                          "PDU type should be smaller than 16");
1826         return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1827                                          (const uint8_t *)&nic_mask,
1828                                          sizeof(struct rte_flow_item_gtp_psc),
1829                                          MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1830 }
1831
1832 /**
1833  * Validate IPV4 item.
1834  * Use existing validation function mlx5_flow_validate_item_ipv4(), and
1835  * add specific validation of fragment_offset field,
1836  *
1837  * @param[in] item
1838  *   Item specification.
1839  * @param[in] item_flags
1840  *   Bit-fields that holds the items detected until now.
1841  * @param[out] error
1842  *   Pointer to error structure.
1843  *
1844  * @return
1845  *   0 on success, a negative errno value otherwise and rte_errno is set.
1846  */
1847 static int
1848 flow_dv_validate_item_ipv4(const struct rte_flow_item *item,
1849                            uint64_t item_flags,
1850                            uint64_t last_item,
1851                            uint16_t ether_type,
1852                            struct rte_flow_error *error)
1853 {
1854         int ret;
1855         const struct rte_flow_item_ipv4 *spec = item->spec;
1856         const struct rte_flow_item_ipv4 *last = item->last;
1857         const struct rte_flow_item_ipv4 *mask = item->mask;
1858         rte_be16_t fragment_offset_spec = 0;
1859         rte_be16_t fragment_offset_last = 0;
1860         const struct rte_flow_item_ipv4 nic_ipv4_mask = {
1861                 .hdr = {
1862                         .src_addr = RTE_BE32(0xffffffff),
1863                         .dst_addr = RTE_BE32(0xffffffff),
1864                         .type_of_service = 0xff,
1865                         .fragment_offset = RTE_BE16(0xffff),
1866                         .next_proto_id = 0xff,
1867                         .time_to_live = 0xff,
1868                 },
1869         };
1870
1871         ret = mlx5_flow_validate_item_ipv4(item, item_flags, last_item,
1872                                            ether_type, &nic_ipv4_mask,
1873                                            MLX5_ITEM_RANGE_ACCEPTED, error);
1874         if (ret < 0)
1875                 return ret;
1876         if (spec && mask)
1877                 fragment_offset_spec = spec->hdr.fragment_offset &
1878                                        mask->hdr.fragment_offset;
1879         if (!fragment_offset_spec)
1880                 return 0;
1881         /*
1882          * spec and mask are valid, enforce using full mask to make sure the
1883          * complete value is used correctly.
1884          */
1885         if ((mask->hdr.fragment_offset & RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
1886                         != RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
1887                 return rte_flow_error_set(error, EINVAL,
1888                                           RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1889                                           item, "must use full mask for"
1890                                           " fragment_offset");
1891         /*
1892          * Match on fragment_offset 0x2000 means MF is 1 and frag-offset is 0,
1893          * indicating this is 1st fragment of fragmented packet.
1894          * This is not yet supported in MLX5, return appropriate error message.
1895          */
1896         if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG))
1897                 return rte_flow_error_set(error, ENOTSUP,
1898                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1899                                           "match on first fragment not "
1900                                           "supported");
1901         if (fragment_offset_spec && !last)
1902                 return rte_flow_error_set(error, ENOTSUP,
1903                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1904                                           "specified value not supported");
1905         /* spec and last are valid, validate the specified range. */
1906         fragment_offset_last = last->hdr.fragment_offset &
1907                                mask->hdr.fragment_offset;
1908         /*
1909          * Match on fragment_offset spec 0x2001 and last 0x3fff
1910          * means MF is 1 and frag-offset is > 0.
1911          * This packet is fragment 2nd and onward, excluding last.
1912          * This is not yet supported in MLX5, return appropriate
1913          * error message.
1914          */
1915         if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG + 1) &&
1916             fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
1917                 return rte_flow_error_set(error, ENOTSUP,
1918                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
1919                                           last, "match on following "
1920                                           "fragments not supported");
1921         /*
1922          * Match on fragment_offset spec 0x0001 and last 0x1fff
1923          * means MF is 0 and frag-offset is > 0.
1924          * This packet is last fragment of fragmented packet.
1925          * This is not yet supported in MLX5, return appropriate
1926          * error message.
1927          */
1928         if (fragment_offset_spec == RTE_BE16(1) &&
1929             fragment_offset_last == RTE_BE16(RTE_IPV4_HDR_OFFSET_MASK))
1930                 return rte_flow_error_set(error, ENOTSUP,
1931                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
1932                                           last, "match on last "
1933                                           "fragment not supported");
1934         /*
1935          * Match on fragment_offset spec 0x0001 and last 0x3fff
1936          * means MF and/or frag-offset is not 0.
1937          * This is a fragmented packet.
1938          * Other range values are invalid and rejected.
1939          */
1940         if (!(fragment_offset_spec == RTE_BE16(1) &&
1941               fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK)))
1942                 return rte_flow_error_set(error, ENOTSUP,
1943                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
1944                                           "specified range not supported");
1945         return 0;
1946 }
1947
1948 /**
1949  * Validate IPV6 fragment extension item.
1950  *
1951  * @param[in] item
1952  *   Item specification.
1953  * @param[in] item_flags
1954  *   Bit-fields that holds the items detected until now.
1955  * @param[out] error
1956  *   Pointer to error structure.
1957  *
1958  * @return
1959  *   0 on success, a negative errno value otherwise and rte_errno is set.
1960  */
1961 static int
1962 flow_dv_validate_item_ipv6_frag_ext(const struct rte_flow_item *item,
1963                                     uint64_t item_flags,
1964                                     struct rte_flow_error *error)
1965 {
1966         const struct rte_flow_item_ipv6_frag_ext *spec = item->spec;
1967         const struct rte_flow_item_ipv6_frag_ext *last = item->last;
1968         const struct rte_flow_item_ipv6_frag_ext *mask = item->mask;
1969         rte_be16_t frag_data_spec = 0;
1970         rte_be16_t frag_data_last = 0;
1971         const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
1972         const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 :
1973                                       MLX5_FLOW_LAYER_OUTER_L4;
1974         int ret = 0;
1975         struct rte_flow_item_ipv6_frag_ext nic_mask = {
1976                 .hdr = {
1977                         .next_header = 0xff,
1978                         .frag_data = RTE_BE16(0xffff),
1979                 },
1980         };
1981
1982         if (item_flags & l4m)
1983                 return rte_flow_error_set(error, EINVAL,
1984                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1985                                           "ipv6 fragment extension item cannot "
1986                                           "follow L4 item.");
1987         if ((tunnel && !(item_flags & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
1988             (!tunnel && !(item_flags & MLX5_FLOW_LAYER_OUTER_L3_IPV6)))
1989                 return rte_flow_error_set(error, EINVAL,
1990                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1991                                           "ipv6 fragment extension item must "
1992                                           "follow ipv6 item");
1993         if (spec && mask)
1994                 frag_data_spec = spec->hdr.frag_data & mask->hdr.frag_data;
1995         if (!frag_data_spec)
1996                 return 0;
1997         /*
1998          * spec and mask are valid, enforce using full mask to make sure the
1999          * complete value is used correctly.
2000          */
2001         if ((mask->hdr.frag_data & RTE_BE16(RTE_IPV6_FRAG_USED_MASK)) !=
2002                                 RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2003                 return rte_flow_error_set(error, EINVAL,
2004                                           RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2005                                           item, "must use full mask for"
2006                                           " frag_data");
2007         /*
2008          * Match on frag_data 0x00001 means M is 1 and frag-offset is 0.
2009          * This is 1st fragment of fragmented packet.
2010          */
2011         if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_MF_MASK))
2012                 return rte_flow_error_set(error, ENOTSUP,
2013                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2014                                           "match on first fragment not "
2015                                           "supported");
2016         if (frag_data_spec && !last)
2017                 return rte_flow_error_set(error, EINVAL,
2018                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2019                                           "specified value not supported");
2020         ret = mlx5_flow_item_acceptable
2021                                 (item, (const uint8_t *)mask,
2022                                  (const uint8_t *)&nic_mask,
2023                                  sizeof(struct rte_flow_item_ipv6_frag_ext),
2024                                  MLX5_ITEM_RANGE_ACCEPTED, error);
2025         if (ret)
2026                 return ret;
2027         /* spec and last are valid, validate the specified range. */
2028         frag_data_last = last->hdr.frag_data & mask->hdr.frag_data;
2029         /*
2030          * Match on frag_data spec 0x0009 and last 0xfff9
2031          * means M is 1 and frag-offset is > 0.
2032          * This packet is fragment 2nd and onward, excluding last.
2033          * This is not yet supported in MLX5, return appropriate
2034          * error message.
2035          */
2036         if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN |
2037                                        RTE_IPV6_EHDR_MF_MASK) &&
2038             frag_data_last == RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2039                 return rte_flow_error_set(error, ENOTSUP,
2040                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2041                                           last, "match on following "
2042                                           "fragments not supported");
2043         /*
2044          * Match on frag_data spec 0x0008 and last 0xfff8
2045          * means M is 0 and frag-offset is > 0.
2046          * This packet is last fragment of fragmented packet.
2047          * This is not yet supported in MLX5, return appropriate
2048          * error message.
2049          */
2050         if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN) &&
2051             frag_data_last == RTE_BE16(RTE_IPV6_EHDR_FO_MASK))
2052                 return rte_flow_error_set(error, ENOTSUP,
2053                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2054                                           last, "match on last "
2055                                           "fragment not supported");
2056         /* Other range values are invalid and rejected. */
2057         return rte_flow_error_set(error, EINVAL,
2058                                   RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2059                                   "specified range not supported");
2060 }
2061
2062 /**
2063  * Validate the pop VLAN action.
2064  *
2065  * @param[in] dev
2066  *   Pointer to the rte_eth_dev structure.
2067  * @param[in] action_flags
2068  *   Holds the actions detected until now.
2069  * @param[in] action
2070  *   Pointer to the pop vlan action.
2071  * @param[in] item_flags
2072  *   The items found in this flow rule.
2073  * @param[in] attr
2074  *   Pointer to flow attributes.
2075  * @param[out] error
2076  *   Pointer to error structure.
2077  *
2078  * @return
2079  *   0 on success, a negative errno value otherwise and rte_errno is set.
2080  */
2081 static int
2082 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
2083                                  uint64_t action_flags,
2084                                  const struct rte_flow_action *action,
2085                                  uint64_t item_flags,
2086                                  const struct rte_flow_attr *attr,
2087                                  struct rte_flow_error *error)
2088 {
2089         const struct mlx5_priv *priv = dev->data->dev_private;
2090
2091         (void)action;
2092         (void)attr;
2093         if (!priv->sh->pop_vlan_action)
2094                 return rte_flow_error_set(error, ENOTSUP,
2095                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2096                                           NULL,
2097                                           "pop vlan action is not supported");
2098         if (attr->egress)
2099                 return rte_flow_error_set(error, ENOTSUP,
2100                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2101                                           NULL,
2102                                           "pop vlan action not supported for "
2103                                           "egress");
2104         if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
2105                 return rte_flow_error_set(error, ENOTSUP,
2106                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2107                                           "no support for multiple VLAN "
2108                                           "actions");
2109         /* Pop VLAN with preceding Decap requires inner header with VLAN. */
2110         if ((action_flags & MLX5_FLOW_ACTION_DECAP) &&
2111             !(item_flags & MLX5_FLOW_LAYER_INNER_VLAN))
2112                 return rte_flow_error_set(error, ENOTSUP,
2113                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2114                                           NULL,
2115                                           "cannot pop vlan after decap without "
2116                                           "match on inner vlan in the flow");
2117         /* Pop VLAN without preceding Decap requires outer header with VLAN. */
2118         if (!(action_flags & MLX5_FLOW_ACTION_DECAP) &&
2119             !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2120                 return rte_flow_error_set(error, ENOTSUP,
2121                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2122                                           NULL,
2123                                           "cannot pop vlan without a "
2124                                           "match on (outer) vlan in the flow");
2125         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2126                 return rte_flow_error_set(error, EINVAL,
2127                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2128                                           "wrong action order, port_id should "
2129                                           "be after pop VLAN action");
2130         if (!attr->transfer && priv->representor)
2131                 return rte_flow_error_set(error, ENOTSUP,
2132                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2133                                           "pop vlan action for VF representor "
2134                                           "not supported on NIC table");
2135         return 0;
2136 }
2137
2138 /**
2139  * Get VLAN default info from vlan match info.
2140  *
2141  * @param[in] items
2142  *   the list of item specifications.
2143  * @param[out] vlan
2144  *   pointer VLAN info to fill to.
2145  *
2146  * @return
2147  *   0 on success, a negative errno value otherwise and rte_errno is set.
2148  */
2149 static void
2150 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
2151                                   struct rte_vlan_hdr *vlan)
2152 {
2153         const struct rte_flow_item_vlan nic_mask = {
2154                 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
2155                                 MLX5DV_FLOW_VLAN_VID_MASK),
2156                 .inner_type = RTE_BE16(0xffff),
2157         };
2158
2159         if (items == NULL)
2160                 return;
2161         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2162                 int type = items->type;
2163
2164                 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
2165                     type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
2166                         break;
2167         }
2168         if (items->type != RTE_FLOW_ITEM_TYPE_END) {
2169                 const struct rte_flow_item_vlan *vlan_m = items->mask;
2170                 const struct rte_flow_item_vlan *vlan_v = items->spec;
2171
2172                 /* If VLAN item in pattern doesn't contain data, return here. */
2173                 if (!vlan_v)
2174                         return;
2175                 if (!vlan_m)
2176                         vlan_m = &nic_mask;
2177                 /* Only full match values are accepted */
2178                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
2179                      MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
2180                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
2181                         vlan->vlan_tci |=
2182                                 rte_be_to_cpu_16(vlan_v->tci &
2183                                                  MLX5DV_FLOW_VLAN_PCP_MASK_BE);
2184                 }
2185                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
2186                      MLX5DV_FLOW_VLAN_VID_MASK_BE) {
2187                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
2188                         vlan->vlan_tci |=
2189                                 rte_be_to_cpu_16(vlan_v->tci &
2190                                                  MLX5DV_FLOW_VLAN_VID_MASK_BE);
2191                 }
2192                 if (vlan_m->inner_type == nic_mask.inner_type)
2193                         vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
2194                                                            vlan_m->inner_type);
2195         }
2196 }
2197
2198 /**
2199  * Validate the push VLAN action.
2200  *
2201  * @param[in] dev
2202  *   Pointer to the rte_eth_dev structure.
2203  * @param[in] action_flags
2204  *   Holds the actions detected until now.
2205  * @param[in] item_flags
2206  *   The items found in this flow rule.
2207  * @param[in] action
2208  *   Pointer to the action structure.
2209  * @param[in] attr
2210  *   Pointer to flow attributes
2211  * @param[out] error
2212  *   Pointer to error structure.
2213  *
2214  * @return
2215  *   0 on success, a negative errno value otherwise and rte_errno is set.
2216  */
2217 static int
2218 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
2219                                   uint64_t action_flags,
2220                                   const struct rte_flow_item_vlan *vlan_m,
2221                                   const struct rte_flow_action *action,
2222                                   const struct rte_flow_attr *attr,
2223                                   struct rte_flow_error *error)
2224 {
2225         const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
2226         const struct mlx5_priv *priv = dev->data->dev_private;
2227
2228         if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
2229             push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
2230                 return rte_flow_error_set(error, EINVAL,
2231                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2232                                           "invalid vlan ethertype");
2233         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2234                 return rte_flow_error_set(error, EINVAL,
2235                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2236                                           "wrong action order, port_id should "
2237                                           "be after push VLAN");
2238         if (!attr->transfer && priv->representor)
2239                 return rte_flow_error_set(error, ENOTSUP,
2240                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2241                                           "push vlan action for VF representor "
2242                                           "not supported on NIC table");
2243         if (vlan_m &&
2244             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
2245             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
2246                 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
2247             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
2248             !(mlx5_flow_find_action
2249                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
2250                 return rte_flow_error_set(error, EINVAL,
2251                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2252                                           "not full match mask on VLAN PCP and "
2253                                           "there is no of_set_vlan_pcp action, "
2254                                           "push VLAN action cannot figure out "
2255                                           "PCP value");
2256         if (vlan_m &&
2257             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
2258             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
2259                 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
2260             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
2261             !(mlx5_flow_find_action
2262                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
2263                 return rte_flow_error_set(error, EINVAL,
2264                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2265                                           "not full match mask on VLAN VID and "
2266                                           "there is no of_set_vlan_vid action, "
2267                                           "push VLAN action cannot figure out "
2268                                           "VID value");
2269         (void)attr;
2270         return 0;
2271 }
2272
2273 /**
2274  * Validate the set VLAN PCP.
2275  *
2276  * @param[in] action_flags
2277  *   Holds the actions detected until now.
2278  * @param[in] actions
2279  *   Pointer to the list of actions remaining in the flow rule.
2280  * @param[out] error
2281  *   Pointer to error structure.
2282  *
2283  * @return
2284  *   0 on success, a negative errno value otherwise and rte_errno is set.
2285  */
2286 static int
2287 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
2288                                      const struct rte_flow_action actions[],
2289                                      struct rte_flow_error *error)
2290 {
2291         const struct rte_flow_action *action = actions;
2292         const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
2293
2294         if (conf->vlan_pcp > 7)
2295                 return rte_flow_error_set(error, EINVAL,
2296                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2297                                           "VLAN PCP value is too big");
2298         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
2299                 return rte_flow_error_set(error, ENOTSUP,
2300                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2301                                           "set VLAN PCP action must follow "
2302                                           "the push VLAN action");
2303         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
2304                 return rte_flow_error_set(error, ENOTSUP,
2305                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2306                                           "Multiple VLAN PCP modification are "
2307                                           "not supported");
2308         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2309                 return rte_flow_error_set(error, EINVAL,
2310                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2311                                           "wrong action order, port_id should "
2312                                           "be after set VLAN PCP");
2313         return 0;
2314 }
2315
2316 /**
2317  * Validate the set VLAN VID.
2318  *
2319  * @param[in] item_flags
2320  *   Holds the items detected in this rule.
2321  * @param[in] action_flags
2322  *   Holds the actions detected until now.
2323  * @param[in] actions
2324  *   Pointer to the list of actions remaining in the flow rule.
2325  * @param[out] error
2326  *   Pointer to error structure.
2327  *
2328  * @return
2329  *   0 on success, a negative errno value otherwise and rte_errno is set.
2330  */
2331 static int
2332 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
2333                                      uint64_t action_flags,
2334                                      const struct rte_flow_action actions[],
2335                                      struct rte_flow_error *error)
2336 {
2337         const struct rte_flow_action *action = actions;
2338         const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
2339
2340         if (rte_be_to_cpu_16(conf->vlan_vid) > 0xFFE)
2341                 return rte_flow_error_set(error, EINVAL,
2342                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2343                                           "VLAN VID value is too big");
2344         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
2345             !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2346                 return rte_flow_error_set(error, ENOTSUP,
2347                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2348                                           "set VLAN VID action must follow push"
2349                                           " VLAN action or match on VLAN item");
2350         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
2351                 return rte_flow_error_set(error, ENOTSUP,
2352                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2353                                           "Multiple VLAN VID modifications are "
2354                                           "not supported");
2355         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2356                 return rte_flow_error_set(error, EINVAL,
2357                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2358                                           "wrong action order, port_id should "
2359                                           "be after set VLAN VID");
2360         return 0;
2361 }
2362
2363 /*
2364  * Validate the FLAG action.
2365  *
2366  * @param[in] dev
2367  *   Pointer to the rte_eth_dev structure.
2368  * @param[in] action_flags
2369  *   Holds the actions detected until now.
2370  * @param[in] attr
2371  *   Pointer to flow attributes
2372  * @param[out] error
2373  *   Pointer to error structure.
2374  *
2375  * @return
2376  *   0 on success, a negative errno value otherwise and rte_errno is set.
2377  */
2378 static int
2379 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
2380                              uint64_t action_flags,
2381                              const struct rte_flow_attr *attr,
2382                              struct rte_flow_error *error)
2383 {
2384         struct mlx5_priv *priv = dev->data->dev_private;
2385         struct mlx5_dev_config *config = &priv->config;
2386         int ret;
2387
2388         /* Fall back if no extended metadata register support. */
2389         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2390                 return mlx5_flow_validate_action_flag(action_flags, attr,
2391                                                       error);
2392         /* Extensive metadata mode requires registers. */
2393         if (!mlx5_flow_ext_mreg_supported(dev))
2394                 return rte_flow_error_set(error, ENOTSUP,
2395                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2396                                           "no metadata registers "
2397                                           "to support flag action");
2398         if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
2399                 return rte_flow_error_set(error, ENOTSUP,
2400                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2401                                           "extended metadata register"
2402                                           " isn't available");
2403         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2404         if (ret < 0)
2405                 return ret;
2406         MLX5_ASSERT(ret > 0);
2407         if (action_flags & MLX5_FLOW_ACTION_MARK)
2408                 return rte_flow_error_set(error, EINVAL,
2409                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2410                                           "can't mark and flag in same flow");
2411         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2412                 return rte_flow_error_set(error, EINVAL,
2413                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2414                                           "can't have 2 flag"
2415                                           " actions in same flow");
2416         return 0;
2417 }
2418
2419 /**
2420  * Validate MARK action.
2421  *
2422  * @param[in] dev
2423  *   Pointer to the rte_eth_dev structure.
2424  * @param[in] action
2425  *   Pointer to action.
2426  * @param[in] action_flags
2427  *   Holds the actions detected until now.
2428  * @param[in] attr
2429  *   Pointer to flow attributes
2430  * @param[out] error
2431  *   Pointer to error structure.
2432  *
2433  * @return
2434  *   0 on success, a negative errno value otherwise and rte_errno is set.
2435  */
2436 static int
2437 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
2438                              const struct rte_flow_action *action,
2439                              uint64_t action_flags,
2440                              const struct rte_flow_attr *attr,
2441                              struct rte_flow_error *error)
2442 {
2443         struct mlx5_priv *priv = dev->data->dev_private;
2444         struct mlx5_dev_config *config = &priv->config;
2445         const struct rte_flow_action_mark *mark = action->conf;
2446         int ret;
2447
2448         /* Fall back if no extended metadata register support. */
2449         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2450                 return mlx5_flow_validate_action_mark(action, action_flags,
2451                                                       attr, error);
2452         /* Extensive metadata mode requires registers. */
2453         if (!mlx5_flow_ext_mreg_supported(dev))
2454                 return rte_flow_error_set(error, ENOTSUP,
2455                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2456                                           "no metadata registers "
2457                                           "to support mark action");
2458         if (!priv->sh->dv_mark_mask)
2459                 return rte_flow_error_set(error, ENOTSUP,
2460                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2461                                           "extended metadata register"
2462                                           " isn't available");
2463         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2464         if (ret < 0)
2465                 return ret;
2466         MLX5_ASSERT(ret > 0);
2467         if (!mark)
2468                 return rte_flow_error_set(error, EINVAL,
2469                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2470                                           "configuration cannot be null");
2471         if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
2472                 return rte_flow_error_set(error, EINVAL,
2473                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2474                                           &mark->id,
2475                                           "mark id exceeds the limit");
2476         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2477                 return rte_flow_error_set(error, EINVAL,
2478                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2479                                           "can't flag and mark in same flow");
2480         if (action_flags & MLX5_FLOW_ACTION_MARK)
2481                 return rte_flow_error_set(error, EINVAL,
2482                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2483                                           "can't have 2 mark actions in same"
2484                                           " flow");
2485         return 0;
2486 }
2487
2488 /**
2489  * Validate SET_META action.
2490  *
2491  * @param[in] dev
2492  *   Pointer to the rte_eth_dev structure.
2493  * @param[in] action
2494  *   Pointer to the action structure.
2495  * @param[in] action_flags
2496  *   Holds the actions detected until now.
2497  * @param[in] attr
2498  *   Pointer to flow attributes
2499  * @param[out] error
2500  *   Pointer to error structure.
2501  *
2502  * @return
2503  *   0 on success, a negative errno value otherwise and rte_errno is set.
2504  */
2505 static int
2506 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
2507                                  const struct rte_flow_action *action,
2508                                  uint64_t action_flags __rte_unused,
2509                                  const struct rte_flow_attr *attr,
2510                                  struct rte_flow_error *error)
2511 {
2512         const struct rte_flow_action_set_meta *conf;
2513         uint32_t nic_mask = UINT32_MAX;
2514         int reg;
2515
2516         if (!mlx5_flow_ext_mreg_supported(dev))
2517                 return rte_flow_error_set(error, ENOTSUP,
2518                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2519                                           "extended metadata register"
2520                                           " isn't supported");
2521         reg = flow_dv_get_metadata_reg(dev, attr, error);
2522         if (reg < 0)
2523                 return reg;
2524         if (reg == REG_NON)
2525                 return rte_flow_error_set(error, ENOTSUP,
2526                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2527                                           "unavalable extended metadata register");
2528         if (reg != REG_A && reg != REG_B) {
2529                 struct mlx5_priv *priv = dev->data->dev_private;
2530
2531                 nic_mask = priv->sh->dv_meta_mask;
2532         }
2533         if (!(action->conf))
2534                 return rte_flow_error_set(error, EINVAL,
2535                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2536                                           "configuration cannot be null");
2537         conf = (const struct rte_flow_action_set_meta *)action->conf;
2538         if (!conf->mask)
2539                 return rte_flow_error_set(error, EINVAL,
2540                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2541                                           "zero mask doesn't have any effect");
2542         if (conf->mask & ~nic_mask)
2543                 return rte_flow_error_set(error, EINVAL,
2544                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2545                                           "meta data must be within reg C0");
2546         return 0;
2547 }
2548
2549 /**
2550  * Validate SET_TAG action.
2551  *
2552  * @param[in] dev
2553  *   Pointer to the rte_eth_dev structure.
2554  * @param[in] action
2555  *   Pointer to the action structure.
2556  * @param[in] action_flags
2557  *   Holds the actions detected until now.
2558  * @param[in] attr
2559  *   Pointer to flow attributes
2560  * @param[out] error
2561  *   Pointer to error structure.
2562  *
2563  * @return
2564  *   0 on success, a negative errno value otherwise and rte_errno is set.
2565  */
2566 static int
2567 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
2568                                 const struct rte_flow_action *action,
2569                                 uint64_t action_flags,
2570                                 const struct rte_flow_attr *attr,
2571                                 struct rte_flow_error *error)
2572 {
2573         const struct rte_flow_action_set_tag *conf;
2574         const uint64_t terminal_action_flags =
2575                 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
2576                 MLX5_FLOW_ACTION_RSS;
2577         int ret;
2578
2579         if (!mlx5_flow_ext_mreg_supported(dev))
2580                 return rte_flow_error_set(error, ENOTSUP,
2581                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2582                                           "extensive metadata register"
2583                                           " isn't supported");
2584         if (!(action->conf))
2585                 return rte_flow_error_set(error, EINVAL,
2586                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2587                                           "configuration cannot be null");
2588         conf = (const struct rte_flow_action_set_tag *)action->conf;
2589         if (!conf->mask)
2590                 return rte_flow_error_set(error, EINVAL,
2591                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2592                                           "zero mask doesn't have any effect");
2593         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
2594         if (ret < 0)
2595                 return ret;
2596         if (!attr->transfer && attr->ingress &&
2597             (action_flags & terminal_action_flags))
2598                 return rte_flow_error_set(error, EINVAL,
2599                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2600                                           "set_tag has no effect"
2601                                           " with terminal actions");
2602         return 0;
2603 }
2604
2605 /**
2606  * Validate count action.
2607  *
2608  * @param[in] dev
2609  *   Pointer to rte_eth_dev structure.
2610  * @param[out] error
2611  *   Pointer to error structure.
2612  *
2613  * @return
2614  *   0 on success, a negative errno value otherwise and rte_errno is set.
2615  */
2616 static int
2617 flow_dv_validate_action_count(struct rte_eth_dev *dev,
2618                               struct rte_flow_error *error)
2619 {
2620         struct mlx5_priv *priv = dev->data->dev_private;
2621
2622         if (!priv->config.devx)
2623                 goto notsup_err;
2624 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
2625         return 0;
2626 #endif
2627 notsup_err:
2628         return rte_flow_error_set
2629                       (error, ENOTSUP,
2630                        RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2631                        NULL,
2632                        "count action not supported");
2633 }
2634
2635 /**
2636  * Validate the L2 encap action.
2637  *
2638  * @param[in] dev
2639  *   Pointer to the rte_eth_dev structure.
2640  * @param[in] action_flags
2641  *   Holds the actions detected until now.
2642  * @param[in] action
2643  *   Pointer to the action structure.
2644  * @param[in] attr
2645  *   Pointer to flow attributes.
2646  * @param[out] error
2647  *   Pointer to error structure.
2648  *
2649  * @return
2650  *   0 on success, a negative errno value otherwise and rte_errno is set.
2651  */
2652 static int
2653 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
2654                                  uint64_t action_flags,
2655                                  const struct rte_flow_action *action,
2656                                  const struct rte_flow_attr *attr,
2657                                  struct rte_flow_error *error)
2658 {
2659         const struct mlx5_priv *priv = dev->data->dev_private;
2660
2661         if (!(action->conf))
2662                 return rte_flow_error_set(error, EINVAL,
2663                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2664                                           "configuration cannot be null");
2665         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
2666                 return rte_flow_error_set(error, EINVAL,
2667                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2668                                           "can only have a single encap action "
2669                                           "in a flow");
2670         if (!attr->transfer && priv->representor)
2671                 return rte_flow_error_set(error, ENOTSUP,
2672                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2673                                           "encap action for VF representor "
2674                                           "not supported on NIC table");
2675         return 0;
2676 }
2677
2678 /**
2679  * Validate a decap action.
2680  *
2681  * @param[in] dev
2682  *   Pointer to the rte_eth_dev structure.
2683  * @param[in] action_flags
2684  *   Holds the actions detected until now.
2685  * @param[in] action
2686  *   Pointer to the action structure.
2687  * @param[in] item_flags
2688  *   Holds the items detected.
2689  * @param[in] attr
2690  *   Pointer to flow attributes
2691  * @param[out] error
2692  *   Pointer to error structure.
2693  *
2694  * @return
2695  *   0 on success, a negative errno value otherwise and rte_errno is set.
2696  */
2697 static int
2698 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
2699                               uint64_t action_flags,
2700                               const struct rte_flow_action *action,
2701                               const uint64_t item_flags,
2702                               const struct rte_flow_attr *attr,
2703                               struct rte_flow_error *error)
2704 {
2705         const struct mlx5_priv *priv = dev->data->dev_private;
2706
2707         if (priv->config.hca_attr.scatter_fcs_w_decap_disable &&
2708             !priv->config.decap_en)
2709                 return rte_flow_error_set(error, ENOTSUP,
2710                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2711                                           "decap is not enabled");
2712         if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
2713                 return rte_flow_error_set(error, ENOTSUP,
2714                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2715                                           action_flags &
2716                                           MLX5_FLOW_ACTION_DECAP ? "can only "
2717                                           "have a single decap action" : "decap "
2718                                           "after encap is not supported");
2719         if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
2720                 return rte_flow_error_set(error, EINVAL,
2721                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2722                                           "can't have decap action after"
2723                                           " modify action");
2724         if (attr->egress)
2725                 return rte_flow_error_set(error, ENOTSUP,
2726                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2727                                           NULL,
2728                                           "decap action not supported for "
2729                                           "egress");
2730         if (!attr->transfer && priv->representor)
2731                 return rte_flow_error_set(error, ENOTSUP,
2732                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2733                                           "decap action for VF representor "
2734                                           "not supported on NIC table");
2735         if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_DECAP &&
2736             !(item_flags & MLX5_FLOW_LAYER_VXLAN))
2737                 return rte_flow_error_set(error, ENOTSUP,
2738                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2739                                 "VXLAN item should be present for VXLAN decap");
2740         return 0;
2741 }
2742
2743 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
2744
2745 /**
2746  * Validate the raw encap and decap actions.
2747  *
2748  * @param[in] dev
2749  *   Pointer to the rte_eth_dev structure.
2750  * @param[in] decap
2751  *   Pointer to the decap action.
2752  * @param[in] encap
2753  *   Pointer to the encap action.
2754  * @param[in] attr
2755  *   Pointer to flow attributes
2756  * @param[in/out] action_flags
2757  *   Holds the actions detected until now.
2758  * @param[out] actions_n
2759  *   pointer to the number of actions counter.
2760  * @param[in] action
2761  *   Pointer to the action structure.
2762  * @param[in] item_flags
2763  *   Holds the items detected.
2764  * @param[out] error
2765  *   Pointer to error structure.
2766  *
2767  * @return
2768  *   0 on success, a negative errno value otherwise and rte_errno is set.
2769  */
2770 static int
2771 flow_dv_validate_action_raw_encap_decap
2772         (struct rte_eth_dev *dev,
2773          const struct rte_flow_action_raw_decap *decap,
2774          const struct rte_flow_action_raw_encap *encap,
2775          const struct rte_flow_attr *attr, uint64_t *action_flags,
2776          int *actions_n, const struct rte_flow_action *action,
2777          uint64_t item_flags, struct rte_flow_error *error)
2778 {
2779         const struct mlx5_priv *priv = dev->data->dev_private;
2780         int ret;
2781
2782         if (encap && (!encap->size || !encap->data))
2783                 return rte_flow_error_set(error, EINVAL,
2784                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2785                                           "raw encap data cannot be empty");
2786         if (decap && encap) {
2787                 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
2788                     encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
2789                         /* L3 encap. */
2790                         decap = NULL;
2791                 else if (encap->size <=
2792                            MLX5_ENCAPSULATION_DECISION_SIZE &&
2793                            decap->size >
2794                            MLX5_ENCAPSULATION_DECISION_SIZE)
2795                         /* L3 decap. */
2796                         encap = NULL;
2797                 else if (encap->size >
2798                            MLX5_ENCAPSULATION_DECISION_SIZE &&
2799                            decap->size >
2800                            MLX5_ENCAPSULATION_DECISION_SIZE)
2801                         /* 2 L2 actions: encap and decap. */
2802                         ;
2803                 else
2804                         return rte_flow_error_set(error,
2805                                 ENOTSUP,
2806                                 RTE_FLOW_ERROR_TYPE_ACTION,
2807                                 NULL, "unsupported too small "
2808                                 "raw decap and too small raw "
2809                                 "encap combination");
2810         }
2811         if (decap) {
2812                 ret = flow_dv_validate_action_decap(dev, *action_flags, action,
2813                                                     item_flags, attr, error);
2814                 if (ret < 0)
2815                         return ret;
2816                 *action_flags |= MLX5_FLOW_ACTION_DECAP;
2817                 ++(*actions_n);
2818         }
2819         if (encap) {
2820                 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
2821                         return rte_flow_error_set(error, ENOTSUP,
2822                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2823                                                   NULL,
2824                                                   "small raw encap size");
2825                 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
2826                         return rte_flow_error_set(error, EINVAL,
2827                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2828                                                   NULL,
2829                                                   "more than one encap action");
2830                 if (!attr->transfer && priv->representor)
2831                         return rte_flow_error_set
2832                                         (error, ENOTSUP,
2833                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2834                                          "encap action for VF representor "
2835                                          "not supported on NIC table");
2836                 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
2837                 ++(*actions_n);
2838         }
2839         return 0;
2840 }
2841
2842 /**
2843  * Match encap_decap resource.
2844  *
2845  * @param list
2846  *   Pointer to the hash list.
2847  * @param entry
2848  *   Pointer to exist resource entry object.
2849  * @param key
2850  *   Key of the new entry.
2851  * @param ctx_cb
2852  *   Pointer to new encap_decap resource.
2853  *
2854  * @return
2855  *   0 on matching, none-zero otherwise.
2856  */
2857 int
2858 flow_dv_encap_decap_match_cb(struct mlx5_hlist *list __rte_unused,
2859                              struct mlx5_hlist_entry *entry,
2860                              uint64_t key __rte_unused, void *cb_ctx)
2861 {
2862         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
2863         struct mlx5_flow_dv_encap_decap_resource *resource = ctx->data;
2864         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2865
2866         cache_resource = container_of(entry,
2867                                       struct mlx5_flow_dv_encap_decap_resource,
2868                                       entry);
2869         if (resource->reformat_type == cache_resource->reformat_type &&
2870             resource->ft_type == cache_resource->ft_type &&
2871             resource->flags == cache_resource->flags &&
2872             resource->size == cache_resource->size &&
2873             !memcmp((const void *)resource->buf,
2874                     (const void *)cache_resource->buf,
2875                     resource->size))
2876                 return 0;
2877         return -1;
2878 }
2879
2880 /**
2881  * Allocate encap_decap resource.
2882  *
2883  * @param list
2884  *   Pointer to the hash list.
2885  * @param entry
2886  *   Pointer to exist resource entry object.
2887  * @param ctx_cb
2888  *   Pointer to new encap_decap resource.
2889  *
2890  * @return
2891  *   0 on matching, none-zero otherwise.
2892  */
2893 struct mlx5_hlist_entry *
2894 flow_dv_encap_decap_create_cb(struct mlx5_hlist *list,
2895                               uint64_t key __rte_unused,
2896                               void *cb_ctx)
2897 {
2898         struct mlx5_dev_ctx_shared *sh = list->ctx;
2899         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
2900         struct mlx5dv_dr_domain *domain;
2901         struct mlx5_flow_dv_encap_decap_resource *resource = ctx->data;
2902         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2903         uint32_t idx;
2904         int ret;
2905
2906         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2907                 domain = sh->fdb_domain;
2908         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2909                 domain = sh->rx_domain;
2910         else
2911                 domain = sh->tx_domain;
2912         /* Register new encap/decap resource. */
2913         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
2914                                        &idx);
2915         if (!cache_resource) {
2916                 rte_flow_error_set(ctx->error, ENOMEM,
2917                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2918                                    "cannot allocate resource memory");
2919                 return NULL;
2920         }
2921         *cache_resource = *resource;
2922         cache_resource->idx = idx;
2923         ret = mlx5_flow_os_create_flow_action_packet_reformat
2924                                         (sh->ctx, domain, cache_resource,
2925                                          &cache_resource->action);
2926         if (ret) {
2927                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);
2928                 rte_flow_error_set(ctx->error, ENOMEM,
2929                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2930                                    NULL, "cannot create action");
2931                 return NULL;
2932         }
2933
2934         return &cache_resource->entry;
2935 }
2936
2937 /**
2938  * Find existing encap/decap resource or create and register a new one.
2939  *
2940  * @param[in, out] dev
2941  *   Pointer to rte_eth_dev structure.
2942  * @param[in, out] resource
2943  *   Pointer to encap/decap resource.
2944  * @parm[in, out] dev_flow
2945  *   Pointer to the dev_flow.
2946  * @param[out] error
2947  *   pointer to error structure.
2948  *
2949  * @return
2950  *   0 on success otherwise -errno and errno is set.
2951  */
2952 static int
2953 flow_dv_encap_decap_resource_register
2954                         (struct rte_eth_dev *dev,
2955                          struct mlx5_flow_dv_encap_decap_resource *resource,
2956                          struct mlx5_flow *dev_flow,
2957                          struct rte_flow_error *error)
2958 {
2959         struct mlx5_priv *priv = dev->data->dev_private;
2960         struct mlx5_dev_ctx_shared *sh = priv->sh;
2961         struct mlx5_hlist_entry *entry;
2962         union {
2963                 struct {
2964                         uint32_t ft_type:8;
2965                         uint32_t refmt_type:8;
2966                         /*
2967                          * Header reformat actions can be shared between
2968                          * non-root tables. One bit to indicate non-root
2969                          * table or not.
2970                          */
2971                         uint32_t is_root:1;
2972                         uint32_t reserve:15;
2973                 };
2974                 uint32_t v32;
2975         } encap_decap_key = {
2976                 {
2977                         .ft_type = resource->ft_type,
2978                         .refmt_type = resource->reformat_type,
2979                         .is_root = !!dev_flow->dv.group,
2980                         .reserve = 0,
2981                 }
2982         };
2983         struct mlx5_flow_cb_ctx ctx = {
2984                 .error = error,
2985                 .data = resource,
2986         };
2987         uint64_t key64;
2988
2989         resource->flags = dev_flow->dv.group ? 0 : 1;
2990         key64 =  __rte_raw_cksum(&encap_decap_key.v32,
2991                                  sizeof(encap_decap_key.v32), 0);
2992         if (resource->reformat_type !=
2993             MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2 &&
2994             resource->size)
2995                 key64 = __rte_raw_cksum(resource->buf, resource->size, key64);
2996         entry = mlx5_hlist_register(sh->encaps_decaps, key64, &ctx);
2997         if (!entry)
2998                 return -rte_errno;
2999         resource = container_of(entry, typeof(*resource), entry);
3000         dev_flow->dv.encap_decap = resource;
3001         dev_flow->handle->dvh.rix_encap_decap = resource->idx;
3002         return 0;
3003 }
3004
3005 /**
3006  * Find existing table jump resource or create and register a new one.
3007  *
3008  * @param[in, out] dev
3009  *   Pointer to rte_eth_dev structure.
3010  * @param[in, out] tbl
3011  *   Pointer to flow table resource.
3012  * @parm[in, out] dev_flow
3013  *   Pointer to the dev_flow.
3014  * @param[out] error
3015  *   pointer to error structure.
3016  *
3017  * @return
3018  *   0 on success otherwise -errno and errno is set.
3019  */
3020 static int
3021 flow_dv_jump_tbl_resource_register
3022                         (struct rte_eth_dev *dev __rte_unused,
3023                          struct mlx5_flow_tbl_resource *tbl,
3024                          struct mlx5_flow *dev_flow,
3025                          struct rte_flow_error *error __rte_unused)
3026 {
3027         struct mlx5_flow_tbl_data_entry *tbl_data =
3028                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
3029
3030         MLX5_ASSERT(tbl);
3031         MLX5_ASSERT(tbl_data->jump.action);
3032         dev_flow->handle->rix_jump = tbl_data->idx;
3033         dev_flow->dv.jump = &tbl_data->jump;
3034         return 0;
3035 }
3036
3037 int
3038 flow_dv_port_id_match_cb(struct mlx5_cache_list *list __rte_unused,
3039                          struct mlx5_cache_entry *entry, void *cb_ctx)
3040 {
3041         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3042         struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3043         struct mlx5_flow_dv_port_id_action_resource *res =
3044                         container_of(entry, typeof(*res), entry);
3045
3046         return ref->port_id != res->port_id;
3047 }
3048
3049 struct mlx5_cache_entry *
3050 flow_dv_port_id_create_cb(struct mlx5_cache_list *list,
3051                           struct mlx5_cache_entry *entry __rte_unused,
3052                           void *cb_ctx)
3053 {
3054         struct mlx5_dev_ctx_shared *sh = list->ctx;
3055         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3056         struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3057         struct mlx5_flow_dv_port_id_action_resource *cache;
3058         uint32_t idx;
3059         int ret;
3060
3061         /* Register new port id action resource. */
3062         cache = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID], &idx);
3063         if (!cache) {
3064                 rte_flow_error_set(ctx->error, ENOMEM,
3065                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3066                                    "cannot allocate port_id action cache memory");
3067                 return NULL;
3068         }
3069         *cache = *ref;
3070         ret = mlx5_flow_os_create_flow_action_dest_port(sh->fdb_domain,
3071                                                         ref->port_id,
3072                                                         &cache->action);
3073         if (ret) {
3074                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], idx);
3075                 rte_flow_error_set(ctx->error, ENOMEM,
3076                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3077                                    "cannot create action");
3078                 return NULL;
3079         }
3080         return &cache->entry;
3081 }
3082
3083 /**
3084  * Find existing table port ID resource or create and register a new one.
3085  *
3086  * @param[in, out] dev
3087  *   Pointer to rte_eth_dev structure.
3088  * @param[in, out] resource
3089  *   Pointer to port ID action resource.
3090  * @parm[in, out] dev_flow
3091  *   Pointer to the dev_flow.
3092  * @param[out] error
3093  *   pointer to error structure.
3094  *
3095  * @return
3096  *   0 on success otherwise -errno and errno is set.
3097  */
3098 static int
3099 flow_dv_port_id_action_resource_register
3100                         (struct rte_eth_dev *dev,
3101                          struct mlx5_flow_dv_port_id_action_resource *resource,
3102                          struct mlx5_flow *dev_flow,
3103                          struct rte_flow_error *error)
3104 {
3105         struct mlx5_priv *priv = dev->data->dev_private;
3106         struct mlx5_cache_entry *entry;
3107         struct mlx5_flow_dv_port_id_action_resource *cache;
3108         struct mlx5_flow_cb_ctx ctx = {
3109                 .error = error,
3110                 .data = resource,
3111         };
3112
3113         entry = mlx5_cache_register(&priv->sh->port_id_action_list, &ctx);
3114         if (!entry)
3115                 return -rte_errno;
3116         cache = container_of(entry, typeof(*cache), entry);
3117         dev_flow->dv.port_id_action = cache;
3118         dev_flow->handle->rix_port_id_action = cache->idx;
3119         return 0;
3120 }
3121
3122 int
3123 flow_dv_push_vlan_match_cb(struct mlx5_cache_list *list __rte_unused,
3124                          struct mlx5_cache_entry *entry, void *cb_ctx)
3125 {
3126         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3127         struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3128         struct mlx5_flow_dv_push_vlan_action_resource *res =
3129                         container_of(entry, typeof(*res), entry);
3130
3131         return ref->vlan_tag != res->vlan_tag || ref->ft_type != res->ft_type;
3132 }
3133
3134 struct mlx5_cache_entry *
3135 flow_dv_push_vlan_create_cb(struct mlx5_cache_list *list,
3136                           struct mlx5_cache_entry *entry __rte_unused,
3137                           void *cb_ctx)
3138 {
3139         struct mlx5_dev_ctx_shared *sh = list->ctx;
3140         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3141         struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3142         struct mlx5_flow_dv_push_vlan_action_resource *cache;
3143         struct mlx5dv_dr_domain *domain;
3144         uint32_t idx;
3145         int ret;
3146
3147         /* Register new port id action resource. */
3148         cache = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN], &idx);
3149         if (!cache) {
3150                 rte_flow_error_set(ctx->error, ENOMEM,
3151                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3152                                    "cannot allocate push_vlan action cache memory");
3153                 return NULL;
3154         }
3155         *cache = *ref;
3156         if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3157                 domain = sh->fdb_domain;
3158         else if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3159                 domain = sh->rx_domain;
3160         else
3161                 domain = sh->tx_domain;
3162         ret = mlx5_flow_os_create_flow_action_push_vlan(domain, ref->vlan_tag,
3163                                                         &cache->action);
3164         if (ret) {
3165                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
3166                 rte_flow_error_set(ctx->error, ENOMEM,
3167                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3168                                    "cannot create push vlan action");
3169                 return NULL;
3170         }
3171         return &cache->entry;
3172 }
3173
3174 /**
3175  * Find existing push vlan resource or create and register a new one.
3176  *
3177  * @param [in, out] dev
3178  *   Pointer to rte_eth_dev structure.
3179  * @param[in, out] resource
3180  *   Pointer to port ID action resource.
3181  * @parm[in, out] dev_flow
3182  *   Pointer to the dev_flow.
3183  * @param[out] error
3184  *   pointer to error structure.
3185  *
3186  * @return
3187  *   0 on success otherwise -errno and errno is set.
3188  */
3189 static int
3190 flow_dv_push_vlan_action_resource_register
3191                        (struct rte_eth_dev *dev,
3192                         struct mlx5_flow_dv_push_vlan_action_resource *resource,
3193                         struct mlx5_flow *dev_flow,
3194                         struct rte_flow_error *error)
3195 {
3196         struct mlx5_priv *priv = dev->data->dev_private;
3197         struct mlx5_flow_dv_push_vlan_action_resource *cache;
3198         struct mlx5_cache_entry *entry;
3199         struct mlx5_flow_cb_ctx ctx = {
3200                 .error = error,
3201                 .data = resource,
3202         };
3203
3204         entry = mlx5_cache_register(&priv->sh->push_vlan_action_list, &ctx);
3205         if (!entry)
3206                 return -rte_errno;
3207         cache = container_of(entry, typeof(*cache), entry);
3208
3209         dev_flow->handle->dvh.rix_push_vlan = cache->idx;
3210         dev_flow->dv.push_vlan_res = cache;
3211         return 0;
3212 }
3213
3214 /**
3215  * Get the size of specific rte_flow_item_type hdr size
3216  *
3217  * @param[in] item_type
3218  *   Tested rte_flow_item_type.
3219  *
3220  * @return
3221  *   sizeof struct item_type, 0 if void or irrelevant.
3222  */
3223 static size_t
3224 flow_dv_get_item_hdr_len(const enum rte_flow_item_type item_type)
3225 {
3226         size_t retval;
3227
3228         switch (item_type) {
3229         case RTE_FLOW_ITEM_TYPE_ETH:
3230                 retval = sizeof(struct rte_ether_hdr);
3231                 break;
3232         case RTE_FLOW_ITEM_TYPE_VLAN:
3233                 retval = sizeof(struct rte_vlan_hdr);
3234                 break;
3235         case RTE_FLOW_ITEM_TYPE_IPV4:
3236                 retval = sizeof(struct rte_ipv4_hdr);
3237                 break;
3238         case RTE_FLOW_ITEM_TYPE_IPV6:
3239                 retval = sizeof(struct rte_ipv6_hdr);
3240                 break;
3241         case RTE_FLOW_ITEM_TYPE_UDP:
3242                 retval = sizeof(struct rte_udp_hdr);
3243                 break;
3244         case RTE_FLOW_ITEM_TYPE_TCP:
3245                 retval = sizeof(struct rte_tcp_hdr);
3246                 break;
3247         case RTE_FLOW_ITEM_TYPE_VXLAN:
3248         case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3249                 retval = sizeof(struct rte_vxlan_hdr);
3250                 break;
3251         case RTE_FLOW_ITEM_TYPE_GRE:
3252         case RTE_FLOW_ITEM_TYPE_NVGRE:
3253                 retval = sizeof(struct rte_gre_hdr);
3254                 break;
3255         case RTE_FLOW_ITEM_TYPE_MPLS:
3256                 retval = sizeof(struct rte_mpls_hdr);
3257                 break;
3258         case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
3259         default:
3260                 retval = 0;
3261                 break;
3262         }
3263         return retval;
3264 }
3265
3266 #define MLX5_ENCAP_IPV4_VERSION         0x40
3267 #define MLX5_ENCAP_IPV4_IHL_MIN         0x05
3268 #define MLX5_ENCAP_IPV4_TTL_DEF         0x40
3269 #define MLX5_ENCAP_IPV6_VTC_FLOW        0x60000000
3270 #define MLX5_ENCAP_IPV6_HOP_LIMIT       0xff
3271 #define MLX5_ENCAP_VXLAN_FLAGS          0x08000000
3272 #define MLX5_ENCAP_VXLAN_GPE_FLAGS      0x04
3273
3274 /**
3275  * Convert the encap action data from list of rte_flow_item to raw buffer
3276  *
3277  * @param[in] items
3278  *   Pointer to rte_flow_item objects list.
3279  * @param[out] buf
3280  *   Pointer to the output buffer.
3281  * @param[out] size
3282  *   Pointer to the output buffer size.
3283  * @param[out] error
3284  *   Pointer to the error structure.
3285  *
3286  * @return
3287  *   0 on success, a negative errno value otherwise and rte_errno is set.
3288  */
3289 static int
3290 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
3291                            size_t *size, struct rte_flow_error *error)
3292 {
3293         struct rte_ether_hdr *eth = NULL;
3294         struct rte_vlan_hdr *vlan = NULL;
3295         struct rte_ipv4_hdr *ipv4 = NULL;
3296         struct rte_ipv6_hdr *ipv6 = NULL;
3297         struct rte_udp_hdr *udp = NULL;
3298         struct rte_vxlan_hdr *vxlan = NULL;
3299         struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
3300         struct rte_gre_hdr *gre = NULL;
3301         size_t len;
3302         size_t temp_size = 0;
3303
3304         if (!items)
3305                 return rte_flow_error_set(error, EINVAL,
3306                                           RTE_FLOW_ERROR_TYPE_ACTION,
3307                                           NULL, "invalid empty data");
3308         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
3309                 len = flow_dv_get_item_hdr_len(items->type);
3310                 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
3311                         return rte_flow_error_set(error, EINVAL,
3312                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3313                                                   (void *)items->type,
3314                                                   "items total size is too big"
3315                                                   " for encap action");
3316                 rte_memcpy((void *)&buf[temp_size], items->spec, len);
3317                 switch (items->type) {
3318                 case RTE_FLOW_ITEM_TYPE_ETH:
3319                         eth = (struct rte_ether_hdr *)&buf[temp_size];
3320                         break;
3321                 case RTE_FLOW_ITEM_TYPE_VLAN:
3322                         vlan = (struct rte_vlan_hdr *)&buf[temp_size];
3323                         if (!eth)
3324                                 return rte_flow_error_set(error, EINVAL,
3325                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3326                                                 (void *)items->type,
3327                                                 "eth header not found");
3328                         if (!eth->ether_type)
3329                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
3330                         break;
3331                 case RTE_FLOW_ITEM_TYPE_IPV4:
3332                         ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
3333                         if (!vlan && !eth)
3334                                 return rte_flow_error_set(error, EINVAL,
3335                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3336                                                 (void *)items->type,
3337                                                 "neither eth nor vlan"
3338                                                 " header found");
3339                         if (vlan && !vlan->eth_proto)
3340                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3341                         else if (eth && !eth->ether_type)
3342                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3343                         if (!ipv4->version_ihl)
3344                                 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
3345                                                     MLX5_ENCAP_IPV4_IHL_MIN;
3346                         if (!ipv4->time_to_live)
3347                                 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
3348                         break;
3349                 case RTE_FLOW_ITEM_TYPE_IPV6:
3350                         ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
3351                         if (!vlan && !eth)
3352                                 return rte_flow_error_set(error, EINVAL,
3353                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3354                                                 (void *)items->type,
3355                                                 "neither eth nor vlan"
3356                                                 " header found");
3357                         if (vlan && !vlan->eth_proto)
3358                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3359                         else if (eth && !eth->ether_type)
3360                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3361                         if (!ipv6->vtc_flow)
3362                                 ipv6->vtc_flow =
3363                                         RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
3364                         if (!ipv6->hop_limits)
3365                                 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
3366                         break;
3367                 case RTE_FLOW_ITEM_TYPE_UDP:
3368                         udp = (struct rte_udp_hdr *)&buf[temp_size];
3369                         if (!ipv4 && !ipv6)
3370                                 return rte_flow_error_set(error, EINVAL,
3371                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3372                                                 (void *)items->type,
3373                                                 "ip header not found");
3374                         if (ipv4 && !ipv4->next_proto_id)
3375                                 ipv4->next_proto_id = IPPROTO_UDP;
3376                         else if (ipv6 && !ipv6->proto)
3377                                 ipv6->proto = IPPROTO_UDP;
3378                         break;
3379                 case RTE_FLOW_ITEM_TYPE_VXLAN:
3380                         vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
3381                         if (!udp)
3382                                 return rte_flow_error_set(error, EINVAL,
3383                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3384                                                 (void *)items->type,
3385                                                 "udp header not found");
3386                         if (!udp->dst_port)
3387                                 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
3388                         if (!vxlan->vx_flags)
3389                                 vxlan->vx_flags =
3390                                         RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
3391                         break;
3392                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3393                         vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
3394                         if (!udp)
3395                                 return rte_flow_error_set(error, EINVAL,
3396                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3397                                                 (void *)items->type,
3398                                                 "udp header not found");
3399                         if (!vxlan_gpe->proto)
3400                                 return rte_flow_error_set(error, EINVAL,
3401                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3402                                                 (void *)items->type,
3403                                                 "next protocol not found");
3404                         if (!udp->dst_port)
3405                                 udp->dst_port =
3406                                         RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
3407                         if (!vxlan_gpe->vx_flags)
3408                                 vxlan_gpe->vx_flags =
3409                                                 MLX5_ENCAP_VXLAN_GPE_FLAGS;
3410                         break;
3411                 case RTE_FLOW_ITEM_TYPE_GRE:
3412                 case RTE_FLOW_ITEM_TYPE_NVGRE:
3413                         gre = (struct rte_gre_hdr *)&buf[temp_size];
3414                         if (!gre->proto)
3415                                 return rte_flow_error_set(error, EINVAL,
3416                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3417                                                 (void *)items->type,
3418                                                 "next protocol not found");
3419                         if (!ipv4 && !ipv6)
3420                                 return rte_flow_error_set(error, EINVAL,
3421                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3422                                                 (void *)items->type,
3423                                                 "ip header not found");
3424                         if (ipv4 && !ipv4->next_proto_id)
3425                                 ipv4->next_proto_id = IPPROTO_GRE;
3426                         else if (ipv6 && !ipv6->proto)
3427                                 ipv6->proto = IPPROTO_GRE;
3428                         break;
3429                 case RTE_FLOW_ITEM_TYPE_VOID:
3430                         break;
3431                 default:
3432                         return rte_flow_error_set(error, EINVAL,
3433                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3434                                                   (void *)items->type,
3435                                                   "unsupported item type");
3436                         break;
3437                 }
3438                 temp_size += len;
3439         }
3440         *size = temp_size;
3441         return 0;
3442 }
3443
3444 static int
3445 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
3446 {
3447         struct rte_ether_hdr *eth = NULL;
3448         struct rte_vlan_hdr *vlan = NULL;
3449         struct rte_ipv6_hdr *ipv6 = NULL;
3450         struct rte_udp_hdr *udp = NULL;
3451         char *next_hdr;
3452         uint16_t proto;
3453
3454         eth = (struct rte_ether_hdr *)data;
3455         next_hdr = (char *)(eth + 1);
3456         proto = RTE_BE16(eth->ether_type);
3457
3458         /* VLAN skipping */
3459         while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
3460                 vlan = (struct rte_vlan_hdr *)next_hdr;
3461                 proto = RTE_BE16(vlan->eth_proto);
3462                 next_hdr += sizeof(struct rte_vlan_hdr);
3463         }
3464
3465         /* HW calculates IPv4 csum. no need to proceed */
3466         if (proto == RTE_ETHER_TYPE_IPV4)
3467                 return 0;
3468
3469         /* non IPv4/IPv6 header. not supported */
3470         if (proto != RTE_ETHER_TYPE_IPV6) {
3471                 return rte_flow_error_set(error, ENOTSUP,
3472                                           RTE_FLOW_ERROR_TYPE_ACTION,
3473                                           NULL, "Cannot offload non IPv4/IPv6");
3474         }
3475
3476         ipv6 = (struct rte_ipv6_hdr *)next_hdr;
3477
3478         /* ignore non UDP */
3479         if (ipv6->proto != IPPROTO_UDP)
3480                 return 0;
3481
3482         udp = (struct rte_udp_hdr *)(ipv6 + 1);
3483         udp->dgram_cksum = 0;
3484
3485         return 0;
3486 }
3487
3488 /**
3489  * Convert L2 encap action to DV specification.
3490  *
3491  * @param[in] dev
3492  *   Pointer to rte_eth_dev structure.
3493  * @param[in] action
3494  *   Pointer to action structure.
3495  * @param[in, out] dev_flow
3496  *   Pointer to the mlx5_flow.
3497  * @param[in] transfer
3498  *   Mark if the flow is E-Switch flow.
3499  * @param[out] error
3500  *   Pointer to the error structure.
3501  *
3502  * @return
3503  *   0 on success, a negative errno value otherwise and rte_errno is set.
3504  */
3505 static int
3506 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
3507                                const struct rte_flow_action *action,
3508                                struct mlx5_flow *dev_flow,
3509                                uint8_t transfer,
3510                                struct rte_flow_error *error)
3511 {
3512         const struct rte_flow_item *encap_data;
3513         const struct rte_flow_action_raw_encap *raw_encap_data;
3514         struct mlx5_flow_dv_encap_decap_resource res = {
3515                 .reformat_type =
3516                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
3517                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3518                                       MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
3519         };
3520
3521         if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
3522                 raw_encap_data =
3523                         (const struct rte_flow_action_raw_encap *)action->conf;
3524                 res.size = raw_encap_data->size;
3525                 memcpy(res.buf, raw_encap_data->data, res.size);
3526         } else {
3527                 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
3528                         encap_data =
3529                                 ((const struct rte_flow_action_vxlan_encap *)
3530                                                 action->conf)->definition;
3531                 else
3532                         encap_data =
3533                                 ((const struct rte_flow_action_nvgre_encap *)
3534                                                 action->conf)->definition;
3535                 if (flow_dv_convert_encap_data(encap_data, res.buf,
3536                                                &res.size, error))
3537                         return -rte_errno;
3538         }
3539         if (flow_dv_zero_encap_udp_csum(res.buf, error))
3540                 return -rte_errno;
3541         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3542                 return rte_flow_error_set(error, EINVAL,
3543                                           RTE_FLOW_ERROR_TYPE_ACTION,
3544                                           NULL, "can't create L2 encap action");
3545         return 0;
3546 }
3547
3548 /**
3549  * Convert L2 decap action to DV specification.
3550  *
3551  * @param[in] dev
3552  *   Pointer to rte_eth_dev structure.
3553  * @param[in, out] dev_flow
3554  *   Pointer to the mlx5_flow.
3555  * @param[in] transfer
3556  *   Mark if the flow is E-Switch flow.
3557  * @param[out] error
3558  *   Pointer to the error structure.
3559  *
3560  * @return
3561  *   0 on success, a negative errno value otherwise and rte_errno is set.
3562  */
3563 static int
3564 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
3565                                struct mlx5_flow *dev_flow,
3566                                uint8_t transfer,
3567                                struct rte_flow_error *error)
3568 {
3569         struct mlx5_flow_dv_encap_decap_resource res = {
3570                 .size = 0,
3571                 .reformat_type =
3572                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
3573                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3574                                       MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
3575         };
3576
3577         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3578                 return rte_flow_error_set(error, EINVAL,
3579                                           RTE_FLOW_ERROR_TYPE_ACTION,
3580                                           NULL, "can't create L2 decap action");
3581         return 0;
3582 }
3583
3584 /**
3585  * Convert raw decap/encap (L3 tunnel) action to DV specification.
3586  *
3587  * @param[in] dev
3588  *   Pointer to rte_eth_dev structure.
3589  * @param[in] action
3590  *   Pointer to action structure.
3591  * @param[in, out] dev_flow
3592  *   Pointer to the mlx5_flow.
3593  * @param[in] attr
3594  *   Pointer to the flow attributes.
3595  * @param[out] error
3596  *   Pointer to the error structure.
3597  *
3598  * @return
3599  *   0 on success, a negative errno value otherwise and rte_errno is set.
3600  */
3601 static int
3602 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
3603                                 const struct rte_flow_action *action,
3604                                 struct mlx5_flow *dev_flow,
3605                                 const struct rte_flow_attr *attr,
3606                                 struct rte_flow_error *error)
3607 {
3608         const struct rte_flow_action_raw_encap *encap_data;
3609         struct mlx5_flow_dv_encap_decap_resource res;
3610
3611         memset(&res, 0, sizeof(res));
3612         encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
3613         res.size = encap_data->size;
3614         memcpy(res.buf, encap_data->data, res.size);
3615         res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
3616                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
3617                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
3618         if (attr->transfer)
3619                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3620         else
3621                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3622                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3623         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3624                 return rte_flow_error_set(error, EINVAL,
3625                                           RTE_FLOW_ERROR_TYPE_ACTION,
3626                                           NULL, "can't create encap action");
3627         return 0;
3628 }
3629
3630 /**
3631  * Create action push VLAN.
3632  *
3633  * @param[in] dev
3634  *   Pointer to rte_eth_dev structure.
3635  * @param[in] attr
3636  *   Pointer to the flow attributes.
3637  * @param[in] vlan
3638  *   Pointer to the vlan to push to the Ethernet header.
3639  * @param[in, out] dev_flow
3640  *   Pointer to the mlx5_flow.
3641  * @param[out] error
3642  *   Pointer to the error structure.
3643  *
3644  * @return
3645  *   0 on success, a negative errno value otherwise and rte_errno is set.
3646  */
3647 static int
3648 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
3649                                 const struct rte_flow_attr *attr,
3650                                 const struct rte_vlan_hdr *vlan,
3651                                 struct mlx5_flow *dev_flow,
3652                                 struct rte_flow_error *error)
3653 {
3654         struct mlx5_flow_dv_push_vlan_action_resource res;
3655
3656         memset(&res, 0, sizeof(res));
3657         res.vlan_tag =
3658                 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
3659                                  vlan->vlan_tci);
3660         if (attr->transfer)
3661                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3662         else
3663                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3664                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3665         return flow_dv_push_vlan_action_resource_register
3666                                             (dev, &res, dev_flow, error);
3667 }
3668
3669 /**
3670  * Validate the modify-header actions.
3671  *
3672  * @param[in] action_flags
3673  *   Holds the actions detected until now.
3674  * @param[in] action
3675  *   Pointer to the modify action.
3676  * @param[out] error
3677  *   Pointer to error structure.
3678  *
3679  * @return
3680  *   0 on success, a negative errno value otherwise and rte_errno is set.
3681  */
3682 static int
3683 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
3684                                    const struct rte_flow_action *action,
3685                                    struct rte_flow_error *error)
3686 {
3687         if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
3688                 return rte_flow_error_set(error, EINVAL,
3689                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3690                                           NULL, "action configuration not set");
3691         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3692                 return rte_flow_error_set(error, EINVAL,
3693                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3694                                           "can't have encap action before"
3695                                           " modify action");
3696         return 0;
3697 }
3698
3699 /**
3700  * Validate the modify-header MAC address actions.
3701  *
3702  * @param[in] action_flags
3703  *   Holds the actions detected until now.
3704  * @param[in] action
3705  *   Pointer to the modify action.
3706  * @param[in] item_flags
3707  *   Holds the items detected.
3708  * @param[out] error
3709  *   Pointer to error structure.
3710  *
3711  * @return
3712  *   0 on success, a negative errno value otherwise and rte_errno is set.
3713  */
3714 static int
3715 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
3716                                    const struct rte_flow_action *action,
3717                                    const uint64_t item_flags,
3718                                    struct rte_flow_error *error)
3719 {
3720         int ret = 0;
3721
3722         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3723         if (!ret) {
3724                 if (!(item_flags & MLX5_FLOW_LAYER_L2))
3725                         return rte_flow_error_set(error, EINVAL,
3726                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3727                                                   NULL,
3728                                                   "no L2 item in pattern");
3729         }
3730         return ret;
3731 }
3732
3733 /**
3734  * Validate the modify-header IPv4 address actions.
3735  *
3736  * @param[in] action_flags
3737  *   Holds the actions detected until now.
3738  * @param[in] action
3739  *   Pointer to the modify action.
3740  * @param[in] item_flags
3741  *   Holds the items detected.
3742  * @param[out] error
3743  *   Pointer to error structure.
3744  *
3745  * @return
3746  *   0 on success, a negative errno value otherwise and rte_errno is set.
3747  */
3748 static int
3749 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
3750                                     const struct rte_flow_action *action,
3751                                     const uint64_t item_flags,
3752                                     struct rte_flow_error *error)
3753 {
3754         int ret = 0;
3755         uint64_t layer;
3756
3757         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3758         if (!ret) {
3759                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3760                                  MLX5_FLOW_LAYER_INNER_L3_IPV4 :
3761                                  MLX5_FLOW_LAYER_OUTER_L3_IPV4;
3762                 if (!(item_flags & layer))
3763                         return rte_flow_error_set(error, EINVAL,
3764                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3765                                                   NULL,
3766                                                   "no ipv4 item in pattern");
3767         }
3768         return ret;
3769 }
3770
3771 /**
3772  * Validate the modify-header IPv6 address actions.
3773  *
3774  * @param[in] action_flags
3775  *   Holds the actions detected until now.
3776  * @param[in] action
3777  *   Pointer to the modify action.
3778  * @param[in] item_flags
3779  *   Holds the items detected.
3780  * @param[out] error
3781  *   Pointer to error structure.
3782  *
3783  * @return
3784  *   0 on success, a negative errno value otherwise and rte_errno is set.
3785  */
3786 static int
3787 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
3788                                     const struct rte_flow_action *action,
3789                                     const uint64_t item_flags,
3790                                     struct rte_flow_error *error)
3791 {
3792         int ret = 0;
3793         uint64_t layer;
3794
3795         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3796         if (!ret) {
3797                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3798                                  MLX5_FLOW_LAYER_INNER_L3_IPV6 :
3799                                  MLX5_FLOW_LAYER_OUTER_L3_IPV6;
3800                 if (!(item_flags & layer))
3801                         return rte_flow_error_set(error, EINVAL,
3802                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3803                                                   NULL,
3804                                                   "no ipv6 item in pattern");
3805         }
3806         return ret;
3807 }
3808
3809 /**
3810  * Validate the modify-header TP actions.
3811  *
3812  * @param[in] action_flags
3813  *   Holds the actions detected until now.
3814  * @param[in] action
3815  *   Pointer to the modify action.
3816  * @param[in] item_flags
3817  *   Holds the items detected.
3818  * @param[out] error
3819  *   Pointer to error structure.
3820  *
3821  * @return
3822  *   0 on success, a negative errno value otherwise and rte_errno is set.
3823  */
3824 static int
3825 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
3826                                   const struct rte_flow_action *action,
3827                                   const uint64_t item_flags,
3828                                   struct rte_flow_error *error)
3829 {
3830         int ret = 0;
3831         uint64_t layer;
3832
3833         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3834         if (!ret) {
3835                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3836                                  MLX5_FLOW_LAYER_INNER_L4 :
3837                                  MLX5_FLOW_LAYER_OUTER_L4;
3838                 if (!(item_flags & layer))
3839                         return rte_flow_error_set(error, EINVAL,
3840                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3841                                                   NULL, "no transport layer "
3842                                                   "in pattern");
3843         }
3844         return ret;
3845 }
3846
3847 /**
3848  * Validate the modify-header actions of increment/decrement
3849  * TCP Sequence-number.
3850  *
3851  * @param[in] action_flags
3852  *   Holds the actions detected until now.
3853  * @param[in] action
3854  *   Pointer to the modify action.
3855  * @param[in] item_flags
3856  *   Holds the items detected.
3857  * @param[out] error
3858  *   Pointer to error structure.
3859  *
3860  * @return
3861  *   0 on success, a negative errno value otherwise and rte_errno is set.
3862  */
3863 static int
3864 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
3865                                        const struct rte_flow_action *action,
3866                                        const uint64_t item_flags,
3867                                        struct rte_flow_error *error)
3868 {
3869         int ret = 0;
3870         uint64_t layer;
3871
3872         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3873         if (!ret) {
3874                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3875                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
3876                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
3877                 if (!(item_flags & layer))
3878                         return rte_flow_error_set(error, EINVAL,
3879                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3880                                                   NULL, "no TCP item in"
3881                                                   " pattern");
3882                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
3883                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
3884                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
3885                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
3886                         return rte_flow_error_set(error, EINVAL,
3887                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3888                                                   NULL,
3889                                                   "cannot decrease and increase"
3890                                                   " TCP sequence number"
3891                                                   " at the same time");
3892         }
3893         return ret;
3894 }
3895
3896 /**
3897  * Validate the modify-header actions of increment/decrement
3898  * TCP Acknowledgment number.
3899  *
3900  * @param[in] action_flags
3901  *   Holds the actions detected until now.
3902  * @param[in] action
3903  *   Pointer to the modify action.
3904  * @param[in] item_flags
3905  *   Holds the items detected.
3906  * @param[out] error
3907  *   Pointer to error structure.
3908  *
3909  * @return
3910  *   0 on success, a negative errno value otherwise and rte_errno is set.
3911  */
3912 static int
3913 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
3914                                        const struct rte_flow_action *action,
3915                                        const uint64_t item_flags,
3916                                        struct rte_flow_error *error)
3917 {
3918         int ret = 0;
3919         uint64_t layer;
3920
3921         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3922         if (!ret) {
3923                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3924                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
3925                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
3926                 if (!(item_flags & layer))
3927                         return rte_flow_error_set(error, EINVAL,
3928                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3929                                                   NULL, "no TCP item in"
3930                                                   " pattern");
3931                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
3932                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
3933                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
3934                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
3935                         return rte_flow_error_set(error, EINVAL,
3936                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3937                                                   NULL,
3938                                                   "cannot decrease and increase"
3939                                                   " TCP acknowledgment number"
3940                                                   " at the same time");
3941         }
3942         return ret;
3943 }
3944
3945 /**
3946  * Validate the modify-header TTL actions.
3947  *
3948  * @param[in] action_flags
3949  *   Holds the actions detected until now.
3950  * @param[in] action
3951  *   Pointer to the modify action.
3952  * @param[in] item_flags
3953  *   Holds the items detected.
3954  * @param[out] error
3955  *   Pointer to error structure.
3956  *
3957  * @return
3958  *   0 on success, a negative errno value otherwise and rte_errno is set.
3959  */
3960 static int
3961 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
3962                                    const struct rte_flow_action *action,
3963                                    const uint64_t item_flags,
3964                                    struct rte_flow_error *error)
3965 {
3966         int ret = 0;
3967         uint64_t layer;
3968
3969         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3970         if (!ret) {
3971                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3972                                  MLX5_FLOW_LAYER_INNER_L3 :
3973                                  MLX5_FLOW_LAYER_OUTER_L3;
3974                 if (!(item_flags & layer))
3975                         return rte_flow_error_set(error, EINVAL,
3976                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3977                                                   NULL,
3978                                                   "no IP protocol in pattern");
3979         }
3980         return ret;
3981 }
3982
3983 /**
3984  * Validate jump action.
3985  *
3986  * @param[in] action
3987  *   Pointer to the jump action.
3988  * @param[in] action_flags
3989  *   Holds the actions detected until now.
3990  * @param[in] attributes
3991  *   Pointer to flow attributes
3992  * @param[in] external
3993  *   Action belongs to flow rule created by request external to PMD.
3994  * @param[out] error
3995  *   Pointer to error structure.
3996  *
3997  * @return
3998  *   0 on success, a negative errno value otherwise and rte_errno is set.
3999  */
4000 static int
4001 flow_dv_validate_action_jump(struct rte_eth_dev *dev,
4002                              const struct mlx5_flow_tunnel *tunnel,
4003                              const struct rte_flow_action *action,
4004                              uint64_t action_flags,
4005                              const struct rte_flow_attr *attributes,
4006                              bool external, struct rte_flow_error *error)
4007 {
4008         uint32_t target_group, table;
4009         int ret = 0;
4010         struct flow_grp_info grp_info = {
4011                 .external = !!external,
4012                 .transfer = !!attributes->transfer,
4013                 .fdb_def_rule = 1,
4014                 .std_tbl_fix = 0
4015         };
4016         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
4017                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4018                 return rte_flow_error_set(error, EINVAL,
4019                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4020                                           "can't have 2 fate actions in"
4021                                           " same flow");
4022         if (action_flags & MLX5_FLOW_ACTION_METER)
4023                 return rte_flow_error_set(error, ENOTSUP,
4024                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4025                                           "jump with meter not support");
4026         if (!action->conf)
4027                 return rte_flow_error_set(error, EINVAL,
4028                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4029                                           NULL, "action configuration not set");
4030         target_group =
4031                 ((const struct rte_flow_action_jump *)action->conf)->group;
4032         ret = mlx5_flow_group_to_table(dev, tunnel, target_group, &table,
4033                                        &grp_info, error);
4034         if (ret)
4035                 return ret;
4036         if (attributes->group == target_group &&
4037             !(action_flags & (MLX5_FLOW_ACTION_TUNNEL_SET |
4038                               MLX5_FLOW_ACTION_TUNNEL_MATCH)))
4039                 return rte_flow_error_set(error, EINVAL,
4040                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4041                                           "target group must be other than"
4042                                           " the current flow group");
4043         return 0;
4044 }
4045
4046 /*
4047  * Validate the port_id action.
4048  *
4049  * @param[in] dev
4050  *   Pointer to rte_eth_dev structure.
4051  * @param[in] action_flags
4052  *   Bit-fields that holds the actions detected until now.
4053  * @param[in] action
4054  *   Port_id RTE action structure.
4055  * @param[in] attr
4056  *   Attributes of flow that includes this action.
4057  * @param[out] error
4058  *   Pointer to error structure.
4059  *
4060  * @return
4061  *   0 on success, a negative errno value otherwise and rte_errno is set.
4062  */
4063 static int
4064 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
4065                                 uint64_t action_flags,
4066                                 const struct rte_flow_action *action,
4067                                 const struct rte_flow_attr *attr,
4068                                 struct rte_flow_error *error)
4069 {
4070         const struct rte_flow_action_port_id *port_id;
4071         struct mlx5_priv *act_priv;
4072         struct mlx5_priv *dev_priv;
4073         uint16_t port;
4074
4075         if (!attr->transfer)
4076                 return rte_flow_error_set(error, ENOTSUP,
4077                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4078                                           NULL,
4079                                           "port id action is valid in transfer"
4080                                           " mode only");
4081         if (!action || !action->conf)
4082                 return rte_flow_error_set(error, ENOTSUP,
4083                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4084                                           NULL,
4085                                           "port id action parameters must be"
4086                                           " specified");
4087         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
4088                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4089                 return rte_flow_error_set(error, EINVAL,
4090                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4091                                           "can have only one fate actions in"
4092                                           " a flow");
4093         dev_priv = mlx5_dev_to_eswitch_info(dev);
4094         if (!dev_priv)
4095                 return rte_flow_error_set(error, rte_errno,
4096                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4097                                           NULL,
4098                                           "failed to obtain E-Switch info");
4099         port_id = action->conf;
4100         port = port_id->original ? dev->data->port_id : port_id->id;
4101         act_priv = mlx5_port_to_eswitch_info(port, false);
4102         if (!act_priv)
4103                 return rte_flow_error_set
4104                                 (error, rte_errno,
4105                                  RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
4106                                  "failed to obtain E-Switch port id for port");
4107         if (act_priv->domain_id != dev_priv->domain_id)
4108                 return rte_flow_error_set
4109                                 (error, EINVAL,
4110                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4111                                  "port does not belong to"
4112                                  " E-Switch being configured");
4113         return 0;
4114 }
4115
4116 /**
4117  * Get the maximum number of modify header actions.
4118  *
4119  * @param dev
4120  *   Pointer to rte_eth_dev structure.
4121  * @param flags
4122  *   Flags bits to check if root level.
4123  *
4124  * @return
4125  *   Max number of modify header actions device can support.
4126  */
4127 static inline unsigned int
4128 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev __rte_unused,
4129                               uint64_t flags)
4130 {
4131         /*
4132          * There's no way to directly query the max capacity from FW.
4133          * The maximal value on root table should be assumed to be supported.
4134          */
4135         if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
4136                 return MLX5_MAX_MODIFY_NUM;
4137         else
4138                 return MLX5_ROOT_TBL_MODIFY_NUM;
4139 }
4140
4141 /**
4142  * Validate the meter action.
4143  *
4144  * @param[in] dev
4145  *   Pointer to rte_eth_dev structure.
4146  * @param[in] action_flags
4147  *   Bit-fields that holds the actions detected until now.
4148  * @param[in] action
4149  *   Pointer to the meter action.
4150  * @param[in] attr
4151  *   Attributes of flow that includes this action.
4152  * @param[out] error
4153  *   Pointer to error structure.
4154  *
4155  * @return
4156  *   0 on success, a negative errno value otherwise and rte_ernno is set.
4157  */
4158 static int
4159 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
4160                                 uint64_t action_flags,
4161                                 const struct rte_flow_action *action,
4162                                 const struct rte_flow_attr *attr,
4163                                 struct rte_flow_error *error)
4164 {
4165         struct mlx5_priv *priv = dev->data->dev_private;
4166         const struct rte_flow_action_meter *am = action->conf;
4167         struct mlx5_flow_meter *fm;
4168
4169         if (!am)
4170                 return rte_flow_error_set(error, EINVAL,
4171                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4172                                           "meter action conf is NULL");
4173
4174         if (action_flags & MLX5_FLOW_ACTION_METER)
4175                 return rte_flow_error_set(error, ENOTSUP,
4176                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4177                                           "meter chaining not support");
4178         if (action_flags & MLX5_FLOW_ACTION_JUMP)
4179                 return rte_flow_error_set(error, ENOTSUP,
4180                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4181                                           "meter with jump not support");
4182         if (!priv->mtr_en)
4183                 return rte_flow_error_set(error, ENOTSUP,
4184                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4185                                           NULL,
4186                                           "meter action not supported");
4187         fm = mlx5_flow_meter_find(priv, am->mtr_id);
4188         if (!fm)
4189                 return rte_flow_error_set(error, EINVAL,
4190                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4191                                           "Meter not found");
4192         if (fm->ref_cnt && (!(fm->transfer == attr->transfer ||
4193               (!fm->ingress && !attr->ingress && attr->egress) ||
4194               (!fm->egress && !attr->egress && attr->ingress))))
4195                 return rte_flow_error_set(error, EINVAL,
4196                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4197                                           "Flow attributes are either invalid "
4198                                           "or have a conflict with current "
4199                                           "meter attributes");
4200         return 0;
4201 }
4202
4203 /**
4204  * Validate the age action.
4205  *
4206  * @param[in] action_flags
4207  *   Holds the actions detected until now.
4208  * @param[in] action
4209  *   Pointer to the age action.
4210  * @param[in] dev
4211  *   Pointer to the Ethernet device structure.
4212  * @param[out] error
4213  *   Pointer to error structure.
4214  *
4215  * @return
4216  *   0 on success, a negative errno value otherwise and rte_errno is set.
4217  */
4218 static int
4219 flow_dv_validate_action_age(uint64_t action_flags,
4220                             const struct rte_flow_action *action,
4221                             struct rte_eth_dev *dev,
4222                             struct rte_flow_error *error)
4223 {
4224         struct mlx5_priv *priv = dev->data->dev_private;
4225         const struct rte_flow_action_age *age = action->conf;
4226
4227         if (!priv->config.devx || (priv->sh->cmng.counter_fallback &&
4228             !priv->sh->aso_age_mng))
4229                 return rte_flow_error_set(error, ENOTSUP,
4230                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4231                                           NULL,
4232                                           "age action not supported");
4233         if (!(action->conf))
4234                 return rte_flow_error_set(error, EINVAL,
4235                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4236                                           "configuration cannot be null");
4237         if (!(age->timeout))
4238                 return rte_flow_error_set(error, EINVAL,
4239                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4240                                           "invalid timeout value 0");
4241         if (action_flags & MLX5_FLOW_ACTION_AGE)
4242                 return rte_flow_error_set(error, EINVAL,
4243                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4244                                           "duplicate age actions set");
4245         return 0;
4246 }
4247
4248 /**
4249  * Validate the modify-header IPv4 DSCP actions.
4250  *
4251  * @param[in] action_flags
4252  *   Holds the actions detected until now.
4253  * @param[in] action
4254  *   Pointer to the modify action.
4255  * @param[in] item_flags
4256  *   Holds the items detected.
4257  * @param[out] error
4258  *   Pointer to error structure.
4259  *
4260  * @return
4261  *   0 on success, a negative errno value otherwise and rte_errno is set.
4262  */
4263 static int
4264 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
4265                                          const struct rte_flow_action *action,
4266                                          const uint64_t item_flags,
4267                                          struct rte_flow_error *error)
4268 {
4269         int ret = 0;
4270
4271         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4272         if (!ret) {
4273                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
4274                         return rte_flow_error_set(error, EINVAL,
4275                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4276                                                   NULL,
4277                                                   "no ipv4 item in pattern");
4278         }
4279         return ret;
4280 }
4281
4282 /**
4283  * Validate the modify-header IPv6 DSCP actions.
4284  *
4285  * @param[in] action_flags
4286  *   Holds the actions detected until now.
4287  * @param[in] action
4288  *   Pointer to the modify action.
4289  * @param[in] item_flags
4290  *   Holds the items detected.
4291  * @param[out] error
4292  *   Pointer to error structure.
4293  *
4294  * @return
4295  *   0 on success, a negative errno value otherwise and rte_errno is set.
4296  */
4297 static int
4298 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
4299                                          const struct rte_flow_action *action,
4300                                          const uint64_t item_flags,
4301                                          struct rte_flow_error *error)
4302 {
4303         int ret = 0;
4304
4305         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4306         if (!ret) {
4307                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
4308                         return rte_flow_error_set(error, EINVAL,
4309                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4310                                                   NULL,
4311                                                   "no ipv6 item in pattern");
4312         }
4313         return ret;
4314 }
4315
4316 /**
4317  * Match modify-header resource.
4318  *
4319  * @param list
4320  *   Pointer to the hash list.
4321  * @param entry
4322  *   Pointer to exist resource entry object.
4323  * @param key
4324  *   Key of the new entry.
4325  * @param ctx
4326  *   Pointer to new modify-header resource.
4327  *
4328  * @return
4329  *   0 on matching, non-zero otherwise.
4330  */
4331 int
4332 flow_dv_modify_match_cb(struct mlx5_hlist *list __rte_unused,
4333                         struct mlx5_hlist_entry *entry,
4334                         uint64_t key __rte_unused, void *cb_ctx)
4335 {
4336         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
4337         struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
4338         struct mlx5_flow_dv_modify_hdr_resource *resource =
4339                         container_of(entry, typeof(*resource), entry);
4340         uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
4341
4342         key_len += ref->actions_num * sizeof(ref->actions[0]);
4343         return ref->actions_num != resource->actions_num ||
4344                memcmp(&ref->ft_type, &resource->ft_type, key_len);
4345 }
4346
4347 struct mlx5_hlist_entry *
4348 flow_dv_modify_create_cb(struct mlx5_hlist *list, uint64_t key __rte_unused,
4349                          void *cb_ctx)
4350 {
4351         struct mlx5_dev_ctx_shared *sh = list->ctx;
4352         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
4353         struct mlx5dv_dr_domain *ns;
4354         struct mlx5_flow_dv_modify_hdr_resource *entry;
4355         struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
4356         int ret;
4357         uint32_t data_len = ref->actions_num * sizeof(ref->actions[0]);
4358         uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
4359
4360         entry = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*entry) + data_len, 0,
4361                             SOCKET_ID_ANY);
4362         if (!entry) {
4363                 rte_flow_error_set(ctx->error, ENOMEM,
4364                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4365                                    "cannot allocate resource memory");
4366                 return NULL;
4367         }
4368         rte_memcpy(&entry->ft_type,
4369                    RTE_PTR_ADD(ref, offsetof(typeof(*ref), ft_type)),
4370                    key_len + data_len);
4371         if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
4372                 ns = sh->fdb_domain;
4373         else if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
4374                 ns = sh->tx_domain;
4375         else
4376                 ns = sh->rx_domain;
4377         ret = mlx5_flow_os_create_flow_action_modify_header
4378                                         (sh->ctx, ns, entry,
4379                                          data_len, &entry->action);
4380         if (ret) {
4381                 mlx5_free(entry);
4382                 rte_flow_error_set(ctx->error, ENOMEM,
4383                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4384                                    NULL, "cannot create modification action");
4385                 return NULL;
4386         }
4387         return &entry->entry;
4388 }
4389
4390 /**
4391  * Validate the sample action.
4392  *
4393  * @param[in] action_flags
4394  *   Holds the actions detected until now.
4395  * @param[in] action
4396  *   Pointer to the sample action.
4397  * @param[in] dev
4398  *   Pointer to the Ethernet device structure.
4399  * @param[in] attr
4400  *   Attributes of flow that includes this action.
4401  * @param[in] item_flags
4402  *   Holds the items detected.
4403  * @param[in] rss
4404  *   Pointer to the RSS action.
4405  * @param[out] sample_rss
4406  *   Pointer to the RSS action in sample action list.
4407  * @param[out] error
4408  *   Pointer to error structure.
4409  *
4410  * @return
4411  *   0 on success, a negative errno value otherwise and rte_errno is set.
4412  */
4413 static int
4414 flow_dv_validate_action_sample(uint64_t action_flags,
4415                                const struct rte_flow_action *action,
4416                                struct rte_eth_dev *dev,
4417                                const struct rte_flow_attr *attr,
4418                                uint64_t item_flags,
4419                                const struct rte_flow_action_rss *rss,
4420                                const struct rte_flow_action_rss **sample_rss,
4421                                struct rte_flow_error *error)
4422 {
4423         struct mlx5_priv *priv = dev->data->dev_private;
4424         struct mlx5_dev_config *dev_conf = &priv->config;
4425         const struct rte_flow_action_sample *sample = action->conf;
4426         const struct rte_flow_action *act;
4427         uint64_t sub_action_flags = 0;
4428         uint16_t queue_index = 0xFFFF;
4429         int actions_n = 0;
4430         int ret;
4431
4432         if (!sample)
4433                 return rte_flow_error_set(error, EINVAL,
4434                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4435                                           "configuration cannot be NULL");
4436         if (sample->ratio == 0)
4437                 return rte_flow_error_set(error, EINVAL,
4438                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4439                                           "ratio value starts from 1");
4440         if (!priv->config.devx || (sample->ratio > 0 && !priv->sampler_en))
4441                 return rte_flow_error_set(error, ENOTSUP,
4442                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4443                                           NULL,
4444                                           "sample action not supported");
4445         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
4446                 return rte_flow_error_set(error, EINVAL,
4447                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4448                                           "Multiple sample actions not "
4449                                           "supported");
4450         if (action_flags & MLX5_FLOW_ACTION_METER)
4451                 return rte_flow_error_set(error, EINVAL,
4452                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4453                                           "wrong action order, meter should "
4454                                           "be after sample action");
4455         if (action_flags & MLX5_FLOW_ACTION_JUMP)
4456                 return rte_flow_error_set(error, EINVAL,
4457                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4458                                           "wrong action order, jump should "
4459                                           "be after sample action");
4460         act = sample->actions;
4461         for (; act->type != RTE_FLOW_ACTION_TYPE_END; act++) {
4462                 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
4463                         return rte_flow_error_set(error, ENOTSUP,
4464                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4465                                                   act, "too many actions");
4466                 switch (act->type) {
4467                 case RTE_FLOW_ACTION_TYPE_QUEUE:
4468                         ret = mlx5_flow_validate_action_queue(act,
4469                                                               sub_action_flags,
4470                                                               dev,
4471                                                               attr, error);
4472                         if (ret < 0)
4473                                 return ret;
4474                         queue_index = ((const struct rte_flow_action_queue *)
4475                                                         (act->conf))->index;
4476                         sub_action_flags |= MLX5_FLOW_ACTION_QUEUE;
4477                         ++actions_n;
4478                         break;
4479                 case RTE_FLOW_ACTION_TYPE_RSS:
4480                         *sample_rss = act->conf;
4481                         ret = mlx5_flow_validate_action_rss(act,
4482                                                             sub_action_flags,
4483                                                             dev, attr,
4484                                                             item_flags,
4485                                                             error);
4486                         if (ret < 0)
4487                                 return ret;
4488                         if (rss && *sample_rss &&
4489                             ((*sample_rss)->level != rss->level ||
4490                             (*sample_rss)->types != rss->types))
4491                                 return rte_flow_error_set(error, ENOTSUP,
4492                                         RTE_FLOW_ERROR_TYPE_ACTION,
4493                                         NULL,
4494                                         "Can't use the different RSS types "
4495                                         "or level in the same flow");
4496                         if (*sample_rss != NULL && (*sample_rss)->queue_num)
4497                                 queue_index = (*sample_rss)->queue[0];
4498                         sub_action_flags |= MLX5_FLOW_ACTION_RSS;
4499                         ++actions_n;
4500                         break;
4501                 case RTE_FLOW_ACTION_TYPE_MARK:
4502                         ret = flow_dv_validate_action_mark(dev, act,
4503                                                            sub_action_flags,
4504                                                            attr, error);
4505                         if (ret < 0)
4506                                 return ret;
4507                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY)
4508                                 sub_action_flags |= MLX5_FLOW_ACTION_MARK |
4509                                                 MLX5_FLOW_ACTION_MARK_EXT;
4510                         else
4511                                 sub_action_flags |= MLX5_FLOW_ACTION_MARK;
4512                         ++actions_n;
4513                         break;
4514                 case RTE_FLOW_ACTION_TYPE_COUNT:
4515                         ret = flow_dv_validate_action_count(dev, error);
4516                         if (ret < 0)
4517                                 return ret;
4518                         sub_action_flags |= MLX5_FLOW_ACTION_COUNT;
4519                         ++actions_n;
4520                         break;
4521                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
4522                         ret = flow_dv_validate_action_port_id(dev,
4523                                                               sub_action_flags,
4524                                                               act,
4525                                                               attr,
4526                                                               error);
4527                         if (ret)
4528                                 return ret;
4529                         sub_action_flags |= MLX5_FLOW_ACTION_PORT_ID;
4530                         ++actions_n;
4531                         break;
4532                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
4533                         ret = flow_dv_validate_action_raw_encap_decap
4534                                 (dev, NULL, act->conf, attr, &sub_action_flags,
4535                                  &actions_n, action, item_flags, error);
4536                         if (ret < 0)
4537                                 return ret;
4538                         ++actions_n;
4539                         break;
4540                 default:
4541                         return rte_flow_error_set(error, ENOTSUP,
4542                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4543                                                   NULL,
4544                                                   "Doesn't support optional "
4545                                                   "action");
4546                 }
4547         }
4548         if (attr->ingress && !attr->transfer) {
4549                 if (!(sub_action_flags & (MLX5_FLOW_ACTION_QUEUE |
4550                                           MLX5_FLOW_ACTION_RSS)))
4551                         return rte_flow_error_set(error, EINVAL,
4552                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4553                                                   NULL,
4554                                                   "Ingress must has a dest "
4555                                                   "QUEUE for Sample");
4556         } else if (attr->egress && !attr->transfer) {
4557                 return rte_flow_error_set(error, ENOTSUP,
4558                                           RTE_FLOW_ERROR_TYPE_ACTION,
4559                                           NULL,
4560                                           "Sample Only support Ingress "
4561                                           "or E-Switch");
4562         } else if (sample->actions->type != RTE_FLOW_ACTION_TYPE_END) {
4563                 MLX5_ASSERT(attr->transfer);
4564                 if (sample->ratio > 1)
4565                         return rte_flow_error_set(error, ENOTSUP,
4566                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4567                                                   NULL,
4568                                                   "E-Switch doesn't support "
4569                                                   "any optional action "
4570                                                   "for sampling");
4571                 if (sub_action_flags & MLX5_FLOW_ACTION_QUEUE)
4572                         return rte_flow_error_set(error, ENOTSUP,
4573                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4574                                                   NULL,
4575                                                   "unsupported action QUEUE");
4576                 if (sub_action_flags & MLX5_FLOW_ACTION_RSS)
4577                         return rte_flow_error_set(error, ENOTSUP,
4578                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4579                                                   NULL,
4580                                                   "unsupported action QUEUE");
4581                 if (!(sub_action_flags & MLX5_FLOW_ACTION_PORT_ID))
4582                         return rte_flow_error_set(error, EINVAL,
4583                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4584                                                   NULL,
4585                                                   "E-Switch must has a dest "
4586                                                   "port for mirroring");
4587         }
4588         /* Continue validation for Xcap actions.*/
4589         if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) &&
4590             (queue_index == 0xFFFF ||
4591              mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
4592                 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
4593                      MLX5_FLOW_XCAP_ACTIONS)
4594                         return rte_flow_error_set(error, ENOTSUP,
4595                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4596                                                   NULL, "encap and decap "
4597                                                   "combination aren't "
4598                                                   "supported");
4599                 if (!attr->transfer && attr->ingress && (sub_action_flags &
4600                                                         MLX5_FLOW_ACTION_ENCAP))
4601                         return rte_flow_error_set(error, ENOTSUP,
4602                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4603                                                   NULL, "encap is not supported"
4604                                                   " for ingress traffic");
4605         }
4606         return 0;
4607 }
4608
4609 /**
4610  * Find existing modify-header resource or create and register a new one.
4611  *
4612  * @param dev[in, out]
4613  *   Pointer to rte_eth_dev structure.
4614  * @param[in, out] resource
4615  *   Pointer to modify-header resource.
4616  * @parm[in, out] dev_flow
4617  *   Pointer to the dev_flow.
4618  * @param[out] error
4619  *   pointer to error structure.
4620  *
4621  * @return
4622  *   0 on success otherwise -errno and errno is set.
4623  */
4624 static int
4625 flow_dv_modify_hdr_resource_register
4626                         (struct rte_eth_dev *dev,
4627                          struct mlx5_flow_dv_modify_hdr_resource *resource,
4628                          struct mlx5_flow *dev_flow,
4629                          struct rte_flow_error *error)
4630 {
4631         struct mlx5_priv *priv = dev->data->dev_private;
4632         struct mlx5_dev_ctx_shared *sh = priv->sh;
4633         uint32_t key_len = sizeof(*resource) -
4634                            offsetof(typeof(*resource), ft_type) +
4635                            resource->actions_num * sizeof(resource->actions[0]);
4636         struct mlx5_hlist_entry *entry;
4637         struct mlx5_flow_cb_ctx ctx = {
4638                 .error = error,
4639                 .data = resource,
4640         };
4641         uint64_t key64;
4642
4643         resource->flags = dev_flow->dv.group ? 0 :
4644                           MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
4645         if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
4646                                     resource->flags))
4647                 return rte_flow_error_set(error, EOVERFLOW,
4648                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4649                                           "too many modify header items");
4650         key64 = __rte_raw_cksum(&resource->ft_type, key_len, 0);
4651         entry = mlx5_hlist_register(sh->modify_cmds, key64, &ctx);
4652         if (!entry)
4653                 return -rte_errno;
4654         resource = container_of(entry, typeof(*resource), entry);
4655         dev_flow->handle->dvh.modify_hdr = resource;
4656         return 0;
4657 }
4658
4659 /**
4660  * Get DV flow counter by index.
4661  *
4662  * @param[in] dev
4663  *   Pointer to the Ethernet device structure.
4664  * @param[in] idx
4665  *   mlx5 flow counter index in the container.
4666  * @param[out] ppool
4667  *   mlx5 flow counter pool in the container,
4668  *
4669  * @return
4670  *   Pointer to the counter, NULL otherwise.
4671  */
4672 static struct mlx5_flow_counter *
4673 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
4674                            uint32_t idx,
4675                            struct mlx5_flow_counter_pool **ppool)
4676 {
4677         struct mlx5_priv *priv = dev->data->dev_private;
4678         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4679         struct mlx5_flow_counter_pool *pool;
4680
4681         /* Decrease to original index and clear shared bit. */
4682         idx = (idx - 1) & (MLX5_CNT_SHARED_OFFSET - 1);
4683         MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cmng->n);
4684         pool = cmng->pools[idx / MLX5_COUNTERS_PER_POOL];
4685         MLX5_ASSERT(pool);
4686         if (ppool)
4687                 *ppool = pool;
4688         return MLX5_POOL_GET_CNT(pool, idx % MLX5_COUNTERS_PER_POOL);
4689 }
4690
4691 /**
4692  * Check the devx counter belongs to the pool.
4693  *
4694  * @param[in] pool
4695  *   Pointer to the counter pool.
4696  * @param[in] id
4697  *   The counter devx ID.
4698  *
4699  * @return
4700  *   True if counter belongs to the pool, false otherwise.
4701  */
4702 static bool
4703 flow_dv_is_counter_in_pool(struct mlx5_flow_counter_pool *pool, int id)
4704 {
4705         int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
4706                    MLX5_COUNTERS_PER_POOL;
4707
4708         if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
4709                 return true;
4710         return false;
4711 }
4712
4713 /**
4714  * Get a pool by devx counter ID.
4715  *
4716  * @param[in] cmng
4717  *   Pointer to the counter management.
4718  * @param[in] id
4719  *   The counter devx ID.
4720  *
4721  * @return
4722  *   The counter pool pointer if exists, NULL otherwise,
4723  */
4724 static struct mlx5_flow_counter_pool *
4725 flow_dv_find_pool_by_id(struct mlx5_flow_counter_mng *cmng, int id)
4726 {
4727         uint32_t i;
4728         struct mlx5_flow_counter_pool *pool = NULL;
4729
4730         rte_spinlock_lock(&cmng->pool_update_sl);
4731         /* Check last used pool. */
4732         if (cmng->last_pool_idx != POOL_IDX_INVALID &&
4733             flow_dv_is_counter_in_pool(cmng->pools[cmng->last_pool_idx], id)) {
4734                 pool = cmng->pools[cmng->last_pool_idx];
4735                 goto out;
4736         }
4737         /* ID out of range means no suitable pool in the container. */
4738         if (id > cmng->max_id || id < cmng->min_id)
4739                 goto out;
4740         /*
4741          * Find the pool from the end of the container, since mostly counter
4742          * ID is sequence increasing, and the last pool should be the needed
4743          * one.
4744          */
4745         i = cmng->n_valid;
4746         while (i--) {
4747                 struct mlx5_flow_counter_pool *pool_tmp = cmng->pools[i];
4748
4749                 if (flow_dv_is_counter_in_pool(pool_tmp, id)) {
4750                         pool = pool_tmp;
4751                         break;
4752                 }
4753         }
4754 out:
4755         rte_spinlock_unlock(&cmng->pool_update_sl);
4756         return pool;
4757 }
4758
4759 /**
4760  * Resize a counter container.
4761  *
4762  * @param[in] dev
4763  *   Pointer to the Ethernet device structure.
4764  *
4765  * @return
4766  *   0 on success, otherwise negative errno value and rte_errno is set.
4767  */
4768 static int
4769 flow_dv_container_resize(struct rte_eth_dev *dev)
4770 {
4771         struct mlx5_priv *priv = dev->data->dev_private;
4772         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4773         void *old_pools = cmng->pools;
4774         uint32_t resize = cmng->n + MLX5_CNT_CONTAINER_RESIZE;
4775         uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
4776         void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
4777
4778         if (!pools) {
4779                 rte_errno = ENOMEM;
4780                 return -ENOMEM;
4781         }
4782         if (old_pools)
4783                 memcpy(pools, old_pools, cmng->n *
4784                                        sizeof(struct mlx5_flow_counter_pool *));
4785         cmng->n = resize;
4786         cmng->pools = pools;
4787         if (old_pools)
4788                 mlx5_free(old_pools);
4789         return 0;
4790 }
4791
4792 /**
4793  * Query a devx flow counter.
4794  *
4795  * @param[in] dev
4796  *   Pointer to the Ethernet device structure.
4797  * @param[in] cnt
4798  *   Index to the flow counter.
4799  * @param[out] pkts
4800  *   The statistics value of packets.
4801  * @param[out] bytes
4802  *   The statistics value of bytes.
4803  *
4804  * @return
4805  *   0 on success, otherwise a negative errno value and rte_errno is set.
4806  */
4807 static inline int
4808 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
4809                      uint64_t *bytes)
4810 {
4811         struct mlx5_priv *priv = dev->data->dev_private;
4812         struct mlx5_flow_counter_pool *pool = NULL;
4813         struct mlx5_flow_counter *cnt;
4814         int offset;
4815
4816         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
4817         MLX5_ASSERT(pool);
4818         if (priv->sh->cmng.counter_fallback)
4819                 return mlx5_devx_cmd_flow_counter_query(cnt->dcs_when_active, 0,
4820                                         0, pkts, bytes, 0, NULL, NULL, 0);
4821         rte_spinlock_lock(&pool->sl);
4822         if (!pool->raw) {
4823                 *pkts = 0;
4824                 *bytes = 0;
4825         } else {
4826                 offset = MLX5_CNT_ARRAY_IDX(pool, cnt);
4827                 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
4828                 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
4829         }
4830         rte_spinlock_unlock(&pool->sl);
4831         return 0;
4832 }
4833
4834 /**
4835  * Create and initialize a new counter pool.
4836  *
4837  * @param[in] dev
4838  *   Pointer to the Ethernet device structure.
4839  * @param[out] dcs
4840  *   The devX counter handle.
4841  * @param[in] age
4842  *   Whether the pool is for counter that was allocated for aging.
4843  * @param[in/out] cont_cur
4844  *   Pointer to the container pointer, it will be update in pool resize.
4845  *
4846  * @return
4847  *   The pool container pointer on success, NULL otherwise and rte_errno is set.
4848  */
4849 static struct mlx5_flow_counter_pool *
4850 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
4851                     uint32_t age)
4852 {
4853         struct mlx5_priv *priv = dev->data->dev_private;
4854         struct mlx5_flow_counter_pool *pool;
4855         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4856         bool fallback = priv->sh->cmng.counter_fallback;
4857         uint32_t size = sizeof(*pool);
4858
4859         size += MLX5_COUNTERS_PER_POOL * MLX5_CNT_SIZE;
4860         size += (!age ? 0 : MLX5_COUNTERS_PER_POOL * MLX5_AGE_SIZE);
4861         pool = mlx5_malloc(MLX5_MEM_ZERO, size, 0, SOCKET_ID_ANY);
4862         if (!pool) {
4863                 rte_errno = ENOMEM;
4864                 return NULL;
4865         }
4866         pool->raw = NULL;
4867         pool->is_aged = !!age;
4868         pool->query_gen = 0;
4869         pool->min_dcs = dcs;
4870         rte_spinlock_init(&pool->sl);
4871         rte_spinlock_init(&pool->csl);
4872         TAILQ_INIT(&pool->counters[0]);
4873         TAILQ_INIT(&pool->counters[1]);
4874         pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
4875         rte_spinlock_lock(&cmng->pool_update_sl);
4876         pool->index = cmng->n_valid;
4877         if (pool->index == cmng->n && flow_dv_container_resize(dev)) {
4878                 mlx5_free(pool);
4879                 rte_spinlock_unlock(&cmng->pool_update_sl);
4880                 return NULL;
4881         }
4882         cmng->pools[pool->index] = pool;
4883         cmng->n_valid++;
4884         if (unlikely(fallback)) {
4885                 int base = RTE_ALIGN_FLOOR(dcs->id, MLX5_COUNTERS_PER_POOL);
4886
4887                 if (base < cmng->min_id)
4888                         cmng->min_id = base;
4889                 if (base > cmng->max_id)
4890                         cmng->max_id = base + MLX5_COUNTERS_PER_POOL - 1;
4891                 cmng->last_pool_idx = pool->index;
4892         }
4893         rte_spinlock_unlock(&cmng->pool_update_sl);
4894         return pool;
4895 }
4896
4897 /**
4898  * Prepare a new counter and/or a new counter pool.
4899  *
4900  * @param[in] dev
4901  *   Pointer to the Ethernet device structure.
4902  * @param[out] cnt_free
4903  *   Where to put the pointer of a new counter.
4904  * @param[in] age
4905  *   Whether the pool is for counter that was allocated for aging.
4906  *
4907  * @return
4908  *   The counter pool pointer and @p cnt_free is set on success,
4909  *   NULL otherwise and rte_errno is set.
4910  */
4911 static struct mlx5_flow_counter_pool *
4912 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
4913                              struct mlx5_flow_counter **cnt_free,
4914                              uint32_t age)
4915 {
4916         struct mlx5_priv *priv = dev->data->dev_private;
4917         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4918         struct mlx5_flow_counter_pool *pool;
4919         struct mlx5_counters tmp_tq;
4920         struct mlx5_devx_obj *dcs = NULL;
4921         struct mlx5_flow_counter *cnt;
4922         enum mlx5_counter_type cnt_type =
4923                         age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
4924         bool fallback = priv->sh->cmng.counter_fallback;
4925         uint32_t i;
4926
4927         if (fallback) {
4928                 /* bulk_bitmap must be 0 for single counter allocation. */
4929                 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
4930                 if (!dcs)
4931                         return NULL;
4932                 pool = flow_dv_find_pool_by_id(cmng, dcs->id);
4933                 if (!pool) {
4934                         pool = flow_dv_pool_create(dev, dcs, age);
4935                         if (!pool) {
4936                                 mlx5_devx_cmd_destroy(dcs);
4937                                 return NULL;
4938                         }
4939                 }
4940                 i = dcs->id % MLX5_COUNTERS_PER_POOL;
4941                 cnt = MLX5_POOL_GET_CNT(pool, i);
4942                 cnt->pool = pool;
4943                 cnt->dcs_when_free = dcs;
4944                 *cnt_free = cnt;
4945                 return pool;
4946         }
4947         dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
4948         if (!dcs) {
4949                 rte_errno = ENODATA;
4950                 return NULL;
4951         }
4952         pool = flow_dv_pool_create(dev, dcs, age);
4953         if (!pool) {
4954                 mlx5_devx_cmd_destroy(dcs);
4955                 return NULL;
4956         }
4957         TAILQ_INIT(&tmp_tq);
4958         for (i = 1; i < MLX5_COUNTERS_PER_POOL; ++i) {
4959                 cnt = MLX5_POOL_GET_CNT(pool, i);
4960                 cnt->pool = pool;
4961                 TAILQ_INSERT_HEAD(&tmp_tq, cnt, next);
4962         }
4963         rte_spinlock_lock(&cmng->csl[cnt_type]);
4964         TAILQ_CONCAT(&cmng->counters[cnt_type], &tmp_tq, next);
4965         rte_spinlock_unlock(&cmng->csl[cnt_type]);
4966         *cnt_free = MLX5_POOL_GET_CNT(pool, 0);
4967         (*cnt_free)->pool = pool;
4968         return pool;
4969 }
4970
4971 /**
4972  * Allocate a flow counter.
4973  *
4974  * @param[in] dev
4975  *   Pointer to the Ethernet device structure.
4976  * @param[in] age
4977  *   Whether the counter was allocated for aging.
4978  *
4979  * @return
4980  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
4981  */
4982 static uint32_t
4983 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t age)
4984 {
4985         struct mlx5_priv *priv = dev->data->dev_private;
4986         struct mlx5_flow_counter_pool *pool = NULL;
4987         struct mlx5_flow_counter *cnt_free = NULL;
4988         bool fallback = priv->sh->cmng.counter_fallback;
4989         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4990         enum mlx5_counter_type cnt_type =
4991                         age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
4992         uint32_t cnt_idx;
4993
4994         if (!priv->config.devx) {
4995                 rte_errno = ENOTSUP;
4996                 return 0;
4997         }
4998         /* Get free counters from container. */
4999         rte_spinlock_lock(&cmng->csl[cnt_type]);
5000         cnt_free = TAILQ_FIRST(&cmng->counters[cnt_type]);
5001         if (cnt_free)
5002                 TAILQ_REMOVE(&cmng->counters[cnt_type], cnt_free, next);
5003         rte_spinlock_unlock(&cmng->csl[cnt_type]);
5004         if (!cnt_free && !flow_dv_counter_pool_prepare(dev, &cnt_free, age))
5005                 goto err;
5006         pool = cnt_free->pool;
5007         if (fallback)
5008                 cnt_free->dcs_when_active = cnt_free->dcs_when_free;
5009         /* Create a DV counter action only in the first time usage. */
5010         if (!cnt_free->action) {
5011                 uint16_t offset;
5012                 struct mlx5_devx_obj *dcs;
5013                 int ret;
5014
5015                 if (!fallback) {
5016                         offset = MLX5_CNT_ARRAY_IDX(pool, cnt_free);
5017                         dcs = pool->min_dcs;
5018                 } else {
5019                         offset = 0;
5020                         dcs = cnt_free->dcs_when_free;
5021                 }
5022                 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, offset,
5023                                                             &cnt_free->action);
5024                 if (ret) {
5025                         rte_errno = errno;
5026                         goto err;
5027                 }
5028         }
5029         cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
5030                                 MLX5_CNT_ARRAY_IDX(pool, cnt_free));
5031         /* Update the counter reset values. */
5032         if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
5033                                  &cnt_free->bytes))
5034                 goto err;
5035         if (!fallback && !priv->sh->cmng.query_thread_on)
5036                 /* Start the asynchronous batch query by the host thread. */
5037                 mlx5_set_query_alarm(priv->sh);
5038         return cnt_idx;
5039 err:
5040         if (cnt_free) {
5041                 cnt_free->pool = pool;
5042                 if (fallback)
5043                         cnt_free->dcs_when_free = cnt_free->dcs_when_active;
5044                 rte_spinlock_lock(&cmng->csl[cnt_type]);
5045                 TAILQ_INSERT_TAIL(&cmng->counters[cnt_type], cnt_free, next);
5046                 rte_spinlock_unlock(&cmng->csl[cnt_type]);
5047         }
5048         return 0;
5049 }
5050
5051 /**
5052  * Allocate a shared flow counter.
5053  *
5054  * @param[in] ctx
5055  *   Pointer to the shared counter configuration.
5056  * @param[in] data
5057  *   Pointer to save the allocated counter index.
5058  *
5059  * @return
5060  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
5061  */
5062
5063 static int32_t
5064 flow_dv_counter_alloc_shared_cb(void *ctx, union mlx5_l3t_data *data)
5065 {
5066         struct mlx5_shared_counter_conf *conf = ctx;
5067         struct rte_eth_dev *dev = conf->dev;
5068         struct mlx5_flow_counter *cnt;
5069
5070         data->dword = flow_dv_counter_alloc(dev, 0);
5071         data->dword |= MLX5_CNT_SHARED_OFFSET;
5072         cnt = flow_dv_counter_get_by_idx(dev, data->dword, NULL);
5073         cnt->shared_info.id = conf->id;
5074         return 0;
5075 }
5076
5077 /**
5078  * Get a shared flow counter.
5079  *
5080  * @param[in] dev
5081  *   Pointer to the Ethernet device structure.
5082  * @param[in] id
5083  *   Counter identifier.
5084  *
5085  * @return
5086  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
5087  */
5088 static uint32_t
5089 flow_dv_counter_get_shared(struct rte_eth_dev *dev, uint32_t id)
5090 {
5091         struct mlx5_priv *priv = dev->data->dev_private;
5092         struct mlx5_shared_counter_conf conf = {
5093                 .dev = dev,
5094                 .id = id,
5095         };
5096         union mlx5_l3t_data data = {
5097                 .dword = 0,
5098         };
5099
5100         mlx5_l3t_prepare_entry(priv->sh->cnt_id_tbl, id, &data,
5101                                flow_dv_counter_alloc_shared_cb, &conf);
5102         return data.dword;
5103 }
5104
5105 /**
5106  * Get age param from counter index.
5107  *
5108  * @param[in] dev
5109  *   Pointer to the Ethernet device structure.
5110  * @param[in] counter
5111  *   Index to the counter handler.
5112  *
5113  * @return
5114  *   The aging parameter specified for the counter index.
5115  */
5116 static struct mlx5_age_param*
5117 flow_dv_counter_idx_get_age(struct rte_eth_dev *dev,
5118                                 uint32_t counter)
5119 {
5120         struct mlx5_flow_counter *cnt;
5121         struct mlx5_flow_counter_pool *pool = NULL;
5122
5123         flow_dv_counter_get_by_idx(dev, counter, &pool);
5124         counter = (counter - 1) % MLX5_COUNTERS_PER_POOL;
5125         cnt = MLX5_POOL_GET_CNT(pool, counter);
5126         return MLX5_CNT_TO_AGE(cnt);
5127 }
5128
5129 /**
5130  * Remove a flow counter from aged counter list.
5131  *
5132  * @param[in] dev
5133  *   Pointer to the Ethernet device structure.
5134  * @param[in] counter
5135  *   Index to the counter handler.
5136  * @param[in] cnt
5137  *   Pointer to the counter handler.
5138  */
5139 static void
5140 flow_dv_counter_remove_from_age(struct rte_eth_dev *dev,
5141                                 uint32_t counter, struct mlx5_flow_counter *cnt)
5142 {
5143         struct mlx5_age_info *age_info;
5144         struct mlx5_age_param *age_param;
5145         struct mlx5_priv *priv = dev->data->dev_private;
5146         uint16_t expected = AGE_CANDIDATE;
5147
5148         age_info = GET_PORT_AGE_INFO(priv);
5149         age_param = flow_dv_counter_idx_get_age(dev, counter);
5150         if (!__atomic_compare_exchange_n(&age_param->state, &expected,
5151                                          AGE_FREE, false, __ATOMIC_RELAXED,
5152                                          __ATOMIC_RELAXED)) {
5153                 /**
5154                  * We need the lock even it is age timeout,
5155                  * since counter may still in process.
5156                  */
5157                 rte_spinlock_lock(&age_info->aged_sl);
5158                 TAILQ_REMOVE(&age_info->aged_counters, cnt, next);
5159                 rte_spinlock_unlock(&age_info->aged_sl);
5160                 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
5161         }
5162 }
5163
5164 /**
5165  * Release a flow counter.
5166  *
5167  * @param[in] dev
5168  *   Pointer to the Ethernet device structure.
5169  * @param[in] counter
5170  *   Index to the counter handler.
5171  */
5172 static void
5173 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t counter)
5174 {
5175         struct mlx5_priv *priv = dev->data->dev_private;
5176         struct mlx5_flow_counter_pool *pool = NULL;
5177         struct mlx5_flow_counter *cnt;
5178         enum mlx5_counter_type cnt_type;
5179
5180         if (!counter)
5181                 return;
5182         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
5183         MLX5_ASSERT(pool);
5184         if (IS_SHARED_CNT(counter) &&
5185             mlx5_l3t_clear_entry(priv->sh->cnt_id_tbl, cnt->shared_info.id))
5186                 return;
5187         if (pool->is_aged)
5188                 flow_dv_counter_remove_from_age(dev, counter, cnt);
5189         cnt->pool = pool;
5190         /*
5191          * Put the counter back to list to be updated in none fallback mode.
5192          * Currently, we are using two list alternately, while one is in query,
5193          * add the freed counter to the other list based on the pool query_gen
5194          * value. After query finishes, add counter the list to the global
5195          * container counter list. The list changes while query starts. In
5196          * this case, lock will not be needed as query callback and release
5197          * function both operate with the different list.
5198          *
5199          */
5200         if (!priv->sh->cmng.counter_fallback) {
5201                 rte_spinlock_lock(&pool->csl);
5202                 TAILQ_INSERT_TAIL(&pool->counters[pool->query_gen], cnt, next);
5203                 rte_spinlock_unlock(&pool->csl);
5204         } else {
5205                 cnt->dcs_when_free = cnt->dcs_when_active;
5206                 cnt_type = pool->is_aged ? MLX5_COUNTER_TYPE_AGE :
5207                                            MLX5_COUNTER_TYPE_ORIGIN;
5208                 rte_spinlock_lock(&priv->sh->cmng.csl[cnt_type]);
5209                 TAILQ_INSERT_TAIL(&priv->sh->cmng.counters[cnt_type],
5210                                   cnt, next);
5211                 rte_spinlock_unlock(&priv->sh->cmng.csl[cnt_type]);
5212         }
5213 }
5214
5215 /**
5216  * Verify the @p attributes will be correctly understood by the NIC and store
5217  * them in the @p flow if everything is correct.
5218  *
5219  * @param[in] dev
5220  *   Pointer to dev struct.
5221  * @param[in] attributes
5222  *   Pointer to flow attributes
5223  * @param[in] external
5224  *   This flow rule is created by request external to PMD.
5225  * @param[out] error
5226  *   Pointer to error structure.
5227  *
5228  * @return
5229  *   - 0 on success and non root table.
5230  *   - 1 on success and root table.
5231  *   - a negative errno value otherwise and rte_errno is set.
5232  */
5233 static int
5234 flow_dv_validate_attributes(struct rte_eth_dev *dev,
5235                             const struct mlx5_flow_tunnel *tunnel,
5236                             const struct rte_flow_attr *attributes,
5237                             const struct flow_grp_info *grp_info,
5238                             struct rte_flow_error *error)
5239 {
5240         struct mlx5_priv *priv = dev->data->dev_private;
5241         uint32_t lowest_priority = mlx5_get_lowest_priority(dev, attributes);
5242         int ret = 0;
5243
5244 #ifndef HAVE_MLX5DV_DR
5245         RTE_SET_USED(tunnel);
5246         RTE_SET_USED(grp_info);
5247         if (attributes->group)
5248                 return rte_flow_error_set(error, ENOTSUP,
5249                                           RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
5250                                           NULL,
5251                                           "groups are not supported");
5252 #else
5253         uint32_t table = 0;
5254
5255         ret = mlx5_flow_group_to_table(dev, tunnel, attributes->group, &table,
5256                                        grp_info, error);
5257         if (ret)
5258                 return ret;
5259         if (!table)
5260                 ret = MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
5261 #endif
5262         if (attributes->priority != MLX5_FLOW_LOWEST_PRIO_INDICATOR &&
5263             attributes->priority > lowest_priority)
5264                 return rte_flow_error_set(error, ENOTSUP,
5265                                           RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
5266                                           NULL,
5267                                           "priority out of range");
5268         if (attributes->transfer) {
5269                 if (!priv->config.dv_esw_en)
5270                         return rte_flow_error_set
5271                                 (error, ENOTSUP,
5272                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5273                                  "E-Switch dr is not supported");
5274                 if (!(priv->representor || priv->master))
5275                         return rte_flow_error_set
5276                                 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5277                                  NULL, "E-Switch configuration can only be"
5278                                  " done by a master or a representor device");
5279                 if (attributes->egress)
5280                         return rte_flow_error_set
5281                                 (error, ENOTSUP,
5282                                  RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
5283                                  "egress is not supported");
5284         }
5285         if (!(attributes->egress ^ attributes->ingress))
5286                 return rte_flow_error_set(error, ENOTSUP,
5287                                           RTE_FLOW_ERROR_TYPE_ATTR, NULL,
5288                                           "must specify exactly one of "
5289                                           "ingress or egress");
5290         return ret;
5291 }
5292
5293 /**
5294  * Internal validation function. For validating both actions and items.
5295  *
5296  * @param[in] dev
5297  *   Pointer to the rte_eth_dev structure.
5298  * @param[in] attr
5299  *   Pointer to the flow attributes.
5300  * @param[in] items
5301  *   Pointer to the list of items.
5302  * @param[in] actions
5303  *   Pointer to the list of actions.
5304  * @param[in] external
5305  *   This flow rule is created by request external to PMD.
5306  * @param[in] hairpin
5307  *   Number of hairpin TX actions, 0 means classic flow.
5308  * @param[out] error
5309  *   Pointer to the error structure.
5310  *
5311  * @return
5312  *   0 on success, a negative errno value otherwise and rte_errno is set.
5313  */
5314 static int
5315 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
5316                  const struct rte_flow_item items[],
5317                  const struct rte_flow_action actions[],
5318                  bool external, int hairpin, struct rte_flow_error *error)
5319 {
5320         int ret;
5321         uint64_t action_flags = 0;
5322         uint64_t item_flags = 0;
5323         uint64_t last_item = 0;
5324         uint8_t next_protocol = 0xff;
5325         uint16_t ether_type = 0;
5326         int actions_n = 0;
5327         uint8_t item_ipv6_proto = 0;
5328         const struct rte_flow_item *geneve_item = NULL;
5329         const struct rte_flow_item *gre_item = NULL;
5330         const struct rte_flow_item *gtp_item = NULL;
5331         const struct rte_flow_action_raw_decap *decap;
5332         const struct rte_flow_action_raw_encap *encap;
5333         const struct rte_flow_action_rss *rss = NULL;
5334         const struct rte_flow_action_rss *sample_rss = NULL;
5335         const struct rte_flow_item_tcp nic_tcp_mask = {
5336                 .hdr = {
5337                         .tcp_flags = 0xFF,
5338                         .src_port = RTE_BE16(UINT16_MAX),
5339                         .dst_port = RTE_BE16(UINT16_MAX),
5340                 }
5341         };
5342         const struct rte_flow_item_ipv6 nic_ipv6_mask = {
5343                 .hdr = {
5344                         .src_addr =
5345                         "\xff\xff\xff\xff\xff\xff\xff\xff"
5346                         "\xff\xff\xff\xff\xff\xff\xff\xff",
5347                         .dst_addr =
5348                         "\xff\xff\xff\xff\xff\xff\xff\xff"
5349                         "\xff\xff\xff\xff\xff\xff\xff\xff",
5350                         .vtc_flow = RTE_BE32(0xffffffff),
5351                         .proto = 0xff,
5352                         .hop_limits = 0xff,
5353                 },
5354                 .has_frag_ext = 1,
5355         };
5356         const struct rte_flow_item_ecpri nic_ecpri_mask = {
5357                 .hdr = {
5358                         .common = {
5359                                 .u32 =
5360                                 RTE_BE32(((const struct rte_ecpri_common_hdr) {
5361                                         .type = 0xFF,
5362                                         }).u32),
5363                         },
5364                         .dummy[0] = 0xffffffff,
5365                 },
5366         };
5367         struct mlx5_priv *priv = dev->data->dev_private;
5368         struct mlx5_dev_config *dev_conf = &priv->config;
5369         uint16_t queue_index = 0xFFFF;
5370         const struct rte_flow_item_vlan *vlan_m = NULL;
5371         int16_t rw_act_num = 0;
5372         uint64_t is_root;
5373         const struct mlx5_flow_tunnel *tunnel;
5374         struct flow_grp_info grp_info = {
5375                 .external = !!external,
5376                 .transfer = !!attr->transfer,
5377                 .fdb_def_rule = !!priv->fdb_def_rule,
5378         };
5379         const struct rte_eth_hairpin_conf *conf;
5380
5381         if (items == NULL)
5382                 return -1;
5383         if (is_flow_tunnel_match_rule(dev, attr, items, actions)) {
5384                 tunnel = flow_items_to_tunnel(items);
5385                 action_flags |= MLX5_FLOW_ACTION_TUNNEL_MATCH |
5386                                 MLX5_FLOW_ACTION_DECAP;
5387         } else if (is_flow_tunnel_steer_rule(dev, attr, items, actions)) {
5388                 tunnel = flow_actions_to_tunnel(actions);
5389                 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
5390         } else {
5391                 tunnel = NULL;
5392         }
5393         if (tunnel && priv->representor)
5394                 return rte_flow_error_set(error, ENOTSUP,
5395                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5396                                           "decap not supported "
5397                                           "for VF representor");
5398         grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
5399                                 (dev, tunnel, attr, items, actions);
5400         ret = flow_dv_validate_attributes(dev, tunnel, attr, &grp_info, error);
5401         if (ret < 0)
5402                 return ret;
5403         is_root = (uint64_t)ret;
5404         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
5405                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
5406                 int type = items->type;
5407
5408                 if (!mlx5_flow_os_item_supported(type))
5409                         return rte_flow_error_set(error, ENOTSUP,
5410                                                   RTE_FLOW_ERROR_TYPE_ITEM,
5411                                                   NULL, "item not supported");
5412                 switch (type) {
5413                 case MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL:
5414                         if (items[0].type != (typeof(items[0].type))
5415                                                 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL)
5416                                 return rte_flow_error_set
5417                                                 (error, EINVAL,
5418                                                 RTE_FLOW_ERROR_TYPE_ITEM,
5419                                                 NULL, "MLX5 private items "
5420                                                 "must be the first");
5421                         break;
5422                 case RTE_FLOW_ITEM_TYPE_VOID:
5423                         break;
5424                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
5425                         ret = flow_dv_validate_item_port_id
5426                                         (dev, items, attr, item_flags, error);
5427                         if (ret < 0)
5428                                 return ret;
5429                         last_item = MLX5_FLOW_ITEM_PORT_ID;
5430                         break;
5431                 case RTE_FLOW_ITEM_TYPE_ETH:
5432                         ret = mlx5_flow_validate_item_eth(items, item_flags,
5433                                                           true, error);
5434                         if (ret < 0)
5435                                 return ret;
5436                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
5437                                              MLX5_FLOW_LAYER_OUTER_L2;
5438                         if (items->mask != NULL && items->spec != NULL) {
5439                                 ether_type =
5440                                         ((const struct rte_flow_item_eth *)
5441                                          items->spec)->type;
5442                                 ether_type &=
5443                                         ((const struct rte_flow_item_eth *)
5444                                          items->mask)->type;
5445                                 ether_type = rte_be_to_cpu_16(ether_type);
5446                         } else {
5447                                 ether_type = 0;
5448                         }
5449                         break;
5450                 case RTE_FLOW_ITEM_TYPE_VLAN:
5451                         ret = flow_dv_validate_item_vlan(items, item_flags,
5452                                                          dev, error);
5453                         if (ret < 0)
5454                                 return ret;
5455                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
5456                                              MLX5_FLOW_LAYER_OUTER_VLAN;
5457                         if (items->mask != NULL && items->spec != NULL) {
5458                                 ether_type =
5459                                         ((const struct rte_flow_item_vlan *)
5460                                          items->spec)->inner_type;
5461                                 ether_type &=
5462                                         ((const struct rte_flow_item_vlan *)
5463                                          items->mask)->inner_type;
5464                                 ether_type = rte_be_to_cpu_16(ether_type);
5465                         } else {
5466                                 ether_type = 0;
5467                         }
5468                         /* Store outer VLAN mask for of_push_vlan action. */
5469                         if (!tunnel)
5470                                 vlan_m = items->mask;
5471                         break;
5472                 case RTE_FLOW_ITEM_TYPE_IPV4:
5473                         mlx5_flow_tunnel_ip_check(items, next_protocol,
5474                                                   &item_flags, &tunnel);
5475                         ret = flow_dv_validate_item_ipv4(items, item_flags,
5476                                                          last_item, ether_type,
5477                                                          error);
5478                         if (ret < 0)
5479                                 return ret;
5480                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
5481                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
5482                         if (items->mask != NULL &&
5483                             ((const struct rte_flow_item_ipv4 *)
5484                              items->mask)->hdr.next_proto_id) {
5485                                 next_protocol =
5486                                         ((const struct rte_flow_item_ipv4 *)
5487                                          (items->spec))->hdr.next_proto_id;
5488                                 next_protocol &=
5489                                         ((const struct rte_flow_item_ipv4 *)
5490                                          (items->mask))->hdr.next_proto_id;
5491                         } else {
5492                                 /* Reset for inner layer. */
5493                                 next_protocol = 0xff;
5494                         }
5495                         break;
5496                 case RTE_FLOW_ITEM_TYPE_IPV6:
5497                         mlx5_flow_tunnel_ip_check(items, next_protocol,
5498                                                   &item_flags, &tunnel);
5499                         ret = mlx5_flow_validate_item_ipv6(items, item_flags,
5500                                                            last_item,
5501                                                            ether_type,
5502                                                            &nic_ipv6_mask,
5503                                                            error);
5504                         if (ret < 0)
5505                                 return ret;
5506                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
5507                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
5508                         if (items->mask != NULL &&
5509                             ((const struct rte_flow_item_ipv6 *)
5510                              items->mask)->hdr.proto) {
5511                                 item_ipv6_proto =
5512                                         ((const struct rte_flow_item_ipv6 *)
5513                                          items->spec)->hdr.proto;
5514                                 next_protocol =
5515                                         ((const struct rte_flow_item_ipv6 *)
5516                                          items->spec)->hdr.proto;
5517                                 next_protocol &=
5518                                         ((const struct rte_flow_item_ipv6 *)
5519                                          items->mask)->hdr.proto;
5520                         } else {
5521                                 /* Reset for inner layer. */
5522                                 next_protocol = 0xff;
5523                         }
5524                         break;
5525                 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
5526                         ret = flow_dv_validate_item_ipv6_frag_ext(items,
5527                                                                   item_flags,
5528                                                                   error);
5529                         if (ret < 0)
5530                                 return ret;
5531                         last_item = tunnel ?
5532                                         MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
5533                                         MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
5534                         if (items->mask != NULL &&
5535                             ((const struct rte_flow_item_ipv6_frag_ext *)
5536                              items->mask)->hdr.next_header) {
5537                                 next_protocol =
5538                                 ((const struct rte_flow_item_ipv6_frag_ext *)
5539                                  items->spec)->hdr.next_header;
5540                                 next_protocol &=
5541                                 ((const struct rte_flow_item_ipv6_frag_ext *)
5542                                  items->mask)->hdr.next_header;
5543                         } else {
5544                                 /* Reset for inner layer. */
5545                                 next_protocol = 0xff;
5546                         }
5547                         break;
5548                 case RTE_FLOW_ITEM_TYPE_TCP:
5549                         ret = mlx5_flow_validate_item_tcp
5550                                                 (items, item_flags,
5551                                                  next_protocol,
5552                                                  &nic_tcp_mask,
5553                                                  error);
5554                         if (ret < 0)
5555                                 return ret;
5556                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
5557                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
5558                         break;
5559                 case RTE_FLOW_ITEM_TYPE_UDP:
5560                         ret = mlx5_flow_validate_item_udp(items, item_flags,
5561                                                           next_protocol,
5562                                                           error);
5563                         if (ret < 0)
5564                                 return ret;
5565                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
5566                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
5567                         break;
5568                 case RTE_FLOW_ITEM_TYPE_GRE:
5569                         ret = mlx5_flow_validate_item_gre(items, item_flags,
5570                                                           next_protocol, error);
5571                         if (ret < 0)
5572                                 return ret;
5573                         gre_item = items;
5574                         last_item = MLX5_FLOW_LAYER_GRE;
5575                         break;
5576                 case RTE_FLOW_ITEM_TYPE_NVGRE:
5577                         ret = mlx5_flow_validate_item_nvgre(items, item_flags,
5578                                                             next_protocol,
5579                                                             error);
5580                         if (ret < 0)
5581                                 return ret;
5582                         last_item = MLX5_FLOW_LAYER_NVGRE;
5583                         break;
5584                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
5585                         ret = mlx5_flow_validate_item_gre_key
5586                                 (items, item_flags, gre_item, error);
5587                         if (ret < 0)
5588                                 return ret;
5589                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
5590                         break;
5591                 case RTE_FLOW_ITEM_TYPE_VXLAN:
5592                         ret = mlx5_flow_validate_item_vxlan(items, item_flags,
5593                                                             error);
5594                         if (ret < 0)
5595                                 return ret;
5596                         last_item = MLX5_FLOW_LAYER_VXLAN;
5597                         break;
5598                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
5599                         ret = mlx5_flow_validate_item_vxlan_gpe(items,
5600                                                                 item_flags, dev,
5601                                                                 error);
5602                         if (ret < 0)
5603                                 return ret;
5604                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
5605                         break;
5606                 case RTE_FLOW_ITEM_TYPE_GENEVE:
5607                         ret = mlx5_flow_validate_item_geneve(items,
5608                                                              item_flags, dev,
5609                                                              error);
5610                         if (ret < 0)
5611                                 return ret;
5612                         geneve_item = items;
5613                         last_item = MLX5_FLOW_LAYER_GENEVE;
5614                         break;
5615                 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
5616                         ret = mlx5_flow_validate_item_geneve_opt(items,
5617                                                                  last_item,
5618                                                                  geneve_item,
5619                                                                  dev,
5620                                                                  error);
5621                         if (ret < 0)
5622                                 return ret;
5623                         last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
5624                         break;
5625                 case RTE_FLOW_ITEM_TYPE_MPLS:
5626                         ret = mlx5_flow_validate_item_mpls(dev, items,
5627                                                            item_flags,
5628                                                            last_item, error);
5629                         if (ret < 0)
5630                                 return ret;
5631                         last_item = MLX5_FLOW_LAYER_MPLS;
5632                         break;
5633
5634                 case RTE_FLOW_ITEM_TYPE_MARK:
5635                         ret = flow_dv_validate_item_mark(dev, items, attr,
5636                                                          error);
5637                         if (ret < 0)
5638                                 return ret;
5639                         last_item = MLX5_FLOW_ITEM_MARK;
5640                         break;
5641                 case RTE_FLOW_ITEM_TYPE_META:
5642                         ret = flow_dv_validate_item_meta(dev, items, attr,
5643                                                          error);
5644                         if (ret < 0)
5645                                 return ret;
5646                         last_item = MLX5_FLOW_ITEM_METADATA;
5647                         break;
5648                 case RTE_FLOW_ITEM_TYPE_ICMP:
5649                         ret = mlx5_flow_validate_item_icmp(items, item_flags,
5650                                                            next_protocol,
5651                                                            error);
5652                         if (ret < 0)
5653                                 return ret;
5654                         last_item = MLX5_FLOW_LAYER_ICMP;
5655                         break;
5656                 case RTE_FLOW_ITEM_TYPE_ICMP6:
5657                         ret = mlx5_flow_validate_item_icmp6(items, item_flags,
5658                                                             next_protocol,
5659                                                             error);
5660                         if (ret < 0)
5661                                 return ret;
5662                         item_ipv6_proto = IPPROTO_ICMPV6;
5663                         last_item = MLX5_FLOW_LAYER_ICMP6;
5664                         break;
5665                 case RTE_FLOW_ITEM_TYPE_TAG:
5666                         ret = flow_dv_validate_item_tag(dev, items,
5667                                                         attr, error);
5668                         if (ret < 0)
5669                                 return ret;
5670                         last_item = MLX5_FLOW_ITEM_TAG;
5671                         break;
5672                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
5673                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
5674                         break;
5675                 case RTE_FLOW_ITEM_TYPE_GTP:
5676                         ret = flow_dv_validate_item_gtp(dev, items, item_flags,
5677                                                         error);
5678                         if (ret < 0)
5679                                 return ret;
5680                         gtp_item = items;
5681                         last_item = MLX5_FLOW_LAYER_GTP;
5682                         break;
5683                 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
5684                         ret = flow_dv_validate_item_gtp_psc(items, last_item,
5685                                                             gtp_item, attr,
5686                                                             error);
5687                         if (ret < 0)
5688                                 return ret;
5689                         last_item = MLX5_FLOW_LAYER_GTP_PSC;
5690                         break;
5691                 case RTE_FLOW_ITEM_TYPE_ECPRI:
5692                         /* Capacity will be checked in the translate stage. */
5693                         ret = mlx5_flow_validate_item_ecpri(items, item_flags,
5694                                                             last_item,
5695                                                             ether_type,
5696                                                             &nic_ecpri_mask,
5697                                                             error);
5698                         if (ret < 0)
5699                                 return ret;
5700                         last_item = MLX5_FLOW_LAYER_ECPRI;
5701                         break;
5702                 default:
5703                         return rte_flow_error_set(error, ENOTSUP,
5704                                                   RTE_FLOW_ERROR_TYPE_ITEM,
5705                                                   NULL, "item not supported");
5706                 }
5707                 item_flags |= last_item;
5708         }
5709         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
5710                 int type = actions->type;
5711
5712                 if (!mlx5_flow_os_action_supported(type))
5713                         return rte_flow_error_set(error, ENOTSUP,
5714                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5715                                                   actions,
5716                                                   "action not supported");
5717                 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
5718                         return rte_flow_error_set(error, ENOTSUP,
5719                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5720                                                   actions, "too many actions");
5721                 switch (type) {
5722                 case RTE_FLOW_ACTION_TYPE_VOID:
5723                         break;
5724                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5725                         ret = flow_dv_validate_action_port_id(dev,
5726                                                               action_flags,
5727                                                               actions,
5728                                                               attr,
5729                                                               error);
5730                         if (ret)
5731                                 return ret;
5732                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5733                         ++actions_n;
5734                         break;
5735                 case RTE_FLOW_ACTION_TYPE_FLAG:
5736                         ret = flow_dv_validate_action_flag(dev, action_flags,
5737                                                            attr, error);
5738                         if (ret < 0)
5739                                 return ret;
5740                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
5741                                 /* Count all modify-header actions as one. */
5742                                 if (!(action_flags &
5743                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
5744                                         ++actions_n;
5745                                 action_flags |= MLX5_FLOW_ACTION_FLAG |
5746                                                 MLX5_FLOW_ACTION_MARK_EXT;
5747                         } else {
5748                                 action_flags |= MLX5_FLOW_ACTION_FLAG;
5749                                 ++actions_n;
5750                         }
5751                         rw_act_num += MLX5_ACT_NUM_SET_MARK;
5752                         break;
5753                 case RTE_FLOW_ACTION_TYPE_MARK:
5754                         ret = flow_dv_validate_action_mark(dev, actions,
5755                                                            action_flags,
5756                                                            attr, error);
5757                         if (ret < 0)
5758                                 return ret;
5759                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
5760                                 /* Count all modify-header actions as one. */
5761                                 if (!(action_flags &
5762                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
5763                                         ++actions_n;
5764                                 action_flags |= MLX5_FLOW_ACTION_MARK |
5765                                                 MLX5_FLOW_ACTION_MARK_EXT;
5766                         } else {
5767                                 action_flags |= MLX5_FLOW_ACTION_MARK;
5768                                 ++actions_n;
5769                         }
5770                         rw_act_num += MLX5_ACT_NUM_SET_MARK;
5771                         break;
5772                 case RTE_FLOW_ACTION_TYPE_SET_META:
5773                         ret = flow_dv_validate_action_set_meta(dev, actions,
5774                                                                action_flags,
5775                                                                attr, error);
5776                         if (ret < 0)
5777                                 return ret;
5778                         /* Count all modify-header actions as one action. */
5779                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5780                                 ++actions_n;
5781                         action_flags |= MLX5_FLOW_ACTION_SET_META;
5782                         rw_act_num += MLX5_ACT_NUM_SET_META;
5783                         break;
5784                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
5785                         ret = flow_dv_validate_action_set_tag(dev, actions,
5786                                                               action_flags,
5787                                                               attr, error);
5788                         if (ret < 0)
5789                                 return ret;
5790                         /* Count all modify-header actions as one action. */
5791                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5792                                 ++actions_n;
5793                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
5794                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
5795                         break;
5796                 case RTE_FLOW_ACTION_TYPE_DROP:
5797                         ret = mlx5_flow_validate_action_drop(action_flags,
5798                                                              attr, error);
5799                         if (ret < 0)
5800                                 return ret;
5801                         action_flags |= MLX5_FLOW_ACTION_DROP;
5802                         ++actions_n;
5803                         break;
5804                 case RTE_FLOW_ACTION_TYPE_QUEUE:
5805                         ret = mlx5_flow_validate_action_queue(actions,
5806                                                               action_flags, dev,
5807                                                               attr, error);
5808                         if (ret < 0)
5809                                 return ret;
5810                         queue_index = ((const struct rte_flow_action_queue *)
5811                                                         (actions->conf))->index;
5812                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
5813                         ++actions_n;
5814                         break;
5815                 case RTE_FLOW_ACTION_TYPE_RSS:
5816                         rss = actions->conf;
5817                         ret = mlx5_flow_validate_action_rss(actions,
5818                                                             action_flags, dev,
5819                                                             attr, item_flags,
5820                                                             error);
5821                         if (ret < 0)
5822                                 return ret;
5823                         if (rss && sample_rss &&
5824                             (sample_rss->level != rss->level ||
5825                             sample_rss->types != rss->types))
5826                                 return rte_flow_error_set(error, ENOTSUP,
5827                                         RTE_FLOW_ERROR_TYPE_ACTION,
5828                                         NULL,
5829                                         "Can't use the different RSS types "
5830                                         "or level in the same flow");
5831                         if (rss != NULL && rss->queue_num)
5832                                 queue_index = rss->queue[0];
5833                         action_flags |= MLX5_FLOW_ACTION_RSS;
5834                         ++actions_n;
5835                         break;
5836                 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
5837                         ret =
5838                         mlx5_flow_validate_action_default_miss(action_flags,
5839                                         attr, error);
5840                         if (ret < 0)
5841                                 return ret;
5842                         action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
5843                         ++actions_n;
5844                         break;
5845                 case RTE_FLOW_ACTION_TYPE_COUNT:
5846                         ret = flow_dv_validate_action_count(dev, error);
5847                         if (ret < 0)
5848                                 return ret;
5849                         action_flags |= MLX5_FLOW_ACTION_COUNT;
5850                         ++actions_n;
5851                         break;
5852                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
5853                         if (flow_dv_validate_action_pop_vlan(dev,
5854                                                              action_flags,
5855                                                              actions,
5856                                                              item_flags, attr,
5857                                                              error))
5858                                 return -rte_errno;
5859                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
5860                         ++actions_n;
5861                         break;
5862                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
5863                         ret = flow_dv_validate_action_push_vlan(dev,
5864                                                                 action_flags,
5865                                                                 vlan_m,
5866                                                                 actions, attr,
5867                                                                 error);
5868                         if (ret < 0)
5869                                 return ret;
5870                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
5871                         ++actions_n;
5872                         break;
5873                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
5874                         ret = flow_dv_validate_action_set_vlan_pcp
5875                                                 (action_flags, actions, error);
5876                         if (ret < 0)
5877                                 return ret;
5878                         /* Count PCP with push_vlan command. */
5879                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
5880                         break;
5881                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
5882                         ret = flow_dv_validate_action_set_vlan_vid
5883                                                 (item_flags, action_flags,
5884                                                  actions, error);
5885                         if (ret < 0)
5886                                 return ret;
5887                         /* Count VID with push_vlan command. */
5888                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
5889                         rw_act_num += MLX5_ACT_NUM_MDF_VID;
5890                         break;
5891                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5892                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5893                         ret = flow_dv_validate_action_l2_encap(dev,
5894                                                                action_flags,
5895                                                                actions, attr,
5896                                                                error);
5897                         if (ret < 0)
5898                                 return ret;
5899                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
5900                         ++actions_n;
5901                         break;
5902                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
5903                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
5904                         ret = flow_dv_validate_action_decap(dev, action_flags,
5905                                                             actions, item_flags,
5906                                                             attr, error);
5907                         if (ret < 0)
5908                                 return ret;
5909                         action_flags |= MLX5_FLOW_ACTION_DECAP;
5910                         ++actions_n;
5911                         break;
5912                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5913                         ret = flow_dv_validate_action_raw_encap_decap
5914                                 (dev, NULL, actions->conf, attr, &action_flags,
5915                                  &actions_n, actions, item_flags, error);
5916                         if (ret < 0)
5917                                 return ret;
5918                         break;
5919                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
5920                         decap = actions->conf;
5921                         while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
5922                                 ;
5923                         if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
5924                                 encap = NULL;
5925                                 actions--;
5926                         } else {
5927                                 encap = actions->conf;
5928                         }
5929                         ret = flow_dv_validate_action_raw_encap_decap
5930                                            (dev,
5931                                             decap ? decap : &empty_decap, encap,
5932                                             attr, &action_flags, &actions_n,
5933                                             actions, item_flags, error);
5934                         if (ret < 0)
5935                                 return ret;
5936                         break;
5937                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
5938                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
5939                         ret = flow_dv_validate_action_modify_mac(action_flags,
5940                                                                  actions,
5941                                                                  item_flags,
5942                                                                  error);
5943                         if (ret < 0)
5944                                 return ret;
5945                         /* Count all modify-header actions as one action. */
5946                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5947                                 ++actions_n;
5948                         action_flags |= actions->type ==
5949                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
5950                                                 MLX5_FLOW_ACTION_SET_MAC_SRC :
5951                                                 MLX5_FLOW_ACTION_SET_MAC_DST;
5952                         /*
5953                          * Even if the source and destination MAC addresses have
5954                          * overlap in the header with 4B alignment, the convert
5955                          * function will handle them separately and 4 SW actions
5956                          * will be created. And 2 actions will be added each
5957                          * time no matter how many bytes of address will be set.
5958                          */
5959                         rw_act_num += MLX5_ACT_NUM_MDF_MAC;
5960                         break;
5961                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
5962                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
5963                         ret = flow_dv_validate_action_modify_ipv4(action_flags,
5964                                                                   actions,
5965                                                                   item_flags,
5966                                                                   error);
5967                         if (ret < 0)
5968                                 return ret;
5969                         /* Count all modify-header actions as one action. */
5970                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5971                                 ++actions_n;
5972                         action_flags |= actions->type ==
5973                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
5974                                                 MLX5_FLOW_ACTION_SET_IPV4_SRC :
5975                                                 MLX5_FLOW_ACTION_SET_IPV4_DST;
5976                         rw_act_num += MLX5_ACT_NUM_MDF_IPV4;
5977                         break;
5978                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
5979                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
5980                         ret = flow_dv_validate_action_modify_ipv6(action_flags,
5981                                                                   actions,
5982                                                                   item_flags,
5983                                                                   error);
5984                         if (ret < 0)
5985                                 return ret;
5986                         if (item_ipv6_proto == IPPROTO_ICMPV6)
5987                                 return rte_flow_error_set(error, ENOTSUP,
5988                                         RTE_FLOW_ERROR_TYPE_ACTION,
5989                                         actions,
5990                                         "Can't change header "
5991                                         "with ICMPv6 proto");
5992                         /* Count all modify-header actions as one action. */
5993                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5994                                 ++actions_n;
5995                         action_flags |= actions->type ==
5996                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
5997                                                 MLX5_FLOW_ACTION_SET_IPV6_SRC :
5998                                                 MLX5_FLOW_ACTION_SET_IPV6_DST;
5999                         rw_act_num += MLX5_ACT_NUM_MDF_IPV6;
6000                         break;
6001                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
6002                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
6003                         ret = flow_dv_validate_action_modify_tp(action_flags,
6004                                                                 actions,
6005                                                                 item_flags,
6006                                                                 error);
6007                         if (ret < 0)
6008                                 return ret;
6009                         /* Count all modify-header actions as one action. */
6010                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6011                                 ++actions_n;
6012                         action_flags |= actions->type ==
6013                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
6014                                                 MLX5_FLOW_ACTION_SET_TP_SRC :
6015                                                 MLX5_FLOW_ACTION_SET_TP_DST;
6016                         rw_act_num += MLX5_ACT_NUM_MDF_PORT;
6017                         break;
6018                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
6019                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
6020                         ret = flow_dv_validate_action_modify_ttl(action_flags,
6021                                                                  actions,
6022                                                                  item_flags,
6023                                                                  error);
6024                         if (ret < 0)
6025                                 return ret;
6026                         /* Count all modify-header actions as one action. */
6027                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6028                                 ++actions_n;
6029                         action_flags |= actions->type ==
6030                                         RTE_FLOW_ACTION_TYPE_SET_TTL ?
6031                                                 MLX5_FLOW_ACTION_SET_TTL :
6032                                                 MLX5_FLOW_ACTION_DEC_TTL;
6033                         rw_act_num += MLX5_ACT_NUM_MDF_TTL;
6034                         break;
6035                 case RTE_FLOW_ACTION_TYPE_JUMP:
6036                         ret = flow_dv_validate_action_jump(dev, tunnel, actions,
6037                                                            action_flags,
6038                                                            attr, external,
6039                                                            error);
6040                         if (ret)
6041                                 return ret;
6042                         ++actions_n;
6043                         action_flags |= MLX5_FLOW_ACTION_JUMP;
6044                         break;
6045                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
6046                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
6047                         ret = flow_dv_validate_action_modify_tcp_seq
6048                                                                 (action_flags,
6049                                                                  actions,
6050                                                                  item_flags,
6051                                                                  error);
6052                         if (ret < 0)
6053                                 return ret;
6054                         /* Count all modify-header actions as one action. */
6055                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6056                                 ++actions_n;
6057                         action_flags |= actions->type ==
6058                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
6059                                                 MLX5_FLOW_ACTION_INC_TCP_SEQ :
6060                                                 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
6061                         rw_act_num += MLX5_ACT_NUM_MDF_TCPSEQ;
6062                         break;
6063                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
6064                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
6065                         ret = flow_dv_validate_action_modify_tcp_ack
6066                                                                 (action_flags,
6067                                                                  actions,
6068                                                                  item_flags,
6069                                                                  error);
6070                         if (ret < 0)
6071                                 return ret;
6072                         /* Count all modify-header actions as one action. */
6073                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6074                                 ++actions_n;
6075                         action_flags |= actions->type ==
6076                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
6077                                                 MLX5_FLOW_ACTION_INC_TCP_ACK :
6078                                                 MLX5_FLOW_ACTION_DEC_TCP_ACK;
6079                         rw_act_num += MLX5_ACT_NUM_MDF_TCPACK;
6080                         break;
6081                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
6082                         break;
6083                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
6084                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
6085                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
6086                         break;
6087                 case RTE_FLOW_ACTION_TYPE_METER:
6088                         ret = mlx5_flow_validate_action_meter(dev,
6089                                                               action_flags,
6090                                                               actions, attr,
6091                                                               error);
6092                         if (ret < 0)
6093                                 return ret;
6094                         action_flags |= MLX5_FLOW_ACTION_METER;
6095                         ++actions_n;
6096                         /* Meter action will add one more TAG action. */
6097                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
6098                         break;
6099                 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
6100                         if (!attr->transfer && !attr->group)
6101                                 return rte_flow_error_set(error, ENOTSUP,
6102                                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6103                                                                            NULL,
6104                           "Shared ASO age action is not supported for group 0");
6105                         action_flags |= MLX5_FLOW_ACTION_AGE;
6106                         ++actions_n;
6107                         break;
6108                 case RTE_FLOW_ACTION_TYPE_AGE:
6109                         ret = flow_dv_validate_action_age(action_flags,
6110                                                           actions, dev,
6111                                                           error);
6112                         if (ret < 0)
6113                                 return ret;
6114                         action_flags |= MLX5_FLOW_ACTION_AGE;
6115                         ++actions_n;
6116                         break;
6117                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
6118                         ret = flow_dv_validate_action_modify_ipv4_dscp
6119                                                          (action_flags,
6120                                                           actions,
6121                                                           item_flags,
6122                                                           error);
6123                         if (ret < 0)
6124                                 return ret;
6125                         /* Count all modify-header actions as one action. */
6126                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6127                                 ++actions_n;
6128                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
6129                         rw_act_num += MLX5_ACT_NUM_SET_DSCP;
6130                         break;
6131                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
6132                         ret = flow_dv_validate_action_modify_ipv6_dscp
6133                                                                 (action_flags,
6134                                                                  actions,
6135                                                                  item_flags,
6136                                                                  error);
6137                         if (ret < 0)
6138                                 return ret;
6139                         /* Count all modify-header actions as one action. */
6140                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6141                                 ++actions_n;
6142                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
6143                         rw_act_num += MLX5_ACT_NUM_SET_DSCP;
6144                         break;
6145                 case RTE_FLOW_ACTION_TYPE_SAMPLE:
6146                         ret = flow_dv_validate_action_sample(action_flags,
6147                                                              actions, dev,
6148                                                              attr, item_flags,
6149                                                              rss, &sample_rss,
6150                                                              error);
6151                         if (ret < 0)
6152                                 return ret;
6153                         action_flags |= MLX5_FLOW_ACTION_SAMPLE;
6154                         ++actions_n;
6155                         break;
6156                 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
6157                         if (actions[0].type != (typeof(actions[0].type))
6158                                 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET)
6159                                 return rte_flow_error_set
6160                                                 (error, EINVAL,
6161                                                 RTE_FLOW_ERROR_TYPE_ACTION,
6162                                                 NULL, "MLX5 private action "
6163                                                 "must be the first");
6164
6165                         action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
6166                         break;
6167                 default:
6168                         return rte_flow_error_set(error, ENOTSUP,
6169                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6170                                                   actions,
6171                                                   "action not supported");
6172                 }
6173         }
6174         /*
6175          * Validate actions in flow rules
6176          * - Explicit decap action is prohibited by the tunnel offload API.
6177          * - Drop action in tunnel steer rule is prohibited by the API.
6178          * - Application cannot use MARK action because it's value can mask
6179          *   tunnel default miss nitification.
6180          * - JUMP in tunnel match rule has no support in current PMD
6181          *   implementation.
6182          * - TAG & META are reserved for future uses.
6183          */
6184         if (action_flags & MLX5_FLOW_ACTION_TUNNEL_SET) {
6185                 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_DECAP    |
6186                                             MLX5_FLOW_ACTION_MARK     |
6187                                             MLX5_FLOW_ACTION_SET_TAG  |
6188                                             MLX5_FLOW_ACTION_SET_META |
6189                                             MLX5_FLOW_ACTION_DROP;
6190
6191                 if (action_flags & bad_actions_mask)
6192                         return rte_flow_error_set
6193                                         (error, EINVAL,
6194                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6195                                         "Invalid RTE action in tunnel "
6196                                         "set decap rule");
6197                 if (!(action_flags & MLX5_FLOW_ACTION_JUMP))
6198                         return rte_flow_error_set
6199                                         (error, EINVAL,
6200                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6201                                         "tunnel set decap rule must terminate "
6202                                         "with JUMP");
6203                 if (!attr->ingress)
6204                         return rte_flow_error_set
6205                                         (error, EINVAL,
6206                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6207                                         "tunnel flows for ingress traffic only");
6208         }
6209         if (action_flags & MLX5_FLOW_ACTION_TUNNEL_MATCH) {
6210                 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_JUMP    |
6211                                             MLX5_FLOW_ACTION_MARK    |
6212                                             MLX5_FLOW_ACTION_SET_TAG |
6213                                             MLX5_FLOW_ACTION_SET_META;
6214
6215                 if (action_flags & bad_actions_mask)
6216                         return rte_flow_error_set
6217                                         (error, EINVAL,
6218                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6219                                         "Invalid RTE action in tunnel "
6220                                         "set match rule");
6221         }
6222         /*
6223          * Validate the drop action mutual exclusion with other actions.
6224          * Drop action is mutually-exclusive with any other action, except for
6225          * Count action.
6226          */
6227         if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
6228             (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
6229                 return rte_flow_error_set(error, EINVAL,
6230                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6231                                           "Drop action is mutually-exclusive "
6232                                           "with any other action, except for "
6233                                           "Count action");
6234         /* Eswitch has few restrictions on using items and actions */
6235         if (attr->transfer) {
6236                 if (!mlx5_flow_ext_mreg_supported(dev) &&
6237                     action_flags & MLX5_FLOW_ACTION_FLAG)
6238                         return rte_flow_error_set(error, ENOTSUP,
6239                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6240                                                   NULL,
6241                                                   "unsupported action FLAG");
6242                 if (!mlx5_flow_ext_mreg_supported(dev) &&
6243                     action_flags & MLX5_FLOW_ACTION_MARK)
6244                         return rte_flow_error_set(error, ENOTSUP,
6245                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6246                                                   NULL,
6247                                                   "unsupported action MARK");
6248                 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
6249                         return rte_flow_error_set(error, ENOTSUP,
6250                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6251                                                   NULL,
6252                                                   "unsupported action QUEUE");
6253                 if (action_flags & MLX5_FLOW_ACTION_RSS)
6254                         return rte_flow_error_set(error, ENOTSUP,
6255                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6256                                                   NULL,
6257                                                   "unsupported action RSS");
6258                 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
6259                         return rte_flow_error_set(error, EINVAL,
6260                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6261                                                   actions,
6262                                                   "no fate action is found");
6263         } else {
6264                 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
6265                         return rte_flow_error_set(error, EINVAL,
6266                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6267                                                   actions,
6268                                                   "no fate action is found");
6269         }
6270         /*
6271          * Continue validation for Xcap and VLAN actions.
6272          * If hairpin is working in explicit TX rule mode, there is no actions
6273          * splitting and the validation of hairpin ingress flow should be the
6274          * same as other standard flows.
6275          */
6276         if ((action_flags & (MLX5_FLOW_XCAP_ACTIONS |
6277                              MLX5_FLOW_VLAN_ACTIONS)) &&
6278             (queue_index == 0xFFFF ||
6279              mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN ||
6280              ((conf = mlx5_rxq_get_hairpin_conf(dev, queue_index)) != NULL &&
6281              conf->tx_explicit != 0))) {
6282                 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
6283                     MLX5_FLOW_XCAP_ACTIONS)
6284                         return rte_flow_error_set(error, ENOTSUP,
6285                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6286                                                   NULL, "encap and decap "
6287                                                   "combination aren't supported");
6288                 if (!attr->transfer && attr->ingress) {
6289                         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
6290                                 return rte_flow_error_set
6291                                                 (error, ENOTSUP,
6292                                                  RTE_FLOW_ERROR_TYPE_ACTION,
6293                                                  NULL, "encap is not supported"
6294                                                  " for ingress traffic");
6295                         else if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
6296                                 return rte_flow_error_set
6297                                                 (error, ENOTSUP,
6298                                                  RTE_FLOW_ERROR_TYPE_ACTION,
6299                                                  NULL, "push VLAN action not "
6300                                                  "supported for ingress");
6301                         else if ((action_flags & MLX5_FLOW_VLAN_ACTIONS) ==
6302                                         MLX5_FLOW_VLAN_ACTIONS)
6303                                 return rte_flow_error_set
6304                                                 (error, ENOTSUP,
6305                                                  RTE_FLOW_ERROR_TYPE_ACTION,
6306                                                  NULL, "no support for "
6307                                                  "multiple VLAN actions");
6308                 }
6309         }
6310         /*
6311          * Hairpin flow will add one more TAG action in TX implicit mode.
6312          * In TX explicit mode, there will be no hairpin flow ID.
6313          */
6314         if (hairpin > 0)
6315                 rw_act_num += MLX5_ACT_NUM_SET_TAG;
6316         /* extra metadata enabled: one more TAG action will be add. */
6317         if (dev_conf->dv_flow_en &&
6318             dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
6319             mlx5_flow_ext_mreg_supported(dev))
6320                 rw_act_num += MLX5_ACT_NUM_SET_TAG;
6321         if ((uint32_t)rw_act_num >
6322                         flow_dv_modify_hdr_action_max(dev, is_root)) {
6323                 return rte_flow_error_set(error, ENOTSUP,
6324                                           RTE_FLOW_ERROR_TYPE_ACTION,
6325                                           NULL, "too many header modify"
6326                                           " actions to support");
6327         }
6328         return 0;
6329 }
6330
6331 /**
6332  * Internal preparation function. Allocates the DV flow size,
6333  * this size is constant.
6334  *
6335  * @param[in] dev
6336  *   Pointer to the rte_eth_dev structure.
6337  * @param[in] attr
6338  *   Pointer to the flow attributes.
6339  * @param[in] items
6340  *   Pointer to the list of items.
6341  * @param[in] actions
6342  *   Pointer to the list of actions.
6343  * @param[out] error
6344  *   Pointer to the error structure.
6345  *
6346  * @return
6347  *   Pointer to mlx5_flow object on success,
6348  *   otherwise NULL and rte_errno is set.
6349  */
6350 static struct mlx5_flow *
6351 flow_dv_prepare(struct rte_eth_dev *dev,
6352                 const struct rte_flow_attr *attr __rte_unused,
6353                 const struct rte_flow_item items[] __rte_unused,
6354                 const struct rte_flow_action actions[] __rte_unused,
6355                 struct rte_flow_error *error)
6356 {
6357         uint32_t handle_idx = 0;
6358         struct mlx5_flow *dev_flow;
6359         struct mlx5_flow_handle *dev_handle;
6360         struct mlx5_priv *priv = dev->data->dev_private;
6361         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
6362
6363         MLX5_ASSERT(wks);
6364         /* In case of corrupting the memory. */
6365         if (wks->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
6366                 rte_flow_error_set(error, ENOSPC,
6367                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6368                                    "not free temporary device flow");
6369                 return NULL;
6370         }
6371         dev_handle = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
6372                                    &handle_idx);
6373         if (!dev_handle) {
6374                 rte_flow_error_set(error, ENOMEM,
6375                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6376                                    "not enough memory to create flow handle");
6377                 return NULL;
6378         }
6379         MLX5_ASSERT(wks->flow_idx < RTE_DIM(wks->flows));
6380         dev_flow = &wks->flows[wks->flow_idx++];
6381         memset(dev_flow, 0, sizeof(*dev_flow));
6382         dev_flow->handle = dev_handle;
6383         dev_flow->handle_idx = handle_idx;
6384         /*
6385          * In some old rdma-core releases, before continuing, a check of the
6386          * length of matching parameter will be done at first. It needs to use
6387          * the length without misc4 param. If the flow has misc4 support, then
6388          * the length needs to be adjusted accordingly. Each param member is
6389          * aligned with a 64B boundary naturally.
6390          */
6391         dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param) -
6392                                   MLX5_ST_SZ_BYTES(fte_match_set_misc4);
6393         dev_flow->ingress = attr->ingress;
6394         dev_flow->dv.transfer = attr->transfer;
6395         return dev_flow;
6396 }
6397
6398 #ifdef RTE_LIBRTE_MLX5_DEBUG
6399 /**
6400  * Sanity check for match mask and value. Similar to check_valid_spec() in
6401  * kernel driver. If unmasked bit is present in value, it returns failure.
6402  *
6403  * @param match_mask
6404  *   pointer to match mask buffer.
6405  * @param match_value
6406  *   pointer to match value buffer.
6407  *
6408  * @return
6409  *   0 if valid, -EINVAL otherwise.
6410  */
6411 static int
6412 flow_dv_check_valid_spec(void *match_mask, void *match_value)
6413 {
6414         uint8_t *m = match_mask;
6415         uint8_t *v = match_value;
6416         unsigned int i;
6417
6418         for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
6419                 if (v[i] & ~m[i]) {
6420                         DRV_LOG(ERR,
6421                                 "match_value differs from match_criteria"
6422                                 " %p[%u] != %p[%u]",
6423                                 match_value, i, match_mask, i);
6424                         return -EINVAL;
6425                 }
6426         }
6427         return 0;
6428 }
6429 #endif
6430
6431 /**
6432  * Add match of ip_version.
6433  *
6434  * @param[in] group
6435  *   Flow group.
6436  * @param[in] headers_v
6437  *   Values header pointer.
6438  * @param[in] headers_m
6439  *   Masks header pointer.
6440  * @param[in] ip_version
6441  *   The IP version to set.
6442  */
6443 static inline void
6444 flow_dv_set_match_ip_version(uint32_t group,
6445                              void *headers_v,
6446                              void *headers_m,
6447                              uint8_t ip_version)
6448 {
6449         if (group == 0)
6450                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
6451         else
6452                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version,
6453                          ip_version);
6454         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, ip_version);
6455         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, 0);
6456         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype, 0);
6457 }
6458
6459 /**
6460  * Add Ethernet item to matcher and to the value.
6461  *
6462  * @param[in, out] matcher
6463  *   Flow matcher.
6464  * @param[in, out] key
6465  *   Flow matcher value.
6466  * @param[in] item
6467  *   Flow pattern to translate.
6468  * @param[in] inner
6469  *   Item is inner pattern.
6470  */
6471 static void
6472 flow_dv_translate_item_eth(void *matcher, void *key,
6473                            const struct rte_flow_item *item, int inner,
6474                            uint32_t group)
6475 {
6476         const struct rte_flow_item_eth *eth_m = item->mask;
6477         const struct rte_flow_item_eth *eth_v = item->spec;
6478         const struct rte_flow_item_eth nic_mask = {
6479                 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
6480                 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
6481                 .type = RTE_BE16(0xffff),
6482                 .has_vlan = 0,
6483         };
6484         void *hdrs_m;
6485         void *hdrs_v;
6486         char *l24_v;
6487         unsigned int i;
6488
6489         if (!eth_v)
6490                 return;
6491         if (!eth_m)
6492                 eth_m = &nic_mask;
6493         if (inner) {
6494                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
6495                                          inner_headers);
6496                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6497         } else {
6498                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
6499                                          outer_headers);
6500                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6501         }
6502         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, dmac_47_16),
6503                &eth_m->dst, sizeof(eth_m->dst));
6504         /* The value must be in the range of the mask. */
6505         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, dmac_47_16);
6506         for (i = 0; i < sizeof(eth_m->dst); ++i)
6507                 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
6508         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, smac_47_16),
6509                &eth_m->src, sizeof(eth_m->src));
6510         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, smac_47_16);
6511         /* The value must be in the range of the mask. */
6512         for (i = 0; i < sizeof(eth_m->dst); ++i)
6513                 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
6514         /*
6515          * HW supports match on one Ethertype, the Ethertype following the last
6516          * VLAN tag of the packet (see PRM).
6517          * Set match on ethertype only if ETH header is not followed by VLAN.
6518          * HW is optimized for IPv4/IPv6. In such cases, avoid setting
6519          * ethertype, and use ip_version field instead.
6520          * eCPRI over Ether layer will use type value 0xAEFE.
6521          */
6522         if (eth_m->type == 0xFFFF) {
6523                 /* Set cvlan_tag mask for any single\multi\un-tagged case. */
6524                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
6525                 switch (eth_v->type) {
6526                 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
6527                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
6528                         return;
6529                 case RTE_BE16(RTE_ETHER_TYPE_QINQ):
6530                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
6531                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
6532                         return;
6533                 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
6534                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
6535                         return;
6536                 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
6537                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
6538                         return;
6539                 default:
6540                         break;
6541                 }
6542         }
6543         if (eth_m->has_vlan) {
6544                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
6545                 if (eth_v->has_vlan) {
6546                         /*
6547                          * Here, when also has_more_vlan field in VLAN item is
6548                          * not set, only single-tagged packets will be matched.
6549                          */
6550                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
6551                         return;
6552                 }
6553         }
6554         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
6555                  rte_be_to_cpu_16(eth_m->type));
6556         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, ethertype);
6557         *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
6558 }
6559
6560 /**
6561  * Add VLAN item to matcher and to the value.
6562  *
6563  * @param[in, out] dev_flow
6564  *   Flow descriptor.
6565  * @param[in, out] matcher
6566  *   Flow matcher.
6567  * @param[in, out] key
6568  *   Flow matcher value.
6569  * @param[in] item
6570  *   Flow pattern to translate.
6571  * @param[in] inner
6572  *   Item is inner pattern.
6573  */
6574 static void
6575 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
6576                             void *matcher, void *key,
6577                             const struct rte_flow_item *item,
6578                             int inner, uint32_t group)
6579 {
6580         const struct rte_flow_item_vlan *vlan_m = item->mask;
6581         const struct rte_flow_item_vlan *vlan_v = item->spec;
6582         void *hdrs_m;
6583         void *hdrs_v;
6584         uint16_t tci_m;
6585         uint16_t tci_v;
6586
6587         if (inner) {
6588                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
6589                                          inner_headers);
6590                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6591         } else {
6592                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
6593                                          outer_headers);
6594                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6595                 /*
6596                  * This is workaround, masks are not supported,
6597                  * and pre-validated.
6598                  */
6599                 if (vlan_v)
6600                         dev_flow->handle->vf_vlan.tag =
6601                                         rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
6602         }
6603         /*
6604          * When VLAN item exists in flow, mark packet as tagged,
6605          * even if TCI is not specified.
6606          */
6607         if (!MLX5_GET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag)) {
6608                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
6609                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
6610         }
6611         if (!vlan_v)
6612                 return;
6613         if (!vlan_m)
6614                 vlan_m = &rte_flow_item_vlan_mask;
6615         tci_m = rte_be_to_cpu_16(vlan_m->tci);
6616         tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
6617         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_vid, tci_m);
6618         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_vid, tci_v);
6619         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_cfi, tci_m >> 12);
6620         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_cfi, tci_v >> 12);
6621         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_prio, tci_m >> 13);
6622         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_prio, tci_v >> 13);
6623         /*
6624          * HW is optimized for IPv4/IPv6. In such cases, avoid setting
6625          * ethertype, and use ip_version field instead.
6626          */
6627         if (vlan_m->inner_type == 0xFFFF) {
6628                 switch (vlan_v->inner_type) {
6629                 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
6630                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
6631                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
6632                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
6633                         return;
6634                 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
6635                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
6636                         return;
6637                 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
6638                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
6639                         return;
6640                 default:
6641                         break;
6642                 }
6643         }
6644         if (vlan_m->has_more_vlan && vlan_v->has_more_vlan) {
6645                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
6646                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
6647                 /* Only one vlan_tag bit can be set. */
6648                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
6649                 return;
6650         }
6651         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
6652                  rte_be_to_cpu_16(vlan_m->inner_type));
6653         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, ethertype,
6654                  rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
6655 }
6656
6657 /**
6658  * Add IPV4 item to matcher and to the value.
6659  *
6660  * @param[in, out] matcher
6661  *   Flow matcher.
6662  * @param[in, out] key
6663  *   Flow matcher value.
6664  * @param[in] item
6665  *   Flow pattern to translate.
6666  * @param[in] inner
6667  *   Item is inner pattern.
6668  * @param[in] group
6669  *   The group to insert the rule.
6670  */
6671 static void
6672 flow_dv_translate_item_ipv4(void *matcher, void *key,
6673                             const struct rte_flow_item *item,
6674                             int inner, uint32_t group)
6675 {
6676         const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
6677         const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
6678         const struct rte_flow_item_ipv4 nic_mask = {
6679                 .hdr = {
6680                         .src_addr = RTE_BE32(0xffffffff),
6681                         .dst_addr = RTE_BE32(0xffffffff),
6682                         .type_of_service = 0xff,
6683                         .next_proto_id = 0xff,
6684                         .time_to_live = 0xff,
6685                 },
6686         };
6687         void *headers_m;
6688         void *headers_v;
6689         char *l24_m;
6690         char *l24_v;
6691         uint8_t tos;
6692
6693         if (inner) {
6694                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6695                                          inner_headers);
6696                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6697         } else {
6698                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6699                                          outer_headers);
6700                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6701         }
6702         flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
6703         if (!ipv4_v)
6704                 return;
6705         if (!ipv4_m)
6706                 ipv4_m = &nic_mask;
6707         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6708                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
6709         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6710                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
6711         *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
6712         *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
6713         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6714                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
6715         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6716                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
6717         *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
6718         *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
6719         tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
6720         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
6721                  ipv4_m->hdr.type_of_service);
6722         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
6723         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
6724                  ipv4_m->hdr.type_of_service >> 2);
6725         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
6726         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6727                  ipv4_m->hdr.next_proto_id);
6728         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6729                  ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
6730         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
6731                  ipv4_m->hdr.time_to_live);
6732         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
6733                  ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
6734         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
6735                  !!(ipv4_m->hdr.fragment_offset));
6736         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
6737                  !!(ipv4_v->hdr.fragment_offset & ipv4_m->hdr.fragment_offset));
6738 }
6739
6740 /**
6741  * Add IPV6 item to matcher and to the value.
6742  *
6743  * @param[in, out] matcher
6744  *   Flow matcher.
6745  * @param[in, out] key
6746  *   Flow matcher value.
6747  * @param[in] item
6748  *   Flow pattern to translate.
6749  * @param[in] inner
6750  *   Item is inner pattern.
6751  * @param[in] group
6752  *   The group to insert the rule.
6753  */
6754 static void
6755 flow_dv_translate_item_ipv6(void *matcher, void *key,
6756                             const struct rte_flow_item *item,
6757                             int inner, uint32_t group)
6758 {
6759         const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
6760         const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
6761         const struct rte_flow_item_ipv6 nic_mask = {
6762                 .hdr = {
6763                         .src_addr =
6764                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
6765                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
6766                         .dst_addr =
6767                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
6768                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
6769                         .vtc_flow = RTE_BE32(0xffffffff),
6770                         .proto = 0xff,
6771                         .hop_limits = 0xff,
6772                 },
6773         };
6774         void *headers_m;
6775         void *headers_v;
6776         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6777         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6778         char *l24_m;
6779         char *l24_v;
6780         uint32_t vtc_m;
6781         uint32_t vtc_v;
6782         int i;
6783         int size;
6784
6785         if (inner) {
6786                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6787                                          inner_headers);
6788                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6789         } else {
6790                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6791                                          outer_headers);
6792                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6793         }
6794         flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
6795         if (!ipv6_v)
6796                 return;
6797         if (!ipv6_m)
6798                 ipv6_m = &nic_mask;
6799         size = sizeof(ipv6_m->hdr.dst_addr);
6800         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6801                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
6802         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6803                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
6804         memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
6805         for (i = 0; i < size; ++i)
6806                 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
6807         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6808                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
6809         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6810                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
6811         memcpy(l24_m, ipv6_m->hdr.src_addr, size);
6812         for (i = 0; i < size; ++i)
6813                 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
6814         /* TOS. */
6815         vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
6816         vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
6817         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
6818         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
6819         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
6820         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
6821         /* Label. */
6822         if (inner) {
6823                 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
6824                          vtc_m);
6825                 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
6826                          vtc_v);
6827         } else {
6828                 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
6829                          vtc_m);
6830                 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
6831                          vtc_v);
6832         }
6833         /* Protocol. */
6834         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6835                  ipv6_m->hdr.proto);
6836         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6837                  ipv6_v->hdr.proto & ipv6_m->hdr.proto);
6838         /* Hop limit. */
6839         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
6840                  ipv6_m->hdr.hop_limits);
6841         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
6842                  ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
6843         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
6844                  !!(ipv6_m->has_frag_ext));
6845         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
6846                  !!(ipv6_v->has_frag_ext & ipv6_m->has_frag_ext));
6847 }
6848
6849 /**
6850  * Add IPV6 fragment extension item to matcher and to the value.
6851  *
6852  * @param[in, out] matcher
6853  *   Flow matcher.
6854  * @param[in, out] key
6855  *   Flow matcher value.
6856  * @param[in] item
6857  *   Flow pattern to translate.
6858  * @param[in] inner
6859  *   Item is inner pattern.
6860  */
6861 static void
6862 flow_dv_translate_item_ipv6_frag_ext(void *matcher, void *key,
6863                                      const struct rte_flow_item *item,
6864                                      int inner)
6865 {
6866         const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_m = item->mask;
6867         const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_v = item->spec;
6868         const struct rte_flow_item_ipv6_frag_ext nic_mask = {
6869                 .hdr = {
6870                         .next_header = 0xff,
6871                         .frag_data = RTE_BE16(0xffff),
6872                 },
6873         };
6874         void *headers_m;
6875         void *headers_v;
6876
6877         if (inner) {
6878                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6879                                          inner_headers);
6880                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6881         } else {
6882                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6883                                          outer_headers);
6884                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6885         }
6886         /* IPv6 fragment extension item exists, so packet is IP fragment. */
6887         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
6888         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 1);
6889         if (!ipv6_frag_ext_v)
6890                 return;
6891         if (!ipv6_frag_ext_m)
6892                 ipv6_frag_ext_m = &nic_mask;
6893         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6894                  ipv6_frag_ext_m->hdr.next_header);
6895         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6896                  ipv6_frag_ext_v->hdr.next_header &
6897                  ipv6_frag_ext_m->hdr.next_header);
6898 }
6899
6900 /**
6901  * Add TCP item to matcher and to the value.
6902  *
6903  * @param[in, out] matcher
6904  *   Flow matcher.
6905  * @param[in, out] key
6906  *   Flow matcher value.
6907  * @param[in] item
6908  *   Flow pattern to translate.
6909  * @param[in] inner
6910  *   Item is inner pattern.
6911  */
6912 static void
6913 flow_dv_translate_item_tcp(void *matcher, void *key,
6914                            const struct rte_flow_item *item,
6915                            int inner)
6916 {
6917         const struct rte_flow_item_tcp *tcp_m = item->mask;
6918         const struct rte_flow_item_tcp *tcp_v = item->spec;
6919         void *headers_m;
6920         void *headers_v;
6921
6922         if (inner) {
6923                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6924                                          inner_headers);
6925                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6926         } else {
6927                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6928                                          outer_headers);
6929                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6930         }
6931         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6932         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
6933         if (!tcp_v)
6934                 return;
6935         if (!tcp_m)
6936                 tcp_m = &rte_flow_item_tcp_mask;
6937         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
6938                  rte_be_to_cpu_16(tcp_m->hdr.src_port));
6939         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
6940                  rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
6941         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
6942                  rte_be_to_cpu_16(tcp_m->hdr.dst_port));
6943         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
6944                  rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
6945         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
6946                  tcp_m->hdr.tcp_flags);
6947         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
6948                  (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
6949 }
6950
6951 /**
6952  * Add UDP item to matcher and to the value.
6953  *
6954  * @param[in, out] matcher
6955  *   Flow matcher.
6956  * @param[in, out] key
6957  *   Flow matcher value.
6958  * @param[in] item
6959  *   Flow pattern to translate.
6960  * @param[in] inner
6961  *   Item is inner pattern.
6962  */
6963 static void
6964 flow_dv_translate_item_udp(void *matcher, void *key,
6965                            const struct rte_flow_item *item,
6966                            int inner)
6967 {
6968         const struct rte_flow_item_udp *udp_m = item->mask;
6969         const struct rte_flow_item_udp *udp_v = item->spec;
6970         void *headers_m;
6971         void *headers_v;
6972
6973         if (inner) {
6974                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6975                                          inner_headers);
6976                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6977         } else {
6978                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6979                                          outer_headers);
6980                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6981         }
6982         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6983         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
6984         if (!udp_v)
6985                 return;
6986         if (!udp_m)
6987                 udp_m = &rte_flow_item_udp_mask;
6988         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
6989                  rte_be_to_cpu_16(udp_m->hdr.src_port));
6990         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
6991                  rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
6992         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
6993                  rte_be_to_cpu_16(udp_m->hdr.dst_port));
6994         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
6995                  rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
6996 }
6997
6998 /**
6999  * Add GRE optional Key item to matcher and to the value.
7000  *
7001  * @param[in, out] matcher
7002  *   Flow matcher.
7003  * @param[in, out] key
7004  *   Flow matcher value.
7005  * @param[in] item
7006  *   Flow pattern to translate.
7007  * @param[in] inner
7008  *   Item is inner pattern.
7009  */
7010 static void
7011 flow_dv_translate_item_gre_key(void *matcher, void *key,
7012                                    const struct rte_flow_item *item)
7013 {
7014         const rte_be32_t *key_m = item->mask;
7015         const rte_be32_t *key_v = item->spec;
7016         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7017         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7018         rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
7019
7020         /* GRE K bit must be on and should already be validated */
7021         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
7022         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
7023         if (!key_v)
7024                 return;
7025         if (!key_m)
7026                 key_m = &gre_key_default_mask;
7027         MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
7028                  rte_be_to_cpu_32(*key_m) >> 8);
7029         MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
7030                  rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
7031         MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
7032                  rte_be_to_cpu_32(*key_m) & 0xFF);
7033         MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
7034                  rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
7035 }
7036
7037 /**
7038  * Add GRE item to matcher and to the value.
7039  *
7040  * @param[in, out] matcher
7041  *   Flow matcher.
7042  * @param[in, out] key
7043  *   Flow matcher value.
7044  * @param[in] item
7045  *   Flow pattern to translate.
7046  * @param[in] inner
7047  *   Item is inner pattern.
7048  */
7049 static void
7050 flow_dv_translate_item_gre(void *matcher, void *key,
7051                            const struct rte_flow_item *item,
7052                            int inner)
7053 {
7054         const struct rte_flow_item_gre *gre_m = item->mask;
7055         const struct rte_flow_item_gre *gre_v = item->spec;
7056         void *headers_m;
7057         void *headers_v;
7058         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7059         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7060         struct {
7061                 union {
7062                         __extension__
7063                         struct {
7064                                 uint16_t version:3;
7065                                 uint16_t rsvd0:9;
7066                                 uint16_t s_present:1;
7067                                 uint16_t k_present:1;
7068                                 uint16_t rsvd_bit1:1;
7069                                 uint16_t c_present:1;
7070                         };
7071                         uint16_t value;
7072                 };
7073         } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
7074
7075         if (inner) {
7076                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7077                                          inner_headers);
7078                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7079         } else {
7080                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7081                                          outer_headers);
7082                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7083         }
7084         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7085         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
7086         if (!gre_v)
7087                 return;
7088         if (!gre_m)
7089                 gre_m = &rte_flow_item_gre_mask;
7090         MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
7091                  rte_be_to_cpu_16(gre_m->protocol));
7092         MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
7093                  rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
7094         gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
7095         gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
7096         MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
7097                  gre_crks_rsvd0_ver_m.c_present);
7098         MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
7099                  gre_crks_rsvd0_ver_v.c_present &
7100                  gre_crks_rsvd0_ver_m.c_present);
7101         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
7102                  gre_crks_rsvd0_ver_m.k_present);
7103         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
7104                  gre_crks_rsvd0_ver_v.k_present &
7105                  gre_crks_rsvd0_ver_m.k_present);
7106         MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
7107                  gre_crks_rsvd0_ver_m.s_present);
7108         MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
7109                  gre_crks_rsvd0_ver_v.s_present &
7110                  gre_crks_rsvd0_ver_m.s_present);
7111 }
7112
7113 /**
7114  * Add NVGRE item to matcher and to the value.
7115  *
7116  * @param[in, out] matcher
7117  *   Flow matcher.
7118  * @param[in, out] key
7119  *   Flow matcher value.
7120  * @param[in] item
7121  *   Flow pattern to translate.
7122  * @param[in] inner
7123  *   Item is inner pattern.
7124  */
7125 static void
7126 flow_dv_translate_item_nvgre(void *matcher, void *key,
7127                              const struct rte_flow_item *item,
7128                              int inner)
7129 {
7130         const struct rte_flow_item_nvgre *nvgre_m = item->mask;
7131         const struct rte_flow_item_nvgre *nvgre_v = item->spec;
7132         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7133         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7134         const char *tni_flow_id_m;
7135         const char *tni_flow_id_v;
7136         char *gre_key_m;
7137         char *gre_key_v;
7138         int size;
7139         int i;
7140
7141         /* For NVGRE, GRE header fields must be set with defined values. */
7142         const struct rte_flow_item_gre gre_spec = {
7143                 .c_rsvd0_ver = RTE_BE16(0x2000),
7144                 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
7145         };
7146         const struct rte_flow_item_gre gre_mask = {
7147                 .c_rsvd0_ver = RTE_BE16(0xB000),
7148                 .protocol = RTE_BE16(UINT16_MAX),
7149         };
7150         const struct rte_flow_item gre_item = {
7151                 .spec = &gre_spec,
7152                 .mask = &gre_mask,
7153                 .last = NULL,
7154         };
7155         flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
7156         if (!nvgre_v)
7157                 return;
7158         if (!nvgre_m)
7159                 nvgre_m = &rte_flow_item_nvgre_mask;
7160         tni_flow_id_m = (const char *)nvgre_m->tni;
7161         tni_flow_id_v = (const char *)nvgre_v->tni;
7162         size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
7163         gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
7164         gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
7165         memcpy(gre_key_m, tni_flow_id_m, size);
7166         for (i = 0; i < size; ++i)
7167                 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
7168 }
7169
7170 /**
7171  * Add VXLAN item to matcher and to the value.
7172  *
7173  * @param[in, out] matcher
7174  *   Flow matcher.
7175  * @param[in, out] key
7176  *   Flow matcher value.
7177  * @param[in] item
7178  *   Flow pattern to translate.
7179  * @param[in] inner
7180  *   Item is inner pattern.
7181  */
7182 static void
7183 flow_dv_translate_item_vxlan(void *matcher, void *key,
7184                              const struct rte_flow_item *item,
7185                              int inner)
7186 {
7187         const struct rte_flow_item_vxlan *vxlan_m = item->mask;
7188         const struct rte_flow_item_vxlan *vxlan_v = item->spec;
7189         void *headers_m;
7190         void *headers_v;
7191         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7192         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7193         char *vni_m;
7194         char *vni_v;
7195         uint16_t dport;
7196         int size;
7197         int i;
7198
7199         if (inner) {
7200                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7201                                          inner_headers);
7202                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7203         } else {
7204                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7205                                          outer_headers);
7206                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7207         }
7208         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
7209                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
7210         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7211                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7212                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7213         }
7214         if (!vxlan_v)
7215                 return;
7216         if (!vxlan_m)
7217                 vxlan_m = &rte_flow_item_vxlan_mask;
7218         size = sizeof(vxlan_m->vni);
7219         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
7220         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
7221         memcpy(vni_m, vxlan_m->vni, size);
7222         for (i = 0; i < size; ++i)
7223                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
7224 }
7225
7226 /**
7227  * Add VXLAN-GPE item to matcher and to the value.
7228  *
7229  * @param[in, out] matcher
7230  *   Flow matcher.
7231  * @param[in, out] key
7232  *   Flow matcher value.
7233  * @param[in] item
7234  *   Flow pattern to translate.
7235  * @param[in] inner
7236  *   Item is inner pattern.
7237  */
7238
7239 static void
7240 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
7241                                  const struct rte_flow_item *item, int inner)
7242 {
7243         const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
7244         const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
7245         void *headers_m;
7246         void *headers_v;
7247         void *misc_m =
7248                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
7249         void *misc_v =
7250                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7251         char *vni_m;
7252         char *vni_v;
7253         uint16_t dport;
7254         int size;
7255         int i;
7256         uint8_t flags_m = 0xff;
7257         uint8_t flags_v = 0xc;
7258
7259         if (inner) {
7260                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7261                                          inner_headers);
7262                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7263         } else {
7264                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7265                                          outer_headers);
7266                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7267         }
7268         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
7269                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
7270         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7271                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7272                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7273         }
7274         if (!vxlan_v)
7275                 return;
7276         if (!vxlan_m)
7277                 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
7278         size = sizeof(vxlan_m->vni);
7279         vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
7280         vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
7281         memcpy(vni_m, vxlan_m->vni, size);
7282         for (i = 0; i < size; ++i)
7283                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
7284         if (vxlan_m->flags) {
7285                 flags_m = vxlan_m->flags;
7286                 flags_v = vxlan_v->flags;
7287         }
7288         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
7289         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
7290         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
7291                  vxlan_m->protocol);
7292         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
7293                  vxlan_v->protocol);
7294 }
7295
7296 /**
7297  * Add Geneve item to matcher and to the value.
7298  *
7299  * @param[in, out] matcher
7300  *   Flow matcher.
7301  * @param[in, out] key
7302  *   Flow matcher value.
7303  * @param[in] item
7304  *   Flow pattern to translate.
7305  * @param[in] inner
7306  *   Item is inner pattern.
7307  */
7308
7309 static void
7310 flow_dv_translate_item_geneve(void *matcher, void *key,
7311                               const struct rte_flow_item *item, int inner)
7312 {
7313         const struct rte_flow_item_geneve *geneve_m = item->mask;
7314         const struct rte_flow_item_geneve *geneve_v = item->spec;
7315         void *headers_m;
7316         void *headers_v;
7317         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7318         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7319         uint16_t dport;
7320         uint16_t gbhdr_m;
7321         uint16_t gbhdr_v;
7322         char *vni_m;
7323         char *vni_v;
7324         size_t size, i;
7325
7326         if (inner) {
7327                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7328                                          inner_headers);
7329                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7330         } else {
7331                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7332                                          outer_headers);
7333                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7334         }
7335         dport = MLX5_UDP_PORT_GENEVE;
7336         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7337                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7338                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7339         }
7340         if (!geneve_v)
7341                 return;
7342         if (!geneve_m)
7343                 geneve_m = &rte_flow_item_geneve_mask;
7344         size = sizeof(geneve_m->vni);
7345         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
7346         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
7347         memcpy(vni_m, geneve_m->vni, size);
7348         for (i = 0; i < size; ++i)
7349                 vni_v[i] = vni_m[i] & geneve_v->vni[i];
7350         MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
7351                  rte_be_to_cpu_16(geneve_m->protocol));
7352         MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
7353                  rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
7354         gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
7355         gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
7356         MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
7357                  MLX5_GENEVE_OAMF_VAL(gbhdr_m));
7358         MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
7359                  MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
7360         MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
7361                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
7362         MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
7363                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
7364                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
7365 }
7366
7367 /**
7368  * Create Geneve TLV option resource.
7369  *
7370  * @param dev[in, out]
7371  *   Pointer to rte_eth_dev structure.
7372  * @param[in, out] tag_be24
7373  *   Tag value in big endian then R-shift 8.
7374  * @parm[in, out] dev_flow
7375  *   Pointer to the dev_flow.
7376  * @param[out] error
7377  *   pointer to error structure.
7378  *
7379  * @return
7380  *   0 on success otherwise -errno and errno is set.
7381  */
7382
7383 int
7384 flow_dev_geneve_tlv_option_resource_register(struct rte_eth_dev *dev,
7385                                              const struct rte_flow_item *item,
7386                                              struct rte_flow_error *error)
7387 {
7388         struct mlx5_priv *priv = dev->data->dev_private;
7389         struct mlx5_dev_ctx_shared *sh = priv->sh;
7390         struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
7391                         sh->geneve_tlv_option_resource;
7392         struct mlx5_devx_obj *obj;
7393         const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
7394         int ret = 0;
7395
7396         if (!geneve_opt_v)
7397                 return -1;
7398         rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
7399         if (geneve_opt_resource != NULL) {
7400                 if (geneve_opt_resource->option_class ==
7401                         geneve_opt_v->option_class &&
7402                         geneve_opt_resource->option_type ==
7403                         geneve_opt_v->option_type &&
7404                         geneve_opt_resource->length ==
7405                         geneve_opt_v->option_len) {
7406                         /* We already have GENVE TLV option obj allocated. */
7407                         __atomic_fetch_add(&geneve_opt_resource->refcnt, 1,
7408                                            __ATOMIC_RELAXED);
7409                 } else {
7410                         ret = rte_flow_error_set(error, ENOMEM,
7411                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7412                                 "Only one GENEVE TLV option supported");
7413                         goto exit;
7414                 }
7415         } else {
7416                 /* Create a GENEVE TLV object and resource. */
7417                 obj = mlx5_devx_cmd_create_geneve_tlv_option(sh->ctx,
7418                                 geneve_opt_v->option_class,
7419                                 geneve_opt_v->option_type,
7420                                 geneve_opt_v->option_len);
7421                 if (!obj) {
7422                         ret = rte_flow_error_set(error, ENODATA,
7423                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7424                                 "Failed to create GENEVE TLV Devx object");
7425                         goto exit;
7426                 }
7427                 sh->geneve_tlv_option_resource =
7428                                 mlx5_malloc(MLX5_MEM_ZERO,
7429                                                 sizeof(*geneve_opt_resource),
7430                                                 0, SOCKET_ID_ANY);
7431                 if (!sh->geneve_tlv_option_resource) {
7432                         claim_zero(mlx5_devx_cmd_destroy(obj));
7433                         ret = rte_flow_error_set(error, ENOMEM,
7434                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7435                                 "GENEVE TLV object memory allocation failed");
7436                         goto exit;
7437                 }
7438                 geneve_opt_resource = sh->geneve_tlv_option_resource;
7439                 geneve_opt_resource->obj = obj;
7440                 geneve_opt_resource->option_class = geneve_opt_v->option_class;
7441                 geneve_opt_resource->option_type = geneve_opt_v->option_type;
7442                 geneve_opt_resource->length = geneve_opt_v->option_len;
7443                 __atomic_store_n(&geneve_opt_resource->refcnt, 1,
7444                                 __ATOMIC_RELAXED);
7445         }
7446 exit:
7447         rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
7448         return ret;
7449 }
7450
7451 /**
7452  * Add Geneve TLV option item to matcher.
7453  *
7454  * @param[in, out] dev
7455  *   Pointer to rte_eth_dev structure.
7456  * @param[in, out] matcher
7457  *   Flow matcher.
7458  * @param[in, out] key
7459  *   Flow matcher value.
7460  * @param[in] item
7461  *   Flow pattern to translate.
7462  * @param[out] error
7463  *   Pointer to error structure.
7464  */
7465 static int
7466 flow_dv_translate_item_geneve_opt(struct rte_eth_dev *dev, void *matcher,
7467                                   void *key, const struct rte_flow_item *item,
7468                                   struct rte_flow_error *error)
7469 {
7470         const struct rte_flow_item_geneve_opt *geneve_opt_m = item->mask;
7471         const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
7472         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7473         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7474         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7475                         misc_parameters_3);
7476         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7477         rte_be32_t opt_data_key = 0, opt_data_mask = 0;
7478         int ret = 0;
7479
7480         if (!geneve_opt_v)
7481                 return -1;
7482         if (!geneve_opt_m)
7483                 geneve_opt_m = &rte_flow_item_geneve_opt_mask;
7484         ret = flow_dev_geneve_tlv_option_resource_register(dev, item,
7485                                                            error);
7486         if (ret) {
7487                 DRV_LOG(ERR, "Failed to create geneve_tlv_obj");
7488                 return ret;
7489         }
7490         /*
7491          * Set the option length in GENEVE header if not requested.
7492          * The GENEVE TLV option length is expressed by the option length field
7493          * in the GENEVE header.
7494          * If the option length was not requested but the GENEVE TLV option item
7495          * is present we set the option length field implicitly.
7496          */
7497         if (!MLX5_GET16(fte_match_set_misc, misc_m, geneve_opt_len)) {
7498                 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
7499                          MLX5_GENEVE_OPTLEN_MASK);
7500                 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
7501                          geneve_opt_v->option_len + 1);
7502         }
7503         /* Set the data. */
7504         if (geneve_opt_v->data) {
7505                 memcpy(&opt_data_key, geneve_opt_v->data,
7506                         RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
7507                                 sizeof(opt_data_key)));
7508                 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
7509                                 sizeof(opt_data_key));
7510                 memcpy(&opt_data_mask, geneve_opt_m->data,
7511                         RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
7512                                 sizeof(opt_data_mask)));
7513                 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
7514                                 sizeof(opt_data_mask));
7515                 MLX5_SET(fte_match_set_misc3, misc3_m,
7516                                 geneve_tlv_option_0_data,
7517                                 rte_be_to_cpu_32(opt_data_mask));
7518                 MLX5_SET(fte_match_set_misc3, misc3_v,
7519                                 geneve_tlv_option_0_data,
7520                         rte_be_to_cpu_32(opt_data_key & opt_data_mask));
7521         }
7522         return ret;
7523 }
7524
7525 /**
7526  * Add MPLS item to matcher and to the value.
7527  *
7528  * @param[in, out] matcher
7529  *   Flow matcher.
7530  * @param[in, out] key
7531  *   Flow matcher value.
7532  * @param[in] item
7533  *   Flow pattern to translate.
7534  * @param[in] prev_layer
7535  *   The protocol layer indicated in previous item.
7536  * @param[in] inner
7537  *   Item is inner pattern.
7538  */
7539 static void
7540 flow_dv_translate_item_mpls(void *matcher, void *key,
7541                             const struct rte_flow_item *item,
7542                             uint64_t prev_layer,
7543                             int inner)
7544 {
7545         const uint32_t *in_mpls_m = item->mask;
7546         const uint32_t *in_mpls_v = item->spec;
7547         uint32_t *out_mpls_m = 0;
7548         uint32_t *out_mpls_v = 0;
7549         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7550         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7551         void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
7552                                      misc_parameters_2);
7553         void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
7554         void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
7555         void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7556
7557         switch (prev_layer) {
7558         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
7559                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
7560                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
7561                          MLX5_UDP_PORT_MPLS);
7562                 break;
7563         case MLX5_FLOW_LAYER_GRE:
7564                 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
7565                 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
7566                          RTE_ETHER_TYPE_MPLS);
7567                 break;
7568         default:
7569                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7570                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
7571                          IPPROTO_MPLS);
7572                 break;
7573         }
7574         if (!in_mpls_v)
7575                 return;
7576         if (!in_mpls_m)
7577                 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
7578         switch (prev_layer) {
7579         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
7580                 out_mpls_m =
7581                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
7582                                                  outer_first_mpls_over_udp);
7583                 out_mpls_v =
7584                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
7585                                                  outer_first_mpls_over_udp);
7586                 break;
7587         case MLX5_FLOW_LAYER_GRE:
7588                 out_mpls_m =
7589                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
7590                                                  outer_first_mpls_over_gre);
7591                 out_mpls_v =
7592                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
7593                                                  outer_first_mpls_over_gre);
7594                 break;
7595         default:
7596                 /* Inner MPLS not over GRE is not supported. */
7597                 if (!inner) {
7598                         out_mpls_m =
7599                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
7600                                                          misc2_m,
7601                                                          outer_first_mpls);
7602                         out_mpls_v =
7603                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
7604                                                          misc2_v,
7605                                                          outer_first_mpls);
7606                 }
7607                 break;
7608         }
7609         if (out_mpls_m && out_mpls_v) {
7610                 *out_mpls_m = *in_mpls_m;
7611                 *out_mpls_v = *in_mpls_v & *in_mpls_m;
7612         }
7613 }
7614
7615 /**
7616  * Add metadata register item to matcher
7617  *
7618  * @param[in, out] matcher
7619  *   Flow matcher.
7620  * @param[in, out] key
7621  *   Flow matcher value.
7622  * @param[in] reg_type
7623  *   Type of device metadata register
7624  * @param[in] value
7625  *   Register value
7626  * @param[in] mask
7627  *   Register mask
7628  */
7629 static void
7630 flow_dv_match_meta_reg(void *matcher, void *key,
7631                        enum modify_reg reg_type,
7632                        uint32_t data, uint32_t mask)
7633 {
7634         void *misc2_m =
7635                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
7636         void *misc2_v =
7637                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
7638         uint32_t temp;
7639
7640         data &= mask;
7641         switch (reg_type) {
7642         case REG_A:
7643                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
7644                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
7645                 break;
7646         case REG_B:
7647                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
7648                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
7649                 break;
7650         case REG_C_0:
7651                 /*
7652                  * The metadata register C0 field might be divided into
7653                  * source vport index and META item value, we should set
7654                  * this field according to specified mask, not as whole one.
7655                  */
7656                 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
7657                 temp |= mask;
7658                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
7659                 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
7660                 temp &= ~mask;
7661                 temp |= data;
7662                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
7663                 break;
7664         case REG_C_1:
7665                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
7666                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
7667                 break;
7668         case REG_C_2:
7669                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
7670                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
7671                 break;
7672         case REG_C_3:
7673                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
7674                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
7675                 break;
7676         case REG_C_4:
7677                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
7678                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
7679                 break;
7680         case REG_C_5:
7681                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
7682                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
7683                 break;
7684         case REG_C_6:
7685                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
7686                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
7687                 break;
7688         case REG_C_7:
7689                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
7690                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
7691                 break;
7692         default:
7693                 MLX5_ASSERT(false);
7694                 break;
7695         }
7696 }
7697
7698 /**
7699  * Add MARK item to matcher
7700  *
7701  * @param[in] dev
7702  *   The device to configure through.
7703  * @param[in, out] matcher
7704  *   Flow matcher.
7705  * @param[in, out] key
7706  *   Flow matcher value.
7707  * @param[in] item
7708  *   Flow pattern to translate.
7709  */
7710 static void
7711 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
7712                             void *matcher, void *key,
7713                             const struct rte_flow_item *item)
7714 {
7715         struct mlx5_priv *priv = dev->data->dev_private;
7716         const struct rte_flow_item_mark *mark;
7717         uint32_t value;
7718         uint32_t mask;
7719
7720         mark = item->mask ? (const void *)item->mask :
7721                             &rte_flow_item_mark_mask;
7722         mask = mark->id & priv->sh->dv_mark_mask;
7723         mark = (const void *)item->spec;
7724         MLX5_ASSERT(mark);
7725         value = mark->id & priv->sh->dv_mark_mask & mask;
7726         if (mask) {
7727                 enum modify_reg reg;
7728
7729                 /* Get the metadata register index for the mark. */
7730                 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
7731                 MLX5_ASSERT(reg > 0);
7732                 if (reg == REG_C_0) {
7733                         struct mlx5_priv *priv = dev->data->dev_private;
7734                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
7735                         uint32_t shl_c0 = rte_bsf32(msk_c0);
7736
7737                         mask &= msk_c0;
7738                         mask <<= shl_c0;
7739                         value <<= shl_c0;
7740                 }
7741                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
7742         }
7743 }
7744
7745 /**
7746  * Add META item to matcher
7747  *
7748  * @param[in] dev
7749  *   The devich to configure through.
7750  * @param[in, out] matcher
7751  *   Flow matcher.
7752  * @param[in, out] key
7753  *   Flow matcher value.
7754  * @param[in] attr
7755  *   Attributes of flow that includes this item.
7756  * @param[in] item
7757  *   Flow pattern to translate.
7758  */
7759 static void
7760 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
7761                             void *matcher, void *key,
7762                             const struct rte_flow_attr *attr,
7763                             const struct rte_flow_item *item)
7764 {
7765         const struct rte_flow_item_meta *meta_m;
7766         const struct rte_flow_item_meta *meta_v;
7767
7768         meta_m = (const void *)item->mask;
7769         if (!meta_m)
7770                 meta_m = &rte_flow_item_meta_mask;
7771         meta_v = (const void *)item->spec;
7772         if (meta_v) {
7773                 int reg;
7774                 uint32_t value = meta_v->data;
7775                 uint32_t mask = meta_m->data;
7776
7777                 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
7778                 if (reg < 0)
7779                         return;
7780                 MLX5_ASSERT(reg != REG_NON);
7781                 /*
7782                  * In datapath code there is no endianness
7783                  * coversions for perfromance reasons, all
7784                  * pattern conversions are done in rte_flow.
7785                  */
7786                 value = rte_cpu_to_be_32(value);
7787                 mask = rte_cpu_to_be_32(mask);
7788                 if (reg == REG_C_0) {
7789                         struct mlx5_priv *priv = dev->data->dev_private;
7790                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
7791                         uint32_t shl_c0 = rte_bsf32(msk_c0);
7792 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
7793                         uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
7794
7795                         value >>= shr_c0;
7796                         mask >>= shr_c0;
7797 #endif
7798                         value <<= shl_c0;
7799                         mask <<= shl_c0;
7800                         MLX5_ASSERT(msk_c0);
7801                         MLX5_ASSERT(!(~msk_c0 & mask));
7802                 }
7803                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
7804         }
7805 }
7806
7807 /**
7808  * Add vport metadata Reg C0 item to matcher
7809  *
7810  * @param[in, out] matcher
7811  *   Flow matcher.
7812  * @param[in, out] key
7813  *   Flow matcher value.
7814  * @param[in] reg
7815  *   Flow pattern to translate.
7816  */
7817 static void
7818 flow_dv_translate_item_meta_vport(void *matcher, void *key,
7819                                   uint32_t value, uint32_t mask)
7820 {
7821         flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
7822 }
7823
7824 /**
7825  * Add tag item to matcher
7826  *
7827  * @param[in] dev
7828  *   The devich to configure through.
7829  * @param[in, out] matcher
7830  *   Flow matcher.
7831  * @param[in, out] key
7832  *   Flow matcher value.
7833  * @param[in] item
7834  *   Flow pattern to translate.
7835  */
7836 static void
7837 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
7838                                 void *matcher, void *key,
7839                                 const struct rte_flow_item *item)
7840 {
7841         const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
7842         const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
7843         uint32_t mask, value;
7844
7845         MLX5_ASSERT(tag_v);
7846         value = tag_v->data;
7847         mask = tag_m ? tag_m->data : UINT32_MAX;
7848         if (tag_v->id == REG_C_0) {
7849                 struct mlx5_priv *priv = dev->data->dev_private;
7850                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
7851                 uint32_t shl_c0 = rte_bsf32(msk_c0);
7852
7853                 mask &= msk_c0;
7854                 mask <<= shl_c0;
7855                 value <<= shl_c0;
7856         }
7857         flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
7858 }
7859
7860 /**
7861  * Add TAG item to matcher
7862  *
7863  * @param[in] dev
7864  *   The devich to configure through.
7865  * @param[in, out] matcher
7866  *   Flow matcher.
7867  * @param[in, out] key
7868  *   Flow matcher value.
7869  * @param[in] item
7870  *   Flow pattern to translate.
7871  */
7872 static void
7873 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
7874                            void *matcher, void *key,
7875                            const struct rte_flow_item *item)
7876 {
7877         const struct rte_flow_item_tag *tag_v = item->spec;
7878         const struct rte_flow_item_tag *tag_m = item->mask;
7879         enum modify_reg reg;
7880
7881         MLX5_ASSERT(tag_v);
7882         tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
7883         /* Get the metadata register index for the tag. */
7884         reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
7885         MLX5_ASSERT(reg > 0);
7886         flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
7887 }
7888
7889 /**
7890  * Add source vport match to the specified matcher.
7891  *
7892  * @param[in, out] matcher
7893  *   Flow matcher.
7894  * @param[in, out] key
7895  *   Flow matcher value.
7896  * @param[in] port
7897  *   Source vport value to match
7898  * @param[in] mask
7899  *   Mask
7900  */
7901 static void
7902 flow_dv_translate_item_source_vport(void *matcher, void *key,
7903                                     int16_t port, uint16_t mask)
7904 {
7905         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7906         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7907
7908         MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
7909         MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
7910 }
7911
7912 /**
7913  * Translate port-id item to eswitch match on  port-id.
7914  *
7915  * @param[in] dev
7916  *   The devich to configure through.
7917  * @param[in, out] matcher
7918  *   Flow matcher.
7919  * @param[in, out] key
7920  *   Flow matcher value.
7921  * @param[in] item
7922  *   Flow pattern to translate.
7923  * @param[in]
7924  *   Flow attributes.
7925  *
7926  * @return
7927  *   0 on success, a negative errno value otherwise.
7928  */
7929 static int
7930 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
7931                                void *key, const struct rte_flow_item *item,
7932                                const struct rte_flow_attr *attr)
7933 {
7934         const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
7935         const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
7936         struct mlx5_priv *priv;
7937         uint16_t mask, id;
7938
7939         mask = pid_m ? pid_m->id : 0xffff;
7940         id = pid_v ? pid_v->id : dev->data->port_id;
7941         priv = mlx5_port_to_eswitch_info(id, item == NULL);
7942         if (!priv)
7943                 return -rte_errno;
7944         /*
7945          * Translate to vport field or to metadata, depending on mode.
7946          * Kernel can use either misc.source_port or half of C0 metadata
7947          * register.
7948          */
7949         if (priv->vport_meta_mask) {
7950                 /*
7951                  * Provide the hint for SW steering library
7952                  * to insert the flow into ingress domain and
7953                  * save the extra vport match.
7954                  */
7955                 if (mask == 0xffff && priv->vport_id == 0xffff &&
7956                     priv->pf_bond < 0 && attr->transfer)
7957                         flow_dv_translate_item_source_vport
7958                                 (matcher, key, priv->vport_id, mask);
7959                 else
7960                         flow_dv_translate_item_meta_vport
7961                                 (matcher, key,
7962                                  priv->vport_meta_tag,
7963                                  priv->vport_meta_mask);
7964         } else {
7965                 flow_dv_translate_item_source_vport(matcher, key,
7966                                                     priv->vport_id, mask);
7967         }
7968         return 0;
7969 }
7970
7971 /**
7972  * Add ICMP6 item to matcher and to the value.
7973  *
7974  * @param[in, out] matcher
7975  *   Flow matcher.
7976  * @param[in, out] key
7977  *   Flow matcher value.
7978  * @param[in] item
7979  *   Flow pattern to translate.
7980  * @param[in] inner
7981  *   Item is inner pattern.
7982  */
7983 static void
7984 flow_dv_translate_item_icmp6(void *matcher, void *key,
7985                               const struct rte_flow_item *item,
7986                               int inner)
7987 {
7988         const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
7989         const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
7990         void *headers_m;
7991         void *headers_v;
7992         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7993                                      misc_parameters_3);
7994         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7995         if (inner) {
7996                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7997                                          inner_headers);
7998                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7999         } else {
8000                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8001                                          outer_headers);
8002                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8003         }
8004         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
8005         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
8006         if (!icmp6_v)
8007                 return;
8008         if (!icmp6_m)
8009                 icmp6_m = &rte_flow_item_icmp6_mask;
8010         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
8011         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
8012                  icmp6_v->type & icmp6_m->type);
8013         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
8014         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
8015                  icmp6_v->code & icmp6_m->code);
8016 }
8017
8018 /**
8019  * Add ICMP item to matcher and to the value.
8020  *
8021  * @param[in, out] matcher
8022  *   Flow matcher.
8023  * @param[in, out] key
8024  *   Flow matcher value.
8025  * @param[in] item
8026  *   Flow pattern to translate.
8027  * @param[in] inner
8028  *   Item is inner pattern.
8029  */
8030 static void
8031 flow_dv_translate_item_icmp(void *matcher, void *key,
8032                             const struct rte_flow_item *item,
8033                             int inner)
8034 {
8035         const struct rte_flow_item_icmp *icmp_m = item->mask;
8036         const struct rte_flow_item_icmp *icmp_v = item->spec;
8037         uint32_t icmp_header_data_m = 0;
8038         uint32_t icmp_header_data_v = 0;
8039         void *headers_m;
8040         void *headers_v;
8041         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8042                                      misc_parameters_3);
8043         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8044         if (inner) {
8045                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8046                                          inner_headers);
8047                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8048         } else {
8049                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8050                                          outer_headers);
8051                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8052         }
8053         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
8054         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
8055         if (!icmp_v)
8056                 return;
8057         if (!icmp_m)
8058                 icmp_m = &rte_flow_item_icmp_mask;
8059         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
8060                  icmp_m->hdr.icmp_type);
8061         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
8062                  icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
8063         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
8064                  icmp_m->hdr.icmp_code);
8065         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
8066                  icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
8067         icmp_header_data_m = rte_be_to_cpu_16(icmp_m->hdr.icmp_seq_nb);
8068         icmp_header_data_m |= rte_be_to_cpu_16(icmp_m->hdr.icmp_ident) << 16;
8069         if (icmp_header_data_m) {
8070                 icmp_header_data_v = rte_be_to_cpu_16(icmp_v->hdr.icmp_seq_nb);
8071                 icmp_header_data_v |=
8072                          rte_be_to_cpu_16(icmp_v->hdr.icmp_ident) << 16;
8073                 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_header_data,
8074                          icmp_header_data_m);
8075                 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_header_data,
8076                          icmp_header_data_v & icmp_header_data_m);
8077         }
8078 }
8079
8080 /**
8081  * Add GTP item to matcher and to the value.
8082  *
8083  * @param[in, out] matcher
8084  *   Flow matcher.
8085  * @param[in, out] key
8086  *   Flow matcher value.
8087  * @param[in] item
8088  *   Flow pattern to translate.
8089  * @param[in] inner
8090  *   Item is inner pattern.
8091  */
8092 static void
8093 flow_dv_translate_item_gtp(void *matcher, void *key,
8094                            const struct rte_flow_item *item, int inner)
8095 {
8096         const struct rte_flow_item_gtp *gtp_m = item->mask;
8097         const struct rte_flow_item_gtp *gtp_v = item->spec;
8098         void *headers_m;
8099         void *headers_v;
8100         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8101                                      misc_parameters_3);
8102         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8103         uint16_t dport = RTE_GTPU_UDP_PORT;
8104
8105         if (inner) {
8106                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8107                                          inner_headers);
8108                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8109         } else {
8110                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8111                                          outer_headers);
8112                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8113         }
8114         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8115                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8116                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8117         }
8118         if (!gtp_v)
8119                 return;
8120         if (!gtp_m)
8121                 gtp_m = &rte_flow_item_gtp_mask;
8122         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags,
8123                  gtp_m->v_pt_rsv_flags);
8124         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags,
8125                  gtp_v->v_pt_rsv_flags & gtp_m->v_pt_rsv_flags);
8126         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
8127         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
8128                  gtp_v->msg_type & gtp_m->msg_type);
8129         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
8130                  rte_be_to_cpu_32(gtp_m->teid));
8131         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
8132                  rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
8133 }
8134
8135 /**
8136  * Add GTP PSC item to matcher.
8137  *
8138  * @param[in, out] matcher
8139  *   Flow matcher.
8140  * @param[in, out] key
8141  *   Flow matcher value.
8142  * @param[in] item
8143  *   Flow pattern to translate.
8144  */
8145 static int
8146 flow_dv_translate_item_gtp_psc(void *matcher, void *key,
8147                                const struct rte_flow_item *item)
8148 {
8149         const struct rte_flow_item_gtp_psc *gtp_psc_m = item->mask;
8150         const struct rte_flow_item_gtp_psc *gtp_psc_v = item->spec;
8151         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8152                         misc_parameters_3);
8153         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8154         union {
8155                 uint32_t w32;
8156                 struct {
8157                         uint16_t seq_num;
8158                         uint8_t npdu_num;
8159                         uint8_t next_ext_header_type;
8160                 };
8161         } dw_2;
8162         uint8_t gtp_flags;
8163
8164         /* Always set E-flag match on one, regardless of GTP item settings. */
8165         gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_m, gtpu_msg_flags);
8166         gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
8167         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags, gtp_flags);
8168         gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_v, gtpu_msg_flags);
8169         gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
8170         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags, gtp_flags);
8171         /*Set next extension header type. */
8172         dw_2.seq_num = 0;
8173         dw_2.npdu_num = 0;
8174         dw_2.next_ext_header_type = 0xff;
8175         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_dw_2,
8176                  rte_cpu_to_be_32(dw_2.w32));
8177         dw_2.seq_num = 0;
8178         dw_2.npdu_num = 0;
8179         dw_2.next_ext_header_type = 0x85;
8180         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_dw_2,
8181                  rte_cpu_to_be_32(dw_2.w32));
8182         if (gtp_psc_v) {
8183                 union {
8184                         uint32_t w32;
8185                         struct {
8186                                 uint8_t len;
8187                                 uint8_t type_flags;
8188                                 uint8_t qfi;
8189                                 uint8_t reserved;
8190                         };
8191                 } dw_0;
8192
8193                 /*Set extension header PDU type and Qos. */
8194                 if (!gtp_psc_m)
8195                         gtp_psc_m = &rte_flow_item_gtp_psc_mask;
8196                 dw_0.w32 = 0;
8197                 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_m->pdu_type);
8198                 dw_0.qfi = gtp_psc_m->qfi;
8199                 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_first_ext_dw_0,
8200                          rte_cpu_to_be_32(dw_0.w32));
8201                 dw_0.w32 = 0;
8202                 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_v->pdu_type &
8203                                                         gtp_psc_m->pdu_type);
8204                 dw_0.qfi = gtp_psc_v->qfi & gtp_psc_m->qfi;
8205                 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_first_ext_dw_0,
8206                          rte_cpu_to_be_32(dw_0.w32));
8207         }
8208         return 0;
8209 }
8210
8211 /**
8212  * Add eCPRI item to matcher and to the value.
8213  *
8214  * @param[in] dev
8215  *   The devich to configure through.
8216  * @param[in, out] matcher
8217  *   Flow matcher.
8218  * @param[in, out] key
8219  *   Flow matcher value.
8220  * @param[in] item
8221  *   Flow pattern to translate.
8222  * @param[in] samples
8223  *   Sample IDs to be used in the matching.
8224  */
8225 static void
8226 flow_dv_translate_item_ecpri(struct rte_eth_dev *dev, void *matcher,
8227                              void *key, const struct rte_flow_item *item)
8228 {
8229         struct mlx5_priv *priv = dev->data->dev_private;
8230         const struct rte_flow_item_ecpri *ecpri_m = item->mask;
8231         const struct rte_flow_item_ecpri *ecpri_v = item->spec;
8232         struct rte_ecpri_common_hdr common;
8233         void *misc4_m = MLX5_ADDR_OF(fte_match_param, matcher,
8234                                      misc_parameters_4);
8235         void *misc4_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_4);
8236         uint32_t *samples;
8237         void *dw_m;
8238         void *dw_v;
8239
8240         if (!ecpri_v)
8241                 return;
8242         if (!ecpri_m)
8243                 ecpri_m = &rte_flow_item_ecpri_mask;
8244         /*
8245          * Maximal four DW samples are supported in a single matching now.
8246          * Two are used now for a eCPRI matching:
8247          * 1. Type: one byte, mask should be 0x00ff0000 in network order
8248          * 2. ID of a message: one or two bytes, mask 0xffff0000 or 0xff000000
8249          *    if any.
8250          */
8251         if (!ecpri_m->hdr.common.u32)
8252                 return;
8253         samples = priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0].ids;
8254         /* Need to take the whole DW as the mask to fill the entry. */
8255         dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
8256                             prog_sample_field_value_0);
8257         dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
8258                             prog_sample_field_value_0);
8259         /* Already big endian (network order) in the header. */
8260         *(uint32_t *)dw_m = ecpri_m->hdr.common.u32;
8261         *(uint32_t *)dw_v = ecpri_v->hdr.common.u32 & ecpri_m->hdr.common.u32;
8262         /* Sample#0, used for matching type, offset 0. */
8263         MLX5_SET(fte_match_set_misc4, misc4_m,
8264                  prog_sample_field_id_0, samples[0]);
8265         /* It makes no sense to set the sample ID in the mask field. */
8266         MLX5_SET(fte_match_set_misc4, misc4_v,
8267                  prog_sample_field_id_0, samples[0]);
8268         /*
8269          * Checking if message body part needs to be matched.
8270          * Some wildcard rules only matching type field should be supported.
8271          */
8272         if (ecpri_m->hdr.dummy[0]) {
8273                 common.u32 = rte_be_to_cpu_32(ecpri_v->hdr.common.u32);
8274                 switch (common.type) {
8275                 case RTE_ECPRI_MSG_TYPE_IQ_DATA:
8276                 case RTE_ECPRI_MSG_TYPE_RTC_CTRL:
8277                 case RTE_ECPRI_MSG_TYPE_DLY_MSR:
8278                         dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
8279                                             prog_sample_field_value_1);
8280                         dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
8281                                             prog_sample_field_value_1);
8282                         *(uint32_t *)dw_m = ecpri_m->hdr.dummy[0];
8283                         *(uint32_t *)dw_v = ecpri_v->hdr.dummy[0] &
8284                                             ecpri_m->hdr.dummy[0];
8285                         /* Sample#1, to match message body, offset 4. */
8286                         MLX5_SET(fte_match_set_misc4, misc4_m,
8287                                  prog_sample_field_id_1, samples[1]);
8288                         MLX5_SET(fte_match_set_misc4, misc4_v,
8289                                  prog_sample_field_id_1, samples[1]);
8290                         break;
8291                 default:
8292                         /* Others, do not match any sample ID. */
8293                         break;
8294                 }
8295         }
8296 }
8297
8298 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
8299
8300 #define HEADER_IS_ZERO(match_criteria, headers)                              \
8301         !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers),     \
8302                  matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
8303
8304 /**
8305  * Calculate flow matcher enable bitmap.
8306  *
8307  * @param match_criteria
8308  *   Pointer to flow matcher criteria.
8309  *
8310  * @return
8311  *   Bitmap of enabled fields.
8312  */
8313 static uint8_t
8314 flow_dv_matcher_enable(uint32_t *match_criteria)
8315 {
8316         uint8_t match_criteria_enable;
8317
8318         match_criteria_enable =
8319                 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
8320                 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
8321         match_criteria_enable |=
8322                 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
8323                 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
8324         match_criteria_enable |=
8325                 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
8326                 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
8327         match_criteria_enable |=
8328                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
8329                 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
8330         match_criteria_enable |=
8331                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
8332                 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
8333         match_criteria_enable |=
8334                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_4)) <<
8335                 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT;
8336         return match_criteria_enable;
8337 }
8338
8339 struct mlx5_hlist_entry *
8340 flow_dv_tbl_create_cb(struct mlx5_hlist *list, uint64_t key64, void *cb_ctx)
8341 {
8342         struct mlx5_dev_ctx_shared *sh = list->ctx;
8343         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
8344         struct rte_eth_dev *dev = ctx->dev;
8345         struct mlx5_flow_tbl_data_entry *tbl_data;
8346         struct mlx5_flow_tbl_tunnel_prm *tt_prm = ctx->data;
8347         struct rte_flow_error *error = ctx->error;
8348         union mlx5_flow_tbl_key key = { .v64 = key64 };
8349         struct mlx5_flow_tbl_resource *tbl;
8350         void *domain;
8351         uint32_t idx = 0;
8352         int ret;
8353
8354         tbl_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
8355         if (!tbl_data) {
8356                 rte_flow_error_set(error, ENOMEM,
8357                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8358                                    NULL,
8359                                    "cannot allocate flow table data entry");
8360                 return NULL;
8361         }
8362         tbl_data->idx = idx;
8363         tbl_data->tunnel = tt_prm->tunnel;
8364         tbl_data->group_id = tt_prm->group_id;
8365         tbl_data->external = !!tt_prm->external;
8366         tbl_data->tunnel_offload = is_tunnel_offload_active(dev);
8367         tbl_data->is_egress = !!key.direction;
8368         tbl_data->is_transfer = !!key.domain;
8369         tbl_data->dummy = !!key.dummy;
8370         tbl_data->table_id = key.table_id;
8371         tbl = &tbl_data->tbl;
8372         if (key.dummy)
8373                 return &tbl_data->entry;
8374         if (key.domain)
8375                 domain = sh->fdb_domain;
8376         else if (key.direction)
8377                 domain = sh->tx_domain;
8378         else
8379                 domain = sh->rx_domain;
8380         ret = mlx5_flow_os_create_flow_tbl(domain, key.table_id, &tbl->obj);
8381         if (ret) {
8382                 rte_flow_error_set(error, ENOMEM,
8383                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8384                                    NULL, "cannot create flow table object");
8385                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
8386                 return NULL;
8387         }
8388         if (key.table_id) {
8389                 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
8390                                         (tbl->obj, &tbl_data->jump.action);
8391                 if (ret) {
8392                         rte_flow_error_set(error, ENOMEM,
8393                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8394                                            NULL,
8395                                            "cannot create flow jump action");
8396                         mlx5_flow_os_destroy_flow_tbl(tbl->obj);
8397                         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
8398                         return NULL;
8399                 }
8400         }
8401         MKSTR(matcher_name, "%s_%s_%u_matcher_cache",
8402               key.domain ? "FDB" : "NIC", key.direction ? "egress" : "ingress",
8403               key.table_id);
8404         mlx5_cache_list_init(&tbl_data->matchers, matcher_name, 0, sh,
8405                              flow_dv_matcher_create_cb,
8406                              flow_dv_matcher_match_cb,
8407                              flow_dv_matcher_remove_cb);
8408         return &tbl_data->entry;
8409 }
8410
8411 int
8412 flow_dv_tbl_match_cb(struct mlx5_hlist *list __rte_unused,
8413                      struct mlx5_hlist_entry *entry, uint64_t key64,
8414                      void *cb_ctx __rte_unused)
8415 {
8416         struct mlx5_flow_tbl_data_entry *tbl_data =
8417                 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
8418         union mlx5_flow_tbl_key key = { .v64 = key64 };
8419
8420         return tbl_data->table_id != key.table_id ||
8421                tbl_data->dummy != key.dummy ||
8422                tbl_data->is_transfer != key.domain ||
8423                tbl_data->is_egress != key.direction;
8424 }
8425
8426 /**
8427  * Get a flow table.
8428  *
8429  * @param[in, out] dev
8430  *   Pointer to rte_eth_dev structure.
8431  * @param[in] table_id
8432  *   Table id to use.
8433  * @param[in] egress
8434  *   Direction of the table.
8435  * @param[in] transfer
8436  *   E-Switch or NIC flow.
8437  * @param[in] dummy
8438  *   Dummy entry for dv API.
8439  * @param[out] error
8440  *   pointer to error structure.
8441  *
8442  * @return
8443  *   Returns tables resource based on the index, NULL in case of failed.
8444  */
8445 struct mlx5_flow_tbl_resource *
8446 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
8447                          uint32_t table_id, uint8_t egress,
8448                          uint8_t transfer,
8449                          bool external,
8450                          const struct mlx5_flow_tunnel *tunnel,
8451                          uint32_t group_id, uint8_t dummy,
8452                          struct rte_flow_error *error)
8453 {
8454         struct mlx5_priv *priv = dev->data->dev_private;
8455         union mlx5_flow_tbl_key table_key = {
8456                 {
8457                         .table_id = table_id,
8458                         .dummy = dummy,
8459                         .domain = !!transfer,
8460                         .direction = !!egress,
8461                 }
8462         };
8463         struct mlx5_flow_tbl_tunnel_prm tt_prm = {
8464                 .tunnel = tunnel,
8465                 .group_id = group_id,
8466                 .external = external,
8467         };
8468         struct mlx5_flow_cb_ctx ctx = {
8469                 .dev = dev,
8470                 .error = error,
8471                 .data = &tt_prm,
8472         };
8473         struct mlx5_hlist_entry *entry;
8474         struct mlx5_flow_tbl_data_entry *tbl_data;
8475
8476         entry = mlx5_hlist_register(priv->sh->flow_tbls, table_key.v64, &ctx);
8477         if (!entry) {
8478                 rte_flow_error_set(error, ENOMEM,
8479                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8480                                    "cannot get table");
8481                 return NULL;
8482         }
8483         DRV_LOG(DEBUG, "Table_id %u tunnel %u group %u registered.",
8484                 table_id, tunnel ? tunnel->tunnel_id : 0, group_id);
8485         tbl_data = container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
8486         return &tbl_data->tbl;
8487 }
8488
8489 void
8490 flow_dv_tbl_remove_cb(struct mlx5_hlist *list,
8491                       struct mlx5_hlist_entry *entry)
8492 {
8493         struct mlx5_dev_ctx_shared *sh = list->ctx;
8494         struct mlx5_flow_tbl_data_entry *tbl_data =
8495                 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
8496
8497         MLX5_ASSERT(entry && sh);
8498         if (tbl_data->jump.action)
8499                 mlx5_flow_os_destroy_flow_action(tbl_data->jump.action);
8500         if (tbl_data->tbl.obj)
8501                 mlx5_flow_os_destroy_flow_tbl(tbl_data->tbl.obj);
8502         if (tbl_data->tunnel_offload && tbl_data->external) {
8503                 struct mlx5_hlist_entry *he;
8504                 struct mlx5_hlist *tunnel_grp_hash;
8505                 struct mlx5_flow_tunnel_hub *thub = sh->tunnel_hub;
8506                 union tunnel_tbl_key tunnel_key = {
8507                         .tunnel_id = tbl_data->tunnel ?
8508                                         tbl_data->tunnel->tunnel_id : 0,
8509                         .group = tbl_data->group_id
8510                 };
8511                 uint32_t table_id = tbl_data->table_id;
8512
8513                 tunnel_grp_hash = tbl_data->tunnel ?
8514                                         tbl_data->tunnel->groups :
8515                                         thub->groups;
8516                 he = mlx5_hlist_lookup(tunnel_grp_hash, tunnel_key.val, NULL);
8517                 if (he)
8518                         mlx5_hlist_unregister(tunnel_grp_hash, he);
8519                 DRV_LOG(DEBUG,
8520                         "Table_id %u tunnel %u group %u released.",
8521                         table_id,
8522                         tbl_data->tunnel ?
8523                         tbl_data->tunnel->tunnel_id : 0,
8524                         tbl_data->group_id);
8525         }
8526         mlx5_cache_list_destroy(&tbl_data->matchers);
8527         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], tbl_data->idx);
8528 }
8529
8530 /**
8531  * Release a flow table.
8532  *
8533  * @param[in] sh
8534  *   Pointer to device shared structure.
8535  * @param[in] tbl
8536  *   Table resource to be released.
8537  *
8538  * @return
8539  *   Returns 0 if table was released, else return 1;
8540  */
8541 static int
8542 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
8543                              struct mlx5_flow_tbl_resource *tbl)
8544 {
8545         struct mlx5_flow_tbl_data_entry *tbl_data =
8546                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
8547
8548         if (!tbl)
8549                 return 0;
8550         return mlx5_hlist_unregister(sh->flow_tbls, &tbl_data->entry);
8551 }
8552
8553 int
8554 flow_dv_matcher_match_cb(struct mlx5_cache_list *list __rte_unused,
8555                          struct mlx5_cache_entry *entry, void *cb_ctx)
8556 {
8557         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
8558         struct mlx5_flow_dv_matcher *ref = ctx->data;
8559         struct mlx5_flow_dv_matcher *cur = container_of(entry, typeof(*cur),
8560                                                         entry);
8561
8562         return cur->crc != ref->crc ||
8563                cur->priority != ref->priority ||
8564                memcmp((const void *)cur->mask.buf,
8565                       (const void *)ref->mask.buf, ref->mask.size);
8566 }
8567
8568 struct mlx5_cache_entry *
8569 flow_dv_matcher_create_cb(struct mlx5_cache_list *list,
8570                           struct mlx5_cache_entry *entry __rte_unused,
8571                           void *cb_ctx)
8572 {
8573         struct mlx5_dev_ctx_shared *sh = list->ctx;
8574         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
8575         struct mlx5_flow_dv_matcher *ref = ctx->data;
8576         struct mlx5_flow_dv_matcher *cache;
8577         struct mlx5dv_flow_matcher_attr dv_attr = {
8578                 .type = IBV_FLOW_ATTR_NORMAL,
8579                 .match_mask = (void *)&ref->mask,
8580         };
8581         struct mlx5_flow_tbl_data_entry *tbl = container_of(ref->tbl,
8582                                                             typeof(*tbl), tbl);
8583         int ret;
8584
8585         cache = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*cache), 0, SOCKET_ID_ANY);
8586         if (!cache) {
8587                 rte_flow_error_set(ctx->error, ENOMEM,
8588                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8589                                    "cannot create matcher");
8590                 return NULL;
8591         }
8592         *cache = *ref;
8593         dv_attr.match_criteria_enable =
8594                 flow_dv_matcher_enable(cache->mask.buf);
8595         dv_attr.priority = ref->priority;
8596         if (tbl->is_egress)
8597                 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
8598         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->tbl.obj,
8599                                                &cache->matcher_object);
8600         if (ret) {
8601                 mlx5_free(cache);
8602                 rte_flow_error_set(ctx->error, ENOMEM,
8603                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8604                                    "cannot create matcher");
8605                 return NULL;
8606         }
8607         return &cache->entry;
8608 }
8609
8610 /**
8611  * Register the flow matcher.
8612  *
8613  * @param[in, out] dev
8614  *   Pointer to rte_eth_dev structure.
8615  * @param[in, out] matcher
8616  *   Pointer to flow matcher.
8617  * @param[in, out] key
8618  *   Pointer to flow table key.
8619  * @parm[in, out] dev_flow
8620  *   Pointer to the dev_flow.
8621  * @param[out] error
8622  *   pointer to error structure.
8623  *
8624  * @return
8625  *   0 on success otherwise -errno and errno is set.
8626  */
8627 static int
8628 flow_dv_matcher_register(struct rte_eth_dev *dev,
8629                          struct mlx5_flow_dv_matcher *ref,
8630                          union mlx5_flow_tbl_key *key,
8631                          struct mlx5_flow *dev_flow,
8632                          const struct mlx5_flow_tunnel *tunnel,
8633                          uint32_t group_id,
8634                          struct rte_flow_error *error)
8635 {
8636         struct mlx5_cache_entry *entry;
8637         struct mlx5_flow_dv_matcher *cache;
8638         struct mlx5_flow_tbl_resource *tbl;
8639         struct mlx5_flow_tbl_data_entry *tbl_data;
8640         struct mlx5_flow_cb_ctx ctx = {
8641                 .error = error,
8642                 .data = ref,
8643         };
8644
8645         /**
8646          * tunnel offload API requires this registration for cases when
8647          * tunnel match rule was inserted before tunnel set rule.
8648          */
8649         tbl = flow_dv_tbl_resource_get(dev, key->table_id,
8650                                        key->direction, key->domain,
8651                                        dev_flow->external, tunnel,
8652                                        group_id, 0, error);
8653         if (!tbl)
8654                 return -rte_errno;      /* No need to refill the error info */
8655         tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
8656         ref->tbl = tbl;
8657         entry = mlx5_cache_register(&tbl_data->matchers, &ctx);
8658         if (!entry) {
8659                 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
8660                 return rte_flow_error_set(error, ENOMEM,
8661                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8662                                           "cannot allocate ref memory");
8663         }
8664         cache = container_of(entry, typeof(*cache), entry);
8665         dev_flow->handle->dvh.matcher = cache;
8666         return 0;
8667 }
8668
8669 struct mlx5_hlist_entry *
8670 flow_dv_tag_create_cb(struct mlx5_hlist *list, uint64_t key, void *ctx)
8671 {
8672         struct mlx5_dev_ctx_shared *sh = list->ctx;
8673         struct rte_flow_error *error = ctx;
8674         struct mlx5_flow_dv_tag_resource *entry;
8675         uint32_t idx = 0;
8676         int ret;
8677
8678         entry = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_TAG], &idx);
8679         if (!entry) {
8680                 rte_flow_error_set(error, ENOMEM,
8681                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8682                                    "cannot allocate resource memory");
8683                 return NULL;
8684         }
8685         entry->idx = idx;
8686         entry->tag_id = key;
8687         ret = mlx5_flow_os_create_flow_action_tag(key,
8688                                                   &entry->action);
8689         if (ret) {
8690                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], idx);
8691                 rte_flow_error_set(error, ENOMEM,
8692                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8693                                    NULL, "cannot create action");
8694                 return NULL;
8695         }
8696         return &entry->entry;
8697 }
8698
8699 int
8700 flow_dv_tag_match_cb(struct mlx5_hlist *list __rte_unused,
8701                      struct mlx5_hlist_entry *entry, uint64_t key,
8702                      void *cb_ctx __rte_unused)
8703 {
8704         struct mlx5_flow_dv_tag_resource *tag =
8705                 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
8706
8707         return key != tag->tag_id;
8708 }
8709
8710 /**
8711  * Find existing tag resource or create and register a new one.
8712  *
8713  * @param dev[in, out]
8714  *   Pointer to rte_eth_dev structure.
8715  * @param[in, out] tag_be24
8716  *   Tag value in big endian then R-shift 8.
8717  * @parm[in, out] dev_flow
8718  *   Pointer to the dev_flow.
8719  * @param[out] error
8720  *   pointer to error structure.
8721  *
8722  * @return
8723  *   0 on success otherwise -errno and errno is set.
8724  */
8725 static int
8726 flow_dv_tag_resource_register
8727                         (struct rte_eth_dev *dev,
8728                          uint32_t tag_be24,
8729                          struct mlx5_flow *dev_flow,
8730                          struct rte_flow_error *error)
8731 {
8732         struct mlx5_priv *priv = dev->data->dev_private;
8733         struct mlx5_flow_dv_tag_resource *cache_resource;
8734         struct mlx5_hlist_entry *entry;
8735
8736         entry = mlx5_hlist_register(priv->sh->tag_table, tag_be24, error);
8737         if (entry) {
8738                 cache_resource = container_of
8739                         (entry, struct mlx5_flow_dv_tag_resource, entry);
8740                 dev_flow->handle->dvh.rix_tag = cache_resource->idx;
8741                 dev_flow->dv.tag_resource = cache_resource;
8742                 return 0;
8743         }
8744         return -rte_errno;
8745 }
8746
8747 void
8748 flow_dv_tag_remove_cb(struct mlx5_hlist *list,
8749                       struct mlx5_hlist_entry *entry)
8750 {
8751         struct mlx5_dev_ctx_shared *sh = list->ctx;
8752         struct mlx5_flow_dv_tag_resource *tag =
8753                 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
8754
8755         MLX5_ASSERT(tag && sh && tag->action);
8756         claim_zero(mlx5_flow_os_destroy_flow_action(tag->action));
8757         DRV_LOG(DEBUG, "Tag %p: removed.", (void *)tag);
8758         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], tag->idx);
8759 }
8760
8761 /**
8762  * Release the tag.
8763  *
8764  * @param dev
8765  *   Pointer to Ethernet device.
8766  * @param tag_idx
8767  *   Tag index.
8768  *
8769  * @return
8770  *   1 while a reference on it exists, 0 when freed.
8771  */
8772 static int
8773 flow_dv_tag_release(struct rte_eth_dev *dev,
8774                     uint32_t tag_idx)
8775 {
8776         struct mlx5_priv *priv = dev->data->dev_private;
8777         struct mlx5_flow_dv_tag_resource *tag;
8778
8779         tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
8780         if (!tag)
8781                 return 0;
8782         DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
8783                 dev->data->port_id, (void *)tag, tag->entry.ref_cnt);
8784         return mlx5_hlist_unregister(priv->sh->tag_table, &tag->entry);
8785 }
8786
8787 /**
8788  * Translate port ID action to vport.
8789  *
8790  * @param[in] dev
8791  *   Pointer to rte_eth_dev structure.
8792  * @param[in] action
8793  *   Pointer to the port ID action.
8794  * @param[out] dst_port_id
8795  *   The target port ID.
8796  * @param[out] error
8797  *   Pointer to the error structure.
8798  *
8799  * @return
8800  *   0 on success, a negative errno value otherwise and rte_errno is set.
8801  */
8802 static int
8803 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
8804                                  const struct rte_flow_action *action,
8805                                  uint32_t *dst_port_id,
8806                                  struct rte_flow_error *error)
8807 {
8808         uint32_t port;
8809         struct mlx5_priv *priv;
8810         const struct rte_flow_action_port_id *conf =
8811                         (const struct rte_flow_action_port_id *)action->conf;
8812
8813         port = conf->original ? dev->data->port_id : conf->id;
8814         priv = mlx5_port_to_eswitch_info(port, false);
8815         if (!priv)
8816                 return rte_flow_error_set(error, -rte_errno,
8817                                           RTE_FLOW_ERROR_TYPE_ACTION,
8818                                           NULL,
8819                                           "No eswitch info was found for port");
8820 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
8821         /*
8822          * This parameter is transferred to
8823          * mlx5dv_dr_action_create_dest_ib_port().
8824          */
8825         *dst_port_id = priv->dev_port;
8826 #else
8827         /*
8828          * Legacy mode, no LAG configurations is supported.
8829          * This parameter is transferred to
8830          * mlx5dv_dr_action_create_dest_vport().
8831          */
8832         *dst_port_id = priv->vport_id;
8833 #endif
8834         return 0;
8835 }
8836
8837 /**
8838  * Create a counter with aging configuration.
8839  *
8840  * @param[in] dev
8841  *   Pointer to rte_eth_dev structure.
8842  * @param[out] count
8843  *   Pointer to the counter action configuration.
8844  * @param[in] age
8845  *   Pointer to the aging action configuration.
8846  *
8847  * @return
8848  *   Index to flow counter on success, 0 otherwise.
8849  */
8850 static uint32_t
8851 flow_dv_translate_create_counter(struct rte_eth_dev *dev,
8852                                 struct mlx5_flow *dev_flow,
8853                                 const struct rte_flow_action_count *count,
8854                                 const struct rte_flow_action_age *age)
8855 {
8856         uint32_t counter;
8857         struct mlx5_age_param *age_param;
8858
8859         if (count && count->shared)
8860                 counter = flow_dv_counter_get_shared(dev, count->id);
8861         else
8862                 counter = flow_dv_counter_alloc(dev, !!age);
8863         if (!counter || age == NULL)
8864                 return counter;
8865         age_param  = flow_dv_counter_idx_get_age(dev, counter);
8866         age_param->context = age->context ? age->context :
8867                 (void *)(uintptr_t)(dev_flow->flow_idx);
8868         age_param->timeout = age->timeout;
8869         age_param->port_id = dev->data->port_id;
8870         __atomic_store_n(&age_param->sec_since_last_hit, 0, __ATOMIC_RELAXED);
8871         __atomic_store_n(&age_param->state, AGE_CANDIDATE, __ATOMIC_RELAXED);
8872         return counter;
8873 }
8874
8875 /**
8876  * Add Tx queue matcher
8877  *
8878  * @param[in] dev
8879  *   Pointer to the dev struct.
8880  * @param[in, out] matcher
8881  *   Flow matcher.
8882  * @param[in, out] key
8883  *   Flow matcher value.
8884  * @param[in] item
8885  *   Flow pattern to translate.
8886  * @param[in] inner
8887  *   Item is inner pattern.
8888  */
8889 static void
8890 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
8891                                 void *matcher, void *key,
8892                                 const struct rte_flow_item *item)
8893 {
8894         const struct mlx5_rte_flow_item_tx_queue *queue_m;
8895         const struct mlx5_rte_flow_item_tx_queue *queue_v;
8896         void *misc_m =
8897                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8898         void *misc_v =
8899                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8900         struct mlx5_txq_ctrl *txq;
8901         uint32_t queue;
8902
8903
8904         queue_m = (const void *)item->mask;
8905         if (!queue_m)
8906                 return;
8907         queue_v = (const void *)item->spec;
8908         if (!queue_v)
8909                 return;
8910         txq = mlx5_txq_get(dev, queue_v->queue);
8911         if (!txq)
8912                 return;
8913         queue = txq->obj->sq->id;
8914         MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
8915         MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
8916                  queue & queue_m->queue);
8917         mlx5_txq_release(dev, queue_v->queue);
8918 }
8919
8920 /**
8921  * Set the hash fields according to the @p flow information.
8922  *
8923  * @param[in] dev_flow
8924  *   Pointer to the mlx5_flow.
8925  * @param[in] rss_desc
8926  *   Pointer to the mlx5_flow_rss_desc.
8927  */
8928 static void
8929 flow_dv_hashfields_set(struct mlx5_flow *dev_flow,
8930                        struct mlx5_flow_rss_desc *rss_desc)
8931 {
8932         uint64_t items = dev_flow->handle->layers;
8933         int rss_inner = 0;
8934         uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
8935
8936         dev_flow->hash_fields = 0;
8937 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
8938         if (rss_desc->level >= 2) {
8939                 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
8940                 rss_inner = 1;
8941         }
8942 #endif
8943         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
8944             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
8945                 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
8946                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
8947                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
8948                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
8949                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
8950                         else
8951                                 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
8952                 }
8953         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
8954                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
8955                 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
8956                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
8957                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
8958                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
8959                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
8960                         else
8961                                 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
8962                 }
8963         }
8964         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
8965             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
8966                 if (rss_types & ETH_RSS_UDP) {
8967                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
8968                                 dev_flow->hash_fields |=
8969                                                 IBV_RX_HASH_SRC_PORT_UDP;
8970                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
8971                                 dev_flow->hash_fields |=
8972                                                 IBV_RX_HASH_DST_PORT_UDP;
8973                         else
8974                                 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
8975                 }
8976         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
8977                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
8978                 if (rss_types & ETH_RSS_TCP) {
8979                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
8980                                 dev_flow->hash_fields |=
8981                                                 IBV_RX_HASH_SRC_PORT_TCP;
8982                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
8983                                 dev_flow->hash_fields |=
8984                                                 IBV_RX_HASH_DST_PORT_TCP;
8985                         else
8986                                 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
8987                 }
8988         }
8989 }
8990
8991 /**
8992  * Prepare an Rx Hash queue.
8993  *
8994  * @param dev
8995  *   Pointer to Ethernet device.
8996  * @param[in] dev_flow
8997  *   Pointer to the mlx5_flow.
8998  * @param[in] rss_desc
8999  *   Pointer to the mlx5_flow_rss_desc.
9000  * @param[out] hrxq_idx
9001  *   Hash Rx queue index.
9002  *
9003  * @return
9004  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
9005  */
9006 static struct mlx5_hrxq *
9007 flow_dv_hrxq_prepare(struct rte_eth_dev *dev,
9008                      struct mlx5_flow *dev_flow,
9009                      struct mlx5_flow_rss_desc *rss_desc,
9010                      uint32_t *hrxq_idx)
9011 {
9012         struct mlx5_priv *priv = dev->data->dev_private;
9013         struct mlx5_flow_handle *dh = dev_flow->handle;
9014         struct mlx5_hrxq *hrxq;
9015
9016         MLX5_ASSERT(rss_desc->queue_num);
9017         rss_desc->key_len = MLX5_RSS_HASH_KEY_LEN;
9018         rss_desc->hash_fields = dev_flow->hash_fields;
9019         rss_desc->tunnel = !!(dh->layers & MLX5_FLOW_LAYER_TUNNEL);
9020         rss_desc->shared_rss = 0;
9021         *hrxq_idx = mlx5_hrxq_get(dev, rss_desc);
9022         if (!*hrxq_idx)
9023                 return NULL;
9024         hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
9025                               *hrxq_idx);
9026         return hrxq;
9027 }
9028
9029 /**
9030  * Release sample sub action resource.
9031  *
9032  * @param[in, out] dev
9033  *   Pointer to rte_eth_dev structure.
9034  * @param[in] act_res
9035  *   Pointer to sample sub action resource.
9036  */
9037 static void
9038 flow_dv_sample_sub_actions_release(struct rte_eth_dev *dev,
9039                                    struct mlx5_flow_sub_actions_idx *act_res)
9040 {
9041         if (act_res->rix_hrxq) {
9042                 mlx5_hrxq_release(dev, act_res->rix_hrxq);
9043                 act_res->rix_hrxq = 0;
9044         }
9045         if (act_res->rix_encap_decap) {
9046                 flow_dv_encap_decap_resource_release(dev,
9047                                                      act_res->rix_encap_decap);
9048                 act_res->rix_encap_decap = 0;
9049         }
9050         if (act_res->rix_port_id_action) {
9051                 flow_dv_port_id_action_resource_release(dev,
9052                                                 act_res->rix_port_id_action);
9053                 act_res->rix_port_id_action = 0;
9054         }
9055         if (act_res->rix_tag) {
9056                 flow_dv_tag_release(dev, act_res->rix_tag);
9057                 act_res->rix_tag = 0;
9058         }
9059         if (act_res->cnt) {
9060                 flow_dv_counter_free(dev, act_res->cnt);
9061                 act_res->cnt = 0;
9062         }
9063         if (act_res->rix_jump) {
9064                 flow_dv_jump_tbl_resource_release(dev, act_res->rix_jump);
9065                 act_res->rix_jump = 0;
9066         }
9067 }
9068
9069 int
9070 flow_dv_sample_match_cb(struct mlx5_cache_list *list __rte_unused,
9071                         struct mlx5_cache_entry *entry, void *cb_ctx)
9072 {
9073         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9074         struct rte_eth_dev *dev = ctx->dev;
9075         struct mlx5_flow_dv_sample_resource *resource = ctx->data;
9076         struct mlx5_flow_dv_sample_resource *cache_resource =
9077                         container_of(entry, typeof(*cache_resource), entry);
9078
9079         if (resource->ratio == cache_resource->ratio &&
9080             resource->ft_type == cache_resource->ft_type &&
9081             resource->ft_id == cache_resource->ft_id &&
9082             resource->set_action == cache_resource->set_action &&
9083             !memcmp((void *)&resource->sample_act,
9084                     (void *)&cache_resource->sample_act,
9085                     sizeof(struct mlx5_flow_sub_actions_list))) {
9086                 /*
9087                  * Existing sample action should release the prepared
9088                  * sub-actions reference counter.
9089                  */
9090                 flow_dv_sample_sub_actions_release(dev,
9091                                                 &resource->sample_idx);
9092                 return 0;
9093         }
9094         return 1;
9095 }
9096
9097 struct mlx5_cache_entry *
9098 flow_dv_sample_create_cb(struct mlx5_cache_list *list __rte_unused,
9099                          struct mlx5_cache_entry *entry __rte_unused,
9100                          void *cb_ctx)
9101 {
9102         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9103         struct rte_eth_dev *dev = ctx->dev;
9104         struct mlx5_flow_dv_sample_resource *resource = ctx->data;
9105         void **sample_dv_actions = resource->sub_actions;
9106         struct mlx5_flow_dv_sample_resource *cache_resource;
9107         struct mlx5dv_dr_flow_sampler_attr sampler_attr;
9108         struct mlx5_priv *priv = dev->data->dev_private;
9109         struct mlx5_dev_ctx_shared *sh = priv->sh;
9110         struct mlx5_flow_tbl_resource *tbl;
9111         uint32_t idx = 0;
9112         const uint32_t next_ft_step = 1;
9113         uint32_t next_ft_id = resource->ft_id + next_ft_step;
9114         uint8_t is_egress = 0;
9115         uint8_t is_transfer = 0;
9116         struct rte_flow_error *error = ctx->error;
9117
9118         /* Register new sample resource. */
9119         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_SAMPLE], &idx);
9120         if (!cache_resource) {
9121                 rte_flow_error_set(error, ENOMEM,
9122                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9123                                           NULL,
9124                                           "cannot allocate resource memory");
9125                 return NULL;
9126         }
9127         *cache_resource = *resource;
9128         /* Create normal path table level */
9129         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
9130                 is_transfer = 1;
9131         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
9132                 is_egress = 1;
9133         tbl = flow_dv_tbl_resource_get(dev, next_ft_id,
9134                                         is_egress, is_transfer,
9135                                         true, NULL, 0, 0, error);
9136         if (!tbl) {
9137                 rte_flow_error_set(error, ENOMEM,
9138                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9139                                           NULL,
9140                                           "fail to create normal path table "
9141                                           "for sample");
9142                 goto error;
9143         }
9144         int ret;
9145
9146         cache_resource->normal_path_tbl = tbl;
9147         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB) {
9148                 ret = mlx5_flow_os_create_flow_action_default_miss
9149                         (&cache_resource->default_miss);
9150                 if (!ret) {
9151                         rte_flow_error_set(error, ENOMEM,
9152                                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9153                                                 NULL,
9154                                                 "cannot create default miss "
9155                                                 "action");
9156                         goto error;
9157                 }
9158                 sample_dv_actions[resource->sample_act.actions_num++] =
9159                                                 cache_resource->default_miss;
9160         }
9161         /* Create a DR sample action */
9162         sampler_attr.sample_ratio = cache_resource->ratio;
9163         sampler_attr.default_next_table = tbl->obj;
9164         sampler_attr.num_sample_actions = resource->sample_act.actions_num;
9165         sampler_attr.sample_actions = (struct mlx5dv_dr_action **)
9166                                                         &sample_dv_actions[0];
9167         sampler_attr.action = cache_resource->set_action;
9168         if (mlx5_os_flow_dr_create_flow_action_sampler
9169                         (&sampler_attr, &cache_resource->verbs_action)) {
9170                 rte_flow_error_set(error, ENOMEM,
9171                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9172                                         NULL, "cannot create sample action");
9173                 goto error;
9174         }
9175         cache_resource->idx = idx;
9176         cache_resource->dev = dev;
9177         return &cache_resource->entry;
9178 error:
9179         if (cache_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB &&
9180             cache_resource->default_miss)
9181                 claim_zero(mlx5_flow_os_destroy_flow_action
9182                                 (cache_resource->default_miss));
9183         else
9184                 flow_dv_sample_sub_actions_release(dev,
9185                                                    &cache_resource->sample_idx);
9186         if (cache_resource->normal_path_tbl)
9187                 flow_dv_tbl_resource_release(MLX5_SH(dev),
9188                                 cache_resource->normal_path_tbl);
9189         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_SAMPLE], idx);
9190         return NULL;
9191
9192 }
9193
9194 /**
9195  * Find existing sample resource or create and register a new one.
9196  *
9197  * @param[in, out] dev
9198  *   Pointer to rte_eth_dev structure.
9199  * @param[in] resource
9200  *   Pointer to sample resource.
9201  * @parm[in, out] dev_flow
9202  *   Pointer to the dev_flow.
9203  * @param[out] error
9204  *   pointer to error structure.
9205  *
9206  * @return
9207  *   0 on success otherwise -errno and errno is set.
9208  */
9209 static int
9210 flow_dv_sample_resource_register(struct rte_eth_dev *dev,
9211                          struct mlx5_flow_dv_sample_resource *resource,
9212                          struct mlx5_flow *dev_flow,
9213                          struct rte_flow_error *error)
9214 {
9215         struct mlx5_flow_dv_sample_resource *cache_resource;
9216         struct mlx5_cache_entry *entry;
9217         struct mlx5_priv *priv = dev->data->dev_private;
9218         struct mlx5_flow_cb_ctx ctx = {
9219                 .dev = dev,
9220                 .error = error,
9221                 .data = resource,
9222         };
9223
9224         entry = mlx5_cache_register(&priv->sh->sample_action_list, &ctx);
9225         if (!entry)
9226                 return -rte_errno;
9227         cache_resource = container_of(entry, typeof(*cache_resource), entry);
9228         dev_flow->handle->dvh.rix_sample = cache_resource->idx;
9229         dev_flow->dv.sample_res = cache_resource;
9230         return 0;
9231 }
9232
9233 int
9234 flow_dv_dest_array_match_cb(struct mlx5_cache_list *list __rte_unused,
9235                             struct mlx5_cache_entry *entry, void *cb_ctx)
9236 {
9237         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9238         struct mlx5_flow_dv_dest_array_resource *resource = ctx->data;
9239         struct rte_eth_dev *dev = ctx->dev;
9240         struct mlx5_flow_dv_dest_array_resource *cache_resource =
9241                         container_of(entry, typeof(*cache_resource), entry);
9242         uint32_t idx = 0;
9243
9244         if (resource->num_of_dest == cache_resource->num_of_dest &&
9245             resource->ft_type == cache_resource->ft_type &&
9246             !memcmp((void *)cache_resource->sample_act,
9247                     (void *)resource->sample_act,
9248                    (resource->num_of_dest *
9249                    sizeof(struct mlx5_flow_sub_actions_list)))) {
9250                 /*
9251                  * Existing sample action should release the prepared
9252                  * sub-actions reference counter.
9253                  */
9254                 for (idx = 0; idx < resource->num_of_dest; idx++)
9255                         flow_dv_sample_sub_actions_release(dev,
9256                                         &resource->sample_idx[idx]);
9257                 return 0;
9258         }
9259         return 1;
9260 }
9261
9262 struct mlx5_cache_entry *
9263 flow_dv_dest_array_create_cb(struct mlx5_cache_list *list __rte_unused,
9264                          struct mlx5_cache_entry *entry __rte_unused,
9265                          void *cb_ctx)
9266 {
9267         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9268         struct rte_eth_dev *dev = ctx->dev;
9269         struct mlx5_flow_dv_dest_array_resource *cache_resource;
9270         struct mlx5_flow_dv_dest_array_resource *resource = ctx->data;
9271         struct mlx5dv_dr_action_dest_attr *dest_attr[MLX5_MAX_DEST_NUM] = { 0 };
9272         struct mlx5dv_dr_action_dest_reformat dest_reformat[MLX5_MAX_DEST_NUM];
9273         struct mlx5_priv *priv = dev->data->dev_private;
9274         struct mlx5_dev_ctx_shared *sh = priv->sh;
9275         struct mlx5_flow_sub_actions_list *sample_act;
9276         struct mlx5dv_dr_domain *domain;
9277         uint32_t idx = 0, res_idx = 0;
9278         struct rte_flow_error *error = ctx->error;
9279         uint64_t action_flags;
9280         int ret;
9281
9282         /* Register new destination array resource. */
9283         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
9284                                             &res_idx);
9285         if (!cache_resource) {
9286                 rte_flow_error_set(error, ENOMEM,
9287                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9288                                           NULL,
9289                                           "cannot allocate resource memory");
9290                 return NULL;
9291         }
9292         *cache_resource = *resource;
9293         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
9294                 domain = sh->fdb_domain;
9295         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
9296                 domain = sh->rx_domain;
9297         else
9298                 domain = sh->tx_domain;
9299         for (idx = 0; idx < resource->num_of_dest; idx++) {
9300                 dest_attr[idx] = (struct mlx5dv_dr_action_dest_attr *)
9301                                  mlx5_malloc(MLX5_MEM_ZERO,
9302                                  sizeof(struct mlx5dv_dr_action_dest_attr),
9303                                  0, SOCKET_ID_ANY);
9304                 if (!dest_attr[idx]) {
9305                         rte_flow_error_set(error, ENOMEM,
9306                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9307                                            NULL,
9308                                            "cannot allocate resource memory");
9309                         goto error;
9310                 }
9311                 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST;
9312                 sample_act = &resource->sample_act[idx];
9313                 action_flags = sample_act->action_flags;
9314                 switch (action_flags) {
9315                 case MLX5_FLOW_ACTION_QUEUE:
9316                         dest_attr[idx]->dest = sample_act->dr_queue_action;
9317                         break;
9318                 case (MLX5_FLOW_ACTION_PORT_ID | MLX5_FLOW_ACTION_ENCAP):
9319                         dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST_REFORMAT;
9320                         dest_attr[idx]->dest_reformat = &dest_reformat[idx];
9321                         dest_attr[idx]->dest_reformat->reformat =
9322                                         sample_act->dr_encap_action;
9323                         dest_attr[idx]->dest_reformat->dest =
9324                                         sample_act->dr_port_id_action;
9325                         break;
9326                 case MLX5_FLOW_ACTION_PORT_ID:
9327                         dest_attr[idx]->dest = sample_act->dr_port_id_action;
9328                         break;
9329                 case MLX5_FLOW_ACTION_JUMP:
9330                         dest_attr[idx]->dest = sample_act->dr_jump_action;
9331                         break;
9332                 default:
9333                         rte_flow_error_set(error, EINVAL,
9334                                            RTE_FLOW_ERROR_TYPE_ACTION,
9335                                            NULL,
9336                                            "unsupported actions type");
9337                         goto error;
9338                 }
9339         }
9340         /* create a dest array actioin */
9341         ret = mlx5_os_flow_dr_create_flow_action_dest_array
9342                                                 (domain,
9343                                                  cache_resource->num_of_dest,
9344                                                  dest_attr,
9345                                                  &cache_resource->action);
9346         if (ret) {
9347                 rte_flow_error_set(error, ENOMEM,
9348                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9349                                    NULL,
9350                                    "cannot create destination array action");
9351                 goto error;
9352         }
9353         cache_resource->idx = res_idx;
9354         cache_resource->dev = dev;
9355         for (idx = 0; idx < resource->num_of_dest; idx++)
9356                 mlx5_free(dest_attr[idx]);
9357         return &cache_resource->entry;
9358 error:
9359         for (idx = 0; idx < resource->num_of_dest; idx++) {
9360                 struct mlx5_flow_sub_actions_idx *act_res =
9361                                         &cache_resource->sample_idx[idx];
9362                 if (act_res->rix_hrxq &&
9363                     !mlx5_hrxq_release(dev,
9364                                 act_res->rix_hrxq))
9365                         act_res->rix_hrxq = 0;
9366                 if (act_res->rix_encap_decap &&
9367                         !flow_dv_encap_decap_resource_release(dev,
9368                                 act_res->rix_encap_decap))
9369                         act_res->rix_encap_decap = 0;
9370                 if (act_res->rix_port_id_action &&
9371                         !flow_dv_port_id_action_resource_release(dev,
9372                                 act_res->rix_port_id_action))
9373                         act_res->rix_port_id_action = 0;
9374                 if (act_res->rix_jump &&
9375                         !flow_dv_jump_tbl_resource_release(dev,
9376                                 act_res->rix_jump))
9377                         act_res->rix_jump = 0;
9378                 if (dest_attr[idx])
9379                         mlx5_free(dest_attr[idx]);
9380         }
9381
9382         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DEST_ARRAY], res_idx);
9383         return NULL;
9384 }
9385
9386 /**
9387  * Find existing destination array resource or create and register a new one.
9388  *
9389  * @param[in, out] dev
9390  *   Pointer to rte_eth_dev structure.
9391  * @param[in] resource
9392  *   Pointer to destination array resource.
9393  * @parm[in, out] dev_flow
9394  *   Pointer to the dev_flow.
9395  * @param[out] error
9396  *   pointer to error structure.
9397  *
9398  * @return
9399  *   0 on success otherwise -errno and errno is set.
9400  */
9401 static int
9402 flow_dv_dest_array_resource_register(struct rte_eth_dev *dev,
9403                          struct mlx5_flow_dv_dest_array_resource *resource,
9404                          struct mlx5_flow *dev_flow,
9405                          struct rte_flow_error *error)
9406 {
9407         struct mlx5_flow_dv_dest_array_resource *cache_resource;
9408         struct mlx5_priv *priv = dev->data->dev_private;
9409         struct mlx5_cache_entry *entry;
9410         struct mlx5_flow_cb_ctx ctx = {
9411                 .dev = dev,
9412                 .error = error,
9413                 .data = resource,
9414         };
9415
9416         entry = mlx5_cache_register(&priv->sh->dest_array_list, &ctx);
9417         if (!entry)
9418                 return -rte_errno;
9419         cache_resource = container_of(entry, typeof(*cache_resource), entry);
9420         dev_flow->handle->dvh.rix_dest_array = cache_resource->idx;
9421         dev_flow->dv.dest_array_res = cache_resource;
9422         return 0;
9423 }
9424
9425 /**
9426  * Convert Sample action to DV specification.
9427  *
9428  * @param[in] dev
9429  *   Pointer to rte_eth_dev structure.
9430  * @param[in] action
9431  *   Pointer to sample action structure.
9432  * @param[in, out] dev_flow
9433  *   Pointer to the mlx5_flow.
9434  * @param[in] attr
9435  *   Pointer to the flow attributes.
9436  * @param[in, out] num_of_dest
9437  *   Pointer to the num of destination.
9438  * @param[in, out] sample_actions
9439  *   Pointer to sample actions list.
9440  * @param[in, out] res
9441  *   Pointer to sample resource.
9442  * @param[out] error
9443  *   Pointer to the error structure.
9444  *
9445  * @return
9446  *   0 on success, a negative errno value otherwise and rte_errno is set.
9447  */
9448 static int
9449 flow_dv_translate_action_sample(struct rte_eth_dev *dev,
9450                                 const struct rte_flow_action_sample *action,
9451                                 struct mlx5_flow *dev_flow,
9452                                 const struct rte_flow_attr *attr,
9453                                 uint32_t *num_of_dest,
9454                                 void **sample_actions,
9455                                 struct mlx5_flow_dv_sample_resource *res,
9456                                 struct rte_flow_error *error)
9457 {
9458         struct mlx5_priv *priv = dev->data->dev_private;
9459         const struct rte_flow_action *sub_actions;
9460         struct mlx5_flow_sub_actions_list *sample_act;
9461         struct mlx5_flow_sub_actions_idx *sample_idx;
9462         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
9463         struct mlx5_flow_rss_desc *rss_desc;
9464         uint64_t action_flags = 0;
9465
9466         MLX5_ASSERT(wks);
9467         rss_desc = &wks->rss_desc;
9468         sample_act = &res->sample_act;
9469         sample_idx = &res->sample_idx;
9470         res->ratio = action->ratio;
9471         sub_actions = action->actions;
9472         for (; sub_actions->type != RTE_FLOW_ACTION_TYPE_END; sub_actions++) {
9473                 int type = sub_actions->type;
9474                 uint32_t pre_rix = 0;
9475                 void *pre_r;
9476                 switch (type) {
9477                 case RTE_FLOW_ACTION_TYPE_QUEUE:
9478                 {
9479                         const struct rte_flow_action_queue *queue;
9480                         struct mlx5_hrxq *hrxq;
9481                         uint32_t hrxq_idx;
9482
9483                         queue = sub_actions->conf;
9484                         rss_desc->queue_num = 1;
9485                         rss_desc->queue[0] = queue->index;
9486                         hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
9487                                                     rss_desc, &hrxq_idx);
9488                         if (!hrxq)
9489                                 return rte_flow_error_set
9490                                         (error, rte_errno,
9491                                          RTE_FLOW_ERROR_TYPE_ACTION,
9492                                          NULL,
9493                                          "cannot create fate queue");
9494                         sample_act->dr_queue_action = hrxq->action;
9495                         sample_idx->rix_hrxq = hrxq_idx;
9496                         sample_actions[sample_act->actions_num++] =
9497                                                 hrxq->action;
9498                         (*num_of_dest)++;
9499                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
9500                         if (action_flags & MLX5_FLOW_ACTION_MARK)
9501                                 dev_flow->handle->rix_hrxq = hrxq_idx;
9502                         dev_flow->handle->fate_action =
9503                                         MLX5_FLOW_FATE_QUEUE;
9504                         break;
9505                 }
9506                 case RTE_FLOW_ACTION_TYPE_RSS:
9507                 {
9508                         struct mlx5_hrxq *hrxq;
9509                         uint32_t hrxq_idx;
9510                         const struct rte_flow_action_rss *rss;
9511                         const uint8_t *rss_key;
9512
9513                         rss = sub_actions->conf;
9514                         memcpy(rss_desc->queue, rss->queue,
9515                                rss->queue_num * sizeof(uint16_t));
9516                         rss_desc->queue_num = rss->queue_num;
9517                         /* NULL RSS key indicates default RSS key. */
9518                         rss_key = !rss->key ? rss_hash_default_key : rss->key;
9519                         memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
9520                         /*
9521                          * rss->level and rss.types should be set in advance
9522                          * when expanding items for RSS.
9523                          */
9524                         flow_dv_hashfields_set(dev_flow, rss_desc);
9525                         hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
9526                                                     rss_desc, &hrxq_idx);
9527                         if (!hrxq)
9528                                 return rte_flow_error_set
9529                                         (error, rte_errno,
9530                                          RTE_FLOW_ERROR_TYPE_ACTION,
9531                                          NULL,
9532                                          "cannot create fate queue");
9533                         sample_act->dr_queue_action = hrxq->action;
9534                         sample_idx->rix_hrxq = hrxq_idx;
9535                         sample_actions[sample_act->actions_num++] =
9536                                                 hrxq->action;
9537                         (*num_of_dest)++;
9538                         action_flags |= MLX5_FLOW_ACTION_RSS;
9539                         if (action_flags & MLX5_FLOW_ACTION_MARK)
9540                                 dev_flow->handle->rix_hrxq = hrxq_idx;
9541                         dev_flow->handle->fate_action =
9542                                         MLX5_FLOW_FATE_QUEUE;
9543                         break;
9544                 }
9545                 case RTE_FLOW_ACTION_TYPE_MARK:
9546                 {
9547                         uint32_t tag_be = mlx5_flow_mark_set
9548                                 (((const struct rte_flow_action_mark *)
9549                                 (sub_actions->conf))->id);
9550
9551                         dev_flow->handle->mark = 1;
9552                         pre_rix = dev_flow->handle->dvh.rix_tag;
9553                         /* Save the mark resource before sample */
9554                         pre_r = dev_flow->dv.tag_resource;
9555                         if (flow_dv_tag_resource_register(dev, tag_be,
9556                                                   dev_flow, error))
9557                                 return -rte_errno;
9558                         MLX5_ASSERT(dev_flow->dv.tag_resource);
9559                         sample_act->dr_tag_action =
9560                                 dev_flow->dv.tag_resource->action;
9561                         sample_idx->rix_tag =
9562                                 dev_flow->handle->dvh.rix_tag;
9563                         sample_actions[sample_act->actions_num++] =
9564                                                 sample_act->dr_tag_action;
9565                         /* Recover the mark resource after sample */
9566                         dev_flow->dv.tag_resource = pre_r;
9567                         dev_flow->handle->dvh.rix_tag = pre_rix;
9568                         action_flags |= MLX5_FLOW_ACTION_MARK;
9569                         break;
9570                 }
9571                 case RTE_FLOW_ACTION_TYPE_COUNT:
9572                 {
9573                         uint32_t counter;
9574
9575                         counter = flow_dv_translate_create_counter(dev,
9576                                         dev_flow, sub_actions->conf, 0);
9577                         if (!counter)
9578                                 return rte_flow_error_set
9579                                                 (error, rte_errno,
9580                                                  RTE_FLOW_ERROR_TYPE_ACTION,
9581                                                  NULL,
9582                                                  "cannot create counter"
9583                                                  " object.");
9584                         sample_idx->cnt = counter;
9585                         sample_act->dr_cnt_action =
9586                                   (flow_dv_counter_get_by_idx(dev,
9587                                   counter, NULL))->action;
9588                         sample_actions[sample_act->actions_num++] =
9589                                                 sample_act->dr_cnt_action;
9590                         action_flags |= MLX5_FLOW_ACTION_COUNT;
9591                         break;
9592                 }
9593                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
9594                 {
9595                         struct mlx5_flow_dv_port_id_action_resource
9596                                         port_id_resource;
9597                         uint32_t port_id = 0;
9598
9599                         memset(&port_id_resource, 0, sizeof(port_id_resource));
9600                         /* Save the port id resource before sample */
9601                         pre_rix = dev_flow->handle->rix_port_id_action;
9602                         pre_r = dev_flow->dv.port_id_action;
9603                         if (flow_dv_translate_action_port_id(dev, sub_actions,
9604                                                              &port_id, error))
9605                                 return -rte_errno;
9606                         port_id_resource.port_id = port_id;
9607                         if (flow_dv_port_id_action_resource_register
9608                             (dev, &port_id_resource, dev_flow, error))
9609                                 return -rte_errno;
9610                         sample_act->dr_port_id_action =
9611                                 dev_flow->dv.port_id_action->action;
9612                         sample_idx->rix_port_id_action =
9613                                 dev_flow->handle->rix_port_id_action;
9614                         sample_actions[sample_act->actions_num++] =
9615                                                 sample_act->dr_port_id_action;
9616                         /* Recover the port id resource after sample */
9617                         dev_flow->dv.port_id_action = pre_r;
9618                         dev_flow->handle->rix_port_id_action = pre_rix;
9619                         (*num_of_dest)++;
9620                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
9621                         break;
9622                 }
9623                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
9624                         /* Save the encap resource before sample */
9625                         pre_rix = dev_flow->handle->dvh.rix_encap_decap;
9626                         pre_r = dev_flow->dv.encap_decap;
9627                         if (flow_dv_create_action_l2_encap(dev, sub_actions,
9628                                                            dev_flow,
9629                                                            attr->transfer,
9630                                                            error))
9631                                 return -rte_errno;
9632                         sample_act->dr_encap_action =
9633                                 dev_flow->dv.encap_decap->action;
9634                         sample_idx->rix_encap_decap =
9635                                 dev_flow->handle->dvh.rix_encap_decap;
9636                         sample_actions[sample_act->actions_num++] =
9637                                                 sample_act->dr_encap_action;
9638                         /* Recover the encap resource after sample */
9639                         dev_flow->dv.encap_decap = pre_r;
9640                         dev_flow->handle->dvh.rix_encap_decap = pre_rix;
9641                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
9642                         break;
9643                 default:
9644                         return rte_flow_error_set(error, EINVAL,
9645                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9646                                 NULL,
9647                                 "Not support for sampler action");
9648                 }
9649         }
9650         sample_act->action_flags = action_flags;
9651         res->ft_id = dev_flow->dv.group;
9652         if (attr->transfer) {
9653                 union {
9654                         uint32_t action_in[MLX5_ST_SZ_DW(set_action_in)];
9655                         uint64_t set_action;
9656                 } action_ctx = { .set_action = 0 };
9657
9658                 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
9659                 MLX5_SET(set_action_in, action_ctx.action_in, action_type,
9660                          MLX5_MODIFICATION_TYPE_SET);
9661                 MLX5_SET(set_action_in, action_ctx.action_in, field,
9662                          MLX5_MODI_META_REG_C_0);
9663                 MLX5_SET(set_action_in, action_ctx.action_in, data,
9664                          priv->vport_meta_tag);
9665                 res->set_action = action_ctx.set_action;
9666         } else if (attr->ingress) {
9667                 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
9668         } else {
9669                 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_TX;
9670         }
9671         return 0;
9672 }
9673
9674 /**
9675  * Convert Sample action to DV specification.
9676  *
9677  * @param[in] dev
9678  *   Pointer to rte_eth_dev structure.
9679  * @param[in, out] dev_flow
9680  *   Pointer to the mlx5_flow.
9681  * @param[in] num_of_dest
9682  *   The num of destination.
9683  * @param[in, out] res
9684  *   Pointer to sample resource.
9685  * @param[in, out] mdest_res
9686  *   Pointer to destination array resource.
9687  * @param[in] sample_actions
9688  *   Pointer to sample path actions list.
9689  * @param[in] action_flags
9690  *   Holds the actions detected until now.
9691  * @param[out] error
9692  *   Pointer to the error structure.
9693  *
9694  * @return
9695  *   0 on success, a negative errno value otherwise and rte_errno is set.
9696  */
9697 static int
9698 flow_dv_create_action_sample(struct rte_eth_dev *dev,
9699                              struct mlx5_flow *dev_flow,
9700                              uint32_t num_of_dest,
9701                              struct mlx5_flow_dv_sample_resource *res,
9702                              struct mlx5_flow_dv_dest_array_resource *mdest_res,
9703                              void **sample_actions,
9704                              uint64_t action_flags,
9705                              struct rte_flow_error *error)
9706 {
9707         /* update normal path action resource into last index of array */
9708         uint32_t dest_index = MLX5_MAX_DEST_NUM - 1;
9709         struct mlx5_flow_sub_actions_list *sample_act =
9710                                         &mdest_res->sample_act[dest_index];
9711         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
9712         struct mlx5_flow_rss_desc *rss_desc;
9713         uint32_t normal_idx = 0;
9714         struct mlx5_hrxq *hrxq;
9715         uint32_t hrxq_idx;
9716
9717         MLX5_ASSERT(wks);
9718         rss_desc = &wks->rss_desc;
9719         if (num_of_dest > 1) {
9720                 if (sample_act->action_flags & MLX5_FLOW_ACTION_QUEUE) {
9721                         /* Handle QP action for mirroring */
9722                         hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
9723                                                     rss_desc, &hrxq_idx);
9724                         if (!hrxq)
9725                                 return rte_flow_error_set
9726                                      (error, rte_errno,
9727                                       RTE_FLOW_ERROR_TYPE_ACTION,
9728                                       NULL,
9729                                       "cannot create rx queue");
9730                         normal_idx++;
9731                         mdest_res->sample_idx[dest_index].rix_hrxq = hrxq_idx;
9732                         sample_act->dr_queue_action = hrxq->action;
9733                         if (action_flags & MLX5_FLOW_ACTION_MARK)
9734                                 dev_flow->handle->rix_hrxq = hrxq_idx;
9735                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
9736                 }
9737                 if (sample_act->action_flags & MLX5_FLOW_ACTION_ENCAP) {
9738                         normal_idx++;
9739                         mdest_res->sample_idx[dest_index].rix_encap_decap =
9740                                 dev_flow->handle->dvh.rix_encap_decap;
9741                         sample_act->dr_encap_action =
9742                                 dev_flow->dv.encap_decap->action;
9743                 }
9744                 if (sample_act->action_flags & MLX5_FLOW_ACTION_PORT_ID) {
9745                         normal_idx++;
9746                         mdest_res->sample_idx[dest_index].rix_port_id_action =
9747                                 dev_flow->handle->rix_port_id_action;
9748                         sample_act->dr_port_id_action =
9749                                 dev_flow->dv.port_id_action->action;
9750                 }
9751                 if (sample_act->action_flags & MLX5_FLOW_ACTION_JUMP) {
9752                         normal_idx++;
9753                         mdest_res->sample_idx[dest_index].rix_jump =
9754                                 dev_flow->handle->rix_jump;
9755                         sample_act->dr_jump_action =
9756                                 dev_flow->dv.jump->action;
9757                         dev_flow->handle->rix_jump = 0;
9758                 }
9759                 sample_act->actions_num = normal_idx;
9760                 /* update sample action resource into first index of array */
9761                 mdest_res->ft_type = res->ft_type;
9762                 memcpy(&mdest_res->sample_idx[0], &res->sample_idx,
9763                                 sizeof(struct mlx5_flow_sub_actions_idx));
9764                 memcpy(&mdest_res->sample_act[0], &res->sample_act,
9765                                 sizeof(struct mlx5_flow_sub_actions_list));
9766                 mdest_res->num_of_dest = num_of_dest;
9767                 if (flow_dv_dest_array_resource_register(dev, mdest_res,
9768                                                          dev_flow, error))
9769                         return rte_flow_error_set(error, EINVAL,
9770                                                   RTE_FLOW_ERROR_TYPE_ACTION,
9771                                                   NULL, "can't create sample "
9772                                                   "action");
9773         } else {
9774                 res->sub_actions = sample_actions;
9775                 if (flow_dv_sample_resource_register(dev, res, dev_flow, error))
9776                         return rte_flow_error_set(error, EINVAL,
9777                                                   RTE_FLOW_ERROR_TYPE_ACTION,
9778                                                   NULL,
9779                                                   "can't create sample action");
9780         }
9781         return 0;
9782 }
9783
9784 /**
9785  * Remove an ASO age action from age actions list.
9786  *
9787  * @param[in] dev
9788  *   Pointer to the Ethernet device structure.
9789  * @param[in] age
9790  *   Pointer to the aso age action handler.
9791  */
9792 static void
9793 flow_dv_aso_age_remove_from_age(struct rte_eth_dev *dev,
9794                                 struct mlx5_aso_age_action *age)
9795 {
9796         struct mlx5_age_info *age_info;
9797         struct mlx5_age_param *age_param = &age->age_params;
9798         struct mlx5_priv *priv = dev->data->dev_private;
9799         uint16_t expected = AGE_CANDIDATE;
9800
9801         age_info = GET_PORT_AGE_INFO(priv);
9802         if (!__atomic_compare_exchange_n(&age_param->state, &expected,
9803                                          AGE_FREE, false, __ATOMIC_RELAXED,
9804                                          __ATOMIC_RELAXED)) {
9805                 /**
9806                  * We need the lock even it is age timeout,
9807                  * since age action may still in process.
9808                  */
9809                 rte_spinlock_lock(&age_info->aged_sl);
9810                 LIST_REMOVE(age, next);
9811                 rte_spinlock_unlock(&age_info->aged_sl);
9812                 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
9813         }
9814 }
9815
9816 /**
9817  * Release an ASO age action.
9818  *
9819  * @param[in] dev
9820  *   Pointer to the Ethernet device structure.
9821  * @param[in] age_idx
9822  *   Index of ASO age action to release.
9823  * @param[in] flow
9824  *   True if the release operation is during flow destroy operation.
9825  *   False if the release operation is during action destroy operation.
9826  *
9827  * @return
9828  *   0 when age action was removed, otherwise the number of references.
9829  */
9830 static int
9831 flow_dv_aso_age_release(struct rte_eth_dev *dev, uint32_t age_idx)
9832 {
9833         struct mlx5_priv *priv = dev->data->dev_private;
9834         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
9835         struct mlx5_aso_age_action *age = flow_aso_age_get_by_idx(dev, age_idx);
9836         uint32_t ret = __atomic_sub_fetch(&age->refcnt, 1, __ATOMIC_RELAXED);
9837
9838         if (!ret) {
9839                 flow_dv_aso_age_remove_from_age(dev, age);
9840                 rte_spinlock_lock(&mng->free_sl);
9841                 LIST_INSERT_HEAD(&mng->free, age, next);
9842                 rte_spinlock_unlock(&mng->free_sl);
9843         }
9844         return ret;
9845 }
9846
9847 /**
9848  * Resize the ASO age pools array by MLX5_CNT_CONTAINER_RESIZE pools.
9849  *
9850  * @param[in] dev
9851  *   Pointer to the Ethernet device structure.
9852  *
9853  * @return
9854  *   0 on success, otherwise negative errno value and rte_errno is set.
9855  */
9856 static int
9857 flow_dv_aso_age_pools_resize(struct rte_eth_dev *dev)
9858 {
9859         struct mlx5_priv *priv = dev->data->dev_private;
9860         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
9861         void *old_pools = mng->pools;
9862         uint32_t resize = mng->n + MLX5_CNT_CONTAINER_RESIZE;
9863         uint32_t mem_size = sizeof(struct mlx5_aso_age_pool *) * resize;
9864         void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
9865
9866         if (!pools) {
9867                 rte_errno = ENOMEM;
9868                 return -ENOMEM;
9869         }
9870         if (old_pools) {
9871                 memcpy(pools, old_pools,
9872                        mng->n * sizeof(struct mlx5_flow_counter_pool *));
9873                 mlx5_free(old_pools);
9874         } else {
9875                 /* First ASO flow hit allocation - starting ASO data-path. */
9876                 int ret = mlx5_aso_queue_start(priv->sh);
9877
9878                 if (ret) {
9879                         mlx5_free(pools);
9880                         return ret;
9881                 }
9882         }
9883         mng->n = resize;
9884         mng->pools = pools;
9885         return 0;
9886 }
9887
9888 /**
9889  * Create and initialize a new ASO aging pool.
9890  *
9891  * @param[in] dev
9892  *   Pointer to the Ethernet device structure.
9893  * @param[out] age_free
9894  *   Where to put the pointer of a new age action.
9895  *
9896  * @return
9897  *   The age actions pool pointer and @p age_free is set on success,
9898  *   NULL otherwise and rte_errno is set.
9899  */
9900 static struct mlx5_aso_age_pool *
9901 flow_dv_age_pool_create(struct rte_eth_dev *dev,
9902                         struct mlx5_aso_age_action **age_free)
9903 {
9904         struct mlx5_priv *priv = dev->data->dev_private;
9905         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
9906         struct mlx5_aso_age_pool *pool = NULL;
9907         struct mlx5_devx_obj *obj = NULL;
9908         uint32_t i;
9909
9910         obj = mlx5_devx_cmd_create_flow_hit_aso_obj(priv->sh->ctx,
9911                                                     priv->sh->pdn);
9912         if (!obj) {
9913                 rte_errno = ENODATA;
9914                 DRV_LOG(ERR, "Failed to create flow_hit_aso_obj using DevX.");
9915                 return NULL;
9916         }
9917         pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
9918         if (!pool) {
9919                 claim_zero(mlx5_devx_cmd_destroy(obj));
9920                 rte_errno = ENOMEM;
9921                 return NULL;
9922         }
9923         pool->flow_hit_aso_obj = obj;
9924         pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
9925         rte_spinlock_lock(&mng->resize_sl);
9926         pool->index = mng->next;
9927         /* Resize pools array if there is no room for the new pool in it. */
9928         if (pool->index == mng->n && flow_dv_aso_age_pools_resize(dev)) {
9929                 claim_zero(mlx5_devx_cmd_destroy(obj));
9930                 mlx5_free(pool);
9931                 rte_spinlock_unlock(&mng->resize_sl);
9932                 return NULL;
9933         }
9934         mng->pools[pool->index] = pool;
9935         mng->next++;
9936         rte_spinlock_unlock(&mng->resize_sl);
9937         /* Assign the first action in the new pool, the rest go to free list. */
9938         *age_free = &pool->actions[0];
9939         for (i = 1; i < MLX5_ASO_AGE_ACTIONS_PER_POOL; i++) {
9940                 pool->actions[i].offset = i;
9941                 LIST_INSERT_HEAD(&mng->free, &pool->actions[i], next);
9942         }
9943         return pool;
9944 }
9945
9946 /**
9947  * Allocate a ASO aging bit.
9948  *
9949  * @param[in] dev
9950  *   Pointer to the Ethernet device structure.
9951  * @param[out] error
9952  *   Pointer to the error structure.
9953  *
9954  * @return
9955  *   Index to ASO age action on success, 0 otherwise and rte_errno is set.
9956  */
9957 static uint32_t
9958 flow_dv_aso_age_alloc(struct rte_eth_dev *dev, struct rte_flow_error *error)
9959 {
9960         struct mlx5_priv *priv = dev->data->dev_private;
9961         const struct mlx5_aso_age_pool *pool;
9962         struct mlx5_aso_age_action *age_free = NULL;
9963         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
9964
9965         MLX5_ASSERT(mng);
9966         /* Try to get the next free age action bit. */
9967         rte_spinlock_lock(&mng->free_sl);
9968         age_free = LIST_FIRST(&mng->free);
9969         if (age_free) {
9970                 LIST_REMOVE(age_free, next);
9971         } else if (!flow_dv_age_pool_create(dev, &age_free)) {
9972                 rte_spinlock_unlock(&mng->free_sl);
9973                 rte_flow_error_set(error, rte_errno, RTE_FLOW_ERROR_TYPE_ACTION,
9974                                    NULL, "failed to create ASO age pool");
9975                 return 0; /* 0 is an error. */
9976         }
9977         rte_spinlock_unlock(&mng->free_sl);
9978         pool = container_of
9979           ((const struct mlx5_aso_age_action (*)[MLX5_ASO_AGE_ACTIONS_PER_POOL])
9980                   (age_free - age_free->offset), const struct mlx5_aso_age_pool,
9981                                                                        actions);
9982         if (!age_free->dr_action) {
9983                 int reg_c = mlx5_flow_get_reg_id(dev, MLX5_ASO_FLOW_HIT, 0,
9984                                                  error);
9985
9986                 if (reg_c < 0) {
9987                         rte_flow_error_set(error, rte_errno,
9988                                            RTE_FLOW_ERROR_TYPE_ACTION,
9989                                            NULL, "failed to get reg_c "
9990                                            "for ASO flow hit");
9991                         return 0; /* 0 is an error. */
9992                 }
9993 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
9994                 age_free->dr_action = mlx5_glue->dv_create_flow_action_aso
9995                                 (priv->sh->rx_domain,
9996                                  pool->flow_hit_aso_obj->obj, age_free->offset,
9997                                  MLX5DV_DR_ACTION_FLAGS_ASO_FIRST_HIT_SET,
9998                                  (reg_c - REG_C_0));
9999 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
10000                 if (!age_free->dr_action) {
10001                         rte_errno = errno;
10002                         rte_spinlock_lock(&mng->free_sl);
10003                         LIST_INSERT_HEAD(&mng->free, age_free, next);
10004                         rte_spinlock_unlock(&mng->free_sl);
10005                         rte_flow_error_set(error, rte_errno,
10006                                            RTE_FLOW_ERROR_TYPE_ACTION,
10007                                            NULL, "failed to create ASO "
10008                                            "flow hit action");
10009                         return 0; /* 0 is an error. */
10010                 }
10011         }
10012         __atomic_store_n(&age_free->refcnt, 1, __ATOMIC_RELAXED);
10013         return pool->index | ((age_free->offset + 1) << 16);
10014 }
10015
10016 /**
10017  * Create a age action using ASO mechanism.
10018  *
10019  * @param[in] dev
10020  *   Pointer to rte_eth_dev structure.
10021  * @param[in] age
10022  *   Pointer to the aging action configuration.
10023  * @param[out] error
10024  *   Pointer to the error structure.
10025  *
10026  * @return
10027  *   Index to flow counter on success, 0 otherwise.
10028  */
10029 static uint32_t
10030 flow_dv_translate_create_aso_age(struct rte_eth_dev *dev,
10031                                  const struct rte_flow_action_age *age,
10032                                  struct rte_flow_error *error)
10033 {
10034         uint32_t age_idx = 0;
10035         struct mlx5_aso_age_action *aso_age;
10036
10037         age_idx = flow_dv_aso_age_alloc(dev, error);
10038         if (!age_idx)
10039                 return 0;
10040         aso_age = flow_aso_age_get_by_idx(dev, age_idx);
10041         aso_age->age_params.context = age->context;
10042         aso_age->age_params.timeout = age->timeout;
10043         aso_age->age_params.port_id = dev->data->port_id;
10044         __atomic_store_n(&aso_age->age_params.sec_since_last_hit, 0,
10045                          __ATOMIC_RELAXED);
10046         __atomic_store_n(&aso_age->age_params.state, AGE_CANDIDATE,
10047                          __ATOMIC_RELAXED);
10048         return age_idx;
10049 }
10050
10051 /**
10052  * Fill the flow with DV spec, lock free
10053  * (mutex should be acquired by caller).
10054  *
10055  * @param[in] dev
10056  *   Pointer to rte_eth_dev structure.
10057  * @param[in, out] dev_flow
10058  *   Pointer to the sub flow.
10059  * @param[in] attr
10060  *   Pointer to the flow attributes.
10061  * @param[in] items
10062  *   Pointer to the list of items.
10063  * @param[in] actions
10064  *   Pointer to the list of actions.
10065  * @param[out] error
10066  *   Pointer to the error structure.
10067  *
10068  * @return
10069  *   0 on success, a negative errno value otherwise and rte_errno is set.
10070  */
10071 static int
10072 flow_dv_translate(struct rte_eth_dev *dev,
10073                   struct mlx5_flow *dev_flow,
10074                   const struct rte_flow_attr *attr,
10075                   const struct rte_flow_item items[],
10076                   const struct rte_flow_action actions[],
10077                   struct rte_flow_error *error)
10078 {
10079         struct mlx5_priv *priv = dev->data->dev_private;
10080         struct mlx5_dev_config *dev_conf = &priv->config;
10081         struct rte_flow *flow = dev_flow->flow;
10082         struct mlx5_flow_handle *handle = dev_flow->handle;
10083         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
10084         struct mlx5_flow_rss_desc *rss_desc;
10085         uint64_t item_flags = 0;
10086         uint64_t last_item = 0;
10087         uint64_t action_flags = 0;
10088         struct mlx5_flow_dv_matcher matcher = {
10089                 .mask = {
10090                         .size = sizeof(matcher.mask.buf) -
10091                                 MLX5_ST_SZ_BYTES(fte_match_set_misc4),
10092                 },
10093         };
10094         int actions_n = 0;
10095         bool actions_end = false;
10096         union {
10097                 struct mlx5_flow_dv_modify_hdr_resource res;
10098                 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
10099                             sizeof(struct mlx5_modification_cmd) *
10100                             (MLX5_MAX_MODIFY_NUM + 1)];
10101         } mhdr_dummy;
10102         struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
10103         const struct rte_flow_action_count *count = NULL;
10104         const struct rte_flow_action_age *age = NULL;
10105         union flow_dv_attr flow_attr = { .attr = 0 };
10106         uint32_t tag_be;
10107         union mlx5_flow_tbl_key tbl_key;
10108         uint32_t modify_action_position = UINT32_MAX;
10109         void *match_mask = matcher.mask.buf;
10110         void *match_value = dev_flow->dv.value.buf;
10111         uint8_t next_protocol = 0xff;
10112         struct rte_vlan_hdr vlan = { 0 };
10113         struct mlx5_flow_dv_dest_array_resource mdest_res;
10114         struct mlx5_flow_dv_sample_resource sample_res;
10115         void *sample_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
10116         const struct rte_flow_action_sample *sample = NULL;
10117         struct mlx5_flow_sub_actions_list *sample_act;
10118         uint32_t sample_act_pos = UINT32_MAX;
10119         uint32_t num_of_dest = 0;
10120         int tmp_actions_n = 0;
10121         uint32_t table;
10122         int ret = 0;
10123         const struct mlx5_flow_tunnel *tunnel;
10124         struct flow_grp_info grp_info = {
10125                 .external = !!dev_flow->external,
10126                 .transfer = !!attr->transfer,
10127                 .fdb_def_rule = !!priv->fdb_def_rule,
10128                 .skip_scale = dev_flow->skip_scale &
10129                         (1 << MLX5_SCALE_FLOW_GROUP_BIT),
10130         };
10131
10132         if (!wks)
10133                 return rte_flow_error_set(error, ENOMEM,
10134                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10135                                           NULL,
10136                                           "failed to push flow workspace");
10137         rss_desc = &wks->rss_desc;
10138         memset(&mdest_res, 0, sizeof(struct mlx5_flow_dv_dest_array_resource));
10139         memset(&sample_res, 0, sizeof(struct mlx5_flow_dv_sample_resource));
10140         mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
10141                                            MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
10142         /* update normal path action resource into last index of array */
10143         sample_act = &mdest_res.sample_act[MLX5_MAX_DEST_NUM - 1];
10144         tunnel = is_flow_tunnel_match_rule(dev, attr, items, actions) ?
10145                  flow_items_to_tunnel(items) :
10146                  is_flow_tunnel_steer_rule(dev, attr, items, actions) ?
10147                  flow_actions_to_tunnel(actions) :
10148                  dev_flow->tunnel ? dev_flow->tunnel : NULL;
10149         mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
10150                                            MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
10151         grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
10152                                 (dev, tunnel, attr, items, actions);
10153         ret = mlx5_flow_group_to_table(dev, tunnel, attr->group, &table,
10154                                        &grp_info, error);
10155         if (ret)
10156                 return ret;
10157         dev_flow->dv.group = table;
10158         if (attr->transfer)
10159                 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
10160         /* number of actions must be set to 0 in case of dirty stack. */
10161         mhdr_res->actions_num = 0;
10162         if (is_flow_tunnel_match_rule(dev, attr, items, actions)) {
10163                 /*
10164                  * do not add decap action if match rule drops packet
10165                  * HW rejects rules with decap & drop
10166                  *
10167                  * if tunnel match rule was inserted before matching tunnel set
10168                  * rule flow table used in the match rule must be registered.
10169                  * current implementation handles that in the
10170                  * flow_dv_match_register() at the function end.
10171                  */
10172                 bool add_decap = true;
10173                 const struct rte_flow_action *ptr = actions;
10174
10175                 for (; ptr->type != RTE_FLOW_ACTION_TYPE_END; ptr++) {
10176                         if (ptr->type == RTE_FLOW_ACTION_TYPE_DROP) {
10177                                 add_decap = false;
10178                                 break;
10179                         }
10180                 }
10181                 if (add_decap) {
10182                         if (flow_dv_create_action_l2_decap(dev, dev_flow,
10183                                                            attr->transfer,
10184                                                            error))
10185                                 return -rte_errno;
10186                         dev_flow->dv.actions[actions_n++] =
10187                                         dev_flow->dv.encap_decap->action;
10188                         action_flags |= MLX5_FLOW_ACTION_DECAP;
10189                 }
10190         }
10191         for (; !actions_end ; actions++) {
10192                 const struct rte_flow_action_queue *queue;
10193                 const struct rte_flow_action_rss *rss;
10194                 const struct rte_flow_action *action = actions;
10195                 const uint8_t *rss_key;
10196                 const struct rte_flow_action_meter *mtr;
10197                 struct mlx5_flow_tbl_resource *tbl;
10198                 struct mlx5_aso_age_action *age_act;
10199                 uint32_t port_id = 0;
10200                 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
10201                 int action_type = actions->type;
10202                 const struct rte_flow_action *found_action = NULL;
10203                 struct mlx5_flow_meter *fm = NULL;
10204                 uint32_t jump_group = 0;
10205
10206                 if (!mlx5_flow_os_action_supported(action_type))
10207                         return rte_flow_error_set(error, ENOTSUP,
10208                                                   RTE_FLOW_ERROR_TYPE_ACTION,
10209                                                   actions,
10210                                                   "action not supported");
10211                 switch (action_type) {
10212                 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
10213                         action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
10214                         break;
10215                 case RTE_FLOW_ACTION_TYPE_VOID:
10216                         break;
10217                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
10218                         if (flow_dv_translate_action_port_id(dev, action,
10219                                                              &port_id, error))
10220                                 return -rte_errno;
10221                         port_id_resource.port_id = port_id;
10222                         MLX5_ASSERT(!handle->rix_port_id_action);
10223                         if (flow_dv_port_id_action_resource_register
10224                             (dev, &port_id_resource, dev_flow, error))
10225                                 return -rte_errno;
10226                         dev_flow->dv.actions[actions_n++] =
10227                                         dev_flow->dv.port_id_action->action;
10228                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
10229                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_PORT_ID;
10230                         sample_act->action_flags |= MLX5_FLOW_ACTION_PORT_ID;
10231                         num_of_dest++;
10232                         break;
10233                 case RTE_FLOW_ACTION_TYPE_FLAG:
10234                         action_flags |= MLX5_FLOW_ACTION_FLAG;
10235                         dev_flow->handle->mark = 1;
10236                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
10237                                 struct rte_flow_action_mark mark = {
10238                                         .id = MLX5_FLOW_MARK_DEFAULT,
10239                                 };
10240
10241                                 if (flow_dv_convert_action_mark(dev, &mark,
10242                                                                 mhdr_res,
10243                                                                 error))
10244                                         return -rte_errno;
10245                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
10246                                 break;
10247                         }
10248                         tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
10249                         /*
10250                          * Only one FLAG or MARK is supported per device flow
10251                          * right now. So the pointer to the tag resource must be
10252                          * zero before the register process.
10253                          */
10254                         MLX5_ASSERT(!handle->dvh.rix_tag);
10255                         if (flow_dv_tag_resource_register(dev, tag_be,
10256                                                           dev_flow, error))
10257                                 return -rte_errno;
10258                         MLX5_ASSERT(dev_flow->dv.tag_resource);
10259                         dev_flow->dv.actions[actions_n++] =
10260                                         dev_flow->dv.tag_resource->action;
10261                         break;
10262                 case RTE_FLOW_ACTION_TYPE_MARK:
10263                         action_flags |= MLX5_FLOW_ACTION_MARK;
10264                         dev_flow->handle->mark = 1;
10265                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
10266                                 const struct rte_flow_action_mark *mark =
10267                                         (const struct rte_flow_action_mark *)
10268                                                 actions->conf;
10269
10270                                 if (flow_dv_convert_action_mark(dev, mark,
10271                                                                 mhdr_res,
10272                                                                 error))
10273                                         return -rte_errno;
10274                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
10275                                 break;
10276                         }
10277                         /* Fall-through */
10278                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
10279                         /* Legacy (non-extensive) MARK action. */
10280                         tag_be = mlx5_flow_mark_set
10281                               (((const struct rte_flow_action_mark *)
10282                                (actions->conf))->id);
10283                         MLX5_ASSERT(!handle->dvh.rix_tag);
10284                         if (flow_dv_tag_resource_register(dev, tag_be,
10285                                                           dev_flow, error))
10286                                 return -rte_errno;
10287                         MLX5_ASSERT(dev_flow->dv.tag_resource);
10288                         dev_flow->dv.actions[actions_n++] =
10289                                         dev_flow->dv.tag_resource->action;
10290                         break;
10291                 case RTE_FLOW_ACTION_TYPE_SET_META:
10292                         if (flow_dv_convert_action_set_meta
10293                                 (dev, mhdr_res, attr,
10294                                  (const struct rte_flow_action_set_meta *)
10295                                   actions->conf, error))
10296                                 return -rte_errno;
10297                         action_flags |= MLX5_FLOW_ACTION_SET_META;
10298                         break;
10299                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
10300                         if (flow_dv_convert_action_set_tag
10301                                 (dev, mhdr_res,
10302                                  (const struct rte_flow_action_set_tag *)
10303                                   actions->conf, error))
10304                                 return -rte_errno;
10305                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
10306                         break;
10307                 case RTE_FLOW_ACTION_TYPE_DROP:
10308                         action_flags |= MLX5_FLOW_ACTION_DROP;
10309                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_DROP;
10310                         break;
10311                 case RTE_FLOW_ACTION_TYPE_QUEUE:
10312                         queue = actions->conf;
10313                         rss_desc->queue_num = 1;
10314                         rss_desc->queue[0] = queue->index;
10315                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
10316                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
10317                         sample_act->action_flags |= MLX5_FLOW_ACTION_QUEUE;
10318                         num_of_dest++;
10319                         break;
10320                 case RTE_FLOW_ACTION_TYPE_RSS:
10321                         rss = actions->conf;
10322                         memcpy(rss_desc->queue, rss->queue,
10323                                rss->queue_num * sizeof(uint16_t));
10324                         rss_desc->queue_num = rss->queue_num;
10325                         /* NULL RSS key indicates default RSS key. */
10326                         rss_key = !rss->key ? rss_hash_default_key : rss->key;
10327                         memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
10328                         /*
10329                          * rss->level and rss.types should be set in advance
10330                          * when expanding items for RSS.
10331                          */
10332                         action_flags |= MLX5_FLOW_ACTION_RSS;
10333                         dev_flow->handle->fate_action = rss_desc->shared_rss ?
10334                                 MLX5_FLOW_FATE_SHARED_RSS :
10335                                 MLX5_FLOW_FATE_QUEUE;
10336                         break;
10337                 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
10338                         flow->age = (uint32_t)(uintptr_t)(action->conf);
10339                         age_act = flow_aso_age_get_by_idx(dev, flow->age);
10340                         __atomic_fetch_add(&age_act->refcnt, 1,
10341                                            __ATOMIC_RELAXED);
10342                         dev_flow->dv.actions[actions_n++] = age_act->dr_action;
10343                         action_flags |= MLX5_FLOW_ACTION_AGE;
10344                         break;
10345                 case RTE_FLOW_ACTION_TYPE_AGE:
10346                         if (priv->sh->flow_hit_aso_en && attr->group) {
10347                                 /*
10348                                  * Create one shared age action, to be used
10349                                  * by all sub-flows.
10350                                  */
10351                                 if (!flow->age) {
10352                                         flow->age =
10353                                                 flow_dv_translate_create_aso_age
10354                                                         (dev, action->conf,
10355                                                          error);
10356                                         if (!flow->age)
10357                                                 return rte_flow_error_set
10358                                                 (error, rte_errno,
10359                                                  RTE_FLOW_ERROR_TYPE_ACTION,
10360                                                  NULL,
10361                                                  "can't create ASO age action");
10362                                 }
10363                                 dev_flow->dv.actions[actions_n++] =
10364                                           (flow_aso_age_get_by_idx
10365                                                 (dev, flow->age))->dr_action;
10366                                 action_flags |= MLX5_FLOW_ACTION_AGE;
10367                                 break;
10368                         }
10369                         /* Fall-through */
10370                 case RTE_FLOW_ACTION_TYPE_COUNT:
10371                         if (!dev_conf->devx) {
10372                                 return rte_flow_error_set
10373                                               (error, ENOTSUP,
10374                                                RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10375                                                NULL,
10376                                                "count action not supported");
10377                         }
10378                         /* Save information first, will apply later. */
10379                         if (actions->type == RTE_FLOW_ACTION_TYPE_COUNT)
10380                                 count = action->conf;
10381                         else
10382                                 age = action->conf;
10383                         action_flags |= MLX5_FLOW_ACTION_COUNT;
10384                         break;
10385                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
10386                         dev_flow->dv.actions[actions_n++] =
10387                                                 priv->sh->pop_vlan_action;
10388                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
10389                         break;
10390                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
10391                         if (!(action_flags &
10392                               MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
10393                                 flow_dev_get_vlan_info_from_items(items, &vlan);
10394                         vlan.eth_proto = rte_be_to_cpu_16
10395                              ((((const struct rte_flow_action_of_push_vlan *)
10396                                                    actions->conf)->ethertype));
10397                         found_action = mlx5_flow_find_action
10398                                         (actions + 1,
10399                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
10400                         if (found_action)
10401                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
10402                         found_action = mlx5_flow_find_action
10403                                         (actions + 1,
10404                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
10405                         if (found_action)
10406                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
10407                         if (flow_dv_create_action_push_vlan
10408                                             (dev, attr, &vlan, dev_flow, error))
10409                                 return -rte_errno;
10410                         dev_flow->dv.actions[actions_n++] =
10411                                         dev_flow->dv.push_vlan_res->action;
10412                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
10413                         break;
10414                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
10415                         /* of_vlan_push action handled this action */
10416                         MLX5_ASSERT(action_flags &
10417                                     MLX5_FLOW_ACTION_OF_PUSH_VLAN);
10418                         break;
10419                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
10420                         if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
10421                                 break;
10422                         flow_dev_get_vlan_info_from_items(items, &vlan);
10423                         mlx5_update_vlan_vid_pcp(actions, &vlan);
10424                         /* If no VLAN push - this is a modify header action */
10425                         if (flow_dv_convert_action_modify_vlan_vid
10426                                                 (mhdr_res, actions, error))
10427                                 return -rte_errno;
10428                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
10429                         break;
10430                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
10431                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
10432                         if (flow_dv_create_action_l2_encap(dev, actions,
10433                                                            dev_flow,
10434                                                            attr->transfer,
10435                                                            error))
10436                                 return -rte_errno;
10437                         dev_flow->dv.actions[actions_n++] =
10438                                         dev_flow->dv.encap_decap->action;
10439                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
10440                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
10441                                 sample_act->action_flags |=
10442                                                         MLX5_FLOW_ACTION_ENCAP;
10443                         break;
10444                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
10445                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
10446                         if (flow_dv_create_action_l2_decap(dev, dev_flow,
10447                                                            attr->transfer,
10448                                                            error))
10449                                 return -rte_errno;
10450                         dev_flow->dv.actions[actions_n++] =
10451                                         dev_flow->dv.encap_decap->action;
10452                         action_flags |= MLX5_FLOW_ACTION_DECAP;
10453                         break;
10454                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
10455                         /* Handle encap with preceding decap. */
10456                         if (action_flags & MLX5_FLOW_ACTION_DECAP) {
10457                                 if (flow_dv_create_action_raw_encap
10458                                         (dev, actions, dev_flow, attr, error))
10459                                         return -rte_errno;
10460                                 dev_flow->dv.actions[actions_n++] =
10461                                         dev_flow->dv.encap_decap->action;
10462                         } else {
10463                                 /* Handle encap without preceding decap. */
10464                                 if (flow_dv_create_action_l2_encap
10465                                     (dev, actions, dev_flow, attr->transfer,
10466                                      error))
10467                                         return -rte_errno;
10468                                 dev_flow->dv.actions[actions_n++] =
10469                                         dev_flow->dv.encap_decap->action;
10470                         }
10471                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
10472                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
10473                                 sample_act->action_flags |=
10474                                                         MLX5_FLOW_ACTION_ENCAP;
10475                         break;
10476                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
10477                         while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
10478                                 ;
10479                         if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
10480                                 if (flow_dv_create_action_l2_decap
10481                                     (dev, dev_flow, attr->transfer, error))
10482                                         return -rte_errno;
10483                                 dev_flow->dv.actions[actions_n++] =
10484                                         dev_flow->dv.encap_decap->action;
10485                         }
10486                         /* If decap is followed by encap, handle it at encap. */
10487                         action_flags |= MLX5_FLOW_ACTION_DECAP;
10488                         break;
10489                 case RTE_FLOW_ACTION_TYPE_JUMP:
10490                         jump_group = ((const struct rte_flow_action_jump *)
10491                                                         action->conf)->group;
10492                         grp_info.std_tbl_fix = 0;
10493                         if (dev_flow->skip_scale &
10494                                 (1 << MLX5_SCALE_JUMP_FLOW_GROUP_BIT))
10495                                 grp_info.skip_scale = 1;
10496                         else
10497                                 grp_info.skip_scale = 0;
10498                         ret = mlx5_flow_group_to_table(dev, tunnel,
10499                                                        jump_group,
10500                                                        &table,
10501                                                        &grp_info, error);
10502                         if (ret)
10503                                 return ret;
10504                         tbl = flow_dv_tbl_resource_get(dev, table, attr->egress,
10505                                                        attr->transfer,
10506                                                        !!dev_flow->external,
10507                                                        tunnel, jump_group, 0,
10508                                                        error);
10509                         if (!tbl)
10510                                 return rte_flow_error_set
10511                                                 (error, errno,
10512                                                  RTE_FLOW_ERROR_TYPE_ACTION,
10513                                                  NULL,
10514                                                  "cannot create jump action.");
10515                         if (flow_dv_jump_tbl_resource_register
10516                             (dev, tbl, dev_flow, error)) {
10517                                 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
10518                                 return rte_flow_error_set
10519                                                 (error, errno,
10520                                                  RTE_FLOW_ERROR_TYPE_ACTION,
10521                                                  NULL,
10522                                                  "cannot create jump action.");
10523                         }
10524                         dev_flow->dv.actions[actions_n++] =
10525                                         dev_flow->dv.jump->action;
10526                         action_flags |= MLX5_FLOW_ACTION_JUMP;
10527                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_JUMP;
10528                         sample_act->action_flags |= MLX5_FLOW_ACTION_JUMP;
10529                         num_of_dest++;
10530                         break;
10531                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
10532                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
10533                         if (flow_dv_convert_action_modify_mac
10534                                         (mhdr_res, actions, error))
10535                                 return -rte_errno;
10536                         action_flags |= actions->type ==
10537                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
10538                                         MLX5_FLOW_ACTION_SET_MAC_SRC :
10539                                         MLX5_FLOW_ACTION_SET_MAC_DST;
10540                         break;
10541                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
10542                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
10543                         if (flow_dv_convert_action_modify_ipv4
10544                                         (mhdr_res, actions, error))
10545                                 return -rte_errno;
10546                         action_flags |= actions->type ==
10547                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
10548                                         MLX5_FLOW_ACTION_SET_IPV4_SRC :
10549                                         MLX5_FLOW_ACTION_SET_IPV4_DST;
10550                         break;
10551                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
10552                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
10553                         if (flow_dv_convert_action_modify_ipv6
10554                                         (mhdr_res, actions, error))
10555                                 return -rte_errno;
10556                         action_flags |= actions->type ==
10557                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
10558                                         MLX5_FLOW_ACTION_SET_IPV6_SRC :
10559                                         MLX5_FLOW_ACTION_SET_IPV6_DST;
10560                         break;
10561                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
10562                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
10563                         if (flow_dv_convert_action_modify_tp
10564                                         (mhdr_res, actions, items,
10565                                          &flow_attr, dev_flow, !!(action_flags &
10566                                          MLX5_FLOW_ACTION_DECAP), error))
10567                                 return -rte_errno;
10568                         action_flags |= actions->type ==
10569                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
10570                                         MLX5_FLOW_ACTION_SET_TP_SRC :
10571                                         MLX5_FLOW_ACTION_SET_TP_DST;
10572                         break;
10573                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
10574                         if (flow_dv_convert_action_modify_dec_ttl
10575                                         (mhdr_res, items, &flow_attr, dev_flow,
10576                                          !!(action_flags &
10577                                          MLX5_FLOW_ACTION_DECAP), error))
10578                                 return -rte_errno;
10579                         action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
10580                         break;
10581                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
10582                         if (flow_dv_convert_action_modify_ttl
10583                                         (mhdr_res, actions, items, &flow_attr,
10584                                          dev_flow, !!(action_flags &
10585                                          MLX5_FLOW_ACTION_DECAP), error))
10586                                 return -rte_errno;
10587                         action_flags |= MLX5_FLOW_ACTION_SET_TTL;
10588                         break;
10589                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
10590                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
10591                         if (flow_dv_convert_action_modify_tcp_seq
10592                                         (mhdr_res, actions, error))
10593                                 return -rte_errno;
10594                         action_flags |= actions->type ==
10595                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
10596                                         MLX5_FLOW_ACTION_INC_TCP_SEQ :
10597                                         MLX5_FLOW_ACTION_DEC_TCP_SEQ;
10598                         break;
10599
10600                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
10601                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
10602                         if (flow_dv_convert_action_modify_tcp_ack
10603                                         (mhdr_res, actions, error))
10604                                 return -rte_errno;
10605                         action_flags |= actions->type ==
10606                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
10607                                         MLX5_FLOW_ACTION_INC_TCP_ACK :
10608                                         MLX5_FLOW_ACTION_DEC_TCP_ACK;
10609                         break;
10610                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
10611                         if (flow_dv_convert_action_set_reg
10612                                         (mhdr_res, actions, error))
10613                                 return -rte_errno;
10614                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
10615                         break;
10616                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
10617                         if (flow_dv_convert_action_copy_mreg
10618                                         (dev, mhdr_res, actions, error))
10619                                 return -rte_errno;
10620                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
10621                         break;
10622                 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
10623                         action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
10624                         dev_flow->handle->fate_action =
10625                                         MLX5_FLOW_FATE_DEFAULT_MISS;
10626                         break;
10627                 case RTE_FLOW_ACTION_TYPE_METER:
10628                         mtr = actions->conf;
10629                         if (!flow->meter) {
10630                                 fm = mlx5_flow_meter_attach(priv, mtr->mtr_id,
10631                                                             attr, error);
10632                                 if (!fm)
10633                                         return rte_flow_error_set(error,
10634                                                 rte_errno,
10635                                                 RTE_FLOW_ERROR_TYPE_ACTION,
10636                                                 NULL,
10637                                                 "meter not found "
10638                                                 "or invalid parameters");
10639                                 flow->meter = fm->idx;
10640                         }
10641                         /* Set the meter action. */
10642                         if (!fm) {
10643                                 fm = mlx5_ipool_get(priv->sh->ipool
10644                                                 [MLX5_IPOOL_MTR], flow->meter);
10645                                 if (!fm)
10646                                         return rte_flow_error_set(error,
10647                                                 rte_errno,
10648                                                 RTE_FLOW_ERROR_TYPE_ACTION,
10649                                                 NULL,
10650                                                 "meter not found "
10651                                                 "or invalid parameters");
10652                         }
10653                         dev_flow->dv.actions[actions_n++] =
10654                                 fm->mfts->meter_action;
10655                         action_flags |= MLX5_FLOW_ACTION_METER;
10656                         break;
10657                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
10658                         if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
10659                                                               actions, error))
10660                                 return -rte_errno;
10661                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
10662                         break;
10663                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
10664                         if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
10665                                                               actions, error))
10666                                 return -rte_errno;
10667                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
10668                         break;
10669                 case RTE_FLOW_ACTION_TYPE_SAMPLE:
10670                         sample_act_pos = actions_n;
10671                         sample = (const struct rte_flow_action_sample *)
10672                                  action->conf;
10673                         actions_n++;
10674                         action_flags |= MLX5_FLOW_ACTION_SAMPLE;
10675                         /* put encap action into group if work with port id */
10676                         if ((action_flags & MLX5_FLOW_ACTION_ENCAP) &&
10677                             (action_flags & MLX5_FLOW_ACTION_PORT_ID))
10678                                 sample_act->action_flags |=
10679                                                         MLX5_FLOW_ACTION_ENCAP;
10680                         break;
10681                 case RTE_FLOW_ACTION_TYPE_END:
10682                         actions_end = true;
10683                         if (mhdr_res->actions_num) {
10684                                 /* create modify action if needed. */
10685                                 if (flow_dv_modify_hdr_resource_register
10686                                         (dev, mhdr_res, dev_flow, error))
10687                                         return -rte_errno;
10688                                 dev_flow->dv.actions[modify_action_position] =
10689                                         handle->dvh.modify_hdr->action;
10690                         }
10691                         if (action_flags & MLX5_FLOW_ACTION_COUNT) {
10692                                 /*
10693                                  * Create one count action, to be used
10694                                  * by all sub-flows.
10695                                  */
10696                                 if (!flow->counter) {
10697                                         flow->counter =
10698                                                 flow_dv_translate_create_counter
10699                                                         (dev, dev_flow, count,
10700                                                          age);
10701                                         if (!flow->counter)
10702                                                 return rte_flow_error_set
10703                                                 (error, rte_errno,
10704                                                  RTE_FLOW_ERROR_TYPE_ACTION,
10705                                                  NULL, "cannot create counter"
10706                                                  " object.");
10707                                 }
10708                                 dev_flow->dv.actions[actions_n] =
10709                                           (flow_dv_counter_get_by_idx(dev,
10710                                           flow->counter, NULL))->action;
10711                                 actions_n++;
10712                         }
10713                 default:
10714                         break;
10715                 }
10716                 if (mhdr_res->actions_num &&
10717                     modify_action_position == UINT32_MAX)
10718                         modify_action_position = actions_n++;
10719         }
10720         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
10721                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
10722                 int item_type = items->type;
10723
10724                 if (!mlx5_flow_os_item_supported(item_type))
10725                         return rte_flow_error_set(error, ENOTSUP,
10726                                                   RTE_FLOW_ERROR_TYPE_ITEM,
10727                                                   NULL, "item not supported");
10728                 switch (item_type) {
10729                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
10730                         flow_dv_translate_item_port_id
10731                                 (dev, match_mask, match_value, items, attr);
10732                         last_item = MLX5_FLOW_ITEM_PORT_ID;
10733                         break;
10734                 case RTE_FLOW_ITEM_TYPE_ETH:
10735                         flow_dv_translate_item_eth(match_mask, match_value,
10736                                                    items, tunnel,
10737                                                    dev_flow->dv.group);
10738                         matcher.priority = action_flags &
10739                                         MLX5_FLOW_ACTION_DEFAULT_MISS &&
10740                                         !dev_flow->external ?
10741                                         MLX5_PRIORITY_MAP_L3 :
10742                                         MLX5_PRIORITY_MAP_L2;
10743                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
10744                                              MLX5_FLOW_LAYER_OUTER_L2;
10745                         break;
10746                 case RTE_FLOW_ITEM_TYPE_VLAN:
10747                         flow_dv_translate_item_vlan(dev_flow,
10748                                                     match_mask, match_value,
10749                                                     items, tunnel,
10750                                                     dev_flow->dv.group);
10751                         matcher.priority = MLX5_PRIORITY_MAP_L2;
10752                         last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
10753                                               MLX5_FLOW_LAYER_INNER_VLAN) :
10754                                              (MLX5_FLOW_LAYER_OUTER_L2 |
10755                                               MLX5_FLOW_LAYER_OUTER_VLAN);
10756                         break;
10757                 case RTE_FLOW_ITEM_TYPE_IPV4:
10758                         mlx5_flow_tunnel_ip_check(items, next_protocol,
10759                                                   &item_flags, &tunnel);
10760                         flow_dv_translate_item_ipv4(match_mask, match_value,
10761                                                     items, tunnel,
10762                                                     dev_flow->dv.group);
10763                         matcher.priority = MLX5_PRIORITY_MAP_L3;
10764                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
10765                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
10766                         if (items->mask != NULL &&
10767                             ((const struct rte_flow_item_ipv4 *)
10768                              items->mask)->hdr.next_proto_id) {
10769                                 next_protocol =
10770                                         ((const struct rte_flow_item_ipv4 *)
10771                                          (items->spec))->hdr.next_proto_id;
10772                                 next_protocol &=
10773                                         ((const struct rte_flow_item_ipv4 *)
10774                                          (items->mask))->hdr.next_proto_id;
10775                         } else {
10776                                 /* Reset for inner layer. */
10777                                 next_protocol = 0xff;
10778                         }
10779                         break;
10780                 case RTE_FLOW_ITEM_TYPE_IPV6:
10781                         mlx5_flow_tunnel_ip_check(items, next_protocol,
10782                                                   &item_flags, &tunnel);
10783                         flow_dv_translate_item_ipv6(match_mask, match_value,
10784                                                     items, tunnel,
10785                                                     dev_flow->dv.group);
10786                         matcher.priority = MLX5_PRIORITY_MAP_L3;
10787                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
10788                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
10789                         if (items->mask != NULL &&
10790                             ((const struct rte_flow_item_ipv6 *)
10791                              items->mask)->hdr.proto) {
10792                                 next_protocol =
10793                                         ((const struct rte_flow_item_ipv6 *)
10794                                          items->spec)->hdr.proto;
10795                                 next_protocol &=
10796                                         ((const struct rte_flow_item_ipv6 *)
10797                                          items->mask)->hdr.proto;
10798                         } else {
10799                                 /* Reset for inner layer. */
10800                                 next_protocol = 0xff;
10801                         }
10802                         break;
10803                 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
10804                         flow_dv_translate_item_ipv6_frag_ext(match_mask,
10805                                                              match_value,
10806                                                              items, tunnel);
10807                         last_item = tunnel ?
10808                                         MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
10809                                         MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
10810                         if (items->mask != NULL &&
10811                             ((const struct rte_flow_item_ipv6_frag_ext *)
10812                              items->mask)->hdr.next_header) {
10813                                 next_protocol =
10814                                 ((const struct rte_flow_item_ipv6_frag_ext *)
10815                                  items->spec)->hdr.next_header;
10816                                 next_protocol &=
10817                                 ((const struct rte_flow_item_ipv6_frag_ext *)
10818                                  items->mask)->hdr.next_header;
10819                         } else {
10820                                 /* Reset for inner layer. */
10821                                 next_protocol = 0xff;
10822                         }
10823                         break;
10824                 case RTE_FLOW_ITEM_TYPE_TCP:
10825                         flow_dv_translate_item_tcp(match_mask, match_value,
10826                                                    items, tunnel);
10827                         matcher.priority = MLX5_PRIORITY_MAP_L4;
10828                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
10829                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
10830                         break;
10831                 case RTE_FLOW_ITEM_TYPE_UDP:
10832                         flow_dv_translate_item_udp(match_mask, match_value,
10833                                                    items, tunnel);
10834                         matcher.priority = MLX5_PRIORITY_MAP_L4;
10835                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
10836                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
10837                         break;
10838                 case RTE_FLOW_ITEM_TYPE_GRE:
10839                         flow_dv_translate_item_gre(match_mask, match_value,
10840                                                    items, tunnel);
10841                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10842                         last_item = MLX5_FLOW_LAYER_GRE;
10843                         break;
10844                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
10845                         flow_dv_translate_item_gre_key(match_mask,
10846                                                        match_value, items);
10847                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
10848                         break;
10849                 case RTE_FLOW_ITEM_TYPE_NVGRE:
10850                         flow_dv_translate_item_nvgre(match_mask, match_value,
10851                                                      items, tunnel);
10852                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10853                         last_item = MLX5_FLOW_LAYER_GRE;
10854                         break;
10855                 case RTE_FLOW_ITEM_TYPE_VXLAN:
10856                         flow_dv_translate_item_vxlan(match_mask, match_value,
10857                                                      items, tunnel);
10858                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10859                         last_item = MLX5_FLOW_LAYER_VXLAN;
10860                         break;
10861                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
10862                         flow_dv_translate_item_vxlan_gpe(match_mask,
10863                                                          match_value, items,
10864                                                          tunnel);
10865                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10866                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
10867                         break;
10868                 case RTE_FLOW_ITEM_TYPE_GENEVE:
10869                         flow_dv_translate_item_geneve(match_mask, match_value,
10870                                                       items, tunnel);
10871                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10872                         last_item = MLX5_FLOW_LAYER_GENEVE;
10873                         break;
10874                 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
10875                         ret = flow_dv_translate_item_geneve_opt(dev, match_mask,
10876                                                           match_value,
10877                                                           items, error);
10878                         if (ret)
10879                                 return rte_flow_error_set(error, -ret,
10880                                         RTE_FLOW_ERROR_TYPE_ITEM, NULL,
10881                                         "cannot create GENEVE TLV option");
10882                         flow->geneve_tlv_option = 1;
10883                         last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
10884                         break;
10885                 case RTE_FLOW_ITEM_TYPE_MPLS:
10886                         flow_dv_translate_item_mpls(match_mask, match_value,
10887                                                     items, last_item, tunnel);
10888                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10889                         last_item = MLX5_FLOW_LAYER_MPLS;
10890                         break;
10891                 case RTE_FLOW_ITEM_TYPE_MARK:
10892                         flow_dv_translate_item_mark(dev, match_mask,
10893                                                     match_value, items);
10894                         last_item = MLX5_FLOW_ITEM_MARK;
10895                         break;
10896                 case RTE_FLOW_ITEM_TYPE_META:
10897                         flow_dv_translate_item_meta(dev, match_mask,
10898                                                     match_value, attr, items);
10899                         last_item = MLX5_FLOW_ITEM_METADATA;
10900                         break;
10901                 case RTE_FLOW_ITEM_TYPE_ICMP:
10902                         flow_dv_translate_item_icmp(match_mask, match_value,
10903                                                     items, tunnel);
10904                         last_item = MLX5_FLOW_LAYER_ICMP;
10905                         break;
10906                 case RTE_FLOW_ITEM_TYPE_ICMP6:
10907                         flow_dv_translate_item_icmp6(match_mask, match_value,
10908                                                       items, tunnel);
10909                         last_item = MLX5_FLOW_LAYER_ICMP6;
10910                         break;
10911                 case RTE_FLOW_ITEM_TYPE_TAG:
10912                         flow_dv_translate_item_tag(dev, match_mask,
10913                                                    match_value, items);
10914                         last_item = MLX5_FLOW_ITEM_TAG;
10915                         break;
10916                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
10917                         flow_dv_translate_mlx5_item_tag(dev, match_mask,
10918                                                         match_value, items);
10919                         last_item = MLX5_FLOW_ITEM_TAG;
10920                         break;
10921                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
10922                         flow_dv_translate_item_tx_queue(dev, match_mask,
10923                                                         match_value,
10924                                                         items);
10925                         last_item = MLX5_FLOW_ITEM_TX_QUEUE;
10926                         break;
10927                 case RTE_FLOW_ITEM_TYPE_GTP:
10928                         flow_dv_translate_item_gtp(match_mask, match_value,
10929                                                    items, tunnel);
10930                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10931                         last_item = MLX5_FLOW_LAYER_GTP;
10932                         break;
10933                 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
10934                         ret = flow_dv_translate_item_gtp_psc(match_mask,
10935                                                           match_value,
10936                                                           items);
10937                         if (ret)
10938                                 return rte_flow_error_set(error, -ret,
10939                                         RTE_FLOW_ERROR_TYPE_ITEM, NULL,
10940                                         "cannot create GTP PSC item");
10941                         last_item = MLX5_FLOW_LAYER_GTP_PSC;
10942                         break;
10943                 case RTE_FLOW_ITEM_TYPE_ECPRI:
10944                         if (!mlx5_flex_parser_ecpri_exist(dev)) {
10945                                 /* Create it only the first time to be used. */
10946                                 ret = mlx5_flex_parser_ecpri_alloc(dev);
10947                                 if (ret)
10948                                         return rte_flow_error_set
10949                                                 (error, -ret,
10950                                                 RTE_FLOW_ERROR_TYPE_ITEM,
10951                                                 NULL,
10952                                                 "cannot create eCPRI parser");
10953                         }
10954                         /* Adjust the length matcher and device flow value. */
10955                         matcher.mask.size = MLX5_ST_SZ_BYTES(fte_match_param);
10956                         dev_flow->dv.value.size =
10957                                         MLX5_ST_SZ_BYTES(fte_match_param);
10958                         flow_dv_translate_item_ecpri(dev, match_mask,
10959                                                      match_value, items);
10960                         /* No other protocol should follow eCPRI layer. */
10961                         last_item = MLX5_FLOW_LAYER_ECPRI;
10962                         break;
10963                 default:
10964                         break;
10965                 }
10966                 item_flags |= last_item;
10967         }
10968         /*
10969          * When E-Switch mode is enabled, we have two cases where we need to
10970          * set the source port manually.
10971          * The first one, is in case of Nic steering rule, and the second is
10972          * E-Switch rule where no port_id item was found. In both cases
10973          * the source port is set according the current port in use.
10974          */
10975         if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
10976             (priv->representor || priv->master)) {
10977                 if (flow_dv_translate_item_port_id(dev, match_mask,
10978                                                    match_value, NULL, attr))
10979                         return -rte_errno;
10980         }
10981 #ifdef RTE_LIBRTE_MLX5_DEBUG
10982         MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
10983                                               dev_flow->dv.value.buf));
10984 #endif
10985         /*
10986          * Layers may be already initialized from prefix flow if this dev_flow
10987          * is the suffix flow.
10988          */
10989         handle->layers |= item_flags;
10990         if (action_flags & MLX5_FLOW_ACTION_RSS)
10991                 flow_dv_hashfields_set(dev_flow, rss_desc);
10992         /* If has RSS action in the sample action, the Sample/Mirror resource
10993          * should be registered after the hash filed be update.
10994          */
10995         if (action_flags & MLX5_FLOW_ACTION_SAMPLE) {
10996                 ret = flow_dv_translate_action_sample(dev,
10997                                                       sample,
10998                                                       dev_flow, attr,
10999                                                       &num_of_dest,
11000                                                       sample_actions,
11001                                                       &sample_res,
11002                                                       error);
11003                 if (ret < 0)
11004                         return ret;
11005                 ret = flow_dv_create_action_sample(dev,
11006                                                    dev_flow,
11007                                                    num_of_dest,
11008                                                    &sample_res,
11009                                                    &mdest_res,
11010                                                    sample_actions,
11011                                                    action_flags,
11012                                                    error);
11013                 if (ret < 0)
11014                         return rte_flow_error_set
11015                                                 (error, rte_errno,
11016                                                 RTE_FLOW_ERROR_TYPE_ACTION,
11017                                                 NULL,
11018                                                 "cannot create sample action");
11019                 if (num_of_dest > 1) {
11020                         dev_flow->dv.actions[sample_act_pos] =
11021                         dev_flow->dv.dest_array_res->action;
11022                 } else {
11023                         dev_flow->dv.actions[sample_act_pos] =
11024                         dev_flow->dv.sample_res->verbs_action;
11025                 }
11026         }
11027         /*
11028          * For multiple destination (sample action with ratio=1), the encap
11029          * action and port id action will be combined into group action.
11030          * So need remove the original these actions in the flow and only
11031          * use the sample action instead of.
11032          */
11033         if (num_of_dest > 1 &&
11034             (sample_act->dr_port_id_action || sample_act->dr_jump_action)) {
11035                 int i;
11036                 void *temp_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
11037
11038                 for (i = 0; i < actions_n; i++) {
11039                         if ((sample_act->dr_encap_action &&
11040                                 sample_act->dr_encap_action ==
11041                                 dev_flow->dv.actions[i]) ||
11042                                 (sample_act->dr_port_id_action &&
11043                                 sample_act->dr_port_id_action ==
11044                                 dev_flow->dv.actions[i]) ||
11045                                 (sample_act->dr_jump_action &&
11046                                 sample_act->dr_jump_action ==
11047                                 dev_flow->dv.actions[i]))
11048                                 continue;
11049                         temp_actions[tmp_actions_n++] = dev_flow->dv.actions[i];
11050                 }
11051                 memcpy((void *)dev_flow->dv.actions,
11052                                 (void *)temp_actions,
11053                                 tmp_actions_n * sizeof(void *));
11054                 actions_n = tmp_actions_n;
11055         }
11056         dev_flow->dv.actions_n = actions_n;
11057         dev_flow->act_flags = action_flags;
11058         /* Register matcher. */
11059         matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
11060                                     matcher.mask.size);
11061         matcher.priority = mlx5_get_matcher_priority(dev, attr,
11062                                         matcher.priority);
11063         /* reserved field no needs to be set to 0 here. */
11064         tbl_key.domain = attr->transfer;
11065         tbl_key.direction = attr->egress;
11066         tbl_key.table_id = dev_flow->dv.group;
11067         if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow,
11068                                      tunnel, attr->group, error))
11069                 return -rte_errno;
11070         return 0;
11071 }
11072
11073 /**
11074  * Set hash RX queue by hash fields (see enum ibv_rx_hash_fields)
11075  * and tunnel.
11076  *
11077  * @param[in, out] action
11078  *   Shred RSS action holding hash RX queue objects.
11079  * @param[in] hash_fields
11080  *   Defines combination of packet fields to participate in RX hash.
11081  * @param[in] tunnel
11082  *   Tunnel type
11083  * @param[in] hrxq_idx
11084  *   Hash RX queue index to set.
11085  *
11086  * @return
11087  *   0 on success, otherwise negative errno value.
11088  */
11089 static int
11090 __flow_dv_action_rss_hrxq_set(struct mlx5_shared_action_rss *action,
11091                               const uint64_t hash_fields,
11092                               const int tunnel,
11093                               uint32_t hrxq_idx)
11094 {
11095         uint32_t *hrxqs = tunnel ? action->hrxq : action->hrxq_tunnel;
11096
11097         switch (hash_fields & ~IBV_RX_HASH_INNER) {
11098         case MLX5_RSS_HASH_IPV4:
11099                 hrxqs[0] = hrxq_idx;
11100                 return 0;
11101         case MLX5_RSS_HASH_IPV4_TCP:
11102                 hrxqs[1] = hrxq_idx;
11103                 return 0;
11104         case MLX5_RSS_HASH_IPV4_UDP:
11105                 hrxqs[2] = hrxq_idx;
11106                 return 0;
11107         case MLX5_RSS_HASH_IPV6:
11108                 hrxqs[3] = hrxq_idx;
11109                 return 0;
11110         case MLX5_RSS_HASH_IPV6_TCP:
11111                 hrxqs[4] = hrxq_idx;
11112                 return 0;
11113         case MLX5_RSS_HASH_IPV6_UDP:
11114                 hrxqs[5] = hrxq_idx;
11115                 return 0;
11116         case MLX5_RSS_HASH_NONE:
11117                 hrxqs[6] = hrxq_idx;
11118                 return 0;
11119         default:
11120                 return -1;
11121         }
11122 }
11123
11124 /**
11125  * Look up for hash RX queue by hash fields (see enum ibv_rx_hash_fields)
11126  * and tunnel.
11127  *
11128  * @param[in] dev
11129  *   Pointer to the Ethernet device structure.
11130  * @param[in] idx
11131  *   Shared RSS action ID holding hash RX queue objects.
11132  * @param[in] hash_fields
11133  *   Defines combination of packet fields to participate in RX hash.
11134  * @param[in] tunnel
11135  *   Tunnel type
11136  *
11137  * @return
11138  *   Valid hash RX queue index, otherwise 0.
11139  */
11140 static uint32_t
11141 __flow_dv_action_rss_hrxq_lookup(struct rte_eth_dev *dev, uint32_t idx,
11142                                  const uint64_t hash_fields,
11143                                  const int tunnel)
11144 {
11145         struct mlx5_priv *priv = dev->data->dev_private;
11146         struct mlx5_shared_action_rss *shared_rss =
11147             mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
11148         const uint32_t *hrxqs = tunnel ? shared_rss->hrxq :
11149                                                         shared_rss->hrxq_tunnel;
11150
11151         switch (hash_fields & ~IBV_RX_HASH_INNER) {
11152         case MLX5_RSS_HASH_IPV4:
11153                 return hrxqs[0];
11154         case MLX5_RSS_HASH_IPV4_TCP:
11155                 return hrxqs[1];
11156         case MLX5_RSS_HASH_IPV4_UDP:
11157                 return hrxqs[2];
11158         case MLX5_RSS_HASH_IPV6:
11159                 return hrxqs[3];
11160         case MLX5_RSS_HASH_IPV6_TCP:
11161                 return hrxqs[4];
11162         case MLX5_RSS_HASH_IPV6_UDP:
11163                 return hrxqs[5];
11164         case MLX5_RSS_HASH_NONE:
11165                 return hrxqs[6];
11166         default:
11167                 return 0;
11168         }
11169 }
11170
11171 /**
11172  * Apply the flow to the NIC, lock free,
11173  * (mutex should be acquired by caller).
11174  *
11175  * @param[in] dev
11176  *   Pointer to the Ethernet device structure.
11177  * @param[in, out] flow
11178  *   Pointer to flow structure.
11179  * @param[out] error
11180  *   Pointer to error structure.
11181  *
11182  * @return
11183  *   0 on success, a negative errno value otherwise and rte_errno is set.
11184  */
11185 static int
11186 flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
11187               struct rte_flow_error *error)
11188 {
11189         struct mlx5_flow_dv_workspace *dv;
11190         struct mlx5_flow_handle *dh;
11191         struct mlx5_flow_handle_dv *dv_h;
11192         struct mlx5_flow *dev_flow;
11193         struct mlx5_priv *priv = dev->data->dev_private;
11194         uint32_t handle_idx;
11195         int n;
11196         int err;
11197         int idx;
11198         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
11199         struct mlx5_flow_rss_desc *rss_desc = &wks->rss_desc;
11200
11201         MLX5_ASSERT(wks);
11202         for (idx = wks->flow_idx - 1; idx >= 0; idx--) {
11203                 dev_flow = &wks->flows[idx];
11204                 dv = &dev_flow->dv;
11205                 dh = dev_flow->handle;
11206                 dv_h = &dh->dvh;
11207                 n = dv->actions_n;
11208                 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
11209                         if (dv->transfer) {
11210                                 dv->actions[n++] = priv->sh->esw_drop_action;
11211                         } else {
11212                                 MLX5_ASSERT(priv->drop_queue.hrxq);
11213                                 dv->actions[n++] =
11214                                                 priv->drop_queue.hrxq->action;
11215                         }
11216                 } else if ((dh->fate_action == MLX5_FLOW_FATE_QUEUE &&
11217                            !dv_h->rix_sample && !dv_h->rix_dest_array)) {
11218                         struct mlx5_hrxq *hrxq;
11219                         uint32_t hrxq_idx;
11220
11221                         hrxq = flow_dv_hrxq_prepare(dev, dev_flow, rss_desc,
11222                                                     &hrxq_idx);
11223                         if (!hrxq) {
11224                                 rte_flow_error_set
11225                                         (error, rte_errno,
11226                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11227                                          "cannot get hash queue");
11228                                 goto error;
11229                         }
11230                         dh->rix_hrxq = hrxq_idx;
11231                         dv->actions[n++] = hrxq->action;
11232                 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
11233                         struct mlx5_hrxq *hrxq = NULL;
11234                         uint32_t hrxq_idx;
11235
11236                         hrxq_idx = __flow_dv_action_rss_hrxq_lookup(dev,
11237                                                 rss_desc->shared_rss,
11238                                                 dev_flow->hash_fields,
11239                                                 !!(dh->layers &
11240                                                 MLX5_FLOW_LAYER_TUNNEL));
11241                         if (hrxq_idx)
11242                                 hrxq = mlx5_ipool_get
11243                                         (priv->sh->ipool[MLX5_IPOOL_HRXQ],
11244                                          hrxq_idx);
11245                         if (!hrxq) {
11246                                 rte_flow_error_set
11247                                         (error, rte_errno,
11248                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11249                                          "cannot get hash queue");
11250                                 goto error;
11251                         }
11252                         dh->rix_srss = rss_desc->shared_rss;
11253                         dv->actions[n++] = hrxq->action;
11254                 } else if (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS) {
11255                         if (!priv->sh->default_miss_action) {
11256                                 rte_flow_error_set
11257                                         (error, rte_errno,
11258                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11259                                          "default miss action not be created.");
11260                                 goto error;
11261                         }
11262                         dv->actions[n++] = priv->sh->default_miss_action;
11263                 }
11264                 err = mlx5_flow_os_create_flow(dv_h->matcher->matcher_object,
11265                                                (void *)&dv->value, n,
11266                                                dv->actions, &dh->drv_flow);
11267                 if (err) {
11268                         rte_flow_error_set(error, errno,
11269                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11270                                            NULL,
11271                                            "hardware refuses to create flow");
11272                         goto error;
11273                 }
11274                 if (priv->vmwa_context &&
11275                     dh->vf_vlan.tag && !dh->vf_vlan.created) {
11276                         /*
11277                          * The rule contains the VLAN pattern.
11278                          * For VF we are going to create VLAN
11279                          * interface to make hypervisor set correct
11280                          * e-Switch vport context.
11281                          */
11282                         mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
11283                 }
11284         }
11285         return 0;
11286 error:
11287         err = rte_errno; /* Save rte_errno before cleanup. */
11288         SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles,
11289                        handle_idx, dh, next) {
11290                 /* hrxq is union, don't clear it if the flag is not set. */
11291                 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE && dh->rix_hrxq) {
11292                         mlx5_hrxq_release(dev, dh->rix_hrxq);
11293                         dh->rix_hrxq = 0;
11294                 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
11295                         dh->rix_srss = 0;
11296                 }
11297                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
11298                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
11299         }
11300         rte_errno = err; /* Restore rte_errno. */
11301         return -rte_errno;
11302 }
11303
11304 void
11305 flow_dv_matcher_remove_cb(struct mlx5_cache_list *list __rte_unused,
11306                           struct mlx5_cache_entry *entry)
11307 {
11308         struct mlx5_flow_dv_matcher *cache = container_of(entry, typeof(*cache),
11309                                                           entry);
11310
11311         claim_zero(mlx5_flow_os_destroy_flow_matcher(cache->matcher_object));
11312         mlx5_free(cache);
11313 }
11314
11315 /**
11316  * Release the flow matcher.
11317  *
11318  * @param dev
11319  *   Pointer to Ethernet device.
11320  * @param port_id
11321  *   Index to port ID action resource.
11322  *
11323  * @return
11324  *   1 while a reference on it exists, 0 when freed.
11325  */
11326 static int
11327 flow_dv_matcher_release(struct rte_eth_dev *dev,
11328                         struct mlx5_flow_handle *handle)
11329 {
11330         struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
11331         struct mlx5_flow_tbl_data_entry *tbl = container_of(matcher->tbl,
11332                                                             typeof(*tbl), tbl);
11333         int ret;
11334
11335         MLX5_ASSERT(matcher->matcher_object);
11336         ret = mlx5_cache_unregister(&tbl->matchers, &matcher->entry);
11337         flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl->tbl);
11338         return ret;
11339 }
11340
11341 /**
11342  * Release encap_decap resource.
11343  *
11344  * @param list
11345  *   Pointer to the hash list.
11346  * @param entry
11347  *   Pointer to exist resource entry object.
11348  */
11349 void
11350 flow_dv_encap_decap_remove_cb(struct mlx5_hlist *list,
11351                               struct mlx5_hlist_entry *entry)
11352 {
11353         struct mlx5_dev_ctx_shared *sh = list->ctx;
11354         struct mlx5_flow_dv_encap_decap_resource *res =
11355                 container_of(entry, typeof(*res), entry);
11356
11357         claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
11358         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], res->idx);
11359 }
11360
11361 /**
11362  * Release an encap/decap resource.
11363  *
11364  * @param dev
11365  *   Pointer to Ethernet device.
11366  * @param encap_decap_idx
11367  *   Index of encap decap resource.
11368  *
11369  * @return
11370  *   1 while a reference on it exists, 0 when freed.
11371  */
11372 static int
11373 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
11374                                      uint32_t encap_decap_idx)
11375 {
11376         struct mlx5_priv *priv = dev->data->dev_private;
11377         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
11378
11379         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
11380                                         encap_decap_idx);
11381         if (!cache_resource)
11382                 return 0;
11383         MLX5_ASSERT(cache_resource->action);
11384         return mlx5_hlist_unregister(priv->sh->encaps_decaps,
11385                                      &cache_resource->entry);
11386 }
11387
11388 /**
11389  * Release an jump to table action resource.
11390  *
11391  * @param dev
11392  *   Pointer to Ethernet device.
11393  * @param rix_jump
11394  *   Index to the jump action resource.
11395  *
11396  * @return
11397  *   1 while a reference on it exists, 0 when freed.
11398  */
11399 static int
11400 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
11401                                   uint32_t rix_jump)
11402 {
11403         struct mlx5_priv *priv = dev->data->dev_private;
11404         struct mlx5_flow_tbl_data_entry *tbl_data;
11405
11406         tbl_data = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_JUMP],
11407                                   rix_jump);
11408         if (!tbl_data)
11409                 return 0;
11410         return flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl_data->tbl);
11411 }
11412
11413 void
11414 flow_dv_modify_remove_cb(struct mlx5_hlist *list __rte_unused,
11415                          struct mlx5_hlist_entry *entry)
11416 {
11417         struct mlx5_flow_dv_modify_hdr_resource *res =
11418                 container_of(entry, typeof(*res), entry);
11419
11420         claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
11421         mlx5_free(entry);
11422 }
11423
11424 /**
11425  * Release a modify-header resource.
11426  *
11427  * @param dev
11428  *   Pointer to Ethernet device.
11429  * @param handle
11430  *   Pointer to mlx5_flow_handle.
11431  *
11432  * @return
11433  *   1 while a reference on it exists, 0 when freed.
11434  */
11435 static int
11436 flow_dv_modify_hdr_resource_release(struct rte_eth_dev *dev,
11437                                     struct mlx5_flow_handle *handle)
11438 {
11439         struct mlx5_priv *priv = dev->data->dev_private;
11440         struct mlx5_flow_dv_modify_hdr_resource *entry = handle->dvh.modify_hdr;
11441
11442         MLX5_ASSERT(entry->action);
11443         return mlx5_hlist_unregister(priv->sh->modify_cmds, &entry->entry);
11444 }
11445
11446 void
11447 flow_dv_port_id_remove_cb(struct mlx5_cache_list *list,
11448                           struct mlx5_cache_entry *entry)
11449 {
11450         struct mlx5_dev_ctx_shared *sh = list->ctx;
11451         struct mlx5_flow_dv_port_id_action_resource *cache =
11452                         container_of(entry, typeof(*cache), entry);
11453
11454         claim_zero(mlx5_flow_os_destroy_flow_action(cache->action));
11455         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], cache->idx);
11456 }
11457
11458 /**
11459  * Release port ID action resource.
11460  *
11461  * @param dev
11462  *   Pointer to Ethernet device.
11463  * @param handle
11464  *   Pointer to mlx5_flow_handle.
11465  *
11466  * @return
11467  *   1 while a reference on it exists, 0 when freed.
11468  */
11469 static int
11470 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
11471                                         uint32_t port_id)
11472 {
11473         struct mlx5_priv *priv = dev->data->dev_private;
11474         struct mlx5_flow_dv_port_id_action_resource *cache;
11475
11476         cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID], port_id);
11477         if (!cache)
11478                 return 0;
11479         MLX5_ASSERT(cache->action);
11480         return mlx5_cache_unregister(&priv->sh->port_id_action_list,
11481                                      &cache->entry);
11482 }
11483
11484 /**
11485  * Release shared RSS action resource.
11486  *
11487  * @param dev
11488  *   Pointer to Ethernet device.
11489  * @param srss
11490  *   Shared RSS action index.
11491  */
11492 static void
11493 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss)
11494 {
11495         struct mlx5_priv *priv = dev->data->dev_private;
11496         struct mlx5_shared_action_rss *shared_rss;
11497
11498         shared_rss = mlx5_ipool_get
11499                         (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], srss);
11500         __atomic_sub_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
11501 }
11502
11503 void
11504 flow_dv_push_vlan_remove_cb(struct mlx5_cache_list *list,
11505                             struct mlx5_cache_entry *entry)
11506 {
11507         struct mlx5_dev_ctx_shared *sh = list->ctx;
11508         struct mlx5_flow_dv_push_vlan_action_resource *cache =
11509                         container_of(entry, typeof(*cache), entry);
11510
11511         claim_zero(mlx5_flow_os_destroy_flow_action(cache->action));
11512         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], cache->idx);
11513 }
11514
11515 /**
11516  * Release push vlan action resource.
11517  *
11518  * @param dev
11519  *   Pointer to Ethernet device.
11520  * @param handle
11521  *   Pointer to mlx5_flow_handle.
11522  *
11523  * @return
11524  *   1 while a reference on it exists, 0 when freed.
11525  */
11526 static int
11527 flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,
11528                                           struct mlx5_flow_handle *handle)
11529 {
11530         struct mlx5_priv *priv = dev->data->dev_private;
11531         struct mlx5_flow_dv_push_vlan_action_resource *cache;
11532         uint32_t idx = handle->dvh.rix_push_vlan;
11533
11534         cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
11535         if (!cache)
11536                 return 0;
11537         MLX5_ASSERT(cache->action);
11538         return mlx5_cache_unregister(&priv->sh->push_vlan_action_list,
11539                                      &cache->entry);
11540 }
11541
11542 /**
11543  * Release the fate resource.
11544  *
11545  * @param dev
11546  *   Pointer to Ethernet device.
11547  * @param handle
11548  *   Pointer to mlx5_flow_handle.
11549  */
11550 static void
11551 flow_dv_fate_resource_release(struct rte_eth_dev *dev,
11552                                struct mlx5_flow_handle *handle)
11553 {
11554         if (!handle->rix_fate)
11555                 return;
11556         switch (handle->fate_action) {
11557         case MLX5_FLOW_FATE_QUEUE:
11558                 mlx5_hrxq_release(dev, handle->rix_hrxq);
11559                 break;
11560         case MLX5_FLOW_FATE_JUMP:
11561                 flow_dv_jump_tbl_resource_release(dev, handle->rix_jump);
11562                 break;
11563         case MLX5_FLOW_FATE_PORT_ID:
11564                 flow_dv_port_id_action_resource_release(dev,
11565                                 handle->rix_port_id_action);
11566                 break;
11567         default:
11568                 DRV_LOG(DEBUG, "Incorrect fate action:%d", handle->fate_action);
11569                 break;
11570         }
11571         handle->rix_fate = 0;
11572 }
11573
11574 void
11575 flow_dv_sample_remove_cb(struct mlx5_cache_list *list __rte_unused,
11576                          struct mlx5_cache_entry *entry)
11577 {
11578         struct mlx5_flow_dv_sample_resource *cache_resource =
11579                         container_of(entry, typeof(*cache_resource), entry);
11580         struct rte_eth_dev *dev = cache_resource->dev;
11581         struct mlx5_priv *priv = dev->data->dev_private;
11582
11583         if (cache_resource->verbs_action)
11584                 claim_zero(mlx5_flow_os_destroy_flow_action
11585                                 (cache_resource->verbs_action));
11586         if (cache_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB) {
11587                 if (cache_resource->default_miss)
11588                         claim_zero(mlx5_flow_os_destroy_flow_action
11589                           (cache_resource->default_miss));
11590         }
11591         if (cache_resource->normal_path_tbl)
11592                 flow_dv_tbl_resource_release(MLX5_SH(dev),
11593                         cache_resource->normal_path_tbl);
11594         flow_dv_sample_sub_actions_release(dev,
11595                                 &cache_resource->sample_idx);
11596         mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
11597                         cache_resource->idx);
11598         DRV_LOG(DEBUG, "sample resource %p: removed",
11599                 (void *)cache_resource);
11600 }
11601
11602 /**
11603  * Release an sample resource.
11604  *
11605  * @param dev
11606  *   Pointer to Ethernet device.
11607  * @param handle
11608  *   Pointer to mlx5_flow_handle.
11609  *
11610  * @return
11611  *   1 while a reference on it exists, 0 when freed.
11612  */
11613 static int
11614 flow_dv_sample_resource_release(struct rte_eth_dev *dev,
11615                                      struct mlx5_flow_handle *handle)
11616 {
11617         struct mlx5_priv *priv = dev->data->dev_private;
11618         struct mlx5_flow_dv_sample_resource *cache_resource;
11619
11620         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
11621                          handle->dvh.rix_sample);
11622         if (!cache_resource)
11623                 return 0;
11624         MLX5_ASSERT(cache_resource->verbs_action);
11625         return mlx5_cache_unregister(&priv->sh->sample_action_list,
11626                                      &cache_resource->entry);
11627 }
11628
11629 void
11630 flow_dv_dest_array_remove_cb(struct mlx5_cache_list *list __rte_unused,
11631                              struct mlx5_cache_entry *entry)
11632 {
11633         struct mlx5_flow_dv_dest_array_resource *cache_resource =
11634                         container_of(entry, typeof(*cache_resource), entry);
11635         struct rte_eth_dev *dev = cache_resource->dev;
11636         struct mlx5_priv *priv = dev->data->dev_private;
11637         uint32_t i = 0;
11638
11639         MLX5_ASSERT(cache_resource->action);
11640         if (cache_resource->action)
11641                 claim_zero(mlx5_flow_os_destroy_flow_action
11642                                         (cache_resource->action));
11643         for (; i < cache_resource->num_of_dest; i++)
11644                 flow_dv_sample_sub_actions_release(dev,
11645                                 &cache_resource->sample_idx[i]);
11646         mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
11647                         cache_resource->idx);
11648         DRV_LOG(DEBUG, "destination array resource %p: removed",
11649                 (void *)cache_resource);
11650 }
11651
11652 /**
11653  * Release an destination array resource.
11654  *
11655  * @param dev
11656  *   Pointer to Ethernet device.
11657  * @param handle
11658  *   Pointer to mlx5_flow_handle.
11659  *
11660  * @return
11661  *   1 while a reference on it exists, 0 when freed.
11662  */
11663 static int
11664 flow_dv_dest_array_resource_release(struct rte_eth_dev *dev,
11665                                     struct mlx5_flow_handle *handle)
11666 {
11667         struct mlx5_priv *priv = dev->data->dev_private;
11668         struct mlx5_flow_dv_dest_array_resource *cache;
11669
11670         cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
11671                                handle->dvh.rix_dest_array);
11672         if (!cache)
11673                 return 0;
11674         MLX5_ASSERT(cache->action);
11675         return mlx5_cache_unregister(&priv->sh->dest_array_list,
11676                                      &cache->entry);
11677 }
11678
11679 static void
11680 flow_dv_geneve_tlv_option_resource_release(struct rte_eth_dev *dev)
11681 {
11682         struct mlx5_priv *priv = dev->data->dev_private;
11683         struct mlx5_dev_ctx_shared *sh = priv->sh;
11684         struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
11685                                 sh->geneve_tlv_option_resource;
11686         rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
11687         if (geneve_opt_resource) {
11688                 if (!(__atomic_sub_fetch(&geneve_opt_resource->refcnt, 1,
11689                                          __ATOMIC_RELAXED))) {
11690                         claim_zero(mlx5_devx_cmd_destroy
11691                                         (geneve_opt_resource->obj));
11692                         mlx5_free(sh->geneve_tlv_option_resource);
11693                         sh->geneve_tlv_option_resource = NULL;
11694                 }
11695         }
11696         rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
11697 }
11698
11699 /**
11700  * Remove the flow from the NIC but keeps it in memory.
11701  * Lock free, (mutex should be acquired by caller).
11702  *
11703  * @param[in] dev
11704  *   Pointer to Ethernet device.
11705  * @param[in, out] flow
11706  *   Pointer to flow structure.
11707  */
11708 static void
11709 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
11710 {
11711         struct mlx5_flow_handle *dh;
11712         uint32_t handle_idx;
11713         struct mlx5_priv *priv = dev->data->dev_private;
11714
11715         if (!flow)
11716                 return;
11717         handle_idx = flow->dev_handles;
11718         while (handle_idx) {
11719                 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
11720                                     handle_idx);
11721                 if (!dh)
11722                         return;
11723                 if (dh->drv_flow) {
11724                         claim_zero(mlx5_flow_os_destroy_flow(dh->drv_flow));
11725                         dh->drv_flow = NULL;
11726                 }
11727                 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE)
11728                         flow_dv_fate_resource_release(dev, dh);
11729                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
11730                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
11731                 handle_idx = dh->next.next;
11732         }
11733 }
11734
11735 /**
11736  * Remove the flow from the NIC and the memory.
11737  * Lock free, (mutex should be acquired by caller).
11738  *
11739  * @param[in] dev
11740  *   Pointer to the Ethernet device structure.
11741  * @param[in, out] flow
11742  *   Pointer to flow structure.
11743  */
11744 static void
11745 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
11746 {
11747         struct mlx5_flow_handle *dev_handle;
11748         struct mlx5_priv *priv = dev->data->dev_private;
11749         uint32_t srss = 0;
11750
11751         if (!flow)
11752                 return;
11753         flow_dv_remove(dev, flow);
11754         if (flow->counter) {
11755                 flow_dv_counter_free(dev, flow->counter);
11756                 flow->counter = 0;
11757         }
11758         if (flow->meter) {
11759                 struct mlx5_flow_meter *fm;
11760
11761                 fm = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MTR],
11762                                     flow->meter);
11763                 if (fm)
11764                         mlx5_flow_meter_detach(fm);
11765                 flow->meter = 0;
11766         }
11767         if (flow->age)
11768                 flow_dv_aso_age_release(dev, flow->age);
11769         if (flow->geneve_tlv_option) {
11770                 flow_dv_geneve_tlv_option_resource_release(dev);
11771                 flow->geneve_tlv_option = 0;
11772         }
11773         while (flow->dev_handles) {
11774                 uint32_t tmp_idx = flow->dev_handles;
11775
11776                 dev_handle = mlx5_ipool_get(priv->sh->ipool
11777                                             [MLX5_IPOOL_MLX5_FLOW], tmp_idx);
11778                 if (!dev_handle)
11779                         return;
11780                 flow->dev_handles = dev_handle->next.next;
11781                 if (dev_handle->dvh.matcher)
11782                         flow_dv_matcher_release(dev, dev_handle);
11783                 if (dev_handle->dvh.rix_sample)
11784                         flow_dv_sample_resource_release(dev, dev_handle);
11785                 if (dev_handle->dvh.rix_dest_array)
11786                         flow_dv_dest_array_resource_release(dev, dev_handle);
11787                 if (dev_handle->dvh.rix_encap_decap)
11788                         flow_dv_encap_decap_resource_release(dev,
11789                                 dev_handle->dvh.rix_encap_decap);
11790                 if (dev_handle->dvh.modify_hdr)
11791                         flow_dv_modify_hdr_resource_release(dev, dev_handle);
11792                 if (dev_handle->dvh.rix_push_vlan)
11793                         flow_dv_push_vlan_action_resource_release(dev,
11794                                                                   dev_handle);
11795                 if (dev_handle->dvh.rix_tag)
11796                         flow_dv_tag_release(dev,
11797                                             dev_handle->dvh.rix_tag);
11798                 if (dev_handle->fate_action != MLX5_FLOW_FATE_SHARED_RSS)
11799                         flow_dv_fate_resource_release(dev, dev_handle);
11800                 else if (!srss)
11801                         srss = dev_handle->rix_srss;
11802                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
11803                            tmp_idx);
11804         }
11805         if (srss)
11806                 flow_dv_shared_rss_action_release(dev, srss);
11807 }
11808
11809 /**
11810  * Release array of hash RX queue objects.
11811  * Helper function.
11812  *
11813  * @param[in] dev
11814  *   Pointer to the Ethernet device structure.
11815  * @param[in, out] hrxqs
11816  *   Array of hash RX queue objects.
11817  *
11818  * @return
11819  *   Total number of references to hash RX queue objects in *hrxqs* array
11820  *   after this operation.
11821  */
11822 static int
11823 __flow_dv_hrxqs_release(struct rte_eth_dev *dev,
11824                         uint32_t (*hrxqs)[MLX5_RSS_HASH_FIELDS_LEN])
11825 {
11826         size_t i;
11827         int remaining = 0;
11828
11829         for (i = 0; i < RTE_DIM(*hrxqs); i++) {
11830                 int ret = mlx5_hrxq_release(dev, (*hrxqs)[i]);
11831
11832                 if (!ret)
11833                         (*hrxqs)[i] = 0;
11834                 remaining += ret;
11835         }
11836         return remaining;
11837 }
11838
11839 /**
11840  * Release all hash RX queue objects representing shared RSS action.
11841  *
11842  * @param[in] dev
11843  *   Pointer to the Ethernet device structure.
11844  * @param[in, out] action
11845  *   Shared RSS action to remove hash RX queue objects from.
11846  *
11847  * @return
11848  *   Total number of references to hash RX queue objects stored in *action*
11849  *   after this operation.
11850  *   Expected to be 0 if no external references held.
11851  */
11852 static int
11853 __flow_dv_action_rss_hrxqs_release(struct rte_eth_dev *dev,
11854                                  struct mlx5_shared_action_rss *action)
11855 {
11856         return __flow_dv_hrxqs_release(dev, &action->hrxq) +
11857                 __flow_dv_hrxqs_release(dev, &action->hrxq_tunnel);
11858 }
11859
11860 /**
11861  * Setup shared RSS action.
11862  * Prepare set of hash RX queue objects sufficient to handle all valid
11863  * hash_fields combinations (see enum ibv_rx_hash_fields).
11864  *
11865  * @param[in] dev
11866  *   Pointer to the Ethernet device structure.
11867  * @param[in] action_idx
11868  *   Shared RSS action ipool index.
11869  * @param[in, out] action
11870  *   Partially initialized shared RSS action.
11871  * @param[out] error
11872  *   Perform verbose error reporting if not NULL. Initialized in case of
11873  *   error only.
11874  *
11875  * @return
11876  *   0 on success, otherwise negative errno value.
11877  */
11878 static int
11879 __flow_dv_action_rss_setup(struct rte_eth_dev *dev,
11880                            uint32_t action_idx,
11881                            struct mlx5_shared_action_rss *action,
11882                            struct rte_flow_error *error)
11883 {
11884         struct mlx5_flow_rss_desc rss_desc = { 0 };
11885         size_t i;
11886         int err;
11887
11888         if (mlx5_ind_table_obj_setup(dev, action->ind_tbl)) {
11889                 return rte_flow_error_set(error, rte_errno,
11890                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11891                                           "cannot setup indirection table");
11892         }
11893         memcpy(rss_desc.key, action->origin.key, MLX5_RSS_HASH_KEY_LEN);
11894         rss_desc.key_len = MLX5_RSS_HASH_KEY_LEN;
11895         rss_desc.const_q = action->origin.queue;
11896         rss_desc.queue_num = action->origin.queue_num;
11897         /* Set non-zero value to indicate a shared RSS. */
11898         rss_desc.shared_rss = action_idx;
11899         rss_desc.ind_tbl = action->ind_tbl;
11900         for (i = 0; i < MLX5_RSS_HASH_FIELDS_LEN; i++) {
11901                 uint32_t hrxq_idx;
11902                 uint64_t hash_fields = mlx5_rss_hash_fields[i];
11903                 int tunnel;
11904
11905                 for (tunnel = 0; tunnel < 2; tunnel++) {
11906                         rss_desc.tunnel = tunnel;
11907                         rss_desc.hash_fields = hash_fields;
11908                         hrxq_idx = mlx5_hrxq_get(dev, &rss_desc);
11909                         if (!hrxq_idx) {
11910                                 rte_flow_error_set
11911                                         (error, rte_errno,
11912                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11913                                          "cannot get hash queue");
11914                                 goto error_hrxq_new;
11915                         }
11916                         err = __flow_dv_action_rss_hrxq_set
11917                                 (action, hash_fields, tunnel, hrxq_idx);
11918                         MLX5_ASSERT(!err);
11919                 }
11920         }
11921         return 0;
11922 error_hrxq_new:
11923         err = rte_errno;
11924         __flow_dv_action_rss_hrxqs_release(dev, action);
11925         if (!mlx5_ind_table_obj_release(dev, action->ind_tbl, true))
11926                 action->ind_tbl = NULL;
11927         rte_errno = err;
11928         return -rte_errno;
11929 }
11930
11931 /**
11932  * Create shared RSS action.
11933  *
11934  * @param[in] dev
11935  *   Pointer to the Ethernet device structure.
11936  * @param[in] conf
11937  *   Shared action configuration.
11938  * @param[in] rss
11939  *   RSS action specification used to create shared action.
11940  * @param[out] error
11941  *   Perform verbose error reporting if not NULL. Initialized in case of
11942  *   error only.
11943  *
11944  * @return
11945  *   A valid shared action ID in case of success, 0 otherwise and
11946  *   rte_errno is set.
11947  */
11948 static uint32_t
11949 __flow_dv_action_rss_create(struct rte_eth_dev *dev,
11950                             const struct rte_flow_shared_action_conf *conf,
11951                             const struct rte_flow_action_rss *rss,
11952                             struct rte_flow_error *error)
11953 {
11954         struct mlx5_priv *priv = dev->data->dev_private;
11955         struct mlx5_shared_action_rss *shared_action = NULL;
11956         void *queue = NULL;
11957         struct rte_flow_action_rss *origin;
11958         const uint8_t *rss_key;
11959         uint32_t queue_size = rss->queue_num * sizeof(uint16_t);
11960         uint32_t idx;
11961
11962         RTE_SET_USED(conf);
11963         queue = mlx5_malloc(0, RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
11964                             0, SOCKET_ID_ANY);
11965         shared_action = mlx5_ipool_zmalloc
11966                          (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], &idx);
11967         if (!shared_action || !queue) {
11968                 rte_flow_error_set(error, ENOMEM,
11969                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11970                                    "cannot allocate resource memory");
11971                 goto error_rss_init;
11972         }
11973         if (idx > (1u << MLX5_SHARED_ACTION_TYPE_OFFSET)) {
11974                 rte_flow_error_set(error, E2BIG,
11975                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11976                                    "rss action number out of range");
11977                 goto error_rss_init;
11978         }
11979         shared_action->ind_tbl = mlx5_malloc(MLX5_MEM_ZERO,
11980                                              sizeof(*shared_action->ind_tbl),
11981                                              0, SOCKET_ID_ANY);
11982         if (!shared_action->ind_tbl) {
11983                 rte_flow_error_set(error, ENOMEM,
11984                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11985                                    "cannot allocate resource memory");
11986                 goto error_rss_init;
11987         }
11988         memcpy(queue, rss->queue, queue_size);
11989         shared_action->ind_tbl->queues = queue;
11990         shared_action->ind_tbl->queues_n = rss->queue_num;
11991         origin = &shared_action->origin;
11992         origin->func = rss->func;
11993         origin->level = rss->level;
11994         /* RSS type 0 indicates default RSS type (ETH_RSS_IP). */
11995         origin->types = !rss->types ? ETH_RSS_IP : rss->types;
11996         /* NULL RSS key indicates default RSS key. */
11997         rss_key = !rss->key ? rss_hash_default_key : rss->key;
11998         memcpy(shared_action->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
11999         origin->key = &shared_action->key[0];
12000         origin->key_len = MLX5_RSS_HASH_KEY_LEN;
12001         origin->queue = queue;
12002         origin->queue_num = rss->queue_num;
12003         if (__flow_dv_action_rss_setup(dev, idx, shared_action, error))
12004                 goto error_rss_init;
12005         rte_spinlock_init(&shared_action->action_rss_sl);
12006         __atomic_add_fetch(&shared_action->refcnt, 1, __ATOMIC_RELAXED);
12007         rte_spinlock_lock(&priv->shared_act_sl);
12008         ILIST_INSERT(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
12009                      &priv->rss_shared_actions, idx, shared_action, next);
12010         rte_spinlock_unlock(&priv->shared_act_sl);
12011         return idx;
12012 error_rss_init:
12013         if (shared_action) {
12014                 if (shared_action->ind_tbl)
12015                         mlx5_free(shared_action->ind_tbl);
12016                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
12017                                 idx);
12018         }
12019         if (queue)
12020                 mlx5_free(queue);
12021         return 0;
12022 }
12023
12024 /**
12025  * Destroy the shared RSS action.
12026  * Release related hash RX queue objects.
12027  *
12028  * @param[in] dev
12029  *   Pointer to the Ethernet device structure.
12030  * @param[in] idx
12031  *   The shared RSS action object ID to be removed.
12032  * @param[out] error
12033  *   Perform verbose error reporting if not NULL. Initialized in case of
12034  *   error only.
12035  *
12036  * @return
12037  *   0 on success, otherwise negative errno value.
12038  */
12039 static int
12040 __flow_dv_action_rss_release(struct rte_eth_dev *dev, uint32_t idx,
12041                              struct rte_flow_error *error)
12042 {
12043         struct mlx5_priv *priv = dev->data->dev_private;
12044         struct mlx5_shared_action_rss *shared_rss =
12045             mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
12046         uint32_t old_refcnt = 1;
12047         int remaining;
12048         uint16_t *queue = NULL;
12049
12050         if (!shared_rss)
12051                 return rte_flow_error_set(error, EINVAL,
12052                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12053                                           "invalid shared action");
12054         remaining = __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
12055         if (remaining)
12056                 return rte_flow_error_set(error, EBUSY,
12057                                           RTE_FLOW_ERROR_TYPE_ACTION,
12058                                           NULL,
12059                                           "shared rss hrxq has references");
12060         queue = shared_rss->ind_tbl->queues;
12061         remaining = mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl, true);
12062         if (remaining)
12063                 return rte_flow_error_set(error, EBUSY,
12064                                           RTE_FLOW_ERROR_TYPE_ACTION,
12065                                           NULL,
12066                                           "shared rss indirection table has"
12067                                           " references");
12068         if (!__atomic_compare_exchange_n(&shared_rss->refcnt, &old_refcnt,
12069                                          0, 0, __ATOMIC_ACQUIRE,
12070                                          __ATOMIC_RELAXED))
12071                 return rte_flow_error_set(error, EBUSY,
12072                                           RTE_FLOW_ERROR_TYPE_ACTION,
12073                                           NULL,
12074                                           "shared rss has references");
12075         mlx5_free(queue);
12076         rte_spinlock_lock(&priv->shared_act_sl);
12077         ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
12078                      &priv->rss_shared_actions, idx, shared_rss, next);
12079         rte_spinlock_unlock(&priv->shared_act_sl);
12080         mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
12081                         idx);
12082         return 0;
12083 }
12084
12085 /**
12086  * Create shared action, lock free,
12087  * (mutex should be acquired by caller).
12088  * Dispatcher for action type specific call.
12089  *
12090  * @param[in] dev
12091  *   Pointer to the Ethernet device structure.
12092  * @param[in] conf
12093  *   Shared action configuration.
12094  * @param[in] action
12095  *   Action specification used to create shared action.
12096  * @param[out] error
12097  *   Perform verbose error reporting if not NULL. Initialized in case of
12098  *   error only.
12099  *
12100  * @return
12101  *   A valid shared action handle in case of success, NULL otherwise and
12102  *   rte_errno is set.
12103  */
12104 static struct rte_flow_shared_action *
12105 flow_dv_action_create(struct rte_eth_dev *dev,
12106                       const struct rte_flow_shared_action_conf *conf,
12107                       const struct rte_flow_action *action,
12108                       struct rte_flow_error *err)
12109 {
12110         uint32_t idx = 0;
12111         uint32_t ret = 0;
12112
12113         switch (action->type) {
12114         case RTE_FLOW_ACTION_TYPE_RSS:
12115                 ret = __flow_dv_action_rss_create(dev, conf, action->conf, err);
12116                 idx = (MLX5_SHARED_ACTION_TYPE_RSS <<
12117                        MLX5_SHARED_ACTION_TYPE_OFFSET) | ret;
12118                 break;
12119         case RTE_FLOW_ACTION_TYPE_AGE:
12120                 ret = flow_dv_translate_create_aso_age(dev, action->conf, err);
12121                 idx = (MLX5_SHARED_ACTION_TYPE_AGE <<
12122                        MLX5_SHARED_ACTION_TYPE_OFFSET) | ret;
12123                 if (ret) {
12124                         struct mlx5_aso_age_action *aso_age =
12125                                               flow_aso_age_get_by_idx(dev, ret);
12126
12127                         if (!aso_age->age_params.context)
12128                                 aso_age->age_params.context =
12129                                                          (void *)(uintptr_t)idx;
12130                 }
12131                 break;
12132         default:
12133                 rte_flow_error_set(err, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION,
12134                                    NULL, "action type not supported");
12135                 break;
12136         }
12137         return ret ? (struct rte_flow_shared_action *)(uintptr_t)idx : NULL;
12138 }
12139
12140 /**
12141  * Destroy the shared action.
12142  * Release action related resources on the NIC and the memory.
12143  * Lock free, (mutex should be acquired by caller).
12144  * Dispatcher for action type specific call.
12145  *
12146  * @param[in] dev
12147  *   Pointer to the Ethernet device structure.
12148  * @param[in] action
12149  *   The shared action object to be removed.
12150  * @param[out] error
12151  *   Perform verbose error reporting if not NULL. Initialized in case of
12152  *   error only.
12153  *
12154  * @return
12155  *   0 on success, otherwise negative errno value.
12156  */
12157 static int
12158 flow_dv_action_destroy(struct rte_eth_dev *dev,
12159                        struct rte_flow_shared_action *action,
12160                        struct rte_flow_error *error)
12161 {
12162         uint32_t act_idx = (uint32_t)(uintptr_t)action;
12163         uint32_t type = act_idx >> MLX5_SHARED_ACTION_TYPE_OFFSET;
12164         uint32_t idx = act_idx & ((1u << MLX5_SHARED_ACTION_TYPE_OFFSET) - 1);
12165         int ret;
12166
12167         switch (type) {
12168         case MLX5_SHARED_ACTION_TYPE_RSS:
12169                 return __flow_dv_action_rss_release(dev, idx, error);
12170         case MLX5_SHARED_ACTION_TYPE_AGE:
12171                 ret = flow_dv_aso_age_release(dev, idx);
12172                 if (ret)
12173                         /*
12174                          * In this case, the last flow has a reference will
12175                          * actually release the age action.
12176                          */
12177                         DRV_LOG(DEBUG, "Shared age action %" PRIu32 " was"
12178                                 " released with references %d.", idx, ret);
12179                 return 0;
12180         default:
12181                 return rte_flow_error_set(error, ENOTSUP,
12182                                           RTE_FLOW_ERROR_TYPE_ACTION,
12183                                           NULL,
12184                                           "action type not supported");
12185         }
12186 }
12187
12188 /**
12189  * Updates in place shared RSS action configuration.
12190  *
12191  * @param[in] dev
12192  *   Pointer to the Ethernet device structure.
12193  * @param[in] idx
12194  *   The shared RSS action object ID to be updated.
12195  * @param[in] action_conf
12196  *   RSS action specification used to modify *shared_rss*.
12197  * @param[out] error
12198  *   Perform verbose error reporting if not NULL. Initialized in case of
12199  *   error only.
12200  *
12201  * @return
12202  *   0 on success, otherwise negative errno value.
12203  * @note: currently only support update of RSS queues.
12204  */
12205 static int
12206 __flow_dv_action_rss_update(struct rte_eth_dev *dev, uint32_t idx,
12207                             const struct rte_flow_action_rss *action_conf,
12208                             struct rte_flow_error *error)
12209 {
12210         struct mlx5_priv *priv = dev->data->dev_private;
12211         struct mlx5_shared_action_rss *shared_rss =
12212             mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
12213         int ret = 0;
12214         void *queue = NULL;
12215         uint16_t *queue_old = NULL;
12216         uint32_t queue_size = action_conf->queue_num * sizeof(uint16_t);
12217
12218         if (!shared_rss)
12219                 return rte_flow_error_set(error, EINVAL,
12220                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12221                                           "invalid shared action to update");
12222         queue = mlx5_malloc(MLX5_MEM_ZERO,
12223                             RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
12224                             0, SOCKET_ID_ANY);
12225         if (!queue)
12226                 return rte_flow_error_set(error, ENOMEM,
12227                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12228                                           NULL,
12229                                           "cannot allocate resource memory");
12230         memcpy(queue, action_conf->queue, queue_size);
12231         MLX5_ASSERT(shared_rss->ind_tbl);
12232         rte_spinlock_lock(&shared_rss->action_rss_sl);
12233         queue_old = shared_rss->ind_tbl->queues;
12234         ret = mlx5_ind_table_obj_modify(dev, shared_rss->ind_tbl,
12235                                         queue, action_conf->queue_num, true);
12236         if (ret) {
12237                 mlx5_free(queue);
12238                 ret = rte_flow_error_set(error, rte_errno,
12239                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12240                                           "cannot update indirection table");
12241         } else {
12242                 mlx5_free(queue_old);
12243                 shared_rss->origin.queue = queue;
12244                 shared_rss->origin.queue_num = action_conf->queue_num;
12245         }
12246         rte_spinlock_unlock(&shared_rss->action_rss_sl);
12247         return ret;
12248 }
12249
12250 /**
12251  * Updates in place shared action configuration, lock free,
12252  * (mutex should be acquired by caller).
12253  *
12254  * @param[in] dev
12255  *   Pointer to the Ethernet device structure.
12256  * @param[in] action
12257  *   The shared action object to be updated.
12258  * @param[in] action_conf
12259  *   Action specification used to modify *action*.
12260  *   *action_conf* should be of type correlating with type of the *action*,
12261  *   otherwise considered as invalid.
12262  * @param[out] error
12263  *   Perform verbose error reporting if not NULL. Initialized in case of
12264  *   error only.
12265  *
12266  * @return
12267  *   0 on success, otherwise negative errno value.
12268  */
12269 static int
12270 flow_dv_action_update(struct rte_eth_dev *dev,
12271                         struct rte_flow_shared_action *action,
12272                         const void *action_conf,
12273                         struct rte_flow_error *err)
12274 {
12275         uint32_t act_idx = (uint32_t)(uintptr_t)action;
12276         uint32_t type = act_idx >> MLX5_SHARED_ACTION_TYPE_OFFSET;
12277         uint32_t idx = act_idx & ((1u << MLX5_SHARED_ACTION_TYPE_OFFSET) - 1);
12278
12279         switch (type) {
12280         case MLX5_SHARED_ACTION_TYPE_RSS:
12281                 return __flow_dv_action_rss_update(dev, idx, action_conf, err);
12282         default:
12283                 return rte_flow_error_set(err, ENOTSUP,
12284                                           RTE_FLOW_ERROR_TYPE_ACTION,
12285                                           NULL,
12286                                           "action type update not supported");
12287         }
12288 }
12289
12290 static int
12291 flow_dv_action_query(struct rte_eth_dev *dev,
12292                      const struct rte_flow_shared_action *action, void *data,
12293                      struct rte_flow_error *error)
12294 {
12295         struct mlx5_age_param *age_param;
12296         struct rte_flow_query_age *resp;
12297         uint32_t act_idx = (uint32_t)(uintptr_t)action;
12298         uint32_t type = act_idx >> MLX5_SHARED_ACTION_TYPE_OFFSET;
12299         uint32_t idx = act_idx & ((1u << MLX5_SHARED_ACTION_TYPE_OFFSET) - 1);
12300
12301         switch (type) {
12302         case MLX5_SHARED_ACTION_TYPE_AGE:
12303                 age_param = &flow_aso_age_get_by_idx(dev, idx)->age_params;
12304                 resp = data;
12305                 resp->aged = __atomic_load_n(&age_param->state,
12306                                               __ATOMIC_RELAXED) == AGE_TMOUT ?
12307                                                                           1 : 0;
12308                 resp->sec_since_last_hit_valid = !resp->aged;
12309                 if (resp->sec_since_last_hit_valid)
12310                         resp->sec_since_last_hit = __atomic_load_n
12311                              (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
12312                 return 0;
12313         default:
12314                 return rte_flow_error_set(error, ENOTSUP,
12315                                           RTE_FLOW_ERROR_TYPE_ACTION,
12316                                           NULL,
12317                                           "action type query not supported");
12318         }
12319 }
12320
12321 /**
12322  * Query a dv flow  rule for its statistics via devx.
12323  *
12324  * @param[in] dev
12325  *   Pointer to Ethernet device.
12326  * @param[in] flow
12327  *   Pointer to the sub flow.
12328  * @param[out] data
12329  *   data retrieved by the query.
12330  * @param[out] error
12331  *   Perform verbose error reporting if not NULL.
12332  *
12333  * @return
12334  *   0 on success, a negative errno value otherwise and rte_errno is set.
12335  */
12336 static int
12337 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
12338                     void *data, struct rte_flow_error *error)
12339 {
12340         struct mlx5_priv *priv = dev->data->dev_private;
12341         struct rte_flow_query_count *qc = data;
12342
12343         if (!priv->config.devx)
12344                 return rte_flow_error_set(error, ENOTSUP,
12345                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12346                                           NULL,
12347                                           "counters are not supported");
12348         if (flow->counter) {
12349                 uint64_t pkts, bytes;
12350                 struct mlx5_flow_counter *cnt;
12351
12352                 cnt = flow_dv_counter_get_by_idx(dev, flow->counter,
12353                                                  NULL);
12354                 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
12355                                                &bytes);
12356
12357                 if (err)
12358                         return rte_flow_error_set(error, -err,
12359                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12360                                         NULL, "cannot read counters");
12361                 qc->hits_set = 1;
12362                 qc->bytes_set = 1;
12363                 qc->hits = pkts - cnt->hits;
12364                 qc->bytes = bytes - cnt->bytes;
12365                 if (qc->reset) {
12366                         cnt->hits = pkts;
12367                         cnt->bytes = bytes;
12368                 }
12369                 return 0;
12370         }
12371         return rte_flow_error_set(error, EINVAL,
12372                                   RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12373                                   NULL,
12374                                   "counters are not available");
12375 }
12376
12377 /**
12378  * Query a flow rule AGE action for aging information.
12379  *
12380  * @param[in] dev
12381  *   Pointer to Ethernet device.
12382  * @param[in] flow
12383  *   Pointer to the sub flow.
12384  * @param[out] data
12385  *   data retrieved by the query.
12386  * @param[out] error
12387  *   Perform verbose error reporting if not NULL.
12388  *
12389  * @return
12390  *   0 on success, a negative errno value otherwise and rte_errno is set.
12391  */
12392 static int
12393 flow_dv_query_age(struct rte_eth_dev *dev, struct rte_flow *flow,
12394                   void *data, struct rte_flow_error *error)
12395 {
12396         struct rte_flow_query_age *resp = data;
12397         struct mlx5_age_param *age_param;
12398
12399         if (flow->age) {
12400                 struct mlx5_aso_age_action *act =
12401                                      flow_aso_age_get_by_idx(dev, flow->age);
12402
12403                 age_param = &act->age_params;
12404         } else if (flow->counter) {
12405                 age_param = flow_dv_counter_idx_get_age(dev, flow->counter);
12406
12407                 if (!age_param || !age_param->timeout)
12408                         return rte_flow_error_set
12409                                         (error, EINVAL,
12410                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12411                                          NULL, "cannot read age data");
12412         } else {
12413                 return rte_flow_error_set(error, EINVAL,
12414                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12415                                           NULL, "age data not available");
12416         }
12417         resp->aged = __atomic_load_n(&age_param->state, __ATOMIC_RELAXED) ==
12418                                      AGE_TMOUT ? 1 : 0;
12419         resp->sec_since_last_hit_valid = !resp->aged;
12420         if (resp->sec_since_last_hit_valid)
12421                 resp->sec_since_last_hit = __atomic_load_n
12422                              (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
12423         return 0;
12424 }
12425
12426 /**
12427  * Query a flow.
12428  *
12429  * @see rte_flow_query()
12430  * @see rte_flow_ops
12431  */
12432 static int
12433 flow_dv_query(struct rte_eth_dev *dev,
12434               struct rte_flow *flow __rte_unused,
12435               const struct rte_flow_action *actions __rte_unused,
12436               void *data __rte_unused,
12437               struct rte_flow_error *error __rte_unused)
12438 {
12439         int ret = -EINVAL;
12440
12441         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
12442                 switch (actions->type) {
12443                 case RTE_FLOW_ACTION_TYPE_VOID:
12444                         break;
12445                 case RTE_FLOW_ACTION_TYPE_COUNT:
12446                         ret = flow_dv_query_count(dev, flow, data, error);
12447                         break;
12448                 case RTE_FLOW_ACTION_TYPE_AGE:
12449                         ret = flow_dv_query_age(dev, flow, data, error);
12450                         break;
12451                 default:
12452                         return rte_flow_error_set(error, ENOTSUP,
12453                                                   RTE_FLOW_ERROR_TYPE_ACTION,
12454                                                   actions,
12455                                                   "action not supported");
12456                 }
12457         }
12458         return ret;
12459 }
12460
12461 /**
12462  * Destroy the meter table set.
12463  * Lock free, (mutex should be acquired by caller).
12464  *
12465  * @param[in] dev
12466  *   Pointer to Ethernet device.
12467  * @param[in] tbl
12468  *   Pointer to the meter table set.
12469  *
12470  * @return
12471  *   Always 0.
12472  */
12473 static int
12474 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
12475                         struct mlx5_meter_domains_infos *tbl)
12476 {
12477         struct mlx5_priv *priv = dev->data->dev_private;
12478         struct mlx5_meter_domains_infos *mtd =
12479                                 (struct mlx5_meter_domains_infos *)tbl;
12480
12481         if (!mtd || !priv->config.dv_flow_en)
12482                 return 0;
12483         if (mtd->ingress.policer_rules[RTE_MTR_DROPPED])
12484                 claim_zero(mlx5_flow_os_destroy_flow
12485                            (mtd->ingress.policer_rules[RTE_MTR_DROPPED]));
12486         if (mtd->egress.policer_rules[RTE_MTR_DROPPED])
12487                 claim_zero(mlx5_flow_os_destroy_flow
12488                            (mtd->egress.policer_rules[RTE_MTR_DROPPED]));
12489         if (mtd->transfer.policer_rules[RTE_MTR_DROPPED])
12490                 claim_zero(mlx5_flow_os_destroy_flow
12491                            (mtd->transfer.policer_rules[RTE_MTR_DROPPED]));
12492         if (mtd->egress.color_matcher)
12493                 claim_zero(mlx5_flow_os_destroy_flow_matcher
12494                            (mtd->egress.color_matcher));
12495         if (mtd->egress.any_matcher)
12496                 claim_zero(mlx5_flow_os_destroy_flow_matcher
12497                            (mtd->egress.any_matcher));
12498         if (mtd->egress.tbl)
12499                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->egress.tbl);
12500         if (mtd->egress.sfx_tbl)
12501                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->egress.sfx_tbl);
12502         if (mtd->ingress.color_matcher)
12503                 claim_zero(mlx5_flow_os_destroy_flow_matcher
12504                            (mtd->ingress.color_matcher));
12505         if (mtd->ingress.any_matcher)
12506                 claim_zero(mlx5_flow_os_destroy_flow_matcher
12507                            (mtd->ingress.any_matcher));
12508         if (mtd->ingress.tbl)
12509                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->ingress.tbl);
12510         if (mtd->ingress.sfx_tbl)
12511                 flow_dv_tbl_resource_release(MLX5_SH(dev),
12512                                              mtd->ingress.sfx_tbl);
12513         if (mtd->transfer.color_matcher)
12514                 claim_zero(mlx5_flow_os_destroy_flow_matcher
12515                            (mtd->transfer.color_matcher));
12516         if (mtd->transfer.any_matcher)
12517                 claim_zero(mlx5_flow_os_destroy_flow_matcher
12518                            (mtd->transfer.any_matcher));
12519         if (mtd->transfer.tbl)
12520                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->transfer.tbl);
12521         if (mtd->transfer.sfx_tbl)
12522                 flow_dv_tbl_resource_release(MLX5_SH(dev),
12523                                              mtd->transfer.sfx_tbl);
12524         if (mtd->drop_actn)
12525                 claim_zero(mlx5_flow_os_destroy_flow_action(mtd->drop_actn));
12526         mlx5_free(mtd);
12527         return 0;
12528 }
12529
12530 /* Number of meter flow actions, count and jump or count and drop. */
12531 #define METER_ACTIONS 2
12532
12533 /**
12534  * Create specify domain meter table and suffix table.
12535  *
12536  * @param[in] dev
12537  *   Pointer to Ethernet device.
12538  * @param[in,out] mtb
12539  *   Pointer to DV meter table set.
12540  * @param[in] egress
12541  *   Table attribute.
12542  * @param[in] transfer
12543  *   Table attribute.
12544  * @param[in] color_reg_c_idx
12545  *   Reg C index for color match.
12546  *
12547  * @return
12548  *   0 on success, -1 otherwise and rte_errno is set.
12549  */
12550 static int
12551 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
12552                            struct mlx5_meter_domains_infos *mtb,
12553                            uint8_t egress, uint8_t transfer,
12554                            uint32_t color_reg_c_idx)
12555 {
12556         struct mlx5_priv *priv = dev->data->dev_private;
12557         struct mlx5_dev_ctx_shared *sh = priv->sh;
12558         struct mlx5_flow_dv_match_params mask = {
12559                 .size = sizeof(mask.buf),
12560         };
12561         struct mlx5_flow_dv_match_params value = {
12562                 .size = sizeof(value.buf),
12563         };
12564         struct mlx5dv_flow_matcher_attr dv_attr = {
12565                 .type = IBV_FLOW_ATTR_NORMAL,
12566                 .priority = 0,
12567                 .match_criteria_enable = 0,
12568                 .match_mask = (void *)&mask,
12569         };
12570         void *actions[METER_ACTIONS];
12571         struct mlx5_meter_domain_info *dtb;
12572         struct rte_flow_error error;
12573         int i = 0;
12574         int ret;
12575
12576         if (transfer)
12577                 dtb = &mtb->transfer;
12578         else if (egress)
12579                 dtb = &mtb->egress;
12580         else
12581                 dtb = &mtb->ingress;
12582         /* Create the meter table with METER level. */
12583         dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
12584                                             egress, transfer, false, NULL, 0,
12585                                             0, &error);
12586         if (!dtb->tbl) {
12587                 DRV_LOG(ERR, "Failed to create meter policer table.");
12588                 return -1;
12589         }
12590         /* Create the meter suffix table with SUFFIX level. */
12591         dtb->sfx_tbl = flow_dv_tbl_resource_get(dev,
12592                                             MLX5_FLOW_TABLE_LEVEL_SUFFIX,
12593                                             egress, transfer, false, NULL, 0,
12594                                             0, &error);
12595         if (!dtb->sfx_tbl) {
12596                 DRV_LOG(ERR, "Failed to create meter suffix table.");
12597                 return -1;
12598         }
12599         /* Create matchers, Any and Color. */
12600         dv_attr.priority = 3;
12601         dv_attr.match_criteria_enable = 0;
12602         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, dtb->tbl->obj,
12603                                                &dtb->any_matcher);
12604         if (ret) {
12605                 DRV_LOG(ERR, "Failed to create meter"
12606                              " policer default matcher.");
12607                 goto error_exit;
12608         }
12609         dv_attr.priority = 0;
12610         dv_attr.match_criteria_enable =
12611                                 1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
12612         flow_dv_match_meta_reg(mask.buf, value.buf, color_reg_c_idx,
12613                                rte_col_2_mlx5_col(RTE_COLORS), UINT8_MAX);
12614         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, dtb->tbl->obj,
12615                                                &dtb->color_matcher);
12616         if (ret) {
12617                 DRV_LOG(ERR, "Failed to create meter policer color matcher.");
12618                 goto error_exit;
12619         }
12620         if (mtb->count_actns[RTE_MTR_DROPPED])
12621                 actions[i++] = mtb->count_actns[RTE_MTR_DROPPED];
12622         actions[i++] = mtb->drop_actn;
12623         /* Default rule: lowest priority, match any, actions: drop. */
12624         ret = mlx5_flow_os_create_flow(dtb->any_matcher, (void *)&value, i,
12625                                        actions,
12626                                        &dtb->policer_rules[RTE_MTR_DROPPED]);
12627         if (ret) {
12628                 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
12629                 goto error_exit;
12630         }
12631         return 0;
12632 error_exit:
12633         return -1;
12634 }
12635
12636 /**
12637  * Create the needed meter and suffix tables.
12638  * Lock free, (mutex should be acquired by caller).
12639  *
12640  * @param[in] dev
12641  *   Pointer to Ethernet device.
12642  * @param[in] fm
12643  *   Pointer to the flow meter.
12644  *
12645  * @return
12646  *   Pointer to table set on success, NULL otherwise and rte_errno is set.
12647  */
12648 static struct mlx5_meter_domains_infos *
12649 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev,
12650                        const struct mlx5_flow_meter *fm)
12651 {
12652         struct mlx5_priv *priv = dev->data->dev_private;
12653         struct mlx5_meter_domains_infos *mtb;
12654         int ret;
12655         int i;
12656
12657         if (!priv->mtr_en) {
12658                 rte_errno = ENOTSUP;
12659                 return NULL;
12660         }
12661         mtb = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mtb), 0, SOCKET_ID_ANY);
12662         if (!mtb) {
12663                 DRV_LOG(ERR, "Failed to allocate memory for meter.");
12664                 return NULL;
12665         }
12666         /* Create meter count actions */
12667         for (i = 0; i <= RTE_MTR_DROPPED; i++) {
12668                 struct mlx5_flow_counter *cnt;
12669                 if (!fm->policer_stats.cnt[i])
12670                         continue;
12671                 cnt = flow_dv_counter_get_by_idx(dev,
12672                       fm->policer_stats.cnt[i], NULL);
12673                 mtb->count_actns[i] = cnt->action;
12674         }
12675         /* Create drop action. */
12676         ret = mlx5_flow_os_create_flow_action_drop(&mtb->drop_actn);
12677         if (ret) {
12678                 DRV_LOG(ERR, "Failed to create drop action.");
12679                 goto error_exit;
12680         }
12681         /* Egress meter table. */
12682         ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0, priv->mtr_color_reg);
12683         if (ret) {
12684                 DRV_LOG(ERR, "Failed to prepare egress meter table.");
12685                 goto error_exit;
12686         }
12687         /* Ingress meter table. */
12688         ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0, priv->mtr_color_reg);
12689         if (ret) {
12690                 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
12691                 goto error_exit;
12692         }
12693         /* FDB meter table. */
12694         if (priv->config.dv_esw_en) {
12695                 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1,
12696                                                  priv->mtr_color_reg);
12697                 if (ret) {
12698                         DRV_LOG(ERR, "Failed to prepare fdb meter table.");
12699                         goto error_exit;
12700                 }
12701         }
12702         return mtb;
12703 error_exit:
12704         flow_dv_destroy_mtr_tbl(dev, mtb);
12705         return NULL;
12706 }
12707
12708 /**
12709  * Destroy domain policer rule.
12710  *
12711  * @param[in] dt
12712  *   Pointer to domain table.
12713  */
12714 static void
12715 flow_dv_destroy_domain_policer_rule(struct mlx5_meter_domain_info *dt)
12716 {
12717         int i;
12718
12719         for (i = 0; i < RTE_MTR_DROPPED; i++) {
12720                 if (dt->policer_rules[i]) {
12721                         claim_zero(mlx5_flow_os_destroy_flow
12722                                    (dt->policer_rules[i]));
12723                         dt->policer_rules[i] = NULL;
12724                 }
12725         }
12726         if (dt->jump_actn) {
12727                 claim_zero(mlx5_flow_os_destroy_flow_action(dt->jump_actn));
12728                 dt->jump_actn = NULL;
12729         }
12730 }
12731
12732 /**
12733  * Destroy policer rules.
12734  *
12735  * @param[in] dev
12736  *   Pointer to Ethernet device.
12737  * @param[in] fm
12738  *   Pointer to flow meter structure.
12739  * @param[in] attr
12740  *   Pointer to flow attributes.
12741  *
12742  * @return
12743  *   Always 0.
12744  */
12745 static int
12746 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev __rte_unused,
12747                               const struct mlx5_flow_meter *fm,
12748                               const struct rte_flow_attr *attr)
12749 {
12750         struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
12751
12752         if (!mtb)
12753                 return 0;
12754         if (attr->egress)
12755                 flow_dv_destroy_domain_policer_rule(&mtb->egress);
12756         if (attr->ingress)
12757                 flow_dv_destroy_domain_policer_rule(&mtb->ingress);
12758         if (attr->transfer)
12759                 flow_dv_destroy_domain_policer_rule(&mtb->transfer);
12760         return 0;
12761 }
12762
12763 /**
12764  * Create specify domain meter policer rule.
12765  *
12766  * @param[in] fm
12767  *   Pointer to flow meter structure.
12768  * @param[in] mtb
12769  *   Pointer to DV meter table set.
12770  * @param[in] mtr_reg_c
12771  *   Color match REG_C.
12772  *
12773  * @return
12774  *   0 on success, -1 otherwise.
12775  */
12776 static int
12777 flow_dv_create_policer_forward_rule(struct mlx5_flow_meter *fm,
12778                                     struct mlx5_meter_domain_info *dtb,
12779                                     uint8_t mtr_reg_c)
12780 {
12781         struct mlx5_flow_dv_match_params matcher = {
12782                 .size = sizeof(matcher.buf),
12783         };
12784         struct mlx5_flow_dv_match_params value = {
12785                 .size = sizeof(value.buf),
12786         };
12787         struct mlx5_meter_domains_infos *mtb = fm->mfts;
12788         void *actions[METER_ACTIONS];
12789         int i;
12790         int ret = 0;
12791
12792         /* Create jump action. */
12793         if (!dtb->jump_actn)
12794                 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
12795                                 (dtb->sfx_tbl->obj, &dtb->jump_actn);
12796         if (ret) {
12797                 DRV_LOG(ERR, "Failed to create policer jump action.");
12798                 goto error;
12799         }
12800         for (i = 0; i < RTE_MTR_DROPPED; i++) {
12801                 int j = 0;
12802
12803                 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_reg_c,
12804                                        rte_col_2_mlx5_col(i), UINT8_MAX);
12805                 if (mtb->count_actns[i])
12806                         actions[j++] = mtb->count_actns[i];
12807                 if (fm->action[i] == MTR_POLICER_ACTION_DROP)
12808                         actions[j++] = mtb->drop_actn;
12809                 else
12810                         actions[j++] = dtb->jump_actn;
12811                 ret = mlx5_flow_os_create_flow(dtb->color_matcher,
12812                                                (void *)&value, j, actions,
12813                                                &dtb->policer_rules[i]);
12814                 if (ret) {
12815                         DRV_LOG(ERR, "Failed to create policer rule.");
12816                         goto error;
12817                 }
12818         }
12819         return 0;
12820 error:
12821         rte_errno = errno;
12822         return -1;
12823 }
12824
12825 /**
12826  * Create policer rules.
12827  *
12828  * @param[in] dev
12829  *   Pointer to Ethernet device.
12830  * @param[in] fm
12831  *   Pointer to flow meter structure.
12832  * @param[in] attr
12833  *   Pointer to flow attributes.
12834  *
12835  * @return
12836  *   0 on success, -1 otherwise.
12837  */
12838 static int
12839 flow_dv_create_policer_rules(struct rte_eth_dev *dev,
12840                              struct mlx5_flow_meter *fm,
12841                              const struct rte_flow_attr *attr)
12842 {
12843         struct mlx5_priv *priv = dev->data->dev_private;
12844         struct mlx5_meter_domains_infos *mtb = fm->mfts;
12845         int ret;
12846
12847         if (attr->egress) {
12848                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->egress,
12849                                                 priv->mtr_color_reg);
12850                 if (ret) {
12851                         DRV_LOG(ERR, "Failed to create egress policer.");
12852                         goto error;
12853                 }
12854         }
12855         if (attr->ingress) {
12856                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->ingress,
12857                                                 priv->mtr_color_reg);
12858                 if (ret) {
12859                         DRV_LOG(ERR, "Failed to create ingress policer.");
12860                         goto error;
12861                 }
12862         }
12863         if (attr->transfer) {
12864                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->transfer,
12865                                                 priv->mtr_color_reg);
12866                 if (ret) {
12867                         DRV_LOG(ERR, "Failed to create transfer policer.");
12868                         goto error;
12869                 }
12870         }
12871         return 0;
12872 error:
12873         flow_dv_destroy_policer_rules(dev, fm, attr);
12874         return -1;
12875 }
12876
12877 /**
12878  * Validate the batch counter support in root table.
12879  *
12880  * Create a simple flow with invalid counter and drop action on root table to
12881  * validate if batch counter with offset on root table is supported or not.
12882  *
12883  * @param[in] dev
12884  *   Pointer to rte_eth_dev structure.
12885  *
12886  * @return
12887  *   0 on success, a negative errno value otherwise and rte_errno is set.
12888  */
12889 int
12890 mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev)
12891 {
12892         struct mlx5_priv *priv = dev->data->dev_private;
12893         struct mlx5_dev_ctx_shared *sh = priv->sh;
12894         struct mlx5_flow_dv_match_params mask = {
12895                 .size = sizeof(mask.buf),
12896         };
12897         struct mlx5_flow_dv_match_params value = {
12898                 .size = sizeof(value.buf),
12899         };
12900         struct mlx5dv_flow_matcher_attr dv_attr = {
12901                 .type = IBV_FLOW_ATTR_NORMAL,
12902                 .priority = 0,
12903                 .match_criteria_enable = 0,
12904                 .match_mask = (void *)&mask,
12905         };
12906         void *actions[2] = { 0 };
12907         struct mlx5_flow_tbl_resource *tbl = NULL;
12908         struct mlx5_devx_obj *dcs = NULL;
12909         void *matcher = NULL;
12910         void *flow = NULL;
12911         int ret = -1;
12912
12913         tbl = flow_dv_tbl_resource_get(dev, 0, 0, 0, false, NULL, 0, 0, NULL);
12914         if (!tbl)
12915                 goto err;
12916         dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
12917         if (!dcs)
12918                 goto err;
12919         ret = mlx5_flow_os_create_flow_action_count(dcs->obj, UINT16_MAX,
12920                                                     &actions[0]);
12921         if (ret)
12922                 goto err;
12923         actions[1] = priv->drop_queue.hrxq->action;
12924         dv_attr.match_criteria_enable = flow_dv_matcher_enable(mask.buf);
12925         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj,
12926                                                &matcher);
12927         if (ret)
12928                 goto err;
12929         ret = mlx5_flow_os_create_flow(matcher, (void *)&value, 2,
12930                                        actions, &flow);
12931 err:
12932         /*
12933          * If batch counter with offset is not supported, the driver will not
12934          * validate the invalid offset value, flow create should success.
12935          * In this case, it means batch counter is not supported in root table.
12936          *
12937          * Otherwise, if flow create is failed, counter offset is supported.
12938          */
12939         if (flow) {
12940                 DRV_LOG(INFO, "Batch counter is not supported in root "
12941                               "table. Switch to fallback mode.");
12942                 rte_errno = ENOTSUP;
12943                 ret = -rte_errno;
12944                 claim_zero(mlx5_flow_os_destroy_flow(flow));
12945         } else {
12946                 /* Check matcher to make sure validate fail at flow create. */
12947                 if (!matcher || (matcher && errno != EINVAL))
12948                         DRV_LOG(ERR, "Unexpected error in counter offset "
12949                                      "support detection");
12950                 ret = 0;
12951         }
12952         if (actions[0])
12953                 claim_zero(mlx5_flow_os_destroy_flow_action(actions[0]));
12954         if (matcher)
12955                 claim_zero(mlx5_flow_os_destroy_flow_matcher(matcher));
12956         if (tbl)
12957                 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
12958         if (dcs)
12959                 claim_zero(mlx5_devx_cmd_destroy(dcs));
12960         return ret;
12961 }
12962
12963 /**
12964  * Query a devx counter.
12965  *
12966  * @param[in] dev
12967  *   Pointer to the Ethernet device structure.
12968  * @param[in] cnt
12969  *   Index to the flow counter.
12970  * @param[in] clear
12971  *   Set to clear the counter statistics.
12972  * @param[out] pkts
12973  *   The statistics value of packets.
12974  * @param[out] bytes
12975  *   The statistics value of bytes.
12976  *
12977  * @return
12978  *   0 on success, otherwise return -1.
12979  */
12980 static int
12981 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
12982                       uint64_t *pkts, uint64_t *bytes)
12983 {
12984         struct mlx5_priv *priv = dev->data->dev_private;
12985         struct mlx5_flow_counter *cnt;
12986         uint64_t inn_pkts, inn_bytes;
12987         int ret;
12988
12989         if (!priv->config.devx)
12990                 return -1;
12991
12992         ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
12993         if (ret)
12994                 return -1;
12995         cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
12996         *pkts = inn_pkts - cnt->hits;
12997         *bytes = inn_bytes - cnt->bytes;
12998         if (clear) {
12999                 cnt->hits = inn_pkts;
13000                 cnt->bytes = inn_bytes;
13001         }
13002         return 0;
13003 }
13004
13005 /**
13006  * Get aged-out flows.
13007  *
13008  * @param[in] dev
13009  *   Pointer to the Ethernet device structure.
13010  * @param[in] context
13011  *   The address of an array of pointers to the aged-out flows contexts.
13012  * @param[in] nb_contexts
13013  *   The length of context array pointers.
13014  * @param[out] error
13015  *   Perform verbose error reporting if not NULL. Initialized in case of
13016  *   error only.
13017  *
13018  * @return
13019  *   how many contexts get in success, otherwise negative errno value.
13020  *   if nb_contexts is 0, return the amount of all aged contexts.
13021  *   if nb_contexts is not 0 , return the amount of aged flows reported
13022  *   in the context array.
13023  * @note: only stub for now
13024  */
13025 static int
13026 flow_get_aged_flows(struct rte_eth_dev *dev,
13027                     void **context,
13028                     uint32_t nb_contexts,
13029                     struct rte_flow_error *error)
13030 {
13031         struct mlx5_priv *priv = dev->data->dev_private;
13032         struct mlx5_age_info *age_info;
13033         struct mlx5_age_param *age_param;
13034         struct mlx5_flow_counter *counter;
13035         struct mlx5_aso_age_action *act;
13036         int nb_flows = 0;
13037
13038         if (nb_contexts && !context)
13039                 return rte_flow_error_set(error, EINVAL,
13040                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13041                                           NULL, "empty context");
13042         age_info = GET_PORT_AGE_INFO(priv);
13043         rte_spinlock_lock(&age_info->aged_sl);
13044         LIST_FOREACH(act, &age_info->aged_aso, next) {
13045                 nb_flows++;
13046                 if (nb_contexts) {
13047                         context[nb_flows - 1] =
13048                                                 act->age_params.context;
13049                         if (!(--nb_contexts))
13050                                 break;
13051                 }
13052         }
13053         TAILQ_FOREACH(counter, &age_info->aged_counters, next) {
13054                 nb_flows++;
13055                 if (nb_contexts) {
13056                         age_param = MLX5_CNT_TO_AGE(counter);
13057                         context[nb_flows - 1] = age_param->context;
13058                         if (!(--nb_contexts))
13059                                 break;
13060                 }
13061         }
13062         rte_spinlock_unlock(&age_info->aged_sl);
13063         MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
13064         return nb_flows;
13065 }
13066
13067 /*
13068  * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
13069  */
13070 static uint32_t
13071 flow_dv_counter_allocate(struct rte_eth_dev *dev)
13072 {
13073         return flow_dv_counter_alloc(dev, 0);
13074 }
13075
13076 /**
13077  * Validate shared action.
13078  * Dispatcher for action type specific validation.
13079  *
13080  * @param[in] dev
13081  *   Pointer to the Ethernet device structure.
13082  * @param[in] conf
13083  *   Shared action configuration.
13084  * @param[in] action
13085  *   The shared action object to validate.
13086  * @param[out] error
13087  *   Perform verbose error reporting if not NULL. Initialized in case of
13088  *   error only.
13089  *
13090  * @return
13091  *   0 on success, otherwise negative errno value.
13092  */
13093 static int
13094 flow_dv_action_validate(struct rte_eth_dev *dev,
13095                         const struct rte_flow_shared_action_conf *conf,
13096                         const struct rte_flow_action *action,
13097                         struct rte_flow_error *err)
13098 {
13099         struct mlx5_priv *priv = dev->data->dev_private;
13100
13101         RTE_SET_USED(conf);
13102         switch (action->type) {
13103         case RTE_FLOW_ACTION_TYPE_RSS:
13104                 return mlx5_validate_action_rss(dev, action, err);
13105         case RTE_FLOW_ACTION_TYPE_AGE:
13106                 if (!priv->sh->aso_age_mng)
13107                         return rte_flow_error_set(err, ENOTSUP,
13108                                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13109                                                 NULL,
13110                                              "shared age action not supported");
13111                 return flow_dv_validate_action_age(0, action, dev, err);
13112         default:
13113                 return rte_flow_error_set(err, ENOTSUP,
13114                                           RTE_FLOW_ERROR_TYPE_ACTION,
13115                                           NULL,
13116                                           "action type not supported");
13117         }
13118 }
13119
13120 static int
13121 flow_dv_sync_domain(struct rte_eth_dev *dev, uint32_t domains, uint32_t flags)
13122 {
13123         struct mlx5_priv *priv = dev->data->dev_private;
13124         int ret = 0;
13125
13126         if ((domains & MLX5_DOMAIN_BIT_NIC_RX) && priv->sh->rx_domain != NULL) {
13127                 ret = mlx5_os_flow_dr_sync_domain(priv->sh->rx_domain,
13128                                                 flags);
13129                 if (ret != 0)
13130                         return ret;
13131         }
13132         if ((domains & MLX5_DOMAIN_BIT_NIC_TX) && priv->sh->tx_domain != NULL) {
13133                 ret = mlx5_os_flow_dr_sync_domain(priv->sh->tx_domain, flags);
13134                 if (ret != 0)
13135                         return ret;
13136         }
13137         if ((domains & MLX5_DOMAIN_BIT_FDB) && priv->sh->fdb_domain != NULL) {
13138                 ret = mlx5_os_flow_dr_sync_domain(priv->sh->fdb_domain, flags);
13139                 if (ret != 0)
13140                         return ret;
13141         }
13142         return 0;
13143 }
13144
13145 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
13146         .validate = flow_dv_validate,
13147         .prepare = flow_dv_prepare,
13148         .translate = flow_dv_translate,
13149         .apply = flow_dv_apply,
13150         .remove = flow_dv_remove,
13151         .destroy = flow_dv_destroy,
13152         .query = flow_dv_query,
13153         .create_mtr_tbls = flow_dv_create_mtr_tbl,
13154         .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
13155         .create_policer_rules = flow_dv_create_policer_rules,
13156         .destroy_policer_rules = flow_dv_destroy_policer_rules,
13157         .counter_alloc = flow_dv_counter_allocate,
13158         .counter_free = flow_dv_counter_free,
13159         .counter_query = flow_dv_counter_query,
13160         .get_aged_flows = flow_get_aged_flows,
13161         .action_validate = flow_dv_action_validate,
13162         .action_create = flow_dv_action_create,
13163         .action_destroy = flow_dv_action_destroy,
13164         .action_update = flow_dv_action_update,
13165         .action_query = flow_dv_action_query,
13166         .sync_domain = flow_dv_sync_domain,
13167 };
13168
13169 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */
13170