1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
14 #pragma GCC diagnostic ignored "-Wpedantic"
16 #include <infiniband/verbs.h>
18 #pragma GCC diagnostic error "-Wpedantic"
21 #include <rte_common.h>
22 #include <rte_ether.h>
23 #include <rte_ethdev_driver.h>
25 #include <rte_flow_driver.h>
26 #include <rte_malloc.h>
29 #include <rte_vxlan.h>
32 #include <mlx5_glue.h>
33 #include <mlx5_devx_cmds.h>
36 #include "mlx5_defs.h"
38 #include "mlx5_flow.h"
39 #include "mlx5_rxtx.h"
41 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
43 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
44 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
47 #ifndef HAVE_MLX5DV_DR_ESWITCH
48 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
49 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
53 #ifndef HAVE_MLX5DV_DR
54 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
57 /* VLAN header definitions */
58 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
59 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
60 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
61 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
62 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
77 * Initialize flow attributes structure according to flow items' types.
79 * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
80 * mode. For tunnel mode, the items to be modified are the outermost ones.
83 * Pointer to item specification.
85 * Pointer to flow attributes structure.
87 * Pointer to the sub flow.
88 * @param[in] tunnel_decap
89 * Whether action is after tunnel decapsulation.
92 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
93 struct mlx5_flow *dev_flow, bool tunnel_decap)
96 * If layers is already initialized, it means this dev_flow is the
97 * suffix flow, the layers flags is set by the prefix flow. Need to
98 * use the layer flags from prefix flow as the suffix flow may not
99 * have the user defined items as the flow is split.
101 if (dev_flow->layers) {
102 if (dev_flow->layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
104 else if (dev_flow->layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
106 if (dev_flow->layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
108 else if (dev_flow->layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
113 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
114 uint8_t next_protocol = 0xff;
115 switch (item->type) {
116 case RTE_FLOW_ITEM_TYPE_GRE:
117 case RTE_FLOW_ITEM_TYPE_NVGRE:
118 case RTE_FLOW_ITEM_TYPE_VXLAN:
119 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
120 case RTE_FLOW_ITEM_TYPE_GENEVE:
121 case RTE_FLOW_ITEM_TYPE_MPLS:
125 case RTE_FLOW_ITEM_TYPE_IPV4:
128 if (item->mask != NULL &&
129 ((const struct rte_flow_item_ipv4 *)
130 item->mask)->hdr.next_proto_id)
132 ((const struct rte_flow_item_ipv4 *)
133 (item->spec))->hdr.next_proto_id &
134 ((const struct rte_flow_item_ipv4 *)
135 (item->mask))->hdr.next_proto_id;
136 if ((next_protocol == IPPROTO_IPIP ||
137 next_protocol == IPPROTO_IPV6) && tunnel_decap)
140 case RTE_FLOW_ITEM_TYPE_IPV6:
143 if (item->mask != NULL &&
144 ((const struct rte_flow_item_ipv6 *)
145 item->mask)->hdr.proto)
147 ((const struct rte_flow_item_ipv6 *)
148 (item->spec))->hdr.proto &
149 ((const struct rte_flow_item_ipv6 *)
150 (item->mask))->hdr.proto;
151 if ((next_protocol == IPPROTO_IPIP ||
152 next_protocol == IPPROTO_IPV6) && tunnel_decap)
155 case RTE_FLOW_ITEM_TYPE_UDP:
159 case RTE_FLOW_ITEM_TYPE_TCP:
171 * Convert rte_mtr_color to mlx5 color.
180 rte_col_2_mlx5_col(enum rte_color rcol)
183 case RTE_COLOR_GREEN:
184 return MLX5_FLOW_COLOR_GREEN;
185 case RTE_COLOR_YELLOW:
186 return MLX5_FLOW_COLOR_YELLOW;
188 return MLX5_FLOW_COLOR_RED;
192 return MLX5_FLOW_COLOR_UNDEFINED;
195 struct field_modify_info {
196 uint32_t size; /* Size of field in protocol header, in bytes. */
197 uint32_t offset; /* Offset of field in protocol header, in bytes. */
198 enum mlx5_modification_field id;
201 struct field_modify_info modify_eth[] = {
202 {4, 0, MLX5_MODI_OUT_DMAC_47_16},
203 {2, 4, MLX5_MODI_OUT_DMAC_15_0},
204 {4, 6, MLX5_MODI_OUT_SMAC_47_16},
205 {2, 10, MLX5_MODI_OUT_SMAC_15_0},
209 struct field_modify_info modify_vlan_out_first_vid[] = {
210 /* Size in bits !!! */
211 {12, 0, MLX5_MODI_OUT_FIRST_VID},
215 struct field_modify_info modify_ipv4[] = {
216 {1, 1, MLX5_MODI_OUT_IP_DSCP},
217 {1, 8, MLX5_MODI_OUT_IPV4_TTL},
218 {4, 12, MLX5_MODI_OUT_SIPV4},
219 {4, 16, MLX5_MODI_OUT_DIPV4},
223 struct field_modify_info modify_ipv6[] = {
224 {1, 0, MLX5_MODI_OUT_IP_DSCP},
225 {1, 7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
226 {4, 8, MLX5_MODI_OUT_SIPV6_127_96},
227 {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
228 {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
229 {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
230 {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
231 {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
232 {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
233 {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
237 struct field_modify_info modify_udp[] = {
238 {2, 0, MLX5_MODI_OUT_UDP_SPORT},
239 {2, 2, MLX5_MODI_OUT_UDP_DPORT},
243 struct field_modify_info modify_tcp[] = {
244 {2, 0, MLX5_MODI_OUT_TCP_SPORT},
245 {2, 2, MLX5_MODI_OUT_TCP_DPORT},
246 {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
247 {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
252 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
253 uint8_t next_protocol, uint64_t *item_flags,
256 MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
257 item->type == RTE_FLOW_ITEM_TYPE_IPV6);
258 if (next_protocol == IPPROTO_IPIP) {
259 *item_flags |= MLX5_FLOW_LAYER_IPIP;
262 if (next_protocol == IPPROTO_IPV6) {
263 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
269 * Acquire the synchronizing object to protect multithreaded access
270 * to shared dv context. Lock occurs only if context is actually
271 * shared, i.e. we have multiport IB device and representors are
275 * Pointer to the rte_eth_dev structure.
278 flow_dv_shared_lock(struct rte_eth_dev *dev)
280 struct mlx5_priv *priv = dev->data->dev_private;
281 struct mlx5_ibv_shared *sh = priv->sh;
283 if (sh->dv_refcnt > 1) {
286 ret = pthread_mutex_lock(&sh->dv_mutex);
293 flow_dv_shared_unlock(struct rte_eth_dev *dev)
295 struct mlx5_priv *priv = dev->data->dev_private;
296 struct mlx5_ibv_shared *sh = priv->sh;
298 if (sh->dv_refcnt > 1) {
301 ret = pthread_mutex_unlock(&sh->dv_mutex);
307 /* Update VLAN's VID/PCP based on input rte_flow_action.
310 * Pointer to struct rte_flow_action.
312 * Pointer to struct rte_vlan_hdr.
315 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
316 struct rte_vlan_hdr *vlan)
319 if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
321 ((const struct rte_flow_action_of_set_vlan_pcp *)
322 action->conf)->vlan_pcp;
323 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
324 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
325 vlan->vlan_tci |= vlan_tci;
326 } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
327 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
328 vlan->vlan_tci |= rte_be_to_cpu_16
329 (((const struct rte_flow_action_of_set_vlan_vid *)
330 action->conf)->vlan_vid);
335 * Fetch 1, 2, 3 or 4 byte field from the byte array
336 * and return as unsigned integer in host-endian format.
339 * Pointer to data array.
341 * Size of field to extract.
344 * converted field in host endian format.
346 static inline uint32_t
347 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
356 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
359 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
360 ret = (ret << 8) | *(data + sizeof(uint16_t));
363 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
374 * Convert modify-header action to DV specification.
376 * Data length of each action is determined by provided field description
377 * and the item mask. Data bit offset and width of each action is determined
378 * by provided item mask.
381 * Pointer to item specification.
383 * Pointer to field modification information.
384 * For MLX5_MODIFICATION_TYPE_SET specifies destination field.
385 * For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
386 * For MLX5_MODIFICATION_TYPE_COPY specifies source field.
388 * Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
389 * Negative offset value sets the same offset as source offset.
390 * size field is ignored, value is taken from source field.
391 * @param[in,out] resource
392 * Pointer to the modify-header resource.
394 * Type of modification.
396 * Pointer to the error structure.
399 * 0 on success, a negative errno value otherwise and rte_errno is set.
402 flow_dv_convert_modify_action(struct rte_flow_item *item,
403 struct field_modify_info *field,
404 struct field_modify_info *dcopy,
405 struct mlx5_flow_dv_modify_hdr_resource *resource,
406 uint32_t type, struct rte_flow_error *error)
408 uint32_t i = resource->actions_num;
409 struct mlx5_modification_cmd *actions = resource->actions;
412 * The item and mask are provided in big-endian format.
413 * The fields should be presented as in big-endian format either.
414 * Mask must be always present, it defines the actual field width.
416 MLX5_ASSERT(item->mask);
417 MLX5_ASSERT(field->size);
424 if (i >= MLX5_MAX_MODIFY_NUM)
425 return rte_flow_error_set(error, EINVAL,
426 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
427 "too many items to modify");
428 /* Fetch variable byte size mask from the array. */
429 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
430 field->offset, field->size);
435 /* Deduce actual data width in bits from mask value. */
436 off_b = rte_bsf32(mask);
437 size_b = sizeof(uint32_t) * CHAR_BIT -
438 off_b - __builtin_clz(mask);
440 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
441 actions[i] = (struct mlx5_modification_cmd) {
447 /* Convert entire record to expected big-endian format. */
448 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
449 if (type == MLX5_MODIFICATION_TYPE_COPY) {
451 actions[i].dst_field = dcopy->id;
452 actions[i].dst_offset =
453 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
454 /* Convert entire record to big-endian format. */
455 actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
457 MLX5_ASSERT(item->spec);
458 data = flow_dv_fetch_field((const uint8_t *)item->spec +
459 field->offset, field->size);
460 /* Shift out the trailing masked bits from data. */
461 data = (data & mask) >> off_b;
462 actions[i].data1 = rte_cpu_to_be_32(data);
466 } while (field->size);
467 if (resource->actions_num == i)
468 return rte_flow_error_set(error, EINVAL,
469 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
470 "invalid modification flow item");
471 resource->actions_num = i;
476 * Convert modify-header set IPv4 address action to DV specification.
478 * @param[in,out] resource
479 * Pointer to the modify-header resource.
481 * Pointer to action specification.
483 * Pointer to the error structure.
486 * 0 on success, a negative errno value otherwise and rte_errno is set.
489 flow_dv_convert_action_modify_ipv4
490 (struct mlx5_flow_dv_modify_hdr_resource *resource,
491 const struct rte_flow_action *action,
492 struct rte_flow_error *error)
494 const struct rte_flow_action_set_ipv4 *conf =
495 (const struct rte_flow_action_set_ipv4 *)(action->conf);
496 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
497 struct rte_flow_item_ipv4 ipv4;
498 struct rte_flow_item_ipv4 ipv4_mask;
500 memset(&ipv4, 0, sizeof(ipv4));
501 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
502 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
503 ipv4.hdr.src_addr = conf->ipv4_addr;
504 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
506 ipv4.hdr.dst_addr = conf->ipv4_addr;
507 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
510 item.mask = &ipv4_mask;
511 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
512 MLX5_MODIFICATION_TYPE_SET, error);
516 * Convert modify-header set IPv6 address action to DV specification.
518 * @param[in,out] resource
519 * Pointer to the modify-header resource.
521 * Pointer to action specification.
523 * Pointer to the error structure.
526 * 0 on success, a negative errno value otherwise and rte_errno is set.
529 flow_dv_convert_action_modify_ipv6
530 (struct mlx5_flow_dv_modify_hdr_resource *resource,
531 const struct rte_flow_action *action,
532 struct rte_flow_error *error)
534 const struct rte_flow_action_set_ipv6 *conf =
535 (const struct rte_flow_action_set_ipv6 *)(action->conf);
536 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
537 struct rte_flow_item_ipv6 ipv6;
538 struct rte_flow_item_ipv6 ipv6_mask;
540 memset(&ipv6, 0, sizeof(ipv6));
541 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
542 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
543 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
544 sizeof(ipv6.hdr.src_addr));
545 memcpy(&ipv6_mask.hdr.src_addr,
546 &rte_flow_item_ipv6_mask.hdr.src_addr,
547 sizeof(ipv6.hdr.src_addr));
549 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
550 sizeof(ipv6.hdr.dst_addr));
551 memcpy(&ipv6_mask.hdr.dst_addr,
552 &rte_flow_item_ipv6_mask.hdr.dst_addr,
553 sizeof(ipv6.hdr.dst_addr));
556 item.mask = &ipv6_mask;
557 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
558 MLX5_MODIFICATION_TYPE_SET, error);
562 * Convert modify-header set MAC address action to DV specification.
564 * @param[in,out] resource
565 * Pointer to the modify-header resource.
567 * Pointer to action specification.
569 * Pointer to the error structure.
572 * 0 on success, a negative errno value otherwise and rte_errno is set.
575 flow_dv_convert_action_modify_mac
576 (struct mlx5_flow_dv_modify_hdr_resource *resource,
577 const struct rte_flow_action *action,
578 struct rte_flow_error *error)
580 const struct rte_flow_action_set_mac *conf =
581 (const struct rte_flow_action_set_mac *)(action->conf);
582 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
583 struct rte_flow_item_eth eth;
584 struct rte_flow_item_eth eth_mask;
586 memset(ð, 0, sizeof(eth));
587 memset(ð_mask, 0, sizeof(eth_mask));
588 if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
589 memcpy(ð.src.addr_bytes, &conf->mac_addr,
590 sizeof(eth.src.addr_bytes));
591 memcpy(ð_mask.src.addr_bytes,
592 &rte_flow_item_eth_mask.src.addr_bytes,
593 sizeof(eth_mask.src.addr_bytes));
595 memcpy(ð.dst.addr_bytes, &conf->mac_addr,
596 sizeof(eth.dst.addr_bytes));
597 memcpy(ð_mask.dst.addr_bytes,
598 &rte_flow_item_eth_mask.dst.addr_bytes,
599 sizeof(eth_mask.dst.addr_bytes));
602 item.mask = ð_mask;
603 return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
604 MLX5_MODIFICATION_TYPE_SET, error);
608 * Convert modify-header set VLAN VID action to DV specification.
610 * @param[in,out] resource
611 * Pointer to the modify-header resource.
613 * Pointer to action specification.
615 * Pointer to the error structure.
618 * 0 on success, a negative errno value otherwise and rte_errno is set.
621 flow_dv_convert_action_modify_vlan_vid
622 (struct mlx5_flow_dv_modify_hdr_resource *resource,
623 const struct rte_flow_action *action,
624 struct rte_flow_error *error)
626 const struct rte_flow_action_of_set_vlan_vid *conf =
627 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
628 int i = resource->actions_num;
629 struct mlx5_modification_cmd *actions = resource->actions;
630 struct field_modify_info *field = modify_vlan_out_first_vid;
632 if (i >= MLX5_MAX_MODIFY_NUM)
633 return rte_flow_error_set(error, EINVAL,
634 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
635 "too many items to modify");
636 actions[i] = (struct mlx5_modification_cmd) {
637 .action_type = MLX5_MODIFICATION_TYPE_SET,
639 .length = field->size,
640 .offset = field->offset,
642 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
643 actions[i].data1 = conf->vlan_vid;
644 actions[i].data1 = actions[i].data1 << 16;
645 resource->actions_num = ++i;
650 * Convert modify-header set TP action to DV specification.
652 * @param[in,out] resource
653 * Pointer to the modify-header resource.
655 * Pointer to action specification.
657 * Pointer to rte_flow_item objects list.
659 * Pointer to flow attributes structure.
660 * @param[in] dev_flow
661 * Pointer to the sub flow.
662 * @param[in] tunnel_decap
663 * Whether action is after tunnel decapsulation.
665 * Pointer to the error structure.
668 * 0 on success, a negative errno value otherwise and rte_errno is set.
671 flow_dv_convert_action_modify_tp
672 (struct mlx5_flow_dv_modify_hdr_resource *resource,
673 const struct rte_flow_action *action,
674 const struct rte_flow_item *items,
675 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
676 bool tunnel_decap, struct rte_flow_error *error)
678 const struct rte_flow_action_set_tp *conf =
679 (const struct rte_flow_action_set_tp *)(action->conf);
680 struct rte_flow_item item;
681 struct rte_flow_item_udp udp;
682 struct rte_flow_item_udp udp_mask;
683 struct rte_flow_item_tcp tcp;
684 struct rte_flow_item_tcp tcp_mask;
685 struct field_modify_info *field;
688 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
690 memset(&udp, 0, sizeof(udp));
691 memset(&udp_mask, 0, sizeof(udp_mask));
692 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
693 udp.hdr.src_port = conf->port;
694 udp_mask.hdr.src_port =
695 rte_flow_item_udp_mask.hdr.src_port;
697 udp.hdr.dst_port = conf->port;
698 udp_mask.hdr.dst_port =
699 rte_flow_item_udp_mask.hdr.dst_port;
701 item.type = RTE_FLOW_ITEM_TYPE_UDP;
703 item.mask = &udp_mask;
707 memset(&tcp, 0, sizeof(tcp));
708 memset(&tcp_mask, 0, sizeof(tcp_mask));
709 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
710 tcp.hdr.src_port = conf->port;
711 tcp_mask.hdr.src_port =
712 rte_flow_item_tcp_mask.hdr.src_port;
714 tcp.hdr.dst_port = conf->port;
715 tcp_mask.hdr.dst_port =
716 rte_flow_item_tcp_mask.hdr.dst_port;
718 item.type = RTE_FLOW_ITEM_TYPE_TCP;
720 item.mask = &tcp_mask;
723 return flow_dv_convert_modify_action(&item, field, NULL, resource,
724 MLX5_MODIFICATION_TYPE_SET, error);
728 * Convert modify-header set TTL action to DV specification.
730 * @param[in,out] resource
731 * Pointer to the modify-header resource.
733 * Pointer to action specification.
735 * Pointer to rte_flow_item objects list.
737 * Pointer to flow attributes structure.
738 * @param[in] dev_flow
739 * Pointer to the sub flow.
740 * @param[in] tunnel_decap
741 * Whether action is after tunnel decapsulation.
743 * Pointer to the error structure.
746 * 0 on success, a negative errno value otherwise and rte_errno is set.
749 flow_dv_convert_action_modify_ttl
750 (struct mlx5_flow_dv_modify_hdr_resource *resource,
751 const struct rte_flow_action *action,
752 const struct rte_flow_item *items,
753 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
754 bool tunnel_decap, struct rte_flow_error *error)
756 const struct rte_flow_action_set_ttl *conf =
757 (const struct rte_flow_action_set_ttl *)(action->conf);
758 struct rte_flow_item item;
759 struct rte_flow_item_ipv4 ipv4;
760 struct rte_flow_item_ipv4 ipv4_mask;
761 struct rte_flow_item_ipv6 ipv6;
762 struct rte_flow_item_ipv6 ipv6_mask;
763 struct field_modify_info *field;
766 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
768 memset(&ipv4, 0, sizeof(ipv4));
769 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
770 ipv4.hdr.time_to_live = conf->ttl_value;
771 ipv4_mask.hdr.time_to_live = 0xFF;
772 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
774 item.mask = &ipv4_mask;
778 memset(&ipv6, 0, sizeof(ipv6));
779 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
780 ipv6.hdr.hop_limits = conf->ttl_value;
781 ipv6_mask.hdr.hop_limits = 0xFF;
782 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
784 item.mask = &ipv6_mask;
787 return flow_dv_convert_modify_action(&item, field, NULL, resource,
788 MLX5_MODIFICATION_TYPE_SET, error);
792 * Convert modify-header decrement TTL action to DV specification.
794 * @param[in,out] resource
795 * Pointer to the modify-header resource.
797 * Pointer to action specification.
799 * Pointer to rte_flow_item objects list.
801 * Pointer to flow attributes structure.
802 * @param[in] dev_flow
803 * Pointer to the sub flow.
804 * @param[in] tunnel_decap
805 * Whether action is after tunnel decapsulation.
807 * Pointer to the error structure.
810 * 0 on success, a negative errno value otherwise and rte_errno is set.
813 flow_dv_convert_action_modify_dec_ttl
814 (struct mlx5_flow_dv_modify_hdr_resource *resource,
815 const struct rte_flow_item *items,
816 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
817 bool tunnel_decap, struct rte_flow_error *error)
819 struct rte_flow_item item;
820 struct rte_flow_item_ipv4 ipv4;
821 struct rte_flow_item_ipv4 ipv4_mask;
822 struct rte_flow_item_ipv6 ipv6;
823 struct rte_flow_item_ipv6 ipv6_mask;
824 struct field_modify_info *field;
827 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
829 memset(&ipv4, 0, sizeof(ipv4));
830 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
831 ipv4.hdr.time_to_live = 0xFF;
832 ipv4_mask.hdr.time_to_live = 0xFF;
833 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
835 item.mask = &ipv4_mask;
839 memset(&ipv6, 0, sizeof(ipv6));
840 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
841 ipv6.hdr.hop_limits = 0xFF;
842 ipv6_mask.hdr.hop_limits = 0xFF;
843 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
845 item.mask = &ipv6_mask;
848 return flow_dv_convert_modify_action(&item, field, NULL, resource,
849 MLX5_MODIFICATION_TYPE_ADD, error);
853 * Convert modify-header increment/decrement TCP Sequence number
854 * to DV specification.
856 * @param[in,out] resource
857 * Pointer to the modify-header resource.
859 * Pointer to action specification.
861 * Pointer to the error structure.
864 * 0 on success, a negative errno value otherwise and rte_errno is set.
867 flow_dv_convert_action_modify_tcp_seq
868 (struct mlx5_flow_dv_modify_hdr_resource *resource,
869 const struct rte_flow_action *action,
870 struct rte_flow_error *error)
872 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
873 uint64_t value = rte_be_to_cpu_32(*conf);
874 struct rte_flow_item item;
875 struct rte_flow_item_tcp tcp;
876 struct rte_flow_item_tcp tcp_mask;
878 memset(&tcp, 0, sizeof(tcp));
879 memset(&tcp_mask, 0, sizeof(tcp_mask));
880 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
882 * The HW has no decrement operation, only increment operation.
883 * To simulate decrement X from Y using increment operation
884 * we need to add UINT32_MAX X times to Y.
885 * Each adding of UINT32_MAX decrements Y by 1.
888 tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
889 tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
890 item.type = RTE_FLOW_ITEM_TYPE_TCP;
892 item.mask = &tcp_mask;
893 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
894 MLX5_MODIFICATION_TYPE_ADD, error);
898 * Convert modify-header increment/decrement TCP Acknowledgment number
899 * to DV specification.
901 * @param[in,out] resource
902 * Pointer to the modify-header resource.
904 * Pointer to action specification.
906 * Pointer to the error structure.
909 * 0 on success, a negative errno value otherwise and rte_errno is set.
912 flow_dv_convert_action_modify_tcp_ack
913 (struct mlx5_flow_dv_modify_hdr_resource *resource,
914 const struct rte_flow_action *action,
915 struct rte_flow_error *error)
917 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
918 uint64_t value = rte_be_to_cpu_32(*conf);
919 struct rte_flow_item item;
920 struct rte_flow_item_tcp tcp;
921 struct rte_flow_item_tcp tcp_mask;
923 memset(&tcp, 0, sizeof(tcp));
924 memset(&tcp_mask, 0, sizeof(tcp_mask));
925 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
927 * The HW has no decrement operation, only increment operation.
928 * To simulate decrement X from Y using increment operation
929 * we need to add UINT32_MAX X times to Y.
930 * Each adding of UINT32_MAX decrements Y by 1.
933 tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
934 tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
935 item.type = RTE_FLOW_ITEM_TYPE_TCP;
937 item.mask = &tcp_mask;
938 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
939 MLX5_MODIFICATION_TYPE_ADD, error);
942 static enum mlx5_modification_field reg_to_field[] = {
943 [REG_NONE] = MLX5_MODI_OUT_NONE,
944 [REG_A] = MLX5_MODI_META_DATA_REG_A,
945 [REG_B] = MLX5_MODI_META_DATA_REG_B,
946 [REG_C_0] = MLX5_MODI_META_REG_C_0,
947 [REG_C_1] = MLX5_MODI_META_REG_C_1,
948 [REG_C_2] = MLX5_MODI_META_REG_C_2,
949 [REG_C_3] = MLX5_MODI_META_REG_C_3,
950 [REG_C_4] = MLX5_MODI_META_REG_C_4,
951 [REG_C_5] = MLX5_MODI_META_REG_C_5,
952 [REG_C_6] = MLX5_MODI_META_REG_C_6,
953 [REG_C_7] = MLX5_MODI_META_REG_C_7,
957 * Convert register set to DV specification.
959 * @param[in,out] resource
960 * Pointer to the modify-header resource.
962 * Pointer to action specification.
964 * Pointer to the error structure.
967 * 0 on success, a negative errno value otherwise and rte_errno is set.
970 flow_dv_convert_action_set_reg
971 (struct mlx5_flow_dv_modify_hdr_resource *resource,
972 const struct rte_flow_action *action,
973 struct rte_flow_error *error)
975 const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
976 struct mlx5_modification_cmd *actions = resource->actions;
977 uint32_t i = resource->actions_num;
979 if (i >= MLX5_MAX_MODIFY_NUM)
980 return rte_flow_error_set(error, EINVAL,
981 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
982 "too many items to modify");
983 MLX5_ASSERT(conf->id != REG_NONE);
984 MLX5_ASSERT(conf->id < RTE_DIM(reg_to_field));
985 actions[i] = (struct mlx5_modification_cmd) {
986 .action_type = MLX5_MODIFICATION_TYPE_SET,
987 .field = reg_to_field[conf->id],
989 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
990 actions[i].data1 = rte_cpu_to_be_32(conf->data);
992 resource->actions_num = i;
997 * Convert SET_TAG action to DV specification.
1000 * Pointer to the rte_eth_dev structure.
1001 * @param[in,out] resource
1002 * Pointer to the modify-header resource.
1004 * Pointer to action specification.
1006 * Pointer to the error structure.
1009 * 0 on success, a negative errno value otherwise and rte_errno is set.
1012 flow_dv_convert_action_set_tag
1013 (struct rte_eth_dev *dev,
1014 struct mlx5_flow_dv_modify_hdr_resource *resource,
1015 const struct rte_flow_action_set_tag *conf,
1016 struct rte_flow_error *error)
1018 rte_be32_t data = rte_cpu_to_be_32(conf->data);
1019 rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
1020 struct rte_flow_item item = {
1024 struct field_modify_info reg_c_x[] = {
1027 enum mlx5_modification_field reg_type;
1030 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1033 MLX5_ASSERT(ret != REG_NONE);
1034 MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1035 reg_type = reg_to_field[ret];
1036 MLX5_ASSERT(reg_type > 0);
1037 reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1038 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1039 MLX5_MODIFICATION_TYPE_SET, error);
1043 * Convert internal COPY_REG action to DV specification.
1046 * Pointer to the rte_eth_dev structure.
1047 * @param[in,out] res
1048 * Pointer to the modify-header resource.
1050 * Pointer to action specification.
1052 * Pointer to the error structure.
1055 * 0 on success, a negative errno value otherwise and rte_errno is set.
1058 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1059 struct mlx5_flow_dv_modify_hdr_resource *res,
1060 const struct rte_flow_action *action,
1061 struct rte_flow_error *error)
1063 const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1064 rte_be32_t mask = RTE_BE32(UINT32_MAX);
1065 struct rte_flow_item item = {
1069 struct field_modify_info reg_src[] = {
1070 {4, 0, reg_to_field[conf->src]},
1073 struct field_modify_info reg_dst = {
1075 .id = reg_to_field[conf->dst],
1077 /* Adjust reg_c[0] usage according to reported mask. */
1078 if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1079 struct mlx5_priv *priv = dev->data->dev_private;
1080 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1082 MLX5_ASSERT(reg_c0);
1083 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1084 if (conf->dst == REG_C_0) {
1085 /* Copy to reg_c[0], within mask only. */
1086 reg_dst.offset = rte_bsf32(reg_c0);
1088 * Mask is ignoring the enianness, because
1089 * there is no conversion in datapath.
1091 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1092 /* Copy from destination lower bits to reg_c[0]. */
1093 mask = reg_c0 >> reg_dst.offset;
1095 /* Copy from destination upper bits to reg_c[0]. */
1096 mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1097 rte_fls_u32(reg_c0));
1100 mask = rte_cpu_to_be_32(reg_c0);
1101 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1102 /* Copy from reg_c[0] to destination lower bits. */
1105 /* Copy from reg_c[0] to destination upper bits. */
1106 reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1107 (rte_fls_u32(reg_c0) -
1112 return flow_dv_convert_modify_action(&item,
1113 reg_src, ®_dst, res,
1114 MLX5_MODIFICATION_TYPE_COPY,
1119 * Convert MARK action to DV specification. This routine is used
1120 * in extensive metadata only and requires metadata register to be
1121 * handled. In legacy mode hardware tag resource is engaged.
1124 * Pointer to the rte_eth_dev structure.
1126 * Pointer to MARK action specification.
1127 * @param[in,out] resource
1128 * Pointer to the modify-header resource.
1130 * Pointer to the error structure.
1133 * 0 on success, a negative errno value otherwise and rte_errno is set.
1136 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1137 const struct rte_flow_action_mark *conf,
1138 struct mlx5_flow_dv_modify_hdr_resource *resource,
1139 struct rte_flow_error *error)
1141 struct mlx5_priv *priv = dev->data->dev_private;
1142 rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1143 priv->sh->dv_mark_mask);
1144 rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1145 struct rte_flow_item item = {
1149 struct field_modify_info reg_c_x[] = {
1150 {4, 0, 0}, /* dynamic instead of MLX5_MODI_META_REG_C_1. */
1156 return rte_flow_error_set(error, EINVAL,
1157 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1158 NULL, "zero mark action mask");
1159 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1162 MLX5_ASSERT(reg > 0);
1163 if (reg == REG_C_0) {
1164 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1165 uint32_t shl_c0 = rte_bsf32(msk_c0);
1167 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1168 mask = rte_cpu_to_be_32(mask) & msk_c0;
1169 mask = rte_cpu_to_be_32(mask << shl_c0);
1171 reg_c_x[0].id = reg_to_field[reg];
1172 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1173 MLX5_MODIFICATION_TYPE_SET, error);
1177 * Get metadata register index for specified steering domain.
1180 * Pointer to the rte_eth_dev structure.
1182 * Attributes of flow to determine steering domain.
1184 * Pointer to the error structure.
1187 * positive index on success, a negative errno value otherwise
1188 * and rte_errno is set.
1190 static enum modify_reg
1191 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1192 const struct rte_flow_attr *attr,
1193 struct rte_flow_error *error)
1196 mlx5_flow_get_reg_id(dev, attr->transfer ?
1200 MLX5_METADATA_RX, 0, error);
1202 return rte_flow_error_set(error,
1203 ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1204 NULL, "unavailable "
1205 "metadata register");
1210 * Convert SET_META action to DV specification.
1213 * Pointer to the rte_eth_dev structure.
1214 * @param[in,out] resource
1215 * Pointer to the modify-header resource.
1217 * Attributes of flow that includes this item.
1219 * Pointer to action specification.
1221 * Pointer to the error structure.
1224 * 0 on success, a negative errno value otherwise and rte_errno is set.
1227 flow_dv_convert_action_set_meta
1228 (struct rte_eth_dev *dev,
1229 struct mlx5_flow_dv_modify_hdr_resource *resource,
1230 const struct rte_flow_attr *attr,
1231 const struct rte_flow_action_set_meta *conf,
1232 struct rte_flow_error *error)
1234 uint32_t data = conf->data;
1235 uint32_t mask = conf->mask;
1236 struct rte_flow_item item = {
1240 struct field_modify_info reg_c_x[] = {
1243 int reg = flow_dv_get_metadata_reg(dev, attr, error);
1248 * In datapath code there is no endianness
1249 * coversions for perfromance reasons, all
1250 * pattern conversions are done in rte_flow.
1252 if (reg == REG_C_0) {
1253 struct mlx5_priv *priv = dev->data->dev_private;
1254 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1257 MLX5_ASSERT(msk_c0);
1258 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1259 shl_c0 = rte_bsf32(msk_c0);
1261 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1265 MLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1267 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1268 /* The routine expects parameters in memory as big-endian ones. */
1269 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1270 MLX5_MODIFICATION_TYPE_SET, error);
1274 * Convert modify-header set IPv4 DSCP action to DV specification.
1276 * @param[in,out] resource
1277 * Pointer to the modify-header resource.
1279 * Pointer to action specification.
1281 * Pointer to the error structure.
1284 * 0 on success, a negative errno value otherwise and rte_errno is set.
1287 flow_dv_convert_action_modify_ipv4_dscp
1288 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1289 const struct rte_flow_action *action,
1290 struct rte_flow_error *error)
1292 const struct rte_flow_action_set_dscp *conf =
1293 (const struct rte_flow_action_set_dscp *)(action->conf);
1294 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1295 struct rte_flow_item_ipv4 ipv4;
1296 struct rte_flow_item_ipv4 ipv4_mask;
1298 memset(&ipv4, 0, sizeof(ipv4));
1299 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1300 ipv4.hdr.type_of_service = conf->dscp;
1301 ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1303 item.mask = &ipv4_mask;
1304 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1305 MLX5_MODIFICATION_TYPE_SET, error);
1309 * Convert modify-header set IPv6 DSCP action to DV specification.
1311 * @param[in,out] resource
1312 * Pointer to the modify-header resource.
1314 * Pointer to action specification.
1316 * Pointer to the error structure.
1319 * 0 on success, a negative errno value otherwise and rte_errno is set.
1322 flow_dv_convert_action_modify_ipv6_dscp
1323 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1324 const struct rte_flow_action *action,
1325 struct rte_flow_error *error)
1327 const struct rte_flow_action_set_dscp *conf =
1328 (const struct rte_flow_action_set_dscp *)(action->conf);
1329 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1330 struct rte_flow_item_ipv6 ipv6;
1331 struct rte_flow_item_ipv6 ipv6_mask;
1333 memset(&ipv6, 0, sizeof(ipv6));
1334 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1336 * Even though the DSCP bits offset of IPv6 is not byte aligned,
1337 * rdma-core only accept the DSCP bits byte aligned start from
1338 * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1339 * bits in IPv6 case as rdma-core requires byte aligned value.
1341 ipv6.hdr.vtc_flow = conf->dscp;
1342 ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1344 item.mask = &ipv6_mask;
1345 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1346 MLX5_MODIFICATION_TYPE_SET, error);
1350 * Validate MARK item.
1353 * Pointer to the rte_eth_dev structure.
1355 * Item specification.
1357 * Attributes of flow that includes this item.
1359 * Pointer to error structure.
1362 * 0 on success, a negative errno value otherwise and rte_errno is set.
1365 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1366 const struct rte_flow_item *item,
1367 const struct rte_flow_attr *attr __rte_unused,
1368 struct rte_flow_error *error)
1370 struct mlx5_priv *priv = dev->data->dev_private;
1371 struct mlx5_dev_config *config = &priv->config;
1372 const struct rte_flow_item_mark *spec = item->spec;
1373 const struct rte_flow_item_mark *mask = item->mask;
1374 const struct rte_flow_item_mark nic_mask = {
1375 .id = priv->sh->dv_mark_mask,
1379 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1380 return rte_flow_error_set(error, ENOTSUP,
1381 RTE_FLOW_ERROR_TYPE_ITEM, item,
1382 "extended metadata feature"
1384 if (!mlx5_flow_ext_mreg_supported(dev))
1385 return rte_flow_error_set(error, ENOTSUP,
1386 RTE_FLOW_ERROR_TYPE_ITEM, item,
1387 "extended metadata register"
1388 " isn't supported");
1390 return rte_flow_error_set(error, ENOTSUP,
1391 RTE_FLOW_ERROR_TYPE_ITEM, item,
1392 "extended metadata register"
1393 " isn't available");
1394 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1398 return rte_flow_error_set(error, EINVAL,
1399 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1401 "data cannot be empty");
1402 if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1403 return rte_flow_error_set(error, EINVAL,
1404 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1406 "mark id exceeds the limit");
1409 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1410 (const uint8_t *)&nic_mask,
1411 sizeof(struct rte_flow_item_mark),
1419 * Validate META item.
1422 * Pointer to the rte_eth_dev structure.
1424 * Item specification.
1426 * Attributes of flow that includes this item.
1428 * Pointer to error structure.
1431 * 0 on success, a negative errno value otherwise and rte_errno is set.
1434 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1435 const struct rte_flow_item *item,
1436 const struct rte_flow_attr *attr,
1437 struct rte_flow_error *error)
1439 struct mlx5_priv *priv = dev->data->dev_private;
1440 struct mlx5_dev_config *config = &priv->config;
1441 const struct rte_flow_item_meta *spec = item->spec;
1442 const struct rte_flow_item_meta *mask = item->mask;
1443 struct rte_flow_item_meta nic_mask = {
1450 return rte_flow_error_set(error, EINVAL,
1451 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1453 "data cannot be empty");
1455 return rte_flow_error_set(error, EINVAL,
1456 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1457 "data cannot be zero");
1458 if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1459 if (!mlx5_flow_ext_mreg_supported(dev))
1460 return rte_flow_error_set(error, ENOTSUP,
1461 RTE_FLOW_ERROR_TYPE_ITEM, item,
1462 "extended metadata register"
1463 " isn't supported");
1464 reg = flow_dv_get_metadata_reg(dev, attr, error);
1468 return rte_flow_error_set(error, ENOTSUP,
1469 RTE_FLOW_ERROR_TYPE_ITEM, item,
1473 nic_mask.data = priv->sh->dv_meta_mask;
1476 mask = &rte_flow_item_meta_mask;
1477 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1478 (const uint8_t *)&nic_mask,
1479 sizeof(struct rte_flow_item_meta),
1485 * Validate TAG item.
1488 * Pointer to the rte_eth_dev structure.
1490 * Item specification.
1492 * Attributes of flow that includes this item.
1494 * Pointer to error structure.
1497 * 0 on success, a negative errno value otherwise and rte_errno is set.
1500 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
1501 const struct rte_flow_item *item,
1502 const struct rte_flow_attr *attr __rte_unused,
1503 struct rte_flow_error *error)
1505 const struct rte_flow_item_tag *spec = item->spec;
1506 const struct rte_flow_item_tag *mask = item->mask;
1507 const struct rte_flow_item_tag nic_mask = {
1508 .data = RTE_BE32(UINT32_MAX),
1513 if (!mlx5_flow_ext_mreg_supported(dev))
1514 return rte_flow_error_set(error, ENOTSUP,
1515 RTE_FLOW_ERROR_TYPE_ITEM, item,
1516 "extensive metadata register"
1517 " isn't supported");
1519 return rte_flow_error_set(error, EINVAL,
1520 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1522 "data cannot be empty");
1524 mask = &rte_flow_item_tag_mask;
1525 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1526 (const uint8_t *)&nic_mask,
1527 sizeof(struct rte_flow_item_tag),
1531 if (mask->index != 0xff)
1532 return rte_flow_error_set(error, EINVAL,
1533 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1534 "partial mask for tag index"
1535 " is not supported");
1536 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
1539 MLX5_ASSERT(ret != REG_NONE);
1544 * Validate vport item.
1547 * Pointer to the rte_eth_dev structure.
1549 * Item specification.
1551 * Attributes of flow that includes this item.
1552 * @param[in] item_flags
1553 * Bit-fields that holds the items detected until now.
1555 * Pointer to error structure.
1558 * 0 on success, a negative errno value otherwise and rte_errno is set.
1561 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
1562 const struct rte_flow_item *item,
1563 const struct rte_flow_attr *attr,
1564 uint64_t item_flags,
1565 struct rte_flow_error *error)
1567 const struct rte_flow_item_port_id *spec = item->spec;
1568 const struct rte_flow_item_port_id *mask = item->mask;
1569 const struct rte_flow_item_port_id switch_mask = {
1572 struct mlx5_priv *esw_priv;
1573 struct mlx5_priv *dev_priv;
1576 if (!attr->transfer)
1577 return rte_flow_error_set(error, EINVAL,
1578 RTE_FLOW_ERROR_TYPE_ITEM,
1580 "match on port id is valid only"
1581 " when transfer flag is enabled");
1582 if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
1583 return rte_flow_error_set(error, ENOTSUP,
1584 RTE_FLOW_ERROR_TYPE_ITEM, item,
1585 "multiple source ports are not"
1588 mask = &switch_mask;
1589 if (mask->id != 0xffffffff)
1590 return rte_flow_error_set(error, ENOTSUP,
1591 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1593 "no support for partial mask on"
1595 ret = mlx5_flow_item_acceptable
1596 (item, (const uint8_t *)mask,
1597 (const uint8_t *)&rte_flow_item_port_id_mask,
1598 sizeof(struct rte_flow_item_port_id),
1604 esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
1606 return rte_flow_error_set(error, rte_errno,
1607 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1608 "failed to obtain E-Switch info for"
1610 dev_priv = mlx5_dev_to_eswitch_info(dev);
1612 return rte_flow_error_set(error, rte_errno,
1613 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1615 "failed to obtain E-Switch info");
1616 if (esw_priv->domain_id != dev_priv->domain_id)
1617 return rte_flow_error_set(error, EINVAL,
1618 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1619 "cannot match on a port from a"
1620 " different E-Switch");
1625 * Validate GTP item.
1628 * Pointer to the rte_eth_dev structure.
1630 * Item specification.
1631 * @param[in] item_flags
1632 * Bit-fields that holds the items detected until now.
1634 * Pointer to error structure.
1637 * 0 on success, a negative errno value otherwise and rte_errno is set.
1640 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
1641 const struct rte_flow_item *item,
1642 uint64_t item_flags,
1643 struct rte_flow_error *error)
1645 struct mlx5_priv *priv = dev->data->dev_private;
1646 const struct rte_flow_item_gtp *mask = item->mask;
1647 const struct rte_flow_item_gtp nic_mask = {
1649 .teid = RTE_BE32(0xffffffff),
1652 if (!priv->config.hca_attr.tunnel_stateless_gtp)
1653 return rte_flow_error_set(error, ENOTSUP,
1654 RTE_FLOW_ERROR_TYPE_ITEM, item,
1655 "GTP support is not enabled");
1656 if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
1657 return rte_flow_error_set(error, ENOTSUP,
1658 RTE_FLOW_ERROR_TYPE_ITEM, item,
1659 "multiple tunnel layers not"
1661 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
1662 return rte_flow_error_set(error, EINVAL,
1663 RTE_FLOW_ERROR_TYPE_ITEM, item,
1664 "no outer UDP layer found");
1666 mask = &rte_flow_item_gtp_mask;
1667 return mlx5_flow_item_acceptable
1668 (item, (const uint8_t *)mask,
1669 (const uint8_t *)&nic_mask,
1670 sizeof(struct rte_flow_item_gtp),
1675 * Validate the pop VLAN action.
1678 * Pointer to the rte_eth_dev structure.
1679 * @param[in] action_flags
1680 * Holds the actions detected until now.
1682 * Pointer to the pop vlan action.
1683 * @param[in] item_flags
1684 * The items found in this flow rule.
1686 * Pointer to flow attributes.
1688 * Pointer to error structure.
1691 * 0 on success, a negative errno value otherwise and rte_errno is set.
1694 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
1695 uint64_t action_flags,
1696 const struct rte_flow_action *action,
1697 uint64_t item_flags,
1698 const struct rte_flow_attr *attr,
1699 struct rte_flow_error *error)
1701 struct mlx5_priv *priv = dev->data->dev_private;
1705 if (!priv->sh->pop_vlan_action)
1706 return rte_flow_error_set(error, ENOTSUP,
1707 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1709 "pop vlan action is not supported");
1711 return rte_flow_error_set(error, ENOTSUP,
1712 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1714 "pop vlan action not supported for "
1716 if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
1717 return rte_flow_error_set(error, ENOTSUP,
1718 RTE_FLOW_ERROR_TYPE_ACTION, action,
1719 "no support for multiple VLAN "
1721 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1722 return rte_flow_error_set(error, ENOTSUP,
1723 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1725 "cannot pop vlan without a "
1726 "match on (outer) vlan in the flow");
1727 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1728 return rte_flow_error_set(error, EINVAL,
1729 RTE_FLOW_ERROR_TYPE_ACTION, action,
1730 "wrong action order, port_id should "
1731 "be after pop VLAN action");
1736 * Get VLAN default info from vlan match info.
1739 * the list of item specifications.
1741 * pointer VLAN info to fill to.
1744 * 0 on success, a negative errno value otherwise and rte_errno is set.
1747 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
1748 struct rte_vlan_hdr *vlan)
1750 const struct rte_flow_item_vlan nic_mask = {
1751 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
1752 MLX5DV_FLOW_VLAN_VID_MASK),
1753 .inner_type = RTE_BE16(0xffff),
1758 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
1759 int type = items->type;
1761 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
1762 type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
1765 if (items->type != RTE_FLOW_ITEM_TYPE_END) {
1766 const struct rte_flow_item_vlan *vlan_m = items->mask;
1767 const struct rte_flow_item_vlan *vlan_v = items->spec;
1771 /* Only full match values are accepted */
1772 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
1773 MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
1774 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
1776 rte_be_to_cpu_16(vlan_v->tci &
1777 MLX5DV_FLOW_VLAN_PCP_MASK_BE);
1779 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
1780 MLX5DV_FLOW_VLAN_VID_MASK_BE) {
1781 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
1783 rte_be_to_cpu_16(vlan_v->tci &
1784 MLX5DV_FLOW_VLAN_VID_MASK_BE);
1786 if (vlan_m->inner_type == nic_mask.inner_type)
1787 vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
1788 vlan_m->inner_type);
1793 * Validate the push VLAN action.
1795 * @param[in] action_flags
1796 * Holds the actions detected until now.
1797 * @param[in] item_flags
1798 * The items found in this flow rule.
1800 * Pointer to the action structure.
1802 * Pointer to flow attributes
1804 * Pointer to error structure.
1807 * 0 on success, a negative errno value otherwise and rte_errno is set.
1810 flow_dv_validate_action_push_vlan(uint64_t action_flags,
1811 uint64_t item_flags __rte_unused,
1812 const struct rte_flow_action *action,
1813 const struct rte_flow_attr *attr,
1814 struct rte_flow_error *error)
1816 const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
1818 if (!attr->transfer && attr->ingress)
1819 return rte_flow_error_set(error, ENOTSUP,
1820 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1822 "push VLAN action not supported for "
1824 if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
1825 push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
1826 return rte_flow_error_set(error, EINVAL,
1827 RTE_FLOW_ERROR_TYPE_ACTION, action,
1828 "invalid vlan ethertype");
1829 if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
1830 return rte_flow_error_set(error, ENOTSUP,
1831 RTE_FLOW_ERROR_TYPE_ACTION, action,
1832 "no support for multiple VLAN "
1834 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1835 return rte_flow_error_set(error, EINVAL,
1836 RTE_FLOW_ERROR_TYPE_ACTION, action,
1837 "wrong action order, port_id should "
1838 "be after push VLAN");
1844 * Validate the set VLAN PCP.
1846 * @param[in] action_flags
1847 * Holds the actions detected until now.
1848 * @param[in] actions
1849 * Pointer to the list of actions remaining in the flow rule.
1851 * Pointer to error structure.
1854 * 0 on success, a negative errno value otherwise and rte_errno is set.
1857 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
1858 const struct rte_flow_action actions[],
1859 struct rte_flow_error *error)
1861 const struct rte_flow_action *action = actions;
1862 const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
1864 if (conf->vlan_pcp > 7)
1865 return rte_flow_error_set(error, EINVAL,
1866 RTE_FLOW_ERROR_TYPE_ACTION, action,
1867 "VLAN PCP value is too big");
1868 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
1869 return rte_flow_error_set(error, ENOTSUP,
1870 RTE_FLOW_ERROR_TYPE_ACTION, action,
1871 "set VLAN PCP action must follow "
1872 "the push VLAN action");
1873 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
1874 return rte_flow_error_set(error, ENOTSUP,
1875 RTE_FLOW_ERROR_TYPE_ACTION, action,
1876 "Multiple VLAN PCP modification are "
1878 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1879 return rte_flow_error_set(error, EINVAL,
1880 RTE_FLOW_ERROR_TYPE_ACTION, action,
1881 "wrong action order, port_id should "
1882 "be after set VLAN PCP");
1887 * Validate the set VLAN VID.
1889 * @param[in] item_flags
1890 * Holds the items detected in this rule.
1891 * @param[in] action_flags
1892 * Holds the actions detected until now.
1893 * @param[in] actions
1894 * Pointer to the list of actions remaining in the flow rule.
1896 * Pointer to error structure.
1899 * 0 on success, a negative errno value otherwise and rte_errno is set.
1902 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
1903 uint64_t action_flags,
1904 const struct rte_flow_action actions[],
1905 struct rte_flow_error *error)
1907 const struct rte_flow_action *action = actions;
1908 const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
1910 if (conf->vlan_vid > RTE_BE16(0xFFE))
1911 return rte_flow_error_set(error, EINVAL,
1912 RTE_FLOW_ERROR_TYPE_ACTION, action,
1913 "VLAN VID value is too big");
1914 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
1915 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1916 return rte_flow_error_set(error, ENOTSUP,
1917 RTE_FLOW_ERROR_TYPE_ACTION, action,
1918 "set VLAN VID action must follow push"
1919 " VLAN action or match on VLAN item");
1920 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
1921 return rte_flow_error_set(error, ENOTSUP,
1922 RTE_FLOW_ERROR_TYPE_ACTION, action,
1923 "Multiple VLAN VID modifications are "
1925 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1926 return rte_flow_error_set(error, EINVAL,
1927 RTE_FLOW_ERROR_TYPE_ACTION, action,
1928 "wrong action order, port_id should "
1929 "be after set VLAN VID");
1934 * Validate the FLAG action.
1937 * Pointer to the rte_eth_dev structure.
1938 * @param[in] action_flags
1939 * Holds the actions detected until now.
1941 * Pointer to flow attributes
1943 * Pointer to error structure.
1946 * 0 on success, a negative errno value otherwise and rte_errno is set.
1949 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
1950 uint64_t action_flags,
1951 const struct rte_flow_attr *attr,
1952 struct rte_flow_error *error)
1954 struct mlx5_priv *priv = dev->data->dev_private;
1955 struct mlx5_dev_config *config = &priv->config;
1958 /* Fall back if no extended metadata register support. */
1959 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1960 return mlx5_flow_validate_action_flag(action_flags, attr,
1962 /* Extensive metadata mode requires registers. */
1963 if (!mlx5_flow_ext_mreg_supported(dev))
1964 return rte_flow_error_set(error, ENOTSUP,
1965 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1966 "no metadata registers "
1967 "to support flag action");
1968 if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
1969 return rte_flow_error_set(error, ENOTSUP,
1970 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1971 "extended metadata register"
1972 " isn't available");
1973 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1976 MLX5_ASSERT(ret > 0);
1977 if (action_flags & MLX5_FLOW_ACTION_MARK)
1978 return rte_flow_error_set(error, EINVAL,
1979 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1980 "can't mark and flag in same flow");
1981 if (action_flags & MLX5_FLOW_ACTION_FLAG)
1982 return rte_flow_error_set(error, EINVAL,
1983 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1985 " actions in same flow");
1990 * Validate MARK action.
1993 * Pointer to the rte_eth_dev structure.
1995 * Pointer to action.
1996 * @param[in] action_flags
1997 * Holds the actions detected until now.
1999 * Pointer to flow attributes
2001 * Pointer to error structure.
2004 * 0 on success, a negative errno value otherwise and rte_errno is set.
2007 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
2008 const struct rte_flow_action *action,
2009 uint64_t action_flags,
2010 const struct rte_flow_attr *attr,
2011 struct rte_flow_error *error)
2013 struct mlx5_priv *priv = dev->data->dev_private;
2014 struct mlx5_dev_config *config = &priv->config;
2015 const struct rte_flow_action_mark *mark = action->conf;
2018 /* Fall back if no extended metadata register support. */
2019 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2020 return mlx5_flow_validate_action_mark(action, action_flags,
2022 /* Extensive metadata mode requires registers. */
2023 if (!mlx5_flow_ext_mreg_supported(dev))
2024 return rte_flow_error_set(error, ENOTSUP,
2025 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2026 "no metadata registers "
2027 "to support mark action");
2028 if (!priv->sh->dv_mark_mask)
2029 return rte_flow_error_set(error, ENOTSUP,
2030 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2031 "extended metadata register"
2032 " isn't available");
2033 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2036 MLX5_ASSERT(ret > 0);
2038 return rte_flow_error_set(error, EINVAL,
2039 RTE_FLOW_ERROR_TYPE_ACTION, action,
2040 "configuration cannot be null");
2041 if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
2042 return rte_flow_error_set(error, EINVAL,
2043 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2045 "mark id exceeds the limit");
2046 if (action_flags & MLX5_FLOW_ACTION_FLAG)
2047 return rte_flow_error_set(error, EINVAL,
2048 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2049 "can't flag and mark in same flow");
2050 if (action_flags & MLX5_FLOW_ACTION_MARK)
2051 return rte_flow_error_set(error, EINVAL,
2052 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2053 "can't have 2 mark actions in same"
2059 * Validate SET_META action.
2062 * Pointer to the rte_eth_dev structure.
2064 * Pointer to the action structure.
2065 * @param[in] action_flags
2066 * Holds the actions detected until now.
2068 * Pointer to flow attributes
2070 * Pointer to error structure.
2073 * 0 on success, a negative errno value otherwise and rte_errno is set.
2076 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
2077 const struct rte_flow_action *action,
2078 uint64_t action_flags __rte_unused,
2079 const struct rte_flow_attr *attr,
2080 struct rte_flow_error *error)
2082 const struct rte_flow_action_set_meta *conf;
2083 uint32_t nic_mask = UINT32_MAX;
2086 if (!mlx5_flow_ext_mreg_supported(dev))
2087 return rte_flow_error_set(error, ENOTSUP,
2088 RTE_FLOW_ERROR_TYPE_ACTION, action,
2089 "extended metadata register"
2090 " isn't supported");
2091 reg = flow_dv_get_metadata_reg(dev, attr, error);
2094 if (reg != REG_A && reg != REG_B) {
2095 struct mlx5_priv *priv = dev->data->dev_private;
2097 nic_mask = priv->sh->dv_meta_mask;
2099 if (!(action->conf))
2100 return rte_flow_error_set(error, EINVAL,
2101 RTE_FLOW_ERROR_TYPE_ACTION, action,
2102 "configuration cannot be null");
2103 conf = (const struct rte_flow_action_set_meta *)action->conf;
2105 return rte_flow_error_set(error, EINVAL,
2106 RTE_FLOW_ERROR_TYPE_ACTION, action,
2107 "zero mask doesn't have any effect");
2108 if (conf->mask & ~nic_mask)
2109 return rte_flow_error_set(error, EINVAL,
2110 RTE_FLOW_ERROR_TYPE_ACTION, action,
2111 "meta data must be within reg C0");
2116 * Validate SET_TAG action.
2119 * Pointer to the rte_eth_dev structure.
2121 * Pointer to the action structure.
2122 * @param[in] action_flags
2123 * Holds the actions detected until now.
2125 * Pointer to flow attributes
2127 * Pointer to error structure.
2130 * 0 on success, a negative errno value otherwise and rte_errno is set.
2133 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
2134 const struct rte_flow_action *action,
2135 uint64_t action_flags,
2136 const struct rte_flow_attr *attr,
2137 struct rte_flow_error *error)
2139 const struct rte_flow_action_set_tag *conf;
2140 const uint64_t terminal_action_flags =
2141 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
2142 MLX5_FLOW_ACTION_RSS;
2145 if (!mlx5_flow_ext_mreg_supported(dev))
2146 return rte_flow_error_set(error, ENOTSUP,
2147 RTE_FLOW_ERROR_TYPE_ACTION, action,
2148 "extensive metadata register"
2149 " isn't supported");
2150 if (!(action->conf))
2151 return rte_flow_error_set(error, EINVAL,
2152 RTE_FLOW_ERROR_TYPE_ACTION, action,
2153 "configuration cannot be null");
2154 conf = (const struct rte_flow_action_set_tag *)action->conf;
2156 return rte_flow_error_set(error, EINVAL,
2157 RTE_FLOW_ERROR_TYPE_ACTION, action,
2158 "zero mask doesn't have any effect");
2159 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
2162 if (!attr->transfer && attr->ingress &&
2163 (action_flags & terminal_action_flags))
2164 return rte_flow_error_set(error, EINVAL,
2165 RTE_FLOW_ERROR_TYPE_ACTION, action,
2166 "set_tag has no effect"
2167 " with terminal actions");
2172 * Validate count action.
2175 * Pointer to rte_eth_dev structure.
2177 * Pointer to error structure.
2180 * 0 on success, a negative errno value otherwise and rte_errno is set.
2183 flow_dv_validate_action_count(struct rte_eth_dev *dev,
2184 struct rte_flow_error *error)
2186 struct mlx5_priv *priv = dev->data->dev_private;
2188 if (!priv->config.devx)
2190 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
2194 return rte_flow_error_set
2196 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2198 "count action not supported");
2202 * Validate the L2 encap action.
2204 * @param[in] action_flags
2205 * Holds the actions detected until now.
2207 * Pointer to the action structure.
2209 * Pointer to error structure.
2212 * 0 on success, a negative errno value otherwise and rte_errno is set.
2215 flow_dv_validate_action_l2_encap(uint64_t action_flags,
2216 const struct rte_flow_action *action,
2217 struct rte_flow_error *error)
2219 if (!(action->conf))
2220 return rte_flow_error_set(error, EINVAL,
2221 RTE_FLOW_ERROR_TYPE_ACTION, action,
2222 "configuration cannot be null");
2223 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
2224 return rte_flow_error_set(error, EINVAL,
2225 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2226 "can only have a single encap action "
2232 * Validate a decap action.
2234 * @param[in] action_flags
2235 * Holds the actions detected until now.
2237 * Pointer to flow attributes
2239 * Pointer to error structure.
2242 * 0 on success, a negative errno value otherwise and rte_errno is set.
2245 flow_dv_validate_action_decap(uint64_t action_flags,
2246 const struct rte_flow_attr *attr,
2247 struct rte_flow_error *error)
2249 if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
2250 return rte_flow_error_set(error, ENOTSUP,
2251 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2253 MLX5_FLOW_ACTION_DECAP ? "can only "
2254 "have a single decap action" : "decap "
2255 "after encap is not supported");
2256 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
2257 return rte_flow_error_set(error, EINVAL,
2258 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2259 "can't have decap action after"
2262 return rte_flow_error_set(error, ENOTSUP,
2263 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2265 "decap action not supported for "
2270 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
2273 * Validate the raw encap and decap actions.
2276 * Pointer to the decap action.
2278 * Pointer to the encap action.
2280 * Pointer to flow attributes
2281 * @param[in/out] action_flags
2282 * Holds the actions detected until now.
2283 * @param[out] actions_n
2284 * pointer to the number of actions counter.
2286 * Pointer to error structure.
2289 * 0 on success, a negative errno value otherwise and rte_errno is set.
2292 flow_dv_validate_action_raw_encap_decap
2293 (const struct rte_flow_action_raw_decap *decap,
2294 const struct rte_flow_action_raw_encap *encap,
2295 const struct rte_flow_attr *attr, uint64_t *action_flags,
2296 int *actions_n, struct rte_flow_error *error)
2300 if (encap && (!encap->size || !encap->data))
2301 return rte_flow_error_set(error, EINVAL,
2302 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2303 "raw encap data cannot be empty");
2304 if (decap && encap) {
2305 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
2306 encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
2309 else if (encap->size <=
2310 MLX5_ENCAPSULATION_DECISION_SIZE &&
2312 MLX5_ENCAPSULATION_DECISION_SIZE)
2315 else if (encap->size >
2316 MLX5_ENCAPSULATION_DECISION_SIZE &&
2318 MLX5_ENCAPSULATION_DECISION_SIZE)
2319 /* 2 L2 actions: encap and decap. */
2322 return rte_flow_error_set(error,
2324 RTE_FLOW_ERROR_TYPE_ACTION,
2325 NULL, "unsupported too small "
2326 "raw decap and too small raw "
2327 "encap combination");
2330 ret = flow_dv_validate_action_decap(*action_flags, attr, error);
2333 *action_flags |= MLX5_FLOW_ACTION_DECAP;
2337 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
2338 return rte_flow_error_set(error, ENOTSUP,
2339 RTE_FLOW_ERROR_TYPE_ACTION,
2341 "small raw encap size");
2342 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
2343 return rte_flow_error_set(error, EINVAL,
2344 RTE_FLOW_ERROR_TYPE_ACTION,
2346 "more than one encap action");
2347 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
2354 * Find existing encap/decap resource or create and register a new one.
2356 * @param[in, out] dev
2357 * Pointer to rte_eth_dev structure.
2358 * @param[in, out] resource
2359 * Pointer to encap/decap resource.
2360 * @parm[in, out] dev_flow
2361 * Pointer to the dev_flow.
2363 * pointer to error structure.
2366 * 0 on success otherwise -errno and errno is set.
2369 flow_dv_encap_decap_resource_register
2370 (struct rte_eth_dev *dev,
2371 struct mlx5_flow_dv_encap_decap_resource *resource,
2372 struct mlx5_flow *dev_flow,
2373 struct rte_flow_error *error)
2375 struct mlx5_priv *priv = dev->data->dev_private;
2376 struct mlx5_ibv_shared *sh = priv->sh;
2377 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2378 struct mlx5dv_dr_domain *domain;
2380 resource->flags = dev_flow->group ? 0 : 1;
2381 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2382 domain = sh->fdb_domain;
2383 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2384 domain = sh->rx_domain;
2386 domain = sh->tx_domain;
2387 /* Lookup a matching resource from cache. */
2388 LIST_FOREACH(cache_resource, &sh->encaps_decaps, next) {
2389 if (resource->reformat_type == cache_resource->reformat_type &&
2390 resource->ft_type == cache_resource->ft_type &&
2391 resource->flags == cache_resource->flags &&
2392 resource->size == cache_resource->size &&
2393 !memcmp((const void *)resource->buf,
2394 (const void *)cache_resource->buf,
2396 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d++",
2397 (void *)cache_resource,
2398 rte_atomic32_read(&cache_resource->refcnt));
2399 rte_atomic32_inc(&cache_resource->refcnt);
2400 dev_flow->dv.encap_decap = cache_resource;
2404 /* Register new encap/decap resource. */
2405 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
2406 if (!cache_resource)
2407 return rte_flow_error_set(error, ENOMEM,
2408 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2409 "cannot allocate resource memory");
2410 *cache_resource = *resource;
2411 cache_resource->verbs_action =
2412 mlx5_glue->dv_create_flow_action_packet_reformat
2413 (sh->ctx, cache_resource->reformat_type,
2414 cache_resource->ft_type, domain, cache_resource->flags,
2415 cache_resource->size,
2416 (cache_resource->size ? cache_resource->buf : NULL));
2417 if (!cache_resource->verbs_action) {
2418 rte_free(cache_resource);
2419 return rte_flow_error_set(error, ENOMEM,
2420 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2421 NULL, "cannot create action");
2423 rte_atomic32_init(&cache_resource->refcnt);
2424 rte_atomic32_inc(&cache_resource->refcnt);
2425 LIST_INSERT_HEAD(&sh->encaps_decaps, cache_resource, next);
2426 dev_flow->dv.encap_decap = cache_resource;
2427 DRV_LOG(DEBUG, "new encap/decap resource %p: refcnt %d++",
2428 (void *)cache_resource,
2429 rte_atomic32_read(&cache_resource->refcnt));
2434 * Find existing table jump resource or create and register a new one.
2436 * @param[in, out] dev
2437 * Pointer to rte_eth_dev structure.
2438 * @param[in, out] tbl
2439 * Pointer to flow table resource.
2440 * @parm[in, out] dev_flow
2441 * Pointer to the dev_flow.
2443 * pointer to error structure.
2446 * 0 on success otherwise -errno and errno is set.
2449 flow_dv_jump_tbl_resource_register
2450 (struct rte_eth_dev *dev __rte_unused,
2451 struct mlx5_flow_tbl_resource *tbl,
2452 struct mlx5_flow *dev_flow,
2453 struct rte_flow_error *error)
2455 struct mlx5_flow_tbl_data_entry *tbl_data =
2456 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
2460 cnt = rte_atomic32_read(&tbl_data->jump.refcnt);
2462 tbl_data->jump.action =
2463 mlx5_glue->dr_create_flow_action_dest_flow_tbl
2465 if (!tbl_data->jump.action)
2466 return rte_flow_error_set(error, ENOMEM,
2467 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2468 NULL, "cannot create jump action");
2469 DRV_LOG(DEBUG, "new jump table resource %p: refcnt %d++",
2470 (void *)&tbl_data->jump, cnt);
2472 MLX5_ASSERT(tbl_data->jump.action);
2473 DRV_LOG(DEBUG, "existed jump table resource %p: refcnt %d++",
2474 (void *)&tbl_data->jump, cnt);
2476 rte_atomic32_inc(&tbl_data->jump.refcnt);
2477 dev_flow->dv.jump = &tbl_data->jump;
2482 * Find existing table port ID resource or create and register a new one.
2484 * @param[in, out] dev
2485 * Pointer to rte_eth_dev structure.
2486 * @param[in, out] resource
2487 * Pointer to port ID action resource.
2488 * @parm[in, out] dev_flow
2489 * Pointer to the dev_flow.
2491 * pointer to error structure.
2494 * 0 on success otherwise -errno and errno is set.
2497 flow_dv_port_id_action_resource_register
2498 (struct rte_eth_dev *dev,
2499 struct mlx5_flow_dv_port_id_action_resource *resource,
2500 struct mlx5_flow *dev_flow,
2501 struct rte_flow_error *error)
2503 struct mlx5_priv *priv = dev->data->dev_private;
2504 struct mlx5_ibv_shared *sh = priv->sh;
2505 struct mlx5_flow_dv_port_id_action_resource *cache_resource;
2507 /* Lookup a matching resource from cache. */
2508 LIST_FOREACH(cache_resource, &sh->port_id_action_list, next) {
2509 if (resource->port_id == cache_resource->port_id) {
2510 DRV_LOG(DEBUG, "port id action resource resource %p: "
2512 (void *)cache_resource,
2513 rte_atomic32_read(&cache_resource->refcnt));
2514 rte_atomic32_inc(&cache_resource->refcnt);
2515 dev_flow->dv.port_id_action = cache_resource;
2519 /* Register new port id action resource. */
2520 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
2521 if (!cache_resource)
2522 return rte_flow_error_set(error, ENOMEM,
2523 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2524 "cannot allocate resource memory");
2525 *cache_resource = *resource;
2527 * Depending on rdma_core version the glue routine calls
2528 * either mlx5dv_dr_action_create_dest_ib_port(domain, ibv_port)
2529 * or mlx5dv_dr_action_create_dest_vport(domain, vport_id).
2531 cache_resource->action =
2532 mlx5_glue->dr_create_flow_action_dest_port
2533 (priv->sh->fdb_domain, resource->port_id);
2534 if (!cache_resource->action) {
2535 rte_free(cache_resource);
2536 return rte_flow_error_set(error, ENOMEM,
2537 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2538 NULL, "cannot create action");
2540 rte_atomic32_init(&cache_resource->refcnt);
2541 rte_atomic32_inc(&cache_resource->refcnt);
2542 LIST_INSERT_HEAD(&sh->port_id_action_list, cache_resource, next);
2543 dev_flow->dv.port_id_action = cache_resource;
2544 DRV_LOG(DEBUG, "new port id action resource %p: refcnt %d++",
2545 (void *)cache_resource,
2546 rte_atomic32_read(&cache_resource->refcnt));
2551 * Find existing push vlan resource or create and register a new one.
2553 * @param [in, out] dev
2554 * Pointer to rte_eth_dev structure.
2555 * @param[in, out] resource
2556 * Pointer to port ID action resource.
2557 * @parm[in, out] dev_flow
2558 * Pointer to the dev_flow.
2560 * pointer to error structure.
2563 * 0 on success otherwise -errno and errno is set.
2566 flow_dv_push_vlan_action_resource_register
2567 (struct rte_eth_dev *dev,
2568 struct mlx5_flow_dv_push_vlan_action_resource *resource,
2569 struct mlx5_flow *dev_flow,
2570 struct rte_flow_error *error)
2572 struct mlx5_priv *priv = dev->data->dev_private;
2573 struct mlx5_ibv_shared *sh = priv->sh;
2574 struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
2575 struct mlx5dv_dr_domain *domain;
2577 /* Lookup a matching resource from cache. */
2578 LIST_FOREACH(cache_resource, &sh->push_vlan_action_list, next) {
2579 if (resource->vlan_tag == cache_resource->vlan_tag &&
2580 resource->ft_type == cache_resource->ft_type) {
2581 DRV_LOG(DEBUG, "push-VLAN action resource resource %p: "
2583 (void *)cache_resource,
2584 rte_atomic32_read(&cache_resource->refcnt));
2585 rte_atomic32_inc(&cache_resource->refcnt);
2586 dev_flow->dv.push_vlan_res = cache_resource;
2590 /* Register new push_vlan action resource. */
2591 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
2592 if (!cache_resource)
2593 return rte_flow_error_set(error, ENOMEM,
2594 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2595 "cannot allocate resource memory");
2596 *cache_resource = *resource;
2597 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2598 domain = sh->fdb_domain;
2599 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2600 domain = sh->rx_domain;
2602 domain = sh->tx_domain;
2603 cache_resource->action =
2604 mlx5_glue->dr_create_flow_action_push_vlan(domain,
2605 resource->vlan_tag);
2606 if (!cache_resource->action) {
2607 rte_free(cache_resource);
2608 return rte_flow_error_set(error, ENOMEM,
2609 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2610 NULL, "cannot create action");
2612 rte_atomic32_init(&cache_resource->refcnt);
2613 rte_atomic32_inc(&cache_resource->refcnt);
2614 LIST_INSERT_HEAD(&sh->push_vlan_action_list, cache_resource, next);
2615 dev_flow->dv.push_vlan_res = cache_resource;
2616 DRV_LOG(DEBUG, "new push vlan action resource %p: refcnt %d++",
2617 (void *)cache_resource,
2618 rte_atomic32_read(&cache_resource->refcnt));
2622 * Get the size of specific rte_flow_item_type
2624 * @param[in] item_type
2625 * Tested rte_flow_item_type.
2628 * sizeof struct item_type, 0 if void or irrelevant.
2631 flow_dv_get_item_len(const enum rte_flow_item_type item_type)
2635 switch (item_type) {
2636 case RTE_FLOW_ITEM_TYPE_ETH:
2637 retval = sizeof(struct rte_flow_item_eth);
2639 case RTE_FLOW_ITEM_TYPE_VLAN:
2640 retval = sizeof(struct rte_flow_item_vlan);
2642 case RTE_FLOW_ITEM_TYPE_IPV4:
2643 retval = sizeof(struct rte_flow_item_ipv4);
2645 case RTE_FLOW_ITEM_TYPE_IPV6:
2646 retval = sizeof(struct rte_flow_item_ipv6);
2648 case RTE_FLOW_ITEM_TYPE_UDP:
2649 retval = sizeof(struct rte_flow_item_udp);
2651 case RTE_FLOW_ITEM_TYPE_TCP:
2652 retval = sizeof(struct rte_flow_item_tcp);
2654 case RTE_FLOW_ITEM_TYPE_VXLAN:
2655 retval = sizeof(struct rte_flow_item_vxlan);
2657 case RTE_FLOW_ITEM_TYPE_GRE:
2658 retval = sizeof(struct rte_flow_item_gre);
2660 case RTE_FLOW_ITEM_TYPE_NVGRE:
2661 retval = sizeof(struct rte_flow_item_nvgre);
2663 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2664 retval = sizeof(struct rte_flow_item_vxlan_gpe);
2666 case RTE_FLOW_ITEM_TYPE_MPLS:
2667 retval = sizeof(struct rte_flow_item_mpls);
2669 case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
2677 #define MLX5_ENCAP_IPV4_VERSION 0x40
2678 #define MLX5_ENCAP_IPV4_IHL_MIN 0x05
2679 #define MLX5_ENCAP_IPV4_TTL_DEF 0x40
2680 #define MLX5_ENCAP_IPV6_VTC_FLOW 0x60000000
2681 #define MLX5_ENCAP_IPV6_HOP_LIMIT 0xff
2682 #define MLX5_ENCAP_VXLAN_FLAGS 0x08000000
2683 #define MLX5_ENCAP_VXLAN_GPE_FLAGS 0x04
2686 * Convert the encap action data from list of rte_flow_item to raw buffer
2689 * Pointer to rte_flow_item objects list.
2691 * Pointer to the output buffer.
2693 * Pointer to the output buffer size.
2695 * Pointer to the error structure.
2698 * 0 on success, a negative errno value otherwise and rte_errno is set.
2701 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
2702 size_t *size, struct rte_flow_error *error)
2704 struct rte_ether_hdr *eth = NULL;
2705 struct rte_vlan_hdr *vlan = NULL;
2706 struct rte_ipv4_hdr *ipv4 = NULL;
2707 struct rte_ipv6_hdr *ipv6 = NULL;
2708 struct rte_udp_hdr *udp = NULL;
2709 struct rte_vxlan_hdr *vxlan = NULL;
2710 struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
2711 struct rte_gre_hdr *gre = NULL;
2713 size_t temp_size = 0;
2716 return rte_flow_error_set(error, EINVAL,
2717 RTE_FLOW_ERROR_TYPE_ACTION,
2718 NULL, "invalid empty data");
2719 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2720 len = flow_dv_get_item_len(items->type);
2721 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
2722 return rte_flow_error_set(error, EINVAL,
2723 RTE_FLOW_ERROR_TYPE_ACTION,
2724 (void *)items->type,
2725 "items total size is too big"
2726 " for encap action");
2727 rte_memcpy((void *)&buf[temp_size], items->spec, len);
2728 switch (items->type) {
2729 case RTE_FLOW_ITEM_TYPE_ETH:
2730 eth = (struct rte_ether_hdr *)&buf[temp_size];
2732 case RTE_FLOW_ITEM_TYPE_VLAN:
2733 vlan = (struct rte_vlan_hdr *)&buf[temp_size];
2735 return rte_flow_error_set(error, EINVAL,
2736 RTE_FLOW_ERROR_TYPE_ACTION,
2737 (void *)items->type,
2738 "eth header not found");
2739 if (!eth->ether_type)
2740 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
2742 case RTE_FLOW_ITEM_TYPE_IPV4:
2743 ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
2745 return rte_flow_error_set(error, EINVAL,
2746 RTE_FLOW_ERROR_TYPE_ACTION,
2747 (void *)items->type,
2748 "neither eth nor vlan"
2750 if (vlan && !vlan->eth_proto)
2751 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2752 else if (eth && !eth->ether_type)
2753 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2754 if (!ipv4->version_ihl)
2755 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
2756 MLX5_ENCAP_IPV4_IHL_MIN;
2757 if (!ipv4->time_to_live)
2758 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
2760 case RTE_FLOW_ITEM_TYPE_IPV6:
2761 ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
2763 return rte_flow_error_set(error, EINVAL,
2764 RTE_FLOW_ERROR_TYPE_ACTION,
2765 (void *)items->type,
2766 "neither eth nor vlan"
2768 if (vlan && !vlan->eth_proto)
2769 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2770 else if (eth && !eth->ether_type)
2771 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2772 if (!ipv6->vtc_flow)
2774 RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
2775 if (!ipv6->hop_limits)
2776 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
2778 case RTE_FLOW_ITEM_TYPE_UDP:
2779 udp = (struct rte_udp_hdr *)&buf[temp_size];
2781 return rte_flow_error_set(error, EINVAL,
2782 RTE_FLOW_ERROR_TYPE_ACTION,
2783 (void *)items->type,
2784 "ip header not found");
2785 if (ipv4 && !ipv4->next_proto_id)
2786 ipv4->next_proto_id = IPPROTO_UDP;
2787 else if (ipv6 && !ipv6->proto)
2788 ipv6->proto = IPPROTO_UDP;
2790 case RTE_FLOW_ITEM_TYPE_VXLAN:
2791 vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
2793 return rte_flow_error_set(error, EINVAL,
2794 RTE_FLOW_ERROR_TYPE_ACTION,
2795 (void *)items->type,
2796 "udp header not found");
2798 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
2799 if (!vxlan->vx_flags)
2801 RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
2803 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2804 vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
2806 return rte_flow_error_set(error, EINVAL,
2807 RTE_FLOW_ERROR_TYPE_ACTION,
2808 (void *)items->type,
2809 "udp header not found");
2810 if (!vxlan_gpe->proto)
2811 return rte_flow_error_set(error, EINVAL,
2812 RTE_FLOW_ERROR_TYPE_ACTION,
2813 (void *)items->type,
2814 "next protocol not found");
2817 RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
2818 if (!vxlan_gpe->vx_flags)
2819 vxlan_gpe->vx_flags =
2820 MLX5_ENCAP_VXLAN_GPE_FLAGS;
2822 case RTE_FLOW_ITEM_TYPE_GRE:
2823 case RTE_FLOW_ITEM_TYPE_NVGRE:
2824 gre = (struct rte_gre_hdr *)&buf[temp_size];
2826 return rte_flow_error_set(error, EINVAL,
2827 RTE_FLOW_ERROR_TYPE_ACTION,
2828 (void *)items->type,
2829 "next protocol not found");
2831 return rte_flow_error_set(error, EINVAL,
2832 RTE_FLOW_ERROR_TYPE_ACTION,
2833 (void *)items->type,
2834 "ip header not found");
2835 if (ipv4 && !ipv4->next_proto_id)
2836 ipv4->next_proto_id = IPPROTO_GRE;
2837 else if (ipv6 && !ipv6->proto)
2838 ipv6->proto = IPPROTO_GRE;
2840 case RTE_FLOW_ITEM_TYPE_VOID:
2843 return rte_flow_error_set(error, EINVAL,
2844 RTE_FLOW_ERROR_TYPE_ACTION,
2845 (void *)items->type,
2846 "unsupported item type");
2856 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
2858 struct rte_ether_hdr *eth = NULL;
2859 struct rte_vlan_hdr *vlan = NULL;
2860 struct rte_ipv6_hdr *ipv6 = NULL;
2861 struct rte_udp_hdr *udp = NULL;
2865 eth = (struct rte_ether_hdr *)data;
2866 next_hdr = (char *)(eth + 1);
2867 proto = RTE_BE16(eth->ether_type);
2870 while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
2871 vlan = (struct rte_vlan_hdr *)next_hdr;
2872 proto = RTE_BE16(vlan->eth_proto);
2873 next_hdr += sizeof(struct rte_vlan_hdr);
2876 /* HW calculates IPv4 csum. no need to proceed */
2877 if (proto == RTE_ETHER_TYPE_IPV4)
2880 /* non IPv4/IPv6 header. not supported */
2881 if (proto != RTE_ETHER_TYPE_IPV6) {
2882 return rte_flow_error_set(error, ENOTSUP,
2883 RTE_FLOW_ERROR_TYPE_ACTION,
2884 NULL, "Cannot offload non IPv4/IPv6");
2887 ipv6 = (struct rte_ipv6_hdr *)next_hdr;
2889 /* ignore non UDP */
2890 if (ipv6->proto != IPPROTO_UDP)
2893 udp = (struct rte_udp_hdr *)(ipv6 + 1);
2894 udp->dgram_cksum = 0;
2900 * Convert L2 encap action to DV specification.
2903 * Pointer to rte_eth_dev structure.
2905 * Pointer to action structure.
2906 * @param[in, out] dev_flow
2907 * Pointer to the mlx5_flow.
2908 * @param[in] transfer
2909 * Mark if the flow is E-Switch flow.
2911 * Pointer to the error structure.
2914 * 0 on success, a negative errno value otherwise and rte_errno is set.
2917 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
2918 const struct rte_flow_action *action,
2919 struct mlx5_flow *dev_flow,
2921 struct rte_flow_error *error)
2923 const struct rte_flow_item *encap_data;
2924 const struct rte_flow_action_raw_encap *raw_encap_data;
2925 struct mlx5_flow_dv_encap_decap_resource res = {
2927 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
2928 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
2929 MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
2932 if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
2934 (const struct rte_flow_action_raw_encap *)action->conf;
2935 res.size = raw_encap_data->size;
2936 memcpy(res.buf, raw_encap_data->data, res.size);
2938 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
2940 ((const struct rte_flow_action_vxlan_encap *)
2941 action->conf)->definition;
2944 ((const struct rte_flow_action_nvgre_encap *)
2945 action->conf)->definition;
2946 if (flow_dv_convert_encap_data(encap_data, res.buf,
2950 if (flow_dv_zero_encap_udp_csum(res.buf, error))
2952 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
2953 return rte_flow_error_set(error, EINVAL,
2954 RTE_FLOW_ERROR_TYPE_ACTION,
2955 NULL, "can't create L2 encap action");
2960 * Convert L2 decap action to DV specification.
2963 * Pointer to rte_eth_dev structure.
2964 * @param[in, out] dev_flow
2965 * Pointer to the mlx5_flow.
2966 * @param[in] transfer
2967 * Mark if the flow is E-Switch flow.
2969 * Pointer to the error structure.
2972 * 0 on success, a negative errno value otherwise and rte_errno is set.
2975 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
2976 struct mlx5_flow *dev_flow,
2978 struct rte_flow_error *error)
2980 struct mlx5_flow_dv_encap_decap_resource res = {
2983 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
2984 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
2985 MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
2988 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
2989 return rte_flow_error_set(error, EINVAL,
2990 RTE_FLOW_ERROR_TYPE_ACTION,
2991 NULL, "can't create L2 decap action");
2996 * Convert raw decap/encap (L3 tunnel) action to DV specification.
2999 * Pointer to rte_eth_dev structure.
3001 * Pointer to action structure.
3002 * @param[in, out] dev_flow
3003 * Pointer to the mlx5_flow.
3005 * Pointer to the flow attributes.
3007 * Pointer to the error structure.
3010 * 0 on success, a negative errno value otherwise and rte_errno is set.
3013 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
3014 const struct rte_flow_action *action,
3015 struct mlx5_flow *dev_flow,
3016 const struct rte_flow_attr *attr,
3017 struct rte_flow_error *error)
3019 const struct rte_flow_action_raw_encap *encap_data;
3020 struct mlx5_flow_dv_encap_decap_resource res;
3022 encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
3023 res.size = encap_data->size;
3024 memcpy(res.buf, encap_data->data, res.size);
3025 res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
3026 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
3027 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
3029 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3031 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3032 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3033 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3034 return rte_flow_error_set(error, EINVAL,
3035 RTE_FLOW_ERROR_TYPE_ACTION,
3036 NULL, "can't create encap action");
3041 * Create action push VLAN.
3044 * Pointer to rte_eth_dev structure.
3046 * Pointer to the flow attributes.
3048 * Pointer to the vlan to push to the Ethernet header.
3049 * @param[in, out] dev_flow
3050 * Pointer to the mlx5_flow.
3052 * Pointer to the error structure.
3055 * 0 on success, a negative errno value otherwise and rte_errno is set.
3058 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
3059 const struct rte_flow_attr *attr,
3060 const struct rte_vlan_hdr *vlan,
3061 struct mlx5_flow *dev_flow,
3062 struct rte_flow_error *error)
3064 struct mlx5_flow_dv_push_vlan_action_resource res;
3067 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
3070 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3072 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3073 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3074 return flow_dv_push_vlan_action_resource_register
3075 (dev, &res, dev_flow, error);
3079 * Validate the modify-header actions.
3081 * @param[in] action_flags
3082 * Holds the actions detected until now.
3084 * Pointer to the modify action.
3086 * Pointer to error structure.
3089 * 0 on success, a negative errno value otherwise and rte_errno is set.
3092 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
3093 const struct rte_flow_action *action,
3094 struct rte_flow_error *error)
3096 if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
3097 return rte_flow_error_set(error, EINVAL,
3098 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3099 NULL, "action configuration not set");
3100 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3101 return rte_flow_error_set(error, EINVAL,
3102 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3103 "can't have encap action before"
3109 * Validate the modify-header MAC address actions.
3111 * @param[in] action_flags
3112 * Holds the actions detected until now.
3114 * Pointer to the modify action.
3115 * @param[in] item_flags
3116 * Holds the items detected.
3118 * Pointer to error structure.
3121 * 0 on success, a negative errno value otherwise and rte_errno is set.
3124 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
3125 const struct rte_flow_action *action,
3126 const uint64_t item_flags,
3127 struct rte_flow_error *error)
3131 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3133 if (!(item_flags & MLX5_FLOW_LAYER_L2))
3134 return rte_flow_error_set(error, EINVAL,
3135 RTE_FLOW_ERROR_TYPE_ACTION,
3137 "no L2 item in pattern");
3143 * Validate the modify-header IPv4 address actions.
3145 * @param[in] action_flags
3146 * Holds the actions detected until now.
3148 * Pointer to the modify action.
3149 * @param[in] item_flags
3150 * Holds the items detected.
3152 * Pointer to error structure.
3155 * 0 on success, a negative errno value otherwise and rte_errno is set.
3158 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
3159 const struct rte_flow_action *action,
3160 const uint64_t item_flags,
3161 struct rte_flow_error *error)
3166 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3168 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3169 MLX5_FLOW_LAYER_INNER_L3_IPV4 :
3170 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
3171 if (!(item_flags & layer))
3172 return rte_flow_error_set(error, EINVAL,
3173 RTE_FLOW_ERROR_TYPE_ACTION,
3175 "no ipv4 item in pattern");
3181 * Validate the modify-header IPv6 address actions.
3183 * @param[in] action_flags
3184 * Holds the actions detected until now.
3186 * Pointer to the modify action.
3187 * @param[in] item_flags
3188 * Holds the items detected.
3190 * Pointer to error structure.
3193 * 0 on success, a negative errno value otherwise and rte_errno is set.
3196 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
3197 const struct rte_flow_action *action,
3198 const uint64_t item_flags,
3199 struct rte_flow_error *error)
3204 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3206 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3207 MLX5_FLOW_LAYER_INNER_L3_IPV6 :
3208 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
3209 if (!(item_flags & layer))
3210 return rte_flow_error_set(error, EINVAL,
3211 RTE_FLOW_ERROR_TYPE_ACTION,
3213 "no ipv6 item in pattern");
3219 * Validate the modify-header TP actions.
3221 * @param[in] action_flags
3222 * Holds the actions detected until now.
3224 * Pointer to the modify action.
3225 * @param[in] item_flags
3226 * Holds the items detected.
3228 * Pointer to error structure.
3231 * 0 on success, a negative errno value otherwise and rte_errno is set.
3234 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
3235 const struct rte_flow_action *action,
3236 const uint64_t item_flags,
3237 struct rte_flow_error *error)
3242 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3244 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3245 MLX5_FLOW_LAYER_INNER_L4 :
3246 MLX5_FLOW_LAYER_OUTER_L4;
3247 if (!(item_flags & layer))
3248 return rte_flow_error_set(error, EINVAL,
3249 RTE_FLOW_ERROR_TYPE_ACTION,
3250 NULL, "no transport layer "
3257 * Validate the modify-header actions of increment/decrement
3258 * TCP Sequence-number.
3260 * @param[in] action_flags
3261 * Holds the actions detected until now.
3263 * Pointer to the modify action.
3264 * @param[in] item_flags
3265 * Holds the items detected.
3267 * Pointer to error structure.
3270 * 0 on success, a negative errno value otherwise and rte_errno is set.
3273 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
3274 const struct rte_flow_action *action,
3275 const uint64_t item_flags,
3276 struct rte_flow_error *error)
3281 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3283 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3284 MLX5_FLOW_LAYER_INNER_L4_TCP :
3285 MLX5_FLOW_LAYER_OUTER_L4_TCP;
3286 if (!(item_flags & layer))
3287 return rte_flow_error_set(error, EINVAL,
3288 RTE_FLOW_ERROR_TYPE_ACTION,
3289 NULL, "no TCP item in"
3291 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
3292 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
3293 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
3294 (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
3295 return rte_flow_error_set(error, EINVAL,
3296 RTE_FLOW_ERROR_TYPE_ACTION,
3298 "cannot decrease and increase"
3299 " TCP sequence number"
3300 " at the same time");
3306 * Validate the modify-header actions of increment/decrement
3307 * TCP Acknowledgment number.
3309 * @param[in] action_flags
3310 * Holds the actions detected until now.
3312 * Pointer to the modify action.
3313 * @param[in] item_flags
3314 * Holds the items detected.
3316 * Pointer to error structure.
3319 * 0 on success, a negative errno value otherwise and rte_errno is set.
3322 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
3323 const struct rte_flow_action *action,
3324 const uint64_t item_flags,
3325 struct rte_flow_error *error)
3330 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3332 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3333 MLX5_FLOW_LAYER_INNER_L4_TCP :
3334 MLX5_FLOW_LAYER_OUTER_L4_TCP;
3335 if (!(item_flags & layer))
3336 return rte_flow_error_set(error, EINVAL,
3337 RTE_FLOW_ERROR_TYPE_ACTION,
3338 NULL, "no TCP item in"
3340 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
3341 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
3342 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
3343 (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
3344 return rte_flow_error_set(error, EINVAL,
3345 RTE_FLOW_ERROR_TYPE_ACTION,
3347 "cannot decrease and increase"
3348 " TCP acknowledgment number"
3349 " at the same time");
3355 * Validate the modify-header TTL actions.
3357 * @param[in] action_flags
3358 * Holds the actions detected until now.
3360 * Pointer to the modify action.
3361 * @param[in] item_flags
3362 * Holds the items detected.
3364 * Pointer to error structure.
3367 * 0 on success, a negative errno value otherwise and rte_errno is set.
3370 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
3371 const struct rte_flow_action *action,
3372 const uint64_t item_flags,
3373 struct rte_flow_error *error)
3378 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3380 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3381 MLX5_FLOW_LAYER_INNER_L3 :
3382 MLX5_FLOW_LAYER_OUTER_L3;
3383 if (!(item_flags & layer))
3384 return rte_flow_error_set(error, EINVAL,
3385 RTE_FLOW_ERROR_TYPE_ACTION,
3387 "no IP protocol in pattern");
3393 * Validate jump action.
3396 * Pointer to the jump action.
3397 * @param[in] action_flags
3398 * Holds the actions detected until now.
3399 * @param[in] attributes
3400 * Pointer to flow attributes
3401 * @param[in] external
3402 * Action belongs to flow rule created by request external to PMD.
3404 * Pointer to error structure.
3407 * 0 on success, a negative errno value otherwise and rte_errno is set.
3410 flow_dv_validate_action_jump(const struct rte_flow_action *action,
3411 uint64_t action_flags,
3412 const struct rte_flow_attr *attributes,
3413 bool external, struct rte_flow_error *error)
3415 uint32_t target_group, table;
3418 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3419 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3420 return rte_flow_error_set(error, EINVAL,
3421 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3422 "can't have 2 fate actions in"
3424 if (action_flags & MLX5_FLOW_ACTION_METER)
3425 return rte_flow_error_set(error, ENOTSUP,
3426 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3427 "jump with meter not support");
3429 return rte_flow_error_set(error, EINVAL,
3430 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3431 NULL, "action configuration not set");
3433 ((const struct rte_flow_action_jump *)action->conf)->group;
3434 ret = mlx5_flow_group_to_table(attributes, external, target_group,
3435 true, &table, error);
3438 if (attributes->group == target_group)
3439 return rte_flow_error_set(error, EINVAL,
3440 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3441 "target group must be other than"
3442 " the current flow group");
3447 * Validate the port_id action.
3450 * Pointer to rte_eth_dev structure.
3451 * @param[in] action_flags
3452 * Bit-fields that holds the actions detected until now.
3454 * Port_id RTE action structure.
3456 * Attributes of flow that includes this action.
3458 * Pointer to error structure.
3461 * 0 on success, a negative errno value otherwise and rte_errno is set.
3464 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
3465 uint64_t action_flags,
3466 const struct rte_flow_action *action,
3467 const struct rte_flow_attr *attr,
3468 struct rte_flow_error *error)
3470 const struct rte_flow_action_port_id *port_id;
3471 struct mlx5_priv *act_priv;
3472 struct mlx5_priv *dev_priv;
3475 if (!attr->transfer)
3476 return rte_flow_error_set(error, ENOTSUP,
3477 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3479 "port id action is valid in transfer"
3481 if (!action || !action->conf)
3482 return rte_flow_error_set(error, ENOTSUP,
3483 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3485 "port id action parameters must be"
3487 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3488 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3489 return rte_flow_error_set(error, EINVAL,
3490 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3491 "can have only one fate actions in"
3493 dev_priv = mlx5_dev_to_eswitch_info(dev);
3495 return rte_flow_error_set(error, rte_errno,
3496 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3498 "failed to obtain E-Switch info");
3499 port_id = action->conf;
3500 port = port_id->original ? dev->data->port_id : port_id->id;
3501 act_priv = mlx5_port_to_eswitch_info(port, false);
3503 return rte_flow_error_set
3505 RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
3506 "failed to obtain E-Switch port id for port");
3507 if (act_priv->domain_id != dev_priv->domain_id)
3508 return rte_flow_error_set
3510 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3511 "port does not belong to"
3512 " E-Switch being configured");
3517 * Get the maximum number of modify header actions.
3520 * Pointer to rte_eth_dev structure.
3522 * Flags bits to check if root level.
3525 * Max number of modify header actions device can support.
3528 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev, uint64_t flags)
3531 * There's no way to directly query the max cap. Although it has to be
3532 * acquried by iterative trial, it is a safe assumption that more
3533 * actions are supported by FW if extensive metadata register is
3534 * supported. (Only in the root table)
3536 if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
3537 return MLX5_MAX_MODIFY_NUM;
3539 return mlx5_flow_ext_mreg_supported(dev) ?
3540 MLX5_ROOT_TBL_MODIFY_NUM :
3541 MLX5_ROOT_TBL_MODIFY_NUM_NO_MREG;
3545 * Validate the meter action.
3548 * Pointer to rte_eth_dev structure.
3549 * @param[in] action_flags
3550 * Bit-fields that holds the actions detected until now.
3552 * Pointer to the meter action.
3554 * Attributes of flow that includes this action.
3556 * Pointer to error structure.
3559 * 0 on success, a negative errno value otherwise and rte_ernno is set.
3562 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
3563 uint64_t action_flags,
3564 const struct rte_flow_action *action,
3565 const struct rte_flow_attr *attr,
3566 struct rte_flow_error *error)
3568 struct mlx5_priv *priv = dev->data->dev_private;
3569 const struct rte_flow_action_meter *am = action->conf;
3570 struct mlx5_flow_meter *fm;
3573 return rte_flow_error_set(error, EINVAL,
3574 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3575 "meter action conf is NULL");
3577 if (action_flags & MLX5_FLOW_ACTION_METER)
3578 return rte_flow_error_set(error, ENOTSUP,
3579 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3580 "meter chaining not support");
3581 if (action_flags & MLX5_FLOW_ACTION_JUMP)
3582 return rte_flow_error_set(error, ENOTSUP,
3583 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3584 "meter with jump not support");
3586 return rte_flow_error_set(error, ENOTSUP,
3587 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3589 "meter action not supported");
3590 fm = mlx5_flow_meter_find(priv, am->mtr_id);
3592 return rte_flow_error_set(error, EINVAL,
3593 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3595 if (fm->ref_cnt && (!(fm->attr.transfer == attr->transfer ||
3596 (!fm->attr.ingress && !attr->ingress && attr->egress) ||
3597 (!fm->attr.egress && !attr->egress && attr->ingress))))
3598 return rte_flow_error_set(error, EINVAL,
3599 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3600 "Flow attributes are either invalid "
3601 "or have a conflict with current "
3602 "meter attributes");
3607 * Validate the modify-header IPv4 DSCP actions.
3609 * @param[in] action_flags
3610 * Holds the actions detected until now.
3612 * Pointer to the modify action.
3613 * @param[in] item_flags
3614 * Holds the items detected.
3616 * Pointer to error structure.
3619 * 0 on success, a negative errno value otherwise and rte_errno is set.
3622 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
3623 const struct rte_flow_action *action,
3624 const uint64_t item_flags,
3625 struct rte_flow_error *error)
3629 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3631 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
3632 return rte_flow_error_set(error, EINVAL,
3633 RTE_FLOW_ERROR_TYPE_ACTION,
3635 "no ipv4 item in pattern");
3641 * Validate the modify-header IPv6 DSCP actions.
3643 * @param[in] action_flags
3644 * Holds the actions detected until now.
3646 * Pointer to the modify action.
3647 * @param[in] item_flags
3648 * Holds the items detected.
3650 * Pointer to error structure.
3653 * 0 on success, a negative errno value otherwise and rte_errno is set.
3656 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
3657 const struct rte_flow_action *action,
3658 const uint64_t item_flags,
3659 struct rte_flow_error *error)
3663 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3665 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
3666 return rte_flow_error_set(error, EINVAL,
3667 RTE_FLOW_ERROR_TYPE_ACTION,
3669 "no ipv6 item in pattern");
3675 * Find existing modify-header resource or create and register a new one.
3677 * @param dev[in, out]
3678 * Pointer to rte_eth_dev structure.
3679 * @param[in, out] resource
3680 * Pointer to modify-header resource.
3681 * @parm[in, out] dev_flow
3682 * Pointer to the dev_flow.
3684 * pointer to error structure.
3687 * 0 on success otherwise -errno and errno is set.
3690 flow_dv_modify_hdr_resource_register
3691 (struct rte_eth_dev *dev,
3692 struct mlx5_flow_dv_modify_hdr_resource *resource,
3693 struct mlx5_flow *dev_flow,
3694 struct rte_flow_error *error)
3696 struct mlx5_priv *priv = dev->data->dev_private;
3697 struct mlx5_ibv_shared *sh = priv->sh;
3698 struct mlx5_flow_dv_modify_hdr_resource *cache_resource;
3699 struct mlx5dv_dr_domain *ns;
3700 uint32_t actions_len;
3703 dev_flow->group ? 0 : MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
3704 if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
3706 return rte_flow_error_set(error, EOVERFLOW,
3707 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3708 "too many modify header items");
3709 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3710 ns = sh->fdb_domain;
3711 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
3715 /* Lookup a matching resource from cache. */
3716 actions_len = resource->actions_num * sizeof(resource->actions[0]);
3717 LIST_FOREACH(cache_resource, &sh->modify_cmds, next) {
3718 if (resource->ft_type == cache_resource->ft_type &&
3719 resource->actions_num == cache_resource->actions_num &&
3720 resource->flags == cache_resource->flags &&
3721 !memcmp((const void *)resource->actions,
3722 (const void *)cache_resource->actions,
3724 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d++",
3725 (void *)cache_resource,
3726 rte_atomic32_read(&cache_resource->refcnt));
3727 rte_atomic32_inc(&cache_resource->refcnt);
3728 dev_flow->dv.modify_hdr = cache_resource;
3732 /* Register new modify-header resource. */
3733 cache_resource = rte_calloc(__func__, 1,
3734 sizeof(*cache_resource) + actions_len, 0);
3735 if (!cache_resource)
3736 return rte_flow_error_set(error, ENOMEM,
3737 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3738 "cannot allocate resource memory");
3739 *cache_resource = *resource;
3740 rte_memcpy(cache_resource->actions, resource->actions, actions_len);
3741 cache_resource->verbs_action =
3742 mlx5_glue->dv_create_flow_action_modify_header
3743 (sh->ctx, cache_resource->ft_type, ns,
3744 cache_resource->flags, actions_len,
3745 (uint64_t *)cache_resource->actions);
3746 if (!cache_resource->verbs_action) {
3747 rte_free(cache_resource);
3748 return rte_flow_error_set(error, ENOMEM,
3749 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3750 NULL, "cannot create action");
3752 rte_atomic32_init(&cache_resource->refcnt);
3753 rte_atomic32_inc(&cache_resource->refcnt);
3754 LIST_INSERT_HEAD(&sh->modify_cmds, cache_resource, next);
3755 dev_flow->dv.modify_hdr = cache_resource;
3756 DRV_LOG(DEBUG, "new modify-header resource %p: refcnt %d++",
3757 (void *)cache_resource,
3758 rte_atomic32_read(&cache_resource->refcnt));
3762 #define MLX5_CNT_CONTAINER_RESIZE 64
3765 * Get or create a flow counter.
3768 * Pointer to the Ethernet device structure.
3770 * Indicate if this counter is shared with other flows.
3772 * Counter identifier.
3775 * pointer to flow counter on success, NULL otherwise and rte_errno is set.
3777 static struct mlx5_flow_counter *
3778 flow_dv_counter_alloc_fallback(struct rte_eth_dev *dev, uint32_t shared,
3781 struct mlx5_priv *priv = dev->data->dev_private;
3782 struct mlx5_flow_counter *cnt = NULL;
3783 struct mlx5_devx_obj *dcs = NULL;
3785 if (!priv->config.devx) {
3786 rte_errno = ENOTSUP;
3790 TAILQ_FOREACH(cnt, &priv->sh->cmng.flow_counters, next) {
3791 if (cnt->shared && cnt->id == id) {
3797 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
3800 cnt = rte_calloc(__func__, 1, sizeof(*cnt), 0);
3802 claim_zero(mlx5_devx_cmd_destroy(cnt->dcs));
3806 struct mlx5_flow_counter tmpl = {
3812 tmpl.action = mlx5_glue->dv_create_flow_action_counter(dcs->obj, 0);
3814 claim_zero(mlx5_devx_cmd_destroy(cnt->dcs));
3820 TAILQ_INSERT_HEAD(&priv->sh->cmng.flow_counters, cnt, next);
3825 * Release a flow counter.
3828 * Pointer to the Ethernet device structure.
3829 * @param[in] counter
3830 * Pointer to the counter handler.
3833 flow_dv_counter_release_fallback(struct rte_eth_dev *dev,
3834 struct mlx5_flow_counter *counter)
3836 struct mlx5_priv *priv = dev->data->dev_private;
3840 if (--counter->ref_cnt == 0) {
3841 TAILQ_REMOVE(&priv->sh->cmng.flow_counters, counter, next);
3842 claim_zero(mlx5_devx_cmd_destroy(counter->dcs));
3848 * Query a devx flow counter.
3851 * Pointer to the Ethernet device structure.
3853 * Pointer to the flow counter.
3855 * The statistics value of packets.
3857 * The statistics value of bytes.
3860 * 0 on success, otherwise a negative errno value and rte_errno is set.
3863 _flow_dv_query_count_fallback(struct rte_eth_dev *dev __rte_unused,
3864 struct mlx5_flow_counter *cnt, uint64_t *pkts,
3867 return mlx5_devx_cmd_flow_counter_query(cnt->dcs, 0, 0, pkts, bytes,
3872 * Get a pool by a counter.
3875 * Pointer to the counter.
3880 static struct mlx5_flow_counter_pool *
3881 flow_dv_counter_pool_get(struct mlx5_flow_counter *cnt)
3884 cnt -= cnt->dcs->id % MLX5_COUNTERS_PER_POOL;
3885 return (struct mlx5_flow_counter_pool *)cnt - 1;
3891 * Get a pool by devx counter ID.
3894 * Pointer to the counter container.
3896 * The counter devx ID.
3899 * The counter pool pointer if exists, NULL otherwise,
3901 static struct mlx5_flow_counter_pool *
3902 flow_dv_find_pool_by_id(struct mlx5_pools_container *cont, int id)
3904 struct mlx5_flow_counter_pool *pool;
3906 TAILQ_FOREACH(pool, &cont->pool_list, next) {
3907 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
3908 MLX5_COUNTERS_PER_POOL;
3910 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
3917 * Allocate a new memory for the counter values wrapped by all the needed
3921 * Pointer to the Ethernet device structure.
3923 * The raw memory areas - each one for MLX5_COUNTERS_PER_POOL counters.
3926 * The new memory management pointer on success, otherwise NULL and rte_errno
3929 static struct mlx5_counter_stats_mem_mng *
3930 flow_dv_create_counter_stat_mem_mng(struct rte_eth_dev *dev, int raws_n)
3932 struct mlx5_ibv_shared *sh = ((struct mlx5_priv *)
3933 (dev->data->dev_private))->sh;
3934 struct mlx5_devx_mkey_attr mkey_attr;
3935 struct mlx5_counter_stats_mem_mng *mem_mng;
3936 volatile struct flow_counter_stats *raw_data;
3937 int size = (sizeof(struct flow_counter_stats) *
3938 MLX5_COUNTERS_PER_POOL +
3939 sizeof(struct mlx5_counter_stats_raw)) * raws_n +
3940 sizeof(struct mlx5_counter_stats_mem_mng);
3941 uint8_t *mem = rte_calloc(__func__, 1, size, sysconf(_SC_PAGESIZE));
3948 mem_mng = (struct mlx5_counter_stats_mem_mng *)(mem + size) - 1;
3949 size = sizeof(*raw_data) * MLX5_COUNTERS_PER_POOL * raws_n;
3950 mem_mng->umem = mlx5_glue->devx_umem_reg(sh->ctx, mem, size,
3951 IBV_ACCESS_LOCAL_WRITE);
3952 if (!mem_mng->umem) {
3957 mkey_attr.addr = (uintptr_t)mem;
3958 mkey_attr.size = size;
3959 mkey_attr.umem_id = mem_mng->umem->umem_id;
3960 mkey_attr.pd = sh->pdn;
3961 mkey_attr.log_entity_size = 0;
3962 mkey_attr.pg_access = 0;
3963 mkey_attr.klm_array = NULL;
3964 mkey_attr.klm_num = 0;
3965 mem_mng->dm = mlx5_devx_cmd_mkey_create(sh->ctx, &mkey_attr);
3967 mlx5_glue->devx_umem_dereg(mem_mng->umem);
3972 mem_mng->raws = (struct mlx5_counter_stats_raw *)(mem + size);
3973 raw_data = (volatile struct flow_counter_stats *)mem;
3974 for (i = 0; i < raws_n; ++i) {
3975 mem_mng->raws[i].mem_mng = mem_mng;
3976 mem_mng->raws[i].data = raw_data + i * MLX5_COUNTERS_PER_POOL;
3978 LIST_INSERT_HEAD(&sh->cmng.mem_mngs, mem_mng, next);
3983 * Resize a counter container.
3986 * Pointer to the Ethernet device structure.
3988 * Whether the pool is for counter that was allocated by batch command.
3991 * The new container pointer on success, otherwise NULL and rte_errno is set.
3993 static struct mlx5_pools_container *
3994 flow_dv_container_resize(struct rte_eth_dev *dev, uint32_t batch)
3996 struct mlx5_priv *priv = dev->data->dev_private;
3997 struct mlx5_pools_container *cont =
3998 MLX5_CNT_CONTAINER(priv->sh, batch, 0);
3999 struct mlx5_pools_container *new_cont =
4000 MLX5_CNT_CONTAINER_UNUSED(priv->sh, batch, 0);
4001 struct mlx5_counter_stats_mem_mng *mem_mng;
4002 uint32_t resize = cont->n + MLX5_CNT_CONTAINER_RESIZE;
4003 uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
4006 if (cont != MLX5_CNT_CONTAINER(priv->sh, batch, 1)) {
4007 /* The last resize still hasn't detected by the host thread. */
4011 new_cont->pools = rte_calloc(__func__, 1, mem_size, 0);
4012 if (!new_cont->pools) {
4017 memcpy(new_cont->pools, cont->pools, cont->n *
4018 sizeof(struct mlx5_flow_counter_pool *));
4019 mem_mng = flow_dv_create_counter_stat_mem_mng(dev,
4020 MLX5_CNT_CONTAINER_RESIZE + MLX5_MAX_PENDING_QUERIES);
4022 rte_free(new_cont->pools);
4025 for (i = 0; i < MLX5_MAX_PENDING_QUERIES; ++i)
4026 LIST_INSERT_HEAD(&priv->sh->cmng.free_stat_raws,
4027 mem_mng->raws + MLX5_CNT_CONTAINER_RESIZE +
4029 new_cont->n = resize;
4030 rte_atomic16_set(&new_cont->n_valid, rte_atomic16_read(&cont->n_valid));
4031 TAILQ_INIT(&new_cont->pool_list);
4032 TAILQ_CONCAT(&new_cont->pool_list, &cont->pool_list, next);
4033 new_cont->init_mem_mng = mem_mng;
4035 /* Flip the master container. */
4036 priv->sh->cmng.mhi[batch] ^= (uint8_t)1;
4041 * Query a devx flow counter.
4044 * Pointer to the Ethernet device structure.
4046 * Pointer to the flow counter.
4048 * The statistics value of packets.
4050 * The statistics value of bytes.
4053 * 0 on success, otherwise a negative errno value and rte_errno is set.
4056 _flow_dv_query_count(struct rte_eth_dev *dev,
4057 struct mlx5_flow_counter *cnt, uint64_t *pkts,
4060 struct mlx5_priv *priv = dev->data->dev_private;
4061 struct mlx5_flow_counter_pool *pool =
4062 flow_dv_counter_pool_get(cnt);
4063 int offset = cnt - &pool->counters_raw[0];
4065 if (priv->counter_fallback)
4066 return _flow_dv_query_count_fallback(dev, cnt, pkts, bytes);
4068 rte_spinlock_lock(&pool->sl);
4070 * The single counters allocation may allocate smaller ID than the
4071 * current allocated in parallel to the host reading.
4072 * In this case the new counter values must be reported as 0.
4074 if (unlikely(!cnt->batch && cnt->dcs->id < pool->raw->min_dcs_id)) {
4078 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
4079 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
4081 rte_spinlock_unlock(&pool->sl);
4086 * Create and initialize a new counter pool.
4089 * Pointer to the Ethernet device structure.
4091 * The devX counter handle.
4093 * Whether the pool is for counter that was allocated by batch command.
4096 * A new pool pointer on success, NULL otherwise and rte_errno is set.
4098 static struct mlx5_flow_counter_pool *
4099 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
4102 struct mlx5_priv *priv = dev->data->dev_private;
4103 struct mlx5_flow_counter_pool *pool;
4104 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4106 int16_t n_valid = rte_atomic16_read(&cont->n_valid);
4109 if (cont->n == n_valid) {
4110 cont = flow_dv_container_resize(dev, batch);
4114 size = sizeof(*pool) + MLX5_COUNTERS_PER_POOL *
4115 sizeof(struct mlx5_flow_counter);
4116 pool = rte_calloc(__func__, 1, size, 0);
4121 pool->min_dcs = dcs;
4122 pool->raw = cont->init_mem_mng->raws + n_valid %
4123 MLX5_CNT_CONTAINER_RESIZE;
4124 pool->raw_hw = NULL;
4125 rte_spinlock_init(&pool->sl);
4127 * The generation of the new allocated counters in this pool is 0, 2 in
4128 * the pool generation makes all the counters valid for allocation.
4130 rte_atomic64_set(&pool->query_gen, 0x2);
4131 TAILQ_INIT(&pool->counters);
4132 TAILQ_INSERT_TAIL(&cont->pool_list, pool, next);
4133 cont->pools[n_valid] = pool;
4134 /* Pool initialization must be updated before host thread access. */
4136 rte_atomic16_add(&cont->n_valid, 1);
4141 * Prepare a new counter and/or a new counter pool.
4144 * Pointer to the Ethernet device structure.
4145 * @param[out] cnt_free
4146 * Where to put the pointer of a new counter.
4148 * Whether the pool is for counter that was allocated by batch command.
4151 * The free counter pool pointer and @p cnt_free is set on success,
4152 * NULL otherwise and rte_errno is set.
4154 static struct mlx5_flow_counter_pool *
4155 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
4156 struct mlx5_flow_counter **cnt_free,
4159 struct mlx5_priv *priv = dev->data->dev_private;
4160 struct mlx5_flow_counter_pool *pool;
4161 struct mlx5_devx_obj *dcs = NULL;
4162 struct mlx5_flow_counter *cnt;
4166 /* bulk_bitmap must be 0 for single counter allocation. */
4167 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
4170 pool = flow_dv_find_pool_by_id
4171 (MLX5_CNT_CONTAINER(priv->sh, batch, 0), dcs->id);
4173 pool = flow_dv_pool_create(dev, dcs, batch);
4175 mlx5_devx_cmd_destroy(dcs);
4178 } else if (dcs->id < pool->min_dcs->id) {
4179 rte_atomic64_set(&pool->a64_dcs,
4180 (int64_t)(uintptr_t)dcs);
4182 cnt = &pool->counters_raw[dcs->id % MLX5_COUNTERS_PER_POOL];
4183 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
4188 /* bulk_bitmap is in 128 counters units. */
4189 if (priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4)
4190 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
4192 rte_errno = ENODATA;
4195 pool = flow_dv_pool_create(dev, dcs, batch);
4197 mlx5_devx_cmd_destroy(dcs);
4200 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
4201 cnt = &pool->counters_raw[i];
4203 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
4205 *cnt_free = &pool->counters_raw[0];
4210 * Search for existed shared counter.
4213 * Pointer to the relevant counter pool container.
4215 * The shared counter ID to search.
4218 * NULL if not existed, otherwise pointer to the shared counter.
4220 static struct mlx5_flow_counter *
4221 flow_dv_counter_shared_search(struct mlx5_pools_container *cont,
4224 static struct mlx5_flow_counter *cnt;
4225 struct mlx5_flow_counter_pool *pool;
4228 TAILQ_FOREACH(pool, &cont->pool_list, next) {
4229 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
4230 cnt = &pool->counters_raw[i];
4231 if (cnt->ref_cnt && cnt->shared && cnt->id == id)
4239 * Allocate a flow counter.
4242 * Pointer to the Ethernet device structure.
4244 * Indicate if this counter is shared with other flows.
4246 * Counter identifier.
4248 * Counter flow group.
4251 * pointer to flow counter on success, NULL otherwise and rte_errno is set.
4253 static struct mlx5_flow_counter *
4254 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t shared, uint32_t id,
4257 struct mlx5_priv *priv = dev->data->dev_private;
4258 struct mlx5_flow_counter_pool *pool = NULL;
4259 struct mlx5_flow_counter *cnt_free = NULL;
4261 * Currently group 0 flow counter cannot be assigned to a flow if it is
4262 * not the first one in the batch counter allocation, so it is better
4263 * to allocate counters one by one for these flows in a separate
4265 * A counter can be shared between different groups so need to take
4266 * shared counters from the single container.
4268 uint32_t batch = (group && !shared) ? 1 : 0;
4269 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4272 if (priv->counter_fallback)
4273 return flow_dv_counter_alloc_fallback(dev, shared, id);
4274 if (!priv->config.devx) {
4275 rte_errno = ENOTSUP;
4279 cnt_free = flow_dv_counter_shared_search(cont, id);
4281 if (cnt_free->ref_cnt + 1 == 0) {
4285 cnt_free->ref_cnt++;
4289 /* Pools which has a free counters are in the start. */
4290 TAILQ_FOREACH(pool, &cont->pool_list, next) {
4292 * The free counter reset values must be updated between the
4293 * counter release to the counter allocation, so, at least one
4294 * query must be done in this time. ensure it by saving the
4295 * query generation in the release time.
4296 * The free list is sorted according to the generation - so if
4297 * the first one is not updated, all the others are not
4300 cnt_free = TAILQ_FIRST(&pool->counters);
4301 if (cnt_free && cnt_free->query_gen + 1 <
4302 rte_atomic64_read(&pool->query_gen))
4307 pool = flow_dv_counter_pool_prepare(dev, &cnt_free, batch);
4311 cnt_free->batch = batch;
4312 /* Create a DV counter action only in the first time usage. */
4313 if (!cnt_free->action) {
4315 struct mlx5_devx_obj *dcs;
4318 offset = cnt_free - &pool->counters_raw[0];
4319 dcs = pool->min_dcs;
4322 dcs = cnt_free->dcs;
4324 cnt_free->action = mlx5_glue->dv_create_flow_action_counter
4326 if (!cnt_free->action) {
4331 /* Update the counter reset values. */
4332 if (_flow_dv_query_count(dev, cnt_free, &cnt_free->hits,
4335 cnt_free->shared = shared;
4336 cnt_free->ref_cnt = 1;
4338 if (!priv->sh->cmng.query_thread_on)
4339 /* Start the asynchronous batch query by the host thread. */
4340 mlx5_set_query_alarm(priv->sh);
4341 TAILQ_REMOVE(&pool->counters, cnt_free, next);
4342 if (TAILQ_EMPTY(&pool->counters)) {
4343 /* Move the pool to the end of the container pool list. */
4344 TAILQ_REMOVE(&cont->pool_list, pool, next);
4345 TAILQ_INSERT_TAIL(&cont->pool_list, pool, next);
4351 * Release a flow counter.
4354 * Pointer to the Ethernet device structure.
4355 * @param[in] counter
4356 * Pointer to the counter handler.
4359 flow_dv_counter_release(struct rte_eth_dev *dev,
4360 struct mlx5_flow_counter *counter)
4362 struct mlx5_priv *priv = dev->data->dev_private;
4366 if (priv->counter_fallback) {
4367 flow_dv_counter_release_fallback(dev, counter);
4370 if (--counter->ref_cnt == 0) {
4371 struct mlx5_flow_counter_pool *pool =
4372 flow_dv_counter_pool_get(counter);
4374 /* Put the counter in the end - the last updated one. */
4375 TAILQ_INSERT_TAIL(&pool->counters, counter, next);
4376 counter->query_gen = rte_atomic64_read(&pool->query_gen);
4381 * Verify the @p attributes will be correctly understood by the NIC and store
4382 * them in the @p flow if everything is correct.
4385 * Pointer to dev struct.
4386 * @param[in] attributes
4387 * Pointer to flow attributes
4388 * @param[in] external
4389 * This flow rule is created by request external to PMD.
4391 * Pointer to error structure.
4394 * 0 on success, a negative errno value otherwise and rte_errno is set.
4397 flow_dv_validate_attributes(struct rte_eth_dev *dev,
4398 const struct rte_flow_attr *attributes,
4399 bool external __rte_unused,
4400 struct rte_flow_error *error)
4402 struct mlx5_priv *priv = dev->data->dev_private;
4403 uint32_t priority_max = priv->config.flow_prio - 1;
4405 #ifndef HAVE_MLX5DV_DR
4406 if (attributes->group)
4407 return rte_flow_error_set(error, ENOTSUP,
4408 RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
4410 "groups are not supported");
4415 ret = mlx5_flow_group_to_table(attributes, external,
4416 attributes->group, !!priv->fdb_def_rule,
4421 if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
4422 attributes->priority >= priority_max)
4423 return rte_flow_error_set(error, ENOTSUP,
4424 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
4426 "priority out of range");
4427 if (attributes->transfer) {
4428 if (!priv->config.dv_esw_en)
4429 return rte_flow_error_set
4431 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4432 "E-Switch dr is not supported");
4433 if (!(priv->representor || priv->master))
4434 return rte_flow_error_set
4435 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4436 NULL, "E-Switch configuration can only be"
4437 " done by a master or a representor device");
4438 if (attributes->egress)
4439 return rte_flow_error_set
4441 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
4442 "egress is not supported");
4444 if (!(attributes->egress ^ attributes->ingress))
4445 return rte_flow_error_set(error, ENOTSUP,
4446 RTE_FLOW_ERROR_TYPE_ATTR, NULL,
4447 "must specify exactly one of "
4448 "ingress or egress");
4453 * Internal validation function. For validating both actions and items.
4456 * Pointer to the rte_eth_dev structure.
4458 * Pointer to the flow attributes.
4460 * Pointer to the list of items.
4461 * @param[in] actions
4462 * Pointer to the list of actions.
4463 * @param[in] external
4464 * This flow rule is created by request external to PMD.
4466 * Pointer to the error structure.
4469 * 0 on success, a negative errno value otherwise and rte_errno is set.
4472 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
4473 const struct rte_flow_item items[],
4474 const struct rte_flow_action actions[],
4475 bool external, struct rte_flow_error *error)
4478 uint64_t action_flags = 0;
4479 uint64_t item_flags = 0;
4480 uint64_t last_item = 0;
4481 uint8_t next_protocol = 0xff;
4482 uint16_t ether_type = 0;
4484 uint8_t item_ipv6_proto = 0;
4485 const struct rte_flow_item *gre_item = NULL;
4486 const struct rte_flow_action_raw_decap *decap;
4487 const struct rte_flow_action_raw_encap *encap;
4488 const struct rte_flow_action_rss *rss;
4489 const struct rte_flow_item_tcp nic_tcp_mask = {
4492 .src_port = RTE_BE16(UINT16_MAX),
4493 .dst_port = RTE_BE16(UINT16_MAX),
4496 const struct rte_flow_item_ipv4 nic_ipv4_mask = {
4498 .src_addr = RTE_BE32(0xffffffff),
4499 .dst_addr = RTE_BE32(0xffffffff),
4500 .type_of_service = 0xff,
4501 .next_proto_id = 0xff,
4502 .time_to_live = 0xff,
4505 const struct rte_flow_item_ipv6 nic_ipv6_mask = {
4508 "\xff\xff\xff\xff\xff\xff\xff\xff"
4509 "\xff\xff\xff\xff\xff\xff\xff\xff",
4511 "\xff\xff\xff\xff\xff\xff\xff\xff"
4512 "\xff\xff\xff\xff\xff\xff\xff\xff",
4513 .vtc_flow = RTE_BE32(0xffffffff),
4518 struct mlx5_priv *priv = dev->data->dev_private;
4519 struct mlx5_dev_config *dev_conf = &priv->config;
4520 uint16_t queue_index = 0xFFFF;
4524 ret = flow_dv_validate_attributes(dev, attr, external, error);
4527 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
4528 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
4529 int type = items->type;
4532 case RTE_FLOW_ITEM_TYPE_VOID:
4534 case RTE_FLOW_ITEM_TYPE_PORT_ID:
4535 ret = flow_dv_validate_item_port_id
4536 (dev, items, attr, item_flags, error);
4539 last_item = MLX5_FLOW_ITEM_PORT_ID;
4541 case RTE_FLOW_ITEM_TYPE_ETH:
4542 ret = mlx5_flow_validate_item_eth(items, item_flags,
4546 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
4547 MLX5_FLOW_LAYER_OUTER_L2;
4548 if (items->mask != NULL && items->spec != NULL) {
4550 ((const struct rte_flow_item_eth *)
4553 ((const struct rte_flow_item_eth *)
4555 ether_type = rte_be_to_cpu_16(ether_type);
4560 case RTE_FLOW_ITEM_TYPE_VLAN:
4561 ret = mlx5_flow_validate_item_vlan(items, item_flags,
4565 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
4566 MLX5_FLOW_LAYER_OUTER_VLAN;
4567 if (items->mask != NULL && items->spec != NULL) {
4569 ((const struct rte_flow_item_vlan *)
4570 items->spec)->inner_type;
4572 ((const struct rte_flow_item_vlan *)
4573 items->mask)->inner_type;
4574 ether_type = rte_be_to_cpu_16(ether_type);
4579 case RTE_FLOW_ITEM_TYPE_IPV4:
4580 mlx5_flow_tunnel_ip_check(items, next_protocol,
4581 &item_flags, &tunnel);
4582 ret = mlx5_flow_validate_item_ipv4(items, item_flags,
4589 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
4590 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
4591 if (items->mask != NULL &&
4592 ((const struct rte_flow_item_ipv4 *)
4593 items->mask)->hdr.next_proto_id) {
4595 ((const struct rte_flow_item_ipv4 *)
4596 (items->spec))->hdr.next_proto_id;
4598 ((const struct rte_flow_item_ipv4 *)
4599 (items->mask))->hdr.next_proto_id;
4601 /* Reset for inner layer. */
4602 next_protocol = 0xff;
4605 case RTE_FLOW_ITEM_TYPE_IPV6:
4606 mlx5_flow_tunnel_ip_check(items, next_protocol,
4607 &item_flags, &tunnel);
4608 ret = mlx5_flow_validate_item_ipv6(items, item_flags,
4615 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
4616 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
4617 if (items->mask != NULL &&
4618 ((const struct rte_flow_item_ipv6 *)
4619 items->mask)->hdr.proto) {
4621 ((const struct rte_flow_item_ipv6 *)
4622 items->spec)->hdr.proto;
4624 ((const struct rte_flow_item_ipv6 *)
4625 items->spec)->hdr.proto;
4627 ((const struct rte_flow_item_ipv6 *)
4628 items->mask)->hdr.proto;
4630 /* Reset for inner layer. */
4631 next_protocol = 0xff;
4634 case RTE_FLOW_ITEM_TYPE_TCP:
4635 ret = mlx5_flow_validate_item_tcp
4642 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
4643 MLX5_FLOW_LAYER_OUTER_L4_TCP;
4645 case RTE_FLOW_ITEM_TYPE_UDP:
4646 ret = mlx5_flow_validate_item_udp(items, item_flags,
4651 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
4652 MLX5_FLOW_LAYER_OUTER_L4_UDP;
4654 case RTE_FLOW_ITEM_TYPE_GRE:
4655 ret = mlx5_flow_validate_item_gre(items, item_flags,
4656 next_protocol, error);
4660 last_item = MLX5_FLOW_LAYER_GRE;
4662 case RTE_FLOW_ITEM_TYPE_NVGRE:
4663 ret = mlx5_flow_validate_item_nvgre(items, item_flags,
4668 last_item = MLX5_FLOW_LAYER_NVGRE;
4670 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
4671 ret = mlx5_flow_validate_item_gre_key
4672 (items, item_flags, gre_item, error);
4675 last_item = MLX5_FLOW_LAYER_GRE_KEY;
4677 case RTE_FLOW_ITEM_TYPE_VXLAN:
4678 ret = mlx5_flow_validate_item_vxlan(items, item_flags,
4682 last_item = MLX5_FLOW_LAYER_VXLAN;
4684 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
4685 ret = mlx5_flow_validate_item_vxlan_gpe(items,
4690 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
4692 case RTE_FLOW_ITEM_TYPE_GENEVE:
4693 ret = mlx5_flow_validate_item_geneve(items,
4698 last_item = MLX5_FLOW_LAYER_GENEVE;
4700 case RTE_FLOW_ITEM_TYPE_MPLS:
4701 ret = mlx5_flow_validate_item_mpls(dev, items,
4706 last_item = MLX5_FLOW_LAYER_MPLS;
4709 case RTE_FLOW_ITEM_TYPE_MARK:
4710 ret = flow_dv_validate_item_mark(dev, items, attr,
4714 last_item = MLX5_FLOW_ITEM_MARK;
4716 case RTE_FLOW_ITEM_TYPE_META:
4717 ret = flow_dv_validate_item_meta(dev, items, attr,
4721 last_item = MLX5_FLOW_ITEM_METADATA;
4723 case RTE_FLOW_ITEM_TYPE_ICMP:
4724 ret = mlx5_flow_validate_item_icmp(items, item_flags,
4729 last_item = MLX5_FLOW_LAYER_ICMP;
4731 case RTE_FLOW_ITEM_TYPE_ICMP6:
4732 ret = mlx5_flow_validate_item_icmp6(items, item_flags,
4737 item_ipv6_proto = IPPROTO_ICMPV6;
4738 last_item = MLX5_FLOW_LAYER_ICMP6;
4740 case RTE_FLOW_ITEM_TYPE_TAG:
4741 ret = flow_dv_validate_item_tag(dev, items,
4745 last_item = MLX5_FLOW_ITEM_TAG;
4747 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
4748 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
4750 case RTE_FLOW_ITEM_TYPE_GTP:
4751 ret = flow_dv_validate_item_gtp(dev, items, item_flags,
4755 last_item = MLX5_FLOW_LAYER_GTP;
4758 return rte_flow_error_set(error, ENOTSUP,
4759 RTE_FLOW_ERROR_TYPE_ITEM,
4760 NULL, "item not supported");
4762 item_flags |= last_item;
4764 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
4765 int type = actions->type;
4766 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
4767 return rte_flow_error_set(error, ENOTSUP,
4768 RTE_FLOW_ERROR_TYPE_ACTION,
4769 actions, "too many actions");
4771 case RTE_FLOW_ACTION_TYPE_VOID:
4773 case RTE_FLOW_ACTION_TYPE_PORT_ID:
4774 ret = flow_dv_validate_action_port_id(dev,
4781 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
4784 case RTE_FLOW_ACTION_TYPE_FLAG:
4785 ret = flow_dv_validate_action_flag(dev, action_flags,
4789 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
4790 /* Count all modify-header actions as one. */
4791 if (!(action_flags &
4792 MLX5_FLOW_MODIFY_HDR_ACTIONS))
4794 action_flags |= MLX5_FLOW_ACTION_FLAG |
4795 MLX5_FLOW_ACTION_MARK_EXT;
4797 action_flags |= MLX5_FLOW_ACTION_FLAG;
4801 case RTE_FLOW_ACTION_TYPE_MARK:
4802 ret = flow_dv_validate_action_mark(dev, actions,
4807 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
4808 /* Count all modify-header actions as one. */
4809 if (!(action_flags &
4810 MLX5_FLOW_MODIFY_HDR_ACTIONS))
4812 action_flags |= MLX5_FLOW_ACTION_MARK |
4813 MLX5_FLOW_ACTION_MARK_EXT;
4815 action_flags |= MLX5_FLOW_ACTION_MARK;
4819 case RTE_FLOW_ACTION_TYPE_SET_META:
4820 ret = flow_dv_validate_action_set_meta(dev, actions,
4825 /* Count all modify-header actions as one action. */
4826 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4828 action_flags |= MLX5_FLOW_ACTION_SET_META;
4830 case RTE_FLOW_ACTION_TYPE_SET_TAG:
4831 ret = flow_dv_validate_action_set_tag(dev, actions,
4836 /* Count all modify-header actions as one action. */
4837 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4839 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
4841 case RTE_FLOW_ACTION_TYPE_DROP:
4842 ret = mlx5_flow_validate_action_drop(action_flags,
4846 action_flags |= MLX5_FLOW_ACTION_DROP;
4849 case RTE_FLOW_ACTION_TYPE_QUEUE:
4850 ret = mlx5_flow_validate_action_queue(actions,
4855 queue_index = ((const struct rte_flow_action_queue *)
4856 (actions->conf))->index;
4857 action_flags |= MLX5_FLOW_ACTION_QUEUE;
4860 case RTE_FLOW_ACTION_TYPE_RSS:
4861 rss = actions->conf;
4862 ret = mlx5_flow_validate_action_rss(actions,
4868 if (rss != NULL && rss->queue_num)
4869 queue_index = rss->queue[0];
4870 action_flags |= MLX5_FLOW_ACTION_RSS;
4873 case RTE_FLOW_ACTION_TYPE_COUNT:
4874 ret = flow_dv_validate_action_count(dev, error);
4877 action_flags |= MLX5_FLOW_ACTION_COUNT;
4880 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
4881 if (flow_dv_validate_action_pop_vlan(dev,
4887 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
4890 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
4891 ret = flow_dv_validate_action_push_vlan(action_flags,
4897 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
4900 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
4901 ret = flow_dv_validate_action_set_vlan_pcp
4902 (action_flags, actions, error);
4905 /* Count PCP with push_vlan command. */
4906 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
4908 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
4909 ret = flow_dv_validate_action_set_vlan_vid
4910 (item_flags, action_flags,
4914 /* Count VID with push_vlan command. */
4915 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
4917 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
4918 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
4919 ret = flow_dv_validate_action_l2_encap(action_flags,
4923 action_flags |= MLX5_FLOW_ACTION_ENCAP;
4926 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
4927 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
4928 ret = flow_dv_validate_action_decap(action_flags, attr,
4932 action_flags |= MLX5_FLOW_ACTION_DECAP;
4935 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
4936 ret = flow_dv_validate_action_raw_encap_decap
4937 (NULL, actions->conf, attr, &action_flags,
4942 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
4943 decap = actions->conf;
4944 while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
4946 if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
4950 encap = actions->conf;
4952 ret = flow_dv_validate_action_raw_encap_decap
4953 (decap ? decap : &empty_decap, encap,
4954 attr, &action_flags, &actions_n,
4959 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
4960 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
4961 ret = flow_dv_validate_action_modify_mac(action_flags,
4967 /* Count all modify-header actions as one action. */
4968 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4970 action_flags |= actions->type ==
4971 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
4972 MLX5_FLOW_ACTION_SET_MAC_SRC :
4973 MLX5_FLOW_ACTION_SET_MAC_DST;
4976 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
4977 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
4978 ret = flow_dv_validate_action_modify_ipv4(action_flags,
4984 /* Count all modify-header actions as one action. */
4985 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4987 action_flags |= actions->type ==
4988 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
4989 MLX5_FLOW_ACTION_SET_IPV4_SRC :
4990 MLX5_FLOW_ACTION_SET_IPV4_DST;
4992 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
4993 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
4994 ret = flow_dv_validate_action_modify_ipv6(action_flags,
5000 if (item_ipv6_proto == IPPROTO_ICMPV6)
5001 return rte_flow_error_set(error, ENOTSUP,
5002 RTE_FLOW_ERROR_TYPE_ACTION,
5004 "Can't change header "
5005 "with ICMPv6 proto");
5006 /* Count all modify-header actions as one action. */
5007 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5009 action_flags |= actions->type ==
5010 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
5011 MLX5_FLOW_ACTION_SET_IPV6_SRC :
5012 MLX5_FLOW_ACTION_SET_IPV6_DST;
5014 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
5015 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
5016 ret = flow_dv_validate_action_modify_tp(action_flags,
5022 /* Count all modify-header actions as one action. */
5023 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5025 action_flags |= actions->type ==
5026 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
5027 MLX5_FLOW_ACTION_SET_TP_SRC :
5028 MLX5_FLOW_ACTION_SET_TP_DST;
5030 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
5031 case RTE_FLOW_ACTION_TYPE_SET_TTL:
5032 ret = flow_dv_validate_action_modify_ttl(action_flags,
5038 /* Count all modify-header actions as one action. */
5039 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5041 action_flags |= actions->type ==
5042 RTE_FLOW_ACTION_TYPE_SET_TTL ?
5043 MLX5_FLOW_ACTION_SET_TTL :
5044 MLX5_FLOW_ACTION_DEC_TTL;
5046 case RTE_FLOW_ACTION_TYPE_JUMP:
5047 ret = flow_dv_validate_action_jump(actions,
5054 action_flags |= MLX5_FLOW_ACTION_JUMP;
5056 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
5057 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
5058 ret = flow_dv_validate_action_modify_tcp_seq
5065 /* Count all modify-header actions as one action. */
5066 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5068 action_flags |= actions->type ==
5069 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
5070 MLX5_FLOW_ACTION_INC_TCP_SEQ :
5071 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
5073 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
5074 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
5075 ret = flow_dv_validate_action_modify_tcp_ack
5082 /* Count all modify-header actions as one action. */
5083 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5085 action_flags |= actions->type ==
5086 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
5087 MLX5_FLOW_ACTION_INC_TCP_ACK :
5088 MLX5_FLOW_ACTION_DEC_TCP_ACK;
5090 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
5091 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
5092 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
5094 case RTE_FLOW_ACTION_TYPE_METER:
5095 ret = mlx5_flow_validate_action_meter(dev,
5101 action_flags |= MLX5_FLOW_ACTION_METER;
5104 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
5105 ret = flow_dv_validate_action_modify_ipv4_dscp
5112 /* Count all modify-header actions as one action. */
5113 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5115 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
5117 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
5118 ret = flow_dv_validate_action_modify_ipv6_dscp
5125 /* Count all modify-header actions as one action. */
5126 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5128 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
5131 return rte_flow_error_set(error, ENOTSUP,
5132 RTE_FLOW_ERROR_TYPE_ACTION,
5134 "action not supported");
5138 * Validate the drop action mutual exclusion with other actions.
5139 * Drop action is mutually-exclusive with any other action, except for
5142 if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
5143 (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
5144 return rte_flow_error_set(error, EINVAL,
5145 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5146 "Drop action is mutually-exclusive "
5147 "with any other action, except for "
5149 /* Eswitch has few restrictions on using items and actions */
5150 if (attr->transfer) {
5151 if (!mlx5_flow_ext_mreg_supported(dev) &&
5152 action_flags & MLX5_FLOW_ACTION_FLAG)
5153 return rte_flow_error_set(error, ENOTSUP,
5154 RTE_FLOW_ERROR_TYPE_ACTION,
5156 "unsupported action FLAG");
5157 if (!mlx5_flow_ext_mreg_supported(dev) &&
5158 action_flags & MLX5_FLOW_ACTION_MARK)
5159 return rte_flow_error_set(error, ENOTSUP,
5160 RTE_FLOW_ERROR_TYPE_ACTION,
5162 "unsupported action MARK");
5163 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
5164 return rte_flow_error_set(error, ENOTSUP,
5165 RTE_FLOW_ERROR_TYPE_ACTION,
5167 "unsupported action QUEUE");
5168 if (action_flags & MLX5_FLOW_ACTION_RSS)
5169 return rte_flow_error_set(error, ENOTSUP,
5170 RTE_FLOW_ERROR_TYPE_ACTION,
5172 "unsupported action RSS");
5173 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
5174 return rte_flow_error_set(error, EINVAL,
5175 RTE_FLOW_ERROR_TYPE_ACTION,
5177 "no fate action is found");
5179 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
5180 return rte_flow_error_set(error, EINVAL,
5181 RTE_FLOW_ERROR_TYPE_ACTION,
5183 "no fate action is found");
5185 /* Continue validation for Xcap actions.*/
5186 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) && (queue_index == 0xFFFF ||
5187 mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
5188 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
5189 MLX5_FLOW_XCAP_ACTIONS)
5190 return rte_flow_error_set(error, ENOTSUP,
5191 RTE_FLOW_ERROR_TYPE_ACTION,
5192 NULL, "encap and decap "
5193 "combination aren't supported");
5194 if (!attr->transfer && attr->ingress && (action_flags &
5195 MLX5_FLOW_ACTION_ENCAP))
5196 return rte_flow_error_set(error, ENOTSUP,
5197 RTE_FLOW_ERROR_TYPE_ACTION,
5198 NULL, "encap is not supported"
5199 " for ingress traffic");
5205 * Internal preparation function. Allocates the DV flow size,
5206 * this size is constant.
5209 * Pointer to the flow attributes.
5211 * Pointer to the list of items.
5212 * @param[in] actions
5213 * Pointer to the list of actions.
5215 * Pointer to the error structure.
5218 * Pointer to mlx5_flow object on success,
5219 * otherwise NULL and rte_errno is set.
5221 static struct mlx5_flow *
5222 flow_dv_prepare(const struct rte_flow_attr *attr __rte_unused,
5223 const struct rte_flow_item items[] __rte_unused,
5224 const struct rte_flow_action actions[] __rte_unused,
5225 struct rte_flow_error *error)
5227 size_t size = sizeof(struct mlx5_flow);
5228 struct mlx5_flow *dev_flow;
5230 dev_flow = rte_calloc(__func__, 1, size, 0);
5232 rte_flow_error_set(error, ENOMEM,
5233 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5234 "not enough memory to create flow");
5237 dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);
5238 dev_flow->ingress = attr->ingress;
5239 dev_flow->transfer = attr->transfer;
5243 #ifdef RTE_LIBRTE_MLX5_DEBUG
5245 * Sanity check for match mask and value. Similar to check_valid_spec() in
5246 * kernel driver. If unmasked bit is present in value, it returns failure.
5249 * pointer to match mask buffer.
5250 * @param match_value
5251 * pointer to match value buffer.
5254 * 0 if valid, -EINVAL otherwise.
5257 flow_dv_check_valid_spec(void *match_mask, void *match_value)
5259 uint8_t *m = match_mask;
5260 uint8_t *v = match_value;
5263 for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
5266 "match_value differs from match_criteria"
5267 " %p[%u] != %p[%u]",
5268 match_value, i, match_mask, i);
5277 * Add Ethernet item to matcher and to the value.
5279 * @param[in, out] matcher
5281 * @param[in, out] key
5282 * Flow matcher value.
5284 * Flow pattern to translate.
5286 * Item is inner pattern.
5289 flow_dv_translate_item_eth(void *matcher, void *key,
5290 const struct rte_flow_item *item, int inner)
5292 const struct rte_flow_item_eth *eth_m = item->mask;
5293 const struct rte_flow_item_eth *eth_v = item->spec;
5294 const struct rte_flow_item_eth nic_mask = {
5295 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5296 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5297 .type = RTE_BE16(0xffff),
5309 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5311 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5313 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5315 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5317 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, dmac_47_16),
5318 ð_m->dst, sizeof(eth_m->dst));
5319 /* The value must be in the range of the mask. */
5320 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, dmac_47_16);
5321 for (i = 0; i < sizeof(eth_m->dst); ++i)
5322 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
5323 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, smac_47_16),
5324 ð_m->src, sizeof(eth_m->src));
5325 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, smac_47_16);
5326 /* The value must be in the range of the mask. */
5327 for (i = 0; i < sizeof(eth_m->dst); ++i)
5328 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
5330 /* When ethertype is present set mask for tagged VLAN. */
5331 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5332 /* Set value for tagged VLAN if ethertype is 802.1Q. */
5333 if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_VLAN) ||
5334 eth_v->type == RTE_BE16(RTE_ETHER_TYPE_QINQ)) {
5335 MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag,
5337 /* Return here to avoid setting match on ethertype. */
5342 * HW supports match on one Ethertype, the Ethertype following the last
5343 * VLAN tag of the packet (see PRM).
5344 * Set match on ethertype only if ETH header is not followed by VLAN.
5346 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
5347 rte_be_to_cpu_16(eth_m->type));
5348 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, ethertype);
5349 *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
5353 * Add VLAN item to matcher and to the value.
5355 * @param[in, out] dev_flow
5357 * @param[in, out] matcher
5359 * @param[in, out] key
5360 * Flow matcher value.
5362 * Flow pattern to translate.
5364 * Item is inner pattern.
5367 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
5368 void *matcher, void *key,
5369 const struct rte_flow_item *item,
5372 const struct rte_flow_item_vlan *vlan_m = item->mask;
5373 const struct rte_flow_item_vlan *vlan_v = item->spec;
5382 vlan_m = &rte_flow_item_vlan_mask;
5384 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5386 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5388 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5390 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5392 * This is workaround, masks are not supported,
5393 * and pre-validated.
5395 dev_flow->dv.vf_vlan.tag =
5396 rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
5398 tci_m = rte_be_to_cpu_16(vlan_m->tci);
5399 tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
5400 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5401 MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
5402 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_vid, tci_m);
5403 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, tci_v);
5404 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_cfi, tci_m >> 12);
5405 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_cfi, tci_v >> 12);
5406 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_prio, tci_m >> 13);
5407 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, tci_v >> 13);
5408 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
5409 rte_be_to_cpu_16(vlan_m->inner_type));
5410 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
5411 rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
5415 * Add IPV4 item to matcher and to the value.
5417 * @param[in, out] matcher
5419 * @param[in, out] key
5420 * Flow matcher value.
5422 * Flow pattern to translate.
5423 * @param[in] item_flags
5424 * Bit-fields that holds the items detected until now.
5426 * Item is inner pattern.
5428 * The group to insert the rule.
5431 flow_dv_translate_item_ipv4(void *matcher, void *key,
5432 const struct rte_flow_item *item,
5433 const uint64_t item_flags,
5434 int inner, uint32_t group)
5436 const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
5437 const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
5438 const struct rte_flow_item_ipv4 nic_mask = {
5440 .src_addr = RTE_BE32(0xffffffff),
5441 .dst_addr = RTE_BE32(0xffffffff),
5442 .type_of_service = 0xff,
5443 .next_proto_id = 0xff,
5444 .time_to_live = 0xff,
5454 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5456 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5458 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5460 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5463 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
5465 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x4);
5466 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 4);
5468 * On outer header (which must contains L2), or inner header with L2,
5469 * set cvlan_tag mask bit to mark this packet as untagged.
5470 * This should be done even if item->spec is empty.
5472 if (!inner || item_flags & MLX5_FLOW_LAYER_INNER_L2)
5473 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5478 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5479 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
5480 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5481 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
5482 *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
5483 *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
5484 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5485 src_ipv4_src_ipv6.ipv4_layout.ipv4);
5486 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5487 src_ipv4_src_ipv6.ipv4_layout.ipv4);
5488 *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
5489 *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
5490 tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
5491 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
5492 ipv4_m->hdr.type_of_service);
5493 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
5494 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
5495 ipv4_m->hdr.type_of_service >> 2);
5496 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
5497 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
5498 ipv4_m->hdr.next_proto_id);
5499 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
5500 ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
5501 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
5502 ipv4_m->hdr.time_to_live);
5503 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
5504 ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
5508 * Add IPV6 item to matcher and to the value.
5510 * @param[in, out] matcher
5512 * @param[in, out] key
5513 * Flow matcher value.
5515 * Flow pattern to translate.
5516 * @param[in] item_flags
5517 * Bit-fields that holds the items detected until now.
5519 * Item is inner pattern.
5521 * The group to insert the rule.
5524 flow_dv_translate_item_ipv6(void *matcher, void *key,
5525 const struct rte_flow_item *item,
5526 const uint64_t item_flags,
5527 int inner, uint32_t group)
5529 const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
5530 const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
5531 const struct rte_flow_item_ipv6 nic_mask = {
5534 "\xff\xff\xff\xff\xff\xff\xff\xff"
5535 "\xff\xff\xff\xff\xff\xff\xff\xff",
5537 "\xff\xff\xff\xff\xff\xff\xff\xff"
5538 "\xff\xff\xff\xff\xff\xff\xff\xff",
5539 .vtc_flow = RTE_BE32(0xffffffff),
5546 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5547 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5556 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5558 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5560 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5562 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5565 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
5567 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x6);
5568 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 6);
5570 * On outer header (which must contains L2), or inner header with L2,
5571 * set cvlan_tag mask bit to mark this packet as untagged.
5572 * This should be done even if item->spec is empty.
5574 if (!inner || item_flags & MLX5_FLOW_LAYER_INNER_L2)
5575 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5580 size = sizeof(ipv6_m->hdr.dst_addr);
5581 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5582 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
5583 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5584 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
5585 memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
5586 for (i = 0; i < size; ++i)
5587 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
5588 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5589 src_ipv4_src_ipv6.ipv6_layout.ipv6);
5590 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5591 src_ipv4_src_ipv6.ipv6_layout.ipv6);
5592 memcpy(l24_m, ipv6_m->hdr.src_addr, size);
5593 for (i = 0; i < size; ++i)
5594 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
5596 vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
5597 vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
5598 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
5599 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
5600 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
5601 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
5604 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
5606 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
5609 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
5611 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
5615 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
5617 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
5618 ipv6_v->hdr.proto & ipv6_m->hdr.proto);
5620 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
5621 ipv6_m->hdr.hop_limits);
5622 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
5623 ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
5627 * Add TCP item to matcher and to the value.
5629 * @param[in, out] matcher
5631 * @param[in, out] key
5632 * Flow matcher value.
5634 * Flow pattern to translate.
5636 * Item is inner pattern.
5639 flow_dv_translate_item_tcp(void *matcher, void *key,
5640 const struct rte_flow_item *item,
5643 const struct rte_flow_item_tcp *tcp_m = item->mask;
5644 const struct rte_flow_item_tcp *tcp_v = item->spec;
5649 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5651 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5653 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5655 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5657 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5658 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
5662 tcp_m = &rte_flow_item_tcp_mask;
5663 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
5664 rte_be_to_cpu_16(tcp_m->hdr.src_port));
5665 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
5666 rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
5667 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
5668 rte_be_to_cpu_16(tcp_m->hdr.dst_port));
5669 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
5670 rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
5671 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
5672 tcp_m->hdr.tcp_flags);
5673 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
5674 (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
5678 * Add UDP item to matcher and to the value.
5680 * @param[in, out] matcher
5682 * @param[in, out] key
5683 * Flow matcher value.
5685 * Flow pattern to translate.
5687 * Item is inner pattern.
5690 flow_dv_translate_item_udp(void *matcher, void *key,
5691 const struct rte_flow_item *item,
5694 const struct rte_flow_item_udp *udp_m = item->mask;
5695 const struct rte_flow_item_udp *udp_v = item->spec;
5700 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5702 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5704 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5706 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5708 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5709 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
5713 udp_m = &rte_flow_item_udp_mask;
5714 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
5715 rte_be_to_cpu_16(udp_m->hdr.src_port));
5716 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
5717 rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
5718 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
5719 rte_be_to_cpu_16(udp_m->hdr.dst_port));
5720 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
5721 rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
5725 * Add GRE optional Key item to matcher and to the value.
5727 * @param[in, out] matcher
5729 * @param[in, out] key
5730 * Flow matcher value.
5732 * Flow pattern to translate.
5734 * Item is inner pattern.
5737 flow_dv_translate_item_gre_key(void *matcher, void *key,
5738 const struct rte_flow_item *item)
5740 const rte_be32_t *key_m = item->mask;
5741 const rte_be32_t *key_v = item->spec;
5742 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5743 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5744 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
5746 /* GRE K bit must be on and should already be validated */
5747 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
5748 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
5752 key_m = &gre_key_default_mask;
5753 MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
5754 rte_be_to_cpu_32(*key_m) >> 8);
5755 MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
5756 rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
5757 MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
5758 rte_be_to_cpu_32(*key_m) & 0xFF);
5759 MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
5760 rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
5764 * Add GRE item to matcher and to the value.
5766 * @param[in, out] matcher
5768 * @param[in, out] key
5769 * Flow matcher value.
5771 * Flow pattern to translate.
5773 * Item is inner pattern.
5776 flow_dv_translate_item_gre(void *matcher, void *key,
5777 const struct rte_flow_item *item,
5780 const struct rte_flow_item_gre *gre_m = item->mask;
5781 const struct rte_flow_item_gre *gre_v = item->spec;
5784 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5785 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5792 uint16_t s_present:1;
5793 uint16_t k_present:1;
5794 uint16_t rsvd_bit1:1;
5795 uint16_t c_present:1;
5799 } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
5802 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5804 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5806 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5808 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5810 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5811 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
5815 gre_m = &rte_flow_item_gre_mask;
5816 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
5817 rte_be_to_cpu_16(gre_m->protocol));
5818 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
5819 rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
5820 gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
5821 gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
5822 MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
5823 gre_crks_rsvd0_ver_m.c_present);
5824 MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
5825 gre_crks_rsvd0_ver_v.c_present &
5826 gre_crks_rsvd0_ver_m.c_present);
5827 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
5828 gre_crks_rsvd0_ver_m.k_present);
5829 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
5830 gre_crks_rsvd0_ver_v.k_present &
5831 gre_crks_rsvd0_ver_m.k_present);
5832 MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
5833 gre_crks_rsvd0_ver_m.s_present);
5834 MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
5835 gre_crks_rsvd0_ver_v.s_present &
5836 gre_crks_rsvd0_ver_m.s_present);
5840 * Add NVGRE item to matcher and to the value.
5842 * @param[in, out] matcher
5844 * @param[in, out] key
5845 * Flow matcher value.
5847 * Flow pattern to translate.
5849 * Item is inner pattern.
5852 flow_dv_translate_item_nvgre(void *matcher, void *key,
5853 const struct rte_flow_item *item,
5856 const struct rte_flow_item_nvgre *nvgre_m = item->mask;
5857 const struct rte_flow_item_nvgre *nvgre_v = item->spec;
5858 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5859 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5860 const char *tni_flow_id_m = (const char *)nvgre_m->tni;
5861 const char *tni_flow_id_v = (const char *)nvgre_v->tni;
5867 /* For NVGRE, GRE header fields must be set with defined values. */
5868 const struct rte_flow_item_gre gre_spec = {
5869 .c_rsvd0_ver = RTE_BE16(0x2000),
5870 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
5872 const struct rte_flow_item_gre gre_mask = {
5873 .c_rsvd0_ver = RTE_BE16(0xB000),
5874 .protocol = RTE_BE16(UINT16_MAX),
5876 const struct rte_flow_item gre_item = {
5881 flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
5885 nvgre_m = &rte_flow_item_nvgre_mask;
5886 size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
5887 gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
5888 gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
5889 memcpy(gre_key_m, tni_flow_id_m, size);
5890 for (i = 0; i < size; ++i)
5891 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
5895 * Add VXLAN item to matcher and to the value.
5897 * @param[in, out] matcher
5899 * @param[in, out] key
5900 * Flow matcher value.
5902 * Flow pattern to translate.
5904 * Item is inner pattern.
5907 flow_dv_translate_item_vxlan(void *matcher, void *key,
5908 const struct rte_flow_item *item,
5911 const struct rte_flow_item_vxlan *vxlan_m = item->mask;
5912 const struct rte_flow_item_vxlan *vxlan_v = item->spec;
5915 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5916 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5924 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5926 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5928 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5930 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5932 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
5933 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
5934 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
5935 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
5936 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
5941 vxlan_m = &rte_flow_item_vxlan_mask;
5942 size = sizeof(vxlan_m->vni);
5943 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
5944 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
5945 memcpy(vni_m, vxlan_m->vni, size);
5946 for (i = 0; i < size; ++i)
5947 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
5951 * Add VXLAN-GPE item to matcher and to the value.
5953 * @param[in, out] matcher
5955 * @param[in, out] key
5956 * Flow matcher value.
5958 * Flow pattern to translate.
5960 * Item is inner pattern.
5964 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
5965 const struct rte_flow_item *item, int inner)
5967 const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
5968 const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
5972 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
5974 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
5980 uint8_t flags_m = 0xff;
5981 uint8_t flags_v = 0xc;
5984 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5986 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5988 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5990 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5992 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
5993 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
5994 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
5995 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
5996 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6001 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
6002 size = sizeof(vxlan_m->vni);
6003 vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
6004 vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
6005 memcpy(vni_m, vxlan_m->vni, size);
6006 for (i = 0; i < size; ++i)
6007 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
6008 if (vxlan_m->flags) {
6009 flags_m = vxlan_m->flags;
6010 flags_v = vxlan_v->flags;
6012 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
6013 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
6014 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
6016 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
6021 * Add Geneve item to matcher and to the value.
6023 * @param[in, out] matcher
6025 * @param[in, out] key
6026 * Flow matcher value.
6028 * Flow pattern to translate.
6030 * Item is inner pattern.
6034 flow_dv_translate_item_geneve(void *matcher, void *key,
6035 const struct rte_flow_item *item, int inner)
6037 const struct rte_flow_item_geneve *geneve_m = item->mask;
6038 const struct rte_flow_item_geneve *geneve_v = item->spec;
6041 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6042 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6051 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6053 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6055 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6057 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6059 dport = MLX5_UDP_PORT_GENEVE;
6060 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6061 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6062 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6067 geneve_m = &rte_flow_item_geneve_mask;
6068 size = sizeof(geneve_m->vni);
6069 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
6070 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
6071 memcpy(vni_m, geneve_m->vni, size);
6072 for (i = 0; i < size; ++i)
6073 vni_v[i] = vni_m[i] & geneve_v->vni[i];
6074 MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
6075 rte_be_to_cpu_16(geneve_m->protocol));
6076 MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
6077 rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
6078 gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
6079 gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
6080 MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
6081 MLX5_GENEVE_OAMF_VAL(gbhdr_m));
6082 MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
6083 MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
6084 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
6085 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
6086 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
6087 MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
6088 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
6092 * Add MPLS item to matcher and to the value.
6094 * @param[in, out] matcher
6096 * @param[in, out] key
6097 * Flow matcher value.
6099 * Flow pattern to translate.
6100 * @param[in] prev_layer
6101 * The protocol layer indicated in previous item.
6103 * Item is inner pattern.
6106 flow_dv_translate_item_mpls(void *matcher, void *key,
6107 const struct rte_flow_item *item,
6108 uint64_t prev_layer,
6111 const uint32_t *in_mpls_m = item->mask;
6112 const uint32_t *in_mpls_v = item->spec;
6113 uint32_t *out_mpls_m = 0;
6114 uint32_t *out_mpls_v = 0;
6115 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6116 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6117 void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
6119 void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
6120 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
6121 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6123 switch (prev_layer) {
6124 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
6125 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
6126 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
6127 MLX5_UDP_PORT_MPLS);
6129 case MLX5_FLOW_LAYER_GRE:
6130 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
6131 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
6132 RTE_ETHER_TYPE_MPLS);
6135 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6136 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6143 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
6144 switch (prev_layer) {
6145 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
6147 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
6148 outer_first_mpls_over_udp);
6150 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
6151 outer_first_mpls_over_udp);
6153 case MLX5_FLOW_LAYER_GRE:
6155 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
6156 outer_first_mpls_over_gre);
6158 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
6159 outer_first_mpls_over_gre);
6162 /* Inner MPLS not over GRE is not supported. */
6165 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
6169 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
6175 if (out_mpls_m && out_mpls_v) {
6176 *out_mpls_m = *in_mpls_m;
6177 *out_mpls_v = *in_mpls_v & *in_mpls_m;
6182 * Add metadata register item to matcher
6184 * @param[in, out] matcher
6186 * @param[in, out] key
6187 * Flow matcher value.
6188 * @param[in] reg_type
6189 * Type of device metadata register
6196 flow_dv_match_meta_reg(void *matcher, void *key,
6197 enum modify_reg reg_type,
6198 uint32_t data, uint32_t mask)
6201 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
6203 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
6209 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
6210 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
6213 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
6214 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
6218 * The metadata register C0 field might be divided into
6219 * source vport index and META item value, we should set
6220 * this field according to specified mask, not as whole one.
6222 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
6224 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
6225 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
6228 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
6231 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
6232 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
6235 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
6236 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
6239 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
6240 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
6243 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
6244 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
6247 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
6248 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
6251 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
6252 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
6255 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
6256 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
6265 * Add MARK item to matcher
6268 * The device to configure through.
6269 * @param[in, out] matcher
6271 * @param[in, out] key
6272 * Flow matcher value.
6274 * Flow pattern to translate.
6277 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
6278 void *matcher, void *key,
6279 const struct rte_flow_item *item)
6281 struct mlx5_priv *priv = dev->data->dev_private;
6282 const struct rte_flow_item_mark *mark;
6286 mark = item->mask ? (const void *)item->mask :
6287 &rte_flow_item_mark_mask;
6288 mask = mark->id & priv->sh->dv_mark_mask;
6289 mark = (const void *)item->spec;
6291 value = mark->id & priv->sh->dv_mark_mask & mask;
6293 enum modify_reg reg;
6295 /* Get the metadata register index for the mark. */
6296 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
6297 MLX5_ASSERT(reg > 0);
6298 if (reg == REG_C_0) {
6299 struct mlx5_priv *priv = dev->data->dev_private;
6300 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6301 uint32_t shl_c0 = rte_bsf32(msk_c0);
6307 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6312 * Add META item to matcher
6315 * The devich to configure through.
6316 * @param[in, out] matcher
6318 * @param[in, out] key
6319 * Flow matcher value.
6321 * Attributes of flow that includes this item.
6323 * Flow pattern to translate.
6326 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
6327 void *matcher, void *key,
6328 const struct rte_flow_attr *attr,
6329 const struct rte_flow_item *item)
6331 const struct rte_flow_item_meta *meta_m;
6332 const struct rte_flow_item_meta *meta_v;
6334 meta_m = (const void *)item->mask;
6336 meta_m = &rte_flow_item_meta_mask;
6337 meta_v = (const void *)item->spec;
6340 uint32_t value = meta_v->data;
6341 uint32_t mask = meta_m->data;
6343 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
6347 * In datapath code there is no endianness
6348 * coversions for perfromance reasons, all
6349 * pattern conversions are done in rte_flow.
6351 value = rte_cpu_to_be_32(value);
6352 mask = rte_cpu_to_be_32(mask);
6353 if (reg == REG_C_0) {
6354 struct mlx5_priv *priv = dev->data->dev_private;
6355 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6356 uint32_t shl_c0 = rte_bsf32(msk_c0);
6357 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
6358 uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
6365 MLX5_ASSERT(msk_c0);
6366 MLX5_ASSERT(!(~msk_c0 & mask));
6368 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6373 * Add vport metadata Reg C0 item to matcher
6375 * @param[in, out] matcher
6377 * @param[in, out] key
6378 * Flow matcher value.
6380 * Flow pattern to translate.
6383 flow_dv_translate_item_meta_vport(void *matcher, void *key,
6384 uint32_t value, uint32_t mask)
6386 flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
6390 * Add tag item to matcher
6393 * The devich to configure through.
6394 * @param[in, out] matcher
6396 * @param[in, out] key
6397 * Flow matcher value.
6399 * Flow pattern to translate.
6402 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
6403 void *matcher, void *key,
6404 const struct rte_flow_item *item)
6406 const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
6407 const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
6408 uint32_t mask, value;
6411 value = tag_v->data;
6412 mask = tag_m ? tag_m->data : UINT32_MAX;
6413 if (tag_v->id == REG_C_0) {
6414 struct mlx5_priv *priv = dev->data->dev_private;
6415 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6416 uint32_t shl_c0 = rte_bsf32(msk_c0);
6422 flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
6426 * Add TAG item to matcher
6429 * The devich to configure through.
6430 * @param[in, out] matcher
6432 * @param[in, out] key
6433 * Flow matcher value.
6435 * Flow pattern to translate.
6438 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
6439 void *matcher, void *key,
6440 const struct rte_flow_item *item)
6442 const struct rte_flow_item_tag *tag_v = item->spec;
6443 const struct rte_flow_item_tag *tag_m = item->mask;
6444 enum modify_reg reg;
6447 tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
6448 /* Get the metadata register index for the tag. */
6449 reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
6450 MLX5_ASSERT(reg > 0);
6451 flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
6455 * Add source vport match to the specified matcher.
6457 * @param[in, out] matcher
6459 * @param[in, out] key
6460 * Flow matcher value.
6462 * Source vport value to match
6467 flow_dv_translate_item_source_vport(void *matcher, void *key,
6468 int16_t port, uint16_t mask)
6470 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6471 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6473 MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
6474 MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
6478 * Translate port-id item to eswitch match on port-id.
6481 * The devich to configure through.
6482 * @param[in, out] matcher
6484 * @param[in, out] key
6485 * Flow matcher value.
6487 * Flow pattern to translate.
6490 * 0 on success, a negative errno value otherwise.
6493 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
6494 void *key, const struct rte_flow_item *item)
6496 const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
6497 const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
6498 struct mlx5_priv *priv;
6501 mask = pid_m ? pid_m->id : 0xffff;
6502 id = pid_v ? pid_v->id : dev->data->port_id;
6503 priv = mlx5_port_to_eswitch_info(id, item == NULL);
6506 /* Translate to vport field or to metadata, depending on mode. */
6507 if (priv->vport_meta_mask)
6508 flow_dv_translate_item_meta_vport(matcher, key,
6509 priv->vport_meta_tag,
6510 priv->vport_meta_mask);
6512 flow_dv_translate_item_source_vport(matcher, key,
6513 priv->vport_id, mask);
6518 * Add ICMP6 item to matcher and to the value.
6520 * @param[in, out] matcher
6522 * @param[in, out] key
6523 * Flow matcher value.
6525 * Flow pattern to translate.
6527 * Item is inner pattern.
6530 flow_dv_translate_item_icmp6(void *matcher, void *key,
6531 const struct rte_flow_item *item,
6534 const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
6535 const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
6538 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
6540 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6542 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6544 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6546 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6548 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6550 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
6551 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
6555 icmp6_m = &rte_flow_item_icmp6_mask;
6557 * Force flow only to match the non-fragmented IPv6 ICMPv6 packets.
6558 * If only the protocol is specified, no need to match the frag.
6560 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
6561 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
6562 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
6563 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
6564 icmp6_v->type & icmp6_m->type);
6565 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
6566 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
6567 icmp6_v->code & icmp6_m->code);
6571 * Add ICMP item to matcher and to the value.
6573 * @param[in, out] matcher
6575 * @param[in, out] key
6576 * Flow matcher value.
6578 * Flow pattern to translate.
6580 * Item is inner pattern.
6583 flow_dv_translate_item_icmp(void *matcher, void *key,
6584 const struct rte_flow_item *item,
6587 const struct rte_flow_item_icmp *icmp_m = item->mask;
6588 const struct rte_flow_item_icmp *icmp_v = item->spec;
6591 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
6593 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6595 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6597 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6599 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6601 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6603 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
6604 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
6608 icmp_m = &rte_flow_item_icmp_mask;
6610 * Force flow only to match the non-fragmented IPv4 ICMP packets.
6611 * If only the protocol is specified, no need to match the frag.
6613 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
6614 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
6615 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
6616 icmp_m->hdr.icmp_type);
6617 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
6618 icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
6619 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
6620 icmp_m->hdr.icmp_code);
6621 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
6622 icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
6626 * Add GTP item to matcher and to the value.
6628 * @param[in, out] matcher
6630 * @param[in, out] key
6631 * Flow matcher value.
6633 * Flow pattern to translate.
6635 * Item is inner pattern.
6638 flow_dv_translate_item_gtp(void *matcher, void *key,
6639 const struct rte_flow_item *item, int inner)
6641 const struct rte_flow_item_gtp *gtp_m = item->mask;
6642 const struct rte_flow_item_gtp *gtp_v = item->spec;
6645 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
6647 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6648 uint16_t dport = RTE_GTPU_UDP_PORT;
6651 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6653 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6655 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6657 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6659 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6660 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6661 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6666 gtp_m = &rte_flow_item_gtp_mask;
6667 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
6668 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
6669 gtp_v->msg_type & gtp_m->msg_type);
6670 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
6671 rte_be_to_cpu_32(gtp_m->teid));
6672 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
6673 rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
6676 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
6678 #define HEADER_IS_ZERO(match_criteria, headers) \
6679 !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
6680 matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
6683 * Calculate flow matcher enable bitmap.
6685 * @param match_criteria
6686 * Pointer to flow matcher criteria.
6689 * Bitmap of enabled fields.
6692 flow_dv_matcher_enable(uint32_t *match_criteria)
6694 uint8_t match_criteria_enable;
6696 match_criteria_enable =
6697 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
6698 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
6699 match_criteria_enable |=
6700 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
6701 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
6702 match_criteria_enable |=
6703 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
6704 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
6705 match_criteria_enable |=
6706 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
6707 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
6708 match_criteria_enable |=
6709 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
6710 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
6711 return match_criteria_enable;
6718 * @param[in, out] dev
6719 * Pointer to rte_eth_dev structure.
6720 * @param[in] table_id
6723 * Direction of the table.
6724 * @param[in] transfer
6725 * E-Switch or NIC flow.
6727 * pointer to error structure.
6730 * Returns tables resource based on the index, NULL in case of failed.
6732 static struct mlx5_flow_tbl_resource *
6733 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
6734 uint32_t table_id, uint8_t egress,
6736 struct rte_flow_error *error)
6738 struct mlx5_priv *priv = dev->data->dev_private;
6739 struct mlx5_ibv_shared *sh = priv->sh;
6740 struct mlx5_flow_tbl_resource *tbl;
6741 union mlx5_flow_tbl_key table_key = {
6743 .table_id = table_id,
6745 .domain = !!transfer,
6746 .direction = !!egress,
6749 struct mlx5_hlist_entry *pos = mlx5_hlist_lookup(sh->flow_tbls,
6751 struct mlx5_flow_tbl_data_entry *tbl_data;
6756 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
6758 tbl = &tbl_data->tbl;
6759 rte_atomic32_inc(&tbl->refcnt);
6762 tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
6764 rte_flow_error_set(error, ENOMEM,
6765 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6767 "cannot allocate flow table data entry");
6770 tbl = &tbl_data->tbl;
6771 pos = &tbl_data->entry;
6773 domain = sh->fdb_domain;
6775 domain = sh->tx_domain;
6777 domain = sh->rx_domain;
6778 tbl->obj = mlx5_glue->dr_create_flow_tbl(domain, table_id);
6780 rte_flow_error_set(error, ENOMEM,
6781 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6782 NULL, "cannot create flow table object");
6787 * No multi-threads now, but still better to initialize the reference
6788 * count before insert it into the hash list.
6790 rte_atomic32_init(&tbl->refcnt);
6791 /* Jump action reference count is initialized here. */
6792 rte_atomic32_init(&tbl_data->jump.refcnt);
6793 pos->key = table_key.v64;
6794 ret = mlx5_hlist_insert(sh->flow_tbls, pos);
6796 rte_flow_error_set(error, -ret,
6797 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6798 "cannot insert flow table data entry");
6799 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
6802 rte_atomic32_inc(&tbl->refcnt);
6807 * Release a flow table.
6810 * Pointer to rte_eth_dev structure.
6812 * Table resource to be released.
6815 * Returns 0 if table was released, else return 1;
6818 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
6819 struct mlx5_flow_tbl_resource *tbl)
6821 struct mlx5_priv *priv = dev->data->dev_private;
6822 struct mlx5_ibv_shared *sh = priv->sh;
6823 struct mlx5_flow_tbl_data_entry *tbl_data =
6824 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
6828 if (rte_atomic32_dec_and_test(&tbl->refcnt)) {
6829 struct mlx5_hlist_entry *pos = &tbl_data->entry;
6831 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
6833 /* remove the entry from the hash list and free memory. */
6834 mlx5_hlist_remove(sh->flow_tbls, pos);
6842 * Register the flow matcher.
6844 * @param[in, out] dev
6845 * Pointer to rte_eth_dev structure.
6846 * @param[in, out] matcher
6847 * Pointer to flow matcher.
6848 * @param[in, out] key
6849 * Pointer to flow table key.
6850 * @parm[in, out] dev_flow
6851 * Pointer to the dev_flow.
6853 * pointer to error structure.
6856 * 0 on success otherwise -errno and errno is set.
6859 flow_dv_matcher_register(struct rte_eth_dev *dev,
6860 struct mlx5_flow_dv_matcher *matcher,
6861 union mlx5_flow_tbl_key *key,
6862 struct mlx5_flow *dev_flow,
6863 struct rte_flow_error *error)
6865 struct mlx5_priv *priv = dev->data->dev_private;
6866 struct mlx5_ibv_shared *sh = priv->sh;
6867 struct mlx5_flow_dv_matcher *cache_matcher;
6868 struct mlx5dv_flow_matcher_attr dv_attr = {
6869 .type = IBV_FLOW_ATTR_NORMAL,
6870 .match_mask = (void *)&matcher->mask,
6872 struct mlx5_flow_tbl_resource *tbl;
6873 struct mlx5_flow_tbl_data_entry *tbl_data;
6875 tbl = flow_dv_tbl_resource_get(dev, key->table_id, key->direction,
6876 key->domain, error);
6878 return -rte_errno; /* No need to refill the error info */
6879 tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
6880 /* Lookup from cache. */
6881 LIST_FOREACH(cache_matcher, &tbl_data->matchers, next) {
6882 if (matcher->crc == cache_matcher->crc &&
6883 matcher->priority == cache_matcher->priority &&
6884 !memcmp((const void *)matcher->mask.buf,
6885 (const void *)cache_matcher->mask.buf,
6886 cache_matcher->mask.size)) {
6888 "%s group %u priority %hd use %s "
6889 "matcher %p: refcnt %d++",
6890 key->domain ? "FDB" : "NIC", key->table_id,
6891 cache_matcher->priority,
6892 key->direction ? "tx" : "rx",
6893 (void *)cache_matcher,
6894 rte_atomic32_read(&cache_matcher->refcnt));
6895 rte_atomic32_inc(&cache_matcher->refcnt);
6896 dev_flow->dv.matcher = cache_matcher;
6897 /* old matcher should not make the table ref++. */
6898 flow_dv_tbl_resource_release(dev, tbl);
6902 /* Register new matcher. */
6903 cache_matcher = rte_calloc(__func__, 1, sizeof(*cache_matcher), 0);
6904 if (!cache_matcher) {
6905 flow_dv_tbl_resource_release(dev, tbl);
6906 return rte_flow_error_set(error, ENOMEM,
6907 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6908 "cannot allocate matcher memory");
6910 *cache_matcher = *matcher;
6911 dv_attr.match_criteria_enable =
6912 flow_dv_matcher_enable(cache_matcher->mask.buf);
6913 dv_attr.priority = matcher->priority;
6915 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
6916 cache_matcher->matcher_object =
6917 mlx5_glue->dv_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj);
6918 if (!cache_matcher->matcher_object) {
6919 rte_free(cache_matcher);
6920 #ifdef HAVE_MLX5DV_DR
6921 flow_dv_tbl_resource_release(dev, tbl);
6923 return rte_flow_error_set(error, ENOMEM,
6924 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6925 NULL, "cannot create matcher");
6927 /* Save the table information */
6928 cache_matcher->tbl = tbl;
6929 rte_atomic32_init(&cache_matcher->refcnt);
6930 /* only matcher ref++, table ref++ already done above in get API. */
6931 rte_atomic32_inc(&cache_matcher->refcnt);
6932 LIST_INSERT_HEAD(&tbl_data->matchers, cache_matcher, next);
6933 dev_flow->dv.matcher = cache_matcher;
6934 DRV_LOG(DEBUG, "%s group %u priority %hd new %s matcher %p: refcnt %d",
6935 key->domain ? "FDB" : "NIC", key->table_id,
6936 cache_matcher->priority,
6937 key->direction ? "tx" : "rx", (void *)cache_matcher,
6938 rte_atomic32_read(&cache_matcher->refcnt));
6943 * Find existing tag resource or create and register a new one.
6945 * @param dev[in, out]
6946 * Pointer to rte_eth_dev structure.
6947 * @param[in, out] tag_be24
6948 * Tag value in big endian then R-shift 8.
6949 * @parm[in, out] dev_flow
6950 * Pointer to the dev_flow.
6952 * pointer to error structure.
6955 * 0 on success otherwise -errno and errno is set.
6958 flow_dv_tag_resource_register
6959 (struct rte_eth_dev *dev,
6961 struct mlx5_flow *dev_flow,
6962 struct rte_flow_error *error)
6964 struct mlx5_priv *priv = dev->data->dev_private;
6965 struct mlx5_ibv_shared *sh = priv->sh;
6966 struct mlx5_flow_dv_tag_resource *cache_resource;
6967 struct mlx5_hlist_entry *entry;
6969 /* Lookup a matching resource from cache. */
6970 entry = mlx5_hlist_lookup(sh->tag_table, (uint64_t)tag_be24);
6972 cache_resource = container_of
6973 (entry, struct mlx5_flow_dv_tag_resource, entry);
6974 rte_atomic32_inc(&cache_resource->refcnt);
6975 dev_flow->dv.tag_resource = cache_resource;
6976 DRV_LOG(DEBUG, "cached tag resource %p: refcnt now %d++",
6977 (void *)cache_resource,
6978 rte_atomic32_read(&cache_resource->refcnt));
6981 /* Register new resource. */
6982 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
6983 if (!cache_resource)
6984 return rte_flow_error_set(error, ENOMEM,
6985 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6986 "cannot allocate resource memory");
6987 cache_resource->entry.key = (uint64_t)tag_be24;
6988 cache_resource->action = mlx5_glue->dv_create_flow_action_tag(tag_be24);
6989 if (!cache_resource->action) {
6990 rte_free(cache_resource);
6991 return rte_flow_error_set(error, ENOMEM,
6992 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6993 NULL, "cannot create action");
6995 rte_atomic32_init(&cache_resource->refcnt);
6996 rte_atomic32_inc(&cache_resource->refcnt);
6997 if (mlx5_hlist_insert(sh->tag_table, &cache_resource->entry)) {
6998 mlx5_glue->destroy_flow_action(cache_resource->action);
6999 rte_free(cache_resource);
7000 return rte_flow_error_set(error, EEXIST,
7001 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7002 NULL, "cannot insert tag");
7004 dev_flow->dv.tag_resource = cache_resource;
7005 DRV_LOG(DEBUG, "new tag resource %p: refcnt now %d++",
7006 (void *)cache_resource,
7007 rte_atomic32_read(&cache_resource->refcnt));
7015 * Pointer to Ethernet device.
7017 * Pointer to mlx5_flow.
7020 * 1 while a reference on it exists, 0 when freed.
7023 flow_dv_tag_release(struct rte_eth_dev *dev,
7024 struct mlx5_flow_dv_tag_resource *tag)
7026 struct mlx5_priv *priv = dev->data->dev_private;
7027 struct mlx5_ibv_shared *sh = priv->sh;
7030 DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
7031 dev->data->port_id, (void *)tag,
7032 rte_atomic32_read(&tag->refcnt));
7033 if (rte_atomic32_dec_and_test(&tag->refcnt)) {
7034 claim_zero(mlx5_glue->destroy_flow_action(tag->action));
7035 mlx5_hlist_remove(sh->tag_table, &tag->entry);
7036 DRV_LOG(DEBUG, "port %u tag %p: removed",
7037 dev->data->port_id, (void *)tag);
7045 * Translate port ID action to vport.
7048 * Pointer to rte_eth_dev structure.
7050 * Pointer to the port ID action.
7051 * @param[out] dst_port_id
7052 * The target port ID.
7054 * Pointer to the error structure.
7057 * 0 on success, a negative errno value otherwise and rte_errno is set.
7060 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
7061 const struct rte_flow_action *action,
7062 uint32_t *dst_port_id,
7063 struct rte_flow_error *error)
7066 struct mlx5_priv *priv;
7067 const struct rte_flow_action_port_id *conf =
7068 (const struct rte_flow_action_port_id *)action->conf;
7070 port = conf->original ? dev->data->port_id : conf->id;
7071 priv = mlx5_port_to_eswitch_info(port, false);
7073 return rte_flow_error_set(error, -rte_errno,
7074 RTE_FLOW_ERROR_TYPE_ACTION,
7076 "No eswitch info was found for port");
7077 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
7079 * This parameter is transferred to
7080 * mlx5dv_dr_action_create_dest_ib_port().
7082 *dst_port_id = priv->ibv_port;
7085 * Legacy mode, no LAG configurations is supported.
7086 * This parameter is transferred to
7087 * mlx5dv_dr_action_create_dest_vport().
7089 *dst_port_id = priv->vport_id;
7095 * Add Tx queue matcher
7098 * Pointer to the dev struct.
7099 * @param[in, out] matcher
7101 * @param[in, out] key
7102 * Flow matcher value.
7104 * Flow pattern to translate.
7106 * Item is inner pattern.
7109 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
7110 void *matcher, void *key,
7111 const struct rte_flow_item *item)
7113 const struct mlx5_rte_flow_item_tx_queue *queue_m;
7114 const struct mlx5_rte_flow_item_tx_queue *queue_v;
7116 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7118 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7119 struct mlx5_txq_ctrl *txq;
7123 queue_m = (const void *)item->mask;
7126 queue_v = (const void *)item->spec;
7129 txq = mlx5_txq_get(dev, queue_v->queue);
7132 queue = txq->obj->sq->id;
7133 MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
7134 MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
7135 queue & queue_m->queue);
7136 mlx5_txq_release(dev, queue_v->queue);
7140 * Set the hash fields according to the @p flow information.
7142 * @param[in] dev_flow
7143 * Pointer to the mlx5_flow.
7146 flow_dv_hashfields_set(struct mlx5_flow *dev_flow)
7148 struct rte_flow *flow = dev_flow->flow;
7149 uint64_t items = dev_flow->layers;
7151 uint64_t rss_types = rte_eth_rss_hf_refine(flow->rss.types);
7153 dev_flow->hash_fields = 0;
7154 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
7155 if (flow->rss.level >= 2) {
7156 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
7160 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
7161 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
7162 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
7163 if (rss_types & ETH_RSS_L3_SRC_ONLY)
7164 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
7165 else if (rss_types & ETH_RSS_L3_DST_ONLY)
7166 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
7168 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
7170 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
7171 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
7172 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
7173 if (rss_types & ETH_RSS_L3_SRC_ONLY)
7174 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
7175 else if (rss_types & ETH_RSS_L3_DST_ONLY)
7176 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
7178 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
7181 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
7182 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
7183 if (rss_types & ETH_RSS_UDP) {
7184 if (rss_types & ETH_RSS_L4_SRC_ONLY)
7185 dev_flow->hash_fields |=
7186 IBV_RX_HASH_SRC_PORT_UDP;
7187 else if (rss_types & ETH_RSS_L4_DST_ONLY)
7188 dev_flow->hash_fields |=
7189 IBV_RX_HASH_DST_PORT_UDP;
7191 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
7193 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
7194 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
7195 if (rss_types & ETH_RSS_TCP) {
7196 if (rss_types & ETH_RSS_L4_SRC_ONLY)
7197 dev_flow->hash_fields |=
7198 IBV_RX_HASH_SRC_PORT_TCP;
7199 else if (rss_types & ETH_RSS_L4_DST_ONLY)
7200 dev_flow->hash_fields |=
7201 IBV_RX_HASH_DST_PORT_TCP;
7203 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
7209 * Fill the flow with DV spec, lock free
7210 * (mutex should be acquired by caller).
7213 * Pointer to rte_eth_dev structure.
7214 * @param[in, out] dev_flow
7215 * Pointer to the sub flow.
7217 * Pointer to the flow attributes.
7219 * Pointer to the list of items.
7220 * @param[in] actions
7221 * Pointer to the list of actions.
7223 * Pointer to the error structure.
7226 * 0 on success, a negative errno value otherwise and rte_errno is set.
7229 __flow_dv_translate(struct rte_eth_dev *dev,
7230 struct mlx5_flow *dev_flow,
7231 const struct rte_flow_attr *attr,
7232 const struct rte_flow_item items[],
7233 const struct rte_flow_action actions[],
7234 struct rte_flow_error *error)
7236 struct mlx5_priv *priv = dev->data->dev_private;
7237 struct mlx5_dev_config *dev_conf = &priv->config;
7238 struct rte_flow *flow = dev_flow->flow;
7239 uint64_t item_flags = 0;
7240 uint64_t last_item = 0;
7241 uint64_t action_flags = 0;
7242 uint64_t priority = attr->priority;
7243 struct mlx5_flow_dv_matcher matcher = {
7245 .size = sizeof(matcher.mask.buf),
7249 bool actions_end = false;
7251 struct mlx5_flow_dv_modify_hdr_resource res;
7252 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
7253 sizeof(struct mlx5_modification_cmd) *
7254 (MLX5_MAX_MODIFY_NUM + 1)];
7256 struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
7257 union flow_dv_attr flow_attr = { .attr = 0 };
7259 union mlx5_flow_tbl_key tbl_key;
7260 uint32_t modify_action_position = UINT32_MAX;
7261 void *match_mask = matcher.mask.buf;
7262 void *match_value = dev_flow->dv.value.buf;
7263 uint8_t next_protocol = 0xff;
7264 struct rte_vlan_hdr vlan = { 0 };
7268 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
7269 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
7270 ret = mlx5_flow_group_to_table(attr, dev_flow->external, attr->group,
7271 !!priv->fdb_def_rule, &table, error);
7274 dev_flow->group = table;
7276 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
7277 if (priority == MLX5_FLOW_PRIO_RSVD)
7278 priority = dev_conf->flow_prio - 1;
7279 /* number of actions must be set to 0 in case of dirty stack. */
7280 mhdr_res->actions_num = 0;
7281 for (; !actions_end ; actions++) {
7282 const struct rte_flow_action_queue *queue;
7283 const struct rte_flow_action_rss *rss;
7284 const struct rte_flow_action *action = actions;
7285 const struct rte_flow_action_count *count = action->conf;
7286 const uint8_t *rss_key;
7287 const struct rte_flow_action_jump *jump_data;
7288 const struct rte_flow_action_meter *mtr;
7289 struct mlx5_flow_tbl_resource *tbl;
7290 uint32_t port_id = 0;
7291 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
7292 int action_type = actions->type;
7293 const struct rte_flow_action *found_action = NULL;
7295 switch (action_type) {
7296 case RTE_FLOW_ACTION_TYPE_VOID:
7298 case RTE_FLOW_ACTION_TYPE_PORT_ID:
7299 if (flow_dv_translate_action_port_id(dev, action,
7302 port_id_resource.port_id = port_id;
7303 if (flow_dv_port_id_action_resource_register
7304 (dev, &port_id_resource, dev_flow, error))
7306 dev_flow->dv.actions[actions_n++] =
7307 dev_flow->dv.port_id_action->action;
7308 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
7310 case RTE_FLOW_ACTION_TYPE_FLAG:
7311 action_flags |= MLX5_FLOW_ACTION_FLAG;
7312 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7313 struct rte_flow_action_mark mark = {
7314 .id = MLX5_FLOW_MARK_DEFAULT,
7317 if (flow_dv_convert_action_mark(dev, &mark,
7321 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
7324 tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
7325 if (!dev_flow->dv.tag_resource)
7326 if (flow_dv_tag_resource_register
7327 (dev, tag_be, dev_flow, error))
7329 dev_flow->dv.actions[actions_n++] =
7330 dev_flow->dv.tag_resource->action;
7332 case RTE_FLOW_ACTION_TYPE_MARK:
7333 action_flags |= MLX5_FLOW_ACTION_MARK;
7334 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7335 const struct rte_flow_action_mark *mark =
7336 (const struct rte_flow_action_mark *)
7339 if (flow_dv_convert_action_mark(dev, mark,
7343 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
7347 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
7348 /* Legacy (non-extensive) MARK action. */
7349 tag_be = mlx5_flow_mark_set
7350 (((const struct rte_flow_action_mark *)
7351 (actions->conf))->id);
7352 if (!dev_flow->dv.tag_resource)
7353 if (flow_dv_tag_resource_register
7354 (dev, tag_be, dev_flow, error))
7356 dev_flow->dv.actions[actions_n++] =
7357 dev_flow->dv.tag_resource->action;
7359 case RTE_FLOW_ACTION_TYPE_SET_META:
7360 if (flow_dv_convert_action_set_meta
7361 (dev, mhdr_res, attr,
7362 (const struct rte_flow_action_set_meta *)
7363 actions->conf, error))
7365 action_flags |= MLX5_FLOW_ACTION_SET_META;
7367 case RTE_FLOW_ACTION_TYPE_SET_TAG:
7368 if (flow_dv_convert_action_set_tag
7370 (const struct rte_flow_action_set_tag *)
7371 actions->conf, error))
7373 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7375 case RTE_FLOW_ACTION_TYPE_DROP:
7376 action_flags |= MLX5_FLOW_ACTION_DROP;
7378 case RTE_FLOW_ACTION_TYPE_QUEUE:
7379 MLX5_ASSERT(flow->rss.queue);
7380 queue = actions->conf;
7381 flow->rss.queue_num = 1;
7382 (*flow->rss.queue)[0] = queue->index;
7383 action_flags |= MLX5_FLOW_ACTION_QUEUE;
7385 case RTE_FLOW_ACTION_TYPE_RSS:
7386 MLX5_ASSERT(flow->rss.queue);
7387 rss = actions->conf;
7388 if (flow->rss.queue)
7389 memcpy((*flow->rss.queue), rss->queue,
7390 rss->queue_num * sizeof(uint16_t));
7391 flow->rss.queue_num = rss->queue_num;
7392 /* NULL RSS key indicates default RSS key. */
7393 rss_key = !rss->key ? rss_hash_default_key : rss->key;
7394 memcpy(flow->rss.key, rss_key, MLX5_RSS_HASH_KEY_LEN);
7396 * rss->level and rss.types should be set in advance
7397 * when expanding items for RSS.
7399 action_flags |= MLX5_FLOW_ACTION_RSS;
7401 case RTE_FLOW_ACTION_TYPE_COUNT:
7402 if (!dev_conf->devx) {
7403 rte_errno = ENOTSUP;
7406 flow->counter = flow_dv_counter_alloc(dev,
7410 if (flow->counter == NULL)
7412 dev_flow->dv.actions[actions_n++] =
7413 flow->counter->action;
7414 action_flags |= MLX5_FLOW_ACTION_COUNT;
7417 if (rte_errno == ENOTSUP)
7418 return rte_flow_error_set
7420 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7422 "count action not supported");
7424 return rte_flow_error_set
7426 RTE_FLOW_ERROR_TYPE_ACTION,
7428 "cannot create counter"
7431 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
7432 dev_flow->dv.actions[actions_n++] =
7433 priv->sh->pop_vlan_action;
7434 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
7436 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
7437 flow_dev_get_vlan_info_from_items(items, &vlan);
7438 vlan.eth_proto = rte_be_to_cpu_16
7439 ((((const struct rte_flow_action_of_push_vlan *)
7440 actions->conf)->ethertype));
7441 found_action = mlx5_flow_find_action
7443 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
7445 mlx5_update_vlan_vid_pcp(found_action, &vlan);
7446 found_action = mlx5_flow_find_action
7448 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
7450 mlx5_update_vlan_vid_pcp(found_action, &vlan);
7451 if (flow_dv_create_action_push_vlan
7452 (dev, attr, &vlan, dev_flow, error))
7454 dev_flow->dv.actions[actions_n++] =
7455 dev_flow->dv.push_vlan_res->action;
7456 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
7458 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
7459 /* of_vlan_push action handled this action */
7460 MLX5_ASSERT(action_flags &
7461 MLX5_FLOW_ACTION_OF_PUSH_VLAN);
7463 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
7464 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
7466 flow_dev_get_vlan_info_from_items(items, &vlan);
7467 mlx5_update_vlan_vid_pcp(actions, &vlan);
7468 /* If no VLAN push - this is a modify header action */
7469 if (flow_dv_convert_action_modify_vlan_vid
7470 (mhdr_res, actions, error))
7472 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
7474 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
7475 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
7476 if (flow_dv_create_action_l2_encap(dev, actions,
7481 dev_flow->dv.actions[actions_n++] =
7482 dev_flow->dv.encap_decap->verbs_action;
7483 action_flags |= MLX5_FLOW_ACTION_ENCAP;
7485 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
7486 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
7487 if (flow_dv_create_action_l2_decap(dev, dev_flow,
7491 dev_flow->dv.actions[actions_n++] =
7492 dev_flow->dv.encap_decap->verbs_action;
7493 action_flags |= MLX5_FLOW_ACTION_DECAP;
7495 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
7496 /* Handle encap with preceding decap. */
7497 if (action_flags & MLX5_FLOW_ACTION_DECAP) {
7498 if (flow_dv_create_action_raw_encap
7499 (dev, actions, dev_flow, attr, error))
7501 dev_flow->dv.actions[actions_n++] =
7502 dev_flow->dv.encap_decap->verbs_action;
7504 /* Handle encap without preceding decap. */
7505 if (flow_dv_create_action_l2_encap
7506 (dev, actions, dev_flow, attr->transfer,
7509 dev_flow->dv.actions[actions_n++] =
7510 dev_flow->dv.encap_decap->verbs_action;
7512 action_flags |= MLX5_FLOW_ACTION_ENCAP;
7514 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
7515 while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
7517 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
7518 if (flow_dv_create_action_l2_decap
7519 (dev, dev_flow, attr->transfer, error))
7521 dev_flow->dv.actions[actions_n++] =
7522 dev_flow->dv.encap_decap->verbs_action;
7524 /* If decap is followed by encap, handle it at encap. */
7525 action_flags |= MLX5_FLOW_ACTION_DECAP;
7527 case RTE_FLOW_ACTION_TYPE_JUMP:
7528 jump_data = action->conf;
7529 ret = mlx5_flow_group_to_table(attr, dev_flow->external,
7531 !!priv->fdb_def_rule,
7535 tbl = flow_dv_tbl_resource_get(dev, table,
7537 attr->transfer, error);
7539 return rte_flow_error_set
7541 RTE_FLOW_ERROR_TYPE_ACTION,
7543 "cannot create jump action.");
7544 if (flow_dv_jump_tbl_resource_register
7545 (dev, tbl, dev_flow, error)) {
7546 flow_dv_tbl_resource_release(dev, tbl);
7547 return rte_flow_error_set
7549 RTE_FLOW_ERROR_TYPE_ACTION,
7551 "cannot create jump action.");
7553 dev_flow->dv.actions[actions_n++] =
7554 dev_flow->dv.jump->action;
7555 action_flags |= MLX5_FLOW_ACTION_JUMP;
7557 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
7558 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
7559 if (flow_dv_convert_action_modify_mac
7560 (mhdr_res, actions, error))
7562 action_flags |= actions->type ==
7563 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
7564 MLX5_FLOW_ACTION_SET_MAC_SRC :
7565 MLX5_FLOW_ACTION_SET_MAC_DST;
7567 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
7568 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
7569 if (flow_dv_convert_action_modify_ipv4
7570 (mhdr_res, actions, error))
7572 action_flags |= actions->type ==
7573 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
7574 MLX5_FLOW_ACTION_SET_IPV4_SRC :
7575 MLX5_FLOW_ACTION_SET_IPV4_DST;
7577 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
7578 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
7579 if (flow_dv_convert_action_modify_ipv6
7580 (mhdr_res, actions, error))
7582 action_flags |= actions->type ==
7583 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
7584 MLX5_FLOW_ACTION_SET_IPV6_SRC :
7585 MLX5_FLOW_ACTION_SET_IPV6_DST;
7587 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
7588 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
7589 if (flow_dv_convert_action_modify_tp
7590 (mhdr_res, actions, items,
7591 &flow_attr, dev_flow, !!(action_flags &
7592 MLX5_FLOW_ACTION_DECAP), error))
7594 action_flags |= actions->type ==
7595 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
7596 MLX5_FLOW_ACTION_SET_TP_SRC :
7597 MLX5_FLOW_ACTION_SET_TP_DST;
7599 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
7600 if (flow_dv_convert_action_modify_dec_ttl
7601 (mhdr_res, items, &flow_attr, dev_flow,
7603 MLX5_FLOW_ACTION_DECAP), error))
7605 action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
7607 case RTE_FLOW_ACTION_TYPE_SET_TTL:
7608 if (flow_dv_convert_action_modify_ttl
7609 (mhdr_res, actions, items, &flow_attr,
7610 dev_flow, !!(action_flags &
7611 MLX5_FLOW_ACTION_DECAP), error))
7613 action_flags |= MLX5_FLOW_ACTION_SET_TTL;
7615 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
7616 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
7617 if (flow_dv_convert_action_modify_tcp_seq
7618 (mhdr_res, actions, error))
7620 action_flags |= actions->type ==
7621 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
7622 MLX5_FLOW_ACTION_INC_TCP_SEQ :
7623 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
7626 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
7627 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
7628 if (flow_dv_convert_action_modify_tcp_ack
7629 (mhdr_res, actions, error))
7631 action_flags |= actions->type ==
7632 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
7633 MLX5_FLOW_ACTION_INC_TCP_ACK :
7634 MLX5_FLOW_ACTION_DEC_TCP_ACK;
7636 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
7637 if (flow_dv_convert_action_set_reg
7638 (mhdr_res, actions, error))
7640 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7642 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
7643 if (flow_dv_convert_action_copy_mreg
7644 (dev, mhdr_res, actions, error))
7646 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7648 case RTE_FLOW_ACTION_TYPE_METER:
7649 mtr = actions->conf;
7651 flow->meter = mlx5_flow_meter_attach(priv,
7655 return rte_flow_error_set(error,
7657 RTE_FLOW_ERROR_TYPE_ACTION,
7660 "or invalid parameters");
7662 /* Set the meter action. */
7663 dev_flow->dv.actions[actions_n++] =
7664 flow->meter->mfts->meter_action;
7665 action_flags |= MLX5_FLOW_ACTION_METER;
7667 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
7668 if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
7671 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
7673 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
7674 if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
7677 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
7679 case RTE_FLOW_ACTION_TYPE_END:
7681 if (mhdr_res->actions_num) {
7682 /* create modify action if needed. */
7683 if (flow_dv_modify_hdr_resource_register
7684 (dev, mhdr_res, dev_flow, error))
7686 dev_flow->dv.actions[modify_action_position] =
7687 dev_flow->dv.modify_hdr->verbs_action;
7693 if (mhdr_res->actions_num &&
7694 modify_action_position == UINT32_MAX)
7695 modify_action_position = actions_n++;
7697 dev_flow->dv.actions_n = actions_n;
7698 dev_flow->actions = action_flags;
7699 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
7700 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
7701 int item_type = items->type;
7703 switch (item_type) {
7704 case RTE_FLOW_ITEM_TYPE_PORT_ID:
7705 flow_dv_translate_item_port_id(dev, match_mask,
7706 match_value, items);
7707 last_item = MLX5_FLOW_ITEM_PORT_ID;
7709 case RTE_FLOW_ITEM_TYPE_ETH:
7710 flow_dv_translate_item_eth(match_mask, match_value,
7712 matcher.priority = MLX5_PRIORITY_MAP_L2;
7713 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
7714 MLX5_FLOW_LAYER_OUTER_L2;
7716 case RTE_FLOW_ITEM_TYPE_VLAN:
7717 flow_dv_translate_item_vlan(dev_flow,
7718 match_mask, match_value,
7720 matcher.priority = MLX5_PRIORITY_MAP_L2;
7721 last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
7722 MLX5_FLOW_LAYER_INNER_VLAN) :
7723 (MLX5_FLOW_LAYER_OUTER_L2 |
7724 MLX5_FLOW_LAYER_OUTER_VLAN);
7726 case RTE_FLOW_ITEM_TYPE_IPV4:
7727 mlx5_flow_tunnel_ip_check(items, next_protocol,
7728 &item_flags, &tunnel);
7729 flow_dv_translate_item_ipv4(match_mask, match_value,
7730 items, item_flags, tunnel,
7732 matcher.priority = MLX5_PRIORITY_MAP_L3;
7733 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
7734 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
7735 if (items->mask != NULL &&
7736 ((const struct rte_flow_item_ipv4 *)
7737 items->mask)->hdr.next_proto_id) {
7739 ((const struct rte_flow_item_ipv4 *)
7740 (items->spec))->hdr.next_proto_id;
7742 ((const struct rte_flow_item_ipv4 *)
7743 (items->mask))->hdr.next_proto_id;
7745 /* Reset for inner layer. */
7746 next_protocol = 0xff;
7749 case RTE_FLOW_ITEM_TYPE_IPV6:
7750 mlx5_flow_tunnel_ip_check(items, next_protocol,
7751 &item_flags, &tunnel);
7752 flow_dv_translate_item_ipv6(match_mask, match_value,
7753 items, item_flags, tunnel,
7755 matcher.priority = MLX5_PRIORITY_MAP_L3;
7756 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
7757 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
7758 if (items->mask != NULL &&
7759 ((const struct rte_flow_item_ipv6 *)
7760 items->mask)->hdr.proto) {
7762 ((const struct rte_flow_item_ipv6 *)
7763 items->spec)->hdr.proto;
7765 ((const struct rte_flow_item_ipv6 *)
7766 items->mask)->hdr.proto;
7768 /* Reset for inner layer. */
7769 next_protocol = 0xff;
7772 case RTE_FLOW_ITEM_TYPE_TCP:
7773 flow_dv_translate_item_tcp(match_mask, match_value,
7775 matcher.priority = MLX5_PRIORITY_MAP_L4;
7776 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
7777 MLX5_FLOW_LAYER_OUTER_L4_TCP;
7779 case RTE_FLOW_ITEM_TYPE_UDP:
7780 flow_dv_translate_item_udp(match_mask, match_value,
7782 matcher.priority = MLX5_PRIORITY_MAP_L4;
7783 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
7784 MLX5_FLOW_LAYER_OUTER_L4_UDP;
7786 case RTE_FLOW_ITEM_TYPE_GRE:
7787 flow_dv_translate_item_gre(match_mask, match_value,
7789 matcher.priority = flow->rss.level >= 2 ?
7790 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7791 last_item = MLX5_FLOW_LAYER_GRE;
7793 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
7794 flow_dv_translate_item_gre_key(match_mask,
7795 match_value, items);
7796 last_item = MLX5_FLOW_LAYER_GRE_KEY;
7798 case RTE_FLOW_ITEM_TYPE_NVGRE:
7799 flow_dv_translate_item_nvgre(match_mask, match_value,
7801 matcher.priority = flow->rss.level >= 2 ?
7802 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7803 last_item = MLX5_FLOW_LAYER_GRE;
7805 case RTE_FLOW_ITEM_TYPE_VXLAN:
7806 flow_dv_translate_item_vxlan(match_mask, match_value,
7808 matcher.priority = flow->rss.level >= 2 ?
7809 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7810 last_item = MLX5_FLOW_LAYER_VXLAN;
7812 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
7813 flow_dv_translate_item_vxlan_gpe(match_mask,
7816 matcher.priority = flow->rss.level >= 2 ?
7817 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7818 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
7820 case RTE_FLOW_ITEM_TYPE_GENEVE:
7821 flow_dv_translate_item_geneve(match_mask, match_value,
7823 matcher.priority = flow->rss.level >= 2 ?
7824 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7825 last_item = MLX5_FLOW_LAYER_GENEVE;
7827 case RTE_FLOW_ITEM_TYPE_MPLS:
7828 flow_dv_translate_item_mpls(match_mask, match_value,
7829 items, last_item, tunnel);
7830 matcher.priority = flow->rss.level >= 2 ?
7831 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7832 last_item = MLX5_FLOW_LAYER_MPLS;
7834 case RTE_FLOW_ITEM_TYPE_MARK:
7835 flow_dv_translate_item_mark(dev, match_mask,
7836 match_value, items);
7837 last_item = MLX5_FLOW_ITEM_MARK;
7839 case RTE_FLOW_ITEM_TYPE_META:
7840 flow_dv_translate_item_meta(dev, match_mask,
7841 match_value, attr, items);
7842 last_item = MLX5_FLOW_ITEM_METADATA;
7844 case RTE_FLOW_ITEM_TYPE_ICMP:
7845 flow_dv_translate_item_icmp(match_mask, match_value,
7847 last_item = MLX5_FLOW_LAYER_ICMP;
7849 case RTE_FLOW_ITEM_TYPE_ICMP6:
7850 flow_dv_translate_item_icmp6(match_mask, match_value,
7852 last_item = MLX5_FLOW_LAYER_ICMP6;
7854 case RTE_FLOW_ITEM_TYPE_TAG:
7855 flow_dv_translate_item_tag(dev, match_mask,
7856 match_value, items);
7857 last_item = MLX5_FLOW_ITEM_TAG;
7859 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
7860 flow_dv_translate_mlx5_item_tag(dev, match_mask,
7861 match_value, items);
7862 last_item = MLX5_FLOW_ITEM_TAG;
7864 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
7865 flow_dv_translate_item_tx_queue(dev, match_mask,
7868 last_item = MLX5_FLOW_ITEM_TX_QUEUE;
7870 case RTE_FLOW_ITEM_TYPE_GTP:
7871 flow_dv_translate_item_gtp(match_mask, match_value,
7873 matcher.priority = flow->rss.level >= 2 ?
7874 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7875 last_item = MLX5_FLOW_LAYER_GTP;
7880 item_flags |= last_item;
7883 * When E-Switch mode is enabled, we have two cases where we need to
7884 * set the source port manually.
7885 * The first one, is in case of Nic steering rule, and the second is
7886 * E-Switch rule where no port_id item was found. In both cases
7887 * the source port is set according the current port in use.
7889 if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
7890 (priv->representor || priv->master)) {
7891 if (flow_dv_translate_item_port_id(dev, match_mask,
7895 #ifdef RTE_LIBRTE_MLX5_DEBUG
7896 MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
7897 dev_flow->dv.value.buf));
7900 * Layers may be already initialized from prefix flow if this dev_flow
7901 * is the suffix flow.
7903 dev_flow->layers |= item_flags;
7904 if (action_flags & MLX5_FLOW_ACTION_RSS)
7905 flow_dv_hashfields_set(dev_flow);
7906 /* Register matcher. */
7907 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
7909 matcher.priority = mlx5_flow_adjust_priority(dev, priority,
7911 /* reserved field no needs to be set to 0 here. */
7912 tbl_key.domain = attr->transfer;
7913 tbl_key.direction = attr->egress;
7914 tbl_key.table_id = dev_flow->group;
7915 if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow, error))
7921 * Apply the flow to the NIC, lock free,
7922 * (mutex should be acquired by caller).
7925 * Pointer to the Ethernet device structure.
7926 * @param[in, out] flow
7927 * Pointer to flow structure.
7929 * Pointer to error structure.
7932 * 0 on success, a negative errno value otherwise and rte_errno is set.
7935 __flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
7936 struct rte_flow_error *error)
7938 struct mlx5_flow_dv *dv;
7939 struct mlx5_flow *dev_flow;
7940 struct mlx5_priv *priv = dev->data->dev_private;
7944 LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
7947 if (dev_flow->actions & MLX5_FLOW_ACTION_DROP) {
7948 if (dev_flow->transfer) {
7949 dv->actions[n++] = priv->sh->esw_drop_action;
7951 dv->hrxq = mlx5_hrxq_drop_new(dev);
7955 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7957 "cannot get drop hash queue");
7960 dv->actions[n++] = dv->hrxq->action;
7962 } else if (dev_flow->actions &
7963 (MLX5_FLOW_ACTION_QUEUE | MLX5_FLOW_ACTION_RSS)) {
7964 struct mlx5_hrxq *hrxq;
7966 MLX5_ASSERT(flow->rss.queue);
7967 hrxq = mlx5_hrxq_get(dev, flow->rss.key,
7968 MLX5_RSS_HASH_KEY_LEN,
7969 dev_flow->hash_fields,
7971 flow->rss.queue_num);
7973 hrxq = mlx5_hrxq_new
7974 (dev, flow->rss.key,
7975 MLX5_RSS_HASH_KEY_LEN,
7976 dev_flow->hash_fields,
7978 flow->rss.queue_num,
7979 !!(dev_flow->layers &
7980 MLX5_FLOW_LAYER_TUNNEL));
7985 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7986 "cannot get hash queue");
7990 dv->actions[n++] = dv->hrxq->action;
7993 mlx5_glue->dv_create_flow(dv->matcher->matcher_object,
7994 (void *)&dv->value, n,
7997 rte_flow_error_set(error, errno,
7998 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8000 "hardware refuses to create flow");
8003 if (priv->vmwa_context &&
8004 dev_flow->dv.vf_vlan.tag &&
8005 !dev_flow->dv.vf_vlan.created) {
8007 * The rule contains the VLAN pattern.
8008 * For VF we are going to create VLAN
8009 * interface to make hypervisor set correct
8010 * e-Switch vport context.
8012 mlx5_vlan_vmwa_acquire(dev, &dev_flow->dv.vf_vlan);
8017 err = rte_errno; /* Save rte_errno before cleanup. */
8018 LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
8019 struct mlx5_flow_dv *dv = &dev_flow->dv;
8021 if (dev_flow->actions & MLX5_FLOW_ACTION_DROP)
8022 mlx5_hrxq_drop_release(dev);
8024 mlx5_hrxq_release(dev, dv->hrxq);
8027 if (dev_flow->dv.vf_vlan.tag &&
8028 dev_flow->dv.vf_vlan.created)
8029 mlx5_vlan_vmwa_release(dev, &dev_flow->dv.vf_vlan);
8031 rte_errno = err; /* Restore rte_errno. */
8036 * Release the flow matcher.
8039 * Pointer to Ethernet device.
8041 * Pointer to mlx5_flow.
8044 * 1 while a reference on it exists, 0 when freed.
8047 flow_dv_matcher_release(struct rte_eth_dev *dev,
8048 struct mlx5_flow *flow)
8050 struct mlx5_flow_dv_matcher *matcher = flow->dv.matcher;
8052 MLX5_ASSERT(matcher->matcher_object);
8053 DRV_LOG(DEBUG, "port %u matcher %p: refcnt %d--",
8054 dev->data->port_id, (void *)matcher,
8055 rte_atomic32_read(&matcher->refcnt));
8056 if (rte_atomic32_dec_and_test(&matcher->refcnt)) {
8057 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8058 (matcher->matcher_object));
8059 LIST_REMOVE(matcher, next);
8060 /* table ref-- in release interface. */
8061 flow_dv_tbl_resource_release(dev, matcher->tbl);
8063 DRV_LOG(DEBUG, "port %u matcher %p: removed",
8064 dev->data->port_id, (void *)matcher);
8071 * Release an encap/decap resource.
8074 * Pointer to mlx5_flow.
8077 * 1 while a reference on it exists, 0 when freed.
8080 flow_dv_encap_decap_resource_release(struct mlx5_flow *flow)
8082 struct mlx5_flow_dv_encap_decap_resource *cache_resource =
8083 flow->dv.encap_decap;
8085 MLX5_ASSERT(cache_resource->verbs_action);
8086 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d--",
8087 (void *)cache_resource,
8088 rte_atomic32_read(&cache_resource->refcnt));
8089 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8090 claim_zero(mlx5_glue->destroy_flow_action
8091 (cache_resource->verbs_action));
8092 LIST_REMOVE(cache_resource, next);
8093 rte_free(cache_resource);
8094 DRV_LOG(DEBUG, "encap/decap resource %p: removed",
8095 (void *)cache_resource);
8102 * Release an jump to table action resource.
8105 * Pointer to Ethernet device.
8107 * Pointer to mlx5_flow.
8110 * 1 while a reference on it exists, 0 when freed.
8113 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
8114 struct mlx5_flow *flow)
8116 struct mlx5_flow_dv_jump_tbl_resource *cache_resource = flow->dv.jump;
8117 struct mlx5_flow_tbl_data_entry *tbl_data =
8118 container_of(cache_resource,
8119 struct mlx5_flow_tbl_data_entry, jump);
8121 MLX5_ASSERT(cache_resource->action);
8122 DRV_LOG(DEBUG, "jump table resource %p: refcnt %d--",
8123 (void *)cache_resource,
8124 rte_atomic32_read(&cache_resource->refcnt));
8125 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8126 claim_zero(mlx5_glue->destroy_flow_action
8127 (cache_resource->action));
8128 /* jump action memory free is inside the table release. */
8129 flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
8130 DRV_LOG(DEBUG, "jump table resource %p: removed",
8131 (void *)cache_resource);
8138 * Release a modify-header resource.
8141 * Pointer to mlx5_flow.
8144 * 1 while a reference on it exists, 0 when freed.
8147 flow_dv_modify_hdr_resource_release(struct mlx5_flow *flow)
8149 struct mlx5_flow_dv_modify_hdr_resource *cache_resource =
8150 flow->dv.modify_hdr;
8152 MLX5_ASSERT(cache_resource->verbs_action);
8153 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d--",
8154 (void *)cache_resource,
8155 rte_atomic32_read(&cache_resource->refcnt));
8156 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8157 claim_zero(mlx5_glue->destroy_flow_action
8158 (cache_resource->verbs_action));
8159 LIST_REMOVE(cache_resource, next);
8160 rte_free(cache_resource);
8161 DRV_LOG(DEBUG, "modify-header resource %p: removed",
8162 (void *)cache_resource);
8169 * Release port ID action resource.
8172 * Pointer to mlx5_flow.
8175 * 1 while a reference on it exists, 0 when freed.
8178 flow_dv_port_id_action_resource_release(struct mlx5_flow *flow)
8180 struct mlx5_flow_dv_port_id_action_resource *cache_resource =
8181 flow->dv.port_id_action;
8183 MLX5_ASSERT(cache_resource->action);
8184 DRV_LOG(DEBUG, "port ID action resource %p: refcnt %d--",
8185 (void *)cache_resource,
8186 rte_atomic32_read(&cache_resource->refcnt));
8187 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8188 claim_zero(mlx5_glue->destroy_flow_action
8189 (cache_resource->action));
8190 LIST_REMOVE(cache_resource, next);
8191 rte_free(cache_resource);
8192 DRV_LOG(DEBUG, "port id action resource %p: removed",
8193 (void *)cache_resource);
8200 * Release push vlan action resource.
8203 * Pointer to mlx5_flow.
8206 * 1 while a reference on it exists, 0 when freed.
8209 flow_dv_push_vlan_action_resource_release(struct mlx5_flow *flow)
8211 struct mlx5_flow_dv_push_vlan_action_resource *cache_resource =
8212 flow->dv.push_vlan_res;
8214 MLX5_ASSERT(cache_resource->action);
8215 DRV_LOG(DEBUG, "push VLAN action resource %p: refcnt %d--",
8216 (void *)cache_resource,
8217 rte_atomic32_read(&cache_resource->refcnt));
8218 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8219 claim_zero(mlx5_glue->destroy_flow_action
8220 (cache_resource->action));
8221 LIST_REMOVE(cache_resource, next);
8222 rte_free(cache_resource);
8223 DRV_LOG(DEBUG, "push vlan action resource %p: removed",
8224 (void *)cache_resource);
8231 * Remove the flow from the NIC but keeps it in memory.
8232 * Lock free, (mutex should be acquired by caller).
8235 * Pointer to Ethernet device.
8236 * @param[in, out] flow
8237 * Pointer to flow structure.
8240 __flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
8242 struct mlx5_flow_dv *dv;
8243 struct mlx5_flow *dev_flow;
8247 LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
8250 claim_zero(mlx5_glue->dv_destroy_flow(dv->flow));
8254 if (dev_flow->actions & MLX5_FLOW_ACTION_DROP)
8255 mlx5_hrxq_drop_release(dev);
8257 mlx5_hrxq_release(dev, dv->hrxq);
8260 if (dev_flow->dv.vf_vlan.tag &&
8261 dev_flow->dv.vf_vlan.created)
8262 mlx5_vlan_vmwa_release(dev, &dev_flow->dv.vf_vlan);
8267 * Remove the flow from the NIC and the memory.
8268 * Lock free, (mutex should be acquired by caller).
8271 * Pointer to the Ethernet device structure.
8272 * @param[in, out] flow
8273 * Pointer to flow structure.
8276 __flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
8278 struct mlx5_flow *dev_flow;
8282 __flow_dv_remove(dev, flow);
8283 if (flow->counter) {
8284 flow_dv_counter_release(dev, flow->counter);
8285 flow->counter = NULL;
8288 mlx5_flow_meter_detach(flow->meter);
8291 while (!LIST_EMPTY(&flow->dev_flows)) {
8292 dev_flow = LIST_FIRST(&flow->dev_flows);
8293 LIST_REMOVE(dev_flow, next);
8294 if (dev_flow->dv.matcher)
8295 flow_dv_matcher_release(dev, dev_flow);
8296 if (dev_flow->dv.encap_decap)
8297 flow_dv_encap_decap_resource_release(dev_flow);
8298 if (dev_flow->dv.modify_hdr)
8299 flow_dv_modify_hdr_resource_release(dev_flow);
8300 if (dev_flow->dv.jump)
8301 flow_dv_jump_tbl_resource_release(dev, dev_flow);
8302 if (dev_flow->dv.port_id_action)
8303 flow_dv_port_id_action_resource_release(dev_flow);
8304 if (dev_flow->dv.push_vlan_res)
8305 flow_dv_push_vlan_action_resource_release(dev_flow);
8306 if (dev_flow->dv.tag_resource)
8307 flow_dv_tag_release(dev, dev_flow->dv.tag_resource);
8313 * Query a dv flow rule for its statistics via devx.
8316 * Pointer to Ethernet device.
8318 * Pointer to the sub flow.
8320 * data retrieved by the query.
8322 * Perform verbose error reporting if not NULL.
8325 * 0 on success, a negative errno value otherwise and rte_errno is set.
8328 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
8329 void *data, struct rte_flow_error *error)
8331 struct mlx5_priv *priv = dev->data->dev_private;
8332 struct rte_flow_query_count *qc = data;
8334 if (!priv->config.devx)
8335 return rte_flow_error_set(error, ENOTSUP,
8336 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8338 "counters are not supported");
8339 if (flow->counter) {
8340 uint64_t pkts, bytes;
8341 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
8345 return rte_flow_error_set(error, -err,
8346 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8347 NULL, "cannot read counters");
8350 qc->hits = pkts - flow->counter->hits;
8351 qc->bytes = bytes - flow->counter->bytes;
8353 flow->counter->hits = pkts;
8354 flow->counter->bytes = bytes;
8358 return rte_flow_error_set(error, EINVAL,
8359 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8361 "counters are not available");
8367 * @see rte_flow_query()
8371 flow_dv_query(struct rte_eth_dev *dev,
8372 struct rte_flow *flow __rte_unused,
8373 const struct rte_flow_action *actions __rte_unused,
8374 void *data __rte_unused,
8375 struct rte_flow_error *error __rte_unused)
8379 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
8380 switch (actions->type) {
8381 case RTE_FLOW_ACTION_TYPE_VOID:
8383 case RTE_FLOW_ACTION_TYPE_COUNT:
8384 ret = flow_dv_query_count(dev, flow, data, error);
8387 return rte_flow_error_set(error, ENOTSUP,
8388 RTE_FLOW_ERROR_TYPE_ACTION,
8390 "action not supported");
8397 * Destroy the meter table set.
8398 * Lock free, (mutex should be acquired by caller).
8401 * Pointer to Ethernet device.
8403 * Pointer to the meter table set.
8409 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
8410 struct mlx5_meter_domains_infos *tbl)
8412 struct mlx5_priv *priv = dev->data->dev_private;
8413 struct mlx5_meter_domains_infos *mtd =
8414 (struct mlx5_meter_domains_infos *)tbl;
8416 if (!mtd || !priv->config.dv_flow_en)
8418 if (mtd->ingress.policer_rules[RTE_MTR_DROPPED])
8419 claim_zero(mlx5_glue->dv_destroy_flow
8420 (mtd->ingress.policer_rules[RTE_MTR_DROPPED]));
8421 if (mtd->egress.policer_rules[RTE_MTR_DROPPED])
8422 claim_zero(mlx5_glue->dv_destroy_flow
8423 (mtd->egress.policer_rules[RTE_MTR_DROPPED]));
8424 if (mtd->transfer.policer_rules[RTE_MTR_DROPPED])
8425 claim_zero(mlx5_glue->dv_destroy_flow
8426 (mtd->transfer.policer_rules[RTE_MTR_DROPPED]));
8427 if (mtd->egress.color_matcher)
8428 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8429 (mtd->egress.color_matcher));
8430 if (mtd->egress.any_matcher)
8431 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8432 (mtd->egress.any_matcher));
8433 if (mtd->egress.tbl)
8434 claim_zero(flow_dv_tbl_resource_release(dev,
8436 if (mtd->ingress.color_matcher)
8437 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8438 (mtd->ingress.color_matcher));
8439 if (mtd->ingress.any_matcher)
8440 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8441 (mtd->ingress.any_matcher));
8442 if (mtd->ingress.tbl)
8443 claim_zero(flow_dv_tbl_resource_release(dev,
8445 if (mtd->transfer.color_matcher)
8446 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8447 (mtd->transfer.color_matcher));
8448 if (mtd->transfer.any_matcher)
8449 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8450 (mtd->transfer.any_matcher));
8451 if (mtd->transfer.tbl)
8452 claim_zero(flow_dv_tbl_resource_release(dev,
8453 mtd->transfer.tbl));
8455 claim_zero(mlx5_glue->destroy_flow_action(mtd->drop_actn));
8460 /* Number of meter flow actions, count and jump or count and drop. */
8461 #define METER_ACTIONS 2
8464 * Create specify domain meter table and suffix table.
8467 * Pointer to Ethernet device.
8468 * @param[in,out] mtb
8469 * Pointer to DV meter table set.
8472 * @param[in] transfer
8474 * @param[in] color_reg_c_idx
8475 * Reg C index for color match.
8478 * 0 on success, -1 otherwise and rte_errno is set.
8481 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
8482 struct mlx5_meter_domains_infos *mtb,
8483 uint8_t egress, uint8_t transfer,
8484 uint32_t color_reg_c_idx)
8486 struct mlx5_priv *priv = dev->data->dev_private;
8487 struct mlx5_ibv_shared *sh = priv->sh;
8488 struct mlx5_flow_dv_match_params mask = {
8489 .size = sizeof(mask.buf),
8491 struct mlx5_flow_dv_match_params value = {
8492 .size = sizeof(value.buf),
8494 struct mlx5dv_flow_matcher_attr dv_attr = {
8495 .type = IBV_FLOW_ATTR_NORMAL,
8497 .match_criteria_enable = 0,
8498 .match_mask = (void *)&mask,
8500 void *actions[METER_ACTIONS];
8501 struct mlx5_flow_tbl_resource **sfx_tbl;
8502 struct mlx5_meter_domain_info *dtb;
8503 struct rte_flow_error error;
8507 sfx_tbl = &sh->fdb_mtr_sfx_tbl;
8508 dtb = &mtb->transfer;
8509 } else if (egress) {
8510 sfx_tbl = &sh->tx_mtr_sfx_tbl;
8513 sfx_tbl = &sh->rx_mtr_sfx_tbl;
8514 dtb = &mtb->ingress;
8516 /* If the suffix table in missing, create it. */
8518 *sfx_tbl = flow_dv_tbl_resource_get(dev,
8519 MLX5_FLOW_TABLE_LEVEL_SUFFIX,
8520 egress, transfer, &error);
8522 DRV_LOG(ERR, "Failed to create meter suffix table.");
8526 /* Create the meter table with METER level. */
8527 dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
8528 egress, transfer, &error);
8530 DRV_LOG(ERR, "Failed to create meter policer table.");
8533 /* Create matchers, Any and Color. */
8534 dv_attr.priority = 3;
8535 dv_attr.match_criteria_enable = 0;
8536 dtb->any_matcher = mlx5_glue->dv_create_flow_matcher(sh->ctx,
8539 if (!dtb->any_matcher) {
8540 DRV_LOG(ERR, "Failed to create meter"
8541 " policer default matcher.");
8544 dv_attr.priority = 0;
8545 dv_attr.match_criteria_enable =
8546 1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
8547 flow_dv_match_meta_reg(mask.buf, value.buf, color_reg_c_idx,
8548 rte_col_2_mlx5_col(RTE_COLORS), UINT8_MAX);
8549 dtb->color_matcher = mlx5_glue->dv_create_flow_matcher(sh->ctx,
8552 if (!dtb->color_matcher) {
8553 DRV_LOG(ERR, "Failed to create meter policer color matcher.");
8556 if (mtb->count_actns[RTE_MTR_DROPPED])
8557 actions[i++] = mtb->count_actns[RTE_MTR_DROPPED];
8558 actions[i++] = mtb->drop_actn;
8559 /* Default rule: lowest priority, match any, actions: drop. */
8560 dtb->policer_rules[RTE_MTR_DROPPED] =
8561 mlx5_glue->dv_create_flow(dtb->any_matcher,
8562 (void *)&value, i, actions);
8563 if (!dtb->policer_rules[RTE_MTR_DROPPED]) {
8564 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
8573 * Create the needed meter and suffix tables.
8574 * Lock free, (mutex should be acquired by caller).
8577 * Pointer to Ethernet device.
8579 * Pointer to the flow meter.
8582 * Pointer to table set on success, NULL otherwise and rte_errno is set.
8584 static struct mlx5_meter_domains_infos *
8585 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev,
8586 const struct mlx5_flow_meter *fm)
8588 struct mlx5_priv *priv = dev->data->dev_private;
8589 struct mlx5_meter_domains_infos *mtb;
8593 if (!priv->mtr_en) {
8594 rte_errno = ENOTSUP;
8597 mtb = rte_calloc(__func__, 1, sizeof(*mtb), 0);
8599 DRV_LOG(ERR, "Failed to allocate memory for meter.");
8602 /* Create meter count actions */
8603 for (i = 0; i <= RTE_MTR_DROPPED; i++) {
8604 if (!fm->policer_stats.cnt[i])
8606 mtb->count_actns[i] = fm->policer_stats.cnt[i]->action;
8608 /* Create drop action. */
8609 mtb->drop_actn = mlx5_glue->dr_create_flow_action_drop();
8610 if (!mtb->drop_actn) {
8611 DRV_LOG(ERR, "Failed to create drop action.");
8614 /* Egress meter table. */
8615 ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0, priv->mtr_color_reg);
8617 DRV_LOG(ERR, "Failed to prepare egress meter table.");
8620 /* Ingress meter table. */
8621 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0, priv->mtr_color_reg);
8623 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
8626 /* FDB meter table. */
8627 if (priv->config.dv_esw_en) {
8628 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1,
8629 priv->mtr_color_reg);
8631 DRV_LOG(ERR, "Failed to prepare fdb meter table.");
8637 flow_dv_destroy_mtr_tbl(dev, mtb);
8642 * Destroy domain policer rule.
8645 * Pointer to domain table.
8648 flow_dv_destroy_domain_policer_rule(struct mlx5_meter_domain_info *dt)
8652 for (i = 0; i < RTE_MTR_DROPPED; i++) {
8653 if (dt->policer_rules[i]) {
8654 claim_zero(mlx5_glue->dv_destroy_flow
8655 (dt->policer_rules[i]));
8656 dt->policer_rules[i] = NULL;
8659 if (dt->jump_actn) {
8660 claim_zero(mlx5_glue->destroy_flow_action(dt->jump_actn));
8661 dt->jump_actn = NULL;
8666 * Destroy policer rules.
8669 * Pointer to Ethernet device.
8671 * Pointer to flow meter structure.
8673 * Pointer to flow attributes.
8679 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev __rte_unused,
8680 const struct mlx5_flow_meter *fm,
8681 const struct rte_flow_attr *attr)
8683 struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
8688 flow_dv_destroy_domain_policer_rule(&mtb->egress);
8690 flow_dv_destroy_domain_policer_rule(&mtb->ingress);
8692 flow_dv_destroy_domain_policer_rule(&mtb->transfer);
8697 * Create specify domain meter policer rule.
8700 * Pointer to flow meter structure.
8702 * Pointer to DV meter table set.
8704 * Pointer to suffix table.
8705 * @param[in] mtr_reg_c
8706 * Color match REG_C.
8709 * 0 on success, -1 otherwise.
8712 flow_dv_create_policer_forward_rule(struct mlx5_flow_meter *fm,
8713 struct mlx5_meter_domain_info *dtb,
8714 struct mlx5_flow_tbl_resource *sfx_tb,
8717 struct mlx5_flow_dv_match_params matcher = {
8718 .size = sizeof(matcher.buf),
8720 struct mlx5_flow_dv_match_params value = {
8721 .size = sizeof(value.buf),
8723 struct mlx5_meter_domains_infos *mtb = fm->mfts;
8724 void *actions[METER_ACTIONS];
8727 /* Create jump action. */
8730 if (!dtb->jump_actn)
8732 mlx5_glue->dr_create_flow_action_dest_flow_tbl
8734 if (!dtb->jump_actn) {
8735 DRV_LOG(ERR, "Failed to create policer jump action.");
8738 for (i = 0; i < RTE_MTR_DROPPED; i++) {
8741 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_reg_c,
8742 rte_col_2_mlx5_col(i), UINT8_MAX);
8743 if (mtb->count_actns[i])
8744 actions[j++] = mtb->count_actns[i];
8745 if (fm->params.action[i] == MTR_POLICER_ACTION_DROP)
8746 actions[j++] = mtb->drop_actn;
8748 actions[j++] = dtb->jump_actn;
8749 dtb->policer_rules[i] =
8750 mlx5_glue->dv_create_flow(dtb->color_matcher,
8753 if (!dtb->policer_rules[i]) {
8754 DRV_LOG(ERR, "Failed to create policer rule.");
8765 * Create policer rules.
8768 * Pointer to Ethernet device.
8770 * Pointer to flow meter structure.
8772 * Pointer to flow attributes.
8775 * 0 on success, -1 otherwise.
8778 flow_dv_create_policer_rules(struct rte_eth_dev *dev,
8779 struct mlx5_flow_meter *fm,
8780 const struct rte_flow_attr *attr)
8782 struct mlx5_priv *priv = dev->data->dev_private;
8783 struct mlx5_meter_domains_infos *mtb = fm->mfts;
8787 ret = flow_dv_create_policer_forward_rule(fm, &mtb->egress,
8788 priv->sh->tx_mtr_sfx_tbl,
8789 priv->mtr_color_reg);
8791 DRV_LOG(ERR, "Failed to create egress policer.");
8795 if (attr->ingress) {
8796 ret = flow_dv_create_policer_forward_rule(fm, &mtb->ingress,
8797 priv->sh->rx_mtr_sfx_tbl,
8798 priv->mtr_color_reg);
8800 DRV_LOG(ERR, "Failed to create ingress policer.");
8804 if (attr->transfer) {
8805 ret = flow_dv_create_policer_forward_rule(fm, &mtb->transfer,
8806 priv->sh->fdb_mtr_sfx_tbl,
8807 priv->mtr_color_reg);
8809 DRV_LOG(ERR, "Failed to create transfer policer.");
8815 flow_dv_destroy_policer_rules(dev, fm, attr);
8820 * Query a devx counter.
8823 * Pointer to the Ethernet device structure.
8825 * Pointer to the flow counter.
8827 * Set to clear the counter statistics.
8829 * The statistics value of packets.
8831 * The statistics value of bytes.
8834 * 0 on success, otherwise return -1.
8837 flow_dv_counter_query(struct rte_eth_dev *dev,
8838 struct mlx5_flow_counter *cnt, bool clear,
8839 uint64_t *pkts, uint64_t *bytes)
8841 struct mlx5_priv *priv = dev->data->dev_private;
8842 uint64_t inn_pkts, inn_bytes;
8845 if (!priv->config.devx)
8847 ret = _flow_dv_query_count(dev, cnt, &inn_pkts, &inn_bytes);
8850 *pkts = inn_pkts - cnt->hits;
8851 *bytes = inn_bytes - cnt->bytes;
8853 cnt->hits = inn_pkts;
8854 cnt->bytes = inn_bytes;
8860 * Mutex-protected thunk to lock-free __flow_dv_translate().
8863 flow_dv_translate(struct rte_eth_dev *dev,
8864 struct mlx5_flow *dev_flow,
8865 const struct rte_flow_attr *attr,
8866 const struct rte_flow_item items[],
8867 const struct rte_flow_action actions[],
8868 struct rte_flow_error *error)
8872 flow_dv_shared_lock(dev);
8873 ret = __flow_dv_translate(dev, dev_flow, attr, items, actions, error);
8874 flow_dv_shared_unlock(dev);
8879 * Mutex-protected thunk to lock-free __flow_dv_apply().
8882 flow_dv_apply(struct rte_eth_dev *dev,
8883 struct rte_flow *flow,
8884 struct rte_flow_error *error)
8888 flow_dv_shared_lock(dev);
8889 ret = __flow_dv_apply(dev, flow, error);
8890 flow_dv_shared_unlock(dev);
8895 * Mutex-protected thunk to lock-free __flow_dv_remove().
8898 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
8900 flow_dv_shared_lock(dev);
8901 __flow_dv_remove(dev, flow);
8902 flow_dv_shared_unlock(dev);
8906 * Mutex-protected thunk to lock-free __flow_dv_destroy().
8909 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
8911 flow_dv_shared_lock(dev);
8912 __flow_dv_destroy(dev, flow);
8913 flow_dv_shared_unlock(dev);
8917 * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
8919 static struct mlx5_flow_counter *
8920 flow_dv_counter_allocate(struct rte_eth_dev *dev)
8922 struct mlx5_flow_counter *cnt;
8924 flow_dv_shared_lock(dev);
8925 cnt = flow_dv_counter_alloc(dev, 0, 0, 1);
8926 flow_dv_shared_unlock(dev);
8931 * Mutex-protected thunk to lock-free flow_dv_counter_release().
8934 flow_dv_counter_free(struct rte_eth_dev *dev, struct mlx5_flow_counter *cnt)
8936 flow_dv_shared_lock(dev);
8937 flow_dv_counter_release(dev, cnt);
8938 flow_dv_shared_unlock(dev);
8941 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
8942 .validate = flow_dv_validate,
8943 .prepare = flow_dv_prepare,
8944 .translate = flow_dv_translate,
8945 .apply = flow_dv_apply,
8946 .remove = flow_dv_remove,
8947 .destroy = flow_dv_destroy,
8948 .query = flow_dv_query,
8949 .create_mtr_tbls = flow_dv_create_mtr_tbl,
8950 .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
8951 .create_policer_rules = flow_dv_create_policer_rules,
8952 .destroy_policer_rules = flow_dv_destroy_policer_rules,
8953 .counter_alloc = flow_dv_counter_allocate,
8954 .counter_free = flow_dv_counter_free,
8955 .counter_query = flow_dv_counter_query,
8958 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */