1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
14 #pragma GCC diagnostic ignored "-Wpedantic"
16 #include <infiniband/verbs.h>
18 #pragma GCC diagnostic error "-Wpedantic"
21 #include <rte_common.h>
22 #include <rte_ether.h>
23 #include <rte_ethdev_driver.h>
25 #include <rte_flow_driver.h>
26 #include <rte_malloc.h>
29 #include <rte_vxlan.h>
32 #include <mlx5_glue.h>
33 #include <mlx5_devx_cmds.h>
36 #include "mlx5_defs.h"
38 #include "mlx5_flow.h"
39 #include "mlx5_rxtx.h"
41 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
43 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
44 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
47 #ifndef HAVE_MLX5DV_DR_ESWITCH
48 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
49 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
53 #ifndef HAVE_MLX5DV_DR
54 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
57 /* VLAN header definitions */
58 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
59 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
60 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
61 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
62 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
77 * Initialize flow attributes structure according to flow items' types.
79 * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
80 * mode. For tunnel mode, the items to be modified are the outermost ones.
83 * Pointer to item specification.
85 * Pointer to flow attributes structure.
87 * Pointer to the sub flow.
88 * @param[in] tunnel_decap
89 * Whether action is after tunnel decapsulation.
92 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
93 struct mlx5_flow *dev_flow, bool tunnel_decap)
95 uint64_t layers = dev_flow->handle->layers;
98 * If layers is already initialized, it means this dev_flow is the
99 * suffix flow, the layers flags is set by the prefix flow. Need to
100 * use the layer flags from prefix flow as the suffix flow may not
101 * have the user defined items as the flow is split.
104 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
106 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
108 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
110 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
115 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
116 uint8_t next_protocol = 0xff;
117 switch (item->type) {
118 case RTE_FLOW_ITEM_TYPE_GRE:
119 case RTE_FLOW_ITEM_TYPE_NVGRE:
120 case RTE_FLOW_ITEM_TYPE_VXLAN:
121 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
122 case RTE_FLOW_ITEM_TYPE_GENEVE:
123 case RTE_FLOW_ITEM_TYPE_MPLS:
127 case RTE_FLOW_ITEM_TYPE_IPV4:
130 if (item->mask != NULL &&
131 ((const struct rte_flow_item_ipv4 *)
132 item->mask)->hdr.next_proto_id)
134 ((const struct rte_flow_item_ipv4 *)
135 (item->spec))->hdr.next_proto_id &
136 ((const struct rte_flow_item_ipv4 *)
137 (item->mask))->hdr.next_proto_id;
138 if ((next_protocol == IPPROTO_IPIP ||
139 next_protocol == IPPROTO_IPV6) && tunnel_decap)
142 case RTE_FLOW_ITEM_TYPE_IPV6:
145 if (item->mask != NULL &&
146 ((const struct rte_flow_item_ipv6 *)
147 item->mask)->hdr.proto)
149 ((const struct rte_flow_item_ipv6 *)
150 (item->spec))->hdr.proto &
151 ((const struct rte_flow_item_ipv6 *)
152 (item->mask))->hdr.proto;
153 if ((next_protocol == IPPROTO_IPIP ||
154 next_protocol == IPPROTO_IPV6) && tunnel_decap)
157 case RTE_FLOW_ITEM_TYPE_UDP:
161 case RTE_FLOW_ITEM_TYPE_TCP:
173 * Convert rte_mtr_color to mlx5 color.
182 rte_col_2_mlx5_col(enum rte_color rcol)
185 case RTE_COLOR_GREEN:
186 return MLX5_FLOW_COLOR_GREEN;
187 case RTE_COLOR_YELLOW:
188 return MLX5_FLOW_COLOR_YELLOW;
190 return MLX5_FLOW_COLOR_RED;
194 return MLX5_FLOW_COLOR_UNDEFINED;
197 struct field_modify_info {
198 uint32_t size; /* Size of field in protocol header, in bytes. */
199 uint32_t offset; /* Offset of field in protocol header, in bytes. */
200 enum mlx5_modification_field id;
203 struct field_modify_info modify_eth[] = {
204 {4, 0, MLX5_MODI_OUT_DMAC_47_16},
205 {2, 4, MLX5_MODI_OUT_DMAC_15_0},
206 {4, 6, MLX5_MODI_OUT_SMAC_47_16},
207 {2, 10, MLX5_MODI_OUT_SMAC_15_0},
211 struct field_modify_info modify_vlan_out_first_vid[] = {
212 /* Size in bits !!! */
213 {12, 0, MLX5_MODI_OUT_FIRST_VID},
217 struct field_modify_info modify_ipv4[] = {
218 {1, 1, MLX5_MODI_OUT_IP_DSCP},
219 {1, 8, MLX5_MODI_OUT_IPV4_TTL},
220 {4, 12, MLX5_MODI_OUT_SIPV4},
221 {4, 16, MLX5_MODI_OUT_DIPV4},
225 struct field_modify_info modify_ipv6[] = {
226 {1, 0, MLX5_MODI_OUT_IP_DSCP},
227 {1, 7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
228 {4, 8, MLX5_MODI_OUT_SIPV6_127_96},
229 {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
230 {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
231 {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
232 {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
233 {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
234 {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
235 {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
239 struct field_modify_info modify_udp[] = {
240 {2, 0, MLX5_MODI_OUT_UDP_SPORT},
241 {2, 2, MLX5_MODI_OUT_UDP_DPORT},
245 struct field_modify_info modify_tcp[] = {
246 {2, 0, MLX5_MODI_OUT_TCP_SPORT},
247 {2, 2, MLX5_MODI_OUT_TCP_DPORT},
248 {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
249 {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
254 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
255 uint8_t next_protocol, uint64_t *item_flags,
258 MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
259 item->type == RTE_FLOW_ITEM_TYPE_IPV6);
260 if (next_protocol == IPPROTO_IPIP) {
261 *item_flags |= MLX5_FLOW_LAYER_IPIP;
264 if (next_protocol == IPPROTO_IPV6) {
265 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
271 * Acquire the synchronizing object to protect multithreaded access
272 * to shared dv context. Lock occurs only if context is actually
273 * shared, i.e. we have multiport IB device and representors are
277 * Pointer to the rte_eth_dev structure.
280 flow_dv_shared_lock(struct rte_eth_dev *dev)
282 struct mlx5_priv *priv = dev->data->dev_private;
283 struct mlx5_ibv_shared *sh = priv->sh;
285 if (sh->dv_refcnt > 1) {
288 ret = pthread_mutex_lock(&sh->dv_mutex);
295 flow_dv_shared_unlock(struct rte_eth_dev *dev)
297 struct mlx5_priv *priv = dev->data->dev_private;
298 struct mlx5_ibv_shared *sh = priv->sh;
300 if (sh->dv_refcnt > 1) {
303 ret = pthread_mutex_unlock(&sh->dv_mutex);
309 /* Update VLAN's VID/PCP based on input rte_flow_action.
312 * Pointer to struct rte_flow_action.
314 * Pointer to struct rte_vlan_hdr.
317 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
318 struct rte_vlan_hdr *vlan)
321 if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
323 ((const struct rte_flow_action_of_set_vlan_pcp *)
324 action->conf)->vlan_pcp;
325 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
326 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
327 vlan->vlan_tci |= vlan_tci;
328 } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
329 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
330 vlan->vlan_tci |= rte_be_to_cpu_16
331 (((const struct rte_flow_action_of_set_vlan_vid *)
332 action->conf)->vlan_vid);
337 * Fetch 1, 2, 3 or 4 byte field from the byte array
338 * and return as unsigned integer in host-endian format.
341 * Pointer to data array.
343 * Size of field to extract.
346 * converted field in host endian format.
348 static inline uint32_t
349 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
358 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
361 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
362 ret = (ret << 8) | *(data + sizeof(uint16_t));
365 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
376 * Convert modify-header action to DV specification.
378 * Data length of each action is determined by provided field description
379 * and the item mask. Data bit offset and width of each action is determined
380 * by provided item mask.
383 * Pointer to item specification.
385 * Pointer to field modification information.
386 * For MLX5_MODIFICATION_TYPE_SET specifies destination field.
387 * For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
388 * For MLX5_MODIFICATION_TYPE_COPY specifies source field.
390 * Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
391 * Negative offset value sets the same offset as source offset.
392 * size field is ignored, value is taken from source field.
393 * @param[in,out] resource
394 * Pointer to the modify-header resource.
396 * Type of modification.
398 * Pointer to the error structure.
401 * 0 on success, a negative errno value otherwise and rte_errno is set.
404 flow_dv_convert_modify_action(struct rte_flow_item *item,
405 struct field_modify_info *field,
406 struct field_modify_info *dcopy,
407 struct mlx5_flow_dv_modify_hdr_resource *resource,
408 uint32_t type, struct rte_flow_error *error)
410 uint32_t i = resource->actions_num;
411 struct mlx5_modification_cmd *actions = resource->actions;
414 * The item and mask are provided in big-endian format.
415 * The fields should be presented as in big-endian format either.
416 * Mask must be always present, it defines the actual field width.
418 MLX5_ASSERT(item->mask);
419 MLX5_ASSERT(field->size);
426 if (i >= MLX5_MAX_MODIFY_NUM)
427 return rte_flow_error_set(error, EINVAL,
428 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
429 "too many items to modify");
430 /* Fetch variable byte size mask from the array. */
431 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
432 field->offset, field->size);
437 /* Deduce actual data width in bits from mask value. */
438 off_b = rte_bsf32(mask);
439 size_b = sizeof(uint32_t) * CHAR_BIT -
440 off_b - __builtin_clz(mask);
442 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
443 actions[i] = (struct mlx5_modification_cmd) {
449 /* Convert entire record to expected big-endian format. */
450 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
451 if (type == MLX5_MODIFICATION_TYPE_COPY) {
453 actions[i].dst_field = dcopy->id;
454 actions[i].dst_offset =
455 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
456 /* Convert entire record to big-endian format. */
457 actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
459 MLX5_ASSERT(item->spec);
460 data = flow_dv_fetch_field((const uint8_t *)item->spec +
461 field->offset, field->size);
462 /* Shift out the trailing masked bits from data. */
463 data = (data & mask) >> off_b;
464 actions[i].data1 = rte_cpu_to_be_32(data);
468 } while (field->size);
469 if (resource->actions_num == i)
470 return rte_flow_error_set(error, EINVAL,
471 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
472 "invalid modification flow item");
473 resource->actions_num = i;
478 * Convert modify-header set IPv4 address action to DV specification.
480 * @param[in,out] resource
481 * Pointer to the modify-header resource.
483 * Pointer to action specification.
485 * Pointer to the error structure.
488 * 0 on success, a negative errno value otherwise and rte_errno is set.
491 flow_dv_convert_action_modify_ipv4
492 (struct mlx5_flow_dv_modify_hdr_resource *resource,
493 const struct rte_flow_action *action,
494 struct rte_flow_error *error)
496 const struct rte_flow_action_set_ipv4 *conf =
497 (const struct rte_flow_action_set_ipv4 *)(action->conf);
498 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
499 struct rte_flow_item_ipv4 ipv4;
500 struct rte_flow_item_ipv4 ipv4_mask;
502 memset(&ipv4, 0, sizeof(ipv4));
503 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
504 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
505 ipv4.hdr.src_addr = conf->ipv4_addr;
506 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
508 ipv4.hdr.dst_addr = conf->ipv4_addr;
509 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
512 item.mask = &ipv4_mask;
513 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
514 MLX5_MODIFICATION_TYPE_SET, error);
518 * Convert modify-header set IPv6 address action to DV specification.
520 * @param[in,out] resource
521 * Pointer to the modify-header resource.
523 * Pointer to action specification.
525 * Pointer to the error structure.
528 * 0 on success, a negative errno value otherwise and rte_errno is set.
531 flow_dv_convert_action_modify_ipv6
532 (struct mlx5_flow_dv_modify_hdr_resource *resource,
533 const struct rte_flow_action *action,
534 struct rte_flow_error *error)
536 const struct rte_flow_action_set_ipv6 *conf =
537 (const struct rte_flow_action_set_ipv6 *)(action->conf);
538 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
539 struct rte_flow_item_ipv6 ipv6;
540 struct rte_flow_item_ipv6 ipv6_mask;
542 memset(&ipv6, 0, sizeof(ipv6));
543 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
544 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
545 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
546 sizeof(ipv6.hdr.src_addr));
547 memcpy(&ipv6_mask.hdr.src_addr,
548 &rte_flow_item_ipv6_mask.hdr.src_addr,
549 sizeof(ipv6.hdr.src_addr));
551 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
552 sizeof(ipv6.hdr.dst_addr));
553 memcpy(&ipv6_mask.hdr.dst_addr,
554 &rte_flow_item_ipv6_mask.hdr.dst_addr,
555 sizeof(ipv6.hdr.dst_addr));
558 item.mask = &ipv6_mask;
559 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
560 MLX5_MODIFICATION_TYPE_SET, error);
564 * Convert modify-header set MAC address action to DV specification.
566 * @param[in,out] resource
567 * Pointer to the modify-header resource.
569 * Pointer to action specification.
571 * Pointer to the error structure.
574 * 0 on success, a negative errno value otherwise and rte_errno is set.
577 flow_dv_convert_action_modify_mac
578 (struct mlx5_flow_dv_modify_hdr_resource *resource,
579 const struct rte_flow_action *action,
580 struct rte_flow_error *error)
582 const struct rte_flow_action_set_mac *conf =
583 (const struct rte_flow_action_set_mac *)(action->conf);
584 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
585 struct rte_flow_item_eth eth;
586 struct rte_flow_item_eth eth_mask;
588 memset(ð, 0, sizeof(eth));
589 memset(ð_mask, 0, sizeof(eth_mask));
590 if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
591 memcpy(ð.src.addr_bytes, &conf->mac_addr,
592 sizeof(eth.src.addr_bytes));
593 memcpy(ð_mask.src.addr_bytes,
594 &rte_flow_item_eth_mask.src.addr_bytes,
595 sizeof(eth_mask.src.addr_bytes));
597 memcpy(ð.dst.addr_bytes, &conf->mac_addr,
598 sizeof(eth.dst.addr_bytes));
599 memcpy(ð_mask.dst.addr_bytes,
600 &rte_flow_item_eth_mask.dst.addr_bytes,
601 sizeof(eth_mask.dst.addr_bytes));
604 item.mask = ð_mask;
605 return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
606 MLX5_MODIFICATION_TYPE_SET, error);
610 * Convert modify-header set VLAN VID action to DV specification.
612 * @param[in,out] resource
613 * Pointer to the modify-header resource.
615 * Pointer to action specification.
617 * Pointer to the error structure.
620 * 0 on success, a negative errno value otherwise and rte_errno is set.
623 flow_dv_convert_action_modify_vlan_vid
624 (struct mlx5_flow_dv_modify_hdr_resource *resource,
625 const struct rte_flow_action *action,
626 struct rte_flow_error *error)
628 const struct rte_flow_action_of_set_vlan_vid *conf =
629 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
630 int i = resource->actions_num;
631 struct mlx5_modification_cmd *actions = resource->actions;
632 struct field_modify_info *field = modify_vlan_out_first_vid;
634 if (i >= MLX5_MAX_MODIFY_NUM)
635 return rte_flow_error_set(error, EINVAL,
636 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
637 "too many items to modify");
638 actions[i] = (struct mlx5_modification_cmd) {
639 .action_type = MLX5_MODIFICATION_TYPE_SET,
641 .length = field->size,
642 .offset = field->offset,
644 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
645 actions[i].data1 = conf->vlan_vid;
646 actions[i].data1 = actions[i].data1 << 16;
647 resource->actions_num = ++i;
652 * Convert modify-header set TP action to DV specification.
654 * @param[in,out] resource
655 * Pointer to the modify-header resource.
657 * Pointer to action specification.
659 * Pointer to rte_flow_item objects list.
661 * Pointer to flow attributes structure.
662 * @param[in] dev_flow
663 * Pointer to the sub flow.
664 * @param[in] tunnel_decap
665 * Whether action is after tunnel decapsulation.
667 * Pointer to the error structure.
670 * 0 on success, a negative errno value otherwise and rte_errno is set.
673 flow_dv_convert_action_modify_tp
674 (struct mlx5_flow_dv_modify_hdr_resource *resource,
675 const struct rte_flow_action *action,
676 const struct rte_flow_item *items,
677 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
678 bool tunnel_decap, struct rte_flow_error *error)
680 const struct rte_flow_action_set_tp *conf =
681 (const struct rte_flow_action_set_tp *)(action->conf);
682 struct rte_flow_item item;
683 struct rte_flow_item_udp udp;
684 struct rte_flow_item_udp udp_mask;
685 struct rte_flow_item_tcp tcp;
686 struct rte_flow_item_tcp tcp_mask;
687 struct field_modify_info *field;
690 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
692 memset(&udp, 0, sizeof(udp));
693 memset(&udp_mask, 0, sizeof(udp_mask));
694 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
695 udp.hdr.src_port = conf->port;
696 udp_mask.hdr.src_port =
697 rte_flow_item_udp_mask.hdr.src_port;
699 udp.hdr.dst_port = conf->port;
700 udp_mask.hdr.dst_port =
701 rte_flow_item_udp_mask.hdr.dst_port;
703 item.type = RTE_FLOW_ITEM_TYPE_UDP;
705 item.mask = &udp_mask;
708 MLX5_ASSERT(attr->tcp);
709 memset(&tcp, 0, sizeof(tcp));
710 memset(&tcp_mask, 0, sizeof(tcp_mask));
711 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
712 tcp.hdr.src_port = conf->port;
713 tcp_mask.hdr.src_port =
714 rte_flow_item_tcp_mask.hdr.src_port;
716 tcp.hdr.dst_port = conf->port;
717 tcp_mask.hdr.dst_port =
718 rte_flow_item_tcp_mask.hdr.dst_port;
720 item.type = RTE_FLOW_ITEM_TYPE_TCP;
722 item.mask = &tcp_mask;
725 return flow_dv_convert_modify_action(&item, field, NULL, resource,
726 MLX5_MODIFICATION_TYPE_SET, error);
730 * Convert modify-header set TTL action to DV specification.
732 * @param[in,out] resource
733 * Pointer to the modify-header resource.
735 * Pointer to action specification.
737 * Pointer to rte_flow_item objects list.
739 * Pointer to flow attributes structure.
740 * @param[in] dev_flow
741 * Pointer to the sub flow.
742 * @param[in] tunnel_decap
743 * Whether action is after tunnel decapsulation.
745 * Pointer to the error structure.
748 * 0 on success, a negative errno value otherwise and rte_errno is set.
751 flow_dv_convert_action_modify_ttl
752 (struct mlx5_flow_dv_modify_hdr_resource *resource,
753 const struct rte_flow_action *action,
754 const struct rte_flow_item *items,
755 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
756 bool tunnel_decap, struct rte_flow_error *error)
758 const struct rte_flow_action_set_ttl *conf =
759 (const struct rte_flow_action_set_ttl *)(action->conf);
760 struct rte_flow_item item;
761 struct rte_flow_item_ipv4 ipv4;
762 struct rte_flow_item_ipv4 ipv4_mask;
763 struct rte_flow_item_ipv6 ipv6;
764 struct rte_flow_item_ipv6 ipv6_mask;
765 struct field_modify_info *field;
768 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
770 memset(&ipv4, 0, sizeof(ipv4));
771 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
772 ipv4.hdr.time_to_live = conf->ttl_value;
773 ipv4_mask.hdr.time_to_live = 0xFF;
774 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
776 item.mask = &ipv4_mask;
779 MLX5_ASSERT(attr->ipv6);
780 memset(&ipv6, 0, sizeof(ipv6));
781 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
782 ipv6.hdr.hop_limits = conf->ttl_value;
783 ipv6_mask.hdr.hop_limits = 0xFF;
784 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
786 item.mask = &ipv6_mask;
789 return flow_dv_convert_modify_action(&item, field, NULL, resource,
790 MLX5_MODIFICATION_TYPE_SET, error);
794 * Convert modify-header decrement TTL action to DV specification.
796 * @param[in,out] resource
797 * Pointer to the modify-header resource.
799 * Pointer to action specification.
801 * Pointer to rte_flow_item objects list.
803 * Pointer to flow attributes structure.
804 * @param[in] dev_flow
805 * Pointer to the sub flow.
806 * @param[in] tunnel_decap
807 * Whether action is after tunnel decapsulation.
809 * Pointer to the error structure.
812 * 0 on success, a negative errno value otherwise and rte_errno is set.
815 flow_dv_convert_action_modify_dec_ttl
816 (struct mlx5_flow_dv_modify_hdr_resource *resource,
817 const struct rte_flow_item *items,
818 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
819 bool tunnel_decap, struct rte_flow_error *error)
821 struct rte_flow_item item;
822 struct rte_flow_item_ipv4 ipv4;
823 struct rte_flow_item_ipv4 ipv4_mask;
824 struct rte_flow_item_ipv6 ipv6;
825 struct rte_flow_item_ipv6 ipv6_mask;
826 struct field_modify_info *field;
829 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
831 memset(&ipv4, 0, sizeof(ipv4));
832 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
833 ipv4.hdr.time_to_live = 0xFF;
834 ipv4_mask.hdr.time_to_live = 0xFF;
835 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
837 item.mask = &ipv4_mask;
840 MLX5_ASSERT(attr->ipv6);
841 memset(&ipv6, 0, sizeof(ipv6));
842 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
843 ipv6.hdr.hop_limits = 0xFF;
844 ipv6_mask.hdr.hop_limits = 0xFF;
845 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
847 item.mask = &ipv6_mask;
850 return flow_dv_convert_modify_action(&item, field, NULL, resource,
851 MLX5_MODIFICATION_TYPE_ADD, error);
855 * Convert modify-header increment/decrement TCP Sequence number
856 * to DV specification.
858 * @param[in,out] resource
859 * Pointer to the modify-header resource.
861 * Pointer to action specification.
863 * Pointer to the error structure.
866 * 0 on success, a negative errno value otherwise and rte_errno is set.
869 flow_dv_convert_action_modify_tcp_seq
870 (struct mlx5_flow_dv_modify_hdr_resource *resource,
871 const struct rte_flow_action *action,
872 struct rte_flow_error *error)
874 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
875 uint64_t value = rte_be_to_cpu_32(*conf);
876 struct rte_flow_item item;
877 struct rte_flow_item_tcp tcp;
878 struct rte_flow_item_tcp tcp_mask;
880 memset(&tcp, 0, sizeof(tcp));
881 memset(&tcp_mask, 0, sizeof(tcp_mask));
882 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
884 * The HW has no decrement operation, only increment operation.
885 * To simulate decrement X from Y using increment operation
886 * we need to add UINT32_MAX X times to Y.
887 * Each adding of UINT32_MAX decrements Y by 1.
890 tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
891 tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
892 item.type = RTE_FLOW_ITEM_TYPE_TCP;
894 item.mask = &tcp_mask;
895 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
896 MLX5_MODIFICATION_TYPE_ADD, error);
900 * Convert modify-header increment/decrement TCP Acknowledgment number
901 * to DV specification.
903 * @param[in,out] resource
904 * Pointer to the modify-header resource.
906 * Pointer to action specification.
908 * Pointer to the error structure.
911 * 0 on success, a negative errno value otherwise and rte_errno is set.
914 flow_dv_convert_action_modify_tcp_ack
915 (struct mlx5_flow_dv_modify_hdr_resource *resource,
916 const struct rte_flow_action *action,
917 struct rte_flow_error *error)
919 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
920 uint64_t value = rte_be_to_cpu_32(*conf);
921 struct rte_flow_item item;
922 struct rte_flow_item_tcp tcp;
923 struct rte_flow_item_tcp tcp_mask;
925 memset(&tcp, 0, sizeof(tcp));
926 memset(&tcp_mask, 0, sizeof(tcp_mask));
927 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
929 * The HW has no decrement operation, only increment operation.
930 * To simulate decrement X from Y using increment operation
931 * we need to add UINT32_MAX X times to Y.
932 * Each adding of UINT32_MAX decrements Y by 1.
935 tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
936 tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
937 item.type = RTE_FLOW_ITEM_TYPE_TCP;
939 item.mask = &tcp_mask;
940 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
941 MLX5_MODIFICATION_TYPE_ADD, error);
944 static enum mlx5_modification_field reg_to_field[] = {
945 [REG_NONE] = MLX5_MODI_OUT_NONE,
946 [REG_A] = MLX5_MODI_META_DATA_REG_A,
947 [REG_B] = MLX5_MODI_META_DATA_REG_B,
948 [REG_C_0] = MLX5_MODI_META_REG_C_0,
949 [REG_C_1] = MLX5_MODI_META_REG_C_1,
950 [REG_C_2] = MLX5_MODI_META_REG_C_2,
951 [REG_C_3] = MLX5_MODI_META_REG_C_3,
952 [REG_C_4] = MLX5_MODI_META_REG_C_4,
953 [REG_C_5] = MLX5_MODI_META_REG_C_5,
954 [REG_C_6] = MLX5_MODI_META_REG_C_6,
955 [REG_C_7] = MLX5_MODI_META_REG_C_7,
959 * Convert register set to DV specification.
961 * @param[in,out] resource
962 * Pointer to the modify-header resource.
964 * Pointer to action specification.
966 * Pointer to the error structure.
969 * 0 on success, a negative errno value otherwise and rte_errno is set.
972 flow_dv_convert_action_set_reg
973 (struct mlx5_flow_dv_modify_hdr_resource *resource,
974 const struct rte_flow_action *action,
975 struct rte_flow_error *error)
977 const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
978 struct mlx5_modification_cmd *actions = resource->actions;
979 uint32_t i = resource->actions_num;
981 if (i >= MLX5_MAX_MODIFY_NUM)
982 return rte_flow_error_set(error, EINVAL,
983 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
984 "too many items to modify");
985 MLX5_ASSERT(conf->id != REG_NONE);
986 MLX5_ASSERT(conf->id < RTE_DIM(reg_to_field));
987 actions[i] = (struct mlx5_modification_cmd) {
988 .action_type = MLX5_MODIFICATION_TYPE_SET,
989 .field = reg_to_field[conf->id],
991 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
992 actions[i].data1 = rte_cpu_to_be_32(conf->data);
994 resource->actions_num = i;
999 * Convert SET_TAG action to DV specification.
1002 * Pointer to the rte_eth_dev structure.
1003 * @param[in,out] resource
1004 * Pointer to the modify-header resource.
1006 * Pointer to action specification.
1008 * Pointer to the error structure.
1011 * 0 on success, a negative errno value otherwise and rte_errno is set.
1014 flow_dv_convert_action_set_tag
1015 (struct rte_eth_dev *dev,
1016 struct mlx5_flow_dv_modify_hdr_resource *resource,
1017 const struct rte_flow_action_set_tag *conf,
1018 struct rte_flow_error *error)
1020 rte_be32_t data = rte_cpu_to_be_32(conf->data);
1021 rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
1022 struct rte_flow_item item = {
1026 struct field_modify_info reg_c_x[] = {
1029 enum mlx5_modification_field reg_type;
1032 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1035 MLX5_ASSERT(ret != REG_NONE);
1036 MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1037 reg_type = reg_to_field[ret];
1038 MLX5_ASSERT(reg_type > 0);
1039 reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1040 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1041 MLX5_MODIFICATION_TYPE_SET, error);
1045 * Convert internal COPY_REG action to DV specification.
1048 * Pointer to the rte_eth_dev structure.
1049 * @param[in,out] res
1050 * Pointer to the modify-header resource.
1052 * Pointer to action specification.
1054 * Pointer to the error structure.
1057 * 0 on success, a negative errno value otherwise and rte_errno is set.
1060 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1061 struct mlx5_flow_dv_modify_hdr_resource *res,
1062 const struct rte_flow_action *action,
1063 struct rte_flow_error *error)
1065 const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1066 rte_be32_t mask = RTE_BE32(UINT32_MAX);
1067 struct rte_flow_item item = {
1071 struct field_modify_info reg_src[] = {
1072 {4, 0, reg_to_field[conf->src]},
1075 struct field_modify_info reg_dst = {
1077 .id = reg_to_field[conf->dst],
1079 /* Adjust reg_c[0] usage according to reported mask. */
1080 if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1081 struct mlx5_priv *priv = dev->data->dev_private;
1082 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1084 MLX5_ASSERT(reg_c0);
1085 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1086 if (conf->dst == REG_C_0) {
1087 /* Copy to reg_c[0], within mask only. */
1088 reg_dst.offset = rte_bsf32(reg_c0);
1090 * Mask is ignoring the enianness, because
1091 * there is no conversion in datapath.
1093 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1094 /* Copy from destination lower bits to reg_c[0]. */
1095 mask = reg_c0 >> reg_dst.offset;
1097 /* Copy from destination upper bits to reg_c[0]. */
1098 mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1099 rte_fls_u32(reg_c0));
1102 mask = rte_cpu_to_be_32(reg_c0);
1103 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1104 /* Copy from reg_c[0] to destination lower bits. */
1107 /* Copy from reg_c[0] to destination upper bits. */
1108 reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1109 (rte_fls_u32(reg_c0) -
1114 return flow_dv_convert_modify_action(&item,
1115 reg_src, ®_dst, res,
1116 MLX5_MODIFICATION_TYPE_COPY,
1121 * Convert MARK action to DV specification. This routine is used
1122 * in extensive metadata only and requires metadata register to be
1123 * handled. In legacy mode hardware tag resource is engaged.
1126 * Pointer to the rte_eth_dev structure.
1128 * Pointer to MARK action specification.
1129 * @param[in,out] resource
1130 * Pointer to the modify-header resource.
1132 * Pointer to the error structure.
1135 * 0 on success, a negative errno value otherwise and rte_errno is set.
1138 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1139 const struct rte_flow_action_mark *conf,
1140 struct mlx5_flow_dv_modify_hdr_resource *resource,
1141 struct rte_flow_error *error)
1143 struct mlx5_priv *priv = dev->data->dev_private;
1144 rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1145 priv->sh->dv_mark_mask);
1146 rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1147 struct rte_flow_item item = {
1151 struct field_modify_info reg_c_x[] = {
1152 {4, 0, 0}, /* dynamic instead of MLX5_MODI_META_REG_C_1. */
1158 return rte_flow_error_set(error, EINVAL,
1159 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1160 NULL, "zero mark action mask");
1161 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1164 MLX5_ASSERT(reg > 0);
1165 if (reg == REG_C_0) {
1166 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1167 uint32_t shl_c0 = rte_bsf32(msk_c0);
1169 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1170 mask = rte_cpu_to_be_32(mask) & msk_c0;
1171 mask = rte_cpu_to_be_32(mask << shl_c0);
1173 reg_c_x[0].id = reg_to_field[reg];
1174 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1175 MLX5_MODIFICATION_TYPE_SET, error);
1179 * Get metadata register index for specified steering domain.
1182 * Pointer to the rte_eth_dev structure.
1184 * Attributes of flow to determine steering domain.
1186 * Pointer to the error structure.
1189 * positive index on success, a negative errno value otherwise
1190 * and rte_errno is set.
1192 static enum modify_reg
1193 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1194 const struct rte_flow_attr *attr,
1195 struct rte_flow_error *error)
1198 mlx5_flow_get_reg_id(dev, attr->transfer ?
1202 MLX5_METADATA_RX, 0, error);
1204 return rte_flow_error_set(error,
1205 ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1206 NULL, "unavailable "
1207 "metadata register");
1212 * Convert SET_META action to DV specification.
1215 * Pointer to the rte_eth_dev structure.
1216 * @param[in,out] resource
1217 * Pointer to the modify-header resource.
1219 * Attributes of flow that includes this item.
1221 * Pointer to action specification.
1223 * Pointer to the error structure.
1226 * 0 on success, a negative errno value otherwise and rte_errno is set.
1229 flow_dv_convert_action_set_meta
1230 (struct rte_eth_dev *dev,
1231 struct mlx5_flow_dv_modify_hdr_resource *resource,
1232 const struct rte_flow_attr *attr,
1233 const struct rte_flow_action_set_meta *conf,
1234 struct rte_flow_error *error)
1236 uint32_t data = conf->data;
1237 uint32_t mask = conf->mask;
1238 struct rte_flow_item item = {
1242 struct field_modify_info reg_c_x[] = {
1245 int reg = flow_dv_get_metadata_reg(dev, attr, error);
1250 * In datapath code there is no endianness
1251 * coversions for perfromance reasons, all
1252 * pattern conversions are done in rte_flow.
1254 if (reg == REG_C_0) {
1255 struct mlx5_priv *priv = dev->data->dev_private;
1256 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1259 MLX5_ASSERT(msk_c0);
1260 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1261 shl_c0 = rte_bsf32(msk_c0);
1263 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1267 MLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1269 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1270 /* The routine expects parameters in memory as big-endian ones. */
1271 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1272 MLX5_MODIFICATION_TYPE_SET, error);
1276 * Convert modify-header set IPv4 DSCP action to DV specification.
1278 * @param[in,out] resource
1279 * Pointer to the modify-header resource.
1281 * Pointer to action specification.
1283 * Pointer to the error structure.
1286 * 0 on success, a negative errno value otherwise and rte_errno is set.
1289 flow_dv_convert_action_modify_ipv4_dscp
1290 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1291 const struct rte_flow_action *action,
1292 struct rte_flow_error *error)
1294 const struct rte_flow_action_set_dscp *conf =
1295 (const struct rte_flow_action_set_dscp *)(action->conf);
1296 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1297 struct rte_flow_item_ipv4 ipv4;
1298 struct rte_flow_item_ipv4 ipv4_mask;
1300 memset(&ipv4, 0, sizeof(ipv4));
1301 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1302 ipv4.hdr.type_of_service = conf->dscp;
1303 ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1305 item.mask = &ipv4_mask;
1306 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1307 MLX5_MODIFICATION_TYPE_SET, error);
1311 * Convert modify-header set IPv6 DSCP action to DV specification.
1313 * @param[in,out] resource
1314 * Pointer to the modify-header resource.
1316 * Pointer to action specification.
1318 * Pointer to the error structure.
1321 * 0 on success, a negative errno value otherwise and rte_errno is set.
1324 flow_dv_convert_action_modify_ipv6_dscp
1325 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1326 const struct rte_flow_action *action,
1327 struct rte_flow_error *error)
1329 const struct rte_flow_action_set_dscp *conf =
1330 (const struct rte_flow_action_set_dscp *)(action->conf);
1331 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1332 struct rte_flow_item_ipv6 ipv6;
1333 struct rte_flow_item_ipv6 ipv6_mask;
1335 memset(&ipv6, 0, sizeof(ipv6));
1336 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1338 * Even though the DSCP bits offset of IPv6 is not byte aligned,
1339 * rdma-core only accept the DSCP bits byte aligned start from
1340 * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1341 * bits in IPv6 case as rdma-core requires byte aligned value.
1343 ipv6.hdr.vtc_flow = conf->dscp;
1344 ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1346 item.mask = &ipv6_mask;
1347 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1348 MLX5_MODIFICATION_TYPE_SET, error);
1352 * Validate MARK item.
1355 * Pointer to the rte_eth_dev structure.
1357 * Item specification.
1359 * Attributes of flow that includes this item.
1361 * Pointer to error structure.
1364 * 0 on success, a negative errno value otherwise and rte_errno is set.
1367 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1368 const struct rte_flow_item *item,
1369 const struct rte_flow_attr *attr __rte_unused,
1370 struct rte_flow_error *error)
1372 struct mlx5_priv *priv = dev->data->dev_private;
1373 struct mlx5_dev_config *config = &priv->config;
1374 const struct rte_flow_item_mark *spec = item->spec;
1375 const struct rte_flow_item_mark *mask = item->mask;
1376 const struct rte_flow_item_mark nic_mask = {
1377 .id = priv->sh->dv_mark_mask,
1381 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1382 return rte_flow_error_set(error, ENOTSUP,
1383 RTE_FLOW_ERROR_TYPE_ITEM, item,
1384 "extended metadata feature"
1386 if (!mlx5_flow_ext_mreg_supported(dev))
1387 return rte_flow_error_set(error, ENOTSUP,
1388 RTE_FLOW_ERROR_TYPE_ITEM, item,
1389 "extended metadata register"
1390 " isn't supported");
1392 return rte_flow_error_set(error, ENOTSUP,
1393 RTE_FLOW_ERROR_TYPE_ITEM, item,
1394 "extended metadata register"
1395 " isn't available");
1396 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1400 return rte_flow_error_set(error, EINVAL,
1401 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1403 "data cannot be empty");
1404 if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1405 return rte_flow_error_set(error, EINVAL,
1406 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1408 "mark id exceeds the limit");
1412 return rte_flow_error_set(error, EINVAL,
1413 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1414 "mask cannot be zero");
1416 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1417 (const uint8_t *)&nic_mask,
1418 sizeof(struct rte_flow_item_mark),
1426 * Validate META item.
1429 * Pointer to the rte_eth_dev structure.
1431 * Item specification.
1433 * Attributes of flow that includes this item.
1435 * Pointer to error structure.
1438 * 0 on success, a negative errno value otherwise and rte_errno is set.
1441 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1442 const struct rte_flow_item *item,
1443 const struct rte_flow_attr *attr,
1444 struct rte_flow_error *error)
1446 struct mlx5_priv *priv = dev->data->dev_private;
1447 struct mlx5_dev_config *config = &priv->config;
1448 const struct rte_flow_item_meta *spec = item->spec;
1449 const struct rte_flow_item_meta *mask = item->mask;
1450 struct rte_flow_item_meta nic_mask = {
1457 return rte_flow_error_set(error, EINVAL,
1458 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1460 "data cannot be empty");
1461 if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1462 if (!mlx5_flow_ext_mreg_supported(dev))
1463 return rte_flow_error_set(error, ENOTSUP,
1464 RTE_FLOW_ERROR_TYPE_ITEM, item,
1465 "extended metadata register"
1466 " isn't supported");
1467 reg = flow_dv_get_metadata_reg(dev, attr, error);
1471 return rte_flow_error_set(error, ENOTSUP,
1472 RTE_FLOW_ERROR_TYPE_ITEM, item,
1476 nic_mask.data = priv->sh->dv_meta_mask;
1479 mask = &rte_flow_item_meta_mask;
1481 return rte_flow_error_set(error, EINVAL,
1482 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1483 "mask cannot be zero");
1485 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1486 (const uint8_t *)&nic_mask,
1487 sizeof(struct rte_flow_item_meta),
1493 * Validate TAG item.
1496 * Pointer to the rte_eth_dev structure.
1498 * Item specification.
1500 * Attributes of flow that includes this item.
1502 * Pointer to error structure.
1505 * 0 on success, a negative errno value otherwise and rte_errno is set.
1508 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
1509 const struct rte_flow_item *item,
1510 const struct rte_flow_attr *attr __rte_unused,
1511 struct rte_flow_error *error)
1513 const struct rte_flow_item_tag *spec = item->spec;
1514 const struct rte_flow_item_tag *mask = item->mask;
1515 const struct rte_flow_item_tag nic_mask = {
1516 .data = RTE_BE32(UINT32_MAX),
1521 if (!mlx5_flow_ext_mreg_supported(dev))
1522 return rte_flow_error_set(error, ENOTSUP,
1523 RTE_FLOW_ERROR_TYPE_ITEM, item,
1524 "extensive metadata register"
1525 " isn't supported");
1527 return rte_flow_error_set(error, EINVAL,
1528 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1530 "data cannot be empty");
1532 mask = &rte_flow_item_tag_mask;
1534 return rte_flow_error_set(error, EINVAL,
1535 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1536 "mask cannot be zero");
1538 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1539 (const uint8_t *)&nic_mask,
1540 sizeof(struct rte_flow_item_tag),
1544 if (mask->index != 0xff)
1545 return rte_flow_error_set(error, EINVAL,
1546 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1547 "partial mask for tag index"
1548 " is not supported");
1549 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
1552 MLX5_ASSERT(ret != REG_NONE);
1557 * Validate vport item.
1560 * Pointer to the rte_eth_dev structure.
1562 * Item specification.
1564 * Attributes of flow that includes this item.
1565 * @param[in] item_flags
1566 * Bit-fields that holds the items detected until now.
1568 * Pointer to error structure.
1571 * 0 on success, a negative errno value otherwise and rte_errno is set.
1574 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
1575 const struct rte_flow_item *item,
1576 const struct rte_flow_attr *attr,
1577 uint64_t item_flags,
1578 struct rte_flow_error *error)
1580 const struct rte_flow_item_port_id *spec = item->spec;
1581 const struct rte_flow_item_port_id *mask = item->mask;
1582 const struct rte_flow_item_port_id switch_mask = {
1585 struct mlx5_priv *esw_priv;
1586 struct mlx5_priv *dev_priv;
1589 if (!attr->transfer)
1590 return rte_flow_error_set(error, EINVAL,
1591 RTE_FLOW_ERROR_TYPE_ITEM,
1593 "match on port id is valid only"
1594 " when transfer flag is enabled");
1595 if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
1596 return rte_flow_error_set(error, ENOTSUP,
1597 RTE_FLOW_ERROR_TYPE_ITEM, item,
1598 "multiple source ports are not"
1601 mask = &switch_mask;
1602 if (mask->id != 0xffffffff)
1603 return rte_flow_error_set(error, ENOTSUP,
1604 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1606 "no support for partial mask on"
1608 ret = mlx5_flow_item_acceptable
1609 (item, (const uint8_t *)mask,
1610 (const uint8_t *)&rte_flow_item_port_id_mask,
1611 sizeof(struct rte_flow_item_port_id),
1617 esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
1619 return rte_flow_error_set(error, rte_errno,
1620 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1621 "failed to obtain E-Switch info for"
1623 dev_priv = mlx5_dev_to_eswitch_info(dev);
1625 return rte_flow_error_set(error, rte_errno,
1626 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1628 "failed to obtain E-Switch info");
1629 if (esw_priv->domain_id != dev_priv->domain_id)
1630 return rte_flow_error_set(error, EINVAL,
1631 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1632 "cannot match on a port from a"
1633 " different E-Switch");
1638 * Validate GTP item.
1641 * Pointer to the rte_eth_dev structure.
1643 * Item specification.
1644 * @param[in] item_flags
1645 * Bit-fields that holds the items detected until now.
1647 * Pointer to error structure.
1650 * 0 on success, a negative errno value otherwise and rte_errno is set.
1653 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
1654 const struct rte_flow_item *item,
1655 uint64_t item_flags,
1656 struct rte_flow_error *error)
1658 struct mlx5_priv *priv = dev->data->dev_private;
1659 const struct rte_flow_item_gtp *mask = item->mask;
1660 const struct rte_flow_item_gtp nic_mask = {
1662 .teid = RTE_BE32(0xffffffff),
1665 if (!priv->config.hca_attr.tunnel_stateless_gtp)
1666 return rte_flow_error_set(error, ENOTSUP,
1667 RTE_FLOW_ERROR_TYPE_ITEM, item,
1668 "GTP support is not enabled");
1669 if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
1670 return rte_flow_error_set(error, ENOTSUP,
1671 RTE_FLOW_ERROR_TYPE_ITEM, item,
1672 "multiple tunnel layers not"
1674 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
1675 return rte_flow_error_set(error, EINVAL,
1676 RTE_FLOW_ERROR_TYPE_ITEM, item,
1677 "no outer UDP layer found");
1679 mask = &rte_flow_item_gtp_mask;
1680 return mlx5_flow_item_acceptable
1681 (item, (const uint8_t *)mask,
1682 (const uint8_t *)&nic_mask,
1683 sizeof(struct rte_flow_item_gtp),
1688 * Validate the pop VLAN action.
1691 * Pointer to the rte_eth_dev structure.
1692 * @param[in] action_flags
1693 * Holds the actions detected until now.
1695 * Pointer to the pop vlan action.
1696 * @param[in] item_flags
1697 * The items found in this flow rule.
1699 * Pointer to flow attributes.
1701 * Pointer to error structure.
1704 * 0 on success, a negative errno value otherwise and rte_errno is set.
1707 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
1708 uint64_t action_flags,
1709 const struct rte_flow_action *action,
1710 uint64_t item_flags,
1711 const struct rte_flow_attr *attr,
1712 struct rte_flow_error *error)
1714 const struct mlx5_priv *priv = dev->data->dev_private;
1718 if (!priv->sh->pop_vlan_action)
1719 return rte_flow_error_set(error, ENOTSUP,
1720 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1722 "pop vlan action is not supported");
1724 return rte_flow_error_set(error, ENOTSUP,
1725 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1727 "pop vlan action not supported for "
1729 if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
1730 return rte_flow_error_set(error, ENOTSUP,
1731 RTE_FLOW_ERROR_TYPE_ACTION, action,
1732 "no support for multiple VLAN "
1734 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1735 return rte_flow_error_set(error, ENOTSUP,
1736 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1738 "cannot pop vlan without a "
1739 "match on (outer) vlan in the flow");
1740 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1741 return rte_flow_error_set(error, EINVAL,
1742 RTE_FLOW_ERROR_TYPE_ACTION, action,
1743 "wrong action order, port_id should "
1744 "be after pop VLAN action");
1745 if (!attr->transfer && priv->representor)
1746 return rte_flow_error_set(error, ENOTSUP,
1747 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1748 "pop vlan action for VF representor "
1749 "not supported on NIC table");
1754 * Get VLAN default info from vlan match info.
1757 * the list of item specifications.
1759 * pointer VLAN info to fill to.
1762 * 0 on success, a negative errno value otherwise and rte_errno is set.
1765 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
1766 struct rte_vlan_hdr *vlan)
1768 const struct rte_flow_item_vlan nic_mask = {
1769 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
1770 MLX5DV_FLOW_VLAN_VID_MASK),
1771 .inner_type = RTE_BE16(0xffff),
1776 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
1777 int type = items->type;
1779 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
1780 type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
1783 if (items->type != RTE_FLOW_ITEM_TYPE_END) {
1784 const struct rte_flow_item_vlan *vlan_m = items->mask;
1785 const struct rte_flow_item_vlan *vlan_v = items->spec;
1789 /* Only full match values are accepted */
1790 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
1791 MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
1792 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
1794 rte_be_to_cpu_16(vlan_v->tci &
1795 MLX5DV_FLOW_VLAN_PCP_MASK_BE);
1797 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
1798 MLX5DV_FLOW_VLAN_VID_MASK_BE) {
1799 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
1801 rte_be_to_cpu_16(vlan_v->tci &
1802 MLX5DV_FLOW_VLAN_VID_MASK_BE);
1804 if (vlan_m->inner_type == nic_mask.inner_type)
1805 vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
1806 vlan_m->inner_type);
1811 * Validate the push VLAN action.
1814 * Pointer to the rte_eth_dev structure.
1815 * @param[in] action_flags
1816 * Holds the actions detected until now.
1817 * @param[in] item_flags
1818 * The items found in this flow rule.
1820 * Pointer to the action structure.
1822 * Pointer to flow attributes
1824 * Pointer to error structure.
1827 * 0 on success, a negative errno value otherwise and rte_errno is set.
1830 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
1831 uint64_t action_flags,
1832 uint64_t item_flags __rte_unused,
1833 const struct rte_flow_action *action,
1834 const struct rte_flow_attr *attr,
1835 struct rte_flow_error *error)
1837 const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
1838 const struct mlx5_priv *priv = dev->data->dev_private;
1840 if (!attr->transfer && attr->ingress)
1841 return rte_flow_error_set(error, ENOTSUP,
1842 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1844 "push VLAN action not supported for "
1846 if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
1847 push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
1848 return rte_flow_error_set(error, EINVAL,
1849 RTE_FLOW_ERROR_TYPE_ACTION, action,
1850 "invalid vlan ethertype");
1851 if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
1852 return rte_flow_error_set(error, ENOTSUP,
1853 RTE_FLOW_ERROR_TYPE_ACTION, action,
1854 "no support for multiple VLAN "
1856 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1857 return rte_flow_error_set(error, EINVAL,
1858 RTE_FLOW_ERROR_TYPE_ACTION, action,
1859 "wrong action order, port_id should "
1860 "be after push VLAN");
1861 if (!attr->transfer && priv->representor)
1862 return rte_flow_error_set(error, ENOTSUP,
1863 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1864 "push vlan action for VF representor "
1865 "not supported on NIC table");
1871 * Validate the set VLAN PCP.
1873 * @param[in] action_flags
1874 * Holds the actions detected until now.
1875 * @param[in] actions
1876 * Pointer to the list of actions remaining in the flow rule.
1878 * Pointer to error structure.
1881 * 0 on success, a negative errno value otherwise and rte_errno is set.
1884 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
1885 const struct rte_flow_action actions[],
1886 struct rte_flow_error *error)
1888 const struct rte_flow_action *action = actions;
1889 const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
1891 if (conf->vlan_pcp > 7)
1892 return rte_flow_error_set(error, EINVAL,
1893 RTE_FLOW_ERROR_TYPE_ACTION, action,
1894 "VLAN PCP value is too big");
1895 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
1896 return rte_flow_error_set(error, ENOTSUP,
1897 RTE_FLOW_ERROR_TYPE_ACTION, action,
1898 "set VLAN PCP action must follow "
1899 "the push VLAN action");
1900 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
1901 return rte_flow_error_set(error, ENOTSUP,
1902 RTE_FLOW_ERROR_TYPE_ACTION, action,
1903 "Multiple VLAN PCP modification are "
1905 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1906 return rte_flow_error_set(error, EINVAL,
1907 RTE_FLOW_ERROR_TYPE_ACTION, action,
1908 "wrong action order, port_id should "
1909 "be after set VLAN PCP");
1914 * Validate the set VLAN VID.
1916 * @param[in] item_flags
1917 * Holds the items detected in this rule.
1918 * @param[in] action_flags
1919 * Holds the actions detected until now.
1920 * @param[in] actions
1921 * Pointer to the list of actions remaining in the flow rule.
1923 * Pointer to error structure.
1926 * 0 on success, a negative errno value otherwise and rte_errno is set.
1929 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
1930 uint64_t action_flags,
1931 const struct rte_flow_action actions[],
1932 struct rte_flow_error *error)
1934 const struct rte_flow_action *action = actions;
1935 const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
1937 if (conf->vlan_vid > RTE_BE16(0xFFE))
1938 return rte_flow_error_set(error, EINVAL,
1939 RTE_FLOW_ERROR_TYPE_ACTION, action,
1940 "VLAN VID value is too big");
1941 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
1942 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1943 return rte_flow_error_set(error, ENOTSUP,
1944 RTE_FLOW_ERROR_TYPE_ACTION, action,
1945 "set VLAN VID action must follow push"
1946 " VLAN action or match on VLAN item");
1947 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
1948 return rte_flow_error_set(error, ENOTSUP,
1949 RTE_FLOW_ERROR_TYPE_ACTION, action,
1950 "Multiple VLAN VID modifications are "
1952 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1953 return rte_flow_error_set(error, EINVAL,
1954 RTE_FLOW_ERROR_TYPE_ACTION, action,
1955 "wrong action order, port_id should "
1956 "be after set VLAN VID");
1961 * Validate the FLAG action.
1964 * Pointer to the rte_eth_dev structure.
1965 * @param[in] action_flags
1966 * Holds the actions detected until now.
1968 * Pointer to flow attributes
1970 * Pointer to error structure.
1973 * 0 on success, a negative errno value otherwise and rte_errno is set.
1976 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
1977 uint64_t action_flags,
1978 const struct rte_flow_attr *attr,
1979 struct rte_flow_error *error)
1981 struct mlx5_priv *priv = dev->data->dev_private;
1982 struct mlx5_dev_config *config = &priv->config;
1985 /* Fall back if no extended metadata register support. */
1986 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1987 return mlx5_flow_validate_action_flag(action_flags, attr,
1989 /* Extensive metadata mode requires registers. */
1990 if (!mlx5_flow_ext_mreg_supported(dev))
1991 return rte_flow_error_set(error, ENOTSUP,
1992 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1993 "no metadata registers "
1994 "to support flag action");
1995 if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
1996 return rte_flow_error_set(error, ENOTSUP,
1997 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1998 "extended metadata register"
1999 " isn't available");
2000 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2003 MLX5_ASSERT(ret > 0);
2004 if (action_flags & MLX5_FLOW_ACTION_MARK)
2005 return rte_flow_error_set(error, EINVAL,
2006 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2007 "can't mark and flag in same flow");
2008 if (action_flags & MLX5_FLOW_ACTION_FLAG)
2009 return rte_flow_error_set(error, EINVAL,
2010 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2012 " actions in same flow");
2017 * Validate MARK action.
2020 * Pointer to the rte_eth_dev structure.
2022 * Pointer to action.
2023 * @param[in] action_flags
2024 * Holds the actions detected until now.
2026 * Pointer to flow attributes
2028 * Pointer to error structure.
2031 * 0 on success, a negative errno value otherwise and rte_errno is set.
2034 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
2035 const struct rte_flow_action *action,
2036 uint64_t action_flags,
2037 const struct rte_flow_attr *attr,
2038 struct rte_flow_error *error)
2040 struct mlx5_priv *priv = dev->data->dev_private;
2041 struct mlx5_dev_config *config = &priv->config;
2042 const struct rte_flow_action_mark *mark = action->conf;
2045 /* Fall back if no extended metadata register support. */
2046 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2047 return mlx5_flow_validate_action_mark(action, action_flags,
2049 /* Extensive metadata mode requires registers. */
2050 if (!mlx5_flow_ext_mreg_supported(dev))
2051 return rte_flow_error_set(error, ENOTSUP,
2052 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2053 "no metadata registers "
2054 "to support mark action");
2055 if (!priv->sh->dv_mark_mask)
2056 return rte_flow_error_set(error, ENOTSUP,
2057 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2058 "extended metadata register"
2059 " isn't available");
2060 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2063 MLX5_ASSERT(ret > 0);
2065 return rte_flow_error_set(error, EINVAL,
2066 RTE_FLOW_ERROR_TYPE_ACTION, action,
2067 "configuration cannot be null");
2068 if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
2069 return rte_flow_error_set(error, EINVAL,
2070 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2072 "mark id exceeds the limit");
2073 if (action_flags & MLX5_FLOW_ACTION_FLAG)
2074 return rte_flow_error_set(error, EINVAL,
2075 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2076 "can't flag and mark in same flow");
2077 if (action_flags & MLX5_FLOW_ACTION_MARK)
2078 return rte_flow_error_set(error, EINVAL,
2079 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2080 "can't have 2 mark actions in same"
2086 * Validate SET_META action.
2089 * Pointer to the rte_eth_dev structure.
2091 * Pointer to the action structure.
2092 * @param[in] action_flags
2093 * Holds the actions detected until now.
2095 * Pointer to flow attributes
2097 * Pointer to error structure.
2100 * 0 on success, a negative errno value otherwise and rte_errno is set.
2103 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
2104 const struct rte_flow_action *action,
2105 uint64_t action_flags __rte_unused,
2106 const struct rte_flow_attr *attr,
2107 struct rte_flow_error *error)
2109 const struct rte_flow_action_set_meta *conf;
2110 uint32_t nic_mask = UINT32_MAX;
2113 if (!mlx5_flow_ext_mreg_supported(dev))
2114 return rte_flow_error_set(error, ENOTSUP,
2115 RTE_FLOW_ERROR_TYPE_ACTION, action,
2116 "extended metadata register"
2117 " isn't supported");
2118 reg = flow_dv_get_metadata_reg(dev, attr, error);
2121 if (reg != REG_A && reg != REG_B) {
2122 struct mlx5_priv *priv = dev->data->dev_private;
2124 nic_mask = priv->sh->dv_meta_mask;
2126 if (!(action->conf))
2127 return rte_flow_error_set(error, EINVAL,
2128 RTE_FLOW_ERROR_TYPE_ACTION, action,
2129 "configuration cannot be null");
2130 conf = (const struct rte_flow_action_set_meta *)action->conf;
2132 return rte_flow_error_set(error, EINVAL,
2133 RTE_FLOW_ERROR_TYPE_ACTION, action,
2134 "zero mask doesn't have any effect");
2135 if (conf->mask & ~nic_mask)
2136 return rte_flow_error_set(error, EINVAL,
2137 RTE_FLOW_ERROR_TYPE_ACTION, action,
2138 "meta data must be within reg C0");
2143 * Validate SET_TAG action.
2146 * Pointer to the rte_eth_dev structure.
2148 * Pointer to the action structure.
2149 * @param[in] action_flags
2150 * Holds the actions detected until now.
2152 * Pointer to flow attributes
2154 * Pointer to error structure.
2157 * 0 on success, a negative errno value otherwise and rte_errno is set.
2160 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
2161 const struct rte_flow_action *action,
2162 uint64_t action_flags,
2163 const struct rte_flow_attr *attr,
2164 struct rte_flow_error *error)
2166 const struct rte_flow_action_set_tag *conf;
2167 const uint64_t terminal_action_flags =
2168 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
2169 MLX5_FLOW_ACTION_RSS;
2172 if (!mlx5_flow_ext_mreg_supported(dev))
2173 return rte_flow_error_set(error, ENOTSUP,
2174 RTE_FLOW_ERROR_TYPE_ACTION, action,
2175 "extensive metadata register"
2176 " isn't supported");
2177 if (!(action->conf))
2178 return rte_flow_error_set(error, EINVAL,
2179 RTE_FLOW_ERROR_TYPE_ACTION, action,
2180 "configuration cannot be null");
2181 conf = (const struct rte_flow_action_set_tag *)action->conf;
2183 return rte_flow_error_set(error, EINVAL,
2184 RTE_FLOW_ERROR_TYPE_ACTION, action,
2185 "zero mask doesn't have any effect");
2186 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
2189 if (!attr->transfer && attr->ingress &&
2190 (action_flags & terminal_action_flags))
2191 return rte_flow_error_set(error, EINVAL,
2192 RTE_FLOW_ERROR_TYPE_ACTION, action,
2193 "set_tag has no effect"
2194 " with terminal actions");
2199 * Validate count action.
2202 * Pointer to rte_eth_dev structure.
2204 * Pointer to error structure.
2207 * 0 on success, a negative errno value otherwise and rte_errno is set.
2210 flow_dv_validate_action_count(struct rte_eth_dev *dev,
2211 struct rte_flow_error *error)
2213 struct mlx5_priv *priv = dev->data->dev_private;
2215 if (!priv->config.devx)
2217 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
2221 return rte_flow_error_set
2223 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2225 "count action not supported");
2229 * Validate the L2 encap action.
2232 * Pointer to the rte_eth_dev structure.
2233 * @param[in] action_flags
2234 * Holds the actions detected until now.
2236 * Pointer to the action structure.
2238 * Pointer to flow attributes.
2240 * Pointer to error structure.
2243 * 0 on success, a negative errno value otherwise and rte_errno is set.
2246 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
2247 uint64_t action_flags,
2248 const struct rte_flow_action *action,
2249 const struct rte_flow_attr *attr,
2250 struct rte_flow_error *error)
2252 const struct mlx5_priv *priv = dev->data->dev_private;
2254 if (!(action->conf))
2255 return rte_flow_error_set(error, EINVAL,
2256 RTE_FLOW_ERROR_TYPE_ACTION, action,
2257 "configuration cannot be null");
2258 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
2259 return rte_flow_error_set(error, EINVAL,
2260 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2261 "can only have a single encap action "
2263 if (!attr->transfer && priv->representor)
2264 return rte_flow_error_set(error, ENOTSUP,
2265 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2266 "encap action for VF representor "
2267 "not supported on NIC table");
2272 * Validate a decap action.
2275 * Pointer to the rte_eth_dev structure.
2276 * @param[in] action_flags
2277 * Holds the actions detected until now.
2279 * Pointer to flow attributes
2281 * Pointer to error structure.
2284 * 0 on success, a negative errno value otherwise and rte_errno is set.
2287 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
2288 uint64_t action_flags,
2289 const struct rte_flow_attr *attr,
2290 struct rte_flow_error *error)
2292 const struct mlx5_priv *priv = dev->data->dev_private;
2294 if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
2295 return rte_flow_error_set(error, ENOTSUP,
2296 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2298 MLX5_FLOW_ACTION_DECAP ? "can only "
2299 "have a single decap action" : "decap "
2300 "after encap is not supported");
2301 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
2302 return rte_flow_error_set(error, EINVAL,
2303 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2304 "can't have decap action after"
2307 return rte_flow_error_set(error, ENOTSUP,
2308 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2310 "decap action not supported for "
2312 if (!attr->transfer && priv->representor)
2313 return rte_flow_error_set(error, ENOTSUP,
2314 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2315 "decap action for VF representor "
2316 "not supported on NIC table");
2320 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
2323 * Validate the raw encap and decap actions.
2326 * Pointer to the rte_eth_dev structure.
2328 * Pointer to the decap action.
2330 * Pointer to the encap action.
2332 * Pointer to flow attributes
2333 * @param[in/out] action_flags
2334 * Holds the actions detected until now.
2335 * @param[out] actions_n
2336 * pointer to the number of actions counter.
2338 * Pointer to error structure.
2341 * 0 on success, a negative errno value otherwise and rte_errno is set.
2344 flow_dv_validate_action_raw_encap_decap
2345 (struct rte_eth_dev *dev,
2346 const struct rte_flow_action_raw_decap *decap,
2347 const struct rte_flow_action_raw_encap *encap,
2348 const struct rte_flow_attr *attr, uint64_t *action_flags,
2349 int *actions_n, struct rte_flow_error *error)
2351 const struct mlx5_priv *priv = dev->data->dev_private;
2354 if (encap && (!encap->size || !encap->data))
2355 return rte_flow_error_set(error, EINVAL,
2356 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2357 "raw encap data cannot be empty");
2358 if (decap && encap) {
2359 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
2360 encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
2363 else if (encap->size <=
2364 MLX5_ENCAPSULATION_DECISION_SIZE &&
2366 MLX5_ENCAPSULATION_DECISION_SIZE)
2369 else if (encap->size >
2370 MLX5_ENCAPSULATION_DECISION_SIZE &&
2372 MLX5_ENCAPSULATION_DECISION_SIZE)
2373 /* 2 L2 actions: encap and decap. */
2376 return rte_flow_error_set(error,
2378 RTE_FLOW_ERROR_TYPE_ACTION,
2379 NULL, "unsupported too small "
2380 "raw decap and too small raw "
2381 "encap combination");
2384 ret = flow_dv_validate_action_decap(dev, *action_flags, attr,
2388 *action_flags |= MLX5_FLOW_ACTION_DECAP;
2392 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
2393 return rte_flow_error_set(error, ENOTSUP,
2394 RTE_FLOW_ERROR_TYPE_ACTION,
2396 "small raw encap size");
2397 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
2398 return rte_flow_error_set(error, EINVAL,
2399 RTE_FLOW_ERROR_TYPE_ACTION,
2401 "more than one encap action");
2402 if (!attr->transfer && priv->representor)
2403 return rte_flow_error_set
2405 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2406 "encap action for VF representor "
2407 "not supported on NIC table");
2408 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
2415 * Find existing encap/decap resource or create and register a new one.
2417 * @param[in, out] dev
2418 * Pointer to rte_eth_dev structure.
2419 * @param[in, out] resource
2420 * Pointer to encap/decap resource.
2421 * @parm[in, out] dev_flow
2422 * Pointer to the dev_flow.
2424 * pointer to error structure.
2427 * 0 on success otherwise -errno and errno is set.
2430 flow_dv_encap_decap_resource_register
2431 (struct rte_eth_dev *dev,
2432 struct mlx5_flow_dv_encap_decap_resource *resource,
2433 struct mlx5_flow *dev_flow,
2434 struct rte_flow_error *error)
2436 struct mlx5_priv *priv = dev->data->dev_private;
2437 struct mlx5_ibv_shared *sh = priv->sh;
2438 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2439 struct mlx5dv_dr_domain *domain;
2441 resource->flags = dev_flow->dv.group ? 0 : 1;
2442 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2443 domain = sh->fdb_domain;
2444 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2445 domain = sh->rx_domain;
2447 domain = sh->tx_domain;
2448 /* Lookup a matching resource from cache. */
2449 LIST_FOREACH(cache_resource, &sh->encaps_decaps, next) {
2450 if (resource->reformat_type == cache_resource->reformat_type &&
2451 resource->ft_type == cache_resource->ft_type &&
2452 resource->flags == cache_resource->flags &&
2453 resource->size == cache_resource->size &&
2454 !memcmp((const void *)resource->buf,
2455 (const void *)cache_resource->buf,
2457 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d++",
2458 (void *)cache_resource,
2459 rte_atomic32_read(&cache_resource->refcnt));
2460 rte_atomic32_inc(&cache_resource->refcnt);
2461 dev_flow->handle->dvh.encap_decap = cache_resource;
2465 /* Register new encap/decap resource. */
2466 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
2467 if (!cache_resource)
2468 return rte_flow_error_set(error, ENOMEM,
2469 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2470 "cannot allocate resource memory");
2471 *cache_resource = *resource;
2472 cache_resource->verbs_action =
2473 mlx5_glue->dv_create_flow_action_packet_reformat
2474 (sh->ctx, cache_resource->reformat_type,
2475 cache_resource->ft_type, domain, cache_resource->flags,
2476 cache_resource->size,
2477 (cache_resource->size ? cache_resource->buf : NULL));
2478 if (!cache_resource->verbs_action) {
2479 rte_free(cache_resource);
2480 return rte_flow_error_set(error, ENOMEM,
2481 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2482 NULL, "cannot create action");
2484 rte_atomic32_init(&cache_resource->refcnt);
2485 rte_atomic32_inc(&cache_resource->refcnt);
2486 LIST_INSERT_HEAD(&sh->encaps_decaps, cache_resource, next);
2487 dev_flow->handle->dvh.encap_decap = cache_resource;
2488 DRV_LOG(DEBUG, "new encap/decap resource %p: refcnt %d++",
2489 (void *)cache_resource,
2490 rte_atomic32_read(&cache_resource->refcnt));
2495 * Find existing table jump resource or create and register a new one.
2497 * @param[in, out] dev
2498 * Pointer to rte_eth_dev structure.
2499 * @param[in, out] tbl
2500 * Pointer to flow table resource.
2501 * @parm[in, out] dev_flow
2502 * Pointer to the dev_flow.
2504 * pointer to error structure.
2507 * 0 on success otherwise -errno and errno is set.
2510 flow_dv_jump_tbl_resource_register
2511 (struct rte_eth_dev *dev __rte_unused,
2512 struct mlx5_flow_tbl_resource *tbl,
2513 struct mlx5_flow *dev_flow,
2514 struct rte_flow_error *error)
2516 struct mlx5_flow_tbl_data_entry *tbl_data =
2517 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
2521 cnt = rte_atomic32_read(&tbl_data->jump.refcnt);
2523 tbl_data->jump.action =
2524 mlx5_glue->dr_create_flow_action_dest_flow_tbl
2526 if (!tbl_data->jump.action)
2527 return rte_flow_error_set(error, ENOMEM,
2528 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2529 NULL, "cannot create jump action");
2530 DRV_LOG(DEBUG, "new jump table resource %p: refcnt %d++",
2531 (void *)&tbl_data->jump, cnt);
2533 MLX5_ASSERT(tbl_data->jump.action);
2534 DRV_LOG(DEBUG, "existed jump table resource %p: refcnt %d++",
2535 (void *)&tbl_data->jump, cnt);
2537 rte_atomic32_inc(&tbl_data->jump.refcnt);
2538 dev_flow->handle->dvh.jump = &tbl_data->jump;
2543 * Find existing table port ID resource or create and register a new one.
2545 * @param[in, out] dev
2546 * Pointer to rte_eth_dev structure.
2547 * @param[in, out] resource
2548 * Pointer to port ID action resource.
2549 * @parm[in, out] dev_flow
2550 * Pointer to the dev_flow.
2552 * pointer to error structure.
2555 * 0 on success otherwise -errno and errno is set.
2558 flow_dv_port_id_action_resource_register
2559 (struct rte_eth_dev *dev,
2560 struct mlx5_flow_dv_port_id_action_resource *resource,
2561 struct mlx5_flow *dev_flow,
2562 struct rte_flow_error *error)
2564 struct mlx5_priv *priv = dev->data->dev_private;
2565 struct mlx5_ibv_shared *sh = priv->sh;
2566 struct mlx5_flow_dv_port_id_action_resource *cache_resource;
2568 /* Lookup a matching resource from cache. */
2569 LIST_FOREACH(cache_resource, &sh->port_id_action_list, next) {
2570 if (resource->port_id == cache_resource->port_id) {
2571 DRV_LOG(DEBUG, "port id action resource resource %p: "
2573 (void *)cache_resource,
2574 rte_atomic32_read(&cache_resource->refcnt));
2575 rte_atomic32_inc(&cache_resource->refcnt);
2576 dev_flow->handle->dvh.port_id_action = cache_resource;
2580 /* Register new port id action resource. */
2581 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
2582 if (!cache_resource)
2583 return rte_flow_error_set(error, ENOMEM,
2584 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2585 "cannot allocate resource memory");
2586 *cache_resource = *resource;
2588 * Depending on rdma_core version the glue routine calls
2589 * either mlx5dv_dr_action_create_dest_ib_port(domain, ibv_port)
2590 * or mlx5dv_dr_action_create_dest_vport(domain, vport_id).
2592 cache_resource->action =
2593 mlx5_glue->dr_create_flow_action_dest_port
2594 (priv->sh->fdb_domain, resource->port_id);
2595 if (!cache_resource->action) {
2596 rte_free(cache_resource);
2597 return rte_flow_error_set(error, ENOMEM,
2598 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2599 NULL, "cannot create action");
2601 rte_atomic32_init(&cache_resource->refcnt);
2602 rte_atomic32_inc(&cache_resource->refcnt);
2603 LIST_INSERT_HEAD(&sh->port_id_action_list, cache_resource, next);
2604 dev_flow->handle->dvh.port_id_action = cache_resource;
2605 DRV_LOG(DEBUG, "new port id action resource %p: refcnt %d++",
2606 (void *)cache_resource,
2607 rte_atomic32_read(&cache_resource->refcnt));
2612 * Find existing push vlan resource or create and register a new one.
2614 * @param [in, out] dev
2615 * Pointer to rte_eth_dev structure.
2616 * @param[in, out] resource
2617 * Pointer to port ID action resource.
2618 * @parm[in, out] dev_flow
2619 * Pointer to the dev_flow.
2621 * pointer to error structure.
2624 * 0 on success otherwise -errno and errno is set.
2627 flow_dv_push_vlan_action_resource_register
2628 (struct rte_eth_dev *dev,
2629 struct mlx5_flow_dv_push_vlan_action_resource *resource,
2630 struct mlx5_flow *dev_flow,
2631 struct rte_flow_error *error)
2633 struct mlx5_priv *priv = dev->data->dev_private;
2634 struct mlx5_ibv_shared *sh = priv->sh;
2635 struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
2636 struct mlx5dv_dr_domain *domain;
2638 /* Lookup a matching resource from cache. */
2639 LIST_FOREACH(cache_resource, &sh->push_vlan_action_list, next) {
2640 if (resource->vlan_tag == cache_resource->vlan_tag &&
2641 resource->ft_type == cache_resource->ft_type) {
2642 DRV_LOG(DEBUG, "push-VLAN action resource resource %p: "
2644 (void *)cache_resource,
2645 rte_atomic32_read(&cache_resource->refcnt));
2646 rte_atomic32_inc(&cache_resource->refcnt);
2647 dev_flow->handle->dvh.push_vlan_res = cache_resource;
2651 /* Register new push_vlan action resource. */
2652 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
2653 if (!cache_resource)
2654 return rte_flow_error_set(error, ENOMEM,
2655 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2656 "cannot allocate resource memory");
2657 *cache_resource = *resource;
2658 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2659 domain = sh->fdb_domain;
2660 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2661 domain = sh->rx_domain;
2663 domain = sh->tx_domain;
2664 cache_resource->action =
2665 mlx5_glue->dr_create_flow_action_push_vlan(domain,
2666 resource->vlan_tag);
2667 if (!cache_resource->action) {
2668 rte_free(cache_resource);
2669 return rte_flow_error_set(error, ENOMEM,
2670 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2671 NULL, "cannot create action");
2673 rte_atomic32_init(&cache_resource->refcnt);
2674 rte_atomic32_inc(&cache_resource->refcnt);
2675 LIST_INSERT_HEAD(&sh->push_vlan_action_list, cache_resource, next);
2676 dev_flow->handle->dvh.push_vlan_res = cache_resource;
2677 DRV_LOG(DEBUG, "new push vlan action resource %p: refcnt %d++",
2678 (void *)cache_resource,
2679 rte_atomic32_read(&cache_resource->refcnt));
2683 * Get the size of specific rte_flow_item_type
2685 * @param[in] item_type
2686 * Tested rte_flow_item_type.
2689 * sizeof struct item_type, 0 if void or irrelevant.
2692 flow_dv_get_item_len(const enum rte_flow_item_type item_type)
2696 switch (item_type) {
2697 case RTE_FLOW_ITEM_TYPE_ETH:
2698 retval = sizeof(struct rte_flow_item_eth);
2700 case RTE_FLOW_ITEM_TYPE_VLAN:
2701 retval = sizeof(struct rte_flow_item_vlan);
2703 case RTE_FLOW_ITEM_TYPE_IPV4:
2704 retval = sizeof(struct rte_flow_item_ipv4);
2706 case RTE_FLOW_ITEM_TYPE_IPV6:
2707 retval = sizeof(struct rte_flow_item_ipv6);
2709 case RTE_FLOW_ITEM_TYPE_UDP:
2710 retval = sizeof(struct rte_flow_item_udp);
2712 case RTE_FLOW_ITEM_TYPE_TCP:
2713 retval = sizeof(struct rte_flow_item_tcp);
2715 case RTE_FLOW_ITEM_TYPE_VXLAN:
2716 retval = sizeof(struct rte_flow_item_vxlan);
2718 case RTE_FLOW_ITEM_TYPE_GRE:
2719 retval = sizeof(struct rte_flow_item_gre);
2721 case RTE_FLOW_ITEM_TYPE_NVGRE:
2722 retval = sizeof(struct rte_flow_item_nvgre);
2724 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2725 retval = sizeof(struct rte_flow_item_vxlan_gpe);
2727 case RTE_FLOW_ITEM_TYPE_MPLS:
2728 retval = sizeof(struct rte_flow_item_mpls);
2730 case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
2738 #define MLX5_ENCAP_IPV4_VERSION 0x40
2739 #define MLX5_ENCAP_IPV4_IHL_MIN 0x05
2740 #define MLX5_ENCAP_IPV4_TTL_DEF 0x40
2741 #define MLX5_ENCAP_IPV6_VTC_FLOW 0x60000000
2742 #define MLX5_ENCAP_IPV6_HOP_LIMIT 0xff
2743 #define MLX5_ENCAP_VXLAN_FLAGS 0x08000000
2744 #define MLX5_ENCAP_VXLAN_GPE_FLAGS 0x04
2747 * Convert the encap action data from list of rte_flow_item to raw buffer
2750 * Pointer to rte_flow_item objects list.
2752 * Pointer to the output buffer.
2754 * Pointer to the output buffer size.
2756 * Pointer to the error structure.
2759 * 0 on success, a negative errno value otherwise and rte_errno is set.
2762 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
2763 size_t *size, struct rte_flow_error *error)
2765 struct rte_ether_hdr *eth = NULL;
2766 struct rte_vlan_hdr *vlan = NULL;
2767 struct rte_ipv4_hdr *ipv4 = NULL;
2768 struct rte_ipv6_hdr *ipv6 = NULL;
2769 struct rte_udp_hdr *udp = NULL;
2770 struct rte_vxlan_hdr *vxlan = NULL;
2771 struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
2772 struct rte_gre_hdr *gre = NULL;
2774 size_t temp_size = 0;
2777 return rte_flow_error_set(error, EINVAL,
2778 RTE_FLOW_ERROR_TYPE_ACTION,
2779 NULL, "invalid empty data");
2780 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2781 len = flow_dv_get_item_len(items->type);
2782 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
2783 return rte_flow_error_set(error, EINVAL,
2784 RTE_FLOW_ERROR_TYPE_ACTION,
2785 (void *)items->type,
2786 "items total size is too big"
2787 " for encap action");
2788 rte_memcpy((void *)&buf[temp_size], items->spec, len);
2789 switch (items->type) {
2790 case RTE_FLOW_ITEM_TYPE_ETH:
2791 eth = (struct rte_ether_hdr *)&buf[temp_size];
2793 case RTE_FLOW_ITEM_TYPE_VLAN:
2794 vlan = (struct rte_vlan_hdr *)&buf[temp_size];
2796 return rte_flow_error_set(error, EINVAL,
2797 RTE_FLOW_ERROR_TYPE_ACTION,
2798 (void *)items->type,
2799 "eth header not found");
2800 if (!eth->ether_type)
2801 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
2803 case RTE_FLOW_ITEM_TYPE_IPV4:
2804 ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
2806 return rte_flow_error_set(error, EINVAL,
2807 RTE_FLOW_ERROR_TYPE_ACTION,
2808 (void *)items->type,
2809 "neither eth nor vlan"
2811 if (vlan && !vlan->eth_proto)
2812 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2813 else if (eth && !eth->ether_type)
2814 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2815 if (!ipv4->version_ihl)
2816 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
2817 MLX5_ENCAP_IPV4_IHL_MIN;
2818 if (!ipv4->time_to_live)
2819 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
2821 case RTE_FLOW_ITEM_TYPE_IPV6:
2822 ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
2824 return rte_flow_error_set(error, EINVAL,
2825 RTE_FLOW_ERROR_TYPE_ACTION,
2826 (void *)items->type,
2827 "neither eth nor vlan"
2829 if (vlan && !vlan->eth_proto)
2830 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2831 else if (eth && !eth->ether_type)
2832 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2833 if (!ipv6->vtc_flow)
2835 RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
2836 if (!ipv6->hop_limits)
2837 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
2839 case RTE_FLOW_ITEM_TYPE_UDP:
2840 udp = (struct rte_udp_hdr *)&buf[temp_size];
2842 return rte_flow_error_set(error, EINVAL,
2843 RTE_FLOW_ERROR_TYPE_ACTION,
2844 (void *)items->type,
2845 "ip header not found");
2846 if (ipv4 && !ipv4->next_proto_id)
2847 ipv4->next_proto_id = IPPROTO_UDP;
2848 else if (ipv6 && !ipv6->proto)
2849 ipv6->proto = IPPROTO_UDP;
2851 case RTE_FLOW_ITEM_TYPE_VXLAN:
2852 vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
2854 return rte_flow_error_set(error, EINVAL,
2855 RTE_FLOW_ERROR_TYPE_ACTION,
2856 (void *)items->type,
2857 "udp header not found");
2859 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
2860 if (!vxlan->vx_flags)
2862 RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
2864 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2865 vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
2867 return rte_flow_error_set(error, EINVAL,
2868 RTE_FLOW_ERROR_TYPE_ACTION,
2869 (void *)items->type,
2870 "udp header not found");
2871 if (!vxlan_gpe->proto)
2872 return rte_flow_error_set(error, EINVAL,
2873 RTE_FLOW_ERROR_TYPE_ACTION,
2874 (void *)items->type,
2875 "next protocol not found");
2878 RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
2879 if (!vxlan_gpe->vx_flags)
2880 vxlan_gpe->vx_flags =
2881 MLX5_ENCAP_VXLAN_GPE_FLAGS;
2883 case RTE_FLOW_ITEM_TYPE_GRE:
2884 case RTE_FLOW_ITEM_TYPE_NVGRE:
2885 gre = (struct rte_gre_hdr *)&buf[temp_size];
2887 return rte_flow_error_set(error, EINVAL,
2888 RTE_FLOW_ERROR_TYPE_ACTION,
2889 (void *)items->type,
2890 "next protocol not found");
2892 return rte_flow_error_set(error, EINVAL,
2893 RTE_FLOW_ERROR_TYPE_ACTION,
2894 (void *)items->type,
2895 "ip header not found");
2896 if (ipv4 && !ipv4->next_proto_id)
2897 ipv4->next_proto_id = IPPROTO_GRE;
2898 else if (ipv6 && !ipv6->proto)
2899 ipv6->proto = IPPROTO_GRE;
2901 case RTE_FLOW_ITEM_TYPE_VOID:
2904 return rte_flow_error_set(error, EINVAL,
2905 RTE_FLOW_ERROR_TYPE_ACTION,
2906 (void *)items->type,
2907 "unsupported item type");
2917 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
2919 struct rte_ether_hdr *eth = NULL;
2920 struct rte_vlan_hdr *vlan = NULL;
2921 struct rte_ipv6_hdr *ipv6 = NULL;
2922 struct rte_udp_hdr *udp = NULL;
2926 eth = (struct rte_ether_hdr *)data;
2927 next_hdr = (char *)(eth + 1);
2928 proto = RTE_BE16(eth->ether_type);
2931 while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
2932 vlan = (struct rte_vlan_hdr *)next_hdr;
2933 proto = RTE_BE16(vlan->eth_proto);
2934 next_hdr += sizeof(struct rte_vlan_hdr);
2937 /* HW calculates IPv4 csum. no need to proceed */
2938 if (proto == RTE_ETHER_TYPE_IPV4)
2941 /* non IPv4/IPv6 header. not supported */
2942 if (proto != RTE_ETHER_TYPE_IPV6) {
2943 return rte_flow_error_set(error, ENOTSUP,
2944 RTE_FLOW_ERROR_TYPE_ACTION,
2945 NULL, "Cannot offload non IPv4/IPv6");
2948 ipv6 = (struct rte_ipv6_hdr *)next_hdr;
2950 /* ignore non UDP */
2951 if (ipv6->proto != IPPROTO_UDP)
2954 udp = (struct rte_udp_hdr *)(ipv6 + 1);
2955 udp->dgram_cksum = 0;
2961 * Convert L2 encap action to DV specification.
2964 * Pointer to rte_eth_dev structure.
2966 * Pointer to action structure.
2967 * @param[in, out] dev_flow
2968 * Pointer to the mlx5_flow.
2969 * @param[in] transfer
2970 * Mark if the flow is E-Switch flow.
2972 * Pointer to the error structure.
2975 * 0 on success, a negative errno value otherwise and rte_errno is set.
2978 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
2979 const struct rte_flow_action *action,
2980 struct mlx5_flow *dev_flow,
2982 struct rte_flow_error *error)
2984 const struct rte_flow_item *encap_data;
2985 const struct rte_flow_action_raw_encap *raw_encap_data;
2986 struct mlx5_flow_dv_encap_decap_resource res = {
2988 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
2989 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
2990 MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
2993 if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
2995 (const struct rte_flow_action_raw_encap *)action->conf;
2996 res.size = raw_encap_data->size;
2997 memcpy(res.buf, raw_encap_data->data, res.size);
2999 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
3001 ((const struct rte_flow_action_vxlan_encap *)
3002 action->conf)->definition;
3005 ((const struct rte_flow_action_nvgre_encap *)
3006 action->conf)->definition;
3007 if (flow_dv_convert_encap_data(encap_data, res.buf,
3011 if (flow_dv_zero_encap_udp_csum(res.buf, error))
3013 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3014 return rte_flow_error_set(error, EINVAL,
3015 RTE_FLOW_ERROR_TYPE_ACTION,
3016 NULL, "can't create L2 encap action");
3021 * Convert L2 decap action to DV specification.
3024 * Pointer to rte_eth_dev structure.
3025 * @param[in, out] dev_flow
3026 * Pointer to the mlx5_flow.
3027 * @param[in] transfer
3028 * Mark if the flow is E-Switch flow.
3030 * Pointer to the error structure.
3033 * 0 on success, a negative errno value otherwise and rte_errno is set.
3036 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
3037 struct mlx5_flow *dev_flow,
3039 struct rte_flow_error *error)
3041 struct mlx5_flow_dv_encap_decap_resource res = {
3044 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
3045 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3046 MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
3049 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3050 return rte_flow_error_set(error, EINVAL,
3051 RTE_FLOW_ERROR_TYPE_ACTION,
3052 NULL, "can't create L2 decap action");
3057 * Convert raw decap/encap (L3 tunnel) action to DV specification.
3060 * Pointer to rte_eth_dev structure.
3062 * Pointer to action structure.
3063 * @param[in, out] dev_flow
3064 * Pointer to the mlx5_flow.
3066 * Pointer to the flow attributes.
3068 * Pointer to the error structure.
3071 * 0 on success, a negative errno value otherwise and rte_errno is set.
3074 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
3075 const struct rte_flow_action *action,
3076 struct mlx5_flow *dev_flow,
3077 const struct rte_flow_attr *attr,
3078 struct rte_flow_error *error)
3080 const struct rte_flow_action_raw_encap *encap_data;
3081 struct mlx5_flow_dv_encap_decap_resource res;
3083 encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
3084 res.size = encap_data->size;
3085 memcpy(res.buf, encap_data->data, res.size);
3086 res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
3087 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
3088 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
3090 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3092 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3093 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3094 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3095 return rte_flow_error_set(error, EINVAL,
3096 RTE_FLOW_ERROR_TYPE_ACTION,
3097 NULL, "can't create encap action");
3102 * Create action push VLAN.
3105 * Pointer to rte_eth_dev structure.
3107 * Pointer to the flow attributes.
3109 * Pointer to the vlan to push to the Ethernet header.
3110 * @param[in, out] dev_flow
3111 * Pointer to the mlx5_flow.
3113 * Pointer to the error structure.
3116 * 0 on success, a negative errno value otherwise and rte_errno is set.
3119 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
3120 const struct rte_flow_attr *attr,
3121 const struct rte_vlan_hdr *vlan,
3122 struct mlx5_flow *dev_flow,
3123 struct rte_flow_error *error)
3125 struct mlx5_flow_dv_push_vlan_action_resource res;
3128 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
3131 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3133 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3134 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3135 return flow_dv_push_vlan_action_resource_register
3136 (dev, &res, dev_flow, error);
3140 * Validate the modify-header actions.
3142 * @param[in] action_flags
3143 * Holds the actions detected until now.
3145 * Pointer to the modify action.
3147 * Pointer to error structure.
3150 * 0 on success, a negative errno value otherwise and rte_errno is set.
3153 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
3154 const struct rte_flow_action *action,
3155 struct rte_flow_error *error)
3157 if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
3158 return rte_flow_error_set(error, EINVAL,
3159 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3160 NULL, "action configuration not set");
3161 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3162 return rte_flow_error_set(error, EINVAL,
3163 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3164 "can't have encap action before"
3170 * Validate the modify-header MAC address actions.
3172 * @param[in] action_flags
3173 * Holds the actions detected until now.
3175 * Pointer to the modify action.
3176 * @param[in] item_flags
3177 * Holds the items detected.
3179 * Pointer to error structure.
3182 * 0 on success, a negative errno value otherwise and rte_errno is set.
3185 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
3186 const struct rte_flow_action *action,
3187 const uint64_t item_flags,
3188 struct rte_flow_error *error)
3192 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3194 if (!(item_flags & MLX5_FLOW_LAYER_L2))
3195 return rte_flow_error_set(error, EINVAL,
3196 RTE_FLOW_ERROR_TYPE_ACTION,
3198 "no L2 item in pattern");
3204 * Validate the modify-header IPv4 address actions.
3206 * @param[in] action_flags
3207 * Holds the actions detected until now.
3209 * Pointer to the modify action.
3210 * @param[in] item_flags
3211 * Holds the items detected.
3213 * Pointer to error structure.
3216 * 0 on success, a negative errno value otherwise and rte_errno is set.
3219 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
3220 const struct rte_flow_action *action,
3221 const uint64_t item_flags,
3222 struct rte_flow_error *error)
3227 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3229 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3230 MLX5_FLOW_LAYER_INNER_L3_IPV4 :
3231 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
3232 if (!(item_flags & layer))
3233 return rte_flow_error_set(error, EINVAL,
3234 RTE_FLOW_ERROR_TYPE_ACTION,
3236 "no ipv4 item in pattern");
3242 * Validate the modify-header IPv6 address actions.
3244 * @param[in] action_flags
3245 * Holds the actions detected until now.
3247 * Pointer to the modify action.
3248 * @param[in] item_flags
3249 * Holds the items detected.
3251 * Pointer to error structure.
3254 * 0 on success, a negative errno value otherwise and rte_errno is set.
3257 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
3258 const struct rte_flow_action *action,
3259 const uint64_t item_flags,
3260 struct rte_flow_error *error)
3265 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3267 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3268 MLX5_FLOW_LAYER_INNER_L3_IPV6 :
3269 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
3270 if (!(item_flags & layer))
3271 return rte_flow_error_set(error, EINVAL,
3272 RTE_FLOW_ERROR_TYPE_ACTION,
3274 "no ipv6 item in pattern");
3280 * Validate the modify-header TP actions.
3282 * @param[in] action_flags
3283 * Holds the actions detected until now.
3285 * Pointer to the modify action.
3286 * @param[in] item_flags
3287 * Holds the items detected.
3289 * Pointer to error structure.
3292 * 0 on success, a negative errno value otherwise and rte_errno is set.
3295 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
3296 const struct rte_flow_action *action,
3297 const uint64_t item_flags,
3298 struct rte_flow_error *error)
3303 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3305 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3306 MLX5_FLOW_LAYER_INNER_L4 :
3307 MLX5_FLOW_LAYER_OUTER_L4;
3308 if (!(item_flags & layer))
3309 return rte_flow_error_set(error, EINVAL,
3310 RTE_FLOW_ERROR_TYPE_ACTION,
3311 NULL, "no transport layer "
3318 * Validate the modify-header actions of increment/decrement
3319 * TCP Sequence-number.
3321 * @param[in] action_flags
3322 * Holds the actions detected until now.
3324 * Pointer to the modify action.
3325 * @param[in] item_flags
3326 * Holds the items detected.
3328 * Pointer to error structure.
3331 * 0 on success, a negative errno value otherwise and rte_errno is set.
3334 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
3335 const struct rte_flow_action *action,
3336 const uint64_t item_flags,
3337 struct rte_flow_error *error)
3342 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3344 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3345 MLX5_FLOW_LAYER_INNER_L4_TCP :
3346 MLX5_FLOW_LAYER_OUTER_L4_TCP;
3347 if (!(item_flags & layer))
3348 return rte_flow_error_set(error, EINVAL,
3349 RTE_FLOW_ERROR_TYPE_ACTION,
3350 NULL, "no TCP item in"
3352 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
3353 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
3354 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
3355 (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
3356 return rte_flow_error_set(error, EINVAL,
3357 RTE_FLOW_ERROR_TYPE_ACTION,
3359 "cannot decrease and increase"
3360 " TCP sequence number"
3361 " at the same time");
3367 * Validate the modify-header actions of increment/decrement
3368 * TCP Acknowledgment number.
3370 * @param[in] action_flags
3371 * Holds the actions detected until now.
3373 * Pointer to the modify action.
3374 * @param[in] item_flags
3375 * Holds the items detected.
3377 * Pointer to error structure.
3380 * 0 on success, a negative errno value otherwise and rte_errno is set.
3383 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
3384 const struct rte_flow_action *action,
3385 const uint64_t item_flags,
3386 struct rte_flow_error *error)
3391 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3393 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3394 MLX5_FLOW_LAYER_INNER_L4_TCP :
3395 MLX5_FLOW_LAYER_OUTER_L4_TCP;
3396 if (!(item_flags & layer))
3397 return rte_flow_error_set(error, EINVAL,
3398 RTE_FLOW_ERROR_TYPE_ACTION,
3399 NULL, "no TCP item in"
3401 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
3402 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
3403 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
3404 (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
3405 return rte_flow_error_set(error, EINVAL,
3406 RTE_FLOW_ERROR_TYPE_ACTION,
3408 "cannot decrease and increase"
3409 " TCP acknowledgment number"
3410 " at the same time");
3416 * Validate the modify-header TTL actions.
3418 * @param[in] action_flags
3419 * Holds the actions detected until now.
3421 * Pointer to the modify action.
3422 * @param[in] item_flags
3423 * Holds the items detected.
3425 * Pointer to error structure.
3428 * 0 on success, a negative errno value otherwise and rte_errno is set.
3431 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
3432 const struct rte_flow_action *action,
3433 const uint64_t item_flags,
3434 struct rte_flow_error *error)
3439 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3441 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3442 MLX5_FLOW_LAYER_INNER_L3 :
3443 MLX5_FLOW_LAYER_OUTER_L3;
3444 if (!(item_flags & layer))
3445 return rte_flow_error_set(error, EINVAL,
3446 RTE_FLOW_ERROR_TYPE_ACTION,
3448 "no IP protocol in pattern");
3454 * Validate jump action.
3457 * Pointer to the jump action.
3458 * @param[in] action_flags
3459 * Holds the actions detected until now.
3460 * @param[in] attributes
3461 * Pointer to flow attributes
3462 * @param[in] external
3463 * Action belongs to flow rule created by request external to PMD.
3465 * Pointer to error structure.
3468 * 0 on success, a negative errno value otherwise and rte_errno is set.
3471 flow_dv_validate_action_jump(const struct rte_flow_action *action,
3472 uint64_t action_flags,
3473 const struct rte_flow_attr *attributes,
3474 bool external, struct rte_flow_error *error)
3476 uint32_t target_group, table;
3479 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3480 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3481 return rte_flow_error_set(error, EINVAL,
3482 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3483 "can't have 2 fate actions in"
3485 if (action_flags & MLX5_FLOW_ACTION_METER)
3486 return rte_flow_error_set(error, ENOTSUP,
3487 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3488 "jump with meter not support");
3490 return rte_flow_error_set(error, EINVAL,
3491 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3492 NULL, "action configuration not set");
3494 ((const struct rte_flow_action_jump *)action->conf)->group;
3495 ret = mlx5_flow_group_to_table(attributes, external, target_group,
3496 true, &table, error);
3499 if (attributes->group == target_group)
3500 return rte_flow_error_set(error, EINVAL,
3501 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3502 "target group must be other than"
3503 " the current flow group");
3508 * Validate the port_id action.
3511 * Pointer to rte_eth_dev structure.
3512 * @param[in] action_flags
3513 * Bit-fields that holds the actions detected until now.
3515 * Port_id RTE action structure.
3517 * Attributes of flow that includes this action.
3519 * Pointer to error structure.
3522 * 0 on success, a negative errno value otherwise and rte_errno is set.
3525 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
3526 uint64_t action_flags,
3527 const struct rte_flow_action *action,
3528 const struct rte_flow_attr *attr,
3529 struct rte_flow_error *error)
3531 const struct rte_flow_action_port_id *port_id;
3532 struct mlx5_priv *act_priv;
3533 struct mlx5_priv *dev_priv;
3536 if (!attr->transfer)
3537 return rte_flow_error_set(error, ENOTSUP,
3538 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3540 "port id action is valid in transfer"
3542 if (!action || !action->conf)
3543 return rte_flow_error_set(error, ENOTSUP,
3544 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3546 "port id action parameters must be"
3548 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3549 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3550 return rte_flow_error_set(error, EINVAL,
3551 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3552 "can have only one fate actions in"
3554 dev_priv = mlx5_dev_to_eswitch_info(dev);
3556 return rte_flow_error_set(error, rte_errno,
3557 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3559 "failed to obtain E-Switch info");
3560 port_id = action->conf;
3561 port = port_id->original ? dev->data->port_id : port_id->id;
3562 act_priv = mlx5_port_to_eswitch_info(port, false);
3564 return rte_flow_error_set
3566 RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
3567 "failed to obtain E-Switch port id for port");
3568 if (act_priv->domain_id != dev_priv->domain_id)
3569 return rte_flow_error_set
3571 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3572 "port does not belong to"
3573 " E-Switch being configured");
3578 * Get the maximum number of modify header actions.
3581 * Pointer to rte_eth_dev structure.
3583 * Flags bits to check if root level.
3586 * Max number of modify header actions device can support.
3589 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev, uint64_t flags)
3592 * There's no way to directly query the max cap. Although it has to be
3593 * acquried by iterative trial, it is a safe assumption that more
3594 * actions are supported by FW if extensive metadata register is
3595 * supported. (Only in the root table)
3597 if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
3598 return MLX5_MAX_MODIFY_NUM;
3600 return mlx5_flow_ext_mreg_supported(dev) ?
3601 MLX5_ROOT_TBL_MODIFY_NUM :
3602 MLX5_ROOT_TBL_MODIFY_NUM_NO_MREG;
3606 * Validate the meter action.
3609 * Pointer to rte_eth_dev structure.
3610 * @param[in] action_flags
3611 * Bit-fields that holds the actions detected until now.
3613 * Pointer to the meter action.
3615 * Attributes of flow that includes this action.
3617 * Pointer to error structure.
3620 * 0 on success, a negative errno value otherwise and rte_ernno is set.
3623 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
3624 uint64_t action_flags,
3625 const struct rte_flow_action *action,
3626 const struct rte_flow_attr *attr,
3627 struct rte_flow_error *error)
3629 struct mlx5_priv *priv = dev->data->dev_private;
3630 const struct rte_flow_action_meter *am = action->conf;
3631 struct mlx5_flow_meter *fm;
3634 return rte_flow_error_set(error, EINVAL,
3635 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3636 "meter action conf is NULL");
3638 if (action_flags & MLX5_FLOW_ACTION_METER)
3639 return rte_flow_error_set(error, ENOTSUP,
3640 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3641 "meter chaining not support");
3642 if (action_flags & MLX5_FLOW_ACTION_JUMP)
3643 return rte_flow_error_set(error, ENOTSUP,
3644 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3645 "meter with jump not support");
3647 return rte_flow_error_set(error, ENOTSUP,
3648 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3650 "meter action not supported");
3651 fm = mlx5_flow_meter_find(priv, am->mtr_id);
3653 return rte_flow_error_set(error, EINVAL,
3654 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3656 if (fm->ref_cnt && (!(fm->attr.transfer == attr->transfer ||
3657 (!fm->attr.ingress && !attr->ingress && attr->egress) ||
3658 (!fm->attr.egress && !attr->egress && attr->ingress))))
3659 return rte_flow_error_set(error, EINVAL,
3660 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3661 "Flow attributes are either invalid "
3662 "or have a conflict with current "
3663 "meter attributes");
3668 * Validate the modify-header IPv4 DSCP actions.
3670 * @param[in] action_flags
3671 * Holds the actions detected until now.
3673 * Pointer to the modify action.
3674 * @param[in] item_flags
3675 * Holds the items detected.
3677 * Pointer to error structure.
3680 * 0 on success, a negative errno value otherwise and rte_errno is set.
3683 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
3684 const struct rte_flow_action *action,
3685 const uint64_t item_flags,
3686 struct rte_flow_error *error)
3690 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3692 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
3693 return rte_flow_error_set(error, EINVAL,
3694 RTE_FLOW_ERROR_TYPE_ACTION,
3696 "no ipv4 item in pattern");
3702 * Validate the modify-header IPv6 DSCP actions.
3704 * @param[in] action_flags
3705 * Holds the actions detected until now.
3707 * Pointer to the modify action.
3708 * @param[in] item_flags
3709 * Holds the items detected.
3711 * Pointer to error structure.
3714 * 0 on success, a negative errno value otherwise and rte_errno is set.
3717 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
3718 const struct rte_flow_action *action,
3719 const uint64_t item_flags,
3720 struct rte_flow_error *error)
3724 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3726 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
3727 return rte_flow_error_set(error, EINVAL,
3728 RTE_FLOW_ERROR_TYPE_ACTION,
3730 "no ipv6 item in pattern");
3736 * Find existing modify-header resource or create and register a new one.
3738 * @param dev[in, out]
3739 * Pointer to rte_eth_dev structure.
3740 * @param[in, out] resource
3741 * Pointer to modify-header resource.
3742 * @parm[in, out] dev_flow
3743 * Pointer to the dev_flow.
3745 * pointer to error structure.
3748 * 0 on success otherwise -errno and errno is set.
3751 flow_dv_modify_hdr_resource_register
3752 (struct rte_eth_dev *dev,
3753 struct mlx5_flow_dv_modify_hdr_resource *resource,
3754 struct mlx5_flow *dev_flow,
3755 struct rte_flow_error *error)
3757 struct mlx5_priv *priv = dev->data->dev_private;
3758 struct mlx5_ibv_shared *sh = priv->sh;
3759 struct mlx5_flow_dv_modify_hdr_resource *cache_resource;
3760 struct mlx5dv_dr_domain *ns;
3761 uint32_t actions_len;
3763 resource->flags = dev_flow->dv.group ? 0 :
3764 MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
3765 if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
3767 return rte_flow_error_set(error, EOVERFLOW,
3768 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3769 "too many modify header items");
3770 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3771 ns = sh->fdb_domain;
3772 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
3776 /* Lookup a matching resource from cache. */
3777 actions_len = resource->actions_num * sizeof(resource->actions[0]);
3778 LIST_FOREACH(cache_resource, &sh->modify_cmds, next) {
3779 if (resource->ft_type == cache_resource->ft_type &&
3780 resource->actions_num == cache_resource->actions_num &&
3781 resource->flags == cache_resource->flags &&
3782 !memcmp((const void *)resource->actions,
3783 (const void *)cache_resource->actions,
3785 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d++",
3786 (void *)cache_resource,
3787 rte_atomic32_read(&cache_resource->refcnt));
3788 rte_atomic32_inc(&cache_resource->refcnt);
3789 dev_flow->handle->dvh.modify_hdr = cache_resource;
3793 /* Register new modify-header resource. */
3794 cache_resource = rte_calloc(__func__, 1,
3795 sizeof(*cache_resource) + actions_len, 0);
3796 if (!cache_resource)
3797 return rte_flow_error_set(error, ENOMEM,
3798 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3799 "cannot allocate resource memory");
3800 *cache_resource = *resource;
3801 rte_memcpy(cache_resource->actions, resource->actions, actions_len);
3802 cache_resource->verbs_action =
3803 mlx5_glue->dv_create_flow_action_modify_header
3804 (sh->ctx, cache_resource->ft_type, ns,
3805 cache_resource->flags, actions_len,
3806 (uint64_t *)cache_resource->actions);
3807 if (!cache_resource->verbs_action) {
3808 rte_free(cache_resource);
3809 return rte_flow_error_set(error, ENOMEM,
3810 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3811 NULL, "cannot create action");
3813 rte_atomic32_init(&cache_resource->refcnt);
3814 rte_atomic32_inc(&cache_resource->refcnt);
3815 LIST_INSERT_HEAD(&sh->modify_cmds, cache_resource, next);
3816 dev_flow->handle->dvh.modify_hdr = cache_resource;
3817 DRV_LOG(DEBUG, "new modify-header resource %p: refcnt %d++",
3818 (void *)cache_resource,
3819 rte_atomic32_read(&cache_resource->refcnt));
3824 * Get DV flow counter by index.
3827 * Pointer to the Ethernet device structure.
3829 * mlx5 flow counter index in the container.
3831 * mlx5 flow counter pool in the container,
3834 * Pointer to the counter, NULL otherwise.
3836 static struct mlx5_flow_counter *
3837 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
3839 struct mlx5_flow_counter_pool **ppool)
3841 struct mlx5_priv *priv = dev->data->dev_private;
3842 struct mlx5_pools_container *cont;
3843 struct mlx5_flow_counter_pool *pool;
3847 if (idx >= MLX5_CNT_BATCH_OFFSET) {
3848 idx -= MLX5_CNT_BATCH_OFFSET;
3851 cont = MLX5_CNT_CONTAINER(priv->sh, batch, 0);
3852 MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cont->n);
3853 pool = cont->pools[idx / MLX5_COUNTERS_PER_POOL];
3857 return &pool->counters_raw[idx % MLX5_COUNTERS_PER_POOL];
3861 * Get a pool by devx counter ID.
3864 * Pointer to the counter container.
3866 * The counter devx ID.
3869 * The counter pool pointer if exists, NULL otherwise,
3871 static struct mlx5_flow_counter_pool *
3872 flow_dv_find_pool_by_id(struct mlx5_pools_container *cont, int id)
3875 uint32_t n_valid = rte_atomic16_read(&cont->n_valid);
3877 for (i = 0; i < n_valid; i++) {
3878 struct mlx5_flow_counter_pool *pool = cont->pools[i];
3879 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
3880 MLX5_COUNTERS_PER_POOL;
3882 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL) {
3884 * Move the pool to the head, as counter allocate
3885 * always gets the first pool in the container.
3887 if (pool != TAILQ_FIRST(&cont->pool_list)) {
3888 TAILQ_REMOVE(&cont->pool_list, pool, next);
3889 TAILQ_INSERT_HEAD(&cont->pool_list, pool, next);
3898 * Allocate a new memory for the counter values wrapped by all the needed
3902 * Pointer to the Ethernet device structure.
3904 * The raw memory areas - each one for MLX5_COUNTERS_PER_POOL counters.
3907 * The new memory management pointer on success, otherwise NULL and rte_errno
3910 static struct mlx5_counter_stats_mem_mng *
3911 flow_dv_create_counter_stat_mem_mng(struct rte_eth_dev *dev, int raws_n)
3913 struct mlx5_ibv_shared *sh = ((struct mlx5_priv *)
3914 (dev->data->dev_private))->sh;
3915 struct mlx5_devx_mkey_attr mkey_attr;
3916 struct mlx5_counter_stats_mem_mng *mem_mng;
3917 volatile struct flow_counter_stats *raw_data;
3918 int size = (sizeof(struct flow_counter_stats) *
3919 MLX5_COUNTERS_PER_POOL +
3920 sizeof(struct mlx5_counter_stats_raw)) * raws_n +
3921 sizeof(struct mlx5_counter_stats_mem_mng);
3922 uint8_t *mem = rte_calloc(__func__, 1, size, sysconf(_SC_PAGESIZE));
3929 mem_mng = (struct mlx5_counter_stats_mem_mng *)(mem + size) - 1;
3930 size = sizeof(*raw_data) * MLX5_COUNTERS_PER_POOL * raws_n;
3931 mem_mng->umem = mlx5_glue->devx_umem_reg(sh->ctx, mem, size,
3932 IBV_ACCESS_LOCAL_WRITE);
3933 if (!mem_mng->umem) {
3938 mkey_attr.addr = (uintptr_t)mem;
3939 mkey_attr.size = size;
3940 mkey_attr.umem_id = mem_mng->umem->umem_id;
3941 mkey_attr.pd = sh->pdn;
3942 mkey_attr.log_entity_size = 0;
3943 mkey_attr.pg_access = 0;
3944 mkey_attr.klm_array = NULL;
3945 mkey_attr.klm_num = 0;
3946 mkey_attr.relaxed_ordering = 1;
3947 mem_mng->dm = mlx5_devx_cmd_mkey_create(sh->ctx, &mkey_attr);
3949 mlx5_glue->devx_umem_dereg(mem_mng->umem);
3954 mem_mng->raws = (struct mlx5_counter_stats_raw *)(mem + size);
3955 raw_data = (volatile struct flow_counter_stats *)mem;
3956 for (i = 0; i < raws_n; ++i) {
3957 mem_mng->raws[i].mem_mng = mem_mng;
3958 mem_mng->raws[i].data = raw_data + i * MLX5_COUNTERS_PER_POOL;
3960 LIST_INSERT_HEAD(&sh->cmng.mem_mngs, mem_mng, next);
3965 * Resize a counter container.
3968 * Pointer to the Ethernet device structure.
3970 * Whether the pool is for counter that was allocated by batch command.
3973 * The new container pointer on success, otherwise NULL and rte_errno is set.
3975 static struct mlx5_pools_container *
3976 flow_dv_container_resize(struct rte_eth_dev *dev, uint32_t batch)
3978 struct mlx5_priv *priv = dev->data->dev_private;
3979 struct mlx5_pools_container *cont =
3980 MLX5_CNT_CONTAINER(priv->sh, batch, 0);
3981 struct mlx5_pools_container *new_cont =
3982 MLX5_CNT_CONTAINER_UNUSED(priv->sh, batch, 0);
3983 struct mlx5_counter_stats_mem_mng *mem_mng = NULL;
3984 uint32_t resize = cont->n + MLX5_CNT_CONTAINER_RESIZE;
3985 uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
3988 /* Fallback mode has no background thread. Skip the check. */
3989 if (!priv->counter_fallback &&
3990 cont != MLX5_CNT_CONTAINER(priv->sh, batch, 1)) {
3991 /* The last resize still hasn't detected by the host thread. */
3995 new_cont->pools = rte_calloc(__func__, 1, mem_size, 0);
3996 if (!new_cont->pools) {
4001 memcpy(new_cont->pools, cont->pools, cont->n *
4002 sizeof(struct mlx5_flow_counter_pool *));
4004 * Fallback mode query the counter directly, no background query
4005 * resources are needed.
4007 if (!priv->counter_fallback) {
4008 mem_mng = flow_dv_create_counter_stat_mem_mng(dev,
4009 MLX5_CNT_CONTAINER_RESIZE + MLX5_MAX_PENDING_QUERIES);
4011 rte_free(new_cont->pools);
4014 for (i = 0; i < MLX5_MAX_PENDING_QUERIES; ++i)
4015 LIST_INSERT_HEAD(&priv->sh->cmng.free_stat_raws,
4017 MLX5_CNT_CONTAINER_RESIZE +
4021 * Release the old container pools directly as no background
4022 * thread helps that.
4024 rte_free(cont->pools);
4026 new_cont->n = resize;
4027 rte_atomic16_set(&new_cont->n_valid, rte_atomic16_read(&cont->n_valid));
4028 TAILQ_INIT(&new_cont->pool_list);
4029 TAILQ_CONCAT(&new_cont->pool_list, &cont->pool_list, next);
4030 new_cont->init_mem_mng = mem_mng;
4032 /* Flip the master container. */
4033 priv->sh->cmng.mhi[batch] ^= (uint8_t)1;
4038 * Query a devx flow counter.
4041 * Pointer to the Ethernet device structure.
4043 * Index to the flow counter.
4045 * The statistics value of packets.
4047 * The statistics value of bytes.
4050 * 0 on success, otherwise a negative errno value and rte_errno is set.
4053 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
4056 struct mlx5_priv *priv = dev->data->dev_private;
4057 struct mlx5_flow_counter_pool *pool = NULL;
4058 struct mlx5_flow_counter *cnt;
4059 struct mlx5_flow_counter_ext *cnt_ext = NULL;
4062 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
4064 if (counter < MLX5_CNT_BATCH_OFFSET) {
4065 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt);
4066 if (priv->counter_fallback)
4067 return mlx5_devx_cmd_flow_counter_query(cnt_ext->dcs, 0,
4068 0, pkts, bytes, 0, NULL, NULL, 0);
4071 rte_spinlock_lock(&pool->sl);
4073 * The single counters allocation may allocate smaller ID than the
4074 * current allocated in parallel to the host reading.
4075 * In this case the new counter values must be reported as 0.
4077 if (unlikely(cnt_ext && cnt_ext->dcs->id < pool->raw->min_dcs_id)) {
4081 offset = cnt - &pool->counters_raw[0];
4082 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
4083 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
4085 rte_spinlock_unlock(&pool->sl);
4090 * Create and initialize a new counter pool.
4093 * Pointer to the Ethernet device structure.
4095 * The devX counter handle.
4097 * Whether the pool is for counter that was allocated by batch command.
4098 * @param[in/out] cont_cur
4099 * Pointer to the container pointer, it will be update in pool resize.
4102 * The pool container pointer on success, NULL otherwise and rte_errno is set.
4104 static struct mlx5_pools_container *
4105 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
4108 struct mlx5_priv *priv = dev->data->dev_private;
4109 struct mlx5_flow_counter_pool *pool;
4110 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4112 int16_t n_valid = rte_atomic16_read(&cont->n_valid);
4115 if (cont->n == n_valid) {
4116 cont = flow_dv_container_resize(dev, batch);
4120 size = sizeof(*pool);
4122 size += MLX5_COUNTERS_PER_POOL *
4123 sizeof(struct mlx5_flow_counter_ext);
4124 pool = rte_calloc(__func__, 1, size, 0);
4129 pool->min_dcs = dcs;
4130 if (!priv->counter_fallback)
4131 pool->raw = cont->init_mem_mng->raws + n_valid %
4132 MLX5_CNT_CONTAINER_RESIZE;
4133 pool->raw_hw = NULL;
4134 rte_spinlock_init(&pool->sl);
4136 * The generation of the new allocated counters in this pool is 0, 2 in
4137 * the pool generation makes all the counters valid for allocation.
4138 * The start and end query generation protect the counters be released
4139 * between the query and update gap period will not be reallocated
4140 * without the last query finished and stats updated to the memory.
4142 rte_atomic64_set(&pool->start_query_gen, 0x2);
4144 * There's no background query thread for fallback mode, set the
4145 * end_query_gen to the maximum value since no need to wait for
4146 * statistics update.
4148 rte_atomic64_set(&pool->end_query_gen, priv->counter_fallback ?
4150 TAILQ_INIT(&pool->counters);
4151 TAILQ_INSERT_HEAD(&cont->pool_list, pool, next);
4152 pool->index = n_valid;
4153 cont->pools[n_valid] = pool;
4154 /* Pool initialization must be updated before host thread access. */
4156 rte_atomic16_add(&cont->n_valid, 1);
4161 * Prepare a new counter and/or a new counter pool.
4164 * Pointer to the Ethernet device structure.
4165 * @param[out] cnt_free
4166 * Where to put the pointer of a new counter.
4168 * Whether the pool is for counter that was allocated by batch command.
4171 * The counter container pointer and @p cnt_free is set on success,
4172 * NULL otherwise and rte_errno is set.
4174 static struct mlx5_pools_container *
4175 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
4176 struct mlx5_flow_counter **cnt_free,
4179 struct mlx5_priv *priv = dev->data->dev_private;
4180 struct mlx5_pools_container *cont;
4181 struct mlx5_flow_counter_pool *pool;
4182 struct mlx5_devx_obj *dcs = NULL;
4183 struct mlx5_flow_counter *cnt;
4186 cont = MLX5_CNT_CONTAINER(priv->sh, batch, 0);
4188 /* bulk_bitmap must be 0 for single counter allocation. */
4189 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
4192 pool = flow_dv_find_pool_by_id(cont, dcs->id);
4194 cont = flow_dv_pool_create(dev, dcs, batch);
4196 mlx5_devx_cmd_destroy(dcs);
4199 pool = TAILQ_FIRST(&cont->pool_list);
4200 } else if (dcs->id < pool->min_dcs->id) {
4201 rte_atomic64_set(&pool->a64_dcs,
4202 (int64_t)(uintptr_t)dcs);
4204 i = dcs->id % MLX5_COUNTERS_PER_POOL;
4205 cnt = &pool->counters_raw[i];
4206 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
4207 MLX5_GET_POOL_CNT_EXT(pool, i)->dcs = dcs;
4211 /* bulk_bitmap is in 128 counters units. */
4212 if (priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4)
4213 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
4215 rte_errno = ENODATA;
4218 cont = flow_dv_pool_create(dev, dcs, batch);
4220 mlx5_devx_cmd_destroy(dcs);
4223 pool = TAILQ_FIRST(&cont->pool_list);
4224 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
4225 cnt = &pool->counters_raw[i];
4226 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
4228 *cnt_free = &pool->counters_raw[0];
4233 * Search for existed shared counter.
4236 * Pointer to the relevant counter pool container.
4238 * The shared counter ID to search.
4240 * mlx5 flow counter pool in the container,
4243 * NULL if not existed, otherwise pointer to the shared extend counter.
4245 static struct mlx5_flow_counter_ext *
4246 flow_dv_counter_shared_search(struct mlx5_pools_container *cont, uint32_t id,
4247 struct mlx5_flow_counter_pool **ppool)
4249 static struct mlx5_flow_counter_ext *cnt;
4250 struct mlx5_flow_counter_pool *pool;
4252 uint32_t n_valid = rte_atomic16_read(&cont->n_valid);
4254 for (i = 0; i < n_valid; i++) {
4255 pool = cont->pools[i];
4256 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
4257 cnt = MLX5_GET_POOL_CNT_EXT(pool, i);
4258 if (cnt->ref_cnt && cnt->shared && cnt->id == id) {
4260 *ppool = cont->pools[i];
4269 * Allocate a flow counter.
4272 * Pointer to the Ethernet device structure.
4274 * Indicate if this counter is shared with other flows.
4276 * Counter identifier.
4278 * Counter flow group.
4281 * Index to flow counter on success, 0 otherwise and rte_errno is set.
4284 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t shared, uint32_t id,
4287 struct mlx5_priv *priv = dev->data->dev_private;
4288 struct mlx5_flow_counter_pool *pool = NULL;
4289 struct mlx5_flow_counter *cnt_free = NULL;
4290 struct mlx5_flow_counter_ext *cnt_ext = NULL;
4292 * Currently group 0 flow counter cannot be assigned to a flow if it is
4293 * not the first one in the batch counter allocation, so it is better
4294 * to allocate counters one by one for these flows in a separate
4296 * A counter can be shared between different groups so need to take
4297 * shared counters from the single container.
4299 uint32_t batch = (group && !shared && !priv->counter_fallback) ? 1 : 0;
4300 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4304 if (!priv->config.devx) {
4305 rte_errno = ENOTSUP;
4309 cnt_ext = flow_dv_counter_shared_search(cont, id, &pool);
4311 if (cnt_ext->ref_cnt + 1 == 0) {
4316 cnt_idx = pool->index * MLX5_COUNTERS_PER_POOL +
4317 (cnt_ext->dcs->id % MLX5_COUNTERS_PER_POOL)
4322 /* Pools which has a free counters are in the start. */
4323 TAILQ_FOREACH(pool, &cont->pool_list, next) {
4325 * The free counter reset values must be updated between the
4326 * counter release to the counter allocation, so, at least one
4327 * query must be done in this time. ensure it by saving the
4328 * query generation in the release time.
4329 * The free list is sorted according to the generation - so if
4330 * the first one is not updated, all the others are not
4333 cnt_free = TAILQ_FIRST(&pool->counters);
4334 if (cnt_free && cnt_free->query_gen <
4335 rte_atomic64_read(&pool->end_query_gen))
4340 cont = flow_dv_counter_pool_prepare(dev, &cnt_free, batch);
4343 pool = TAILQ_FIRST(&cont->pool_list);
4346 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt_free);
4347 /* Create a DV counter action only in the first time usage. */
4348 if (!cnt_free->action) {
4350 struct mlx5_devx_obj *dcs;
4353 offset = cnt_free - &pool->counters_raw[0];
4354 dcs = pool->min_dcs;
4359 cnt_free->action = mlx5_glue->dv_create_flow_action_counter
4361 if (!cnt_free->action) {
4366 cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
4367 (cnt_free - pool->counters_raw));
4368 cnt_idx += batch * MLX5_CNT_BATCH_OFFSET;
4369 /* Update the counter reset values. */
4370 if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
4374 cnt_ext->shared = shared;
4375 cnt_ext->ref_cnt = 1;
4378 if (!priv->counter_fallback && !priv->sh->cmng.query_thread_on)
4379 /* Start the asynchronous batch query by the host thread. */
4380 mlx5_set_query_alarm(priv->sh);
4381 TAILQ_REMOVE(&pool->counters, cnt_free, next);
4382 if (TAILQ_EMPTY(&pool->counters)) {
4383 /* Move the pool to the end of the container pool list. */
4384 TAILQ_REMOVE(&cont->pool_list, pool, next);
4385 TAILQ_INSERT_TAIL(&cont->pool_list, pool, next);
4391 * Release a flow counter.
4394 * Pointer to the Ethernet device structure.
4395 * @param[in] counter
4396 * Index to the counter handler.
4399 flow_dv_counter_release(struct rte_eth_dev *dev, uint32_t counter)
4401 struct mlx5_flow_counter_pool *pool = NULL;
4402 struct mlx5_flow_counter *cnt;
4403 struct mlx5_flow_counter_ext *cnt_ext = NULL;
4407 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
4409 if (counter < MLX5_CNT_BATCH_OFFSET) {
4410 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt);
4411 if (cnt_ext && --cnt_ext->ref_cnt)
4414 /* Put the counter in the end - the last updated one. */
4415 TAILQ_INSERT_TAIL(&pool->counters, cnt, next);
4417 * Counters released between query trigger and handler need
4418 * to wait the next round of query. Since the packets arrive
4419 * in the gap period will not be taken into account to the
4422 cnt->query_gen = rte_atomic64_read(&pool->start_query_gen);
4426 * Verify the @p attributes will be correctly understood by the NIC and store
4427 * them in the @p flow if everything is correct.
4430 * Pointer to dev struct.
4431 * @param[in] attributes
4432 * Pointer to flow attributes
4433 * @param[in] external
4434 * This flow rule is created by request external to PMD.
4436 * Pointer to error structure.
4439 * 0 on success, a negative errno value otherwise and rte_errno is set.
4442 flow_dv_validate_attributes(struct rte_eth_dev *dev,
4443 const struct rte_flow_attr *attributes,
4444 bool external __rte_unused,
4445 struct rte_flow_error *error)
4447 struct mlx5_priv *priv = dev->data->dev_private;
4448 uint32_t priority_max = priv->config.flow_prio - 1;
4450 #ifndef HAVE_MLX5DV_DR
4451 if (attributes->group)
4452 return rte_flow_error_set(error, ENOTSUP,
4453 RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
4455 "groups are not supported");
4460 ret = mlx5_flow_group_to_table(attributes, external,
4461 attributes->group, !!priv->fdb_def_rule,
4466 if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
4467 attributes->priority >= priority_max)
4468 return rte_flow_error_set(error, ENOTSUP,
4469 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
4471 "priority out of range");
4472 if (attributes->transfer) {
4473 if (!priv->config.dv_esw_en)
4474 return rte_flow_error_set
4476 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4477 "E-Switch dr is not supported");
4478 if (!(priv->representor || priv->master))
4479 return rte_flow_error_set
4480 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4481 NULL, "E-Switch configuration can only be"
4482 " done by a master or a representor device");
4483 if (attributes->egress)
4484 return rte_flow_error_set
4486 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
4487 "egress is not supported");
4489 if (!(attributes->egress ^ attributes->ingress))
4490 return rte_flow_error_set(error, ENOTSUP,
4491 RTE_FLOW_ERROR_TYPE_ATTR, NULL,
4492 "must specify exactly one of "
4493 "ingress or egress");
4498 * Internal validation function. For validating both actions and items.
4501 * Pointer to the rte_eth_dev structure.
4503 * Pointer to the flow attributes.
4505 * Pointer to the list of items.
4506 * @param[in] actions
4507 * Pointer to the list of actions.
4508 * @param[in] external
4509 * This flow rule is created by request external to PMD.
4511 * Pointer to the error structure.
4514 * 0 on success, a negative errno value otherwise and rte_errno is set.
4517 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
4518 const struct rte_flow_item items[],
4519 const struct rte_flow_action actions[],
4520 bool external, struct rte_flow_error *error)
4523 uint64_t action_flags = 0;
4524 uint64_t item_flags = 0;
4525 uint64_t last_item = 0;
4526 uint8_t next_protocol = 0xff;
4527 uint16_t ether_type = 0;
4529 uint8_t item_ipv6_proto = 0;
4530 const struct rte_flow_item *gre_item = NULL;
4531 const struct rte_flow_action_raw_decap *decap;
4532 const struct rte_flow_action_raw_encap *encap;
4533 const struct rte_flow_action_rss *rss;
4534 const struct rte_flow_item_tcp nic_tcp_mask = {
4537 .src_port = RTE_BE16(UINT16_MAX),
4538 .dst_port = RTE_BE16(UINT16_MAX),
4541 const struct rte_flow_item_ipv4 nic_ipv4_mask = {
4543 .src_addr = RTE_BE32(0xffffffff),
4544 .dst_addr = RTE_BE32(0xffffffff),
4545 .type_of_service = 0xff,
4546 .next_proto_id = 0xff,
4547 .time_to_live = 0xff,
4550 const struct rte_flow_item_ipv6 nic_ipv6_mask = {
4553 "\xff\xff\xff\xff\xff\xff\xff\xff"
4554 "\xff\xff\xff\xff\xff\xff\xff\xff",
4556 "\xff\xff\xff\xff\xff\xff\xff\xff"
4557 "\xff\xff\xff\xff\xff\xff\xff\xff",
4558 .vtc_flow = RTE_BE32(0xffffffff),
4563 struct mlx5_priv *priv = dev->data->dev_private;
4564 struct mlx5_dev_config *dev_conf = &priv->config;
4565 uint16_t queue_index = 0xFFFF;
4569 ret = flow_dv_validate_attributes(dev, attr, external, error);
4572 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
4573 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
4574 int type = items->type;
4577 case RTE_FLOW_ITEM_TYPE_VOID:
4579 case RTE_FLOW_ITEM_TYPE_PORT_ID:
4580 ret = flow_dv_validate_item_port_id
4581 (dev, items, attr, item_flags, error);
4584 last_item = MLX5_FLOW_ITEM_PORT_ID;
4586 case RTE_FLOW_ITEM_TYPE_ETH:
4587 ret = mlx5_flow_validate_item_eth(items, item_flags,
4591 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
4592 MLX5_FLOW_LAYER_OUTER_L2;
4593 if (items->mask != NULL && items->spec != NULL) {
4595 ((const struct rte_flow_item_eth *)
4598 ((const struct rte_flow_item_eth *)
4600 ether_type = rte_be_to_cpu_16(ether_type);
4605 case RTE_FLOW_ITEM_TYPE_VLAN:
4606 ret = mlx5_flow_validate_item_vlan(items, item_flags,
4610 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
4611 MLX5_FLOW_LAYER_OUTER_VLAN;
4612 if (items->mask != NULL && items->spec != NULL) {
4614 ((const struct rte_flow_item_vlan *)
4615 items->spec)->inner_type;
4617 ((const struct rte_flow_item_vlan *)
4618 items->mask)->inner_type;
4619 ether_type = rte_be_to_cpu_16(ether_type);
4624 case RTE_FLOW_ITEM_TYPE_IPV4:
4625 mlx5_flow_tunnel_ip_check(items, next_protocol,
4626 &item_flags, &tunnel);
4627 ret = mlx5_flow_validate_item_ipv4(items, item_flags,
4634 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
4635 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
4636 if (items->mask != NULL &&
4637 ((const struct rte_flow_item_ipv4 *)
4638 items->mask)->hdr.next_proto_id) {
4640 ((const struct rte_flow_item_ipv4 *)
4641 (items->spec))->hdr.next_proto_id;
4643 ((const struct rte_flow_item_ipv4 *)
4644 (items->mask))->hdr.next_proto_id;
4646 /* Reset for inner layer. */
4647 next_protocol = 0xff;
4650 case RTE_FLOW_ITEM_TYPE_IPV6:
4651 mlx5_flow_tunnel_ip_check(items, next_protocol,
4652 &item_flags, &tunnel);
4653 ret = mlx5_flow_validate_item_ipv6(items, item_flags,
4660 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
4661 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
4662 if (items->mask != NULL &&
4663 ((const struct rte_flow_item_ipv6 *)
4664 items->mask)->hdr.proto) {
4666 ((const struct rte_flow_item_ipv6 *)
4667 items->spec)->hdr.proto;
4669 ((const struct rte_flow_item_ipv6 *)
4670 items->spec)->hdr.proto;
4672 ((const struct rte_flow_item_ipv6 *)
4673 items->mask)->hdr.proto;
4675 /* Reset for inner layer. */
4676 next_protocol = 0xff;
4679 case RTE_FLOW_ITEM_TYPE_TCP:
4680 ret = mlx5_flow_validate_item_tcp
4687 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
4688 MLX5_FLOW_LAYER_OUTER_L4_TCP;
4690 case RTE_FLOW_ITEM_TYPE_UDP:
4691 ret = mlx5_flow_validate_item_udp(items, item_flags,
4696 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
4697 MLX5_FLOW_LAYER_OUTER_L4_UDP;
4699 case RTE_FLOW_ITEM_TYPE_GRE:
4700 ret = mlx5_flow_validate_item_gre(items, item_flags,
4701 next_protocol, error);
4705 last_item = MLX5_FLOW_LAYER_GRE;
4707 case RTE_FLOW_ITEM_TYPE_NVGRE:
4708 ret = mlx5_flow_validate_item_nvgre(items, item_flags,
4713 last_item = MLX5_FLOW_LAYER_NVGRE;
4715 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
4716 ret = mlx5_flow_validate_item_gre_key
4717 (items, item_flags, gre_item, error);
4720 last_item = MLX5_FLOW_LAYER_GRE_KEY;
4722 case RTE_FLOW_ITEM_TYPE_VXLAN:
4723 ret = mlx5_flow_validate_item_vxlan(items, item_flags,
4727 last_item = MLX5_FLOW_LAYER_VXLAN;
4729 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
4730 ret = mlx5_flow_validate_item_vxlan_gpe(items,
4735 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
4737 case RTE_FLOW_ITEM_TYPE_GENEVE:
4738 ret = mlx5_flow_validate_item_geneve(items,
4743 last_item = MLX5_FLOW_LAYER_GENEVE;
4745 case RTE_FLOW_ITEM_TYPE_MPLS:
4746 ret = mlx5_flow_validate_item_mpls(dev, items,
4751 last_item = MLX5_FLOW_LAYER_MPLS;
4754 case RTE_FLOW_ITEM_TYPE_MARK:
4755 ret = flow_dv_validate_item_mark(dev, items, attr,
4759 last_item = MLX5_FLOW_ITEM_MARK;
4761 case RTE_FLOW_ITEM_TYPE_META:
4762 ret = flow_dv_validate_item_meta(dev, items, attr,
4766 last_item = MLX5_FLOW_ITEM_METADATA;
4768 case RTE_FLOW_ITEM_TYPE_ICMP:
4769 ret = mlx5_flow_validate_item_icmp(items, item_flags,
4774 last_item = MLX5_FLOW_LAYER_ICMP;
4776 case RTE_FLOW_ITEM_TYPE_ICMP6:
4777 ret = mlx5_flow_validate_item_icmp6(items, item_flags,
4782 item_ipv6_proto = IPPROTO_ICMPV6;
4783 last_item = MLX5_FLOW_LAYER_ICMP6;
4785 case RTE_FLOW_ITEM_TYPE_TAG:
4786 ret = flow_dv_validate_item_tag(dev, items,
4790 last_item = MLX5_FLOW_ITEM_TAG;
4792 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
4793 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
4795 case RTE_FLOW_ITEM_TYPE_GTP:
4796 ret = flow_dv_validate_item_gtp(dev, items, item_flags,
4800 last_item = MLX5_FLOW_LAYER_GTP;
4803 return rte_flow_error_set(error, ENOTSUP,
4804 RTE_FLOW_ERROR_TYPE_ITEM,
4805 NULL, "item not supported");
4807 item_flags |= last_item;
4809 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
4810 int type = actions->type;
4811 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
4812 return rte_flow_error_set(error, ENOTSUP,
4813 RTE_FLOW_ERROR_TYPE_ACTION,
4814 actions, "too many actions");
4816 case RTE_FLOW_ACTION_TYPE_VOID:
4818 case RTE_FLOW_ACTION_TYPE_PORT_ID:
4819 ret = flow_dv_validate_action_port_id(dev,
4826 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
4829 case RTE_FLOW_ACTION_TYPE_FLAG:
4830 ret = flow_dv_validate_action_flag(dev, action_flags,
4834 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
4835 /* Count all modify-header actions as one. */
4836 if (!(action_flags &
4837 MLX5_FLOW_MODIFY_HDR_ACTIONS))
4839 action_flags |= MLX5_FLOW_ACTION_FLAG |
4840 MLX5_FLOW_ACTION_MARK_EXT;
4842 action_flags |= MLX5_FLOW_ACTION_FLAG;
4846 case RTE_FLOW_ACTION_TYPE_MARK:
4847 ret = flow_dv_validate_action_mark(dev, actions,
4852 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
4853 /* Count all modify-header actions as one. */
4854 if (!(action_flags &
4855 MLX5_FLOW_MODIFY_HDR_ACTIONS))
4857 action_flags |= MLX5_FLOW_ACTION_MARK |
4858 MLX5_FLOW_ACTION_MARK_EXT;
4860 action_flags |= MLX5_FLOW_ACTION_MARK;
4864 case RTE_FLOW_ACTION_TYPE_SET_META:
4865 ret = flow_dv_validate_action_set_meta(dev, actions,
4870 /* Count all modify-header actions as one action. */
4871 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4873 action_flags |= MLX5_FLOW_ACTION_SET_META;
4875 case RTE_FLOW_ACTION_TYPE_SET_TAG:
4876 ret = flow_dv_validate_action_set_tag(dev, actions,
4881 /* Count all modify-header actions as one action. */
4882 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4884 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
4886 case RTE_FLOW_ACTION_TYPE_DROP:
4887 ret = mlx5_flow_validate_action_drop(action_flags,
4891 action_flags |= MLX5_FLOW_ACTION_DROP;
4894 case RTE_FLOW_ACTION_TYPE_QUEUE:
4895 ret = mlx5_flow_validate_action_queue(actions,
4900 queue_index = ((const struct rte_flow_action_queue *)
4901 (actions->conf))->index;
4902 action_flags |= MLX5_FLOW_ACTION_QUEUE;
4905 case RTE_FLOW_ACTION_TYPE_RSS:
4906 rss = actions->conf;
4907 ret = mlx5_flow_validate_action_rss(actions,
4913 if (rss != NULL && rss->queue_num)
4914 queue_index = rss->queue[0];
4915 action_flags |= MLX5_FLOW_ACTION_RSS;
4918 case RTE_FLOW_ACTION_TYPE_COUNT:
4919 ret = flow_dv_validate_action_count(dev, error);
4922 action_flags |= MLX5_FLOW_ACTION_COUNT;
4925 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
4926 if (flow_dv_validate_action_pop_vlan(dev,
4932 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
4935 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
4936 ret = flow_dv_validate_action_push_vlan(dev,
4943 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
4946 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
4947 ret = flow_dv_validate_action_set_vlan_pcp
4948 (action_flags, actions, error);
4951 /* Count PCP with push_vlan command. */
4952 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
4954 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
4955 ret = flow_dv_validate_action_set_vlan_vid
4956 (item_flags, action_flags,
4960 /* Count VID with push_vlan command. */
4961 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
4963 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
4964 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
4965 ret = flow_dv_validate_action_l2_encap(dev,
4971 action_flags |= MLX5_FLOW_ACTION_ENCAP;
4974 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
4975 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
4976 ret = flow_dv_validate_action_decap(dev, action_flags,
4980 action_flags |= MLX5_FLOW_ACTION_DECAP;
4983 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
4984 ret = flow_dv_validate_action_raw_encap_decap
4985 (dev, NULL, actions->conf, attr, &action_flags,
4990 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
4991 decap = actions->conf;
4992 while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
4994 if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
4998 encap = actions->conf;
5000 ret = flow_dv_validate_action_raw_encap_decap
5002 decap ? decap : &empty_decap, encap,
5003 attr, &action_flags, &actions_n,
5008 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
5009 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
5010 ret = flow_dv_validate_action_modify_mac(action_flags,
5016 /* Count all modify-header actions as one action. */
5017 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5019 action_flags |= actions->type ==
5020 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
5021 MLX5_FLOW_ACTION_SET_MAC_SRC :
5022 MLX5_FLOW_ACTION_SET_MAC_DST;
5025 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
5026 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
5027 ret = flow_dv_validate_action_modify_ipv4(action_flags,
5033 /* Count all modify-header actions as one action. */
5034 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5036 action_flags |= actions->type ==
5037 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
5038 MLX5_FLOW_ACTION_SET_IPV4_SRC :
5039 MLX5_FLOW_ACTION_SET_IPV4_DST;
5041 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
5042 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
5043 ret = flow_dv_validate_action_modify_ipv6(action_flags,
5049 if (item_ipv6_proto == IPPROTO_ICMPV6)
5050 return rte_flow_error_set(error, ENOTSUP,
5051 RTE_FLOW_ERROR_TYPE_ACTION,
5053 "Can't change header "
5054 "with ICMPv6 proto");
5055 /* Count all modify-header actions as one action. */
5056 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5058 action_flags |= actions->type ==
5059 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
5060 MLX5_FLOW_ACTION_SET_IPV6_SRC :
5061 MLX5_FLOW_ACTION_SET_IPV6_DST;
5063 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
5064 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
5065 ret = flow_dv_validate_action_modify_tp(action_flags,
5071 /* Count all modify-header actions as one action. */
5072 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5074 action_flags |= actions->type ==
5075 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
5076 MLX5_FLOW_ACTION_SET_TP_SRC :
5077 MLX5_FLOW_ACTION_SET_TP_DST;
5079 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
5080 case RTE_FLOW_ACTION_TYPE_SET_TTL:
5081 ret = flow_dv_validate_action_modify_ttl(action_flags,
5087 /* Count all modify-header actions as one action. */
5088 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5090 action_flags |= actions->type ==
5091 RTE_FLOW_ACTION_TYPE_SET_TTL ?
5092 MLX5_FLOW_ACTION_SET_TTL :
5093 MLX5_FLOW_ACTION_DEC_TTL;
5095 case RTE_FLOW_ACTION_TYPE_JUMP:
5096 ret = flow_dv_validate_action_jump(actions,
5103 action_flags |= MLX5_FLOW_ACTION_JUMP;
5105 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
5106 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
5107 ret = flow_dv_validate_action_modify_tcp_seq
5114 /* Count all modify-header actions as one action. */
5115 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5117 action_flags |= actions->type ==
5118 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
5119 MLX5_FLOW_ACTION_INC_TCP_SEQ :
5120 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
5122 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
5123 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
5124 ret = flow_dv_validate_action_modify_tcp_ack
5131 /* Count all modify-header actions as one action. */
5132 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5134 action_flags |= actions->type ==
5135 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
5136 MLX5_FLOW_ACTION_INC_TCP_ACK :
5137 MLX5_FLOW_ACTION_DEC_TCP_ACK;
5139 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
5140 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
5141 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
5143 case RTE_FLOW_ACTION_TYPE_METER:
5144 ret = mlx5_flow_validate_action_meter(dev,
5150 action_flags |= MLX5_FLOW_ACTION_METER;
5153 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
5154 ret = flow_dv_validate_action_modify_ipv4_dscp
5161 /* Count all modify-header actions as one action. */
5162 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5164 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
5166 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
5167 ret = flow_dv_validate_action_modify_ipv6_dscp
5174 /* Count all modify-header actions as one action. */
5175 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5177 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
5180 return rte_flow_error_set(error, ENOTSUP,
5181 RTE_FLOW_ERROR_TYPE_ACTION,
5183 "action not supported");
5187 * Validate the drop action mutual exclusion with other actions.
5188 * Drop action is mutually-exclusive with any other action, except for
5191 if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
5192 (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
5193 return rte_flow_error_set(error, EINVAL,
5194 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5195 "Drop action is mutually-exclusive "
5196 "with any other action, except for "
5198 /* Eswitch has few restrictions on using items and actions */
5199 if (attr->transfer) {
5200 if (!mlx5_flow_ext_mreg_supported(dev) &&
5201 action_flags & MLX5_FLOW_ACTION_FLAG)
5202 return rte_flow_error_set(error, ENOTSUP,
5203 RTE_FLOW_ERROR_TYPE_ACTION,
5205 "unsupported action FLAG");
5206 if (!mlx5_flow_ext_mreg_supported(dev) &&
5207 action_flags & MLX5_FLOW_ACTION_MARK)
5208 return rte_flow_error_set(error, ENOTSUP,
5209 RTE_FLOW_ERROR_TYPE_ACTION,
5211 "unsupported action MARK");
5212 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
5213 return rte_flow_error_set(error, ENOTSUP,
5214 RTE_FLOW_ERROR_TYPE_ACTION,
5216 "unsupported action QUEUE");
5217 if (action_flags & MLX5_FLOW_ACTION_RSS)
5218 return rte_flow_error_set(error, ENOTSUP,
5219 RTE_FLOW_ERROR_TYPE_ACTION,
5221 "unsupported action RSS");
5222 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
5223 return rte_flow_error_set(error, EINVAL,
5224 RTE_FLOW_ERROR_TYPE_ACTION,
5226 "no fate action is found");
5228 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
5229 return rte_flow_error_set(error, EINVAL,
5230 RTE_FLOW_ERROR_TYPE_ACTION,
5232 "no fate action is found");
5234 /* Continue validation for Xcap actions.*/
5235 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) && (queue_index == 0xFFFF ||
5236 mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
5237 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
5238 MLX5_FLOW_XCAP_ACTIONS)
5239 return rte_flow_error_set(error, ENOTSUP,
5240 RTE_FLOW_ERROR_TYPE_ACTION,
5241 NULL, "encap and decap "
5242 "combination aren't supported");
5243 if (!attr->transfer && attr->ingress && (action_flags &
5244 MLX5_FLOW_ACTION_ENCAP))
5245 return rte_flow_error_set(error, ENOTSUP,
5246 RTE_FLOW_ERROR_TYPE_ACTION,
5247 NULL, "encap is not supported"
5248 " for ingress traffic");
5254 * Internal preparation function. Allocates the DV flow size,
5255 * this size is constant.
5258 * Pointer to the rte_eth_dev structure.
5260 * Pointer to the flow attributes.
5262 * Pointer to the list of items.
5263 * @param[in] actions
5264 * Pointer to the list of actions.
5266 * Pointer to the error structure.
5269 * Pointer to mlx5_flow object on success,
5270 * otherwise NULL and rte_errno is set.
5272 static struct mlx5_flow *
5273 flow_dv_prepare(struct rte_eth_dev *dev,
5274 const struct rte_flow_attr *attr __rte_unused,
5275 const struct rte_flow_item items[] __rte_unused,
5276 const struct rte_flow_action actions[] __rte_unused,
5277 struct rte_flow_error *error)
5279 size_t size = sizeof(struct mlx5_flow_handle);
5280 struct mlx5_flow *dev_flow;
5281 struct mlx5_flow_handle *dev_handle;
5282 struct mlx5_priv *priv = dev->data->dev_private;
5284 /* In case of corrupting the memory. */
5285 if (priv->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
5286 rte_flow_error_set(error, ENOSPC,
5287 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5288 "not free temporary device flow");
5291 dev_handle = rte_calloc(__func__, 1, size, 0);
5293 rte_flow_error_set(error, ENOMEM,
5294 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5295 "not enough memory to create flow handle");
5298 /* No multi-thread supporting. */
5299 dev_flow = &((struct mlx5_flow *)priv->inter_flows)[priv->flow_idx++];
5300 dev_flow->handle = dev_handle;
5301 dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);
5303 * The matching value needs to be cleared to 0 before using. In the
5304 * past, it will be automatically cleared when using rte_*alloc
5305 * API. The time consumption will be almost the same as before.
5307 memset(dev_flow->dv.value.buf, 0, MLX5_ST_SZ_BYTES(fte_match_param));
5308 dev_flow->ingress = attr->ingress;
5309 dev_flow->dv.transfer = attr->transfer;
5313 #ifdef RTE_LIBRTE_MLX5_DEBUG
5315 * Sanity check for match mask and value. Similar to check_valid_spec() in
5316 * kernel driver. If unmasked bit is present in value, it returns failure.
5319 * pointer to match mask buffer.
5320 * @param match_value
5321 * pointer to match value buffer.
5324 * 0 if valid, -EINVAL otherwise.
5327 flow_dv_check_valid_spec(void *match_mask, void *match_value)
5329 uint8_t *m = match_mask;
5330 uint8_t *v = match_value;
5333 for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
5336 "match_value differs from match_criteria"
5337 " %p[%u] != %p[%u]",
5338 match_value, i, match_mask, i);
5347 * Add Ethernet item to matcher and to the value.
5349 * @param[in, out] matcher
5351 * @param[in, out] key
5352 * Flow matcher value.
5354 * Flow pattern to translate.
5356 * Item is inner pattern.
5359 flow_dv_translate_item_eth(void *matcher, void *key,
5360 const struct rte_flow_item *item, int inner)
5362 const struct rte_flow_item_eth *eth_m = item->mask;
5363 const struct rte_flow_item_eth *eth_v = item->spec;
5364 const struct rte_flow_item_eth nic_mask = {
5365 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5366 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5367 .type = RTE_BE16(0xffff),
5379 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5381 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5383 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5385 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5387 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, dmac_47_16),
5388 ð_m->dst, sizeof(eth_m->dst));
5389 /* The value must be in the range of the mask. */
5390 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, dmac_47_16);
5391 for (i = 0; i < sizeof(eth_m->dst); ++i)
5392 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
5393 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, smac_47_16),
5394 ð_m->src, sizeof(eth_m->src));
5395 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, smac_47_16);
5396 /* The value must be in the range of the mask. */
5397 for (i = 0; i < sizeof(eth_m->dst); ++i)
5398 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
5400 /* When ethertype is present set mask for tagged VLAN. */
5401 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5402 /* Set value for tagged VLAN if ethertype is 802.1Q. */
5403 if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_VLAN) ||
5404 eth_v->type == RTE_BE16(RTE_ETHER_TYPE_QINQ)) {
5405 MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag,
5407 /* Return here to avoid setting match on ethertype. */
5412 * HW supports match on one Ethertype, the Ethertype following the last
5413 * VLAN tag of the packet (see PRM).
5414 * Set match on ethertype only if ETH header is not followed by VLAN.
5416 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
5417 rte_be_to_cpu_16(eth_m->type));
5418 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, ethertype);
5419 *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
5423 * Add VLAN item to matcher and to the value.
5425 * @param[in, out] dev_flow
5427 * @param[in, out] matcher
5429 * @param[in, out] key
5430 * Flow matcher value.
5432 * Flow pattern to translate.
5434 * Item is inner pattern.
5437 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
5438 void *matcher, void *key,
5439 const struct rte_flow_item *item,
5442 const struct rte_flow_item_vlan *vlan_m = item->mask;
5443 const struct rte_flow_item_vlan *vlan_v = item->spec;
5452 vlan_m = &rte_flow_item_vlan_mask;
5454 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5456 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5458 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5460 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5462 * This is workaround, masks are not supported,
5463 * and pre-validated.
5465 dev_flow->handle->vf_vlan.tag =
5466 rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
5468 tci_m = rte_be_to_cpu_16(vlan_m->tci);
5469 tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
5470 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5471 MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
5472 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_vid, tci_m);
5473 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, tci_v);
5474 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_cfi, tci_m >> 12);
5475 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_cfi, tci_v >> 12);
5476 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_prio, tci_m >> 13);
5477 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, tci_v >> 13);
5478 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
5479 rte_be_to_cpu_16(vlan_m->inner_type));
5480 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
5481 rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
5485 * Add IPV4 item to matcher and to the value.
5487 * @param[in, out] matcher
5489 * @param[in, out] key
5490 * Flow matcher value.
5492 * Flow pattern to translate.
5493 * @param[in] item_flags
5494 * Bit-fields that holds the items detected until now.
5496 * Item is inner pattern.
5498 * The group to insert the rule.
5501 flow_dv_translate_item_ipv4(void *matcher, void *key,
5502 const struct rte_flow_item *item,
5503 const uint64_t item_flags,
5504 int inner, uint32_t group)
5506 const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
5507 const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
5508 const struct rte_flow_item_ipv4 nic_mask = {
5510 .src_addr = RTE_BE32(0xffffffff),
5511 .dst_addr = RTE_BE32(0xffffffff),
5512 .type_of_service = 0xff,
5513 .next_proto_id = 0xff,
5514 .time_to_live = 0xff,
5524 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5526 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5528 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5530 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5533 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
5535 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x4);
5536 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 4);
5538 * On outer header (which must contains L2), or inner header with L2,
5539 * set cvlan_tag mask bit to mark this packet as untagged.
5540 * This should be done even if item->spec is empty.
5542 if (!inner || item_flags & MLX5_FLOW_LAYER_INNER_L2)
5543 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5548 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5549 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
5550 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5551 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
5552 *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
5553 *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
5554 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5555 src_ipv4_src_ipv6.ipv4_layout.ipv4);
5556 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5557 src_ipv4_src_ipv6.ipv4_layout.ipv4);
5558 *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
5559 *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
5560 tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
5561 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
5562 ipv4_m->hdr.type_of_service);
5563 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
5564 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
5565 ipv4_m->hdr.type_of_service >> 2);
5566 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
5567 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
5568 ipv4_m->hdr.next_proto_id);
5569 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
5570 ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
5571 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
5572 ipv4_m->hdr.time_to_live);
5573 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
5574 ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
5578 * Add IPV6 item to matcher and to the value.
5580 * @param[in, out] matcher
5582 * @param[in, out] key
5583 * Flow matcher value.
5585 * Flow pattern to translate.
5586 * @param[in] item_flags
5587 * Bit-fields that holds the items detected until now.
5589 * Item is inner pattern.
5591 * The group to insert the rule.
5594 flow_dv_translate_item_ipv6(void *matcher, void *key,
5595 const struct rte_flow_item *item,
5596 const uint64_t item_flags,
5597 int inner, uint32_t group)
5599 const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
5600 const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
5601 const struct rte_flow_item_ipv6 nic_mask = {
5604 "\xff\xff\xff\xff\xff\xff\xff\xff"
5605 "\xff\xff\xff\xff\xff\xff\xff\xff",
5607 "\xff\xff\xff\xff\xff\xff\xff\xff"
5608 "\xff\xff\xff\xff\xff\xff\xff\xff",
5609 .vtc_flow = RTE_BE32(0xffffffff),
5616 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5617 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5626 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5628 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5630 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5632 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5635 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
5637 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x6);
5638 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 6);
5640 * On outer header (which must contains L2), or inner header with L2,
5641 * set cvlan_tag mask bit to mark this packet as untagged.
5642 * This should be done even if item->spec is empty.
5644 if (!inner || item_flags & MLX5_FLOW_LAYER_INNER_L2)
5645 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5650 size = sizeof(ipv6_m->hdr.dst_addr);
5651 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5652 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
5653 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5654 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
5655 memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
5656 for (i = 0; i < size; ++i)
5657 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
5658 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5659 src_ipv4_src_ipv6.ipv6_layout.ipv6);
5660 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5661 src_ipv4_src_ipv6.ipv6_layout.ipv6);
5662 memcpy(l24_m, ipv6_m->hdr.src_addr, size);
5663 for (i = 0; i < size; ++i)
5664 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
5666 vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
5667 vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
5668 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
5669 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
5670 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
5671 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
5674 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
5676 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
5679 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
5681 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
5685 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
5687 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
5688 ipv6_v->hdr.proto & ipv6_m->hdr.proto);
5690 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
5691 ipv6_m->hdr.hop_limits);
5692 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
5693 ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
5697 * Add TCP item to matcher and to the value.
5699 * @param[in, out] matcher
5701 * @param[in, out] key
5702 * Flow matcher value.
5704 * Flow pattern to translate.
5706 * Item is inner pattern.
5709 flow_dv_translate_item_tcp(void *matcher, void *key,
5710 const struct rte_flow_item *item,
5713 const struct rte_flow_item_tcp *tcp_m = item->mask;
5714 const struct rte_flow_item_tcp *tcp_v = item->spec;
5719 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5721 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5723 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5725 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5727 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5728 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
5732 tcp_m = &rte_flow_item_tcp_mask;
5733 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
5734 rte_be_to_cpu_16(tcp_m->hdr.src_port));
5735 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
5736 rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
5737 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
5738 rte_be_to_cpu_16(tcp_m->hdr.dst_port));
5739 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
5740 rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
5741 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
5742 tcp_m->hdr.tcp_flags);
5743 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
5744 (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
5748 * Add UDP item to matcher and to the value.
5750 * @param[in, out] matcher
5752 * @param[in, out] key
5753 * Flow matcher value.
5755 * Flow pattern to translate.
5757 * Item is inner pattern.
5760 flow_dv_translate_item_udp(void *matcher, void *key,
5761 const struct rte_flow_item *item,
5764 const struct rte_flow_item_udp *udp_m = item->mask;
5765 const struct rte_flow_item_udp *udp_v = item->spec;
5770 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5772 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5774 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5776 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5778 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5779 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
5783 udp_m = &rte_flow_item_udp_mask;
5784 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
5785 rte_be_to_cpu_16(udp_m->hdr.src_port));
5786 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
5787 rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
5788 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
5789 rte_be_to_cpu_16(udp_m->hdr.dst_port));
5790 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
5791 rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
5795 * Add GRE optional Key item to matcher and to the value.
5797 * @param[in, out] matcher
5799 * @param[in, out] key
5800 * Flow matcher value.
5802 * Flow pattern to translate.
5804 * Item is inner pattern.
5807 flow_dv_translate_item_gre_key(void *matcher, void *key,
5808 const struct rte_flow_item *item)
5810 const rte_be32_t *key_m = item->mask;
5811 const rte_be32_t *key_v = item->spec;
5812 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5813 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5814 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
5816 /* GRE K bit must be on and should already be validated */
5817 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
5818 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
5822 key_m = &gre_key_default_mask;
5823 MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
5824 rte_be_to_cpu_32(*key_m) >> 8);
5825 MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
5826 rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
5827 MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
5828 rte_be_to_cpu_32(*key_m) & 0xFF);
5829 MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
5830 rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
5834 * Add GRE item to matcher and to the value.
5836 * @param[in, out] matcher
5838 * @param[in, out] key
5839 * Flow matcher value.
5841 * Flow pattern to translate.
5843 * Item is inner pattern.
5846 flow_dv_translate_item_gre(void *matcher, void *key,
5847 const struct rte_flow_item *item,
5850 const struct rte_flow_item_gre *gre_m = item->mask;
5851 const struct rte_flow_item_gre *gre_v = item->spec;
5854 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5855 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5862 uint16_t s_present:1;
5863 uint16_t k_present:1;
5864 uint16_t rsvd_bit1:1;
5865 uint16_t c_present:1;
5869 } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
5872 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5874 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5876 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5878 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5880 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5881 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
5885 gre_m = &rte_flow_item_gre_mask;
5886 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
5887 rte_be_to_cpu_16(gre_m->protocol));
5888 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
5889 rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
5890 gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
5891 gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
5892 MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
5893 gre_crks_rsvd0_ver_m.c_present);
5894 MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
5895 gre_crks_rsvd0_ver_v.c_present &
5896 gre_crks_rsvd0_ver_m.c_present);
5897 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
5898 gre_crks_rsvd0_ver_m.k_present);
5899 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
5900 gre_crks_rsvd0_ver_v.k_present &
5901 gre_crks_rsvd0_ver_m.k_present);
5902 MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
5903 gre_crks_rsvd0_ver_m.s_present);
5904 MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
5905 gre_crks_rsvd0_ver_v.s_present &
5906 gre_crks_rsvd0_ver_m.s_present);
5910 * Add NVGRE item to matcher and to the value.
5912 * @param[in, out] matcher
5914 * @param[in, out] key
5915 * Flow matcher value.
5917 * Flow pattern to translate.
5919 * Item is inner pattern.
5922 flow_dv_translate_item_nvgre(void *matcher, void *key,
5923 const struct rte_flow_item *item,
5926 const struct rte_flow_item_nvgre *nvgre_m = item->mask;
5927 const struct rte_flow_item_nvgre *nvgre_v = item->spec;
5928 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5929 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5930 const char *tni_flow_id_m = (const char *)nvgre_m->tni;
5931 const char *tni_flow_id_v = (const char *)nvgre_v->tni;
5937 /* For NVGRE, GRE header fields must be set with defined values. */
5938 const struct rte_flow_item_gre gre_spec = {
5939 .c_rsvd0_ver = RTE_BE16(0x2000),
5940 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
5942 const struct rte_flow_item_gre gre_mask = {
5943 .c_rsvd0_ver = RTE_BE16(0xB000),
5944 .protocol = RTE_BE16(UINT16_MAX),
5946 const struct rte_flow_item gre_item = {
5951 flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
5955 nvgre_m = &rte_flow_item_nvgre_mask;
5956 size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
5957 gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
5958 gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
5959 memcpy(gre_key_m, tni_flow_id_m, size);
5960 for (i = 0; i < size; ++i)
5961 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
5965 * Add VXLAN item to matcher and to the value.
5967 * @param[in, out] matcher
5969 * @param[in, out] key
5970 * Flow matcher value.
5972 * Flow pattern to translate.
5974 * Item is inner pattern.
5977 flow_dv_translate_item_vxlan(void *matcher, void *key,
5978 const struct rte_flow_item *item,
5981 const struct rte_flow_item_vxlan *vxlan_m = item->mask;
5982 const struct rte_flow_item_vxlan *vxlan_v = item->spec;
5985 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5986 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5994 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5996 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5998 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6000 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6002 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
6003 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
6004 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6005 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6006 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6011 vxlan_m = &rte_flow_item_vxlan_mask;
6012 size = sizeof(vxlan_m->vni);
6013 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
6014 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
6015 memcpy(vni_m, vxlan_m->vni, size);
6016 for (i = 0; i < size; ++i)
6017 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
6021 * Add VXLAN-GPE item to matcher and to the value.
6023 * @param[in, out] matcher
6025 * @param[in, out] key
6026 * Flow matcher value.
6028 * Flow pattern to translate.
6030 * Item is inner pattern.
6034 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
6035 const struct rte_flow_item *item, int inner)
6037 const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
6038 const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
6042 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
6044 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6050 uint8_t flags_m = 0xff;
6051 uint8_t flags_v = 0xc;
6054 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6056 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6058 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6060 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6062 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
6063 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
6064 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6065 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6066 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6071 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
6072 size = sizeof(vxlan_m->vni);
6073 vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
6074 vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
6075 memcpy(vni_m, vxlan_m->vni, size);
6076 for (i = 0; i < size; ++i)
6077 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
6078 if (vxlan_m->flags) {
6079 flags_m = vxlan_m->flags;
6080 flags_v = vxlan_v->flags;
6082 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
6083 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
6084 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
6086 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
6091 * Add Geneve item to matcher and to the value.
6093 * @param[in, out] matcher
6095 * @param[in, out] key
6096 * Flow matcher value.
6098 * Flow pattern to translate.
6100 * Item is inner pattern.
6104 flow_dv_translate_item_geneve(void *matcher, void *key,
6105 const struct rte_flow_item *item, int inner)
6107 const struct rte_flow_item_geneve *geneve_m = item->mask;
6108 const struct rte_flow_item_geneve *geneve_v = item->spec;
6111 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6112 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6121 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6123 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6125 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6127 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6129 dport = MLX5_UDP_PORT_GENEVE;
6130 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6131 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6132 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6137 geneve_m = &rte_flow_item_geneve_mask;
6138 size = sizeof(geneve_m->vni);
6139 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
6140 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
6141 memcpy(vni_m, geneve_m->vni, size);
6142 for (i = 0; i < size; ++i)
6143 vni_v[i] = vni_m[i] & geneve_v->vni[i];
6144 MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
6145 rte_be_to_cpu_16(geneve_m->protocol));
6146 MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
6147 rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
6148 gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
6149 gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
6150 MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
6151 MLX5_GENEVE_OAMF_VAL(gbhdr_m));
6152 MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
6153 MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
6154 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
6155 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
6156 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
6157 MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
6158 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
6162 * Add MPLS item to matcher and to the value.
6164 * @param[in, out] matcher
6166 * @param[in, out] key
6167 * Flow matcher value.
6169 * Flow pattern to translate.
6170 * @param[in] prev_layer
6171 * The protocol layer indicated in previous item.
6173 * Item is inner pattern.
6176 flow_dv_translate_item_mpls(void *matcher, void *key,
6177 const struct rte_flow_item *item,
6178 uint64_t prev_layer,
6181 const uint32_t *in_mpls_m = item->mask;
6182 const uint32_t *in_mpls_v = item->spec;
6183 uint32_t *out_mpls_m = 0;
6184 uint32_t *out_mpls_v = 0;
6185 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6186 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6187 void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
6189 void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
6190 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
6191 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6193 switch (prev_layer) {
6194 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
6195 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
6196 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
6197 MLX5_UDP_PORT_MPLS);
6199 case MLX5_FLOW_LAYER_GRE:
6200 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
6201 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
6202 RTE_ETHER_TYPE_MPLS);
6205 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6206 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6213 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
6214 switch (prev_layer) {
6215 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
6217 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
6218 outer_first_mpls_over_udp);
6220 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
6221 outer_first_mpls_over_udp);
6223 case MLX5_FLOW_LAYER_GRE:
6225 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
6226 outer_first_mpls_over_gre);
6228 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
6229 outer_first_mpls_over_gre);
6232 /* Inner MPLS not over GRE is not supported. */
6235 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
6239 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
6245 if (out_mpls_m && out_mpls_v) {
6246 *out_mpls_m = *in_mpls_m;
6247 *out_mpls_v = *in_mpls_v & *in_mpls_m;
6252 * Add metadata register item to matcher
6254 * @param[in, out] matcher
6256 * @param[in, out] key
6257 * Flow matcher value.
6258 * @param[in] reg_type
6259 * Type of device metadata register
6266 flow_dv_match_meta_reg(void *matcher, void *key,
6267 enum modify_reg reg_type,
6268 uint32_t data, uint32_t mask)
6271 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
6273 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
6279 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
6280 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
6283 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
6284 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
6288 * The metadata register C0 field might be divided into
6289 * source vport index and META item value, we should set
6290 * this field according to specified mask, not as whole one.
6292 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
6294 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
6295 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
6298 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
6301 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
6302 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
6305 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
6306 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
6309 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
6310 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
6313 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
6314 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
6317 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
6318 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
6321 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
6322 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
6325 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
6326 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
6335 * Add MARK item to matcher
6338 * The device to configure through.
6339 * @param[in, out] matcher
6341 * @param[in, out] key
6342 * Flow matcher value.
6344 * Flow pattern to translate.
6347 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
6348 void *matcher, void *key,
6349 const struct rte_flow_item *item)
6351 struct mlx5_priv *priv = dev->data->dev_private;
6352 const struct rte_flow_item_mark *mark;
6356 mark = item->mask ? (const void *)item->mask :
6357 &rte_flow_item_mark_mask;
6358 mask = mark->id & priv->sh->dv_mark_mask;
6359 mark = (const void *)item->spec;
6361 value = mark->id & priv->sh->dv_mark_mask & mask;
6363 enum modify_reg reg;
6365 /* Get the metadata register index for the mark. */
6366 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
6367 MLX5_ASSERT(reg > 0);
6368 if (reg == REG_C_0) {
6369 struct mlx5_priv *priv = dev->data->dev_private;
6370 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6371 uint32_t shl_c0 = rte_bsf32(msk_c0);
6377 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6382 * Add META item to matcher
6385 * The devich to configure through.
6386 * @param[in, out] matcher
6388 * @param[in, out] key
6389 * Flow matcher value.
6391 * Attributes of flow that includes this item.
6393 * Flow pattern to translate.
6396 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
6397 void *matcher, void *key,
6398 const struct rte_flow_attr *attr,
6399 const struct rte_flow_item *item)
6401 const struct rte_flow_item_meta *meta_m;
6402 const struct rte_flow_item_meta *meta_v;
6404 meta_m = (const void *)item->mask;
6406 meta_m = &rte_flow_item_meta_mask;
6407 meta_v = (const void *)item->spec;
6410 uint32_t value = meta_v->data;
6411 uint32_t mask = meta_m->data;
6413 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
6417 * In datapath code there is no endianness
6418 * coversions for perfromance reasons, all
6419 * pattern conversions are done in rte_flow.
6421 value = rte_cpu_to_be_32(value);
6422 mask = rte_cpu_to_be_32(mask);
6423 if (reg == REG_C_0) {
6424 struct mlx5_priv *priv = dev->data->dev_private;
6425 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6426 uint32_t shl_c0 = rte_bsf32(msk_c0);
6427 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
6428 uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
6435 MLX5_ASSERT(msk_c0);
6436 MLX5_ASSERT(!(~msk_c0 & mask));
6438 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6443 * Add vport metadata Reg C0 item to matcher
6445 * @param[in, out] matcher
6447 * @param[in, out] key
6448 * Flow matcher value.
6450 * Flow pattern to translate.
6453 flow_dv_translate_item_meta_vport(void *matcher, void *key,
6454 uint32_t value, uint32_t mask)
6456 flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
6460 * Add tag item to matcher
6463 * The devich to configure through.
6464 * @param[in, out] matcher
6466 * @param[in, out] key
6467 * Flow matcher value.
6469 * Flow pattern to translate.
6472 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
6473 void *matcher, void *key,
6474 const struct rte_flow_item *item)
6476 const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
6477 const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
6478 uint32_t mask, value;
6481 value = tag_v->data;
6482 mask = tag_m ? tag_m->data : UINT32_MAX;
6483 if (tag_v->id == REG_C_0) {
6484 struct mlx5_priv *priv = dev->data->dev_private;
6485 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6486 uint32_t shl_c0 = rte_bsf32(msk_c0);
6492 flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
6496 * Add TAG item to matcher
6499 * The devich to configure through.
6500 * @param[in, out] matcher
6502 * @param[in, out] key
6503 * Flow matcher value.
6505 * Flow pattern to translate.
6508 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
6509 void *matcher, void *key,
6510 const struct rte_flow_item *item)
6512 const struct rte_flow_item_tag *tag_v = item->spec;
6513 const struct rte_flow_item_tag *tag_m = item->mask;
6514 enum modify_reg reg;
6517 tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
6518 /* Get the metadata register index for the tag. */
6519 reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
6520 MLX5_ASSERT(reg > 0);
6521 flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
6525 * Add source vport match to the specified matcher.
6527 * @param[in, out] matcher
6529 * @param[in, out] key
6530 * Flow matcher value.
6532 * Source vport value to match
6537 flow_dv_translate_item_source_vport(void *matcher, void *key,
6538 int16_t port, uint16_t mask)
6540 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6541 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6543 MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
6544 MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
6548 * Translate port-id item to eswitch match on port-id.
6551 * The devich to configure through.
6552 * @param[in, out] matcher
6554 * @param[in, out] key
6555 * Flow matcher value.
6557 * Flow pattern to translate.
6560 * 0 on success, a negative errno value otherwise.
6563 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
6564 void *key, const struct rte_flow_item *item)
6566 const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
6567 const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
6568 struct mlx5_priv *priv;
6571 mask = pid_m ? pid_m->id : 0xffff;
6572 id = pid_v ? pid_v->id : dev->data->port_id;
6573 priv = mlx5_port_to_eswitch_info(id, item == NULL);
6576 /* Translate to vport field or to metadata, depending on mode. */
6577 if (priv->vport_meta_mask)
6578 flow_dv_translate_item_meta_vport(matcher, key,
6579 priv->vport_meta_tag,
6580 priv->vport_meta_mask);
6582 flow_dv_translate_item_source_vport(matcher, key,
6583 priv->vport_id, mask);
6588 * Add ICMP6 item to matcher and to the value.
6590 * @param[in, out] matcher
6592 * @param[in, out] key
6593 * Flow matcher value.
6595 * Flow pattern to translate.
6597 * Item is inner pattern.
6600 flow_dv_translate_item_icmp6(void *matcher, void *key,
6601 const struct rte_flow_item *item,
6604 const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
6605 const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
6608 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
6610 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6612 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6614 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6616 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6618 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6620 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
6621 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
6625 icmp6_m = &rte_flow_item_icmp6_mask;
6627 * Force flow only to match the non-fragmented IPv6 ICMPv6 packets.
6628 * If only the protocol is specified, no need to match the frag.
6630 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
6631 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
6632 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
6633 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
6634 icmp6_v->type & icmp6_m->type);
6635 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
6636 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
6637 icmp6_v->code & icmp6_m->code);
6641 * Add ICMP item to matcher and to the value.
6643 * @param[in, out] matcher
6645 * @param[in, out] key
6646 * Flow matcher value.
6648 * Flow pattern to translate.
6650 * Item is inner pattern.
6653 flow_dv_translate_item_icmp(void *matcher, void *key,
6654 const struct rte_flow_item *item,
6657 const struct rte_flow_item_icmp *icmp_m = item->mask;
6658 const struct rte_flow_item_icmp *icmp_v = item->spec;
6661 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
6663 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6665 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6667 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6669 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6671 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6673 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
6674 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
6678 icmp_m = &rte_flow_item_icmp_mask;
6680 * Force flow only to match the non-fragmented IPv4 ICMP packets.
6681 * If only the protocol is specified, no need to match the frag.
6683 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
6684 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
6685 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
6686 icmp_m->hdr.icmp_type);
6687 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
6688 icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
6689 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
6690 icmp_m->hdr.icmp_code);
6691 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
6692 icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
6696 * Add GTP item to matcher and to the value.
6698 * @param[in, out] matcher
6700 * @param[in, out] key
6701 * Flow matcher value.
6703 * Flow pattern to translate.
6705 * Item is inner pattern.
6708 flow_dv_translate_item_gtp(void *matcher, void *key,
6709 const struct rte_flow_item *item, int inner)
6711 const struct rte_flow_item_gtp *gtp_m = item->mask;
6712 const struct rte_flow_item_gtp *gtp_v = item->spec;
6715 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
6717 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6718 uint16_t dport = RTE_GTPU_UDP_PORT;
6721 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6723 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6725 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6727 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6729 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6730 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6731 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6736 gtp_m = &rte_flow_item_gtp_mask;
6737 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
6738 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
6739 gtp_v->msg_type & gtp_m->msg_type);
6740 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
6741 rte_be_to_cpu_32(gtp_m->teid));
6742 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
6743 rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
6746 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
6748 #define HEADER_IS_ZERO(match_criteria, headers) \
6749 !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
6750 matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
6753 * Calculate flow matcher enable bitmap.
6755 * @param match_criteria
6756 * Pointer to flow matcher criteria.
6759 * Bitmap of enabled fields.
6762 flow_dv_matcher_enable(uint32_t *match_criteria)
6764 uint8_t match_criteria_enable;
6766 match_criteria_enable =
6767 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
6768 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
6769 match_criteria_enable |=
6770 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
6771 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
6772 match_criteria_enable |=
6773 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
6774 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
6775 match_criteria_enable |=
6776 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
6777 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
6778 match_criteria_enable |=
6779 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
6780 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
6781 return match_criteria_enable;
6788 * @param[in, out] dev
6789 * Pointer to rte_eth_dev structure.
6790 * @param[in] table_id
6793 * Direction of the table.
6794 * @param[in] transfer
6795 * E-Switch or NIC flow.
6797 * pointer to error structure.
6800 * Returns tables resource based on the index, NULL in case of failed.
6802 static struct mlx5_flow_tbl_resource *
6803 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
6804 uint32_t table_id, uint8_t egress,
6806 struct rte_flow_error *error)
6808 struct mlx5_priv *priv = dev->data->dev_private;
6809 struct mlx5_ibv_shared *sh = priv->sh;
6810 struct mlx5_flow_tbl_resource *tbl;
6811 union mlx5_flow_tbl_key table_key = {
6813 .table_id = table_id,
6815 .domain = !!transfer,
6816 .direction = !!egress,
6819 struct mlx5_hlist_entry *pos = mlx5_hlist_lookup(sh->flow_tbls,
6821 struct mlx5_flow_tbl_data_entry *tbl_data;
6826 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
6828 tbl = &tbl_data->tbl;
6829 rte_atomic32_inc(&tbl->refcnt);
6832 tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
6834 rte_flow_error_set(error, ENOMEM,
6835 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6837 "cannot allocate flow table data entry");
6840 tbl = &tbl_data->tbl;
6841 pos = &tbl_data->entry;
6843 domain = sh->fdb_domain;
6845 domain = sh->tx_domain;
6847 domain = sh->rx_domain;
6848 tbl->obj = mlx5_glue->dr_create_flow_tbl(domain, table_id);
6850 rte_flow_error_set(error, ENOMEM,
6851 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6852 NULL, "cannot create flow table object");
6857 * No multi-threads now, but still better to initialize the reference
6858 * count before insert it into the hash list.
6860 rte_atomic32_init(&tbl->refcnt);
6861 /* Jump action reference count is initialized here. */
6862 rte_atomic32_init(&tbl_data->jump.refcnt);
6863 pos->key = table_key.v64;
6864 ret = mlx5_hlist_insert(sh->flow_tbls, pos);
6866 rte_flow_error_set(error, -ret,
6867 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6868 "cannot insert flow table data entry");
6869 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
6872 rte_atomic32_inc(&tbl->refcnt);
6877 * Release a flow table.
6880 * Pointer to rte_eth_dev structure.
6882 * Table resource to be released.
6885 * Returns 0 if table was released, else return 1;
6888 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
6889 struct mlx5_flow_tbl_resource *tbl)
6891 struct mlx5_priv *priv = dev->data->dev_private;
6892 struct mlx5_ibv_shared *sh = priv->sh;
6893 struct mlx5_flow_tbl_data_entry *tbl_data =
6894 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
6898 if (rte_atomic32_dec_and_test(&tbl->refcnt)) {
6899 struct mlx5_hlist_entry *pos = &tbl_data->entry;
6901 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
6903 /* remove the entry from the hash list and free memory. */
6904 mlx5_hlist_remove(sh->flow_tbls, pos);
6912 * Register the flow matcher.
6914 * @param[in, out] dev
6915 * Pointer to rte_eth_dev structure.
6916 * @param[in, out] matcher
6917 * Pointer to flow matcher.
6918 * @param[in, out] key
6919 * Pointer to flow table key.
6920 * @parm[in, out] dev_flow
6921 * Pointer to the dev_flow.
6923 * pointer to error structure.
6926 * 0 on success otherwise -errno and errno is set.
6929 flow_dv_matcher_register(struct rte_eth_dev *dev,
6930 struct mlx5_flow_dv_matcher *matcher,
6931 union mlx5_flow_tbl_key *key,
6932 struct mlx5_flow *dev_flow,
6933 struct rte_flow_error *error)
6935 struct mlx5_priv *priv = dev->data->dev_private;
6936 struct mlx5_ibv_shared *sh = priv->sh;
6937 struct mlx5_flow_dv_matcher *cache_matcher;
6938 struct mlx5dv_flow_matcher_attr dv_attr = {
6939 .type = IBV_FLOW_ATTR_NORMAL,
6940 .match_mask = (void *)&matcher->mask,
6942 struct mlx5_flow_tbl_resource *tbl;
6943 struct mlx5_flow_tbl_data_entry *tbl_data;
6945 tbl = flow_dv_tbl_resource_get(dev, key->table_id, key->direction,
6946 key->domain, error);
6948 return -rte_errno; /* No need to refill the error info */
6949 tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
6950 /* Lookup from cache. */
6951 LIST_FOREACH(cache_matcher, &tbl_data->matchers, next) {
6952 if (matcher->crc == cache_matcher->crc &&
6953 matcher->priority == cache_matcher->priority &&
6954 !memcmp((const void *)matcher->mask.buf,
6955 (const void *)cache_matcher->mask.buf,
6956 cache_matcher->mask.size)) {
6958 "%s group %u priority %hd use %s "
6959 "matcher %p: refcnt %d++",
6960 key->domain ? "FDB" : "NIC", key->table_id,
6961 cache_matcher->priority,
6962 key->direction ? "tx" : "rx",
6963 (void *)cache_matcher,
6964 rte_atomic32_read(&cache_matcher->refcnt));
6965 rte_atomic32_inc(&cache_matcher->refcnt);
6966 dev_flow->handle->dvh.matcher = cache_matcher;
6967 /* old matcher should not make the table ref++. */
6968 flow_dv_tbl_resource_release(dev, tbl);
6972 /* Register new matcher. */
6973 cache_matcher = rte_calloc(__func__, 1, sizeof(*cache_matcher), 0);
6974 if (!cache_matcher) {
6975 flow_dv_tbl_resource_release(dev, tbl);
6976 return rte_flow_error_set(error, ENOMEM,
6977 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6978 "cannot allocate matcher memory");
6980 *cache_matcher = *matcher;
6981 dv_attr.match_criteria_enable =
6982 flow_dv_matcher_enable(cache_matcher->mask.buf);
6983 dv_attr.priority = matcher->priority;
6985 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
6986 cache_matcher->matcher_object =
6987 mlx5_glue->dv_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj);
6988 if (!cache_matcher->matcher_object) {
6989 rte_free(cache_matcher);
6990 #ifdef HAVE_MLX5DV_DR
6991 flow_dv_tbl_resource_release(dev, tbl);
6993 return rte_flow_error_set(error, ENOMEM,
6994 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6995 NULL, "cannot create matcher");
6997 /* Save the table information */
6998 cache_matcher->tbl = tbl;
6999 rte_atomic32_init(&cache_matcher->refcnt);
7000 /* only matcher ref++, table ref++ already done above in get API. */
7001 rte_atomic32_inc(&cache_matcher->refcnt);
7002 LIST_INSERT_HEAD(&tbl_data->matchers, cache_matcher, next);
7003 dev_flow->handle->dvh.matcher = cache_matcher;
7004 DRV_LOG(DEBUG, "%s group %u priority %hd new %s matcher %p: refcnt %d",
7005 key->domain ? "FDB" : "NIC", key->table_id,
7006 cache_matcher->priority,
7007 key->direction ? "tx" : "rx", (void *)cache_matcher,
7008 rte_atomic32_read(&cache_matcher->refcnt));
7013 * Find existing tag resource or create and register a new one.
7015 * @param dev[in, out]
7016 * Pointer to rte_eth_dev structure.
7017 * @param[in, out] tag_be24
7018 * Tag value in big endian then R-shift 8.
7019 * @parm[in, out] dev_flow
7020 * Pointer to the dev_flow.
7022 * pointer to error structure.
7025 * 0 on success otherwise -errno and errno is set.
7028 flow_dv_tag_resource_register
7029 (struct rte_eth_dev *dev,
7031 struct mlx5_flow *dev_flow,
7032 struct rte_flow_error *error)
7034 struct mlx5_priv *priv = dev->data->dev_private;
7035 struct mlx5_ibv_shared *sh = priv->sh;
7036 struct mlx5_flow_dv_tag_resource *cache_resource;
7037 struct mlx5_hlist_entry *entry;
7039 /* Lookup a matching resource from cache. */
7040 entry = mlx5_hlist_lookup(sh->tag_table, (uint64_t)tag_be24);
7042 cache_resource = container_of
7043 (entry, struct mlx5_flow_dv_tag_resource, entry);
7044 rte_atomic32_inc(&cache_resource->refcnt);
7045 dev_flow->handle->dvh.tag_resource = cache_resource;
7046 DRV_LOG(DEBUG, "cached tag resource %p: refcnt now %d++",
7047 (void *)cache_resource,
7048 rte_atomic32_read(&cache_resource->refcnt));
7051 /* Register new resource. */
7052 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
7053 if (!cache_resource)
7054 return rte_flow_error_set(error, ENOMEM,
7055 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7056 "cannot allocate resource memory");
7057 cache_resource->entry.key = (uint64_t)tag_be24;
7058 cache_resource->action = mlx5_glue->dv_create_flow_action_tag(tag_be24);
7059 if (!cache_resource->action) {
7060 rte_free(cache_resource);
7061 return rte_flow_error_set(error, ENOMEM,
7062 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7063 NULL, "cannot create action");
7065 rte_atomic32_init(&cache_resource->refcnt);
7066 rte_atomic32_inc(&cache_resource->refcnt);
7067 if (mlx5_hlist_insert(sh->tag_table, &cache_resource->entry)) {
7068 mlx5_glue->destroy_flow_action(cache_resource->action);
7069 rte_free(cache_resource);
7070 return rte_flow_error_set(error, EEXIST,
7071 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7072 NULL, "cannot insert tag");
7074 dev_flow->handle->dvh.tag_resource = cache_resource;
7075 DRV_LOG(DEBUG, "new tag resource %p: refcnt now %d++",
7076 (void *)cache_resource,
7077 rte_atomic32_read(&cache_resource->refcnt));
7085 * Pointer to Ethernet device.
7087 * Pointer to mlx5_flow.
7090 * 1 while a reference on it exists, 0 when freed.
7093 flow_dv_tag_release(struct rte_eth_dev *dev,
7094 struct mlx5_flow_dv_tag_resource *tag)
7096 struct mlx5_priv *priv = dev->data->dev_private;
7097 struct mlx5_ibv_shared *sh = priv->sh;
7100 DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
7101 dev->data->port_id, (void *)tag,
7102 rte_atomic32_read(&tag->refcnt));
7103 if (rte_atomic32_dec_and_test(&tag->refcnt)) {
7104 claim_zero(mlx5_glue->destroy_flow_action(tag->action));
7105 mlx5_hlist_remove(sh->tag_table, &tag->entry);
7106 DRV_LOG(DEBUG, "port %u tag %p: removed",
7107 dev->data->port_id, (void *)tag);
7115 * Translate port ID action to vport.
7118 * Pointer to rte_eth_dev structure.
7120 * Pointer to the port ID action.
7121 * @param[out] dst_port_id
7122 * The target port ID.
7124 * Pointer to the error structure.
7127 * 0 on success, a negative errno value otherwise and rte_errno is set.
7130 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
7131 const struct rte_flow_action *action,
7132 uint32_t *dst_port_id,
7133 struct rte_flow_error *error)
7136 struct mlx5_priv *priv;
7137 const struct rte_flow_action_port_id *conf =
7138 (const struct rte_flow_action_port_id *)action->conf;
7140 port = conf->original ? dev->data->port_id : conf->id;
7141 priv = mlx5_port_to_eswitch_info(port, false);
7143 return rte_flow_error_set(error, -rte_errno,
7144 RTE_FLOW_ERROR_TYPE_ACTION,
7146 "No eswitch info was found for port");
7147 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
7149 * This parameter is transferred to
7150 * mlx5dv_dr_action_create_dest_ib_port().
7152 *dst_port_id = priv->ibv_port;
7155 * Legacy mode, no LAG configurations is supported.
7156 * This parameter is transferred to
7157 * mlx5dv_dr_action_create_dest_vport().
7159 *dst_port_id = priv->vport_id;
7165 * Add Tx queue matcher
7168 * Pointer to the dev struct.
7169 * @param[in, out] matcher
7171 * @param[in, out] key
7172 * Flow matcher value.
7174 * Flow pattern to translate.
7176 * Item is inner pattern.
7179 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
7180 void *matcher, void *key,
7181 const struct rte_flow_item *item)
7183 const struct mlx5_rte_flow_item_tx_queue *queue_m;
7184 const struct mlx5_rte_flow_item_tx_queue *queue_v;
7186 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7188 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7189 struct mlx5_txq_ctrl *txq;
7193 queue_m = (const void *)item->mask;
7196 queue_v = (const void *)item->spec;
7199 txq = mlx5_txq_get(dev, queue_v->queue);
7202 queue = txq->obj->sq->id;
7203 MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
7204 MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
7205 queue & queue_m->queue);
7206 mlx5_txq_release(dev, queue_v->queue);
7210 * Set the hash fields according to the @p flow information.
7212 * @param[in] dev_flow
7213 * Pointer to the mlx5_flow.
7216 flow_dv_hashfields_set(struct mlx5_flow *dev_flow)
7218 struct rte_flow *flow = dev_flow->flow;
7219 uint64_t items = dev_flow->handle->layers;
7221 uint64_t rss_types = rte_eth_rss_hf_refine(flow->rss.types);
7223 dev_flow->hash_fields = 0;
7224 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
7225 if (flow->rss.level >= 2) {
7226 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
7230 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
7231 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
7232 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
7233 if (rss_types & ETH_RSS_L3_SRC_ONLY)
7234 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
7235 else if (rss_types & ETH_RSS_L3_DST_ONLY)
7236 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
7238 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
7240 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
7241 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
7242 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
7243 if (rss_types & ETH_RSS_L3_SRC_ONLY)
7244 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
7245 else if (rss_types & ETH_RSS_L3_DST_ONLY)
7246 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
7248 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
7251 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
7252 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
7253 if (rss_types & ETH_RSS_UDP) {
7254 if (rss_types & ETH_RSS_L4_SRC_ONLY)
7255 dev_flow->hash_fields |=
7256 IBV_RX_HASH_SRC_PORT_UDP;
7257 else if (rss_types & ETH_RSS_L4_DST_ONLY)
7258 dev_flow->hash_fields |=
7259 IBV_RX_HASH_DST_PORT_UDP;
7261 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
7263 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
7264 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
7265 if (rss_types & ETH_RSS_TCP) {
7266 if (rss_types & ETH_RSS_L4_SRC_ONLY)
7267 dev_flow->hash_fields |=
7268 IBV_RX_HASH_SRC_PORT_TCP;
7269 else if (rss_types & ETH_RSS_L4_DST_ONLY)
7270 dev_flow->hash_fields |=
7271 IBV_RX_HASH_DST_PORT_TCP;
7273 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
7279 * Fill the flow with DV spec, lock free
7280 * (mutex should be acquired by caller).
7283 * Pointer to rte_eth_dev structure.
7284 * @param[in, out] dev_flow
7285 * Pointer to the sub flow.
7287 * Pointer to the flow attributes.
7289 * Pointer to the list of items.
7290 * @param[in] actions
7291 * Pointer to the list of actions.
7293 * Pointer to the error structure.
7296 * 0 on success, a negative errno value otherwise and rte_errno is set.
7299 __flow_dv_translate(struct rte_eth_dev *dev,
7300 struct mlx5_flow *dev_flow,
7301 const struct rte_flow_attr *attr,
7302 const struct rte_flow_item items[],
7303 const struct rte_flow_action actions[],
7304 struct rte_flow_error *error)
7306 struct mlx5_priv *priv = dev->data->dev_private;
7307 struct mlx5_dev_config *dev_conf = &priv->config;
7308 struct rte_flow *flow = dev_flow->flow;
7309 struct mlx5_flow_handle *handle = dev_flow->handle;
7310 uint64_t item_flags = 0;
7311 uint64_t last_item = 0;
7312 uint64_t action_flags = 0;
7313 uint64_t priority = attr->priority;
7314 struct mlx5_flow_dv_matcher matcher = {
7316 .size = sizeof(matcher.mask.buf),
7320 bool actions_end = false;
7322 struct mlx5_flow_dv_modify_hdr_resource res;
7323 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
7324 sizeof(struct mlx5_modification_cmd) *
7325 (MLX5_MAX_MODIFY_NUM + 1)];
7327 struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
7328 union flow_dv_attr flow_attr = { .attr = 0 };
7330 union mlx5_flow_tbl_key tbl_key;
7331 uint32_t modify_action_position = UINT32_MAX;
7332 void *match_mask = matcher.mask.buf;
7333 void *match_value = dev_flow->dv.value.buf;
7334 uint8_t next_protocol = 0xff;
7335 struct rte_vlan_hdr vlan = { 0 };
7339 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
7340 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
7341 ret = mlx5_flow_group_to_table(attr, dev_flow->external, attr->group,
7342 !!priv->fdb_def_rule, &table, error);
7345 dev_flow->dv.group = table;
7347 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
7348 if (priority == MLX5_FLOW_PRIO_RSVD)
7349 priority = dev_conf->flow_prio - 1;
7350 /* number of actions must be set to 0 in case of dirty stack. */
7351 mhdr_res->actions_num = 0;
7352 for (; !actions_end ; actions++) {
7353 const struct rte_flow_action_queue *queue;
7354 const struct rte_flow_action_rss *rss;
7355 const struct rte_flow_action *action = actions;
7356 const struct rte_flow_action_count *count = action->conf;
7357 const uint8_t *rss_key;
7358 const struct rte_flow_action_jump *jump_data;
7359 const struct rte_flow_action_meter *mtr;
7360 struct mlx5_flow_tbl_resource *tbl;
7361 uint32_t port_id = 0;
7362 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
7363 int action_type = actions->type;
7364 const struct rte_flow_action *found_action = NULL;
7366 switch (action_type) {
7367 case RTE_FLOW_ACTION_TYPE_VOID:
7369 case RTE_FLOW_ACTION_TYPE_PORT_ID:
7370 if (flow_dv_translate_action_port_id(dev, action,
7373 port_id_resource.port_id = port_id;
7374 if (flow_dv_port_id_action_resource_register
7375 (dev, &port_id_resource, dev_flow, error))
7377 dev_flow->dv.actions[actions_n++] =
7378 handle->dvh.port_id_action->action;
7379 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
7381 case RTE_FLOW_ACTION_TYPE_FLAG:
7382 action_flags |= MLX5_FLOW_ACTION_FLAG;
7383 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7384 struct rte_flow_action_mark mark = {
7385 .id = MLX5_FLOW_MARK_DEFAULT,
7388 if (flow_dv_convert_action_mark(dev, &mark,
7392 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
7395 tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
7397 * Only one FLAG or MARK is supported per device flow
7398 * right now. So the pointer to the tag resource must be
7399 * zero before the register process.
7401 MLX5_ASSERT(!handle->dvh.tag_resource);
7402 if (flow_dv_tag_resource_register(dev, tag_be,
7405 dev_flow->dv.actions[actions_n++] =
7406 handle->dvh.tag_resource->action;
7408 case RTE_FLOW_ACTION_TYPE_MARK:
7409 action_flags |= MLX5_FLOW_ACTION_MARK;
7410 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7411 const struct rte_flow_action_mark *mark =
7412 (const struct rte_flow_action_mark *)
7415 if (flow_dv_convert_action_mark(dev, mark,
7419 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
7423 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
7424 /* Legacy (non-extensive) MARK action. */
7425 tag_be = mlx5_flow_mark_set
7426 (((const struct rte_flow_action_mark *)
7427 (actions->conf))->id);
7428 MLX5_ASSERT(!handle->dvh.tag_resource);
7429 if (flow_dv_tag_resource_register(dev, tag_be,
7432 dev_flow->dv.actions[actions_n++] =
7433 handle->dvh.tag_resource->action;
7435 case RTE_FLOW_ACTION_TYPE_SET_META:
7436 if (flow_dv_convert_action_set_meta
7437 (dev, mhdr_res, attr,
7438 (const struct rte_flow_action_set_meta *)
7439 actions->conf, error))
7441 action_flags |= MLX5_FLOW_ACTION_SET_META;
7443 case RTE_FLOW_ACTION_TYPE_SET_TAG:
7444 if (flow_dv_convert_action_set_tag
7446 (const struct rte_flow_action_set_tag *)
7447 actions->conf, error))
7449 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7451 case RTE_FLOW_ACTION_TYPE_DROP:
7452 action_flags |= MLX5_FLOW_ACTION_DROP;
7454 case RTE_FLOW_ACTION_TYPE_QUEUE:
7455 MLX5_ASSERT(flow->rss.queue);
7456 queue = actions->conf;
7457 flow->rss.queue_num = 1;
7458 (*flow->rss.queue)[0] = queue->index;
7459 action_flags |= MLX5_FLOW_ACTION_QUEUE;
7461 case RTE_FLOW_ACTION_TYPE_RSS:
7462 MLX5_ASSERT(flow->rss.queue);
7463 rss = actions->conf;
7464 if (flow->rss.queue)
7465 memcpy((*flow->rss.queue), rss->queue,
7466 rss->queue_num * sizeof(uint16_t));
7467 flow->rss.queue_num = rss->queue_num;
7468 /* NULL RSS key indicates default RSS key. */
7469 rss_key = !rss->key ? rss_hash_default_key : rss->key;
7470 memcpy(flow->rss.key, rss_key, MLX5_RSS_HASH_KEY_LEN);
7472 * rss->level and rss.types should be set in advance
7473 * when expanding items for RSS.
7475 action_flags |= MLX5_FLOW_ACTION_RSS;
7477 case RTE_FLOW_ACTION_TYPE_COUNT:
7478 if (!dev_conf->devx) {
7479 rte_errno = ENOTSUP;
7482 flow->counter = flow_dv_counter_alloc(dev,
7485 dev_flow->dv.group);
7488 dev_flow->dv.actions[actions_n++] =
7489 (flow_dv_counter_get_by_idx(dev,
7490 flow->counter, NULL))->action;
7491 action_flags |= MLX5_FLOW_ACTION_COUNT;
7494 if (rte_errno == ENOTSUP)
7495 return rte_flow_error_set
7497 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7499 "count action not supported");
7501 return rte_flow_error_set
7503 RTE_FLOW_ERROR_TYPE_ACTION,
7505 "cannot create counter"
7508 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
7509 dev_flow->dv.actions[actions_n++] =
7510 priv->sh->pop_vlan_action;
7511 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
7513 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
7514 flow_dev_get_vlan_info_from_items(items, &vlan);
7515 vlan.eth_proto = rte_be_to_cpu_16
7516 ((((const struct rte_flow_action_of_push_vlan *)
7517 actions->conf)->ethertype));
7518 found_action = mlx5_flow_find_action
7520 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
7522 mlx5_update_vlan_vid_pcp(found_action, &vlan);
7523 found_action = mlx5_flow_find_action
7525 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
7527 mlx5_update_vlan_vid_pcp(found_action, &vlan);
7528 if (flow_dv_create_action_push_vlan
7529 (dev, attr, &vlan, dev_flow, error))
7531 dev_flow->dv.actions[actions_n++] =
7532 handle->dvh.push_vlan_res->action;
7533 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
7535 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
7536 /* of_vlan_push action handled this action */
7537 MLX5_ASSERT(action_flags &
7538 MLX5_FLOW_ACTION_OF_PUSH_VLAN);
7540 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
7541 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
7543 flow_dev_get_vlan_info_from_items(items, &vlan);
7544 mlx5_update_vlan_vid_pcp(actions, &vlan);
7545 /* If no VLAN push - this is a modify header action */
7546 if (flow_dv_convert_action_modify_vlan_vid
7547 (mhdr_res, actions, error))
7549 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
7551 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
7552 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
7553 if (flow_dv_create_action_l2_encap(dev, actions,
7558 dev_flow->dv.actions[actions_n++] =
7559 handle->dvh.encap_decap->verbs_action;
7560 action_flags |= MLX5_FLOW_ACTION_ENCAP;
7562 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
7563 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
7564 if (flow_dv_create_action_l2_decap(dev, dev_flow,
7568 dev_flow->dv.actions[actions_n++] =
7569 handle->dvh.encap_decap->verbs_action;
7570 action_flags |= MLX5_FLOW_ACTION_DECAP;
7572 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
7573 /* Handle encap with preceding decap. */
7574 if (action_flags & MLX5_FLOW_ACTION_DECAP) {
7575 if (flow_dv_create_action_raw_encap
7576 (dev, actions, dev_flow, attr, error))
7578 dev_flow->dv.actions[actions_n++] =
7579 handle->dvh.encap_decap->verbs_action;
7581 /* Handle encap without preceding decap. */
7582 if (flow_dv_create_action_l2_encap
7583 (dev, actions, dev_flow, attr->transfer,
7586 dev_flow->dv.actions[actions_n++] =
7587 handle->dvh.encap_decap->verbs_action;
7589 action_flags |= MLX5_FLOW_ACTION_ENCAP;
7591 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
7592 while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
7594 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
7595 if (flow_dv_create_action_l2_decap
7596 (dev, dev_flow, attr->transfer, error))
7598 dev_flow->dv.actions[actions_n++] =
7599 handle->dvh.encap_decap->verbs_action;
7601 /* If decap is followed by encap, handle it at encap. */
7602 action_flags |= MLX5_FLOW_ACTION_DECAP;
7604 case RTE_FLOW_ACTION_TYPE_JUMP:
7605 jump_data = action->conf;
7606 ret = mlx5_flow_group_to_table(attr, dev_flow->external,
7608 !!priv->fdb_def_rule,
7612 tbl = flow_dv_tbl_resource_get(dev, table,
7614 attr->transfer, error);
7616 return rte_flow_error_set
7618 RTE_FLOW_ERROR_TYPE_ACTION,
7620 "cannot create jump action.");
7621 if (flow_dv_jump_tbl_resource_register
7622 (dev, tbl, dev_flow, error)) {
7623 flow_dv_tbl_resource_release(dev, tbl);
7624 return rte_flow_error_set
7626 RTE_FLOW_ERROR_TYPE_ACTION,
7628 "cannot create jump action.");
7630 dev_flow->dv.actions[actions_n++] =
7631 handle->dvh.jump->action;
7632 action_flags |= MLX5_FLOW_ACTION_JUMP;
7634 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
7635 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
7636 if (flow_dv_convert_action_modify_mac
7637 (mhdr_res, actions, error))
7639 action_flags |= actions->type ==
7640 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
7641 MLX5_FLOW_ACTION_SET_MAC_SRC :
7642 MLX5_FLOW_ACTION_SET_MAC_DST;
7644 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
7645 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
7646 if (flow_dv_convert_action_modify_ipv4
7647 (mhdr_res, actions, error))
7649 action_flags |= actions->type ==
7650 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
7651 MLX5_FLOW_ACTION_SET_IPV4_SRC :
7652 MLX5_FLOW_ACTION_SET_IPV4_DST;
7654 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
7655 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
7656 if (flow_dv_convert_action_modify_ipv6
7657 (mhdr_res, actions, error))
7659 action_flags |= actions->type ==
7660 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
7661 MLX5_FLOW_ACTION_SET_IPV6_SRC :
7662 MLX5_FLOW_ACTION_SET_IPV6_DST;
7664 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
7665 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
7666 if (flow_dv_convert_action_modify_tp
7667 (mhdr_res, actions, items,
7668 &flow_attr, dev_flow, !!(action_flags &
7669 MLX5_FLOW_ACTION_DECAP), error))
7671 action_flags |= actions->type ==
7672 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
7673 MLX5_FLOW_ACTION_SET_TP_SRC :
7674 MLX5_FLOW_ACTION_SET_TP_DST;
7676 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
7677 if (flow_dv_convert_action_modify_dec_ttl
7678 (mhdr_res, items, &flow_attr, dev_flow,
7680 MLX5_FLOW_ACTION_DECAP), error))
7682 action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
7684 case RTE_FLOW_ACTION_TYPE_SET_TTL:
7685 if (flow_dv_convert_action_modify_ttl
7686 (mhdr_res, actions, items, &flow_attr,
7687 dev_flow, !!(action_flags &
7688 MLX5_FLOW_ACTION_DECAP), error))
7690 action_flags |= MLX5_FLOW_ACTION_SET_TTL;
7692 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
7693 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
7694 if (flow_dv_convert_action_modify_tcp_seq
7695 (mhdr_res, actions, error))
7697 action_flags |= actions->type ==
7698 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
7699 MLX5_FLOW_ACTION_INC_TCP_SEQ :
7700 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
7703 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
7704 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
7705 if (flow_dv_convert_action_modify_tcp_ack
7706 (mhdr_res, actions, error))
7708 action_flags |= actions->type ==
7709 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
7710 MLX5_FLOW_ACTION_INC_TCP_ACK :
7711 MLX5_FLOW_ACTION_DEC_TCP_ACK;
7713 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
7714 if (flow_dv_convert_action_set_reg
7715 (mhdr_res, actions, error))
7717 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7719 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
7720 if (flow_dv_convert_action_copy_mreg
7721 (dev, mhdr_res, actions, error))
7723 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7725 case RTE_FLOW_ACTION_TYPE_METER:
7726 mtr = actions->conf;
7728 flow->meter = mlx5_flow_meter_attach(priv,
7732 return rte_flow_error_set(error,
7734 RTE_FLOW_ERROR_TYPE_ACTION,
7737 "or invalid parameters");
7739 /* Set the meter action. */
7740 dev_flow->dv.actions[actions_n++] =
7741 flow->meter->mfts->meter_action;
7742 action_flags |= MLX5_FLOW_ACTION_METER;
7744 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
7745 if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
7748 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
7750 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
7751 if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
7754 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
7756 case RTE_FLOW_ACTION_TYPE_END:
7758 if (mhdr_res->actions_num) {
7759 /* create modify action if needed. */
7760 if (flow_dv_modify_hdr_resource_register
7761 (dev, mhdr_res, dev_flow, error))
7763 dev_flow->dv.actions[modify_action_position] =
7764 handle->dvh.modify_hdr->verbs_action;
7770 if (mhdr_res->actions_num &&
7771 modify_action_position == UINT32_MAX)
7772 modify_action_position = actions_n++;
7774 dev_flow->dv.actions_n = actions_n;
7775 handle->act_flags = action_flags;
7776 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
7777 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
7778 int item_type = items->type;
7780 switch (item_type) {
7781 case RTE_FLOW_ITEM_TYPE_PORT_ID:
7782 flow_dv_translate_item_port_id(dev, match_mask,
7783 match_value, items);
7784 last_item = MLX5_FLOW_ITEM_PORT_ID;
7786 case RTE_FLOW_ITEM_TYPE_ETH:
7787 flow_dv_translate_item_eth(match_mask, match_value,
7789 matcher.priority = MLX5_PRIORITY_MAP_L2;
7790 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
7791 MLX5_FLOW_LAYER_OUTER_L2;
7793 case RTE_FLOW_ITEM_TYPE_VLAN:
7794 flow_dv_translate_item_vlan(dev_flow,
7795 match_mask, match_value,
7797 matcher.priority = MLX5_PRIORITY_MAP_L2;
7798 last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
7799 MLX5_FLOW_LAYER_INNER_VLAN) :
7800 (MLX5_FLOW_LAYER_OUTER_L2 |
7801 MLX5_FLOW_LAYER_OUTER_VLAN);
7803 case RTE_FLOW_ITEM_TYPE_IPV4:
7804 mlx5_flow_tunnel_ip_check(items, next_protocol,
7805 &item_flags, &tunnel);
7806 flow_dv_translate_item_ipv4(match_mask, match_value,
7807 items, item_flags, tunnel,
7808 dev_flow->dv.group);
7809 matcher.priority = MLX5_PRIORITY_MAP_L3;
7810 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
7811 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
7812 if (items->mask != NULL &&
7813 ((const struct rte_flow_item_ipv4 *)
7814 items->mask)->hdr.next_proto_id) {
7816 ((const struct rte_flow_item_ipv4 *)
7817 (items->spec))->hdr.next_proto_id;
7819 ((const struct rte_flow_item_ipv4 *)
7820 (items->mask))->hdr.next_proto_id;
7822 /* Reset for inner layer. */
7823 next_protocol = 0xff;
7826 case RTE_FLOW_ITEM_TYPE_IPV6:
7827 mlx5_flow_tunnel_ip_check(items, next_protocol,
7828 &item_flags, &tunnel);
7829 flow_dv_translate_item_ipv6(match_mask, match_value,
7830 items, item_flags, tunnel,
7831 dev_flow->dv.group);
7832 matcher.priority = MLX5_PRIORITY_MAP_L3;
7833 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
7834 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
7835 if (items->mask != NULL &&
7836 ((const struct rte_flow_item_ipv6 *)
7837 items->mask)->hdr.proto) {
7839 ((const struct rte_flow_item_ipv6 *)
7840 items->spec)->hdr.proto;
7842 ((const struct rte_flow_item_ipv6 *)
7843 items->mask)->hdr.proto;
7845 /* Reset for inner layer. */
7846 next_protocol = 0xff;
7849 case RTE_FLOW_ITEM_TYPE_TCP:
7850 flow_dv_translate_item_tcp(match_mask, match_value,
7852 matcher.priority = MLX5_PRIORITY_MAP_L4;
7853 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
7854 MLX5_FLOW_LAYER_OUTER_L4_TCP;
7856 case RTE_FLOW_ITEM_TYPE_UDP:
7857 flow_dv_translate_item_udp(match_mask, match_value,
7859 matcher.priority = MLX5_PRIORITY_MAP_L4;
7860 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
7861 MLX5_FLOW_LAYER_OUTER_L4_UDP;
7863 case RTE_FLOW_ITEM_TYPE_GRE:
7864 flow_dv_translate_item_gre(match_mask, match_value,
7866 matcher.priority = flow->rss.level >= 2 ?
7867 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7868 last_item = MLX5_FLOW_LAYER_GRE;
7870 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
7871 flow_dv_translate_item_gre_key(match_mask,
7872 match_value, items);
7873 last_item = MLX5_FLOW_LAYER_GRE_KEY;
7875 case RTE_FLOW_ITEM_TYPE_NVGRE:
7876 flow_dv_translate_item_nvgre(match_mask, match_value,
7878 matcher.priority = flow->rss.level >= 2 ?
7879 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7880 last_item = MLX5_FLOW_LAYER_GRE;
7882 case RTE_FLOW_ITEM_TYPE_VXLAN:
7883 flow_dv_translate_item_vxlan(match_mask, match_value,
7885 matcher.priority = flow->rss.level >= 2 ?
7886 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7887 last_item = MLX5_FLOW_LAYER_VXLAN;
7889 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
7890 flow_dv_translate_item_vxlan_gpe(match_mask,
7893 matcher.priority = flow->rss.level >= 2 ?
7894 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7895 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
7897 case RTE_FLOW_ITEM_TYPE_GENEVE:
7898 flow_dv_translate_item_geneve(match_mask, match_value,
7900 matcher.priority = flow->rss.level >= 2 ?
7901 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7902 last_item = MLX5_FLOW_LAYER_GENEVE;
7904 case RTE_FLOW_ITEM_TYPE_MPLS:
7905 flow_dv_translate_item_mpls(match_mask, match_value,
7906 items, last_item, tunnel);
7907 matcher.priority = flow->rss.level >= 2 ?
7908 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7909 last_item = MLX5_FLOW_LAYER_MPLS;
7911 case RTE_FLOW_ITEM_TYPE_MARK:
7912 flow_dv_translate_item_mark(dev, match_mask,
7913 match_value, items);
7914 last_item = MLX5_FLOW_ITEM_MARK;
7916 case RTE_FLOW_ITEM_TYPE_META:
7917 flow_dv_translate_item_meta(dev, match_mask,
7918 match_value, attr, items);
7919 last_item = MLX5_FLOW_ITEM_METADATA;
7921 case RTE_FLOW_ITEM_TYPE_ICMP:
7922 flow_dv_translate_item_icmp(match_mask, match_value,
7924 last_item = MLX5_FLOW_LAYER_ICMP;
7926 case RTE_FLOW_ITEM_TYPE_ICMP6:
7927 flow_dv_translate_item_icmp6(match_mask, match_value,
7929 last_item = MLX5_FLOW_LAYER_ICMP6;
7931 case RTE_FLOW_ITEM_TYPE_TAG:
7932 flow_dv_translate_item_tag(dev, match_mask,
7933 match_value, items);
7934 last_item = MLX5_FLOW_ITEM_TAG;
7936 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
7937 flow_dv_translate_mlx5_item_tag(dev, match_mask,
7938 match_value, items);
7939 last_item = MLX5_FLOW_ITEM_TAG;
7941 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
7942 flow_dv_translate_item_tx_queue(dev, match_mask,
7945 last_item = MLX5_FLOW_ITEM_TX_QUEUE;
7947 case RTE_FLOW_ITEM_TYPE_GTP:
7948 flow_dv_translate_item_gtp(match_mask, match_value,
7950 matcher.priority = flow->rss.level >= 2 ?
7951 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7952 last_item = MLX5_FLOW_LAYER_GTP;
7957 item_flags |= last_item;
7960 * When E-Switch mode is enabled, we have two cases where we need to
7961 * set the source port manually.
7962 * The first one, is in case of Nic steering rule, and the second is
7963 * E-Switch rule where no port_id item was found. In both cases
7964 * the source port is set according the current port in use.
7966 if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
7967 (priv->representor || priv->master)) {
7968 if (flow_dv_translate_item_port_id(dev, match_mask,
7972 #ifdef RTE_LIBRTE_MLX5_DEBUG
7973 MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
7974 dev_flow->dv.value.buf));
7977 * Layers may be already initialized from prefix flow if this dev_flow
7978 * is the suffix flow.
7980 handle->layers |= item_flags;
7981 if (action_flags & MLX5_FLOW_ACTION_RSS)
7982 flow_dv_hashfields_set(dev_flow);
7983 /* Register matcher. */
7984 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
7986 matcher.priority = mlx5_flow_adjust_priority(dev, priority,
7988 /* reserved field no needs to be set to 0 here. */
7989 tbl_key.domain = attr->transfer;
7990 tbl_key.direction = attr->egress;
7991 tbl_key.table_id = dev_flow->dv.group;
7992 if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow, error))
7998 * Apply the flow to the NIC, lock free,
7999 * (mutex should be acquired by caller).
8002 * Pointer to the Ethernet device structure.
8003 * @param[in, out] flow
8004 * Pointer to flow structure.
8006 * Pointer to error structure.
8009 * 0 on success, a negative errno value otherwise and rte_errno is set.
8012 __flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
8013 struct rte_flow_error *error)
8015 struct mlx5_flow_dv_workspace *dv;
8016 struct mlx5_flow_handle *dh;
8017 struct mlx5_flow_handle_dv *dv_h;
8018 struct mlx5_flow *dev_flow;
8019 struct mlx5_priv *priv = dev->data->dev_private;
8024 for (idx = priv->flow_idx - 1; idx >= priv->flow_nested_idx; idx--) {
8025 dev_flow = &((struct mlx5_flow *)priv->inter_flows)[idx];
8027 dh = dev_flow->handle;
8030 if (dh->act_flags & MLX5_FLOW_ACTION_DROP) {
8032 dv->actions[n++] = priv->sh->esw_drop_action;
8034 dh->hrxq = mlx5_hrxq_drop_new(dev);
8038 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8040 "cannot get drop hash queue");
8043 dv->actions[n++] = dh->hrxq->action;
8045 } else if (dh->act_flags &
8046 (MLX5_FLOW_ACTION_QUEUE | MLX5_FLOW_ACTION_RSS)) {
8047 struct mlx5_hrxq *hrxq;
8049 MLX5_ASSERT(flow->rss.queue);
8050 hrxq = mlx5_hrxq_get(dev, flow->rss.key,
8051 MLX5_RSS_HASH_KEY_LEN,
8052 dev_flow->hash_fields,
8054 flow->rss.queue_num);
8056 hrxq = mlx5_hrxq_new
8057 (dev, flow->rss.key,
8058 MLX5_RSS_HASH_KEY_LEN,
8059 dev_flow->hash_fields,
8061 flow->rss.queue_num,
8063 MLX5_FLOW_LAYER_TUNNEL));
8068 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8069 "cannot get hash queue");
8073 dv->actions[n++] = dh->hrxq->action;
8076 mlx5_glue->dv_create_flow(dv_h->matcher->matcher_object,
8077 (void *)&dv->value, n,
8080 rte_flow_error_set(error, errno,
8081 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8083 "hardware refuses to create flow");
8086 if (priv->vmwa_context &&
8087 dh->vf_vlan.tag && !dh->vf_vlan.created) {
8089 * The rule contains the VLAN pattern.
8090 * For VF we are going to create VLAN
8091 * interface to make hypervisor set correct
8092 * e-Switch vport context.
8094 mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
8099 err = rte_errno; /* Save rte_errno before cleanup. */
8100 LIST_FOREACH(dh, &flow->dev_handles, next) {
8102 if (dh->act_flags & MLX5_FLOW_ACTION_DROP)
8103 mlx5_hrxq_drop_release(dev);
8105 mlx5_hrxq_release(dev, dh->hrxq);
8108 if (dh->vf_vlan.tag && dh->vf_vlan.created)
8109 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
8111 rte_errno = err; /* Restore rte_errno. */
8116 * Release the flow matcher.
8119 * Pointer to Ethernet device.
8121 * Pointer to mlx5_flow_handle.
8124 * 1 while a reference on it exists, 0 when freed.
8127 flow_dv_matcher_release(struct rte_eth_dev *dev,
8128 struct mlx5_flow_handle *handle)
8130 struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
8132 MLX5_ASSERT(matcher->matcher_object);
8133 DRV_LOG(DEBUG, "port %u matcher %p: refcnt %d--",
8134 dev->data->port_id, (void *)matcher,
8135 rte_atomic32_read(&matcher->refcnt));
8136 if (rte_atomic32_dec_and_test(&matcher->refcnt)) {
8137 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8138 (matcher->matcher_object));
8139 LIST_REMOVE(matcher, next);
8140 /* table ref-- in release interface. */
8141 flow_dv_tbl_resource_release(dev, matcher->tbl);
8143 DRV_LOG(DEBUG, "port %u matcher %p: removed",
8144 dev->data->port_id, (void *)matcher);
8151 * Release an encap/decap resource.
8154 * Pointer to mlx5_flow_handle.
8157 * 1 while a reference on it exists, 0 when freed.
8160 flow_dv_encap_decap_resource_release(struct mlx5_flow_handle *handle)
8162 struct mlx5_flow_dv_encap_decap_resource *cache_resource =
8163 handle->dvh.encap_decap;
8165 MLX5_ASSERT(cache_resource->verbs_action);
8166 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d--",
8167 (void *)cache_resource,
8168 rte_atomic32_read(&cache_resource->refcnt));
8169 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8170 claim_zero(mlx5_glue->destroy_flow_action
8171 (cache_resource->verbs_action));
8172 LIST_REMOVE(cache_resource, next);
8173 rte_free(cache_resource);
8174 DRV_LOG(DEBUG, "encap/decap resource %p: removed",
8175 (void *)cache_resource);
8182 * Release an jump to table action resource.
8185 * Pointer to Ethernet device.
8187 * Pointer to mlx5_flow_handle.
8190 * 1 while a reference on it exists, 0 when freed.
8193 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
8194 struct mlx5_flow_handle *handle)
8196 struct mlx5_flow_dv_jump_tbl_resource *cache_resource =
8198 struct mlx5_flow_tbl_data_entry *tbl_data =
8199 container_of(cache_resource,
8200 struct mlx5_flow_tbl_data_entry, jump);
8202 MLX5_ASSERT(cache_resource->action);
8203 DRV_LOG(DEBUG, "jump table resource %p: refcnt %d--",
8204 (void *)cache_resource,
8205 rte_atomic32_read(&cache_resource->refcnt));
8206 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8207 claim_zero(mlx5_glue->destroy_flow_action
8208 (cache_resource->action));
8209 /* jump action memory free is inside the table release. */
8210 flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
8211 DRV_LOG(DEBUG, "jump table resource %p: removed",
8212 (void *)cache_resource);
8219 * Release a modify-header resource.
8222 * Pointer to mlx5_flow_handle.
8225 * 1 while a reference on it exists, 0 when freed.
8228 flow_dv_modify_hdr_resource_release(struct mlx5_flow_handle *handle)
8230 struct mlx5_flow_dv_modify_hdr_resource *cache_resource =
8231 handle->dvh.modify_hdr;
8233 MLX5_ASSERT(cache_resource->verbs_action);
8234 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d--",
8235 (void *)cache_resource,
8236 rte_atomic32_read(&cache_resource->refcnt));
8237 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8238 claim_zero(mlx5_glue->destroy_flow_action
8239 (cache_resource->verbs_action));
8240 LIST_REMOVE(cache_resource, next);
8241 rte_free(cache_resource);
8242 DRV_LOG(DEBUG, "modify-header resource %p: removed",
8243 (void *)cache_resource);
8250 * Release port ID action resource.
8253 * Pointer to mlx5_flow_handle.
8256 * 1 while a reference on it exists, 0 when freed.
8259 flow_dv_port_id_action_resource_release(struct mlx5_flow_handle *handle)
8261 struct mlx5_flow_dv_port_id_action_resource *cache_resource =
8262 handle->dvh.port_id_action;
8264 MLX5_ASSERT(cache_resource->action);
8265 DRV_LOG(DEBUG, "port ID action resource %p: refcnt %d--",
8266 (void *)cache_resource,
8267 rte_atomic32_read(&cache_resource->refcnt));
8268 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8269 claim_zero(mlx5_glue->destroy_flow_action
8270 (cache_resource->action));
8271 LIST_REMOVE(cache_resource, next);
8272 rte_free(cache_resource);
8273 DRV_LOG(DEBUG, "port id action resource %p: removed",
8274 (void *)cache_resource);
8281 * Release push vlan action resource.
8284 * Pointer to mlx5_flow_handle.
8287 * 1 while a reference on it exists, 0 when freed.
8290 flow_dv_push_vlan_action_resource_release(struct mlx5_flow_handle *handle)
8292 struct mlx5_flow_dv_push_vlan_action_resource *cache_resource =
8293 handle->dvh.push_vlan_res;
8295 MLX5_ASSERT(cache_resource->action);
8296 DRV_LOG(DEBUG, "push VLAN action resource %p: refcnt %d--",
8297 (void *)cache_resource,
8298 rte_atomic32_read(&cache_resource->refcnt));
8299 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8300 claim_zero(mlx5_glue->destroy_flow_action
8301 (cache_resource->action));
8302 LIST_REMOVE(cache_resource, next);
8303 rte_free(cache_resource);
8304 DRV_LOG(DEBUG, "push vlan action resource %p: removed",
8305 (void *)cache_resource);
8312 * Remove the flow from the NIC but keeps it in memory.
8313 * Lock free, (mutex should be acquired by caller).
8316 * Pointer to Ethernet device.
8317 * @param[in, out] flow
8318 * Pointer to flow structure.
8321 __flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
8323 struct mlx5_flow_handle *dh;
8327 LIST_FOREACH(dh, &flow->dev_handles, next) {
8329 claim_zero(mlx5_glue->dv_destroy_flow(dh->ib_flow));
8333 if (dh->act_flags & MLX5_FLOW_ACTION_DROP)
8334 mlx5_hrxq_drop_release(dev);
8336 mlx5_hrxq_release(dev, dh->hrxq);
8339 if (dh->vf_vlan.tag && dh->vf_vlan.created)
8340 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
8345 * Remove the flow from the NIC and the memory.
8346 * Lock free, (mutex should be acquired by caller).
8349 * Pointer to the Ethernet device structure.
8350 * @param[in, out] flow
8351 * Pointer to flow structure.
8354 __flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
8356 struct mlx5_flow_handle *dev_handle;
8360 __flow_dv_remove(dev, flow);
8361 if (flow->counter) {
8362 flow_dv_counter_release(dev, flow->counter);
8366 mlx5_flow_meter_detach(flow->meter);
8369 while (!LIST_EMPTY(&flow->dev_handles)) {
8370 dev_handle = LIST_FIRST(&flow->dev_handles);
8371 LIST_REMOVE(dev_handle, next);
8372 if (dev_handle->dvh.matcher)
8373 flow_dv_matcher_release(dev, dev_handle);
8374 if (dev_handle->dvh.encap_decap)
8375 flow_dv_encap_decap_resource_release(dev_handle);
8376 if (dev_handle->dvh.modify_hdr)
8377 flow_dv_modify_hdr_resource_release(dev_handle);
8378 if (dev_handle->dvh.jump)
8379 flow_dv_jump_tbl_resource_release(dev, dev_handle);
8380 if (dev_handle->dvh.port_id_action)
8381 flow_dv_port_id_action_resource_release(dev_handle);
8382 if (dev_handle->dvh.push_vlan_res)
8383 flow_dv_push_vlan_action_resource_release(dev_handle);
8384 if (dev_handle->dvh.tag_resource)
8385 flow_dv_tag_release(dev,
8386 dev_handle->dvh.tag_resource);
8387 rte_free(dev_handle);
8392 * Query a dv flow rule for its statistics via devx.
8395 * Pointer to Ethernet device.
8397 * Pointer to the sub flow.
8399 * data retrieved by the query.
8401 * Perform verbose error reporting if not NULL.
8404 * 0 on success, a negative errno value otherwise and rte_errno is set.
8407 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
8408 void *data, struct rte_flow_error *error)
8410 struct mlx5_priv *priv = dev->data->dev_private;
8411 struct rte_flow_query_count *qc = data;
8413 if (!priv->config.devx)
8414 return rte_flow_error_set(error, ENOTSUP,
8415 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8417 "counters are not supported");
8418 if (flow->counter) {
8419 uint64_t pkts, bytes;
8420 struct mlx5_flow_counter *cnt;
8422 cnt = flow_dv_counter_get_by_idx(dev, flow->counter,
8424 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
8428 return rte_flow_error_set(error, -err,
8429 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8430 NULL, "cannot read counters");
8433 qc->hits = pkts - cnt->hits;
8434 qc->bytes = bytes - cnt->bytes;
8441 return rte_flow_error_set(error, EINVAL,
8442 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8444 "counters are not available");
8450 * @see rte_flow_query()
8454 flow_dv_query(struct rte_eth_dev *dev,
8455 struct rte_flow *flow __rte_unused,
8456 const struct rte_flow_action *actions __rte_unused,
8457 void *data __rte_unused,
8458 struct rte_flow_error *error __rte_unused)
8462 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
8463 switch (actions->type) {
8464 case RTE_FLOW_ACTION_TYPE_VOID:
8466 case RTE_FLOW_ACTION_TYPE_COUNT:
8467 ret = flow_dv_query_count(dev, flow, data, error);
8470 return rte_flow_error_set(error, ENOTSUP,
8471 RTE_FLOW_ERROR_TYPE_ACTION,
8473 "action not supported");
8480 * Destroy the meter table set.
8481 * Lock free, (mutex should be acquired by caller).
8484 * Pointer to Ethernet device.
8486 * Pointer to the meter table set.
8492 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
8493 struct mlx5_meter_domains_infos *tbl)
8495 struct mlx5_priv *priv = dev->data->dev_private;
8496 struct mlx5_meter_domains_infos *mtd =
8497 (struct mlx5_meter_domains_infos *)tbl;
8499 if (!mtd || !priv->config.dv_flow_en)
8501 if (mtd->ingress.policer_rules[RTE_MTR_DROPPED])
8502 claim_zero(mlx5_glue->dv_destroy_flow
8503 (mtd->ingress.policer_rules[RTE_MTR_DROPPED]));
8504 if (mtd->egress.policer_rules[RTE_MTR_DROPPED])
8505 claim_zero(mlx5_glue->dv_destroy_flow
8506 (mtd->egress.policer_rules[RTE_MTR_DROPPED]));
8507 if (mtd->transfer.policer_rules[RTE_MTR_DROPPED])
8508 claim_zero(mlx5_glue->dv_destroy_flow
8509 (mtd->transfer.policer_rules[RTE_MTR_DROPPED]));
8510 if (mtd->egress.color_matcher)
8511 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8512 (mtd->egress.color_matcher));
8513 if (mtd->egress.any_matcher)
8514 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8515 (mtd->egress.any_matcher));
8516 if (mtd->egress.tbl)
8517 claim_zero(flow_dv_tbl_resource_release(dev,
8519 if (mtd->ingress.color_matcher)
8520 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8521 (mtd->ingress.color_matcher));
8522 if (mtd->ingress.any_matcher)
8523 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8524 (mtd->ingress.any_matcher));
8525 if (mtd->ingress.tbl)
8526 claim_zero(flow_dv_tbl_resource_release(dev,
8528 if (mtd->transfer.color_matcher)
8529 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8530 (mtd->transfer.color_matcher));
8531 if (mtd->transfer.any_matcher)
8532 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8533 (mtd->transfer.any_matcher));
8534 if (mtd->transfer.tbl)
8535 claim_zero(flow_dv_tbl_resource_release(dev,
8536 mtd->transfer.tbl));
8538 claim_zero(mlx5_glue->destroy_flow_action(mtd->drop_actn));
8543 /* Number of meter flow actions, count and jump or count and drop. */
8544 #define METER_ACTIONS 2
8547 * Create specify domain meter table and suffix table.
8550 * Pointer to Ethernet device.
8551 * @param[in,out] mtb
8552 * Pointer to DV meter table set.
8555 * @param[in] transfer
8557 * @param[in] color_reg_c_idx
8558 * Reg C index for color match.
8561 * 0 on success, -1 otherwise and rte_errno is set.
8564 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
8565 struct mlx5_meter_domains_infos *mtb,
8566 uint8_t egress, uint8_t transfer,
8567 uint32_t color_reg_c_idx)
8569 struct mlx5_priv *priv = dev->data->dev_private;
8570 struct mlx5_ibv_shared *sh = priv->sh;
8571 struct mlx5_flow_dv_match_params mask = {
8572 .size = sizeof(mask.buf),
8574 struct mlx5_flow_dv_match_params value = {
8575 .size = sizeof(value.buf),
8577 struct mlx5dv_flow_matcher_attr dv_attr = {
8578 .type = IBV_FLOW_ATTR_NORMAL,
8580 .match_criteria_enable = 0,
8581 .match_mask = (void *)&mask,
8583 void *actions[METER_ACTIONS];
8584 struct mlx5_flow_tbl_resource **sfx_tbl;
8585 struct mlx5_meter_domain_info *dtb;
8586 struct rte_flow_error error;
8590 sfx_tbl = &sh->fdb_mtr_sfx_tbl;
8591 dtb = &mtb->transfer;
8592 } else if (egress) {
8593 sfx_tbl = &sh->tx_mtr_sfx_tbl;
8596 sfx_tbl = &sh->rx_mtr_sfx_tbl;
8597 dtb = &mtb->ingress;
8599 /* If the suffix table in missing, create it. */
8601 *sfx_tbl = flow_dv_tbl_resource_get(dev,
8602 MLX5_FLOW_TABLE_LEVEL_SUFFIX,
8603 egress, transfer, &error);
8605 DRV_LOG(ERR, "Failed to create meter suffix table.");
8609 /* Create the meter table with METER level. */
8610 dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
8611 egress, transfer, &error);
8613 DRV_LOG(ERR, "Failed to create meter policer table.");
8616 /* Create matchers, Any and Color. */
8617 dv_attr.priority = 3;
8618 dv_attr.match_criteria_enable = 0;
8619 dtb->any_matcher = mlx5_glue->dv_create_flow_matcher(sh->ctx,
8622 if (!dtb->any_matcher) {
8623 DRV_LOG(ERR, "Failed to create meter"
8624 " policer default matcher.");
8627 dv_attr.priority = 0;
8628 dv_attr.match_criteria_enable =
8629 1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
8630 flow_dv_match_meta_reg(mask.buf, value.buf, color_reg_c_idx,
8631 rte_col_2_mlx5_col(RTE_COLORS), UINT8_MAX);
8632 dtb->color_matcher = mlx5_glue->dv_create_flow_matcher(sh->ctx,
8635 if (!dtb->color_matcher) {
8636 DRV_LOG(ERR, "Failed to create meter policer color matcher.");
8639 if (mtb->count_actns[RTE_MTR_DROPPED])
8640 actions[i++] = mtb->count_actns[RTE_MTR_DROPPED];
8641 actions[i++] = mtb->drop_actn;
8642 /* Default rule: lowest priority, match any, actions: drop. */
8643 dtb->policer_rules[RTE_MTR_DROPPED] =
8644 mlx5_glue->dv_create_flow(dtb->any_matcher,
8645 (void *)&value, i, actions);
8646 if (!dtb->policer_rules[RTE_MTR_DROPPED]) {
8647 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
8656 * Create the needed meter and suffix tables.
8657 * Lock free, (mutex should be acquired by caller).
8660 * Pointer to Ethernet device.
8662 * Pointer to the flow meter.
8665 * Pointer to table set on success, NULL otherwise and rte_errno is set.
8667 static struct mlx5_meter_domains_infos *
8668 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev,
8669 const struct mlx5_flow_meter *fm)
8671 struct mlx5_priv *priv = dev->data->dev_private;
8672 struct mlx5_meter_domains_infos *mtb;
8676 if (!priv->mtr_en) {
8677 rte_errno = ENOTSUP;
8680 mtb = rte_calloc(__func__, 1, sizeof(*mtb), 0);
8682 DRV_LOG(ERR, "Failed to allocate memory for meter.");
8685 /* Create meter count actions */
8686 for (i = 0; i <= RTE_MTR_DROPPED; i++) {
8687 struct mlx5_flow_counter *cnt;
8688 if (!fm->policer_stats.cnt[i])
8690 cnt = flow_dv_counter_get_by_idx(dev,
8691 fm->policer_stats.cnt[i], NULL);
8692 mtb->count_actns[i] = cnt->action;
8694 /* Create drop action. */
8695 mtb->drop_actn = mlx5_glue->dr_create_flow_action_drop();
8696 if (!mtb->drop_actn) {
8697 DRV_LOG(ERR, "Failed to create drop action.");
8700 /* Egress meter table. */
8701 ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0, priv->mtr_color_reg);
8703 DRV_LOG(ERR, "Failed to prepare egress meter table.");
8706 /* Ingress meter table. */
8707 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0, priv->mtr_color_reg);
8709 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
8712 /* FDB meter table. */
8713 if (priv->config.dv_esw_en) {
8714 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1,
8715 priv->mtr_color_reg);
8717 DRV_LOG(ERR, "Failed to prepare fdb meter table.");
8723 flow_dv_destroy_mtr_tbl(dev, mtb);
8728 * Destroy domain policer rule.
8731 * Pointer to domain table.
8734 flow_dv_destroy_domain_policer_rule(struct mlx5_meter_domain_info *dt)
8738 for (i = 0; i < RTE_MTR_DROPPED; i++) {
8739 if (dt->policer_rules[i]) {
8740 claim_zero(mlx5_glue->dv_destroy_flow
8741 (dt->policer_rules[i]));
8742 dt->policer_rules[i] = NULL;
8745 if (dt->jump_actn) {
8746 claim_zero(mlx5_glue->destroy_flow_action(dt->jump_actn));
8747 dt->jump_actn = NULL;
8752 * Destroy policer rules.
8755 * Pointer to Ethernet device.
8757 * Pointer to flow meter structure.
8759 * Pointer to flow attributes.
8765 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev __rte_unused,
8766 const struct mlx5_flow_meter *fm,
8767 const struct rte_flow_attr *attr)
8769 struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
8774 flow_dv_destroy_domain_policer_rule(&mtb->egress);
8776 flow_dv_destroy_domain_policer_rule(&mtb->ingress);
8778 flow_dv_destroy_domain_policer_rule(&mtb->transfer);
8783 * Create specify domain meter policer rule.
8786 * Pointer to flow meter structure.
8788 * Pointer to DV meter table set.
8790 * Pointer to suffix table.
8791 * @param[in] mtr_reg_c
8792 * Color match REG_C.
8795 * 0 on success, -1 otherwise.
8798 flow_dv_create_policer_forward_rule(struct mlx5_flow_meter *fm,
8799 struct mlx5_meter_domain_info *dtb,
8800 struct mlx5_flow_tbl_resource *sfx_tb,
8803 struct mlx5_flow_dv_match_params matcher = {
8804 .size = sizeof(matcher.buf),
8806 struct mlx5_flow_dv_match_params value = {
8807 .size = sizeof(value.buf),
8809 struct mlx5_meter_domains_infos *mtb = fm->mfts;
8810 void *actions[METER_ACTIONS];
8813 /* Create jump action. */
8816 if (!dtb->jump_actn)
8818 mlx5_glue->dr_create_flow_action_dest_flow_tbl
8820 if (!dtb->jump_actn) {
8821 DRV_LOG(ERR, "Failed to create policer jump action.");
8824 for (i = 0; i < RTE_MTR_DROPPED; i++) {
8827 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_reg_c,
8828 rte_col_2_mlx5_col(i), UINT8_MAX);
8829 if (mtb->count_actns[i])
8830 actions[j++] = mtb->count_actns[i];
8831 if (fm->params.action[i] == MTR_POLICER_ACTION_DROP)
8832 actions[j++] = mtb->drop_actn;
8834 actions[j++] = dtb->jump_actn;
8835 dtb->policer_rules[i] =
8836 mlx5_glue->dv_create_flow(dtb->color_matcher,
8839 if (!dtb->policer_rules[i]) {
8840 DRV_LOG(ERR, "Failed to create policer rule.");
8851 * Create policer rules.
8854 * Pointer to Ethernet device.
8856 * Pointer to flow meter structure.
8858 * Pointer to flow attributes.
8861 * 0 on success, -1 otherwise.
8864 flow_dv_create_policer_rules(struct rte_eth_dev *dev,
8865 struct mlx5_flow_meter *fm,
8866 const struct rte_flow_attr *attr)
8868 struct mlx5_priv *priv = dev->data->dev_private;
8869 struct mlx5_meter_domains_infos *mtb = fm->mfts;
8873 ret = flow_dv_create_policer_forward_rule(fm, &mtb->egress,
8874 priv->sh->tx_mtr_sfx_tbl,
8875 priv->mtr_color_reg);
8877 DRV_LOG(ERR, "Failed to create egress policer.");
8881 if (attr->ingress) {
8882 ret = flow_dv_create_policer_forward_rule(fm, &mtb->ingress,
8883 priv->sh->rx_mtr_sfx_tbl,
8884 priv->mtr_color_reg);
8886 DRV_LOG(ERR, "Failed to create ingress policer.");
8890 if (attr->transfer) {
8891 ret = flow_dv_create_policer_forward_rule(fm, &mtb->transfer,
8892 priv->sh->fdb_mtr_sfx_tbl,
8893 priv->mtr_color_reg);
8895 DRV_LOG(ERR, "Failed to create transfer policer.");
8901 flow_dv_destroy_policer_rules(dev, fm, attr);
8906 * Query a devx counter.
8909 * Pointer to the Ethernet device structure.
8911 * Index to the flow counter.
8913 * Set to clear the counter statistics.
8915 * The statistics value of packets.
8917 * The statistics value of bytes.
8920 * 0 on success, otherwise return -1.
8923 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
8924 uint64_t *pkts, uint64_t *bytes)
8926 struct mlx5_priv *priv = dev->data->dev_private;
8927 struct mlx5_flow_counter *cnt;
8928 uint64_t inn_pkts, inn_bytes;
8931 if (!priv->config.devx)
8934 ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
8937 cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
8938 *pkts = inn_pkts - cnt->hits;
8939 *bytes = inn_bytes - cnt->bytes;
8941 cnt->hits = inn_pkts;
8942 cnt->bytes = inn_bytes;
8948 * Mutex-protected thunk to lock-free __flow_dv_translate().
8951 flow_dv_translate(struct rte_eth_dev *dev,
8952 struct mlx5_flow *dev_flow,
8953 const struct rte_flow_attr *attr,
8954 const struct rte_flow_item items[],
8955 const struct rte_flow_action actions[],
8956 struct rte_flow_error *error)
8960 flow_dv_shared_lock(dev);
8961 ret = __flow_dv_translate(dev, dev_flow, attr, items, actions, error);
8962 flow_dv_shared_unlock(dev);
8967 * Mutex-protected thunk to lock-free __flow_dv_apply().
8970 flow_dv_apply(struct rte_eth_dev *dev,
8971 struct rte_flow *flow,
8972 struct rte_flow_error *error)
8976 flow_dv_shared_lock(dev);
8977 ret = __flow_dv_apply(dev, flow, error);
8978 flow_dv_shared_unlock(dev);
8983 * Mutex-protected thunk to lock-free __flow_dv_remove().
8986 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
8988 flow_dv_shared_lock(dev);
8989 __flow_dv_remove(dev, flow);
8990 flow_dv_shared_unlock(dev);
8994 * Mutex-protected thunk to lock-free __flow_dv_destroy().
8997 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
8999 flow_dv_shared_lock(dev);
9000 __flow_dv_destroy(dev, flow);
9001 flow_dv_shared_unlock(dev);
9005 * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
9008 flow_dv_counter_allocate(struct rte_eth_dev *dev)
9012 flow_dv_shared_lock(dev);
9013 cnt = flow_dv_counter_alloc(dev, 0, 0, 1);
9014 flow_dv_shared_unlock(dev);
9019 * Mutex-protected thunk to lock-free flow_dv_counter_release().
9022 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t cnt)
9024 flow_dv_shared_lock(dev);
9025 flow_dv_counter_release(dev, cnt);
9026 flow_dv_shared_unlock(dev);
9029 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
9030 .validate = flow_dv_validate,
9031 .prepare = flow_dv_prepare,
9032 .translate = flow_dv_translate,
9033 .apply = flow_dv_apply,
9034 .remove = flow_dv_remove,
9035 .destroy = flow_dv_destroy,
9036 .query = flow_dv_query,
9037 .create_mtr_tbls = flow_dv_create_mtr_tbl,
9038 .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
9039 .create_policer_rules = flow_dv_create_policer_rules,
9040 .destroy_policer_rules = flow_dv_destroy_policer_rules,
9041 .counter_alloc = flow_dv_counter_allocate,
9042 .counter_free = flow_dv_counter_free,
9043 .counter_query = flow_dv_counter_query,
9046 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */