net/mlx5: add internal tag item and action
[dpdk.git] / drivers / net / mlx5 / mlx5_flow_dv.c
1 /* SPDX-License-Identifier: BSD-3-Clause
2  * Copyright 2018 Mellanox Technologies, Ltd
3  */
4
5 #include <sys/queue.h>
6 #include <stdalign.h>
7 #include <stdint.h>
8 #include <string.h>
9 #include <unistd.h>
10
11 /* Verbs header. */
12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
13 #ifdef PEDANTIC
14 #pragma GCC diagnostic ignored "-Wpedantic"
15 #endif
16 #include <infiniband/verbs.h>
17 #ifdef PEDANTIC
18 #pragma GCC diagnostic error "-Wpedantic"
19 #endif
20
21 #include <rte_common.h>
22 #include <rte_ether.h>
23 #include <rte_ethdev_driver.h>
24 #include <rte_flow.h>
25 #include <rte_flow_driver.h>
26 #include <rte_malloc.h>
27 #include <rte_ip.h>
28 #include <rte_gre.h>
29 #include <rte_vxlan.h>
30
31 #include "mlx5.h"
32 #include "mlx5_defs.h"
33 #include "mlx5_glue.h"
34 #include "mlx5_flow.h"
35 #include "mlx5_prm.h"
36 #include "mlx5_rxtx.h"
37
38 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
39
40 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
41 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
42 #endif
43
44 #ifndef HAVE_MLX5DV_DR_ESWITCH
45 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
46 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
47 #endif
48 #endif
49
50 #ifndef HAVE_MLX5DV_DR
51 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
52 #endif
53
54 /* VLAN header definitions */
55 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
56 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
57 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
58 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
59 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
60
61 union flow_dv_attr {
62         struct {
63                 uint32_t valid:1;
64                 uint32_t ipv4:1;
65                 uint32_t ipv6:1;
66                 uint32_t tcp:1;
67                 uint32_t udp:1;
68                 uint32_t reserved:27;
69         };
70         uint32_t attr;
71 };
72
73 /**
74  * Initialize flow attributes structure according to flow items' types.
75  *
76  * @param[in] item
77  *   Pointer to item specification.
78  * @param[out] attr
79  *   Pointer to flow attributes structure.
80  */
81 static void
82 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr)
83 {
84         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
85                 switch (item->type) {
86                 case RTE_FLOW_ITEM_TYPE_IPV4:
87                         attr->ipv4 = 1;
88                         break;
89                 case RTE_FLOW_ITEM_TYPE_IPV6:
90                         attr->ipv6 = 1;
91                         break;
92                 case RTE_FLOW_ITEM_TYPE_UDP:
93                         attr->udp = 1;
94                         break;
95                 case RTE_FLOW_ITEM_TYPE_TCP:
96                         attr->tcp = 1;
97                         break;
98                 default:
99                         break;
100                 }
101         }
102         attr->valid = 1;
103 }
104
105 struct field_modify_info {
106         uint32_t size; /* Size of field in protocol header, in bytes. */
107         uint32_t offset; /* Offset of field in protocol header, in bytes. */
108         enum mlx5_modification_field id;
109 };
110
111 struct field_modify_info modify_eth[] = {
112         {4,  0, MLX5_MODI_OUT_DMAC_47_16},
113         {2,  4, MLX5_MODI_OUT_DMAC_15_0},
114         {4,  6, MLX5_MODI_OUT_SMAC_47_16},
115         {2, 10, MLX5_MODI_OUT_SMAC_15_0},
116         {0, 0, 0},
117 };
118
119 struct field_modify_info modify_vlan_out_first_vid[] = {
120         /* Size in bits !!! */
121         {12, 0, MLX5_MODI_OUT_FIRST_VID},
122         {0, 0, 0},
123 };
124
125 struct field_modify_info modify_ipv4[] = {
126         {1,  8, MLX5_MODI_OUT_IPV4_TTL},
127         {4, 12, MLX5_MODI_OUT_SIPV4},
128         {4, 16, MLX5_MODI_OUT_DIPV4},
129         {0, 0, 0},
130 };
131
132 struct field_modify_info modify_ipv6[] = {
133         {1,  7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
134         {4,  8, MLX5_MODI_OUT_SIPV6_127_96},
135         {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
136         {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
137         {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
138         {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
139         {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
140         {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
141         {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
142         {0, 0, 0},
143 };
144
145 struct field_modify_info modify_udp[] = {
146         {2, 0, MLX5_MODI_OUT_UDP_SPORT},
147         {2, 2, MLX5_MODI_OUT_UDP_DPORT},
148         {0, 0, 0},
149 };
150
151 struct field_modify_info modify_tcp[] = {
152         {2, 0, MLX5_MODI_OUT_TCP_SPORT},
153         {2, 2, MLX5_MODI_OUT_TCP_DPORT},
154         {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
155         {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
156         {0, 0, 0},
157 };
158
159 static void
160 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
161                           uint8_t next_protocol, uint64_t *item_flags,
162                           int *tunnel)
163 {
164         assert(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
165                item->type == RTE_FLOW_ITEM_TYPE_IPV6);
166         if (next_protocol == IPPROTO_IPIP) {
167                 *item_flags |= MLX5_FLOW_LAYER_IPIP;
168                 *tunnel = 1;
169         }
170         if (next_protocol == IPPROTO_IPV6) {
171                 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
172                 *tunnel = 1;
173         }
174 }
175
176 /**
177  * Acquire the synchronizing object to protect multithreaded access
178  * to shared dv context. Lock occurs only if context is actually
179  * shared, i.e. we have multiport IB device and representors are
180  * created.
181  *
182  * @param[in] dev
183  *   Pointer to the rte_eth_dev structure.
184  */
185 static void
186 flow_d_shared_lock(struct rte_eth_dev *dev)
187 {
188         struct mlx5_priv *priv = dev->data->dev_private;
189         struct mlx5_ibv_shared *sh = priv->sh;
190
191         if (sh->dv_refcnt > 1) {
192                 int ret;
193
194                 ret = pthread_mutex_lock(&sh->dv_mutex);
195                 assert(!ret);
196                 (void)ret;
197         }
198 }
199
200 static void
201 flow_d_shared_unlock(struct rte_eth_dev *dev)
202 {
203         struct mlx5_priv *priv = dev->data->dev_private;
204         struct mlx5_ibv_shared *sh = priv->sh;
205
206         if (sh->dv_refcnt > 1) {
207                 int ret;
208
209                 ret = pthread_mutex_unlock(&sh->dv_mutex);
210                 assert(!ret);
211                 (void)ret;
212         }
213 }
214
215 /**
216  * Convert modify-header action to DV specification.
217  *
218  * @param[in] item
219  *   Pointer to item specification.
220  * @param[in] field
221  *   Pointer to field modification information.
222  * @param[in,out] resource
223  *   Pointer to the modify-header resource.
224  * @param[in] type
225  *   Type of modification.
226  * @param[out] error
227  *   Pointer to the error structure.
228  *
229  * @return
230  *   0 on success, a negative errno value otherwise and rte_errno is set.
231  */
232 static int
233 flow_dv_convert_modify_action(struct rte_flow_item *item,
234                               struct field_modify_info *field,
235                               struct mlx5_flow_dv_modify_hdr_resource *resource,
236                               uint32_t type,
237                               struct rte_flow_error *error)
238 {
239         uint32_t i = resource->actions_num;
240         struct mlx5_modification_cmd *actions = resource->actions;
241         const uint8_t *spec = item->spec;
242         const uint8_t *mask = item->mask;
243         uint32_t set;
244
245         while (field->size) {
246                 set = 0;
247                 /* Generate modify command for each mask segment. */
248                 memcpy(&set, &mask[field->offset], field->size);
249                 if (set) {
250                         if (i >= MLX5_MODIFY_NUM)
251                                 return rte_flow_error_set(error, EINVAL,
252                                          RTE_FLOW_ERROR_TYPE_ACTION, NULL,
253                                          "too many items to modify");
254                         actions[i].action_type = type;
255                         actions[i].field = field->id;
256                         actions[i].length = field->size ==
257                                         4 ? 0 : field->size * 8;
258                         rte_memcpy(&actions[i].data[4 - field->size],
259                                    &spec[field->offset], field->size);
260                         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
261                         ++i;
262                 }
263                 if (resource->actions_num != i)
264                         resource->actions_num = i;
265                 field++;
266         }
267         if (!resource->actions_num)
268                 return rte_flow_error_set(error, EINVAL,
269                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
270                                           "invalid modification flow item");
271         return 0;
272 }
273
274 /**
275  * Convert modify-header set IPv4 address action to DV specification.
276  *
277  * @param[in,out] resource
278  *   Pointer to the modify-header resource.
279  * @param[in] action
280  *   Pointer to action specification.
281  * @param[out] error
282  *   Pointer to the error structure.
283  *
284  * @return
285  *   0 on success, a negative errno value otherwise and rte_errno is set.
286  */
287 static int
288 flow_dv_convert_action_modify_ipv4
289                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
290                          const struct rte_flow_action *action,
291                          struct rte_flow_error *error)
292 {
293         const struct rte_flow_action_set_ipv4 *conf =
294                 (const struct rte_flow_action_set_ipv4 *)(action->conf);
295         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
296         struct rte_flow_item_ipv4 ipv4;
297         struct rte_flow_item_ipv4 ipv4_mask;
298
299         memset(&ipv4, 0, sizeof(ipv4));
300         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
301         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
302                 ipv4.hdr.src_addr = conf->ipv4_addr;
303                 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
304         } else {
305                 ipv4.hdr.dst_addr = conf->ipv4_addr;
306                 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
307         }
308         item.spec = &ipv4;
309         item.mask = &ipv4_mask;
310         return flow_dv_convert_modify_action(&item, modify_ipv4, resource,
311                                              MLX5_MODIFICATION_TYPE_SET, error);
312 }
313
314 /**
315  * Convert modify-header set IPv6 address action to DV specification.
316  *
317  * @param[in,out] resource
318  *   Pointer to the modify-header resource.
319  * @param[in] action
320  *   Pointer to action specification.
321  * @param[out] error
322  *   Pointer to the error structure.
323  *
324  * @return
325  *   0 on success, a negative errno value otherwise and rte_errno is set.
326  */
327 static int
328 flow_dv_convert_action_modify_ipv6
329                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
330                          const struct rte_flow_action *action,
331                          struct rte_flow_error *error)
332 {
333         const struct rte_flow_action_set_ipv6 *conf =
334                 (const struct rte_flow_action_set_ipv6 *)(action->conf);
335         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
336         struct rte_flow_item_ipv6 ipv6;
337         struct rte_flow_item_ipv6 ipv6_mask;
338
339         memset(&ipv6, 0, sizeof(ipv6));
340         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
341         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
342                 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
343                        sizeof(ipv6.hdr.src_addr));
344                 memcpy(&ipv6_mask.hdr.src_addr,
345                        &rte_flow_item_ipv6_mask.hdr.src_addr,
346                        sizeof(ipv6.hdr.src_addr));
347         } else {
348                 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
349                        sizeof(ipv6.hdr.dst_addr));
350                 memcpy(&ipv6_mask.hdr.dst_addr,
351                        &rte_flow_item_ipv6_mask.hdr.dst_addr,
352                        sizeof(ipv6.hdr.dst_addr));
353         }
354         item.spec = &ipv6;
355         item.mask = &ipv6_mask;
356         return flow_dv_convert_modify_action(&item, modify_ipv6, resource,
357                                              MLX5_MODIFICATION_TYPE_SET, error);
358 }
359
360 /**
361  * Convert modify-header set MAC address action to DV specification.
362  *
363  * @param[in,out] resource
364  *   Pointer to the modify-header resource.
365  * @param[in] action
366  *   Pointer to action specification.
367  * @param[out] error
368  *   Pointer to the error structure.
369  *
370  * @return
371  *   0 on success, a negative errno value otherwise and rte_errno is set.
372  */
373 static int
374 flow_dv_convert_action_modify_mac
375                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
376                          const struct rte_flow_action *action,
377                          struct rte_flow_error *error)
378 {
379         const struct rte_flow_action_set_mac *conf =
380                 (const struct rte_flow_action_set_mac *)(action->conf);
381         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
382         struct rte_flow_item_eth eth;
383         struct rte_flow_item_eth eth_mask;
384
385         memset(&eth, 0, sizeof(eth));
386         memset(&eth_mask, 0, sizeof(eth_mask));
387         if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
388                 memcpy(&eth.src.addr_bytes, &conf->mac_addr,
389                        sizeof(eth.src.addr_bytes));
390                 memcpy(&eth_mask.src.addr_bytes,
391                        &rte_flow_item_eth_mask.src.addr_bytes,
392                        sizeof(eth_mask.src.addr_bytes));
393         } else {
394                 memcpy(&eth.dst.addr_bytes, &conf->mac_addr,
395                        sizeof(eth.dst.addr_bytes));
396                 memcpy(&eth_mask.dst.addr_bytes,
397                        &rte_flow_item_eth_mask.dst.addr_bytes,
398                        sizeof(eth_mask.dst.addr_bytes));
399         }
400         item.spec = &eth;
401         item.mask = &eth_mask;
402         return flow_dv_convert_modify_action(&item, modify_eth, resource,
403                                              MLX5_MODIFICATION_TYPE_SET, error);
404 }
405
406 /**
407  * Convert modify-header set VLAN VID action to DV specification.
408  *
409  * @param[in,out] resource
410  *   Pointer to the modify-header resource.
411  * @param[in] action
412  *   Pointer to action specification.
413  * @param[out] error
414  *   Pointer to the error structure.
415  *
416  * @return
417  *   0 on success, a negative errno value otherwise and rte_errno is set.
418  */
419 static int
420 flow_dv_convert_action_modify_vlan_vid
421                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
422                          const struct rte_flow_action *action,
423                          struct rte_flow_error *error)
424 {
425         const struct rte_flow_action_of_set_vlan_vid *conf =
426                 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
427         int i = resource->actions_num;
428         struct mlx5_modification_cmd *actions = &resource->actions[i];
429         struct field_modify_info *field = modify_vlan_out_first_vid;
430
431         if (i >= MLX5_MODIFY_NUM)
432                 return rte_flow_error_set(error, EINVAL,
433                          RTE_FLOW_ERROR_TYPE_ACTION, NULL,
434                          "too many items to modify");
435         actions[i].action_type = MLX5_MODIFICATION_TYPE_SET;
436         actions[i].field = field->id;
437         actions[i].length = field->size;
438         actions[i].offset = field->offset;
439         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
440         actions[i].data1 = conf->vlan_vid;
441         actions[i].data1 = actions[i].data1 << 16;
442         resource->actions_num = ++i;
443         return 0;
444 }
445
446 /**
447  * Convert modify-header set TP action to DV specification.
448  *
449  * @param[in,out] resource
450  *   Pointer to the modify-header resource.
451  * @param[in] action
452  *   Pointer to action specification.
453  * @param[in] items
454  *   Pointer to rte_flow_item objects list.
455  * @param[in] attr
456  *   Pointer to flow attributes structure.
457  * @param[out] error
458  *   Pointer to the error structure.
459  *
460  * @return
461  *   0 on success, a negative errno value otherwise and rte_errno is set.
462  */
463 static int
464 flow_dv_convert_action_modify_tp
465                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
466                          const struct rte_flow_action *action,
467                          const struct rte_flow_item *items,
468                          union flow_dv_attr *attr,
469                          struct rte_flow_error *error)
470 {
471         const struct rte_flow_action_set_tp *conf =
472                 (const struct rte_flow_action_set_tp *)(action->conf);
473         struct rte_flow_item item;
474         struct rte_flow_item_udp udp;
475         struct rte_flow_item_udp udp_mask;
476         struct rte_flow_item_tcp tcp;
477         struct rte_flow_item_tcp tcp_mask;
478         struct field_modify_info *field;
479
480         if (!attr->valid)
481                 flow_dv_attr_init(items, attr);
482         if (attr->udp) {
483                 memset(&udp, 0, sizeof(udp));
484                 memset(&udp_mask, 0, sizeof(udp_mask));
485                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
486                         udp.hdr.src_port = conf->port;
487                         udp_mask.hdr.src_port =
488                                         rte_flow_item_udp_mask.hdr.src_port;
489                 } else {
490                         udp.hdr.dst_port = conf->port;
491                         udp_mask.hdr.dst_port =
492                                         rte_flow_item_udp_mask.hdr.dst_port;
493                 }
494                 item.type = RTE_FLOW_ITEM_TYPE_UDP;
495                 item.spec = &udp;
496                 item.mask = &udp_mask;
497                 field = modify_udp;
498         }
499         if (attr->tcp) {
500                 memset(&tcp, 0, sizeof(tcp));
501                 memset(&tcp_mask, 0, sizeof(tcp_mask));
502                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
503                         tcp.hdr.src_port = conf->port;
504                         tcp_mask.hdr.src_port =
505                                         rte_flow_item_tcp_mask.hdr.src_port;
506                 } else {
507                         tcp.hdr.dst_port = conf->port;
508                         tcp_mask.hdr.dst_port =
509                                         rte_flow_item_tcp_mask.hdr.dst_port;
510                 }
511                 item.type = RTE_FLOW_ITEM_TYPE_TCP;
512                 item.spec = &tcp;
513                 item.mask = &tcp_mask;
514                 field = modify_tcp;
515         }
516         return flow_dv_convert_modify_action(&item, field, resource,
517                                              MLX5_MODIFICATION_TYPE_SET, error);
518 }
519
520 /**
521  * Convert modify-header set TTL action to DV specification.
522  *
523  * @param[in,out] resource
524  *   Pointer to the modify-header resource.
525  * @param[in] action
526  *   Pointer to action specification.
527  * @param[in] items
528  *   Pointer to rte_flow_item objects list.
529  * @param[in] attr
530  *   Pointer to flow attributes structure.
531  * @param[out] error
532  *   Pointer to the error structure.
533  *
534  * @return
535  *   0 on success, a negative errno value otherwise and rte_errno is set.
536  */
537 static int
538 flow_dv_convert_action_modify_ttl
539                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
540                          const struct rte_flow_action *action,
541                          const struct rte_flow_item *items,
542                          union flow_dv_attr *attr,
543                          struct rte_flow_error *error)
544 {
545         const struct rte_flow_action_set_ttl *conf =
546                 (const struct rte_flow_action_set_ttl *)(action->conf);
547         struct rte_flow_item item;
548         struct rte_flow_item_ipv4 ipv4;
549         struct rte_flow_item_ipv4 ipv4_mask;
550         struct rte_flow_item_ipv6 ipv6;
551         struct rte_flow_item_ipv6 ipv6_mask;
552         struct field_modify_info *field;
553
554         if (!attr->valid)
555                 flow_dv_attr_init(items, attr);
556         if (attr->ipv4) {
557                 memset(&ipv4, 0, sizeof(ipv4));
558                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
559                 ipv4.hdr.time_to_live = conf->ttl_value;
560                 ipv4_mask.hdr.time_to_live = 0xFF;
561                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
562                 item.spec = &ipv4;
563                 item.mask = &ipv4_mask;
564                 field = modify_ipv4;
565         }
566         if (attr->ipv6) {
567                 memset(&ipv6, 0, sizeof(ipv6));
568                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
569                 ipv6.hdr.hop_limits = conf->ttl_value;
570                 ipv6_mask.hdr.hop_limits = 0xFF;
571                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
572                 item.spec = &ipv6;
573                 item.mask = &ipv6_mask;
574                 field = modify_ipv6;
575         }
576         return flow_dv_convert_modify_action(&item, field, resource,
577                                              MLX5_MODIFICATION_TYPE_SET, error);
578 }
579
580 /**
581  * Convert modify-header decrement TTL action to DV specification.
582  *
583  * @param[in,out] resource
584  *   Pointer to the modify-header resource.
585  * @param[in] action
586  *   Pointer to action specification.
587  * @param[in] items
588  *   Pointer to rte_flow_item objects list.
589  * @param[in] attr
590  *   Pointer to flow attributes structure.
591  * @param[out] error
592  *   Pointer to the error structure.
593  *
594  * @return
595  *   0 on success, a negative errno value otherwise and rte_errno is set.
596  */
597 static int
598 flow_dv_convert_action_modify_dec_ttl
599                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
600                          const struct rte_flow_item *items,
601                          union flow_dv_attr *attr,
602                          struct rte_flow_error *error)
603 {
604         struct rte_flow_item item;
605         struct rte_flow_item_ipv4 ipv4;
606         struct rte_flow_item_ipv4 ipv4_mask;
607         struct rte_flow_item_ipv6 ipv6;
608         struct rte_flow_item_ipv6 ipv6_mask;
609         struct field_modify_info *field;
610
611         if (!attr->valid)
612                 flow_dv_attr_init(items, attr);
613         if (attr->ipv4) {
614                 memset(&ipv4, 0, sizeof(ipv4));
615                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
616                 ipv4.hdr.time_to_live = 0xFF;
617                 ipv4_mask.hdr.time_to_live = 0xFF;
618                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
619                 item.spec = &ipv4;
620                 item.mask = &ipv4_mask;
621                 field = modify_ipv4;
622         }
623         if (attr->ipv6) {
624                 memset(&ipv6, 0, sizeof(ipv6));
625                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
626                 ipv6.hdr.hop_limits = 0xFF;
627                 ipv6_mask.hdr.hop_limits = 0xFF;
628                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
629                 item.spec = &ipv6;
630                 item.mask = &ipv6_mask;
631                 field = modify_ipv6;
632         }
633         return flow_dv_convert_modify_action(&item, field, resource,
634                                              MLX5_MODIFICATION_TYPE_ADD, error);
635 }
636
637 /**
638  * Convert modify-header increment/decrement TCP Sequence number
639  * to DV specification.
640  *
641  * @param[in,out] resource
642  *   Pointer to the modify-header resource.
643  * @param[in] action
644  *   Pointer to action specification.
645  * @param[out] error
646  *   Pointer to the error structure.
647  *
648  * @return
649  *   0 on success, a negative errno value otherwise and rte_errno is set.
650  */
651 static int
652 flow_dv_convert_action_modify_tcp_seq
653                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
654                          const struct rte_flow_action *action,
655                          struct rte_flow_error *error)
656 {
657         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
658         uint64_t value = rte_be_to_cpu_32(*conf);
659         struct rte_flow_item item;
660         struct rte_flow_item_tcp tcp;
661         struct rte_flow_item_tcp tcp_mask;
662
663         memset(&tcp, 0, sizeof(tcp));
664         memset(&tcp_mask, 0, sizeof(tcp_mask));
665         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
666                 /*
667                  * The HW has no decrement operation, only increment operation.
668                  * To simulate decrement X from Y using increment operation
669                  * we need to add UINT32_MAX X times to Y.
670                  * Each adding of UINT32_MAX decrements Y by 1.
671                  */
672                 value *= UINT32_MAX;
673         tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
674         tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
675         item.type = RTE_FLOW_ITEM_TYPE_TCP;
676         item.spec = &tcp;
677         item.mask = &tcp_mask;
678         return flow_dv_convert_modify_action(&item, modify_tcp, resource,
679                                              MLX5_MODIFICATION_TYPE_ADD, error);
680 }
681
682 /**
683  * Convert modify-header increment/decrement TCP Acknowledgment number
684  * to DV specification.
685  *
686  * @param[in,out] resource
687  *   Pointer to the modify-header resource.
688  * @param[in] action
689  *   Pointer to action specification.
690  * @param[out] error
691  *   Pointer to the error structure.
692  *
693  * @return
694  *   0 on success, a negative errno value otherwise and rte_errno is set.
695  */
696 static int
697 flow_dv_convert_action_modify_tcp_ack
698                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
699                          const struct rte_flow_action *action,
700                          struct rte_flow_error *error)
701 {
702         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
703         uint64_t value = rte_be_to_cpu_32(*conf);
704         struct rte_flow_item item;
705         struct rte_flow_item_tcp tcp;
706         struct rte_flow_item_tcp tcp_mask;
707
708         memset(&tcp, 0, sizeof(tcp));
709         memset(&tcp_mask, 0, sizeof(tcp_mask));
710         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
711                 /*
712                  * The HW has no decrement operation, only increment operation.
713                  * To simulate decrement X from Y using increment operation
714                  * we need to add UINT32_MAX X times to Y.
715                  * Each adding of UINT32_MAX decrements Y by 1.
716                  */
717                 value *= UINT32_MAX;
718         tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
719         tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
720         item.type = RTE_FLOW_ITEM_TYPE_TCP;
721         item.spec = &tcp;
722         item.mask = &tcp_mask;
723         return flow_dv_convert_modify_action(&item, modify_tcp, resource,
724                                              MLX5_MODIFICATION_TYPE_ADD, error);
725 }
726
727 static enum mlx5_modification_field reg_to_field[] = {
728         [REG_A] = MLX5_MODI_META_DATA_REG_A,
729         [REG_B] = MLX5_MODI_META_DATA_REG_B,
730         [REG_C_0] = MLX5_MODI_META_REG_C_0,
731         [REG_C_1] = MLX5_MODI_META_REG_C_1,
732         [REG_C_2] = MLX5_MODI_META_REG_C_2,
733         [REG_C_3] = MLX5_MODI_META_REG_C_3,
734         [REG_C_4] = MLX5_MODI_META_REG_C_4,
735         [REG_C_5] = MLX5_MODI_META_REG_C_5,
736         [REG_C_6] = MLX5_MODI_META_REG_C_6,
737         [REG_C_7] = MLX5_MODI_META_REG_C_7,
738 };
739
740 /**
741  * Convert register set to DV specification.
742  *
743  * @param[in,out] resource
744  *   Pointer to the modify-header resource.
745  * @param[in] action
746  *   Pointer to action specification.
747  * @param[out] error
748  *   Pointer to the error structure.
749  *
750  * @return
751  *   0 on success, a negative errno value otherwise and rte_errno is set.
752  */
753 static int
754 flow_dv_convert_action_set_reg
755                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
756                          const struct rte_flow_action *action,
757                          struct rte_flow_error *error)
758 {
759         const struct mlx5_rte_flow_action_set_tag *conf = (action->conf);
760         struct mlx5_modification_cmd *actions = resource->actions;
761         uint32_t i = resource->actions_num;
762
763         if (i >= MLX5_MODIFY_NUM)
764                 return rte_flow_error_set(error, EINVAL,
765                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
766                                           "too many items to modify");
767         actions[i].action_type = MLX5_MODIFICATION_TYPE_SET;
768         actions[i].field = reg_to_field[conf->id];
769         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
770         actions[i].data1 = conf->data;
771         ++i;
772         resource->actions_num = i;
773         if (!resource->actions_num)
774                 return rte_flow_error_set(error, EINVAL,
775                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
776                                           "invalid modification flow item");
777         return 0;
778 }
779
780 /**
781  * Validate META item.
782  *
783  * @param[in] dev
784  *   Pointer to the rte_eth_dev structure.
785  * @param[in] item
786  *   Item specification.
787  * @param[in] attr
788  *   Attributes of flow that includes this item.
789  * @param[out] error
790  *   Pointer to error structure.
791  *
792  * @return
793  *   0 on success, a negative errno value otherwise and rte_errno is set.
794  */
795 static int
796 flow_dv_validate_item_meta(struct rte_eth_dev *dev,
797                            const struct rte_flow_item *item,
798                            const struct rte_flow_attr *attr,
799                            struct rte_flow_error *error)
800 {
801         const struct rte_flow_item_meta *spec = item->spec;
802         const struct rte_flow_item_meta *mask = item->mask;
803         const struct rte_flow_item_meta nic_mask = {
804                 .data = RTE_BE32(UINT32_MAX)
805         };
806         int ret;
807         uint64_t offloads = dev->data->dev_conf.txmode.offloads;
808
809         if (!(offloads & DEV_TX_OFFLOAD_MATCH_METADATA))
810                 return rte_flow_error_set(error, EPERM,
811                                           RTE_FLOW_ERROR_TYPE_ITEM,
812                                           NULL,
813                                           "match on metadata offload "
814                                           "configuration is off for this port");
815         if (!spec)
816                 return rte_flow_error_set(error, EINVAL,
817                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
818                                           item->spec,
819                                           "data cannot be empty");
820         if (!spec->data)
821                 return rte_flow_error_set(error, EINVAL,
822                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
823                                           NULL,
824                                           "data cannot be zero");
825         if (!mask)
826                 mask = &rte_flow_item_meta_mask;
827         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
828                                         (const uint8_t *)&nic_mask,
829                                         sizeof(struct rte_flow_item_meta),
830                                         error);
831         if (ret < 0)
832                 return ret;
833         if (attr->ingress)
834                 return rte_flow_error_set(error, ENOTSUP,
835                                           RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
836                                           NULL,
837                                           "pattern not supported for ingress");
838         return 0;
839 }
840
841 /**
842  * Validate vport item.
843  *
844  * @param[in] dev
845  *   Pointer to the rte_eth_dev structure.
846  * @param[in] item
847  *   Item specification.
848  * @param[in] attr
849  *   Attributes of flow that includes this item.
850  * @param[in] item_flags
851  *   Bit-fields that holds the items detected until now.
852  * @param[out] error
853  *   Pointer to error structure.
854  *
855  * @return
856  *   0 on success, a negative errno value otherwise and rte_errno is set.
857  */
858 static int
859 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
860                               const struct rte_flow_item *item,
861                               const struct rte_flow_attr *attr,
862                               uint64_t item_flags,
863                               struct rte_flow_error *error)
864 {
865         const struct rte_flow_item_port_id *spec = item->spec;
866         const struct rte_flow_item_port_id *mask = item->mask;
867         const struct rte_flow_item_port_id switch_mask = {
868                         .id = 0xffffffff,
869         };
870         struct mlx5_priv *esw_priv;
871         struct mlx5_priv *dev_priv;
872         int ret;
873
874         if (!attr->transfer)
875                 return rte_flow_error_set(error, EINVAL,
876                                           RTE_FLOW_ERROR_TYPE_ITEM,
877                                           NULL,
878                                           "match on port id is valid only"
879                                           " when transfer flag is enabled");
880         if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
881                 return rte_flow_error_set(error, ENOTSUP,
882                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
883                                           "multiple source ports are not"
884                                           " supported");
885         if (!mask)
886                 mask = &switch_mask;
887         if (mask->id != 0xffffffff)
888                 return rte_flow_error_set(error, ENOTSUP,
889                                            RTE_FLOW_ERROR_TYPE_ITEM_MASK,
890                                            mask,
891                                            "no support for partial mask on"
892                                            " \"id\" field");
893         ret = mlx5_flow_item_acceptable
894                                 (item, (const uint8_t *)mask,
895                                  (const uint8_t *)&rte_flow_item_port_id_mask,
896                                  sizeof(struct rte_flow_item_port_id),
897                                  error);
898         if (ret)
899                 return ret;
900         if (!spec)
901                 return 0;
902         esw_priv = mlx5_port_to_eswitch_info(spec->id);
903         if (!esw_priv)
904                 return rte_flow_error_set(error, rte_errno,
905                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
906                                           "failed to obtain E-Switch info for"
907                                           " port");
908         dev_priv = mlx5_dev_to_eswitch_info(dev);
909         if (!dev_priv)
910                 return rte_flow_error_set(error, rte_errno,
911                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
912                                           NULL,
913                                           "failed to obtain E-Switch info");
914         if (esw_priv->domain_id != dev_priv->domain_id)
915                 return rte_flow_error_set(error, EINVAL,
916                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
917                                           "cannot match on a port from a"
918                                           " different E-Switch");
919         return 0;
920 }
921
922 /**
923  * Validate the pop VLAN action.
924  *
925  * @param[in] dev
926  *   Pointer to the rte_eth_dev structure.
927  * @param[in] action_flags
928  *   Holds the actions detected until now.
929  * @param[in] action
930  *   Pointer to the pop vlan action.
931  * @param[in] item_flags
932  *   The items found in this flow rule.
933  * @param[in] attr
934  *   Pointer to flow attributes.
935  * @param[out] error
936  *   Pointer to error structure.
937  *
938  * @return
939  *   0 on success, a negative errno value otherwise and rte_errno is set.
940  */
941 static int
942 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
943                                  uint64_t action_flags,
944                                  const struct rte_flow_action *action,
945                                  uint64_t item_flags,
946                                  const struct rte_flow_attr *attr,
947                                  struct rte_flow_error *error)
948 {
949         struct mlx5_priv *priv = dev->data->dev_private;
950
951         (void)action;
952         (void)attr;
953         if (!priv->sh->pop_vlan_action)
954                 return rte_flow_error_set(error, ENOTSUP,
955                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
956                                           NULL,
957                                           "pop vlan action is not supported");
958         /*
959          * Check for inconsistencies:
960          *  fail strip_vlan in a flow that matches packets without VLAN tags.
961          *  fail strip_vlan in a flow that matches packets without explicitly a
962          *  matching on VLAN tag ?
963          */
964         if (action_flags & MLX5_FLOW_ACTION_OF_POP_VLAN)
965                 return rte_flow_error_set(error, ENOTSUP,
966                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
967                                           NULL,
968                                           "no support for multiple vlan pop "
969                                           "actions");
970         if (!(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
971                 return rte_flow_error_set(error, ENOTSUP,
972                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
973                                           NULL,
974                                           "cannot pop vlan without a "
975                                           "match on (outer) vlan in the flow");
976         return 0;
977 }
978
979 /**
980  * Get VLAN default info from vlan match info.
981  *
982  * @param[in] dev
983  *   Pointer to the rte_eth_dev structure.
984  * @param[in] item
985  *   the list of item specifications.
986  * @param[out] vlan
987  *   pointer VLAN info to fill to.
988  * @param[out] error
989  *   Pointer to error structure.
990  *
991  * @return
992  *   0 on success, a negative errno value otherwise and rte_errno is set.
993  */
994 static void
995 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
996                                   struct rte_vlan_hdr *vlan)
997 {
998         const struct rte_flow_item_vlan nic_mask = {
999                 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
1000                                 MLX5DV_FLOW_VLAN_VID_MASK),
1001                 .inner_type = RTE_BE16(0xffff),
1002         };
1003
1004         if (items == NULL)
1005                 return;
1006         for (; items->type != RTE_FLOW_ITEM_TYPE_END &&
1007                items->type != RTE_FLOW_ITEM_TYPE_VLAN; items++)
1008                 ;
1009         if (items->type == RTE_FLOW_ITEM_TYPE_VLAN) {
1010                 const struct rte_flow_item_vlan *vlan_m = items->mask;
1011                 const struct rte_flow_item_vlan *vlan_v = items->spec;
1012
1013                 if (!vlan_m)
1014                         vlan_m = &nic_mask;
1015                 /* Only full match values are accepted */
1016                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
1017                      MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
1018                         vlan->vlan_tci &= MLX5DV_FLOW_VLAN_PCP_MASK;
1019                         vlan->vlan_tci |=
1020                                 rte_be_to_cpu_16(vlan_v->tci &
1021                                                  MLX5DV_FLOW_VLAN_PCP_MASK_BE);
1022                 }
1023                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
1024                      MLX5DV_FLOW_VLAN_VID_MASK_BE) {
1025                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
1026                         vlan->vlan_tci |=
1027                                 rte_be_to_cpu_16(vlan_v->tci &
1028                                                  MLX5DV_FLOW_VLAN_VID_MASK_BE);
1029                 }
1030                 if (vlan_m->inner_type == nic_mask.inner_type)
1031                         vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
1032                                                            vlan_m->inner_type);
1033         }
1034 }
1035
1036 /**
1037  * Validate the push VLAN action.
1038  *
1039  * @param[in] action_flags
1040  *   Holds the actions detected until now.
1041  * @param[in] action
1042  *   Pointer to the encap action.
1043  * @param[in] attr
1044  *   Pointer to flow attributes
1045  * @param[out] error
1046  *   Pointer to error structure.
1047  *
1048  * @return
1049  *   0 on success, a negative errno value otherwise and rte_errno is set.
1050  */
1051 static int
1052 flow_dv_validate_action_push_vlan(uint64_t action_flags,
1053                                   const struct rte_flow_action *action,
1054                                   const struct rte_flow_attr *attr,
1055                                   struct rte_flow_error *error)
1056 {
1057         const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
1058
1059         if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
1060             push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
1061                 return rte_flow_error_set(error, EINVAL,
1062                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1063                                           "invalid vlan ethertype");
1064         if (action_flags &
1065                 (MLX5_FLOW_ACTION_OF_POP_VLAN | MLX5_FLOW_ACTION_OF_PUSH_VLAN))
1066                 return rte_flow_error_set(error, ENOTSUP,
1067                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1068                                           "no support for multiple VLAN "
1069                                           "actions");
1070         (void)attr;
1071         return 0;
1072 }
1073
1074 /**
1075  * Validate the set VLAN PCP.
1076  *
1077  * @param[in] action_flags
1078  *   Holds the actions detected until now.
1079  * @param[in] actions
1080  *   Pointer to the list of actions remaining in the flow rule.
1081  * @param[in] attr
1082  *   Pointer to flow attributes
1083  * @param[out] error
1084  *   Pointer to error structure.
1085  *
1086  * @return
1087  *   0 on success, a negative errno value otherwise and rte_errno is set.
1088  */
1089 static int
1090 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
1091                                      const struct rte_flow_action actions[],
1092                                      struct rte_flow_error *error)
1093 {
1094         const struct rte_flow_action *action = actions;
1095         const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
1096
1097         if (conf->vlan_pcp > 7)
1098                 return rte_flow_error_set(error, EINVAL,
1099                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1100                                           "VLAN PCP value is too big");
1101         if (mlx5_flow_find_action(actions,
1102                                   RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN) == NULL)
1103                 return rte_flow_error_set(error, ENOTSUP,
1104                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1105                                           "set VLAN PCP can only be used "
1106                                           "with push VLAN action");
1107         if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
1108                 return rte_flow_error_set(error, ENOTSUP,
1109                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1110                                           "set VLAN PCP action must precede "
1111                                           "the push VLAN action");
1112         return 0;
1113 }
1114
1115 /**
1116  * Validate the set VLAN VID.
1117  *
1118  * @param[in] item_flags
1119  *   Holds the items detected in this rule.
1120  * @param[in] actions
1121  *   Pointer to the list of actions remaining in the flow rule.
1122  * @param[in] attr
1123  *   Pointer to flow attributes
1124  * @param[out] error
1125  *   Pointer to error structure.
1126  *
1127  * @return
1128  *   0 on success, a negative errno value otherwise and rte_errno is set.
1129  */
1130 static int
1131 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
1132                                      const struct rte_flow_action actions[],
1133                                      struct rte_flow_error *error)
1134 {
1135         const struct rte_flow_action *action = actions;
1136         const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
1137
1138         if (conf->vlan_vid > RTE_BE16(0xFFE))
1139                 return rte_flow_error_set(error, EINVAL,
1140                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1141                                           "VLAN VID value is too big");
1142         /* If a push VLAN action follows then it will handle this action */
1143         if (mlx5_flow_find_action(actions,
1144                                   RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN))
1145                 return 0;
1146
1147         /*
1148          * Action is on an existing VLAN header:
1149          *    Need to verify this is a single modify CID action.
1150          *   Rule mast include a match on outer VLAN.
1151          */
1152         if (mlx5_flow_find_action(++action,
1153                                   RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID))
1154                 return rte_flow_error_set(error, ENOTSUP,
1155                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1156                                           "Multiple VLAN VID modifications are "
1157                                           "not supported");
1158         if (!(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1159                 return rte_flow_error_set(error, EINVAL,
1160                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1161                                           "match on VLAN is required in order "
1162                                           "to set VLAN VID");
1163         return 0;
1164 }
1165
1166 /**
1167  * Validate count action.
1168  *
1169  * @param[in] dev
1170  *   device otr.
1171  * @param[out] error
1172  *   Pointer to error structure.
1173  *
1174  * @return
1175  *   0 on success, a negative errno value otherwise and rte_errno is set.
1176  */
1177 static int
1178 flow_dv_validate_action_count(struct rte_eth_dev *dev,
1179                               struct rte_flow_error *error)
1180 {
1181         struct mlx5_priv *priv = dev->data->dev_private;
1182
1183         if (!priv->config.devx)
1184                 goto notsup_err;
1185 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
1186         return 0;
1187 #endif
1188 notsup_err:
1189         return rte_flow_error_set
1190                       (error, ENOTSUP,
1191                        RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1192                        NULL,
1193                        "count action not supported");
1194 }
1195
1196 /**
1197  * Validate the L2 encap action.
1198  *
1199  * @param[in] action_flags
1200  *   Holds the actions detected until now.
1201  * @param[in] action
1202  *   Pointer to the encap action.
1203  * @param[in] attr
1204  *   Pointer to flow attributes
1205  * @param[out] error
1206  *   Pointer to error structure.
1207  *
1208  * @return
1209  *   0 on success, a negative errno value otherwise and rte_errno is set.
1210  */
1211 static int
1212 flow_dv_validate_action_l2_encap(uint64_t action_flags,
1213                                  const struct rte_flow_action *action,
1214                                  const struct rte_flow_attr *attr,
1215                                  struct rte_flow_error *error)
1216 {
1217         if (!(action->conf))
1218                 return rte_flow_error_set(error, EINVAL,
1219                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1220                                           "configuration cannot be null");
1221         if (action_flags & MLX5_FLOW_ACTION_DROP)
1222                 return rte_flow_error_set(error, EINVAL,
1223                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1224                                           "can't drop and encap in same flow");
1225         if (action_flags & (MLX5_FLOW_ENCAP_ACTIONS | MLX5_FLOW_DECAP_ACTIONS))
1226                 return rte_flow_error_set(error, EINVAL,
1227                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1228                                           "can only have a single encap or"
1229                                           " decap action in a flow");
1230         if (!attr->transfer && attr->ingress)
1231                 return rte_flow_error_set(error, ENOTSUP,
1232                                           RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1233                                           NULL,
1234                                           "encap action not supported for "
1235                                           "ingress");
1236         return 0;
1237 }
1238
1239 /**
1240  * Validate the L2 decap action.
1241  *
1242  * @param[in] action_flags
1243  *   Holds the actions detected until now.
1244  * @param[in] attr
1245  *   Pointer to flow attributes
1246  * @param[out] error
1247  *   Pointer to error structure.
1248  *
1249  * @return
1250  *   0 on success, a negative errno value otherwise and rte_errno is set.
1251  */
1252 static int
1253 flow_dv_validate_action_l2_decap(uint64_t action_flags,
1254                                  const struct rte_flow_attr *attr,
1255                                  struct rte_flow_error *error)
1256 {
1257         if (action_flags & MLX5_FLOW_ACTION_DROP)
1258                 return rte_flow_error_set(error, EINVAL,
1259                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1260                                           "can't drop and decap in same flow");
1261         if (action_flags & (MLX5_FLOW_ENCAP_ACTIONS | MLX5_FLOW_DECAP_ACTIONS))
1262                 return rte_flow_error_set(error, EINVAL,
1263                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1264                                           "can only have a single encap or"
1265                                           " decap action in a flow");
1266         if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
1267                 return rte_flow_error_set(error, EINVAL,
1268                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1269                                           "can't have decap action after"
1270                                           " modify action");
1271         if (attr->egress)
1272                 return rte_flow_error_set(error, ENOTSUP,
1273                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1274                                           NULL,
1275                                           "decap action not supported for "
1276                                           "egress");
1277         return 0;
1278 }
1279
1280 /**
1281  * Validate the raw encap action.
1282  *
1283  * @param[in] action_flags
1284  *   Holds the actions detected until now.
1285  * @param[in] action
1286  *   Pointer to the encap action.
1287  * @param[in] attr
1288  *   Pointer to flow attributes
1289  * @param[out] error
1290  *   Pointer to error structure.
1291  *
1292  * @return
1293  *   0 on success, a negative errno value otherwise and rte_errno is set.
1294  */
1295 static int
1296 flow_dv_validate_action_raw_encap(uint64_t action_flags,
1297                                   const struct rte_flow_action *action,
1298                                   const struct rte_flow_attr *attr,
1299                                   struct rte_flow_error *error)
1300 {
1301         const struct rte_flow_action_raw_encap *raw_encap =
1302                 (const struct rte_flow_action_raw_encap *)action->conf;
1303         if (!(action->conf))
1304                 return rte_flow_error_set(error, EINVAL,
1305                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1306                                           "configuration cannot be null");
1307         if (action_flags & MLX5_FLOW_ACTION_DROP)
1308                 return rte_flow_error_set(error, EINVAL,
1309                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1310                                           "can't drop and encap in same flow");
1311         if (action_flags & MLX5_FLOW_ENCAP_ACTIONS)
1312                 return rte_flow_error_set(error, EINVAL,
1313                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1314                                           "can only have a single encap"
1315                                           " action in a flow");
1316         /* encap without preceding decap is not supported for ingress */
1317         if (!attr->transfer &&  attr->ingress &&
1318             !(action_flags & MLX5_FLOW_ACTION_RAW_DECAP))
1319                 return rte_flow_error_set(error, ENOTSUP,
1320                                           RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1321                                           NULL,
1322                                           "encap action not supported for "
1323                                           "ingress");
1324         if (!raw_encap->size || !raw_encap->data)
1325                 return rte_flow_error_set(error, EINVAL,
1326                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1327                                           "raw encap data cannot be empty");
1328         return 0;
1329 }
1330
1331 /**
1332  * Validate the raw decap action.
1333  *
1334  * @param[in] action_flags
1335  *   Holds the actions detected until now.
1336  * @param[in] action
1337  *   Pointer to the encap action.
1338  * @param[in] attr
1339  *   Pointer to flow attributes
1340  * @param[out] error
1341  *   Pointer to error structure.
1342  *
1343  * @return
1344  *   0 on success, a negative errno value otherwise and rte_errno is set.
1345  */
1346 static int
1347 flow_dv_validate_action_raw_decap(uint64_t action_flags,
1348                                   const struct rte_flow_action *action,
1349                                   const struct rte_flow_attr *attr,
1350                                   struct rte_flow_error *error)
1351 {
1352         if (action_flags & MLX5_FLOW_ACTION_DROP)
1353                 return rte_flow_error_set(error, EINVAL,
1354                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1355                                           "can't drop and decap in same flow");
1356         if (action_flags & MLX5_FLOW_ENCAP_ACTIONS)
1357                 return rte_flow_error_set(error, EINVAL,
1358                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1359                                           "can't have encap action before"
1360                                           " decap action");
1361         if (action_flags & MLX5_FLOW_DECAP_ACTIONS)
1362                 return rte_flow_error_set(error, EINVAL,
1363                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1364                                           "can only have a single decap"
1365                                           " action in a flow");
1366         if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
1367                 return rte_flow_error_set(error, EINVAL,
1368                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1369                                           "can't have decap action after"
1370                                           " modify action");
1371         /* decap action is valid on egress only if it is followed by encap */
1372         if (attr->egress) {
1373                 for (; action->type != RTE_FLOW_ACTION_TYPE_END &&
1374                        action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP;
1375                        action++) {
1376                 }
1377                 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP)
1378                         return rte_flow_error_set
1379                                         (error, ENOTSUP,
1380                                          RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1381                                          NULL, "decap action not supported"
1382                                          " for egress");
1383         }
1384         return 0;
1385 }
1386
1387 /**
1388  * Find existing encap/decap resource or create and register a new one.
1389  *
1390  * @param dev[in, out]
1391  *   Pointer to rte_eth_dev structure.
1392  * @param[in, out] resource
1393  *   Pointer to encap/decap resource.
1394  * @parm[in, out] dev_flow
1395  *   Pointer to the dev_flow.
1396  * @param[out] error
1397  *   pointer to error structure.
1398  *
1399  * @return
1400  *   0 on success otherwise -errno and errno is set.
1401  */
1402 static int
1403 flow_dv_encap_decap_resource_register
1404                         (struct rte_eth_dev *dev,
1405                          struct mlx5_flow_dv_encap_decap_resource *resource,
1406                          struct mlx5_flow *dev_flow,
1407                          struct rte_flow_error *error)
1408 {
1409         struct mlx5_priv *priv = dev->data->dev_private;
1410         struct mlx5_ibv_shared *sh = priv->sh;
1411         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
1412         struct rte_flow *flow = dev_flow->flow;
1413         struct mlx5dv_dr_domain *domain;
1414
1415         resource->flags = flow->group ? 0 : 1;
1416         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
1417                 domain = sh->fdb_domain;
1418         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
1419                 domain = sh->rx_domain;
1420         else
1421                 domain = sh->tx_domain;
1422
1423         /* Lookup a matching resource from cache. */
1424         LIST_FOREACH(cache_resource, &sh->encaps_decaps, next) {
1425                 if (resource->reformat_type == cache_resource->reformat_type &&
1426                     resource->ft_type == cache_resource->ft_type &&
1427                     resource->flags == cache_resource->flags &&
1428                     resource->size == cache_resource->size &&
1429                     !memcmp((const void *)resource->buf,
1430                             (const void *)cache_resource->buf,
1431                             resource->size)) {
1432                         DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d++",
1433                                 (void *)cache_resource,
1434                                 rte_atomic32_read(&cache_resource->refcnt));
1435                         rte_atomic32_inc(&cache_resource->refcnt);
1436                         dev_flow->dv.encap_decap = cache_resource;
1437                         return 0;
1438                 }
1439         }
1440         /* Register new encap/decap resource. */
1441         cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
1442         if (!cache_resource)
1443                 return rte_flow_error_set(error, ENOMEM,
1444                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1445                                           "cannot allocate resource memory");
1446         *cache_resource = *resource;
1447         cache_resource->verbs_action =
1448                 mlx5_glue->dv_create_flow_action_packet_reformat
1449                         (sh->ctx, cache_resource->reformat_type,
1450                          cache_resource->ft_type, domain, cache_resource->flags,
1451                          cache_resource->size,
1452                          (cache_resource->size ? cache_resource->buf : NULL));
1453         if (!cache_resource->verbs_action) {
1454                 rte_free(cache_resource);
1455                 return rte_flow_error_set(error, ENOMEM,
1456                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1457                                           NULL, "cannot create action");
1458         }
1459         rte_atomic32_init(&cache_resource->refcnt);
1460         rte_atomic32_inc(&cache_resource->refcnt);
1461         LIST_INSERT_HEAD(&sh->encaps_decaps, cache_resource, next);
1462         dev_flow->dv.encap_decap = cache_resource;
1463         DRV_LOG(DEBUG, "new encap/decap resource %p: refcnt %d++",
1464                 (void *)cache_resource,
1465                 rte_atomic32_read(&cache_resource->refcnt));
1466         return 0;
1467 }
1468
1469 /**
1470  * Find existing table jump resource or create and register a new one.
1471  *
1472  * @param dev[in, out]
1473  *   Pointer to rte_eth_dev structure.
1474  * @param[in, out] resource
1475  *   Pointer to jump table resource.
1476  * @parm[in, out] dev_flow
1477  *   Pointer to the dev_flow.
1478  * @param[out] error
1479  *   pointer to error structure.
1480  *
1481  * @return
1482  *   0 on success otherwise -errno and errno is set.
1483  */
1484 static int
1485 flow_dv_jump_tbl_resource_register
1486                         (struct rte_eth_dev *dev,
1487                          struct mlx5_flow_dv_jump_tbl_resource *resource,
1488                          struct mlx5_flow *dev_flow,
1489                          struct rte_flow_error *error)
1490 {
1491         struct mlx5_priv *priv = dev->data->dev_private;
1492         struct mlx5_ibv_shared *sh = priv->sh;
1493         struct mlx5_flow_dv_jump_tbl_resource *cache_resource;
1494
1495         /* Lookup a matching resource from cache. */
1496         LIST_FOREACH(cache_resource, &sh->jump_tbl, next) {
1497                 if (resource->tbl == cache_resource->tbl) {
1498                         DRV_LOG(DEBUG, "jump table resource resource %p: refcnt %d++",
1499                                 (void *)cache_resource,
1500                                 rte_atomic32_read(&cache_resource->refcnt));
1501                         rte_atomic32_inc(&cache_resource->refcnt);
1502                         dev_flow->dv.jump = cache_resource;
1503                         return 0;
1504                 }
1505         }
1506         /* Register new jump table resource. */
1507         cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
1508         if (!cache_resource)
1509                 return rte_flow_error_set(error, ENOMEM,
1510                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1511                                           "cannot allocate resource memory");
1512         *cache_resource = *resource;
1513         cache_resource->action =
1514                 mlx5_glue->dr_create_flow_action_dest_flow_tbl
1515                 (resource->tbl->obj);
1516         if (!cache_resource->action) {
1517                 rte_free(cache_resource);
1518                 return rte_flow_error_set(error, ENOMEM,
1519                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1520                                           NULL, "cannot create action");
1521         }
1522         rte_atomic32_init(&cache_resource->refcnt);
1523         rte_atomic32_inc(&cache_resource->refcnt);
1524         LIST_INSERT_HEAD(&sh->jump_tbl, cache_resource, next);
1525         dev_flow->dv.jump = cache_resource;
1526         DRV_LOG(DEBUG, "new jump table  resource %p: refcnt %d++",
1527                 (void *)cache_resource,
1528                 rte_atomic32_read(&cache_resource->refcnt));
1529         return 0;
1530 }
1531
1532 /**
1533  * Find existing table port ID resource or create and register a new one.
1534  *
1535  * @param dev[in, out]
1536  *   Pointer to rte_eth_dev structure.
1537  * @param[in, out] resource
1538  *   Pointer to port ID action resource.
1539  * @parm[in, out] dev_flow
1540  *   Pointer to the dev_flow.
1541  * @param[out] error
1542  *   pointer to error structure.
1543  *
1544  * @return
1545  *   0 on success otherwise -errno and errno is set.
1546  */
1547 static int
1548 flow_dv_port_id_action_resource_register
1549                         (struct rte_eth_dev *dev,
1550                          struct mlx5_flow_dv_port_id_action_resource *resource,
1551                          struct mlx5_flow *dev_flow,
1552                          struct rte_flow_error *error)
1553 {
1554         struct mlx5_priv *priv = dev->data->dev_private;
1555         struct mlx5_ibv_shared *sh = priv->sh;
1556         struct mlx5_flow_dv_port_id_action_resource *cache_resource;
1557
1558         /* Lookup a matching resource from cache. */
1559         LIST_FOREACH(cache_resource, &sh->port_id_action_list, next) {
1560                 if (resource->port_id == cache_resource->port_id) {
1561                         DRV_LOG(DEBUG, "port id action resource resource %p: "
1562                                 "refcnt %d++",
1563                                 (void *)cache_resource,
1564                                 rte_atomic32_read(&cache_resource->refcnt));
1565                         rte_atomic32_inc(&cache_resource->refcnt);
1566                         dev_flow->dv.port_id_action = cache_resource;
1567                         return 0;
1568                 }
1569         }
1570         /* Register new port id action resource. */
1571         cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
1572         if (!cache_resource)
1573                 return rte_flow_error_set(error, ENOMEM,
1574                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1575                                           "cannot allocate resource memory");
1576         *cache_resource = *resource;
1577         cache_resource->action =
1578                 mlx5_glue->dr_create_flow_action_dest_vport
1579                         (priv->sh->fdb_domain, resource->port_id);
1580         if (!cache_resource->action) {
1581                 rte_free(cache_resource);
1582                 return rte_flow_error_set(error, ENOMEM,
1583                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1584                                           NULL, "cannot create action");
1585         }
1586         rte_atomic32_init(&cache_resource->refcnt);
1587         rte_atomic32_inc(&cache_resource->refcnt);
1588         LIST_INSERT_HEAD(&sh->port_id_action_list, cache_resource, next);
1589         dev_flow->dv.port_id_action = cache_resource;
1590         DRV_LOG(DEBUG, "new port id action resource %p: refcnt %d++",
1591                 (void *)cache_resource,
1592                 rte_atomic32_read(&cache_resource->refcnt));
1593         return 0;
1594 }
1595
1596 /**
1597  * Find existing push vlan resource or create and register a new one.
1598  *
1599  * @param dev[in, out]
1600  *   Pointer to rte_eth_dev structure.
1601  * @param[in, out] resource
1602  *   Pointer to port ID action resource.
1603  * @parm[in, out] dev_flow
1604  *   Pointer to the dev_flow.
1605  * @param[out] error
1606  *   pointer to error structure.
1607  *
1608  * @return
1609  *   0 on success otherwise -errno and errno is set.
1610  */
1611 static int
1612 flow_dv_push_vlan_action_resource_register
1613                        (struct rte_eth_dev *dev,
1614                         struct mlx5_flow_dv_push_vlan_action_resource *resource,
1615                         struct mlx5_flow *dev_flow,
1616                         struct rte_flow_error *error)
1617 {
1618         struct mlx5_priv *priv = dev->data->dev_private;
1619         struct mlx5_ibv_shared *sh = priv->sh;
1620         struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
1621         struct mlx5dv_dr_domain *domain;
1622
1623         /* Lookup a matching resource from cache. */
1624         LIST_FOREACH(cache_resource, &sh->push_vlan_action_list, next) {
1625                 if (resource->vlan_tag == cache_resource->vlan_tag &&
1626                     resource->ft_type == cache_resource->ft_type) {
1627                         DRV_LOG(DEBUG, "push-VLAN action resource resource %p: "
1628                                 "refcnt %d++",
1629                                 (void *)cache_resource,
1630                                 rte_atomic32_read(&cache_resource->refcnt));
1631                         rte_atomic32_inc(&cache_resource->refcnt);
1632                         dev_flow->dv.push_vlan_res = cache_resource;
1633                         return 0;
1634                 }
1635         }
1636         /* Register new push_vlan action resource. */
1637         cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
1638         if (!cache_resource)
1639                 return rte_flow_error_set(error, ENOMEM,
1640                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1641                                           "cannot allocate resource memory");
1642         *cache_resource = *resource;
1643         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
1644                 domain = sh->fdb_domain;
1645         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
1646                 domain = sh->rx_domain;
1647         else
1648                 domain = sh->tx_domain;
1649         cache_resource->action =
1650                 mlx5_glue->dr_create_flow_action_push_vlan(domain,
1651                                                            resource->vlan_tag);
1652         if (!cache_resource->action) {
1653                 rte_free(cache_resource);
1654                 return rte_flow_error_set(error, ENOMEM,
1655                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1656                                           NULL, "cannot create action");
1657         }
1658         rte_atomic32_init(&cache_resource->refcnt);
1659         rte_atomic32_inc(&cache_resource->refcnt);
1660         LIST_INSERT_HEAD(&sh->push_vlan_action_list, cache_resource, next);
1661         dev_flow->dv.push_vlan_res = cache_resource;
1662         DRV_LOG(DEBUG, "new push vlan action resource %p: refcnt %d++",
1663                 (void *)cache_resource,
1664                 rte_atomic32_read(&cache_resource->refcnt));
1665         return 0;
1666 }
1667 /**
1668  * Get the size of specific rte_flow_item_type
1669  *
1670  * @param[in] item_type
1671  *   Tested rte_flow_item_type.
1672  *
1673  * @return
1674  *   sizeof struct item_type, 0 if void or irrelevant.
1675  */
1676 static size_t
1677 flow_dv_get_item_len(const enum rte_flow_item_type item_type)
1678 {
1679         size_t retval;
1680
1681         switch (item_type) {
1682         case RTE_FLOW_ITEM_TYPE_ETH:
1683                 retval = sizeof(struct rte_flow_item_eth);
1684                 break;
1685         case RTE_FLOW_ITEM_TYPE_VLAN:
1686                 retval = sizeof(struct rte_flow_item_vlan);
1687                 break;
1688         case RTE_FLOW_ITEM_TYPE_IPV4:
1689                 retval = sizeof(struct rte_flow_item_ipv4);
1690                 break;
1691         case RTE_FLOW_ITEM_TYPE_IPV6:
1692                 retval = sizeof(struct rte_flow_item_ipv6);
1693                 break;
1694         case RTE_FLOW_ITEM_TYPE_UDP:
1695                 retval = sizeof(struct rte_flow_item_udp);
1696                 break;
1697         case RTE_FLOW_ITEM_TYPE_TCP:
1698                 retval = sizeof(struct rte_flow_item_tcp);
1699                 break;
1700         case RTE_FLOW_ITEM_TYPE_VXLAN:
1701                 retval = sizeof(struct rte_flow_item_vxlan);
1702                 break;
1703         case RTE_FLOW_ITEM_TYPE_GRE:
1704                 retval = sizeof(struct rte_flow_item_gre);
1705                 break;
1706         case RTE_FLOW_ITEM_TYPE_NVGRE:
1707                 retval = sizeof(struct rte_flow_item_nvgre);
1708                 break;
1709         case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
1710                 retval = sizeof(struct rte_flow_item_vxlan_gpe);
1711                 break;
1712         case RTE_FLOW_ITEM_TYPE_MPLS:
1713                 retval = sizeof(struct rte_flow_item_mpls);
1714                 break;
1715         case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
1716         default:
1717                 retval = 0;
1718                 break;
1719         }
1720         return retval;
1721 }
1722
1723 #define MLX5_ENCAP_IPV4_VERSION         0x40
1724 #define MLX5_ENCAP_IPV4_IHL_MIN         0x05
1725 #define MLX5_ENCAP_IPV4_TTL_DEF         0x40
1726 #define MLX5_ENCAP_IPV6_VTC_FLOW        0x60000000
1727 #define MLX5_ENCAP_IPV6_HOP_LIMIT       0xff
1728 #define MLX5_ENCAP_VXLAN_FLAGS          0x08000000
1729 #define MLX5_ENCAP_VXLAN_GPE_FLAGS      0x04
1730
1731 /**
1732  * Convert the encap action data from list of rte_flow_item to raw buffer
1733  *
1734  * @param[in] items
1735  *   Pointer to rte_flow_item objects list.
1736  * @param[out] buf
1737  *   Pointer to the output buffer.
1738  * @param[out] size
1739  *   Pointer to the output buffer size.
1740  * @param[out] error
1741  *   Pointer to the error structure.
1742  *
1743  * @return
1744  *   0 on success, a negative errno value otherwise and rte_errno is set.
1745  */
1746 static int
1747 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
1748                            size_t *size, struct rte_flow_error *error)
1749 {
1750         struct rte_ether_hdr *eth = NULL;
1751         struct rte_vlan_hdr *vlan = NULL;
1752         struct rte_ipv4_hdr *ipv4 = NULL;
1753         struct rte_ipv6_hdr *ipv6 = NULL;
1754         struct rte_udp_hdr *udp = NULL;
1755         struct rte_vxlan_hdr *vxlan = NULL;
1756         struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
1757         struct rte_gre_hdr *gre = NULL;
1758         size_t len;
1759         size_t temp_size = 0;
1760
1761         if (!items)
1762                 return rte_flow_error_set(error, EINVAL,
1763                                           RTE_FLOW_ERROR_TYPE_ACTION,
1764                                           NULL, "invalid empty data");
1765         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
1766                 len = flow_dv_get_item_len(items->type);
1767                 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
1768                         return rte_flow_error_set(error, EINVAL,
1769                                                   RTE_FLOW_ERROR_TYPE_ACTION,
1770                                                   (void *)items->type,
1771                                                   "items total size is too big"
1772                                                   " for encap action");
1773                 rte_memcpy((void *)&buf[temp_size], items->spec, len);
1774                 switch (items->type) {
1775                 case RTE_FLOW_ITEM_TYPE_ETH:
1776                         eth = (struct rte_ether_hdr *)&buf[temp_size];
1777                         break;
1778                 case RTE_FLOW_ITEM_TYPE_VLAN:
1779                         vlan = (struct rte_vlan_hdr *)&buf[temp_size];
1780                         if (!eth)
1781                                 return rte_flow_error_set(error, EINVAL,
1782                                                 RTE_FLOW_ERROR_TYPE_ACTION,
1783                                                 (void *)items->type,
1784                                                 "eth header not found");
1785                         if (!eth->ether_type)
1786                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
1787                         break;
1788                 case RTE_FLOW_ITEM_TYPE_IPV4:
1789                         ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
1790                         if (!vlan && !eth)
1791                                 return rte_flow_error_set(error, EINVAL,
1792                                                 RTE_FLOW_ERROR_TYPE_ACTION,
1793                                                 (void *)items->type,
1794                                                 "neither eth nor vlan"
1795                                                 " header found");
1796                         if (vlan && !vlan->eth_proto)
1797                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
1798                         else if (eth && !eth->ether_type)
1799                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
1800                         if (!ipv4->version_ihl)
1801                                 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
1802                                                     MLX5_ENCAP_IPV4_IHL_MIN;
1803                         if (!ipv4->time_to_live)
1804                                 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
1805                         break;
1806                 case RTE_FLOW_ITEM_TYPE_IPV6:
1807                         ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
1808                         if (!vlan && !eth)
1809                                 return rte_flow_error_set(error, EINVAL,
1810                                                 RTE_FLOW_ERROR_TYPE_ACTION,
1811                                                 (void *)items->type,
1812                                                 "neither eth nor vlan"
1813                                                 " header found");
1814                         if (vlan && !vlan->eth_proto)
1815                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
1816                         else if (eth && !eth->ether_type)
1817                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
1818                         if (!ipv6->vtc_flow)
1819                                 ipv6->vtc_flow =
1820                                         RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
1821                         if (!ipv6->hop_limits)
1822                                 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
1823                         break;
1824                 case RTE_FLOW_ITEM_TYPE_UDP:
1825                         udp = (struct rte_udp_hdr *)&buf[temp_size];
1826                         if (!ipv4 && !ipv6)
1827                                 return rte_flow_error_set(error, EINVAL,
1828                                                 RTE_FLOW_ERROR_TYPE_ACTION,
1829                                                 (void *)items->type,
1830                                                 "ip header not found");
1831                         if (ipv4 && !ipv4->next_proto_id)
1832                                 ipv4->next_proto_id = IPPROTO_UDP;
1833                         else if (ipv6 && !ipv6->proto)
1834                                 ipv6->proto = IPPROTO_UDP;
1835                         break;
1836                 case RTE_FLOW_ITEM_TYPE_VXLAN:
1837                         vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
1838                         if (!udp)
1839                                 return rte_flow_error_set(error, EINVAL,
1840                                                 RTE_FLOW_ERROR_TYPE_ACTION,
1841                                                 (void *)items->type,
1842                                                 "udp header not found");
1843                         if (!udp->dst_port)
1844                                 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
1845                         if (!vxlan->vx_flags)
1846                                 vxlan->vx_flags =
1847                                         RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
1848                         break;
1849                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
1850                         vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
1851                         if (!udp)
1852                                 return rte_flow_error_set(error, EINVAL,
1853                                                 RTE_FLOW_ERROR_TYPE_ACTION,
1854                                                 (void *)items->type,
1855                                                 "udp header not found");
1856                         if (!vxlan_gpe->proto)
1857                                 return rte_flow_error_set(error, EINVAL,
1858                                                 RTE_FLOW_ERROR_TYPE_ACTION,
1859                                                 (void *)items->type,
1860                                                 "next protocol not found");
1861                         if (!udp->dst_port)
1862                                 udp->dst_port =
1863                                         RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
1864                         if (!vxlan_gpe->vx_flags)
1865                                 vxlan_gpe->vx_flags =
1866                                                 MLX5_ENCAP_VXLAN_GPE_FLAGS;
1867                         break;
1868                 case RTE_FLOW_ITEM_TYPE_GRE:
1869                 case RTE_FLOW_ITEM_TYPE_NVGRE:
1870                         gre = (struct rte_gre_hdr *)&buf[temp_size];
1871                         if (!gre->proto)
1872                                 return rte_flow_error_set(error, EINVAL,
1873                                                 RTE_FLOW_ERROR_TYPE_ACTION,
1874                                                 (void *)items->type,
1875                                                 "next protocol not found");
1876                         if (!ipv4 && !ipv6)
1877                                 return rte_flow_error_set(error, EINVAL,
1878                                                 RTE_FLOW_ERROR_TYPE_ACTION,
1879                                                 (void *)items->type,
1880                                                 "ip header not found");
1881                         if (ipv4 && !ipv4->next_proto_id)
1882                                 ipv4->next_proto_id = IPPROTO_GRE;
1883                         else if (ipv6 && !ipv6->proto)
1884                                 ipv6->proto = IPPROTO_GRE;
1885                         break;
1886                 case RTE_FLOW_ITEM_TYPE_VOID:
1887                         break;
1888                 default:
1889                         return rte_flow_error_set(error, EINVAL,
1890                                                   RTE_FLOW_ERROR_TYPE_ACTION,
1891                                                   (void *)items->type,
1892                                                   "unsupported item type");
1893                         break;
1894                 }
1895                 temp_size += len;
1896         }
1897         *size = temp_size;
1898         return 0;
1899 }
1900
1901 static int
1902 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
1903 {
1904         struct rte_ether_hdr *eth = NULL;
1905         struct rte_vlan_hdr *vlan = NULL;
1906         struct rte_ipv6_hdr *ipv6 = NULL;
1907         struct rte_udp_hdr *udp = NULL;
1908         char *next_hdr;
1909         uint16_t proto;
1910
1911         eth = (struct rte_ether_hdr *)data;
1912         next_hdr = (char *)(eth + 1);
1913         proto = RTE_BE16(eth->ether_type);
1914
1915         /* VLAN skipping */
1916         while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
1917                 vlan = (struct rte_vlan_hdr *)next_hdr;
1918                 proto = RTE_BE16(vlan->eth_proto);
1919                 next_hdr += sizeof(struct rte_vlan_hdr);
1920         }
1921
1922         /* HW calculates IPv4 csum. no need to proceed */
1923         if (proto == RTE_ETHER_TYPE_IPV4)
1924                 return 0;
1925
1926         /* non IPv4/IPv6 header. not supported */
1927         if (proto != RTE_ETHER_TYPE_IPV6) {
1928                 return rte_flow_error_set(error, ENOTSUP,
1929                                           RTE_FLOW_ERROR_TYPE_ACTION,
1930                                           NULL, "Cannot offload non IPv4/IPv6");
1931         }
1932
1933         ipv6 = (struct rte_ipv6_hdr *)next_hdr;
1934
1935         /* ignore non UDP */
1936         if (ipv6->proto != IPPROTO_UDP)
1937                 return 0;
1938
1939         udp = (struct rte_udp_hdr *)(ipv6 + 1);
1940         udp->dgram_cksum = 0;
1941
1942         return 0;
1943 }
1944
1945 /**
1946  * Convert L2 encap action to DV specification.
1947  *
1948  * @param[in] dev
1949  *   Pointer to rte_eth_dev structure.
1950  * @param[in] action
1951  *   Pointer to action structure.
1952  * @param[in, out] dev_flow
1953  *   Pointer to the mlx5_flow.
1954  * @param[in] transfer
1955  *   Mark if the flow is E-Switch flow.
1956  * @param[out] error
1957  *   Pointer to the error structure.
1958  *
1959  * @return
1960  *   0 on success, a negative errno value otherwise and rte_errno is set.
1961  */
1962 static int
1963 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
1964                                const struct rte_flow_action *action,
1965                                struct mlx5_flow *dev_flow,
1966                                uint8_t transfer,
1967                                struct rte_flow_error *error)
1968 {
1969         const struct rte_flow_item *encap_data;
1970         const struct rte_flow_action_raw_encap *raw_encap_data;
1971         struct mlx5_flow_dv_encap_decap_resource res = {
1972                 .reformat_type =
1973                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
1974                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
1975                                       MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
1976         };
1977
1978         if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
1979                 raw_encap_data =
1980                         (const struct rte_flow_action_raw_encap *)action->conf;
1981                 res.size = raw_encap_data->size;
1982                 memcpy(res.buf, raw_encap_data->data, res.size);
1983                 if (flow_dv_zero_encap_udp_csum(res.buf, error))
1984                         return -rte_errno;
1985         } else {
1986                 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
1987                         encap_data =
1988                                 ((const struct rte_flow_action_vxlan_encap *)
1989                                                 action->conf)->definition;
1990                 else
1991                         encap_data =
1992                                 ((const struct rte_flow_action_nvgre_encap *)
1993                                                 action->conf)->definition;
1994                 if (flow_dv_convert_encap_data(encap_data, res.buf,
1995                                                &res.size, error))
1996                         return -rte_errno;
1997         }
1998         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
1999                 return rte_flow_error_set(error, EINVAL,
2000                                           RTE_FLOW_ERROR_TYPE_ACTION,
2001                                           NULL, "can't create L2 encap action");
2002         return 0;
2003 }
2004
2005 /**
2006  * Convert L2 decap action to DV specification.
2007  *
2008  * @param[in] dev
2009  *   Pointer to rte_eth_dev structure.
2010  * @param[in, out] dev_flow
2011  *   Pointer to the mlx5_flow.
2012  * @param[in] transfer
2013  *   Mark if the flow is E-Switch flow.
2014  * @param[out] error
2015  *   Pointer to the error structure.
2016  *
2017  * @return
2018  *   0 on success, a negative errno value otherwise and rte_errno is set.
2019  */
2020 static int
2021 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
2022                                struct mlx5_flow *dev_flow,
2023                                uint8_t transfer,
2024                                struct rte_flow_error *error)
2025 {
2026         struct mlx5_flow_dv_encap_decap_resource res = {
2027                 .size = 0,
2028                 .reformat_type =
2029                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
2030                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
2031                                       MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
2032         };
2033
2034         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
2035                 return rte_flow_error_set(error, EINVAL,
2036                                           RTE_FLOW_ERROR_TYPE_ACTION,
2037                                           NULL, "can't create L2 decap action");
2038         return 0;
2039 }
2040
2041 /**
2042  * Convert raw decap/encap (L3 tunnel) action to DV specification.
2043  *
2044  * @param[in] dev
2045  *   Pointer to rte_eth_dev structure.
2046  * @param[in] action
2047  *   Pointer to action structure.
2048  * @param[in, out] dev_flow
2049  *   Pointer to the mlx5_flow.
2050  * @param[in] attr
2051  *   Pointer to the flow attributes.
2052  * @param[out] error
2053  *   Pointer to the error structure.
2054  *
2055  * @return
2056  *   0 on success, a negative errno value otherwise and rte_errno is set.
2057  */
2058 static int
2059 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
2060                                 const struct rte_flow_action *action,
2061                                 struct mlx5_flow *dev_flow,
2062                                 const struct rte_flow_attr *attr,
2063                                 struct rte_flow_error *error)
2064 {
2065         const struct rte_flow_action_raw_encap *encap_data;
2066         struct mlx5_flow_dv_encap_decap_resource res;
2067
2068         encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
2069         res.size = encap_data->size;
2070         memcpy(res.buf, encap_data->data, res.size);
2071         res.reformat_type = attr->egress ?
2072                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL :
2073                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2;
2074         if (attr->transfer)
2075                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
2076         else
2077                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
2078                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
2079         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
2080                 return rte_flow_error_set(error, EINVAL,
2081                                           RTE_FLOW_ERROR_TYPE_ACTION,
2082                                           NULL, "can't create encap action");
2083         return 0;
2084 }
2085
2086 /**
2087  * Create action push VLAN.
2088  *
2089  * @param[in] dev
2090  *   Pointer to rte_eth_dev structure.
2091  * @param[in] vlan_tag
2092  *   the vlan tag to push to the Ethernet header.
2093  * @param[in, out] dev_flow
2094  *   Pointer to the mlx5_flow.
2095  * @param[in] attr
2096  *   Pointer to the flow attributes.
2097  * @param[out] error
2098  *   Pointer to the error structure.
2099  *
2100  * @return
2101  *   0 on success, a negative errno value otherwise and rte_errno is set.
2102  */
2103 static int
2104 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
2105                                 const struct rte_flow_attr *attr,
2106                                 const struct rte_vlan_hdr *vlan,
2107                                 struct mlx5_flow *dev_flow,
2108                                 struct rte_flow_error *error)
2109 {
2110         struct mlx5_flow_dv_push_vlan_action_resource res;
2111
2112         res.vlan_tag =
2113                 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
2114                                  vlan->vlan_tci);
2115         if (attr->transfer)
2116                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
2117         else
2118                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
2119                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
2120         return flow_dv_push_vlan_action_resource_register
2121                                             (dev, &res, dev_flow, error);
2122 }
2123
2124 /**
2125  * Validate the modify-header actions.
2126  *
2127  * @param[in] action_flags
2128  *   Holds the actions detected until now.
2129  * @param[in] action
2130  *   Pointer to the modify action.
2131  * @param[out] error
2132  *   Pointer to error structure.
2133  *
2134  * @return
2135  *   0 on success, a negative errno value otherwise and rte_errno is set.
2136  */
2137 static int
2138 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
2139                                    const struct rte_flow_action *action,
2140                                    struct rte_flow_error *error)
2141 {
2142         if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
2143                 return rte_flow_error_set(error, EINVAL,
2144                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2145                                           NULL, "action configuration not set");
2146         if (action_flags & MLX5_FLOW_ENCAP_ACTIONS)
2147                 return rte_flow_error_set(error, EINVAL,
2148                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2149                                           "can't have encap action before"
2150                                           " modify action");
2151         return 0;
2152 }
2153
2154 /**
2155  * Validate the modify-header MAC address actions.
2156  *
2157  * @param[in] action_flags
2158  *   Holds the actions detected until now.
2159  * @param[in] action
2160  *   Pointer to the modify action.
2161  * @param[in] item_flags
2162  *   Holds the items detected.
2163  * @param[out] error
2164  *   Pointer to error structure.
2165  *
2166  * @return
2167  *   0 on success, a negative errno value otherwise and rte_errno is set.
2168  */
2169 static int
2170 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
2171                                    const struct rte_flow_action *action,
2172                                    const uint64_t item_flags,
2173                                    struct rte_flow_error *error)
2174 {
2175         int ret = 0;
2176
2177         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2178         if (!ret) {
2179                 if (!(item_flags & MLX5_FLOW_LAYER_L2))
2180                         return rte_flow_error_set(error, EINVAL,
2181                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2182                                                   NULL,
2183                                                   "no L2 item in pattern");
2184         }
2185         return ret;
2186 }
2187
2188 /**
2189  * Validate the modify-header IPv4 address actions.
2190  *
2191  * @param[in] action_flags
2192  *   Holds the actions detected until now.
2193  * @param[in] action
2194  *   Pointer to the modify action.
2195  * @param[in] item_flags
2196  *   Holds the items detected.
2197  * @param[out] error
2198  *   Pointer to error structure.
2199  *
2200  * @return
2201  *   0 on success, a negative errno value otherwise and rte_errno is set.
2202  */
2203 static int
2204 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
2205                                     const struct rte_flow_action *action,
2206                                     const uint64_t item_flags,
2207                                     struct rte_flow_error *error)
2208 {
2209         int ret = 0;
2210
2211         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2212         if (!ret) {
2213                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
2214                         return rte_flow_error_set(error, EINVAL,
2215                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2216                                                   NULL,
2217                                                   "no ipv4 item in pattern");
2218         }
2219         return ret;
2220 }
2221
2222 /**
2223  * Validate the modify-header IPv6 address actions.
2224  *
2225  * @param[in] action_flags
2226  *   Holds the actions detected until now.
2227  * @param[in] action
2228  *   Pointer to the modify action.
2229  * @param[in] item_flags
2230  *   Holds the items detected.
2231  * @param[out] error
2232  *   Pointer to error structure.
2233  *
2234  * @return
2235  *   0 on success, a negative errno value otherwise and rte_errno is set.
2236  */
2237 static int
2238 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
2239                                     const struct rte_flow_action *action,
2240                                     const uint64_t item_flags,
2241                                     struct rte_flow_error *error)
2242 {
2243         int ret = 0;
2244
2245         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2246         if (!ret) {
2247                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
2248                         return rte_flow_error_set(error, EINVAL,
2249                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2250                                                   NULL,
2251                                                   "no ipv6 item in pattern");
2252         }
2253         return ret;
2254 }
2255
2256 /**
2257  * Validate the modify-header TP actions.
2258  *
2259  * @param[in] action_flags
2260  *   Holds the actions detected until now.
2261  * @param[in] action
2262  *   Pointer to the modify action.
2263  * @param[in] item_flags
2264  *   Holds the items detected.
2265  * @param[out] error
2266  *   Pointer to error structure.
2267  *
2268  * @return
2269  *   0 on success, a negative errno value otherwise and rte_errno is set.
2270  */
2271 static int
2272 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
2273                                   const struct rte_flow_action *action,
2274                                   const uint64_t item_flags,
2275                                   struct rte_flow_error *error)
2276 {
2277         int ret = 0;
2278
2279         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2280         if (!ret) {
2281                 if (!(item_flags & MLX5_FLOW_LAYER_L4))
2282                         return rte_flow_error_set(error, EINVAL,
2283                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2284                                                   NULL, "no transport layer "
2285                                                   "in pattern");
2286         }
2287         return ret;
2288 }
2289
2290 /**
2291  * Validate the modify-header actions of increment/decrement
2292  * TCP Sequence-number.
2293  *
2294  * @param[in] action_flags
2295  *   Holds the actions detected until now.
2296  * @param[in] action
2297  *   Pointer to the modify action.
2298  * @param[in] item_flags
2299  *   Holds the items detected.
2300  * @param[out] error
2301  *   Pointer to error structure.
2302  *
2303  * @return
2304  *   0 on success, a negative errno value otherwise and rte_errno is set.
2305  */
2306 static int
2307 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
2308                                        const struct rte_flow_action *action,
2309                                        const uint64_t item_flags,
2310                                        struct rte_flow_error *error)
2311 {
2312         int ret = 0;
2313
2314         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2315         if (!ret) {
2316                 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_TCP))
2317                         return rte_flow_error_set(error, EINVAL,
2318                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2319                                                   NULL, "no TCP item in"
2320                                                   " pattern");
2321                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
2322                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
2323                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
2324                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
2325                         return rte_flow_error_set(error, EINVAL,
2326                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2327                                                   NULL,
2328                                                   "cannot decrease and increase"
2329                                                   " TCP sequence number"
2330                                                   " at the same time");
2331         }
2332         return ret;
2333 }
2334
2335 /**
2336  * Validate the modify-header actions of increment/decrement
2337  * TCP Acknowledgment number.
2338  *
2339  * @param[in] action_flags
2340  *   Holds the actions detected until now.
2341  * @param[in] action
2342  *   Pointer to the modify action.
2343  * @param[in] item_flags
2344  *   Holds the items detected.
2345  * @param[out] error
2346  *   Pointer to error structure.
2347  *
2348  * @return
2349  *   0 on success, a negative errno value otherwise and rte_errno is set.
2350  */
2351 static int
2352 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
2353                                        const struct rte_flow_action *action,
2354                                        const uint64_t item_flags,
2355                                        struct rte_flow_error *error)
2356 {
2357         int ret = 0;
2358
2359         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2360         if (!ret) {
2361                 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_TCP))
2362                         return rte_flow_error_set(error, EINVAL,
2363                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2364                                                   NULL, "no TCP item in"
2365                                                   " pattern");
2366                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
2367                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
2368                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
2369                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
2370                         return rte_flow_error_set(error, EINVAL,
2371                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2372                                                   NULL,
2373                                                   "cannot decrease and increase"
2374                                                   " TCP acknowledgment number"
2375                                                   " at the same time");
2376         }
2377         return ret;
2378 }
2379
2380 /**
2381  * Validate the modify-header TTL actions.
2382  *
2383  * @param[in] action_flags
2384  *   Holds the actions detected until now.
2385  * @param[in] action
2386  *   Pointer to the modify action.
2387  * @param[in] item_flags
2388  *   Holds the items detected.
2389  * @param[out] error
2390  *   Pointer to error structure.
2391  *
2392  * @return
2393  *   0 on success, a negative errno value otherwise and rte_errno is set.
2394  */
2395 static int
2396 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
2397                                    const struct rte_flow_action *action,
2398                                    const uint64_t item_flags,
2399                                    struct rte_flow_error *error)
2400 {
2401         int ret = 0;
2402
2403         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2404         if (!ret) {
2405                 if (!(item_flags & MLX5_FLOW_LAYER_L3))
2406                         return rte_flow_error_set(error, EINVAL,
2407                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2408                                                   NULL,
2409                                                   "no IP protocol in pattern");
2410         }
2411         return ret;
2412 }
2413
2414 /**
2415  * Validate jump action.
2416  *
2417  * @param[in] action
2418  *   Pointer to the jump action.
2419  * @param[in] action_flags
2420  *   Holds the actions detected until now.
2421  * @param[in] attributes
2422  *   Pointer to flow attributes
2423  * @param[in] external
2424  *   Action belongs to flow rule created by request external to PMD.
2425  * @param[out] error
2426  *   Pointer to error structure.
2427  *
2428  * @return
2429  *   0 on success, a negative errno value otherwise and rte_errno is set.
2430  */
2431 static int
2432 flow_dv_validate_action_jump(const struct rte_flow_action *action,
2433                              uint64_t action_flags,
2434                              const struct rte_flow_attr *attributes,
2435                              bool external, struct rte_flow_error *error)
2436 {
2437         uint32_t max_group = attributes->transfer ? MLX5_MAX_TABLES_FDB :
2438                                                     MLX5_MAX_TABLES;
2439         uint32_t target_group, table;
2440         int ret = 0;
2441
2442         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
2443                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
2444                 return rte_flow_error_set(error, EINVAL,
2445                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2446                                           "can't have 2 fate actions in"
2447                                           " same flow");
2448         if (!action->conf)
2449                 return rte_flow_error_set(error, EINVAL,
2450                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2451                                           NULL, "action configuration not set");
2452         target_group =
2453                 ((const struct rte_flow_action_jump *)action->conf)->group;
2454         ret = mlx5_flow_group_to_table(attributes, external, target_group,
2455                                        &table, error);
2456         if (ret)
2457                 return ret;
2458         if (table >= max_group)
2459                 return rte_flow_error_set(error, EINVAL,
2460                                           RTE_FLOW_ERROR_TYPE_ATTR_GROUP, NULL,
2461                                           "target group index out of range");
2462         if (attributes->group >= target_group)
2463                 return rte_flow_error_set(error, EINVAL,
2464                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2465                                           "target group must be higher than"
2466                                           " the current flow group");
2467         return 0;
2468 }
2469
2470 /*
2471  * Validate the port_id action.
2472  *
2473  * @param[in] dev
2474  *   Pointer to rte_eth_dev structure.
2475  * @param[in] action_flags
2476  *   Bit-fields that holds the actions detected until now.
2477  * @param[in] action
2478  *   Port_id RTE action structure.
2479  * @param[in] attr
2480  *   Attributes of flow that includes this action.
2481  * @param[out] error
2482  *   Pointer to error structure.
2483  *
2484  * @return
2485  *   0 on success, a negative errno value otherwise and rte_errno is set.
2486  */
2487 static int
2488 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
2489                                 uint64_t action_flags,
2490                                 const struct rte_flow_action *action,
2491                                 const struct rte_flow_attr *attr,
2492                                 struct rte_flow_error *error)
2493 {
2494         const struct rte_flow_action_port_id *port_id;
2495         struct mlx5_priv *act_priv;
2496         struct mlx5_priv *dev_priv;
2497         uint16_t port;
2498
2499         if (!attr->transfer)
2500                 return rte_flow_error_set(error, ENOTSUP,
2501                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2502                                           NULL,
2503                                           "port id action is valid in transfer"
2504                                           " mode only");
2505         if (!action || !action->conf)
2506                 return rte_flow_error_set(error, ENOTSUP,
2507                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2508                                           NULL,
2509                                           "port id action parameters must be"
2510                                           " specified");
2511         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
2512                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
2513                 return rte_flow_error_set(error, EINVAL,
2514                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2515                                           "can have only one fate actions in"
2516                                           " a flow");
2517         dev_priv = mlx5_dev_to_eswitch_info(dev);
2518         if (!dev_priv)
2519                 return rte_flow_error_set(error, rte_errno,
2520                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2521                                           NULL,
2522                                           "failed to obtain E-Switch info");
2523         port_id = action->conf;
2524         port = port_id->original ? dev->data->port_id : port_id->id;
2525         act_priv = mlx5_port_to_eswitch_info(port);
2526         if (!act_priv)
2527                 return rte_flow_error_set
2528                                 (error, rte_errno,
2529                                  RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
2530                                  "failed to obtain E-Switch port id for port");
2531         if (act_priv->domain_id != dev_priv->domain_id)
2532                 return rte_flow_error_set
2533                                 (error, EINVAL,
2534                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2535                                  "port does not belong to"
2536                                  " E-Switch being configured");
2537         return 0;
2538 }
2539
2540 /**
2541  * Find existing modify-header resource or create and register a new one.
2542  *
2543  * @param dev[in, out]
2544  *   Pointer to rte_eth_dev structure.
2545  * @param[in, out] resource
2546  *   Pointer to modify-header resource.
2547  * @parm[in, out] dev_flow
2548  *   Pointer to the dev_flow.
2549  * @param[out] error
2550  *   pointer to error structure.
2551  *
2552  * @return
2553  *   0 on success otherwise -errno and errno is set.
2554  */
2555 static int
2556 flow_dv_modify_hdr_resource_register
2557                         (struct rte_eth_dev *dev,
2558                          struct mlx5_flow_dv_modify_hdr_resource *resource,
2559                          struct mlx5_flow *dev_flow,
2560                          struct rte_flow_error *error)
2561 {
2562         struct mlx5_priv *priv = dev->data->dev_private;
2563         struct mlx5_ibv_shared *sh = priv->sh;
2564         struct mlx5_flow_dv_modify_hdr_resource *cache_resource;
2565         struct mlx5dv_dr_domain *ns;
2566
2567         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2568                 ns = sh->fdb_domain;
2569         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
2570                 ns = sh->tx_domain;
2571         else
2572                 ns = sh->rx_domain;
2573         resource->flags =
2574                 dev_flow->flow->group ? 0 : MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
2575         /* Lookup a matching resource from cache. */
2576         LIST_FOREACH(cache_resource, &sh->modify_cmds, next) {
2577                 if (resource->ft_type == cache_resource->ft_type &&
2578                     resource->actions_num == cache_resource->actions_num &&
2579                     resource->flags == cache_resource->flags &&
2580                     !memcmp((const void *)resource->actions,
2581                             (const void *)cache_resource->actions,
2582                             (resource->actions_num *
2583                                             sizeof(resource->actions[0])))) {
2584                         DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d++",
2585                                 (void *)cache_resource,
2586                                 rte_atomic32_read(&cache_resource->refcnt));
2587                         rte_atomic32_inc(&cache_resource->refcnt);
2588                         dev_flow->dv.modify_hdr = cache_resource;
2589                         return 0;
2590                 }
2591         }
2592         /* Register new modify-header resource. */
2593         cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
2594         if (!cache_resource)
2595                 return rte_flow_error_set(error, ENOMEM,
2596                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2597                                           "cannot allocate resource memory");
2598         *cache_resource = *resource;
2599         cache_resource->verbs_action =
2600                 mlx5_glue->dv_create_flow_action_modify_header
2601                                         (sh->ctx, cache_resource->ft_type,
2602                                          ns, cache_resource->flags,
2603                                          cache_resource->actions_num *
2604                                          sizeof(cache_resource->actions[0]),
2605                                          (uint64_t *)cache_resource->actions);
2606         if (!cache_resource->verbs_action) {
2607                 rte_free(cache_resource);
2608                 return rte_flow_error_set(error, ENOMEM,
2609                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2610                                           NULL, "cannot create action");
2611         }
2612         rte_atomic32_init(&cache_resource->refcnt);
2613         rte_atomic32_inc(&cache_resource->refcnt);
2614         LIST_INSERT_HEAD(&sh->modify_cmds, cache_resource, next);
2615         dev_flow->dv.modify_hdr = cache_resource;
2616         DRV_LOG(DEBUG, "new modify-header resource %p: refcnt %d++",
2617                 (void *)cache_resource,
2618                 rte_atomic32_read(&cache_resource->refcnt));
2619         return 0;
2620 }
2621
2622 #define MLX5_CNT_CONTAINER_RESIZE 64
2623
2624 /**
2625  * Get or create a flow counter.
2626  *
2627  * @param[in] dev
2628  *   Pointer to the Ethernet device structure.
2629  * @param[in] shared
2630  *   Indicate if this counter is shared with other flows.
2631  * @param[in] id
2632  *   Counter identifier.
2633  *
2634  * @return
2635  *   pointer to flow counter on success, NULL otherwise and rte_errno is set.
2636  */
2637 static struct mlx5_flow_counter *
2638 flow_dv_counter_alloc_fallback(struct rte_eth_dev *dev, uint32_t shared,
2639                                uint32_t id)
2640 {
2641         struct mlx5_priv *priv = dev->data->dev_private;
2642         struct mlx5_flow_counter *cnt = NULL;
2643         struct mlx5_devx_obj *dcs = NULL;
2644
2645         if (!priv->config.devx) {
2646                 rte_errno = ENOTSUP;
2647                 return NULL;
2648         }
2649         if (shared) {
2650                 TAILQ_FOREACH(cnt, &priv->sh->cmng.flow_counters, next) {
2651                         if (cnt->shared && cnt->id == id) {
2652                                 cnt->ref_cnt++;
2653                                 return cnt;
2654                         }
2655                 }
2656         }
2657         dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
2658         if (!dcs)
2659                 return NULL;
2660         cnt = rte_calloc(__func__, 1, sizeof(*cnt), 0);
2661         if (!cnt) {
2662                 claim_zero(mlx5_devx_cmd_destroy(cnt->dcs));
2663                 rte_errno = ENOMEM;
2664                 return NULL;
2665         }
2666         struct mlx5_flow_counter tmpl = {
2667                 .shared = shared,
2668                 .ref_cnt = 1,
2669                 .id = id,
2670                 .dcs = dcs,
2671         };
2672         tmpl.action = mlx5_glue->dv_create_flow_action_counter(dcs->obj, 0);
2673         if (!tmpl.action) {
2674                 claim_zero(mlx5_devx_cmd_destroy(cnt->dcs));
2675                 rte_errno = errno;
2676                 rte_free(cnt);
2677                 return NULL;
2678         }
2679         *cnt = tmpl;
2680         TAILQ_INSERT_HEAD(&priv->sh->cmng.flow_counters, cnt, next);
2681         return cnt;
2682 }
2683
2684 /**
2685  * Release a flow counter.
2686  *
2687  * @param[in] dev
2688  *   Pointer to the Ethernet device structure.
2689  * @param[in] counter
2690  *   Pointer to the counter handler.
2691  */
2692 static void
2693 flow_dv_counter_release_fallback(struct rte_eth_dev *dev,
2694                                  struct mlx5_flow_counter *counter)
2695 {
2696         struct mlx5_priv *priv = dev->data->dev_private;
2697
2698         if (!counter)
2699                 return;
2700         if (--counter->ref_cnt == 0) {
2701                 TAILQ_REMOVE(&priv->sh->cmng.flow_counters, counter, next);
2702                 claim_zero(mlx5_devx_cmd_destroy(counter->dcs));
2703                 rte_free(counter);
2704         }
2705 }
2706
2707 /**
2708  * Query a devx flow counter.
2709  *
2710  * @param[in] dev
2711  *   Pointer to the Ethernet device structure.
2712  * @param[in] cnt
2713  *   Pointer to the flow counter.
2714  * @param[out] pkts
2715  *   The statistics value of packets.
2716  * @param[out] bytes
2717  *   The statistics value of bytes.
2718  *
2719  * @return
2720  *   0 on success, otherwise a negative errno value and rte_errno is set.
2721  */
2722 static inline int
2723 _flow_dv_query_count_fallback(struct rte_eth_dev *dev __rte_unused,
2724                      struct mlx5_flow_counter *cnt, uint64_t *pkts,
2725                      uint64_t *bytes)
2726 {
2727         return mlx5_devx_cmd_flow_counter_query(cnt->dcs, 0, 0, pkts, bytes,
2728                                                 0, NULL, NULL, 0);
2729 }
2730
2731 /**
2732  * Get a pool by a counter.
2733  *
2734  * @param[in] cnt
2735  *   Pointer to the counter.
2736  *
2737  * @return
2738  *   The counter pool.
2739  */
2740 static struct mlx5_flow_counter_pool *
2741 flow_dv_counter_pool_get(struct mlx5_flow_counter *cnt)
2742 {
2743         if (!cnt->batch) {
2744                 cnt -= cnt->dcs->id % MLX5_COUNTERS_PER_POOL;
2745                 return (struct mlx5_flow_counter_pool *)cnt - 1;
2746         }
2747         return cnt->pool;
2748 }
2749
2750 /**
2751  * Get a pool by devx counter ID.
2752  *
2753  * @param[in] cont
2754  *   Pointer to the counter container.
2755  * @param[in] id
2756  *   The counter devx ID.
2757  *
2758  * @return
2759  *   The counter pool pointer if exists, NULL otherwise,
2760  */
2761 static struct mlx5_flow_counter_pool *
2762 flow_dv_find_pool_by_id(struct mlx5_pools_container *cont, int id)
2763 {
2764         struct mlx5_flow_counter_pool *pool;
2765
2766         TAILQ_FOREACH(pool, &cont->pool_list, next) {
2767                 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
2768                                 MLX5_COUNTERS_PER_POOL;
2769
2770                 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
2771                         return pool;
2772         };
2773         return NULL;
2774 }
2775
2776 /**
2777  * Allocate a new memory for the counter values wrapped by all the needed
2778  * management.
2779  *
2780  * @param[in] dev
2781  *   Pointer to the Ethernet device structure.
2782  * @param[in] raws_n
2783  *   The raw memory areas - each one for MLX5_COUNTERS_PER_POOL counters.
2784  *
2785  * @return
2786  *   The new memory management pointer on success, otherwise NULL and rte_errno
2787  *   is set.
2788  */
2789 static struct mlx5_counter_stats_mem_mng *
2790 flow_dv_create_counter_stat_mem_mng(struct rte_eth_dev *dev, int raws_n)
2791 {
2792         struct mlx5_ibv_shared *sh = ((struct mlx5_priv *)
2793                                         (dev->data->dev_private))->sh;
2794         struct mlx5_devx_mkey_attr mkey_attr;
2795         struct mlx5_counter_stats_mem_mng *mem_mng;
2796         volatile struct flow_counter_stats *raw_data;
2797         int size = (sizeof(struct flow_counter_stats) *
2798                         MLX5_COUNTERS_PER_POOL +
2799                         sizeof(struct mlx5_counter_stats_raw)) * raws_n +
2800                         sizeof(struct mlx5_counter_stats_mem_mng);
2801         uint8_t *mem = rte_calloc(__func__, 1, size, sysconf(_SC_PAGESIZE));
2802         int i;
2803
2804         if (!mem) {
2805                 rte_errno = ENOMEM;
2806                 return NULL;
2807         }
2808         mem_mng = (struct mlx5_counter_stats_mem_mng *)(mem + size) - 1;
2809         size = sizeof(*raw_data) * MLX5_COUNTERS_PER_POOL * raws_n;
2810         mem_mng->umem = mlx5_glue->devx_umem_reg(sh->ctx, mem, size,
2811                                                  IBV_ACCESS_LOCAL_WRITE);
2812         if (!mem_mng->umem) {
2813                 rte_errno = errno;
2814                 rte_free(mem);
2815                 return NULL;
2816         }
2817         mkey_attr.addr = (uintptr_t)mem;
2818         mkey_attr.size = size;
2819         mkey_attr.umem_id = mem_mng->umem->umem_id;
2820         mkey_attr.pd = sh->pdn;
2821         mem_mng->dm = mlx5_devx_cmd_mkey_create(sh->ctx, &mkey_attr);
2822         if (!mem_mng->dm) {
2823                 mlx5_glue->devx_umem_dereg(mem_mng->umem);
2824                 rte_errno = errno;
2825                 rte_free(mem);
2826                 return NULL;
2827         }
2828         mem_mng->raws = (struct mlx5_counter_stats_raw *)(mem + size);
2829         raw_data = (volatile struct flow_counter_stats *)mem;
2830         for (i = 0; i < raws_n; ++i) {
2831                 mem_mng->raws[i].mem_mng = mem_mng;
2832                 mem_mng->raws[i].data = raw_data + i * MLX5_COUNTERS_PER_POOL;
2833         }
2834         LIST_INSERT_HEAD(&sh->cmng.mem_mngs, mem_mng, next);
2835         return mem_mng;
2836 }
2837
2838 /**
2839  * Resize a counter container.
2840  *
2841  * @param[in] dev
2842  *   Pointer to the Ethernet device structure.
2843  * @param[in] batch
2844  *   Whether the pool is for counter that was allocated by batch command.
2845  *
2846  * @return
2847  *   The new container pointer on success, otherwise NULL and rte_errno is set.
2848  */
2849 static struct mlx5_pools_container *
2850 flow_dv_container_resize(struct rte_eth_dev *dev, uint32_t batch)
2851 {
2852         struct mlx5_priv *priv = dev->data->dev_private;
2853         struct mlx5_pools_container *cont =
2854                         MLX5_CNT_CONTAINER(priv->sh, batch, 0);
2855         struct mlx5_pools_container *new_cont =
2856                         MLX5_CNT_CONTAINER_UNUSED(priv->sh, batch, 0);
2857         struct mlx5_counter_stats_mem_mng *mem_mng;
2858         uint32_t resize = cont->n + MLX5_CNT_CONTAINER_RESIZE;
2859         uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
2860         int i;
2861
2862         if (cont != MLX5_CNT_CONTAINER(priv->sh, batch, 1)) {
2863                 /* The last resize still hasn't detected by the host thread. */
2864                 rte_errno = EAGAIN;
2865                 return NULL;
2866         }
2867         new_cont->pools = rte_calloc(__func__, 1, mem_size, 0);
2868         if (!new_cont->pools) {
2869                 rte_errno = ENOMEM;
2870                 return NULL;
2871         }
2872         if (cont->n)
2873                 memcpy(new_cont->pools, cont->pools, cont->n *
2874                        sizeof(struct mlx5_flow_counter_pool *));
2875         mem_mng = flow_dv_create_counter_stat_mem_mng(dev,
2876                 MLX5_CNT_CONTAINER_RESIZE + MLX5_MAX_PENDING_QUERIES);
2877         if (!mem_mng) {
2878                 rte_free(new_cont->pools);
2879                 return NULL;
2880         }
2881         for (i = 0; i < MLX5_MAX_PENDING_QUERIES; ++i)
2882                 LIST_INSERT_HEAD(&priv->sh->cmng.free_stat_raws,
2883                                  mem_mng->raws + MLX5_CNT_CONTAINER_RESIZE +
2884                                  i, next);
2885         new_cont->n = resize;
2886         rte_atomic16_set(&new_cont->n_valid, rte_atomic16_read(&cont->n_valid));
2887         TAILQ_INIT(&new_cont->pool_list);
2888         TAILQ_CONCAT(&new_cont->pool_list, &cont->pool_list, next);
2889         new_cont->init_mem_mng = mem_mng;
2890         rte_cio_wmb();
2891          /* Flip the master container. */
2892         priv->sh->cmng.mhi[batch] ^= (uint8_t)1;
2893         return new_cont;
2894 }
2895
2896 /**
2897  * Query a devx flow counter.
2898  *
2899  * @param[in] dev
2900  *   Pointer to the Ethernet device structure.
2901  * @param[in] cnt
2902  *   Pointer to the flow counter.
2903  * @param[out] pkts
2904  *   The statistics value of packets.
2905  * @param[out] bytes
2906  *   The statistics value of bytes.
2907  *
2908  * @return
2909  *   0 on success, otherwise a negative errno value and rte_errno is set.
2910  */
2911 static inline int
2912 _flow_dv_query_count(struct rte_eth_dev *dev,
2913                      struct mlx5_flow_counter *cnt, uint64_t *pkts,
2914                      uint64_t *bytes)
2915 {
2916         struct mlx5_priv *priv = dev->data->dev_private;
2917         struct mlx5_flow_counter_pool *pool =
2918                         flow_dv_counter_pool_get(cnt);
2919         int offset = cnt - &pool->counters_raw[0];
2920
2921         if (priv->counter_fallback)
2922                 return _flow_dv_query_count_fallback(dev, cnt, pkts, bytes);
2923
2924         rte_spinlock_lock(&pool->sl);
2925         /*
2926          * The single counters allocation may allocate smaller ID than the
2927          * current allocated in parallel to the host reading.
2928          * In this case the new counter values must be reported as 0.
2929          */
2930         if (unlikely(!cnt->batch && cnt->dcs->id < pool->raw->min_dcs_id)) {
2931                 *pkts = 0;
2932                 *bytes = 0;
2933         } else {
2934                 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
2935                 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
2936         }
2937         rte_spinlock_unlock(&pool->sl);
2938         return 0;
2939 }
2940
2941 /**
2942  * Create and initialize a new counter pool.
2943  *
2944  * @param[in] dev
2945  *   Pointer to the Ethernet device structure.
2946  * @param[out] dcs
2947  *   The devX counter handle.
2948  * @param[in] batch
2949  *   Whether the pool is for counter that was allocated by batch command.
2950  *
2951  * @return
2952  *   A new pool pointer on success, NULL otherwise and rte_errno is set.
2953  */
2954 static struct mlx5_flow_counter_pool *
2955 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
2956                     uint32_t batch)
2957 {
2958         struct mlx5_priv *priv = dev->data->dev_private;
2959         struct mlx5_flow_counter_pool *pool;
2960         struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
2961                                                                0);
2962         int16_t n_valid = rte_atomic16_read(&cont->n_valid);
2963         uint32_t size;
2964
2965         if (cont->n == n_valid) {
2966                 cont = flow_dv_container_resize(dev, batch);
2967                 if (!cont)
2968                         return NULL;
2969         }
2970         size = sizeof(*pool) + MLX5_COUNTERS_PER_POOL *
2971                         sizeof(struct mlx5_flow_counter);
2972         pool = rte_calloc(__func__, 1, size, 0);
2973         if (!pool) {
2974                 rte_errno = ENOMEM;
2975                 return NULL;
2976         }
2977         pool->min_dcs = dcs;
2978         pool->raw = cont->init_mem_mng->raws + n_valid %
2979                                                      MLX5_CNT_CONTAINER_RESIZE;
2980         pool->raw_hw = NULL;
2981         rte_spinlock_init(&pool->sl);
2982         /*
2983          * The generation of the new allocated counters in this pool is 0, 2 in
2984          * the pool generation makes all the counters valid for allocation.
2985          */
2986         rte_atomic64_set(&pool->query_gen, 0x2);
2987         TAILQ_INIT(&pool->counters);
2988         TAILQ_INSERT_TAIL(&cont->pool_list, pool, next);
2989         cont->pools[n_valid] = pool;
2990         /* Pool initialization must be updated before host thread access. */
2991         rte_cio_wmb();
2992         rte_atomic16_add(&cont->n_valid, 1);
2993         return pool;
2994 }
2995
2996 /**
2997  * Prepare a new counter and/or a new counter pool.
2998  *
2999  * @param[in] dev
3000  *   Pointer to the Ethernet device structure.
3001  * @param[out] cnt_free
3002  *   Where to put the pointer of a new counter.
3003  * @param[in] batch
3004  *   Whether the pool is for counter that was allocated by batch command.
3005  *
3006  * @return
3007  *   The free counter pool pointer and @p cnt_free is set on success,
3008  *   NULL otherwise and rte_errno is set.
3009  */
3010 static struct mlx5_flow_counter_pool *
3011 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
3012                              struct mlx5_flow_counter **cnt_free,
3013                              uint32_t batch)
3014 {
3015         struct mlx5_priv *priv = dev->data->dev_private;
3016         struct mlx5_flow_counter_pool *pool;
3017         struct mlx5_devx_obj *dcs = NULL;
3018         struct mlx5_flow_counter *cnt;
3019         uint32_t i;
3020
3021         if (!batch) {
3022                 /* bulk_bitmap must be 0 for single counter allocation. */
3023                 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
3024                 if (!dcs)
3025                         return NULL;
3026                 pool = flow_dv_find_pool_by_id
3027                         (MLX5_CNT_CONTAINER(priv->sh, batch, 0), dcs->id);
3028                 if (!pool) {
3029                         pool = flow_dv_pool_create(dev, dcs, batch);
3030                         if (!pool) {
3031                                 mlx5_devx_cmd_destroy(dcs);
3032                                 return NULL;
3033                         }
3034                 } else if (dcs->id < pool->min_dcs->id) {
3035                         rte_atomic64_set(&pool->a64_dcs,
3036                                          (int64_t)(uintptr_t)dcs);
3037                 }
3038                 cnt = &pool->counters_raw[dcs->id % MLX5_COUNTERS_PER_POOL];
3039                 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
3040                 cnt->dcs = dcs;
3041                 *cnt_free = cnt;
3042                 return pool;
3043         }
3044         /* bulk_bitmap is in 128 counters units. */
3045         if (priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4)
3046                 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
3047         if (!dcs) {
3048                 rte_errno = ENODATA;
3049                 return NULL;
3050         }
3051         pool = flow_dv_pool_create(dev, dcs, batch);
3052         if (!pool) {
3053                 mlx5_devx_cmd_destroy(dcs);
3054                 return NULL;
3055         }
3056         for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
3057                 cnt = &pool->counters_raw[i];
3058                 cnt->pool = pool;
3059                 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
3060         }
3061         *cnt_free = &pool->counters_raw[0];
3062         return pool;
3063 }
3064
3065 /**
3066  * Search for existed shared counter.
3067  *
3068  * @param[in] cont
3069  *   Pointer to the relevant counter pool container.
3070  * @param[in] id
3071  *   The shared counter ID to search.
3072  *
3073  * @return
3074  *   NULL if not existed, otherwise pointer to the shared counter.
3075  */
3076 static struct mlx5_flow_counter *
3077 flow_dv_counter_shared_search(struct mlx5_pools_container *cont,
3078                               uint32_t id)
3079 {
3080         static struct mlx5_flow_counter *cnt;
3081         struct mlx5_flow_counter_pool *pool;
3082         int i;
3083
3084         TAILQ_FOREACH(pool, &cont->pool_list, next) {
3085                 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
3086                         cnt = &pool->counters_raw[i];
3087                         if (cnt->ref_cnt && cnt->shared && cnt->id == id)
3088                                 return cnt;
3089                 }
3090         }
3091         return NULL;
3092 }
3093
3094 /**
3095  * Allocate a flow counter.
3096  *
3097  * @param[in] dev
3098  *   Pointer to the Ethernet device structure.
3099  * @param[in] shared
3100  *   Indicate if this counter is shared with other flows.
3101  * @param[in] id
3102  *   Counter identifier.
3103  * @param[in] group
3104  *   Counter flow group.
3105  *
3106  * @return
3107  *   pointer to flow counter on success, NULL otherwise and rte_errno is set.
3108  */
3109 static struct mlx5_flow_counter *
3110 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t shared, uint32_t id,
3111                       uint16_t group)
3112 {
3113         struct mlx5_priv *priv = dev->data->dev_private;
3114         struct mlx5_flow_counter_pool *pool = NULL;
3115         struct mlx5_flow_counter *cnt_free = NULL;
3116         /*
3117          * Currently group 0 flow counter cannot be assigned to a flow if it is
3118          * not the first one in the batch counter allocation, so it is better
3119          * to allocate counters one by one for these flows in a separate
3120          * container.
3121          * A counter can be shared between different groups so need to take
3122          * shared counters from the single container.
3123          */
3124         uint32_t batch = (group && !shared) ? 1 : 0;
3125         struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
3126                                                                0);
3127
3128         if (priv->counter_fallback)
3129                 return flow_dv_counter_alloc_fallback(dev, shared, id);
3130         if (!priv->config.devx) {
3131                 rte_errno = ENOTSUP;
3132                 return NULL;
3133         }
3134         if (shared) {
3135                 cnt_free = flow_dv_counter_shared_search(cont, id);
3136                 if (cnt_free) {
3137                         if (cnt_free->ref_cnt + 1 == 0) {
3138                                 rte_errno = E2BIG;
3139                                 return NULL;
3140                         }
3141                         cnt_free->ref_cnt++;
3142                         return cnt_free;
3143                 }
3144         }
3145         /* Pools which has a free counters are in the start. */
3146         TAILQ_FOREACH(pool, &cont->pool_list, next) {
3147                 /*
3148                  * The free counter reset values must be updated between the
3149                  * counter release to the counter allocation, so, at least one
3150                  * query must be done in this time. ensure it by saving the
3151                  * query generation in the release time.
3152                  * The free list is sorted according to the generation - so if
3153                  * the first one is not updated, all the others are not
3154                  * updated too.
3155                  */
3156                 cnt_free = TAILQ_FIRST(&pool->counters);
3157                 if (cnt_free && cnt_free->query_gen + 1 <
3158                     rte_atomic64_read(&pool->query_gen))
3159                         break;
3160                 cnt_free = NULL;
3161         }
3162         if (!cnt_free) {
3163                 pool = flow_dv_counter_pool_prepare(dev, &cnt_free, batch);
3164                 if (!pool)
3165                         return NULL;
3166         }
3167         cnt_free->batch = batch;
3168         /* Create a DV counter action only in the first time usage. */
3169         if (!cnt_free->action) {
3170                 uint16_t offset;
3171                 struct mlx5_devx_obj *dcs;
3172
3173                 if (batch) {
3174                         offset = cnt_free - &pool->counters_raw[0];
3175                         dcs = pool->min_dcs;
3176                 } else {
3177                         offset = 0;
3178                         dcs = cnt_free->dcs;
3179                 }
3180                 cnt_free->action = mlx5_glue->dv_create_flow_action_counter
3181                                         (dcs->obj, offset);
3182                 if (!cnt_free->action) {
3183                         rte_errno = errno;
3184                         return NULL;
3185                 }
3186         }
3187         /* Update the counter reset values. */
3188         if (_flow_dv_query_count(dev, cnt_free, &cnt_free->hits,
3189                                  &cnt_free->bytes))
3190                 return NULL;
3191         cnt_free->shared = shared;
3192         cnt_free->ref_cnt = 1;
3193         cnt_free->id = id;
3194         if (!priv->sh->cmng.query_thread_on)
3195                 /* Start the asynchronous batch query by the host thread. */
3196                 mlx5_set_query_alarm(priv->sh);
3197         TAILQ_REMOVE(&pool->counters, cnt_free, next);
3198         if (TAILQ_EMPTY(&pool->counters)) {
3199                 /* Move the pool to the end of the container pool list. */
3200                 TAILQ_REMOVE(&cont->pool_list, pool, next);
3201                 TAILQ_INSERT_TAIL(&cont->pool_list, pool, next);
3202         }
3203         return cnt_free;
3204 }
3205
3206 /**
3207  * Release a flow counter.
3208  *
3209  * @param[in] dev
3210  *   Pointer to the Ethernet device structure.
3211  * @param[in] counter
3212  *   Pointer to the counter handler.
3213  */
3214 static void
3215 flow_dv_counter_release(struct rte_eth_dev *dev,
3216                         struct mlx5_flow_counter *counter)
3217 {
3218         struct mlx5_priv *priv = dev->data->dev_private;
3219
3220         if (!counter)
3221                 return;
3222         if (priv->counter_fallback) {
3223                 flow_dv_counter_release_fallback(dev, counter);
3224                 return;
3225         }
3226         if (--counter->ref_cnt == 0) {
3227                 struct mlx5_flow_counter_pool *pool =
3228                                 flow_dv_counter_pool_get(counter);
3229
3230                 /* Put the counter in the end - the last updated one. */
3231                 TAILQ_INSERT_TAIL(&pool->counters, counter, next);
3232                 counter->query_gen = rte_atomic64_read(&pool->query_gen);
3233         }
3234 }
3235
3236 /**
3237  * Verify the @p attributes will be correctly understood by the NIC and store
3238  * them in the @p flow if everything is correct.
3239  *
3240  * @param[in] dev
3241  *   Pointer to dev struct.
3242  * @param[in] attributes
3243  *   Pointer to flow attributes
3244  * @param[in] external
3245  *   This flow rule is created by request external to PMD.
3246  * @param[out] error
3247  *   Pointer to error structure.
3248  *
3249  * @return
3250  *   0 on success, a negative errno value otherwise and rte_errno is set.
3251  */
3252 static int
3253 flow_dv_validate_attributes(struct rte_eth_dev *dev,
3254                             const struct rte_flow_attr *attributes,
3255                             bool external __rte_unused,
3256                             struct rte_flow_error *error)
3257 {
3258         struct mlx5_priv *priv = dev->data->dev_private;
3259         uint32_t priority_max = priv->config.flow_prio - 1;
3260
3261 #ifndef HAVE_MLX5DV_DR
3262         if (attributes->group)
3263                 return rte_flow_error_set(error, ENOTSUP,
3264                                           RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
3265                                           NULL,
3266                                           "groups are not supported");
3267 #else
3268         uint32_t max_group = attributes->transfer ? MLX5_MAX_TABLES_FDB :
3269                                                     MLX5_MAX_TABLES;
3270         uint32_t table;
3271         int ret;
3272
3273         ret = mlx5_flow_group_to_table(attributes, external,
3274                                        attributes->group,
3275                                        &table, error);
3276         if (ret)
3277                 return ret;
3278         if (table >= max_group)
3279                 return rte_flow_error_set(error, EINVAL,
3280                                           RTE_FLOW_ERROR_TYPE_ATTR_GROUP, NULL,
3281                                           "group index out of range");
3282 #endif
3283         if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
3284             attributes->priority >= priority_max)
3285                 return rte_flow_error_set(error, ENOTSUP,
3286                                           RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
3287                                           NULL,
3288                                           "priority out of range");
3289         if (attributes->transfer) {
3290                 if (!priv->config.dv_esw_en)
3291                         return rte_flow_error_set
3292                                 (error, ENOTSUP,
3293                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3294                                  "E-Switch dr is not supported");
3295                 if (!(priv->representor || priv->master))
3296                         return rte_flow_error_set
3297                                 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3298                                  NULL, "E-Switch configuration can only be"
3299                                  " done by a master or a representor device");
3300                 if (attributes->egress)
3301                         return rte_flow_error_set
3302                                 (error, ENOTSUP,
3303                                  RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
3304                                  "egress is not supported");
3305         }
3306         if (!(attributes->egress ^ attributes->ingress))
3307                 return rte_flow_error_set(error, ENOTSUP,
3308                                           RTE_FLOW_ERROR_TYPE_ATTR, NULL,
3309                                           "must specify exactly one of "
3310                                           "ingress or egress");
3311         return 0;
3312 }
3313
3314 /**
3315  * Internal validation function. For validating both actions and items.
3316  *
3317  * @param[in] dev
3318  *   Pointer to the rte_eth_dev structure.
3319  * @param[in] attr
3320  *   Pointer to the flow attributes.
3321  * @param[in] items
3322  *   Pointer to the list of items.
3323  * @param[in] actions
3324  *   Pointer to the list of actions.
3325  * @param[in] external
3326  *   This flow rule is created by request external to PMD.
3327  * @param[out] error
3328  *   Pointer to the error structure.
3329  *
3330  * @return
3331  *   0 on success, a negative errno value otherwise and rte_errno is set.
3332  */
3333 static int
3334 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
3335                  const struct rte_flow_item items[],
3336                  const struct rte_flow_action actions[],
3337                  bool external, struct rte_flow_error *error)
3338 {
3339         int ret;
3340         uint64_t action_flags = 0;
3341         uint64_t item_flags = 0;
3342         uint64_t last_item = 0;
3343         uint8_t next_protocol = 0xff;
3344         int actions_n = 0;
3345         const struct rte_flow_item *gre_item = NULL;
3346         struct rte_flow_item_tcp nic_tcp_mask = {
3347                 .hdr = {
3348                         .tcp_flags = 0xFF,
3349                         .src_port = RTE_BE16(UINT16_MAX),
3350                         .dst_port = RTE_BE16(UINT16_MAX),
3351                 }
3352         };
3353
3354         if (items == NULL)
3355                 return -1;
3356         ret = flow_dv_validate_attributes(dev, attr, external, error);
3357         if (ret < 0)
3358                 return ret;
3359         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
3360                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
3361                 switch (items->type) {
3362                 case RTE_FLOW_ITEM_TYPE_VOID:
3363                         break;
3364                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
3365                         ret = flow_dv_validate_item_port_id
3366                                         (dev, items, attr, item_flags, error);
3367                         if (ret < 0)
3368                                 return ret;
3369                         last_item = MLX5_FLOW_ITEM_PORT_ID;
3370                         break;
3371                 case RTE_FLOW_ITEM_TYPE_ETH:
3372                         ret = mlx5_flow_validate_item_eth(items, item_flags,
3373                                                           error);
3374                         if (ret < 0)
3375                                 return ret;
3376                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
3377                                              MLX5_FLOW_LAYER_OUTER_L2;
3378                         break;
3379                 case RTE_FLOW_ITEM_TYPE_VLAN:
3380                         ret = mlx5_flow_validate_item_vlan(items, item_flags,
3381                                                            dev, error);
3382                         if (ret < 0)
3383                                 return ret;
3384                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
3385                                              MLX5_FLOW_LAYER_OUTER_VLAN;
3386                         break;
3387                 case RTE_FLOW_ITEM_TYPE_IPV4:
3388                         mlx5_flow_tunnel_ip_check(items, next_protocol,
3389                                                   &item_flags, &tunnel);
3390                         ret = mlx5_flow_validate_item_ipv4(items, item_flags,
3391                                                            NULL, error);
3392                         if (ret < 0)
3393                                 return ret;
3394                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
3395                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
3396                         if (items->mask != NULL &&
3397                             ((const struct rte_flow_item_ipv4 *)
3398                              items->mask)->hdr.next_proto_id) {
3399                                 next_protocol =
3400                                         ((const struct rte_flow_item_ipv4 *)
3401                                          (items->spec))->hdr.next_proto_id;
3402                                 next_protocol &=
3403                                         ((const struct rte_flow_item_ipv4 *)
3404                                          (items->mask))->hdr.next_proto_id;
3405                         } else {
3406                                 /* Reset for inner layer. */
3407                                 next_protocol = 0xff;
3408                         }
3409                         break;
3410                 case RTE_FLOW_ITEM_TYPE_IPV6:
3411                         mlx5_flow_tunnel_ip_check(items, next_protocol,
3412                                                   &item_flags, &tunnel);
3413                         ret = mlx5_flow_validate_item_ipv6(items, item_flags,
3414                                                            NULL, error);
3415                         if (ret < 0)
3416                                 return ret;
3417                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
3418                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
3419                         if (items->mask != NULL &&
3420                             ((const struct rte_flow_item_ipv6 *)
3421                              items->mask)->hdr.proto) {
3422                                 next_protocol =
3423                                         ((const struct rte_flow_item_ipv6 *)
3424                                          items->spec)->hdr.proto;
3425                                 next_protocol &=
3426                                         ((const struct rte_flow_item_ipv6 *)
3427                                          items->mask)->hdr.proto;
3428                         } else {
3429                                 /* Reset for inner layer. */
3430                                 next_protocol = 0xff;
3431                         }
3432                         break;
3433                 case RTE_FLOW_ITEM_TYPE_TCP:
3434                         ret = mlx5_flow_validate_item_tcp
3435                                                 (items, item_flags,
3436                                                  next_protocol,
3437                                                  &nic_tcp_mask,
3438                                                  error);
3439                         if (ret < 0)
3440                                 return ret;
3441                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
3442                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
3443                         break;
3444                 case RTE_FLOW_ITEM_TYPE_UDP:
3445                         ret = mlx5_flow_validate_item_udp(items, item_flags,
3446                                                           next_protocol,
3447                                                           error);
3448                         if (ret < 0)
3449                                 return ret;
3450                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
3451                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
3452                         break;
3453                 case RTE_FLOW_ITEM_TYPE_GRE:
3454                         ret = mlx5_flow_validate_item_gre(items, item_flags,
3455                                                           next_protocol, error);
3456                         if (ret < 0)
3457                                 return ret;
3458                         gre_item = items;
3459                         last_item = MLX5_FLOW_LAYER_GRE;
3460                         break;
3461                 case RTE_FLOW_ITEM_TYPE_NVGRE:
3462                         ret = mlx5_flow_validate_item_nvgre(items, item_flags,
3463                                                             next_protocol,
3464                                                             error);
3465                         if (ret < 0)
3466                                 return ret;
3467                         last_item = MLX5_FLOW_LAYER_NVGRE;
3468                         break;
3469                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
3470                         ret = mlx5_flow_validate_item_gre_key
3471                                 (items, item_flags, gre_item, error);
3472                         if (ret < 0)
3473                                 return ret;
3474                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
3475                         break;
3476                 case RTE_FLOW_ITEM_TYPE_VXLAN:
3477                         ret = mlx5_flow_validate_item_vxlan(items, item_flags,
3478                                                             error);
3479                         if (ret < 0)
3480                                 return ret;
3481                         last_item = MLX5_FLOW_LAYER_VXLAN;
3482                         break;
3483                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3484                         ret = mlx5_flow_validate_item_vxlan_gpe(items,
3485                                                                 item_flags, dev,
3486                                                                 error);
3487                         if (ret < 0)
3488                                 return ret;
3489                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
3490                         break;
3491                 case RTE_FLOW_ITEM_TYPE_GENEVE:
3492                         ret = mlx5_flow_validate_item_geneve(items,
3493                                                              item_flags, dev,
3494                                                              error);
3495                         if (ret < 0)
3496                                 return ret;
3497                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
3498                         break;
3499                 case RTE_FLOW_ITEM_TYPE_MPLS:
3500                         ret = mlx5_flow_validate_item_mpls(dev, items,
3501                                                            item_flags,
3502                                                            last_item, error);
3503                         if (ret < 0)
3504                                 return ret;
3505                         last_item = MLX5_FLOW_LAYER_MPLS;
3506                         break;
3507                 case RTE_FLOW_ITEM_TYPE_META:
3508                         ret = flow_dv_validate_item_meta(dev, items, attr,
3509                                                          error);
3510                         if (ret < 0)
3511                                 return ret;
3512                         last_item = MLX5_FLOW_ITEM_METADATA;
3513                         break;
3514                 case RTE_FLOW_ITEM_TYPE_ICMP:
3515                         ret = mlx5_flow_validate_item_icmp(items, item_flags,
3516                                                            next_protocol,
3517                                                            error);
3518                         if (ret < 0)
3519                                 return ret;
3520                         last_item = MLX5_FLOW_LAYER_ICMP;
3521                         break;
3522                 case RTE_FLOW_ITEM_TYPE_ICMP6:
3523                         ret = mlx5_flow_validate_item_icmp6(items, item_flags,
3524                                                             next_protocol,
3525                                                             error);
3526                         if (ret < 0)
3527                                 return ret;
3528                         last_item = MLX5_FLOW_LAYER_ICMP6;
3529                         break;
3530                 default:
3531                         return rte_flow_error_set(error, ENOTSUP,
3532                                                   RTE_FLOW_ERROR_TYPE_ITEM,
3533                                                   NULL, "item not supported");
3534                 }
3535                 item_flags |= last_item;
3536         }
3537         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
3538                 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
3539                         return rte_flow_error_set(error, ENOTSUP,
3540                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3541                                                   actions, "too many actions");
3542                 switch (actions->type) {
3543                 case RTE_FLOW_ACTION_TYPE_VOID:
3544                         break;
3545                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
3546                         ret = flow_dv_validate_action_port_id(dev,
3547                                                               action_flags,
3548                                                               actions,
3549                                                               attr,
3550                                                               error);
3551                         if (ret)
3552                                 return ret;
3553                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
3554                         ++actions_n;
3555                         break;
3556                 case RTE_FLOW_ACTION_TYPE_FLAG:
3557                         ret = mlx5_flow_validate_action_flag(action_flags,
3558                                                              attr, error);
3559                         if (ret < 0)
3560                                 return ret;
3561                         action_flags |= MLX5_FLOW_ACTION_FLAG;
3562                         ++actions_n;
3563                         break;
3564                 case RTE_FLOW_ACTION_TYPE_MARK:
3565                         ret = mlx5_flow_validate_action_mark(actions,
3566                                                              action_flags,
3567                                                              attr, error);
3568                         if (ret < 0)
3569                                 return ret;
3570                         action_flags |= MLX5_FLOW_ACTION_MARK;
3571                         ++actions_n;
3572                         break;
3573                 case RTE_FLOW_ACTION_TYPE_DROP:
3574                         ret = mlx5_flow_validate_action_drop(action_flags,
3575                                                              attr, error);
3576                         if (ret < 0)
3577                                 return ret;
3578                         action_flags |= MLX5_FLOW_ACTION_DROP;
3579                         ++actions_n;
3580                         break;
3581                 case RTE_FLOW_ACTION_TYPE_QUEUE:
3582                         ret = mlx5_flow_validate_action_queue(actions,
3583                                                               action_flags, dev,
3584                                                               attr, error);
3585                         if (ret < 0)
3586                                 return ret;
3587                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
3588                         ++actions_n;
3589                         break;
3590                 case RTE_FLOW_ACTION_TYPE_RSS:
3591                         ret = mlx5_flow_validate_action_rss(actions,
3592                                                             action_flags, dev,
3593                                                             attr, item_flags,
3594                                                             error);
3595                         if (ret < 0)
3596                                 return ret;
3597                         action_flags |= MLX5_FLOW_ACTION_RSS;
3598                         ++actions_n;
3599                         break;
3600                 case RTE_FLOW_ACTION_TYPE_COUNT:
3601                         ret = flow_dv_validate_action_count(dev, error);
3602                         if (ret < 0)
3603                                 return ret;
3604                         action_flags |= MLX5_FLOW_ACTION_COUNT;
3605                         ++actions_n;
3606                         break;
3607                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
3608                         if (flow_dv_validate_action_pop_vlan(dev,
3609                                                              action_flags,
3610                                                              actions,
3611                                                              item_flags, attr,
3612                                                              error))
3613                                 return -rte_errno;
3614                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
3615                         ++actions_n;
3616                         break;
3617                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
3618                         ret = flow_dv_validate_action_push_vlan(action_flags,
3619                                                                 actions, attr,
3620                                                                 error);
3621                         if (ret < 0)
3622                                 return ret;
3623                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
3624                         ++actions_n;
3625                         break;
3626                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
3627                         ret = flow_dv_validate_action_set_vlan_pcp
3628                                                 (action_flags, actions, error);
3629                         if (ret < 0)
3630                                 return ret;
3631                         /* Count PCP with push_vlan command. */
3632                         break;
3633                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
3634                         ret = flow_dv_validate_action_set_vlan_vid
3635                                                 (item_flags, actions, error);
3636                         if (ret < 0)
3637                                 return ret;
3638                         /* Count VID with push_vlan command. */
3639                         break;
3640                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
3641                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
3642                         ret = flow_dv_validate_action_l2_encap(action_flags,
3643                                                                actions, attr,
3644                                                                error);
3645                         if (ret < 0)
3646                                 return ret;
3647                         action_flags |= actions->type ==
3648                                         RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP ?
3649                                         MLX5_FLOW_ACTION_VXLAN_ENCAP :
3650                                         MLX5_FLOW_ACTION_NVGRE_ENCAP;
3651                         ++actions_n;
3652                         break;
3653                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
3654                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
3655                         ret = flow_dv_validate_action_l2_decap(action_flags,
3656                                                                attr, error);
3657                         if (ret < 0)
3658                                 return ret;
3659                         action_flags |= actions->type ==
3660                                         RTE_FLOW_ACTION_TYPE_VXLAN_DECAP ?
3661                                         MLX5_FLOW_ACTION_VXLAN_DECAP :
3662                                         MLX5_FLOW_ACTION_NVGRE_DECAP;
3663                         ++actions_n;
3664                         break;
3665                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
3666                         ret = flow_dv_validate_action_raw_encap(action_flags,
3667                                                                 actions, attr,
3668                                                                 error);
3669                         if (ret < 0)
3670                                 return ret;
3671                         action_flags |= MLX5_FLOW_ACTION_RAW_ENCAP;
3672                         ++actions_n;
3673                         break;
3674                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
3675                         ret = flow_dv_validate_action_raw_decap(action_flags,
3676                                                                 actions, attr,
3677                                                                 error);
3678                         if (ret < 0)
3679                                 return ret;
3680                         action_flags |= MLX5_FLOW_ACTION_RAW_DECAP;
3681                         ++actions_n;
3682                         break;
3683                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
3684                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
3685                         ret = flow_dv_validate_action_modify_mac(action_flags,
3686                                                                  actions,
3687                                                                  item_flags,
3688                                                                  error);
3689                         if (ret < 0)
3690                                 return ret;
3691                         /* Count all modify-header actions as one action. */
3692                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
3693                                 ++actions_n;
3694                         action_flags |= actions->type ==
3695                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
3696                                                 MLX5_FLOW_ACTION_SET_MAC_SRC :
3697                                                 MLX5_FLOW_ACTION_SET_MAC_DST;
3698                         break;
3699
3700                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
3701                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
3702                         ret = flow_dv_validate_action_modify_ipv4(action_flags,
3703                                                                   actions,
3704                                                                   item_flags,
3705                                                                   error);
3706                         if (ret < 0)
3707                                 return ret;
3708                         /* Count all modify-header actions as one action. */
3709                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
3710                                 ++actions_n;
3711                         action_flags |= actions->type ==
3712                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
3713                                                 MLX5_FLOW_ACTION_SET_IPV4_SRC :
3714                                                 MLX5_FLOW_ACTION_SET_IPV4_DST;
3715                         break;
3716                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
3717                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
3718                         ret = flow_dv_validate_action_modify_ipv6(action_flags,
3719                                                                   actions,
3720                                                                   item_flags,
3721                                                                   error);
3722                         if (ret < 0)
3723                                 return ret;
3724                         /* Count all modify-header actions as one action. */
3725                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
3726                                 ++actions_n;
3727                         action_flags |= actions->type ==
3728                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
3729                                                 MLX5_FLOW_ACTION_SET_IPV6_SRC :
3730                                                 MLX5_FLOW_ACTION_SET_IPV6_DST;
3731                         break;
3732                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
3733                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
3734                         ret = flow_dv_validate_action_modify_tp(action_flags,
3735                                                                 actions,
3736                                                                 item_flags,
3737                                                                 error);
3738                         if (ret < 0)
3739                                 return ret;
3740                         /* Count all modify-header actions as one action. */
3741                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
3742                                 ++actions_n;
3743                         action_flags |= actions->type ==
3744                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
3745                                                 MLX5_FLOW_ACTION_SET_TP_SRC :
3746                                                 MLX5_FLOW_ACTION_SET_TP_DST;
3747                         break;
3748                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
3749                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
3750                         ret = flow_dv_validate_action_modify_ttl(action_flags,
3751                                                                  actions,
3752                                                                  item_flags,
3753                                                                  error);
3754                         if (ret < 0)
3755                                 return ret;
3756                         /* Count all modify-header actions as one action. */
3757                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
3758                                 ++actions_n;
3759                         action_flags |= actions->type ==
3760                                         RTE_FLOW_ACTION_TYPE_SET_TTL ?
3761                                                 MLX5_FLOW_ACTION_SET_TTL :
3762                                                 MLX5_FLOW_ACTION_DEC_TTL;
3763                         break;
3764                 case RTE_FLOW_ACTION_TYPE_JUMP:
3765                         ret = flow_dv_validate_action_jump(actions,
3766                                                            action_flags,
3767                                                            attr, external,
3768                                                            error);
3769                         if (ret)
3770                                 return ret;
3771                         ++actions_n;
3772                         action_flags |= MLX5_FLOW_ACTION_JUMP;
3773                         break;
3774                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
3775                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
3776                         ret = flow_dv_validate_action_modify_tcp_seq
3777                                                                 (action_flags,
3778                                                                  actions,
3779                                                                  item_flags,
3780                                                                  error);
3781                         if (ret < 0)
3782                                 return ret;
3783                         /* Count all modify-header actions as one action. */
3784                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
3785                                 ++actions_n;
3786                         action_flags |= actions->type ==
3787                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
3788                                                 MLX5_FLOW_ACTION_INC_TCP_SEQ :
3789                                                 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
3790                         break;
3791                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
3792                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
3793                         ret = flow_dv_validate_action_modify_tcp_ack
3794                                                                 (action_flags,
3795                                                                  actions,
3796                                                                  item_flags,
3797                                                                  error);
3798                         if (ret < 0)
3799                                 return ret;
3800                         /* Count all modify-header actions as one action. */
3801                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
3802                                 ++actions_n;
3803                         action_flags |= actions->type ==
3804                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
3805                                                 MLX5_FLOW_ACTION_INC_TCP_ACK :
3806                                                 MLX5_FLOW_ACTION_DEC_TCP_ACK;
3807                         break;
3808                 default:
3809                         return rte_flow_error_set(error, ENOTSUP,
3810                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3811                                                   actions,
3812                                                   "action not supported");
3813                 }
3814         }
3815         if ((action_flags & MLX5_FLOW_LAYER_TUNNEL) &&
3816             (action_flags & MLX5_FLOW_VLAN_ACTIONS))
3817                 return rte_flow_error_set(error, ENOTSUP,
3818                                           RTE_FLOW_ERROR_TYPE_ACTION,
3819                                           actions,
3820                                           "can't have vxlan and vlan"
3821                                           " actions in the same rule");
3822         /* Eswitch has few restrictions on using items and actions */
3823         if (attr->transfer) {
3824                 if (action_flags & MLX5_FLOW_ACTION_FLAG)
3825                         return rte_flow_error_set(error, ENOTSUP,
3826                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3827                                                   NULL,
3828                                                   "unsupported action FLAG");
3829                 if (action_flags & MLX5_FLOW_ACTION_MARK)
3830                         return rte_flow_error_set(error, ENOTSUP,
3831                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3832                                                   NULL,
3833                                                   "unsupported action MARK");
3834                 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
3835                         return rte_flow_error_set(error, ENOTSUP,
3836                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3837                                                   NULL,
3838                                                   "unsupported action QUEUE");
3839                 if (action_flags & MLX5_FLOW_ACTION_RSS)
3840                         return rte_flow_error_set(error, ENOTSUP,
3841                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3842                                                   NULL,
3843                                                   "unsupported action RSS");
3844                 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3845                         return rte_flow_error_set(error, EINVAL,
3846                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3847                                                   actions,
3848                                                   "no fate action is found");
3849         } else {
3850                 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
3851                         return rte_flow_error_set(error, EINVAL,
3852                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3853                                                   actions,
3854                                                   "no fate action is found");
3855         }
3856         return 0;
3857 }
3858
3859 /**
3860  * Internal preparation function. Allocates the DV flow size,
3861  * this size is constant.
3862  *
3863  * @param[in] attr
3864  *   Pointer to the flow attributes.
3865  * @param[in] items
3866  *   Pointer to the list of items.
3867  * @param[in] actions
3868  *   Pointer to the list of actions.
3869  * @param[out] error
3870  *   Pointer to the error structure.
3871  *
3872  * @return
3873  *   Pointer to mlx5_flow object on success,
3874  *   otherwise NULL and rte_errno is set.
3875  */
3876 static struct mlx5_flow *
3877 flow_dv_prepare(const struct rte_flow_attr *attr __rte_unused,
3878                 const struct rte_flow_item items[] __rte_unused,
3879                 const struct rte_flow_action actions[] __rte_unused,
3880                 struct rte_flow_error *error)
3881 {
3882         uint32_t size = sizeof(struct mlx5_flow);
3883         struct mlx5_flow *flow;
3884
3885         flow = rte_calloc(__func__, 1, size, 0);
3886         if (!flow) {
3887                 rte_flow_error_set(error, ENOMEM,
3888                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3889                                    "not enough memory to create flow");
3890                 return NULL;
3891         }
3892         flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);
3893         return flow;
3894 }
3895
3896 #ifndef NDEBUG
3897 /**
3898  * Sanity check for match mask and value. Similar to check_valid_spec() in
3899  * kernel driver. If unmasked bit is present in value, it returns failure.
3900  *
3901  * @param match_mask
3902  *   pointer to match mask buffer.
3903  * @param match_value
3904  *   pointer to match value buffer.
3905  *
3906  * @return
3907  *   0 if valid, -EINVAL otherwise.
3908  */
3909 static int
3910 flow_dv_check_valid_spec(void *match_mask, void *match_value)
3911 {
3912         uint8_t *m = match_mask;
3913         uint8_t *v = match_value;
3914         unsigned int i;
3915
3916         for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
3917                 if (v[i] & ~m[i]) {
3918                         DRV_LOG(ERR,
3919                                 "match_value differs from match_criteria"
3920                                 " %p[%u] != %p[%u]",
3921                                 match_value, i, match_mask, i);
3922                         return -EINVAL;
3923                 }
3924         }
3925         return 0;
3926 }
3927 #endif
3928
3929 /**
3930  * Add Ethernet item to matcher and to the value.
3931  *
3932  * @param[in, out] matcher
3933  *   Flow matcher.
3934  * @param[in, out] key
3935  *   Flow matcher value.
3936  * @param[in] item
3937  *   Flow pattern to translate.
3938  * @param[in] inner
3939  *   Item is inner pattern.
3940  */
3941 static void
3942 flow_dv_translate_item_eth(void *matcher, void *key,
3943                            const struct rte_flow_item *item, int inner)
3944 {
3945         const struct rte_flow_item_eth *eth_m = item->mask;
3946         const struct rte_flow_item_eth *eth_v = item->spec;
3947         const struct rte_flow_item_eth nic_mask = {
3948                 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
3949                 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
3950                 .type = RTE_BE16(0xffff),
3951         };
3952         void *headers_m;
3953         void *headers_v;
3954         char *l24_v;
3955         unsigned int i;
3956
3957         if (!eth_v)
3958                 return;
3959         if (!eth_m)
3960                 eth_m = &nic_mask;
3961         if (inner) {
3962                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
3963                                          inner_headers);
3964                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
3965         } else {
3966                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
3967                                          outer_headers);
3968                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
3969         }
3970         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, dmac_47_16),
3971                &eth_m->dst, sizeof(eth_m->dst));
3972         /* The value must be in the range of the mask. */
3973         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, dmac_47_16);
3974         for (i = 0; i < sizeof(eth_m->dst); ++i)
3975                 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
3976         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, smac_47_16),
3977                &eth_m->src, sizeof(eth_m->src));
3978         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, smac_47_16);
3979         /* The value must be in the range of the mask. */
3980         for (i = 0; i < sizeof(eth_m->dst); ++i)
3981                 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
3982         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
3983                  rte_be_to_cpu_16(eth_m->type));
3984         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, ethertype);
3985         *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
3986 }
3987
3988 /**
3989  * Add VLAN item to matcher and to the value.
3990  *
3991  * @param[in, out] dev_flow
3992  *   Flow descriptor.
3993  * @param[in, out] matcher
3994  *   Flow matcher.
3995  * @param[in, out] key
3996  *   Flow matcher value.
3997  * @param[in] item
3998  *   Flow pattern to translate.
3999  * @param[in] inner
4000  *   Item is inner pattern.
4001  */
4002 static void
4003 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
4004                             void *matcher, void *key,
4005                             const struct rte_flow_item *item,
4006                             int inner)
4007 {
4008         const struct rte_flow_item_vlan *vlan_m = item->mask;
4009         const struct rte_flow_item_vlan *vlan_v = item->spec;
4010         void *headers_m;
4011         void *headers_v;
4012         uint16_t tci_m;
4013         uint16_t tci_v;
4014
4015         if (!vlan_v)
4016                 return;
4017         if (!vlan_m)
4018                 vlan_m = &rte_flow_item_vlan_mask;
4019         if (inner) {
4020                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4021                                          inner_headers);
4022                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4023         } else {
4024                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4025                                          outer_headers);
4026                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4027                 /*
4028                  * This is workaround, masks are not supported,
4029                  * and pre-validated.
4030                  */
4031                 dev_flow->dv.vf_vlan.tag =
4032                         rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
4033         }
4034         tci_m = rte_be_to_cpu_16(vlan_m->tci);
4035         tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
4036         MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
4037         MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
4038         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_vid, tci_m);
4039         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, tci_v);
4040         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_cfi, tci_m >> 12);
4041         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_cfi, tci_v >> 12);
4042         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_prio, tci_m >> 13);
4043         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, tci_v >> 13);
4044         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
4045                  rte_be_to_cpu_16(vlan_m->inner_type));
4046         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
4047                  rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
4048 }
4049
4050 /**
4051  * Add IPV4 item to matcher and to the value.
4052  *
4053  * @param[in, out] matcher
4054  *   Flow matcher.
4055  * @param[in, out] key
4056  *   Flow matcher value.
4057  * @param[in] item
4058  *   Flow pattern to translate.
4059  * @param[in] inner
4060  *   Item is inner pattern.
4061  * @param[in] group
4062  *   The group to insert the rule.
4063  */
4064 static void
4065 flow_dv_translate_item_ipv4(void *matcher, void *key,
4066                             const struct rte_flow_item *item,
4067                             int inner, uint32_t group)
4068 {
4069         const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
4070         const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
4071         const struct rte_flow_item_ipv4 nic_mask = {
4072                 .hdr = {
4073                         .src_addr = RTE_BE32(0xffffffff),
4074                         .dst_addr = RTE_BE32(0xffffffff),
4075                         .type_of_service = 0xff,
4076                         .next_proto_id = 0xff,
4077                 },
4078         };
4079         void *headers_m;
4080         void *headers_v;
4081         char *l24_m;
4082         char *l24_v;
4083         uint8_t tos;
4084
4085         if (inner) {
4086                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4087                                          inner_headers);
4088                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4089         } else {
4090                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4091                                          outer_headers);
4092                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4093         }
4094         if (group == 0)
4095                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
4096         else
4097                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x4);
4098         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 4);
4099         if (!ipv4_v)
4100                 return;
4101         if (!ipv4_m)
4102                 ipv4_m = &nic_mask;
4103         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
4104                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
4105         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
4106                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
4107         *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
4108         *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
4109         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
4110                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
4111         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
4112                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
4113         *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
4114         *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
4115         tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
4116         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
4117                  ipv4_m->hdr.type_of_service);
4118         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
4119         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
4120                  ipv4_m->hdr.type_of_service >> 2);
4121         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
4122         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
4123                  ipv4_m->hdr.next_proto_id);
4124         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
4125                  ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
4126 }
4127
4128 /**
4129  * Add IPV6 item to matcher and to the value.
4130  *
4131  * @param[in, out] matcher
4132  *   Flow matcher.
4133  * @param[in, out] key
4134  *   Flow matcher value.
4135  * @param[in] item
4136  *   Flow pattern to translate.
4137  * @param[in] inner
4138  *   Item is inner pattern.
4139  * @param[in] group
4140  *   The group to insert the rule.
4141  */
4142 static void
4143 flow_dv_translate_item_ipv6(void *matcher, void *key,
4144                             const struct rte_flow_item *item,
4145                             int inner, uint32_t group)
4146 {
4147         const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
4148         const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
4149         const struct rte_flow_item_ipv6 nic_mask = {
4150                 .hdr = {
4151                         .src_addr =
4152                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
4153                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
4154                         .dst_addr =
4155                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
4156                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
4157                         .vtc_flow = RTE_BE32(0xffffffff),
4158                         .proto = 0xff,
4159                         .hop_limits = 0xff,
4160                 },
4161         };
4162         void *headers_m;
4163         void *headers_v;
4164         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4165         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4166         char *l24_m;
4167         char *l24_v;
4168         uint32_t vtc_m;
4169         uint32_t vtc_v;
4170         int i;
4171         int size;
4172
4173         if (inner) {
4174                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4175                                          inner_headers);
4176                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4177         } else {
4178                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4179                                          outer_headers);
4180                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4181         }
4182         if (group == 0)
4183                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
4184         else
4185                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x6);
4186         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 6);
4187         if (!ipv6_v)
4188                 return;
4189         if (!ipv6_m)
4190                 ipv6_m = &nic_mask;
4191         size = sizeof(ipv6_m->hdr.dst_addr);
4192         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
4193                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
4194         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
4195                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
4196         memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
4197         for (i = 0; i < size; ++i)
4198                 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
4199         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
4200                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
4201         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
4202                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
4203         memcpy(l24_m, ipv6_m->hdr.src_addr, size);
4204         for (i = 0; i < size; ++i)
4205                 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
4206         /* TOS. */
4207         vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
4208         vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
4209         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
4210         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
4211         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
4212         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
4213         /* Label. */
4214         if (inner) {
4215                 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
4216                          vtc_m);
4217                 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
4218                          vtc_v);
4219         } else {
4220                 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
4221                          vtc_m);
4222                 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
4223                          vtc_v);
4224         }
4225         /* Protocol. */
4226         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
4227                  ipv6_m->hdr.proto);
4228         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
4229                  ipv6_v->hdr.proto & ipv6_m->hdr.proto);
4230 }
4231
4232 /**
4233  * Add TCP item to matcher and to the value.
4234  *
4235  * @param[in, out] matcher
4236  *   Flow matcher.
4237  * @param[in, out] key
4238  *   Flow matcher value.
4239  * @param[in] item
4240  *   Flow pattern to translate.
4241  * @param[in] inner
4242  *   Item is inner pattern.
4243  */
4244 static void
4245 flow_dv_translate_item_tcp(void *matcher, void *key,
4246                            const struct rte_flow_item *item,
4247                            int inner)
4248 {
4249         const struct rte_flow_item_tcp *tcp_m = item->mask;
4250         const struct rte_flow_item_tcp *tcp_v = item->spec;
4251         void *headers_m;
4252         void *headers_v;
4253
4254         if (inner) {
4255                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4256                                          inner_headers);
4257                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4258         } else {
4259                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4260                                          outer_headers);
4261                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4262         }
4263         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
4264         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
4265         if (!tcp_v)
4266                 return;
4267         if (!tcp_m)
4268                 tcp_m = &rte_flow_item_tcp_mask;
4269         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
4270                  rte_be_to_cpu_16(tcp_m->hdr.src_port));
4271         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
4272                  rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
4273         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
4274                  rte_be_to_cpu_16(tcp_m->hdr.dst_port));
4275         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
4276                  rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
4277         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
4278                  tcp_m->hdr.tcp_flags);
4279         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
4280                  (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
4281 }
4282
4283 /**
4284  * Add UDP item to matcher and to the value.
4285  *
4286  * @param[in, out] matcher
4287  *   Flow matcher.
4288  * @param[in, out] key
4289  *   Flow matcher value.
4290  * @param[in] item
4291  *   Flow pattern to translate.
4292  * @param[in] inner
4293  *   Item is inner pattern.
4294  */
4295 static void
4296 flow_dv_translate_item_udp(void *matcher, void *key,
4297                            const struct rte_flow_item *item,
4298                            int inner)
4299 {
4300         const struct rte_flow_item_udp *udp_m = item->mask;
4301         const struct rte_flow_item_udp *udp_v = item->spec;
4302         void *headers_m;
4303         void *headers_v;
4304
4305         if (inner) {
4306                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4307                                          inner_headers);
4308                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4309         } else {
4310                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4311                                          outer_headers);
4312                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4313         }
4314         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
4315         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
4316         if (!udp_v)
4317                 return;
4318         if (!udp_m)
4319                 udp_m = &rte_flow_item_udp_mask;
4320         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
4321                  rte_be_to_cpu_16(udp_m->hdr.src_port));
4322         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
4323                  rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
4324         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
4325                  rte_be_to_cpu_16(udp_m->hdr.dst_port));
4326         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
4327                  rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
4328 }
4329
4330 /**
4331  * Add GRE optional Key item to matcher and to the value.
4332  *
4333  * @param[in, out] matcher
4334  *   Flow matcher.
4335  * @param[in, out] key
4336  *   Flow matcher value.
4337  * @param[in] item
4338  *   Flow pattern to translate.
4339  * @param[in] inner
4340  *   Item is inner pattern.
4341  */
4342 static void
4343 flow_dv_translate_item_gre_key(void *matcher, void *key,
4344                                    const struct rte_flow_item *item)
4345 {
4346         const rte_be32_t *key_m = item->mask;
4347         const rte_be32_t *key_v = item->spec;
4348         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4349         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4350         rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
4351
4352         if (!key_v)
4353                 return;
4354         if (!key_m)
4355                 key_m = &gre_key_default_mask;
4356         /* GRE K bit must be on and should already be validated */
4357         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
4358         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
4359         MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
4360                  rte_be_to_cpu_32(*key_m) >> 8);
4361         MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
4362                  rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
4363         MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
4364                  rte_be_to_cpu_32(*key_m) & 0xFF);
4365         MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
4366                  rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
4367 }
4368
4369 /**
4370  * Add GRE item to matcher and to the value.
4371  *
4372  * @param[in, out] matcher
4373  *   Flow matcher.
4374  * @param[in, out] key
4375  *   Flow matcher value.
4376  * @param[in] item
4377  *   Flow pattern to translate.
4378  * @param[in] inner
4379  *   Item is inner pattern.
4380  */
4381 static void
4382 flow_dv_translate_item_gre(void *matcher, void *key,
4383                            const struct rte_flow_item *item,
4384                            int inner)
4385 {
4386         const struct rte_flow_item_gre *gre_m = item->mask;
4387         const struct rte_flow_item_gre *gre_v = item->spec;
4388         void *headers_m;
4389         void *headers_v;
4390         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4391         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4392         struct {
4393                 union {
4394                         __extension__
4395                         struct {
4396                                 uint16_t version:3;
4397                                 uint16_t rsvd0:9;
4398                                 uint16_t s_present:1;
4399                                 uint16_t k_present:1;
4400                                 uint16_t rsvd_bit1:1;
4401                                 uint16_t c_present:1;
4402                         };
4403                         uint16_t value;
4404                 };
4405         } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
4406
4407         if (inner) {
4408                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4409                                          inner_headers);
4410                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4411         } else {
4412                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4413                                          outer_headers);
4414                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4415         }
4416         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
4417         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
4418         if (!gre_v)
4419                 return;
4420         if (!gre_m)
4421                 gre_m = &rte_flow_item_gre_mask;
4422         MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
4423                  rte_be_to_cpu_16(gre_m->protocol));
4424         MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
4425                  rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
4426         gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
4427         gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
4428         MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
4429                  gre_crks_rsvd0_ver_m.c_present);
4430         MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
4431                  gre_crks_rsvd0_ver_v.c_present &
4432                  gre_crks_rsvd0_ver_m.c_present);
4433         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
4434                  gre_crks_rsvd0_ver_m.k_present);
4435         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
4436                  gre_crks_rsvd0_ver_v.k_present &
4437                  gre_crks_rsvd0_ver_m.k_present);
4438         MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
4439                  gre_crks_rsvd0_ver_m.s_present);
4440         MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
4441                  gre_crks_rsvd0_ver_v.s_present &
4442                  gre_crks_rsvd0_ver_m.s_present);
4443 }
4444
4445 /**
4446  * Add NVGRE item to matcher and to the value.
4447  *
4448  * @param[in, out] matcher
4449  *   Flow matcher.
4450  * @param[in, out] key
4451  *   Flow matcher value.
4452  * @param[in] item
4453  *   Flow pattern to translate.
4454  * @param[in] inner
4455  *   Item is inner pattern.
4456  */
4457 static void
4458 flow_dv_translate_item_nvgre(void *matcher, void *key,
4459                              const struct rte_flow_item *item,
4460                              int inner)
4461 {
4462         const struct rte_flow_item_nvgre *nvgre_m = item->mask;
4463         const struct rte_flow_item_nvgre *nvgre_v = item->spec;
4464         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4465         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4466         const char *tni_flow_id_m = (const char *)nvgre_m->tni;
4467         const char *tni_flow_id_v = (const char *)nvgre_v->tni;
4468         char *gre_key_m;
4469         char *gre_key_v;
4470         int size;
4471         int i;
4472
4473         /* For NVGRE, GRE header fields must be set with defined values. */
4474         const struct rte_flow_item_gre gre_spec = {
4475                 .c_rsvd0_ver = RTE_BE16(0x2000),
4476                 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
4477         };
4478         const struct rte_flow_item_gre gre_mask = {
4479                 .c_rsvd0_ver = RTE_BE16(0xB000),
4480                 .protocol = RTE_BE16(UINT16_MAX),
4481         };
4482         const struct rte_flow_item gre_item = {
4483                 .spec = &gre_spec,
4484                 .mask = &gre_mask,
4485                 .last = NULL,
4486         };
4487         flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
4488         if (!nvgre_v)
4489                 return;
4490         if (!nvgre_m)
4491                 nvgre_m = &rte_flow_item_nvgre_mask;
4492         size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
4493         gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
4494         gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
4495         memcpy(gre_key_m, tni_flow_id_m, size);
4496         for (i = 0; i < size; ++i)
4497                 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
4498 }
4499
4500 /**
4501  * Add VXLAN item to matcher and to the value.
4502  *
4503  * @param[in, out] matcher
4504  *   Flow matcher.
4505  * @param[in, out] key
4506  *   Flow matcher value.
4507  * @param[in] item
4508  *   Flow pattern to translate.
4509  * @param[in] inner
4510  *   Item is inner pattern.
4511  */
4512 static void
4513 flow_dv_translate_item_vxlan(void *matcher, void *key,
4514                              const struct rte_flow_item *item,
4515                              int inner)
4516 {
4517         const struct rte_flow_item_vxlan *vxlan_m = item->mask;
4518         const struct rte_flow_item_vxlan *vxlan_v = item->spec;
4519         void *headers_m;
4520         void *headers_v;
4521         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4522         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4523         char *vni_m;
4524         char *vni_v;
4525         uint16_t dport;
4526         int size;
4527         int i;
4528
4529         if (inner) {
4530                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4531                                          inner_headers);
4532                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4533         } else {
4534                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4535                                          outer_headers);
4536                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4537         }
4538         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
4539                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
4540         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
4541                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
4542                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
4543         }
4544         if (!vxlan_v)
4545                 return;
4546         if (!vxlan_m)
4547                 vxlan_m = &rte_flow_item_vxlan_mask;
4548         size = sizeof(vxlan_m->vni);
4549         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
4550         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
4551         memcpy(vni_m, vxlan_m->vni, size);
4552         for (i = 0; i < size; ++i)
4553                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
4554 }
4555
4556 /**
4557  * Add Geneve item to matcher and to the value.
4558  *
4559  * @param[in, out] matcher
4560  *   Flow matcher.
4561  * @param[in, out] key
4562  *   Flow matcher value.
4563  * @param[in] item
4564  *   Flow pattern to translate.
4565  * @param[in] inner
4566  *   Item is inner pattern.
4567  */
4568
4569 static void
4570 flow_dv_translate_item_geneve(void *matcher, void *key,
4571                               const struct rte_flow_item *item, int inner)
4572 {
4573         const struct rte_flow_item_geneve *geneve_m = item->mask;
4574         const struct rte_flow_item_geneve *geneve_v = item->spec;
4575         void *headers_m;
4576         void *headers_v;
4577         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4578         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4579         uint16_t dport;
4580         uint16_t gbhdr_m;
4581         uint16_t gbhdr_v;
4582         char *vni_m;
4583         char *vni_v;
4584         size_t size, i;
4585
4586         if (inner) {
4587                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4588                                          inner_headers);
4589                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4590         } else {
4591                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4592                                          outer_headers);
4593                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4594         }
4595         dport = MLX5_UDP_PORT_GENEVE;
4596         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
4597                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
4598                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
4599         }
4600         if (!geneve_v)
4601                 return;
4602         if (!geneve_m)
4603                 geneve_m = &rte_flow_item_geneve_mask;
4604         size = sizeof(geneve_m->vni);
4605         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
4606         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
4607         memcpy(vni_m, geneve_m->vni, size);
4608         for (i = 0; i < size; ++i)
4609                 vni_v[i] = vni_m[i] & geneve_v->vni[i];
4610         MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
4611                  rte_be_to_cpu_16(geneve_m->protocol));
4612         MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
4613                  rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
4614         gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
4615         gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
4616         MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
4617                  MLX5_GENEVE_OAMF_VAL(gbhdr_m));
4618         MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
4619                  MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
4620         MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
4621                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
4622         MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
4623                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
4624                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
4625 }
4626
4627 /**
4628  * Add MPLS item to matcher and to the value.
4629  *
4630  * @param[in, out] matcher
4631  *   Flow matcher.
4632  * @param[in, out] key
4633  *   Flow matcher value.
4634  * @param[in] item
4635  *   Flow pattern to translate.
4636  * @param[in] prev_layer
4637  *   The protocol layer indicated in previous item.
4638  * @param[in] inner
4639  *   Item is inner pattern.
4640  */
4641 static void
4642 flow_dv_translate_item_mpls(void *matcher, void *key,
4643                             const struct rte_flow_item *item,
4644                             uint64_t prev_layer,
4645                             int inner)
4646 {
4647         const uint32_t *in_mpls_m = item->mask;
4648         const uint32_t *in_mpls_v = item->spec;
4649         uint32_t *out_mpls_m = 0;
4650         uint32_t *out_mpls_v = 0;
4651         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4652         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4653         void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
4654                                      misc_parameters_2);
4655         void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
4656         void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
4657         void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4658
4659         switch (prev_layer) {
4660         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
4661                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
4662                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
4663                          MLX5_UDP_PORT_MPLS);
4664                 break;
4665         case MLX5_FLOW_LAYER_GRE:
4666                 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
4667                 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
4668                          RTE_ETHER_TYPE_MPLS);
4669                 break;
4670         default:
4671                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
4672                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
4673                          IPPROTO_MPLS);
4674                 break;
4675         }
4676         if (!in_mpls_v)
4677                 return;
4678         if (!in_mpls_m)
4679                 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
4680         switch (prev_layer) {
4681         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
4682                 out_mpls_m =
4683                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
4684                                                  outer_first_mpls_over_udp);
4685                 out_mpls_v =
4686                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
4687                                                  outer_first_mpls_over_udp);
4688                 break;
4689         case MLX5_FLOW_LAYER_GRE:
4690                 out_mpls_m =
4691                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
4692                                                  outer_first_mpls_over_gre);
4693                 out_mpls_v =
4694                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
4695                                                  outer_first_mpls_over_gre);
4696                 break;
4697         default:
4698                 /* Inner MPLS not over GRE is not supported. */
4699                 if (!inner) {
4700                         out_mpls_m =
4701                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
4702                                                          misc2_m,
4703                                                          outer_first_mpls);
4704                         out_mpls_v =
4705                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
4706                                                          misc2_v,
4707                                                          outer_first_mpls);
4708                 }
4709                 break;
4710         }
4711         if (out_mpls_m && out_mpls_v) {
4712                 *out_mpls_m = *in_mpls_m;
4713                 *out_mpls_v = *in_mpls_v & *in_mpls_m;
4714         }
4715 }
4716
4717 /**
4718  * Add META item to matcher
4719  *
4720  * @param[in, out] matcher
4721  *   Flow matcher.
4722  * @param[in, out] key
4723  *   Flow matcher value.
4724  * @param[in] item
4725  *   Flow pattern to translate.
4726  * @param[in] inner
4727  *   Item is inner pattern.
4728  */
4729 static void
4730 flow_dv_translate_item_meta(void *matcher, void *key,
4731                             const struct rte_flow_item *item)
4732 {
4733         const struct rte_flow_item_meta *meta_m;
4734         const struct rte_flow_item_meta *meta_v;
4735         void *misc2_m =
4736                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
4737         void *misc2_v =
4738                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
4739
4740         meta_m = (const void *)item->mask;
4741         if (!meta_m)
4742                 meta_m = &rte_flow_item_meta_mask;
4743         meta_v = (const void *)item->spec;
4744         if (meta_v) {
4745                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a,
4746                          rte_be_to_cpu_32(meta_m->data));
4747                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a,
4748                          rte_be_to_cpu_32(meta_v->data & meta_m->data));
4749         }
4750 }
4751
4752 /**
4753  * Add vport metadata Reg C0 item to matcher
4754  *
4755  * @param[in, out] matcher
4756  *   Flow matcher.
4757  * @param[in, out] key
4758  *   Flow matcher value.
4759  * @param[in] reg
4760  *   Flow pattern to translate.
4761  */
4762 static void
4763 flow_dv_translate_item_meta_vport(void *matcher, void *key,
4764                                   uint32_t value, uint32_t mask)
4765 {
4766         void *misc2_m =
4767                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
4768         void *misc2_v =
4769                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
4770
4771         MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, mask);
4772         MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, value);
4773 }
4774
4775 /**
4776  * Add tag item to matcher
4777  *
4778  * @param[in, out] matcher
4779  *   Flow matcher.
4780  * @param[in, out] key
4781  *   Flow matcher value.
4782  * @param[in] item
4783  *   Flow pattern to translate.
4784  */
4785 static void
4786 flow_dv_translate_item_tag(void *matcher, void *key,
4787                            const struct rte_flow_item *item)
4788 {
4789         void *misc2_m =
4790                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
4791         void *misc2_v =
4792                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
4793         const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
4794         const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
4795         enum modify_reg reg = tag_v->id;
4796         rte_be32_t value = tag_v->data;
4797         rte_be32_t mask = tag_m->data;
4798
4799         switch (reg) {
4800         case REG_A:
4801                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a,
4802                                 rte_be_to_cpu_32(mask));
4803                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a,
4804                                 rte_be_to_cpu_32(value));
4805                 break;
4806         case REG_B:
4807                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b,
4808                                  rte_be_to_cpu_32(mask));
4809                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b,
4810                                 rte_be_to_cpu_32(value));
4811                 break;
4812         case REG_C_0:
4813                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0,
4814                                  rte_be_to_cpu_32(mask));
4815                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0,
4816                                 rte_be_to_cpu_32(value));
4817                 break;
4818         case REG_C_1:
4819                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1,
4820                                  rte_be_to_cpu_32(mask));
4821                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1,
4822                                 rte_be_to_cpu_32(value));
4823                 break;
4824         case REG_C_2:
4825                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2,
4826                                  rte_be_to_cpu_32(mask));
4827                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2,
4828                                 rte_be_to_cpu_32(value));
4829                 break;
4830         case REG_C_3:
4831                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3,
4832                                  rte_be_to_cpu_32(mask));
4833                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3,
4834                                 rte_be_to_cpu_32(value));
4835                 break;
4836         case REG_C_4:
4837                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4,
4838                                  rte_be_to_cpu_32(mask));
4839                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4,
4840                                 rte_be_to_cpu_32(value));
4841                 break;
4842         case REG_C_5:
4843                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5,
4844                                  rte_be_to_cpu_32(mask));
4845                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5,
4846                                 rte_be_to_cpu_32(value));
4847                 break;
4848         case REG_C_6:
4849                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6,
4850                                  rte_be_to_cpu_32(mask));
4851                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6,
4852                                 rte_be_to_cpu_32(value));
4853                 break;
4854         case REG_C_7:
4855                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7,
4856                                  rte_be_to_cpu_32(mask));
4857                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7,
4858                                 rte_be_to_cpu_32(value));
4859                 break;
4860         }
4861 }
4862
4863 /**
4864  * Add source vport match to the specified matcher.
4865  *
4866  * @param[in, out] matcher
4867  *   Flow matcher.
4868  * @param[in, out] key
4869  *   Flow matcher value.
4870  * @param[in] port
4871  *   Source vport value to match
4872  * @param[in] mask
4873  *   Mask
4874  */
4875 static void
4876 flow_dv_translate_item_source_vport(void *matcher, void *key,
4877                                     int16_t port, uint16_t mask)
4878 {
4879         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4880         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4881
4882         MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
4883         MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
4884 }
4885
4886 /**
4887  * Translate port-id item to eswitch match on  port-id.
4888  *
4889  * @param[in] dev
4890  *   The devich to configure through.
4891  * @param[in, out] matcher
4892  *   Flow matcher.
4893  * @param[in, out] key
4894  *   Flow matcher value.
4895  * @param[in] item
4896  *   Flow pattern to translate.
4897  *
4898  * @return
4899  *   0 on success, a negative errno value otherwise.
4900  */
4901 static int
4902 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
4903                                void *key, const struct rte_flow_item *item)
4904 {
4905         const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
4906         const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
4907         struct mlx5_priv *priv;
4908         uint16_t mask, id;
4909
4910         mask = pid_m ? pid_m->id : 0xffff;
4911         id = pid_v ? pid_v->id : dev->data->port_id;
4912         priv = mlx5_port_to_eswitch_info(id);
4913         if (!priv)
4914                 return -rte_errno;
4915         /* Translate to vport field or to metadata, depending on mode. */
4916         if (priv->vport_meta_mask)
4917                 flow_dv_translate_item_meta_vport(matcher, key,
4918                                                   priv->vport_meta_tag,
4919                                                   priv->vport_meta_mask);
4920         else
4921                 flow_dv_translate_item_source_vport(matcher, key,
4922                                                     priv->vport_id, mask);
4923         return 0;
4924 }
4925
4926 /**
4927  * Add ICMP6 item to matcher and to the value.
4928  *
4929  * @param[in, out] matcher
4930  *   Flow matcher.
4931  * @param[in, out] key
4932  *   Flow matcher value.
4933  * @param[in] item
4934  *   Flow pattern to translate.
4935  * @param[in] inner
4936  *   Item is inner pattern.
4937  */
4938 static void
4939 flow_dv_translate_item_icmp6(void *matcher, void *key,
4940                               const struct rte_flow_item *item,
4941                               int inner)
4942 {
4943         const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
4944         const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
4945         void *headers_m;
4946         void *headers_v;
4947         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
4948                                      misc_parameters_3);
4949         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
4950         if (inner) {
4951                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4952                                          inner_headers);
4953                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4954         } else {
4955                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4956                                          outer_headers);
4957                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4958         }
4959         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
4960         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
4961         if (!icmp6_v)
4962                 return;
4963         if (!icmp6_m)
4964                 icmp6_m = &rte_flow_item_icmp6_mask;
4965         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
4966         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
4967                  icmp6_v->type & icmp6_m->type);
4968         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
4969         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
4970                  icmp6_v->code & icmp6_m->code);
4971 }
4972
4973 /**
4974  * Add ICMP item to matcher and to the value.
4975  *
4976  * @param[in, out] matcher
4977  *   Flow matcher.
4978  * @param[in, out] key
4979  *   Flow matcher value.
4980  * @param[in] item
4981  *   Flow pattern to translate.
4982  * @param[in] inner
4983  *   Item is inner pattern.
4984  */
4985 static void
4986 flow_dv_translate_item_icmp(void *matcher, void *key,
4987                             const struct rte_flow_item *item,
4988                             int inner)
4989 {
4990         const struct rte_flow_item_icmp *icmp_m = item->mask;
4991         const struct rte_flow_item_icmp *icmp_v = item->spec;
4992         void *headers_m;
4993         void *headers_v;
4994         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
4995                                      misc_parameters_3);
4996         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
4997         if (inner) {
4998                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4999                                          inner_headers);
5000                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5001         } else {
5002                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5003                                          outer_headers);
5004                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5005         }
5006         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
5007         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
5008         if (!icmp_v)
5009                 return;
5010         if (!icmp_m)
5011                 icmp_m = &rte_flow_item_icmp_mask;
5012         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
5013                  icmp_m->hdr.icmp_type);
5014         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
5015                  icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
5016         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
5017                  icmp_m->hdr.icmp_code);
5018         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
5019                  icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
5020 }
5021
5022 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
5023
5024 #define HEADER_IS_ZERO(match_criteria, headers)                              \
5025         !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers),     \
5026                  matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
5027
5028 /**
5029  * Calculate flow matcher enable bitmap.
5030  *
5031  * @param match_criteria
5032  *   Pointer to flow matcher criteria.
5033  *
5034  * @return
5035  *   Bitmap of enabled fields.
5036  */
5037 static uint8_t
5038 flow_dv_matcher_enable(uint32_t *match_criteria)
5039 {
5040         uint8_t match_criteria_enable;
5041
5042         match_criteria_enable =
5043                 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
5044                 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
5045         match_criteria_enable |=
5046                 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
5047                 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
5048         match_criteria_enable |=
5049                 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
5050                 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
5051         match_criteria_enable |=
5052                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
5053                 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
5054         match_criteria_enable |=
5055                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
5056                 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
5057         return match_criteria_enable;
5058 }
5059
5060
5061 /**
5062  * Get a flow table.
5063  *
5064  * @param dev[in, out]
5065  *   Pointer to rte_eth_dev structure.
5066  * @param[in] table_id
5067  *   Table id to use.
5068  * @param[in] egress
5069  *   Direction of the table.
5070  * @param[in] transfer
5071  *   E-Switch or NIC flow.
5072  * @param[out] error
5073  *   pointer to error structure.
5074  *
5075  * @return
5076  *   Returns tables resource based on the index, NULL in case of failed.
5077  */
5078 static struct mlx5_flow_tbl_resource *
5079 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
5080                          uint32_t table_id, uint8_t egress,
5081                          uint8_t transfer,
5082                          struct rte_flow_error *error)
5083 {
5084         struct mlx5_priv *priv = dev->data->dev_private;
5085         struct mlx5_ibv_shared *sh = priv->sh;
5086         struct mlx5_flow_tbl_resource *tbl;
5087
5088 #ifdef HAVE_MLX5DV_DR
5089         if (transfer) {
5090                 tbl = &sh->fdb_tbl[table_id];
5091                 if (!tbl->obj)
5092                         tbl->obj = mlx5_glue->dr_create_flow_tbl
5093                                 (sh->fdb_domain, table_id);
5094         } else if (egress) {
5095                 tbl = &sh->tx_tbl[table_id];
5096                 if (!tbl->obj)
5097                         tbl->obj = mlx5_glue->dr_create_flow_tbl
5098                                 (sh->tx_domain, table_id);
5099         } else {
5100                 tbl = &sh->rx_tbl[table_id];
5101                 if (!tbl->obj)
5102                         tbl->obj = mlx5_glue->dr_create_flow_tbl
5103                                 (sh->rx_domain, table_id);
5104         }
5105         if (!tbl->obj) {
5106                 rte_flow_error_set(error, ENOMEM,
5107                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5108                                    NULL, "cannot create table");
5109                 return NULL;
5110         }
5111         rte_atomic32_inc(&tbl->refcnt);
5112         return tbl;
5113 #else
5114         (void)error;
5115         (void)tbl;
5116         if (transfer)
5117                 return &sh->fdb_tbl[table_id];
5118         else if (egress)
5119                 return &sh->tx_tbl[table_id];
5120         else
5121                 return &sh->rx_tbl[table_id];
5122 #endif
5123 }
5124
5125 /**
5126  * Release a flow table.
5127  *
5128  * @param[in] tbl
5129  *   Table resource to be released.
5130  *
5131  * @return
5132  *   Returns 0 if table was released, else return 1;
5133  */
5134 static int
5135 flow_dv_tbl_resource_release(struct mlx5_flow_tbl_resource *tbl)
5136 {
5137         if (!tbl)
5138                 return 0;
5139         if (rte_atomic32_dec_and_test(&tbl->refcnt)) {
5140                 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
5141                 tbl->obj = NULL;
5142                 return 0;
5143         }
5144         return 1;
5145 }
5146
5147 /**
5148  * Register the flow matcher.
5149  *
5150  * @param dev[in, out]
5151  *   Pointer to rte_eth_dev structure.
5152  * @param[in, out] matcher
5153  *   Pointer to flow matcher.
5154  * @parm[in, out] dev_flow
5155  *   Pointer to the dev_flow.
5156  * @param[out] error
5157  *   pointer to error structure.
5158  *
5159  * @return
5160  *   0 on success otherwise -errno and errno is set.
5161  */
5162 static int
5163 flow_dv_matcher_register(struct rte_eth_dev *dev,
5164                          struct mlx5_flow_dv_matcher *matcher,
5165                          struct mlx5_flow *dev_flow,
5166                          struct rte_flow_error *error)
5167 {
5168         struct mlx5_priv *priv = dev->data->dev_private;
5169         struct mlx5_ibv_shared *sh = priv->sh;
5170         struct mlx5_flow_dv_matcher *cache_matcher;
5171         struct mlx5dv_flow_matcher_attr dv_attr = {
5172                 .type = IBV_FLOW_ATTR_NORMAL,
5173                 .match_mask = (void *)&matcher->mask,
5174         };
5175         struct mlx5_flow_tbl_resource *tbl = NULL;
5176
5177         /* Lookup from cache. */
5178         LIST_FOREACH(cache_matcher, &sh->matchers, next) {
5179                 if (matcher->crc == cache_matcher->crc &&
5180                     matcher->priority == cache_matcher->priority &&
5181                     matcher->egress == cache_matcher->egress &&
5182                     matcher->group == cache_matcher->group &&
5183                     matcher->transfer == cache_matcher->transfer &&
5184                     !memcmp((const void *)matcher->mask.buf,
5185                             (const void *)cache_matcher->mask.buf,
5186                             cache_matcher->mask.size)) {
5187                         DRV_LOG(DEBUG,
5188                                 "priority %hd use %s matcher %p: refcnt %d++",
5189                                 cache_matcher->priority,
5190                                 cache_matcher->egress ? "tx" : "rx",
5191                                 (void *)cache_matcher,
5192                                 rte_atomic32_read(&cache_matcher->refcnt));
5193                         rte_atomic32_inc(&cache_matcher->refcnt);
5194                         dev_flow->dv.matcher = cache_matcher;
5195                         return 0;
5196                 }
5197         }
5198         /* Register new matcher. */
5199         cache_matcher = rte_calloc(__func__, 1, sizeof(*cache_matcher), 0);
5200         if (!cache_matcher)
5201                 return rte_flow_error_set(error, ENOMEM,
5202                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5203                                           "cannot allocate matcher memory");
5204         tbl = flow_dv_tbl_resource_get(dev, matcher->group,
5205                                        matcher->egress, matcher->transfer,
5206                                        error);
5207         if (!tbl) {
5208                 rte_free(cache_matcher);
5209                 return rte_flow_error_set(error, ENOMEM,
5210                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5211                                           NULL, "cannot create table");
5212         }
5213         *cache_matcher = *matcher;
5214         dv_attr.match_criteria_enable =
5215                 flow_dv_matcher_enable(cache_matcher->mask.buf);
5216         dv_attr.priority = matcher->priority;
5217         if (matcher->egress)
5218                 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
5219         cache_matcher->matcher_object =
5220                 mlx5_glue->dv_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj);
5221         if (!cache_matcher->matcher_object) {
5222                 rte_free(cache_matcher);
5223 #ifdef HAVE_MLX5DV_DR
5224                 flow_dv_tbl_resource_release(tbl);
5225 #endif
5226                 return rte_flow_error_set(error, ENOMEM,
5227                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5228                                           NULL, "cannot create matcher");
5229         }
5230         rte_atomic32_inc(&cache_matcher->refcnt);
5231         LIST_INSERT_HEAD(&sh->matchers, cache_matcher, next);
5232         dev_flow->dv.matcher = cache_matcher;
5233         DRV_LOG(DEBUG, "priority %hd new %s matcher %p: refcnt %d",
5234                 cache_matcher->priority,
5235                 cache_matcher->egress ? "tx" : "rx", (void *)cache_matcher,
5236                 rte_atomic32_read(&cache_matcher->refcnt));
5237         rte_atomic32_inc(&tbl->refcnt);
5238         return 0;
5239 }
5240
5241 /**
5242  * Find existing tag resource or create and register a new one.
5243  *
5244  * @param dev[in, out]
5245  *   Pointer to rte_eth_dev structure.
5246  * @param[in, out] resource
5247  *   Pointer to tag resource.
5248  * @parm[in, out] dev_flow
5249  *   Pointer to the dev_flow.
5250  * @param[out] error
5251  *   pointer to error structure.
5252  *
5253  * @return
5254  *   0 on success otherwise -errno and errno is set.
5255  */
5256 static int
5257 flow_dv_tag_resource_register
5258                         (struct rte_eth_dev *dev,
5259                          struct mlx5_flow_dv_tag_resource *resource,
5260                          struct mlx5_flow *dev_flow,
5261                          struct rte_flow_error *error)
5262 {
5263         struct mlx5_priv *priv = dev->data->dev_private;
5264         struct mlx5_ibv_shared *sh = priv->sh;
5265         struct mlx5_flow_dv_tag_resource *cache_resource;
5266
5267         /* Lookup a matching resource from cache. */
5268         LIST_FOREACH(cache_resource, &sh->tags, next) {
5269                 if (resource->tag == cache_resource->tag) {
5270                         DRV_LOG(DEBUG, "tag resource %p: refcnt %d++",
5271                                 (void *)cache_resource,
5272                                 rte_atomic32_read(&cache_resource->refcnt));
5273                         rte_atomic32_inc(&cache_resource->refcnt);
5274                         dev_flow->flow->tag_resource = cache_resource;
5275                         return 0;
5276                 }
5277         }
5278         /* Register new  resource. */
5279         cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
5280         if (!cache_resource)
5281                 return rte_flow_error_set(error, ENOMEM,
5282                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5283                                           "cannot allocate resource memory");
5284         *cache_resource = *resource;
5285         cache_resource->action = mlx5_glue->dv_create_flow_action_tag
5286                 (resource->tag);
5287         if (!cache_resource->action) {
5288                 rte_free(cache_resource);
5289                 return rte_flow_error_set(error, ENOMEM,
5290                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5291                                           NULL, "cannot create action");
5292         }
5293         rte_atomic32_init(&cache_resource->refcnt);
5294         rte_atomic32_inc(&cache_resource->refcnt);
5295         LIST_INSERT_HEAD(&sh->tags, cache_resource, next);
5296         dev_flow->flow->tag_resource = cache_resource;
5297         DRV_LOG(DEBUG, "new tag resource %p: refcnt %d++",
5298                 (void *)cache_resource,
5299                 rte_atomic32_read(&cache_resource->refcnt));
5300         return 0;
5301 }
5302
5303 /**
5304  * Release the tag.
5305  *
5306  * @param dev
5307  *   Pointer to Ethernet device.
5308  * @param flow
5309  *   Pointer to mlx5_flow.
5310  *
5311  * @return
5312  *   1 while a reference on it exists, 0 when freed.
5313  */
5314 static int
5315 flow_dv_tag_release(struct rte_eth_dev *dev,
5316                     struct mlx5_flow_dv_tag_resource *tag)
5317 {
5318         assert(tag);
5319         DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
5320                 dev->data->port_id, (void *)tag,
5321                 rte_atomic32_read(&tag->refcnt));
5322         if (rte_atomic32_dec_and_test(&tag->refcnt)) {
5323                 claim_zero(mlx5_glue->destroy_flow_action(tag->action));
5324                 LIST_REMOVE(tag, next);
5325                 DRV_LOG(DEBUG, "port %u tag %p: removed",
5326                         dev->data->port_id, (void *)tag);
5327                 rte_free(tag);
5328                 return 0;
5329         }
5330         return 1;
5331 }
5332
5333 /**
5334  * Translate port ID action to vport.
5335  *
5336  * @param[in] dev
5337  *   Pointer to rte_eth_dev structure.
5338  * @param[in] action
5339  *   Pointer to the port ID action.
5340  * @param[out] dst_port_id
5341  *   The target port ID.
5342  * @param[out] error
5343  *   Pointer to the error structure.
5344  *
5345  * @return
5346  *   0 on success, a negative errno value otherwise and rte_errno is set.
5347  */
5348 static int
5349 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
5350                                  const struct rte_flow_action *action,
5351                                  uint32_t *dst_port_id,
5352                                  struct rte_flow_error *error)
5353 {
5354         uint32_t port;
5355         struct mlx5_priv *priv;
5356         const struct rte_flow_action_port_id *conf =
5357                         (const struct rte_flow_action_port_id *)action->conf;
5358
5359         port = conf->original ? dev->data->port_id : conf->id;
5360         priv = mlx5_port_to_eswitch_info(port);
5361         if (!priv)
5362                 return rte_flow_error_set(error, -rte_errno,
5363                                           RTE_FLOW_ERROR_TYPE_ACTION,
5364                                           NULL,
5365                                           "No eswitch info was found for port");
5366         if (priv->vport_meta_mask)
5367                 *dst_port_id = priv->vport_meta_tag;
5368         else
5369                 *dst_port_id = priv->vport_id;
5370         return 0;
5371 }
5372
5373 /**
5374  * Fill the flow with DV spec.
5375  *
5376  * @param[in] dev
5377  *   Pointer to rte_eth_dev structure.
5378  * @param[in, out] dev_flow
5379  *   Pointer to the sub flow.
5380  * @param[in] attr
5381  *   Pointer to the flow attributes.
5382  * @param[in] items
5383  *   Pointer to the list of items.
5384  * @param[in] actions
5385  *   Pointer to the list of actions.
5386  * @param[out] error
5387  *   Pointer to the error structure.
5388  *
5389  * @return
5390  *   0 on success, a negative errno value otherwise and rte_errno is set.
5391  */
5392 static int
5393 flow_dv_translate(struct rte_eth_dev *dev,
5394                   struct mlx5_flow *dev_flow,
5395                   const struct rte_flow_attr *attr,
5396                   const struct rte_flow_item items[],
5397                   const struct rte_flow_action actions[],
5398                   struct rte_flow_error *error)
5399 {
5400         struct mlx5_priv *priv = dev->data->dev_private;
5401         struct rte_flow *flow = dev_flow->flow;
5402         uint64_t item_flags = 0;
5403         uint64_t last_item = 0;
5404         uint64_t action_flags = 0;
5405         uint64_t priority = attr->priority;
5406         struct mlx5_flow_dv_matcher matcher = {
5407                 .mask = {
5408                         .size = sizeof(matcher.mask.buf),
5409                 },
5410         };
5411         int actions_n = 0;
5412         bool actions_end = false;
5413         struct mlx5_flow_dv_modify_hdr_resource res = {
5414                 .ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
5415                                           MLX5DV_FLOW_TABLE_TYPE_NIC_RX
5416         };
5417         union flow_dv_attr flow_attr = { .attr = 0 };
5418         struct mlx5_flow_dv_tag_resource tag_resource;
5419         uint32_t modify_action_position = UINT32_MAX;
5420         void *match_mask = matcher.mask.buf;
5421         void *match_value = dev_flow->dv.value.buf;
5422         uint8_t next_protocol = 0xff;
5423         struct rte_vlan_hdr vlan = { 0 };
5424         bool vlan_inherited = false;
5425         uint16_t vlan_tci;
5426         uint32_t table;
5427         int ret = 0;
5428
5429         ret = mlx5_flow_group_to_table(attr, dev_flow->external, attr->group,
5430                                        &table, error);
5431         if (ret)
5432                 return ret;
5433         flow->group = table;
5434         if (attr->transfer)
5435                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
5436         if (priority == MLX5_FLOW_PRIO_RSVD)
5437                 priority = priv->config.flow_prio - 1;
5438         for (; !actions_end ; actions++) {
5439                 const struct rte_flow_action_queue *queue;
5440                 const struct rte_flow_action_rss *rss;
5441                 const struct rte_flow_action *action = actions;
5442                 const struct rte_flow_action_count *count = action->conf;
5443                 const uint8_t *rss_key;
5444                 const struct rte_flow_action_jump *jump_data;
5445                 struct mlx5_flow_dv_jump_tbl_resource jump_tbl_resource;
5446                 struct mlx5_flow_tbl_resource *tbl;
5447                 uint32_t port_id = 0;
5448                 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
5449                 int action_type = actions->type;
5450
5451                 switch (action_type) {
5452                 case RTE_FLOW_ACTION_TYPE_VOID:
5453                         break;
5454                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5455                         if (flow_dv_translate_action_port_id(dev, action,
5456                                                              &port_id, error))
5457                                 return -rte_errno;
5458                         port_id_resource.port_id = port_id;
5459                         if (flow_dv_port_id_action_resource_register
5460                             (dev, &port_id_resource, dev_flow, error))
5461                                 return -rte_errno;
5462                         dev_flow->dv.actions[actions_n++] =
5463                                 dev_flow->dv.port_id_action->action;
5464                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5465                         break;
5466                 case RTE_FLOW_ACTION_TYPE_FLAG:
5467                         tag_resource.tag =
5468                                 mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
5469                         if (!flow->tag_resource)
5470                                 if (flow_dv_tag_resource_register
5471                                     (dev, &tag_resource, dev_flow, error))
5472                                         return errno;
5473                         dev_flow->dv.actions[actions_n++] =
5474                                 flow->tag_resource->action;
5475                         action_flags |= MLX5_FLOW_ACTION_FLAG;
5476                         break;
5477                 case RTE_FLOW_ACTION_TYPE_MARK:
5478                         tag_resource.tag = mlx5_flow_mark_set
5479                               (((const struct rte_flow_action_mark *)
5480                                (actions->conf))->id);
5481                         if (!flow->tag_resource)
5482                                 if (flow_dv_tag_resource_register
5483                                     (dev, &tag_resource, dev_flow, error))
5484                                         return errno;
5485                         dev_flow->dv.actions[actions_n++] =
5486                                 flow->tag_resource->action;
5487                         action_flags |= MLX5_FLOW_ACTION_MARK;
5488                         break;
5489                 case RTE_FLOW_ACTION_TYPE_DROP:
5490                         action_flags |= MLX5_FLOW_ACTION_DROP;
5491                         break;
5492                 case RTE_FLOW_ACTION_TYPE_QUEUE:
5493                         queue = actions->conf;
5494                         flow->rss.queue_num = 1;
5495                         (*flow->queue)[0] = queue->index;
5496                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
5497                         break;
5498                 case RTE_FLOW_ACTION_TYPE_RSS:
5499                         rss = actions->conf;
5500                         if (flow->queue)
5501                                 memcpy((*flow->queue), rss->queue,
5502                                        rss->queue_num * sizeof(uint16_t));
5503                         flow->rss.queue_num = rss->queue_num;
5504                         /* NULL RSS key indicates default RSS key. */
5505                         rss_key = !rss->key ? rss_hash_default_key : rss->key;
5506                         memcpy(flow->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
5507                         /* RSS type 0 indicates default RSS type ETH_RSS_IP. */
5508                         flow->rss.types = !rss->types ? ETH_RSS_IP : rss->types;
5509                         flow->rss.level = rss->level;
5510                         action_flags |= MLX5_FLOW_ACTION_RSS;
5511                         break;
5512                 case RTE_FLOW_ACTION_TYPE_COUNT:
5513                         if (!priv->config.devx) {
5514                                 rte_errno = ENOTSUP;
5515                                 goto cnt_err;
5516                         }
5517                         flow->counter = flow_dv_counter_alloc(dev,
5518                                                               count->shared,
5519                                                               count->id,
5520                                                               flow->group);
5521                         if (flow->counter == NULL)
5522                                 goto cnt_err;
5523                         dev_flow->dv.actions[actions_n++] =
5524                                 flow->counter->action;
5525                         action_flags |= MLX5_FLOW_ACTION_COUNT;
5526                         break;
5527 cnt_err:
5528                         if (rte_errno == ENOTSUP)
5529                                 return rte_flow_error_set
5530                                               (error, ENOTSUP,
5531                                                RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5532                                                NULL,
5533                                                "count action not supported");
5534                         else
5535                                 return rte_flow_error_set
5536                                                 (error, rte_errno,
5537                                                  RTE_FLOW_ERROR_TYPE_ACTION,
5538                                                  action,
5539                                                  "cannot create counter"
5540                                                   " object.");
5541                         break;
5542                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
5543                         dev_flow->dv.actions[actions_n++] =
5544                                                 priv->sh->pop_vlan_action;
5545                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
5546                         break;
5547                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
5548                         if (!vlan_inherited) {
5549                                 flow_dev_get_vlan_info_from_items(items, &vlan);
5550                                 vlan_inherited = true;
5551                         }
5552                         vlan.eth_proto = rte_be_to_cpu_16
5553                              ((((const struct rte_flow_action_of_push_vlan *)
5554                                                    actions->conf)->ethertype));
5555                         if (flow_dv_create_action_push_vlan
5556                                             (dev, attr, &vlan, dev_flow, error))
5557                                 return -rte_errno;
5558                         dev_flow->dv.actions[actions_n++] =
5559                                            dev_flow->dv.push_vlan_res->action;
5560                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
5561                         /* Push VLAN command is also handling this VLAN_VID */
5562                         action_flags &= ~MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
5563                         break;
5564                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
5565                         if (!vlan_inherited) {
5566                                 flow_dev_get_vlan_info_from_items(items, &vlan);
5567                                 vlan_inherited = true;
5568                         }
5569                         vlan_tci =
5570                             ((const struct rte_flow_action_of_set_vlan_pcp *)
5571                                                        actions->conf)->vlan_pcp;
5572                         vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
5573                         vlan.vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
5574                         vlan.vlan_tci |= vlan_tci;
5575                         /* Push VLAN command will use this value */
5576                         break;
5577                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
5578                         if (!vlan_inherited) {
5579                                 flow_dev_get_vlan_info_from_items(items, &vlan);
5580                                 vlan_inherited = true;
5581                         }
5582                         vlan.vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
5583                         vlan.vlan_tci |= rte_be_to_cpu_16
5584                             (((const struct rte_flow_action_of_set_vlan_vid *)
5585                                                      actions->conf)->vlan_vid);
5586                         /* Push VLAN command will use this value */
5587                         if (mlx5_flow_find_action
5588                                 (actions,
5589                                  RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN))
5590                                 break;
5591                         /* If no VLAN push - this is a modify header action */
5592                         if (flow_dv_convert_action_modify_vlan_vid
5593                                                         (&res, actions, error))
5594                                 return -rte_errno;
5595                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
5596                         break;
5597                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5598                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5599                         if (flow_dv_create_action_l2_encap(dev, actions,
5600                                                            dev_flow,
5601                                                            attr->transfer,
5602                                                            error))
5603                                 return -rte_errno;
5604                         dev_flow->dv.actions[actions_n++] =
5605                                 dev_flow->dv.encap_decap->verbs_action;
5606                         action_flags |= actions->type ==
5607                                         RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP ?
5608                                         MLX5_FLOW_ACTION_VXLAN_ENCAP :
5609                                         MLX5_FLOW_ACTION_NVGRE_ENCAP;
5610                         break;
5611                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
5612                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
5613                         if (flow_dv_create_action_l2_decap(dev, dev_flow,
5614                                                            attr->transfer,
5615                                                            error))
5616                                 return -rte_errno;
5617                         dev_flow->dv.actions[actions_n++] =
5618                                 dev_flow->dv.encap_decap->verbs_action;
5619                         action_flags |= actions->type ==
5620                                         RTE_FLOW_ACTION_TYPE_VXLAN_DECAP ?
5621                                         MLX5_FLOW_ACTION_VXLAN_DECAP :
5622                                         MLX5_FLOW_ACTION_NVGRE_DECAP;
5623                         break;
5624                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5625                         /* Handle encap with preceding decap. */
5626                         if (action_flags & MLX5_FLOW_ACTION_RAW_DECAP) {
5627                                 if (flow_dv_create_action_raw_encap
5628                                         (dev, actions, dev_flow, attr, error))
5629                                         return -rte_errno;
5630                                 dev_flow->dv.actions[actions_n++] =
5631                                         dev_flow->dv.encap_decap->verbs_action;
5632                         } else {
5633                                 /* Handle encap without preceding decap. */
5634                                 if (flow_dv_create_action_l2_encap
5635                                     (dev, actions, dev_flow, attr->transfer,
5636                                      error))
5637                                         return -rte_errno;
5638                                 dev_flow->dv.actions[actions_n++] =
5639                                         dev_flow->dv.encap_decap->verbs_action;
5640                         }
5641                         action_flags |= MLX5_FLOW_ACTION_RAW_ENCAP;
5642                         break;
5643                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
5644                         /* Check if this decap is followed by encap. */
5645                         for (; action->type != RTE_FLOW_ACTION_TYPE_END &&
5646                                action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP;
5647                                action++) {
5648                         }
5649                         /* Handle decap only if it isn't followed by encap. */
5650                         if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
5651                                 if (flow_dv_create_action_l2_decap
5652                                     (dev, dev_flow, attr->transfer, error))
5653                                         return -rte_errno;
5654                                 dev_flow->dv.actions[actions_n++] =
5655                                         dev_flow->dv.encap_decap->verbs_action;
5656                         }
5657                         /* If decap is followed by encap, handle it at encap. */
5658                         action_flags |= MLX5_FLOW_ACTION_RAW_DECAP;
5659                         break;
5660                 case RTE_FLOW_ACTION_TYPE_JUMP:
5661                         jump_data = action->conf;
5662                         ret = mlx5_flow_group_to_table(attr, dev_flow->external,
5663                                                        jump_data->group, &table,
5664                                                        error);
5665                         if (ret)
5666                                 return ret;
5667                         tbl = flow_dv_tbl_resource_get(dev, table,
5668                                                        attr->egress,
5669                                                        attr->transfer, error);
5670                         if (!tbl)
5671                                 return rte_flow_error_set
5672                                                 (error, errno,
5673                                                  RTE_FLOW_ERROR_TYPE_ACTION,
5674                                                  NULL,
5675                                                  "cannot create jump action.");
5676                         jump_tbl_resource.tbl = tbl;
5677                         if (flow_dv_jump_tbl_resource_register
5678                             (dev, &jump_tbl_resource, dev_flow, error)) {
5679                                 flow_dv_tbl_resource_release(tbl);
5680                                 return rte_flow_error_set
5681                                                 (error, errno,
5682                                                  RTE_FLOW_ERROR_TYPE_ACTION,
5683                                                  NULL,
5684                                                  "cannot create jump action.");
5685                         }
5686                         dev_flow->dv.actions[actions_n++] =
5687                                 dev_flow->dv.jump->action;
5688                         action_flags |= MLX5_FLOW_ACTION_JUMP;
5689                         break;
5690                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
5691                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
5692                         if (flow_dv_convert_action_modify_mac(&res, actions,
5693                                                               error))
5694                                 return -rte_errno;
5695                         action_flags |= actions->type ==
5696                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
5697                                         MLX5_FLOW_ACTION_SET_MAC_SRC :
5698                                         MLX5_FLOW_ACTION_SET_MAC_DST;
5699                         break;
5700                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
5701                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
5702                         if (flow_dv_convert_action_modify_ipv4(&res, actions,
5703                                                                error))
5704                                 return -rte_errno;
5705                         action_flags |= actions->type ==
5706                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
5707                                         MLX5_FLOW_ACTION_SET_IPV4_SRC :
5708                                         MLX5_FLOW_ACTION_SET_IPV4_DST;
5709                         break;
5710                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
5711                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
5712                         if (flow_dv_convert_action_modify_ipv6(&res, actions,
5713                                                                error))
5714                                 return -rte_errno;
5715                         action_flags |= actions->type ==
5716                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
5717                                         MLX5_FLOW_ACTION_SET_IPV6_SRC :
5718                                         MLX5_FLOW_ACTION_SET_IPV6_DST;
5719                         break;
5720                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
5721                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
5722                         if (flow_dv_convert_action_modify_tp(&res, actions,
5723                                                              items, &flow_attr,
5724                                                              error))
5725                                 return -rte_errno;
5726                         action_flags |= actions->type ==
5727                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
5728                                         MLX5_FLOW_ACTION_SET_TP_SRC :
5729                                         MLX5_FLOW_ACTION_SET_TP_DST;
5730                         break;
5731                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
5732                         if (flow_dv_convert_action_modify_dec_ttl(&res, items,
5733                                                                   &flow_attr,
5734                                                                   error))
5735                                 return -rte_errno;
5736                         action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
5737                         break;
5738                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
5739                         if (flow_dv_convert_action_modify_ttl(&res, actions,
5740                                                              items, &flow_attr,
5741                                                              error))
5742                                 return -rte_errno;
5743                         action_flags |= MLX5_FLOW_ACTION_SET_TTL;
5744                         break;
5745                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
5746                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
5747                         if (flow_dv_convert_action_modify_tcp_seq(&res, actions,
5748                                                                   error))
5749                                 return -rte_errno;
5750                         action_flags |= actions->type ==
5751                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
5752                                         MLX5_FLOW_ACTION_INC_TCP_SEQ :
5753                                         MLX5_FLOW_ACTION_DEC_TCP_SEQ;
5754                         break;
5755
5756                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
5757                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
5758                         if (flow_dv_convert_action_modify_tcp_ack(&res, actions,
5759                                                                   error))
5760                                 return -rte_errno;
5761                         action_flags |= actions->type ==
5762                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
5763                                         MLX5_FLOW_ACTION_INC_TCP_ACK :
5764                                         MLX5_FLOW_ACTION_DEC_TCP_ACK;
5765                         break;
5766                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
5767                         if (flow_dv_convert_action_set_reg(&res, actions,
5768                                                            error))
5769                                 return -rte_errno;
5770                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
5771                         break;
5772                 case RTE_FLOW_ACTION_TYPE_END:
5773                         actions_end = true;
5774                         if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS) {
5775                                 /* create modify action if needed. */
5776                                 if (flow_dv_modify_hdr_resource_register
5777                                                                 (dev, &res,
5778                                                                  dev_flow,
5779                                                                  error))
5780                                         return -rte_errno;
5781                                 dev_flow->dv.actions[modify_action_position] =
5782                                         dev_flow->dv.modify_hdr->verbs_action;
5783                         }
5784                         break;
5785                 default:
5786                         break;
5787                 }
5788                 if ((action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS) &&
5789                     modify_action_position == UINT32_MAX)
5790                         modify_action_position = actions_n++;
5791         }
5792         dev_flow->dv.actions_n = actions_n;
5793         flow->actions = action_flags;
5794         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
5795                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
5796                 int item_type = items->type;
5797
5798                 switch (item_type) {
5799                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
5800                         flow_dv_translate_item_port_id(dev, match_mask,
5801                                                        match_value, items);
5802                         last_item = MLX5_FLOW_ITEM_PORT_ID;
5803                         break;
5804                 case RTE_FLOW_ITEM_TYPE_ETH:
5805                         flow_dv_translate_item_eth(match_mask, match_value,
5806                                                    items, tunnel);
5807                         matcher.priority = MLX5_PRIORITY_MAP_L2;
5808                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
5809                                              MLX5_FLOW_LAYER_OUTER_L2;
5810                         break;
5811                 case RTE_FLOW_ITEM_TYPE_VLAN:
5812                         flow_dv_translate_item_vlan(dev_flow,
5813                                                     match_mask, match_value,
5814                                                     items, tunnel);
5815                         matcher.priority = MLX5_PRIORITY_MAP_L2;
5816                         last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
5817                                               MLX5_FLOW_LAYER_INNER_VLAN) :
5818                                              (MLX5_FLOW_LAYER_OUTER_L2 |
5819                                               MLX5_FLOW_LAYER_OUTER_VLAN);
5820                         break;
5821                 case RTE_FLOW_ITEM_TYPE_IPV4:
5822                         mlx5_flow_tunnel_ip_check(items, next_protocol,
5823                                                   &item_flags, &tunnel);
5824                         flow_dv_translate_item_ipv4(match_mask, match_value,
5825                                                     items, tunnel, flow->group);
5826                         matcher.priority = MLX5_PRIORITY_MAP_L3;
5827                         dev_flow->dv.hash_fields |=
5828                                 mlx5_flow_hashfields_adjust
5829                                         (dev_flow, tunnel,
5830                                          MLX5_IPV4_LAYER_TYPES,
5831                                          MLX5_IPV4_IBV_RX_HASH);
5832                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
5833                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
5834                         if (items->mask != NULL &&
5835                             ((const struct rte_flow_item_ipv4 *)
5836                              items->mask)->hdr.next_proto_id) {
5837                                 next_protocol =
5838                                         ((const struct rte_flow_item_ipv4 *)
5839                                          (items->spec))->hdr.next_proto_id;
5840                                 next_protocol &=
5841                                         ((const struct rte_flow_item_ipv4 *)
5842                                          (items->mask))->hdr.next_proto_id;
5843                         } else {
5844                                 /* Reset for inner layer. */
5845                                 next_protocol = 0xff;
5846                         }
5847                         break;
5848                 case RTE_FLOW_ITEM_TYPE_IPV6:
5849                         mlx5_flow_tunnel_ip_check(items, next_protocol,
5850                                                   &item_flags, &tunnel);
5851                         flow_dv_translate_item_ipv6(match_mask, match_value,
5852                                                     items, tunnel, flow->group);
5853                         matcher.priority = MLX5_PRIORITY_MAP_L3;
5854                         dev_flow->dv.hash_fields |=
5855                                 mlx5_flow_hashfields_adjust
5856                                         (dev_flow, tunnel,
5857                                          MLX5_IPV6_LAYER_TYPES,
5858                                          MLX5_IPV6_IBV_RX_HASH);
5859                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
5860                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
5861                         if (items->mask != NULL &&
5862                             ((const struct rte_flow_item_ipv6 *)
5863                              items->mask)->hdr.proto) {
5864                                 next_protocol =
5865                                         ((const struct rte_flow_item_ipv6 *)
5866                                          items->spec)->hdr.proto;
5867                                 next_protocol &=
5868                                         ((const struct rte_flow_item_ipv6 *)
5869                                          items->mask)->hdr.proto;
5870                         } else {
5871                                 /* Reset for inner layer. */
5872                                 next_protocol = 0xff;
5873                         }
5874                         break;
5875                 case RTE_FLOW_ITEM_TYPE_TCP:
5876                         flow_dv_translate_item_tcp(match_mask, match_value,
5877                                                    items, tunnel);
5878                         matcher.priority = MLX5_PRIORITY_MAP_L4;
5879                         dev_flow->dv.hash_fields |=
5880                                 mlx5_flow_hashfields_adjust
5881                                         (dev_flow, tunnel, ETH_RSS_TCP,
5882                                          IBV_RX_HASH_SRC_PORT_TCP |
5883                                          IBV_RX_HASH_DST_PORT_TCP);
5884                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
5885                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
5886                         break;
5887                 case RTE_FLOW_ITEM_TYPE_UDP:
5888                         flow_dv_translate_item_udp(match_mask, match_value,
5889                                                    items, tunnel);
5890                         matcher.priority = MLX5_PRIORITY_MAP_L4;
5891                         dev_flow->dv.hash_fields |=
5892                                 mlx5_flow_hashfields_adjust
5893                                         (dev_flow, tunnel, ETH_RSS_UDP,
5894                                          IBV_RX_HASH_SRC_PORT_UDP |
5895                                          IBV_RX_HASH_DST_PORT_UDP);
5896                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
5897                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
5898                         break;
5899                 case RTE_FLOW_ITEM_TYPE_GRE:
5900                         flow_dv_translate_item_gre(match_mask, match_value,
5901                                                    items, tunnel);
5902                         last_item = MLX5_FLOW_LAYER_GRE;
5903                         break;
5904                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
5905                         flow_dv_translate_item_gre_key(match_mask,
5906                                                        match_value, items);
5907                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
5908                         break;
5909                 case RTE_FLOW_ITEM_TYPE_NVGRE:
5910                         flow_dv_translate_item_nvgre(match_mask, match_value,
5911                                                      items, tunnel);
5912                         last_item = MLX5_FLOW_LAYER_GRE;
5913                         break;
5914                 case RTE_FLOW_ITEM_TYPE_VXLAN:
5915                         flow_dv_translate_item_vxlan(match_mask, match_value,
5916                                                      items, tunnel);
5917                         last_item = MLX5_FLOW_LAYER_VXLAN;
5918                         break;
5919                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
5920                         flow_dv_translate_item_vxlan(match_mask, match_value,
5921                                                      items, tunnel);
5922                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
5923                         break;
5924                 case RTE_FLOW_ITEM_TYPE_GENEVE:
5925                         flow_dv_translate_item_geneve(match_mask, match_value,
5926                                                       items, tunnel);
5927                         last_item = MLX5_FLOW_LAYER_GENEVE;
5928                         break;
5929                 case RTE_FLOW_ITEM_TYPE_MPLS:
5930                         flow_dv_translate_item_mpls(match_mask, match_value,
5931                                                     items, last_item, tunnel);
5932                         last_item = MLX5_FLOW_LAYER_MPLS;
5933                         break;
5934                 case RTE_FLOW_ITEM_TYPE_META:
5935                         flow_dv_translate_item_meta(match_mask, match_value,
5936                                                     items);
5937                         last_item = MLX5_FLOW_ITEM_METADATA;
5938                         break;
5939                 case RTE_FLOW_ITEM_TYPE_ICMP:
5940                         flow_dv_translate_item_icmp(match_mask, match_value,
5941                                                     items, tunnel);
5942                         last_item = MLX5_FLOW_LAYER_ICMP;
5943                         break;
5944                 case RTE_FLOW_ITEM_TYPE_ICMP6:
5945                         flow_dv_translate_item_icmp6(match_mask, match_value,
5946                                                       items, tunnel);
5947                         last_item = MLX5_FLOW_LAYER_ICMP6;
5948                         break;
5949                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
5950                         flow_dv_translate_item_tag(match_mask, match_value,
5951                                                    items);
5952                         last_item = MLX5_FLOW_ITEM_TAG;
5953                         break;
5954                 default:
5955                         break;
5956                 }
5957                 item_flags |= last_item;
5958         }
5959         /*
5960          * In case of ingress traffic when E-Switch mode is enabled,
5961          * we have two cases where we need to set the source port manually.
5962          * The first one, is in case of Nic steering rule, and the second is
5963          * E-Switch rule where no port_id item was found. In both cases
5964          * the source port is set according the current port in use.
5965          */
5966         if ((attr->ingress && !(item_flags & MLX5_FLOW_ITEM_PORT_ID)) &&
5967             (priv->representor || priv->master)) {
5968                 if (flow_dv_translate_item_port_id(dev, match_mask,
5969                                                    match_value, NULL))
5970                         return -rte_errno;
5971         }
5972         assert(!flow_dv_check_valid_spec(matcher.mask.buf,
5973                                          dev_flow->dv.value.buf));
5974         dev_flow->layers = item_flags;
5975         /* Register matcher. */
5976         matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
5977                                     matcher.mask.size);
5978         matcher.priority = mlx5_flow_adjust_priority(dev, priority,
5979                                                      matcher.priority);
5980         matcher.egress = attr->egress;
5981         matcher.group = flow->group;
5982         matcher.transfer = attr->transfer;
5983         if (flow_dv_matcher_register(dev, &matcher, dev_flow, error))
5984                 return -rte_errno;
5985         return 0;
5986 }
5987
5988 /**
5989  * Apply the flow to the NIC.
5990  *
5991  * @param[in] dev
5992  *   Pointer to the Ethernet device structure.
5993  * @param[in, out] flow
5994  *   Pointer to flow structure.
5995  * @param[out] error
5996  *   Pointer to error structure.
5997  *
5998  * @return
5999  *   0 on success, a negative errno value otherwise and rte_errno is set.
6000  */
6001 static int
6002 flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
6003               struct rte_flow_error *error)
6004 {
6005         struct mlx5_flow_dv *dv;
6006         struct mlx5_flow *dev_flow;
6007         struct mlx5_priv *priv = dev->data->dev_private;
6008         int n;
6009         int err;
6010
6011         LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
6012                 dv = &dev_flow->dv;
6013                 n = dv->actions_n;
6014                 if (flow->actions & MLX5_FLOW_ACTION_DROP) {
6015                         if (flow->transfer) {
6016                                 dv->actions[n++] = priv->sh->esw_drop_action;
6017                         } else {
6018                                 dv->hrxq = mlx5_hrxq_drop_new(dev);
6019                                 if (!dv->hrxq) {
6020                                         rte_flow_error_set
6021                                                 (error, errno,
6022                                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6023                                                  NULL,
6024                                                  "cannot get drop hash queue");
6025                                         goto error;
6026                                 }
6027                                 dv->actions[n++] = dv->hrxq->action;
6028                         }
6029                 } else if (flow->actions &
6030                            (MLX5_FLOW_ACTION_QUEUE | MLX5_FLOW_ACTION_RSS)) {
6031                         struct mlx5_hrxq *hrxq;
6032
6033                         hrxq = mlx5_hrxq_get(dev, flow->key,
6034                                              MLX5_RSS_HASH_KEY_LEN,
6035                                              dv->hash_fields,
6036                                              (*flow->queue),
6037                                              flow->rss.queue_num);
6038                         if (!hrxq) {
6039                                 hrxq = mlx5_hrxq_new
6040                                         (dev, flow->key, MLX5_RSS_HASH_KEY_LEN,
6041                                          dv->hash_fields, (*flow->queue),
6042                                          flow->rss.queue_num,
6043                                          !!(dev_flow->layers &
6044                                             MLX5_FLOW_LAYER_TUNNEL));
6045                         }
6046                         if (!hrxq) {
6047                                 rte_flow_error_set
6048                                         (error, rte_errno,
6049                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6050                                          "cannot get hash queue");
6051                                 goto error;
6052                         }
6053                         dv->hrxq = hrxq;
6054                         dv->actions[n++] = dv->hrxq->action;
6055                 }
6056                 dv->flow =
6057                         mlx5_glue->dv_create_flow(dv->matcher->matcher_object,
6058                                                   (void *)&dv->value, n,
6059                                                   dv->actions);
6060                 if (!dv->flow) {
6061                         rte_flow_error_set(error, errno,
6062                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6063                                            NULL,
6064                                            "hardware refuses to create flow");
6065                         goto error;
6066                 }
6067                 if (priv->vmwa_context &&
6068                     dev_flow->dv.vf_vlan.tag &&
6069                     !dev_flow->dv.vf_vlan.created) {
6070                         /*
6071                          * The rule contains the VLAN pattern.
6072                          * For VF we are going to create VLAN
6073                          * interface to make hypervisor set correct
6074                          * e-Switch vport context.
6075                          */
6076                         mlx5_vlan_vmwa_acquire(dev, &dev_flow->dv.vf_vlan);
6077                 }
6078         }
6079         return 0;
6080 error:
6081         err = rte_errno; /* Save rte_errno before cleanup. */
6082         LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
6083                 struct mlx5_flow_dv *dv = &dev_flow->dv;
6084                 if (dv->hrxq) {
6085                         if (flow->actions & MLX5_FLOW_ACTION_DROP)
6086                                 mlx5_hrxq_drop_release(dev);
6087                         else
6088                                 mlx5_hrxq_release(dev, dv->hrxq);
6089                         dv->hrxq = NULL;
6090                 }
6091                 if (dev_flow->dv.vf_vlan.tag &&
6092                     dev_flow->dv.vf_vlan.created)
6093                         mlx5_vlan_vmwa_release(dev, &dev_flow->dv.vf_vlan);
6094         }
6095         rte_errno = err; /* Restore rte_errno. */
6096         return -rte_errno;
6097 }
6098
6099 /**
6100  * Release the flow matcher.
6101  *
6102  * @param dev
6103  *   Pointer to Ethernet device.
6104  * @param flow
6105  *   Pointer to mlx5_flow.
6106  *
6107  * @return
6108  *   1 while a reference on it exists, 0 when freed.
6109  */
6110 static int
6111 flow_dv_matcher_release(struct rte_eth_dev *dev,
6112                         struct mlx5_flow *flow)
6113 {
6114         struct mlx5_flow_dv_matcher *matcher = flow->dv.matcher;
6115         struct mlx5_priv *priv = dev->data->dev_private;
6116         struct mlx5_ibv_shared *sh = priv->sh;
6117         struct mlx5_flow_tbl_resource *tbl;
6118
6119         assert(matcher->matcher_object);
6120         DRV_LOG(DEBUG, "port %u matcher %p: refcnt %d--",
6121                 dev->data->port_id, (void *)matcher,
6122                 rte_atomic32_read(&matcher->refcnt));
6123         if (rte_atomic32_dec_and_test(&matcher->refcnt)) {
6124                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
6125                            (matcher->matcher_object));
6126                 LIST_REMOVE(matcher, next);
6127                 if (matcher->egress)
6128                         tbl = &sh->tx_tbl[matcher->group];
6129                 else
6130                         tbl = &sh->rx_tbl[matcher->group];
6131                 flow_dv_tbl_resource_release(tbl);
6132                 rte_free(matcher);
6133                 DRV_LOG(DEBUG, "port %u matcher %p: removed",
6134                         dev->data->port_id, (void *)matcher);
6135                 return 0;
6136         }
6137         return 1;
6138 }
6139
6140 /**
6141  * Release an encap/decap resource.
6142  *
6143  * @param flow
6144  *   Pointer to mlx5_flow.
6145  *
6146  * @return
6147  *   1 while a reference on it exists, 0 when freed.
6148  */
6149 static int
6150 flow_dv_encap_decap_resource_release(struct mlx5_flow *flow)
6151 {
6152         struct mlx5_flow_dv_encap_decap_resource *cache_resource =
6153                                                 flow->dv.encap_decap;
6154
6155         assert(cache_resource->verbs_action);
6156         DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d--",
6157                 (void *)cache_resource,
6158                 rte_atomic32_read(&cache_resource->refcnt));
6159         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
6160                 claim_zero(mlx5_glue->destroy_flow_action
6161                                 (cache_resource->verbs_action));
6162                 LIST_REMOVE(cache_resource, next);
6163                 rte_free(cache_resource);
6164                 DRV_LOG(DEBUG, "encap/decap resource %p: removed",
6165                         (void *)cache_resource);
6166                 return 0;
6167         }
6168         return 1;
6169 }
6170
6171 /**
6172  * Release an jump to table action resource.
6173  *
6174  * @param flow
6175  *   Pointer to mlx5_flow.
6176  *
6177  * @return
6178  *   1 while a reference on it exists, 0 when freed.
6179  */
6180 static int
6181 flow_dv_jump_tbl_resource_release(struct mlx5_flow *flow)
6182 {
6183         struct mlx5_flow_dv_jump_tbl_resource *cache_resource =
6184                                                 flow->dv.jump;
6185
6186         assert(cache_resource->action);
6187         DRV_LOG(DEBUG, "jump table resource %p: refcnt %d--",
6188                 (void *)cache_resource,
6189                 rte_atomic32_read(&cache_resource->refcnt));
6190         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
6191                 claim_zero(mlx5_glue->destroy_flow_action
6192                                 (cache_resource->action));
6193                 LIST_REMOVE(cache_resource, next);
6194                 flow_dv_tbl_resource_release(cache_resource->tbl);
6195                 rte_free(cache_resource);
6196                 DRV_LOG(DEBUG, "jump table resource %p: removed",
6197                         (void *)cache_resource);
6198                 return 0;
6199         }
6200         return 1;
6201 }
6202
6203 /**
6204  * Release a modify-header resource.
6205  *
6206  * @param flow
6207  *   Pointer to mlx5_flow.
6208  *
6209  * @return
6210  *   1 while a reference on it exists, 0 when freed.
6211  */
6212 static int
6213 flow_dv_modify_hdr_resource_release(struct mlx5_flow *flow)
6214 {
6215         struct mlx5_flow_dv_modify_hdr_resource *cache_resource =
6216                                                 flow->dv.modify_hdr;
6217
6218         assert(cache_resource->verbs_action);
6219         DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d--",
6220                 (void *)cache_resource,
6221                 rte_atomic32_read(&cache_resource->refcnt));
6222         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
6223                 claim_zero(mlx5_glue->destroy_flow_action
6224                                 (cache_resource->verbs_action));
6225                 LIST_REMOVE(cache_resource, next);
6226                 rte_free(cache_resource);
6227                 DRV_LOG(DEBUG, "modify-header resource %p: removed",
6228                         (void *)cache_resource);
6229                 return 0;
6230         }
6231         return 1;
6232 }
6233
6234 /**
6235  * Release port ID action resource.
6236  *
6237  * @param flow
6238  *   Pointer to mlx5_flow.
6239  *
6240  * @return
6241  *   1 while a reference on it exists, 0 when freed.
6242  */
6243 static int
6244 flow_dv_port_id_action_resource_release(struct mlx5_flow *flow)
6245 {
6246         struct mlx5_flow_dv_port_id_action_resource *cache_resource =
6247                 flow->dv.port_id_action;
6248
6249         assert(cache_resource->action);
6250         DRV_LOG(DEBUG, "port ID action resource %p: refcnt %d--",
6251                 (void *)cache_resource,
6252                 rte_atomic32_read(&cache_resource->refcnt));
6253         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
6254                 claim_zero(mlx5_glue->destroy_flow_action
6255                                 (cache_resource->action));
6256                 LIST_REMOVE(cache_resource, next);
6257                 rte_free(cache_resource);
6258                 DRV_LOG(DEBUG, "port id action resource %p: removed",
6259                         (void *)cache_resource);
6260                 return 0;
6261         }
6262         return 1;
6263 }
6264
6265 /**
6266  * Release push vlan action resource.
6267  *
6268  * @param flow
6269  *   Pointer to mlx5_flow.
6270  *
6271  * @return
6272  *   1 while a reference on it exists, 0 when freed.
6273  */
6274 static int
6275 flow_dv_push_vlan_action_resource_release(struct mlx5_flow *flow)
6276 {
6277         struct mlx5_flow_dv_push_vlan_action_resource *cache_resource =
6278                 flow->dv.push_vlan_res;
6279
6280         assert(cache_resource->action);
6281         DRV_LOG(DEBUG, "push VLAN action resource %p: refcnt %d--",
6282                 (void *)cache_resource,
6283                 rte_atomic32_read(&cache_resource->refcnt));
6284         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
6285                 claim_zero(mlx5_glue->destroy_flow_action
6286                                 (cache_resource->action));
6287                 LIST_REMOVE(cache_resource, next);
6288                 rte_free(cache_resource);
6289                 DRV_LOG(DEBUG, "push vlan action resource %p: removed",
6290                         (void *)cache_resource);
6291                 return 0;
6292         }
6293         return 1;
6294 }
6295
6296 /**
6297  * Remove the flow from the NIC but keeps it in memory.
6298  *
6299  * @param[in] dev
6300  *   Pointer to Ethernet device.
6301  * @param[in, out] flow
6302  *   Pointer to flow structure.
6303  */
6304 static void
6305 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
6306 {
6307         struct mlx5_flow_dv *dv;
6308         struct mlx5_flow *dev_flow;
6309
6310         if (!flow)
6311                 return;
6312         LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
6313                 dv = &dev_flow->dv;
6314                 if (dv->flow) {
6315                         claim_zero(mlx5_glue->dv_destroy_flow(dv->flow));
6316                         dv->flow = NULL;
6317                 }
6318                 if (dv->hrxq) {
6319                         if (flow->actions & MLX5_FLOW_ACTION_DROP)
6320                                 mlx5_hrxq_drop_release(dev);
6321                         else
6322                                 mlx5_hrxq_release(dev, dv->hrxq);
6323                         dv->hrxq = NULL;
6324                 }
6325                 if (dev_flow->dv.vf_vlan.tag &&
6326                     dev_flow->dv.vf_vlan.created)
6327                         mlx5_vlan_vmwa_release(dev, &dev_flow->dv.vf_vlan);
6328         }
6329 }
6330
6331 /**
6332  * Remove the flow from the NIC and the memory.
6333  *
6334  * @param[in] dev
6335  *   Pointer to the Ethernet device structure.
6336  * @param[in, out] flow
6337  *   Pointer to flow structure.
6338  */
6339 static void
6340 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
6341 {
6342         struct mlx5_flow *dev_flow;
6343
6344         if (!flow)
6345                 return;
6346         flow_dv_remove(dev, flow);
6347         if (flow->counter) {
6348                 flow_dv_counter_release(dev, flow->counter);
6349                 flow->counter = NULL;
6350         }
6351         if (flow->tag_resource) {
6352                 flow_dv_tag_release(dev, flow->tag_resource);
6353                 flow->tag_resource = NULL;
6354         }
6355         while (!LIST_EMPTY(&flow->dev_flows)) {
6356                 dev_flow = LIST_FIRST(&flow->dev_flows);
6357                 LIST_REMOVE(dev_flow, next);
6358                 if (dev_flow->dv.matcher)
6359                         flow_dv_matcher_release(dev, dev_flow);
6360                 if (dev_flow->dv.encap_decap)
6361                         flow_dv_encap_decap_resource_release(dev_flow);
6362                 if (dev_flow->dv.modify_hdr)
6363                         flow_dv_modify_hdr_resource_release(dev_flow);
6364                 if (dev_flow->dv.jump)
6365                         flow_dv_jump_tbl_resource_release(dev_flow);
6366                 if (dev_flow->dv.port_id_action)
6367                         flow_dv_port_id_action_resource_release(dev_flow);
6368                 if (dev_flow->dv.push_vlan_res)
6369                         flow_dv_push_vlan_action_resource_release(dev_flow);
6370                 rte_free(dev_flow);
6371         }
6372 }
6373
6374 /**
6375  * Query a dv flow  rule for its statistics via devx.
6376  *
6377  * @param[in] dev
6378  *   Pointer to Ethernet device.
6379  * @param[in] flow
6380  *   Pointer to the sub flow.
6381  * @param[out] data
6382  *   data retrieved by the query.
6383  * @param[out] error
6384  *   Perform verbose error reporting if not NULL.
6385  *
6386  * @return
6387  *   0 on success, a negative errno value otherwise and rte_errno is set.
6388  */
6389 static int
6390 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
6391                     void *data, struct rte_flow_error *error)
6392 {
6393         struct mlx5_priv *priv = dev->data->dev_private;
6394         struct rte_flow_query_count *qc = data;
6395
6396         if (!priv->config.devx)
6397                 return rte_flow_error_set(error, ENOTSUP,
6398                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6399                                           NULL,
6400                                           "counters are not supported");
6401         if (flow->counter) {
6402                 uint64_t pkts, bytes;
6403                 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
6404                                                &bytes);
6405
6406                 if (err)
6407                         return rte_flow_error_set(error, -err,
6408                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6409                                         NULL, "cannot read counters");
6410                 qc->hits_set = 1;
6411                 qc->bytes_set = 1;
6412                 qc->hits = pkts - flow->counter->hits;
6413                 qc->bytes = bytes - flow->counter->bytes;
6414                 if (qc->reset) {
6415                         flow->counter->hits = pkts;
6416                         flow->counter->bytes = bytes;
6417                 }
6418                 return 0;
6419         }
6420         return rte_flow_error_set(error, EINVAL,
6421                                   RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6422                                   NULL,
6423                                   "counters are not available");
6424 }
6425
6426 /**
6427  * Query a flow.
6428  *
6429  * @see rte_flow_query()
6430  * @see rte_flow_ops
6431  */
6432 static int
6433 flow_dv_query(struct rte_eth_dev *dev,
6434               struct rte_flow *flow __rte_unused,
6435               const struct rte_flow_action *actions __rte_unused,
6436               void *data __rte_unused,
6437               struct rte_flow_error *error __rte_unused)
6438 {
6439         int ret = -EINVAL;
6440
6441         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
6442                 switch (actions->type) {
6443                 case RTE_FLOW_ACTION_TYPE_VOID:
6444                         break;
6445                 case RTE_FLOW_ACTION_TYPE_COUNT:
6446                         ret = flow_dv_query_count(dev, flow, data, error);
6447                         break;
6448                 default:
6449                         return rte_flow_error_set(error, ENOTSUP,
6450                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6451                                                   actions,
6452                                                   "action not supported");
6453                 }
6454         }
6455         return ret;
6456 }
6457
6458 /*
6459  * Mutex-protected thunk to flow_dv_translate().
6460  */
6461 static int
6462 flow_d_translate(struct rte_eth_dev *dev,
6463                  struct mlx5_flow *dev_flow,
6464                  const struct rte_flow_attr *attr,
6465                  const struct rte_flow_item items[],
6466                  const struct rte_flow_action actions[],
6467                  struct rte_flow_error *error)
6468 {
6469         int ret;
6470
6471         flow_d_shared_lock(dev);
6472         ret = flow_dv_translate(dev, dev_flow, attr, items, actions, error);
6473         flow_d_shared_unlock(dev);
6474         return ret;
6475 }
6476
6477 /*
6478  * Mutex-protected thunk to flow_dv_apply().
6479  */
6480 static int
6481 flow_d_apply(struct rte_eth_dev *dev,
6482              struct rte_flow *flow,
6483              struct rte_flow_error *error)
6484 {
6485         int ret;
6486
6487         flow_d_shared_lock(dev);
6488         ret = flow_dv_apply(dev, flow, error);
6489         flow_d_shared_unlock(dev);
6490         return ret;
6491 }
6492
6493 /*
6494  * Mutex-protected thunk to flow_dv_remove().
6495  */
6496 static void
6497 flow_d_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
6498 {
6499         flow_d_shared_lock(dev);
6500         flow_dv_remove(dev, flow);
6501         flow_d_shared_unlock(dev);
6502 }
6503
6504 /*
6505  * Mutex-protected thunk to flow_dv_destroy().
6506  */
6507 static void
6508 flow_d_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
6509 {
6510         flow_d_shared_lock(dev);
6511         flow_dv_destroy(dev, flow);
6512         flow_d_shared_unlock(dev);
6513 }
6514
6515 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
6516         .validate = flow_dv_validate,
6517         .prepare = flow_dv_prepare,
6518         .translate = flow_d_translate,
6519         .apply = flow_d_apply,
6520         .remove = flow_d_remove,
6521         .destroy = flow_d_destroy,
6522         .query = flow_dv_query,
6523 };
6524
6525 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */