drivers/net/mlx5/mlx5_flow_dv.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2018 Mellanox Technologies, Ltd
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdalign.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10
  11 /* Verbs header. */
  12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  13 #ifdef PEDANTIC
  14 #pragma GCC diagnostic ignored "-Wpedantic"
  15 #endif
  16 #include <infiniband/verbs.h>
  17 #ifdef PEDANTIC
  18 #pragma GCC diagnostic error "-Wpedantic"
  19 #endif
  20
  21 #include <rte_common.h>
  22 #include <rte_ether.h>
  23 #include <rte_ethdev_driver.h>
  24 #include <rte_flow.h>
  25 #include <rte_flow_driver.h>
  26 #include <rte_malloc.h>
  27 #include <rte_ip.h>
  28 #include <rte_gre.h>
  29 #include <rte_vxlan.h>
  30 #include <rte_gtp.h>
  31
  32 #include <mlx5_glue.h>
  33 #include <mlx5_devx_cmds.h>
  34 #include <mlx5_prm.h>
  35
  36 #include "mlx5_defs.h"
  37 #include "mlx5.h"
  38 #include "mlx5_flow.h"
  39 #include "mlx5_rxtx.h"
  40
  41 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
  42
  43 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
  44 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
  45 #endif
  46
  47 #ifndef HAVE_MLX5DV_DR_ESWITCH
  48 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
  49 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
  50 #endif
  51 #endif
  52
  53 #ifndef HAVE_MLX5DV_DR
  54 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
  55 #endif
  56
  57 /* VLAN header definitions */
  58 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
  59 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
  60 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
  61 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
  62 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
  63
  64 union flow_dv_attr {
  65         struct {
  66                 uint32_t valid:1;
  67                 uint32_t ipv4:1;
  68                 uint32_t ipv6:1;
  69                 uint32_t tcp:1;
  70                 uint32_t udp:1;
  71                 uint32_t reserved:27;
  72         };
  73         uint32_t attr;
  74 };
  75
  76 static struct mlx5_flow_counter_pool *
  77 flow_dv_find_pool_by_id(struct mlx5_pools_container *cont, bool fallback,
  78                         int id);
  79 static struct mlx5_pools_container *
  80 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
  81                     uint32_t batch);
  82
  83 /**
  84  * Initialize flow attributes structure according to flow items' types.
  85  *
  86  * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
  87  * mode. For tunnel mode, the items to be modified are the outermost ones.
  88  *
  89  * @param[in] item
  90  *   Pointer to item specification.
  91  * @param[out] attr
  92  *   Pointer to flow attributes structure.
  93  * @param[in] dev_flow
  94  *   Pointer to the sub flow.
  95  * @param[in] tunnel_decap
  96  *   Whether action is after tunnel decapsulation.
  97  */
  98 static void
  99 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
 100                   struct mlx5_flow *dev_flow, bool tunnel_decap)
 101 {
 102         uint64_t layers = dev_flow->handle->layers;
 103
 104         /*
 105          * If layers is already initialized, it means this dev_flow is the
 106          * suffix flow, the layers flags is set by the prefix flow. Need to
 107          * use the layer flags from prefix flow as the suffix flow may not
 108          * have the user defined items as the flow is split.
 109          */
 110         if (layers) {
 111                 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
 112                         attr->ipv4 = 1;
 113                 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
 114                         attr->ipv6 = 1;
 115                 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
 116                         attr->tcp = 1;
 117                 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
 118                         attr->udp = 1;
 119                 attr->valid = 1;
 120                 return;
 121         }
 122         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
 123                 uint8_t next_protocol = 0xff;
 124                 switch (item->type) {
 125                 case RTE_FLOW_ITEM_TYPE_GRE:
 126                 case RTE_FLOW_ITEM_TYPE_NVGRE:
 127                 case RTE_FLOW_ITEM_TYPE_VXLAN:
 128                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
 129                 case RTE_FLOW_ITEM_TYPE_GENEVE:
 130                 case RTE_FLOW_ITEM_TYPE_MPLS:
 131                         if (tunnel_decap)
 132                                 attr->attr = 0;
 133                         break;
 134                 case RTE_FLOW_ITEM_TYPE_IPV4:
 135                         if (!attr->ipv6)
 136                                 attr->ipv4 = 1;
 137                         if (item->mask != NULL &&
 138                             ((const struct rte_flow_item_ipv4 *)
 139                             item->mask)->hdr.next_proto_id)
 140                                 next_protocol =
 141                                     ((const struct rte_flow_item_ipv4 *)
 142                                       (item->spec))->hdr.next_proto_id &
 143                                     ((const struct rte_flow_item_ipv4 *)
 144                                       (item->mask))->hdr.next_proto_id;
 145                         if ((next_protocol == IPPROTO_IPIP ||
 146                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 147                                 attr->attr = 0;
 148                         break;
 149                 case RTE_FLOW_ITEM_TYPE_IPV6:
 150                         if (!attr->ipv4)
 151                                 attr->ipv6 = 1;
 152                         if (item->mask != NULL &&
 153                             ((const struct rte_flow_item_ipv6 *)
 154                             item->mask)->hdr.proto)
 155                                 next_protocol =
 156                                     ((const struct rte_flow_item_ipv6 *)
 157                                       (item->spec))->hdr.proto &
 158                                     ((const struct rte_flow_item_ipv6 *)
 159                                       (item->mask))->hdr.proto;
 160                         if ((next_protocol == IPPROTO_IPIP ||
 161                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 162                                 attr->attr = 0;
 163                         break;
 164                 case RTE_FLOW_ITEM_TYPE_UDP:
 165                         if (!attr->tcp)
 166                                 attr->udp = 1;
 167                         break;
 168                 case RTE_FLOW_ITEM_TYPE_TCP:
 169                         if (!attr->udp)
 170                                 attr->tcp = 1;
 171                         break;
 172                 default:
 173                         break;
 174                 }
 175         }
 176         attr->valid = 1;
 177 }
 178
 179 /**
 180  * Convert rte_mtr_color to mlx5 color.
 181  *
 182  * @param[in] rcol
 183  *   rte_mtr_color.
 184  *
 185  * @return
 186  *   mlx5 color.
 187  */
 188 static int
 189 rte_col_2_mlx5_col(enum rte_color rcol)
 190 {
 191         switch (rcol) {
 192         case RTE_COLOR_GREEN:
 193                 return MLX5_FLOW_COLOR_GREEN;
 194         case RTE_COLOR_YELLOW:
 195                 return MLX5_FLOW_COLOR_YELLOW;
 196         case RTE_COLOR_RED:
 197                 return MLX5_FLOW_COLOR_RED;
 198         default:
 199                 break;
 200         }
 201         return MLX5_FLOW_COLOR_UNDEFINED;
 202 }
 203
 204 struct field_modify_info {
 205         uint32_t size; /* Size of field in protocol header, in bytes. */
 206         uint32_t offset; /* Offset of field in protocol header, in bytes. */
 207         enum mlx5_modification_field id;
 208 };
 209
 210 struct field_modify_info modify_eth[] = {
 211         {4,  0, MLX5_MODI_OUT_DMAC_47_16},
 212         {2,  4, MLX5_MODI_OUT_DMAC_15_0},
 213         {4,  6, MLX5_MODI_OUT_SMAC_47_16},
 214         {2, 10, MLX5_MODI_OUT_SMAC_15_0},
 215         {0, 0, 0},
 216 };
 217
 218 struct field_modify_info modify_vlan_out_first_vid[] = {
 219         /* Size in bits !!! */
 220         {12, 0, MLX5_MODI_OUT_FIRST_VID},
 221         {0, 0, 0},
 222 };
 223
 224 struct field_modify_info modify_ipv4[] = {
 225         {1,  1, MLX5_MODI_OUT_IP_DSCP},
 226         {1,  8, MLX5_MODI_OUT_IPV4_TTL},
 227         {4, 12, MLX5_MODI_OUT_SIPV4},
 228         {4, 16, MLX5_MODI_OUT_DIPV4},
 229         {0, 0, 0},
 230 };
 231
 232 struct field_modify_info modify_ipv6[] = {
 233         {1,  0, MLX5_MODI_OUT_IP_DSCP},
 234         {1,  7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
 235         {4,  8, MLX5_MODI_OUT_SIPV6_127_96},
 236         {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
 237         {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
 238         {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
 239         {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
 240         {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
 241         {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
 242         {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
 243         {0, 0, 0},
 244 };
 245
 246 struct field_modify_info modify_udp[] = {
 247         {2, 0, MLX5_MODI_OUT_UDP_SPORT},
 248         {2, 2, MLX5_MODI_OUT_UDP_DPORT},
 249         {0, 0, 0},
 250 };
 251
 252 struct field_modify_info modify_tcp[] = {
 253         {2, 0, MLX5_MODI_OUT_TCP_SPORT},
 254         {2, 2, MLX5_MODI_OUT_TCP_DPORT},
 255         {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
 256         {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
 257         {0, 0, 0},
 258 };
 259
 260 static void
 261 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
 262                           uint8_t next_protocol, uint64_t *item_flags,
 263                           int *tunnel)
 264 {
 265         MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
 266                     item->type == RTE_FLOW_ITEM_TYPE_IPV6);
 267         if (next_protocol == IPPROTO_IPIP) {
 268                 *item_flags |= MLX5_FLOW_LAYER_IPIP;
 269                 *tunnel = 1;
 270         }
 271         if (next_protocol == IPPROTO_IPV6) {
 272                 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
 273                 *tunnel = 1;
 274         }
 275 }
 276
 277 /**
 278  * Acquire the synchronizing object to protect multithreaded access
 279  * to shared dv context. Lock occurs only if context is actually
 280  * shared, i.e. we have multiport IB device and representors are
 281  * created.
 282  *
 283  * @param[in] dev
 284  *   Pointer to the rte_eth_dev structure.
 285  */
 286 static void
 287 flow_dv_shared_lock(struct rte_eth_dev *dev)
 288 {
 289         struct mlx5_priv *priv = dev->data->dev_private;
 290         struct mlx5_ibv_shared *sh = priv->sh;
 291
 292         if (sh->dv_refcnt > 1) {
 293                 int ret;
 294
 295                 ret = pthread_mutex_lock(&sh->dv_mutex);
 296                 MLX5_ASSERT(!ret);
 297                 (void)ret;
 298         }
 299 }
 300
 301 static void
 302 flow_dv_shared_unlock(struct rte_eth_dev *dev)
 303 {
 304         struct mlx5_priv *priv = dev->data->dev_private;
 305         struct mlx5_ibv_shared *sh = priv->sh;
 306
 307         if (sh->dv_refcnt > 1) {
 308                 int ret;
 309
 310                 ret = pthread_mutex_unlock(&sh->dv_mutex);
 311                 MLX5_ASSERT(!ret);
 312                 (void)ret;
 313         }
 314 }
 315
 316 /* Update VLAN's VID/PCP based on input rte_flow_action.
 317  *
 318  * @param[in] action
 319  *   Pointer to struct rte_flow_action.
 320  * @param[out] vlan
 321  *   Pointer to struct rte_vlan_hdr.
 322  */
 323 static void
 324 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
 325                          struct rte_vlan_hdr *vlan)
 326 {
 327         uint16_t vlan_tci;
 328         if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
 329                 vlan_tci =
 330                     ((const struct rte_flow_action_of_set_vlan_pcp *)
 331                                                action->conf)->vlan_pcp;
 332                 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
 333                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
 334                 vlan->vlan_tci |= vlan_tci;
 335         } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
 336                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
 337                 vlan->vlan_tci |= rte_be_to_cpu_16
 338                     (((const struct rte_flow_action_of_set_vlan_vid *)
 339                                              action->conf)->vlan_vid);
 340         }
 341 }
 342
 343 /**
 344  * Fetch 1, 2, 3 or 4 byte field from the byte array
 345  * and return as unsigned integer in host-endian format.
 346  *
 347  * @param[in] data
 348  *   Pointer to data array.
 349  * @param[in] size
 350  *   Size of field to extract.
 351  *
 352  * @return
 353  *   converted field in host endian format.
 354  */
 355 static inline uint32_t
 356 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
 357 {
 358         uint32_t ret;
 359
 360         switch (size) {
 361         case 1:
 362                 ret = *data;
 363                 break;
 364         case 2:
 365                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 366                 break;
 367         case 3:
 368                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 369                 ret = (ret << 8) | *(data + sizeof(uint16_t));
 370                 break;
 371         case 4:
 372                 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
 373                 break;
 374         default:
 375                 MLX5_ASSERT(false);
 376                 ret = 0;
 377                 break;
 378         }
 379         return ret;
 380 }
 381
 382 /**
 383  * Convert modify-header action to DV specification.
 384  *
 385  * Data length of each action is determined by provided field description
 386  * and the item mask. Data bit offset and width of each action is determined
 387  * by provided item mask.
 388  *
 389  * @param[in] item
 390  *   Pointer to item specification.
 391  * @param[in] field
 392  *   Pointer to field modification information.
 393  *     For MLX5_MODIFICATION_TYPE_SET specifies destination field.
 394  *     For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
 395  *     For MLX5_MODIFICATION_TYPE_COPY specifies source field.
 396  * @param[in] dcopy
 397  *   Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
 398  *   Negative offset value sets the same offset as source offset.
 399  *   size field is ignored, value is taken from source field.
 400  * @param[in,out] resource
 401  *   Pointer to the modify-header resource.
 402  * @param[in] type
 403  *   Type of modification.
 404  * @param[out] error
 405  *   Pointer to the error structure.
 406  *
 407  * @return
 408  *   0 on success, a negative errno value otherwise and rte_errno is set.
 409  */
 410 static int
 411 flow_dv_convert_modify_action(struct rte_flow_item *item,
 412                               struct field_modify_info *field,
 413                               struct field_modify_info *dcopy,
 414                               struct mlx5_flow_dv_modify_hdr_resource *resource,
 415                               uint32_t type, struct rte_flow_error *error)
 416 {
 417         uint32_t i = resource->actions_num;
 418         struct mlx5_modification_cmd *actions = resource->actions;
 419
 420         /*
 421          * The item and mask are provided in big-endian format.
 422          * The fields should be presented as in big-endian format either.
 423          * Mask must be always present, it defines the actual field width.
 424          */
 425         MLX5_ASSERT(item->mask);
 426         MLX5_ASSERT(field->size);
 427         do {
 428                 unsigned int size_b;
 429                 unsigned int off_b;
 430                 uint32_t mask;
 431                 uint32_t data;
 432
 433                 if (i >= MLX5_MAX_MODIFY_NUM)
 434                         return rte_flow_error_set(error, EINVAL,
 435                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 436                                  "too many items to modify");
 437                 /* Fetch variable byte size mask from the array. */
 438                 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
 439                                            field->offset, field->size);
 440                 if (!mask) {
 441                         ++field;
 442                         continue;
 443                 }
 444                 /* Deduce actual data width in bits from mask value. */
 445                 off_b = rte_bsf32(mask);
 446                 size_b = sizeof(uint32_t) * CHAR_BIT -
 447                          off_b - __builtin_clz(mask);
 448                 MLX5_ASSERT(size_b);
 449                 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
 450                 actions[i] = (struct mlx5_modification_cmd) {
 451                         .action_type = type,
 452                         .field = field->id,
 453                         .offset = off_b,
 454                         .length = size_b,
 455                 };
 456                 /* Convert entire record to expected big-endian format. */
 457                 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 458                 if (type == MLX5_MODIFICATION_TYPE_COPY) {
 459                         MLX5_ASSERT(dcopy);
 460                         actions[i].dst_field = dcopy->id;
 461                         actions[i].dst_offset =
 462                                 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
 463                         /* Convert entire record to big-endian format. */
 464                         actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
 465                 } else {
 466                         MLX5_ASSERT(item->spec);
 467                         data = flow_dv_fetch_field((const uint8_t *)item->spec +
 468                                                    field->offset, field->size);
 469                         /* Shift out the trailing masked bits from data. */
 470                         data = (data & mask) >> off_b;
 471                         actions[i].data1 = rte_cpu_to_be_32(data);
 472                 }
 473                 ++i;
 474                 ++field;
 475         } while (field->size);
 476         if (resource->actions_num == i)
 477                 return rte_flow_error_set(error, EINVAL,
 478                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 479                                           "invalid modification flow item");
 480         resource->actions_num = i;
 481         return 0;
 482 }
 483
 484 /**
 485  * Convert modify-header set IPv4 address action to DV specification.
 486  *
 487  * @param[in,out] resource
 488  *   Pointer to the modify-header resource.
 489  * @param[in] action
 490  *   Pointer to action specification.
 491  * @param[out] error
 492  *   Pointer to the error structure.
 493  *
 494  * @return
 495  *   0 on success, a negative errno value otherwise and rte_errno is set.
 496  */
 497 static int
 498 flow_dv_convert_action_modify_ipv4
 499                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 500                          const struct rte_flow_action *action,
 501                          struct rte_flow_error *error)
 502 {
 503         const struct rte_flow_action_set_ipv4 *conf =
 504                 (const struct rte_flow_action_set_ipv4 *)(action->conf);
 505         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
 506         struct rte_flow_item_ipv4 ipv4;
 507         struct rte_flow_item_ipv4 ipv4_mask;
 508
 509         memset(&ipv4, 0, sizeof(ipv4));
 510         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 511         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
 512                 ipv4.hdr.src_addr = conf->ipv4_addr;
 513                 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
 514         } else {
 515                 ipv4.hdr.dst_addr = conf->ipv4_addr;
 516                 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
 517         }
 518         item.spec = &ipv4;
 519         item.mask = &ipv4_mask;
 520         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
 521                                              MLX5_MODIFICATION_TYPE_SET, error);
 522 }
 523
 524 /**
 525  * Convert modify-header set IPv6 address action to DV specification.
 526  *
 527  * @param[in,out] resource
 528  *   Pointer to the modify-header resource.
 529  * @param[in] action
 530  *   Pointer to action specification.
 531  * @param[out] error
 532  *   Pointer to the error structure.
 533  *
 534  * @return
 535  *   0 on success, a negative errno value otherwise and rte_errno is set.
 536  */
 537 static int
 538 flow_dv_convert_action_modify_ipv6
 539                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 540                          const struct rte_flow_action *action,
 541                          struct rte_flow_error *error)
 542 {
 543         const struct rte_flow_action_set_ipv6 *conf =
 544                 (const struct rte_flow_action_set_ipv6 *)(action->conf);
 545         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
 546         struct rte_flow_item_ipv6 ipv6;
 547         struct rte_flow_item_ipv6 ipv6_mask;
 548
 549         memset(&ipv6, 0, sizeof(ipv6));
 550         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 551         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
 552                 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
 553                        sizeof(ipv6.hdr.src_addr));
 554                 memcpy(&ipv6_mask.hdr.src_addr,
 555                        &rte_flow_item_ipv6_mask.hdr.src_addr,
 556                        sizeof(ipv6.hdr.src_addr));
 557         } else {
 558                 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
 559                        sizeof(ipv6.hdr.dst_addr));
 560                 memcpy(&ipv6_mask.hdr.dst_addr,
 561                        &rte_flow_item_ipv6_mask.hdr.dst_addr,
 562                        sizeof(ipv6.hdr.dst_addr));
 563         }
 564         item.spec = &ipv6;
 565         item.mask = &ipv6_mask;
 566         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
 567                                              MLX5_MODIFICATION_TYPE_SET, error);
 568 }
 569
 570 /**
 571  * Convert modify-header set MAC address action to DV specification.
 572  *
 573  * @param[in,out] resource
 574  *   Pointer to the modify-header resource.
 575  * @param[in] action
 576  *   Pointer to action specification.
 577  * @param[out] error
 578  *   Pointer to the error structure.
 579  *
 580  * @return
 581  *   0 on success, a negative errno value otherwise and rte_errno is set.
 582  */
 583 static int
 584 flow_dv_convert_action_modify_mac
 585                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 586                          const struct rte_flow_action *action,
 587                          struct rte_flow_error *error)
 588 {
 589         const struct rte_flow_action_set_mac *conf =
 590                 (const struct rte_flow_action_set_mac *)(action->conf);
 591         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
 592         struct rte_flow_item_eth eth;
 593         struct rte_flow_item_eth eth_mask;
 594
 595         memset(&eth, 0, sizeof(eth));
 596         memset(&eth_mask, 0, sizeof(eth_mask));
 597         if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
 598                 memcpy(&eth.src.addr_bytes, &conf->mac_addr,
 599                        sizeof(eth.src.addr_bytes));
 600                 memcpy(&eth_mask.src.addr_bytes,
 601                        &rte_flow_item_eth_mask.src.addr_bytes,
 602                        sizeof(eth_mask.src.addr_bytes));
 603         } else {
 604                 memcpy(&eth.dst.addr_bytes, &conf->mac_addr,
 605                        sizeof(eth.dst.addr_bytes));
 606                 memcpy(&eth_mask.dst.addr_bytes,
 607                        &rte_flow_item_eth_mask.dst.addr_bytes,
 608                        sizeof(eth_mask.dst.addr_bytes));
 609         }
 610         item.spec = &eth;
 611         item.mask = &eth_mask;
 612         return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
 613                                              MLX5_MODIFICATION_TYPE_SET, error);
 614 }
 615
 616 /**
 617  * Convert modify-header set VLAN VID action to DV specification.
 618  *
 619  * @param[in,out] resource
 620  *   Pointer to the modify-header resource.
 621  * @param[in] action
 622  *   Pointer to action specification.
 623  * @param[out] error
 624  *   Pointer to the error structure.
 625  *
 626  * @return
 627  *   0 on success, a negative errno value otherwise and rte_errno is set.
 628  */
 629 static int
 630 flow_dv_convert_action_modify_vlan_vid
 631                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 632                          const struct rte_flow_action *action,
 633                          struct rte_flow_error *error)
 634 {
 635         const struct rte_flow_action_of_set_vlan_vid *conf =
 636                 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
 637         int i = resource->actions_num;
 638         struct mlx5_modification_cmd *actions = resource->actions;
 639         struct field_modify_info *field = modify_vlan_out_first_vid;
 640
 641         if (i >= MLX5_MAX_MODIFY_NUM)
 642                 return rte_flow_error_set(error, EINVAL,
 643                          RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 644                          "too many items to modify");
 645         actions[i] = (struct mlx5_modification_cmd) {
 646                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 647                 .field = field->id,
 648                 .length = field->size,
 649                 .offset = field->offset,
 650         };
 651         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 652         actions[i].data1 = conf->vlan_vid;
 653         actions[i].data1 = actions[i].data1 << 16;
 654         resource->actions_num = ++i;
 655         return 0;
 656 }
 657
 658 /**
 659  * Convert modify-header set TP action to DV specification.
 660  *
 661  * @param[in,out] resource
 662  *   Pointer to the modify-header resource.
 663  * @param[in] action
 664  *   Pointer to action specification.
 665  * @param[in] items
 666  *   Pointer to rte_flow_item objects list.
 667  * @param[in] attr
 668  *   Pointer to flow attributes structure.
 669  * @param[in] dev_flow
 670  *   Pointer to the sub flow.
 671  * @param[in] tunnel_decap
 672  *   Whether action is after tunnel decapsulation.
 673  * @param[out] error
 674  *   Pointer to the error structure.
 675  *
 676  * @return
 677  *   0 on success, a negative errno value otherwise and rte_errno is set.
 678  */
 679 static int
 680 flow_dv_convert_action_modify_tp
 681                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 682                          const struct rte_flow_action *action,
 683                          const struct rte_flow_item *items,
 684                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 685                          bool tunnel_decap, struct rte_flow_error *error)
 686 {
 687         const struct rte_flow_action_set_tp *conf =
 688                 (const struct rte_flow_action_set_tp *)(action->conf);
 689         struct rte_flow_item item;
 690         struct rte_flow_item_udp udp;
 691         struct rte_flow_item_udp udp_mask;
 692         struct rte_flow_item_tcp tcp;
 693         struct rte_flow_item_tcp tcp_mask;
 694         struct field_modify_info *field;
 695
 696         if (!attr->valid)
 697                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 698         if (attr->udp) {
 699                 memset(&udp, 0, sizeof(udp));
 700                 memset(&udp_mask, 0, sizeof(udp_mask));
 701                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 702                         udp.hdr.src_port = conf->port;
 703                         udp_mask.hdr.src_port =
 704                                         rte_flow_item_udp_mask.hdr.src_port;
 705                 } else {
 706                         udp.hdr.dst_port = conf->port;
 707                         udp_mask.hdr.dst_port =
 708                                         rte_flow_item_udp_mask.hdr.dst_port;
 709                 }
 710                 item.type = RTE_FLOW_ITEM_TYPE_UDP;
 711                 item.spec = &udp;
 712                 item.mask = &udp_mask;
 713                 field = modify_udp;
 714         } else {
 715                 MLX5_ASSERT(attr->tcp);
 716                 memset(&tcp, 0, sizeof(tcp));
 717                 memset(&tcp_mask, 0, sizeof(tcp_mask));
 718                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 719                         tcp.hdr.src_port = conf->port;
 720                         tcp_mask.hdr.src_port =
 721                                         rte_flow_item_tcp_mask.hdr.src_port;
 722                 } else {
 723                         tcp.hdr.dst_port = conf->port;
 724                         tcp_mask.hdr.dst_port =
 725                                         rte_flow_item_tcp_mask.hdr.dst_port;
 726                 }
 727                 item.type = RTE_FLOW_ITEM_TYPE_TCP;
 728                 item.spec = &tcp;
 729                 item.mask = &tcp_mask;
 730                 field = modify_tcp;
 731         }
 732         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 733                                              MLX5_MODIFICATION_TYPE_SET, error);
 734 }
 735
 736 /**
 737  * Convert modify-header set TTL action to DV specification.
 738  *
 739  * @param[in,out] resource
 740  *   Pointer to the modify-header resource.
 741  * @param[in] action
 742  *   Pointer to action specification.
 743  * @param[in] items
 744  *   Pointer to rte_flow_item objects list.
 745  * @param[in] attr
 746  *   Pointer to flow attributes structure.
 747  * @param[in] dev_flow
 748  *   Pointer to the sub flow.
 749  * @param[in] tunnel_decap
 750  *   Whether action is after tunnel decapsulation.
 751  * @param[out] error
 752  *   Pointer to the error structure.
 753  *
 754  * @return
 755  *   0 on success, a negative errno value otherwise and rte_errno is set.
 756  */
 757 static int
 758 flow_dv_convert_action_modify_ttl
 759                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 760                          const struct rte_flow_action *action,
 761                          const struct rte_flow_item *items,
 762                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 763                          bool tunnel_decap, struct rte_flow_error *error)
 764 {
 765         const struct rte_flow_action_set_ttl *conf =
 766                 (const struct rte_flow_action_set_ttl *)(action->conf);
 767         struct rte_flow_item item;
 768         struct rte_flow_item_ipv4 ipv4;
 769         struct rte_flow_item_ipv4 ipv4_mask;
 770         struct rte_flow_item_ipv6 ipv6;
 771         struct rte_flow_item_ipv6 ipv6_mask;
 772         struct field_modify_info *field;
 773
 774         if (!attr->valid)
 775                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 776         if (attr->ipv4) {
 777                 memset(&ipv4, 0, sizeof(ipv4));
 778                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 779                 ipv4.hdr.time_to_live = conf->ttl_value;
 780                 ipv4_mask.hdr.time_to_live = 0xFF;
 781                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 782                 item.spec = &ipv4;
 783                 item.mask = &ipv4_mask;
 784                 field = modify_ipv4;
 785         } else {
 786                 MLX5_ASSERT(attr->ipv6);
 787                 memset(&ipv6, 0, sizeof(ipv6));
 788                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 789                 ipv6.hdr.hop_limits = conf->ttl_value;
 790                 ipv6_mask.hdr.hop_limits = 0xFF;
 791                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 792                 item.spec = &ipv6;
 793                 item.mask = &ipv6_mask;
 794                 field = modify_ipv6;
 795         }
 796         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 797                                              MLX5_MODIFICATION_TYPE_SET, error);
 798 }
 799
 800 /**
 801  * Convert modify-header decrement TTL action to DV specification.
 802  *
 803  * @param[in,out] resource
 804  *   Pointer to the modify-header resource.
 805  * @param[in] action
 806  *   Pointer to action specification.
 807  * @param[in] items
 808  *   Pointer to rte_flow_item objects list.
 809  * @param[in] attr
 810  *   Pointer to flow attributes structure.
 811  * @param[in] dev_flow
 812  *   Pointer to the sub flow.
 813  * @param[in] tunnel_decap
 814  *   Whether action is after tunnel decapsulation.
 815  * @param[out] error
 816  *   Pointer to the error structure.
 817  *
 818  * @return
 819  *   0 on success, a negative errno value otherwise and rte_errno is set.
 820  */
 821 static int
 822 flow_dv_convert_action_modify_dec_ttl
 823                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 824                          const struct rte_flow_item *items,
 825                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 826                          bool tunnel_decap, struct rte_flow_error *error)
 827 {
 828         struct rte_flow_item item;
 829         struct rte_flow_item_ipv4 ipv4;
 830         struct rte_flow_item_ipv4 ipv4_mask;
 831         struct rte_flow_item_ipv6 ipv6;
 832         struct rte_flow_item_ipv6 ipv6_mask;
 833         struct field_modify_info *field;
 834
 835         if (!attr->valid)
 836                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 837         if (attr->ipv4) {
 838                 memset(&ipv4, 0, sizeof(ipv4));
 839                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 840                 ipv4.hdr.time_to_live = 0xFF;
 841                 ipv4_mask.hdr.time_to_live = 0xFF;
 842                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 843                 item.spec = &ipv4;
 844                 item.mask = &ipv4_mask;
 845                 field = modify_ipv4;
 846         } else {
 847                 MLX5_ASSERT(attr->ipv6);
 848                 memset(&ipv6, 0, sizeof(ipv6));
 849                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 850                 ipv6.hdr.hop_limits = 0xFF;
 851                 ipv6_mask.hdr.hop_limits = 0xFF;
 852                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 853                 item.spec = &ipv6;
 854                 item.mask = &ipv6_mask;
 855                 field = modify_ipv6;
 856         }
 857         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 858                                              MLX5_MODIFICATION_TYPE_ADD, error);
 859 }
 860
 861 /**
 862  * Convert modify-header increment/decrement TCP Sequence number
 863  * to DV specification.
 864  *
 865  * @param[in,out] resource
 866  *   Pointer to the modify-header resource.
 867  * @param[in] action
 868  *   Pointer to action specification.
 869  * @param[out] error
 870  *   Pointer to the error structure.
 871  *
 872  * @return
 873  *   0 on success, a negative errno value otherwise and rte_errno is set.
 874  */
 875 static int
 876 flow_dv_convert_action_modify_tcp_seq
 877                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 878                          const struct rte_flow_action *action,
 879                          struct rte_flow_error *error)
 880 {
 881         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 882         uint64_t value = rte_be_to_cpu_32(*conf);
 883         struct rte_flow_item item;
 884         struct rte_flow_item_tcp tcp;
 885         struct rte_flow_item_tcp tcp_mask;
 886
 887         memset(&tcp, 0, sizeof(tcp));
 888         memset(&tcp_mask, 0, sizeof(tcp_mask));
 889         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
 890                 /*
 891                  * The HW has no decrement operation, only increment operation.
 892                  * To simulate decrement X from Y using increment operation
 893                  * we need to add UINT32_MAX X times to Y.
 894                  * Each adding of UINT32_MAX decrements Y by 1.
 895                  */
 896                 value *= UINT32_MAX;
 897         tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
 898         tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
 899         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 900         item.spec = &tcp;
 901         item.mask = &tcp_mask;
 902         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 903                                              MLX5_MODIFICATION_TYPE_ADD, error);
 904 }
 905
 906 /**
 907  * Convert modify-header increment/decrement TCP Acknowledgment number
 908  * to DV specification.
 909  *
 910  * @param[in,out] resource
 911  *   Pointer to the modify-header resource.
 912  * @param[in] action
 913  *   Pointer to action specification.
 914  * @param[out] error
 915  *   Pointer to the error structure.
 916  *
 917  * @return
 918  *   0 on success, a negative errno value otherwise and rte_errno is set.
 919  */
 920 static int
 921 flow_dv_convert_action_modify_tcp_ack
 922                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 923                          const struct rte_flow_action *action,
 924                          struct rte_flow_error *error)
 925 {
 926         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 927         uint64_t value = rte_be_to_cpu_32(*conf);
 928         struct rte_flow_item item;
 929         struct rte_flow_item_tcp tcp;
 930         struct rte_flow_item_tcp tcp_mask;
 931
 932         memset(&tcp, 0, sizeof(tcp));
 933         memset(&tcp_mask, 0, sizeof(tcp_mask));
 934         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
 935                 /*
 936                  * The HW has no decrement operation, only increment operation.
 937                  * To simulate decrement X from Y using increment operation
 938                  * we need to add UINT32_MAX X times to Y.
 939                  * Each adding of UINT32_MAX decrements Y by 1.
 940                  */
 941                 value *= UINT32_MAX;
 942         tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
 943         tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
 944         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 945         item.spec = &tcp;
 946         item.mask = &tcp_mask;
 947         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 948                                              MLX5_MODIFICATION_TYPE_ADD, error);
 949 }
 950
 951 static enum mlx5_modification_field reg_to_field[] = {
 952         [REG_NONE] = MLX5_MODI_OUT_NONE,
 953         [REG_A] = MLX5_MODI_META_DATA_REG_A,
 954         [REG_B] = MLX5_MODI_META_DATA_REG_B,
 955         [REG_C_0] = MLX5_MODI_META_REG_C_0,
 956         [REG_C_1] = MLX5_MODI_META_REG_C_1,
 957         [REG_C_2] = MLX5_MODI_META_REG_C_2,
 958         [REG_C_3] = MLX5_MODI_META_REG_C_3,
 959         [REG_C_4] = MLX5_MODI_META_REG_C_4,
 960         [REG_C_5] = MLX5_MODI_META_REG_C_5,
 961         [REG_C_6] = MLX5_MODI_META_REG_C_6,
 962         [REG_C_7] = MLX5_MODI_META_REG_C_7,
 963 };
 964
 965 /**
 966  * Convert register set to DV specification.
 967  *
 968  * @param[in,out] resource
 969  *   Pointer to the modify-header resource.
 970  * @param[in] action
 971  *   Pointer to action specification.
 972  * @param[out] error
 973  *   Pointer to the error structure.
 974  *
 975  * @return
 976  *   0 on success, a negative errno value otherwise and rte_errno is set.
 977  */
 978 static int
 979 flow_dv_convert_action_set_reg
 980                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 981                          const struct rte_flow_action *action,
 982                          struct rte_flow_error *error)
 983 {
 984         const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
 985         struct mlx5_modification_cmd *actions = resource->actions;
 986         uint32_t i = resource->actions_num;
 987
 988         if (i >= MLX5_MAX_MODIFY_NUM)
 989                 return rte_flow_error_set(error, EINVAL,
 990                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 991                                           "too many items to modify");
 992         MLX5_ASSERT(conf->id != REG_NONE);
 993         MLX5_ASSERT(conf->id < RTE_DIM(reg_to_field));
 994         actions[i] = (struct mlx5_modification_cmd) {
 995                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 996                 .field = reg_to_field[conf->id],
 997         };
 998         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 999         actions[i].data1 = rte_cpu_to_be_32(conf->data);
1000         ++i;
1001         resource->actions_num = i;
1002         return 0;
1003 }
1004
1005 /**
1006  * Convert SET_TAG action to DV specification.
1007  *
1008  * @param[in] dev
1009  *   Pointer to the rte_eth_dev structure.
1010  * @param[in,out] resource
1011  *   Pointer to the modify-header resource.
1012  * @param[in] conf
1013  *   Pointer to action specification.
1014  * @param[out] error
1015  *   Pointer to the error structure.
1016  *
1017  * @return
1018  *   0 on success, a negative errno value otherwise and rte_errno is set.
1019  */
1020 static int
1021 flow_dv_convert_action_set_tag
1022                         (struct rte_eth_dev *dev,
1023                          struct mlx5_flow_dv_modify_hdr_resource *resource,
1024                          const struct rte_flow_action_set_tag *conf,
1025                          struct rte_flow_error *error)
1026 {
1027         rte_be32_t data = rte_cpu_to_be_32(conf->data);
1028         rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
1029         struct rte_flow_item item = {
1030                 .spec = &data,
1031                 .mask = &mask,
1032         };
1033         struct field_modify_info reg_c_x[] = {
1034                 [1] = {0, 0, 0},
1035         };
1036         enum mlx5_modification_field reg_type;
1037         int ret;
1038
1039         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1040         if (ret < 0)
1041                 return ret;
1042         MLX5_ASSERT(ret != REG_NONE);
1043         MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1044         reg_type = reg_to_field[ret];
1045         MLX5_ASSERT(reg_type > 0);
1046         reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1047         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1048                                              MLX5_MODIFICATION_TYPE_SET, error);
1049 }
1050
1051 /**
1052  * Convert internal COPY_REG action to DV specification.
1053  *
1054  * @param[in] dev
1055  *   Pointer to the rte_eth_dev structure.
1056  * @param[in,out] res
1057  *   Pointer to the modify-header resource.
1058  * @param[in] action
1059  *   Pointer to action specification.
1060  * @param[out] error
1061  *   Pointer to the error structure.
1062  *
1063  * @return
1064  *   0 on success, a negative errno value otherwise and rte_errno is set.
1065  */
1066 static int
1067 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1068                                  struct mlx5_flow_dv_modify_hdr_resource *res,
1069                                  const struct rte_flow_action *action,
1070                                  struct rte_flow_error *error)
1071 {
1072         const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1073         rte_be32_t mask = RTE_BE32(UINT32_MAX);
1074         struct rte_flow_item item = {
1075                 .spec = NULL,
1076                 .mask = &mask,
1077         };
1078         struct field_modify_info reg_src[] = {
1079                 {4, 0, reg_to_field[conf->src]},
1080                 {0, 0, 0},
1081         };
1082         struct field_modify_info reg_dst = {
1083                 .offset = 0,
1084                 .id = reg_to_field[conf->dst],
1085         };
1086         /* Adjust reg_c[0] usage according to reported mask. */
1087         if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1088                 struct mlx5_priv *priv = dev->data->dev_private;
1089                 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1090
1091                 MLX5_ASSERT(reg_c0);
1092                 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1093                 if (conf->dst == REG_C_0) {
1094                         /* Copy to reg_c[0], within mask only. */
1095                         reg_dst.offset = rte_bsf32(reg_c0);
1096                         /*
1097                          * Mask is ignoring the enianness, because
1098                          * there is no conversion in datapath.
1099                          */
1100 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1101                         /* Copy from destination lower bits to reg_c[0]. */
1102                         mask = reg_c0 >> reg_dst.offset;
1103 #else
1104                         /* Copy from destination upper bits to reg_c[0]. */
1105                         mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1106                                           rte_fls_u32(reg_c0));
1107 #endif
1108                 } else {
1109                         mask = rte_cpu_to_be_32(reg_c0);
1110 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1111                         /* Copy from reg_c[0] to destination lower bits. */
1112                         reg_dst.offset = 0;
1113 #else
1114                         /* Copy from reg_c[0] to destination upper bits. */
1115                         reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1116                                          (rte_fls_u32(reg_c0) -
1117                                           rte_bsf32(reg_c0));
1118 #endif
1119                 }
1120         }
1121         return flow_dv_convert_modify_action(&item,
1122                                              reg_src, &reg_dst, res,
1123                                              MLX5_MODIFICATION_TYPE_COPY,
1124                                              error);
1125 }
1126
1127 /**
1128  * Convert MARK action to DV specification. This routine is used
1129  * in extensive metadata only and requires metadata register to be
1130  * handled. In legacy mode hardware tag resource is engaged.
1131  *
1132  * @param[in] dev
1133  *   Pointer to the rte_eth_dev structure.
1134  * @param[in] conf
1135  *   Pointer to MARK action specification.
1136  * @param[in,out] resource
1137  *   Pointer to the modify-header resource.
1138  * @param[out] error
1139  *   Pointer to the error structure.
1140  *
1141  * @return
1142  *   0 on success, a negative errno value otherwise and rte_errno is set.
1143  */
1144 static int
1145 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1146                             const struct rte_flow_action_mark *conf,
1147                             struct mlx5_flow_dv_modify_hdr_resource *resource,
1148                             struct rte_flow_error *error)
1149 {
1150         struct mlx5_priv *priv = dev->data->dev_private;
1151         rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1152                                            priv->sh->dv_mark_mask);
1153         rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1154         struct rte_flow_item item = {
1155                 .spec = &data,
1156                 .mask = &mask,
1157         };
1158         struct field_modify_info reg_c_x[] = {
1159                 {4, 0, 0}, /* dynamic instead of MLX5_MODI_META_REG_C_1. */
1160                 {0, 0, 0},
1161         };
1162         int reg;
1163
1164         if (!mask)
1165                 return rte_flow_error_set(error, EINVAL,
1166                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1167                                           NULL, "zero mark action mask");
1168         reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1169         if (reg < 0)
1170                 return reg;
1171         MLX5_ASSERT(reg > 0);
1172         if (reg == REG_C_0) {
1173                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1174                 uint32_t shl_c0 = rte_bsf32(msk_c0);
1175
1176                 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1177                 mask = rte_cpu_to_be_32(mask) & msk_c0;
1178                 mask = rte_cpu_to_be_32(mask << shl_c0);
1179         }
1180         reg_c_x[0].id = reg_to_field[reg];
1181         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1182                                              MLX5_MODIFICATION_TYPE_SET, error);
1183 }
1184
1185 /**
1186  * Get metadata register index for specified steering domain.
1187  *
1188  * @param[in] dev
1189  *   Pointer to the rte_eth_dev structure.
1190  * @param[in] attr
1191  *   Attributes of flow to determine steering domain.
1192  * @param[out] error
1193  *   Pointer to the error structure.
1194  *
1195  * @return
1196  *   positive index on success, a negative errno value otherwise
1197  *   and rte_errno is set.
1198  */
1199 static enum modify_reg
1200 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1201                          const struct rte_flow_attr *attr,
1202                          struct rte_flow_error *error)
1203 {
1204         int reg =
1205                 mlx5_flow_get_reg_id(dev, attr->transfer ?
1206                                           MLX5_METADATA_FDB :
1207                                             attr->egress ?
1208                                             MLX5_METADATA_TX :
1209                                             MLX5_METADATA_RX, 0, error);
1210         if (reg < 0)
1211                 return rte_flow_error_set(error,
1212                                           ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1213                                           NULL, "unavailable "
1214                                           "metadata register");
1215         return reg;
1216 }
1217
1218 /**
1219  * Convert SET_META action to DV specification.
1220  *
1221  * @param[in] dev
1222  *   Pointer to the rte_eth_dev structure.
1223  * @param[in,out] resource
1224  *   Pointer to the modify-header resource.
1225  * @param[in] attr
1226  *   Attributes of flow that includes this item.
1227  * @param[in] conf
1228  *   Pointer to action specification.
1229  * @param[out] error
1230  *   Pointer to the error structure.
1231  *
1232  * @return
1233  *   0 on success, a negative errno value otherwise and rte_errno is set.
1234  */
1235 static int
1236 flow_dv_convert_action_set_meta
1237                         (struct rte_eth_dev *dev,
1238                          struct mlx5_flow_dv_modify_hdr_resource *resource,
1239                          const struct rte_flow_attr *attr,
1240                          const struct rte_flow_action_set_meta *conf,
1241                          struct rte_flow_error *error)
1242 {
1243         uint32_t data = conf->data;
1244         uint32_t mask = conf->mask;
1245         struct rte_flow_item item = {
1246                 .spec = &data,
1247                 .mask = &mask,
1248         };
1249         struct field_modify_info reg_c_x[] = {
1250                 [1] = {0, 0, 0},
1251         };
1252         int reg = flow_dv_get_metadata_reg(dev, attr, error);
1253
1254         if (reg < 0)
1255                 return reg;
1256         /*
1257          * In datapath code there is no endianness
1258          * coversions for perfromance reasons, all
1259          * pattern conversions are done in rte_flow.
1260          */
1261         if (reg == REG_C_0) {
1262                 struct mlx5_priv *priv = dev->data->dev_private;
1263                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1264                 uint32_t shl_c0;
1265
1266                 MLX5_ASSERT(msk_c0);
1267 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1268                 shl_c0 = rte_bsf32(msk_c0);
1269 #else
1270                 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1271 #endif
1272                 mask <<= shl_c0;
1273                 data <<= shl_c0;
1274                 MLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1275         }
1276         reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1277         /* The routine expects parameters in memory as big-endian ones. */
1278         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1279                                              MLX5_MODIFICATION_TYPE_SET, error);
1280 }
1281
1282 /**
1283  * Convert modify-header set IPv4 DSCP action to DV specification.
1284  *
1285  * @param[in,out] resource
1286  *   Pointer to the modify-header resource.
1287  * @param[in] action
1288  *   Pointer to action specification.
1289  * @param[out] error
1290  *   Pointer to the error structure.
1291  *
1292  * @return
1293  *   0 on success, a negative errno value otherwise and rte_errno is set.
1294  */
1295 static int
1296 flow_dv_convert_action_modify_ipv4_dscp
1297                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1298                          const struct rte_flow_action *action,
1299                          struct rte_flow_error *error)
1300 {
1301         const struct rte_flow_action_set_dscp *conf =
1302                 (const struct rte_flow_action_set_dscp *)(action->conf);
1303         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1304         struct rte_flow_item_ipv4 ipv4;
1305         struct rte_flow_item_ipv4 ipv4_mask;
1306
1307         memset(&ipv4, 0, sizeof(ipv4));
1308         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1309         ipv4.hdr.type_of_service = conf->dscp;
1310         ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1311         item.spec = &ipv4;
1312         item.mask = &ipv4_mask;
1313         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1314                                              MLX5_MODIFICATION_TYPE_SET, error);
1315 }
1316
1317 /**
1318  * Convert modify-header set IPv6 DSCP action to DV specification.
1319  *
1320  * @param[in,out] resource
1321  *   Pointer to the modify-header resource.
1322  * @param[in] action
1323  *   Pointer to action specification.
1324  * @param[out] error
1325  *   Pointer to the error structure.
1326  *
1327  * @return
1328  *   0 on success, a negative errno value otherwise and rte_errno is set.
1329  */
1330 static int
1331 flow_dv_convert_action_modify_ipv6_dscp
1332                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1333                          const struct rte_flow_action *action,
1334                          struct rte_flow_error *error)
1335 {
1336         const struct rte_flow_action_set_dscp *conf =
1337                 (const struct rte_flow_action_set_dscp *)(action->conf);
1338         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1339         struct rte_flow_item_ipv6 ipv6;
1340         struct rte_flow_item_ipv6 ipv6_mask;
1341
1342         memset(&ipv6, 0, sizeof(ipv6));
1343         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1344         /*
1345          * Even though the DSCP bits offset of IPv6 is not byte aligned,
1346          * rdma-core only accept the DSCP bits byte aligned start from
1347          * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1348          * bits in IPv6 case as rdma-core requires byte aligned value.
1349          */
1350         ipv6.hdr.vtc_flow = conf->dscp;
1351         ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1352         item.spec = &ipv6;
1353         item.mask = &ipv6_mask;
1354         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1355                                              MLX5_MODIFICATION_TYPE_SET, error);
1356 }
1357
1358 /**
1359  * Validate MARK item.
1360  *
1361  * @param[in] dev
1362  *   Pointer to the rte_eth_dev structure.
1363  * @param[in] item
1364  *   Item specification.
1365  * @param[in] attr
1366  *   Attributes of flow that includes this item.
1367  * @param[out] error
1368  *   Pointer to error structure.
1369  *
1370  * @return
1371  *   0 on success, a negative errno value otherwise and rte_errno is set.
1372  */
1373 static int
1374 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1375                            const struct rte_flow_item *item,
1376                            const struct rte_flow_attr *attr __rte_unused,
1377                            struct rte_flow_error *error)
1378 {
1379         struct mlx5_priv *priv = dev->data->dev_private;
1380         struct mlx5_dev_config *config = &priv->config;
1381         const struct rte_flow_item_mark *spec = item->spec;
1382         const struct rte_flow_item_mark *mask = item->mask;
1383         const struct rte_flow_item_mark nic_mask = {
1384                 .id = priv->sh->dv_mark_mask,
1385         };
1386         int ret;
1387
1388         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1389                 return rte_flow_error_set(error, ENOTSUP,
1390                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1391                                           "extended metadata feature"
1392                                           " isn't enabled");
1393         if (!mlx5_flow_ext_mreg_supported(dev))
1394                 return rte_flow_error_set(error, ENOTSUP,
1395                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1396                                           "extended metadata register"
1397                                           " isn't supported");
1398         if (!nic_mask.id)
1399                 return rte_flow_error_set(error, ENOTSUP,
1400                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1401                                           "extended metadata register"
1402                                           " isn't available");
1403         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1404         if (ret < 0)
1405                 return ret;
1406         if (!spec)
1407                 return rte_flow_error_set(error, EINVAL,
1408                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1409                                           item->spec,
1410                                           "data cannot be empty");
1411         if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1412                 return rte_flow_error_set(error, EINVAL,
1413                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1414                                           &spec->id,
1415                                           "mark id exceeds the limit");
1416         if (!mask)
1417                 mask = &nic_mask;
1418         if (!mask->id)
1419                 return rte_flow_error_set(error, EINVAL,
1420                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1421                                         "mask cannot be zero");
1422
1423         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1424                                         (const uint8_t *)&nic_mask,
1425                                         sizeof(struct rte_flow_item_mark),
1426                                         error);
1427         if (ret < 0)
1428                 return ret;
1429         return 0;
1430 }
1431
1432 /**
1433  * Validate META item.
1434  *
1435  * @param[in] dev
1436  *   Pointer to the rte_eth_dev structure.
1437  * @param[in] item
1438  *   Item specification.
1439  * @param[in] attr
1440  *   Attributes of flow that includes this item.
1441  * @param[out] error
1442  *   Pointer to error structure.
1443  *
1444  * @return
1445  *   0 on success, a negative errno value otherwise and rte_errno is set.
1446  */
1447 static int
1448 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1449                            const struct rte_flow_item *item,
1450                            const struct rte_flow_attr *attr,
1451                            struct rte_flow_error *error)
1452 {
1453         struct mlx5_priv *priv = dev->data->dev_private;
1454         struct mlx5_dev_config *config = &priv->config;
1455         const struct rte_flow_item_meta *spec = item->spec;
1456         const struct rte_flow_item_meta *mask = item->mask;
1457         struct rte_flow_item_meta nic_mask = {
1458                 .data = UINT32_MAX
1459         };
1460         int reg;
1461         int ret;
1462
1463         if (!spec)
1464                 return rte_flow_error_set(error, EINVAL,
1465                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1466                                           item->spec,
1467                                           "data cannot be empty");
1468         if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1469                 if (!mlx5_flow_ext_mreg_supported(dev))
1470                         return rte_flow_error_set(error, ENOTSUP,
1471                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1472                                           "extended metadata register"
1473                                           " isn't supported");
1474                 reg = flow_dv_get_metadata_reg(dev, attr, error);
1475                 if (reg < 0)
1476                         return reg;
1477                 if (reg == REG_B)
1478                         return rte_flow_error_set(error, ENOTSUP,
1479                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1480                                           "match on reg_b "
1481                                           "isn't supported");
1482                 if (reg != REG_A)
1483                         nic_mask.data = priv->sh->dv_meta_mask;
1484         }
1485         if (!mask)
1486                 mask = &rte_flow_item_meta_mask;
1487         if (!mask->data)
1488                 return rte_flow_error_set(error, EINVAL,
1489                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1490                                         "mask cannot be zero");
1491
1492         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1493                                         (const uint8_t *)&nic_mask,
1494                                         sizeof(struct rte_flow_item_meta),
1495                                         error);
1496         return ret;
1497 }
1498
1499 /**
1500  * Validate TAG item.
1501  *
1502  * @param[in] dev
1503  *   Pointer to the rte_eth_dev structure.
1504  * @param[in] item
1505  *   Item specification.
1506  * @param[in] attr
1507  *   Attributes of flow that includes this item.
1508  * @param[out] error
1509  *   Pointer to error structure.
1510  *
1511  * @return
1512  *   0 on success, a negative errno value otherwise and rte_errno is set.
1513  */
1514 static int
1515 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
1516                           const struct rte_flow_item *item,
1517                           const struct rte_flow_attr *attr __rte_unused,
1518                           struct rte_flow_error *error)
1519 {
1520         const struct rte_flow_item_tag *spec = item->spec;
1521         const struct rte_flow_item_tag *mask = item->mask;
1522         const struct rte_flow_item_tag nic_mask = {
1523                 .data = RTE_BE32(UINT32_MAX),
1524                 .index = 0xff,
1525         };
1526         int ret;
1527
1528         if (!mlx5_flow_ext_mreg_supported(dev))
1529                 return rte_flow_error_set(error, ENOTSUP,
1530                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1531                                           "extensive metadata register"
1532                                           " isn't supported");
1533         if (!spec)
1534                 return rte_flow_error_set(error, EINVAL,
1535                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1536                                           item->spec,
1537                                           "data cannot be empty");
1538         if (!mask)
1539                 mask = &rte_flow_item_tag_mask;
1540         if (!mask->data)
1541                 return rte_flow_error_set(error, EINVAL,
1542                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1543                                         "mask cannot be zero");
1544
1545         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1546                                         (const uint8_t *)&nic_mask,
1547                                         sizeof(struct rte_flow_item_tag),
1548                                         error);
1549         if (ret < 0)
1550                 return ret;
1551         if (mask->index != 0xff)
1552                 return rte_flow_error_set(error, EINVAL,
1553                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1554                                           "partial mask for tag index"
1555                                           " is not supported");
1556         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
1557         if (ret < 0)
1558                 return ret;
1559         MLX5_ASSERT(ret != REG_NONE);
1560         return 0;
1561 }
1562
1563 /**
1564  * Validate vport item.
1565  *
1566  * @param[in] dev
1567  *   Pointer to the rte_eth_dev structure.
1568  * @param[in] item
1569  *   Item specification.
1570  * @param[in] attr
1571  *   Attributes of flow that includes this item.
1572  * @param[in] item_flags
1573  *   Bit-fields that holds the items detected until now.
1574  * @param[out] error
1575  *   Pointer to error structure.
1576  *
1577  * @return
1578  *   0 on success, a negative errno value otherwise and rte_errno is set.
1579  */
1580 static int
1581 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
1582                               const struct rte_flow_item *item,
1583                               const struct rte_flow_attr *attr,
1584                               uint64_t item_flags,
1585                               struct rte_flow_error *error)
1586 {
1587         const struct rte_flow_item_port_id *spec = item->spec;
1588         const struct rte_flow_item_port_id *mask = item->mask;
1589         const struct rte_flow_item_port_id switch_mask = {
1590                         .id = 0xffffffff,
1591         };
1592         struct mlx5_priv *esw_priv;
1593         struct mlx5_priv *dev_priv;
1594         int ret;
1595
1596         if (!attr->transfer)
1597                 return rte_flow_error_set(error, EINVAL,
1598                                           RTE_FLOW_ERROR_TYPE_ITEM,
1599                                           NULL,
1600                                           "match on port id is valid only"
1601                                           " when transfer flag is enabled");
1602         if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
1603                 return rte_flow_error_set(error, ENOTSUP,
1604                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1605                                           "multiple source ports are not"
1606                                           " supported");
1607         if (!mask)
1608                 mask = &switch_mask;
1609         if (mask->id != 0xffffffff)
1610                 return rte_flow_error_set(error, ENOTSUP,
1611                                            RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1612                                            mask,
1613                                            "no support for partial mask on"
1614                                            " \"id\" field");
1615         ret = mlx5_flow_item_acceptable
1616                                 (item, (const uint8_t *)mask,
1617                                  (const uint8_t *)&rte_flow_item_port_id_mask,
1618                                  sizeof(struct rte_flow_item_port_id),
1619                                  error);
1620         if (ret)
1621                 return ret;
1622         if (!spec)
1623                 return 0;
1624         esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
1625         if (!esw_priv)
1626                 return rte_flow_error_set(error, rte_errno,
1627                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1628                                           "failed to obtain E-Switch info for"
1629                                           " port");
1630         dev_priv = mlx5_dev_to_eswitch_info(dev);
1631         if (!dev_priv)
1632                 return rte_flow_error_set(error, rte_errno,
1633                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1634                                           NULL,
1635                                           "failed to obtain E-Switch info");
1636         if (esw_priv->domain_id != dev_priv->domain_id)
1637                 return rte_flow_error_set(error, EINVAL,
1638                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1639                                           "cannot match on a port from a"
1640                                           " different E-Switch");
1641         return 0;
1642 }
1643
1644 /**
1645  * Validate GTP item.
1646  *
1647  * @param[in] dev
1648  *   Pointer to the rte_eth_dev structure.
1649  * @param[in] item
1650  *   Item specification.
1651  * @param[in] item_flags
1652  *   Bit-fields that holds the items detected until now.
1653  * @param[out] error
1654  *   Pointer to error structure.
1655  *
1656  * @return
1657  *   0 on success, a negative errno value otherwise and rte_errno is set.
1658  */
1659 static int
1660 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
1661                           const struct rte_flow_item *item,
1662                           uint64_t item_flags,
1663                           struct rte_flow_error *error)
1664 {
1665         struct mlx5_priv *priv = dev->data->dev_private;
1666         const struct rte_flow_item_gtp *mask = item->mask;
1667         const struct rte_flow_item_gtp nic_mask = {
1668                 .msg_type = 0xff,
1669                 .teid = RTE_BE32(0xffffffff),
1670         };
1671
1672         if (!priv->config.hca_attr.tunnel_stateless_gtp)
1673                 return rte_flow_error_set(error, ENOTSUP,
1674                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1675                                           "GTP support is not enabled");
1676         if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
1677                 return rte_flow_error_set(error, ENOTSUP,
1678                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1679                                           "multiple tunnel layers not"
1680                                           " supported");
1681         if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
1682                 return rte_flow_error_set(error, EINVAL,
1683                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1684                                           "no outer UDP layer found");
1685         if (!mask)
1686                 mask = &rte_flow_item_gtp_mask;
1687         return mlx5_flow_item_acceptable
1688                 (item, (const uint8_t *)mask,
1689                  (const uint8_t *)&nic_mask,
1690                  sizeof(struct rte_flow_item_gtp),
1691                  error);
1692 }
1693
1694 /**
1695  * Validate the pop VLAN action.
1696  *
1697  * @param[in] dev
1698  *   Pointer to the rte_eth_dev structure.
1699  * @param[in] action_flags
1700  *   Holds the actions detected until now.
1701  * @param[in] action
1702  *   Pointer to the pop vlan action.
1703  * @param[in] item_flags
1704  *   The items found in this flow rule.
1705  * @param[in] attr
1706  *   Pointer to flow attributes.
1707  * @param[out] error
1708  *   Pointer to error structure.
1709  *
1710  * @return
1711  *   0 on success, a negative errno value otherwise and rte_errno is set.
1712  */
1713 static int
1714 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
1715                                  uint64_t action_flags,
1716                                  const struct rte_flow_action *action,
1717                                  uint64_t item_flags,
1718                                  const struct rte_flow_attr *attr,
1719                                  struct rte_flow_error *error)
1720 {
1721         const struct mlx5_priv *priv = dev->data->dev_private;
1722
1723         (void)action;
1724         (void)attr;
1725         if (!priv->sh->pop_vlan_action)
1726                 return rte_flow_error_set(error, ENOTSUP,
1727                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1728                                           NULL,
1729                                           "pop vlan action is not supported");
1730         if (attr->egress)
1731                 return rte_flow_error_set(error, ENOTSUP,
1732                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1733                                           NULL,
1734                                           "pop vlan action not supported for "
1735                                           "egress");
1736         if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
1737                 return rte_flow_error_set(error, ENOTSUP,
1738                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1739                                           "no support for multiple VLAN "
1740                                           "actions");
1741         if (!(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1742                 return rte_flow_error_set(error, ENOTSUP,
1743                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1744                                           NULL,
1745                                           "cannot pop vlan without a "
1746                                           "match on (outer) vlan in the flow");
1747         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1748                 return rte_flow_error_set(error, EINVAL,
1749                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1750                                           "wrong action order, port_id should "
1751                                           "be after pop VLAN action");
1752         if (!attr->transfer && priv->representor)
1753                 return rte_flow_error_set(error, ENOTSUP,
1754                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1755                                           "pop vlan action for VF representor "
1756                                           "not supported on NIC table");
1757         return 0;
1758 }
1759
1760 /**
1761  * Get VLAN default info from vlan match info.
1762  *
1763  * @param[in] items
1764  *   the list of item specifications.
1765  * @param[out] vlan
1766  *   pointer VLAN info to fill to.
1767  *
1768  * @return
1769  *   0 on success, a negative errno value otherwise and rte_errno is set.
1770  */
1771 static void
1772 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
1773                                   struct rte_vlan_hdr *vlan)
1774 {
1775         const struct rte_flow_item_vlan nic_mask = {
1776                 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
1777                                 MLX5DV_FLOW_VLAN_VID_MASK),
1778                 .inner_type = RTE_BE16(0xffff),
1779         };
1780
1781         if (items == NULL)
1782                 return;
1783         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
1784                 int type = items->type;
1785
1786                 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
1787                     type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
1788                         break;
1789         }
1790         if (items->type != RTE_FLOW_ITEM_TYPE_END) {
1791                 const struct rte_flow_item_vlan *vlan_m = items->mask;
1792                 const struct rte_flow_item_vlan *vlan_v = items->spec;
1793
1794                 if (!vlan_m)
1795                         vlan_m = &nic_mask;
1796                 /* Only full match values are accepted */
1797                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
1798                      MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
1799                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
1800                         vlan->vlan_tci |=
1801                                 rte_be_to_cpu_16(vlan_v->tci &
1802                                                  MLX5DV_FLOW_VLAN_PCP_MASK_BE);
1803                 }
1804                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
1805                      MLX5DV_FLOW_VLAN_VID_MASK_BE) {
1806                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
1807                         vlan->vlan_tci |=
1808                                 rte_be_to_cpu_16(vlan_v->tci &
1809                                                  MLX5DV_FLOW_VLAN_VID_MASK_BE);
1810                 }
1811                 if (vlan_m->inner_type == nic_mask.inner_type)
1812                         vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
1813                                                            vlan_m->inner_type);
1814         }
1815 }
1816
1817 /**
1818  * Validate the push VLAN action.
1819  *
1820  * @param[in] dev
1821  *   Pointer to the rte_eth_dev structure.
1822  * @param[in] action_flags
1823  *   Holds the actions detected until now.
1824  * @param[in] item_flags
1825  *   The items found in this flow rule.
1826  * @param[in] action
1827  *   Pointer to the action structure.
1828  * @param[in] attr
1829  *   Pointer to flow attributes
1830  * @param[out] error
1831  *   Pointer to error structure.
1832  *
1833  * @return
1834  *   0 on success, a negative errno value otherwise and rte_errno is set.
1835  */
1836 static int
1837 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
1838                                   uint64_t action_flags,
1839                                   uint64_t item_flags __rte_unused,
1840                                   const struct rte_flow_action *action,
1841                                   const struct rte_flow_attr *attr,
1842                                   struct rte_flow_error *error)
1843 {
1844         const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
1845         const struct mlx5_priv *priv = dev->data->dev_private;
1846
1847         if (!attr->transfer && attr->ingress)
1848                 return rte_flow_error_set(error, ENOTSUP,
1849                                           RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1850                                           NULL,
1851                                           "push VLAN action not supported for "
1852                                           "ingress");
1853         if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
1854             push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
1855                 return rte_flow_error_set(error, EINVAL,
1856                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1857                                           "invalid vlan ethertype");
1858         if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
1859                 return rte_flow_error_set(error, ENOTSUP,
1860                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1861                                           "no support for multiple VLAN "
1862                                           "actions");
1863         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1864                 return rte_flow_error_set(error, EINVAL,
1865                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1866                                           "wrong action order, port_id should "
1867                                           "be after push VLAN");
1868         if (!attr->transfer && priv->representor)
1869                 return rte_flow_error_set(error, ENOTSUP,
1870                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1871                                           "push vlan action for VF representor "
1872                                           "not supported on NIC table");
1873         (void)attr;
1874         return 0;
1875 }
1876
1877 /**
1878  * Validate the set VLAN PCP.
1879  *
1880  * @param[in] action_flags
1881  *   Holds the actions detected until now.
1882  * @param[in] actions
1883  *   Pointer to the list of actions remaining in the flow rule.
1884  * @param[out] error
1885  *   Pointer to error structure.
1886  *
1887  * @return
1888  *   0 on success, a negative errno value otherwise and rte_errno is set.
1889  */
1890 static int
1891 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
1892                                      const struct rte_flow_action actions[],
1893                                      struct rte_flow_error *error)
1894 {
1895         const struct rte_flow_action *action = actions;
1896         const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
1897
1898         if (conf->vlan_pcp > 7)
1899                 return rte_flow_error_set(error, EINVAL,
1900                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1901                                           "VLAN PCP value is too big");
1902         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
1903                 return rte_flow_error_set(error, ENOTSUP,
1904                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1905                                           "set VLAN PCP action must follow "
1906                                           "the push VLAN action");
1907         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
1908                 return rte_flow_error_set(error, ENOTSUP,
1909                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1910                                           "Multiple VLAN PCP modification are "
1911                                           "not supported");
1912         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1913                 return rte_flow_error_set(error, EINVAL,
1914                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1915                                           "wrong action order, port_id should "
1916                                           "be after set VLAN PCP");
1917         return 0;
1918 }
1919
1920 /**
1921  * Validate the set VLAN VID.
1922  *
1923  * @param[in] item_flags
1924  *   Holds the items detected in this rule.
1925  * @param[in] action_flags
1926  *   Holds the actions detected until now.
1927  * @param[in] actions
1928  *   Pointer to the list of actions remaining in the flow rule.
1929  * @param[out] error
1930  *   Pointer to error structure.
1931  *
1932  * @return
1933  *   0 on success, a negative errno value otherwise and rte_errno is set.
1934  */
1935 static int
1936 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
1937                                      uint64_t action_flags,
1938                                      const struct rte_flow_action actions[],
1939                                      struct rte_flow_error *error)
1940 {
1941         const struct rte_flow_action *action = actions;
1942         const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
1943
1944         if (conf->vlan_vid > RTE_BE16(0xFFE))
1945                 return rte_flow_error_set(error, EINVAL,
1946                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1947                                           "VLAN VID value is too big");
1948         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
1949             !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1950                 return rte_flow_error_set(error, ENOTSUP,
1951                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1952                                           "set VLAN VID action must follow push"
1953                                           " VLAN action or match on VLAN item");
1954         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
1955                 return rte_flow_error_set(error, ENOTSUP,
1956                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1957                                           "Multiple VLAN VID modifications are "
1958                                           "not supported");
1959         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1960                 return rte_flow_error_set(error, EINVAL,
1961                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1962                                           "wrong action order, port_id should "
1963                                           "be after set VLAN VID");
1964         return 0;
1965 }
1966
1967 /*
1968  * Validate the FLAG action.
1969  *
1970  * @param[in] dev
1971  *   Pointer to the rte_eth_dev structure.
1972  * @param[in] action_flags
1973  *   Holds the actions detected until now.
1974  * @param[in] attr
1975  *   Pointer to flow attributes
1976  * @param[out] error
1977  *   Pointer to error structure.
1978  *
1979  * @return
1980  *   0 on success, a negative errno value otherwise and rte_errno is set.
1981  */
1982 static int
1983 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
1984                              uint64_t action_flags,
1985                              const struct rte_flow_attr *attr,
1986                              struct rte_flow_error *error)
1987 {
1988         struct mlx5_priv *priv = dev->data->dev_private;
1989         struct mlx5_dev_config *config = &priv->config;
1990         int ret;
1991
1992         /* Fall back if no extended metadata register support. */
1993         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1994                 return mlx5_flow_validate_action_flag(action_flags, attr,
1995                                                       error);
1996         /* Extensive metadata mode requires registers. */
1997         if (!mlx5_flow_ext_mreg_supported(dev))
1998                 return rte_flow_error_set(error, ENOTSUP,
1999                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2000                                           "no metadata registers "
2001                                           "to support flag action");
2002         if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
2003                 return rte_flow_error_set(error, ENOTSUP,
2004                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2005                                           "extended metadata register"
2006                                           " isn't available");
2007         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2008         if (ret < 0)
2009                 return ret;
2010         MLX5_ASSERT(ret > 0);
2011         if (action_flags & MLX5_FLOW_ACTION_MARK)
2012                 return rte_flow_error_set(error, EINVAL,
2013                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2014                                           "can't mark and flag in same flow");
2015         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2016                 return rte_flow_error_set(error, EINVAL,
2017                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2018                                           "can't have 2 flag"
2019                                           " actions in same flow");
2020         return 0;
2021 }
2022
2023 /**
2024  * Validate MARK action.
2025  *
2026  * @param[in] dev
2027  *   Pointer to the rte_eth_dev structure.
2028  * @param[in] action
2029  *   Pointer to action.
2030  * @param[in] action_flags
2031  *   Holds the actions detected until now.
2032  * @param[in] attr
2033  *   Pointer to flow attributes
2034  * @param[out] error
2035  *   Pointer to error structure.
2036  *
2037  * @return
2038  *   0 on success, a negative errno value otherwise and rte_errno is set.
2039  */
2040 static int
2041 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
2042                              const struct rte_flow_action *action,
2043                              uint64_t action_flags,
2044                              const struct rte_flow_attr *attr,
2045                              struct rte_flow_error *error)
2046 {
2047         struct mlx5_priv *priv = dev->data->dev_private;
2048         struct mlx5_dev_config *config = &priv->config;
2049         const struct rte_flow_action_mark *mark = action->conf;
2050         int ret;
2051
2052         /* Fall back if no extended metadata register support. */
2053         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2054                 return mlx5_flow_validate_action_mark(action, action_flags,
2055                                                       attr, error);
2056         /* Extensive metadata mode requires registers. */
2057         if (!mlx5_flow_ext_mreg_supported(dev))
2058                 return rte_flow_error_set(error, ENOTSUP,
2059                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2060                                           "no metadata registers "
2061                                           "to support mark action");
2062         if (!priv->sh->dv_mark_mask)
2063                 return rte_flow_error_set(error, ENOTSUP,
2064                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2065                                           "extended metadata register"
2066                                           " isn't available");
2067         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2068         if (ret < 0)
2069                 return ret;
2070         MLX5_ASSERT(ret > 0);
2071         if (!mark)
2072                 return rte_flow_error_set(error, EINVAL,
2073                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2074                                           "configuration cannot be null");
2075         if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
2076                 return rte_flow_error_set(error, EINVAL,
2077                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2078                                           &mark->id,
2079                                           "mark id exceeds the limit");
2080         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2081                 return rte_flow_error_set(error, EINVAL,
2082                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2083                                           "can't flag and mark in same flow");
2084         if (action_flags & MLX5_FLOW_ACTION_MARK)
2085                 return rte_flow_error_set(error, EINVAL,
2086                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2087                                           "can't have 2 mark actions in same"
2088                                           " flow");
2089         return 0;
2090 }
2091
2092 /**
2093  * Validate SET_META action.
2094  *
2095  * @param[in] dev
2096  *   Pointer to the rte_eth_dev structure.
2097  * @param[in] action
2098  *   Pointer to the action structure.
2099  * @param[in] action_flags
2100  *   Holds the actions detected until now.
2101  * @param[in] attr
2102  *   Pointer to flow attributes
2103  * @param[out] error
2104  *   Pointer to error structure.
2105  *
2106  * @return
2107  *   0 on success, a negative errno value otherwise and rte_errno is set.
2108  */
2109 static int
2110 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
2111                                  const struct rte_flow_action *action,
2112                                  uint64_t action_flags __rte_unused,
2113                                  const struct rte_flow_attr *attr,
2114                                  struct rte_flow_error *error)
2115 {
2116         const struct rte_flow_action_set_meta *conf;
2117         uint32_t nic_mask = UINT32_MAX;
2118         int reg;
2119
2120         if (!mlx5_flow_ext_mreg_supported(dev))
2121                 return rte_flow_error_set(error, ENOTSUP,
2122                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2123                                           "extended metadata register"
2124                                           " isn't supported");
2125         reg = flow_dv_get_metadata_reg(dev, attr, error);
2126         if (reg < 0)
2127                 return reg;
2128         if (reg != REG_A && reg != REG_B) {
2129                 struct mlx5_priv *priv = dev->data->dev_private;
2130
2131                 nic_mask = priv->sh->dv_meta_mask;
2132         }
2133         if (!(action->conf))
2134                 return rte_flow_error_set(error, EINVAL,
2135                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2136                                           "configuration cannot be null");
2137         conf = (const struct rte_flow_action_set_meta *)action->conf;
2138         if (!conf->mask)
2139                 return rte_flow_error_set(error, EINVAL,
2140                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2141                                           "zero mask doesn't have any effect");
2142         if (conf->mask & ~nic_mask)
2143                 return rte_flow_error_set(error, EINVAL,
2144                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2145                                           "meta data must be within reg C0");
2146         return 0;
2147 }
2148
2149 /**
2150  * Validate SET_TAG action.
2151  *
2152  * @param[in] dev
2153  *   Pointer to the rte_eth_dev structure.
2154  * @param[in] action
2155  *   Pointer to the action structure.
2156  * @param[in] action_flags
2157  *   Holds the actions detected until now.
2158  * @param[in] attr
2159  *   Pointer to flow attributes
2160  * @param[out] error
2161  *   Pointer to error structure.
2162  *
2163  * @return
2164  *   0 on success, a negative errno value otherwise and rte_errno is set.
2165  */
2166 static int
2167 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
2168                                 const struct rte_flow_action *action,
2169                                 uint64_t action_flags,
2170                                 const struct rte_flow_attr *attr,
2171                                 struct rte_flow_error *error)
2172 {
2173         const struct rte_flow_action_set_tag *conf;
2174         const uint64_t terminal_action_flags =
2175                 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
2176                 MLX5_FLOW_ACTION_RSS;
2177         int ret;
2178
2179         if (!mlx5_flow_ext_mreg_supported(dev))
2180                 return rte_flow_error_set(error, ENOTSUP,
2181                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2182                                           "extensive metadata register"
2183                                           " isn't supported");
2184         if (!(action->conf))
2185                 return rte_flow_error_set(error, EINVAL,
2186                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2187                                           "configuration cannot be null");
2188         conf = (const struct rte_flow_action_set_tag *)action->conf;
2189         if (!conf->mask)
2190                 return rte_flow_error_set(error, EINVAL,
2191                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2192                                           "zero mask doesn't have any effect");
2193         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
2194         if (ret < 0)
2195                 return ret;
2196         if (!attr->transfer && attr->ingress &&
2197             (action_flags & terminal_action_flags))
2198                 return rte_flow_error_set(error, EINVAL,
2199                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2200                                           "set_tag has no effect"
2201                                           " with terminal actions");
2202         return 0;
2203 }
2204
2205 /**
2206  * Validate count action.
2207  *
2208  * @param[in] dev
2209  *   Pointer to rte_eth_dev structure.
2210  * @param[out] error
2211  *   Pointer to error structure.
2212  *
2213  * @return
2214  *   0 on success, a negative errno value otherwise and rte_errno is set.
2215  */
2216 static int
2217 flow_dv_validate_action_count(struct rte_eth_dev *dev,
2218                               struct rte_flow_error *error)
2219 {
2220         struct mlx5_priv *priv = dev->data->dev_private;
2221
2222         if (!priv->config.devx)
2223                 goto notsup_err;
2224 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
2225         return 0;
2226 #endif
2227 notsup_err:
2228         return rte_flow_error_set
2229                       (error, ENOTSUP,
2230                        RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2231                        NULL,
2232                        "count action not supported");
2233 }
2234
2235 /**
2236  * Validate the L2 encap action.
2237  *
2238  * @param[in] dev
2239  *   Pointer to the rte_eth_dev structure.
2240  * @param[in] action_flags
2241  *   Holds the actions detected until now.
2242  * @param[in] action
2243  *   Pointer to the action structure.
2244  * @param[in] attr
2245  *   Pointer to flow attributes.
2246  * @param[out] error
2247  *   Pointer to error structure.
2248  *
2249  * @return
2250  *   0 on success, a negative errno value otherwise and rte_errno is set.
2251  */
2252 static int
2253 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
2254                                  uint64_t action_flags,
2255                                  const struct rte_flow_action *action,
2256                                  const struct rte_flow_attr *attr,
2257                                  struct rte_flow_error *error)
2258 {
2259         const struct mlx5_priv *priv = dev->data->dev_private;
2260
2261         if (!(action->conf))
2262                 return rte_flow_error_set(error, EINVAL,
2263                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2264                                           "configuration cannot be null");
2265         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
2266                 return rte_flow_error_set(error, EINVAL,
2267                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2268                                           "can only have a single encap action "
2269                                           "in a flow");
2270         if (!attr->transfer && priv->representor)
2271                 return rte_flow_error_set(error, ENOTSUP,
2272                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2273                                           "encap action for VF representor "
2274                                           "not supported on NIC table");
2275         return 0;
2276 }
2277
2278 /**
2279  * Validate a decap action.
2280  *
2281  * @param[in] dev
2282  *   Pointer to the rte_eth_dev structure.
2283  * @param[in] action_flags
2284  *   Holds the actions detected until now.
2285  * @param[in] attr
2286  *   Pointer to flow attributes
2287  * @param[out] error
2288  *   Pointer to error structure.
2289  *
2290  * @return
2291  *   0 on success, a negative errno value otherwise and rte_errno is set.
2292  */
2293 static int
2294 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
2295                               uint64_t action_flags,
2296                               const struct rte_flow_attr *attr,
2297                               struct rte_flow_error *error)
2298 {
2299         const struct mlx5_priv *priv = dev->data->dev_private;
2300
2301         if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
2302                 return rte_flow_error_set(error, ENOTSUP,
2303                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2304                                           action_flags &
2305                                           MLX5_FLOW_ACTION_DECAP ? "can only "
2306                                           "have a single decap action" : "decap "
2307                                           "after encap is not supported");
2308         if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
2309                 return rte_flow_error_set(error, EINVAL,
2310                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2311                                           "can't have decap action after"
2312                                           " modify action");
2313         if (attr->egress)
2314                 return rte_flow_error_set(error, ENOTSUP,
2315                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2316                                           NULL,
2317                                           "decap action not supported for "
2318                                           "egress");
2319         if (!attr->transfer && priv->representor)
2320                 return rte_flow_error_set(error, ENOTSUP,
2321                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2322                                           "decap action for VF representor "
2323                                           "not supported on NIC table");
2324         return 0;
2325 }
2326
2327 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
2328
2329 /**
2330  * Validate the raw encap and decap actions.
2331  *
2332  * @param[in] dev
2333  *   Pointer to the rte_eth_dev structure.
2334  * @param[in] decap
2335  *   Pointer to the decap action.
2336  * @param[in] encap
2337  *   Pointer to the encap action.
2338  * @param[in] attr
2339  *   Pointer to flow attributes
2340  * @param[in/out] action_flags
2341  *   Holds the actions detected until now.
2342  * @param[out] actions_n
2343  *   pointer to the number of actions counter.
2344  * @param[out] error
2345  *   Pointer to error structure.
2346  *
2347  * @return
2348  *   0 on success, a negative errno value otherwise and rte_errno is set.
2349  */
2350 static int
2351 flow_dv_validate_action_raw_encap_decap
2352         (struct rte_eth_dev *dev,
2353          const struct rte_flow_action_raw_decap *decap,
2354          const struct rte_flow_action_raw_encap *encap,
2355          const struct rte_flow_attr *attr, uint64_t *action_flags,
2356          int *actions_n, struct rte_flow_error *error)
2357 {
2358         const struct mlx5_priv *priv = dev->data->dev_private;
2359         int ret;
2360
2361         if (encap && (!encap->size || !encap->data))
2362                 return rte_flow_error_set(error, EINVAL,
2363                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2364                                           "raw encap data cannot be empty");
2365         if (decap && encap) {
2366                 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
2367                     encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
2368                         /* L3 encap. */
2369                         decap = NULL;
2370                 else if (encap->size <=
2371                            MLX5_ENCAPSULATION_DECISION_SIZE &&
2372                            decap->size >
2373                            MLX5_ENCAPSULATION_DECISION_SIZE)
2374                         /* L3 decap. */
2375                         encap = NULL;
2376                 else if (encap->size >
2377                            MLX5_ENCAPSULATION_DECISION_SIZE &&
2378                            decap->size >
2379                            MLX5_ENCAPSULATION_DECISION_SIZE)
2380                         /* 2 L2 actions: encap and decap. */
2381                         ;
2382                 else
2383                         return rte_flow_error_set(error,
2384                                 ENOTSUP,
2385                                 RTE_FLOW_ERROR_TYPE_ACTION,
2386                                 NULL, "unsupported too small "
2387                                 "raw decap and too small raw "
2388                                 "encap combination");
2389         }
2390         if (decap) {
2391                 ret = flow_dv_validate_action_decap(dev, *action_flags, attr,
2392                                                     error);
2393                 if (ret < 0)
2394                         return ret;
2395                 *action_flags |= MLX5_FLOW_ACTION_DECAP;
2396                 ++(*actions_n);
2397         }
2398         if (encap) {
2399                 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
2400                         return rte_flow_error_set(error, ENOTSUP,
2401                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2402                                                   NULL,
2403                                                   "small raw encap size");
2404                 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
2405                         return rte_flow_error_set(error, EINVAL,
2406                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2407                                                   NULL,
2408                                                   "more than one encap action");
2409                 if (!attr->transfer && priv->representor)
2410                         return rte_flow_error_set
2411                                         (error, ENOTSUP,
2412                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2413                                          "encap action for VF representor "
2414                                          "not supported on NIC table");
2415                 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
2416                 ++(*actions_n);
2417         }
2418         return 0;
2419 }
2420
2421 /**
2422  * Find existing encap/decap resource or create and register a new one.
2423  *
2424  * @param[in, out] dev
2425  *   Pointer to rte_eth_dev structure.
2426  * @param[in, out] resource
2427  *   Pointer to encap/decap resource.
2428  * @parm[in, out] dev_flow
2429  *   Pointer to the dev_flow.
2430  * @param[out] error
2431  *   pointer to error structure.
2432  *
2433  * @return
2434  *   0 on success otherwise -errno and errno is set.
2435  */
2436 static int
2437 flow_dv_encap_decap_resource_register
2438                         (struct rte_eth_dev *dev,
2439                          struct mlx5_flow_dv_encap_decap_resource *resource,
2440                          struct mlx5_flow *dev_flow,
2441                          struct rte_flow_error *error)
2442 {
2443         struct mlx5_priv *priv = dev->data->dev_private;
2444         struct mlx5_ibv_shared *sh = priv->sh;
2445         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2446         struct mlx5dv_dr_domain *domain;
2447
2448         resource->flags = dev_flow->dv.group ? 0 : 1;
2449         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2450                 domain = sh->fdb_domain;
2451         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2452                 domain = sh->rx_domain;
2453         else
2454                 domain = sh->tx_domain;
2455         /* Lookup a matching resource from cache. */
2456         LIST_FOREACH(cache_resource, &sh->encaps_decaps, next) {
2457                 if (resource->reformat_type == cache_resource->reformat_type &&
2458                     resource->ft_type == cache_resource->ft_type &&
2459                     resource->flags == cache_resource->flags &&
2460                     resource->size == cache_resource->size &&
2461                     !memcmp((const void *)resource->buf,
2462                             (const void *)cache_resource->buf,
2463                             resource->size)) {
2464                         DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d++",
2465                                 (void *)cache_resource,
2466                                 rte_atomic32_read(&cache_resource->refcnt));
2467                         rte_atomic32_inc(&cache_resource->refcnt);
2468                         dev_flow->handle->dvh.encap_decap = cache_resource;
2469                         return 0;
2470                 }
2471         }
2472         /* Register new encap/decap resource. */
2473         cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
2474         if (!cache_resource)
2475                 return rte_flow_error_set(error, ENOMEM,
2476                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2477                                           "cannot allocate resource memory");
2478         *cache_resource = *resource;
2479         cache_resource->verbs_action =
2480                 mlx5_glue->dv_create_flow_action_packet_reformat
2481                         (sh->ctx, cache_resource->reformat_type,
2482                          cache_resource->ft_type, domain, cache_resource->flags,
2483                          cache_resource->size,
2484                          (cache_resource->size ? cache_resource->buf : NULL));
2485         if (!cache_resource->verbs_action) {
2486                 rte_free(cache_resource);
2487                 return rte_flow_error_set(error, ENOMEM,
2488                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2489                                           NULL, "cannot create action");
2490         }
2491         rte_atomic32_init(&cache_resource->refcnt);
2492         rte_atomic32_inc(&cache_resource->refcnt);
2493         LIST_INSERT_HEAD(&sh->encaps_decaps, cache_resource, next);
2494         dev_flow->handle->dvh.encap_decap = cache_resource;
2495         DRV_LOG(DEBUG, "new encap/decap resource %p: refcnt %d++",
2496                 (void *)cache_resource,
2497                 rte_atomic32_read(&cache_resource->refcnt));
2498         return 0;
2499 }
2500
2501 /**
2502  * Find existing table jump resource or create and register a new one.
2503  *
2504  * @param[in, out] dev
2505  *   Pointer to rte_eth_dev structure.
2506  * @param[in, out] tbl
2507  *   Pointer to flow table resource.
2508  * @parm[in, out] dev_flow
2509  *   Pointer to the dev_flow.
2510  * @param[out] error
2511  *   pointer to error structure.
2512  *
2513  * @return
2514  *   0 on success otherwise -errno and errno is set.
2515  */
2516 static int
2517 flow_dv_jump_tbl_resource_register
2518                         (struct rte_eth_dev *dev __rte_unused,
2519                          struct mlx5_flow_tbl_resource *tbl,
2520                          struct mlx5_flow *dev_flow,
2521                          struct rte_flow_error *error)
2522 {
2523         struct mlx5_flow_tbl_data_entry *tbl_data =
2524                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
2525         int cnt;
2526
2527         MLX5_ASSERT(tbl);
2528         cnt = rte_atomic32_read(&tbl_data->jump.refcnt);
2529         if (!cnt) {
2530                 tbl_data->jump.action =
2531                         mlx5_glue->dr_create_flow_action_dest_flow_tbl
2532                         (tbl->obj);
2533                 if (!tbl_data->jump.action)
2534                         return rte_flow_error_set(error, ENOMEM,
2535                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2536                                         NULL, "cannot create jump action");
2537                 DRV_LOG(DEBUG, "new jump table resource %p: refcnt %d++",
2538                         (void *)&tbl_data->jump, cnt);
2539         } else {
2540                 MLX5_ASSERT(tbl_data->jump.action);
2541                 DRV_LOG(DEBUG, "existed jump table resource %p: refcnt %d++",
2542                         (void *)&tbl_data->jump, cnt);
2543         }
2544         rte_atomic32_inc(&tbl_data->jump.refcnt);
2545         dev_flow->handle->dvh.jump = &tbl_data->jump;
2546         return 0;
2547 }
2548
2549 /**
2550  * Find existing table port ID resource or create and register a new one.
2551  *
2552  * @param[in, out] dev
2553  *   Pointer to rte_eth_dev structure.
2554  * @param[in, out] resource
2555  *   Pointer to port ID action resource.
2556  * @parm[in, out] dev_flow
2557  *   Pointer to the dev_flow.
2558  * @param[out] error
2559  *   pointer to error structure.
2560  *
2561  * @return
2562  *   0 on success otherwise -errno and errno is set.
2563  */
2564 static int
2565 flow_dv_port_id_action_resource_register
2566                         (struct rte_eth_dev *dev,
2567                          struct mlx5_flow_dv_port_id_action_resource *resource,
2568                          struct mlx5_flow *dev_flow,
2569                          struct rte_flow_error *error)
2570 {
2571         struct mlx5_priv *priv = dev->data->dev_private;
2572         struct mlx5_ibv_shared *sh = priv->sh;
2573         struct mlx5_flow_dv_port_id_action_resource *cache_resource;
2574
2575         /* Lookup a matching resource from cache. */
2576         LIST_FOREACH(cache_resource, &sh->port_id_action_list, next) {
2577                 if (resource->port_id == cache_resource->port_id) {
2578                         DRV_LOG(DEBUG, "port id action resource resource %p: "
2579                                 "refcnt %d++",
2580                                 (void *)cache_resource,
2581                                 rte_atomic32_read(&cache_resource->refcnt));
2582                         rte_atomic32_inc(&cache_resource->refcnt);
2583                         dev_flow->handle->dvh.port_id_action = cache_resource;
2584                         return 0;
2585                 }
2586         }
2587         /* Register new port id action resource. */
2588         cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
2589         if (!cache_resource)
2590                 return rte_flow_error_set(error, ENOMEM,
2591                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2592                                           "cannot allocate resource memory");
2593         *cache_resource = *resource;
2594         /*
2595          * Depending on rdma_core version the glue routine calls
2596          * either mlx5dv_dr_action_create_dest_ib_port(domain, ibv_port)
2597          * or mlx5dv_dr_action_create_dest_vport(domain, vport_id).
2598          */
2599         cache_resource->action =
2600                 mlx5_glue->dr_create_flow_action_dest_port
2601                         (priv->sh->fdb_domain, resource->port_id);
2602         if (!cache_resource->action) {
2603                 rte_free(cache_resource);
2604                 return rte_flow_error_set(error, ENOMEM,
2605                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2606                                           NULL, "cannot create action");
2607         }
2608         rte_atomic32_init(&cache_resource->refcnt);
2609         rte_atomic32_inc(&cache_resource->refcnt);
2610         LIST_INSERT_HEAD(&sh->port_id_action_list, cache_resource, next);
2611         dev_flow->handle->dvh.port_id_action = cache_resource;
2612         DRV_LOG(DEBUG, "new port id action resource %p: refcnt %d++",
2613                 (void *)cache_resource,
2614                 rte_atomic32_read(&cache_resource->refcnt));
2615         return 0;
2616 }
2617
2618 /**
2619  * Find existing push vlan resource or create and register a new one.
2620  *
2621  * @param [in, out] dev
2622  *   Pointer to rte_eth_dev structure.
2623  * @param[in, out] resource
2624  *   Pointer to port ID action resource.
2625  * @parm[in, out] dev_flow
2626  *   Pointer to the dev_flow.
2627  * @param[out] error
2628  *   pointer to error structure.
2629  *
2630  * @return
2631  *   0 on success otherwise -errno and errno is set.
2632  */
2633 static int
2634 flow_dv_push_vlan_action_resource_register
2635                        (struct rte_eth_dev *dev,
2636                         struct mlx5_flow_dv_push_vlan_action_resource *resource,
2637                         struct mlx5_flow *dev_flow,
2638                         struct rte_flow_error *error)
2639 {
2640         struct mlx5_priv *priv = dev->data->dev_private;
2641         struct mlx5_ibv_shared *sh = priv->sh;
2642         struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
2643         struct mlx5dv_dr_domain *domain;
2644
2645         /* Lookup a matching resource from cache. */
2646         LIST_FOREACH(cache_resource, &sh->push_vlan_action_list, next) {
2647                 if (resource->vlan_tag == cache_resource->vlan_tag &&
2648                     resource->ft_type == cache_resource->ft_type) {
2649                         DRV_LOG(DEBUG, "push-VLAN action resource resource %p: "
2650                                 "refcnt %d++",
2651                                 (void *)cache_resource,
2652                                 rte_atomic32_read(&cache_resource->refcnt));
2653                         rte_atomic32_inc(&cache_resource->refcnt);
2654                         dev_flow->handle->dvh.push_vlan_res = cache_resource;
2655                         return 0;
2656                 }
2657         }
2658         /* Register new push_vlan action resource. */
2659         cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
2660         if (!cache_resource)
2661                 return rte_flow_error_set(error, ENOMEM,
2662                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2663                                           "cannot allocate resource memory");
2664         *cache_resource = *resource;
2665         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2666                 domain = sh->fdb_domain;
2667         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2668                 domain = sh->rx_domain;
2669         else
2670                 domain = sh->tx_domain;
2671         cache_resource->action =
2672                 mlx5_glue->dr_create_flow_action_push_vlan(domain,
2673                                                            resource->vlan_tag);
2674         if (!cache_resource->action) {
2675                 rte_free(cache_resource);
2676                 return rte_flow_error_set(error, ENOMEM,
2677                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2678                                           NULL, "cannot create action");
2679         }
2680         rte_atomic32_init(&cache_resource->refcnt);
2681         rte_atomic32_inc(&cache_resource->refcnt);
2682         LIST_INSERT_HEAD(&sh->push_vlan_action_list, cache_resource, next);
2683         dev_flow->handle->dvh.push_vlan_res = cache_resource;
2684         DRV_LOG(DEBUG, "new push vlan action resource %p: refcnt %d++",
2685                 (void *)cache_resource,
2686                 rte_atomic32_read(&cache_resource->refcnt));
2687         return 0;
2688 }
2689 /**
2690  * Get the size of specific rte_flow_item_type
2691  *
2692  * @param[in] item_type
2693  *   Tested rte_flow_item_type.
2694  *
2695  * @return
2696  *   sizeof struct item_type, 0 if void or irrelevant.
2697  */
2698 static size_t
2699 flow_dv_get_item_len(const enum rte_flow_item_type item_type)
2700 {
2701         size_t retval;
2702
2703         switch (item_type) {
2704         case RTE_FLOW_ITEM_TYPE_ETH:
2705                 retval = sizeof(struct rte_flow_item_eth);
2706                 break;
2707         case RTE_FLOW_ITEM_TYPE_VLAN:
2708                 retval = sizeof(struct rte_flow_item_vlan);
2709                 break;
2710         case RTE_FLOW_ITEM_TYPE_IPV4:
2711                 retval = sizeof(struct rte_flow_item_ipv4);
2712                 break;
2713         case RTE_FLOW_ITEM_TYPE_IPV6:
2714                 retval = sizeof(struct rte_flow_item_ipv6);
2715                 break;
2716         case RTE_FLOW_ITEM_TYPE_UDP:
2717                 retval = sizeof(struct rte_flow_item_udp);
2718                 break;
2719         case RTE_FLOW_ITEM_TYPE_TCP:
2720                 retval = sizeof(struct rte_flow_item_tcp);
2721                 break;
2722         case RTE_FLOW_ITEM_TYPE_VXLAN:
2723                 retval = sizeof(struct rte_flow_item_vxlan);
2724                 break;
2725         case RTE_FLOW_ITEM_TYPE_GRE:
2726                 retval = sizeof(struct rte_flow_item_gre);
2727                 break;
2728         case RTE_FLOW_ITEM_TYPE_NVGRE:
2729                 retval = sizeof(struct rte_flow_item_nvgre);
2730                 break;
2731         case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2732                 retval = sizeof(struct rte_flow_item_vxlan_gpe);
2733                 break;
2734         case RTE_FLOW_ITEM_TYPE_MPLS:
2735                 retval = sizeof(struct rte_flow_item_mpls);
2736                 break;
2737         case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
2738         default:
2739                 retval = 0;
2740                 break;
2741         }
2742         return retval;
2743 }
2744
2745 #define MLX5_ENCAP_IPV4_VERSION         0x40
2746 #define MLX5_ENCAP_IPV4_IHL_MIN         0x05
2747 #define MLX5_ENCAP_IPV4_TTL_DEF         0x40
2748 #define MLX5_ENCAP_IPV6_VTC_FLOW        0x60000000
2749 #define MLX5_ENCAP_IPV6_HOP_LIMIT       0xff
2750 #define MLX5_ENCAP_VXLAN_FLAGS          0x08000000
2751 #define MLX5_ENCAP_VXLAN_GPE_FLAGS      0x04
2752
2753 /**
2754  * Convert the encap action data from list of rte_flow_item to raw buffer
2755  *
2756  * @param[in] items
2757  *   Pointer to rte_flow_item objects list.
2758  * @param[out] buf
2759  *   Pointer to the output buffer.
2760  * @param[out] size
2761  *   Pointer to the output buffer size.
2762  * @param[out] error
2763  *   Pointer to the error structure.
2764  *
2765  * @return
2766  *   0 on success, a negative errno value otherwise and rte_errno is set.
2767  */
2768 static int
2769 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
2770                            size_t *size, struct rte_flow_error *error)
2771 {
2772         struct rte_ether_hdr *eth = NULL;
2773         struct rte_vlan_hdr *vlan = NULL;
2774         struct rte_ipv4_hdr *ipv4 = NULL;
2775         struct rte_ipv6_hdr *ipv6 = NULL;
2776         struct rte_udp_hdr *udp = NULL;
2777         struct rte_vxlan_hdr *vxlan = NULL;
2778         struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
2779         struct rte_gre_hdr *gre = NULL;
2780         size_t len;
2781         size_t temp_size = 0;
2782
2783         if (!items)
2784                 return rte_flow_error_set(error, EINVAL,
2785                                           RTE_FLOW_ERROR_TYPE_ACTION,
2786                                           NULL, "invalid empty data");
2787         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2788                 len = flow_dv_get_item_len(items->type);
2789                 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
2790                         return rte_flow_error_set(error, EINVAL,
2791                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2792                                                   (void *)items->type,
2793                                                   "items total size is too big"
2794                                                   " for encap action");
2795                 rte_memcpy((void *)&buf[temp_size], items->spec, len);
2796                 switch (items->type) {
2797                 case RTE_FLOW_ITEM_TYPE_ETH:
2798                         eth = (struct rte_ether_hdr *)&buf[temp_size];
2799                         break;
2800                 case RTE_FLOW_ITEM_TYPE_VLAN:
2801                         vlan = (struct rte_vlan_hdr *)&buf[temp_size];
2802                         if (!eth)
2803                                 return rte_flow_error_set(error, EINVAL,
2804                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2805                                                 (void *)items->type,
2806                                                 "eth header not found");
2807                         if (!eth->ether_type)
2808                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
2809                         break;
2810                 case RTE_FLOW_ITEM_TYPE_IPV4:
2811                         ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
2812                         if (!vlan && !eth)
2813                                 return rte_flow_error_set(error, EINVAL,
2814                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2815                                                 (void *)items->type,
2816                                                 "neither eth nor vlan"
2817                                                 " header found");
2818                         if (vlan && !vlan->eth_proto)
2819                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2820                         else if (eth && !eth->ether_type)
2821                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2822                         if (!ipv4->version_ihl)
2823                                 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
2824                                                     MLX5_ENCAP_IPV4_IHL_MIN;
2825                         if (!ipv4->time_to_live)
2826                                 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
2827                         break;
2828                 case RTE_FLOW_ITEM_TYPE_IPV6:
2829                         ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
2830                         if (!vlan && !eth)
2831                                 return rte_flow_error_set(error, EINVAL,
2832                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2833                                                 (void *)items->type,
2834                                                 "neither eth nor vlan"
2835                                                 " header found");
2836                         if (vlan && !vlan->eth_proto)
2837                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2838                         else if (eth && !eth->ether_type)
2839                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2840                         if (!ipv6->vtc_flow)
2841                                 ipv6->vtc_flow =
2842                                         RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
2843                         if (!ipv6->hop_limits)
2844                                 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
2845                         break;
2846                 case RTE_FLOW_ITEM_TYPE_UDP:
2847                         udp = (struct rte_udp_hdr *)&buf[temp_size];
2848                         if (!ipv4 && !ipv6)
2849                                 return rte_flow_error_set(error, EINVAL,
2850                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2851                                                 (void *)items->type,
2852                                                 "ip header not found");
2853                         if (ipv4 && !ipv4->next_proto_id)
2854                                 ipv4->next_proto_id = IPPROTO_UDP;
2855                         else if (ipv6 && !ipv6->proto)
2856                                 ipv6->proto = IPPROTO_UDP;
2857                         break;
2858                 case RTE_FLOW_ITEM_TYPE_VXLAN:
2859                         vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
2860                         if (!udp)
2861                                 return rte_flow_error_set(error, EINVAL,
2862                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2863                                                 (void *)items->type,
2864                                                 "udp header not found");
2865                         if (!udp->dst_port)
2866                                 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
2867                         if (!vxlan->vx_flags)
2868                                 vxlan->vx_flags =
2869                                         RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
2870                         break;
2871                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2872                         vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
2873                         if (!udp)
2874                                 return rte_flow_error_set(error, EINVAL,
2875                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2876                                                 (void *)items->type,
2877                                                 "udp header not found");
2878                         if (!vxlan_gpe->proto)
2879                                 return rte_flow_error_set(error, EINVAL,
2880                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2881                                                 (void *)items->type,
2882                                                 "next protocol not found");
2883                         if (!udp->dst_port)
2884                                 udp->dst_port =
2885                                         RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
2886                         if (!vxlan_gpe->vx_flags)
2887                                 vxlan_gpe->vx_flags =
2888                                                 MLX5_ENCAP_VXLAN_GPE_FLAGS;
2889                         break;
2890                 case RTE_FLOW_ITEM_TYPE_GRE:
2891                 case RTE_FLOW_ITEM_TYPE_NVGRE:
2892                         gre = (struct rte_gre_hdr *)&buf[temp_size];
2893                         if (!gre->proto)
2894                                 return rte_flow_error_set(error, EINVAL,
2895                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2896                                                 (void *)items->type,
2897                                                 "next protocol not found");
2898                         if (!ipv4 && !ipv6)
2899                                 return rte_flow_error_set(error, EINVAL,
2900                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2901                                                 (void *)items->type,
2902                                                 "ip header not found");
2903                         if (ipv4 && !ipv4->next_proto_id)
2904                                 ipv4->next_proto_id = IPPROTO_GRE;
2905                         else if (ipv6 && !ipv6->proto)
2906                                 ipv6->proto = IPPROTO_GRE;
2907                         break;
2908                 case RTE_FLOW_ITEM_TYPE_VOID:
2909                         break;
2910                 default:
2911                         return rte_flow_error_set(error, EINVAL,
2912                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2913                                                   (void *)items->type,
2914                                                   "unsupported item type");
2915                         break;
2916                 }
2917                 temp_size += len;
2918         }
2919         *size = temp_size;
2920         return 0;
2921 }
2922
2923 static int
2924 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
2925 {
2926         struct rte_ether_hdr *eth = NULL;
2927         struct rte_vlan_hdr *vlan = NULL;
2928         struct rte_ipv6_hdr *ipv6 = NULL;
2929         struct rte_udp_hdr *udp = NULL;
2930         char *next_hdr;
2931         uint16_t proto;
2932
2933         eth = (struct rte_ether_hdr *)data;
2934         next_hdr = (char *)(eth + 1);
2935         proto = RTE_BE16(eth->ether_type);
2936
2937         /* VLAN skipping */
2938         while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
2939                 vlan = (struct rte_vlan_hdr *)next_hdr;
2940                 proto = RTE_BE16(vlan->eth_proto);
2941                 next_hdr += sizeof(struct rte_vlan_hdr);
2942         }
2943
2944         /* HW calculates IPv4 csum. no need to proceed */
2945         if (proto == RTE_ETHER_TYPE_IPV4)
2946                 return 0;
2947
2948         /* non IPv4/IPv6 header. not supported */
2949         if (proto != RTE_ETHER_TYPE_IPV6) {
2950                 return rte_flow_error_set(error, ENOTSUP,
2951                                           RTE_FLOW_ERROR_TYPE_ACTION,
2952                                           NULL, "Cannot offload non IPv4/IPv6");
2953         }
2954
2955         ipv6 = (struct rte_ipv6_hdr *)next_hdr;
2956
2957         /* ignore non UDP */
2958         if (ipv6->proto != IPPROTO_UDP)
2959                 return 0;
2960
2961         udp = (struct rte_udp_hdr *)(ipv6 + 1);
2962         udp->dgram_cksum = 0;
2963
2964         return 0;
2965 }
2966
2967 /**
2968  * Convert L2 encap action to DV specification.
2969  *
2970  * @param[in] dev
2971  *   Pointer to rte_eth_dev structure.
2972  * @param[in] action
2973  *   Pointer to action structure.
2974  * @param[in, out] dev_flow
2975  *   Pointer to the mlx5_flow.
2976  * @param[in] transfer
2977  *   Mark if the flow is E-Switch flow.
2978  * @param[out] error
2979  *   Pointer to the error structure.
2980  *
2981  * @return
2982  *   0 on success, a negative errno value otherwise and rte_errno is set.
2983  */
2984 static int
2985 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
2986                                const struct rte_flow_action *action,
2987                                struct mlx5_flow *dev_flow,
2988                                uint8_t transfer,
2989                                struct rte_flow_error *error)
2990 {
2991         const struct rte_flow_item *encap_data;
2992         const struct rte_flow_action_raw_encap *raw_encap_data;
2993         struct mlx5_flow_dv_encap_decap_resource res = {
2994                 .reformat_type =
2995                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
2996                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
2997                                       MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
2998         };
2999
3000         if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
3001                 raw_encap_data =
3002                         (const struct rte_flow_action_raw_encap *)action->conf;
3003                 res.size = raw_encap_data->size;
3004                 memcpy(res.buf, raw_encap_data->data, res.size);
3005         } else {
3006                 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
3007                         encap_data =
3008                                 ((const struct rte_flow_action_vxlan_encap *)
3009                                                 action->conf)->definition;
3010                 else
3011                         encap_data =
3012                                 ((const struct rte_flow_action_nvgre_encap *)
3013                                                 action->conf)->definition;
3014                 if (flow_dv_convert_encap_data(encap_data, res.buf,
3015                                                &res.size, error))
3016                         return -rte_errno;
3017         }
3018         if (flow_dv_zero_encap_udp_csum(res.buf, error))
3019                 return -rte_errno;
3020         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3021                 return rte_flow_error_set(error, EINVAL,
3022                                           RTE_FLOW_ERROR_TYPE_ACTION,
3023                                           NULL, "can't create L2 encap action");
3024         return 0;
3025 }
3026
3027 /**
3028  * Convert L2 decap action to DV specification.
3029  *
3030  * @param[in] dev
3031  *   Pointer to rte_eth_dev structure.
3032  * @param[in, out] dev_flow
3033  *   Pointer to the mlx5_flow.
3034  * @param[in] transfer
3035  *   Mark if the flow is E-Switch flow.
3036  * @param[out] error
3037  *   Pointer to the error structure.
3038  *
3039  * @return
3040  *   0 on success, a negative errno value otherwise and rte_errno is set.
3041  */
3042 static int
3043 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
3044                                struct mlx5_flow *dev_flow,
3045                                uint8_t transfer,
3046                                struct rte_flow_error *error)
3047 {
3048         struct mlx5_flow_dv_encap_decap_resource res = {
3049                 .size = 0,
3050                 .reformat_type =
3051                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
3052                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3053                                       MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
3054         };
3055
3056         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3057                 return rte_flow_error_set(error, EINVAL,
3058                                           RTE_FLOW_ERROR_TYPE_ACTION,
3059                                           NULL, "can't create L2 decap action");
3060         return 0;
3061 }
3062
3063 /**
3064  * Convert raw decap/encap (L3 tunnel) action to DV specification.
3065  *
3066  * @param[in] dev
3067  *   Pointer to rte_eth_dev structure.
3068  * @param[in] action
3069  *   Pointer to action structure.
3070  * @param[in, out] dev_flow
3071  *   Pointer to the mlx5_flow.
3072  * @param[in] attr
3073  *   Pointer to the flow attributes.
3074  * @param[out] error
3075  *   Pointer to the error structure.
3076  *
3077  * @return
3078  *   0 on success, a negative errno value otherwise and rte_errno is set.
3079  */
3080 static int
3081 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
3082                                 const struct rte_flow_action *action,
3083                                 struct mlx5_flow *dev_flow,
3084                                 const struct rte_flow_attr *attr,
3085                                 struct rte_flow_error *error)
3086 {
3087         const struct rte_flow_action_raw_encap *encap_data;
3088         struct mlx5_flow_dv_encap_decap_resource res;
3089
3090         encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
3091         res.size = encap_data->size;
3092         memcpy(res.buf, encap_data->data, res.size);
3093         res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
3094                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
3095                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
3096         if (attr->transfer)
3097                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3098         else
3099                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3100                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3101         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3102                 return rte_flow_error_set(error, EINVAL,
3103                                           RTE_FLOW_ERROR_TYPE_ACTION,
3104                                           NULL, "can't create encap action");
3105         return 0;
3106 }
3107
3108 /**
3109  * Create action push VLAN.
3110  *
3111  * @param[in] dev
3112  *   Pointer to rte_eth_dev structure.
3113  * @param[in] attr
3114  *   Pointer to the flow attributes.
3115  * @param[in] vlan
3116  *   Pointer to the vlan to push to the Ethernet header.
3117  * @param[in, out] dev_flow
3118  *   Pointer to the mlx5_flow.
3119  * @param[out] error
3120  *   Pointer to the error structure.
3121  *
3122  * @return
3123  *   0 on success, a negative errno value otherwise and rte_errno is set.
3124  */
3125 static int
3126 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
3127                                 const struct rte_flow_attr *attr,
3128                                 const struct rte_vlan_hdr *vlan,
3129                                 struct mlx5_flow *dev_flow,
3130                                 struct rte_flow_error *error)
3131 {
3132         struct mlx5_flow_dv_push_vlan_action_resource res;
3133
3134         res.vlan_tag =
3135                 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
3136                                  vlan->vlan_tci);
3137         if (attr->transfer)
3138                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3139         else
3140                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3141                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3142         return flow_dv_push_vlan_action_resource_register
3143                                             (dev, &res, dev_flow, error);
3144 }
3145
3146 /**
3147  * Validate the modify-header actions.
3148  *
3149  * @param[in] action_flags
3150  *   Holds the actions detected until now.
3151  * @param[in] action
3152  *   Pointer to the modify action.
3153  * @param[out] error
3154  *   Pointer to error structure.
3155  *
3156  * @return
3157  *   0 on success, a negative errno value otherwise and rte_errno is set.
3158  */
3159 static int
3160 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
3161                                    const struct rte_flow_action *action,
3162                                    struct rte_flow_error *error)
3163 {
3164         if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
3165                 return rte_flow_error_set(error, EINVAL,
3166                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3167                                           NULL, "action configuration not set");
3168         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3169                 return rte_flow_error_set(error, EINVAL,
3170                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3171                                           "can't have encap action before"
3172                                           " modify action");
3173         return 0;
3174 }
3175
3176 /**
3177  * Validate the modify-header MAC address actions.
3178  *
3179  * @param[in] action_flags
3180  *   Holds the actions detected until now.
3181  * @param[in] action
3182  *   Pointer to the modify action.
3183  * @param[in] item_flags
3184  *   Holds the items detected.
3185  * @param[out] error
3186  *   Pointer to error structure.
3187  *
3188  * @return
3189  *   0 on success, a negative errno value otherwise and rte_errno is set.
3190  */
3191 static int
3192 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
3193                                    const struct rte_flow_action *action,
3194                                    const uint64_t item_flags,
3195                                    struct rte_flow_error *error)
3196 {
3197         int ret = 0;
3198
3199         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3200         if (!ret) {
3201                 if (!(item_flags & MLX5_FLOW_LAYER_L2))
3202                         return rte_flow_error_set(error, EINVAL,
3203                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3204                                                   NULL,
3205                                                   "no L2 item in pattern");
3206         }
3207         return ret;
3208 }
3209
3210 /**
3211  * Validate the modify-header IPv4 address actions.
3212  *
3213  * @param[in] action_flags
3214  *   Holds the actions detected until now.
3215  * @param[in] action
3216  *   Pointer to the modify action.
3217  * @param[in] item_flags
3218  *   Holds the items detected.
3219  * @param[out] error
3220  *   Pointer to error structure.
3221  *
3222  * @return
3223  *   0 on success, a negative errno value otherwise and rte_errno is set.
3224  */
3225 static int
3226 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
3227                                     const struct rte_flow_action *action,
3228                                     const uint64_t item_flags,
3229                                     struct rte_flow_error *error)
3230 {
3231         int ret = 0;
3232         uint64_t layer;
3233
3234         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3235         if (!ret) {
3236                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3237                                  MLX5_FLOW_LAYER_INNER_L3_IPV4 :
3238                                  MLX5_FLOW_LAYER_OUTER_L3_IPV4;
3239                 if (!(item_flags & layer))
3240                         return rte_flow_error_set(error, EINVAL,
3241                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3242                                                   NULL,
3243                                                   "no ipv4 item in pattern");
3244         }
3245         return ret;
3246 }
3247
3248 /**
3249  * Validate the modify-header IPv6 address actions.
3250  *
3251  * @param[in] action_flags
3252  *   Holds the actions detected until now.
3253  * @param[in] action
3254  *   Pointer to the modify action.
3255  * @param[in] item_flags
3256  *   Holds the items detected.
3257  * @param[out] error
3258  *   Pointer to error structure.
3259  *
3260  * @return
3261  *   0 on success, a negative errno value otherwise and rte_errno is set.
3262  */
3263 static int
3264 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
3265                                     const struct rte_flow_action *action,
3266                                     const uint64_t item_flags,
3267                                     struct rte_flow_error *error)
3268 {
3269         int ret = 0;
3270         uint64_t layer;
3271
3272         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3273         if (!ret) {
3274                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3275                                  MLX5_FLOW_LAYER_INNER_L3_IPV6 :
3276                                  MLX5_FLOW_LAYER_OUTER_L3_IPV6;
3277                 if (!(item_flags & layer))
3278                         return rte_flow_error_set(error, EINVAL,
3279                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3280                                                   NULL,
3281                                                   "no ipv6 item in pattern");
3282         }
3283         return ret;
3284 }
3285
3286 /**
3287  * Validate the modify-header TP actions.
3288  *
3289  * @param[in] action_flags
3290  *   Holds the actions detected until now.
3291  * @param[in] action
3292  *   Pointer to the modify action.
3293  * @param[in] item_flags
3294  *   Holds the items detected.
3295  * @param[out] error
3296  *   Pointer to error structure.
3297  *
3298  * @return
3299  *   0 on success, a negative errno value otherwise and rte_errno is set.
3300  */
3301 static int
3302 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
3303                                   const struct rte_flow_action *action,
3304                                   const uint64_t item_flags,
3305                                   struct rte_flow_error *error)
3306 {
3307         int ret = 0;
3308         uint64_t layer;
3309
3310         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3311         if (!ret) {
3312                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3313                                  MLX5_FLOW_LAYER_INNER_L4 :
3314                                  MLX5_FLOW_LAYER_OUTER_L4;
3315                 if (!(item_flags & layer))
3316                         return rte_flow_error_set(error, EINVAL,
3317                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3318                                                   NULL, "no transport layer "
3319                                                   "in pattern");
3320         }
3321         return ret;
3322 }
3323
3324 /**
3325  * Validate the modify-header actions of increment/decrement
3326  * TCP Sequence-number.
3327  *
3328  * @param[in] action_flags
3329  *   Holds the actions detected until now.
3330  * @param[in] action
3331  *   Pointer to the modify action.
3332  * @param[in] item_flags
3333  *   Holds the items detected.
3334  * @param[out] error
3335  *   Pointer to error structure.
3336  *
3337  * @return
3338  *   0 on success, a negative errno value otherwise and rte_errno is set.
3339  */
3340 static int
3341 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
3342                                        const struct rte_flow_action *action,
3343                                        const uint64_t item_flags,
3344                                        struct rte_flow_error *error)
3345 {
3346         int ret = 0;
3347         uint64_t layer;
3348
3349         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3350         if (!ret) {
3351                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3352                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
3353                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
3354                 if (!(item_flags & layer))
3355                         return rte_flow_error_set(error, EINVAL,
3356                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3357                                                   NULL, "no TCP item in"
3358                                                   " pattern");
3359                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
3360                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
3361                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
3362                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
3363                         return rte_flow_error_set(error, EINVAL,
3364                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3365                                                   NULL,
3366                                                   "cannot decrease and increase"
3367                                                   " TCP sequence number"
3368                                                   " at the same time");
3369         }
3370         return ret;
3371 }
3372
3373 /**
3374  * Validate the modify-header actions of increment/decrement
3375  * TCP Acknowledgment number.
3376  *
3377  * @param[in] action_flags
3378  *   Holds the actions detected until now.
3379  * @param[in] action
3380  *   Pointer to the modify action.
3381  * @param[in] item_flags
3382  *   Holds the items detected.
3383  * @param[out] error
3384  *   Pointer to error structure.
3385  *
3386  * @return
3387  *   0 on success, a negative errno value otherwise and rte_errno is set.
3388  */
3389 static int
3390 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
3391                                        const struct rte_flow_action *action,
3392                                        const uint64_t item_flags,
3393                                        struct rte_flow_error *error)
3394 {
3395         int ret = 0;
3396         uint64_t layer;
3397
3398         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3399         if (!ret) {
3400                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3401                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
3402                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
3403                 if (!(item_flags & layer))
3404                         return rte_flow_error_set(error, EINVAL,
3405                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3406                                                   NULL, "no TCP item in"
3407                                                   " pattern");
3408                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
3409                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
3410                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
3411                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
3412                         return rte_flow_error_set(error, EINVAL,
3413                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3414                                                   NULL,
3415                                                   "cannot decrease and increase"
3416                                                   " TCP acknowledgment number"
3417                                                   " at the same time");
3418         }
3419         return ret;
3420 }
3421
3422 /**
3423  * Validate the modify-header TTL actions.
3424  *
3425  * @param[in] action_flags
3426  *   Holds the actions detected until now.
3427  * @param[in] action
3428  *   Pointer to the modify action.
3429  * @param[in] item_flags
3430  *   Holds the items detected.
3431  * @param[out] error
3432  *   Pointer to error structure.
3433  *
3434  * @return
3435  *   0 on success, a negative errno value otherwise and rte_errno is set.
3436  */
3437 static int
3438 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
3439                                    const struct rte_flow_action *action,
3440                                    const uint64_t item_flags,
3441                                    struct rte_flow_error *error)
3442 {
3443         int ret = 0;
3444         uint64_t layer;
3445
3446         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3447         if (!ret) {
3448                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3449                                  MLX5_FLOW_LAYER_INNER_L3 :
3450                                  MLX5_FLOW_LAYER_OUTER_L3;
3451                 if (!(item_flags & layer))
3452                         return rte_flow_error_set(error, EINVAL,
3453                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3454                                                   NULL,
3455                                                   "no IP protocol in pattern");
3456         }
3457         return ret;
3458 }
3459
3460 /**
3461  * Validate jump action.
3462  *
3463  * @param[in] action
3464  *   Pointer to the jump action.
3465  * @param[in] action_flags
3466  *   Holds the actions detected until now.
3467  * @param[in] attributes
3468  *   Pointer to flow attributes
3469  * @param[in] external
3470  *   Action belongs to flow rule created by request external to PMD.
3471  * @param[out] error
3472  *   Pointer to error structure.
3473  *
3474  * @return
3475  *   0 on success, a negative errno value otherwise and rte_errno is set.
3476  */
3477 static int
3478 flow_dv_validate_action_jump(const struct rte_flow_action *action,
3479                              uint64_t action_flags,
3480                              const struct rte_flow_attr *attributes,
3481                              bool external, struct rte_flow_error *error)
3482 {
3483         uint32_t target_group, table;
3484         int ret = 0;
3485
3486         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3487                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3488                 return rte_flow_error_set(error, EINVAL,
3489                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3490                                           "can't have 2 fate actions in"
3491                                           " same flow");
3492         if (action_flags & MLX5_FLOW_ACTION_METER)
3493                 return rte_flow_error_set(error, ENOTSUP,
3494                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3495                                           "jump with meter not support");
3496         if (!action->conf)
3497                 return rte_flow_error_set(error, EINVAL,
3498                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3499                                           NULL, "action configuration not set");
3500         target_group =
3501                 ((const struct rte_flow_action_jump *)action->conf)->group;
3502         ret = mlx5_flow_group_to_table(attributes, external, target_group,
3503                                        true, &table, error);
3504         if (ret)
3505                 return ret;
3506         if (attributes->group == target_group)
3507                 return rte_flow_error_set(error, EINVAL,
3508                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3509                                           "target group must be other than"
3510                                           " the current flow group");
3511         return 0;
3512 }
3513
3514 /*
3515  * Validate the port_id action.
3516  *
3517  * @param[in] dev
3518  *   Pointer to rte_eth_dev structure.
3519  * @param[in] action_flags
3520  *   Bit-fields that holds the actions detected until now.
3521  * @param[in] action
3522  *   Port_id RTE action structure.
3523  * @param[in] attr
3524  *   Attributes of flow that includes this action.
3525  * @param[out] error
3526  *   Pointer to error structure.
3527  *
3528  * @return
3529  *   0 on success, a negative errno value otherwise and rte_errno is set.
3530  */
3531 static int
3532 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
3533                                 uint64_t action_flags,
3534                                 const struct rte_flow_action *action,
3535                                 const struct rte_flow_attr *attr,
3536                                 struct rte_flow_error *error)
3537 {
3538         const struct rte_flow_action_port_id *port_id;
3539         struct mlx5_priv *act_priv;
3540         struct mlx5_priv *dev_priv;
3541         uint16_t port;
3542
3543         if (!attr->transfer)
3544                 return rte_flow_error_set(error, ENOTSUP,
3545                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3546                                           NULL,
3547                                           "port id action is valid in transfer"
3548                                           " mode only");
3549         if (!action || !action->conf)
3550                 return rte_flow_error_set(error, ENOTSUP,
3551                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3552                                           NULL,
3553                                           "port id action parameters must be"
3554                                           " specified");
3555         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3556                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3557                 return rte_flow_error_set(error, EINVAL,
3558                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3559                                           "can have only one fate actions in"
3560                                           " a flow");
3561         dev_priv = mlx5_dev_to_eswitch_info(dev);
3562         if (!dev_priv)
3563                 return rte_flow_error_set(error, rte_errno,
3564                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3565                                           NULL,
3566                                           "failed to obtain E-Switch info");
3567         port_id = action->conf;
3568         port = port_id->original ? dev->data->port_id : port_id->id;
3569         act_priv = mlx5_port_to_eswitch_info(port, false);
3570         if (!act_priv)
3571                 return rte_flow_error_set
3572                                 (error, rte_errno,
3573                                  RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
3574                                  "failed to obtain E-Switch port id for port");
3575         if (act_priv->domain_id != dev_priv->domain_id)
3576                 return rte_flow_error_set
3577                                 (error, EINVAL,
3578                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3579                                  "port does not belong to"
3580                                  " E-Switch being configured");
3581         return 0;
3582 }
3583
3584 /**
3585  * Get the maximum number of modify header actions.
3586  *
3587  * @param dev
3588  *   Pointer to rte_eth_dev structure.
3589  * @param flags
3590  *   Flags bits to check if root level.
3591  *
3592  * @return
3593  *   Max number of modify header actions device can support.
3594  */
3595 static unsigned int
3596 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev, uint64_t flags)
3597 {
3598         /*
3599          * There's no way to directly query the max cap. Although it has to be
3600          * acquried by iterative trial, it is a safe assumption that more
3601          * actions are supported by FW if extensive metadata register is
3602          * supported. (Only in the root table)
3603          */
3604         if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
3605                 return MLX5_MAX_MODIFY_NUM;
3606         else
3607                 return mlx5_flow_ext_mreg_supported(dev) ?
3608                                         MLX5_ROOT_TBL_MODIFY_NUM :
3609                                         MLX5_ROOT_TBL_MODIFY_NUM_NO_MREG;
3610 }
3611
3612 /**
3613  * Validate the meter action.
3614  *
3615  * @param[in] dev
3616  *   Pointer to rte_eth_dev structure.
3617  * @param[in] action_flags
3618  *   Bit-fields that holds the actions detected until now.
3619  * @param[in] action
3620  *   Pointer to the meter action.
3621  * @param[in] attr
3622  *   Attributes of flow that includes this action.
3623  * @param[out] error
3624  *   Pointer to error structure.
3625  *
3626  * @return
3627  *   0 on success, a negative errno value otherwise and rte_ernno is set.
3628  */
3629 static int
3630 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
3631                                 uint64_t action_flags,
3632                                 const struct rte_flow_action *action,
3633                                 const struct rte_flow_attr *attr,
3634                                 struct rte_flow_error *error)
3635 {
3636         struct mlx5_priv *priv = dev->data->dev_private;
3637         const struct rte_flow_action_meter *am = action->conf;
3638         struct mlx5_flow_meter *fm;
3639
3640         if (!am)
3641                 return rte_flow_error_set(error, EINVAL,
3642                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3643                                           "meter action conf is NULL");
3644
3645         if (action_flags & MLX5_FLOW_ACTION_METER)
3646                 return rte_flow_error_set(error, ENOTSUP,
3647                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3648                                           "meter chaining not support");
3649         if (action_flags & MLX5_FLOW_ACTION_JUMP)
3650                 return rte_flow_error_set(error, ENOTSUP,
3651                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3652                                           "meter with jump not support");
3653         if (!priv->mtr_en)
3654                 return rte_flow_error_set(error, ENOTSUP,
3655                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3656                                           NULL,
3657                                           "meter action not supported");
3658         fm = mlx5_flow_meter_find(priv, am->mtr_id);
3659         if (!fm)
3660                 return rte_flow_error_set(error, EINVAL,
3661                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3662                                           "Meter not found");
3663         if (fm->ref_cnt && (!(fm->attr.transfer == attr->transfer ||
3664               (!fm->attr.ingress && !attr->ingress && attr->egress) ||
3665               (!fm->attr.egress && !attr->egress && attr->ingress))))
3666                 return rte_flow_error_set(error, EINVAL,
3667                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3668                                           "Flow attributes are either invalid "
3669                                           "or have a conflict with current "
3670                                           "meter attributes");
3671         return 0;
3672 }
3673
3674 /**
3675  * Validate the modify-header IPv4 DSCP actions.
3676  *
3677  * @param[in] action_flags
3678  *   Holds the actions detected until now.
3679  * @param[in] action
3680  *   Pointer to the modify action.
3681  * @param[in] item_flags
3682  *   Holds the items detected.
3683  * @param[out] error
3684  *   Pointer to error structure.
3685  *
3686  * @return
3687  *   0 on success, a negative errno value otherwise and rte_errno is set.
3688  */
3689 static int
3690 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
3691                                          const struct rte_flow_action *action,
3692                                          const uint64_t item_flags,
3693                                          struct rte_flow_error *error)
3694 {
3695         int ret = 0;
3696
3697         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3698         if (!ret) {
3699                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
3700                         return rte_flow_error_set(error, EINVAL,
3701                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3702                                                   NULL,
3703                                                   "no ipv4 item in pattern");
3704         }
3705         return ret;
3706 }
3707
3708 /**
3709  * Validate the modify-header IPv6 DSCP actions.
3710  *
3711  * @param[in] action_flags
3712  *   Holds the actions detected until now.
3713  * @param[in] action
3714  *   Pointer to the modify action.
3715  * @param[in] item_flags
3716  *   Holds the items detected.
3717  * @param[out] error
3718  *   Pointer to error structure.
3719  *
3720  * @return
3721  *   0 on success, a negative errno value otherwise and rte_errno is set.
3722  */
3723 static int
3724 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
3725                                          const struct rte_flow_action *action,
3726                                          const uint64_t item_flags,
3727                                          struct rte_flow_error *error)
3728 {
3729         int ret = 0;
3730
3731         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3732         if (!ret) {
3733                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
3734                         return rte_flow_error_set(error, EINVAL,
3735                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3736                                                   NULL,
3737                                                   "no ipv6 item in pattern");
3738         }
3739         return ret;
3740 }
3741
3742 /**
3743  * Find existing modify-header resource or create and register a new one.
3744  *
3745  * @param dev[in, out]
3746  *   Pointer to rte_eth_dev structure.
3747  * @param[in, out] resource
3748  *   Pointer to modify-header resource.
3749  * @parm[in, out] dev_flow
3750  *   Pointer to the dev_flow.
3751  * @param[out] error
3752  *   pointer to error structure.
3753  *
3754  * @return
3755  *   0 on success otherwise -errno and errno is set.
3756  */
3757 static int
3758 flow_dv_modify_hdr_resource_register
3759                         (struct rte_eth_dev *dev,
3760                          struct mlx5_flow_dv_modify_hdr_resource *resource,
3761                          struct mlx5_flow *dev_flow,
3762                          struct rte_flow_error *error)
3763 {
3764         struct mlx5_priv *priv = dev->data->dev_private;
3765         struct mlx5_ibv_shared *sh = priv->sh;
3766         struct mlx5_flow_dv_modify_hdr_resource *cache_resource;
3767         struct mlx5dv_dr_domain *ns;
3768         uint32_t actions_len;
3769
3770         resource->flags = dev_flow->dv.group ? 0 :
3771                           MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
3772         if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
3773                                     resource->flags))
3774                 return rte_flow_error_set(error, EOVERFLOW,
3775                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3776                                           "too many modify header items");
3777         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3778                 ns = sh->fdb_domain;
3779         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
3780                 ns = sh->tx_domain;
3781         else
3782                 ns = sh->rx_domain;
3783         /* Lookup a matching resource from cache. */
3784         actions_len = resource->actions_num * sizeof(resource->actions[0]);
3785         LIST_FOREACH(cache_resource, &sh->modify_cmds, next) {
3786                 if (resource->ft_type == cache_resource->ft_type &&
3787                     resource->actions_num == cache_resource->actions_num &&
3788                     resource->flags == cache_resource->flags &&
3789                     !memcmp((const void *)resource->actions,
3790                             (const void *)cache_resource->actions,
3791                             actions_len)) {
3792                         DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d++",
3793                                 (void *)cache_resource,
3794                                 rte_atomic32_read(&cache_resource->refcnt));
3795                         rte_atomic32_inc(&cache_resource->refcnt);
3796                         dev_flow->handle->dvh.modify_hdr = cache_resource;
3797                         return 0;
3798                 }
3799         }
3800         /* Register new modify-header resource. */
3801         cache_resource = rte_calloc(__func__, 1,
3802                                     sizeof(*cache_resource) + actions_len, 0);
3803         if (!cache_resource)
3804                 return rte_flow_error_set(error, ENOMEM,
3805                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3806                                           "cannot allocate resource memory");
3807         *cache_resource = *resource;
3808         rte_memcpy(cache_resource->actions, resource->actions, actions_len);
3809         cache_resource->verbs_action =
3810                 mlx5_glue->dv_create_flow_action_modify_header
3811                                         (sh->ctx, cache_resource->ft_type, ns,
3812                                          cache_resource->flags, actions_len,
3813                                          (uint64_t *)cache_resource->actions);
3814         if (!cache_resource->verbs_action) {
3815                 rte_free(cache_resource);
3816                 return rte_flow_error_set(error, ENOMEM,
3817                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3818                                           NULL, "cannot create action");
3819         }
3820         rte_atomic32_init(&cache_resource->refcnt);
3821         rte_atomic32_inc(&cache_resource->refcnt);
3822         LIST_INSERT_HEAD(&sh->modify_cmds, cache_resource, next);
3823         dev_flow->handle->dvh.modify_hdr = cache_resource;
3824         DRV_LOG(DEBUG, "new modify-header resource %p: refcnt %d++",
3825                 (void *)cache_resource,
3826                 rte_atomic32_read(&cache_resource->refcnt));
3827         return 0;
3828 }
3829
3830 /**
3831  * Get or create a flow counter.
3832  *
3833  * @param[in] dev
3834  *   Pointer to the Ethernet device structure.
3835  * @param[in] shared
3836  *   Indicate if this counter is shared with other flows.
3837  * @param[in] id
3838  *   Counter identifier.
3839  *
3840  * @return
3841  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
3842  */
3843 static uint32_t
3844 flow_dv_counter_alloc_fallback(struct rte_eth_dev *dev, uint32_t shared,
3845                                uint32_t id)
3846 {
3847         struct mlx5_priv *priv = dev->data->dev_private;
3848         struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, 0, 0);
3849         struct mlx5_flow_counter_pool *pool;
3850         struct mlx5_flow_counter_ext *cnt_ext;
3851         struct mlx5_devx_obj *dcs = NULL;
3852         uint32_t offset;
3853
3854         if (!priv->config.devx) {
3855                 rte_errno = ENOTSUP;
3856                 return 0;
3857         }
3858         dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
3859         if (!dcs)
3860                 return 0;
3861         pool = flow_dv_find_pool_by_id(cont, true, dcs->id);
3862         if (!pool) {
3863                 cont = flow_dv_pool_create(dev, dcs, 0);
3864                 if (!cont) {
3865                         mlx5_devx_cmd_destroy(dcs);
3866                         rte_errno = ENOMEM;
3867                         return 0;
3868                 }
3869                 pool = TAILQ_FIRST(&cont->pool_list);
3870         }
3871         offset = dcs->id % MLX5_COUNTERS_PER_POOL;
3872         cnt_ext = MLX5_GET_POOL_CNT_EXT(pool, offset);
3873         cnt_ext->shared = shared;
3874         cnt_ext->ref_cnt = 1;
3875         cnt_ext->id = id;
3876         cnt_ext->dcs = dcs;
3877         pool->counters_raw[offset].action =
3878               mlx5_glue->dv_create_flow_action_counter(dcs->obj, 0);
3879         if (!pool->counters_raw[offset].action) {
3880                 claim_zero(mlx5_devx_cmd_destroy(dcs));
3881                 rte_errno = errno;
3882                 return 0;
3883         }
3884         return MLX5_MAKE_CNT_IDX(pool->index, offset);
3885 }
3886
3887 /**
3888  * Release a flow counter.
3889  *
3890  * @param[in] dev
3891  *   Pointer to the Ethernet device structure.
3892  * @param[in] counter
3893  *   Extend counter handler.
3894  */
3895 static void
3896 flow_dv_counter_release_fallback(struct rte_eth_dev *dev __rte_unused,
3897                                  struct mlx5_flow_counter_ext *counter)
3898 {
3899         if (!counter)
3900                 return;
3901         claim_zero(mlx5_devx_cmd_destroy(counter->dcs));
3902         counter->dcs = NULL;
3903 }
3904
3905 /**
3906  * Query a devx flow counter.
3907  *
3908  * @param[in] dev
3909  *   Pointer to the Ethernet device structure.
3910  * @param[in] cnt
3911  *   Pointer to the flow counter.
3912  * @param[out] pkts
3913  *   The statistics value of packets.
3914  * @param[out] bytes
3915  *   The statistics value of bytes.
3916  *
3917  * @return
3918  *   0 on success, otherwise a negative errno value and rte_errno is set.
3919  */
3920 static inline int
3921 _flow_dv_query_count_fallback(struct rte_eth_dev *dev __rte_unused,
3922                      struct mlx5_flow_counter_ext *cnt, uint64_t *pkts,
3923                      uint64_t *bytes)
3924 {
3925         return mlx5_devx_cmd_flow_counter_query(cnt->dcs, 0, 0, pkts, bytes,
3926                                                 0, NULL, NULL, 0);
3927 }
3928
3929 /**
3930  * Get DV flow counter by index.
3931  *
3932  * @param[in] dev
3933  *   Pointer to the Ethernet device structure.
3934  * @param[in] idx
3935  *   mlx5 flow counter index in the container.
3936  * @param[out] ppool
3937  *   mlx5 flow counter pool in the container,
3938  *
3939  * @return
3940  *   Pointer to the counter, NULL otherwise.
3941  */
3942 static struct mlx5_flow_counter *
3943 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
3944                            uint32_t idx,
3945                            struct mlx5_flow_counter_pool **ppool)
3946 {
3947         struct mlx5_priv *priv = dev->data->dev_private;
3948         struct mlx5_pools_container *cont;
3949         struct mlx5_flow_counter_pool *pool;
3950         uint32_t batch = 0;
3951
3952         idx--;
3953         if (idx >= MLX5_CNT_BATCH_OFFSET) {
3954                 idx -= MLX5_CNT_BATCH_OFFSET;
3955                 batch = 1;
3956         }
3957         cont = MLX5_CNT_CONTAINER(priv->sh, batch, 0);
3958         MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cont->n);
3959         pool = cont->pools[idx / MLX5_COUNTERS_PER_POOL];
3960         MLX5_ASSERT(pool);
3961         if (ppool)
3962                 *ppool = pool;
3963         return &pool->counters_raw[idx % MLX5_COUNTERS_PER_POOL];
3964 }
3965
3966 /**
3967  * Get a pool by devx counter ID.
3968  *
3969  * @param[in] cont
3970  *   Pointer to the counter container.
3971  * @param[in] fallback
3972  *   Fallback mode.
3973  * @param[in] id
3974  *   The counter devx ID.
3975  *
3976  * @return
3977  *   The counter pool pointer if exists, NULL otherwise,
3978  */
3979 static struct mlx5_flow_counter_pool *
3980 flow_dv_find_pool_by_id(struct mlx5_pools_container *cont, bool fallback,
3981                         int id)
3982 {
3983         uint32_t i;
3984         uint32_t n_valid = rte_atomic16_read(&cont->n_valid);
3985
3986         for (i = 0; i < n_valid; i++) {
3987                 struct mlx5_flow_counter_pool *pool = cont->pools[i];
3988                 int base = ((fallback ? pool->dcs_id : pool->min_dcs->id) /
3989                            MLX5_COUNTERS_PER_POOL) * MLX5_COUNTERS_PER_POOL;
3990
3991                 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL) {
3992                         /*
3993                          * Move the pool to the head, as counter allocate
3994                          * always gets the first pool in the container.
3995                          */
3996                         if (pool != TAILQ_FIRST(&cont->pool_list)) {
3997                                 TAILQ_REMOVE(&cont->pool_list, pool, next);
3998                                 TAILQ_INSERT_HEAD(&cont->pool_list, pool, next);
3999                         }
4000                         return pool;
4001                 }
4002         }
4003         return NULL;
4004 }
4005
4006 /**
4007  * Allocate a new memory for the counter values wrapped by all the needed
4008  * management.
4009  *
4010  * @param[in] dev
4011  *   Pointer to the Ethernet device structure.
4012  * @param[in] raws_n
4013  *   The raw memory areas - each one for MLX5_COUNTERS_PER_POOL counters.
4014  *
4015  * @return
4016  *   The new memory management pointer on success, otherwise NULL and rte_errno
4017  *   is set.
4018  */
4019 static struct mlx5_counter_stats_mem_mng *
4020 flow_dv_create_counter_stat_mem_mng(struct rte_eth_dev *dev, int raws_n)
4021 {
4022         struct mlx5_ibv_shared *sh = ((struct mlx5_priv *)
4023                                         (dev->data->dev_private))->sh;
4024         struct mlx5_devx_mkey_attr mkey_attr;
4025         struct mlx5_counter_stats_mem_mng *mem_mng;
4026         volatile struct flow_counter_stats *raw_data;
4027         int size = (sizeof(struct flow_counter_stats) *
4028                         MLX5_COUNTERS_PER_POOL +
4029                         sizeof(struct mlx5_counter_stats_raw)) * raws_n +
4030                         sizeof(struct mlx5_counter_stats_mem_mng);
4031         uint8_t *mem = rte_calloc(__func__, 1, size, sysconf(_SC_PAGESIZE));
4032         int i;
4033
4034         if (!mem) {
4035                 rte_errno = ENOMEM;
4036                 return NULL;
4037         }
4038         mem_mng = (struct mlx5_counter_stats_mem_mng *)(mem + size) - 1;
4039         size = sizeof(*raw_data) * MLX5_COUNTERS_PER_POOL * raws_n;
4040         mem_mng->umem = mlx5_glue->devx_umem_reg(sh->ctx, mem, size,
4041                                                  IBV_ACCESS_LOCAL_WRITE);
4042         if (!mem_mng->umem) {
4043                 rte_errno = errno;
4044                 rte_free(mem);
4045                 return NULL;
4046         }
4047         mkey_attr.addr = (uintptr_t)mem;
4048         mkey_attr.size = size;
4049         mkey_attr.umem_id = mem_mng->umem->umem_id;
4050         mkey_attr.pd = sh->pdn;
4051         mkey_attr.log_entity_size = 0;
4052         mkey_attr.pg_access = 0;
4053         mkey_attr.klm_array = NULL;
4054         mkey_attr.klm_num = 0;
4055         mkey_attr.relaxed_ordering = 1;
4056         mem_mng->dm = mlx5_devx_cmd_mkey_create(sh->ctx, &mkey_attr);
4057         if (!mem_mng->dm) {
4058                 mlx5_glue->devx_umem_dereg(mem_mng->umem);
4059                 rte_errno = errno;
4060                 rte_free(mem);
4061                 return NULL;
4062         }
4063         mem_mng->raws = (struct mlx5_counter_stats_raw *)(mem + size);
4064         raw_data = (volatile struct flow_counter_stats *)mem;
4065         for (i = 0; i < raws_n; ++i) {
4066                 mem_mng->raws[i].mem_mng = mem_mng;
4067                 mem_mng->raws[i].data = raw_data + i * MLX5_COUNTERS_PER_POOL;
4068         }
4069         LIST_INSERT_HEAD(&sh->cmng.mem_mngs, mem_mng, next);
4070         return mem_mng;
4071 }
4072
4073 /**
4074  * Resize a counter container.
4075  *
4076  * @param[in] dev
4077  *   Pointer to the Ethernet device structure.
4078  * @param[in] batch
4079  *   Whether the pool is for counter that was allocated by batch command.
4080  *
4081  * @return
4082  *   The new container pointer on success, otherwise NULL and rte_errno is set.
4083  */
4084 static struct mlx5_pools_container *
4085 flow_dv_container_resize(struct rte_eth_dev *dev, uint32_t batch)
4086 {
4087         struct mlx5_priv *priv = dev->data->dev_private;
4088         struct mlx5_pools_container *cont =
4089                         MLX5_CNT_CONTAINER(priv->sh, batch, 0);
4090         struct mlx5_pools_container *new_cont =
4091                         MLX5_CNT_CONTAINER_UNUSED(priv->sh, batch, 0);
4092         struct mlx5_counter_stats_mem_mng *mem_mng;
4093         uint32_t resize = cont->n + MLX5_CNT_CONTAINER_RESIZE;
4094         uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
4095         int i;
4096
4097         if (cont != MLX5_CNT_CONTAINER(priv->sh, batch, 1)) {
4098                 /* The last resize still hasn't detected by the host thread. */
4099                 rte_errno = EAGAIN;
4100                 return NULL;
4101         }
4102         new_cont->pools = rte_calloc(__func__, 1, mem_size, 0);
4103         if (!new_cont->pools) {
4104                 rte_errno = ENOMEM;
4105                 return NULL;
4106         }
4107         if (cont->n)
4108                 memcpy(new_cont->pools, cont->pools, cont->n *
4109                        sizeof(struct mlx5_flow_counter_pool *));
4110         mem_mng = flow_dv_create_counter_stat_mem_mng(dev,
4111                 MLX5_CNT_CONTAINER_RESIZE + MLX5_MAX_PENDING_QUERIES);
4112         if (!mem_mng) {
4113                 rte_free(new_cont->pools);
4114                 return NULL;
4115         }
4116         for (i = 0; i < MLX5_MAX_PENDING_QUERIES; ++i)
4117                 LIST_INSERT_HEAD(&priv->sh->cmng.free_stat_raws,
4118                                  mem_mng->raws + MLX5_CNT_CONTAINER_RESIZE +
4119                                  i, next);
4120         new_cont->n = resize;
4121         rte_atomic16_set(&new_cont->n_valid, rte_atomic16_read(&cont->n_valid));
4122         TAILQ_INIT(&new_cont->pool_list);
4123         TAILQ_CONCAT(&new_cont->pool_list, &cont->pool_list, next);
4124         new_cont->init_mem_mng = mem_mng;
4125         rte_cio_wmb();
4126          /* Flip the master container. */
4127         priv->sh->cmng.mhi[batch] ^= (uint8_t)1;
4128         return new_cont;
4129 }
4130
4131 /**
4132  * Query a devx flow counter.
4133  *
4134  * @param[in] dev
4135  *   Pointer to the Ethernet device structure.
4136  * @param[in] cnt
4137  *   Index to the flow counter.
4138  * @param[out] pkts
4139  *   The statistics value of packets.
4140  * @param[out] bytes
4141  *   The statistics value of bytes.
4142  *
4143  * @return
4144  *   0 on success, otherwise a negative errno value and rte_errno is set.
4145  */
4146 static inline int
4147 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
4148                      uint64_t *bytes)
4149 {
4150         struct mlx5_priv *priv = dev->data->dev_private;
4151         struct mlx5_flow_counter_pool *pool = NULL;
4152         struct mlx5_flow_counter *cnt;
4153         struct mlx5_flow_counter_ext *cnt_ext = NULL;
4154         int offset;
4155
4156         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
4157         MLX5_ASSERT(pool);
4158         if (counter < MLX5_CNT_BATCH_OFFSET) {
4159                 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt);
4160                 if (priv->counter_fallback)
4161                         return _flow_dv_query_count_fallback(dev, cnt_ext,
4162                                                              pkts, bytes);
4163         }
4164
4165         rte_spinlock_lock(&pool->sl);
4166         /*
4167          * The single counters allocation may allocate smaller ID than the
4168          * current allocated in parallel to the host reading.
4169          * In this case the new counter values must be reported as 0.
4170          */
4171         if (unlikely(cnt_ext && cnt_ext->dcs->id < pool->raw->min_dcs_id)) {
4172                 *pkts = 0;
4173                 *bytes = 0;
4174         } else {
4175                 offset = cnt - &pool->counters_raw[0];
4176                 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
4177                 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
4178         }
4179         rte_spinlock_unlock(&pool->sl);
4180         return 0;
4181 }
4182
4183 /**
4184  * Create and initialize a new counter pool.
4185  *
4186  * @param[in] dev
4187  *   Pointer to the Ethernet device structure.
4188  * @param[out] dcs
4189  *   The devX counter handle.
4190  * @param[in] batch
4191  *   Whether the pool is for counter that was allocated by batch command.
4192  * @param[in/out] cont_cur
4193  *   Pointer to the container pointer, it will be update in pool resize.
4194  *
4195  * @return
4196  *   The pool container pointer on success, NULL otherwise and rte_errno is set.
4197  */
4198 static struct mlx5_pools_container *
4199 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
4200                     uint32_t batch)
4201 {
4202         struct mlx5_priv *priv = dev->data->dev_private;
4203         struct mlx5_flow_counter_pool *pool;
4204         struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4205                                                                0);
4206         int16_t n_valid = rte_atomic16_read(&cont->n_valid);
4207         uint32_t size;
4208
4209         if (cont->n == n_valid) {
4210                 cont = flow_dv_container_resize(dev, batch);
4211                 if (!cont)
4212                         return NULL;
4213         }
4214         size = sizeof(*pool);
4215         if (!batch)
4216                 size += MLX5_COUNTERS_PER_POOL *
4217                         sizeof(struct mlx5_flow_counter_ext);
4218         pool = rte_calloc(__func__, 1, size, 0);
4219         if (!pool) {
4220                 rte_errno = ENOMEM;
4221                 return NULL;
4222         }
4223         if (priv->counter_fallback)
4224                 pool->dcs_id = dcs->id;
4225         else
4226                 pool->min_dcs = dcs;
4227         pool->raw = cont->init_mem_mng->raws + n_valid %
4228                                                      MLX5_CNT_CONTAINER_RESIZE;
4229         pool->raw_hw = NULL;
4230         rte_spinlock_init(&pool->sl);
4231         /*
4232          * The generation of the new allocated counters in this pool is 0, 2 in
4233          * the pool generation makes all the counters valid for allocation.
4234          * The start and end query generation protect the counters be released
4235          * between the query and update gap period will not be reallocated
4236          * without the last query finished and stats updated to the memory.
4237          */
4238         rte_atomic64_set(&pool->start_query_gen, 0x2);
4239         rte_atomic64_set(&pool->end_query_gen, 0x2);
4240         TAILQ_INIT(&pool->counters);
4241         TAILQ_INSERT_HEAD(&cont->pool_list, pool, next);
4242         pool->index = n_valid;
4243         cont->pools[n_valid] = pool;
4244         /* Pool initialization must be updated before host thread access. */
4245         rte_cio_wmb();
4246         rte_atomic16_add(&cont->n_valid, 1);
4247         return cont;
4248 }
4249
4250 /**
4251  * Prepare a new counter and/or a new counter pool.
4252  *
4253  * @param[in] dev
4254  *   Pointer to the Ethernet device structure.
4255  * @param[out] cnt_free
4256  *   Where to put the pointer of a new counter.
4257  * @param[in] batch
4258  *   Whether the pool is for counter that was allocated by batch command.
4259  *
4260  * @return
4261  *   The counter container pointer and @p cnt_free is set on success,
4262  *   NULL otherwise and rte_errno is set.
4263  */
4264 static struct mlx5_pools_container *
4265 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
4266                              struct mlx5_flow_counter **cnt_free,
4267                              uint32_t batch)
4268 {
4269         struct mlx5_priv *priv = dev->data->dev_private;
4270         struct mlx5_pools_container *cont;
4271         struct mlx5_flow_counter_pool *pool;
4272         struct mlx5_devx_obj *dcs = NULL;
4273         struct mlx5_flow_counter *cnt;
4274         uint32_t i;
4275
4276         cont = MLX5_CNT_CONTAINER(priv->sh, batch, 0);
4277         if (!batch) {
4278                 /* bulk_bitmap must be 0 for single counter allocation. */
4279                 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
4280                 if (!dcs)
4281                         return NULL;
4282                 pool = flow_dv_find_pool_by_id(cont, false, dcs->id);
4283                 if (!pool) {
4284                         cont = flow_dv_pool_create(dev, dcs, batch);
4285                         if (!cont) {
4286                                 mlx5_devx_cmd_destroy(dcs);
4287                                 return NULL;
4288                         }
4289                         pool = TAILQ_FIRST(&cont->pool_list);
4290                 } else if (dcs->id < pool->min_dcs->id) {
4291                         rte_atomic64_set(&pool->a64_dcs,
4292                                          (int64_t)(uintptr_t)dcs);
4293                 }
4294                 i = dcs->id % MLX5_COUNTERS_PER_POOL;
4295                 cnt = &pool->counters_raw[i];
4296                 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
4297                 MLX5_GET_POOL_CNT_EXT(pool, i)->dcs = dcs;
4298                 *cnt_free = cnt;
4299                 return cont;
4300         }
4301         /* bulk_bitmap is in 128 counters units. */
4302         if (priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4)
4303                 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
4304         if (!dcs) {
4305                 rte_errno = ENODATA;
4306                 return NULL;
4307         }
4308         cont = flow_dv_pool_create(dev, dcs, batch);
4309         if (!cont) {
4310                 mlx5_devx_cmd_destroy(dcs);
4311                 return NULL;
4312         }
4313         pool = TAILQ_FIRST(&cont->pool_list);
4314         for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
4315                 cnt = &pool->counters_raw[i];
4316                 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
4317         }
4318         *cnt_free = &pool->counters_raw[0];
4319         return cont;
4320 }
4321
4322 /**
4323  * Search for existed shared counter.
4324  *
4325  * @param[in] cont
4326  *   Pointer to the relevant counter pool container.
4327  * @param[in] id
4328  *   The shared counter ID to search.
4329  * @param[out] ppool
4330  *   mlx5 flow counter pool in the container,
4331  *
4332  * @return
4333  *   NULL if not existed, otherwise pointer to the shared extend counter.
4334  */
4335 static struct mlx5_flow_counter_ext *
4336 flow_dv_counter_shared_search(struct mlx5_pools_container *cont, uint32_t id,
4337                               struct mlx5_flow_counter_pool **ppool)
4338 {
4339         static struct mlx5_flow_counter_ext *cnt;
4340         struct mlx5_flow_counter_pool *pool;
4341         uint32_t i;
4342         uint32_t n_valid = rte_atomic16_read(&cont->n_valid);
4343
4344         for (i = 0; i < n_valid; i++) {
4345                 pool = cont->pools[i];
4346                 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
4347                         cnt = MLX5_GET_POOL_CNT_EXT(pool, i);
4348                         if (cnt->ref_cnt && cnt->shared && cnt->id == id) {
4349                                 if (ppool)
4350                                         *ppool = cont->pools[i];
4351                                 return cnt;
4352                         }
4353                 }
4354         }
4355         return NULL;
4356 }
4357
4358 /**
4359  * Allocate a flow counter.
4360  *
4361  * @param[in] dev
4362  *   Pointer to the Ethernet device structure.
4363  * @param[in] shared
4364  *   Indicate if this counter is shared with other flows.
4365  * @param[in] id
4366  *   Counter identifier.
4367  * @param[in] group
4368  *   Counter flow group.
4369  *
4370  * @return
4371  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
4372  */
4373 static uint32_t
4374 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t shared, uint32_t id,
4375                       uint16_t group)
4376 {
4377         struct mlx5_priv *priv = dev->data->dev_private;
4378         struct mlx5_flow_counter_pool *pool = NULL;
4379         struct mlx5_flow_counter *cnt_free = NULL;
4380         struct mlx5_flow_counter_ext *cnt_ext = NULL;
4381         /*
4382          * Currently group 0 flow counter cannot be assigned to a flow if it is
4383          * not the first one in the batch counter allocation, so it is better
4384          * to allocate counters one by one for these flows in a separate
4385          * container.
4386          * A counter can be shared between different groups so need to take
4387          * shared counters from the single container.
4388          */
4389         uint32_t batch = (group && !shared) ? 1 : 0;
4390         struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4391                                                                0);
4392         uint32_t cnt_idx;
4393
4394         if (!priv->config.devx) {
4395                 rte_errno = ENOTSUP;
4396                 return 0;
4397         }
4398         if (shared) {
4399                 cnt_ext = flow_dv_counter_shared_search(cont, id, &pool);
4400                 if (cnt_ext) {
4401                         if (cnt_ext->ref_cnt + 1 == 0) {
4402                                 rte_errno = E2BIG;
4403                                 return 0;
4404                         }
4405                         cnt_ext->ref_cnt++;
4406                         cnt_idx = pool->index * MLX5_COUNTERS_PER_POOL +
4407                                   (cnt_ext->dcs->id % MLX5_COUNTERS_PER_POOL)
4408                                   + 1;
4409                         return cnt_idx;
4410                 }
4411         }
4412         if (priv->counter_fallback)
4413                 return flow_dv_counter_alloc_fallback(dev, shared, id);
4414
4415         /* Pools which has a free counters are in the start. */
4416         TAILQ_FOREACH(pool, &cont->pool_list, next) {
4417                 /*
4418                  * The free counter reset values must be updated between the
4419                  * counter release to the counter allocation, so, at least one
4420                  * query must be done in this time. ensure it by saving the
4421                  * query generation in the release time.
4422                  * The free list is sorted according to the generation - so if
4423                  * the first one is not updated, all the others are not
4424                  * updated too.
4425                  */
4426                 cnt_free = TAILQ_FIRST(&pool->counters);
4427                 if (cnt_free && cnt_free->query_gen <
4428                     rte_atomic64_read(&pool->end_query_gen))
4429                         break;
4430                 cnt_free = NULL;
4431         }
4432         if (!cnt_free) {
4433                 cont = flow_dv_counter_pool_prepare(dev, &cnt_free, batch);
4434                 if (!cont)
4435                         return 0;
4436                 pool = TAILQ_FIRST(&cont->pool_list);
4437         }
4438         if (!batch)
4439                 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt_free);
4440         /* Create a DV counter action only in the first time usage. */
4441         if (!cnt_free->action) {
4442                 uint16_t offset;
4443                 struct mlx5_devx_obj *dcs;
4444
4445                 if (batch) {
4446                         offset = cnt_free - &pool->counters_raw[0];
4447                         dcs = pool->min_dcs;
4448                 } else {
4449                         offset = 0;
4450                         dcs = cnt_ext->dcs;
4451                 }
4452                 cnt_free->action = mlx5_glue->dv_create_flow_action_counter
4453                                         (dcs->obj, offset);
4454                 if (!cnt_free->action) {
4455                         rte_errno = errno;
4456                         return 0;
4457                 }
4458         }
4459         cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
4460                                     (cnt_free - pool->counters_raw));
4461         cnt_idx += batch * MLX5_CNT_BATCH_OFFSET;
4462         /* Update the counter reset values. */
4463         if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
4464                                  &cnt_free->bytes))
4465                 return 0;
4466         if (cnt_ext) {
4467                 cnt_ext->shared = shared;
4468                 cnt_ext->ref_cnt = 1;
4469                 cnt_ext->id = id;
4470         }
4471         if (!priv->sh->cmng.query_thread_on)
4472                 /* Start the asynchronous batch query by the host thread. */
4473                 mlx5_set_query_alarm(priv->sh);
4474         TAILQ_REMOVE(&pool->counters, cnt_free, next);
4475         if (TAILQ_EMPTY(&pool->counters)) {
4476                 /* Move the pool to the end of the container pool list. */
4477                 TAILQ_REMOVE(&cont->pool_list, pool, next);
4478                 TAILQ_INSERT_TAIL(&cont->pool_list, pool, next);
4479         }
4480         return cnt_idx;
4481 }
4482
4483 /**
4484  * Release a flow counter.
4485  *
4486  * @param[in] dev
4487  *   Pointer to the Ethernet device structure.
4488  * @param[in] counter
4489  *   Index to the counter handler.
4490  */
4491 static void
4492 flow_dv_counter_release(struct rte_eth_dev *dev, uint32_t counter)
4493 {
4494         struct mlx5_priv *priv = dev->data->dev_private;
4495         struct mlx5_flow_counter_pool *pool = NULL;
4496         struct mlx5_flow_counter *cnt;
4497         struct mlx5_flow_counter_ext *cnt_ext = NULL;
4498
4499         if (!counter)
4500                 return;
4501         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
4502         MLX5_ASSERT(pool);
4503         if (counter < MLX5_CNT_BATCH_OFFSET)
4504                 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt);
4505         if (cnt_ext && --cnt_ext->ref_cnt)
4506                 return;
4507         if (priv->counter_fallback) {
4508                 claim_zero(mlx5_glue->destroy_flow_action(cnt->action));
4509                 flow_dv_counter_release_fallback(dev, cnt_ext);
4510                 cnt->action = NULL;
4511                 return;
4512         }
4513         /* Put the counter in the end - the last updated one. */
4514         TAILQ_INSERT_TAIL(&pool->counters, cnt, next);
4515         /*
4516          * Counters released between query trigger and handler need
4517          * to wait the next round of query. Since the packets arrive
4518          * in the gap period will not be taken into account to the
4519          * old counter.
4520          */
4521         cnt->query_gen = rte_atomic64_read(&pool->start_query_gen);
4522 }
4523
4524 /**
4525  * Verify the @p attributes will be correctly understood by the NIC and store
4526  * them in the @p flow if everything is correct.
4527  *
4528  * @param[in] dev
4529  *   Pointer to dev struct.
4530  * @param[in] attributes
4531  *   Pointer to flow attributes
4532  * @param[in] external
4533  *   This flow rule is created by request external to PMD.
4534  * @param[out] error
4535  *   Pointer to error structure.
4536  *
4537  * @return
4538  *   0 on success, a negative errno value otherwise and rte_errno is set.
4539  */
4540 static int
4541 flow_dv_validate_attributes(struct rte_eth_dev *dev,
4542                             const struct rte_flow_attr *attributes,
4543                             bool external __rte_unused,
4544                             struct rte_flow_error *error)
4545 {
4546         struct mlx5_priv *priv = dev->data->dev_private;
4547         uint32_t priority_max = priv->config.flow_prio - 1;
4548
4549 #ifndef HAVE_MLX5DV_DR
4550         if (attributes->group)
4551                 return rte_flow_error_set(error, ENOTSUP,
4552                                           RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
4553                                           NULL,
4554                                           "groups are not supported");
4555 #else
4556         uint32_t table;
4557         int ret;
4558
4559         ret = mlx5_flow_group_to_table(attributes, external,
4560                                        attributes->group, !!priv->fdb_def_rule,
4561                                        &table, error);
4562         if (ret)
4563                 return ret;
4564 #endif
4565         if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
4566             attributes->priority >= priority_max)
4567                 return rte_flow_error_set(error, ENOTSUP,
4568                                           RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
4569                                           NULL,
4570                                           "priority out of range");
4571         if (attributes->transfer) {
4572                 if (!priv->config.dv_esw_en)
4573                         return rte_flow_error_set
4574                                 (error, ENOTSUP,
4575                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4576                                  "E-Switch dr is not supported");
4577                 if (!(priv->representor || priv->master))
4578                         return rte_flow_error_set
4579                                 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4580                                  NULL, "E-Switch configuration can only be"
4581                                  " done by a master or a representor device");
4582                 if (attributes->egress)
4583                         return rte_flow_error_set
4584                                 (error, ENOTSUP,
4585                                  RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
4586                                  "egress is not supported");
4587         }
4588         if (!(attributes->egress ^ attributes->ingress))
4589                 return rte_flow_error_set(error, ENOTSUP,
4590                                           RTE_FLOW_ERROR_TYPE_ATTR, NULL,
4591                                           "must specify exactly one of "
4592                                           "ingress or egress");
4593         return 0;
4594 }
4595
4596 /**
4597  * Internal validation function. For validating both actions and items.
4598  *
4599  * @param[in] dev
4600  *   Pointer to the rte_eth_dev structure.
4601  * @param[in] attr
4602  *   Pointer to the flow attributes.
4603  * @param[in] items
4604  *   Pointer to the list of items.
4605  * @param[in] actions
4606  *   Pointer to the list of actions.
4607  * @param[in] external
4608  *   This flow rule is created by request external to PMD.
4609  * @param[out] error
4610  *   Pointer to the error structure.
4611  *
4612  * @return
4613  *   0 on success, a negative errno value otherwise and rte_errno is set.
4614  */
4615 static int
4616 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
4617                  const struct rte_flow_item items[],
4618                  const struct rte_flow_action actions[],
4619                  bool external, struct rte_flow_error *error)
4620 {
4621         int ret;
4622         uint64_t action_flags = 0;
4623         uint64_t item_flags = 0;
4624         uint64_t last_item = 0;
4625         uint8_t next_protocol = 0xff;
4626         uint16_t ether_type = 0;
4627         int actions_n = 0;
4628         uint8_t item_ipv6_proto = 0;
4629         const struct rte_flow_item *gre_item = NULL;
4630         const struct rte_flow_action_raw_decap *decap;
4631         const struct rte_flow_action_raw_encap *encap;
4632         const struct rte_flow_action_rss *rss;
4633         const struct rte_flow_item_tcp nic_tcp_mask = {
4634                 .hdr = {
4635                         .tcp_flags = 0xFF,
4636                         .src_port = RTE_BE16(UINT16_MAX),
4637                         .dst_port = RTE_BE16(UINT16_MAX),
4638                 }
4639         };
4640         const struct rte_flow_item_ipv4 nic_ipv4_mask = {
4641                 .hdr = {
4642                         .src_addr = RTE_BE32(0xffffffff),
4643                         .dst_addr = RTE_BE32(0xffffffff),
4644                         .type_of_service = 0xff,
4645                         .next_proto_id = 0xff,
4646                         .time_to_live = 0xff,
4647                 },
4648         };
4649         const struct rte_flow_item_ipv6 nic_ipv6_mask = {
4650                 .hdr = {
4651                         .src_addr =
4652                         "\xff\xff\xff\xff\xff\xff\xff\xff"
4653                         "\xff\xff\xff\xff\xff\xff\xff\xff",
4654                         .dst_addr =
4655                         "\xff\xff\xff\xff\xff\xff\xff\xff"
4656                         "\xff\xff\xff\xff\xff\xff\xff\xff",
4657                         .vtc_flow = RTE_BE32(0xffffffff),
4658                         .proto = 0xff,
4659                         .hop_limits = 0xff,
4660                 },
4661         };
4662         struct mlx5_priv *priv = dev->data->dev_private;
4663         struct mlx5_dev_config *dev_conf = &priv->config;
4664         uint16_t queue_index = 0xFFFF;
4665
4666         if (items == NULL)
4667                 return -1;
4668         ret = flow_dv_validate_attributes(dev, attr, external, error);
4669         if (ret < 0)
4670                 return ret;
4671         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
4672                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
4673                 int type = items->type;
4674
4675                 switch (type) {
4676                 case RTE_FLOW_ITEM_TYPE_VOID:
4677                         break;
4678                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
4679                         ret = flow_dv_validate_item_port_id
4680                                         (dev, items, attr, item_flags, error);
4681                         if (ret < 0)
4682                                 return ret;
4683                         last_item = MLX5_FLOW_ITEM_PORT_ID;
4684                         break;
4685                 case RTE_FLOW_ITEM_TYPE_ETH:
4686                         ret = mlx5_flow_validate_item_eth(items, item_flags,
4687                                                           error);
4688                         if (ret < 0)
4689                                 return ret;
4690                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
4691                                              MLX5_FLOW_LAYER_OUTER_L2;
4692                         if (items->mask != NULL && items->spec != NULL) {
4693                                 ether_type =
4694                                         ((const struct rte_flow_item_eth *)
4695                                          items->spec)->type;
4696                                 ether_type &=
4697                                         ((const struct rte_flow_item_eth *)
4698                                          items->mask)->type;
4699                                 ether_type = rte_be_to_cpu_16(ether_type);
4700                         } else {
4701                                 ether_type = 0;
4702                         }
4703                         break;
4704                 case RTE_FLOW_ITEM_TYPE_VLAN:
4705                         ret = mlx5_flow_validate_item_vlan(items, item_flags,
4706                                                            dev, error);
4707                         if (ret < 0)
4708                                 return ret;
4709                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
4710                                              MLX5_FLOW_LAYER_OUTER_VLAN;
4711                         if (items->mask != NULL && items->spec != NULL) {
4712                                 ether_type =
4713                                         ((const struct rte_flow_item_vlan *)
4714                                          items->spec)->inner_type;
4715                                 ether_type &=
4716                                         ((const struct rte_flow_item_vlan *)
4717                                          items->mask)->inner_type;
4718                                 ether_type = rte_be_to_cpu_16(ether_type);
4719                         } else {
4720                                 ether_type = 0;
4721                         }
4722                         break;
4723                 case RTE_FLOW_ITEM_TYPE_IPV4:
4724                         mlx5_flow_tunnel_ip_check(items, next_protocol,
4725                                                   &item_flags, &tunnel);
4726                         ret = mlx5_flow_validate_item_ipv4(items, item_flags,
4727                                                            last_item,
4728                                                            ether_type,
4729                                                            &nic_ipv4_mask,
4730                                                            error);
4731                         if (ret < 0)
4732                                 return ret;
4733                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
4734                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
4735                         if (items->mask != NULL &&
4736                             ((const struct rte_flow_item_ipv4 *)
4737                              items->mask)->hdr.next_proto_id) {
4738                                 next_protocol =
4739                                         ((const struct rte_flow_item_ipv4 *)
4740                                          (items->spec))->hdr.next_proto_id;
4741                                 next_protocol &=
4742                                         ((const struct rte_flow_item_ipv4 *)
4743                                          (items->mask))->hdr.next_proto_id;
4744                         } else {
4745                                 /* Reset for inner layer. */
4746                                 next_protocol = 0xff;
4747                         }
4748                         break;
4749                 case RTE_FLOW_ITEM_TYPE_IPV6:
4750                         mlx5_flow_tunnel_ip_check(items, next_protocol,
4751                                                   &item_flags, &tunnel);
4752                         ret = mlx5_flow_validate_item_ipv6(items, item_flags,
4753                                                            last_item,
4754                                                            ether_type,
4755                                                            &nic_ipv6_mask,
4756                                                            error);
4757                         if (ret < 0)
4758                                 return ret;
4759                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
4760                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
4761                         if (items->mask != NULL &&
4762                             ((const struct rte_flow_item_ipv6 *)
4763                              items->mask)->hdr.proto) {
4764                                 item_ipv6_proto =
4765                                         ((const struct rte_flow_item_ipv6 *)
4766                                          items->spec)->hdr.proto;
4767                                 next_protocol =
4768                                         ((const struct rte_flow_item_ipv6 *)
4769                                          items->spec)->hdr.proto;
4770                                 next_protocol &=
4771                                         ((const struct rte_flow_item_ipv6 *)
4772                                          items->mask)->hdr.proto;
4773                         } else {
4774                                 /* Reset for inner layer. */
4775                                 next_protocol = 0xff;
4776                         }
4777                         break;
4778                 case RTE_FLOW_ITEM_TYPE_TCP:
4779                         ret = mlx5_flow_validate_item_tcp
4780                                                 (items, item_flags,
4781                                                  next_protocol,
4782                                                  &nic_tcp_mask,
4783                                                  error);
4784                         if (ret < 0)
4785                                 return ret;
4786                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
4787                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
4788                         break;
4789                 case RTE_FLOW_ITEM_TYPE_UDP:
4790                         ret = mlx5_flow_validate_item_udp(items, item_flags,
4791                                                           next_protocol,
4792                                                           error);
4793                         if (ret < 0)
4794                                 return ret;
4795                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
4796                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
4797                         break;
4798                 case RTE_FLOW_ITEM_TYPE_GRE:
4799                         ret = mlx5_flow_validate_item_gre(items, item_flags,
4800                                                           next_protocol, error);
4801                         if (ret < 0)
4802                                 return ret;
4803                         gre_item = items;
4804                         last_item = MLX5_FLOW_LAYER_GRE;
4805                         break;
4806                 case RTE_FLOW_ITEM_TYPE_NVGRE:
4807                         ret = mlx5_flow_validate_item_nvgre(items, item_flags,
4808                                                             next_protocol,
4809                                                             error);
4810                         if (ret < 0)
4811                                 return ret;
4812                         last_item = MLX5_FLOW_LAYER_NVGRE;
4813                         break;
4814                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
4815                         ret = mlx5_flow_validate_item_gre_key
4816                                 (items, item_flags, gre_item, error);
4817                         if (ret < 0)
4818                                 return ret;
4819                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
4820                         break;
4821                 case RTE_FLOW_ITEM_TYPE_VXLAN:
4822                         ret = mlx5_flow_validate_item_vxlan(items, item_flags,
4823                                                             error);
4824                         if (ret < 0)
4825                                 return ret;
4826                         last_item = MLX5_FLOW_LAYER_VXLAN;
4827                         break;
4828                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
4829                         ret = mlx5_flow_validate_item_vxlan_gpe(items,
4830                                                                 item_flags, dev,
4831                                                                 error);
4832                         if (ret < 0)
4833                                 return ret;
4834                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
4835                         break;
4836                 case RTE_FLOW_ITEM_TYPE_GENEVE:
4837                         ret = mlx5_flow_validate_item_geneve(items,
4838                                                              item_flags, dev,
4839                                                              error);
4840                         if (ret < 0)
4841                                 return ret;
4842                         last_item = MLX5_FLOW_LAYER_GENEVE;
4843                         break;
4844                 case RTE_FLOW_ITEM_TYPE_MPLS:
4845                         ret = mlx5_flow_validate_item_mpls(dev, items,
4846                                                            item_flags,
4847                                                            last_item, error);
4848                         if (ret < 0)
4849                                 return ret;
4850                         last_item = MLX5_FLOW_LAYER_MPLS;
4851                         break;
4852
4853                 case RTE_FLOW_ITEM_TYPE_MARK:
4854                         ret = flow_dv_validate_item_mark(dev, items, attr,
4855                                                          error);
4856                         if (ret < 0)
4857                                 return ret;
4858                         last_item = MLX5_FLOW_ITEM_MARK;
4859                         break;
4860                 case RTE_FLOW_ITEM_TYPE_META:
4861                         ret = flow_dv_validate_item_meta(dev, items, attr,
4862                                                          error);
4863                         if (ret < 0)
4864                                 return ret;
4865                         last_item = MLX5_FLOW_ITEM_METADATA;
4866                         break;
4867                 case RTE_FLOW_ITEM_TYPE_ICMP:
4868                         ret = mlx5_flow_validate_item_icmp(items, item_flags,
4869                                                            next_protocol,
4870                                                            error);
4871                         if (ret < 0)
4872                                 return ret;
4873                         last_item = MLX5_FLOW_LAYER_ICMP;
4874                         break;
4875                 case RTE_FLOW_ITEM_TYPE_ICMP6:
4876                         ret = mlx5_flow_validate_item_icmp6(items, item_flags,
4877                                                             next_protocol,
4878                                                             error);
4879                         if (ret < 0)
4880                                 return ret;
4881                         item_ipv6_proto = IPPROTO_ICMPV6;
4882                         last_item = MLX5_FLOW_LAYER_ICMP6;
4883                         break;
4884                 case RTE_FLOW_ITEM_TYPE_TAG:
4885                         ret = flow_dv_validate_item_tag(dev, items,
4886                                                         attr, error);
4887                         if (ret < 0)
4888                                 return ret;
4889                         last_item = MLX5_FLOW_ITEM_TAG;
4890                         break;
4891                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
4892                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
4893                         break;
4894                 case RTE_FLOW_ITEM_TYPE_GTP:
4895                         ret = flow_dv_validate_item_gtp(dev, items, item_flags,
4896                                                         error);
4897                         if (ret < 0)
4898                                 return ret;
4899                         last_item = MLX5_FLOW_LAYER_GTP;
4900                         break;
4901                 default:
4902                         return rte_flow_error_set(error, ENOTSUP,
4903                                                   RTE_FLOW_ERROR_TYPE_ITEM,
4904                                                   NULL, "item not supported");
4905                 }
4906                 item_flags |= last_item;
4907         }
4908         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
4909                 int type = actions->type;
4910                 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
4911                         return rte_flow_error_set(error, ENOTSUP,
4912                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4913                                                   actions, "too many actions");
4914                 switch (type) {
4915                 case RTE_FLOW_ACTION_TYPE_VOID:
4916                         break;
4917                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
4918                         ret = flow_dv_validate_action_port_id(dev,
4919                                                               action_flags,
4920                                                               actions,
4921                                                               attr,
4922                                                               error);
4923                         if (ret)
4924                                 return ret;
4925                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
4926                         ++actions_n;
4927                         break;
4928                 case RTE_FLOW_ACTION_TYPE_FLAG:
4929                         ret = flow_dv_validate_action_flag(dev, action_flags,
4930                                                            attr, error);
4931                         if (ret < 0)
4932                                 return ret;
4933                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
4934                                 /* Count all modify-header actions as one. */
4935                                 if (!(action_flags &
4936                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
4937                                         ++actions_n;
4938                                 action_flags |= MLX5_FLOW_ACTION_FLAG |
4939                                                 MLX5_FLOW_ACTION_MARK_EXT;
4940                         } else {
4941                                 action_flags |= MLX5_FLOW_ACTION_FLAG;
4942                                 ++actions_n;
4943                         }
4944                         break;
4945                 case RTE_FLOW_ACTION_TYPE_MARK:
4946                         ret = flow_dv_validate_action_mark(dev, actions,
4947                                                            action_flags,
4948                                                            attr, error);
4949                         if (ret < 0)
4950                                 return ret;
4951                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
4952                                 /* Count all modify-header actions as one. */
4953                                 if (!(action_flags &
4954                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
4955                                         ++actions_n;
4956                                 action_flags |= MLX5_FLOW_ACTION_MARK |
4957                                                 MLX5_FLOW_ACTION_MARK_EXT;
4958                         } else {
4959                                 action_flags |= MLX5_FLOW_ACTION_MARK;
4960                                 ++actions_n;
4961                         }
4962                         break;
4963                 case RTE_FLOW_ACTION_TYPE_SET_META:
4964                         ret = flow_dv_validate_action_set_meta(dev, actions,
4965                                                                action_flags,
4966                                                                attr, error);
4967                         if (ret < 0)
4968                                 return ret;
4969                         /* Count all modify-header actions as one action. */
4970                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4971                                 ++actions_n;
4972                         action_flags |= MLX5_FLOW_ACTION_SET_META;
4973                         break;
4974                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
4975                         ret = flow_dv_validate_action_set_tag(dev, actions,
4976                                                               action_flags,
4977                                                               attr, error);
4978                         if (ret < 0)
4979                                 return ret;
4980                         /* Count all modify-header actions as one action. */
4981                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4982                                 ++actions_n;
4983                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
4984                         break;
4985                 case RTE_FLOW_ACTION_TYPE_DROP:
4986                         ret = mlx5_flow_validate_action_drop(action_flags,
4987                                                              attr, error);
4988                         if (ret < 0)
4989                                 return ret;
4990                         action_flags |= MLX5_FLOW_ACTION_DROP;
4991                         ++actions_n;
4992                         break;
4993                 case RTE_FLOW_ACTION_TYPE_QUEUE:
4994                         ret = mlx5_flow_validate_action_queue(actions,
4995                                                               action_flags, dev,
4996                                                               attr, error);
4997                         if (ret < 0)
4998                                 return ret;
4999                         queue_index = ((const struct rte_flow_action_queue *)
5000                                                         (actions->conf))->index;
5001                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
5002                         ++actions_n;
5003                         break;
5004                 case RTE_FLOW_ACTION_TYPE_RSS:
5005                         rss = actions->conf;
5006                         ret = mlx5_flow_validate_action_rss(actions,
5007                                                             action_flags, dev,
5008                                                             attr, item_flags,
5009                                                             error);
5010                         if (ret < 0)
5011                                 return ret;
5012                         if (rss != NULL && rss->queue_num)
5013                                 queue_index = rss->queue[0];
5014                         action_flags |= MLX5_FLOW_ACTION_RSS;
5015                         ++actions_n;
5016                         break;
5017                 case RTE_FLOW_ACTION_TYPE_COUNT:
5018                         ret = flow_dv_validate_action_count(dev, error);
5019                         if (ret < 0)
5020                                 return ret;
5021                         action_flags |= MLX5_FLOW_ACTION_COUNT;
5022                         ++actions_n;
5023                         break;
5024                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
5025                         if (flow_dv_validate_action_pop_vlan(dev,
5026                                                              action_flags,
5027                                                              actions,
5028                                                              item_flags, attr,
5029                                                              error))
5030                                 return -rte_errno;
5031                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
5032                         ++actions_n;
5033                         break;
5034                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
5035                         ret = flow_dv_validate_action_push_vlan(dev,
5036                                                                 action_flags,
5037                                                                 item_flags,
5038                                                                 actions, attr,
5039                                                                 error);
5040                         if (ret < 0)
5041                                 return ret;
5042                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
5043                         ++actions_n;
5044                         break;
5045                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
5046                         ret = flow_dv_validate_action_set_vlan_pcp
5047                                                 (action_flags, actions, error);
5048                         if (ret < 0)
5049                                 return ret;
5050                         /* Count PCP with push_vlan command. */
5051                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
5052                         break;
5053                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
5054                         ret = flow_dv_validate_action_set_vlan_vid
5055                                                 (item_flags, action_flags,
5056                                                  actions, error);
5057                         if (ret < 0)
5058                                 return ret;
5059                         /* Count VID with push_vlan command. */
5060                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
5061                         break;
5062                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5063                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5064                         ret = flow_dv_validate_action_l2_encap(dev,
5065                                                                action_flags,
5066                                                                actions, attr,
5067                                                                error);
5068                         if (ret < 0)
5069                                 return ret;
5070                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
5071                         ++actions_n;
5072                         break;
5073                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
5074                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
5075                         ret = flow_dv_validate_action_decap(dev, action_flags,
5076                                                             attr, error);
5077                         if (ret < 0)
5078                                 return ret;
5079                         action_flags |= MLX5_FLOW_ACTION_DECAP;
5080                         ++actions_n;
5081                         break;
5082                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5083                         ret = flow_dv_validate_action_raw_encap_decap
5084                                 (dev, NULL, actions->conf, attr, &action_flags,
5085                                  &actions_n, error);
5086                         if (ret < 0)
5087                                 return ret;
5088                         break;
5089                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
5090                         decap = actions->conf;
5091                         while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
5092                                 ;
5093                         if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
5094                                 encap = NULL;
5095                                 actions--;
5096                         } else {
5097                                 encap = actions->conf;
5098                         }
5099                         ret = flow_dv_validate_action_raw_encap_decap
5100                                            (dev,
5101                                             decap ? decap : &empty_decap, encap,
5102                                             attr, &action_flags, &actions_n,
5103                                             error);
5104                         if (ret < 0)
5105                                 return ret;
5106                         break;
5107                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
5108                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
5109                         ret = flow_dv_validate_action_modify_mac(action_flags,
5110                                                                  actions,
5111                                                                  item_flags,
5112                                                                  error);
5113                         if (ret < 0)
5114                                 return ret;
5115                         /* Count all modify-header actions as one action. */
5116                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5117                                 ++actions_n;
5118                         action_flags |= actions->type ==
5119                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
5120                                                 MLX5_FLOW_ACTION_SET_MAC_SRC :
5121                                                 MLX5_FLOW_ACTION_SET_MAC_DST;
5122                         break;
5123
5124                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
5125                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
5126                         ret = flow_dv_validate_action_modify_ipv4(action_flags,
5127                                                                   actions,
5128                                                                   item_flags,
5129                                                                   error);
5130                         if (ret < 0)
5131                                 return ret;
5132                         /* Count all modify-header actions as one action. */
5133                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5134                                 ++actions_n;
5135                         action_flags |= actions->type ==
5136                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
5137                                                 MLX5_FLOW_ACTION_SET_IPV4_SRC :
5138                                                 MLX5_FLOW_ACTION_SET_IPV4_DST;
5139                         break;
5140                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
5141                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
5142                         ret = flow_dv_validate_action_modify_ipv6(action_flags,
5143                                                                   actions,
5144                                                                   item_flags,
5145                                                                   error);
5146                         if (ret < 0)
5147                                 return ret;
5148                         if (item_ipv6_proto == IPPROTO_ICMPV6)
5149                                 return rte_flow_error_set(error, ENOTSUP,
5150                                         RTE_FLOW_ERROR_TYPE_ACTION,
5151                                         actions,
5152                                         "Can't change header "
5153                                         "with ICMPv6 proto");
5154                         /* Count all modify-header actions as one action. */
5155                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5156                                 ++actions_n;
5157                         action_flags |= actions->type ==
5158                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
5159                                                 MLX5_FLOW_ACTION_SET_IPV6_SRC :
5160                                                 MLX5_FLOW_ACTION_SET_IPV6_DST;
5161                         break;
5162                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
5163                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
5164                         ret = flow_dv_validate_action_modify_tp(action_flags,
5165                                                                 actions,
5166                                                                 item_flags,
5167                                                                 error);
5168                         if (ret < 0)
5169                                 return ret;
5170                         /* Count all modify-header actions as one action. */
5171                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5172                                 ++actions_n;
5173                         action_flags |= actions->type ==
5174                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
5175                                                 MLX5_FLOW_ACTION_SET_TP_SRC :
5176                                                 MLX5_FLOW_ACTION_SET_TP_DST;
5177                         break;
5178                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
5179                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
5180                         ret = flow_dv_validate_action_modify_ttl(action_flags,
5181                                                                  actions,
5182                                                                  item_flags,
5183                                                                  error);
5184                         if (ret < 0)
5185                                 return ret;
5186                         /* Count all modify-header actions as one action. */
5187                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5188                                 ++actions_n;
5189                         action_flags |= actions->type ==
5190                                         RTE_FLOW_ACTION_TYPE_SET_TTL ?
5191                                                 MLX5_FLOW_ACTION_SET_TTL :
5192                                                 MLX5_FLOW_ACTION_DEC_TTL;
5193                         break;
5194                 case RTE_FLOW_ACTION_TYPE_JUMP:
5195                         ret = flow_dv_validate_action_jump(actions,
5196                                                            action_flags,
5197                                                            attr, external,
5198                                                            error);
5199                         if (ret)
5200                                 return ret;
5201                         ++actions_n;
5202                         action_flags |= MLX5_FLOW_ACTION_JUMP;
5203                         break;
5204                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
5205                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
5206                         ret = flow_dv_validate_action_modify_tcp_seq
5207                                                                 (action_flags,
5208                                                                  actions,
5209                                                                  item_flags,
5210                                                                  error);
5211                         if (ret < 0)
5212                                 return ret;
5213                         /* Count all modify-header actions as one action. */
5214                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5215                                 ++actions_n;
5216                         action_flags |= actions->type ==
5217                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
5218                                                 MLX5_FLOW_ACTION_INC_TCP_SEQ :
5219                                                 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
5220                         break;
5221                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
5222                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
5223                         ret = flow_dv_validate_action_modify_tcp_ack
5224                                                                 (action_flags,
5225                                                                  actions,
5226                                                                  item_flags,
5227                                                                  error);
5228                         if (ret < 0)
5229                                 return ret;
5230                         /* Count all modify-header actions as one action. */
5231                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5232                                 ++actions_n;
5233                         action_flags |= actions->type ==
5234                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
5235                                                 MLX5_FLOW_ACTION_INC_TCP_ACK :
5236                                                 MLX5_FLOW_ACTION_DEC_TCP_ACK;
5237                         break;
5238                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
5239                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
5240                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
5241                         break;
5242                 case RTE_FLOW_ACTION_TYPE_METER:
5243                         ret = mlx5_flow_validate_action_meter(dev,
5244                                                               action_flags,
5245                                                               actions, attr,
5246                                                               error);
5247                         if (ret < 0)
5248                                 return ret;
5249                         action_flags |= MLX5_FLOW_ACTION_METER;
5250                         ++actions_n;
5251                         break;
5252                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
5253                         ret = flow_dv_validate_action_modify_ipv4_dscp
5254                                                          (action_flags,
5255                                                           actions,
5256                                                           item_flags,
5257                                                           error);
5258                         if (ret < 0)
5259                                 return ret;
5260                         /* Count all modify-header actions as one action. */
5261                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5262                                 ++actions_n;
5263                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
5264                         break;
5265                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
5266                         ret = flow_dv_validate_action_modify_ipv6_dscp
5267                                                                 (action_flags,
5268                                                                  actions,
5269                                                                  item_flags,
5270                                                                  error);
5271                         if (ret < 0)
5272                                 return ret;
5273                         /* Count all modify-header actions as one action. */
5274                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5275                                 ++actions_n;
5276                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
5277                         break;
5278                 default:
5279                         return rte_flow_error_set(error, ENOTSUP,
5280                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5281                                                   actions,
5282                                                   "action not supported");
5283                 }
5284         }
5285         /*
5286          * Validate the drop action mutual exclusion with other actions.
5287          * Drop action is mutually-exclusive with any other action, except for
5288          * Count action.
5289          */
5290         if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
5291             (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
5292                 return rte_flow_error_set(error, EINVAL,
5293                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5294                                           "Drop action is mutually-exclusive "
5295                                           "with any other action, except for "
5296                                           "Count action");
5297         /* Eswitch has few restrictions on using items and actions */
5298         if (attr->transfer) {
5299                 if (!mlx5_flow_ext_mreg_supported(dev) &&
5300                     action_flags & MLX5_FLOW_ACTION_FLAG)
5301                         return rte_flow_error_set(error, ENOTSUP,
5302                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5303                                                   NULL,
5304                                                   "unsupported action FLAG");
5305                 if (!mlx5_flow_ext_mreg_supported(dev) &&
5306                     action_flags & MLX5_FLOW_ACTION_MARK)
5307                         return rte_flow_error_set(error, ENOTSUP,
5308                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5309                                                   NULL,
5310                                                   "unsupported action MARK");
5311                 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
5312                         return rte_flow_error_set(error, ENOTSUP,
5313                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5314                                                   NULL,
5315                                                   "unsupported action QUEUE");
5316                 if (action_flags & MLX5_FLOW_ACTION_RSS)
5317                         return rte_flow_error_set(error, ENOTSUP,
5318                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5319                                                   NULL,
5320                                                   "unsupported action RSS");
5321                 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
5322                         return rte_flow_error_set(error, EINVAL,
5323                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5324                                                   actions,
5325                                                   "no fate action is found");
5326         } else {
5327                 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
5328                         return rte_flow_error_set(error, EINVAL,
5329                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5330                                                   actions,
5331                                                   "no fate action is found");
5332         }
5333         /* Continue validation for Xcap actions.*/
5334         if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) && (queue_index == 0xFFFF ||
5335             mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
5336                 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
5337                     MLX5_FLOW_XCAP_ACTIONS)
5338                         return rte_flow_error_set(error, ENOTSUP,
5339                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5340                                                   NULL, "encap and decap "
5341                                                   "combination aren't supported");
5342                 if (!attr->transfer && attr->ingress && (action_flags &
5343                                                         MLX5_FLOW_ACTION_ENCAP))
5344                         return rte_flow_error_set(error, ENOTSUP,
5345                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5346                                                   NULL, "encap is not supported"
5347                                                   " for ingress traffic");
5348         }
5349         return 0;
5350 }
5351
5352 /**
5353  * Internal preparation function. Allocates the DV flow size,
5354  * this size is constant.
5355  *
5356  * @param[in] dev
5357  *   Pointer to the rte_eth_dev structure.
5358  * @param[in] attr
5359  *   Pointer to the flow attributes.
5360  * @param[in] items
5361  *   Pointer to the list of items.
5362  * @param[in] actions
5363  *   Pointer to the list of actions.
5364  * @param[out] error
5365  *   Pointer to the error structure.
5366  *
5367  * @return
5368  *   Pointer to mlx5_flow object on success,
5369  *   otherwise NULL and rte_errno is set.
5370  */
5371 static struct mlx5_flow *
5372 flow_dv_prepare(struct rte_eth_dev *dev,
5373                 const struct rte_flow_attr *attr __rte_unused,
5374                 const struct rte_flow_item items[] __rte_unused,
5375                 const struct rte_flow_action actions[] __rte_unused,
5376                 struct rte_flow_error *error)
5377 {
5378         size_t size = sizeof(struct mlx5_flow_handle);
5379         struct mlx5_flow *dev_flow;
5380         struct mlx5_flow_handle *dev_handle;
5381         struct mlx5_priv *priv = dev->data->dev_private;
5382
5383         /* In case of corrupting the memory. */
5384         if (priv->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
5385                 rte_flow_error_set(error, ENOSPC,
5386                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5387                                    "not free temporary device flow");
5388                 return NULL;
5389         }
5390         dev_handle = rte_calloc(__func__, 1, size, 0);
5391         if (!dev_handle) {
5392                 rte_flow_error_set(error, ENOMEM,
5393                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5394                                    "not enough memory to create flow handle");
5395                 return NULL;
5396         }
5397         /* No multi-thread supporting. */
5398         dev_flow = &((struct mlx5_flow *)priv->inter_flows)[priv->flow_idx++];
5399         dev_flow->handle = dev_handle;
5400         dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);
5401         /*
5402          * The matching value needs to be cleared to 0 before using. In the
5403          * past, it will be automatically cleared when using rte_*alloc
5404          * API. The time consumption will be almost the same as before.
5405          */
5406         memset(dev_flow->dv.value.buf, 0, MLX5_ST_SZ_BYTES(fte_match_param));
5407         dev_flow->ingress = attr->ingress;
5408         dev_flow->dv.transfer = attr->transfer;
5409         return dev_flow;
5410 }
5411
5412 #ifdef RTE_LIBRTE_MLX5_DEBUG
5413 /**
5414  * Sanity check for match mask and value. Similar to check_valid_spec() in
5415  * kernel driver. If unmasked bit is present in value, it returns failure.
5416  *
5417  * @param match_mask
5418  *   pointer to match mask buffer.
5419  * @param match_value
5420  *   pointer to match value buffer.
5421  *
5422  * @return
5423  *   0 if valid, -EINVAL otherwise.
5424  */
5425 static int
5426 flow_dv_check_valid_spec(void *match_mask, void *match_value)
5427 {
5428         uint8_t *m = match_mask;
5429         uint8_t *v = match_value;
5430         unsigned int i;
5431
5432         for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
5433                 if (v[i] & ~m[i]) {
5434                         DRV_LOG(ERR,
5435                                 "match_value differs from match_criteria"
5436                                 " %p[%u] != %p[%u]",
5437                                 match_value, i, match_mask, i);
5438                         return -EINVAL;
5439                 }
5440         }
5441         return 0;
5442 }
5443 #endif
5444
5445 /**
5446  * Add Ethernet item to matcher and to the value.
5447  *
5448  * @param[in, out] matcher
5449  *   Flow matcher.
5450  * @param[in, out] key
5451  *   Flow matcher value.
5452  * @param[in] item
5453  *   Flow pattern to translate.
5454  * @param[in] inner
5455  *   Item is inner pattern.
5456  */
5457 static void
5458 flow_dv_translate_item_eth(void *matcher, void *key,
5459                            const struct rte_flow_item *item, int inner)
5460 {
5461         const struct rte_flow_item_eth *eth_m = item->mask;
5462         const struct rte_flow_item_eth *eth_v = item->spec;
5463         const struct rte_flow_item_eth nic_mask = {
5464                 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5465                 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5466                 .type = RTE_BE16(0xffff),
5467         };
5468         void *headers_m;
5469         void *headers_v;
5470         char *l24_v;
5471         unsigned int i;
5472
5473         if (!eth_v)
5474                 return;
5475         if (!eth_m)
5476                 eth_m = &nic_mask;
5477         if (inner) {
5478                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5479                                          inner_headers);
5480                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5481         } else {
5482                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5483                                          outer_headers);
5484                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5485         }
5486         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, dmac_47_16),
5487                &eth_m->dst, sizeof(eth_m->dst));
5488         /* The value must be in the range of the mask. */
5489         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, dmac_47_16);
5490         for (i = 0; i < sizeof(eth_m->dst); ++i)
5491                 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
5492         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, smac_47_16),
5493                &eth_m->src, sizeof(eth_m->src));
5494         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, smac_47_16);
5495         /* The value must be in the range of the mask. */
5496         for (i = 0; i < sizeof(eth_m->dst); ++i)
5497                 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
5498         if (eth_v->type) {
5499                 /* When ethertype is present set mask for tagged VLAN. */
5500                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5501                 /* Set value for tagged VLAN if ethertype is 802.1Q. */
5502                 if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_VLAN) ||
5503                     eth_v->type == RTE_BE16(RTE_ETHER_TYPE_QINQ)) {
5504                         MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag,
5505                                  1);
5506                         /* Return here to avoid setting match on ethertype. */
5507                         return;
5508                 }
5509         }
5510         /*
5511          * HW supports match on one Ethertype, the Ethertype following the last
5512          * VLAN tag of the packet (see PRM).
5513          * Set match on ethertype only if ETH header is not followed by VLAN.
5514          */
5515         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
5516                  rte_be_to_cpu_16(eth_m->type));
5517         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, ethertype);
5518         *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
5519 }
5520
5521 /**
5522  * Add VLAN item to matcher and to the value.
5523  *
5524  * @param[in, out] dev_flow
5525  *   Flow descriptor.
5526  * @param[in, out] matcher
5527  *   Flow matcher.
5528  * @param[in, out] key
5529  *   Flow matcher value.
5530  * @param[in] item
5531  *   Flow pattern to translate.
5532  * @param[in] inner
5533  *   Item is inner pattern.
5534  */
5535 static void
5536 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
5537                             void *matcher, void *key,
5538                             const struct rte_flow_item *item,
5539                             int inner)
5540 {
5541         const struct rte_flow_item_vlan *vlan_m = item->mask;
5542         const struct rte_flow_item_vlan *vlan_v = item->spec;
5543         void *headers_m;
5544         void *headers_v;
5545         uint16_t tci_m;
5546         uint16_t tci_v;
5547
5548         if (!vlan_v)
5549                 return;
5550         if (!vlan_m)
5551                 vlan_m = &rte_flow_item_vlan_mask;
5552         if (inner) {
5553                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5554                                          inner_headers);
5555                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5556         } else {
5557                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5558                                          outer_headers);
5559                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5560                 /*
5561                  * This is workaround, masks are not supported,
5562                  * and pre-validated.
5563                  */
5564                 dev_flow->handle->vf_vlan.tag =
5565                         rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
5566         }
5567         tci_m = rte_be_to_cpu_16(vlan_m->tci);
5568         tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
5569         MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5570         MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
5571         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_vid, tci_m);
5572         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, tci_v);
5573         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_cfi, tci_m >> 12);
5574         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_cfi, tci_v >> 12);
5575         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_prio, tci_m >> 13);
5576         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, tci_v >> 13);
5577         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
5578                  rte_be_to_cpu_16(vlan_m->inner_type));
5579         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
5580                  rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
5581 }
5582
5583 /**
5584  * Add IPV4 item to matcher and to the value.
5585  *
5586  * @param[in, out] matcher
5587  *   Flow matcher.
5588  * @param[in, out] key
5589  *   Flow matcher value.
5590  * @param[in] item
5591  *   Flow pattern to translate.
5592  * @param[in] item_flags
5593  *   Bit-fields that holds the items detected until now.
5594  * @param[in] inner
5595  *   Item is inner pattern.
5596  * @param[in] group
5597  *   The group to insert the rule.
5598  */
5599 static void
5600 flow_dv_translate_item_ipv4(void *matcher, void *key,
5601                             const struct rte_flow_item *item,
5602                             const uint64_t item_flags,
5603                             int inner, uint32_t group)
5604 {
5605         const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
5606         const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
5607         const struct rte_flow_item_ipv4 nic_mask = {
5608                 .hdr = {
5609                         .src_addr = RTE_BE32(0xffffffff),
5610                         .dst_addr = RTE_BE32(0xffffffff),
5611                         .type_of_service = 0xff,
5612                         .next_proto_id = 0xff,
5613                         .time_to_live = 0xff,
5614                 },
5615         };
5616         void *headers_m;
5617         void *headers_v;
5618         char *l24_m;
5619         char *l24_v;
5620         uint8_t tos;
5621
5622         if (inner) {
5623                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5624                                          inner_headers);
5625                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5626         } else {
5627                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5628                                          outer_headers);
5629                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5630         }
5631         if (group == 0)
5632                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
5633         else
5634                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x4);
5635         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 4);
5636         /*
5637          * On outer header (which must contains L2), or inner header with L2,
5638          * set cvlan_tag mask bit to mark this packet as untagged.
5639          * This should be done even if item->spec is empty.
5640          */
5641         if (!inner || item_flags & MLX5_FLOW_LAYER_INNER_L2)
5642                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5643         if (!ipv4_v)
5644                 return;
5645         if (!ipv4_m)
5646                 ipv4_m = &nic_mask;
5647         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5648                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
5649         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5650                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
5651         *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
5652         *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
5653         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5654                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
5655         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5656                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
5657         *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
5658         *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
5659         tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
5660         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
5661                  ipv4_m->hdr.type_of_service);
5662         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
5663         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
5664                  ipv4_m->hdr.type_of_service >> 2);
5665         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
5666         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
5667                  ipv4_m->hdr.next_proto_id);
5668         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
5669                  ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
5670         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
5671                  ipv4_m->hdr.time_to_live);
5672         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
5673                  ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
5674 }
5675
5676 /**
5677  * Add IPV6 item to matcher and to the value.
5678  *
5679  * @param[in, out] matcher
5680  *   Flow matcher.
5681  * @param[in, out] key
5682  *   Flow matcher value.
5683  * @param[in] item
5684  *   Flow pattern to translate.
5685  * @param[in] item_flags
5686  *   Bit-fields that holds the items detected until now.
5687  * @param[in] inner
5688  *   Item is inner pattern.
5689  * @param[in] group
5690  *   The group to insert the rule.
5691  */
5692 static void
5693 flow_dv_translate_item_ipv6(void *matcher, void *key,
5694                             const struct rte_flow_item *item,
5695                             const uint64_t item_flags,
5696                             int inner, uint32_t group)
5697 {
5698         const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
5699         const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
5700         const struct rte_flow_item_ipv6 nic_mask = {
5701                 .hdr = {
5702                         .src_addr =
5703                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
5704                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
5705                         .dst_addr =
5706                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
5707                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
5708                         .vtc_flow = RTE_BE32(0xffffffff),
5709                         .proto = 0xff,
5710                         .hop_limits = 0xff,
5711                 },
5712         };
5713         void *headers_m;
5714         void *headers_v;
5715         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5716         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5717         char *l24_m;
5718         char *l24_v;
5719         uint32_t vtc_m;
5720         uint32_t vtc_v;
5721         int i;
5722         int size;
5723
5724         if (inner) {
5725                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5726                                          inner_headers);
5727                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5728         } else {
5729                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5730                                          outer_headers);
5731                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5732         }
5733         if (group == 0)
5734                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
5735         else
5736                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x6);
5737         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 6);
5738         /*
5739          * On outer header (which must contains L2), or inner header with L2,
5740          * set cvlan_tag mask bit to mark this packet as untagged.
5741          * This should be done even if item->spec is empty.
5742          */
5743         if (!inner || item_flags & MLX5_FLOW_LAYER_INNER_L2)
5744                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5745         if (!ipv6_v)
5746                 return;
5747         if (!ipv6_m)
5748                 ipv6_m = &nic_mask;
5749         size = sizeof(ipv6_m->hdr.dst_addr);
5750         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5751                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
5752         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5753                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
5754         memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
5755         for (i = 0; i < size; ++i)
5756                 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
5757         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5758                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
5759         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5760                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
5761         memcpy(l24_m, ipv6_m->hdr.src_addr, size);
5762         for (i = 0; i < size; ++i)
5763                 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
5764         /* TOS. */
5765         vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
5766         vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
5767         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
5768         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
5769         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
5770         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
5771         /* Label. */
5772         if (inner) {
5773                 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
5774                          vtc_m);
5775                 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
5776                          vtc_v);
5777         } else {
5778                 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
5779                          vtc_m);
5780                 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
5781                          vtc_v);
5782         }
5783         /* Protocol. */
5784         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
5785                  ipv6_m->hdr.proto);
5786         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
5787                  ipv6_v->hdr.proto & ipv6_m->hdr.proto);
5788         /* Hop limit. */
5789         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
5790                  ipv6_m->hdr.hop_limits);
5791         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
5792                  ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
5793 }
5794
5795 /**
5796  * Add TCP item to matcher and to the value.
5797  *
5798  * @param[in, out] matcher
5799  *   Flow matcher.
5800  * @param[in, out] key
5801  *   Flow matcher value.
5802  * @param[in] item
5803  *   Flow pattern to translate.
5804  * @param[in] inner
5805  *   Item is inner pattern.
5806  */
5807 static void
5808 flow_dv_translate_item_tcp(void *matcher, void *key,
5809                            const struct rte_flow_item *item,
5810                            int inner)
5811 {
5812         const struct rte_flow_item_tcp *tcp_m = item->mask;
5813         const struct rte_flow_item_tcp *tcp_v = item->spec;
5814         void *headers_m;
5815         void *headers_v;
5816
5817         if (inner) {
5818                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5819                                          inner_headers);
5820                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5821         } else {
5822                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5823                                          outer_headers);
5824                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5825         }
5826         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5827         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
5828         if (!tcp_v)
5829                 return;
5830         if (!tcp_m)
5831                 tcp_m = &rte_flow_item_tcp_mask;
5832         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
5833                  rte_be_to_cpu_16(tcp_m->hdr.src_port));
5834         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
5835                  rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
5836         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
5837                  rte_be_to_cpu_16(tcp_m->hdr.dst_port));
5838         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
5839                  rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
5840         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
5841                  tcp_m->hdr.tcp_flags);
5842         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
5843                  (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
5844 }
5845
5846 /**
5847  * Add UDP item to matcher and to the value.
5848  *
5849  * @param[in, out] matcher
5850  *   Flow matcher.
5851  * @param[in, out] key
5852  *   Flow matcher value.
5853  * @param[in] item
5854  *   Flow pattern to translate.
5855  * @param[in] inner
5856  *   Item is inner pattern.
5857  */
5858 static void
5859 flow_dv_translate_item_udp(void *matcher, void *key,
5860                            const struct rte_flow_item *item,
5861                            int inner)
5862 {
5863         const struct rte_flow_item_udp *udp_m = item->mask;
5864         const struct rte_flow_item_udp *udp_v = item->spec;
5865         void *headers_m;
5866         void *headers_v;
5867
5868         if (inner) {
5869                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5870                                          inner_headers);
5871                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5872         } else {
5873                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5874                                          outer_headers);
5875                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5876         }
5877         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5878         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
5879         if (!udp_v)
5880                 return;
5881         if (!udp_m)
5882                 udp_m = &rte_flow_item_udp_mask;
5883         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
5884                  rte_be_to_cpu_16(udp_m->hdr.src_port));
5885         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
5886                  rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
5887         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
5888                  rte_be_to_cpu_16(udp_m->hdr.dst_port));
5889         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
5890                  rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
5891 }
5892
5893 /**
5894  * Add GRE optional Key item to matcher and to the value.
5895  *
5896  * @param[in, out] matcher
5897  *   Flow matcher.
5898  * @param[in, out] key
5899  *   Flow matcher value.
5900  * @param[in] item
5901  *   Flow pattern to translate.
5902  * @param[in] inner
5903  *   Item is inner pattern.
5904  */
5905 static void
5906 flow_dv_translate_item_gre_key(void *matcher, void *key,
5907                                    const struct rte_flow_item *item)
5908 {
5909         const rte_be32_t *key_m = item->mask;
5910         const rte_be32_t *key_v = item->spec;
5911         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5912         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5913         rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
5914
5915         /* GRE K bit must be on and should already be validated */
5916         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
5917         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
5918         if (!key_v)
5919                 return;
5920         if (!key_m)
5921                 key_m = &gre_key_default_mask;
5922         MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
5923                  rte_be_to_cpu_32(*key_m) >> 8);
5924         MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
5925                  rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
5926         MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
5927                  rte_be_to_cpu_32(*key_m) & 0xFF);
5928         MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
5929                  rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
5930 }
5931
5932 /**
5933  * Add GRE item to matcher and to the value.
5934  *
5935  * @param[in, out] matcher
5936  *   Flow matcher.
5937  * @param[in, out] key
5938  *   Flow matcher value.
5939  * @param[in] item
5940  *   Flow pattern to translate.
5941  * @param[in] inner
5942  *   Item is inner pattern.
5943  */
5944 static void
5945 flow_dv_translate_item_gre(void *matcher, void *key,
5946                            const struct rte_flow_item *item,
5947                            int inner)
5948 {
5949         const struct rte_flow_item_gre *gre_m = item->mask;
5950         const struct rte_flow_item_gre *gre_v = item->spec;
5951         void *headers_m;
5952         void *headers_v;
5953         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5954         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5955         struct {
5956                 union {
5957                         __extension__
5958                         struct {
5959                                 uint16_t version:3;
5960                                 uint16_t rsvd0:9;
5961                                 uint16_t s_present:1;
5962                                 uint16_t k_present:1;
5963                                 uint16_t rsvd_bit1:1;
5964                                 uint16_t c_present:1;
5965                         };
5966                         uint16_t value;
5967                 };
5968         } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
5969
5970         if (inner) {
5971                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5972                                          inner_headers);
5973                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5974         } else {
5975                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5976                                          outer_headers);
5977                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5978         }
5979         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5980         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
5981         if (!gre_v)
5982                 return;
5983         if (!gre_m)
5984                 gre_m = &rte_flow_item_gre_mask;
5985         MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
5986                  rte_be_to_cpu_16(gre_m->protocol));
5987         MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
5988                  rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
5989         gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
5990         gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
5991         MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
5992                  gre_crks_rsvd0_ver_m.c_present);
5993         MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
5994                  gre_crks_rsvd0_ver_v.c_present &
5995                  gre_crks_rsvd0_ver_m.c_present);
5996         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
5997                  gre_crks_rsvd0_ver_m.k_present);
5998         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
5999                  gre_crks_rsvd0_ver_v.k_present &
6000                  gre_crks_rsvd0_ver_m.k_present);
6001         MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
6002                  gre_crks_rsvd0_ver_m.s_present);
6003         MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
6004                  gre_crks_rsvd0_ver_v.s_present &
6005                  gre_crks_rsvd0_ver_m.s_present);
6006 }
6007
6008 /**
6009  * Add NVGRE item to matcher and to the value.
6010  *
6011  * @param[in, out] matcher
6012  *   Flow matcher.
6013  * @param[in, out] key
6014  *   Flow matcher value.
6015  * @param[in] item
6016  *   Flow pattern to translate.
6017  * @param[in] inner
6018  *   Item is inner pattern.
6019  */
6020 static void
6021 flow_dv_translate_item_nvgre(void *matcher, void *key,
6022                              const struct rte_flow_item *item,
6023                              int inner)
6024 {
6025         const struct rte_flow_item_nvgre *nvgre_m = item->mask;
6026         const struct rte_flow_item_nvgre *nvgre_v = item->spec;
6027         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6028         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6029         const char *tni_flow_id_m = (const char *)nvgre_m->tni;
6030         const char *tni_flow_id_v = (const char *)nvgre_v->tni;
6031         char *gre_key_m;
6032         char *gre_key_v;
6033         int size;
6034         int i;
6035
6036         /* For NVGRE, GRE header fields must be set with defined values. */
6037         const struct rte_flow_item_gre gre_spec = {
6038                 .c_rsvd0_ver = RTE_BE16(0x2000),
6039                 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
6040         };
6041         const struct rte_flow_item_gre gre_mask = {
6042                 .c_rsvd0_ver = RTE_BE16(0xB000),
6043                 .protocol = RTE_BE16(UINT16_MAX),
6044         };
6045         const struct rte_flow_item gre_item = {
6046                 .spec = &gre_spec,
6047                 .mask = &gre_mask,
6048                 .last = NULL,
6049         };
6050         flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
6051         if (!nvgre_v)
6052                 return;
6053         if (!nvgre_m)
6054                 nvgre_m = &rte_flow_item_nvgre_mask;
6055         size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
6056         gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
6057         gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
6058         memcpy(gre_key_m, tni_flow_id_m, size);
6059         for (i = 0; i < size; ++i)
6060                 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
6061 }
6062
6063 /**
6064  * Add VXLAN item to matcher and to the value.
6065  *
6066  * @param[in, out] matcher
6067  *   Flow matcher.
6068  * @param[in, out] key
6069  *   Flow matcher value.
6070  * @param[in] item
6071  *   Flow pattern to translate.
6072  * @param[in] inner
6073  *   Item is inner pattern.
6074  */
6075 static void
6076 flow_dv_translate_item_vxlan(void *matcher, void *key,
6077                              const struct rte_flow_item *item,
6078                              int inner)
6079 {
6080         const struct rte_flow_item_vxlan *vxlan_m = item->mask;
6081         const struct rte_flow_item_vxlan *vxlan_v = item->spec;
6082         void *headers_m;
6083         void *headers_v;
6084         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6085         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6086         char *vni_m;
6087         char *vni_v;
6088         uint16_t dport;
6089         int size;
6090         int i;
6091
6092         if (inner) {
6093                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6094                                          inner_headers);
6095                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6096         } else {
6097                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6098                                          outer_headers);
6099                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6100         }
6101         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
6102                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
6103         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6104                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6105                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6106         }
6107         if (!vxlan_v)
6108                 return;
6109         if (!vxlan_m)
6110                 vxlan_m = &rte_flow_item_vxlan_mask;
6111         size = sizeof(vxlan_m->vni);
6112         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
6113         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
6114         memcpy(vni_m, vxlan_m->vni, size);
6115         for (i = 0; i < size; ++i)
6116                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
6117 }
6118
6119 /**
6120  * Add VXLAN-GPE item to matcher and to the value.
6121  *
6122  * @param[in, out] matcher
6123  *   Flow matcher.
6124  * @param[in, out] key
6125  *   Flow matcher value.
6126  * @param[in] item
6127  *   Flow pattern to translate.
6128  * @param[in] inner
6129  *   Item is inner pattern.
6130  */
6131
6132 static void
6133 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
6134                                  const struct rte_flow_item *item, int inner)
6135 {
6136         const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
6137         const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
6138         void *headers_m;
6139         void *headers_v;
6140         void *misc_m =
6141                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
6142         void *misc_v =
6143                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6144         char *vni_m;
6145         char *vni_v;
6146         uint16_t dport;
6147         int size;
6148         int i;
6149         uint8_t flags_m = 0xff;
6150         uint8_t flags_v = 0xc;
6151
6152         if (inner) {
6153                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6154                                          inner_headers);
6155                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6156         } else {
6157                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6158                                          outer_headers);
6159                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6160         }
6161         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
6162                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
6163         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6164                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6165                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6166         }
6167         if (!vxlan_v)
6168                 return;
6169         if (!vxlan_m)
6170                 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
6171         size = sizeof(vxlan_m->vni);
6172         vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
6173         vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
6174         memcpy(vni_m, vxlan_m->vni, size);
6175         for (i = 0; i < size; ++i)
6176                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
6177         if (vxlan_m->flags) {
6178                 flags_m = vxlan_m->flags;
6179                 flags_v = vxlan_v->flags;
6180         }
6181         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
6182         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
6183         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
6184                  vxlan_m->protocol);
6185         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
6186                  vxlan_v->protocol);
6187 }
6188
6189 /**
6190  * Add Geneve item to matcher and to the value.
6191  *
6192  * @param[in, out] matcher
6193  *   Flow matcher.
6194  * @param[in, out] key
6195  *   Flow matcher value.
6196  * @param[in] item
6197  *   Flow pattern to translate.
6198  * @param[in] inner
6199  *   Item is inner pattern.
6200  */
6201
6202 static void
6203 flow_dv_translate_item_geneve(void *matcher, void *key,
6204                               const struct rte_flow_item *item, int inner)
6205 {
6206         const struct rte_flow_item_geneve *geneve_m = item->mask;
6207         const struct rte_flow_item_geneve *geneve_v = item->spec;
6208         void *headers_m;
6209         void *headers_v;
6210         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6211         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6212         uint16_t dport;
6213         uint16_t gbhdr_m;
6214         uint16_t gbhdr_v;
6215         char *vni_m;
6216         char *vni_v;
6217         size_t size, i;
6218
6219         if (inner) {
6220                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6221                                          inner_headers);
6222                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6223         } else {
6224                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6225                                          outer_headers);
6226                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6227         }
6228         dport = MLX5_UDP_PORT_GENEVE;
6229         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6230                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6231                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6232         }
6233         if (!geneve_v)
6234                 return;
6235         if (!geneve_m)
6236                 geneve_m = &rte_flow_item_geneve_mask;
6237         size = sizeof(geneve_m->vni);
6238         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
6239         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
6240         memcpy(vni_m, geneve_m->vni, size);
6241         for (i = 0; i < size; ++i)
6242                 vni_v[i] = vni_m[i] & geneve_v->vni[i];
6243         MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
6244                  rte_be_to_cpu_16(geneve_m->protocol));
6245         MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
6246                  rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
6247         gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
6248         gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
6249         MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
6250                  MLX5_GENEVE_OAMF_VAL(gbhdr_m));
6251         MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
6252                  MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
6253         MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
6254                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
6255         MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
6256                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
6257                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
6258 }
6259
6260 /**
6261  * Add MPLS item to matcher and to the value.
6262  *
6263  * @param[in, out] matcher
6264  *   Flow matcher.
6265  * @param[in, out] key
6266  *   Flow matcher value.
6267  * @param[in] item
6268  *   Flow pattern to translate.
6269  * @param[in] prev_layer
6270  *   The protocol layer indicated in previous item.
6271  * @param[in] inner
6272  *   Item is inner pattern.
6273  */
6274 static void
6275 flow_dv_translate_item_mpls(void *matcher, void *key,
6276                             const struct rte_flow_item *item,
6277                             uint64_t prev_layer,
6278                             int inner)
6279 {
6280         const uint32_t *in_mpls_m = item->mask;
6281         const uint32_t *in_mpls_v = item->spec;
6282         uint32_t *out_mpls_m = 0;
6283         uint32_t *out_mpls_v = 0;
6284         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6285         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6286         void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
6287                                      misc_parameters_2);
6288         void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
6289         void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
6290         void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6291
6292         switch (prev_layer) {
6293         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
6294                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
6295                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
6296                          MLX5_UDP_PORT_MPLS);
6297                 break;
6298         case MLX5_FLOW_LAYER_GRE:
6299                 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
6300                 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
6301                          RTE_ETHER_TYPE_MPLS);
6302                 break;
6303         default:
6304                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6305                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6306                          IPPROTO_MPLS);
6307                 break;
6308         }
6309         if (!in_mpls_v)
6310                 return;
6311         if (!in_mpls_m)
6312                 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
6313         switch (prev_layer) {
6314         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
6315                 out_mpls_m =
6316                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
6317                                                  outer_first_mpls_over_udp);
6318                 out_mpls_v =
6319                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
6320                                                  outer_first_mpls_over_udp);
6321                 break;
6322         case MLX5_FLOW_LAYER_GRE:
6323                 out_mpls_m =
6324                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
6325                                                  outer_first_mpls_over_gre);
6326                 out_mpls_v =
6327                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
6328                                                  outer_first_mpls_over_gre);
6329                 break;
6330         default:
6331                 /* Inner MPLS not over GRE is not supported. */
6332                 if (!inner) {
6333                         out_mpls_m =
6334                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
6335                                                          misc2_m,
6336                                                          outer_first_mpls);
6337                         out_mpls_v =
6338                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
6339                                                          misc2_v,
6340                                                          outer_first_mpls);
6341                 }
6342                 break;
6343         }
6344         if (out_mpls_m && out_mpls_v) {
6345                 *out_mpls_m = *in_mpls_m;
6346                 *out_mpls_v = *in_mpls_v & *in_mpls_m;
6347         }
6348 }
6349
6350 /**
6351  * Add metadata register item to matcher
6352  *
6353  * @param[in, out] matcher
6354  *   Flow matcher.
6355  * @param[in, out] key
6356  *   Flow matcher value.
6357  * @param[in] reg_type
6358  *   Type of device metadata register
6359  * @param[in] value
6360  *   Register value
6361  * @param[in] mask
6362  *   Register mask
6363  */
6364 static void
6365 flow_dv_match_meta_reg(void *matcher, void *key,
6366                        enum modify_reg reg_type,
6367                        uint32_t data, uint32_t mask)
6368 {
6369         void *misc2_m =
6370                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
6371         void *misc2_v =
6372                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
6373         uint32_t temp;
6374
6375         data &= mask;
6376         switch (reg_type) {
6377         case REG_A:
6378                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
6379                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
6380                 break;
6381         case REG_B:
6382                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
6383                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
6384                 break;
6385         case REG_C_0:
6386                 /*
6387                  * The metadata register C0 field might be divided into
6388                  * source vport index and META item value, we should set
6389                  * this field according to specified mask, not as whole one.
6390                  */
6391                 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
6392                 temp |= mask;
6393                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
6394                 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
6395                 temp &= ~mask;
6396                 temp |= data;
6397                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
6398                 break;
6399         case REG_C_1:
6400                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
6401                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
6402                 break;
6403         case REG_C_2:
6404                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
6405                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
6406                 break;
6407         case REG_C_3:
6408                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
6409                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
6410                 break;
6411         case REG_C_4:
6412                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
6413                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
6414                 break;
6415         case REG_C_5:
6416                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
6417                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
6418                 break;
6419         case REG_C_6:
6420                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
6421                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
6422                 break;
6423         case REG_C_7:
6424                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
6425                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
6426                 break;
6427         default:
6428                 MLX5_ASSERT(false);
6429                 break;
6430         }
6431 }
6432
6433 /**
6434  * Add MARK item to matcher
6435  *
6436  * @param[in] dev
6437  *   The device to configure through.
6438  * @param[in, out] matcher
6439  *   Flow matcher.
6440  * @param[in, out] key
6441  *   Flow matcher value.
6442  * @param[in] item
6443  *   Flow pattern to translate.
6444  */
6445 static void
6446 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
6447                             void *matcher, void *key,
6448                             const struct rte_flow_item *item)
6449 {
6450         struct mlx5_priv *priv = dev->data->dev_private;
6451         const struct rte_flow_item_mark *mark;
6452         uint32_t value;
6453         uint32_t mask;
6454
6455         mark = item->mask ? (const void *)item->mask :
6456                             &rte_flow_item_mark_mask;
6457         mask = mark->id & priv->sh->dv_mark_mask;
6458         mark = (const void *)item->spec;
6459         MLX5_ASSERT(mark);
6460         value = mark->id & priv->sh->dv_mark_mask & mask;
6461         if (mask) {
6462                 enum modify_reg reg;
6463
6464                 /* Get the metadata register index for the mark. */
6465                 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
6466                 MLX5_ASSERT(reg > 0);
6467                 if (reg == REG_C_0) {
6468                         struct mlx5_priv *priv = dev->data->dev_private;
6469                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6470                         uint32_t shl_c0 = rte_bsf32(msk_c0);
6471
6472                         mask &= msk_c0;
6473                         mask <<= shl_c0;
6474                         value <<= shl_c0;
6475                 }
6476                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6477         }
6478 }
6479
6480 /**
6481  * Add META item to matcher
6482  *
6483  * @param[in] dev
6484  *   The devich to configure through.
6485  * @param[in, out] matcher
6486  *   Flow matcher.
6487  * @param[in, out] key
6488  *   Flow matcher value.
6489  * @param[in] attr
6490  *   Attributes of flow that includes this item.
6491  * @param[in] item
6492  *   Flow pattern to translate.
6493  */
6494 static void
6495 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
6496                             void *matcher, void *key,
6497                             const struct rte_flow_attr *attr,
6498                             const struct rte_flow_item *item)
6499 {
6500         const struct rte_flow_item_meta *meta_m;
6501         const struct rte_flow_item_meta *meta_v;
6502
6503         meta_m = (const void *)item->mask;
6504         if (!meta_m)
6505                 meta_m = &rte_flow_item_meta_mask;
6506         meta_v = (const void *)item->spec;
6507         if (meta_v) {
6508                 int reg;
6509                 uint32_t value = meta_v->data;
6510                 uint32_t mask = meta_m->data;
6511
6512                 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
6513                 if (reg < 0)
6514                         return;
6515                 /*
6516                  * In datapath code there is no endianness
6517                  * coversions for perfromance reasons, all
6518                  * pattern conversions are done in rte_flow.
6519                  */
6520                 value = rte_cpu_to_be_32(value);
6521                 mask = rte_cpu_to_be_32(mask);
6522                 if (reg == REG_C_0) {
6523                         struct mlx5_priv *priv = dev->data->dev_private;
6524                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6525                         uint32_t shl_c0 = rte_bsf32(msk_c0);
6526 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
6527                         uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
6528
6529                         value >>= shr_c0;
6530                         mask >>= shr_c0;
6531 #endif
6532                         value <<= shl_c0;
6533                         mask <<= shl_c0;
6534                         MLX5_ASSERT(msk_c0);
6535                         MLX5_ASSERT(!(~msk_c0 & mask));
6536                 }
6537                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6538         }
6539 }
6540
6541 /**
6542  * Add vport metadata Reg C0 item to matcher
6543  *
6544  * @param[in, out] matcher
6545  *   Flow matcher.
6546  * @param[in, out] key
6547  *   Flow matcher value.
6548  * @param[in] reg
6549  *   Flow pattern to translate.
6550  */
6551 static void
6552 flow_dv_translate_item_meta_vport(void *matcher, void *key,
6553                                   uint32_t value, uint32_t mask)
6554 {
6555         flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
6556 }
6557
6558 /**
6559  * Add tag item to matcher
6560  *
6561  * @param[in] dev
6562  *   The devich to configure through.
6563  * @param[in, out] matcher
6564  *   Flow matcher.
6565  * @param[in, out] key
6566  *   Flow matcher value.
6567  * @param[in] item
6568  *   Flow pattern to translate.
6569  */
6570 static void
6571 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
6572                                 void *matcher, void *key,
6573                                 const struct rte_flow_item *item)
6574 {
6575         const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
6576         const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
6577         uint32_t mask, value;
6578
6579         MLX5_ASSERT(tag_v);
6580         value = tag_v->data;
6581         mask = tag_m ? tag_m->data : UINT32_MAX;
6582         if (tag_v->id == REG_C_0) {
6583                 struct mlx5_priv *priv = dev->data->dev_private;
6584                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6585                 uint32_t shl_c0 = rte_bsf32(msk_c0);
6586
6587                 mask &= msk_c0;
6588                 mask <<= shl_c0;
6589                 value <<= shl_c0;
6590         }
6591         flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
6592 }
6593
6594 /**
6595  * Add TAG item to matcher
6596  *
6597  * @param[in] dev
6598  *   The devich to configure through.
6599  * @param[in, out] matcher
6600  *   Flow matcher.
6601  * @param[in, out] key
6602  *   Flow matcher value.
6603  * @param[in] item
6604  *   Flow pattern to translate.
6605  */
6606 static void
6607 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
6608                            void *matcher, void *key,
6609                            const struct rte_flow_item *item)
6610 {
6611         const struct rte_flow_item_tag *tag_v = item->spec;
6612         const struct rte_flow_item_tag *tag_m = item->mask;
6613         enum modify_reg reg;
6614
6615         MLX5_ASSERT(tag_v);
6616         tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
6617         /* Get the metadata register index for the tag. */
6618         reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
6619         MLX5_ASSERT(reg > 0);
6620         flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
6621 }
6622
6623 /**
6624  * Add source vport match to the specified matcher.
6625  *
6626  * @param[in, out] matcher
6627  *   Flow matcher.
6628  * @param[in, out] key
6629  *   Flow matcher value.
6630  * @param[in] port
6631  *   Source vport value to match
6632  * @param[in] mask
6633  *   Mask
6634  */
6635 static void
6636 flow_dv_translate_item_source_vport(void *matcher, void *key,
6637                                     int16_t port, uint16_t mask)
6638 {
6639         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6640         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6641
6642         MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
6643         MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
6644 }
6645
6646 /**
6647  * Translate port-id item to eswitch match on  port-id.
6648  *
6649  * @param[in] dev
6650  *   The devich to configure through.
6651  * @param[in, out] matcher
6652  *   Flow matcher.
6653  * @param[in, out] key
6654  *   Flow matcher value.
6655  * @param[in] item
6656  *   Flow pattern to translate.
6657  *
6658  * @return
6659  *   0 on success, a negative errno value otherwise.
6660  */
6661 static int
6662 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
6663                                void *key, const struct rte_flow_item *item)
6664 {
6665         const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
6666         const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
6667         struct mlx5_priv *priv;
6668         uint16_t mask, id;
6669
6670         mask = pid_m ? pid_m->id : 0xffff;
6671         id = pid_v ? pid_v->id : dev->data->port_id;
6672         priv = mlx5_port_to_eswitch_info(id, item == NULL);
6673         if (!priv)
6674                 return -rte_errno;
6675         /* Translate to vport field or to metadata, depending on mode. */
6676         if (priv->vport_meta_mask)
6677                 flow_dv_translate_item_meta_vport(matcher, key,
6678                                                   priv->vport_meta_tag,
6679                                                   priv->vport_meta_mask);
6680         else
6681                 flow_dv_translate_item_source_vport(matcher, key,
6682                                                     priv->vport_id, mask);
6683         return 0;
6684 }
6685
6686 /**
6687  * Add ICMP6 item to matcher and to the value.
6688  *
6689  * @param[in, out] matcher
6690  *   Flow matcher.
6691  * @param[in, out] key
6692  *   Flow matcher value.
6693  * @param[in] item
6694  *   Flow pattern to translate.
6695  * @param[in] inner
6696  *   Item is inner pattern.
6697  */
6698 static void
6699 flow_dv_translate_item_icmp6(void *matcher, void *key,
6700                               const struct rte_flow_item *item,
6701                               int inner)
6702 {
6703         const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
6704         const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
6705         void *headers_m;
6706         void *headers_v;
6707         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
6708                                      misc_parameters_3);
6709         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6710         if (inner) {
6711                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6712                                          inner_headers);
6713                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6714         } else {
6715                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6716                                          outer_headers);
6717                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6718         }
6719         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
6720         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
6721         if (!icmp6_v)
6722                 return;
6723         if (!icmp6_m)
6724                 icmp6_m = &rte_flow_item_icmp6_mask;
6725         /*
6726          * Force flow only to match the non-fragmented IPv6 ICMPv6 packets.
6727          * If only the protocol is specified, no need to match the frag.
6728          */
6729         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
6730         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
6731         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
6732         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
6733                  icmp6_v->type & icmp6_m->type);
6734         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
6735         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
6736                  icmp6_v->code & icmp6_m->code);
6737 }
6738
6739 /**
6740  * Add ICMP item to matcher and to the value.
6741  *
6742  * @param[in, out] matcher
6743  *   Flow matcher.
6744  * @param[in, out] key
6745  *   Flow matcher value.
6746  * @param[in] item
6747  *   Flow pattern to translate.
6748  * @param[in] inner
6749  *   Item is inner pattern.
6750  */
6751 static void
6752 flow_dv_translate_item_icmp(void *matcher, void *key,
6753                             const struct rte_flow_item *item,
6754                             int inner)
6755 {
6756         const struct rte_flow_item_icmp *icmp_m = item->mask;
6757         const struct rte_flow_item_icmp *icmp_v = item->spec;
6758         void *headers_m;
6759         void *headers_v;
6760         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
6761                                      misc_parameters_3);
6762         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6763         if (inner) {
6764                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6765                                          inner_headers);
6766                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6767         } else {
6768                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6769                                          outer_headers);
6770                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6771         }
6772         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
6773         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
6774         if (!icmp_v)
6775                 return;
6776         if (!icmp_m)
6777                 icmp_m = &rte_flow_item_icmp_mask;
6778         /*
6779          * Force flow only to match the non-fragmented IPv4 ICMP packets.
6780          * If only the protocol is specified, no need to match the frag.
6781          */
6782         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
6783         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
6784         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
6785                  icmp_m->hdr.icmp_type);
6786         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
6787                  icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
6788         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
6789                  icmp_m->hdr.icmp_code);
6790         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
6791                  icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
6792 }
6793
6794 /**
6795  * Add GTP item to matcher and to the value.
6796  *
6797  * @param[in, out] matcher
6798  *   Flow matcher.
6799  * @param[in, out] key
6800  *   Flow matcher value.
6801  * @param[in] item
6802  *   Flow pattern to translate.
6803  * @param[in] inner
6804  *   Item is inner pattern.
6805  */
6806 static void
6807 flow_dv_translate_item_gtp(void *matcher, void *key,
6808                            const struct rte_flow_item *item, int inner)
6809 {
6810         const struct rte_flow_item_gtp *gtp_m = item->mask;
6811         const struct rte_flow_item_gtp *gtp_v = item->spec;
6812         void *headers_m;
6813         void *headers_v;
6814         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
6815                                      misc_parameters_3);
6816         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6817         uint16_t dport = RTE_GTPU_UDP_PORT;
6818
6819         if (inner) {
6820                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6821                                          inner_headers);
6822                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6823         } else {
6824                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6825                                          outer_headers);
6826                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6827         }
6828         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6829                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6830                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6831         }
6832         if (!gtp_v)
6833                 return;
6834         if (!gtp_m)
6835                 gtp_m = &rte_flow_item_gtp_mask;
6836         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
6837         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
6838                  gtp_v->msg_type & gtp_m->msg_type);
6839         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
6840                  rte_be_to_cpu_32(gtp_m->teid));
6841         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
6842                  rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
6843 }
6844
6845 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
6846
6847 #define HEADER_IS_ZERO(match_criteria, headers)                              \
6848         !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers),     \
6849                  matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
6850
6851 /**
6852  * Calculate flow matcher enable bitmap.
6853  *
6854  * @param match_criteria
6855  *   Pointer to flow matcher criteria.
6856  *
6857  * @return
6858  *   Bitmap of enabled fields.
6859  */
6860 static uint8_t
6861 flow_dv_matcher_enable(uint32_t *match_criteria)
6862 {
6863         uint8_t match_criteria_enable;
6864
6865         match_criteria_enable =
6866                 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
6867                 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
6868         match_criteria_enable |=
6869                 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
6870                 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
6871         match_criteria_enable |=
6872                 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
6873                 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
6874         match_criteria_enable |=
6875                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
6876                 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
6877         match_criteria_enable |=
6878                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
6879                 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
6880         return match_criteria_enable;
6881 }
6882
6883
6884 /**
6885  * Get a flow table.
6886  *
6887  * @param[in, out] dev
6888  *   Pointer to rte_eth_dev structure.
6889  * @param[in] table_id
6890  *   Table id to use.
6891  * @param[in] egress
6892  *   Direction of the table.
6893  * @param[in] transfer
6894  *   E-Switch or NIC flow.
6895  * @param[out] error
6896  *   pointer to error structure.
6897  *
6898  * @return
6899  *   Returns tables resource based on the index, NULL in case of failed.
6900  */
6901 static struct mlx5_flow_tbl_resource *
6902 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
6903                          uint32_t table_id, uint8_t egress,
6904                          uint8_t transfer,
6905                          struct rte_flow_error *error)
6906 {
6907         struct mlx5_priv *priv = dev->data->dev_private;
6908         struct mlx5_ibv_shared *sh = priv->sh;
6909         struct mlx5_flow_tbl_resource *tbl;
6910         union mlx5_flow_tbl_key table_key = {
6911                 {
6912                         .table_id = table_id,
6913                         .reserved = 0,
6914                         .domain = !!transfer,
6915                         .direction = !!egress,
6916                 }
6917         };
6918         struct mlx5_hlist_entry *pos = mlx5_hlist_lookup(sh->flow_tbls,
6919                                                          table_key.v64);
6920         struct mlx5_flow_tbl_data_entry *tbl_data;
6921         int ret;
6922         void *domain;
6923
6924         if (pos) {
6925                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
6926                                         entry);
6927                 tbl = &tbl_data->tbl;
6928                 rte_atomic32_inc(&tbl->refcnt);
6929                 return tbl;
6930         }
6931         tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
6932         if (!tbl_data) {
6933                 rte_flow_error_set(error, ENOMEM,
6934                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6935                                    NULL,
6936                                    "cannot allocate flow table data entry");
6937                 return NULL;
6938         }
6939         tbl = &tbl_data->tbl;
6940         pos = &tbl_data->entry;
6941         if (transfer)
6942                 domain = sh->fdb_domain;
6943         else if (egress)
6944                 domain = sh->tx_domain;
6945         else
6946                 domain = sh->rx_domain;
6947         tbl->obj = mlx5_glue->dr_create_flow_tbl(domain, table_id);
6948         if (!tbl->obj) {
6949                 rte_flow_error_set(error, ENOMEM,
6950                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6951                                    NULL, "cannot create flow table object");
6952                 rte_free(tbl_data);
6953                 return NULL;
6954         }
6955         /*
6956          * No multi-threads now, but still better to initialize the reference
6957          * count before insert it into the hash list.
6958          */
6959         rte_atomic32_init(&tbl->refcnt);
6960         /* Jump action reference count is initialized here. */
6961         rte_atomic32_init(&tbl_data->jump.refcnt);
6962         pos->key = table_key.v64;
6963         ret = mlx5_hlist_insert(sh->flow_tbls, pos);
6964         if (ret < 0) {
6965                 rte_flow_error_set(error, -ret,
6966                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6967                                    "cannot insert flow table data entry");
6968                 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
6969                 rte_free(tbl_data);
6970         }
6971         rte_atomic32_inc(&tbl->refcnt);
6972         return tbl;
6973 }
6974
6975 /**
6976  * Release a flow table.
6977  *
6978  * @param[in] dev
6979  *   Pointer to rte_eth_dev structure.
6980  * @param[in] tbl
6981  *   Table resource to be released.
6982  *
6983  * @return
6984  *   Returns 0 if table was released, else return 1;
6985  */
6986 static int
6987 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
6988                              struct mlx5_flow_tbl_resource *tbl)
6989 {
6990         struct mlx5_priv *priv = dev->data->dev_private;
6991         struct mlx5_ibv_shared *sh = priv->sh;
6992         struct mlx5_flow_tbl_data_entry *tbl_data =
6993                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
6994
6995         if (!tbl)
6996                 return 0;
6997         if (rte_atomic32_dec_and_test(&tbl->refcnt)) {
6998                 struct mlx5_hlist_entry *pos = &tbl_data->entry;
6999
7000                 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
7001                 tbl->obj = NULL;
7002                 /* remove the entry from the hash list and free memory. */
7003                 mlx5_hlist_remove(sh->flow_tbls, pos);
7004                 rte_free(tbl_data);
7005                 return 0;
7006         }
7007         return 1;
7008 }
7009
7010 /**
7011  * Register the flow matcher.
7012  *
7013  * @param[in, out] dev
7014  *   Pointer to rte_eth_dev structure.
7015  * @param[in, out] matcher
7016  *   Pointer to flow matcher.
7017  * @param[in, out] key
7018  *   Pointer to flow table key.
7019  * @parm[in, out] dev_flow
7020  *   Pointer to the dev_flow.
7021  * @param[out] error
7022  *   pointer to error structure.
7023  *
7024  * @return
7025  *   0 on success otherwise -errno and errno is set.
7026  */
7027 static int
7028 flow_dv_matcher_register(struct rte_eth_dev *dev,
7029                          struct mlx5_flow_dv_matcher *matcher,
7030                          union mlx5_flow_tbl_key *key,
7031                          struct mlx5_flow *dev_flow,
7032                          struct rte_flow_error *error)
7033 {
7034         struct mlx5_priv *priv = dev->data->dev_private;
7035         struct mlx5_ibv_shared *sh = priv->sh;
7036         struct mlx5_flow_dv_matcher *cache_matcher;
7037         struct mlx5dv_flow_matcher_attr dv_attr = {
7038                 .type = IBV_FLOW_ATTR_NORMAL,
7039                 .match_mask = (void *)&matcher->mask,
7040         };
7041         struct mlx5_flow_tbl_resource *tbl;
7042         struct mlx5_flow_tbl_data_entry *tbl_data;
7043
7044         tbl = flow_dv_tbl_resource_get(dev, key->table_id, key->direction,
7045                                        key->domain, error);
7046         if (!tbl)
7047                 return -rte_errno;      /* No need to refill the error info */
7048         tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
7049         /* Lookup from cache. */
7050         LIST_FOREACH(cache_matcher, &tbl_data->matchers, next) {
7051                 if (matcher->crc == cache_matcher->crc &&
7052                     matcher->priority == cache_matcher->priority &&
7053                     !memcmp((const void *)matcher->mask.buf,
7054                             (const void *)cache_matcher->mask.buf,
7055                             cache_matcher->mask.size)) {
7056                         DRV_LOG(DEBUG,
7057                                 "%s group %u priority %hd use %s "
7058                                 "matcher %p: refcnt %d++",
7059                                 key->domain ? "FDB" : "NIC", key->table_id,
7060                                 cache_matcher->priority,
7061                                 key->direction ? "tx" : "rx",
7062                                 (void *)cache_matcher,
7063                                 rte_atomic32_read(&cache_matcher->refcnt));
7064                         rte_atomic32_inc(&cache_matcher->refcnt);
7065                         dev_flow->handle->dvh.matcher = cache_matcher;
7066                         /* old matcher should not make the table ref++. */
7067                         flow_dv_tbl_resource_release(dev, tbl);
7068                         return 0;
7069                 }
7070         }
7071         /* Register new matcher. */
7072         cache_matcher = rte_calloc(__func__, 1, sizeof(*cache_matcher), 0);
7073         if (!cache_matcher) {
7074                 flow_dv_tbl_resource_release(dev, tbl);
7075                 return rte_flow_error_set(error, ENOMEM,
7076                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7077                                           "cannot allocate matcher memory");
7078         }
7079         *cache_matcher = *matcher;
7080         dv_attr.match_criteria_enable =
7081                 flow_dv_matcher_enable(cache_matcher->mask.buf);
7082         dv_attr.priority = matcher->priority;
7083         if (key->direction)
7084                 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
7085         cache_matcher->matcher_object =
7086                 mlx5_glue->dv_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj);
7087         if (!cache_matcher->matcher_object) {
7088                 rte_free(cache_matcher);
7089 #ifdef HAVE_MLX5DV_DR
7090                 flow_dv_tbl_resource_release(dev, tbl);
7091 #endif
7092                 return rte_flow_error_set(error, ENOMEM,
7093                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7094                                           NULL, "cannot create matcher");
7095         }
7096         /* Save the table information */
7097         cache_matcher->tbl = tbl;
7098         rte_atomic32_init(&cache_matcher->refcnt);
7099         /* only matcher ref++, table ref++ already done above in get API. */
7100         rte_atomic32_inc(&cache_matcher->refcnt);
7101         LIST_INSERT_HEAD(&tbl_data->matchers, cache_matcher, next);
7102         dev_flow->handle->dvh.matcher = cache_matcher;
7103         DRV_LOG(DEBUG, "%s group %u priority %hd new %s matcher %p: refcnt %d",
7104                 key->domain ? "FDB" : "NIC", key->table_id,
7105                 cache_matcher->priority,
7106                 key->direction ? "tx" : "rx", (void *)cache_matcher,
7107                 rte_atomic32_read(&cache_matcher->refcnt));
7108         return 0;
7109 }
7110
7111 /**
7112  * Find existing tag resource or create and register a new one.
7113  *
7114  * @param dev[in, out]
7115  *   Pointer to rte_eth_dev structure.
7116  * @param[in, out] tag_be24
7117  *   Tag value in big endian then R-shift 8.
7118  * @parm[in, out] dev_flow
7119  *   Pointer to the dev_flow.
7120  * @param[out] error
7121  *   pointer to error structure.
7122  *
7123  * @return
7124  *   0 on success otherwise -errno and errno is set.
7125  */
7126 static int
7127 flow_dv_tag_resource_register
7128                         (struct rte_eth_dev *dev,
7129                          uint32_t tag_be24,
7130                          struct mlx5_flow *dev_flow,
7131                          struct rte_flow_error *error)
7132 {
7133         struct mlx5_priv *priv = dev->data->dev_private;
7134         struct mlx5_ibv_shared *sh = priv->sh;
7135         struct mlx5_flow_dv_tag_resource *cache_resource;
7136         struct mlx5_hlist_entry *entry;
7137
7138         /* Lookup a matching resource from cache. */
7139         entry = mlx5_hlist_lookup(sh->tag_table, (uint64_t)tag_be24);
7140         if (entry) {
7141                 cache_resource = container_of
7142                         (entry, struct mlx5_flow_dv_tag_resource, entry);
7143                 rte_atomic32_inc(&cache_resource->refcnt);
7144                 dev_flow->handle->dvh.tag_resource = cache_resource;
7145                 DRV_LOG(DEBUG, "cached tag resource %p: refcnt now %d++",
7146                         (void *)cache_resource,
7147                         rte_atomic32_read(&cache_resource->refcnt));
7148                 return 0;
7149         }
7150         /* Register new resource. */
7151         cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
7152         if (!cache_resource)
7153                 return rte_flow_error_set(error, ENOMEM,
7154                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7155                                           "cannot allocate resource memory");
7156         cache_resource->entry.key = (uint64_t)tag_be24;
7157         cache_resource->action = mlx5_glue->dv_create_flow_action_tag(tag_be24);
7158         if (!cache_resource->action) {
7159                 rte_free(cache_resource);
7160                 return rte_flow_error_set(error, ENOMEM,
7161                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7162                                           NULL, "cannot create action");
7163         }
7164         rte_atomic32_init(&cache_resource->refcnt);
7165         rte_atomic32_inc(&cache_resource->refcnt);
7166         if (mlx5_hlist_insert(sh->tag_table, &cache_resource->entry)) {
7167                 mlx5_glue->destroy_flow_action(cache_resource->action);
7168                 rte_free(cache_resource);
7169                 return rte_flow_error_set(error, EEXIST,
7170                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7171                                           NULL, "cannot insert tag");
7172         }
7173         dev_flow->handle->dvh.tag_resource = cache_resource;
7174         DRV_LOG(DEBUG, "new tag resource %p: refcnt now %d++",
7175                 (void *)cache_resource,
7176                 rte_atomic32_read(&cache_resource->refcnt));
7177         return 0;
7178 }
7179
7180 /**
7181  * Release the tag.
7182  *
7183  * @param dev
7184  *   Pointer to Ethernet device.
7185  * @param flow
7186  *   Pointer to mlx5_flow.
7187  *
7188  * @return
7189  *   1 while a reference on it exists, 0 when freed.
7190  */
7191 static int
7192 flow_dv_tag_release(struct rte_eth_dev *dev,
7193                     struct mlx5_flow_dv_tag_resource *tag)
7194 {
7195         struct mlx5_priv *priv = dev->data->dev_private;
7196         struct mlx5_ibv_shared *sh = priv->sh;
7197
7198         MLX5_ASSERT(tag);
7199         DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
7200                 dev->data->port_id, (void *)tag,
7201                 rte_atomic32_read(&tag->refcnt));
7202         if (rte_atomic32_dec_and_test(&tag->refcnt)) {
7203                 claim_zero(mlx5_glue->destroy_flow_action(tag->action));
7204                 mlx5_hlist_remove(sh->tag_table, &tag->entry);
7205                 DRV_LOG(DEBUG, "port %u tag %p: removed",
7206                         dev->data->port_id, (void *)tag);
7207                 rte_free(tag);
7208                 return 0;
7209         }
7210         return 1;
7211 }
7212
7213 /**
7214  * Translate port ID action to vport.
7215  *
7216  * @param[in] dev
7217  *   Pointer to rte_eth_dev structure.
7218  * @param[in] action
7219  *   Pointer to the port ID action.
7220  * @param[out] dst_port_id
7221  *   The target port ID.
7222  * @param[out] error
7223  *   Pointer to the error structure.
7224  *
7225  * @return
7226  *   0 on success, a negative errno value otherwise and rte_errno is set.
7227  */
7228 static int
7229 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
7230                                  const struct rte_flow_action *action,
7231                                  uint32_t *dst_port_id,
7232                                  struct rte_flow_error *error)
7233 {
7234         uint32_t port;
7235         struct mlx5_priv *priv;
7236         const struct rte_flow_action_port_id *conf =
7237                         (const struct rte_flow_action_port_id *)action->conf;
7238
7239         port = conf->original ? dev->data->port_id : conf->id;
7240         priv = mlx5_port_to_eswitch_info(port, false);
7241         if (!priv)
7242                 return rte_flow_error_set(error, -rte_errno,
7243                                           RTE_FLOW_ERROR_TYPE_ACTION,
7244                                           NULL,
7245                                           "No eswitch info was found for port");
7246 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
7247         /*
7248          * This parameter is transferred to
7249          * mlx5dv_dr_action_create_dest_ib_port().
7250          */
7251         *dst_port_id = priv->ibv_port;
7252 #else
7253         /*
7254          * Legacy mode, no LAG configurations is supported.
7255          * This parameter is transferred to
7256          * mlx5dv_dr_action_create_dest_vport().
7257          */
7258         *dst_port_id = priv->vport_id;
7259 #endif
7260         return 0;
7261 }
7262
7263 /**
7264  * Add Tx queue matcher
7265  *
7266  * @param[in] dev
7267  *   Pointer to the dev struct.
7268  * @param[in, out] matcher
7269  *   Flow matcher.
7270  * @param[in, out] key
7271  *   Flow matcher value.
7272  * @param[in] item
7273  *   Flow pattern to translate.
7274  * @param[in] inner
7275  *   Item is inner pattern.
7276  */
7277 static void
7278 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
7279                                 void *matcher, void *key,
7280                                 const struct rte_flow_item *item)
7281 {
7282         const struct mlx5_rte_flow_item_tx_queue *queue_m;
7283         const struct mlx5_rte_flow_item_tx_queue *queue_v;
7284         void *misc_m =
7285                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7286         void *misc_v =
7287                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7288         struct mlx5_txq_ctrl *txq;
7289         uint32_t queue;
7290
7291
7292         queue_m = (const void *)item->mask;
7293         if (!queue_m)
7294                 return;
7295         queue_v = (const void *)item->spec;
7296         if (!queue_v)
7297                 return;
7298         txq = mlx5_txq_get(dev, queue_v->queue);
7299         if (!txq)
7300                 return;
7301         queue = txq->obj->sq->id;
7302         MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
7303         MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
7304                  queue & queue_m->queue);
7305         mlx5_txq_release(dev, queue_v->queue);
7306 }
7307
7308 /**
7309  * Set the hash fields according to the @p flow information.
7310  *
7311  * @param[in] dev_flow
7312  *   Pointer to the mlx5_flow.
7313  */
7314 static void
7315 flow_dv_hashfields_set(struct mlx5_flow *dev_flow)
7316 {
7317         struct rte_flow *flow = dev_flow->flow;
7318         uint64_t items = dev_flow->handle->layers;
7319         int rss_inner = 0;
7320         uint64_t rss_types = rte_eth_rss_hf_refine(flow->rss.types);
7321
7322         dev_flow->hash_fields = 0;
7323 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
7324         if (flow->rss.level >= 2) {
7325                 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
7326                 rss_inner = 1;
7327         }
7328 #endif
7329         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
7330             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
7331                 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
7332                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
7333                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
7334                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
7335                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
7336                         else
7337                                 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
7338                 }
7339         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
7340                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
7341                 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
7342                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
7343                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
7344                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
7345                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
7346                         else
7347                                 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
7348                 }
7349         }
7350         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
7351             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
7352                 if (rss_types & ETH_RSS_UDP) {
7353                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
7354                                 dev_flow->hash_fields |=
7355                                                 IBV_RX_HASH_SRC_PORT_UDP;
7356                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
7357                                 dev_flow->hash_fields |=
7358                                                 IBV_RX_HASH_DST_PORT_UDP;
7359                         else
7360                                 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
7361                 }
7362         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
7363                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
7364                 if (rss_types & ETH_RSS_TCP) {
7365                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
7366                                 dev_flow->hash_fields |=
7367                                                 IBV_RX_HASH_SRC_PORT_TCP;
7368                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
7369                                 dev_flow->hash_fields |=
7370                                                 IBV_RX_HASH_DST_PORT_TCP;
7371                         else
7372                                 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
7373                 }
7374         }
7375 }
7376
7377 /**
7378  * Fill the flow with DV spec, lock free
7379  * (mutex should be acquired by caller).
7380  *
7381  * @param[in] dev
7382  *   Pointer to rte_eth_dev structure.
7383  * @param[in, out] dev_flow
7384  *   Pointer to the sub flow.
7385  * @param[in] attr
7386  *   Pointer to the flow attributes.
7387  * @param[in] items
7388  *   Pointer to the list of items.
7389  * @param[in] actions
7390  *   Pointer to the list of actions.
7391  * @param[out] error
7392  *   Pointer to the error structure.
7393  *
7394  * @return
7395  *   0 on success, a negative errno value otherwise and rte_errno is set.
7396  */
7397 static int
7398 __flow_dv_translate(struct rte_eth_dev *dev,
7399                     struct mlx5_flow *dev_flow,
7400                     const struct rte_flow_attr *attr,
7401                     const struct rte_flow_item items[],
7402                     const struct rte_flow_action actions[],
7403                     struct rte_flow_error *error)
7404 {
7405         struct mlx5_priv *priv = dev->data->dev_private;
7406         struct mlx5_dev_config *dev_conf = &priv->config;
7407         struct rte_flow *flow = dev_flow->flow;
7408         struct mlx5_flow_handle *handle = dev_flow->handle;
7409         uint64_t item_flags = 0;
7410         uint64_t last_item = 0;
7411         uint64_t action_flags = 0;
7412         uint64_t priority = attr->priority;
7413         struct mlx5_flow_dv_matcher matcher = {
7414                 .mask = {
7415                         .size = sizeof(matcher.mask.buf),
7416                 },
7417         };
7418         int actions_n = 0;
7419         bool actions_end = false;
7420         union {
7421                 struct mlx5_flow_dv_modify_hdr_resource res;
7422                 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
7423                             sizeof(struct mlx5_modification_cmd) *
7424                             (MLX5_MAX_MODIFY_NUM + 1)];
7425         } mhdr_dummy;
7426         struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
7427         union flow_dv_attr flow_attr = { .attr = 0 };
7428         uint32_t tag_be;
7429         union mlx5_flow_tbl_key tbl_key;
7430         uint32_t modify_action_position = UINT32_MAX;
7431         void *match_mask = matcher.mask.buf;
7432         void *match_value = dev_flow->dv.value.buf;
7433         uint8_t next_protocol = 0xff;
7434         struct rte_vlan_hdr vlan = { 0 };
7435         uint32_t table;
7436         int ret = 0;
7437
7438         mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
7439                                            MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
7440         ret = mlx5_flow_group_to_table(attr, dev_flow->external, attr->group,
7441                                        !!priv->fdb_def_rule, &table, error);
7442         if (ret)
7443                 return ret;
7444         dev_flow->dv.group = table;
7445         if (attr->transfer)
7446                 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
7447         if (priority == MLX5_FLOW_PRIO_RSVD)
7448                 priority = dev_conf->flow_prio - 1;
7449         /* number of actions must be set to 0 in case of dirty stack. */
7450         mhdr_res->actions_num = 0;
7451         for (; !actions_end ; actions++) {
7452                 const struct rte_flow_action_queue *queue;
7453                 const struct rte_flow_action_rss *rss;
7454                 const struct rte_flow_action *action = actions;
7455                 const struct rte_flow_action_count *count = action->conf;
7456                 const uint8_t *rss_key;
7457                 const struct rte_flow_action_jump *jump_data;
7458                 const struct rte_flow_action_meter *mtr;
7459                 struct mlx5_flow_tbl_resource *tbl;
7460                 uint32_t port_id = 0;
7461                 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
7462                 int action_type = actions->type;
7463                 const struct rte_flow_action *found_action = NULL;
7464
7465                 switch (action_type) {
7466                 case RTE_FLOW_ACTION_TYPE_VOID:
7467                         break;
7468                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
7469                         if (flow_dv_translate_action_port_id(dev, action,
7470                                                              &port_id, error))
7471                                 return -rte_errno;
7472                         port_id_resource.port_id = port_id;
7473                         if (flow_dv_port_id_action_resource_register
7474                             (dev, &port_id_resource, dev_flow, error))
7475                                 return -rte_errno;
7476                         dev_flow->dv.actions[actions_n++] =
7477                                         handle->dvh.port_id_action->action;
7478                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
7479                         break;
7480                 case RTE_FLOW_ACTION_TYPE_FLAG:
7481                         action_flags |= MLX5_FLOW_ACTION_FLAG;
7482                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7483                                 struct rte_flow_action_mark mark = {
7484                                         .id = MLX5_FLOW_MARK_DEFAULT,
7485                                 };
7486
7487                                 if (flow_dv_convert_action_mark(dev, &mark,
7488                                                                 mhdr_res,
7489                                                                 error))
7490                                         return -rte_errno;
7491                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
7492                                 break;
7493                         }
7494                         tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
7495                         /*
7496                          * Only one FLAG or MARK is supported per device flow
7497                          * right now. So the pointer to the tag resource must be
7498                          * zero before the register process.
7499                          */
7500                         MLX5_ASSERT(!handle->dvh.tag_resource);
7501                         if (flow_dv_tag_resource_register(dev, tag_be,
7502                                                           dev_flow, error))
7503                                 return -rte_errno;
7504                         dev_flow->dv.actions[actions_n++] =
7505                                         handle->dvh.tag_resource->action;
7506                         break;
7507                 case RTE_FLOW_ACTION_TYPE_MARK:
7508                         action_flags |= MLX5_FLOW_ACTION_MARK;
7509                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7510                                 const struct rte_flow_action_mark *mark =
7511                                         (const struct rte_flow_action_mark *)
7512                                                 actions->conf;
7513
7514                                 if (flow_dv_convert_action_mark(dev, mark,
7515                                                                 mhdr_res,
7516                                                                 error))
7517                                         return -rte_errno;
7518                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
7519                                 break;
7520                         }
7521                         /* Fall-through */
7522                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
7523                         /* Legacy (non-extensive) MARK action. */
7524                         tag_be = mlx5_flow_mark_set
7525                               (((const struct rte_flow_action_mark *)
7526                                (actions->conf))->id);
7527                         MLX5_ASSERT(!handle->dvh.tag_resource);
7528                         if (flow_dv_tag_resource_register(dev, tag_be,
7529                                                           dev_flow, error))
7530                                 return -rte_errno;
7531                         dev_flow->dv.actions[actions_n++] =
7532                                         handle->dvh.tag_resource->action;
7533                         break;
7534                 case RTE_FLOW_ACTION_TYPE_SET_META:
7535                         if (flow_dv_convert_action_set_meta
7536                                 (dev, mhdr_res, attr,
7537                                  (const struct rte_flow_action_set_meta *)
7538                                   actions->conf, error))
7539                                 return -rte_errno;
7540                         action_flags |= MLX5_FLOW_ACTION_SET_META;
7541                         break;
7542                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
7543                         if (flow_dv_convert_action_set_tag
7544                                 (dev, mhdr_res,
7545                                  (const struct rte_flow_action_set_tag *)
7546                                   actions->conf, error))
7547                                 return -rte_errno;
7548                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7549                         break;
7550                 case RTE_FLOW_ACTION_TYPE_DROP:
7551                         action_flags |= MLX5_FLOW_ACTION_DROP;
7552                         break;
7553                 case RTE_FLOW_ACTION_TYPE_QUEUE:
7554                         MLX5_ASSERT(flow->rss.queue);
7555                         queue = actions->conf;
7556                         flow->rss.queue_num = 1;
7557                         (*flow->rss.queue)[0] = queue->index;
7558                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
7559                         break;
7560                 case RTE_FLOW_ACTION_TYPE_RSS:
7561                         MLX5_ASSERT(flow->rss.queue);
7562                         rss = actions->conf;
7563                         if (flow->rss.queue)
7564                                 memcpy((*flow->rss.queue), rss->queue,
7565                                        rss->queue_num * sizeof(uint16_t));
7566                         flow->rss.queue_num = rss->queue_num;
7567                         /* NULL RSS key indicates default RSS key. */
7568                         rss_key = !rss->key ? rss_hash_default_key : rss->key;
7569                         memcpy(flow->rss.key, rss_key, MLX5_RSS_HASH_KEY_LEN);
7570                         /*
7571                          * rss->level and rss.types should be set in advance
7572                          * when expanding items for RSS.
7573                          */
7574                         action_flags |= MLX5_FLOW_ACTION_RSS;
7575                         break;
7576                 case RTE_FLOW_ACTION_TYPE_COUNT:
7577                         if (!dev_conf->devx) {
7578                                 rte_errno = ENOTSUP;
7579                                 goto cnt_err;
7580                         }
7581                         flow->counter = flow_dv_counter_alloc(dev,
7582                                                         count->shared,
7583                                                         count->id,
7584                                                         dev_flow->dv.group);
7585                         if (!flow->counter)
7586                                 goto cnt_err;
7587                         dev_flow->dv.actions[actions_n++] =
7588                                   (flow_dv_counter_get_by_idx(dev,
7589                                   flow->counter, NULL))->action;
7590                         action_flags |= MLX5_FLOW_ACTION_COUNT;
7591                         break;
7592 cnt_err:
7593                         if (rte_errno == ENOTSUP)
7594                                 return rte_flow_error_set
7595                                               (error, ENOTSUP,
7596                                                RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7597                                                NULL,
7598                                                "count action not supported");
7599                         else
7600                                 return rte_flow_error_set
7601                                                 (error, rte_errno,
7602                                                  RTE_FLOW_ERROR_TYPE_ACTION,
7603                                                  action,
7604                                                  "cannot create counter"
7605                                                   " object.");
7606                         break;
7607                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
7608                         dev_flow->dv.actions[actions_n++] =
7609                                                 priv->sh->pop_vlan_action;
7610                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
7611                         break;
7612                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
7613                         flow_dev_get_vlan_info_from_items(items, &vlan);
7614                         vlan.eth_proto = rte_be_to_cpu_16
7615                              ((((const struct rte_flow_action_of_push_vlan *)
7616                                                    actions->conf)->ethertype));
7617                         found_action = mlx5_flow_find_action
7618                                         (actions + 1,
7619                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
7620                         if (found_action)
7621                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
7622                         found_action = mlx5_flow_find_action
7623                                         (actions + 1,
7624                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
7625                         if (found_action)
7626                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
7627                         if (flow_dv_create_action_push_vlan
7628                                             (dev, attr, &vlan, dev_flow, error))
7629                                 return -rte_errno;
7630                         dev_flow->dv.actions[actions_n++] =
7631                                         handle->dvh.push_vlan_res->action;
7632                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
7633                         break;
7634                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
7635                         /* of_vlan_push action handled this action */
7636                         MLX5_ASSERT(action_flags &
7637                                     MLX5_FLOW_ACTION_OF_PUSH_VLAN);
7638                         break;
7639                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
7640                         if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
7641                                 break;
7642                         flow_dev_get_vlan_info_from_items(items, &vlan);
7643                         mlx5_update_vlan_vid_pcp(actions, &vlan);
7644                         /* If no VLAN push - this is a modify header action */
7645                         if (flow_dv_convert_action_modify_vlan_vid
7646                                                 (mhdr_res, actions, error))
7647                                 return -rte_errno;
7648                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
7649                         break;
7650                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
7651                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
7652                         if (flow_dv_create_action_l2_encap(dev, actions,
7653                                                            dev_flow,
7654                                                            attr->transfer,
7655                                                            error))
7656                                 return -rte_errno;
7657                         dev_flow->dv.actions[actions_n++] =
7658                                         handle->dvh.encap_decap->verbs_action;
7659                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
7660                         break;
7661                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
7662                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
7663                         if (flow_dv_create_action_l2_decap(dev, dev_flow,
7664                                                            attr->transfer,
7665                                                            error))
7666                                 return -rte_errno;
7667                         dev_flow->dv.actions[actions_n++] =
7668                                         handle->dvh.encap_decap->verbs_action;
7669                         action_flags |= MLX5_FLOW_ACTION_DECAP;
7670                         break;
7671                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
7672                         /* Handle encap with preceding decap. */
7673                         if (action_flags & MLX5_FLOW_ACTION_DECAP) {
7674                                 if (flow_dv_create_action_raw_encap
7675                                         (dev, actions, dev_flow, attr, error))
7676                                         return -rte_errno;
7677                                 dev_flow->dv.actions[actions_n++] =
7678                                         handle->dvh.encap_decap->verbs_action;
7679                         } else {
7680                                 /* Handle encap without preceding decap. */
7681                                 if (flow_dv_create_action_l2_encap
7682                                     (dev, actions, dev_flow, attr->transfer,
7683                                      error))
7684                                         return -rte_errno;
7685                                 dev_flow->dv.actions[actions_n++] =
7686                                         handle->dvh.encap_decap->verbs_action;
7687                         }
7688                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
7689                         break;
7690                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
7691                         while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
7692                                 ;
7693                         if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
7694                                 if (flow_dv_create_action_l2_decap
7695                                     (dev, dev_flow, attr->transfer, error))
7696                                         return -rte_errno;
7697                                 dev_flow->dv.actions[actions_n++] =
7698                                         handle->dvh.encap_decap->verbs_action;
7699                         }
7700                         /* If decap is followed by encap, handle it at encap. */
7701                         action_flags |= MLX5_FLOW_ACTION_DECAP;
7702                         break;
7703                 case RTE_FLOW_ACTION_TYPE_JUMP:
7704                         jump_data = action->conf;
7705                         ret = mlx5_flow_group_to_table(attr, dev_flow->external,
7706                                                        jump_data->group,
7707                                                        !!priv->fdb_def_rule,
7708                                                        &table, error);
7709                         if (ret)
7710                                 return ret;
7711                         tbl = flow_dv_tbl_resource_get(dev, table,
7712                                                        attr->egress,
7713                                                        attr->transfer, error);
7714                         if (!tbl)
7715                                 return rte_flow_error_set
7716                                                 (error, errno,
7717                                                  RTE_FLOW_ERROR_TYPE_ACTION,
7718                                                  NULL,
7719                                                  "cannot create jump action.");
7720                         if (flow_dv_jump_tbl_resource_register
7721                             (dev, tbl, dev_flow, error)) {
7722                                 flow_dv_tbl_resource_release(dev, tbl);
7723                                 return rte_flow_error_set
7724                                                 (error, errno,
7725                                                  RTE_FLOW_ERROR_TYPE_ACTION,
7726                                                  NULL,
7727                                                  "cannot create jump action.");
7728                         }
7729                         dev_flow->dv.actions[actions_n++] =
7730                                         handle->dvh.jump->action;
7731                         action_flags |= MLX5_FLOW_ACTION_JUMP;
7732                         break;
7733                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
7734                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
7735                         if (flow_dv_convert_action_modify_mac
7736                                         (mhdr_res, actions, error))
7737                                 return -rte_errno;
7738                         action_flags |= actions->type ==
7739                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
7740                                         MLX5_FLOW_ACTION_SET_MAC_SRC :
7741                                         MLX5_FLOW_ACTION_SET_MAC_DST;
7742                         break;
7743                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
7744                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
7745                         if (flow_dv_convert_action_modify_ipv4
7746                                         (mhdr_res, actions, error))
7747                                 return -rte_errno;
7748                         action_flags |= actions->type ==
7749                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
7750                                         MLX5_FLOW_ACTION_SET_IPV4_SRC :
7751                                         MLX5_FLOW_ACTION_SET_IPV4_DST;
7752                         break;
7753                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
7754                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
7755                         if (flow_dv_convert_action_modify_ipv6
7756                                         (mhdr_res, actions, error))
7757                                 return -rte_errno;
7758                         action_flags |= actions->type ==
7759                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
7760                                         MLX5_FLOW_ACTION_SET_IPV6_SRC :
7761                                         MLX5_FLOW_ACTION_SET_IPV6_DST;
7762                         break;
7763                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
7764                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
7765                         if (flow_dv_convert_action_modify_tp
7766                                         (mhdr_res, actions, items,
7767                                          &flow_attr, dev_flow, !!(action_flags &
7768                                          MLX5_FLOW_ACTION_DECAP), error))
7769                                 return -rte_errno;
7770                         action_flags |= actions->type ==
7771                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
7772                                         MLX5_FLOW_ACTION_SET_TP_SRC :
7773                                         MLX5_FLOW_ACTION_SET_TP_DST;
7774                         break;
7775                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
7776                         if (flow_dv_convert_action_modify_dec_ttl
7777                                         (mhdr_res, items, &flow_attr, dev_flow,
7778                                          !!(action_flags &
7779                                          MLX5_FLOW_ACTION_DECAP), error))
7780                                 return -rte_errno;
7781                         action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
7782                         break;
7783                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
7784                         if (flow_dv_convert_action_modify_ttl
7785                                         (mhdr_res, actions, items, &flow_attr,
7786                                          dev_flow, !!(action_flags &
7787                                          MLX5_FLOW_ACTION_DECAP), error))
7788                                 return -rte_errno;
7789                         action_flags |= MLX5_FLOW_ACTION_SET_TTL;
7790                         break;
7791                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
7792                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
7793                         if (flow_dv_convert_action_modify_tcp_seq
7794                                         (mhdr_res, actions, error))
7795                                 return -rte_errno;
7796                         action_flags |= actions->type ==
7797                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
7798                                         MLX5_FLOW_ACTION_INC_TCP_SEQ :
7799                                         MLX5_FLOW_ACTION_DEC_TCP_SEQ;
7800                         break;
7801
7802                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
7803                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
7804                         if (flow_dv_convert_action_modify_tcp_ack
7805                                         (mhdr_res, actions, error))
7806                                 return -rte_errno;
7807                         action_flags |= actions->type ==
7808                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
7809                                         MLX5_FLOW_ACTION_INC_TCP_ACK :
7810                                         MLX5_FLOW_ACTION_DEC_TCP_ACK;
7811                         break;
7812                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
7813                         if (flow_dv_convert_action_set_reg
7814                                         (mhdr_res, actions, error))
7815                                 return -rte_errno;
7816                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7817                         break;
7818                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
7819                         if (flow_dv_convert_action_copy_mreg
7820                                         (dev, mhdr_res, actions, error))
7821                                 return -rte_errno;
7822                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7823                         break;
7824                 case RTE_FLOW_ACTION_TYPE_METER:
7825                         mtr = actions->conf;
7826                         if (!flow->meter) {
7827                                 flow->meter = mlx5_flow_meter_attach(priv,
7828                                                         mtr->mtr_id, attr,
7829                                                         error);
7830                                 if (!flow->meter)
7831                                         return rte_flow_error_set(error,
7832                                                 rte_errno,
7833                                                 RTE_FLOW_ERROR_TYPE_ACTION,
7834                                                 NULL,
7835                                                 "meter not found "
7836                                                 "or invalid parameters");
7837                         }
7838                         /* Set the meter action. */
7839                         dev_flow->dv.actions[actions_n++] =
7840                                 flow->meter->mfts->meter_action;
7841                         action_flags |= MLX5_FLOW_ACTION_METER;
7842                         break;
7843                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
7844                         if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
7845                                                               actions, error))
7846                                 return -rte_errno;
7847                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
7848                         break;
7849                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
7850                         if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
7851                                                               actions, error))
7852                                 return -rte_errno;
7853                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
7854                         break;
7855                 case RTE_FLOW_ACTION_TYPE_END:
7856                         actions_end = true;
7857                         if (mhdr_res->actions_num) {
7858                                 /* create modify action if needed. */
7859                                 if (flow_dv_modify_hdr_resource_register
7860                                         (dev, mhdr_res, dev_flow, error))
7861                                         return -rte_errno;
7862                                 dev_flow->dv.actions[modify_action_position] =
7863                                         handle->dvh.modify_hdr->verbs_action;
7864                         }
7865                         break;
7866                 default:
7867                         break;
7868                 }
7869                 if (mhdr_res->actions_num &&
7870                     modify_action_position == UINT32_MAX)
7871                         modify_action_position = actions_n++;
7872         }
7873         dev_flow->dv.actions_n = actions_n;
7874         handle->act_flags = action_flags;
7875         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
7876                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
7877                 int item_type = items->type;
7878
7879                 switch (item_type) {
7880                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
7881                         flow_dv_translate_item_port_id(dev, match_mask,
7882                                                        match_value, items);
7883                         last_item = MLX5_FLOW_ITEM_PORT_ID;
7884                         break;
7885                 case RTE_FLOW_ITEM_TYPE_ETH:
7886                         flow_dv_translate_item_eth(match_mask, match_value,
7887                                                    items, tunnel);
7888                         matcher.priority = MLX5_PRIORITY_MAP_L2;
7889                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
7890                                              MLX5_FLOW_LAYER_OUTER_L2;
7891                         break;
7892                 case RTE_FLOW_ITEM_TYPE_VLAN:
7893                         flow_dv_translate_item_vlan(dev_flow,
7894                                                     match_mask, match_value,
7895                                                     items, tunnel);
7896                         matcher.priority = MLX5_PRIORITY_MAP_L2;
7897                         last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
7898                                               MLX5_FLOW_LAYER_INNER_VLAN) :
7899                                              (MLX5_FLOW_LAYER_OUTER_L2 |
7900                                               MLX5_FLOW_LAYER_OUTER_VLAN);
7901                         break;
7902                 case RTE_FLOW_ITEM_TYPE_IPV4:
7903                         mlx5_flow_tunnel_ip_check(items, next_protocol,
7904                                                   &item_flags, &tunnel);
7905                         flow_dv_translate_item_ipv4(match_mask, match_value,
7906                                                     items, item_flags, tunnel,
7907                                                     dev_flow->dv.group);
7908                         matcher.priority = MLX5_PRIORITY_MAP_L3;
7909                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
7910                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
7911                         if (items->mask != NULL &&
7912                             ((const struct rte_flow_item_ipv4 *)
7913                              items->mask)->hdr.next_proto_id) {
7914                                 next_protocol =
7915                                         ((const struct rte_flow_item_ipv4 *)
7916                                          (items->spec))->hdr.next_proto_id;
7917                                 next_protocol &=
7918                                         ((const struct rte_flow_item_ipv4 *)
7919                                          (items->mask))->hdr.next_proto_id;
7920                         } else {
7921                                 /* Reset for inner layer. */
7922                                 next_protocol = 0xff;
7923                         }
7924                         break;
7925                 case RTE_FLOW_ITEM_TYPE_IPV6:
7926                         mlx5_flow_tunnel_ip_check(items, next_protocol,
7927                                                   &item_flags, &tunnel);
7928                         flow_dv_translate_item_ipv6(match_mask, match_value,
7929                                                     items, item_flags, tunnel,
7930                                                     dev_flow->dv.group);
7931                         matcher.priority = MLX5_PRIORITY_MAP_L3;
7932                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
7933                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
7934                         if (items->mask != NULL &&
7935                             ((const struct rte_flow_item_ipv6 *)
7936                              items->mask)->hdr.proto) {
7937                                 next_protocol =
7938                                         ((const struct rte_flow_item_ipv6 *)
7939                                          items->spec)->hdr.proto;
7940                                 next_protocol &=
7941                                         ((const struct rte_flow_item_ipv6 *)
7942                                          items->mask)->hdr.proto;
7943                         } else {
7944                                 /* Reset for inner layer. */
7945                                 next_protocol = 0xff;
7946                         }
7947                         break;
7948                 case RTE_FLOW_ITEM_TYPE_TCP:
7949                         flow_dv_translate_item_tcp(match_mask, match_value,
7950                                                    items, tunnel);
7951                         matcher.priority = MLX5_PRIORITY_MAP_L4;
7952                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
7953                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
7954                         break;
7955                 case RTE_FLOW_ITEM_TYPE_UDP:
7956                         flow_dv_translate_item_udp(match_mask, match_value,
7957                                                    items, tunnel);
7958                         matcher.priority = MLX5_PRIORITY_MAP_L4;
7959                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
7960                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
7961                         break;
7962                 case RTE_FLOW_ITEM_TYPE_GRE:
7963                         flow_dv_translate_item_gre(match_mask, match_value,
7964                                                    items, tunnel);
7965                         matcher.priority = flow->rss.level >= 2 ?
7966                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7967                         last_item = MLX5_FLOW_LAYER_GRE;
7968                         break;
7969                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
7970                         flow_dv_translate_item_gre_key(match_mask,
7971                                                        match_value, items);
7972                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
7973                         break;
7974                 case RTE_FLOW_ITEM_TYPE_NVGRE:
7975                         flow_dv_translate_item_nvgre(match_mask, match_value,
7976                                                      items, tunnel);
7977                         matcher.priority = flow->rss.level >= 2 ?
7978                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7979                         last_item = MLX5_FLOW_LAYER_GRE;
7980                         break;
7981                 case RTE_FLOW_ITEM_TYPE_VXLAN:
7982                         flow_dv_translate_item_vxlan(match_mask, match_value,
7983                                                      items, tunnel);
7984                         matcher.priority = flow->rss.level >= 2 ?
7985                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7986                         last_item = MLX5_FLOW_LAYER_VXLAN;
7987                         break;
7988                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
7989                         flow_dv_translate_item_vxlan_gpe(match_mask,
7990                                                          match_value, items,
7991                                                          tunnel);
7992                         matcher.priority = flow->rss.level >= 2 ?
7993                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7994                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
7995                         break;
7996                 case RTE_FLOW_ITEM_TYPE_GENEVE:
7997                         flow_dv_translate_item_geneve(match_mask, match_value,
7998                                                       items, tunnel);
7999                         matcher.priority = flow->rss.level >= 2 ?
8000                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8001                         last_item = MLX5_FLOW_LAYER_GENEVE;
8002                         break;
8003                 case RTE_FLOW_ITEM_TYPE_MPLS:
8004                         flow_dv_translate_item_mpls(match_mask, match_value,
8005                                                     items, last_item, tunnel);
8006                         matcher.priority = flow->rss.level >= 2 ?
8007                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8008                         last_item = MLX5_FLOW_LAYER_MPLS;
8009                         break;
8010                 case RTE_FLOW_ITEM_TYPE_MARK:
8011                         flow_dv_translate_item_mark(dev, match_mask,
8012                                                     match_value, items);
8013                         last_item = MLX5_FLOW_ITEM_MARK;
8014                         break;
8015                 case RTE_FLOW_ITEM_TYPE_META:
8016                         flow_dv_translate_item_meta(dev, match_mask,
8017                                                     match_value, attr, items);
8018                         last_item = MLX5_FLOW_ITEM_METADATA;
8019                         break;
8020                 case RTE_FLOW_ITEM_TYPE_ICMP:
8021                         flow_dv_translate_item_icmp(match_mask, match_value,
8022                                                     items, tunnel);
8023                         last_item = MLX5_FLOW_LAYER_ICMP;
8024                         break;
8025                 case RTE_FLOW_ITEM_TYPE_ICMP6:
8026                         flow_dv_translate_item_icmp6(match_mask, match_value,
8027                                                       items, tunnel);
8028                         last_item = MLX5_FLOW_LAYER_ICMP6;
8029                         break;
8030                 case RTE_FLOW_ITEM_TYPE_TAG:
8031                         flow_dv_translate_item_tag(dev, match_mask,
8032                                                    match_value, items);
8033                         last_item = MLX5_FLOW_ITEM_TAG;
8034                         break;
8035                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
8036                         flow_dv_translate_mlx5_item_tag(dev, match_mask,
8037                                                         match_value, items);
8038                         last_item = MLX5_FLOW_ITEM_TAG;
8039                         break;
8040                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
8041                         flow_dv_translate_item_tx_queue(dev, match_mask,
8042                                                         match_value,
8043                                                         items);
8044                         last_item = MLX5_FLOW_ITEM_TX_QUEUE;
8045                         break;
8046                 case RTE_FLOW_ITEM_TYPE_GTP:
8047                         flow_dv_translate_item_gtp(match_mask, match_value,
8048                                                    items, tunnel);
8049                         matcher.priority = flow->rss.level >= 2 ?
8050                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8051                         last_item = MLX5_FLOW_LAYER_GTP;
8052                         break;
8053                 default:
8054                         break;
8055                 }
8056                 item_flags |= last_item;
8057         }
8058         /*
8059          * When E-Switch mode is enabled, we have two cases where we need to
8060          * set the source port manually.
8061          * The first one, is in case of Nic steering rule, and the second is
8062          * E-Switch rule where no port_id item was found. In both cases
8063          * the source port is set according the current port in use.
8064          */
8065         if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
8066             (priv->representor || priv->master)) {
8067                 if (flow_dv_translate_item_port_id(dev, match_mask,
8068                                                    match_value, NULL))
8069                         return -rte_errno;
8070         }
8071 #ifdef RTE_LIBRTE_MLX5_DEBUG
8072         MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
8073                                               dev_flow->dv.value.buf));
8074 #endif
8075         /*
8076          * Layers may be already initialized from prefix flow if this dev_flow
8077          * is the suffix flow.
8078          */
8079         handle->layers |= item_flags;
8080         if (action_flags & MLX5_FLOW_ACTION_RSS)
8081                 flow_dv_hashfields_set(dev_flow);
8082         /* Register matcher. */
8083         matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
8084                                     matcher.mask.size);
8085         matcher.priority = mlx5_flow_adjust_priority(dev, priority,
8086                                                      matcher.priority);
8087         /* reserved field no needs to be set to 0 here. */
8088         tbl_key.domain = attr->transfer;
8089         tbl_key.direction = attr->egress;
8090         tbl_key.table_id = dev_flow->dv.group;
8091         if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow, error))
8092                 return -rte_errno;
8093         return 0;
8094 }
8095
8096 /**
8097  * Apply the flow to the NIC, lock free,
8098  * (mutex should be acquired by caller).
8099  *
8100  * @param[in] dev
8101  *   Pointer to the Ethernet device structure.
8102  * @param[in, out] flow
8103  *   Pointer to flow structure.
8104  * @param[out] error
8105  *   Pointer to error structure.
8106  *
8107  * @return
8108  *   0 on success, a negative errno value otherwise and rte_errno is set.
8109  */
8110 static int
8111 __flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
8112                 struct rte_flow_error *error)
8113 {
8114         struct mlx5_flow_dv_workspace *dv;
8115         struct mlx5_flow_handle *dh;
8116         struct mlx5_flow_handle_dv *dv_h;
8117         struct mlx5_flow *dev_flow;
8118         struct mlx5_priv *priv = dev->data->dev_private;
8119         int n;
8120         int err;
8121         int idx;
8122
8123         for (idx = priv->flow_idx - 1; idx >= 0; idx--) {
8124                 dev_flow = &((struct mlx5_flow *)priv->inter_flows)[idx];
8125                 dv = &dev_flow->dv;
8126                 dh = dev_flow->handle;
8127                 dv_h = &dh->dvh;
8128                 n = dv->actions_n;
8129                 if (dh->act_flags & MLX5_FLOW_ACTION_DROP) {
8130                         if (dv->transfer) {
8131                                 dv->actions[n++] = priv->sh->esw_drop_action;
8132                         } else {
8133                                 dh->hrxq = mlx5_hrxq_drop_new(dev);
8134                                 if (!dh->hrxq) {
8135                                         rte_flow_error_set
8136                                                 (error, errno,
8137                                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8138                                                  NULL,
8139                                                  "cannot get drop hash queue");
8140                                         goto error;
8141                                 }
8142                                 dv->actions[n++] = dh->hrxq->action;
8143                         }
8144                 } else if (dh->act_flags &
8145                            (MLX5_FLOW_ACTION_QUEUE | MLX5_FLOW_ACTION_RSS)) {
8146                         struct mlx5_hrxq *hrxq;
8147
8148                         MLX5_ASSERT(flow->rss.queue);
8149                         hrxq = mlx5_hrxq_get(dev, flow->rss.key,
8150                                              MLX5_RSS_HASH_KEY_LEN,
8151                                              dev_flow->hash_fields,
8152                                              (*flow->rss.queue),
8153                                              flow->rss.queue_num);
8154                         if (!hrxq) {
8155                                 hrxq = mlx5_hrxq_new
8156                                         (dev, flow->rss.key,
8157                                          MLX5_RSS_HASH_KEY_LEN,
8158                                          dev_flow->hash_fields,
8159                                          (*flow->rss.queue),
8160                                          flow->rss.queue_num,
8161                                          !!(dh->layers &
8162                                             MLX5_FLOW_LAYER_TUNNEL));
8163                         }
8164                         if (!hrxq) {
8165                                 rte_flow_error_set
8166                                         (error, rte_errno,
8167                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8168                                          "cannot get hash queue");
8169                                 goto error;
8170                         }
8171                         dh->hrxq = hrxq;
8172                         dv->actions[n++] = dh->hrxq->action;
8173                 }
8174                 dh->ib_flow =
8175                         mlx5_glue->dv_create_flow(dv_h->matcher->matcher_object,
8176                                                   (void *)&dv->value, n,
8177                                                   dv->actions);
8178                 if (!dh->ib_flow) {
8179                         rte_flow_error_set(error, errno,
8180                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8181                                            NULL,
8182                                            "hardware refuses to create flow");
8183                         goto error;
8184                 }
8185                 if (priv->vmwa_context &&
8186                     dh->vf_vlan.tag && !dh->vf_vlan.created) {
8187                         /*
8188                          * The rule contains the VLAN pattern.
8189                          * For VF we are going to create VLAN
8190                          * interface to make hypervisor set correct
8191                          * e-Switch vport context.
8192                          */
8193                         mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
8194                 }
8195         }
8196         return 0;
8197 error:
8198         err = rte_errno; /* Save rte_errno before cleanup. */
8199         LIST_FOREACH(dh, &flow->dev_handles, next) {
8200                 if (dh->hrxq) {
8201                         if (dh->act_flags & MLX5_FLOW_ACTION_DROP)
8202                                 mlx5_hrxq_drop_release(dev);
8203                         else
8204                                 mlx5_hrxq_release(dev, dh->hrxq);
8205                         dh->hrxq = NULL;
8206                 }
8207                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
8208                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
8209         }
8210         rte_errno = err; /* Restore rte_errno. */
8211         return -rte_errno;
8212 }
8213
8214 /**
8215  * Release the flow matcher.
8216  *
8217  * @param dev
8218  *   Pointer to Ethernet device.
8219  * @param handle
8220  *   Pointer to mlx5_flow_handle.
8221  *
8222  * @return
8223  *   1 while a reference on it exists, 0 when freed.
8224  */
8225 static int
8226 flow_dv_matcher_release(struct rte_eth_dev *dev,
8227                         struct mlx5_flow_handle *handle)
8228 {
8229         struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
8230
8231         MLX5_ASSERT(matcher->matcher_object);
8232         DRV_LOG(DEBUG, "port %u matcher %p: refcnt %d--",
8233                 dev->data->port_id, (void *)matcher,
8234                 rte_atomic32_read(&matcher->refcnt));
8235         if (rte_atomic32_dec_and_test(&matcher->refcnt)) {
8236                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8237                            (matcher->matcher_object));
8238                 LIST_REMOVE(matcher, next);
8239                 /* table ref-- in release interface. */
8240                 flow_dv_tbl_resource_release(dev, matcher->tbl);
8241                 rte_free(matcher);
8242                 DRV_LOG(DEBUG, "port %u matcher %p: removed",
8243                         dev->data->port_id, (void *)matcher);
8244                 return 0;
8245         }
8246         return 1;
8247 }
8248
8249 /**
8250  * Release an encap/decap resource.
8251  *
8252  * @param handle
8253  *   Pointer to mlx5_flow_handle.
8254  *
8255  * @return
8256  *   1 while a reference on it exists, 0 when freed.
8257  */
8258 static int
8259 flow_dv_encap_decap_resource_release(struct mlx5_flow_handle *handle)
8260 {
8261         struct mlx5_flow_dv_encap_decap_resource *cache_resource =
8262                                                 handle->dvh.encap_decap;
8263
8264         MLX5_ASSERT(cache_resource->verbs_action);
8265         DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d--",
8266                 (void *)cache_resource,
8267                 rte_atomic32_read(&cache_resource->refcnt));
8268         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8269                 claim_zero(mlx5_glue->destroy_flow_action
8270                                 (cache_resource->verbs_action));
8271                 LIST_REMOVE(cache_resource, next);
8272                 rte_free(cache_resource);
8273                 DRV_LOG(DEBUG, "encap/decap resource %p: removed",
8274                         (void *)cache_resource);
8275                 return 0;
8276         }
8277         return 1;
8278 }
8279
8280 /**
8281  * Release an jump to table action resource.
8282  *
8283  * @param dev
8284  *   Pointer to Ethernet device.
8285  * @param handle
8286  *   Pointer to mlx5_flow_handle.
8287  *
8288  * @return
8289  *   1 while a reference on it exists, 0 when freed.
8290  */
8291 static int
8292 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
8293                                   struct mlx5_flow_handle *handle)
8294 {
8295         struct mlx5_flow_dv_jump_tbl_resource *cache_resource =
8296                                                         handle->dvh.jump;
8297         struct mlx5_flow_tbl_data_entry *tbl_data =
8298                         container_of(cache_resource,
8299                                      struct mlx5_flow_tbl_data_entry, jump);
8300
8301         MLX5_ASSERT(cache_resource->action);
8302         DRV_LOG(DEBUG, "jump table resource %p: refcnt %d--",
8303                 (void *)cache_resource,
8304                 rte_atomic32_read(&cache_resource->refcnt));
8305         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8306                 claim_zero(mlx5_glue->destroy_flow_action
8307                                 (cache_resource->action));
8308                 /* jump action memory free is inside the table release. */
8309                 flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
8310                 DRV_LOG(DEBUG, "jump table resource %p: removed",
8311                         (void *)cache_resource);
8312                 return 0;
8313         }
8314         return 1;
8315 }
8316
8317 /**
8318  * Release a modify-header resource.
8319  *
8320  * @param handle
8321  *   Pointer to mlx5_flow_handle.
8322  *
8323  * @return
8324  *   1 while a reference on it exists, 0 when freed.
8325  */
8326 static int
8327 flow_dv_modify_hdr_resource_release(struct mlx5_flow_handle *handle)
8328 {
8329         struct mlx5_flow_dv_modify_hdr_resource *cache_resource =
8330                                                         handle->dvh.modify_hdr;
8331
8332         MLX5_ASSERT(cache_resource->verbs_action);
8333         DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d--",
8334                 (void *)cache_resource,
8335                 rte_atomic32_read(&cache_resource->refcnt));
8336         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8337                 claim_zero(mlx5_glue->destroy_flow_action
8338                                 (cache_resource->verbs_action));
8339                 LIST_REMOVE(cache_resource, next);
8340                 rte_free(cache_resource);
8341                 DRV_LOG(DEBUG, "modify-header resource %p: removed",
8342                         (void *)cache_resource);
8343                 return 0;
8344         }
8345         return 1;
8346 }
8347
8348 /**
8349  * Release port ID action resource.
8350  *
8351  * @param handle
8352  *   Pointer to mlx5_flow_handle.
8353  *
8354  * @return
8355  *   1 while a reference on it exists, 0 when freed.
8356  */
8357 static int
8358 flow_dv_port_id_action_resource_release(struct mlx5_flow_handle *handle)
8359 {
8360         struct mlx5_flow_dv_port_id_action_resource *cache_resource =
8361                                                 handle->dvh.port_id_action;
8362
8363         MLX5_ASSERT(cache_resource->action);
8364         DRV_LOG(DEBUG, "port ID action resource %p: refcnt %d--",
8365                 (void *)cache_resource,
8366                 rte_atomic32_read(&cache_resource->refcnt));
8367         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8368                 claim_zero(mlx5_glue->destroy_flow_action
8369                                 (cache_resource->action));
8370                 LIST_REMOVE(cache_resource, next);
8371                 rte_free(cache_resource);
8372                 DRV_LOG(DEBUG, "port id action resource %p: removed",
8373                         (void *)cache_resource);
8374                 return 0;
8375         }
8376         return 1;
8377 }
8378
8379 /**
8380  * Release push vlan action resource.
8381  *
8382  * @param handle
8383  *   Pointer to mlx5_flow_handle.
8384  *
8385  * @return
8386  *   1 while a reference on it exists, 0 when freed.
8387  */
8388 static int
8389 flow_dv_push_vlan_action_resource_release(struct mlx5_flow_handle *handle)
8390 {
8391         struct mlx5_flow_dv_push_vlan_action_resource *cache_resource =
8392                                                 handle->dvh.push_vlan_res;
8393
8394         MLX5_ASSERT(cache_resource->action);
8395         DRV_LOG(DEBUG, "push VLAN action resource %p: refcnt %d--",
8396                 (void *)cache_resource,
8397                 rte_atomic32_read(&cache_resource->refcnt));
8398         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8399                 claim_zero(mlx5_glue->destroy_flow_action
8400                                 (cache_resource->action));
8401                 LIST_REMOVE(cache_resource, next);
8402                 rte_free(cache_resource);
8403                 DRV_LOG(DEBUG, "push vlan action resource %p: removed",
8404                         (void *)cache_resource);
8405                 return 0;
8406         }
8407         return 1;
8408 }
8409
8410 /**
8411  * Remove the flow from the NIC but keeps it in memory.
8412  * Lock free, (mutex should be acquired by caller).
8413  *
8414  * @param[in] dev
8415  *   Pointer to Ethernet device.
8416  * @param[in, out] flow
8417  *   Pointer to flow structure.
8418  */
8419 static void
8420 __flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
8421 {
8422         struct mlx5_flow_handle *dh;
8423
8424         if (!flow)
8425                 return;
8426         LIST_FOREACH(dh, &flow->dev_handles, next) {
8427                 if (dh->ib_flow) {
8428                         claim_zero(mlx5_glue->dv_destroy_flow(dh->ib_flow));
8429                         dh->ib_flow = NULL;
8430                 }
8431                 if (dh->hrxq) {
8432                         if (dh->act_flags & MLX5_FLOW_ACTION_DROP)
8433                                 mlx5_hrxq_drop_release(dev);
8434                         else
8435                                 mlx5_hrxq_release(dev, dh->hrxq);
8436                         dh->hrxq = NULL;
8437                 }
8438                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
8439                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
8440         }
8441 }
8442
8443 /**
8444  * Remove the flow from the NIC and the memory.
8445  * Lock free, (mutex should be acquired by caller).
8446  *
8447  * @param[in] dev
8448  *   Pointer to the Ethernet device structure.
8449  * @param[in, out] flow
8450  *   Pointer to flow structure.
8451  */
8452 static void
8453 __flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
8454 {
8455         struct mlx5_flow_handle *dev_handle;
8456
8457         if (!flow)
8458                 return;
8459         __flow_dv_remove(dev, flow);
8460         if (flow->counter) {
8461                 flow_dv_counter_release(dev, flow->counter);
8462                 flow->counter = 0;
8463         }
8464         if (flow->meter) {
8465                 mlx5_flow_meter_detach(flow->meter);
8466                 flow->meter = NULL;
8467         }
8468         while (!LIST_EMPTY(&flow->dev_handles)) {
8469                 dev_handle = LIST_FIRST(&flow->dev_handles);
8470                 LIST_REMOVE(dev_handle, next);
8471                 if (dev_handle->dvh.matcher)
8472                         flow_dv_matcher_release(dev, dev_handle);
8473                 if (dev_handle->dvh.encap_decap)
8474                         flow_dv_encap_decap_resource_release(dev_handle);
8475                 if (dev_handle->dvh.modify_hdr)
8476                         flow_dv_modify_hdr_resource_release(dev_handle);
8477                 if (dev_handle->dvh.jump)
8478                         flow_dv_jump_tbl_resource_release(dev, dev_handle);
8479                 if (dev_handle->dvh.port_id_action)
8480                         flow_dv_port_id_action_resource_release(dev_handle);
8481                 if (dev_handle->dvh.push_vlan_res)
8482                         flow_dv_push_vlan_action_resource_release(dev_handle);
8483                 if (dev_handle->dvh.tag_resource)
8484                         flow_dv_tag_release(dev,
8485                                             dev_handle->dvh.tag_resource);
8486                 rte_free(dev_handle);
8487         }
8488 }
8489
8490 /**
8491  * Query a dv flow  rule for its statistics via devx.
8492  *
8493  * @param[in] dev
8494  *   Pointer to Ethernet device.
8495  * @param[in] flow
8496  *   Pointer to the sub flow.
8497  * @param[out] data
8498  *   data retrieved by the query.
8499  * @param[out] error
8500  *   Perform verbose error reporting if not NULL.
8501  *
8502  * @return
8503  *   0 on success, a negative errno value otherwise and rte_errno is set.
8504  */
8505 static int
8506 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
8507                     void *data, struct rte_flow_error *error)
8508 {
8509         struct mlx5_priv *priv = dev->data->dev_private;
8510         struct rte_flow_query_count *qc = data;
8511
8512         if (!priv->config.devx)
8513                 return rte_flow_error_set(error, ENOTSUP,
8514                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8515                                           NULL,
8516                                           "counters are not supported");
8517         if (flow->counter) {
8518                 uint64_t pkts, bytes;
8519                 struct mlx5_flow_counter *cnt;
8520
8521                 cnt = flow_dv_counter_get_by_idx(dev, flow->counter,
8522                                                  NULL);
8523                 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
8524                                                &bytes);
8525
8526                 if (err)
8527                         return rte_flow_error_set(error, -err,
8528                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8529                                         NULL, "cannot read counters");
8530                 qc->hits_set = 1;
8531                 qc->bytes_set = 1;
8532                 qc->hits = pkts - cnt->hits;
8533                 qc->bytes = bytes - cnt->bytes;
8534                 if (qc->reset) {
8535                         cnt->hits = pkts;
8536                         cnt->bytes = bytes;
8537                 }
8538                 return 0;
8539         }
8540         return rte_flow_error_set(error, EINVAL,
8541                                   RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8542                                   NULL,
8543                                   "counters are not available");
8544 }
8545
8546 /**
8547  * Query a flow.
8548  *
8549  * @see rte_flow_query()
8550  * @see rte_flow_ops
8551  */
8552 static int
8553 flow_dv_query(struct rte_eth_dev *dev,
8554               struct rte_flow *flow __rte_unused,
8555               const struct rte_flow_action *actions __rte_unused,
8556               void *data __rte_unused,
8557               struct rte_flow_error *error __rte_unused)
8558 {
8559         int ret = -EINVAL;
8560
8561         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
8562                 switch (actions->type) {
8563                 case RTE_FLOW_ACTION_TYPE_VOID:
8564                         break;
8565                 case RTE_FLOW_ACTION_TYPE_COUNT:
8566                         ret = flow_dv_query_count(dev, flow, data, error);
8567                         break;
8568                 default:
8569                         return rte_flow_error_set(error, ENOTSUP,
8570                                                   RTE_FLOW_ERROR_TYPE_ACTION,
8571                                                   actions,
8572                                                   "action not supported");
8573                 }
8574         }
8575         return ret;
8576 }
8577
8578 /**
8579  * Destroy the meter table set.
8580  * Lock free, (mutex should be acquired by caller).
8581  *
8582  * @param[in] dev
8583  *   Pointer to Ethernet device.
8584  * @param[in] tbl
8585  *   Pointer to the meter table set.
8586  *
8587  * @return
8588  *   Always 0.
8589  */
8590 static int
8591 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
8592                         struct mlx5_meter_domains_infos *tbl)
8593 {
8594         struct mlx5_priv *priv = dev->data->dev_private;
8595         struct mlx5_meter_domains_infos *mtd =
8596                                 (struct mlx5_meter_domains_infos *)tbl;
8597
8598         if (!mtd || !priv->config.dv_flow_en)
8599                 return 0;
8600         if (mtd->ingress.policer_rules[RTE_MTR_DROPPED])
8601                 claim_zero(mlx5_glue->dv_destroy_flow
8602                           (mtd->ingress.policer_rules[RTE_MTR_DROPPED]));
8603         if (mtd->egress.policer_rules[RTE_MTR_DROPPED])
8604                 claim_zero(mlx5_glue->dv_destroy_flow
8605                           (mtd->egress.policer_rules[RTE_MTR_DROPPED]));
8606         if (mtd->transfer.policer_rules[RTE_MTR_DROPPED])
8607                 claim_zero(mlx5_glue->dv_destroy_flow
8608                           (mtd->transfer.policer_rules[RTE_MTR_DROPPED]));
8609         if (mtd->egress.color_matcher)
8610                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8611                           (mtd->egress.color_matcher));
8612         if (mtd->egress.any_matcher)
8613                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8614                           (mtd->egress.any_matcher));
8615         if (mtd->egress.tbl)
8616                 claim_zero(flow_dv_tbl_resource_release(dev,
8617                                                         mtd->egress.tbl));
8618         if (mtd->ingress.color_matcher)
8619                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8620                           (mtd->ingress.color_matcher));
8621         if (mtd->ingress.any_matcher)
8622                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8623                           (mtd->ingress.any_matcher));
8624         if (mtd->ingress.tbl)
8625                 claim_zero(flow_dv_tbl_resource_release(dev,
8626                                                         mtd->ingress.tbl));
8627         if (mtd->transfer.color_matcher)
8628                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8629                           (mtd->transfer.color_matcher));
8630         if (mtd->transfer.any_matcher)
8631                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8632                           (mtd->transfer.any_matcher));
8633         if (mtd->transfer.tbl)
8634                 claim_zero(flow_dv_tbl_resource_release(dev,
8635                                                         mtd->transfer.tbl));
8636         if (mtd->drop_actn)
8637                 claim_zero(mlx5_glue->destroy_flow_action(mtd->drop_actn));
8638         rte_free(mtd);
8639         return 0;
8640 }
8641
8642 /* Number of meter flow actions, count and jump or count and drop. */
8643 #define METER_ACTIONS 2
8644
8645 /**
8646  * Create specify domain meter table and suffix table.
8647  *
8648  * @param[in] dev
8649  *   Pointer to Ethernet device.
8650  * @param[in,out] mtb
8651  *   Pointer to DV meter table set.
8652  * @param[in] egress
8653  *   Table attribute.
8654  * @param[in] transfer
8655  *   Table attribute.
8656  * @param[in] color_reg_c_idx
8657  *   Reg C index for color match.
8658  *
8659  * @return
8660  *   0 on success, -1 otherwise and rte_errno is set.
8661  */
8662 static int
8663 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
8664                            struct mlx5_meter_domains_infos *mtb,
8665                            uint8_t egress, uint8_t transfer,
8666                            uint32_t color_reg_c_idx)
8667 {
8668         struct mlx5_priv *priv = dev->data->dev_private;
8669         struct mlx5_ibv_shared *sh = priv->sh;
8670         struct mlx5_flow_dv_match_params mask = {
8671                 .size = sizeof(mask.buf),
8672         };
8673         struct mlx5_flow_dv_match_params value = {
8674                 .size = sizeof(value.buf),
8675         };
8676         struct mlx5dv_flow_matcher_attr dv_attr = {
8677                 .type = IBV_FLOW_ATTR_NORMAL,
8678                 .priority = 0,
8679                 .match_criteria_enable = 0,
8680                 .match_mask = (void *)&mask,
8681         };
8682         void *actions[METER_ACTIONS];
8683         struct mlx5_flow_tbl_resource **sfx_tbl;
8684         struct mlx5_meter_domain_info *dtb;
8685         struct rte_flow_error error;
8686         int i = 0;
8687
8688         if (transfer) {
8689                 sfx_tbl = &sh->fdb_mtr_sfx_tbl;
8690                 dtb = &mtb->transfer;
8691         } else if (egress) {
8692                 sfx_tbl = &sh->tx_mtr_sfx_tbl;
8693                 dtb = &mtb->egress;
8694         } else {
8695                 sfx_tbl = &sh->rx_mtr_sfx_tbl;
8696                 dtb = &mtb->ingress;
8697         }
8698         /* If the suffix table in missing, create it. */
8699         if (!(*sfx_tbl)) {
8700                 *sfx_tbl = flow_dv_tbl_resource_get(dev,
8701                                                 MLX5_FLOW_TABLE_LEVEL_SUFFIX,
8702                                                 egress, transfer, &error);
8703                 if (!(*sfx_tbl)) {
8704                         DRV_LOG(ERR, "Failed to create meter suffix table.");
8705                         return -1;
8706                 }
8707         }
8708         /* Create the meter table with METER level. */
8709         dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
8710                                             egress, transfer, &error);
8711         if (!dtb->tbl) {
8712                 DRV_LOG(ERR, "Failed to create meter policer table.");
8713                 return -1;
8714         }
8715         /* Create matchers, Any and Color. */
8716         dv_attr.priority = 3;
8717         dv_attr.match_criteria_enable = 0;
8718         dtb->any_matcher = mlx5_glue->dv_create_flow_matcher(sh->ctx,
8719                                                              &dv_attr,
8720                                                              dtb->tbl->obj);
8721         if (!dtb->any_matcher) {
8722                 DRV_LOG(ERR, "Failed to create meter"
8723                              " policer default matcher.");
8724                 goto error_exit;
8725         }
8726         dv_attr.priority = 0;
8727         dv_attr.match_criteria_enable =
8728                                 1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
8729         flow_dv_match_meta_reg(mask.buf, value.buf, color_reg_c_idx,
8730                                rte_col_2_mlx5_col(RTE_COLORS), UINT8_MAX);
8731         dtb->color_matcher = mlx5_glue->dv_create_flow_matcher(sh->ctx,
8732                                                                &dv_attr,
8733                                                                dtb->tbl->obj);
8734         if (!dtb->color_matcher) {
8735                 DRV_LOG(ERR, "Failed to create meter policer color matcher.");
8736                 goto error_exit;
8737         }
8738         if (mtb->count_actns[RTE_MTR_DROPPED])
8739                 actions[i++] = mtb->count_actns[RTE_MTR_DROPPED];
8740         actions[i++] = mtb->drop_actn;
8741         /* Default rule: lowest priority, match any, actions: drop. */
8742         dtb->policer_rules[RTE_MTR_DROPPED] =
8743                         mlx5_glue->dv_create_flow(dtb->any_matcher,
8744                                                  (void *)&value, i, actions);
8745         if (!dtb->policer_rules[RTE_MTR_DROPPED]) {
8746                 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
8747                 goto error_exit;
8748         }
8749         return 0;
8750 error_exit:
8751         return -1;
8752 }
8753
8754 /**
8755  * Create the needed meter and suffix tables.
8756  * Lock free, (mutex should be acquired by caller).
8757  *
8758  * @param[in] dev
8759  *   Pointer to Ethernet device.
8760  * @param[in] fm
8761  *   Pointer to the flow meter.
8762  *
8763  * @return
8764  *   Pointer to table set on success, NULL otherwise and rte_errno is set.
8765  */
8766 static struct mlx5_meter_domains_infos *
8767 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev,
8768                        const struct mlx5_flow_meter *fm)
8769 {
8770         struct mlx5_priv *priv = dev->data->dev_private;
8771         struct mlx5_meter_domains_infos *mtb;
8772         int ret;
8773         int i;
8774
8775         if (!priv->mtr_en) {
8776                 rte_errno = ENOTSUP;
8777                 return NULL;
8778         }
8779         mtb = rte_calloc(__func__, 1, sizeof(*mtb), 0);
8780         if (!mtb) {
8781                 DRV_LOG(ERR, "Failed to allocate memory for meter.");
8782                 return NULL;
8783         }
8784         /* Create meter count actions */
8785         for (i = 0; i <= RTE_MTR_DROPPED; i++) {
8786                 struct mlx5_flow_counter *cnt;
8787                 if (!fm->policer_stats.cnt[i])
8788                         continue;
8789                 cnt = flow_dv_counter_get_by_idx(dev,
8790                       fm->policer_stats.cnt[i], NULL);
8791                 mtb->count_actns[i] = cnt->action;
8792         }
8793         /* Create drop action. */
8794         mtb->drop_actn = mlx5_glue->dr_create_flow_action_drop();
8795         if (!mtb->drop_actn) {
8796                 DRV_LOG(ERR, "Failed to create drop action.");
8797                 goto error_exit;
8798         }
8799         /* Egress meter table. */
8800         ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0, priv->mtr_color_reg);
8801         if (ret) {
8802                 DRV_LOG(ERR, "Failed to prepare egress meter table.");
8803                 goto error_exit;
8804         }
8805         /* Ingress meter table. */
8806         ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0, priv->mtr_color_reg);
8807         if (ret) {
8808                 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
8809                 goto error_exit;
8810         }
8811         /* FDB meter table. */
8812         if (priv->config.dv_esw_en) {
8813                 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1,
8814                                                  priv->mtr_color_reg);
8815                 if (ret) {
8816                         DRV_LOG(ERR, "Failed to prepare fdb meter table.");
8817                         goto error_exit;
8818                 }
8819         }
8820         return mtb;
8821 error_exit:
8822         flow_dv_destroy_mtr_tbl(dev, mtb);
8823         return NULL;
8824 }
8825
8826 /**
8827  * Destroy domain policer rule.
8828  *
8829  * @param[in] dt
8830  *   Pointer to domain table.
8831  */
8832 static void
8833 flow_dv_destroy_domain_policer_rule(struct mlx5_meter_domain_info *dt)
8834 {
8835         int i;
8836
8837         for (i = 0; i < RTE_MTR_DROPPED; i++) {
8838                 if (dt->policer_rules[i]) {
8839                         claim_zero(mlx5_glue->dv_destroy_flow
8840                                   (dt->policer_rules[i]));
8841                         dt->policer_rules[i] = NULL;
8842                 }
8843         }
8844         if (dt->jump_actn) {
8845                 claim_zero(mlx5_glue->destroy_flow_action(dt->jump_actn));
8846                 dt->jump_actn = NULL;
8847         }
8848 }
8849
8850 /**
8851  * Destroy policer rules.
8852  *
8853  * @param[in] dev
8854  *   Pointer to Ethernet device.
8855  * @param[in] fm
8856  *   Pointer to flow meter structure.
8857  * @param[in] attr
8858  *   Pointer to flow attributes.
8859  *
8860  * @return
8861  *   Always 0.
8862  */
8863 static int
8864 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev __rte_unused,
8865                               const struct mlx5_flow_meter *fm,
8866                               const struct rte_flow_attr *attr)
8867 {
8868         struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
8869
8870         if (!mtb)
8871                 return 0;
8872         if (attr->egress)
8873                 flow_dv_destroy_domain_policer_rule(&mtb->egress);
8874         if (attr->ingress)
8875                 flow_dv_destroy_domain_policer_rule(&mtb->ingress);
8876         if (attr->transfer)
8877                 flow_dv_destroy_domain_policer_rule(&mtb->transfer);
8878         return 0;
8879 }
8880
8881 /**
8882  * Create specify domain meter policer rule.
8883  *
8884  * @param[in] fm
8885  *   Pointer to flow meter structure.
8886  * @param[in] mtb
8887  *   Pointer to DV meter table set.
8888  * @param[in] sfx_tb
8889  *   Pointer to suffix table.
8890  * @param[in] mtr_reg_c
8891  *   Color match REG_C.
8892  *
8893  * @return
8894  *   0 on success, -1 otherwise.
8895  */
8896 static int
8897 flow_dv_create_policer_forward_rule(struct mlx5_flow_meter *fm,
8898                                     struct mlx5_meter_domain_info *dtb,
8899                                     struct mlx5_flow_tbl_resource *sfx_tb,
8900                                     uint8_t mtr_reg_c)
8901 {
8902         struct mlx5_flow_dv_match_params matcher = {
8903                 .size = sizeof(matcher.buf),
8904         };
8905         struct mlx5_flow_dv_match_params value = {
8906                 .size = sizeof(value.buf),
8907         };
8908         struct mlx5_meter_domains_infos *mtb = fm->mfts;
8909         void *actions[METER_ACTIONS];
8910         int i;
8911
8912         /* Create jump action. */
8913         if (!sfx_tb)
8914                 return -1;
8915         if (!dtb->jump_actn)
8916                 dtb->jump_actn =
8917                         mlx5_glue->dr_create_flow_action_dest_flow_tbl
8918                                                         (sfx_tb->obj);
8919         if (!dtb->jump_actn) {
8920                 DRV_LOG(ERR, "Failed to create policer jump action.");
8921                 goto error;
8922         }
8923         for (i = 0; i < RTE_MTR_DROPPED; i++) {
8924                 int j = 0;
8925
8926                 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_reg_c,
8927                                        rte_col_2_mlx5_col(i), UINT8_MAX);
8928                 if (mtb->count_actns[i])
8929                         actions[j++] = mtb->count_actns[i];
8930                 if (fm->params.action[i] == MTR_POLICER_ACTION_DROP)
8931                         actions[j++] = mtb->drop_actn;
8932                 else
8933                         actions[j++] = dtb->jump_actn;
8934                 dtb->policer_rules[i] =
8935                         mlx5_glue->dv_create_flow(dtb->color_matcher,
8936                                                  (void *)&value,
8937                                                   j, actions);
8938                 if (!dtb->policer_rules[i]) {
8939                         DRV_LOG(ERR, "Failed to create policer rule.");
8940                         goto error;
8941                 }
8942         }
8943         return 0;
8944 error:
8945         rte_errno = errno;
8946         return -1;
8947 }
8948
8949 /**
8950  * Create policer rules.
8951  *
8952  * @param[in] dev
8953  *   Pointer to Ethernet device.
8954  * @param[in] fm
8955  *   Pointer to flow meter structure.
8956  * @param[in] attr
8957  *   Pointer to flow attributes.
8958  *
8959  * @return
8960  *   0 on success, -1 otherwise.
8961  */
8962 static int
8963 flow_dv_create_policer_rules(struct rte_eth_dev *dev,
8964                              struct mlx5_flow_meter *fm,
8965                              const struct rte_flow_attr *attr)
8966 {
8967         struct mlx5_priv *priv = dev->data->dev_private;
8968         struct mlx5_meter_domains_infos *mtb = fm->mfts;
8969         int ret;
8970
8971         if (attr->egress) {
8972                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->egress,
8973                                                 priv->sh->tx_mtr_sfx_tbl,
8974                                                 priv->mtr_color_reg);
8975                 if (ret) {
8976                         DRV_LOG(ERR, "Failed to create egress policer.");
8977                         goto error;
8978                 }
8979         }
8980         if (attr->ingress) {
8981                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->ingress,
8982                                                 priv->sh->rx_mtr_sfx_tbl,
8983                                                 priv->mtr_color_reg);
8984                 if (ret) {
8985                         DRV_LOG(ERR, "Failed to create ingress policer.");
8986                         goto error;
8987                 }
8988         }
8989         if (attr->transfer) {
8990                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->transfer,
8991                                                 priv->sh->fdb_mtr_sfx_tbl,
8992                                                 priv->mtr_color_reg);
8993                 if (ret) {
8994                         DRV_LOG(ERR, "Failed to create transfer policer.");
8995                         goto error;
8996                 }
8997         }
8998         return 0;
8999 error:
9000         flow_dv_destroy_policer_rules(dev, fm, attr);
9001         return -1;
9002 }
9003
9004 /**
9005  * Query a devx counter.
9006  *
9007  * @param[in] dev
9008  *   Pointer to the Ethernet device structure.
9009  * @param[in] cnt
9010  *   Index to the flow counter.
9011  * @param[in] clear
9012  *   Set to clear the counter statistics.
9013  * @param[out] pkts
9014  *   The statistics value of packets.
9015  * @param[out] bytes
9016  *   The statistics value of bytes.
9017  *
9018  * @return
9019  *   0 on success, otherwise return -1.
9020  */
9021 static int
9022 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
9023                       uint64_t *pkts, uint64_t *bytes)
9024 {
9025         struct mlx5_priv *priv = dev->data->dev_private;
9026         struct mlx5_flow_counter *cnt;
9027         uint64_t inn_pkts, inn_bytes;
9028         int ret;
9029
9030         if (!priv->config.devx)
9031                 return -1;
9032
9033         ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
9034         if (ret)
9035                 return -1;
9036         cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
9037         *pkts = inn_pkts - cnt->hits;
9038         *bytes = inn_bytes - cnt->bytes;
9039         if (clear) {
9040                 cnt->hits = inn_pkts;
9041                 cnt->bytes = inn_bytes;
9042         }
9043         return 0;
9044 }
9045
9046 /*
9047  * Mutex-protected thunk to lock-free  __flow_dv_translate().
9048  */
9049 static int
9050 flow_dv_translate(struct rte_eth_dev *dev,
9051                   struct mlx5_flow *dev_flow,
9052                   const struct rte_flow_attr *attr,
9053                   const struct rte_flow_item items[],
9054                   const struct rte_flow_action actions[],
9055                   struct rte_flow_error *error)
9056 {
9057         int ret;
9058
9059         flow_dv_shared_lock(dev);
9060         ret = __flow_dv_translate(dev, dev_flow, attr, items, actions, error);
9061         flow_dv_shared_unlock(dev);
9062         return ret;
9063 }
9064
9065 /*
9066  * Mutex-protected thunk to lock-free  __flow_dv_apply().
9067  */
9068 static int
9069 flow_dv_apply(struct rte_eth_dev *dev,
9070               struct rte_flow *flow,
9071               struct rte_flow_error *error)
9072 {
9073         int ret;
9074
9075         flow_dv_shared_lock(dev);
9076         ret = __flow_dv_apply(dev, flow, error);
9077         flow_dv_shared_unlock(dev);
9078         return ret;
9079 }
9080
9081 /*
9082  * Mutex-protected thunk to lock-free __flow_dv_remove().
9083  */
9084 static void
9085 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
9086 {
9087         flow_dv_shared_lock(dev);
9088         __flow_dv_remove(dev, flow);
9089         flow_dv_shared_unlock(dev);
9090 }
9091
9092 /*
9093  * Mutex-protected thunk to lock-free __flow_dv_destroy().
9094  */
9095 static void
9096 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
9097 {
9098         flow_dv_shared_lock(dev);
9099         __flow_dv_destroy(dev, flow);
9100         flow_dv_shared_unlock(dev);
9101 }
9102
9103 /*
9104  * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
9105  */
9106 static uint32_t
9107 flow_dv_counter_allocate(struct rte_eth_dev *dev)
9108 {
9109         uint32_t cnt;
9110
9111         flow_dv_shared_lock(dev);
9112         cnt = flow_dv_counter_alloc(dev, 0, 0, 1);
9113         flow_dv_shared_unlock(dev);
9114         return cnt;
9115 }
9116
9117 /*
9118  * Mutex-protected thunk to lock-free flow_dv_counter_release().
9119  */
9120 static void
9121 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t cnt)
9122 {
9123         flow_dv_shared_lock(dev);
9124         flow_dv_counter_release(dev, cnt);
9125         flow_dv_shared_unlock(dev);
9126 }
9127
9128 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
9129         .validate = flow_dv_validate,
9130         .prepare = flow_dv_prepare,
9131         .translate = flow_dv_translate,
9132         .apply = flow_dv_apply,
9133         .remove = flow_dv_remove,
9134         .destroy = flow_dv_destroy,
9135         .query = flow_dv_query,
9136         .create_mtr_tbls = flow_dv_create_mtr_tbl,
9137         .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
9138         .create_policer_rules = flow_dv_create_policer_rules,
9139         .destroy_policer_rules = flow_dv_destroy_policer_rules,
9140         .counter_alloc = flow_dv_counter_allocate,
9141         .counter_free = flow_dv_counter_free,
9142         .counter_query = flow_dv_counter_query,
9143 };
9144
9145 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */