drivers/net/mlx5/mlx5_flow_dv.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2018 Mellanox Technologies, Ltd
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdalign.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10
  11 #include <rte_common.h>
  12 #include <rte_ether.h>
  13 #include <rte_ethdev_driver.h>
  14 #include <rte_flow.h>
  15 #include <rte_flow_driver.h>
  16 #include <rte_malloc.h>
  17 #include <rte_cycles.h>
  18 #include <rte_ip.h>
  19 #include <rte_gre.h>
  20 #include <rte_vxlan.h>
  21 #include <rte_gtp.h>
  22 #include <rte_eal_paging.h>
  23 #include <rte_mpls.h>
  24
  25 #include <mlx5_glue.h>
  26 #include <mlx5_devx_cmds.h>
  27 #include <mlx5_prm.h>
  28 #include <mlx5_malloc.h>
  29
  30 #include "mlx5_defs.h"
  31 #include "mlx5.h"
  32 #include "mlx5_common_os.h"
  33 #include "mlx5_flow.h"
  34 #include "mlx5_flow_os.h"
  35 #include "mlx5_rxtx.h"
  36
  37 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
  38
  39 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
  40 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
  41 #endif
  42
  43 #ifndef HAVE_MLX5DV_DR_ESWITCH
  44 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
  45 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
  46 #endif
  47 #endif
  48
  49 #ifndef HAVE_MLX5DV_DR
  50 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
  51 #endif
  52
  53 /* VLAN header definitions */
  54 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
  55 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
  56 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
  57 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
  58 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
  59
  60 union flow_dv_attr {
  61         struct {
  62                 uint32_t valid:1;
  63                 uint32_t ipv4:1;
  64                 uint32_t ipv6:1;
  65                 uint32_t tcp:1;
  66                 uint32_t udp:1;
  67                 uint32_t reserved:27;
  68         };
  69         uint32_t attr;
  70 };
  71
  72 static int
  73 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
  74                              struct mlx5_flow_tbl_resource *tbl);
  75
  76 static int
  77 flow_dv_default_miss_resource_release(struct rte_eth_dev *dev);
  78
  79 /**
  80  * Initialize flow attributes structure according to flow items' types.
  81  *
  82  * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
  83  * mode. For tunnel mode, the items to be modified are the outermost ones.
  84  *
  85  * @param[in] item
  86  *   Pointer to item specification.
  87  * @param[out] attr
  88  *   Pointer to flow attributes structure.
  89  * @param[in] dev_flow
  90  *   Pointer to the sub flow.
  91  * @param[in] tunnel_decap
  92  *   Whether action is after tunnel decapsulation.
  93  */
  94 static void
  95 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
  96                   struct mlx5_flow *dev_flow, bool tunnel_decap)
  97 {
  98         uint64_t layers = dev_flow->handle->layers;
  99
 100         /*
 101          * If layers is already initialized, it means this dev_flow is the
 102          * suffix flow, the layers flags is set by the prefix flow. Need to
 103          * use the layer flags from prefix flow as the suffix flow may not
 104          * have the user defined items as the flow is split.
 105          */
 106         if (layers) {
 107                 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
 108                         attr->ipv4 = 1;
 109                 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
 110                         attr->ipv6 = 1;
 111                 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
 112                         attr->tcp = 1;
 113                 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
 114                         attr->udp = 1;
 115                 attr->valid = 1;
 116                 return;
 117         }
 118         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
 119                 uint8_t next_protocol = 0xff;
 120                 switch (item->type) {
 121                 case RTE_FLOW_ITEM_TYPE_GRE:
 122                 case RTE_FLOW_ITEM_TYPE_NVGRE:
 123                 case RTE_FLOW_ITEM_TYPE_VXLAN:
 124                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
 125                 case RTE_FLOW_ITEM_TYPE_GENEVE:
 126                 case RTE_FLOW_ITEM_TYPE_MPLS:
 127                         if (tunnel_decap)
 128                                 attr->attr = 0;
 129                         break;
 130                 case RTE_FLOW_ITEM_TYPE_IPV4:
 131                         if (!attr->ipv6)
 132                                 attr->ipv4 = 1;
 133                         if (item->mask != NULL &&
 134                             ((const struct rte_flow_item_ipv4 *)
 135                             item->mask)->hdr.next_proto_id)
 136                                 next_protocol =
 137                                     ((const struct rte_flow_item_ipv4 *)
 138                                       (item->spec))->hdr.next_proto_id &
 139                                     ((const struct rte_flow_item_ipv4 *)
 140                                       (item->mask))->hdr.next_proto_id;
 141                         if ((next_protocol == IPPROTO_IPIP ||
 142                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 143                                 attr->attr = 0;
 144                         break;
 145                 case RTE_FLOW_ITEM_TYPE_IPV6:
 146                         if (!attr->ipv4)
 147                                 attr->ipv6 = 1;
 148                         if (item->mask != NULL &&
 149                             ((const struct rte_flow_item_ipv6 *)
 150                             item->mask)->hdr.proto)
 151                                 next_protocol =
 152                                     ((const struct rte_flow_item_ipv6 *)
 153                                       (item->spec))->hdr.proto &
 154                                     ((const struct rte_flow_item_ipv6 *)
 155                                       (item->mask))->hdr.proto;
 156                         if ((next_protocol == IPPROTO_IPIP ||
 157                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 158                                 attr->attr = 0;
 159                         break;
 160                 case RTE_FLOW_ITEM_TYPE_UDP:
 161                         if (!attr->tcp)
 162                                 attr->udp = 1;
 163                         break;
 164                 case RTE_FLOW_ITEM_TYPE_TCP:
 165                         if (!attr->udp)
 166                                 attr->tcp = 1;
 167                         break;
 168                 default:
 169                         break;
 170                 }
 171         }
 172         attr->valid = 1;
 173 }
 174
 175 /**
 176  * Convert rte_mtr_color to mlx5 color.
 177  *
 178  * @param[in] rcol
 179  *   rte_mtr_color.
 180  *
 181  * @return
 182  *   mlx5 color.
 183  */
 184 static int
 185 rte_col_2_mlx5_col(enum rte_color rcol)
 186 {
 187         switch (rcol) {
 188         case RTE_COLOR_GREEN:
 189                 return MLX5_FLOW_COLOR_GREEN;
 190         case RTE_COLOR_YELLOW:
 191                 return MLX5_FLOW_COLOR_YELLOW;
 192         case RTE_COLOR_RED:
 193                 return MLX5_FLOW_COLOR_RED;
 194         default:
 195                 break;
 196         }
 197         return MLX5_FLOW_COLOR_UNDEFINED;
 198 }
 199
 200 struct field_modify_info {
 201         uint32_t size; /* Size of field in protocol header, in bytes. */
 202         uint32_t offset; /* Offset of field in protocol header, in bytes. */
 203         enum mlx5_modification_field id;
 204 };
 205
 206 struct field_modify_info modify_eth[] = {
 207         {4,  0, MLX5_MODI_OUT_DMAC_47_16},
 208         {2,  4, MLX5_MODI_OUT_DMAC_15_0},
 209         {4,  6, MLX5_MODI_OUT_SMAC_47_16},
 210         {2, 10, MLX5_MODI_OUT_SMAC_15_0},
 211         {0, 0, 0},
 212 };
 213
 214 struct field_modify_info modify_vlan_out_first_vid[] = {
 215         /* Size in bits !!! */
 216         {12, 0, MLX5_MODI_OUT_FIRST_VID},
 217         {0, 0, 0},
 218 };
 219
 220 struct field_modify_info modify_ipv4[] = {
 221         {1,  1, MLX5_MODI_OUT_IP_DSCP},
 222         {1,  8, MLX5_MODI_OUT_IPV4_TTL},
 223         {4, 12, MLX5_MODI_OUT_SIPV4},
 224         {4, 16, MLX5_MODI_OUT_DIPV4},
 225         {0, 0, 0},
 226 };
 227
 228 struct field_modify_info modify_ipv6[] = {
 229         {1,  0, MLX5_MODI_OUT_IP_DSCP},
 230         {1,  7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
 231         {4,  8, MLX5_MODI_OUT_SIPV6_127_96},
 232         {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
 233         {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
 234         {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
 235         {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
 236         {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
 237         {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
 238         {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
 239         {0, 0, 0},
 240 };
 241
 242 struct field_modify_info modify_udp[] = {
 243         {2, 0, MLX5_MODI_OUT_UDP_SPORT},
 244         {2, 2, MLX5_MODI_OUT_UDP_DPORT},
 245         {0, 0, 0},
 246 };
 247
 248 struct field_modify_info modify_tcp[] = {
 249         {2, 0, MLX5_MODI_OUT_TCP_SPORT},
 250         {2, 2, MLX5_MODI_OUT_TCP_DPORT},
 251         {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
 252         {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
 253         {0, 0, 0},
 254 };
 255
 256 static void
 257 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
 258                           uint8_t next_protocol, uint64_t *item_flags,
 259                           int *tunnel)
 260 {
 261         MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
 262                     item->type == RTE_FLOW_ITEM_TYPE_IPV6);
 263         if (next_protocol == IPPROTO_IPIP) {
 264                 *item_flags |= MLX5_FLOW_LAYER_IPIP;
 265                 *tunnel = 1;
 266         }
 267         if (next_protocol == IPPROTO_IPV6) {
 268                 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
 269                 *tunnel = 1;
 270         }
 271 }
 272
 273 /**
 274  * Acquire the synchronizing object to protect multithreaded access
 275  * to shared dv context. Lock occurs only if context is actually
 276  * shared, i.e. we have multiport IB device and representors are
 277  * created.
 278  *
 279  * @param[in] dev
 280  *   Pointer to the rte_eth_dev structure.
 281  */
 282 static void
 283 flow_dv_shared_lock(struct rte_eth_dev *dev)
 284 {
 285         struct mlx5_priv *priv = dev->data->dev_private;
 286         struct mlx5_dev_ctx_shared *sh = priv->sh;
 287
 288         if (sh->dv_refcnt > 1) {
 289                 int ret;
 290
 291                 ret = pthread_mutex_lock(&sh->dv_mutex);
 292                 MLX5_ASSERT(!ret);
 293                 (void)ret;
 294         }
 295 }
 296
 297 static void
 298 flow_dv_shared_unlock(struct rte_eth_dev *dev)
 299 {
 300         struct mlx5_priv *priv = dev->data->dev_private;
 301         struct mlx5_dev_ctx_shared *sh = priv->sh;
 302
 303         if (sh->dv_refcnt > 1) {
 304                 int ret;
 305
 306                 ret = pthread_mutex_unlock(&sh->dv_mutex);
 307                 MLX5_ASSERT(!ret);
 308                 (void)ret;
 309         }
 310 }
 311
 312 /* Update VLAN's VID/PCP based on input rte_flow_action.
 313  *
 314  * @param[in] action
 315  *   Pointer to struct rte_flow_action.
 316  * @param[out] vlan
 317  *   Pointer to struct rte_vlan_hdr.
 318  */
 319 static void
 320 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
 321                          struct rte_vlan_hdr *vlan)
 322 {
 323         uint16_t vlan_tci;
 324         if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
 325                 vlan_tci =
 326                     ((const struct rte_flow_action_of_set_vlan_pcp *)
 327                                                action->conf)->vlan_pcp;
 328                 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
 329                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
 330                 vlan->vlan_tci |= vlan_tci;
 331         } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
 332                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
 333                 vlan->vlan_tci |= rte_be_to_cpu_16
 334                     (((const struct rte_flow_action_of_set_vlan_vid *)
 335                                              action->conf)->vlan_vid);
 336         }
 337 }
 338
 339 /**
 340  * Fetch 1, 2, 3 or 4 byte field from the byte array
 341  * and return as unsigned integer in host-endian format.
 342  *
 343  * @param[in] data
 344  *   Pointer to data array.
 345  * @param[in] size
 346  *   Size of field to extract.
 347  *
 348  * @return
 349  *   converted field in host endian format.
 350  */
 351 static inline uint32_t
 352 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
 353 {
 354         uint32_t ret;
 355
 356         switch (size) {
 357         case 1:
 358                 ret = *data;
 359                 break;
 360         case 2:
 361                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 362                 break;
 363         case 3:
 364                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 365                 ret = (ret << 8) | *(data + sizeof(uint16_t));
 366                 break;
 367         case 4:
 368                 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
 369                 break;
 370         default:
 371                 MLX5_ASSERT(false);
 372                 ret = 0;
 373                 break;
 374         }
 375         return ret;
 376 }
 377
 378 /**
 379  * Convert modify-header action to DV specification.
 380  *
 381  * Data length of each action is determined by provided field description
 382  * and the item mask. Data bit offset and width of each action is determined
 383  * by provided item mask.
 384  *
 385  * @param[in] item
 386  *   Pointer to item specification.
 387  * @param[in] field
 388  *   Pointer to field modification information.
 389  *     For MLX5_MODIFICATION_TYPE_SET specifies destination field.
 390  *     For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
 391  *     For MLX5_MODIFICATION_TYPE_COPY specifies source field.
 392  * @param[in] dcopy
 393  *   Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
 394  *   Negative offset value sets the same offset as source offset.
 395  *   size field is ignored, value is taken from source field.
 396  * @param[in,out] resource
 397  *   Pointer to the modify-header resource.
 398  * @param[in] type
 399  *   Type of modification.
 400  * @param[out] error
 401  *   Pointer to the error structure.
 402  *
 403  * @return
 404  *   0 on success, a negative errno value otherwise and rte_errno is set.
 405  */
 406 static int
 407 flow_dv_convert_modify_action(struct rte_flow_item *item,
 408                               struct field_modify_info *field,
 409                               struct field_modify_info *dcopy,
 410                               struct mlx5_flow_dv_modify_hdr_resource *resource,
 411                               uint32_t type, struct rte_flow_error *error)
 412 {
 413         uint32_t i = resource->actions_num;
 414         struct mlx5_modification_cmd *actions = resource->actions;
 415
 416         /*
 417          * The item and mask are provided in big-endian format.
 418          * The fields should be presented as in big-endian format either.
 419          * Mask must be always present, it defines the actual field width.
 420          */
 421         MLX5_ASSERT(item->mask);
 422         MLX5_ASSERT(field->size);
 423         do {
 424                 unsigned int size_b;
 425                 unsigned int off_b;
 426                 uint32_t mask;
 427                 uint32_t data;
 428
 429                 if (i >= MLX5_MAX_MODIFY_NUM)
 430                         return rte_flow_error_set(error, EINVAL,
 431                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 432                                  "too many items to modify");
 433                 /* Fetch variable byte size mask from the array. */
 434                 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
 435                                            field->offset, field->size);
 436                 if (!mask) {
 437                         ++field;
 438                         continue;
 439                 }
 440                 /* Deduce actual data width in bits from mask value. */
 441                 off_b = rte_bsf32(mask);
 442                 size_b = sizeof(uint32_t) * CHAR_BIT -
 443                          off_b - __builtin_clz(mask);
 444                 MLX5_ASSERT(size_b);
 445                 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
 446                 actions[i] = (struct mlx5_modification_cmd) {
 447                         .action_type = type,
 448                         .field = field->id,
 449                         .offset = off_b,
 450                         .length = size_b,
 451                 };
 452                 /* Convert entire record to expected big-endian format. */
 453                 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 454                 if (type == MLX5_MODIFICATION_TYPE_COPY) {
 455                         MLX5_ASSERT(dcopy);
 456                         actions[i].dst_field = dcopy->id;
 457                         actions[i].dst_offset =
 458                                 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
 459                         /* Convert entire record to big-endian format. */
 460                         actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
 461                 } else {
 462                         MLX5_ASSERT(item->spec);
 463                         data = flow_dv_fetch_field((const uint8_t *)item->spec +
 464                                                    field->offset, field->size);
 465                         /* Shift out the trailing masked bits from data. */
 466                         data = (data & mask) >> off_b;
 467                         actions[i].data1 = rte_cpu_to_be_32(data);
 468                 }
 469                 ++i;
 470                 ++field;
 471         } while (field->size);
 472         if (resource->actions_num == i)
 473                 return rte_flow_error_set(error, EINVAL,
 474                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 475                                           "invalid modification flow item");
 476         resource->actions_num = i;
 477         return 0;
 478 }
 479
 480 /**
 481  * Convert modify-header set IPv4 address action to DV specification.
 482  *
 483  * @param[in,out] resource
 484  *   Pointer to the modify-header resource.
 485  * @param[in] action
 486  *   Pointer to action specification.
 487  * @param[out] error
 488  *   Pointer to the error structure.
 489  *
 490  * @return
 491  *   0 on success, a negative errno value otherwise and rte_errno is set.
 492  */
 493 static int
 494 flow_dv_convert_action_modify_ipv4
 495                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 496                          const struct rte_flow_action *action,
 497                          struct rte_flow_error *error)
 498 {
 499         const struct rte_flow_action_set_ipv4 *conf =
 500                 (const struct rte_flow_action_set_ipv4 *)(action->conf);
 501         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
 502         struct rte_flow_item_ipv4 ipv4;
 503         struct rte_flow_item_ipv4 ipv4_mask;
 504
 505         memset(&ipv4, 0, sizeof(ipv4));
 506         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 507         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
 508                 ipv4.hdr.src_addr = conf->ipv4_addr;
 509                 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
 510         } else {
 511                 ipv4.hdr.dst_addr = conf->ipv4_addr;
 512                 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
 513         }
 514         item.spec = &ipv4;
 515         item.mask = &ipv4_mask;
 516         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
 517                                              MLX5_MODIFICATION_TYPE_SET, error);
 518 }
 519
 520 /**
 521  * Convert modify-header set IPv6 address action to DV specification.
 522  *
 523  * @param[in,out] resource
 524  *   Pointer to the modify-header resource.
 525  * @param[in] action
 526  *   Pointer to action specification.
 527  * @param[out] error
 528  *   Pointer to the error structure.
 529  *
 530  * @return
 531  *   0 on success, a negative errno value otherwise and rte_errno is set.
 532  */
 533 static int
 534 flow_dv_convert_action_modify_ipv6
 535                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 536                          const struct rte_flow_action *action,
 537                          struct rte_flow_error *error)
 538 {
 539         const struct rte_flow_action_set_ipv6 *conf =
 540                 (const struct rte_flow_action_set_ipv6 *)(action->conf);
 541         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
 542         struct rte_flow_item_ipv6 ipv6;
 543         struct rte_flow_item_ipv6 ipv6_mask;
 544
 545         memset(&ipv6, 0, sizeof(ipv6));
 546         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 547         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
 548                 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
 549                        sizeof(ipv6.hdr.src_addr));
 550                 memcpy(&ipv6_mask.hdr.src_addr,
 551                        &rte_flow_item_ipv6_mask.hdr.src_addr,
 552                        sizeof(ipv6.hdr.src_addr));
 553         } else {
 554                 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
 555                        sizeof(ipv6.hdr.dst_addr));
 556                 memcpy(&ipv6_mask.hdr.dst_addr,
 557                        &rte_flow_item_ipv6_mask.hdr.dst_addr,
 558                        sizeof(ipv6.hdr.dst_addr));
 559         }
 560         item.spec = &ipv6;
 561         item.mask = &ipv6_mask;
 562         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
 563                                              MLX5_MODIFICATION_TYPE_SET, error);
 564 }
 565
 566 /**
 567  * Convert modify-header set MAC address action to DV specification.
 568  *
 569  * @param[in,out] resource
 570  *   Pointer to the modify-header resource.
 571  * @param[in] action
 572  *   Pointer to action specification.
 573  * @param[out] error
 574  *   Pointer to the error structure.
 575  *
 576  * @return
 577  *   0 on success, a negative errno value otherwise and rte_errno is set.
 578  */
 579 static int
 580 flow_dv_convert_action_modify_mac
 581                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 582                          const struct rte_flow_action *action,
 583                          struct rte_flow_error *error)
 584 {
 585         const struct rte_flow_action_set_mac *conf =
 586                 (const struct rte_flow_action_set_mac *)(action->conf);
 587         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
 588         struct rte_flow_item_eth eth;
 589         struct rte_flow_item_eth eth_mask;
 590
 591         memset(&eth, 0, sizeof(eth));
 592         memset(&eth_mask, 0, sizeof(eth_mask));
 593         if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
 594                 memcpy(&eth.src.addr_bytes, &conf->mac_addr,
 595                        sizeof(eth.src.addr_bytes));
 596                 memcpy(&eth_mask.src.addr_bytes,
 597                        &rte_flow_item_eth_mask.src.addr_bytes,
 598                        sizeof(eth_mask.src.addr_bytes));
 599         } else {
 600                 memcpy(&eth.dst.addr_bytes, &conf->mac_addr,
 601                        sizeof(eth.dst.addr_bytes));
 602                 memcpy(&eth_mask.dst.addr_bytes,
 603                        &rte_flow_item_eth_mask.dst.addr_bytes,
 604                        sizeof(eth_mask.dst.addr_bytes));
 605         }
 606         item.spec = &eth;
 607         item.mask = &eth_mask;
 608         return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
 609                                              MLX5_MODIFICATION_TYPE_SET, error);
 610 }
 611
 612 /**
 613  * Convert modify-header set VLAN VID action to DV specification.
 614  *
 615  * @param[in,out] resource
 616  *   Pointer to the modify-header resource.
 617  * @param[in] action
 618  *   Pointer to action specification.
 619  * @param[out] error
 620  *   Pointer to the error structure.
 621  *
 622  * @return
 623  *   0 on success, a negative errno value otherwise and rte_errno is set.
 624  */
 625 static int
 626 flow_dv_convert_action_modify_vlan_vid
 627                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 628                          const struct rte_flow_action *action,
 629                          struct rte_flow_error *error)
 630 {
 631         const struct rte_flow_action_of_set_vlan_vid *conf =
 632                 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
 633         int i = resource->actions_num;
 634         struct mlx5_modification_cmd *actions = resource->actions;
 635         struct field_modify_info *field = modify_vlan_out_first_vid;
 636
 637         if (i >= MLX5_MAX_MODIFY_NUM)
 638                 return rte_flow_error_set(error, EINVAL,
 639                          RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 640                          "too many items to modify");
 641         actions[i] = (struct mlx5_modification_cmd) {
 642                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 643                 .field = field->id,
 644                 .length = field->size,
 645                 .offset = field->offset,
 646         };
 647         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 648         actions[i].data1 = conf->vlan_vid;
 649         actions[i].data1 = actions[i].data1 << 16;
 650         resource->actions_num = ++i;
 651         return 0;
 652 }
 653
 654 /**
 655  * Convert modify-header set TP action to DV specification.
 656  *
 657  * @param[in,out] resource
 658  *   Pointer to the modify-header resource.
 659  * @param[in] action
 660  *   Pointer to action specification.
 661  * @param[in] items
 662  *   Pointer to rte_flow_item objects list.
 663  * @param[in] attr
 664  *   Pointer to flow attributes structure.
 665  * @param[in] dev_flow
 666  *   Pointer to the sub flow.
 667  * @param[in] tunnel_decap
 668  *   Whether action is after tunnel decapsulation.
 669  * @param[out] error
 670  *   Pointer to the error structure.
 671  *
 672  * @return
 673  *   0 on success, a negative errno value otherwise and rte_errno is set.
 674  */
 675 static int
 676 flow_dv_convert_action_modify_tp
 677                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 678                          const struct rte_flow_action *action,
 679                          const struct rte_flow_item *items,
 680                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 681                          bool tunnel_decap, struct rte_flow_error *error)
 682 {
 683         const struct rte_flow_action_set_tp *conf =
 684                 (const struct rte_flow_action_set_tp *)(action->conf);
 685         struct rte_flow_item item;
 686         struct rte_flow_item_udp udp;
 687         struct rte_flow_item_udp udp_mask;
 688         struct rte_flow_item_tcp tcp;
 689         struct rte_flow_item_tcp tcp_mask;
 690         struct field_modify_info *field;
 691
 692         if (!attr->valid)
 693                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 694         if (attr->udp) {
 695                 memset(&udp, 0, sizeof(udp));
 696                 memset(&udp_mask, 0, sizeof(udp_mask));
 697                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 698                         udp.hdr.src_port = conf->port;
 699                         udp_mask.hdr.src_port =
 700                                         rte_flow_item_udp_mask.hdr.src_port;
 701                 } else {
 702                         udp.hdr.dst_port = conf->port;
 703                         udp_mask.hdr.dst_port =
 704                                         rte_flow_item_udp_mask.hdr.dst_port;
 705                 }
 706                 item.type = RTE_FLOW_ITEM_TYPE_UDP;
 707                 item.spec = &udp;
 708                 item.mask = &udp_mask;
 709                 field = modify_udp;
 710         } else {
 711                 MLX5_ASSERT(attr->tcp);
 712                 memset(&tcp, 0, sizeof(tcp));
 713                 memset(&tcp_mask, 0, sizeof(tcp_mask));
 714                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 715                         tcp.hdr.src_port = conf->port;
 716                         tcp_mask.hdr.src_port =
 717                                         rte_flow_item_tcp_mask.hdr.src_port;
 718                 } else {
 719                         tcp.hdr.dst_port = conf->port;
 720                         tcp_mask.hdr.dst_port =
 721                                         rte_flow_item_tcp_mask.hdr.dst_port;
 722                 }
 723                 item.type = RTE_FLOW_ITEM_TYPE_TCP;
 724                 item.spec = &tcp;
 725                 item.mask = &tcp_mask;
 726                 field = modify_tcp;
 727         }
 728         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 729                                              MLX5_MODIFICATION_TYPE_SET, error);
 730 }
 731
 732 /**
 733  * Convert modify-header set TTL action to DV specification.
 734  *
 735  * @param[in,out] resource
 736  *   Pointer to the modify-header resource.
 737  * @param[in] action
 738  *   Pointer to action specification.
 739  * @param[in] items
 740  *   Pointer to rte_flow_item objects list.
 741  * @param[in] attr
 742  *   Pointer to flow attributes structure.
 743  * @param[in] dev_flow
 744  *   Pointer to the sub flow.
 745  * @param[in] tunnel_decap
 746  *   Whether action is after tunnel decapsulation.
 747  * @param[out] error
 748  *   Pointer to the error structure.
 749  *
 750  * @return
 751  *   0 on success, a negative errno value otherwise and rte_errno is set.
 752  */
 753 static int
 754 flow_dv_convert_action_modify_ttl
 755                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 756                          const struct rte_flow_action *action,
 757                          const struct rte_flow_item *items,
 758                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 759                          bool tunnel_decap, struct rte_flow_error *error)
 760 {
 761         const struct rte_flow_action_set_ttl *conf =
 762                 (const struct rte_flow_action_set_ttl *)(action->conf);
 763         struct rte_flow_item item;
 764         struct rte_flow_item_ipv4 ipv4;
 765         struct rte_flow_item_ipv4 ipv4_mask;
 766         struct rte_flow_item_ipv6 ipv6;
 767         struct rte_flow_item_ipv6 ipv6_mask;
 768         struct field_modify_info *field;
 769
 770         if (!attr->valid)
 771                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 772         if (attr->ipv4) {
 773                 memset(&ipv4, 0, sizeof(ipv4));
 774                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 775                 ipv4.hdr.time_to_live = conf->ttl_value;
 776                 ipv4_mask.hdr.time_to_live = 0xFF;
 777                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 778                 item.spec = &ipv4;
 779                 item.mask = &ipv4_mask;
 780                 field = modify_ipv4;
 781         } else {
 782                 MLX5_ASSERT(attr->ipv6);
 783                 memset(&ipv6, 0, sizeof(ipv6));
 784                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 785                 ipv6.hdr.hop_limits = conf->ttl_value;
 786                 ipv6_mask.hdr.hop_limits = 0xFF;
 787                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 788                 item.spec = &ipv6;
 789                 item.mask = &ipv6_mask;
 790                 field = modify_ipv6;
 791         }
 792         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 793                                              MLX5_MODIFICATION_TYPE_SET, error);
 794 }
 795
 796 /**
 797  * Convert modify-header decrement TTL action to DV specification.
 798  *
 799  * @param[in,out] resource
 800  *   Pointer to the modify-header resource.
 801  * @param[in] action
 802  *   Pointer to action specification.
 803  * @param[in] items
 804  *   Pointer to rte_flow_item objects list.
 805  * @param[in] attr
 806  *   Pointer to flow attributes structure.
 807  * @param[in] dev_flow
 808  *   Pointer to the sub flow.
 809  * @param[in] tunnel_decap
 810  *   Whether action is after tunnel decapsulation.
 811  * @param[out] error
 812  *   Pointer to the error structure.
 813  *
 814  * @return
 815  *   0 on success, a negative errno value otherwise and rte_errno is set.
 816  */
 817 static int
 818 flow_dv_convert_action_modify_dec_ttl
 819                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 820                          const struct rte_flow_item *items,
 821                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 822                          bool tunnel_decap, struct rte_flow_error *error)
 823 {
 824         struct rte_flow_item item;
 825         struct rte_flow_item_ipv4 ipv4;
 826         struct rte_flow_item_ipv4 ipv4_mask;
 827         struct rte_flow_item_ipv6 ipv6;
 828         struct rte_flow_item_ipv6 ipv6_mask;
 829         struct field_modify_info *field;
 830
 831         if (!attr->valid)
 832                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 833         if (attr->ipv4) {
 834                 memset(&ipv4, 0, sizeof(ipv4));
 835                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 836                 ipv4.hdr.time_to_live = 0xFF;
 837                 ipv4_mask.hdr.time_to_live = 0xFF;
 838                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 839                 item.spec = &ipv4;
 840                 item.mask = &ipv4_mask;
 841                 field = modify_ipv4;
 842         } else {
 843                 MLX5_ASSERT(attr->ipv6);
 844                 memset(&ipv6, 0, sizeof(ipv6));
 845                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 846                 ipv6.hdr.hop_limits = 0xFF;
 847                 ipv6_mask.hdr.hop_limits = 0xFF;
 848                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 849                 item.spec = &ipv6;
 850                 item.mask = &ipv6_mask;
 851                 field = modify_ipv6;
 852         }
 853         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 854                                              MLX5_MODIFICATION_TYPE_ADD, error);
 855 }
 856
 857 /**
 858  * Convert modify-header increment/decrement TCP Sequence number
 859  * to DV specification.
 860  *
 861  * @param[in,out] resource
 862  *   Pointer to the modify-header resource.
 863  * @param[in] action
 864  *   Pointer to action specification.
 865  * @param[out] error
 866  *   Pointer to the error structure.
 867  *
 868  * @return
 869  *   0 on success, a negative errno value otherwise and rte_errno is set.
 870  */
 871 static int
 872 flow_dv_convert_action_modify_tcp_seq
 873                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 874                          const struct rte_flow_action *action,
 875                          struct rte_flow_error *error)
 876 {
 877         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 878         uint64_t value = rte_be_to_cpu_32(*conf);
 879         struct rte_flow_item item;
 880         struct rte_flow_item_tcp tcp;
 881         struct rte_flow_item_tcp tcp_mask;
 882
 883         memset(&tcp, 0, sizeof(tcp));
 884         memset(&tcp_mask, 0, sizeof(tcp_mask));
 885         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
 886                 /*
 887                  * The HW has no decrement operation, only increment operation.
 888                  * To simulate decrement X from Y using increment operation
 889                  * we need to add UINT32_MAX X times to Y.
 890                  * Each adding of UINT32_MAX decrements Y by 1.
 891                  */
 892                 value *= UINT32_MAX;
 893         tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
 894         tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
 895         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 896         item.spec = &tcp;
 897         item.mask = &tcp_mask;
 898         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 899                                              MLX5_MODIFICATION_TYPE_ADD, error);
 900 }
 901
 902 /**
 903  * Convert modify-header increment/decrement TCP Acknowledgment number
 904  * to DV specification.
 905  *
 906  * @param[in,out] resource
 907  *   Pointer to the modify-header resource.
 908  * @param[in] action
 909  *   Pointer to action specification.
 910  * @param[out] error
 911  *   Pointer to the error structure.
 912  *
 913  * @return
 914  *   0 on success, a negative errno value otherwise and rte_errno is set.
 915  */
 916 static int
 917 flow_dv_convert_action_modify_tcp_ack
 918                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 919                          const struct rte_flow_action *action,
 920                          struct rte_flow_error *error)
 921 {
 922         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 923         uint64_t value = rte_be_to_cpu_32(*conf);
 924         struct rte_flow_item item;
 925         struct rte_flow_item_tcp tcp;
 926         struct rte_flow_item_tcp tcp_mask;
 927
 928         memset(&tcp, 0, sizeof(tcp));
 929         memset(&tcp_mask, 0, sizeof(tcp_mask));
 930         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
 931                 /*
 932                  * The HW has no decrement operation, only increment operation.
 933                  * To simulate decrement X from Y using increment operation
 934                  * we need to add UINT32_MAX X times to Y.
 935                  * Each adding of UINT32_MAX decrements Y by 1.
 936                  */
 937                 value *= UINT32_MAX;
 938         tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
 939         tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
 940         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 941         item.spec = &tcp;
 942         item.mask = &tcp_mask;
 943         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 944                                              MLX5_MODIFICATION_TYPE_ADD, error);
 945 }
 946
 947 static enum mlx5_modification_field reg_to_field[] = {
 948         [REG_NON] = MLX5_MODI_OUT_NONE,
 949         [REG_A] = MLX5_MODI_META_DATA_REG_A,
 950         [REG_B] = MLX5_MODI_META_DATA_REG_B,
 951         [REG_C_0] = MLX5_MODI_META_REG_C_0,
 952         [REG_C_1] = MLX5_MODI_META_REG_C_1,
 953         [REG_C_2] = MLX5_MODI_META_REG_C_2,
 954         [REG_C_3] = MLX5_MODI_META_REG_C_3,
 955         [REG_C_4] = MLX5_MODI_META_REG_C_4,
 956         [REG_C_5] = MLX5_MODI_META_REG_C_5,
 957         [REG_C_6] = MLX5_MODI_META_REG_C_6,
 958         [REG_C_7] = MLX5_MODI_META_REG_C_7,
 959 };
 960
 961 /**
 962  * Convert register set to DV specification.
 963  *
 964  * @param[in,out] resource
 965  *   Pointer to the modify-header resource.
 966  * @param[in] action
 967  *   Pointer to action specification.
 968  * @param[out] error
 969  *   Pointer to the error structure.
 970  *
 971  * @return
 972  *   0 on success, a negative errno value otherwise and rte_errno is set.
 973  */
 974 static int
 975 flow_dv_convert_action_set_reg
 976                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 977                          const struct rte_flow_action *action,
 978                          struct rte_flow_error *error)
 979 {
 980         const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
 981         struct mlx5_modification_cmd *actions = resource->actions;
 982         uint32_t i = resource->actions_num;
 983
 984         if (i >= MLX5_MAX_MODIFY_NUM)
 985                 return rte_flow_error_set(error, EINVAL,
 986                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 987                                           "too many items to modify");
 988         MLX5_ASSERT(conf->id != REG_NON);
 989         MLX5_ASSERT(conf->id < RTE_DIM(reg_to_field));
 990         actions[i] = (struct mlx5_modification_cmd) {
 991                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 992                 .field = reg_to_field[conf->id],
 993         };
 994         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 995         actions[i].data1 = rte_cpu_to_be_32(conf->data);
 996         ++i;
 997         resource->actions_num = i;
 998         return 0;
 999 }
1000
1001 /**
1002  * Convert SET_TAG action to DV specification.
1003  *
1004  * @param[in] dev
1005  *   Pointer to the rte_eth_dev structure.
1006  * @param[in,out] resource
1007  *   Pointer to the modify-header resource.
1008  * @param[in] conf
1009  *   Pointer to action specification.
1010  * @param[out] error
1011  *   Pointer to the error structure.
1012  *
1013  * @return
1014  *   0 on success, a negative errno value otherwise and rte_errno is set.
1015  */
1016 static int
1017 flow_dv_convert_action_set_tag
1018                         (struct rte_eth_dev *dev,
1019                          struct mlx5_flow_dv_modify_hdr_resource *resource,
1020                          const struct rte_flow_action_set_tag *conf,
1021                          struct rte_flow_error *error)
1022 {
1023         rte_be32_t data = rte_cpu_to_be_32(conf->data);
1024         rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
1025         struct rte_flow_item item = {
1026                 .spec = &data,
1027                 .mask = &mask,
1028         };
1029         struct field_modify_info reg_c_x[] = {
1030                 [1] = {0, 0, 0},
1031         };
1032         enum mlx5_modification_field reg_type;
1033         int ret;
1034
1035         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1036         if (ret < 0)
1037                 return ret;
1038         MLX5_ASSERT(ret != REG_NON);
1039         MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1040         reg_type = reg_to_field[ret];
1041         MLX5_ASSERT(reg_type > 0);
1042         reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1043         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1044                                              MLX5_MODIFICATION_TYPE_SET, error);
1045 }
1046
1047 /**
1048  * Convert internal COPY_REG action to DV specification.
1049  *
1050  * @param[in] dev
1051  *   Pointer to the rte_eth_dev structure.
1052  * @param[in,out] res
1053  *   Pointer to the modify-header resource.
1054  * @param[in] action
1055  *   Pointer to action specification.
1056  * @param[out] error
1057  *   Pointer to the error structure.
1058  *
1059  * @return
1060  *   0 on success, a negative errno value otherwise and rte_errno is set.
1061  */
1062 static int
1063 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1064                                  struct mlx5_flow_dv_modify_hdr_resource *res,
1065                                  const struct rte_flow_action *action,
1066                                  struct rte_flow_error *error)
1067 {
1068         const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1069         rte_be32_t mask = RTE_BE32(UINT32_MAX);
1070         struct rte_flow_item item = {
1071                 .spec = NULL,
1072                 .mask = &mask,
1073         };
1074         struct field_modify_info reg_src[] = {
1075                 {4, 0, reg_to_field[conf->src]},
1076                 {0, 0, 0},
1077         };
1078         struct field_modify_info reg_dst = {
1079                 .offset = 0,
1080                 .id = reg_to_field[conf->dst],
1081         };
1082         /* Adjust reg_c[0] usage according to reported mask. */
1083         if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1084                 struct mlx5_priv *priv = dev->data->dev_private;
1085                 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1086
1087                 MLX5_ASSERT(reg_c0);
1088                 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1089                 if (conf->dst == REG_C_0) {
1090                         /* Copy to reg_c[0], within mask only. */
1091                         reg_dst.offset = rte_bsf32(reg_c0);
1092                         /*
1093                          * Mask is ignoring the enianness, because
1094                          * there is no conversion in datapath.
1095                          */
1096 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1097                         /* Copy from destination lower bits to reg_c[0]. */
1098                         mask = reg_c0 >> reg_dst.offset;
1099 #else
1100                         /* Copy from destination upper bits to reg_c[0]. */
1101                         mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1102                                           rte_fls_u32(reg_c0));
1103 #endif
1104                 } else {
1105                         mask = rte_cpu_to_be_32(reg_c0);
1106 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1107                         /* Copy from reg_c[0] to destination lower bits. */
1108                         reg_dst.offset = 0;
1109 #else
1110                         /* Copy from reg_c[0] to destination upper bits. */
1111                         reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1112                                          (rte_fls_u32(reg_c0) -
1113                                           rte_bsf32(reg_c0));
1114 #endif
1115                 }
1116         }
1117         return flow_dv_convert_modify_action(&item,
1118                                              reg_src, &reg_dst, res,
1119                                              MLX5_MODIFICATION_TYPE_COPY,
1120                                              error);
1121 }
1122
1123 /**
1124  * Convert MARK action to DV specification. This routine is used
1125  * in extensive metadata only and requires metadata register to be
1126  * handled. In legacy mode hardware tag resource is engaged.
1127  *
1128  * @param[in] dev
1129  *   Pointer to the rte_eth_dev structure.
1130  * @param[in] conf
1131  *   Pointer to MARK action specification.
1132  * @param[in,out] resource
1133  *   Pointer to the modify-header resource.
1134  * @param[out] error
1135  *   Pointer to the error structure.
1136  *
1137  * @return
1138  *   0 on success, a negative errno value otherwise and rte_errno is set.
1139  */
1140 static int
1141 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1142                             const struct rte_flow_action_mark *conf,
1143                             struct mlx5_flow_dv_modify_hdr_resource *resource,
1144                             struct rte_flow_error *error)
1145 {
1146         struct mlx5_priv *priv = dev->data->dev_private;
1147         rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1148                                            priv->sh->dv_mark_mask);
1149         rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1150         struct rte_flow_item item = {
1151                 .spec = &data,
1152                 .mask = &mask,
1153         };
1154         struct field_modify_info reg_c_x[] = {
1155                 [1] = {0, 0, 0},
1156         };
1157         int reg;
1158
1159         if (!mask)
1160                 return rte_flow_error_set(error, EINVAL,
1161                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1162                                           NULL, "zero mark action mask");
1163         reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1164         if (reg < 0)
1165                 return reg;
1166         MLX5_ASSERT(reg > 0);
1167         if (reg == REG_C_0) {
1168                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1169                 uint32_t shl_c0 = rte_bsf32(msk_c0);
1170
1171                 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1172                 mask = rte_cpu_to_be_32(mask) & msk_c0;
1173                 mask = rte_cpu_to_be_32(mask << shl_c0);
1174         }
1175         reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1176         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1177                                              MLX5_MODIFICATION_TYPE_SET, error);
1178 }
1179
1180 /**
1181  * Get metadata register index for specified steering domain.
1182  *
1183  * @param[in] dev
1184  *   Pointer to the rte_eth_dev structure.
1185  * @param[in] attr
1186  *   Attributes of flow to determine steering domain.
1187  * @param[out] error
1188  *   Pointer to the error structure.
1189  *
1190  * @return
1191  *   positive index on success, a negative errno value otherwise
1192  *   and rte_errno is set.
1193  */
1194 static enum modify_reg
1195 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1196                          const struct rte_flow_attr *attr,
1197                          struct rte_flow_error *error)
1198 {
1199         int reg =
1200                 mlx5_flow_get_reg_id(dev, attr->transfer ?
1201                                           MLX5_METADATA_FDB :
1202                                             attr->egress ?
1203                                             MLX5_METADATA_TX :
1204                                             MLX5_METADATA_RX, 0, error);
1205         if (reg < 0)
1206                 return rte_flow_error_set(error,
1207                                           ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1208                                           NULL, "unavailable "
1209                                           "metadata register");
1210         return reg;
1211 }
1212
1213 /**
1214  * Convert SET_META action to DV specification.
1215  *
1216  * @param[in] dev
1217  *   Pointer to the rte_eth_dev structure.
1218  * @param[in,out] resource
1219  *   Pointer to the modify-header resource.
1220  * @param[in] attr
1221  *   Attributes of flow that includes this item.
1222  * @param[in] conf
1223  *   Pointer to action specification.
1224  * @param[out] error
1225  *   Pointer to the error structure.
1226  *
1227  * @return
1228  *   0 on success, a negative errno value otherwise and rte_errno is set.
1229  */
1230 static int
1231 flow_dv_convert_action_set_meta
1232                         (struct rte_eth_dev *dev,
1233                          struct mlx5_flow_dv_modify_hdr_resource *resource,
1234                          const struct rte_flow_attr *attr,
1235                          const struct rte_flow_action_set_meta *conf,
1236                          struct rte_flow_error *error)
1237 {
1238         uint32_t data = conf->data;
1239         uint32_t mask = conf->mask;
1240         struct rte_flow_item item = {
1241                 .spec = &data,
1242                 .mask = &mask,
1243         };
1244         struct field_modify_info reg_c_x[] = {
1245                 [1] = {0, 0, 0},
1246         };
1247         int reg = flow_dv_get_metadata_reg(dev, attr, error);
1248
1249         if (reg < 0)
1250                 return reg;
1251         /*
1252          * In datapath code there is no endianness
1253          * coversions for perfromance reasons, all
1254          * pattern conversions are done in rte_flow.
1255          */
1256         if (reg == REG_C_0) {
1257                 struct mlx5_priv *priv = dev->data->dev_private;
1258                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1259                 uint32_t shl_c0;
1260
1261                 MLX5_ASSERT(msk_c0);
1262 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1263                 shl_c0 = rte_bsf32(msk_c0);
1264 #else
1265                 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1266 #endif
1267                 mask <<= shl_c0;
1268                 data <<= shl_c0;
1269                 MLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1270         }
1271         reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1272         /* The routine expects parameters in memory as big-endian ones. */
1273         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1274                                              MLX5_MODIFICATION_TYPE_SET, error);
1275 }
1276
1277 /**
1278  * Convert modify-header set IPv4 DSCP action to DV specification.
1279  *
1280  * @param[in,out] resource
1281  *   Pointer to the modify-header resource.
1282  * @param[in] action
1283  *   Pointer to action specification.
1284  * @param[out] error
1285  *   Pointer to the error structure.
1286  *
1287  * @return
1288  *   0 on success, a negative errno value otherwise and rte_errno is set.
1289  */
1290 static int
1291 flow_dv_convert_action_modify_ipv4_dscp
1292                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1293                          const struct rte_flow_action *action,
1294                          struct rte_flow_error *error)
1295 {
1296         const struct rte_flow_action_set_dscp *conf =
1297                 (const struct rte_flow_action_set_dscp *)(action->conf);
1298         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1299         struct rte_flow_item_ipv4 ipv4;
1300         struct rte_flow_item_ipv4 ipv4_mask;
1301
1302         memset(&ipv4, 0, sizeof(ipv4));
1303         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1304         ipv4.hdr.type_of_service = conf->dscp;
1305         ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1306         item.spec = &ipv4;
1307         item.mask = &ipv4_mask;
1308         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1309                                              MLX5_MODIFICATION_TYPE_SET, error);
1310 }
1311
1312 /**
1313  * Convert modify-header set IPv6 DSCP action to DV specification.
1314  *
1315  * @param[in,out] resource
1316  *   Pointer to the modify-header resource.
1317  * @param[in] action
1318  *   Pointer to action specification.
1319  * @param[out] error
1320  *   Pointer to the error structure.
1321  *
1322  * @return
1323  *   0 on success, a negative errno value otherwise and rte_errno is set.
1324  */
1325 static int
1326 flow_dv_convert_action_modify_ipv6_dscp
1327                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1328                          const struct rte_flow_action *action,
1329                          struct rte_flow_error *error)
1330 {
1331         const struct rte_flow_action_set_dscp *conf =
1332                 (const struct rte_flow_action_set_dscp *)(action->conf);
1333         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1334         struct rte_flow_item_ipv6 ipv6;
1335         struct rte_flow_item_ipv6 ipv6_mask;
1336
1337         memset(&ipv6, 0, sizeof(ipv6));
1338         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1339         /*
1340          * Even though the DSCP bits offset of IPv6 is not byte aligned,
1341          * rdma-core only accept the DSCP bits byte aligned start from
1342          * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1343          * bits in IPv6 case as rdma-core requires byte aligned value.
1344          */
1345         ipv6.hdr.vtc_flow = conf->dscp;
1346         ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1347         item.spec = &ipv6;
1348         item.mask = &ipv6_mask;
1349         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1350                                              MLX5_MODIFICATION_TYPE_SET, error);
1351 }
1352
1353 /**
1354  * Validate MARK item.
1355  *
1356  * @param[in] dev
1357  *   Pointer to the rte_eth_dev structure.
1358  * @param[in] item
1359  *   Item specification.
1360  * @param[in] attr
1361  *   Attributes of flow that includes this item.
1362  * @param[out] error
1363  *   Pointer to error structure.
1364  *
1365  * @return
1366  *   0 on success, a negative errno value otherwise and rte_errno is set.
1367  */
1368 static int
1369 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1370                            const struct rte_flow_item *item,
1371                            const struct rte_flow_attr *attr __rte_unused,
1372                            struct rte_flow_error *error)
1373 {
1374         struct mlx5_priv *priv = dev->data->dev_private;
1375         struct mlx5_dev_config *config = &priv->config;
1376         const struct rte_flow_item_mark *spec = item->spec;
1377         const struct rte_flow_item_mark *mask = item->mask;
1378         const struct rte_flow_item_mark nic_mask = {
1379                 .id = priv->sh->dv_mark_mask,
1380         };
1381         int ret;
1382
1383         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1384                 return rte_flow_error_set(error, ENOTSUP,
1385                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1386                                           "extended metadata feature"
1387                                           " isn't enabled");
1388         if (!mlx5_flow_ext_mreg_supported(dev))
1389                 return rte_flow_error_set(error, ENOTSUP,
1390                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1391                                           "extended metadata register"
1392                                           " isn't supported");
1393         if (!nic_mask.id)
1394                 return rte_flow_error_set(error, ENOTSUP,
1395                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1396                                           "extended metadata register"
1397                                           " isn't available");
1398         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1399         if (ret < 0)
1400                 return ret;
1401         if (!spec)
1402                 return rte_flow_error_set(error, EINVAL,
1403                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1404                                           item->spec,
1405                                           "data cannot be empty");
1406         if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1407                 return rte_flow_error_set(error, EINVAL,
1408                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1409                                           &spec->id,
1410                                           "mark id exceeds the limit");
1411         if (!mask)
1412                 mask = &nic_mask;
1413         if (!mask->id)
1414                 return rte_flow_error_set(error, EINVAL,
1415                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1416                                         "mask cannot be zero");
1417
1418         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1419                                         (const uint8_t *)&nic_mask,
1420                                         sizeof(struct rte_flow_item_mark),
1421                                         error);
1422         if (ret < 0)
1423                 return ret;
1424         return 0;
1425 }
1426
1427 /**
1428  * Validate META item.
1429  *
1430  * @param[in] dev
1431  *   Pointer to the rte_eth_dev structure.
1432  * @param[in] item
1433  *   Item specification.
1434  * @param[in] attr
1435  *   Attributes of flow that includes this item.
1436  * @param[out] error
1437  *   Pointer to error structure.
1438  *
1439  * @return
1440  *   0 on success, a negative errno value otherwise and rte_errno is set.
1441  */
1442 static int
1443 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1444                            const struct rte_flow_item *item,
1445                            const struct rte_flow_attr *attr,
1446                            struct rte_flow_error *error)
1447 {
1448         struct mlx5_priv *priv = dev->data->dev_private;
1449         struct mlx5_dev_config *config = &priv->config;
1450         const struct rte_flow_item_meta *spec = item->spec;
1451         const struct rte_flow_item_meta *mask = item->mask;
1452         struct rte_flow_item_meta nic_mask = {
1453                 .data = UINT32_MAX
1454         };
1455         int reg;
1456         int ret;
1457
1458         if (!spec)
1459                 return rte_flow_error_set(error, EINVAL,
1460                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1461                                           item->spec,
1462                                           "data cannot be empty");
1463         if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1464                 if (!mlx5_flow_ext_mreg_supported(dev))
1465                         return rte_flow_error_set(error, ENOTSUP,
1466                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1467                                           "extended metadata register"
1468                                           " isn't supported");
1469                 reg = flow_dv_get_metadata_reg(dev, attr, error);
1470                 if (reg < 0)
1471                         return reg;
1472                 if (reg == REG_B)
1473                         return rte_flow_error_set(error, ENOTSUP,
1474                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1475                                           "match on reg_b "
1476                                           "isn't supported");
1477                 if (reg != REG_A)
1478                         nic_mask.data = priv->sh->dv_meta_mask;
1479         } else if (attr->transfer) {
1480                 return rte_flow_error_set(error, ENOTSUP,
1481                                         RTE_FLOW_ERROR_TYPE_ITEM, item,
1482                                         "extended metadata feature "
1483                                         "should be enabled when "
1484                                         "meta item is requested "
1485                                         "with e-switch mode ");
1486         }
1487         if (!mask)
1488                 mask = &rte_flow_item_meta_mask;
1489         if (!mask->data)
1490                 return rte_flow_error_set(error, EINVAL,
1491                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1492                                         "mask cannot be zero");
1493
1494         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1495                                         (const uint8_t *)&nic_mask,
1496                                         sizeof(struct rte_flow_item_meta),
1497                                         error);
1498         return ret;
1499 }
1500
1501 /**
1502  * Validate TAG item.
1503  *
1504  * @param[in] dev
1505  *   Pointer to the rte_eth_dev structure.
1506  * @param[in] item
1507  *   Item specification.
1508  * @param[in] attr
1509  *   Attributes of flow that includes this item.
1510  * @param[out] error
1511  *   Pointer to error structure.
1512  *
1513  * @return
1514  *   0 on success, a negative errno value otherwise and rte_errno is set.
1515  */
1516 static int
1517 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
1518                           const struct rte_flow_item *item,
1519                           const struct rte_flow_attr *attr __rte_unused,
1520                           struct rte_flow_error *error)
1521 {
1522         const struct rte_flow_item_tag *spec = item->spec;
1523         const struct rte_flow_item_tag *mask = item->mask;
1524         const struct rte_flow_item_tag nic_mask = {
1525                 .data = RTE_BE32(UINT32_MAX),
1526                 .index = 0xff,
1527         };
1528         int ret;
1529
1530         if (!mlx5_flow_ext_mreg_supported(dev))
1531                 return rte_flow_error_set(error, ENOTSUP,
1532                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1533                                           "extensive metadata register"
1534                                           " isn't supported");
1535         if (!spec)
1536                 return rte_flow_error_set(error, EINVAL,
1537                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1538                                           item->spec,
1539                                           "data cannot be empty");
1540         if (!mask)
1541                 mask = &rte_flow_item_tag_mask;
1542         if (!mask->data)
1543                 return rte_flow_error_set(error, EINVAL,
1544                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1545                                         "mask cannot be zero");
1546
1547         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1548                                         (const uint8_t *)&nic_mask,
1549                                         sizeof(struct rte_flow_item_tag),
1550                                         error);
1551         if (ret < 0)
1552                 return ret;
1553         if (mask->index != 0xff)
1554                 return rte_flow_error_set(error, EINVAL,
1555                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1556                                           "partial mask for tag index"
1557                                           " is not supported");
1558         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
1559         if (ret < 0)
1560                 return ret;
1561         MLX5_ASSERT(ret != REG_NON);
1562         return 0;
1563 }
1564
1565 /**
1566  * Validate vport item.
1567  *
1568  * @param[in] dev
1569  *   Pointer to the rte_eth_dev structure.
1570  * @param[in] item
1571  *   Item specification.
1572  * @param[in] attr
1573  *   Attributes of flow that includes this item.
1574  * @param[in] item_flags
1575  *   Bit-fields that holds the items detected until now.
1576  * @param[out] error
1577  *   Pointer to error structure.
1578  *
1579  * @return
1580  *   0 on success, a negative errno value otherwise and rte_errno is set.
1581  */
1582 static int
1583 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
1584                               const struct rte_flow_item *item,
1585                               const struct rte_flow_attr *attr,
1586                               uint64_t item_flags,
1587                               struct rte_flow_error *error)
1588 {
1589         const struct rte_flow_item_port_id *spec = item->spec;
1590         const struct rte_flow_item_port_id *mask = item->mask;
1591         const struct rte_flow_item_port_id switch_mask = {
1592                         .id = 0xffffffff,
1593         };
1594         struct mlx5_priv *esw_priv;
1595         struct mlx5_priv *dev_priv;
1596         int ret;
1597
1598         if (!attr->transfer)
1599                 return rte_flow_error_set(error, EINVAL,
1600                                           RTE_FLOW_ERROR_TYPE_ITEM,
1601                                           NULL,
1602                                           "match on port id is valid only"
1603                                           " when transfer flag is enabled");
1604         if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
1605                 return rte_flow_error_set(error, ENOTSUP,
1606                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1607                                           "multiple source ports are not"
1608                                           " supported");
1609         if (!mask)
1610                 mask = &switch_mask;
1611         if (mask->id != 0xffffffff)
1612                 return rte_flow_error_set(error, ENOTSUP,
1613                                            RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1614                                            mask,
1615                                            "no support for partial mask on"
1616                                            " \"id\" field");
1617         ret = mlx5_flow_item_acceptable
1618                                 (item, (const uint8_t *)mask,
1619                                  (const uint8_t *)&rte_flow_item_port_id_mask,
1620                                  sizeof(struct rte_flow_item_port_id),
1621                                  error);
1622         if (ret)
1623                 return ret;
1624         if (!spec)
1625                 return 0;
1626         esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
1627         if (!esw_priv)
1628                 return rte_flow_error_set(error, rte_errno,
1629                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1630                                           "failed to obtain E-Switch info for"
1631                                           " port");
1632         dev_priv = mlx5_dev_to_eswitch_info(dev);
1633         if (!dev_priv)
1634                 return rte_flow_error_set(error, rte_errno,
1635                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1636                                           NULL,
1637                                           "failed to obtain E-Switch info");
1638         if (esw_priv->domain_id != dev_priv->domain_id)
1639                 return rte_flow_error_set(error, EINVAL,
1640                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1641                                           "cannot match on a port from a"
1642                                           " different E-Switch");
1643         return 0;
1644 }
1645
1646 /**
1647  * Validate VLAN item.
1648  *
1649  * @param[in] item
1650  *   Item specification.
1651  * @param[in] item_flags
1652  *   Bit-fields that holds the items detected until now.
1653  * @param[in] dev
1654  *   Ethernet device flow is being created on.
1655  * @param[out] error
1656  *   Pointer to error structure.
1657  *
1658  * @return
1659  *   0 on success, a negative errno value otherwise and rte_errno is set.
1660  */
1661 static int
1662 flow_dv_validate_item_vlan(const struct rte_flow_item *item,
1663                            uint64_t item_flags,
1664                            struct rte_eth_dev *dev,
1665                            struct rte_flow_error *error)
1666 {
1667         const struct rte_flow_item_vlan *mask = item->mask;
1668         const struct rte_flow_item_vlan nic_mask = {
1669                 .tci = RTE_BE16(UINT16_MAX),
1670                 .inner_type = RTE_BE16(UINT16_MAX),
1671         };
1672         const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
1673         int ret;
1674         const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 |
1675                                         MLX5_FLOW_LAYER_INNER_L4) :
1676                                        (MLX5_FLOW_LAYER_OUTER_L3 |
1677                                         MLX5_FLOW_LAYER_OUTER_L4);
1678         const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
1679                                         MLX5_FLOW_LAYER_OUTER_VLAN;
1680
1681         if (item_flags & vlanm)
1682                 return rte_flow_error_set(error, EINVAL,
1683                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1684                                           "multiple VLAN layers not supported");
1685         else if ((item_flags & l34m) != 0)
1686                 return rte_flow_error_set(error, EINVAL,
1687                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1688                                           "VLAN cannot follow L3/L4 layer");
1689         if (!mask)
1690                 mask = &rte_flow_item_vlan_mask;
1691         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1692                                         (const uint8_t *)&nic_mask,
1693                                         sizeof(struct rte_flow_item_vlan),
1694                                         error);
1695         if (ret)
1696                 return ret;
1697         if (!tunnel && mask->tci != RTE_BE16(0x0fff)) {
1698                 struct mlx5_priv *priv = dev->data->dev_private;
1699
1700                 if (priv->vmwa_context) {
1701                         /*
1702                          * Non-NULL context means we have a virtual machine
1703                          * and SR-IOV enabled, we have to create VLAN interface
1704                          * to make hypervisor to setup E-Switch vport
1705                          * context correctly. We avoid creating the multiple
1706                          * VLAN interfaces, so we cannot support VLAN tag mask.
1707                          */
1708                         return rte_flow_error_set(error, EINVAL,
1709                                                   RTE_FLOW_ERROR_TYPE_ITEM,
1710                                                   item,
1711                                                   "VLAN tag mask is not"
1712                                                   " supported in virtual"
1713                                                   " environment");
1714                 }
1715         }
1716         return 0;
1717 }
1718
1719 /*
1720  * GTP flags are contained in 1 byte of the format:
1721  * -------------------------------------------
1722  * | bit   | 0 - 2   | 3  | 4   | 5 | 6 | 7  |
1723  * |-----------------------------------------|
1724  * | value | Version | PT | Res | E | S | PN |
1725  * -------------------------------------------
1726  *
1727  * Matching is supported only for GTP flags E, S, PN.
1728  */
1729 #define MLX5_GTP_FLAGS_MASK     0x07
1730
1731 /**
1732  * Validate GTP item.
1733  *
1734  * @param[in] dev
1735  *   Pointer to the rte_eth_dev structure.
1736  * @param[in] item
1737  *   Item specification.
1738  * @param[in] item_flags
1739  *   Bit-fields that holds the items detected until now.
1740  * @param[out] error
1741  *   Pointer to error structure.
1742  *
1743  * @return
1744  *   0 on success, a negative errno value otherwise and rte_errno is set.
1745  */
1746 static int
1747 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
1748                           const struct rte_flow_item *item,
1749                           uint64_t item_flags,
1750                           struct rte_flow_error *error)
1751 {
1752         struct mlx5_priv *priv = dev->data->dev_private;
1753         const struct rte_flow_item_gtp *spec = item->spec;
1754         const struct rte_flow_item_gtp *mask = item->mask;
1755         const struct rte_flow_item_gtp nic_mask = {
1756                 .v_pt_rsv_flags = MLX5_GTP_FLAGS_MASK,
1757                 .msg_type = 0xff,
1758                 .teid = RTE_BE32(0xffffffff),
1759         };
1760
1761         if (!priv->config.hca_attr.tunnel_stateless_gtp)
1762                 return rte_flow_error_set(error, ENOTSUP,
1763                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1764                                           "GTP support is not enabled");
1765         if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
1766                 return rte_flow_error_set(error, ENOTSUP,
1767                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1768                                           "multiple tunnel layers not"
1769                                           " supported");
1770         if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
1771                 return rte_flow_error_set(error, EINVAL,
1772                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1773                                           "no outer UDP layer found");
1774         if (!mask)
1775                 mask = &rte_flow_item_gtp_mask;
1776         if (spec && spec->v_pt_rsv_flags & ~MLX5_GTP_FLAGS_MASK)
1777                 return rte_flow_error_set(error, ENOTSUP,
1778                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1779                                           "Match is supported for GTP"
1780                                           " flags only");
1781         return mlx5_flow_item_acceptable
1782                 (item, (const uint8_t *)mask,
1783                  (const uint8_t *)&nic_mask,
1784                  sizeof(struct rte_flow_item_gtp),
1785                  error);
1786 }
1787
1788 /**
1789  * Validate the pop VLAN action.
1790  *
1791  * @param[in] dev
1792  *   Pointer to the rte_eth_dev structure.
1793  * @param[in] action_flags
1794  *   Holds the actions detected until now.
1795  * @param[in] action
1796  *   Pointer to the pop vlan action.
1797  * @param[in] item_flags
1798  *   The items found in this flow rule.
1799  * @param[in] attr
1800  *   Pointer to flow attributes.
1801  * @param[out] error
1802  *   Pointer to error structure.
1803  *
1804  * @return
1805  *   0 on success, a negative errno value otherwise and rte_errno is set.
1806  */
1807 static int
1808 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
1809                                  uint64_t action_flags,
1810                                  const struct rte_flow_action *action,
1811                                  uint64_t item_flags,
1812                                  const struct rte_flow_attr *attr,
1813                                  struct rte_flow_error *error)
1814 {
1815         const struct mlx5_priv *priv = dev->data->dev_private;
1816
1817         (void)action;
1818         (void)attr;
1819         if (!priv->sh->pop_vlan_action)
1820                 return rte_flow_error_set(error, ENOTSUP,
1821                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1822                                           NULL,
1823                                           "pop vlan action is not supported");
1824         if (attr->egress)
1825                 return rte_flow_error_set(error, ENOTSUP,
1826                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1827                                           NULL,
1828                                           "pop vlan action not supported for "
1829                                           "egress");
1830         if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
1831                 return rte_flow_error_set(error, ENOTSUP,
1832                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1833                                           "no support for multiple VLAN "
1834                                           "actions");
1835         /* Pop VLAN with preceding Decap requires inner header with VLAN. */
1836         if ((action_flags & MLX5_FLOW_ACTION_DECAP) &&
1837             !(item_flags & MLX5_FLOW_LAYER_INNER_VLAN))
1838                 return rte_flow_error_set(error, ENOTSUP,
1839                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1840                                           NULL,
1841                                           "cannot pop vlan after decap without "
1842                                           "match on inner vlan in the flow");
1843         /* Pop VLAN without preceding Decap requires outer header with VLAN. */
1844         if (!(action_flags & MLX5_FLOW_ACTION_DECAP) &&
1845             !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1846                 return rte_flow_error_set(error, ENOTSUP,
1847                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1848                                           NULL,
1849                                           "cannot pop vlan without a "
1850                                           "match on (outer) vlan in the flow");
1851         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1852                 return rte_flow_error_set(error, EINVAL,
1853                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1854                                           "wrong action order, port_id should "
1855                                           "be after pop VLAN action");
1856         if (!attr->transfer && priv->representor)
1857                 return rte_flow_error_set(error, ENOTSUP,
1858                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1859                                           "pop vlan action for VF representor "
1860                                           "not supported on NIC table");
1861         return 0;
1862 }
1863
1864 /**
1865  * Get VLAN default info from vlan match info.
1866  *
1867  * @param[in] items
1868  *   the list of item specifications.
1869  * @param[out] vlan
1870  *   pointer VLAN info to fill to.
1871  *
1872  * @return
1873  *   0 on success, a negative errno value otherwise and rte_errno is set.
1874  */
1875 static void
1876 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
1877                                   struct rte_vlan_hdr *vlan)
1878 {
1879         const struct rte_flow_item_vlan nic_mask = {
1880                 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
1881                                 MLX5DV_FLOW_VLAN_VID_MASK),
1882                 .inner_type = RTE_BE16(0xffff),
1883         };
1884
1885         if (items == NULL)
1886                 return;
1887         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
1888                 int type = items->type;
1889
1890                 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
1891                     type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
1892                         break;
1893         }
1894         if (items->type != RTE_FLOW_ITEM_TYPE_END) {
1895                 const struct rte_flow_item_vlan *vlan_m = items->mask;
1896                 const struct rte_flow_item_vlan *vlan_v = items->spec;
1897
1898                 /* If VLAN item in pattern doesn't contain data, return here. */
1899                 if (!vlan_v)
1900                         return;
1901                 if (!vlan_m)
1902                         vlan_m = &nic_mask;
1903                 /* Only full match values are accepted */
1904                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
1905                      MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
1906                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
1907                         vlan->vlan_tci |=
1908                                 rte_be_to_cpu_16(vlan_v->tci &
1909                                                  MLX5DV_FLOW_VLAN_PCP_MASK_BE);
1910                 }
1911                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
1912                      MLX5DV_FLOW_VLAN_VID_MASK_BE) {
1913                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
1914                         vlan->vlan_tci |=
1915                                 rte_be_to_cpu_16(vlan_v->tci &
1916                                                  MLX5DV_FLOW_VLAN_VID_MASK_BE);
1917                 }
1918                 if (vlan_m->inner_type == nic_mask.inner_type)
1919                         vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
1920                                                            vlan_m->inner_type);
1921         }
1922 }
1923
1924 /**
1925  * Validate the push VLAN action.
1926  *
1927  * @param[in] dev
1928  *   Pointer to the rte_eth_dev structure.
1929  * @param[in] action_flags
1930  *   Holds the actions detected until now.
1931  * @param[in] item_flags
1932  *   The items found in this flow rule.
1933  * @param[in] action
1934  *   Pointer to the action structure.
1935  * @param[in] attr
1936  *   Pointer to flow attributes
1937  * @param[out] error
1938  *   Pointer to error structure.
1939  *
1940  * @return
1941  *   0 on success, a negative errno value otherwise and rte_errno is set.
1942  */
1943 static int
1944 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
1945                                   uint64_t action_flags,
1946                                   const struct rte_flow_item_vlan *vlan_m,
1947                                   const struct rte_flow_action *action,
1948                                   const struct rte_flow_attr *attr,
1949                                   struct rte_flow_error *error)
1950 {
1951         const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
1952         const struct mlx5_priv *priv = dev->data->dev_private;
1953
1954         if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
1955             push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
1956                 return rte_flow_error_set(error, EINVAL,
1957                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1958                                           "invalid vlan ethertype");
1959         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1960                 return rte_flow_error_set(error, EINVAL,
1961                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1962                                           "wrong action order, port_id should "
1963                                           "be after push VLAN");
1964         if (!attr->transfer && priv->representor)
1965                 return rte_flow_error_set(error, ENOTSUP,
1966                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1967                                           "push vlan action for VF representor "
1968                                           "not supported on NIC table");
1969         if (vlan_m &&
1970             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
1971             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
1972                 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
1973             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
1974             !(mlx5_flow_find_action
1975                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
1976                 return rte_flow_error_set(error, EINVAL,
1977                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1978                                           "not full match mask on VLAN PCP and "
1979                                           "there is no of_set_vlan_pcp action, "
1980                                           "push VLAN action cannot figure out "
1981                                           "PCP value");
1982         if (vlan_m &&
1983             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
1984             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
1985                 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
1986             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
1987             !(mlx5_flow_find_action
1988                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
1989                 return rte_flow_error_set(error, EINVAL,
1990                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1991                                           "not full match mask on VLAN VID and "
1992                                           "there is no of_set_vlan_vid action, "
1993                                           "push VLAN action cannot figure out "
1994                                           "VID value");
1995         (void)attr;
1996         return 0;
1997 }
1998
1999 /**
2000  * Validate the set VLAN PCP.
2001  *
2002  * @param[in] action_flags
2003  *   Holds the actions detected until now.
2004  * @param[in] actions
2005  *   Pointer to the list of actions remaining in the flow rule.
2006  * @param[out] error
2007  *   Pointer to error structure.
2008  *
2009  * @return
2010  *   0 on success, a negative errno value otherwise and rte_errno is set.
2011  */
2012 static int
2013 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
2014                                      const struct rte_flow_action actions[],
2015                                      struct rte_flow_error *error)
2016 {
2017         const struct rte_flow_action *action = actions;
2018         const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
2019
2020         if (conf->vlan_pcp > 7)
2021                 return rte_flow_error_set(error, EINVAL,
2022                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2023                                           "VLAN PCP value is too big");
2024         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
2025                 return rte_flow_error_set(error, ENOTSUP,
2026                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2027                                           "set VLAN PCP action must follow "
2028                                           "the push VLAN action");
2029         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
2030                 return rte_flow_error_set(error, ENOTSUP,
2031                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2032                                           "Multiple VLAN PCP modification are "
2033                                           "not supported");
2034         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2035                 return rte_flow_error_set(error, EINVAL,
2036                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2037                                           "wrong action order, port_id should "
2038                                           "be after set VLAN PCP");
2039         return 0;
2040 }
2041
2042 /**
2043  * Validate the set VLAN VID.
2044  *
2045  * @param[in] item_flags
2046  *   Holds the items detected in this rule.
2047  * @param[in] action_flags
2048  *   Holds the actions detected until now.
2049  * @param[in] actions
2050  *   Pointer to the list of actions remaining in the flow rule.
2051  * @param[out] error
2052  *   Pointer to error structure.
2053  *
2054  * @return
2055  *   0 on success, a negative errno value otherwise and rte_errno is set.
2056  */
2057 static int
2058 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
2059                                      uint64_t action_flags,
2060                                      const struct rte_flow_action actions[],
2061                                      struct rte_flow_error *error)
2062 {
2063         const struct rte_flow_action *action = actions;
2064         const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
2065
2066         if (rte_be_to_cpu_16(conf->vlan_vid) > 0xFFE)
2067                 return rte_flow_error_set(error, EINVAL,
2068                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2069                                           "VLAN VID value is too big");
2070         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
2071             !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2072                 return rte_flow_error_set(error, ENOTSUP,
2073                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2074                                           "set VLAN VID action must follow push"
2075                                           " VLAN action or match on VLAN item");
2076         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
2077                 return rte_flow_error_set(error, ENOTSUP,
2078                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2079                                           "Multiple VLAN VID modifications are "
2080                                           "not supported");
2081         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2082                 return rte_flow_error_set(error, EINVAL,
2083                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2084                                           "wrong action order, port_id should "
2085                                           "be after set VLAN VID");
2086         return 0;
2087 }
2088
2089 /*
2090  * Validate the FLAG action.
2091  *
2092  * @param[in] dev
2093  *   Pointer to the rte_eth_dev structure.
2094  * @param[in] action_flags
2095  *   Holds the actions detected until now.
2096  * @param[in] attr
2097  *   Pointer to flow attributes
2098  * @param[out] error
2099  *   Pointer to error structure.
2100  *
2101  * @return
2102  *   0 on success, a negative errno value otherwise and rte_errno is set.
2103  */
2104 static int
2105 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
2106                              uint64_t action_flags,
2107                              const struct rte_flow_attr *attr,
2108                              struct rte_flow_error *error)
2109 {
2110         struct mlx5_priv *priv = dev->data->dev_private;
2111         struct mlx5_dev_config *config = &priv->config;
2112         int ret;
2113
2114         /* Fall back if no extended metadata register support. */
2115         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2116                 return mlx5_flow_validate_action_flag(action_flags, attr,
2117                                                       error);
2118         /* Extensive metadata mode requires registers. */
2119         if (!mlx5_flow_ext_mreg_supported(dev))
2120                 return rte_flow_error_set(error, ENOTSUP,
2121                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2122                                           "no metadata registers "
2123                                           "to support flag action");
2124         if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
2125                 return rte_flow_error_set(error, ENOTSUP,
2126                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2127                                           "extended metadata register"
2128                                           " isn't available");
2129         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2130         if (ret < 0)
2131                 return ret;
2132         MLX5_ASSERT(ret > 0);
2133         if (action_flags & MLX5_FLOW_ACTION_MARK)
2134                 return rte_flow_error_set(error, EINVAL,
2135                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2136                                           "can't mark and flag in same flow");
2137         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2138                 return rte_flow_error_set(error, EINVAL,
2139                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2140                                           "can't have 2 flag"
2141                                           " actions in same flow");
2142         return 0;
2143 }
2144
2145 /**
2146  * Validate MARK action.
2147  *
2148  * @param[in] dev
2149  *   Pointer to the rte_eth_dev structure.
2150  * @param[in] action
2151  *   Pointer to action.
2152  * @param[in] action_flags
2153  *   Holds the actions detected until now.
2154  * @param[in] attr
2155  *   Pointer to flow attributes
2156  * @param[out] error
2157  *   Pointer to error structure.
2158  *
2159  * @return
2160  *   0 on success, a negative errno value otherwise and rte_errno is set.
2161  */
2162 static int
2163 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
2164                              const struct rte_flow_action *action,
2165                              uint64_t action_flags,
2166                              const struct rte_flow_attr *attr,
2167                              struct rte_flow_error *error)
2168 {
2169         struct mlx5_priv *priv = dev->data->dev_private;
2170         struct mlx5_dev_config *config = &priv->config;
2171         const struct rte_flow_action_mark *mark = action->conf;
2172         int ret;
2173
2174         /* Fall back if no extended metadata register support. */
2175         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2176                 return mlx5_flow_validate_action_mark(action, action_flags,
2177                                                       attr, error);
2178         /* Extensive metadata mode requires registers. */
2179         if (!mlx5_flow_ext_mreg_supported(dev))
2180                 return rte_flow_error_set(error, ENOTSUP,
2181                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2182                                           "no metadata registers "
2183                                           "to support mark action");
2184         if (!priv->sh->dv_mark_mask)
2185                 return rte_flow_error_set(error, ENOTSUP,
2186                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2187                                           "extended metadata register"
2188                                           " isn't available");
2189         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2190         if (ret < 0)
2191                 return ret;
2192         MLX5_ASSERT(ret > 0);
2193         if (!mark)
2194                 return rte_flow_error_set(error, EINVAL,
2195                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2196                                           "configuration cannot be null");
2197         if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
2198                 return rte_flow_error_set(error, EINVAL,
2199                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2200                                           &mark->id,
2201                                           "mark id exceeds the limit");
2202         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2203                 return rte_flow_error_set(error, EINVAL,
2204                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2205                                           "can't flag and mark in same flow");
2206         if (action_flags & MLX5_FLOW_ACTION_MARK)
2207                 return rte_flow_error_set(error, EINVAL,
2208                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2209                                           "can't have 2 mark actions in same"
2210                                           " flow");
2211         return 0;
2212 }
2213
2214 /**
2215  * Validate SET_META action.
2216  *
2217  * @param[in] dev
2218  *   Pointer to the rte_eth_dev structure.
2219  * @param[in] action
2220  *   Pointer to the action structure.
2221  * @param[in] action_flags
2222  *   Holds the actions detected until now.
2223  * @param[in] attr
2224  *   Pointer to flow attributes
2225  * @param[out] error
2226  *   Pointer to error structure.
2227  *
2228  * @return
2229  *   0 on success, a negative errno value otherwise and rte_errno is set.
2230  */
2231 static int
2232 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
2233                                  const struct rte_flow_action *action,
2234                                  uint64_t action_flags __rte_unused,
2235                                  const struct rte_flow_attr *attr,
2236                                  struct rte_flow_error *error)
2237 {
2238         const struct rte_flow_action_set_meta *conf;
2239         uint32_t nic_mask = UINT32_MAX;
2240         int reg;
2241
2242         if (!mlx5_flow_ext_mreg_supported(dev))
2243                 return rte_flow_error_set(error, ENOTSUP,
2244                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2245                                           "extended metadata register"
2246                                           " isn't supported");
2247         reg = flow_dv_get_metadata_reg(dev, attr, error);
2248         if (reg < 0)
2249                 return reg;
2250         if (reg != REG_A && reg != REG_B) {
2251                 struct mlx5_priv *priv = dev->data->dev_private;
2252
2253                 nic_mask = priv->sh->dv_meta_mask;
2254         }
2255         if (!(action->conf))
2256                 return rte_flow_error_set(error, EINVAL,
2257                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2258                                           "configuration cannot be null");
2259         conf = (const struct rte_flow_action_set_meta *)action->conf;
2260         if (!conf->mask)
2261                 return rte_flow_error_set(error, EINVAL,
2262                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2263                                           "zero mask doesn't have any effect");
2264         if (conf->mask & ~nic_mask)
2265                 return rte_flow_error_set(error, EINVAL,
2266                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2267                                           "meta data must be within reg C0");
2268         return 0;
2269 }
2270
2271 /**
2272  * Validate SET_TAG action.
2273  *
2274  * @param[in] dev
2275  *   Pointer to the rte_eth_dev structure.
2276  * @param[in] action
2277  *   Pointer to the action structure.
2278  * @param[in] action_flags
2279  *   Holds the actions detected until now.
2280  * @param[in] attr
2281  *   Pointer to flow attributes
2282  * @param[out] error
2283  *   Pointer to error structure.
2284  *
2285  * @return
2286  *   0 on success, a negative errno value otherwise and rte_errno is set.
2287  */
2288 static int
2289 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
2290                                 const struct rte_flow_action *action,
2291                                 uint64_t action_flags,
2292                                 const struct rte_flow_attr *attr,
2293                                 struct rte_flow_error *error)
2294 {
2295         const struct rte_flow_action_set_tag *conf;
2296         const uint64_t terminal_action_flags =
2297                 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
2298                 MLX5_FLOW_ACTION_RSS;
2299         int ret;
2300
2301         if (!mlx5_flow_ext_mreg_supported(dev))
2302                 return rte_flow_error_set(error, ENOTSUP,
2303                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2304                                           "extensive metadata register"
2305                                           " isn't supported");
2306         if (!(action->conf))
2307                 return rte_flow_error_set(error, EINVAL,
2308                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2309                                           "configuration cannot be null");
2310         conf = (const struct rte_flow_action_set_tag *)action->conf;
2311         if (!conf->mask)
2312                 return rte_flow_error_set(error, EINVAL,
2313                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2314                                           "zero mask doesn't have any effect");
2315         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
2316         if (ret < 0)
2317                 return ret;
2318         if (!attr->transfer && attr->ingress &&
2319             (action_flags & terminal_action_flags))
2320                 return rte_flow_error_set(error, EINVAL,
2321                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2322                                           "set_tag has no effect"
2323                                           " with terminal actions");
2324         return 0;
2325 }
2326
2327 /**
2328  * Validate count action.
2329  *
2330  * @param[in] dev
2331  *   Pointer to rte_eth_dev structure.
2332  * @param[out] error
2333  *   Pointer to error structure.
2334  *
2335  * @return
2336  *   0 on success, a negative errno value otherwise and rte_errno is set.
2337  */
2338 static int
2339 flow_dv_validate_action_count(struct rte_eth_dev *dev,
2340                               struct rte_flow_error *error)
2341 {
2342         struct mlx5_priv *priv = dev->data->dev_private;
2343
2344         if (!priv->config.devx)
2345                 goto notsup_err;
2346 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
2347         return 0;
2348 #endif
2349 notsup_err:
2350         return rte_flow_error_set
2351                       (error, ENOTSUP,
2352                        RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2353                        NULL,
2354                        "count action not supported");
2355 }
2356
2357 /**
2358  * Validate the L2 encap action.
2359  *
2360  * @param[in] dev
2361  *   Pointer to the rte_eth_dev structure.
2362  * @param[in] action_flags
2363  *   Holds the actions detected until now.
2364  * @param[in] action
2365  *   Pointer to the action structure.
2366  * @param[in] attr
2367  *   Pointer to flow attributes.
2368  * @param[out] error
2369  *   Pointer to error structure.
2370  *
2371  * @return
2372  *   0 on success, a negative errno value otherwise and rte_errno is set.
2373  */
2374 static int
2375 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
2376                                  uint64_t action_flags,
2377                                  const struct rte_flow_action *action,
2378                                  const struct rte_flow_attr *attr,
2379                                  struct rte_flow_error *error)
2380 {
2381         const struct mlx5_priv *priv = dev->data->dev_private;
2382
2383         if (!(action->conf))
2384                 return rte_flow_error_set(error, EINVAL,
2385                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2386                                           "configuration cannot be null");
2387         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
2388                 return rte_flow_error_set(error, EINVAL,
2389                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2390                                           "can only have a single encap action "
2391                                           "in a flow");
2392         if (!attr->transfer && priv->representor)
2393                 return rte_flow_error_set(error, ENOTSUP,
2394                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2395                                           "encap action for VF representor "
2396                                           "not supported on NIC table");
2397         return 0;
2398 }
2399
2400 /**
2401  * Validate a decap action.
2402  *
2403  * @param[in] dev
2404  *   Pointer to the rte_eth_dev structure.
2405  * @param[in] action_flags
2406  *   Holds the actions detected until now.
2407  * @param[in] attr
2408  *   Pointer to flow attributes
2409  * @param[out] error
2410  *   Pointer to error structure.
2411  *
2412  * @return
2413  *   0 on success, a negative errno value otherwise and rte_errno is set.
2414  */
2415 static int
2416 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
2417                               uint64_t action_flags,
2418                               const struct rte_flow_attr *attr,
2419                               struct rte_flow_error *error)
2420 {
2421         const struct mlx5_priv *priv = dev->data->dev_private;
2422
2423         if (priv->config.hca_attr.scatter_fcs_w_decap_disable &&
2424             !priv->config.decap_en)
2425                 return rte_flow_error_set(error, ENOTSUP,
2426                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2427                                           "decap is not enabled");
2428         if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
2429                 return rte_flow_error_set(error, ENOTSUP,
2430                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2431                                           action_flags &
2432                                           MLX5_FLOW_ACTION_DECAP ? "can only "
2433                                           "have a single decap action" : "decap "
2434                                           "after encap is not supported");
2435         if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
2436                 return rte_flow_error_set(error, EINVAL,
2437                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2438                                           "can't have decap action after"
2439                                           " modify action");
2440         if (attr->egress)
2441                 return rte_flow_error_set(error, ENOTSUP,
2442                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2443                                           NULL,
2444                                           "decap action not supported for "
2445                                           "egress");
2446         if (!attr->transfer && priv->representor)
2447                 return rte_flow_error_set(error, ENOTSUP,
2448                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2449                                           "decap action for VF representor "
2450                                           "not supported on NIC table");
2451         return 0;
2452 }
2453
2454 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
2455
2456 /**
2457  * Validate the raw encap and decap actions.
2458  *
2459  * @param[in] dev
2460  *   Pointer to the rte_eth_dev structure.
2461  * @param[in] decap
2462  *   Pointer to the decap action.
2463  * @param[in] encap
2464  *   Pointer to the encap action.
2465  * @param[in] attr
2466  *   Pointer to flow attributes
2467  * @param[in/out] action_flags
2468  *   Holds the actions detected until now.
2469  * @param[out] actions_n
2470  *   pointer to the number of actions counter.
2471  * @param[out] error
2472  *   Pointer to error structure.
2473  *
2474  * @return
2475  *   0 on success, a negative errno value otherwise and rte_errno is set.
2476  */
2477 static int
2478 flow_dv_validate_action_raw_encap_decap
2479         (struct rte_eth_dev *dev,
2480          const struct rte_flow_action_raw_decap *decap,
2481          const struct rte_flow_action_raw_encap *encap,
2482          const struct rte_flow_attr *attr, uint64_t *action_flags,
2483          int *actions_n, struct rte_flow_error *error)
2484 {
2485         const struct mlx5_priv *priv = dev->data->dev_private;
2486         int ret;
2487
2488         if (encap && (!encap->size || !encap->data))
2489                 return rte_flow_error_set(error, EINVAL,
2490                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2491                                           "raw encap data cannot be empty");
2492         if (decap && encap) {
2493                 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
2494                     encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
2495                         /* L3 encap. */
2496                         decap = NULL;
2497                 else if (encap->size <=
2498                            MLX5_ENCAPSULATION_DECISION_SIZE &&
2499                            decap->size >
2500                            MLX5_ENCAPSULATION_DECISION_SIZE)
2501                         /* L3 decap. */
2502                         encap = NULL;
2503                 else if (encap->size >
2504                            MLX5_ENCAPSULATION_DECISION_SIZE &&
2505                            decap->size >
2506                            MLX5_ENCAPSULATION_DECISION_SIZE)
2507                         /* 2 L2 actions: encap and decap. */
2508                         ;
2509                 else
2510                         return rte_flow_error_set(error,
2511                                 ENOTSUP,
2512                                 RTE_FLOW_ERROR_TYPE_ACTION,
2513                                 NULL, "unsupported too small "
2514                                 "raw decap and too small raw "
2515                                 "encap combination");
2516         }
2517         if (decap) {
2518                 ret = flow_dv_validate_action_decap(dev, *action_flags, attr,
2519                                                     error);
2520                 if (ret < 0)
2521                         return ret;
2522                 *action_flags |= MLX5_FLOW_ACTION_DECAP;
2523                 ++(*actions_n);
2524         }
2525         if (encap) {
2526                 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
2527                         return rte_flow_error_set(error, ENOTSUP,
2528                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2529                                                   NULL,
2530                                                   "small raw encap size");
2531                 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
2532                         return rte_flow_error_set(error, EINVAL,
2533                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2534                                                   NULL,
2535                                                   "more than one encap action");
2536                 if (!attr->transfer && priv->representor)
2537                         return rte_flow_error_set
2538                                         (error, ENOTSUP,
2539                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2540                                          "encap action for VF representor "
2541                                          "not supported on NIC table");
2542                 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
2543                 ++(*actions_n);
2544         }
2545         return 0;
2546 }
2547
2548 /**
2549  * Match encap_decap resource.
2550  *
2551  * @param entry
2552  *   Pointer to exist resource entry object.
2553  * @param ctx
2554  *   Pointer to new encap_decap resource.
2555  *
2556  * @return
2557  *   0 on matching, -1 otherwise.
2558  */
2559 static int
2560 flow_dv_encap_decap_resource_match(struct mlx5_hlist_entry *entry, void *ctx)
2561 {
2562         struct mlx5_flow_dv_encap_decap_resource *resource;
2563         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2564
2565         resource = (struct mlx5_flow_dv_encap_decap_resource *)ctx;
2566         cache_resource = container_of(entry,
2567                                       struct mlx5_flow_dv_encap_decap_resource,
2568                                       entry);
2569         if (resource->entry.key == cache_resource->entry.key &&
2570             resource->reformat_type == cache_resource->reformat_type &&
2571             resource->ft_type == cache_resource->ft_type &&
2572             resource->flags == cache_resource->flags &&
2573             resource->size == cache_resource->size &&
2574             !memcmp((const void *)resource->buf,
2575                     (const void *)cache_resource->buf,
2576                     resource->size))
2577                 return 0;
2578         return -1;
2579 }
2580
2581 /**
2582  * Find existing encap/decap resource or create and register a new one.
2583  *
2584  * @param[in, out] dev
2585  *   Pointer to rte_eth_dev structure.
2586  * @param[in, out] resource
2587  *   Pointer to encap/decap resource.
2588  * @parm[in, out] dev_flow
2589  *   Pointer to the dev_flow.
2590  * @param[out] error
2591  *   pointer to error structure.
2592  *
2593  * @return
2594  *   0 on success otherwise -errno and errno is set.
2595  */
2596 static int
2597 flow_dv_encap_decap_resource_register
2598                         (struct rte_eth_dev *dev,
2599                          struct mlx5_flow_dv_encap_decap_resource *resource,
2600                          struct mlx5_flow *dev_flow,
2601                          struct rte_flow_error *error)
2602 {
2603         struct mlx5_priv *priv = dev->data->dev_private;
2604         struct mlx5_dev_ctx_shared *sh = priv->sh;
2605         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2606         struct mlx5dv_dr_domain *domain;
2607         struct mlx5_hlist_entry *entry;
2608         union mlx5_flow_encap_decap_key encap_decap_key = {
2609                 {
2610                         .ft_type = resource->ft_type,
2611                         .refmt_type = resource->reformat_type,
2612                         .buf_size = resource->size,
2613                         .table_level = !!dev_flow->dv.group,
2614                         .cksum = 0,
2615                 }
2616         };
2617         int ret;
2618
2619         resource->flags = dev_flow->dv.group ? 0 : 1;
2620         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2621                 domain = sh->fdb_domain;
2622         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2623                 domain = sh->rx_domain;
2624         else
2625                 domain = sh->tx_domain;
2626         encap_decap_key.cksum = __rte_raw_cksum(resource->buf,
2627                                                 resource->size, 0);
2628         resource->entry.key = encap_decap_key.v64;
2629         /* Lookup a matching resource from cache. */
2630         entry = mlx5_hlist_lookup_ex(sh->encaps_decaps, resource->entry.key,
2631                                      flow_dv_encap_decap_resource_match,
2632                                      (void *)resource);
2633         if (entry) {
2634                 cache_resource = container_of(entry,
2635                         struct mlx5_flow_dv_encap_decap_resource, entry);
2636                 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d++",
2637                         (void *)cache_resource,
2638                         rte_atomic32_read(&cache_resource->refcnt));
2639                 rte_atomic32_inc(&cache_resource->refcnt);
2640                 dev_flow->handle->dvh.rix_encap_decap = cache_resource->idx;
2641                 dev_flow->dv.encap_decap = cache_resource;
2642                 return 0;
2643         }
2644         /* Register new encap/decap resource. */
2645         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
2646                                        &dev_flow->handle->dvh.rix_encap_decap);
2647         if (!cache_resource)
2648                 return rte_flow_error_set(error, ENOMEM,
2649                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2650                                           "cannot allocate resource memory");
2651         *cache_resource = *resource;
2652         cache_resource->idx = dev_flow->handle->dvh.rix_encap_decap;
2653         ret = mlx5_flow_os_create_flow_action_packet_reformat
2654                                         (sh->ctx, domain, cache_resource,
2655                                          &cache_resource->action);
2656         if (ret) {
2657                 mlx5_free(cache_resource);
2658                 return rte_flow_error_set(error, ENOMEM,
2659                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2660                                           NULL, "cannot create action");
2661         }
2662         rte_atomic32_init(&cache_resource->refcnt);
2663         rte_atomic32_inc(&cache_resource->refcnt);
2664         if (mlx5_hlist_insert_ex(sh->encaps_decaps, &cache_resource->entry,
2665                                  flow_dv_encap_decap_resource_match,
2666                                  (void *)cache_resource)) {
2667                 claim_zero(mlx5_flow_os_destroy_flow_action
2668                                                 (cache_resource->action));
2669                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
2670                                 cache_resource->idx);
2671                 return rte_flow_error_set(error, EEXIST,
2672                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2673                                           NULL, "action exist");
2674         }
2675         dev_flow->dv.encap_decap = cache_resource;
2676         DRV_LOG(DEBUG, "new encap/decap resource %p: refcnt %d++",
2677                 (void *)cache_resource,
2678                 rte_atomic32_read(&cache_resource->refcnt));
2679         return 0;
2680 }
2681
2682 /**
2683  * Find existing table jump resource or create and register a new one.
2684  *
2685  * @param[in, out] dev
2686  *   Pointer to rte_eth_dev structure.
2687  * @param[in, out] tbl
2688  *   Pointer to flow table resource.
2689  * @parm[in, out] dev_flow
2690  *   Pointer to the dev_flow.
2691  * @param[out] error
2692  *   pointer to error structure.
2693  *
2694  * @return
2695  *   0 on success otherwise -errno and errno is set.
2696  */
2697 static int
2698 flow_dv_jump_tbl_resource_register
2699                         (struct rte_eth_dev *dev __rte_unused,
2700                          struct mlx5_flow_tbl_resource *tbl,
2701                          struct mlx5_flow *dev_flow,
2702                          struct rte_flow_error *error)
2703 {
2704         struct mlx5_flow_tbl_data_entry *tbl_data =
2705                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
2706         int cnt, ret;
2707
2708         MLX5_ASSERT(tbl);
2709         cnt = rte_atomic32_read(&tbl_data->jump.refcnt);
2710         if (!cnt) {
2711                 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
2712                                 (tbl->obj, &tbl_data->jump.action);
2713                 if (ret)
2714                         return rte_flow_error_set(error, ENOMEM,
2715                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2716                                         NULL, "cannot create jump action");
2717                 DRV_LOG(DEBUG, "new jump table resource %p: refcnt %d++",
2718                         (void *)&tbl_data->jump, cnt);
2719         } else {
2720                 /* old jump should not make the table ref++. */
2721                 flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
2722                 MLX5_ASSERT(tbl_data->jump.action);
2723                 DRV_LOG(DEBUG, "existed jump table resource %p: refcnt %d++",
2724                         (void *)&tbl_data->jump, cnt);
2725         }
2726         rte_atomic32_inc(&tbl_data->jump.refcnt);
2727         dev_flow->handle->rix_jump = tbl_data->idx;
2728         dev_flow->dv.jump = &tbl_data->jump;
2729         return 0;
2730 }
2731
2732 /**
2733  * Find existing default miss resource or create and register a new one.
2734  *
2735  * @param[in, out] dev
2736  *   Pointer to rte_eth_dev structure.
2737  * @param[out] error
2738  *   pointer to error structure.
2739  *
2740  * @return
2741  *   0 on success otherwise -errno and errno is set.
2742  */
2743 static int
2744 flow_dv_default_miss_resource_register(struct rte_eth_dev *dev,
2745                 struct rte_flow_error *error)
2746 {
2747         struct mlx5_priv *priv = dev->data->dev_private;
2748         struct mlx5_dev_ctx_shared *sh = priv->sh;
2749         struct mlx5_flow_default_miss_resource *cache_resource =
2750                         &sh->default_miss;
2751         int cnt = rte_atomic32_read(&cache_resource->refcnt);
2752
2753         if (!cnt) {
2754                 MLX5_ASSERT(cache_resource->action);
2755                 cache_resource->action =
2756                 mlx5_glue->dr_create_flow_action_default_miss();
2757                 if (!cache_resource->action)
2758                         return rte_flow_error_set(error, ENOMEM,
2759                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2760                                         "cannot create default miss action");
2761                 DRV_LOG(DEBUG, "new default miss resource %p: refcnt %d++",
2762                                 (void *)cache_resource->action, cnt);
2763         }
2764         rte_atomic32_inc(&cache_resource->refcnt);
2765         return 0;
2766 }
2767
2768 /**
2769  * Find existing table port ID resource or create and register a new one.
2770  *
2771  * @param[in, out] dev
2772  *   Pointer to rte_eth_dev structure.
2773  * @param[in, out] resource
2774  *   Pointer to port ID action resource.
2775  * @parm[in, out] dev_flow
2776  *   Pointer to the dev_flow.
2777  * @param[out] error
2778  *   pointer to error structure.
2779  *
2780  * @return
2781  *   0 on success otherwise -errno and errno is set.
2782  */
2783 static int
2784 flow_dv_port_id_action_resource_register
2785                         (struct rte_eth_dev *dev,
2786                          struct mlx5_flow_dv_port_id_action_resource *resource,
2787                          struct mlx5_flow *dev_flow,
2788                          struct rte_flow_error *error)
2789 {
2790         struct mlx5_priv *priv = dev->data->dev_private;
2791         struct mlx5_dev_ctx_shared *sh = priv->sh;
2792         struct mlx5_flow_dv_port_id_action_resource *cache_resource;
2793         uint32_t idx = 0;
2794         int ret;
2795
2796         /* Lookup a matching resource from cache. */
2797         ILIST_FOREACH(sh->ipool[MLX5_IPOOL_PORT_ID], sh->port_id_action_list,
2798                       idx, cache_resource, next) {
2799                 if (resource->port_id == cache_resource->port_id) {
2800                         DRV_LOG(DEBUG, "port id action resource resource %p: "
2801                                 "refcnt %d++",
2802                                 (void *)cache_resource,
2803                                 rte_atomic32_read(&cache_resource->refcnt));
2804                         rte_atomic32_inc(&cache_resource->refcnt);
2805                         dev_flow->handle->rix_port_id_action = idx;
2806                         dev_flow->dv.port_id_action = cache_resource;
2807                         return 0;
2808                 }
2809         }
2810         /* Register new port id action resource. */
2811         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID],
2812                                        &dev_flow->handle->rix_port_id_action);
2813         if (!cache_resource)
2814                 return rte_flow_error_set(error, ENOMEM,
2815                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2816                                           "cannot allocate resource memory");
2817         *cache_resource = *resource;
2818         ret = mlx5_flow_os_create_flow_action_dest_port
2819                                 (priv->sh->fdb_domain, resource->port_id,
2820                                  &cache_resource->action);
2821         if (ret) {
2822                 mlx5_free(cache_resource);
2823                 return rte_flow_error_set(error, ENOMEM,
2824                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2825                                           NULL, "cannot create action");
2826         }
2827         rte_atomic32_init(&cache_resource->refcnt);
2828         rte_atomic32_inc(&cache_resource->refcnt);
2829         ILIST_INSERT(sh->ipool[MLX5_IPOOL_PORT_ID], &sh->port_id_action_list,
2830                      dev_flow->handle->rix_port_id_action, cache_resource,
2831                      next);
2832         dev_flow->dv.port_id_action = cache_resource;
2833         DRV_LOG(DEBUG, "new port id action resource %p: refcnt %d++",
2834                 (void *)cache_resource,
2835                 rte_atomic32_read(&cache_resource->refcnt));
2836         return 0;
2837 }
2838
2839 /**
2840  * Find existing push vlan resource or create and register a new one.
2841  *
2842  * @param [in, out] dev
2843  *   Pointer to rte_eth_dev structure.
2844  * @param[in, out] resource
2845  *   Pointer to port ID action resource.
2846  * @parm[in, out] dev_flow
2847  *   Pointer to the dev_flow.
2848  * @param[out] error
2849  *   pointer to error structure.
2850  *
2851  * @return
2852  *   0 on success otherwise -errno and errno is set.
2853  */
2854 static int
2855 flow_dv_push_vlan_action_resource_register
2856                        (struct rte_eth_dev *dev,
2857                         struct mlx5_flow_dv_push_vlan_action_resource *resource,
2858                         struct mlx5_flow *dev_flow,
2859                         struct rte_flow_error *error)
2860 {
2861         struct mlx5_priv *priv = dev->data->dev_private;
2862         struct mlx5_dev_ctx_shared *sh = priv->sh;
2863         struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
2864         struct mlx5dv_dr_domain *domain;
2865         uint32_t idx = 0;
2866         int ret;
2867
2868         /* Lookup a matching resource from cache. */
2869         ILIST_FOREACH(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2870                       sh->push_vlan_action_list, idx, cache_resource, next) {
2871                 if (resource->vlan_tag == cache_resource->vlan_tag &&
2872                     resource->ft_type == cache_resource->ft_type) {
2873                         DRV_LOG(DEBUG, "push-VLAN action resource resource %p: "
2874                                 "refcnt %d++",
2875                                 (void *)cache_resource,
2876                                 rte_atomic32_read(&cache_resource->refcnt));
2877                         rte_atomic32_inc(&cache_resource->refcnt);
2878                         dev_flow->handle->dvh.rix_push_vlan = idx;
2879                         dev_flow->dv.push_vlan_res = cache_resource;
2880                         return 0;
2881                 }
2882         }
2883         /* Register new push_vlan action resource. */
2884         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2885                                        &dev_flow->handle->dvh.rix_push_vlan);
2886         if (!cache_resource)
2887                 return rte_flow_error_set(error, ENOMEM,
2888                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2889                                           "cannot allocate resource memory");
2890         *cache_resource = *resource;
2891         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2892                 domain = sh->fdb_domain;
2893         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2894                 domain = sh->rx_domain;
2895         else
2896                 domain = sh->tx_domain;
2897         ret = mlx5_flow_os_create_flow_action_push_vlan
2898                                         (domain, resource->vlan_tag,
2899                                          &cache_resource->action);
2900         if (ret) {
2901                 mlx5_free(cache_resource);
2902                 return rte_flow_error_set(error, ENOMEM,
2903                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2904                                           NULL, "cannot create action");
2905         }
2906         rte_atomic32_init(&cache_resource->refcnt);
2907         rte_atomic32_inc(&cache_resource->refcnt);
2908         ILIST_INSERT(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2909                      &sh->push_vlan_action_list,
2910                      dev_flow->handle->dvh.rix_push_vlan,
2911                      cache_resource, next);
2912         dev_flow->dv.push_vlan_res = cache_resource;
2913         DRV_LOG(DEBUG, "new push vlan action resource %p: refcnt %d++",
2914                 (void *)cache_resource,
2915                 rte_atomic32_read(&cache_resource->refcnt));
2916         return 0;
2917 }
2918 /**
2919  * Get the size of specific rte_flow_item_type hdr size
2920  *
2921  * @param[in] item_type
2922  *   Tested rte_flow_item_type.
2923  *
2924  * @return
2925  *   sizeof struct item_type, 0 if void or irrelevant.
2926  */
2927 static size_t
2928 flow_dv_get_item_hdr_len(const enum rte_flow_item_type item_type)
2929 {
2930         size_t retval;
2931
2932         switch (item_type) {
2933         case RTE_FLOW_ITEM_TYPE_ETH:
2934                 retval = sizeof(struct rte_ether_hdr);
2935                 break;
2936         case RTE_FLOW_ITEM_TYPE_VLAN:
2937                 retval = sizeof(struct rte_vlan_hdr);
2938                 break;
2939         case RTE_FLOW_ITEM_TYPE_IPV4:
2940                 retval = sizeof(struct rte_ipv4_hdr);
2941                 break;
2942         case RTE_FLOW_ITEM_TYPE_IPV6:
2943                 retval = sizeof(struct rte_ipv6_hdr);
2944                 break;
2945         case RTE_FLOW_ITEM_TYPE_UDP:
2946                 retval = sizeof(struct rte_udp_hdr);
2947                 break;
2948         case RTE_FLOW_ITEM_TYPE_TCP:
2949                 retval = sizeof(struct rte_tcp_hdr);
2950                 break;
2951         case RTE_FLOW_ITEM_TYPE_VXLAN:
2952         case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2953                 retval = sizeof(struct rte_vxlan_hdr);
2954                 break;
2955         case RTE_FLOW_ITEM_TYPE_GRE:
2956         case RTE_FLOW_ITEM_TYPE_NVGRE:
2957                 retval = sizeof(struct rte_gre_hdr);
2958                 break;
2959         case RTE_FLOW_ITEM_TYPE_MPLS:
2960                 retval = sizeof(struct rte_mpls_hdr);
2961                 break;
2962         case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
2963         default:
2964                 retval = 0;
2965                 break;
2966         }
2967         return retval;
2968 }
2969
2970 #define MLX5_ENCAP_IPV4_VERSION         0x40
2971 #define MLX5_ENCAP_IPV4_IHL_MIN         0x05
2972 #define MLX5_ENCAP_IPV4_TTL_DEF         0x40
2973 #define MLX5_ENCAP_IPV6_VTC_FLOW        0x60000000
2974 #define MLX5_ENCAP_IPV6_HOP_LIMIT       0xff
2975 #define MLX5_ENCAP_VXLAN_FLAGS          0x08000000
2976 #define MLX5_ENCAP_VXLAN_GPE_FLAGS      0x04
2977
2978 /**
2979  * Convert the encap action data from list of rte_flow_item to raw buffer
2980  *
2981  * @param[in] items
2982  *   Pointer to rte_flow_item objects list.
2983  * @param[out] buf
2984  *   Pointer to the output buffer.
2985  * @param[out] size
2986  *   Pointer to the output buffer size.
2987  * @param[out] error
2988  *   Pointer to the error structure.
2989  *
2990  * @return
2991  *   0 on success, a negative errno value otherwise and rte_errno is set.
2992  */
2993 static int
2994 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
2995                            size_t *size, struct rte_flow_error *error)
2996 {
2997         struct rte_ether_hdr *eth = NULL;
2998         struct rte_vlan_hdr *vlan = NULL;
2999         struct rte_ipv4_hdr *ipv4 = NULL;
3000         struct rte_ipv6_hdr *ipv6 = NULL;
3001         struct rte_udp_hdr *udp = NULL;
3002         struct rte_vxlan_hdr *vxlan = NULL;
3003         struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
3004         struct rte_gre_hdr *gre = NULL;
3005         size_t len;
3006         size_t temp_size = 0;
3007
3008         if (!items)
3009                 return rte_flow_error_set(error, EINVAL,
3010                                           RTE_FLOW_ERROR_TYPE_ACTION,
3011                                           NULL, "invalid empty data");
3012         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
3013                 len = flow_dv_get_item_hdr_len(items->type);
3014                 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
3015                         return rte_flow_error_set(error, EINVAL,
3016                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3017                                                   (void *)items->type,
3018                                                   "items total size is too big"
3019                                                   " for encap action");
3020                 rte_memcpy((void *)&buf[temp_size], items->spec, len);
3021                 switch (items->type) {
3022                 case RTE_FLOW_ITEM_TYPE_ETH:
3023                         eth = (struct rte_ether_hdr *)&buf[temp_size];
3024                         break;
3025                 case RTE_FLOW_ITEM_TYPE_VLAN:
3026                         vlan = (struct rte_vlan_hdr *)&buf[temp_size];
3027                         if (!eth)
3028                                 return rte_flow_error_set(error, EINVAL,
3029                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3030                                                 (void *)items->type,
3031                                                 "eth header not found");
3032                         if (!eth->ether_type)
3033                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
3034                         break;
3035                 case RTE_FLOW_ITEM_TYPE_IPV4:
3036                         ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
3037                         if (!vlan && !eth)
3038                                 return rte_flow_error_set(error, EINVAL,
3039                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3040                                                 (void *)items->type,
3041                                                 "neither eth nor vlan"
3042                                                 " header found");
3043                         if (vlan && !vlan->eth_proto)
3044                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3045                         else if (eth && !eth->ether_type)
3046                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3047                         if (!ipv4->version_ihl)
3048                                 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
3049                                                     MLX5_ENCAP_IPV4_IHL_MIN;
3050                         if (!ipv4->time_to_live)
3051                                 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
3052                         break;
3053                 case RTE_FLOW_ITEM_TYPE_IPV6:
3054                         ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
3055                         if (!vlan && !eth)
3056                                 return rte_flow_error_set(error, EINVAL,
3057                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3058                                                 (void *)items->type,
3059                                                 "neither eth nor vlan"
3060                                                 " header found");
3061                         if (vlan && !vlan->eth_proto)
3062                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3063                         else if (eth && !eth->ether_type)
3064                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3065                         if (!ipv6->vtc_flow)
3066                                 ipv6->vtc_flow =
3067                                         RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
3068                         if (!ipv6->hop_limits)
3069                                 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
3070                         break;
3071                 case RTE_FLOW_ITEM_TYPE_UDP:
3072                         udp = (struct rte_udp_hdr *)&buf[temp_size];
3073                         if (!ipv4 && !ipv6)
3074                                 return rte_flow_error_set(error, EINVAL,
3075                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3076                                                 (void *)items->type,
3077                                                 "ip header not found");
3078                         if (ipv4 && !ipv4->next_proto_id)
3079                                 ipv4->next_proto_id = IPPROTO_UDP;
3080                         else if (ipv6 && !ipv6->proto)
3081                                 ipv6->proto = IPPROTO_UDP;
3082                         break;
3083                 case RTE_FLOW_ITEM_TYPE_VXLAN:
3084                         vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
3085                         if (!udp)
3086                                 return rte_flow_error_set(error, EINVAL,
3087                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3088                                                 (void *)items->type,
3089                                                 "udp header not found");
3090                         if (!udp->dst_port)
3091                                 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
3092                         if (!vxlan->vx_flags)
3093                                 vxlan->vx_flags =
3094                                         RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
3095                         break;
3096                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3097                         vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
3098                         if (!udp)
3099                                 return rte_flow_error_set(error, EINVAL,
3100                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3101                                                 (void *)items->type,
3102                                                 "udp header not found");
3103                         if (!vxlan_gpe->proto)
3104                                 return rte_flow_error_set(error, EINVAL,
3105                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3106                                                 (void *)items->type,
3107                                                 "next protocol not found");
3108                         if (!udp->dst_port)
3109                                 udp->dst_port =
3110                                         RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
3111                         if (!vxlan_gpe->vx_flags)
3112                                 vxlan_gpe->vx_flags =
3113                                                 MLX5_ENCAP_VXLAN_GPE_FLAGS;
3114                         break;
3115                 case RTE_FLOW_ITEM_TYPE_GRE:
3116                 case RTE_FLOW_ITEM_TYPE_NVGRE:
3117                         gre = (struct rte_gre_hdr *)&buf[temp_size];
3118                         if (!gre->proto)
3119                                 return rte_flow_error_set(error, EINVAL,
3120                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3121                                                 (void *)items->type,
3122                                                 "next protocol not found");
3123                         if (!ipv4 && !ipv6)
3124                                 return rte_flow_error_set(error, EINVAL,
3125                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3126                                                 (void *)items->type,
3127                                                 "ip header not found");
3128                         if (ipv4 && !ipv4->next_proto_id)
3129                                 ipv4->next_proto_id = IPPROTO_GRE;
3130                         else if (ipv6 && !ipv6->proto)
3131                                 ipv6->proto = IPPROTO_GRE;
3132                         break;
3133                 case RTE_FLOW_ITEM_TYPE_VOID:
3134                         break;
3135                 default:
3136                         return rte_flow_error_set(error, EINVAL,
3137                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3138                                                   (void *)items->type,
3139                                                   "unsupported item type");
3140                         break;
3141                 }
3142                 temp_size += len;
3143         }
3144         *size = temp_size;
3145         return 0;
3146 }
3147
3148 static int
3149 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
3150 {
3151         struct rte_ether_hdr *eth = NULL;
3152         struct rte_vlan_hdr *vlan = NULL;
3153         struct rte_ipv6_hdr *ipv6 = NULL;
3154         struct rte_udp_hdr *udp = NULL;
3155         char *next_hdr;
3156         uint16_t proto;
3157
3158         eth = (struct rte_ether_hdr *)data;
3159         next_hdr = (char *)(eth + 1);
3160         proto = RTE_BE16(eth->ether_type);
3161
3162         /* VLAN skipping */
3163         while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
3164                 vlan = (struct rte_vlan_hdr *)next_hdr;
3165                 proto = RTE_BE16(vlan->eth_proto);
3166                 next_hdr += sizeof(struct rte_vlan_hdr);
3167         }
3168
3169         /* HW calculates IPv4 csum. no need to proceed */
3170         if (proto == RTE_ETHER_TYPE_IPV4)
3171                 return 0;
3172
3173         /* non IPv4/IPv6 header. not supported */
3174         if (proto != RTE_ETHER_TYPE_IPV6) {
3175                 return rte_flow_error_set(error, ENOTSUP,
3176                                           RTE_FLOW_ERROR_TYPE_ACTION,
3177                                           NULL, "Cannot offload non IPv4/IPv6");
3178         }
3179
3180         ipv6 = (struct rte_ipv6_hdr *)next_hdr;
3181
3182         /* ignore non UDP */
3183         if (ipv6->proto != IPPROTO_UDP)
3184                 return 0;
3185
3186         udp = (struct rte_udp_hdr *)(ipv6 + 1);
3187         udp->dgram_cksum = 0;
3188
3189         return 0;
3190 }
3191
3192 /**
3193  * Convert L2 encap action to DV specification.
3194  *
3195  * @param[in] dev
3196  *   Pointer to rte_eth_dev structure.
3197  * @param[in] action
3198  *   Pointer to action structure.
3199  * @param[in, out] dev_flow
3200  *   Pointer to the mlx5_flow.
3201  * @param[in] transfer
3202  *   Mark if the flow is E-Switch flow.
3203  * @param[out] error
3204  *   Pointer to the error structure.
3205  *
3206  * @return
3207  *   0 on success, a negative errno value otherwise and rte_errno is set.
3208  */
3209 static int
3210 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
3211                                const struct rte_flow_action *action,
3212                                struct mlx5_flow *dev_flow,
3213                                uint8_t transfer,
3214                                struct rte_flow_error *error)
3215 {
3216         const struct rte_flow_item *encap_data;
3217         const struct rte_flow_action_raw_encap *raw_encap_data;
3218         struct mlx5_flow_dv_encap_decap_resource res = {
3219                 .reformat_type =
3220                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
3221                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3222                                       MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
3223         };
3224
3225         if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
3226                 raw_encap_data =
3227                         (const struct rte_flow_action_raw_encap *)action->conf;
3228                 res.size = raw_encap_data->size;
3229                 memcpy(res.buf, raw_encap_data->data, res.size);
3230         } else {
3231                 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
3232                         encap_data =
3233                                 ((const struct rte_flow_action_vxlan_encap *)
3234                                                 action->conf)->definition;
3235                 else
3236                         encap_data =
3237                                 ((const struct rte_flow_action_nvgre_encap *)
3238                                                 action->conf)->definition;
3239                 if (flow_dv_convert_encap_data(encap_data, res.buf,
3240                                                &res.size, error))
3241                         return -rte_errno;
3242         }
3243         if (flow_dv_zero_encap_udp_csum(res.buf, error))
3244                 return -rte_errno;
3245         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3246                 return rte_flow_error_set(error, EINVAL,
3247                                           RTE_FLOW_ERROR_TYPE_ACTION,
3248                                           NULL, "can't create L2 encap action");
3249         return 0;
3250 }
3251
3252 /**
3253  * Convert L2 decap action to DV specification.
3254  *
3255  * @param[in] dev
3256  *   Pointer to rte_eth_dev structure.
3257  * @param[in, out] dev_flow
3258  *   Pointer to the mlx5_flow.
3259  * @param[in] transfer
3260  *   Mark if the flow is E-Switch flow.
3261  * @param[out] error
3262  *   Pointer to the error structure.
3263  *
3264  * @return
3265  *   0 on success, a negative errno value otherwise and rte_errno is set.
3266  */
3267 static int
3268 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
3269                                struct mlx5_flow *dev_flow,
3270                                uint8_t transfer,
3271                                struct rte_flow_error *error)
3272 {
3273         struct mlx5_flow_dv_encap_decap_resource res = {
3274                 .size = 0,
3275                 .reformat_type =
3276                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
3277                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3278                                       MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
3279         };
3280
3281         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3282                 return rte_flow_error_set(error, EINVAL,
3283                                           RTE_FLOW_ERROR_TYPE_ACTION,
3284                                           NULL, "can't create L2 decap action");
3285         return 0;
3286 }
3287
3288 /**
3289  * Convert raw decap/encap (L3 tunnel) action to DV specification.
3290  *
3291  * @param[in] dev
3292  *   Pointer to rte_eth_dev structure.
3293  * @param[in] action
3294  *   Pointer to action structure.
3295  * @param[in, out] dev_flow
3296  *   Pointer to the mlx5_flow.
3297  * @param[in] attr
3298  *   Pointer to the flow attributes.
3299  * @param[out] error
3300  *   Pointer to the error structure.
3301  *
3302  * @return
3303  *   0 on success, a negative errno value otherwise and rte_errno is set.
3304  */
3305 static int
3306 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
3307                                 const struct rte_flow_action *action,
3308                                 struct mlx5_flow *dev_flow,
3309                                 const struct rte_flow_attr *attr,
3310                                 struct rte_flow_error *error)
3311 {
3312         const struct rte_flow_action_raw_encap *encap_data;
3313         struct mlx5_flow_dv_encap_decap_resource res;
3314
3315         memset(&res, 0, sizeof(res));
3316         encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
3317         res.size = encap_data->size;
3318         memcpy(res.buf, encap_data->data, res.size);
3319         res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
3320                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
3321                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
3322         if (attr->transfer)
3323                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3324         else
3325                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3326                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3327         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3328                 return rte_flow_error_set(error, EINVAL,
3329                                           RTE_FLOW_ERROR_TYPE_ACTION,
3330                                           NULL, "can't create encap action");
3331         return 0;
3332 }
3333
3334 /**
3335  * Create action push VLAN.
3336  *
3337  * @param[in] dev
3338  *   Pointer to rte_eth_dev structure.
3339  * @param[in] attr
3340  *   Pointer to the flow attributes.
3341  * @param[in] vlan
3342  *   Pointer to the vlan to push to the Ethernet header.
3343  * @param[in, out] dev_flow
3344  *   Pointer to the mlx5_flow.
3345  * @param[out] error
3346  *   Pointer to the error structure.
3347  *
3348  * @return
3349  *   0 on success, a negative errno value otherwise and rte_errno is set.
3350  */
3351 static int
3352 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
3353                                 const struct rte_flow_attr *attr,
3354                                 const struct rte_vlan_hdr *vlan,
3355                                 struct mlx5_flow *dev_flow,
3356                                 struct rte_flow_error *error)
3357 {
3358         struct mlx5_flow_dv_push_vlan_action_resource res;
3359
3360         memset(&res, 0, sizeof(res));
3361         res.vlan_tag =
3362                 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
3363                                  vlan->vlan_tci);
3364         if (attr->transfer)
3365                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3366         else
3367                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3368                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3369         return flow_dv_push_vlan_action_resource_register
3370                                             (dev, &res, dev_flow, error);
3371 }
3372
3373 /**
3374  * Validate the modify-header actions.
3375  *
3376  * @param[in] action_flags
3377  *   Holds the actions detected until now.
3378  * @param[in] action
3379  *   Pointer to the modify action.
3380  * @param[out] error
3381  *   Pointer to error structure.
3382  *
3383  * @return
3384  *   0 on success, a negative errno value otherwise and rte_errno is set.
3385  */
3386 static int
3387 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
3388                                    const struct rte_flow_action *action,
3389                                    struct rte_flow_error *error)
3390 {
3391         if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
3392                 return rte_flow_error_set(error, EINVAL,
3393                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3394                                           NULL, "action configuration not set");
3395         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3396                 return rte_flow_error_set(error, EINVAL,
3397                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3398                                           "can't have encap action before"
3399                                           " modify action");
3400         return 0;
3401 }
3402
3403 /**
3404  * Validate the modify-header MAC address actions.
3405  *
3406  * @param[in] action_flags
3407  *   Holds the actions detected until now.
3408  * @param[in] action
3409  *   Pointer to the modify action.
3410  * @param[in] item_flags
3411  *   Holds the items detected.
3412  * @param[out] error
3413  *   Pointer to error structure.
3414  *
3415  * @return
3416  *   0 on success, a negative errno value otherwise and rte_errno is set.
3417  */
3418 static int
3419 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
3420                                    const struct rte_flow_action *action,
3421                                    const uint64_t item_flags,
3422                                    struct rte_flow_error *error)
3423 {
3424         int ret = 0;
3425
3426         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3427         if (!ret) {
3428                 if (!(item_flags & MLX5_FLOW_LAYER_L2))
3429                         return rte_flow_error_set(error, EINVAL,
3430                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3431                                                   NULL,
3432                                                   "no L2 item in pattern");
3433         }
3434         return ret;
3435 }
3436
3437 /**
3438  * Validate the modify-header IPv4 address actions.
3439  *
3440  * @param[in] action_flags
3441  *   Holds the actions detected until now.
3442  * @param[in] action
3443  *   Pointer to the modify action.
3444  * @param[in] item_flags
3445  *   Holds the items detected.
3446  * @param[out] error
3447  *   Pointer to error structure.
3448  *
3449  * @return
3450  *   0 on success, a negative errno value otherwise and rte_errno is set.
3451  */
3452 static int
3453 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
3454                                     const struct rte_flow_action *action,
3455                                     const uint64_t item_flags,
3456                                     struct rte_flow_error *error)
3457 {
3458         int ret = 0;
3459         uint64_t layer;
3460
3461         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3462         if (!ret) {
3463                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3464                                  MLX5_FLOW_LAYER_INNER_L3_IPV4 :
3465                                  MLX5_FLOW_LAYER_OUTER_L3_IPV4;
3466                 if (!(item_flags & layer))
3467                         return rte_flow_error_set(error, EINVAL,
3468                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3469                                                   NULL,
3470                                                   "no ipv4 item in pattern");
3471         }
3472         return ret;
3473 }
3474
3475 /**
3476  * Validate the modify-header IPv6 address actions.
3477  *
3478  * @param[in] action_flags
3479  *   Holds the actions detected until now.
3480  * @param[in] action
3481  *   Pointer to the modify action.
3482  * @param[in] item_flags
3483  *   Holds the items detected.
3484  * @param[out] error
3485  *   Pointer to error structure.
3486  *
3487  * @return
3488  *   0 on success, a negative errno value otherwise and rte_errno is set.
3489  */
3490 static int
3491 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
3492                                     const struct rte_flow_action *action,
3493                                     const uint64_t item_flags,
3494                                     struct rte_flow_error *error)
3495 {
3496         int ret = 0;
3497         uint64_t layer;
3498
3499         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3500         if (!ret) {
3501                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3502                                  MLX5_FLOW_LAYER_INNER_L3_IPV6 :
3503                                  MLX5_FLOW_LAYER_OUTER_L3_IPV6;
3504                 if (!(item_flags & layer))
3505                         return rte_flow_error_set(error, EINVAL,
3506                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3507                                                   NULL,
3508                                                   "no ipv6 item in pattern");
3509         }
3510         return ret;
3511 }
3512
3513 /**
3514  * Validate the modify-header TP actions.
3515  *
3516  * @param[in] action_flags
3517  *   Holds the actions detected until now.
3518  * @param[in] action
3519  *   Pointer to the modify action.
3520  * @param[in] item_flags
3521  *   Holds the items detected.
3522  * @param[out] error
3523  *   Pointer to error structure.
3524  *
3525  * @return
3526  *   0 on success, a negative errno value otherwise and rte_errno is set.
3527  */
3528 static int
3529 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
3530                                   const struct rte_flow_action *action,
3531                                   const uint64_t item_flags,
3532                                   struct rte_flow_error *error)
3533 {
3534         int ret = 0;
3535         uint64_t layer;
3536
3537         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3538         if (!ret) {
3539                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3540                                  MLX5_FLOW_LAYER_INNER_L4 :
3541                                  MLX5_FLOW_LAYER_OUTER_L4;
3542                 if (!(item_flags & layer))
3543                         return rte_flow_error_set(error, EINVAL,
3544                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3545                                                   NULL, "no transport layer "
3546                                                   "in pattern");
3547         }
3548         return ret;
3549 }
3550
3551 /**
3552  * Validate the modify-header actions of increment/decrement
3553  * TCP Sequence-number.
3554  *
3555  * @param[in] action_flags
3556  *   Holds the actions detected until now.
3557  * @param[in] action
3558  *   Pointer to the modify action.
3559  * @param[in] item_flags
3560  *   Holds the items detected.
3561  * @param[out] error
3562  *   Pointer to error structure.
3563  *
3564  * @return
3565  *   0 on success, a negative errno value otherwise and rte_errno is set.
3566  */
3567 static int
3568 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
3569                                        const struct rte_flow_action *action,
3570                                        const uint64_t item_flags,
3571                                        struct rte_flow_error *error)
3572 {
3573         int ret = 0;
3574         uint64_t layer;
3575
3576         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3577         if (!ret) {
3578                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3579                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
3580                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
3581                 if (!(item_flags & layer))
3582                         return rte_flow_error_set(error, EINVAL,
3583                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3584                                                   NULL, "no TCP item in"
3585                                                   " pattern");
3586                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
3587                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
3588                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
3589                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
3590                         return rte_flow_error_set(error, EINVAL,
3591                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3592                                                   NULL,
3593                                                   "cannot decrease and increase"
3594                                                   " TCP sequence number"
3595                                                   " at the same time");
3596         }
3597         return ret;
3598 }
3599
3600 /**
3601  * Validate the modify-header actions of increment/decrement
3602  * TCP Acknowledgment number.
3603  *
3604  * @param[in] action_flags
3605  *   Holds the actions detected until now.
3606  * @param[in] action
3607  *   Pointer to the modify action.
3608  * @param[in] item_flags
3609  *   Holds the items detected.
3610  * @param[out] error
3611  *   Pointer to error structure.
3612  *
3613  * @return
3614  *   0 on success, a negative errno value otherwise and rte_errno is set.
3615  */
3616 static int
3617 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
3618                                        const struct rte_flow_action *action,
3619                                        const uint64_t item_flags,
3620                                        struct rte_flow_error *error)
3621 {
3622         int ret = 0;
3623         uint64_t layer;
3624
3625         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3626         if (!ret) {
3627                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3628                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
3629                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
3630                 if (!(item_flags & layer))
3631                         return rte_flow_error_set(error, EINVAL,
3632                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3633                                                   NULL, "no TCP item in"
3634                                                   " pattern");
3635                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
3636                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
3637                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
3638                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
3639                         return rte_flow_error_set(error, EINVAL,
3640                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3641                                                   NULL,
3642                                                   "cannot decrease and increase"
3643                                                   " TCP acknowledgment number"
3644                                                   " at the same time");
3645         }
3646         return ret;
3647 }
3648
3649 /**
3650  * Validate the modify-header TTL actions.
3651  *
3652  * @param[in] action_flags
3653  *   Holds the actions detected until now.
3654  * @param[in] action
3655  *   Pointer to the modify action.
3656  * @param[in] item_flags
3657  *   Holds the items detected.
3658  * @param[out] error
3659  *   Pointer to error structure.
3660  *
3661  * @return
3662  *   0 on success, a negative errno value otherwise and rte_errno is set.
3663  */
3664 static int
3665 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
3666                                    const struct rte_flow_action *action,
3667                                    const uint64_t item_flags,
3668                                    struct rte_flow_error *error)
3669 {
3670         int ret = 0;
3671         uint64_t layer;
3672
3673         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3674         if (!ret) {
3675                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3676                                  MLX5_FLOW_LAYER_INNER_L3 :
3677                                  MLX5_FLOW_LAYER_OUTER_L3;
3678                 if (!(item_flags & layer))
3679                         return rte_flow_error_set(error, EINVAL,
3680                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3681                                                   NULL,
3682                                                   "no IP protocol in pattern");
3683         }
3684         return ret;
3685 }
3686
3687 /**
3688  * Validate jump action.
3689  *
3690  * @param[in] action
3691  *   Pointer to the jump action.
3692  * @param[in] action_flags
3693  *   Holds the actions detected until now.
3694  * @param[in] attributes
3695  *   Pointer to flow attributes
3696  * @param[in] external
3697  *   Action belongs to flow rule created by request external to PMD.
3698  * @param[out] error
3699  *   Pointer to error structure.
3700  *
3701  * @return
3702  *   0 on success, a negative errno value otherwise and rte_errno is set.
3703  */
3704 static int
3705 flow_dv_validate_action_jump(const struct rte_flow_action *action,
3706                              uint64_t action_flags,
3707                              const struct rte_flow_attr *attributes,
3708                              bool external, struct rte_flow_error *error)
3709 {
3710         uint32_t target_group, table;
3711         int ret = 0;
3712
3713         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3714                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3715                 return rte_flow_error_set(error, EINVAL,
3716                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3717                                           "can't have 2 fate actions in"
3718                                           " same flow");
3719         if (action_flags & MLX5_FLOW_ACTION_METER)
3720                 return rte_flow_error_set(error, ENOTSUP,
3721                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3722                                           "jump with meter not support");
3723         if (!action->conf)
3724                 return rte_flow_error_set(error, EINVAL,
3725                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3726                                           NULL, "action configuration not set");
3727         target_group =
3728                 ((const struct rte_flow_action_jump *)action->conf)->group;
3729         ret = mlx5_flow_group_to_table(attributes, external, target_group,
3730                                        true, &table, error);
3731         if (ret)
3732                 return ret;
3733         if (attributes->group == target_group)
3734                 return rte_flow_error_set(error, EINVAL,
3735                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3736                                           "target group must be other than"
3737                                           " the current flow group");
3738         return 0;
3739 }
3740
3741 /*
3742  * Validate the port_id action.
3743  *
3744  * @param[in] dev
3745  *   Pointer to rte_eth_dev structure.
3746  * @param[in] action_flags
3747  *   Bit-fields that holds the actions detected until now.
3748  * @param[in] action
3749  *   Port_id RTE action structure.
3750  * @param[in] attr
3751  *   Attributes of flow that includes this action.
3752  * @param[out] error
3753  *   Pointer to error structure.
3754  *
3755  * @return
3756  *   0 on success, a negative errno value otherwise and rte_errno is set.
3757  */
3758 static int
3759 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
3760                                 uint64_t action_flags,
3761                                 const struct rte_flow_action *action,
3762                                 const struct rte_flow_attr *attr,
3763                                 struct rte_flow_error *error)
3764 {
3765         const struct rte_flow_action_port_id *port_id;
3766         struct mlx5_priv *act_priv;
3767         struct mlx5_priv *dev_priv;
3768         uint16_t port;
3769
3770         if (!attr->transfer)
3771                 return rte_flow_error_set(error, ENOTSUP,
3772                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3773                                           NULL,
3774                                           "port id action is valid in transfer"
3775                                           " mode only");
3776         if (!action || !action->conf)
3777                 return rte_flow_error_set(error, ENOTSUP,
3778                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3779                                           NULL,
3780                                           "port id action parameters must be"
3781                                           " specified");
3782         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3783                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3784                 return rte_flow_error_set(error, EINVAL,
3785                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3786                                           "can have only one fate actions in"
3787                                           " a flow");
3788         dev_priv = mlx5_dev_to_eswitch_info(dev);
3789         if (!dev_priv)
3790                 return rte_flow_error_set(error, rte_errno,
3791                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3792                                           NULL,
3793                                           "failed to obtain E-Switch info");
3794         port_id = action->conf;
3795         port = port_id->original ? dev->data->port_id : port_id->id;
3796         act_priv = mlx5_port_to_eswitch_info(port, false);
3797         if (!act_priv)
3798                 return rte_flow_error_set
3799                                 (error, rte_errno,
3800                                  RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
3801                                  "failed to obtain E-Switch port id for port");
3802         if (act_priv->domain_id != dev_priv->domain_id)
3803                 return rte_flow_error_set
3804                                 (error, EINVAL,
3805                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3806                                  "port does not belong to"
3807                                  " E-Switch being configured");
3808         return 0;
3809 }
3810
3811 /**
3812  * Get the maximum number of modify header actions.
3813  *
3814  * @param dev
3815  *   Pointer to rte_eth_dev structure.
3816  * @param flags
3817  *   Flags bits to check if root level.
3818  *
3819  * @return
3820  *   Max number of modify header actions device can support.
3821  */
3822 static inline unsigned int
3823 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev __rte_unused,
3824                               uint64_t flags)
3825 {
3826         /*
3827          * There's no way to directly query the max capacity from FW.
3828          * The maximal value on root table should be assumed to be supported.
3829          */
3830         if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
3831                 return MLX5_MAX_MODIFY_NUM;
3832         else
3833                 return MLX5_ROOT_TBL_MODIFY_NUM;
3834 }
3835
3836 /**
3837  * Validate the meter action.
3838  *
3839  * @param[in] dev
3840  *   Pointer to rte_eth_dev structure.
3841  * @param[in] action_flags
3842  *   Bit-fields that holds the actions detected until now.
3843  * @param[in] action
3844  *   Pointer to the meter action.
3845  * @param[in] attr
3846  *   Attributes of flow that includes this action.
3847  * @param[out] error
3848  *   Pointer to error structure.
3849  *
3850  * @return
3851  *   0 on success, a negative errno value otherwise and rte_ernno is set.
3852  */
3853 static int
3854 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
3855                                 uint64_t action_flags,
3856                                 const struct rte_flow_action *action,
3857                                 const struct rte_flow_attr *attr,
3858                                 struct rte_flow_error *error)
3859 {
3860         struct mlx5_priv *priv = dev->data->dev_private;
3861         const struct rte_flow_action_meter *am = action->conf;
3862         struct mlx5_flow_meter *fm;
3863
3864         if (!am)
3865                 return rte_flow_error_set(error, EINVAL,
3866                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3867                                           "meter action conf is NULL");
3868
3869         if (action_flags & MLX5_FLOW_ACTION_METER)
3870                 return rte_flow_error_set(error, ENOTSUP,
3871                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3872                                           "meter chaining not support");
3873         if (action_flags & MLX5_FLOW_ACTION_JUMP)
3874                 return rte_flow_error_set(error, ENOTSUP,
3875                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3876                                           "meter with jump not support");
3877         if (!priv->mtr_en)
3878                 return rte_flow_error_set(error, ENOTSUP,
3879                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3880                                           NULL,
3881                                           "meter action not supported");
3882         fm = mlx5_flow_meter_find(priv, am->mtr_id);
3883         if (!fm)
3884                 return rte_flow_error_set(error, EINVAL,
3885                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3886                                           "Meter not found");
3887         if (fm->ref_cnt && (!(fm->transfer == attr->transfer ||
3888               (!fm->ingress && !attr->ingress && attr->egress) ||
3889               (!fm->egress && !attr->egress && attr->ingress))))
3890                 return rte_flow_error_set(error, EINVAL,
3891                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3892                                           "Flow attributes are either invalid "
3893                                           "or have a conflict with current "
3894                                           "meter attributes");
3895         return 0;
3896 }
3897
3898 /**
3899  * Validate the age action.
3900  *
3901  * @param[in] action_flags
3902  *   Holds the actions detected until now.
3903  * @param[in] action
3904  *   Pointer to the age action.
3905  * @param[in] dev
3906  *   Pointer to the Ethernet device structure.
3907  * @param[out] error
3908  *   Pointer to error structure.
3909  *
3910  * @return
3911  *   0 on success, a negative errno value otherwise and rte_errno is set.
3912  */
3913 static int
3914 flow_dv_validate_action_age(uint64_t action_flags,
3915                             const struct rte_flow_action *action,
3916                             struct rte_eth_dev *dev,
3917                             struct rte_flow_error *error)
3918 {
3919         struct mlx5_priv *priv = dev->data->dev_private;
3920         const struct rte_flow_action_age *age = action->conf;
3921
3922         if (!priv->config.devx || priv->counter_fallback)
3923                 return rte_flow_error_set(error, ENOTSUP,
3924                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3925                                           NULL,
3926                                           "age action not supported");
3927         if (!(action->conf))
3928                 return rte_flow_error_set(error, EINVAL,
3929                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3930                                           "configuration cannot be null");
3931         if (age->timeout >= UINT16_MAX / 2 / 10)
3932                 return rte_flow_error_set(error, ENOTSUP,
3933                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3934                                           "Max age time: 3275 seconds");
3935         if (action_flags & MLX5_FLOW_ACTION_AGE)
3936                 return rte_flow_error_set(error, EINVAL,
3937                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3938                                           "Duplicate age ctions set");
3939         return 0;
3940 }
3941
3942 /**
3943  * Validate the modify-header IPv4 DSCP actions.
3944  *
3945  * @param[in] action_flags
3946  *   Holds the actions detected until now.
3947  * @param[in] action
3948  *   Pointer to the modify action.
3949  * @param[in] item_flags
3950  *   Holds the items detected.
3951  * @param[out] error
3952  *   Pointer to error structure.
3953  *
3954  * @return
3955  *   0 on success, a negative errno value otherwise and rte_errno is set.
3956  */
3957 static int
3958 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
3959                                          const struct rte_flow_action *action,
3960                                          const uint64_t item_flags,
3961                                          struct rte_flow_error *error)
3962 {
3963         int ret = 0;
3964
3965         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3966         if (!ret) {
3967                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
3968                         return rte_flow_error_set(error, EINVAL,
3969                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3970                                                   NULL,
3971                                                   "no ipv4 item in pattern");
3972         }
3973         return ret;
3974 }
3975
3976 /**
3977  * Validate the modify-header IPv6 DSCP actions.
3978  *
3979  * @param[in] action_flags
3980  *   Holds the actions detected until now.
3981  * @param[in] action
3982  *   Pointer to the modify action.
3983  * @param[in] item_flags
3984  *   Holds the items detected.
3985  * @param[out] error
3986  *   Pointer to error structure.
3987  *
3988  * @return
3989  *   0 on success, a negative errno value otherwise and rte_errno is set.
3990  */
3991 static int
3992 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
3993                                          const struct rte_flow_action *action,
3994                                          const uint64_t item_flags,
3995                                          struct rte_flow_error *error)
3996 {
3997         int ret = 0;
3998
3999         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4000         if (!ret) {
4001                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
4002                         return rte_flow_error_set(error, EINVAL,
4003                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4004                                                   NULL,
4005                                                   "no ipv6 item in pattern");
4006         }
4007         return ret;
4008 }
4009
4010 /**
4011  * Match modify-header resource.
4012  *
4013  * @param entry
4014  *   Pointer to exist resource entry object.
4015  * @param ctx
4016  *   Pointer to new modify-header resource.
4017  *
4018  * @return
4019  *   0 on matching, -1 otherwise.
4020  */
4021 static int
4022 flow_dv_modify_hdr_resource_match(struct mlx5_hlist_entry *entry, void *ctx)
4023 {
4024         struct mlx5_flow_dv_modify_hdr_resource *resource;
4025         struct mlx5_flow_dv_modify_hdr_resource *cache_resource;
4026         uint32_t actions_len;
4027
4028         resource = (struct mlx5_flow_dv_modify_hdr_resource *)ctx;
4029         cache_resource = container_of(entry,
4030                                       struct mlx5_flow_dv_modify_hdr_resource,
4031                                       entry);
4032         actions_len = resource->actions_num * sizeof(resource->actions[0]);
4033         if (resource->entry.key == cache_resource->entry.key &&
4034             resource->ft_type == cache_resource->ft_type &&
4035             resource->actions_num == cache_resource->actions_num &&
4036             resource->flags == cache_resource->flags &&
4037             !memcmp((const void *)resource->actions,
4038                     (const void *)cache_resource->actions,
4039                     actions_len))
4040                 return 0;
4041         return -1;
4042 }
4043
4044 /**
4045  * Validate the sample action.
4046  *
4047  * @param[in] action_flags
4048  *   Holds the actions detected until now.
4049  * @param[in] action
4050  *   Pointer to the sample action.
4051  * @param[in] dev
4052  *   Pointer to the Ethernet device structure.
4053  * @param[in] attr
4054  *   Attributes of flow that includes this action.
4055  * @param[out] error
4056  *   Pointer to error structure.
4057  *
4058  * @return
4059  *   0 on success, a negative errno value otherwise and rte_errno is set.
4060  */
4061 static int
4062 flow_dv_validate_action_sample(uint64_t action_flags,
4063                                const struct rte_flow_action *action,
4064                                struct rte_eth_dev *dev,
4065                                const struct rte_flow_attr *attr,
4066                                struct rte_flow_error *error)
4067 {
4068         struct mlx5_priv *priv = dev->data->dev_private;
4069         struct mlx5_dev_config *dev_conf = &priv->config;
4070         const struct rte_flow_action_sample *sample = action->conf;
4071         const struct rte_flow_action *act;
4072         uint64_t sub_action_flags = 0;
4073         int actions_n = 0;
4074         int ret;
4075
4076         if (!sample)
4077                 return rte_flow_error_set(error, EINVAL,
4078                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4079                                           "configuration cannot be NULL");
4080         if (sample->ratio == 0)
4081                 return rte_flow_error_set(error, EINVAL,
4082                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4083                                           "ratio value starts from 1");
4084         if (!priv->config.devx || (sample->ratio > 0 && !priv->sampler_en))
4085                 return rte_flow_error_set(error, ENOTSUP,
4086                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4087                                           NULL,
4088                                           "sample action not supported");
4089         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
4090                 return rte_flow_error_set(error, EINVAL,
4091                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4092                                           "Multiple sample actions not "
4093                                           "supported");
4094         if (action_flags & MLX5_FLOW_ACTION_METER)
4095                 return rte_flow_error_set(error, EINVAL,
4096                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4097                                           "wrong action order, meter should "
4098                                           "be after sample action");
4099         if (action_flags & MLX5_FLOW_ACTION_JUMP)
4100                 return rte_flow_error_set(error, EINVAL,
4101                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4102                                           "wrong action order, jump should "
4103                                           "be after sample action");
4104         act = sample->actions;
4105         for (; act->type != RTE_FLOW_ACTION_TYPE_END; act++) {
4106                 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
4107                         return rte_flow_error_set(error, ENOTSUP,
4108                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4109                                                   act, "too many actions");
4110                 switch (act->type) {
4111                 case RTE_FLOW_ACTION_TYPE_QUEUE:
4112                         ret = mlx5_flow_validate_action_queue(act,
4113                                                               sub_action_flags,
4114                                                               dev,
4115                                                               attr, error);
4116                         if (ret < 0)
4117                                 return ret;
4118                         sub_action_flags |= MLX5_FLOW_ACTION_QUEUE;
4119                         ++actions_n;
4120                         break;
4121                 case RTE_FLOW_ACTION_TYPE_MARK:
4122                         ret = flow_dv_validate_action_mark(dev, act,
4123                                                            sub_action_flags,
4124                                                            attr, error);
4125                         if (ret < 0)
4126                                 return ret;
4127                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY)
4128                                 sub_action_flags |= MLX5_FLOW_ACTION_MARK |
4129                                                 MLX5_FLOW_ACTION_MARK_EXT;
4130                         else
4131                                 sub_action_flags |= MLX5_FLOW_ACTION_MARK;
4132                         ++actions_n;
4133                         break;
4134                 case RTE_FLOW_ACTION_TYPE_COUNT:
4135                         ret = flow_dv_validate_action_count(dev, error);
4136                         if (ret < 0)
4137                                 return ret;
4138                         sub_action_flags |= MLX5_FLOW_ACTION_COUNT;
4139                         ++actions_n;
4140                         break;
4141                 default:
4142                         return rte_flow_error_set(error, ENOTSUP,
4143                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4144                                                   NULL,
4145                                                   "Doesn't support optional "
4146                                                   "action");
4147                 }
4148         }
4149         if (attr->ingress && !attr->transfer) {
4150                 if (!(sub_action_flags & MLX5_FLOW_ACTION_QUEUE))
4151                         return rte_flow_error_set(error, EINVAL,
4152                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4153                                                   NULL,
4154                                                   "Ingress must has a dest "
4155                                                   "QUEUE for Sample");
4156         } else if (attr->egress && !attr->transfer) {
4157                 return rte_flow_error_set(error, ENOTSUP,
4158                                           RTE_FLOW_ERROR_TYPE_ACTION,
4159                                           NULL,
4160                                           "Sample Only support Ingress "
4161                                           "or E-Switch");
4162         } else if (sample->actions->type != RTE_FLOW_ACTION_TYPE_END) {
4163                 MLX5_ASSERT(attr->transfer);
4164                 return rte_flow_error_set(error, ENOTSUP,
4165                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4166                                           "E-Switch doesn't support any "
4167                                           "optional action for sampling");
4168         }
4169         return 0;
4170 }
4171
4172 /**
4173  * Find existing modify-header resource or create and register a new one.
4174  *
4175  * @param dev[in, out]
4176  *   Pointer to rte_eth_dev structure.
4177  * @param[in, out] resource
4178  *   Pointer to modify-header resource.
4179  * @parm[in, out] dev_flow
4180  *   Pointer to the dev_flow.
4181  * @param[out] error
4182  *   pointer to error structure.
4183  *
4184  * @return
4185  *   0 on success otherwise -errno and errno is set.
4186  */
4187 static int
4188 flow_dv_modify_hdr_resource_register
4189                         (struct rte_eth_dev *dev,
4190                          struct mlx5_flow_dv_modify_hdr_resource *resource,
4191                          struct mlx5_flow *dev_flow,
4192                          struct rte_flow_error *error)
4193 {
4194         struct mlx5_priv *priv = dev->data->dev_private;
4195         struct mlx5_dev_ctx_shared *sh = priv->sh;
4196         struct mlx5_flow_dv_modify_hdr_resource *cache_resource;
4197         struct mlx5dv_dr_domain *ns;
4198         uint32_t actions_len;
4199         struct mlx5_hlist_entry *entry;
4200         union mlx5_flow_modify_hdr_key hdr_mod_key = {
4201                 {
4202                         .ft_type = resource->ft_type,
4203                         .actions_num = resource->actions_num,
4204                         .group = dev_flow->dv.group,
4205                         .cksum = 0,
4206                 }
4207         };
4208         int ret;
4209
4210         resource->flags = dev_flow->dv.group ? 0 :
4211                           MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
4212         if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
4213                                     resource->flags))
4214                 return rte_flow_error_set(error, EOVERFLOW,
4215                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4216                                           "too many modify header items");
4217         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
4218                 ns = sh->fdb_domain;
4219         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
4220                 ns = sh->tx_domain;
4221         else
4222                 ns = sh->rx_domain;
4223         /* Lookup a matching resource from cache. */
4224         actions_len = resource->actions_num * sizeof(resource->actions[0]);
4225         hdr_mod_key.cksum = __rte_raw_cksum(resource->actions, actions_len, 0);
4226         resource->entry.key = hdr_mod_key.v64;
4227         entry = mlx5_hlist_lookup_ex(sh->modify_cmds, resource->entry.key,
4228                                      flow_dv_modify_hdr_resource_match,
4229                                      (void *)resource);
4230         if (entry) {
4231                 cache_resource = container_of(entry,
4232                                         struct mlx5_flow_dv_modify_hdr_resource,
4233                                         entry);
4234                 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d++",
4235                         (void *)cache_resource,
4236                         rte_atomic32_read(&cache_resource->refcnt));
4237                 rte_atomic32_inc(&cache_resource->refcnt);
4238                 dev_flow->handle->dvh.modify_hdr = cache_resource;
4239                 return 0;
4240
4241         }
4242         /* Register new modify-header resource. */
4243         cache_resource = mlx5_malloc(MLX5_MEM_ZERO,
4244                                     sizeof(*cache_resource) + actions_len, 0,
4245                                     SOCKET_ID_ANY);
4246         if (!cache_resource)
4247                 return rte_flow_error_set(error, ENOMEM,
4248                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4249                                           "cannot allocate resource memory");
4250         *cache_resource = *resource;
4251         rte_memcpy(cache_resource->actions, resource->actions, actions_len);
4252         ret = mlx5_flow_os_create_flow_action_modify_header
4253                                         (sh->ctx, ns, cache_resource,
4254                                          actions_len, &cache_resource->action);
4255         if (ret) {
4256                 mlx5_free(cache_resource);
4257                 return rte_flow_error_set(error, ENOMEM,
4258                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4259                                           NULL, "cannot create action");
4260         }
4261         rte_atomic32_init(&cache_resource->refcnt);
4262         rte_atomic32_inc(&cache_resource->refcnt);
4263         if (mlx5_hlist_insert_ex(sh->modify_cmds, &cache_resource->entry,
4264                                  flow_dv_modify_hdr_resource_match,
4265                                  (void *)cache_resource)) {
4266                 claim_zero(mlx5_flow_os_destroy_flow_action
4267                                                 (cache_resource->action));
4268                 mlx5_free(cache_resource);
4269                 return rte_flow_error_set(error, EEXIST,
4270                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4271                                           NULL, "action exist");
4272         }
4273         dev_flow->handle->dvh.modify_hdr = cache_resource;
4274         DRV_LOG(DEBUG, "new modify-header resource %p: refcnt %d++",
4275                 (void *)cache_resource,
4276                 rte_atomic32_read(&cache_resource->refcnt));
4277         return 0;
4278 }
4279
4280 /**
4281  * Get DV flow counter by index.
4282  *
4283  * @param[in] dev
4284  *   Pointer to the Ethernet device structure.
4285  * @param[in] idx
4286  *   mlx5 flow counter index in the container.
4287  * @param[out] ppool
4288  *   mlx5 flow counter pool in the container,
4289  *
4290  * @return
4291  *   Pointer to the counter, NULL otherwise.
4292  */
4293 static struct mlx5_flow_counter *
4294 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
4295                            uint32_t idx,
4296                            struct mlx5_flow_counter_pool **ppool)
4297 {
4298         struct mlx5_priv *priv = dev->data->dev_private;
4299         struct mlx5_pools_container *cont;
4300         struct mlx5_flow_counter_pool *pool;
4301         uint32_t batch = 0, age = 0;
4302
4303         idx--;
4304         age = MLX_CNT_IS_AGE(idx);
4305         idx = age ? idx - MLX5_CNT_AGE_OFFSET : idx;
4306         if (idx >= MLX5_CNT_BATCH_OFFSET) {
4307                 idx -= MLX5_CNT_BATCH_OFFSET;
4308                 batch = 1;
4309         }
4310         cont = MLX5_CNT_CONTAINER(priv->sh, batch, age);
4311         MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cont->n);
4312         pool = cont->pools[idx / MLX5_COUNTERS_PER_POOL];
4313         MLX5_ASSERT(pool);
4314         if (ppool)
4315                 *ppool = pool;
4316         return MLX5_POOL_GET_CNT(pool, idx % MLX5_COUNTERS_PER_POOL);
4317 }
4318
4319 /**
4320  * Check the devx counter belongs to the pool.
4321  *
4322  * @param[in] pool
4323  *   Pointer to the counter pool.
4324  * @param[in] id
4325  *   The counter devx ID.
4326  *
4327  * @return
4328  *   True if counter belongs to the pool, false otherwise.
4329  */
4330 static bool
4331 flow_dv_is_counter_in_pool(struct mlx5_flow_counter_pool *pool, int id)
4332 {
4333         int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
4334                    MLX5_COUNTERS_PER_POOL;
4335
4336         if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
4337                 return true;
4338         return false;
4339 }
4340
4341 /**
4342  * Get a pool by devx counter ID.
4343  *
4344  * @param[in] cont
4345  *   Pointer to the counter container.
4346  * @param[in] id
4347  *   The counter devx ID.
4348  *
4349  * @return
4350  *   The counter pool pointer if exists, NULL otherwise,
4351  */
4352 static struct mlx5_flow_counter_pool *
4353 flow_dv_find_pool_by_id(struct mlx5_pools_container *cont, int id)
4354 {
4355         uint32_t i;
4356
4357         /* Check last used pool. */
4358         if (cont->last_pool_idx != POOL_IDX_INVALID &&
4359             flow_dv_is_counter_in_pool(cont->pools[cont->last_pool_idx], id))
4360                 return cont->pools[cont->last_pool_idx];
4361         /* ID out of range means no suitable pool in the container. */
4362         if (id > cont->max_id || id < cont->min_id)
4363                 return NULL;
4364         /*
4365          * Find the pool from the end of the container, since mostly counter
4366          * ID is sequence increasing, and the last pool should be the needed
4367          * one.
4368          */
4369         i = rte_atomic16_read(&cont->n_valid);
4370         while (i--) {
4371                 struct mlx5_flow_counter_pool *pool = cont->pools[i];
4372
4373                 if (flow_dv_is_counter_in_pool(pool, id))
4374                         return pool;
4375         }
4376         return NULL;
4377 }
4378
4379 /**
4380  * Allocate a new memory for the counter values wrapped by all the needed
4381  * management.
4382  *
4383  * @param[in] dev
4384  *   Pointer to the Ethernet device structure.
4385  * @param[in] raws_n
4386  *   The raw memory areas - each one for MLX5_COUNTERS_PER_POOL counters.
4387  *
4388  * @return
4389  *   The new memory management pointer on success, otherwise NULL and rte_errno
4390  *   is set.
4391  */
4392 static struct mlx5_counter_stats_mem_mng *
4393 flow_dv_create_counter_stat_mem_mng(struct rte_eth_dev *dev, int raws_n)
4394 {
4395         struct mlx5_priv *priv = dev->data->dev_private;
4396         struct mlx5_dev_ctx_shared *sh = priv->sh;
4397         struct mlx5_devx_mkey_attr mkey_attr;
4398         struct mlx5_counter_stats_mem_mng *mem_mng;
4399         volatile struct flow_counter_stats *raw_data;
4400         int size = (sizeof(struct flow_counter_stats) *
4401                         MLX5_COUNTERS_PER_POOL +
4402                         sizeof(struct mlx5_counter_stats_raw)) * raws_n +
4403                         sizeof(struct mlx5_counter_stats_mem_mng);
4404         size_t pgsize = rte_mem_page_size();
4405         if (pgsize == (size_t)-1) {
4406                 DRV_LOG(ERR, "Failed to get mem page size");
4407                 rte_errno = ENOMEM;
4408                 return NULL;
4409         }
4410         uint8_t *mem = mlx5_malloc(MLX5_MEM_ZERO, size, pgsize,
4411                                   SOCKET_ID_ANY);
4412         int i;
4413
4414         if (!mem) {
4415                 rte_errno = ENOMEM;
4416                 return NULL;
4417         }
4418         mem_mng = (struct mlx5_counter_stats_mem_mng *)(mem + size) - 1;
4419         size = sizeof(*raw_data) * MLX5_COUNTERS_PER_POOL * raws_n;
4420         mem_mng->umem = mlx5_glue->devx_umem_reg(sh->ctx, mem, size,
4421                                                  IBV_ACCESS_LOCAL_WRITE);
4422         if (!mem_mng->umem) {
4423                 rte_errno = errno;
4424                 mlx5_free(mem);
4425                 return NULL;
4426         }
4427         mkey_attr.addr = (uintptr_t)mem;
4428         mkey_attr.size = size;
4429         mkey_attr.umem_id = mlx5_os_get_umem_id(mem_mng->umem);
4430         mkey_attr.pd = sh->pdn;
4431         mkey_attr.log_entity_size = 0;
4432         mkey_attr.pg_access = 0;
4433         mkey_attr.klm_array = NULL;
4434         mkey_attr.klm_num = 0;
4435         if (priv->config.hca_attr.relaxed_ordering_write &&
4436                 priv->config.hca_attr.relaxed_ordering_read  &&
4437                 !haswell_broadwell_cpu)
4438                 mkey_attr.relaxed_ordering = 1;
4439         mem_mng->dm = mlx5_devx_cmd_mkey_create(sh->ctx, &mkey_attr);
4440         if (!mem_mng->dm) {
4441                 mlx5_glue->devx_umem_dereg(mem_mng->umem);
4442                 rte_errno = errno;
4443                 mlx5_free(mem);
4444                 return NULL;
4445         }
4446         mem_mng->raws = (struct mlx5_counter_stats_raw *)(mem + size);
4447         raw_data = (volatile struct flow_counter_stats *)mem;
4448         for (i = 0; i < raws_n; ++i) {
4449                 mem_mng->raws[i].mem_mng = mem_mng;
4450                 mem_mng->raws[i].data = raw_data + i * MLX5_COUNTERS_PER_POOL;
4451         }
4452         LIST_INSERT_HEAD(&sh->cmng.mem_mngs, mem_mng, next);
4453         return mem_mng;
4454 }
4455
4456 /**
4457  * Resize a counter container.
4458  *
4459  * @param[in] dev
4460  *   Pointer to the Ethernet device structure.
4461  * @param[in] batch
4462  *   Whether the pool is for counter that was allocated by batch command.
4463  * @param[in] age
4464  *   Whether the pool is for Aging counter.
4465  *
4466  * @return
4467  *   0 on success, otherwise negative errno value and rte_errno is set.
4468  */
4469 static int
4470 flow_dv_container_resize(struct rte_eth_dev *dev,
4471                                 uint32_t batch, uint32_t age)
4472 {
4473         struct mlx5_priv *priv = dev->data->dev_private;
4474         struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4475                                                                age);
4476         struct mlx5_counter_stats_mem_mng *mem_mng = NULL;
4477         void *old_pools = cont->pools;
4478         uint32_t resize = cont->n + MLX5_CNT_CONTAINER_RESIZE;
4479         uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
4480         void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
4481
4482         if (!pools) {
4483                 rte_errno = ENOMEM;
4484                 return -ENOMEM;
4485         }
4486         if (old_pools)
4487                 memcpy(pools, old_pools, cont->n *
4488                                        sizeof(struct mlx5_flow_counter_pool *));
4489         /*
4490          * Fallback mode query the counter directly, no background query
4491          * resources are needed.
4492          */
4493         if (!priv->counter_fallback) {
4494                 int i;
4495
4496                 mem_mng = flow_dv_create_counter_stat_mem_mng(dev,
4497                           MLX5_CNT_CONTAINER_RESIZE + MLX5_MAX_PENDING_QUERIES);
4498                 if (!mem_mng) {
4499                         mlx5_free(pools);
4500                         return -ENOMEM;
4501                 }
4502                 for (i = 0; i < MLX5_MAX_PENDING_QUERIES; ++i)
4503                         LIST_INSERT_HEAD(&priv->sh->cmng.free_stat_raws,
4504                                          mem_mng->raws +
4505                                          MLX5_CNT_CONTAINER_RESIZE +
4506                                          i, next);
4507         }
4508         rte_spinlock_lock(&cont->resize_sl);
4509         cont->n = resize;
4510         cont->mem_mng = mem_mng;
4511         cont->pools = pools;
4512         rte_spinlock_unlock(&cont->resize_sl);
4513         if (old_pools)
4514                 mlx5_free(old_pools);
4515         return 0;
4516 }
4517
4518 /**
4519  * Query a devx flow counter.
4520  *
4521  * @param[in] dev
4522  *   Pointer to the Ethernet device structure.
4523  * @param[in] cnt
4524  *   Index to the flow counter.
4525  * @param[out] pkts
4526  *   The statistics value of packets.
4527  * @param[out] bytes
4528  *   The statistics value of bytes.
4529  *
4530  * @return
4531  *   0 on success, otherwise a negative errno value and rte_errno is set.
4532  */
4533 static inline int
4534 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
4535                      uint64_t *bytes)
4536 {
4537         struct mlx5_priv *priv = dev->data->dev_private;
4538         struct mlx5_flow_counter_pool *pool = NULL;
4539         struct mlx5_flow_counter *cnt;
4540         struct mlx5_flow_counter_ext *cnt_ext = NULL;
4541         int offset;
4542
4543         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
4544         MLX5_ASSERT(pool);
4545         if (counter < MLX5_CNT_BATCH_OFFSET) {
4546                 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt);
4547                 if (priv->counter_fallback)
4548                         return mlx5_devx_cmd_flow_counter_query(cnt_ext->dcs, 0,
4549                                         0, pkts, bytes, 0, NULL, NULL, 0);
4550         }
4551
4552         rte_spinlock_lock(&pool->sl);
4553         /*
4554          * The single counters allocation may allocate smaller ID than the
4555          * current allocated in parallel to the host reading.
4556          * In this case the new counter values must be reported as 0.
4557          */
4558         if (unlikely(cnt_ext && cnt_ext->dcs->id < pool->raw->min_dcs_id)) {
4559                 *pkts = 0;
4560                 *bytes = 0;
4561         } else {
4562                 offset = MLX5_CNT_ARRAY_IDX(pool, cnt);
4563                 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
4564                 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
4565         }
4566         rte_spinlock_unlock(&pool->sl);
4567         return 0;
4568 }
4569
4570 /**
4571  * Create and initialize a new counter pool.
4572  *
4573  * @param[in] dev
4574  *   Pointer to the Ethernet device structure.
4575  * @param[out] dcs
4576  *   The devX counter handle.
4577  * @param[in] batch
4578  *   Whether the pool is for counter that was allocated by batch command.
4579  * @param[in] age
4580  *   Whether the pool is for counter that was allocated for aging.
4581  * @param[in/out] cont_cur
4582  *   Pointer to the container pointer, it will be update in pool resize.
4583  *
4584  * @return
4585  *   The pool container pointer on success, NULL otherwise and rte_errno is set.
4586  */
4587 static struct mlx5_flow_counter_pool *
4588 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
4589                     uint32_t batch, uint32_t age)
4590 {
4591         struct mlx5_priv *priv = dev->data->dev_private;
4592         struct mlx5_flow_counter_pool *pool;
4593         struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4594                                                                age);
4595         int16_t n_valid = rte_atomic16_read(&cont->n_valid);
4596         uint32_t size = sizeof(*pool);
4597
4598         if (cont->n == n_valid && flow_dv_container_resize(dev, batch, age))
4599                 return NULL;
4600         size += MLX5_COUNTERS_PER_POOL * CNT_SIZE;
4601         size += (batch ? 0 : MLX5_COUNTERS_PER_POOL * CNTEXT_SIZE);
4602         size += (!age ? 0 : MLX5_COUNTERS_PER_POOL * AGE_SIZE);
4603         pool = mlx5_malloc(MLX5_MEM_ZERO, size, 0, SOCKET_ID_ANY);
4604         if (!pool) {
4605                 rte_errno = ENOMEM;
4606                 return NULL;
4607         }
4608         pool->min_dcs = dcs;
4609         if (!priv->counter_fallback)
4610                 pool->raw = cont->mem_mng->raws + n_valid %
4611                                                       MLX5_CNT_CONTAINER_RESIZE;
4612         pool->raw_hw = NULL;
4613         pool->type = 0;
4614         pool->type |= (batch ? 0 :  CNT_POOL_TYPE_EXT);
4615         pool->type |= (!age ? 0 :  CNT_POOL_TYPE_AGE);
4616         pool->query_gen = 0;
4617         rte_spinlock_init(&pool->sl);
4618         TAILQ_INIT(&pool->counters[0]);
4619         TAILQ_INIT(&pool->counters[1]);
4620         TAILQ_INSERT_HEAD(&cont->pool_list, pool, next);
4621         pool->index = n_valid;
4622         cont->pools[n_valid] = pool;
4623         if (!batch) {
4624                 int base = RTE_ALIGN_FLOOR(dcs->id, MLX5_COUNTERS_PER_POOL);
4625
4626                 if (base < cont->min_id)
4627                         cont->min_id = base;
4628                 if (base > cont->max_id)
4629                         cont->max_id = base + MLX5_COUNTERS_PER_POOL - 1;
4630                 cont->last_pool_idx = pool->index;
4631         }
4632         /* Pool initialization must be updated before host thread access. */
4633         rte_io_wmb();
4634         rte_atomic16_add(&cont->n_valid, 1);
4635         return pool;
4636 }
4637
4638 /**
4639  * Restore skipped counters in the pool.
4640  *
4641  * As counter pool query requires the first counter dcs
4642  * ID start with 4 alinged, if the pool counters with
4643  * min_dcs ID are not aligned with 4, the counters will
4644  * be skipped.
4645  * Once other min_dcs ID less than these skipped counter
4646  * dcs ID appears, the skipped counters will be safe to
4647  * use.
4648  * Should be called when min_dcs is updated.
4649  *
4650  * @param[in] pool
4651  *   Current counter pool.
4652  * @param[in] last_min_dcs
4653  *   Last min_dcs.
4654  */
4655 static void
4656 flow_dv_counter_restore(struct mlx5_flow_counter_pool *pool,
4657                         struct mlx5_devx_obj *last_min_dcs)
4658 {
4659         struct mlx5_flow_counter_ext *cnt_ext;
4660         uint32_t offset, new_offset;
4661         uint32_t skip_cnt = 0;
4662         uint32_t i;
4663
4664         if (!pool->skip_cnt)
4665                 return;
4666         /*
4667          * If last min_dcs is not valid. The skipped counter may even after
4668          * last min_dcs, set the offset to the whole pool.
4669          */
4670         if (last_min_dcs->id & (MLX5_CNT_BATCH_QUERY_ID_ALIGNMENT - 1))
4671                 offset = MLX5_COUNTERS_PER_POOL;
4672         else
4673                 offset = last_min_dcs->id % MLX5_COUNTERS_PER_POOL;
4674         new_offset = pool->min_dcs->id % MLX5_COUNTERS_PER_POOL;
4675         /*
4676          * Check the counters from 1 to the last_min_dcs range. Counters
4677          * before new min_dcs indicates pool still has skipped counters.
4678          * Counters be skipped after new min_dcs will be ready to use.
4679          * Offset 0 counter must be empty or min_dcs, start from 1.
4680          */
4681         for (i = 1; i < offset; i++) {
4682                 cnt_ext = MLX5_GET_POOL_CNT_EXT(pool, i);
4683                 if (cnt_ext->skipped) {
4684                         if (i > new_offset) {
4685                                 cnt_ext->skipped = 0;
4686                                 TAILQ_INSERT_TAIL
4687                                         (&pool->counters[pool->query_gen],
4688                                          MLX5_POOL_GET_CNT(pool, i), next);
4689                         } else {
4690                                 skip_cnt++;
4691                         }
4692                 }
4693         }
4694         if (!skip_cnt)
4695                 pool->skip_cnt = 0;
4696 }
4697
4698 /**
4699  * Prepare a new counter and/or a new counter pool.
4700  *
4701  * @param[in] dev
4702  *   Pointer to the Ethernet device structure.
4703  * @param[out] cnt_free
4704  *   Where to put the pointer of a new counter.
4705  * @param[in] batch
4706  *   Whether the pool is for counter that was allocated by batch command.
4707  * @param[in] age
4708  *   Whether the pool is for counter that was allocated for aging.
4709  *
4710  * @return
4711  *   The counter pool pointer and @p cnt_free is set on success,
4712  *   NULL otherwise and rte_errno is set.
4713  */
4714 static struct mlx5_flow_counter_pool *
4715 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
4716                              struct mlx5_flow_counter **cnt_free,
4717                              uint32_t batch, uint32_t age)
4718 {
4719         struct mlx5_priv *priv = dev->data->dev_private;
4720         struct mlx5_pools_container *cont;
4721         struct mlx5_flow_counter_pool *pool;
4722         struct mlx5_counters tmp_tq;
4723         struct mlx5_devx_obj *last_min_dcs;
4724         struct mlx5_devx_obj *dcs = NULL;
4725         struct mlx5_flow_counter *cnt;
4726         uint32_t add2other;
4727         uint32_t i;
4728
4729         cont = MLX5_CNT_CONTAINER(priv->sh, batch, age);
4730         if (!batch) {
4731 retry:
4732                 add2other = 0;
4733                 /* bulk_bitmap must be 0 for single counter allocation. */
4734                 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
4735                 if (!dcs)
4736                         return NULL;
4737                 pool = flow_dv_find_pool_by_id(cont, dcs->id);
4738                 /* Check if counter belongs to exist pool ID range. */
4739                 if (!pool) {
4740                         pool = flow_dv_find_pool_by_id
4741                                (MLX5_CNT_CONTAINER
4742                                (priv->sh, batch, (age ^ 0x1)), dcs->id);
4743                         /*
4744                          * Pool eixsts, counter will be added to the other
4745                          * container, need to reallocate it later.
4746                          */
4747                         if (pool) {
4748                                 add2other = 1;
4749                         } else {
4750                                 pool = flow_dv_pool_create(dev, dcs, batch,
4751                                                            age);
4752                                 if (!pool) {
4753                                         mlx5_devx_cmd_destroy(dcs);
4754                                         return NULL;
4755                                 }
4756                         }
4757                 }
4758                 if ((dcs->id < pool->min_dcs->id ||
4759                     pool->min_dcs->id &
4760                     (MLX5_CNT_BATCH_QUERY_ID_ALIGNMENT - 1)) &&
4761                     !(dcs->id & (MLX5_CNT_BATCH_QUERY_ID_ALIGNMENT - 1))) {
4762                         /*
4763                          * Update the pool min_dcs only if current dcs is
4764                          * valid and exist min_dcs is not valid or greater
4765                          * than new dcs.
4766                          */
4767                         last_min_dcs = pool->min_dcs;
4768                         rte_atomic64_set(&pool->a64_dcs,
4769                                          (int64_t)(uintptr_t)dcs);
4770                         /*
4771                          * Restore any skipped counters if the new min_dcs
4772                          * ID is smaller or min_dcs is not valid.
4773                          */
4774                         if (dcs->id < last_min_dcs->id ||
4775                             last_min_dcs->id &
4776                             (MLX5_CNT_BATCH_QUERY_ID_ALIGNMENT - 1))
4777                                 flow_dv_counter_restore(pool, last_min_dcs);
4778                 }
4779                 i = dcs->id % MLX5_COUNTERS_PER_POOL;
4780                 cnt = MLX5_POOL_GET_CNT(pool, i);
4781                 cnt->pool = pool;
4782                 MLX5_GET_POOL_CNT_EXT(pool, i)->dcs = dcs;
4783                 /*
4784                  * If min_dcs is not valid, it means the new allocated dcs
4785                  * also fail to become the valid min_dcs, just skip it.
4786                  * Or if min_dcs is valid, and new dcs ID is smaller than
4787                  * min_dcs, but not become the min_dcs, also skip it.
4788                  */
4789                 if (pool->min_dcs->id &
4790                     (MLX5_CNT_BATCH_QUERY_ID_ALIGNMENT - 1) ||
4791                     dcs->id < pool->min_dcs->id) {
4792                         MLX5_GET_POOL_CNT_EXT(pool, i)->skipped = 1;
4793                         pool->skip_cnt = 1;
4794                         goto retry;
4795                 }
4796                 if (add2other) {
4797                         TAILQ_INSERT_TAIL(&pool->counters[pool->query_gen],
4798                                           cnt, next);
4799                         goto retry;
4800                 }
4801                 *cnt_free = cnt;
4802                 return pool;
4803         }
4804         /* bulk_bitmap is in 128 counters units. */
4805         if (priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4)
4806                 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
4807         if (!dcs) {
4808                 rte_errno = ENODATA;
4809                 return NULL;
4810         }
4811         pool = flow_dv_pool_create(dev, dcs, batch, age);
4812         if (!pool) {
4813                 mlx5_devx_cmd_destroy(dcs);
4814                 return NULL;
4815         }
4816         TAILQ_INIT(&tmp_tq);
4817         for (i = 1; i < MLX5_COUNTERS_PER_POOL; ++i) {
4818                 cnt = MLX5_POOL_GET_CNT(pool, i);
4819                 cnt->pool = pool;
4820                 TAILQ_INSERT_HEAD(&tmp_tq, cnt, next);
4821         }
4822         rte_spinlock_lock(&cont->csl);
4823         TAILQ_CONCAT(&cont->counters, &tmp_tq, next);
4824         rte_spinlock_unlock(&cont->csl);
4825         *cnt_free = MLX5_POOL_GET_CNT(pool, 0);
4826         (*cnt_free)->pool = pool;
4827         return pool;
4828 }
4829
4830 /**
4831  * Search for existed shared counter.
4832  *
4833  * @param[in] dev
4834  *   Pointer to the Ethernet device structure.
4835  * @param[in] id
4836  *   The shared counter ID to search.
4837  * @param[out] ppool
4838  *   mlx5 flow counter pool in the container,
4839  *
4840  * @return
4841  *   NULL if not existed, otherwise pointer to the shared extend counter.
4842  */
4843 static struct mlx5_flow_counter_ext *
4844 flow_dv_counter_shared_search(struct rte_eth_dev *dev, uint32_t id,
4845                               struct mlx5_flow_counter_pool **ppool)
4846 {
4847         struct mlx5_priv *priv = dev->data->dev_private;
4848         union mlx5_l3t_data data;
4849         uint32_t cnt_idx;
4850
4851         if (mlx5_l3t_get_entry(priv->sh->cnt_id_tbl, id, &data) || !data.dword)
4852                 return NULL;
4853         cnt_idx = data.dword;
4854         /*
4855          * Shared counters don't have age info. The counter extend is after
4856          * the counter datat structure.
4857          */
4858         return (struct mlx5_flow_counter_ext *)
4859                ((flow_dv_counter_get_by_idx(dev, cnt_idx, ppool)) + 1);
4860 }
4861
4862 /**
4863  * Allocate a flow counter.
4864  *
4865  * @param[in] dev
4866  *   Pointer to the Ethernet device structure.
4867  * @param[in] shared
4868  *   Indicate if this counter is shared with other flows.
4869  * @param[in] id
4870  *   Counter identifier.
4871  * @param[in] group
4872  *   Counter flow group.
4873  * @param[in] age
4874  *   Whether the counter was allocated for aging.
4875  *
4876  * @return
4877  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
4878  */
4879 static uint32_t
4880 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t shared, uint32_t id,
4881                       uint16_t group, uint32_t age)
4882 {
4883         struct mlx5_priv *priv = dev->data->dev_private;
4884         struct mlx5_flow_counter_pool *pool = NULL;
4885         struct mlx5_flow_counter *cnt_free = NULL;
4886         struct mlx5_flow_counter_ext *cnt_ext = NULL;
4887         /*
4888          * Currently group 0 flow counter cannot be assigned to a flow if it is
4889          * not the first one in the batch counter allocation, so it is better
4890          * to allocate counters one by one for these flows in a separate
4891          * container.
4892          * A counter can be shared between different groups so need to take
4893          * shared counters from the single container.
4894          */
4895         uint32_t batch = (group && !shared && !priv->counter_fallback) ? 1 : 0;
4896         struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4897                                                                age);
4898         uint32_t cnt_idx;
4899
4900         if (!priv->config.devx) {
4901                 rte_errno = ENOTSUP;
4902                 return 0;
4903         }
4904         if (shared) {
4905                 cnt_ext = flow_dv_counter_shared_search(dev, id, &pool);
4906                 if (cnt_ext) {
4907                         if (cnt_ext->ref_cnt + 1 == 0) {
4908                                 rte_errno = E2BIG;
4909                                 return 0;
4910                         }
4911                         cnt_ext->ref_cnt++;
4912                         cnt_idx = pool->index * MLX5_COUNTERS_PER_POOL +
4913                                   (cnt_ext->dcs->id % MLX5_COUNTERS_PER_POOL)
4914                                   + 1;
4915                         return cnt_idx;
4916                 }
4917         }
4918         /* Get free counters from container. */
4919         rte_spinlock_lock(&cont->csl);
4920         cnt_free = TAILQ_FIRST(&cont->counters);
4921         if (cnt_free)
4922                 TAILQ_REMOVE(&cont->counters, cnt_free, next);
4923         rte_spinlock_unlock(&cont->csl);
4924         if (!cnt_free && !flow_dv_counter_pool_prepare(dev, &cnt_free,
4925                                                        batch, age))
4926                 goto err;
4927         pool = cnt_free->pool;
4928         if (!batch)
4929                 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt_free);
4930         /* Create a DV counter action only in the first time usage. */
4931         if (!cnt_free->action) {
4932                 uint16_t offset;
4933                 struct mlx5_devx_obj *dcs;
4934                 int ret;
4935
4936                 if (batch) {
4937                         offset = MLX5_CNT_ARRAY_IDX(pool, cnt_free);
4938                         dcs = pool->min_dcs;
4939                 } else {
4940                         offset = 0;
4941                         dcs = cnt_ext->dcs;
4942                 }
4943                 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, offset,
4944                                                             &cnt_free->action);
4945                 if (ret) {
4946                         rte_errno = errno;
4947                         goto err;
4948                 }
4949         }
4950         cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
4951                                 MLX5_CNT_ARRAY_IDX(pool, cnt_free));
4952         cnt_idx += batch * MLX5_CNT_BATCH_OFFSET;
4953         cnt_idx += age * MLX5_CNT_AGE_OFFSET;
4954         /* Update the counter reset values. */
4955         if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
4956                                  &cnt_free->bytes))
4957                 goto err;
4958         if (cnt_ext) {
4959                 cnt_ext->shared = shared;
4960                 cnt_ext->ref_cnt = 1;
4961                 cnt_ext->id = id;
4962                 if (shared) {
4963                         union mlx5_l3t_data data;
4964
4965                         data.dword = cnt_idx;
4966                         if (mlx5_l3t_set_entry(priv->sh->cnt_id_tbl, id, &data))
4967                                 return 0;
4968                 }
4969         }
4970         if (!priv->counter_fallback && !priv->sh->cmng.query_thread_on)
4971                 /* Start the asynchronous batch query by the host thread. */
4972                 mlx5_set_query_alarm(priv->sh);
4973         return cnt_idx;
4974 err:
4975         if (cnt_free) {
4976                 cnt_free->pool = pool;
4977                 rte_spinlock_lock(&cont->csl);
4978                 TAILQ_INSERT_TAIL(&cont->counters, cnt_free, next);
4979                 rte_spinlock_unlock(&cont->csl);
4980         }
4981         return 0;
4982 }
4983
4984 /**
4985  * Get age param from counter index.
4986  *
4987  * @param[in] dev
4988  *   Pointer to the Ethernet device structure.
4989  * @param[in] counter
4990  *   Index to the counter handler.
4991  *
4992  * @return
4993  *   The aging parameter specified for the counter index.
4994  */
4995 static struct mlx5_age_param*
4996 flow_dv_counter_idx_get_age(struct rte_eth_dev *dev,
4997                                 uint32_t counter)
4998 {
4999         struct mlx5_flow_counter *cnt;
5000         struct mlx5_flow_counter_pool *pool = NULL;
5001
5002         flow_dv_counter_get_by_idx(dev, counter, &pool);
5003         counter = (counter - 1) % MLX5_COUNTERS_PER_POOL;
5004         cnt = MLX5_POOL_GET_CNT(pool, counter);
5005         return MLX5_CNT_TO_AGE(cnt);
5006 }
5007
5008 /**
5009  * Remove a flow counter from aged counter list.
5010  *
5011  * @param[in] dev
5012  *   Pointer to the Ethernet device structure.
5013  * @param[in] counter
5014  *   Index to the counter handler.
5015  * @param[in] cnt
5016  *   Pointer to the counter handler.
5017  */
5018 static void
5019 flow_dv_counter_remove_from_age(struct rte_eth_dev *dev,
5020                                 uint32_t counter, struct mlx5_flow_counter *cnt)
5021 {
5022         struct mlx5_age_info *age_info;
5023         struct mlx5_age_param *age_param;
5024         struct mlx5_priv *priv = dev->data->dev_private;
5025
5026         age_info = GET_PORT_AGE_INFO(priv);
5027         age_param = flow_dv_counter_idx_get_age(dev, counter);
5028         if (rte_atomic16_cmpset((volatile uint16_t *)
5029                         &age_param->state,
5030                         AGE_CANDIDATE, AGE_FREE)
5031                         != AGE_CANDIDATE) {
5032                 /**
5033                  * We need the lock even it is age timeout,
5034                  * since counter may still in process.
5035                  */
5036                 rte_spinlock_lock(&age_info->aged_sl);
5037                 TAILQ_REMOVE(&age_info->aged_counters, cnt, next);
5038                 rte_spinlock_unlock(&age_info->aged_sl);
5039         }
5040         rte_atomic16_set(&age_param->state, AGE_FREE);
5041 }
5042 /**
5043  * Release a flow counter.
5044  *
5045  * @param[in] dev
5046  *   Pointer to the Ethernet device structure.
5047  * @param[in] counter
5048  *   Index to the counter handler.
5049  */
5050 static void
5051 flow_dv_counter_release(struct rte_eth_dev *dev, uint32_t counter)
5052 {
5053         struct mlx5_priv *priv = dev->data->dev_private;
5054         struct mlx5_flow_counter_pool *pool = NULL;
5055         struct mlx5_flow_counter *cnt;
5056         struct mlx5_flow_counter_ext *cnt_ext = NULL;
5057
5058         if (!counter)
5059                 return;
5060         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
5061         MLX5_ASSERT(pool);
5062         if (counter < MLX5_CNT_BATCH_OFFSET) {
5063                 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt);
5064                 if (cnt_ext) {
5065                         if (--cnt_ext->ref_cnt)
5066                                 return;
5067                         if (cnt_ext->shared)
5068                                 mlx5_l3t_clear_entry(priv->sh->cnt_id_tbl,
5069                                                      cnt_ext->id);
5070                 }
5071         }
5072         if (IS_AGE_POOL(pool))
5073                 flow_dv_counter_remove_from_age(dev, counter, cnt);
5074         cnt->pool = pool;
5075         /*
5076          * Put the counter back to list to be updated in none fallback mode.
5077          * Currently, we are using two list alternately, while one is in query,
5078          * add the freed counter to the other list based on the pool query_gen
5079          * value. After query finishes, add counter the list to the global
5080          * container counter list. The list changes while query starts. In
5081          * this case, lock will not be needed as query callback and release
5082          * function both operate with the different list.
5083          *
5084          */
5085         if (!priv->counter_fallback)
5086                 TAILQ_INSERT_TAIL(&pool->counters[pool->query_gen], cnt, next);
5087         else
5088                 TAILQ_INSERT_TAIL(&((MLX5_CNT_CONTAINER
5089                                   (priv->sh, 0, 0))->counters),
5090                                   cnt, next);
5091 }
5092
5093 /**
5094  * Verify the @p attributes will be correctly understood by the NIC and store
5095  * them in the @p flow if everything is correct.
5096  *
5097  * @param[in] dev
5098  *   Pointer to dev struct.
5099  * @param[in] attributes
5100  *   Pointer to flow attributes
5101  * @param[in] external
5102  *   This flow rule is created by request external to PMD.
5103  * @param[out] error
5104  *   Pointer to error structure.
5105  *
5106  * @return
5107  *   - 0 on success and non root table.
5108  *   - 1 on success and root table.
5109  *   - a negative errno value otherwise and rte_errno is set.
5110  */
5111 static int
5112 flow_dv_validate_attributes(struct rte_eth_dev *dev,
5113                             const struct rte_flow_attr *attributes,
5114                             bool external __rte_unused,
5115                             struct rte_flow_error *error)
5116 {
5117         struct mlx5_priv *priv = dev->data->dev_private;
5118         uint32_t priority_max = priv->config.flow_prio - 1;
5119         int ret = 0;
5120
5121 #ifndef HAVE_MLX5DV_DR
5122         if (attributes->group)
5123                 return rte_flow_error_set(error, ENOTSUP,
5124                                           RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
5125                                           NULL,
5126                                           "groups are not supported");
5127 #else
5128         uint32_t table = 0;
5129
5130         ret = mlx5_flow_group_to_table(attributes, external,
5131                                        attributes->group, !!priv->fdb_def_rule,
5132                                        &table, error);
5133         if (ret)
5134                 return ret;
5135         if (!table)
5136                 ret = MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
5137 #endif
5138         if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
5139             attributes->priority >= priority_max)
5140                 return rte_flow_error_set(error, ENOTSUP,
5141                                           RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
5142                                           NULL,
5143                                           "priority out of range");
5144         if (attributes->transfer) {
5145                 if (!priv->config.dv_esw_en)
5146                         return rte_flow_error_set
5147                                 (error, ENOTSUP,
5148                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5149                                  "E-Switch dr is not supported");
5150                 if (!(priv->representor || priv->master))
5151                         return rte_flow_error_set
5152                                 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5153                                  NULL, "E-Switch configuration can only be"
5154                                  " done by a master or a representor device");
5155                 if (attributes->egress)
5156                         return rte_flow_error_set
5157                                 (error, ENOTSUP,
5158                                  RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
5159                                  "egress is not supported");
5160         }
5161         if (!(attributes->egress ^ attributes->ingress))
5162                 return rte_flow_error_set(error, ENOTSUP,
5163                                           RTE_FLOW_ERROR_TYPE_ATTR, NULL,
5164                                           "must specify exactly one of "
5165                                           "ingress or egress");
5166         return ret;
5167 }
5168
5169 /**
5170  * Internal validation function. For validating both actions and items.
5171  *
5172  * @param[in] dev
5173  *   Pointer to the rte_eth_dev structure.
5174  * @param[in] attr
5175  *   Pointer to the flow attributes.
5176  * @param[in] items
5177  *   Pointer to the list of items.
5178  * @param[in] actions
5179  *   Pointer to the list of actions.
5180  * @param[in] external
5181  *   This flow rule is created by request external to PMD.
5182  * @param[in] hairpin
5183  *   Number of hairpin TX actions, 0 means classic flow.
5184  * @param[out] error
5185  *   Pointer to the error structure.
5186  *
5187  * @return
5188  *   0 on success, a negative errno value otherwise and rte_errno is set.
5189  */
5190 static int
5191 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
5192                  const struct rte_flow_item items[],
5193                  const struct rte_flow_action actions[],
5194                  bool external, int hairpin, struct rte_flow_error *error)
5195 {
5196         int ret;
5197         uint64_t action_flags = 0;
5198         uint64_t item_flags = 0;
5199         uint64_t last_item = 0;
5200         uint8_t next_protocol = 0xff;
5201         uint16_t ether_type = 0;
5202         int actions_n = 0;
5203         uint8_t item_ipv6_proto = 0;
5204         const struct rte_flow_item *gre_item = NULL;
5205         const struct rte_flow_action_raw_decap *decap;
5206         const struct rte_flow_action_raw_encap *encap;
5207         const struct rte_flow_action_rss *rss;
5208         const struct rte_flow_item_tcp nic_tcp_mask = {
5209                 .hdr = {
5210                         .tcp_flags = 0xFF,
5211                         .src_port = RTE_BE16(UINT16_MAX),
5212                         .dst_port = RTE_BE16(UINT16_MAX),
5213                 }
5214         };
5215         const struct rte_flow_item_ipv4 nic_ipv4_mask = {
5216                 .hdr = {
5217                         .src_addr = RTE_BE32(0xffffffff),
5218                         .dst_addr = RTE_BE32(0xffffffff),
5219                         .type_of_service = 0xff,
5220                         .next_proto_id = 0xff,
5221                         .time_to_live = 0xff,
5222                 },
5223         };
5224         const struct rte_flow_item_ipv6 nic_ipv6_mask = {
5225                 .hdr = {
5226                         .src_addr =
5227                         "\xff\xff\xff\xff\xff\xff\xff\xff"
5228                         "\xff\xff\xff\xff\xff\xff\xff\xff",
5229                         .dst_addr =
5230                         "\xff\xff\xff\xff\xff\xff\xff\xff"
5231                         "\xff\xff\xff\xff\xff\xff\xff\xff",
5232                         .vtc_flow = RTE_BE32(0xffffffff),
5233                         .proto = 0xff,
5234                         .hop_limits = 0xff,
5235                 },
5236         };
5237         const struct rte_flow_item_ecpri nic_ecpri_mask = {
5238                 .hdr = {
5239                         .common = {
5240                                 .u32 =
5241                                 RTE_BE32(((const struct rte_ecpri_common_hdr) {
5242                                         .type = 0xFF,
5243                                         }).u32),
5244                         },
5245                         .dummy[0] = 0xffffffff,
5246                 },
5247         };
5248         struct mlx5_priv *priv = dev->data->dev_private;
5249         struct mlx5_dev_config *dev_conf = &priv->config;
5250         uint16_t queue_index = 0xFFFF;
5251         const struct rte_flow_item_vlan *vlan_m = NULL;
5252         int16_t rw_act_num = 0;
5253         uint64_t is_root;
5254
5255         if (items == NULL)
5256                 return -1;
5257         ret = flow_dv_validate_attributes(dev, attr, external, error);
5258         if (ret < 0)
5259                 return ret;
5260         is_root = (uint64_t)ret;
5261         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
5262                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
5263                 int type = items->type;
5264
5265                 if (!mlx5_flow_os_item_supported(type))
5266                         return rte_flow_error_set(error, ENOTSUP,
5267                                                   RTE_FLOW_ERROR_TYPE_ITEM,
5268                                                   NULL, "item not supported");
5269                 switch (type) {
5270                 case RTE_FLOW_ITEM_TYPE_VOID:
5271                         break;
5272                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
5273                         ret = flow_dv_validate_item_port_id
5274                                         (dev, items, attr, item_flags, error);
5275                         if (ret < 0)
5276                                 return ret;
5277                         last_item = MLX5_FLOW_ITEM_PORT_ID;
5278                         break;
5279                 case RTE_FLOW_ITEM_TYPE_ETH:
5280                         ret = mlx5_flow_validate_item_eth(items, item_flags,
5281                                                           error);
5282                         if (ret < 0)
5283                                 return ret;
5284                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
5285                                              MLX5_FLOW_LAYER_OUTER_L2;
5286                         if (items->mask != NULL && items->spec != NULL) {
5287                                 ether_type =
5288                                         ((const struct rte_flow_item_eth *)
5289                                          items->spec)->type;
5290                                 ether_type &=
5291                                         ((const struct rte_flow_item_eth *)
5292                                          items->mask)->type;
5293                                 ether_type = rte_be_to_cpu_16(ether_type);
5294                         } else {
5295                                 ether_type = 0;
5296                         }
5297                         break;
5298                 case RTE_FLOW_ITEM_TYPE_VLAN:
5299                         ret = flow_dv_validate_item_vlan(items, item_flags,
5300                                                          dev, error);
5301                         if (ret < 0)
5302                                 return ret;
5303                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
5304                                              MLX5_FLOW_LAYER_OUTER_VLAN;
5305                         if (items->mask != NULL && items->spec != NULL) {
5306                                 ether_type =
5307                                         ((const struct rte_flow_item_vlan *)
5308                                          items->spec)->inner_type;
5309                                 ether_type &=
5310                                         ((const struct rte_flow_item_vlan *)
5311                                          items->mask)->inner_type;
5312                                 ether_type = rte_be_to_cpu_16(ether_type);
5313                         } else {
5314                                 ether_type = 0;
5315                         }
5316                         /* Store outer VLAN mask for of_push_vlan action. */
5317                         if (!tunnel)
5318                                 vlan_m = items->mask;
5319                         break;
5320                 case RTE_FLOW_ITEM_TYPE_IPV4:
5321                         mlx5_flow_tunnel_ip_check(items, next_protocol,
5322                                                   &item_flags, &tunnel);
5323                         ret = mlx5_flow_validate_item_ipv4(items, item_flags,
5324                                                            last_item,
5325                                                            ether_type,
5326                                                            &nic_ipv4_mask,
5327                                                            error);
5328                         if (ret < 0)
5329                                 return ret;
5330                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
5331                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
5332                         if (items->mask != NULL &&
5333                             ((const struct rte_flow_item_ipv4 *)
5334                              items->mask)->hdr.next_proto_id) {
5335                                 next_protocol =
5336                                         ((const struct rte_flow_item_ipv4 *)
5337                                          (items->spec))->hdr.next_proto_id;
5338                                 next_protocol &=
5339                                         ((const struct rte_flow_item_ipv4 *)
5340                                          (items->mask))->hdr.next_proto_id;
5341                         } else {
5342                                 /* Reset for inner layer. */
5343                                 next_protocol = 0xff;
5344                         }
5345                         break;
5346                 case RTE_FLOW_ITEM_TYPE_IPV6:
5347                         mlx5_flow_tunnel_ip_check(items, next_protocol,
5348                                                   &item_flags, &tunnel);
5349                         ret = mlx5_flow_validate_item_ipv6(items, item_flags,
5350                                                            last_item,
5351                                                            ether_type,
5352                                                            &nic_ipv6_mask,
5353                                                            error);
5354                         if (ret < 0)
5355                                 return ret;
5356                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
5357                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
5358                         if (items->mask != NULL &&
5359                             ((const struct rte_flow_item_ipv6 *)
5360                              items->mask)->hdr.proto) {
5361                                 item_ipv6_proto =
5362                                         ((const struct rte_flow_item_ipv6 *)
5363                                          items->spec)->hdr.proto;
5364                                 next_protocol =
5365                                         ((const struct rte_flow_item_ipv6 *)
5366                                          items->spec)->hdr.proto;
5367                                 next_protocol &=
5368                                         ((const struct rte_flow_item_ipv6 *)
5369                                          items->mask)->hdr.proto;
5370                         } else {
5371                                 /* Reset for inner layer. */
5372                                 next_protocol = 0xff;
5373                         }
5374                         break;
5375                 case RTE_FLOW_ITEM_TYPE_TCP:
5376                         ret = mlx5_flow_validate_item_tcp
5377                                                 (items, item_flags,
5378                                                  next_protocol,
5379                                                  &nic_tcp_mask,
5380                                                  error);
5381                         if (ret < 0)
5382                                 return ret;
5383                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
5384                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
5385                         break;
5386                 case RTE_FLOW_ITEM_TYPE_UDP:
5387                         ret = mlx5_flow_validate_item_udp(items, item_flags,
5388                                                           next_protocol,
5389                                                           error);
5390                         if (ret < 0)
5391                                 return ret;
5392                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
5393                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
5394                         break;
5395                 case RTE_FLOW_ITEM_TYPE_GRE:
5396                         ret = mlx5_flow_validate_item_gre(items, item_flags,
5397                                                           next_protocol, error);
5398                         if (ret < 0)
5399                                 return ret;
5400                         gre_item = items;
5401                         last_item = MLX5_FLOW_LAYER_GRE;
5402                         break;
5403                 case RTE_FLOW_ITEM_TYPE_NVGRE:
5404                         ret = mlx5_flow_validate_item_nvgre(items, item_flags,
5405                                                             next_protocol,
5406                                                             error);
5407                         if (ret < 0)
5408                                 return ret;
5409                         last_item = MLX5_FLOW_LAYER_NVGRE;
5410                         break;
5411                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
5412                         ret = mlx5_flow_validate_item_gre_key
5413                                 (items, item_flags, gre_item, error);
5414                         if (ret < 0)
5415                                 return ret;
5416                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
5417                         break;
5418                 case RTE_FLOW_ITEM_TYPE_VXLAN:
5419                         ret = mlx5_flow_validate_item_vxlan(items, item_flags,
5420                                                             error);
5421                         if (ret < 0)
5422                                 return ret;
5423                         last_item = MLX5_FLOW_LAYER_VXLAN;
5424                         break;
5425                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
5426                         ret = mlx5_flow_validate_item_vxlan_gpe(items,
5427                                                                 item_flags, dev,
5428                                                                 error);
5429                         if (ret < 0)
5430                                 return ret;
5431                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
5432                         break;
5433                 case RTE_FLOW_ITEM_TYPE_GENEVE:
5434                         ret = mlx5_flow_validate_item_geneve(items,
5435                                                              item_flags, dev,
5436                                                              error);
5437                         if (ret < 0)
5438                                 return ret;
5439                         last_item = MLX5_FLOW_LAYER_GENEVE;
5440                         break;
5441                 case RTE_FLOW_ITEM_TYPE_MPLS:
5442                         ret = mlx5_flow_validate_item_mpls(dev, items,
5443                                                            item_flags,
5444                                                            last_item, error);
5445                         if (ret < 0)
5446                                 return ret;
5447                         last_item = MLX5_FLOW_LAYER_MPLS;
5448                         break;
5449
5450                 case RTE_FLOW_ITEM_TYPE_MARK:
5451                         ret = flow_dv_validate_item_mark(dev, items, attr,
5452                                                          error);
5453                         if (ret < 0)
5454                                 return ret;
5455                         last_item = MLX5_FLOW_ITEM_MARK;
5456                         break;
5457                 case RTE_FLOW_ITEM_TYPE_META:
5458                         ret = flow_dv_validate_item_meta(dev, items, attr,
5459                                                          error);
5460                         if (ret < 0)
5461                                 return ret;
5462                         last_item = MLX5_FLOW_ITEM_METADATA;
5463                         break;
5464                 case RTE_FLOW_ITEM_TYPE_ICMP:
5465                         ret = mlx5_flow_validate_item_icmp(items, item_flags,
5466                                                            next_protocol,
5467                                                            error);
5468                         if (ret < 0)
5469                                 return ret;
5470                         last_item = MLX5_FLOW_LAYER_ICMP;
5471                         break;
5472                 case RTE_FLOW_ITEM_TYPE_ICMP6:
5473                         ret = mlx5_flow_validate_item_icmp6(items, item_flags,
5474                                                             next_protocol,
5475                                                             error);
5476                         if (ret < 0)
5477                                 return ret;
5478                         item_ipv6_proto = IPPROTO_ICMPV6;
5479                         last_item = MLX5_FLOW_LAYER_ICMP6;
5480                         break;
5481                 case RTE_FLOW_ITEM_TYPE_TAG:
5482                         ret = flow_dv_validate_item_tag(dev, items,
5483                                                         attr, error);
5484                         if (ret < 0)
5485                                 return ret;
5486                         last_item = MLX5_FLOW_ITEM_TAG;
5487                         break;
5488                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
5489                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
5490                         break;
5491                 case RTE_FLOW_ITEM_TYPE_GTP:
5492                         ret = flow_dv_validate_item_gtp(dev, items, item_flags,
5493                                                         error);
5494                         if (ret < 0)
5495                                 return ret;
5496                         last_item = MLX5_FLOW_LAYER_GTP;
5497                         break;
5498                 case RTE_FLOW_ITEM_TYPE_ECPRI:
5499                         /* Capacity will be checked in the translate stage. */
5500                         ret = mlx5_flow_validate_item_ecpri(items, item_flags,
5501                                                             last_item,
5502                                                             ether_type,
5503                                                             &nic_ecpri_mask,
5504                                                             error);
5505                         if (ret < 0)
5506                                 return ret;
5507                         last_item = MLX5_FLOW_LAYER_ECPRI;
5508                         break;
5509                 default:
5510                         return rte_flow_error_set(error, ENOTSUP,
5511                                                   RTE_FLOW_ERROR_TYPE_ITEM,
5512                                                   NULL, "item not supported");
5513                 }
5514                 item_flags |= last_item;
5515         }
5516         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
5517                 int type = actions->type;
5518
5519                 if (!mlx5_flow_os_action_supported(type))
5520                         return rte_flow_error_set(error, ENOTSUP,
5521                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5522                                                   actions,
5523                                                   "action not supported");
5524                 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
5525                         return rte_flow_error_set(error, ENOTSUP,
5526                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5527                                                   actions, "too many actions");
5528                 switch (type) {
5529                 case RTE_FLOW_ACTION_TYPE_VOID:
5530                         break;
5531                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5532                         ret = flow_dv_validate_action_port_id(dev,
5533                                                               action_flags,
5534                                                               actions,
5535                                                               attr,
5536                                                               error);
5537                         if (ret)
5538                                 return ret;
5539                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5540                         ++actions_n;
5541                         break;
5542                 case RTE_FLOW_ACTION_TYPE_FLAG:
5543                         ret = flow_dv_validate_action_flag(dev, action_flags,
5544                                                            attr, error);
5545                         if (ret < 0)
5546                                 return ret;
5547                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
5548                                 /* Count all modify-header actions as one. */
5549                                 if (!(action_flags &
5550                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
5551                                         ++actions_n;
5552                                 action_flags |= MLX5_FLOW_ACTION_FLAG |
5553                                                 MLX5_FLOW_ACTION_MARK_EXT;
5554                         } else {
5555                                 action_flags |= MLX5_FLOW_ACTION_FLAG;
5556                                 ++actions_n;
5557                         }
5558                         rw_act_num += MLX5_ACT_NUM_SET_MARK;
5559                         break;
5560                 case RTE_FLOW_ACTION_TYPE_MARK:
5561                         ret = flow_dv_validate_action_mark(dev, actions,
5562                                                            action_flags,
5563                                                            attr, error);
5564                         if (ret < 0)
5565                                 return ret;
5566                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
5567                                 /* Count all modify-header actions as one. */
5568                                 if (!(action_flags &
5569                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
5570                                         ++actions_n;
5571                                 action_flags |= MLX5_FLOW_ACTION_MARK |
5572                                                 MLX5_FLOW_ACTION_MARK_EXT;
5573                         } else {
5574                                 action_flags |= MLX5_FLOW_ACTION_MARK;
5575                                 ++actions_n;
5576                         }
5577                         rw_act_num += MLX5_ACT_NUM_SET_MARK;
5578                         break;
5579                 case RTE_FLOW_ACTION_TYPE_SET_META:
5580                         ret = flow_dv_validate_action_set_meta(dev, actions,
5581                                                                action_flags,
5582                                                                attr, error);
5583                         if (ret < 0)
5584                                 return ret;
5585                         /* Count all modify-header actions as one action. */
5586                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5587                                 ++actions_n;
5588                         action_flags |= MLX5_FLOW_ACTION_SET_META;
5589                         rw_act_num += MLX5_ACT_NUM_SET_META;
5590                         break;
5591                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
5592                         ret = flow_dv_validate_action_set_tag(dev, actions,
5593                                                               action_flags,
5594                                                               attr, error);
5595                         if (ret < 0)
5596                                 return ret;
5597                         /* Count all modify-header actions as one action. */
5598                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5599                                 ++actions_n;
5600                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
5601                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
5602                         break;
5603                 case RTE_FLOW_ACTION_TYPE_DROP:
5604                         ret = mlx5_flow_validate_action_drop(action_flags,
5605                                                              attr, error);
5606                         if (ret < 0)
5607                                 return ret;
5608                         action_flags |= MLX5_FLOW_ACTION_DROP;
5609                         ++actions_n;
5610                         break;
5611                 case RTE_FLOW_ACTION_TYPE_QUEUE:
5612                         ret = mlx5_flow_validate_action_queue(actions,
5613                                                               action_flags, dev,
5614                                                               attr, error);
5615                         if (ret < 0)
5616                                 return ret;
5617                         queue_index = ((const struct rte_flow_action_queue *)
5618                                                         (actions->conf))->index;
5619                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
5620                         ++actions_n;
5621                         break;
5622                 case RTE_FLOW_ACTION_TYPE_RSS:
5623                         rss = actions->conf;
5624                         ret = mlx5_flow_validate_action_rss(actions,
5625                                                             action_flags, dev,
5626                                                             attr, item_flags,
5627                                                             error);
5628                         if (ret < 0)
5629                                 return ret;
5630                         if (rss != NULL && rss->queue_num)
5631                                 queue_index = rss->queue[0];
5632                         action_flags |= MLX5_FLOW_ACTION_RSS;
5633                         ++actions_n;
5634                         break;
5635                 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
5636                         ret =
5637                         mlx5_flow_validate_action_default_miss(action_flags,
5638                                         attr, error);
5639                         if (ret < 0)
5640                                 return ret;
5641                         action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
5642                         ++actions_n;
5643                         break;
5644                 case RTE_FLOW_ACTION_TYPE_COUNT:
5645                         ret = flow_dv_validate_action_count(dev, error);
5646                         if (ret < 0)
5647                                 return ret;
5648                         action_flags |= MLX5_FLOW_ACTION_COUNT;
5649                         ++actions_n;
5650                         break;
5651                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
5652                         if (flow_dv_validate_action_pop_vlan(dev,
5653                                                              action_flags,
5654                                                              actions,
5655                                                              item_flags, attr,
5656                                                              error))
5657                                 return -rte_errno;
5658                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
5659                         ++actions_n;
5660                         break;
5661                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
5662                         ret = flow_dv_validate_action_push_vlan(dev,
5663                                                                 action_flags,
5664                                                                 vlan_m,
5665                                                                 actions, attr,
5666                                                                 error);
5667                         if (ret < 0)
5668                                 return ret;
5669                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
5670                         ++actions_n;
5671                         break;
5672                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
5673                         ret = flow_dv_validate_action_set_vlan_pcp
5674                                                 (action_flags, actions, error);
5675                         if (ret < 0)
5676                                 return ret;
5677                         /* Count PCP with push_vlan command. */
5678                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
5679                         break;
5680                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
5681                         ret = flow_dv_validate_action_set_vlan_vid
5682                                                 (item_flags, action_flags,
5683                                                  actions, error);
5684                         if (ret < 0)
5685                                 return ret;
5686                         /* Count VID with push_vlan command. */
5687                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
5688                         rw_act_num += MLX5_ACT_NUM_MDF_VID;
5689                         break;
5690                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5691                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5692                         ret = flow_dv_validate_action_l2_encap(dev,
5693                                                                action_flags,
5694                                                                actions, attr,
5695                                                                error);
5696                         if (ret < 0)
5697                                 return ret;
5698                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
5699                         ++actions_n;
5700                         break;
5701                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
5702                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
5703                         ret = flow_dv_validate_action_decap(dev, action_flags,
5704                                                             attr, error);
5705                         if (ret < 0)
5706                                 return ret;
5707                         action_flags |= MLX5_FLOW_ACTION_DECAP;
5708                         ++actions_n;
5709                         break;
5710                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5711                         ret = flow_dv_validate_action_raw_encap_decap
5712                                 (dev, NULL, actions->conf, attr, &action_flags,
5713                                  &actions_n, error);
5714                         if (ret < 0)
5715                                 return ret;
5716                         break;
5717                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
5718                         decap = actions->conf;
5719                         while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
5720                                 ;
5721                         if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
5722                                 encap = NULL;
5723                                 actions--;
5724                         } else {
5725                                 encap = actions->conf;
5726                         }
5727                         ret = flow_dv_validate_action_raw_encap_decap
5728                                            (dev,
5729                                             decap ? decap : &empty_decap, encap,
5730                                             attr, &action_flags, &actions_n,
5731                                             error);
5732                         if (ret < 0)
5733                                 return ret;
5734                         break;
5735                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
5736                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
5737                         ret = flow_dv_validate_action_modify_mac(action_flags,
5738                                                                  actions,
5739                                                                  item_flags,
5740                                                                  error);
5741                         if (ret < 0)
5742                                 return ret;
5743                         /* Count all modify-header actions as one action. */
5744                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5745                                 ++actions_n;
5746                         action_flags |= actions->type ==
5747                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
5748                                                 MLX5_FLOW_ACTION_SET_MAC_SRC :
5749                                                 MLX5_FLOW_ACTION_SET_MAC_DST;
5750                         /*
5751                          * Even if the source and destination MAC addresses have
5752                          * overlap in the header with 4B alignment, the convert
5753                          * function will handle them separately and 4 SW actions
5754                          * will be created. And 2 actions will be added each
5755                          * time no matter how many bytes of address will be set.
5756                          */
5757                         rw_act_num += MLX5_ACT_NUM_MDF_MAC;
5758                         break;
5759                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
5760                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
5761                         ret = flow_dv_validate_action_modify_ipv4(action_flags,
5762                                                                   actions,
5763                                                                   item_flags,
5764                                                                   error);
5765                         if (ret < 0)
5766                                 return ret;
5767                         /* Count all modify-header actions as one action. */
5768                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5769                                 ++actions_n;
5770                         action_flags |= actions->type ==
5771                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
5772                                                 MLX5_FLOW_ACTION_SET_IPV4_SRC :
5773                                                 MLX5_FLOW_ACTION_SET_IPV4_DST;
5774                         rw_act_num += MLX5_ACT_NUM_MDF_IPV4;
5775                         break;
5776                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
5777                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
5778                         ret = flow_dv_validate_action_modify_ipv6(action_flags,
5779                                                                   actions,
5780                                                                   item_flags,
5781                                                                   error);
5782                         if (ret < 0)
5783                                 return ret;
5784                         if (item_ipv6_proto == IPPROTO_ICMPV6)
5785                                 return rte_flow_error_set(error, ENOTSUP,
5786                                         RTE_FLOW_ERROR_TYPE_ACTION,
5787                                         actions,
5788                                         "Can't change header "
5789                                         "with ICMPv6 proto");
5790                         /* Count all modify-header actions as one action. */
5791                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5792                                 ++actions_n;
5793                         action_flags |= actions->type ==
5794                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
5795                                                 MLX5_FLOW_ACTION_SET_IPV6_SRC :
5796                                                 MLX5_FLOW_ACTION_SET_IPV6_DST;
5797                         rw_act_num += MLX5_ACT_NUM_MDF_IPV6;
5798                         break;
5799                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
5800                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
5801                         ret = flow_dv_validate_action_modify_tp(action_flags,
5802                                                                 actions,
5803                                                                 item_flags,
5804                                                                 error);
5805                         if (ret < 0)
5806                                 return ret;
5807                         /* Count all modify-header actions as one action. */
5808                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5809                                 ++actions_n;
5810                         action_flags |= actions->type ==
5811                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
5812                                                 MLX5_FLOW_ACTION_SET_TP_SRC :
5813                                                 MLX5_FLOW_ACTION_SET_TP_DST;
5814                         rw_act_num += MLX5_ACT_NUM_MDF_PORT;
5815                         break;
5816                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
5817                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
5818                         ret = flow_dv_validate_action_modify_ttl(action_flags,
5819                                                                  actions,
5820                                                                  item_flags,
5821                                                                  error);
5822                         if (ret < 0)
5823                                 return ret;
5824                         /* Count all modify-header actions as one action. */
5825                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5826                                 ++actions_n;
5827                         action_flags |= actions->type ==
5828                                         RTE_FLOW_ACTION_TYPE_SET_TTL ?
5829                                                 MLX5_FLOW_ACTION_SET_TTL :
5830                                                 MLX5_FLOW_ACTION_DEC_TTL;
5831                         rw_act_num += MLX5_ACT_NUM_MDF_TTL;
5832                         break;
5833                 case RTE_FLOW_ACTION_TYPE_JUMP:
5834                         ret = flow_dv_validate_action_jump(actions,
5835                                                            action_flags,
5836                                                            attr, external,
5837                                                            error);
5838                         if (ret)
5839                                 return ret;
5840                         ++actions_n;
5841                         action_flags |= MLX5_FLOW_ACTION_JUMP;
5842                         break;
5843                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
5844                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
5845                         ret = flow_dv_validate_action_modify_tcp_seq
5846                                                                 (action_flags,
5847                                                                  actions,
5848                                                                  item_flags,
5849                                                                  error);
5850                         if (ret < 0)
5851                                 return ret;
5852                         /* Count all modify-header actions as one action. */
5853                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5854                                 ++actions_n;
5855                         action_flags |= actions->type ==
5856                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
5857                                                 MLX5_FLOW_ACTION_INC_TCP_SEQ :
5858                                                 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
5859                         rw_act_num += MLX5_ACT_NUM_MDF_TCPSEQ;
5860                         break;
5861                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
5862                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
5863                         ret = flow_dv_validate_action_modify_tcp_ack
5864                                                                 (action_flags,
5865                                                                  actions,
5866                                                                  item_flags,
5867                                                                  error);
5868                         if (ret < 0)
5869                                 return ret;
5870                         /* Count all modify-header actions as one action. */
5871                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5872                                 ++actions_n;
5873                         action_flags |= actions->type ==
5874                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
5875                                                 MLX5_FLOW_ACTION_INC_TCP_ACK :
5876                                                 MLX5_FLOW_ACTION_DEC_TCP_ACK;
5877                         rw_act_num += MLX5_ACT_NUM_MDF_TCPACK;
5878                         break;
5879                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
5880                         break;
5881                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
5882                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
5883                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
5884                         break;
5885                 case RTE_FLOW_ACTION_TYPE_METER:
5886                         ret = mlx5_flow_validate_action_meter(dev,
5887                                                               action_flags,
5888                                                               actions, attr,
5889                                                               error);
5890                         if (ret < 0)
5891                                 return ret;
5892                         action_flags |= MLX5_FLOW_ACTION_METER;
5893                         ++actions_n;
5894                         /* Meter action will add one more TAG action. */
5895                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
5896                         break;
5897                 case RTE_FLOW_ACTION_TYPE_AGE:
5898                         ret = flow_dv_validate_action_age(action_flags,
5899                                                           actions, dev,
5900                                                           error);
5901                         if (ret < 0)
5902                                 return ret;
5903                         action_flags |= MLX5_FLOW_ACTION_AGE;
5904                         ++actions_n;
5905                         break;
5906                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
5907                         ret = flow_dv_validate_action_modify_ipv4_dscp
5908                                                          (action_flags,
5909                                                           actions,
5910                                                           item_flags,
5911                                                           error);
5912                         if (ret < 0)
5913                                 return ret;
5914                         /* Count all modify-header actions as one action. */
5915                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5916                                 ++actions_n;
5917                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
5918                         rw_act_num += MLX5_ACT_NUM_SET_DSCP;
5919                         break;
5920                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
5921                         ret = flow_dv_validate_action_modify_ipv6_dscp
5922                                                                 (action_flags,
5923                                                                  actions,
5924                                                                  item_flags,
5925                                                                  error);
5926                         if (ret < 0)
5927                                 return ret;
5928                         /* Count all modify-header actions as one action. */
5929                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5930                                 ++actions_n;
5931                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
5932                         rw_act_num += MLX5_ACT_NUM_SET_DSCP;
5933                         break;
5934                 case RTE_FLOW_ACTION_TYPE_SAMPLE:
5935                         ret = flow_dv_validate_action_sample(action_flags,
5936                                                              actions, dev,
5937                                                              attr, error);
5938                         if (ret < 0)
5939                                 return ret;
5940                         action_flags |= MLX5_FLOW_ACTION_SAMPLE;
5941                         ++actions_n;
5942                         break;
5943                 default:
5944                         return rte_flow_error_set(error, ENOTSUP,
5945                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5946                                                   actions,
5947                                                   "action not supported");
5948                 }
5949         }
5950         /*
5951          * Validate the drop action mutual exclusion with other actions.
5952          * Drop action is mutually-exclusive with any other action, except for
5953          * Count action.
5954          */
5955         if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
5956             (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
5957                 return rte_flow_error_set(error, EINVAL,
5958                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5959                                           "Drop action is mutually-exclusive "
5960                                           "with any other action, except for "
5961                                           "Count action");
5962         /* Eswitch has few restrictions on using items and actions */
5963         if (attr->transfer) {
5964                 if (!mlx5_flow_ext_mreg_supported(dev) &&
5965                     action_flags & MLX5_FLOW_ACTION_FLAG)
5966                         return rte_flow_error_set(error, ENOTSUP,
5967                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5968                                                   NULL,
5969                                                   "unsupported action FLAG");
5970                 if (!mlx5_flow_ext_mreg_supported(dev) &&
5971                     action_flags & MLX5_FLOW_ACTION_MARK)
5972                         return rte_flow_error_set(error, ENOTSUP,
5973                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5974                                                   NULL,
5975                                                   "unsupported action MARK");
5976                 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
5977                         return rte_flow_error_set(error, ENOTSUP,
5978                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5979                                                   NULL,
5980                                                   "unsupported action QUEUE");
5981                 if (action_flags & MLX5_FLOW_ACTION_RSS)
5982                         return rte_flow_error_set(error, ENOTSUP,
5983                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5984                                                   NULL,
5985                                                   "unsupported action RSS");
5986                 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
5987                         return rte_flow_error_set(error, EINVAL,
5988                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5989                                                   actions,
5990                                                   "no fate action is found");
5991         } else {
5992                 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
5993                         return rte_flow_error_set(error, EINVAL,
5994                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5995                                                   actions,
5996                                                   "no fate action is found");
5997         }
5998         /* Continue validation for Xcap and VLAN actions.*/
5999         if ((action_flags & (MLX5_FLOW_XCAP_ACTIONS |
6000                              MLX5_FLOW_VLAN_ACTIONS)) &&
6001             (queue_index == 0xFFFF ||
6002              mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
6003                 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
6004                     MLX5_FLOW_XCAP_ACTIONS)
6005                         return rte_flow_error_set(error, ENOTSUP,
6006                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6007                                                   NULL, "encap and decap "
6008                                                   "combination aren't supported");
6009                 if (!attr->transfer && attr->ingress) {
6010                         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
6011                                 return rte_flow_error_set
6012                                                 (error, ENOTSUP,
6013                                                  RTE_FLOW_ERROR_TYPE_ACTION,
6014                                                  NULL, "encap is not supported"
6015                                                  " for ingress traffic");
6016                         else if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
6017                                 return rte_flow_error_set
6018                                                 (error, ENOTSUP,
6019                                                  RTE_FLOW_ERROR_TYPE_ACTION,
6020                                                  NULL, "push VLAN action not "
6021                                                  "supported for ingress");
6022                         else if ((action_flags & MLX5_FLOW_VLAN_ACTIONS) ==
6023                                         MLX5_FLOW_VLAN_ACTIONS)
6024                                 return rte_flow_error_set
6025                                                 (error, ENOTSUP,
6026                                                  RTE_FLOW_ERROR_TYPE_ACTION,
6027                                                  NULL, "no support for "
6028                                                  "multiple VLAN actions");
6029                 }
6030         }
6031         /* Hairpin flow will add one more TAG action. */
6032         if (hairpin > 0)
6033                 rw_act_num += MLX5_ACT_NUM_SET_TAG;
6034         /* extra metadata enabled: one more TAG action will be add. */
6035         if (dev_conf->dv_flow_en &&
6036             dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
6037             mlx5_flow_ext_mreg_supported(dev))
6038                 rw_act_num += MLX5_ACT_NUM_SET_TAG;
6039         if ((uint32_t)rw_act_num >
6040                         flow_dv_modify_hdr_action_max(dev, is_root)) {
6041                 return rte_flow_error_set(error, ENOTSUP,
6042                                           RTE_FLOW_ERROR_TYPE_ACTION,
6043                                           NULL, "too many header modify"
6044                                           " actions to support");
6045         }
6046         return 0;
6047 }
6048
6049 /**
6050  * Internal preparation function. Allocates the DV flow size,
6051  * this size is constant.
6052  *
6053  * @param[in] dev
6054  *   Pointer to the rte_eth_dev structure.
6055  * @param[in] attr
6056  *   Pointer to the flow attributes.
6057  * @param[in] items
6058  *   Pointer to the list of items.
6059  * @param[in] actions
6060  *   Pointer to the list of actions.
6061  * @param[out] error
6062  *   Pointer to the error structure.
6063  *
6064  * @return
6065  *   Pointer to mlx5_flow object on success,
6066  *   otherwise NULL and rte_errno is set.
6067  */
6068 static struct mlx5_flow *
6069 flow_dv_prepare(struct rte_eth_dev *dev,
6070                 const struct rte_flow_attr *attr __rte_unused,
6071                 const struct rte_flow_item items[] __rte_unused,
6072                 const struct rte_flow_action actions[] __rte_unused,
6073                 struct rte_flow_error *error)
6074 {
6075         uint32_t handle_idx = 0;
6076         struct mlx5_flow *dev_flow;
6077         struct mlx5_flow_handle *dev_handle;
6078         struct mlx5_priv *priv = dev->data->dev_private;
6079
6080         /* In case of corrupting the memory. */
6081         if (priv->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
6082                 rte_flow_error_set(error, ENOSPC,
6083                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6084                                    "not free temporary device flow");
6085                 return NULL;
6086         }
6087         dev_handle = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
6088                                    &handle_idx);
6089         if (!dev_handle) {
6090                 rte_flow_error_set(error, ENOMEM,
6091                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6092                                    "not enough memory to create flow handle");
6093                 return NULL;
6094         }
6095         /* No multi-thread supporting. */
6096         dev_flow = &((struct mlx5_flow *)priv->inter_flows)[priv->flow_idx++];
6097         dev_flow->handle = dev_handle;
6098         dev_flow->handle_idx = handle_idx;
6099         /*
6100          * In some old rdma-core releases, before continuing, a check of the
6101          * length of matching parameter will be done at first. It needs to use
6102          * the length without misc4 param. If the flow has misc4 support, then
6103          * the length needs to be adjusted accordingly. Each param member is
6104          * aligned with a 64B boundary naturally.
6105          */
6106         dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param) -
6107                                   MLX5_ST_SZ_BYTES(fte_match_set_misc4);
6108         /*
6109          * The matching value needs to be cleared to 0 before using. In the
6110          * past, it will be automatically cleared when using rte_*alloc
6111          * API. The time consumption will be almost the same as before.
6112          */
6113         memset(dev_flow->dv.value.buf, 0, MLX5_ST_SZ_BYTES(fte_match_param));
6114         dev_flow->ingress = attr->ingress;
6115         dev_flow->dv.transfer = attr->transfer;
6116         return dev_flow;
6117 }
6118
6119 #ifdef RTE_LIBRTE_MLX5_DEBUG
6120 /**
6121  * Sanity check for match mask and value. Similar to check_valid_spec() in
6122  * kernel driver. If unmasked bit is present in value, it returns failure.
6123  *
6124  * @param match_mask
6125  *   pointer to match mask buffer.
6126  * @param match_value
6127  *   pointer to match value buffer.
6128  *
6129  * @return
6130  *   0 if valid, -EINVAL otherwise.
6131  */
6132 static int
6133 flow_dv_check_valid_spec(void *match_mask, void *match_value)
6134 {
6135         uint8_t *m = match_mask;
6136         uint8_t *v = match_value;
6137         unsigned int i;
6138
6139         for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
6140                 if (v[i] & ~m[i]) {
6141                         DRV_LOG(ERR,
6142                                 "match_value differs from match_criteria"
6143                                 " %p[%u] != %p[%u]",
6144                                 match_value, i, match_mask, i);
6145                         return -EINVAL;
6146                 }
6147         }
6148         return 0;
6149 }
6150 #endif
6151
6152 /**
6153  * Add match of ip_version.
6154  *
6155  * @param[in] group
6156  *   Flow group.
6157  * @param[in] headers_v
6158  *   Values header pointer.
6159  * @param[in] headers_m
6160  *   Masks header pointer.
6161  * @param[in] ip_version
6162  *   The IP version to set.
6163  */
6164 static inline void
6165 flow_dv_set_match_ip_version(uint32_t group,
6166                              void *headers_v,
6167                              void *headers_m,
6168                              uint8_t ip_version)
6169 {
6170         if (group == 0)
6171                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
6172         else
6173                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version,
6174                          ip_version);
6175         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, ip_version);
6176         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, 0);
6177         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype, 0);
6178 }
6179
6180 /**
6181  * Add Ethernet item to matcher and to the value.
6182  *
6183  * @param[in, out] matcher
6184  *   Flow matcher.
6185  * @param[in, out] key
6186  *   Flow matcher value.
6187  * @param[in] item
6188  *   Flow pattern to translate.
6189  * @param[in] inner
6190  *   Item is inner pattern.
6191  */
6192 static void
6193 flow_dv_translate_item_eth(void *matcher, void *key,
6194                            const struct rte_flow_item *item, int inner,
6195                            uint32_t group)
6196 {
6197         const struct rte_flow_item_eth *eth_m = item->mask;
6198         const struct rte_flow_item_eth *eth_v = item->spec;
6199         const struct rte_flow_item_eth nic_mask = {
6200                 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
6201                 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
6202                 .type = RTE_BE16(0xffff),
6203         };
6204         void *headers_m;
6205         void *headers_v;
6206         char *l24_v;
6207         unsigned int i;
6208
6209         if (!eth_v)
6210                 return;
6211         if (!eth_m)
6212                 eth_m = &nic_mask;
6213         if (inner) {
6214                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6215                                          inner_headers);
6216                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6217         } else {
6218                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6219                                          outer_headers);
6220                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6221         }
6222         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, dmac_47_16),
6223                &eth_m->dst, sizeof(eth_m->dst));
6224         /* The value must be in the range of the mask. */
6225         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, dmac_47_16);
6226         for (i = 0; i < sizeof(eth_m->dst); ++i)
6227                 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
6228         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, smac_47_16),
6229                &eth_m->src, sizeof(eth_m->src));
6230         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, smac_47_16);
6231         /* The value must be in the range of the mask. */
6232         for (i = 0; i < sizeof(eth_m->dst); ++i)
6233                 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
6234         if (eth_v->type) {
6235                 /* When ethertype is present set mask for tagged VLAN. */
6236                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
6237                 /* Set value for tagged VLAN if ethertype is 802.1Q. */
6238                 if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_VLAN) ||
6239                     eth_v->type == RTE_BE16(RTE_ETHER_TYPE_QINQ)) {
6240                         MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag,
6241                                  1);
6242                         /* Return here to avoid setting match on ethertype. */
6243                         return;
6244                 }
6245         }
6246         /*
6247          * HW supports match on one Ethertype, the Ethertype following the last
6248          * VLAN tag of the packet (see PRM).
6249          * Set match on ethertype only if ETH header is not followed by VLAN.
6250          * HW is optimized for IPv4/IPv6. In such cases, avoid setting
6251          * ethertype, and use ip_version field instead.
6252          * eCPRI over Ether layer will use type value 0xAEFE.
6253          */
6254         if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_IPV4) &&
6255             eth_m->type == 0xFFFF) {
6256                 flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
6257         } else if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_IPV6) &&
6258                    eth_m->type == 0xFFFF) {
6259                 flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
6260         } else {
6261                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
6262                          rte_be_to_cpu_16(eth_m->type));
6263                 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6264                                      ethertype);
6265                 *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
6266         }
6267 }
6268
6269 /**
6270  * Add VLAN item to matcher and to the value.
6271  *
6272  * @param[in, out] dev_flow
6273  *   Flow descriptor.
6274  * @param[in, out] matcher
6275  *   Flow matcher.
6276  * @param[in, out] key
6277  *   Flow matcher value.
6278  * @param[in] item
6279  *   Flow pattern to translate.
6280  * @param[in] inner
6281  *   Item is inner pattern.
6282  */
6283 static void
6284 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
6285                             void *matcher, void *key,
6286                             const struct rte_flow_item *item,
6287                             int inner, uint32_t group)
6288 {
6289         const struct rte_flow_item_vlan *vlan_m = item->mask;
6290         const struct rte_flow_item_vlan *vlan_v = item->spec;
6291         void *headers_m;
6292         void *headers_v;
6293         uint16_t tci_m;
6294         uint16_t tci_v;
6295
6296         if (inner) {
6297                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6298                                          inner_headers);
6299                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6300         } else {
6301                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6302                                          outer_headers);
6303                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6304                 /*
6305                  * This is workaround, masks are not supported,
6306                  * and pre-validated.
6307                  */
6308                 if (vlan_v)
6309                         dev_flow->handle->vf_vlan.tag =
6310                                         rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
6311         }
6312         /*
6313          * When VLAN item exists in flow, mark packet as tagged,
6314          * even if TCI is not specified.
6315          */
6316         MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
6317         MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
6318         if (!vlan_v)
6319                 return;
6320         if (!vlan_m)
6321                 vlan_m = &rte_flow_item_vlan_mask;
6322         tci_m = rte_be_to_cpu_16(vlan_m->tci);
6323         tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
6324         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_vid, tci_m);
6325         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, tci_v);
6326         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_cfi, tci_m >> 12);
6327         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_cfi, tci_v >> 12);
6328         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_prio, tci_m >> 13);
6329         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, tci_v >> 13);
6330         /*
6331          * HW is optimized for IPv4/IPv6. In such cases, avoid setting
6332          * ethertype, and use ip_version field instead.
6333          */
6334         if (vlan_v->inner_type == RTE_BE16(RTE_ETHER_TYPE_IPV4) &&
6335             vlan_m->inner_type == 0xFFFF) {
6336                 flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
6337         } else if (vlan_v->inner_type == RTE_BE16(RTE_ETHER_TYPE_IPV6) &&
6338                    vlan_m->inner_type == 0xFFFF) {
6339                 flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
6340         } else {
6341                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
6342                          rte_be_to_cpu_16(vlan_m->inner_type));
6343                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
6344                          rte_be_to_cpu_16(vlan_m->inner_type &
6345                                           vlan_v->inner_type));
6346         }
6347 }
6348
6349 /**
6350  * Add IPV4 item to matcher and to the value.
6351  *
6352  * @param[in, out] matcher
6353  *   Flow matcher.
6354  * @param[in, out] key
6355  *   Flow matcher value.
6356  * @param[in] item
6357  *   Flow pattern to translate.
6358  * @param[in] item_flags
6359  *   Bit-fields that holds the items detected until now.
6360  * @param[in] inner
6361  *   Item is inner pattern.
6362  * @param[in] group
6363  *   The group to insert the rule.
6364  */
6365 static void
6366 flow_dv_translate_item_ipv4(void *matcher, void *key,
6367                             const struct rte_flow_item *item,
6368                             const uint64_t item_flags,
6369                             int inner, uint32_t group)
6370 {
6371         const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
6372         const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
6373         const struct rte_flow_item_ipv4 nic_mask = {
6374                 .hdr = {
6375                         .src_addr = RTE_BE32(0xffffffff),
6376                         .dst_addr = RTE_BE32(0xffffffff),
6377                         .type_of_service = 0xff,
6378                         .next_proto_id = 0xff,
6379                         .time_to_live = 0xff,
6380                 },
6381         };
6382         void *headers_m;
6383         void *headers_v;
6384         char *l24_m;
6385         char *l24_v;
6386         uint8_t tos;
6387
6388         if (inner) {
6389                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6390                                          inner_headers);
6391                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6392         } else {
6393                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6394                                          outer_headers);
6395                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6396         }
6397         flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
6398         /*
6399          * On outer header (which must contains L2), or inner header with L2,
6400          * set cvlan_tag mask bit to mark this packet as untagged.
6401          * This should be done even if item->spec is empty.
6402          */
6403         if (!inner || item_flags & MLX5_FLOW_LAYER_INNER_L2)
6404                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
6405         if (!ipv4_v)
6406                 return;
6407         if (!ipv4_m)
6408                 ipv4_m = &nic_mask;
6409         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6410                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
6411         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6412                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
6413         *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
6414         *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
6415         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6416                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
6417         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6418                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
6419         *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
6420         *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
6421         tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
6422         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
6423                  ipv4_m->hdr.type_of_service);
6424         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
6425         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
6426                  ipv4_m->hdr.type_of_service >> 2);
6427         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
6428         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6429                  ipv4_m->hdr.next_proto_id);
6430         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6431                  ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
6432         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
6433                  ipv4_m->hdr.time_to_live);
6434         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
6435                  ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
6436 }
6437
6438 /**
6439  * Add IPV6 item to matcher and to the value.
6440  *
6441  * @param[in, out] matcher
6442  *   Flow matcher.
6443  * @param[in, out] key
6444  *   Flow matcher value.
6445  * @param[in] item
6446  *   Flow pattern to translate.
6447  * @param[in] item_flags
6448  *   Bit-fields that holds the items detected until now.
6449  * @param[in] inner
6450  *   Item is inner pattern.
6451  * @param[in] group
6452  *   The group to insert the rule.
6453  */
6454 static void
6455 flow_dv_translate_item_ipv6(void *matcher, void *key,
6456                             const struct rte_flow_item *item,
6457                             const uint64_t item_flags,
6458                             int inner, uint32_t group)
6459 {
6460         const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
6461         const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
6462         const struct rte_flow_item_ipv6 nic_mask = {
6463                 .hdr = {
6464                         .src_addr =
6465                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
6466                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
6467                         .dst_addr =
6468                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
6469                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
6470                         .vtc_flow = RTE_BE32(0xffffffff),
6471                         .proto = 0xff,
6472                         .hop_limits = 0xff,
6473                 },
6474         };
6475         void *headers_m;
6476         void *headers_v;
6477         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6478         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6479         char *l24_m;
6480         char *l24_v;
6481         uint32_t vtc_m;
6482         uint32_t vtc_v;
6483         int i;
6484         int size;
6485
6486         if (inner) {
6487                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6488                                          inner_headers);
6489                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6490         } else {
6491                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6492                                          outer_headers);
6493                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6494         }
6495         flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
6496         /*
6497          * On outer header (which must contains L2), or inner header with L2,
6498          * set cvlan_tag mask bit to mark this packet as untagged.
6499          * This should be done even if item->spec is empty.
6500          */
6501         if (!inner || item_flags & MLX5_FLOW_LAYER_INNER_L2)
6502                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
6503         if (!ipv6_v)
6504                 return;
6505         if (!ipv6_m)
6506                 ipv6_m = &nic_mask;
6507         size = sizeof(ipv6_m->hdr.dst_addr);
6508         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6509                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
6510         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6511                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
6512         memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
6513         for (i = 0; i < size; ++i)
6514                 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
6515         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6516                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
6517         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6518                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
6519         memcpy(l24_m, ipv6_m->hdr.src_addr, size);
6520         for (i = 0; i < size; ++i)
6521                 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
6522         /* TOS. */
6523         vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
6524         vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
6525         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
6526         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
6527         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
6528         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
6529         /* Label. */
6530         if (inner) {
6531                 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
6532                          vtc_m);
6533                 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
6534                          vtc_v);
6535         } else {
6536                 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
6537                          vtc_m);
6538                 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
6539                          vtc_v);
6540         }
6541         /* Protocol. */
6542         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6543                  ipv6_m->hdr.proto);
6544         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6545                  ipv6_v->hdr.proto & ipv6_m->hdr.proto);
6546         /* Hop limit. */
6547         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
6548                  ipv6_m->hdr.hop_limits);
6549         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
6550                  ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
6551 }
6552
6553 /**
6554  * Add TCP item to matcher and to the value.
6555  *
6556  * @param[in, out] matcher
6557  *   Flow matcher.
6558  * @param[in, out] key
6559  *   Flow matcher value.
6560  * @param[in] item
6561  *   Flow pattern to translate.
6562  * @param[in] inner
6563  *   Item is inner pattern.
6564  */
6565 static void
6566 flow_dv_translate_item_tcp(void *matcher, void *key,
6567                            const struct rte_flow_item *item,
6568                            int inner)
6569 {
6570         const struct rte_flow_item_tcp *tcp_m = item->mask;
6571         const struct rte_flow_item_tcp *tcp_v = item->spec;
6572         void *headers_m;
6573         void *headers_v;
6574
6575         if (inner) {
6576                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6577                                          inner_headers);
6578                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6579         } else {
6580                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6581                                          outer_headers);
6582                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6583         }
6584         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6585         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
6586         if (!tcp_v)
6587                 return;
6588         if (!tcp_m)
6589                 tcp_m = &rte_flow_item_tcp_mask;
6590         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
6591                  rte_be_to_cpu_16(tcp_m->hdr.src_port));
6592         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
6593                  rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
6594         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
6595                  rte_be_to_cpu_16(tcp_m->hdr.dst_port));
6596         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
6597                  rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
6598         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
6599                  tcp_m->hdr.tcp_flags);
6600         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
6601                  (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
6602 }
6603
6604 /**
6605  * Add UDP item to matcher and to the value.
6606  *
6607  * @param[in, out] matcher
6608  *   Flow matcher.
6609  * @param[in, out] key
6610  *   Flow matcher value.
6611  * @param[in] item
6612  *   Flow pattern to translate.
6613  * @param[in] inner
6614  *   Item is inner pattern.
6615  */
6616 static void
6617 flow_dv_translate_item_udp(void *matcher, void *key,
6618                            const struct rte_flow_item *item,
6619                            int inner)
6620 {
6621         const struct rte_flow_item_udp *udp_m = item->mask;
6622         const struct rte_flow_item_udp *udp_v = item->spec;
6623         void *headers_m;
6624         void *headers_v;
6625
6626         if (inner) {
6627                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6628                                          inner_headers);
6629                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6630         } else {
6631                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6632                                          outer_headers);
6633                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6634         }
6635         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6636         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
6637         if (!udp_v)
6638                 return;
6639         if (!udp_m)
6640                 udp_m = &rte_flow_item_udp_mask;
6641         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
6642                  rte_be_to_cpu_16(udp_m->hdr.src_port));
6643         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
6644                  rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
6645         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
6646                  rte_be_to_cpu_16(udp_m->hdr.dst_port));
6647         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
6648                  rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
6649 }
6650
6651 /**
6652  * Add GRE optional Key item to matcher and to the value.
6653  *
6654  * @param[in, out] matcher
6655  *   Flow matcher.
6656  * @param[in, out] key
6657  *   Flow matcher value.
6658  * @param[in] item
6659  *   Flow pattern to translate.
6660  * @param[in] inner
6661  *   Item is inner pattern.
6662  */
6663 static void
6664 flow_dv_translate_item_gre_key(void *matcher, void *key,
6665                                    const struct rte_flow_item *item)
6666 {
6667         const rte_be32_t *key_m = item->mask;
6668         const rte_be32_t *key_v = item->spec;
6669         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6670         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6671         rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
6672
6673         /* GRE K bit must be on and should already be validated */
6674         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
6675         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
6676         if (!key_v)
6677                 return;
6678         if (!key_m)
6679                 key_m = &gre_key_default_mask;
6680         MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
6681                  rte_be_to_cpu_32(*key_m) >> 8);
6682         MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
6683                  rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
6684         MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
6685                  rte_be_to_cpu_32(*key_m) & 0xFF);
6686         MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
6687                  rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
6688 }
6689
6690 /**
6691  * Add GRE item to matcher and to the value.
6692  *
6693  * @param[in, out] matcher
6694  *   Flow matcher.
6695  * @param[in, out] key
6696  *   Flow matcher value.
6697  * @param[in] item
6698  *   Flow pattern to translate.
6699  * @param[in] inner
6700  *   Item is inner pattern.
6701  */
6702 static void
6703 flow_dv_translate_item_gre(void *matcher, void *key,
6704                            const struct rte_flow_item *item,
6705                            int inner)
6706 {
6707         const struct rte_flow_item_gre *gre_m = item->mask;
6708         const struct rte_flow_item_gre *gre_v = item->spec;
6709         void *headers_m;
6710         void *headers_v;
6711         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6712         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6713         struct {
6714                 union {
6715                         __extension__
6716                         struct {
6717                                 uint16_t version:3;
6718                                 uint16_t rsvd0:9;
6719                                 uint16_t s_present:1;
6720                                 uint16_t k_present:1;
6721                                 uint16_t rsvd_bit1:1;
6722                                 uint16_t c_present:1;
6723                         };
6724                         uint16_t value;
6725                 };
6726         } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
6727
6728         if (inner) {
6729                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6730                                          inner_headers);
6731                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6732         } else {
6733                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6734                                          outer_headers);
6735                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6736         }
6737         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6738         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
6739         if (!gre_v)
6740                 return;
6741         if (!gre_m)
6742                 gre_m = &rte_flow_item_gre_mask;
6743         MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
6744                  rte_be_to_cpu_16(gre_m->protocol));
6745         MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
6746                  rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
6747         gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
6748         gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
6749         MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
6750                  gre_crks_rsvd0_ver_m.c_present);
6751         MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
6752                  gre_crks_rsvd0_ver_v.c_present &
6753                  gre_crks_rsvd0_ver_m.c_present);
6754         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
6755                  gre_crks_rsvd0_ver_m.k_present);
6756         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
6757                  gre_crks_rsvd0_ver_v.k_present &
6758                  gre_crks_rsvd0_ver_m.k_present);
6759         MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
6760                  gre_crks_rsvd0_ver_m.s_present);
6761         MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
6762                  gre_crks_rsvd0_ver_v.s_present &
6763                  gre_crks_rsvd0_ver_m.s_present);
6764 }
6765
6766 /**
6767  * Add NVGRE item to matcher and to the value.
6768  *
6769  * @param[in, out] matcher
6770  *   Flow matcher.
6771  * @param[in, out] key
6772  *   Flow matcher value.
6773  * @param[in] item
6774  *   Flow pattern to translate.
6775  * @param[in] inner
6776  *   Item is inner pattern.
6777  */
6778 static void
6779 flow_dv_translate_item_nvgre(void *matcher, void *key,
6780                              const struct rte_flow_item *item,
6781                              int inner)
6782 {
6783         const struct rte_flow_item_nvgre *nvgre_m = item->mask;
6784         const struct rte_flow_item_nvgre *nvgre_v = item->spec;
6785         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6786         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6787         const char *tni_flow_id_m;
6788         const char *tni_flow_id_v;
6789         char *gre_key_m;
6790         char *gre_key_v;
6791         int size;
6792         int i;
6793
6794         /* For NVGRE, GRE header fields must be set with defined values. */
6795         const struct rte_flow_item_gre gre_spec = {
6796                 .c_rsvd0_ver = RTE_BE16(0x2000),
6797                 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
6798         };
6799         const struct rte_flow_item_gre gre_mask = {
6800                 .c_rsvd0_ver = RTE_BE16(0xB000),
6801                 .protocol = RTE_BE16(UINT16_MAX),
6802         };
6803         const struct rte_flow_item gre_item = {
6804                 .spec = &gre_spec,
6805                 .mask = &gre_mask,
6806                 .last = NULL,
6807         };
6808         flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
6809         if (!nvgre_v)
6810                 return;
6811         if (!nvgre_m)
6812                 nvgre_m = &rte_flow_item_nvgre_mask;
6813         tni_flow_id_m = (const char *)nvgre_m->tni;
6814         tni_flow_id_v = (const char *)nvgre_v->tni;
6815         size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
6816         gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
6817         gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
6818         memcpy(gre_key_m, tni_flow_id_m, size);
6819         for (i = 0; i < size; ++i)
6820                 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
6821 }
6822
6823 /**
6824  * Add VXLAN item to matcher and to the value.
6825  *
6826  * @param[in, out] matcher
6827  *   Flow matcher.
6828  * @param[in, out] key
6829  *   Flow matcher value.
6830  * @param[in] item
6831  *   Flow pattern to translate.
6832  * @param[in] inner
6833  *   Item is inner pattern.
6834  */
6835 static void
6836 flow_dv_translate_item_vxlan(void *matcher, void *key,
6837                              const struct rte_flow_item *item,
6838                              int inner)
6839 {
6840         const struct rte_flow_item_vxlan *vxlan_m = item->mask;
6841         const struct rte_flow_item_vxlan *vxlan_v = item->spec;
6842         void *headers_m;
6843         void *headers_v;
6844         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6845         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6846         char *vni_m;
6847         char *vni_v;
6848         uint16_t dport;
6849         int size;
6850         int i;
6851
6852         if (inner) {
6853                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6854                                          inner_headers);
6855                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6856         } else {
6857                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6858                                          outer_headers);
6859                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6860         }
6861         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
6862                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
6863         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6864                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6865                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6866         }
6867         if (!vxlan_v)
6868                 return;
6869         if (!vxlan_m)
6870                 vxlan_m = &rte_flow_item_vxlan_mask;
6871         size = sizeof(vxlan_m->vni);
6872         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
6873         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
6874         memcpy(vni_m, vxlan_m->vni, size);
6875         for (i = 0; i < size; ++i)
6876                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
6877 }
6878
6879 /**
6880  * Add VXLAN-GPE item to matcher and to the value.
6881  *
6882  * @param[in, out] matcher
6883  *   Flow matcher.
6884  * @param[in, out] key
6885  *   Flow matcher value.
6886  * @param[in] item
6887  *   Flow pattern to translate.
6888  * @param[in] inner
6889  *   Item is inner pattern.
6890  */
6891
6892 static void
6893 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
6894                                  const struct rte_flow_item *item, int inner)
6895 {
6896         const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
6897         const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
6898         void *headers_m;
6899         void *headers_v;
6900         void *misc_m =
6901                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
6902         void *misc_v =
6903                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6904         char *vni_m;
6905         char *vni_v;
6906         uint16_t dport;
6907         int size;
6908         int i;
6909         uint8_t flags_m = 0xff;
6910         uint8_t flags_v = 0xc;
6911
6912         if (inner) {
6913                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6914                                          inner_headers);
6915                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6916         } else {
6917                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6918                                          outer_headers);
6919                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6920         }
6921         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
6922                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
6923         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6924                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6925                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6926         }
6927         if (!vxlan_v)
6928                 return;
6929         if (!vxlan_m)
6930                 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
6931         size = sizeof(vxlan_m->vni);
6932         vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
6933         vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
6934         memcpy(vni_m, vxlan_m->vni, size);
6935         for (i = 0; i < size; ++i)
6936                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
6937         if (vxlan_m->flags) {
6938                 flags_m = vxlan_m->flags;
6939                 flags_v = vxlan_v->flags;
6940         }
6941         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
6942         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
6943         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
6944                  vxlan_m->protocol);
6945         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
6946                  vxlan_v->protocol);
6947 }
6948
6949 /**
6950  * Add Geneve item to matcher and to the value.
6951  *
6952  * @param[in, out] matcher
6953  *   Flow matcher.
6954  * @param[in, out] key
6955  *   Flow matcher value.
6956  * @param[in] item
6957  *   Flow pattern to translate.
6958  * @param[in] inner
6959  *   Item is inner pattern.
6960  */
6961
6962 static void
6963 flow_dv_translate_item_geneve(void *matcher, void *key,
6964                               const struct rte_flow_item *item, int inner)
6965 {
6966         const struct rte_flow_item_geneve *geneve_m = item->mask;
6967         const struct rte_flow_item_geneve *geneve_v = item->spec;
6968         void *headers_m;
6969         void *headers_v;
6970         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6971         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6972         uint16_t dport;
6973         uint16_t gbhdr_m;
6974         uint16_t gbhdr_v;
6975         char *vni_m;
6976         char *vni_v;
6977         size_t size, i;
6978
6979         if (inner) {
6980                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6981                                          inner_headers);
6982                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6983         } else {
6984                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6985                                          outer_headers);
6986                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6987         }
6988         dport = MLX5_UDP_PORT_GENEVE;
6989         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6990                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6991                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6992         }
6993         if (!geneve_v)
6994                 return;
6995         if (!geneve_m)
6996                 geneve_m = &rte_flow_item_geneve_mask;
6997         size = sizeof(geneve_m->vni);
6998         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
6999         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
7000         memcpy(vni_m, geneve_m->vni, size);
7001         for (i = 0; i < size; ++i)
7002                 vni_v[i] = vni_m[i] & geneve_v->vni[i];
7003         MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
7004                  rte_be_to_cpu_16(geneve_m->protocol));
7005         MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
7006                  rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
7007         gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
7008         gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
7009         MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
7010                  MLX5_GENEVE_OAMF_VAL(gbhdr_m));
7011         MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
7012                  MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
7013         MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
7014                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
7015         MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
7016                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
7017                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
7018 }
7019
7020 /**
7021  * Add MPLS item to matcher and to the value.
7022  *
7023  * @param[in, out] matcher
7024  *   Flow matcher.
7025  * @param[in, out] key
7026  *   Flow matcher value.
7027  * @param[in] item
7028  *   Flow pattern to translate.
7029  * @param[in] prev_layer
7030  *   The protocol layer indicated in previous item.
7031  * @param[in] inner
7032  *   Item is inner pattern.
7033  */
7034 static void
7035 flow_dv_translate_item_mpls(void *matcher, void *key,
7036                             const struct rte_flow_item *item,
7037                             uint64_t prev_layer,
7038                             int inner)
7039 {
7040         const uint32_t *in_mpls_m = item->mask;
7041         const uint32_t *in_mpls_v = item->spec;
7042         uint32_t *out_mpls_m = 0;
7043         uint32_t *out_mpls_v = 0;
7044         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7045         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7046         void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
7047                                      misc_parameters_2);
7048         void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
7049         void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
7050         void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7051
7052         switch (prev_layer) {
7053         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
7054                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
7055                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
7056                          MLX5_UDP_PORT_MPLS);
7057                 break;
7058         case MLX5_FLOW_LAYER_GRE:
7059                 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
7060                 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
7061                          RTE_ETHER_TYPE_MPLS);
7062                 break;
7063         default:
7064                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7065                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
7066                          IPPROTO_MPLS);
7067                 break;
7068         }
7069         if (!in_mpls_v)
7070                 return;
7071         if (!in_mpls_m)
7072                 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
7073         switch (prev_layer) {
7074         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
7075                 out_mpls_m =
7076                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
7077                                                  outer_first_mpls_over_udp);
7078                 out_mpls_v =
7079                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
7080                                                  outer_first_mpls_over_udp);
7081                 break;
7082         case MLX5_FLOW_LAYER_GRE:
7083                 out_mpls_m =
7084                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
7085                                                  outer_first_mpls_over_gre);
7086                 out_mpls_v =
7087                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
7088                                                  outer_first_mpls_over_gre);
7089                 break;
7090         default:
7091                 /* Inner MPLS not over GRE is not supported. */
7092                 if (!inner) {
7093                         out_mpls_m =
7094                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
7095                                                          misc2_m,
7096                                                          outer_first_mpls);
7097                         out_mpls_v =
7098                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
7099                                                          misc2_v,
7100                                                          outer_first_mpls);
7101                 }
7102                 break;
7103         }
7104         if (out_mpls_m && out_mpls_v) {
7105                 *out_mpls_m = *in_mpls_m;
7106                 *out_mpls_v = *in_mpls_v & *in_mpls_m;
7107         }
7108 }
7109
7110 /**
7111  * Add metadata register item to matcher
7112  *
7113  * @param[in, out] matcher
7114  *   Flow matcher.
7115  * @param[in, out] key
7116  *   Flow matcher value.
7117  * @param[in] reg_type
7118  *   Type of device metadata register
7119  * @param[in] value
7120  *   Register value
7121  * @param[in] mask
7122  *   Register mask
7123  */
7124 static void
7125 flow_dv_match_meta_reg(void *matcher, void *key,
7126                        enum modify_reg reg_type,
7127                        uint32_t data, uint32_t mask)
7128 {
7129         void *misc2_m =
7130                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
7131         void *misc2_v =
7132                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
7133         uint32_t temp;
7134
7135         data &= mask;
7136         switch (reg_type) {
7137         case REG_A:
7138                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
7139                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
7140                 break;
7141         case REG_B:
7142                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
7143                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
7144                 break;
7145         case REG_C_0:
7146                 /*
7147                  * The metadata register C0 field might be divided into
7148                  * source vport index and META item value, we should set
7149                  * this field according to specified mask, not as whole one.
7150                  */
7151                 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
7152                 temp |= mask;
7153                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
7154                 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
7155                 temp &= ~mask;
7156                 temp |= data;
7157                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
7158                 break;
7159         case REG_C_1:
7160                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
7161                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
7162                 break;
7163         case REG_C_2:
7164                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
7165                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
7166                 break;
7167         case REG_C_3:
7168                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
7169                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
7170                 break;
7171         case REG_C_4:
7172                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
7173                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
7174                 break;
7175         case REG_C_5:
7176                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
7177                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
7178                 break;
7179         case REG_C_6:
7180                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
7181                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
7182                 break;
7183         case REG_C_7:
7184                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
7185                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
7186                 break;
7187         default:
7188                 MLX5_ASSERT(false);
7189                 break;
7190         }
7191 }
7192
7193 /**
7194  * Add MARK item to matcher
7195  *
7196  * @param[in] dev
7197  *   The device to configure through.
7198  * @param[in, out] matcher
7199  *   Flow matcher.
7200  * @param[in, out] key
7201  *   Flow matcher value.
7202  * @param[in] item
7203  *   Flow pattern to translate.
7204  */
7205 static void
7206 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
7207                             void *matcher, void *key,
7208                             const struct rte_flow_item *item)
7209 {
7210         struct mlx5_priv *priv = dev->data->dev_private;
7211         const struct rte_flow_item_mark *mark;
7212         uint32_t value;
7213         uint32_t mask;
7214
7215         mark = item->mask ? (const void *)item->mask :
7216                             &rte_flow_item_mark_mask;
7217         mask = mark->id & priv->sh->dv_mark_mask;
7218         mark = (const void *)item->spec;
7219         MLX5_ASSERT(mark);
7220         value = mark->id & priv->sh->dv_mark_mask & mask;
7221         if (mask) {
7222                 enum modify_reg reg;
7223
7224                 /* Get the metadata register index for the mark. */
7225                 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
7226                 MLX5_ASSERT(reg > 0);
7227                 if (reg == REG_C_0) {
7228                         struct mlx5_priv *priv = dev->data->dev_private;
7229                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
7230                         uint32_t shl_c0 = rte_bsf32(msk_c0);
7231
7232                         mask &= msk_c0;
7233                         mask <<= shl_c0;
7234                         value <<= shl_c0;
7235                 }
7236                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
7237         }
7238 }
7239
7240 /**
7241  * Add META item to matcher
7242  *
7243  * @param[in] dev
7244  *   The devich to configure through.
7245  * @param[in, out] matcher
7246  *   Flow matcher.
7247  * @param[in, out] key
7248  *   Flow matcher value.
7249  * @param[in] attr
7250  *   Attributes of flow that includes this item.
7251  * @param[in] item
7252  *   Flow pattern to translate.
7253  */
7254 static void
7255 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
7256                             void *matcher, void *key,
7257                             const struct rte_flow_attr *attr,
7258                             const struct rte_flow_item *item)
7259 {
7260         const struct rte_flow_item_meta *meta_m;
7261         const struct rte_flow_item_meta *meta_v;
7262
7263         meta_m = (const void *)item->mask;
7264         if (!meta_m)
7265                 meta_m = &rte_flow_item_meta_mask;
7266         meta_v = (const void *)item->spec;
7267         if (meta_v) {
7268                 int reg;
7269                 uint32_t value = meta_v->data;
7270                 uint32_t mask = meta_m->data;
7271
7272                 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
7273                 if (reg < 0)
7274                         return;
7275                 /*
7276                  * In datapath code there is no endianness
7277                  * coversions for perfromance reasons, all
7278                  * pattern conversions are done in rte_flow.
7279                  */
7280                 value = rte_cpu_to_be_32(value);
7281                 mask = rte_cpu_to_be_32(mask);
7282                 if (reg == REG_C_0) {
7283                         struct mlx5_priv *priv = dev->data->dev_private;
7284                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
7285                         uint32_t shl_c0 = rte_bsf32(msk_c0);
7286 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
7287                         uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
7288
7289                         value >>= shr_c0;
7290                         mask >>= shr_c0;
7291 #endif
7292                         value <<= shl_c0;
7293                         mask <<= shl_c0;
7294                         MLX5_ASSERT(msk_c0);
7295                         MLX5_ASSERT(!(~msk_c0 & mask));
7296                 }
7297                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
7298         }
7299 }
7300
7301 /**
7302  * Add vport metadata Reg C0 item to matcher
7303  *
7304  * @param[in, out] matcher
7305  *   Flow matcher.
7306  * @param[in, out] key
7307  *   Flow matcher value.
7308  * @param[in] reg
7309  *   Flow pattern to translate.
7310  */
7311 static void
7312 flow_dv_translate_item_meta_vport(void *matcher, void *key,
7313                                   uint32_t value, uint32_t mask)
7314 {
7315         flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
7316 }
7317
7318 /**
7319  * Add tag item to matcher
7320  *
7321  * @param[in] dev
7322  *   The devich to configure through.
7323  * @param[in, out] matcher
7324  *   Flow matcher.
7325  * @param[in, out] key
7326  *   Flow matcher value.
7327  * @param[in] item
7328  *   Flow pattern to translate.
7329  */
7330 static void
7331 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
7332                                 void *matcher, void *key,
7333                                 const struct rte_flow_item *item)
7334 {
7335         const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
7336         const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
7337         uint32_t mask, value;
7338
7339         MLX5_ASSERT(tag_v);
7340         value = tag_v->data;
7341         mask = tag_m ? tag_m->data : UINT32_MAX;
7342         if (tag_v->id == REG_C_0) {
7343                 struct mlx5_priv *priv = dev->data->dev_private;
7344                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
7345                 uint32_t shl_c0 = rte_bsf32(msk_c0);
7346
7347                 mask &= msk_c0;
7348                 mask <<= shl_c0;
7349                 value <<= shl_c0;
7350         }
7351         flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
7352 }
7353
7354 /**
7355  * Add TAG item to matcher
7356  *
7357  * @param[in] dev
7358  *   The devich to configure through.
7359  * @param[in, out] matcher
7360  *   Flow matcher.
7361  * @param[in, out] key
7362  *   Flow matcher value.
7363  * @param[in] item
7364  *   Flow pattern to translate.
7365  */
7366 static void
7367 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
7368                            void *matcher, void *key,
7369                            const struct rte_flow_item *item)
7370 {
7371         const struct rte_flow_item_tag *tag_v = item->spec;
7372         const struct rte_flow_item_tag *tag_m = item->mask;
7373         enum modify_reg reg;
7374
7375         MLX5_ASSERT(tag_v);
7376         tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
7377         /* Get the metadata register index for the tag. */
7378         reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
7379         MLX5_ASSERT(reg > 0);
7380         flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
7381 }
7382
7383 /**
7384  * Add source vport match to the specified matcher.
7385  *
7386  * @param[in, out] matcher
7387  *   Flow matcher.
7388  * @param[in, out] key
7389  *   Flow matcher value.
7390  * @param[in] port
7391  *   Source vport value to match
7392  * @param[in] mask
7393  *   Mask
7394  */
7395 static void
7396 flow_dv_translate_item_source_vport(void *matcher, void *key,
7397                                     int16_t port, uint16_t mask)
7398 {
7399         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7400         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7401
7402         MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
7403         MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
7404 }
7405
7406 /**
7407  * Translate port-id item to eswitch match on  port-id.
7408  *
7409  * @param[in] dev
7410  *   The devich to configure through.
7411  * @param[in, out] matcher
7412  *   Flow matcher.
7413  * @param[in, out] key
7414  *   Flow matcher value.
7415  * @param[in] item
7416  *   Flow pattern to translate.
7417  *
7418  * @return
7419  *   0 on success, a negative errno value otherwise.
7420  */
7421 static int
7422 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
7423                                void *key, const struct rte_flow_item *item)
7424 {
7425         const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
7426         const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
7427         struct mlx5_priv *priv;
7428         uint16_t mask, id;
7429
7430         mask = pid_m ? pid_m->id : 0xffff;
7431         id = pid_v ? pid_v->id : dev->data->port_id;
7432         priv = mlx5_port_to_eswitch_info(id, item == NULL);
7433         if (!priv)
7434                 return -rte_errno;
7435         /* Translate to vport field or to metadata, depending on mode. */
7436         if (priv->vport_meta_mask)
7437                 flow_dv_translate_item_meta_vport(matcher, key,
7438                                                   priv->vport_meta_tag,
7439                                                   priv->vport_meta_mask);
7440         else
7441                 flow_dv_translate_item_source_vport(matcher, key,
7442                                                     priv->vport_id, mask);
7443         return 0;
7444 }
7445
7446 /**
7447  * Add ICMP6 item to matcher and to the value.
7448  *
7449  * @param[in, out] matcher
7450  *   Flow matcher.
7451  * @param[in, out] key
7452  *   Flow matcher value.
7453  * @param[in] item
7454  *   Flow pattern to translate.
7455  * @param[in] inner
7456  *   Item is inner pattern.
7457  */
7458 static void
7459 flow_dv_translate_item_icmp6(void *matcher, void *key,
7460                               const struct rte_flow_item *item,
7461                               int inner)
7462 {
7463         const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
7464         const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
7465         void *headers_m;
7466         void *headers_v;
7467         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7468                                      misc_parameters_3);
7469         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7470         if (inner) {
7471                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7472                                          inner_headers);
7473                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7474         } else {
7475                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7476                                          outer_headers);
7477                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7478         }
7479         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
7480         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
7481         if (!icmp6_v)
7482                 return;
7483         if (!icmp6_m)
7484                 icmp6_m = &rte_flow_item_icmp6_mask;
7485         /*
7486          * Force flow only to match the non-fragmented IPv6 ICMPv6 packets.
7487          * If only the protocol is specified, no need to match the frag.
7488          */
7489         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
7490         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
7491         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
7492         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
7493                  icmp6_v->type & icmp6_m->type);
7494         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
7495         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
7496                  icmp6_v->code & icmp6_m->code);
7497 }
7498
7499 /**
7500  * Add ICMP item to matcher and to the value.
7501  *
7502  * @param[in, out] matcher
7503  *   Flow matcher.
7504  * @param[in, out] key
7505  *   Flow matcher value.
7506  * @param[in] item
7507  *   Flow pattern to translate.
7508  * @param[in] inner
7509  *   Item is inner pattern.
7510  */
7511 static void
7512 flow_dv_translate_item_icmp(void *matcher, void *key,
7513                             const struct rte_flow_item *item,
7514                             int inner)
7515 {
7516         const struct rte_flow_item_icmp *icmp_m = item->mask;
7517         const struct rte_flow_item_icmp *icmp_v = item->spec;
7518         uint32_t icmp_header_data_m = 0;
7519         uint32_t icmp_header_data_v = 0;
7520         void *headers_m;
7521         void *headers_v;
7522         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7523                                      misc_parameters_3);
7524         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7525         if (inner) {
7526                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7527                                          inner_headers);
7528                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7529         } else {
7530                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7531                                          outer_headers);
7532                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7533         }
7534         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
7535         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
7536         if (!icmp_v)
7537                 return;
7538         if (!icmp_m)
7539                 icmp_m = &rte_flow_item_icmp_mask;
7540         /*
7541          * Force flow only to match the non-fragmented IPv4 ICMP packets.
7542          * If only the protocol is specified, no need to match the frag.
7543          */
7544         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
7545         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
7546         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
7547                  icmp_m->hdr.icmp_type);
7548         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
7549                  icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
7550         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
7551                  icmp_m->hdr.icmp_code);
7552         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
7553                  icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
7554         icmp_header_data_m = rte_be_to_cpu_16(icmp_m->hdr.icmp_seq_nb);
7555         icmp_header_data_m |= rte_be_to_cpu_16(icmp_m->hdr.icmp_ident) << 16;
7556         if (icmp_header_data_m) {
7557                 icmp_header_data_v = rte_be_to_cpu_16(icmp_v->hdr.icmp_seq_nb);
7558                 icmp_header_data_v |=
7559                          rte_be_to_cpu_16(icmp_v->hdr.icmp_ident) << 16;
7560                 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_header_data,
7561                          icmp_header_data_m);
7562                 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_header_data,
7563                          icmp_header_data_v & icmp_header_data_m);
7564         }
7565 }
7566
7567 /**
7568  * Add GTP item to matcher and to the value.
7569  *
7570  * @param[in, out] matcher
7571  *   Flow matcher.
7572  * @param[in, out] key
7573  *   Flow matcher value.
7574  * @param[in] item
7575  *   Flow pattern to translate.
7576  * @param[in] inner
7577  *   Item is inner pattern.
7578  */
7579 static void
7580 flow_dv_translate_item_gtp(void *matcher, void *key,
7581                            const struct rte_flow_item *item, int inner)
7582 {
7583         const struct rte_flow_item_gtp *gtp_m = item->mask;
7584         const struct rte_flow_item_gtp *gtp_v = item->spec;
7585         void *headers_m;
7586         void *headers_v;
7587         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7588                                      misc_parameters_3);
7589         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7590         uint16_t dport = RTE_GTPU_UDP_PORT;
7591
7592         if (inner) {
7593                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7594                                          inner_headers);
7595                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7596         } else {
7597                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7598                                          outer_headers);
7599                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7600         }
7601         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7602                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7603                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7604         }
7605         if (!gtp_v)
7606                 return;
7607         if (!gtp_m)
7608                 gtp_m = &rte_flow_item_gtp_mask;
7609         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags,
7610                  gtp_m->v_pt_rsv_flags);
7611         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags,
7612                  gtp_v->v_pt_rsv_flags & gtp_m->v_pt_rsv_flags);
7613         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
7614         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
7615                  gtp_v->msg_type & gtp_m->msg_type);
7616         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
7617                  rte_be_to_cpu_32(gtp_m->teid));
7618         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
7619                  rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
7620 }
7621
7622 /**
7623  * Add eCPRI item to matcher and to the value.
7624  *
7625  * @param[in] dev
7626  *   The devich to configure through.
7627  * @param[in, out] matcher
7628  *   Flow matcher.
7629  * @param[in, out] key
7630  *   Flow matcher value.
7631  * @param[in] item
7632  *   Flow pattern to translate.
7633  * @param[in] samples
7634  *   Sample IDs to be used in the matching.
7635  */
7636 static void
7637 flow_dv_translate_item_ecpri(struct rte_eth_dev *dev, void *matcher,
7638                              void *key, const struct rte_flow_item *item)
7639 {
7640         struct mlx5_priv *priv = dev->data->dev_private;
7641         const struct rte_flow_item_ecpri *ecpri_m = item->mask;
7642         const struct rte_flow_item_ecpri *ecpri_v = item->spec;
7643         void *misc4_m = MLX5_ADDR_OF(fte_match_param, matcher,
7644                                      misc_parameters_4);
7645         void *misc4_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_4);
7646         uint32_t *samples;
7647         void *dw_m;
7648         void *dw_v;
7649
7650         if (!ecpri_v)
7651                 return;
7652         if (!ecpri_m)
7653                 ecpri_m = &rte_flow_item_ecpri_mask;
7654         /*
7655          * Maximal four DW samples are supported in a single matching now.
7656          * Two are used now for a eCPRI matching:
7657          * 1. Type: one byte, mask should be 0x00ff0000 in network order
7658          * 2. ID of a message: one or two bytes, mask 0xffff0000 or 0xff000000
7659          *    if any.
7660          */
7661         if (!ecpri_m->hdr.common.u32)
7662                 return;
7663         samples = priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0].ids;
7664         /* Need to take the whole DW as the mask to fill the entry. */
7665         dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
7666                             prog_sample_field_value_0);
7667         dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
7668                             prog_sample_field_value_0);
7669         /* Already big endian (network order) in the header. */
7670         *(uint32_t *)dw_m = ecpri_m->hdr.common.u32;
7671         *(uint32_t *)dw_v = ecpri_v->hdr.common.u32;
7672         /* Sample#0, used for matching type, offset 0. */
7673         MLX5_SET(fte_match_set_misc4, misc4_m,
7674                  prog_sample_field_id_0, samples[0]);
7675         /* It makes no sense to set the sample ID in the mask field. */
7676         MLX5_SET(fte_match_set_misc4, misc4_v,
7677                  prog_sample_field_id_0, samples[0]);
7678         /*
7679          * Checking if message body part needs to be matched.
7680          * Some wildcard rules only matching type field should be supported.
7681          */
7682         if (ecpri_m->hdr.dummy[0]) {
7683                 switch (ecpri_v->hdr.common.type) {
7684                 case RTE_ECPRI_MSG_TYPE_IQ_DATA:
7685                 case RTE_ECPRI_MSG_TYPE_RTC_CTRL:
7686                 case RTE_ECPRI_MSG_TYPE_DLY_MSR:
7687                         dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
7688                                             prog_sample_field_value_1);
7689                         dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
7690                                             prog_sample_field_value_1);
7691                         *(uint32_t *)dw_m = ecpri_m->hdr.dummy[0];
7692                         *(uint32_t *)dw_v = ecpri_v->hdr.dummy[0];
7693                         /* Sample#1, to match message body, offset 4. */
7694                         MLX5_SET(fte_match_set_misc4, misc4_m,
7695                                  prog_sample_field_id_1, samples[1]);
7696                         MLX5_SET(fte_match_set_misc4, misc4_v,
7697                                  prog_sample_field_id_1, samples[1]);
7698                         break;
7699                 default:
7700                         /* Others, do not match any sample ID. */
7701                         break;
7702                 }
7703         }
7704 }
7705
7706 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
7707
7708 #define HEADER_IS_ZERO(match_criteria, headers)                              \
7709         !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers),     \
7710                  matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
7711
7712 /**
7713  * Calculate flow matcher enable bitmap.
7714  *
7715  * @param match_criteria
7716  *   Pointer to flow matcher criteria.
7717  *
7718  * @return
7719  *   Bitmap of enabled fields.
7720  */
7721 static uint8_t
7722 flow_dv_matcher_enable(uint32_t *match_criteria)
7723 {
7724         uint8_t match_criteria_enable;
7725
7726         match_criteria_enable =
7727                 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
7728                 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
7729         match_criteria_enable |=
7730                 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
7731                 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
7732         match_criteria_enable |=
7733                 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
7734                 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
7735         match_criteria_enable |=
7736                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
7737                 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
7738         match_criteria_enable |=
7739                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
7740                 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
7741         match_criteria_enable |=
7742                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_4)) <<
7743                 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT;
7744         return match_criteria_enable;
7745 }
7746
7747
7748 /**
7749  * Get a flow table.
7750  *
7751  * @param[in, out] dev
7752  *   Pointer to rte_eth_dev structure.
7753  * @param[in] table_id
7754  *   Table id to use.
7755  * @param[in] egress
7756  *   Direction of the table.
7757  * @param[in] transfer
7758  *   E-Switch or NIC flow.
7759  * @param[out] error
7760  *   pointer to error structure.
7761  *
7762  * @return
7763  *   Returns tables resource based on the index, NULL in case of failed.
7764  */
7765 static struct mlx5_flow_tbl_resource *
7766 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
7767                          uint32_t table_id, uint8_t egress,
7768                          uint8_t transfer,
7769                          struct rte_flow_error *error)
7770 {
7771         struct mlx5_priv *priv = dev->data->dev_private;
7772         struct mlx5_dev_ctx_shared *sh = priv->sh;
7773         struct mlx5_flow_tbl_resource *tbl;
7774         union mlx5_flow_tbl_key table_key = {
7775                 {
7776                         .table_id = table_id,
7777                         .reserved = 0,
7778                         .domain = !!transfer,
7779                         .direction = !!egress,
7780                 }
7781         };
7782         struct mlx5_hlist_entry *pos = mlx5_hlist_lookup(sh->flow_tbls,
7783                                                          table_key.v64);
7784         struct mlx5_flow_tbl_data_entry *tbl_data;
7785         uint32_t idx = 0;
7786         int ret;
7787         void *domain;
7788
7789         if (pos) {
7790                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
7791                                         entry);
7792                 tbl = &tbl_data->tbl;
7793                 rte_atomic32_inc(&tbl->refcnt);
7794                 return tbl;
7795         }
7796         tbl_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
7797         if (!tbl_data) {
7798                 rte_flow_error_set(error, ENOMEM,
7799                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7800                                    NULL,
7801                                    "cannot allocate flow table data entry");
7802                 return NULL;
7803         }
7804         tbl_data->idx = idx;
7805         tbl = &tbl_data->tbl;
7806         pos = &tbl_data->entry;
7807         if (transfer)
7808                 domain = sh->fdb_domain;
7809         else if (egress)
7810                 domain = sh->tx_domain;
7811         else
7812                 domain = sh->rx_domain;
7813         ret = mlx5_flow_os_create_flow_tbl(domain, table_id, &tbl->obj);
7814         if (ret) {
7815                 rte_flow_error_set(error, ENOMEM,
7816                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7817                                    NULL, "cannot create flow table object");
7818                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
7819                 return NULL;
7820         }
7821         /*
7822          * No multi-threads now, but still better to initialize the reference
7823          * count before insert it into the hash list.
7824          */
7825         rte_atomic32_init(&tbl->refcnt);
7826         /* Jump action reference count is initialized here. */
7827         rte_atomic32_init(&tbl_data->jump.refcnt);
7828         pos->key = table_key.v64;
7829         ret = mlx5_hlist_insert(sh->flow_tbls, pos);
7830         if (ret < 0) {
7831                 rte_flow_error_set(error, -ret,
7832                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7833                                    "cannot insert flow table data entry");
7834                 mlx5_flow_os_destroy_flow_tbl(tbl->obj);
7835                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
7836         }
7837         rte_atomic32_inc(&tbl->refcnt);
7838         return tbl;
7839 }
7840
7841 /**
7842  * Release a flow table.
7843  *
7844  * @param[in] dev
7845  *   Pointer to rte_eth_dev structure.
7846  * @param[in] tbl
7847  *   Table resource to be released.
7848  *
7849  * @return
7850  *   Returns 0 if table was released, else return 1;
7851  */
7852 static int
7853 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
7854                              struct mlx5_flow_tbl_resource *tbl)
7855 {
7856         struct mlx5_priv *priv = dev->data->dev_private;
7857         struct mlx5_dev_ctx_shared *sh = priv->sh;
7858         struct mlx5_flow_tbl_data_entry *tbl_data =
7859                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
7860
7861         if (!tbl)
7862                 return 0;
7863         if (rte_atomic32_dec_and_test(&tbl->refcnt)) {
7864                 struct mlx5_hlist_entry *pos = &tbl_data->entry;
7865
7866                 mlx5_flow_os_destroy_flow_tbl(tbl->obj);
7867                 tbl->obj = NULL;
7868                 /* remove the entry from the hash list and free memory. */
7869                 mlx5_hlist_remove(sh->flow_tbls, pos);
7870                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_JUMP],
7871                                 tbl_data->idx);
7872                 return 0;
7873         }
7874         return 1;
7875 }
7876
7877 /**
7878  * Register the flow matcher.
7879  *
7880  * @param[in, out] dev
7881  *   Pointer to rte_eth_dev structure.
7882  * @param[in, out] matcher
7883  *   Pointer to flow matcher.
7884  * @param[in, out] key
7885  *   Pointer to flow table key.
7886  * @parm[in, out] dev_flow
7887  *   Pointer to the dev_flow.
7888  * @param[out] error
7889  *   pointer to error structure.
7890  *
7891  * @return
7892  *   0 on success otherwise -errno and errno is set.
7893  */
7894 static int
7895 flow_dv_matcher_register(struct rte_eth_dev *dev,
7896                          struct mlx5_flow_dv_matcher *matcher,
7897                          union mlx5_flow_tbl_key *key,
7898                          struct mlx5_flow *dev_flow,
7899                          struct rte_flow_error *error)
7900 {
7901         struct mlx5_priv *priv = dev->data->dev_private;
7902         struct mlx5_dev_ctx_shared *sh = priv->sh;
7903         struct mlx5_flow_dv_matcher *cache_matcher;
7904         struct mlx5dv_flow_matcher_attr dv_attr = {
7905                 .type = IBV_FLOW_ATTR_NORMAL,
7906                 .match_mask = (void *)&matcher->mask,
7907         };
7908         struct mlx5_flow_tbl_resource *tbl;
7909         struct mlx5_flow_tbl_data_entry *tbl_data;
7910         int ret;
7911
7912         tbl = flow_dv_tbl_resource_get(dev, key->table_id, key->direction,
7913                                        key->domain, error);
7914         if (!tbl)
7915                 return -rte_errno;      /* No need to refill the error info */
7916         tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
7917         /* Lookup from cache. */
7918         LIST_FOREACH(cache_matcher, &tbl_data->matchers, next) {
7919                 if (matcher->crc == cache_matcher->crc &&
7920                     matcher->priority == cache_matcher->priority &&
7921                     !memcmp((const void *)matcher->mask.buf,
7922                             (const void *)cache_matcher->mask.buf,
7923                             cache_matcher->mask.size)) {
7924                         DRV_LOG(DEBUG,
7925                                 "%s group %u priority %hd use %s "
7926                                 "matcher %p: refcnt %d++",
7927                                 key->domain ? "FDB" : "NIC", key->table_id,
7928                                 cache_matcher->priority,
7929                                 key->direction ? "tx" : "rx",
7930                                 (void *)cache_matcher,
7931                                 rte_atomic32_read(&cache_matcher->refcnt));
7932                         rte_atomic32_inc(&cache_matcher->refcnt);
7933                         dev_flow->handle->dvh.matcher = cache_matcher;
7934                         /* old matcher should not make the table ref++. */
7935                         flow_dv_tbl_resource_release(dev, tbl);
7936                         return 0;
7937                 }
7938         }
7939         /* Register new matcher. */
7940         cache_matcher = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*cache_matcher), 0,
7941                                     SOCKET_ID_ANY);
7942         if (!cache_matcher) {
7943                 flow_dv_tbl_resource_release(dev, tbl);
7944                 return rte_flow_error_set(error, ENOMEM,
7945                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7946                                           "cannot allocate matcher memory");
7947         }
7948         *cache_matcher = *matcher;
7949         dv_attr.match_criteria_enable =
7950                 flow_dv_matcher_enable(cache_matcher->mask.buf);
7951         dv_attr.priority = matcher->priority;
7952         if (key->direction)
7953                 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
7954         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj,
7955                                                &cache_matcher->matcher_object);
7956         if (ret) {
7957                 mlx5_free(cache_matcher);
7958 #ifdef HAVE_MLX5DV_DR
7959                 flow_dv_tbl_resource_release(dev, tbl);
7960 #endif
7961                 return rte_flow_error_set(error, ENOMEM,
7962                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7963                                           NULL, "cannot create matcher");
7964         }
7965         /* Save the table information */
7966         cache_matcher->tbl = tbl;
7967         rte_atomic32_init(&cache_matcher->refcnt);
7968         /* only matcher ref++, table ref++ already done above in get API. */
7969         rte_atomic32_inc(&cache_matcher->refcnt);
7970         LIST_INSERT_HEAD(&tbl_data->matchers, cache_matcher, next);
7971         dev_flow->handle->dvh.matcher = cache_matcher;
7972         DRV_LOG(DEBUG, "%s group %u priority %hd new %s matcher %p: refcnt %d",
7973                 key->domain ? "FDB" : "NIC", key->table_id,
7974                 cache_matcher->priority,
7975                 key->direction ? "tx" : "rx", (void *)cache_matcher,
7976                 rte_atomic32_read(&cache_matcher->refcnt));
7977         return 0;
7978 }
7979
7980 /**
7981  * Find existing tag resource or create and register a new one.
7982  *
7983  * @param dev[in, out]
7984  *   Pointer to rte_eth_dev structure.
7985  * @param[in, out] tag_be24
7986  *   Tag value in big endian then R-shift 8.
7987  * @parm[in, out] dev_flow
7988  *   Pointer to the dev_flow.
7989  * @param[out] error
7990  *   pointer to error structure.
7991  *
7992  * @return
7993  *   0 on success otherwise -errno and errno is set.
7994  */
7995 static int
7996 flow_dv_tag_resource_register
7997                         (struct rte_eth_dev *dev,
7998                          uint32_t tag_be24,
7999                          struct mlx5_flow *dev_flow,
8000                          struct rte_flow_error *error)
8001 {
8002         struct mlx5_priv *priv = dev->data->dev_private;
8003         struct mlx5_dev_ctx_shared *sh = priv->sh;
8004         struct mlx5_flow_dv_tag_resource *cache_resource;
8005         struct mlx5_hlist_entry *entry;
8006         int ret;
8007
8008         /* Lookup a matching resource from cache. */
8009         entry = mlx5_hlist_lookup(sh->tag_table, (uint64_t)tag_be24);
8010         if (entry) {
8011                 cache_resource = container_of
8012                         (entry, struct mlx5_flow_dv_tag_resource, entry);
8013                 rte_atomic32_inc(&cache_resource->refcnt);
8014                 dev_flow->handle->dvh.rix_tag = cache_resource->idx;
8015                 dev_flow->dv.tag_resource = cache_resource;
8016                 DRV_LOG(DEBUG, "cached tag resource %p: refcnt now %d++",
8017                         (void *)cache_resource,
8018                         rte_atomic32_read(&cache_resource->refcnt));
8019                 return 0;
8020         }
8021         /* Register new resource. */
8022         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_TAG],
8023                                        &dev_flow->handle->dvh.rix_tag);
8024         if (!cache_resource)
8025                 return rte_flow_error_set(error, ENOMEM,
8026                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8027                                           "cannot allocate resource memory");
8028         cache_resource->entry.key = (uint64_t)tag_be24;
8029         ret = mlx5_flow_os_create_flow_action_tag(tag_be24,
8030                                                   &cache_resource->action);
8031         if (ret) {
8032                 mlx5_free(cache_resource);
8033                 return rte_flow_error_set(error, ENOMEM,
8034                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8035                                           NULL, "cannot create action");
8036         }
8037         rte_atomic32_init(&cache_resource->refcnt);
8038         rte_atomic32_inc(&cache_resource->refcnt);
8039         if (mlx5_hlist_insert(sh->tag_table, &cache_resource->entry)) {
8040                 mlx5_flow_os_destroy_flow_action(cache_resource->action);
8041                 mlx5_free(cache_resource);
8042                 return rte_flow_error_set(error, EEXIST,
8043                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8044                                           NULL, "cannot insert tag");
8045         }
8046         dev_flow->dv.tag_resource = cache_resource;
8047         DRV_LOG(DEBUG, "new tag resource %p: refcnt now %d++",
8048                 (void *)cache_resource,
8049                 rte_atomic32_read(&cache_resource->refcnt));
8050         return 0;
8051 }
8052
8053 /**
8054  * Release the tag.
8055  *
8056  * @param dev
8057  *   Pointer to Ethernet device.
8058  * @param tag_idx
8059  *   Tag index.
8060  *
8061  * @return
8062  *   1 while a reference on it exists, 0 when freed.
8063  */
8064 static int
8065 flow_dv_tag_release(struct rte_eth_dev *dev,
8066                     uint32_t tag_idx)
8067 {
8068         struct mlx5_priv *priv = dev->data->dev_private;
8069         struct mlx5_dev_ctx_shared *sh = priv->sh;
8070         struct mlx5_flow_dv_tag_resource *tag;
8071
8072         tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
8073         if (!tag)
8074                 return 0;
8075         DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
8076                 dev->data->port_id, (void *)tag,
8077                 rte_atomic32_read(&tag->refcnt));
8078         if (rte_atomic32_dec_and_test(&tag->refcnt)) {
8079                 claim_zero(mlx5_flow_os_destroy_flow_action(tag->action));
8080                 mlx5_hlist_remove(sh->tag_table, &tag->entry);
8081                 DRV_LOG(DEBUG, "port %u tag %p: removed",
8082                         dev->data->port_id, (void *)tag);
8083                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
8084                 return 0;
8085         }
8086         return 1;
8087 }
8088
8089 /**
8090  * Translate port ID action to vport.
8091  *
8092  * @param[in] dev
8093  *   Pointer to rte_eth_dev structure.
8094  * @param[in] action
8095  *   Pointer to the port ID action.
8096  * @param[out] dst_port_id
8097  *   The target port ID.
8098  * @param[out] error
8099  *   Pointer to the error structure.
8100  *
8101  * @return
8102  *   0 on success, a negative errno value otherwise and rte_errno is set.
8103  */
8104 static int
8105 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
8106                                  const struct rte_flow_action *action,
8107                                  uint32_t *dst_port_id,
8108                                  struct rte_flow_error *error)
8109 {
8110         uint32_t port;
8111         struct mlx5_priv *priv;
8112         const struct rte_flow_action_port_id *conf =
8113                         (const struct rte_flow_action_port_id *)action->conf;
8114
8115         port = conf->original ? dev->data->port_id : conf->id;
8116         priv = mlx5_port_to_eswitch_info(port, false);
8117         if (!priv)
8118                 return rte_flow_error_set(error, -rte_errno,
8119                                           RTE_FLOW_ERROR_TYPE_ACTION,
8120                                           NULL,
8121                                           "No eswitch info was found for port");
8122 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
8123         /*
8124          * This parameter is transferred to
8125          * mlx5dv_dr_action_create_dest_ib_port().
8126          */
8127         *dst_port_id = priv->dev_port;
8128 #else
8129         /*
8130          * Legacy mode, no LAG configurations is supported.
8131          * This parameter is transferred to
8132          * mlx5dv_dr_action_create_dest_vport().
8133          */
8134         *dst_port_id = priv->vport_id;
8135 #endif
8136         return 0;
8137 }
8138
8139 /**
8140  * Create a counter with aging configuration.
8141  *
8142  * @param[in] dev
8143  *   Pointer to rte_eth_dev structure.
8144  * @param[out] count
8145  *   Pointer to the counter action configuration.
8146  * @param[in] age
8147  *   Pointer to the aging action configuration.
8148  *
8149  * @return
8150  *   Index to flow counter on success, 0 otherwise.
8151  */
8152 static uint32_t
8153 flow_dv_translate_create_counter(struct rte_eth_dev *dev,
8154                                 struct mlx5_flow *dev_flow,
8155                                 const struct rte_flow_action_count *count,
8156                                 const struct rte_flow_action_age *age)
8157 {
8158         uint32_t counter;
8159         struct mlx5_age_param *age_param;
8160
8161         counter = flow_dv_counter_alloc(dev,
8162                                 count ? count->shared : 0,
8163                                 count ? count->id : 0,
8164                                 dev_flow->dv.group, !!age);
8165         if (!counter || age == NULL)
8166                 return counter;
8167         age_param  = flow_dv_counter_idx_get_age(dev, counter);
8168         /*
8169          * The counter age accuracy may have a bit delay. Have 3/4
8170          * second bias on the timeount in order to let it age in time.
8171          */
8172         age_param->context = age->context ? age->context :
8173                 (void *)(uintptr_t)(dev_flow->flow_idx);
8174         /*
8175          * The counter age accuracy may have a bit delay. Have 3/4
8176          * second bias on the timeount in order to let it age in time.
8177          */
8178         age_param->timeout = age->timeout * 10 - MLX5_AGING_TIME_DELAY;
8179         /* Set expire time in unit of 0.1 sec. */
8180         age_param->port_id = dev->data->port_id;
8181         age_param->expire = age_param->timeout +
8182                         rte_rdtsc() / (rte_get_tsc_hz() / 10);
8183         rte_atomic16_set(&age_param->state, AGE_CANDIDATE);
8184         return counter;
8185 }
8186 /**
8187  * Add Tx queue matcher
8188  *
8189  * @param[in] dev
8190  *   Pointer to the dev struct.
8191  * @param[in, out] matcher
8192  *   Flow matcher.
8193  * @param[in, out] key
8194  *   Flow matcher value.
8195  * @param[in] item
8196  *   Flow pattern to translate.
8197  * @param[in] inner
8198  *   Item is inner pattern.
8199  */
8200 static void
8201 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
8202                                 void *matcher, void *key,
8203                                 const struct rte_flow_item *item)
8204 {
8205         const struct mlx5_rte_flow_item_tx_queue *queue_m;
8206         const struct mlx5_rte_flow_item_tx_queue *queue_v;
8207         void *misc_m =
8208                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8209         void *misc_v =
8210                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8211         struct mlx5_txq_ctrl *txq;
8212         uint32_t queue;
8213
8214
8215         queue_m = (const void *)item->mask;
8216         if (!queue_m)
8217                 return;
8218         queue_v = (const void *)item->spec;
8219         if (!queue_v)
8220                 return;
8221         txq = mlx5_txq_get(dev, queue_v->queue);
8222         if (!txq)
8223                 return;
8224         queue = txq->obj->sq->id;
8225         MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
8226         MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
8227                  queue & queue_m->queue);
8228         mlx5_txq_release(dev, queue_v->queue);
8229 }
8230
8231 /**
8232  * Set the hash fields according to the @p flow information.
8233  *
8234  * @param[in] dev_flow
8235  *   Pointer to the mlx5_flow.
8236  * @param[in] rss_desc
8237  *   Pointer to the mlx5_flow_rss_desc.
8238  */
8239 static void
8240 flow_dv_hashfields_set(struct mlx5_flow *dev_flow,
8241                        struct mlx5_flow_rss_desc *rss_desc)
8242 {
8243         uint64_t items = dev_flow->handle->layers;
8244         int rss_inner = 0;
8245         uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
8246
8247         dev_flow->hash_fields = 0;
8248 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
8249         if (rss_desc->level >= 2) {
8250                 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
8251                 rss_inner = 1;
8252         }
8253 #endif
8254         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
8255             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
8256                 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
8257                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
8258                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
8259                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
8260                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
8261                         else
8262                                 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
8263                 }
8264         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
8265                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
8266                 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
8267                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
8268                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
8269                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
8270                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
8271                         else
8272                                 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
8273                 }
8274         }
8275         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
8276             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
8277                 if (rss_types & ETH_RSS_UDP) {
8278                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
8279                                 dev_flow->hash_fields |=
8280                                                 IBV_RX_HASH_SRC_PORT_UDP;
8281                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
8282                                 dev_flow->hash_fields |=
8283                                                 IBV_RX_HASH_DST_PORT_UDP;
8284                         else
8285                                 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
8286                 }
8287         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
8288                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
8289                 if (rss_types & ETH_RSS_TCP) {
8290                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
8291                                 dev_flow->hash_fields |=
8292                                                 IBV_RX_HASH_SRC_PORT_TCP;
8293                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
8294                                 dev_flow->hash_fields |=
8295                                                 IBV_RX_HASH_DST_PORT_TCP;
8296                         else
8297                                 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
8298                 }
8299         }
8300 }
8301
8302 /**
8303  * Fill the flow with DV spec, lock free
8304  * (mutex should be acquired by caller).
8305  *
8306  * @param[in] dev
8307  *   Pointer to rte_eth_dev structure.
8308  * @param[in, out] dev_flow
8309  *   Pointer to the sub flow.
8310  * @param[in] attr
8311  *   Pointer to the flow attributes.
8312  * @param[in] items
8313  *   Pointer to the list of items.
8314  * @param[in] actions
8315  *   Pointer to the list of actions.
8316  * @param[out] error
8317  *   Pointer to the error structure.
8318  *
8319  * @return
8320  *   0 on success, a negative errno value otherwise and rte_errno is set.
8321  */
8322 static int
8323 __flow_dv_translate(struct rte_eth_dev *dev,
8324                     struct mlx5_flow *dev_flow,
8325                     const struct rte_flow_attr *attr,
8326                     const struct rte_flow_item items[],
8327                     const struct rte_flow_action actions[],
8328                     struct rte_flow_error *error)
8329 {
8330         struct mlx5_priv *priv = dev->data->dev_private;
8331         struct mlx5_dev_config *dev_conf = &priv->config;
8332         struct rte_flow *flow = dev_flow->flow;
8333         struct mlx5_flow_handle *handle = dev_flow->handle;
8334         struct mlx5_flow_rss_desc *rss_desc = &((struct mlx5_flow_rss_desc *)
8335                                               priv->rss_desc)
8336                                               [!!priv->flow_nested_idx];
8337         uint64_t item_flags = 0;
8338         uint64_t last_item = 0;
8339         uint64_t action_flags = 0;
8340         uint64_t priority = attr->priority;
8341         struct mlx5_flow_dv_matcher matcher = {
8342                 .mask = {
8343                         .size = sizeof(matcher.mask.buf) -
8344                                 MLX5_ST_SZ_BYTES(fte_match_set_misc4),
8345                 },
8346         };
8347         int actions_n = 0;
8348         bool actions_end = false;
8349         union {
8350                 struct mlx5_flow_dv_modify_hdr_resource res;
8351                 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
8352                             sizeof(struct mlx5_modification_cmd) *
8353                             (MLX5_MAX_MODIFY_NUM + 1)];
8354         } mhdr_dummy;
8355         struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
8356         const struct rte_flow_action_count *count = NULL;
8357         const struct rte_flow_action_age *age = NULL;
8358         union flow_dv_attr flow_attr = { .attr = 0 };
8359         uint32_t tag_be;
8360         union mlx5_flow_tbl_key tbl_key;
8361         uint32_t modify_action_position = UINT32_MAX;
8362         void *match_mask = matcher.mask.buf;
8363         void *match_value = dev_flow->dv.value.buf;
8364         uint8_t next_protocol = 0xff;
8365         struct rte_vlan_hdr vlan = { 0 };
8366         uint32_t table;
8367         int ret = 0;
8368
8369         mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
8370                                            MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
8371         ret = mlx5_flow_group_to_table(attr, dev_flow->external, attr->group,
8372                                        !!priv->fdb_def_rule, &table, error);
8373         if (ret)
8374                 return ret;
8375         dev_flow->dv.group = table;
8376         if (attr->transfer)
8377                 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
8378         if (priority == MLX5_FLOW_PRIO_RSVD)
8379                 priority = dev_conf->flow_prio - 1;
8380         /* number of actions must be set to 0 in case of dirty stack. */
8381         mhdr_res->actions_num = 0;
8382         for (; !actions_end ; actions++) {
8383                 const struct rte_flow_action_queue *queue;
8384                 const struct rte_flow_action_rss *rss;
8385                 const struct rte_flow_action *action = actions;
8386                 const uint8_t *rss_key;
8387                 const struct rte_flow_action_jump *jump_data;
8388                 const struct rte_flow_action_meter *mtr;
8389                 struct mlx5_flow_tbl_resource *tbl;
8390                 uint32_t port_id = 0;
8391                 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
8392                 int action_type = actions->type;
8393                 const struct rte_flow_action *found_action = NULL;
8394                 struct mlx5_flow_meter *fm = NULL;
8395
8396                 if (!mlx5_flow_os_action_supported(action_type))
8397                         return rte_flow_error_set(error, ENOTSUP,
8398                                                   RTE_FLOW_ERROR_TYPE_ACTION,
8399                                                   actions,
8400                                                   "action not supported");
8401                 switch (action_type) {
8402                 case RTE_FLOW_ACTION_TYPE_VOID:
8403                         break;
8404                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
8405                         if (flow_dv_translate_action_port_id(dev, action,
8406                                                              &port_id, error))
8407                                 return -rte_errno;
8408                         port_id_resource.port_id = port_id;
8409                         MLX5_ASSERT(!handle->rix_port_id_action);
8410                         if (flow_dv_port_id_action_resource_register
8411                             (dev, &port_id_resource, dev_flow, error))
8412                                 return -rte_errno;
8413                         dev_flow->dv.actions[actions_n++] =
8414                                         dev_flow->dv.port_id_action->action;
8415                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
8416                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_PORT_ID;
8417                         break;
8418                 case RTE_FLOW_ACTION_TYPE_FLAG:
8419                         action_flags |= MLX5_FLOW_ACTION_FLAG;
8420                         dev_flow->handle->mark = 1;
8421                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
8422                                 struct rte_flow_action_mark mark = {
8423                                         .id = MLX5_FLOW_MARK_DEFAULT,
8424                                 };
8425
8426                                 if (flow_dv_convert_action_mark(dev, &mark,
8427                                                                 mhdr_res,
8428                                                                 error))
8429                                         return -rte_errno;
8430                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
8431                                 break;
8432                         }
8433                         tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
8434                         /*
8435                          * Only one FLAG or MARK is supported per device flow
8436                          * right now. So the pointer to the tag resource must be
8437                          * zero before the register process.
8438                          */
8439                         MLX5_ASSERT(!handle->dvh.rix_tag);
8440                         if (flow_dv_tag_resource_register(dev, tag_be,
8441                                                           dev_flow, error))
8442                                 return -rte_errno;
8443                         MLX5_ASSERT(dev_flow->dv.tag_resource);
8444                         dev_flow->dv.actions[actions_n++] =
8445                                         dev_flow->dv.tag_resource->action;
8446                         break;
8447                 case RTE_FLOW_ACTION_TYPE_MARK:
8448                         action_flags |= MLX5_FLOW_ACTION_MARK;
8449                         dev_flow->handle->mark = 1;
8450                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
8451                                 const struct rte_flow_action_mark *mark =
8452                                         (const struct rte_flow_action_mark *)
8453                                                 actions->conf;
8454
8455                                 if (flow_dv_convert_action_mark(dev, mark,
8456                                                                 mhdr_res,
8457                                                                 error))
8458                                         return -rte_errno;
8459                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
8460                                 break;
8461                         }
8462                         /* Fall-through */
8463                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
8464                         /* Legacy (non-extensive) MARK action. */
8465                         tag_be = mlx5_flow_mark_set
8466                               (((const struct rte_flow_action_mark *)
8467                                (actions->conf))->id);
8468                         MLX5_ASSERT(!handle->dvh.rix_tag);
8469                         if (flow_dv_tag_resource_register(dev, tag_be,
8470                                                           dev_flow, error))
8471                                 return -rte_errno;
8472                         MLX5_ASSERT(dev_flow->dv.tag_resource);
8473                         dev_flow->dv.actions[actions_n++] =
8474                                         dev_flow->dv.tag_resource->action;
8475                         break;
8476                 case RTE_FLOW_ACTION_TYPE_SET_META:
8477                         if (flow_dv_convert_action_set_meta
8478                                 (dev, mhdr_res, attr,
8479                                  (const struct rte_flow_action_set_meta *)
8480                                   actions->conf, error))
8481                                 return -rte_errno;
8482                         action_flags |= MLX5_FLOW_ACTION_SET_META;
8483                         break;
8484                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
8485                         if (flow_dv_convert_action_set_tag
8486                                 (dev, mhdr_res,
8487                                  (const struct rte_flow_action_set_tag *)
8488                                   actions->conf, error))
8489                                 return -rte_errno;
8490                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
8491                         break;
8492                 case RTE_FLOW_ACTION_TYPE_DROP:
8493                         action_flags |= MLX5_FLOW_ACTION_DROP;
8494                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_DROP;
8495                         break;
8496                 case RTE_FLOW_ACTION_TYPE_QUEUE:
8497                         queue = actions->conf;
8498                         rss_desc->queue_num = 1;
8499                         rss_desc->queue[0] = queue->index;
8500                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
8501                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
8502                         break;
8503                 case RTE_FLOW_ACTION_TYPE_RSS:
8504                         rss = actions->conf;
8505                         memcpy(rss_desc->queue, rss->queue,
8506                                rss->queue_num * sizeof(uint16_t));
8507                         rss_desc->queue_num = rss->queue_num;
8508                         /* NULL RSS key indicates default RSS key. */
8509                         rss_key = !rss->key ? rss_hash_default_key : rss->key;
8510                         memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
8511                         /*
8512                          * rss->level and rss.types should be set in advance
8513                          * when expanding items for RSS.
8514                          */
8515                         action_flags |= MLX5_FLOW_ACTION_RSS;
8516                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
8517                         break;
8518                 case RTE_FLOW_ACTION_TYPE_AGE:
8519                 case RTE_FLOW_ACTION_TYPE_COUNT:
8520                         if (!dev_conf->devx) {
8521                                 return rte_flow_error_set
8522                                               (error, ENOTSUP,
8523                                                RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8524                                                NULL,
8525                                                "count action not supported");
8526                         }
8527                         /* Save information first, will apply later. */
8528                         if (actions->type == RTE_FLOW_ACTION_TYPE_COUNT)
8529                                 count = action->conf;
8530                         else
8531                                 age = action->conf;
8532                         action_flags |= MLX5_FLOW_ACTION_COUNT;
8533                         break;
8534                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
8535                         dev_flow->dv.actions[actions_n++] =
8536                                                 priv->sh->pop_vlan_action;
8537                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
8538                         break;
8539                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
8540                         if (!(action_flags &
8541                               MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
8542                                 flow_dev_get_vlan_info_from_items(items, &vlan);
8543                         vlan.eth_proto = rte_be_to_cpu_16
8544                              ((((const struct rte_flow_action_of_push_vlan *)
8545                                                    actions->conf)->ethertype));
8546                         found_action = mlx5_flow_find_action
8547                                         (actions + 1,
8548                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
8549                         if (found_action)
8550                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
8551                         found_action = mlx5_flow_find_action
8552                                         (actions + 1,
8553                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
8554                         if (found_action)
8555                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
8556                         if (flow_dv_create_action_push_vlan
8557                                             (dev, attr, &vlan, dev_flow, error))
8558                                 return -rte_errno;
8559                         dev_flow->dv.actions[actions_n++] =
8560                                         dev_flow->dv.push_vlan_res->action;
8561                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
8562                         break;
8563                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
8564                         /* of_vlan_push action handled this action */
8565                         MLX5_ASSERT(action_flags &
8566                                     MLX5_FLOW_ACTION_OF_PUSH_VLAN);
8567                         break;
8568                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
8569                         if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
8570                                 break;
8571                         flow_dev_get_vlan_info_from_items(items, &vlan);
8572                         mlx5_update_vlan_vid_pcp(actions, &vlan);
8573                         /* If no VLAN push - this is a modify header action */
8574                         if (flow_dv_convert_action_modify_vlan_vid
8575                                                 (mhdr_res, actions, error))
8576                                 return -rte_errno;
8577                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
8578                         break;
8579                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
8580                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
8581                         if (flow_dv_create_action_l2_encap(dev, actions,
8582                                                            dev_flow,
8583                                                            attr->transfer,
8584                                                            error))
8585                                 return -rte_errno;
8586                         dev_flow->dv.actions[actions_n++] =
8587                                         dev_flow->dv.encap_decap->action;
8588                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
8589                         break;
8590                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
8591                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
8592                         if (flow_dv_create_action_l2_decap(dev, dev_flow,
8593                                                            attr->transfer,
8594                                                            error))
8595                                 return -rte_errno;
8596                         dev_flow->dv.actions[actions_n++] =
8597                                         dev_flow->dv.encap_decap->action;
8598                         action_flags |= MLX5_FLOW_ACTION_DECAP;
8599                         break;
8600                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
8601                         /* Handle encap with preceding decap. */
8602                         if (action_flags & MLX5_FLOW_ACTION_DECAP) {
8603                                 if (flow_dv_create_action_raw_encap
8604                                         (dev, actions, dev_flow, attr, error))
8605                                         return -rte_errno;
8606                                 dev_flow->dv.actions[actions_n++] =
8607                                         dev_flow->dv.encap_decap->action;
8608                         } else {
8609                                 /* Handle encap without preceding decap. */
8610                                 if (flow_dv_create_action_l2_encap
8611                                     (dev, actions, dev_flow, attr->transfer,
8612                                      error))
8613                                         return -rte_errno;
8614                                 dev_flow->dv.actions[actions_n++] =
8615                                         dev_flow->dv.encap_decap->action;
8616                         }
8617                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
8618                         break;
8619                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
8620                         while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
8621                                 ;
8622                         if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
8623                                 if (flow_dv_create_action_l2_decap
8624                                     (dev, dev_flow, attr->transfer, error))
8625                                         return -rte_errno;
8626                                 dev_flow->dv.actions[actions_n++] =
8627                                         dev_flow->dv.encap_decap->action;
8628                         }
8629                         /* If decap is followed by encap, handle it at encap. */
8630                         action_flags |= MLX5_FLOW_ACTION_DECAP;
8631                         break;
8632                 case RTE_FLOW_ACTION_TYPE_JUMP:
8633                         jump_data = action->conf;
8634                         ret = mlx5_flow_group_to_table(attr, dev_flow->external,
8635                                                        jump_data->group,
8636                                                        !!priv->fdb_def_rule,
8637                                                        &table, error);
8638                         if (ret)
8639                                 return ret;
8640                         tbl = flow_dv_tbl_resource_get(dev, table,
8641                                                        attr->egress,
8642                                                        attr->transfer, error);
8643                         if (!tbl)
8644                                 return rte_flow_error_set
8645                                                 (error, errno,
8646                                                  RTE_FLOW_ERROR_TYPE_ACTION,
8647                                                  NULL,
8648                                                  "cannot create jump action.");
8649                         if (flow_dv_jump_tbl_resource_register
8650                             (dev, tbl, dev_flow, error)) {
8651                                 flow_dv_tbl_resource_release(dev, tbl);
8652                                 return rte_flow_error_set
8653                                                 (error, errno,
8654                                                  RTE_FLOW_ERROR_TYPE_ACTION,
8655                                                  NULL,
8656                                                  "cannot create jump action.");
8657                         }
8658                         dev_flow->dv.actions[actions_n++] =
8659                                         dev_flow->dv.jump->action;
8660                         action_flags |= MLX5_FLOW_ACTION_JUMP;
8661                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_JUMP;
8662                         break;
8663                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
8664                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
8665                         if (flow_dv_convert_action_modify_mac
8666                                         (mhdr_res, actions, error))
8667                                 return -rte_errno;
8668                         action_flags |= actions->type ==
8669                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
8670                                         MLX5_FLOW_ACTION_SET_MAC_SRC :
8671                                         MLX5_FLOW_ACTION_SET_MAC_DST;
8672                         break;
8673                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
8674                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
8675                         if (flow_dv_convert_action_modify_ipv4
8676                                         (mhdr_res, actions, error))
8677                                 return -rte_errno;
8678                         action_flags |= actions->type ==
8679                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
8680                                         MLX5_FLOW_ACTION_SET_IPV4_SRC :
8681                                         MLX5_FLOW_ACTION_SET_IPV4_DST;
8682                         break;
8683                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
8684                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
8685                         if (flow_dv_convert_action_modify_ipv6
8686                                         (mhdr_res, actions, error))
8687                                 return -rte_errno;
8688                         action_flags |= actions->type ==
8689                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
8690                                         MLX5_FLOW_ACTION_SET_IPV6_SRC :
8691                                         MLX5_FLOW_ACTION_SET_IPV6_DST;
8692                         break;
8693                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
8694                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
8695                         if (flow_dv_convert_action_modify_tp
8696                                         (mhdr_res, actions, items,
8697                                          &flow_attr, dev_flow, !!(action_flags &
8698                                          MLX5_FLOW_ACTION_DECAP), error))
8699                                 return -rte_errno;
8700                         action_flags |= actions->type ==
8701                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
8702                                         MLX5_FLOW_ACTION_SET_TP_SRC :
8703                                         MLX5_FLOW_ACTION_SET_TP_DST;
8704                         break;
8705                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
8706                         if (flow_dv_convert_action_modify_dec_ttl
8707                                         (mhdr_res, items, &flow_attr, dev_flow,
8708                                          !!(action_flags &
8709                                          MLX5_FLOW_ACTION_DECAP), error))
8710                                 return -rte_errno;
8711                         action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
8712                         break;
8713                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
8714                         if (flow_dv_convert_action_modify_ttl
8715                                         (mhdr_res, actions, items, &flow_attr,
8716                                          dev_flow, !!(action_flags &
8717                                          MLX5_FLOW_ACTION_DECAP), error))
8718                                 return -rte_errno;
8719                         action_flags |= MLX5_FLOW_ACTION_SET_TTL;
8720                         break;
8721                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
8722                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
8723                         if (flow_dv_convert_action_modify_tcp_seq
8724                                         (mhdr_res, actions, error))
8725                                 return -rte_errno;
8726                         action_flags |= actions->type ==
8727                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
8728                                         MLX5_FLOW_ACTION_INC_TCP_SEQ :
8729                                         MLX5_FLOW_ACTION_DEC_TCP_SEQ;
8730                         break;
8731
8732                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
8733                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
8734                         if (flow_dv_convert_action_modify_tcp_ack
8735                                         (mhdr_res, actions, error))
8736                                 return -rte_errno;
8737                         action_flags |= actions->type ==
8738                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
8739                                         MLX5_FLOW_ACTION_INC_TCP_ACK :
8740                                         MLX5_FLOW_ACTION_DEC_TCP_ACK;
8741                         break;
8742                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
8743                         if (flow_dv_convert_action_set_reg
8744                                         (mhdr_res, actions, error))
8745                                 return -rte_errno;
8746                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
8747                         break;
8748                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
8749                         if (flow_dv_convert_action_copy_mreg
8750                                         (dev, mhdr_res, actions, error))
8751                                 return -rte_errno;
8752                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
8753                         break;
8754                 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
8755                         action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
8756                         dev_flow->handle->fate_action =
8757                                         MLX5_FLOW_FATE_DEFAULT_MISS;
8758                         break;
8759                 case RTE_FLOW_ACTION_TYPE_METER:
8760                         mtr = actions->conf;
8761                         if (!flow->meter) {
8762                                 fm = mlx5_flow_meter_attach(priv, mtr->mtr_id,
8763                                                             attr, error);
8764                                 if (!fm)
8765                                         return rte_flow_error_set(error,
8766                                                 rte_errno,
8767                                                 RTE_FLOW_ERROR_TYPE_ACTION,
8768                                                 NULL,
8769                                                 "meter not found "
8770                                                 "or invalid parameters");
8771                                 flow->meter = fm->idx;
8772                         }
8773                         /* Set the meter action. */
8774                         if (!fm) {
8775                                 fm = mlx5_ipool_get(priv->sh->ipool
8776                                                 [MLX5_IPOOL_MTR], flow->meter);
8777                                 if (!fm)
8778                                         return rte_flow_error_set(error,
8779                                                 rte_errno,
8780                                                 RTE_FLOW_ERROR_TYPE_ACTION,
8781                                                 NULL,
8782                                                 "meter not found "
8783                                                 "or invalid parameters");
8784                         }
8785                         dev_flow->dv.actions[actions_n++] =
8786                                 fm->mfts->meter_action;
8787                         action_flags |= MLX5_FLOW_ACTION_METER;
8788                         break;
8789                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
8790                         if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
8791                                                               actions, error))
8792                                 return -rte_errno;
8793                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
8794                         break;
8795                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
8796                         if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
8797                                                               actions, error))
8798                                 return -rte_errno;
8799                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
8800                         break;
8801                 case RTE_FLOW_ACTION_TYPE_END:
8802                         actions_end = true;
8803                         if (mhdr_res->actions_num) {
8804                                 /* create modify action if needed. */
8805                                 if (flow_dv_modify_hdr_resource_register
8806                                         (dev, mhdr_res, dev_flow, error))
8807                                         return -rte_errno;
8808                                 dev_flow->dv.actions[modify_action_position] =
8809                                         handle->dvh.modify_hdr->action;
8810                         }
8811                         if (action_flags & MLX5_FLOW_ACTION_COUNT) {
8812                                 flow->counter =
8813                                         flow_dv_translate_create_counter(dev,
8814                                                 dev_flow, count, age);
8815
8816                                 if (!flow->counter)
8817                                         return rte_flow_error_set
8818                                                 (error, rte_errno,
8819                                                 RTE_FLOW_ERROR_TYPE_ACTION,
8820                                                 NULL,
8821                                                 "cannot create counter"
8822                                                 " object.");
8823                                 dev_flow->dv.actions[actions_n++] =
8824                                           (flow_dv_counter_get_by_idx(dev,
8825                                           flow->counter, NULL))->action;
8826                         }
8827                         break;
8828                 default:
8829                         break;
8830                 }
8831                 if (mhdr_res->actions_num &&
8832                     modify_action_position == UINT32_MAX)
8833                         modify_action_position = actions_n++;
8834         }
8835         dev_flow->dv.actions_n = actions_n;
8836         dev_flow->act_flags = action_flags;
8837         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
8838                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
8839                 int item_type = items->type;
8840
8841                 if (!mlx5_flow_os_item_supported(item_type))
8842                         return rte_flow_error_set(error, ENOTSUP,
8843                                                   RTE_FLOW_ERROR_TYPE_ITEM,
8844                                                   NULL, "item not supported");
8845                 switch (item_type) {
8846                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
8847                         flow_dv_translate_item_port_id(dev, match_mask,
8848                                                        match_value, items);
8849                         last_item = MLX5_FLOW_ITEM_PORT_ID;
8850                         break;
8851                 case RTE_FLOW_ITEM_TYPE_ETH:
8852                         flow_dv_translate_item_eth(match_mask, match_value,
8853                                                    items, tunnel,
8854                                                    dev_flow->dv.group);
8855                         matcher.priority = action_flags &
8856                                         MLX5_FLOW_ACTION_DEFAULT_MISS &&
8857                                         !dev_flow->external ?
8858                                         MLX5_PRIORITY_MAP_L3 :
8859                                         MLX5_PRIORITY_MAP_L2;
8860                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
8861                                              MLX5_FLOW_LAYER_OUTER_L2;
8862                         break;
8863                 case RTE_FLOW_ITEM_TYPE_VLAN:
8864                         flow_dv_translate_item_vlan(dev_flow,
8865                                                     match_mask, match_value,
8866                                                     items, tunnel,
8867                                                     dev_flow->dv.group);
8868                         matcher.priority = MLX5_PRIORITY_MAP_L2;
8869                         last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
8870                                               MLX5_FLOW_LAYER_INNER_VLAN) :
8871                                              (MLX5_FLOW_LAYER_OUTER_L2 |
8872                                               MLX5_FLOW_LAYER_OUTER_VLAN);
8873                         break;
8874                 case RTE_FLOW_ITEM_TYPE_IPV4:
8875                         mlx5_flow_tunnel_ip_check(items, next_protocol,
8876                                                   &item_flags, &tunnel);
8877                         flow_dv_translate_item_ipv4(match_mask, match_value,
8878                                                     items, item_flags, tunnel,
8879                                                     dev_flow->dv.group);
8880                         matcher.priority = MLX5_PRIORITY_MAP_L3;
8881                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
8882                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
8883                         if (items->mask != NULL &&
8884                             ((const struct rte_flow_item_ipv4 *)
8885                              items->mask)->hdr.next_proto_id) {
8886                                 next_protocol =
8887                                         ((const struct rte_flow_item_ipv4 *)
8888                                          (items->spec))->hdr.next_proto_id;
8889                                 next_protocol &=
8890                                         ((const struct rte_flow_item_ipv4 *)
8891                                          (items->mask))->hdr.next_proto_id;
8892                         } else {
8893                                 /* Reset for inner layer. */
8894                                 next_protocol = 0xff;
8895                         }
8896                         break;
8897                 case RTE_FLOW_ITEM_TYPE_IPV6:
8898                         mlx5_flow_tunnel_ip_check(items, next_protocol,
8899                                                   &item_flags, &tunnel);
8900                         flow_dv_translate_item_ipv6(match_mask, match_value,
8901                                                     items, item_flags, tunnel,
8902                                                     dev_flow->dv.group);
8903                         matcher.priority = MLX5_PRIORITY_MAP_L3;
8904                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
8905                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
8906                         if (items->mask != NULL &&
8907                             ((const struct rte_flow_item_ipv6 *)
8908                              items->mask)->hdr.proto) {
8909                                 next_protocol =
8910                                         ((const struct rte_flow_item_ipv6 *)
8911                                          items->spec)->hdr.proto;
8912                                 next_protocol &=
8913                                         ((const struct rte_flow_item_ipv6 *)
8914                                          items->mask)->hdr.proto;
8915                         } else {
8916                                 /* Reset for inner layer. */
8917                                 next_protocol = 0xff;
8918                         }
8919                         break;
8920                 case RTE_FLOW_ITEM_TYPE_TCP:
8921                         flow_dv_translate_item_tcp(match_mask, match_value,
8922                                                    items, tunnel);
8923                         matcher.priority = MLX5_PRIORITY_MAP_L4;
8924                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
8925                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
8926                         break;
8927                 case RTE_FLOW_ITEM_TYPE_UDP:
8928                         flow_dv_translate_item_udp(match_mask, match_value,
8929                                                    items, tunnel);
8930                         matcher.priority = MLX5_PRIORITY_MAP_L4;
8931                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
8932                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
8933                         break;
8934                 case RTE_FLOW_ITEM_TYPE_GRE:
8935                         flow_dv_translate_item_gre(match_mask, match_value,
8936                                                    items, tunnel);
8937                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
8938                         last_item = MLX5_FLOW_LAYER_GRE;
8939                         break;
8940                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
8941                         flow_dv_translate_item_gre_key(match_mask,
8942                                                        match_value, items);
8943                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
8944                         break;
8945                 case RTE_FLOW_ITEM_TYPE_NVGRE:
8946                         flow_dv_translate_item_nvgre(match_mask, match_value,
8947                                                      items, tunnel);
8948                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
8949                         last_item = MLX5_FLOW_LAYER_GRE;
8950                         break;
8951                 case RTE_FLOW_ITEM_TYPE_VXLAN:
8952                         flow_dv_translate_item_vxlan(match_mask, match_value,
8953                                                      items, tunnel);
8954                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
8955                         last_item = MLX5_FLOW_LAYER_VXLAN;
8956                         break;
8957                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
8958                         flow_dv_translate_item_vxlan_gpe(match_mask,
8959                                                          match_value, items,
8960                                                          tunnel);
8961                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
8962                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
8963                         break;
8964                 case RTE_FLOW_ITEM_TYPE_GENEVE:
8965                         flow_dv_translate_item_geneve(match_mask, match_value,
8966                                                       items, tunnel);
8967                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
8968                         last_item = MLX5_FLOW_LAYER_GENEVE;
8969                         break;
8970                 case RTE_FLOW_ITEM_TYPE_MPLS:
8971                         flow_dv_translate_item_mpls(match_mask, match_value,
8972                                                     items, last_item, tunnel);
8973                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
8974                         last_item = MLX5_FLOW_LAYER_MPLS;
8975                         break;
8976                 case RTE_FLOW_ITEM_TYPE_MARK:
8977                         flow_dv_translate_item_mark(dev, match_mask,
8978                                                     match_value, items);
8979                         last_item = MLX5_FLOW_ITEM_MARK;
8980                         break;
8981                 case RTE_FLOW_ITEM_TYPE_META:
8982                         flow_dv_translate_item_meta(dev, match_mask,
8983                                                     match_value, attr, items);
8984                         last_item = MLX5_FLOW_ITEM_METADATA;
8985                         break;
8986                 case RTE_FLOW_ITEM_TYPE_ICMP:
8987                         flow_dv_translate_item_icmp(match_mask, match_value,
8988                                                     items, tunnel);
8989                         last_item = MLX5_FLOW_LAYER_ICMP;
8990                         break;
8991                 case RTE_FLOW_ITEM_TYPE_ICMP6:
8992                         flow_dv_translate_item_icmp6(match_mask, match_value,
8993                                                       items, tunnel);
8994                         last_item = MLX5_FLOW_LAYER_ICMP6;
8995                         break;
8996                 case RTE_FLOW_ITEM_TYPE_TAG:
8997                         flow_dv_translate_item_tag(dev, match_mask,
8998                                                    match_value, items);
8999                         last_item = MLX5_FLOW_ITEM_TAG;
9000                         break;
9001                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
9002                         flow_dv_translate_mlx5_item_tag(dev, match_mask,
9003                                                         match_value, items);
9004                         last_item = MLX5_FLOW_ITEM_TAG;
9005                         break;
9006                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
9007                         flow_dv_translate_item_tx_queue(dev, match_mask,
9008                                                         match_value,
9009                                                         items);
9010                         last_item = MLX5_FLOW_ITEM_TX_QUEUE;
9011                         break;
9012                 case RTE_FLOW_ITEM_TYPE_GTP:
9013                         flow_dv_translate_item_gtp(match_mask, match_value,
9014                                                    items, tunnel);
9015                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
9016                         last_item = MLX5_FLOW_LAYER_GTP;
9017                         break;
9018                 case RTE_FLOW_ITEM_TYPE_ECPRI:
9019                         if (!mlx5_flex_parser_ecpri_exist(dev)) {
9020                                 /* Create it only the first time to be used. */
9021                                 ret = mlx5_flex_parser_ecpri_alloc(dev);
9022                                 if (ret)
9023                                         return rte_flow_error_set
9024                                                 (error, -ret,
9025                                                 RTE_FLOW_ERROR_TYPE_ITEM,
9026                                                 NULL,
9027                                                 "cannot create eCPRI parser");
9028                         }
9029                         /* Adjust the length matcher and device flow value. */
9030                         matcher.mask.size = MLX5_ST_SZ_BYTES(fte_match_param);
9031                         dev_flow->dv.value.size =
9032                                         MLX5_ST_SZ_BYTES(fte_match_param);
9033                         flow_dv_translate_item_ecpri(dev, match_mask,
9034                                                      match_value, items);
9035                         /* No other protocol should follow eCPRI layer. */
9036                         last_item = MLX5_FLOW_LAYER_ECPRI;
9037                         break;
9038                 default:
9039                         break;
9040                 }
9041                 item_flags |= last_item;
9042         }
9043         /*
9044          * When E-Switch mode is enabled, we have two cases where we need to
9045          * set the source port manually.
9046          * The first one, is in case of Nic steering rule, and the second is
9047          * E-Switch rule where no port_id item was found. In both cases
9048          * the source port is set according the current port in use.
9049          */
9050         if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
9051             (priv->representor || priv->master)) {
9052                 if (flow_dv_translate_item_port_id(dev, match_mask,
9053                                                    match_value, NULL))
9054                         return -rte_errno;
9055         }
9056 #ifdef RTE_LIBRTE_MLX5_DEBUG
9057         MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
9058                                               dev_flow->dv.value.buf));
9059 #endif
9060         /*
9061          * Layers may be already initialized from prefix flow if this dev_flow
9062          * is the suffix flow.
9063          */
9064         handle->layers |= item_flags;
9065         if (action_flags & MLX5_FLOW_ACTION_RSS)
9066                 flow_dv_hashfields_set(dev_flow, rss_desc);
9067         /* Register matcher. */
9068         matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
9069                                     matcher.mask.size);
9070         matcher.priority = mlx5_flow_adjust_priority(dev, priority,
9071                                                      matcher.priority);
9072         /* reserved field no needs to be set to 0 here. */
9073         tbl_key.domain = attr->transfer;
9074         tbl_key.direction = attr->egress;
9075         tbl_key.table_id = dev_flow->dv.group;
9076         if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow, error))
9077                 return -rte_errno;
9078         return 0;
9079 }
9080
9081 /**
9082  * Apply the flow to the NIC, lock free,
9083  * (mutex should be acquired by caller).
9084  *
9085  * @param[in] dev
9086  *   Pointer to the Ethernet device structure.
9087  * @param[in, out] flow
9088  *   Pointer to flow structure.
9089  * @param[out] error
9090  *   Pointer to error structure.
9091  *
9092  * @return
9093  *   0 on success, a negative errno value otherwise and rte_errno is set.
9094  */
9095 static int
9096 __flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
9097                 struct rte_flow_error *error)
9098 {
9099         struct mlx5_flow_dv_workspace *dv;
9100         struct mlx5_flow_handle *dh;
9101         struct mlx5_flow_handle_dv *dv_h;
9102         struct mlx5_flow *dev_flow;
9103         struct mlx5_priv *priv = dev->data->dev_private;
9104         uint32_t handle_idx;
9105         int n;
9106         int err;
9107         int idx;
9108
9109         for (idx = priv->flow_idx - 1; idx >= priv->flow_nested_idx; idx--) {
9110                 dev_flow = &((struct mlx5_flow *)priv->inter_flows)[idx];
9111                 dv = &dev_flow->dv;
9112                 dh = dev_flow->handle;
9113                 dv_h = &dh->dvh;
9114                 n = dv->actions_n;
9115                 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
9116                         if (dv->transfer) {
9117                                 dv->actions[n++] = priv->sh->esw_drop_action;
9118                         } else {
9119                                 struct mlx5_hrxq *drop_hrxq;
9120                                 drop_hrxq = mlx5_drop_action_create(dev);
9121                                 if (!drop_hrxq) {
9122                                         rte_flow_error_set
9123                                                 (error, errno,
9124                                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9125                                                  NULL,
9126                                                  "cannot get drop hash queue");
9127                                         goto error;
9128                                 }
9129                                 /*
9130                                  * Drop queues will be released by the specify
9131                                  * mlx5_drop_action_destroy() function. Assign
9132                                  * the special index to hrxq to mark the queue
9133                                  * has been allocated.
9134                                  */
9135                                 dh->rix_hrxq = UINT32_MAX;
9136                                 dv->actions[n++] = drop_hrxq->action;
9137                         }
9138                 } else if (dh->fate_action == MLX5_FLOW_FATE_QUEUE) {
9139                         struct mlx5_hrxq *hrxq;
9140                         uint32_t hrxq_idx;
9141                         struct mlx5_flow_rss_desc *rss_desc =
9142                                 &((struct mlx5_flow_rss_desc *)priv->rss_desc)
9143                                 [!!priv->flow_nested_idx];
9144
9145                         MLX5_ASSERT(rss_desc->queue_num);
9146                         hrxq_idx = mlx5_hrxq_get(dev, rss_desc->key,
9147                                                  MLX5_RSS_HASH_KEY_LEN,
9148                                                  dev_flow->hash_fields,
9149                                                  rss_desc->queue,
9150                                                  rss_desc->queue_num);
9151                         if (!hrxq_idx) {
9152                                 hrxq_idx = mlx5_hrxq_new
9153                                                 (dev, rss_desc->key,
9154                                                  MLX5_RSS_HASH_KEY_LEN,
9155                                                  dev_flow->hash_fields,
9156                                                  rss_desc->queue,
9157                                                  rss_desc->queue_num,
9158                                                  !!(dh->layers &
9159                                                  MLX5_FLOW_LAYER_TUNNEL));
9160                         }
9161                         hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
9162                                               hrxq_idx);
9163                         if (!hrxq) {
9164                                 rte_flow_error_set
9165                                         (error, rte_errno,
9166                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9167                                          "cannot get hash queue");
9168                                 goto error;
9169                         }
9170                         dh->rix_hrxq = hrxq_idx;
9171                         dv->actions[n++] = hrxq->action;
9172                 } else if (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS) {
9173                         if (flow_dv_default_miss_resource_register
9174                                         (dev, error)) {
9175                                 rte_flow_error_set
9176                                         (error, rte_errno,
9177                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9178                                          "cannot create default miss resource");
9179                                 goto error_default_miss;
9180                         }
9181                         dh->rix_default_fate =  MLX5_FLOW_FATE_DEFAULT_MISS;
9182                         dv->actions[n++] = priv->sh->default_miss.action;
9183                 }
9184                 err = mlx5_flow_os_create_flow(dv_h->matcher->matcher_object,
9185                                                (void *)&dv->value, n,
9186                                                dv->actions, &dh->drv_flow);
9187                 if (err) {
9188                         rte_flow_error_set(error, errno,
9189                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9190                                            NULL,
9191                                            "hardware refuses to create flow");
9192                         goto error;
9193                 }
9194                 if (priv->vmwa_context &&
9195                     dh->vf_vlan.tag && !dh->vf_vlan.created) {
9196                         /*
9197                          * The rule contains the VLAN pattern.
9198                          * For VF we are going to create VLAN
9199                          * interface to make hypervisor set correct
9200                          * e-Switch vport context.
9201                          */
9202                         mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
9203                 }
9204         }
9205         return 0;
9206 error:
9207         if (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS)
9208                 flow_dv_default_miss_resource_release(dev);
9209 error_default_miss:
9210         err = rte_errno; /* Save rte_errno before cleanup. */
9211         SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles,
9212                        handle_idx, dh, next) {
9213                 /* hrxq is union, don't clear it if the flag is not set. */
9214                 if (dh->rix_hrxq) {
9215                         if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
9216                                 mlx5_drop_action_destroy(dev);
9217                                 dh->rix_hrxq = 0;
9218                         } else if (dh->fate_action == MLX5_FLOW_FATE_QUEUE) {
9219                                 mlx5_hrxq_release(dev, dh->rix_hrxq);
9220                                 dh->rix_hrxq = 0;
9221                         }
9222                 }
9223                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
9224                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
9225         }
9226         rte_errno = err; /* Restore rte_errno. */
9227         return -rte_errno;
9228 }
9229
9230 /**
9231  * Release the flow matcher.
9232  *
9233  * @param dev
9234  *   Pointer to Ethernet device.
9235  * @param handle
9236  *   Pointer to mlx5_flow_handle.
9237  *
9238  * @return
9239  *   1 while a reference on it exists, 0 when freed.
9240  */
9241 static int
9242 flow_dv_matcher_release(struct rte_eth_dev *dev,
9243                         struct mlx5_flow_handle *handle)
9244 {
9245         struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
9246
9247         MLX5_ASSERT(matcher->matcher_object);
9248         DRV_LOG(DEBUG, "port %u matcher %p: refcnt %d--",
9249                 dev->data->port_id, (void *)matcher,
9250                 rte_atomic32_read(&matcher->refcnt));
9251         if (rte_atomic32_dec_and_test(&matcher->refcnt)) {
9252                 claim_zero(mlx5_flow_os_destroy_flow_matcher
9253                            (matcher->matcher_object));
9254                 LIST_REMOVE(matcher, next);
9255                 /* table ref-- in release interface. */
9256                 flow_dv_tbl_resource_release(dev, matcher->tbl);
9257                 mlx5_free(matcher);
9258                 DRV_LOG(DEBUG, "port %u matcher %p: removed",
9259                         dev->data->port_id, (void *)matcher);
9260                 return 0;
9261         }
9262         return 1;
9263 }
9264
9265 /**
9266  * Release an encap/decap resource.
9267  *
9268  * @param dev
9269  *   Pointer to Ethernet device.
9270  * @param handle
9271  *   Pointer to mlx5_flow_handle.
9272  *
9273  * @return
9274  *   1 while a reference on it exists, 0 when freed.
9275  */
9276 static int
9277 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
9278                                      struct mlx5_flow_handle *handle)
9279 {
9280         struct mlx5_priv *priv = dev->data->dev_private;
9281         uint32_t idx = handle->dvh.rix_encap_decap;
9282         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
9283
9284         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
9285                          idx);
9286         if (!cache_resource)
9287                 return 0;
9288         MLX5_ASSERT(cache_resource->action);
9289         DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d--",
9290                 (void *)cache_resource,
9291                 rte_atomic32_read(&cache_resource->refcnt));
9292         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
9293                 claim_zero(mlx5_flow_os_destroy_flow_action
9294                                                 (cache_resource->action));
9295                 mlx5_hlist_remove(priv->sh->encaps_decaps,
9296                                   &cache_resource->entry);
9297                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);
9298                 DRV_LOG(DEBUG, "encap/decap resource %p: removed",
9299                         (void *)cache_resource);
9300                 return 0;
9301         }
9302         return 1;
9303 }
9304
9305 /**
9306  * Release an jump to table action resource.
9307  *
9308  * @param dev
9309  *   Pointer to Ethernet device.
9310  * @param handle
9311  *   Pointer to mlx5_flow_handle.
9312  *
9313  * @return
9314  *   1 while a reference on it exists, 0 when freed.
9315  */
9316 static int
9317 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
9318                                   struct mlx5_flow_handle *handle)
9319 {
9320         struct mlx5_priv *priv = dev->data->dev_private;
9321         struct mlx5_flow_dv_jump_tbl_resource *cache_resource;
9322         struct mlx5_flow_tbl_data_entry *tbl_data;
9323
9324         tbl_data = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_JUMP],
9325                              handle->rix_jump);
9326         if (!tbl_data)
9327                 return 0;
9328         cache_resource = &tbl_data->jump;
9329         MLX5_ASSERT(cache_resource->action);
9330         DRV_LOG(DEBUG, "jump table resource %p: refcnt %d--",
9331                 (void *)cache_resource,
9332                 rte_atomic32_read(&cache_resource->refcnt));
9333         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
9334                 claim_zero(mlx5_flow_os_destroy_flow_action
9335                                                 (cache_resource->action));
9336                 /* jump action memory free is inside the table release. */
9337                 flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
9338                 DRV_LOG(DEBUG, "jump table resource %p: removed",
9339                         (void *)cache_resource);
9340                 return 0;
9341         }
9342         return 1;
9343 }
9344
9345 /**
9346  * Release a default miss resource.
9347  *
9348  * @param dev
9349  *   Pointer to Ethernet device.
9350  * @return
9351  *   1 while a reference on it exists, 0 when freed.
9352  */
9353 static int
9354 flow_dv_default_miss_resource_release(struct rte_eth_dev *dev)
9355 {
9356         struct mlx5_priv *priv = dev->data->dev_private;
9357         struct mlx5_dev_ctx_shared *sh = priv->sh;
9358         struct mlx5_flow_default_miss_resource *cache_resource =
9359                         &sh->default_miss;
9360
9361         MLX5_ASSERT(cache_resource->action);
9362         DRV_LOG(DEBUG, "default miss resource %p: refcnt %d--",
9363                         (void *)cache_resource->action,
9364                         rte_atomic32_read(&cache_resource->refcnt));
9365         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
9366                 claim_zero(mlx5_glue->destroy_flow_action
9367                                 (cache_resource->action));
9368                 DRV_LOG(DEBUG, "default miss resource %p: removed",
9369                                 (void *)cache_resource->action);
9370                 return 0;
9371         }
9372         return 1;
9373 }
9374
9375 /**
9376  * Release a modify-header resource.
9377  *
9378  * @param dev
9379  *   Pointer to Ethernet device.
9380  * @param handle
9381  *   Pointer to mlx5_flow_handle.
9382  *
9383  * @return
9384  *   1 while a reference on it exists, 0 when freed.
9385  */
9386 static int
9387 flow_dv_modify_hdr_resource_release(struct rte_eth_dev *dev,
9388                                     struct mlx5_flow_handle *handle)
9389 {
9390         struct mlx5_priv *priv = dev->data->dev_private;
9391         struct mlx5_flow_dv_modify_hdr_resource *cache_resource =
9392                                                         handle->dvh.modify_hdr;
9393
9394         MLX5_ASSERT(cache_resource->action);
9395         DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d--",
9396                 (void *)cache_resource,
9397                 rte_atomic32_read(&cache_resource->refcnt));
9398         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
9399                 claim_zero(mlx5_flow_os_destroy_flow_action
9400                                                 (cache_resource->action));
9401                 mlx5_hlist_remove(priv->sh->modify_cmds,
9402                                   &cache_resource->entry);
9403                 mlx5_free(cache_resource);
9404                 DRV_LOG(DEBUG, "modify-header resource %p: removed",
9405                         (void *)cache_resource);
9406                 return 0;
9407         }
9408         return 1;
9409 }
9410
9411 /**
9412  * Release port ID action resource.
9413  *
9414  * @param dev
9415  *   Pointer to Ethernet device.
9416  * @param handle
9417  *   Pointer to mlx5_flow_handle.
9418  *
9419  * @return
9420  *   1 while a reference on it exists, 0 when freed.
9421  */
9422 static int
9423 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
9424                                         struct mlx5_flow_handle *handle)
9425 {
9426         struct mlx5_priv *priv = dev->data->dev_private;
9427         struct mlx5_flow_dv_port_id_action_resource *cache_resource;
9428         uint32_t idx = handle->rix_port_id_action;
9429
9430         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID],
9431                                         idx);
9432         if (!cache_resource)
9433                 return 0;
9434         MLX5_ASSERT(cache_resource->action);
9435         DRV_LOG(DEBUG, "port ID action resource %p: refcnt %d--",
9436                 (void *)cache_resource,
9437                 rte_atomic32_read(&cache_resource->refcnt));
9438         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
9439                 claim_zero(mlx5_flow_os_destroy_flow_action
9440                                                 (cache_resource->action));
9441                 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_PORT_ID],
9442                              &priv->sh->port_id_action_list, idx,
9443                              cache_resource, next);
9444                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_PORT_ID], idx);
9445                 DRV_LOG(DEBUG, "port id action resource %p: removed",
9446                         (void *)cache_resource);
9447                 return 0;
9448         }
9449         return 1;
9450 }
9451
9452 /**
9453  * Release push vlan action resource.
9454  *
9455  * @param dev
9456  *   Pointer to Ethernet device.
9457  * @param handle
9458  *   Pointer to mlx5_flow_handle.
9459  *
9460  * @return
9461  *   1 while a reference on it exists, 0 when freed.
9462  */
9463 static int
9464 flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,
9465                                           struct mlx5_flow_handle *handle)
9466 {
9467         struct mlx5_priv *priv = dev->data->dev_private;
9468         uint32_t idx = handle->dvh.rix_push_vlan;
9469         struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
9470
9471         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN],
9472                                         idx);
9473         if (!cache_resource)
9474                 return 0;
9475         MLX5_ASSERT(cache_resource->action);
9476         DRV_LOG(DEBUG, "push VLAN action resource %p: refcnt %d--",
9477                 (void *)cache_resource,
9478                 rte_atomic32_read(&cache_resource->refcnt));
9479         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
9480                 claim_zero(mlx5_flow_os_destroy_flow_action
9481                                                 (cache_resource->action));
9482                 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN],
9483                              &priv->sh->push_vlan_action_list, idx,
9484                              cache_resource, next);
9485                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
9486                 DRV_LOG(DEBUG, "push vlan action resource %p: removed",
9487                         (void *)cache_resource);
9488                 return 0;
9489         }
9490         return 1;
9491 }
9492
9493 /**
9494  * Release the fate resource.
9495  *
9496  * @param dev
9497  *   Pointer to Ethernet device.
9498  * @param handle
9499  *   Pointer to mlx5_flow_handle.
9500  */
9501 static void
9502 flow_dv_fate_resource_release(struct rte_eth_dev *dev,
9503                                struct mlx5_flow_handle *handle)
9504 {
9505         if (!handle->rix_fate)
9506                 return;
9507         switch (handle->fate_action) {
9508         case MLX5_FLOW_FATE_DROP:
9509                 mlx5_drop_action_destroy(dev);
9510                 break;
9511         case MLX5_FLOW_FATE_QUEUE:
9512                 mlx5_hrxq_release(dev, handle->rix_hrxq);
9513                 break;
9514         case MLX5_FLOW_FATE_JUMP:
9515                 flow_dv_jump_tbl_resource_release(dev, handle);
9516                 break;
9517         case MLX5_FLOW_FATE_PORT_ID:
9518                 flow_dv_port_id_action_resource_release(dev, handle);
9519                 break;
9520         case MLX5_FLOW_FATE_DEFAULT_MISS:
9521                 flow_dv_default_miss_resource_release(dev);
9522                 break;
9523         default:
9524                 DRV_LOG(DEBUG, "Incorrect fate action:%d", handle->fate_action);
9525                 break;
9526         }
9527         handle->rix_fate = 0;
9528 }
9529
9530 /**
9531  * Remove the flow from the NIC but keeps it in memory.
9532  * Lock free, (mutex should be acquired by caller).
9533  *
9534  * @param[in] dev
9535  *   Pointer to Ethernet device.
9536  * @param[in, out] flow
9537  *   Pointer to flow structure.
9538  */
9539 static void
9540 __flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
9541 {
9542         struct mlx5_flow_handle *dh;
9543         uint32_t handle_idx;
9544         struct mlx5_priv *priv = dev->data->dev_private;
9545
9546         if (!flow)
9547                 return;
9548         handle_idx = flow->dev_handles;
9549         while (handle_idx) {
9550                 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
9551                                     handle_idx);
9552                 if (!dh)
9553                         return;
9554                 if (dh->drv_flow) {
9555                         claim_zero(mlx5_flow_os_destroy_flow(dh->drv_flow));
9556                         dh->drv_flow = NULL;
9557                 }
9558                 if (dh->fate_action == MLX5_FLOW_FATE_DROP ||
9559                     dh->fate_action == MLX5_FLOW_FATE_QUEUE ||
9560                     dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS)
9561                         flow_dv_fate_resource_release(dev, dh);
9562                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
9563                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
9564                 handle_idx = dh->next.next;
9565         }
9566 }
9567
9568 /**
9569  * Remove the flow from the NIC and the memory.
9570  * Lock free, (mutex should be acquired by caller).
9571  *
9572  * @param[in] dev
9573  *   Pointer to the Ethernet device structure.
9574  * @param[in, out] flow
9575  *   Pointer to flow structure.
9576  */
9577 static void
9578 __flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
9579 {
9580         struct mlx5_flow_handle *dev_handle;
9581         struct mlx5_priv *priv = dev->data->dev_private;
9582
9583         if (!flow)
9584                 return;
9585         __flow_dv_remove(dev, flow);
9586         if (flow->counter) {
9587                 flow_dv_counter_release(dev, flow->counter);
9588                 flow->counter = 0;
9589         }
9590         if (flow->meter) {
9591                 struct mlx5_flow_meter *fm;
9592
9593                 fm = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MTR],
9594                                     flow->meter);
9595                 if (fm)
9596                         mlx5_flow_meter_detach(fm);
9597                 flow->meter = 0;
9598         }
9599         while (flow->dev_handles) {
9600                 uint32_t tmp_idx = flow->dev_handles;
9601
9602                 dev_handle = mlx5_ipool_get(priv->sh->ipool
9603                                             [MLX5_IPOOL_MLX5_FLOW], tmp_idx);
9604                 if (!dev_handle)
9605                         return;
9606                 flow->dev_handles = dev_handle->next.next;
9607                 if (dev_handle->dvh.matcher)
9608                         flow_dv_matcher_release(dev, dev_handle);
9609                 if (dev_handle->dvh.rix_encap_decap)
9610                         flow_dv_encap_decap_resource_release(dev, dev_handle);
9611                 if (dev_handle->dvh.modify_hdr)
9612                         flow_dv_modify_hdr_resource_release(dev, dev_handle);
9613                 if (dev_handle->dvh.rix_push_vlan)
9614                         flow_dv_push_vlan_action_resource_release(dev,
9615                                                                   dev_handle);
9616                 if (dev_handle->dvh.rix_tag)
9617                         flow_dv_tag_release(dev,
9618                                             dev_handle->dvh.rix_tag);
9619                 flow_dv_fate_resource_release(dev, dev_handle);
9620                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
9621                            tmp_idx);
9622         }
9623 }
9624
9625 /**
9626  * Query a dv flow  rule for its statistics via devx.
9627  *
9628  * @param[in] dev
9629  *   Pointer to Ethernet device.
9630  * @param[in] flow
9631  *   Pointer to the sub flow.
9632  * @param[out] data
9633  *   data retrieved by the query.
9634  * @param[out] error
9635  *   Perform verbose error reporting if not NULL.
9636  *
9637  * @return
9638  *   0 on success, a negative errno value otherwise and rte_errno is set.
9639  */
9640 static int
9641 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
9642                     void *data, struct rte_flow_error *error)
9643 {
9644         struct mlx5_priv *priv = dev->data->dev_private;
9645         struct rte_flow_query_count *qc = data;
9646
9647         if (!priv->config.devx)
9648                 return rte_flow_error_set(error, ENOTSUP,
9649                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9650                                           NULL,
9651                                           "counters are not supported");
9652         if (flow->counter) {
9653                 uint64_t pkts, bytes;
9654                 struct mlx5_flow_counter *cnt;
9655
9656                 cnt = flow_dv_counter_get_by_idx(dev, flow->counter,
9657                                                  NULL);
9658                 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
9659                                                &bytes);
9660
9661                 if (err)
9662                         return rte_flow_error_set(error, -err,
9663                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9664                                         NULL, "cannot read counters");
9665                 qc->hits_set = 1;
9666                 qc->bytes_set = 1;
9667                 qc->hits = pkts - cnt->hits;
9668                 qc->bytes = bytes - cnt->bytes;
9669                 if (qc->reset) {
9670                         cnt->hits = pkts;
9671                         cnt->bytes = bytes;
9672                 }
9673                 return 0;
9674         }
9675         return rte_flow_error_set(error, EINVAL,
9676                                   RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9677                                   NULL,
9678                                   "counters are not available");
9679 }
9680
9681 /**
9682  * Query a flow.
9683  *
9684  * @see rte_flow_query()
9685  * @see rte_flow_ops
9686  */
9687 static int
9688 flow_dv_query(struct rte_eth_dev *dev,
9689               struct rte_flow *flow __rte_unused,
9690               const struct rte_flow_action *actions __rte_unused,
9691               void *data __rte_unused,
9692               struct rte_flow_error *error __rte_unused)
9693 {
9694         int ret = -EINVAL;
9695
9696         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
9697                 switch (actions->type) {
9698                 case RTE_FLOW_ACTION_TYPE_VOID:
9699                         break;
9700                 case RTE_FLOW_ACTION_TYPE_COUNT:
9701                         ret = flow_dv_query_count(dev, flow, data, error);
9702                         break;
9703                 default:
9704                         return rte_flow_error_set(error, ENOTSUP,
9705                                                   RTE_FLOW_ERROR_TYPE_ACTION,
9706                                                   actions,
9707                                                   "action not supported");
9708                 }
9709         }
9710         return ret;
9711 }
9712
9713 /**
9714  * Destroy the meter table set.
9715  * Lock free, (mutex should be acquired by caller).
9716  *
9717  * @param[in] dev
9718  *   Pointer to Ethernet device.
9719  * @param[in] tbl
9720  *   Pointer to the meter table set.
9721  *
9722  * @return
9723  *   Always 0.
9724  */
9725 static int
9726 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
9727                         struct mlx5_meter_domains_infos *tbl)
9728 {
9729         struct mlx5_priv *priv = dev->data->dev_private;
9730         struct mlx5_meter_domains_infos *mtd =
9731                                 (struct mlx5_meter_domains_infos *)tbl;
9732
9733         if (!mtd || !priv->config.dv_flow_en)
9734                 return 0;
9735         if (mtd->ingress.policer_rules[RTE_MTR_DROPPED])
9736                 claim_zero(mlx5_flow_os_destroy_flow
9737                            (mtd->ingress.policer_rules[RTE_MTR_DROPPED]));
9738         if (mtd->egress.policer_rules[RTE_MTR_DROPPED])
9739                 claim_zero(mlx5_flow_os_destroy_flow
9740                            (mtd->egress.policer_rules[RTE_MTR_DROPPED]));
9741         if (mtd->transfer.policer_rules[RTE_MTR_DROPPED])
9742                 claim_zero(mlx5_flow_os_destroy_flow
9743                            (mtd->transfer.policer_rules[RTE_MTR_DROPPED]));
9744         if (mtd->egress.color_matcher)
9745                 claim_zero(mlx5_flow_os_destroy_flow_matcher
9746                            (mtd->egress.color_matcher));
9747         if (mtd->egress.any_matcher)
9748                 claim_zero(mlx5_flow_os_destroy_flow_matcher
9749                            (mtd->egress.any_matcher));
9750         if (mtd->egress.tbl)
9751                 flow_dv_tbl_resource_release(dev, mtd->egress.tbl);
9752         if (mtd->egress.sfx_tbl)
9753                 flow_dv_tbl_resource_release(dev, mtd->egress.sfx_tbl);
9754         if (mtd->ingress.color_matcher)
9755                 claim_zero(mlx5_flow_os_destroy_flow_matcher
9756                            (mtd->ingress.color_matcher));
9757         if (mtd->ingress.any_matcher)
9758                 claim_zero(mlx5_flow_os_destroy_flow_matcher
9759                            (mtd->ingress.any_matcher));
9760         if (mtd->ingress.tbl)
9761                 flow_dv_tbl_resource_release(dev, mtd->ingress.tbl);
9762         if (mtd->ingress.sfx_tbl)
9763                 flow_dv_tbl_resource_release(dev, mtd->ingress.sfx_tbl);
9764         if (mtd->transfer.color_matcher)
9765                 claim_zero(mlx5_flow_os_destroy_flow_matcher
9766                            (mtd->transfer.color_matcher));
9767         if (mtd->transfer.any_matcher)
9768                 claim_zero(mlx5_flow_os_destroy_flow_matcher
9769                            (mtd->transfer.any_matcher));
9770         if (mtd->transfer.tbl)
9771                 flow_dv_tbl_resource_release(dev, mtd->transfer.tbl);
9772         if (mtd->transfer.sfx_tbl)
9773                 flow_dv_tbl_resource_release(dev, mtd->transfer.sfx_tbl);
9774         if (mtd->drop_actn)
9775                 claim_zero(mlx5_flow_os_destroy_flow_action(mtd->drop_actn));
9776         mlx5_free(mtd);
9777         return 0;
9778 }
9779
9780 /* Number of meter flow actions, count and jump or count and drop. */
9781 #define METER_ACTIONS 2
9782
9783 /**
9784  * Create specify domain meter table and suffix table.
9785  *
9786  * @param[in] dev
9787  *   Pointer to Ethernet device.
9788  * @param[in,out] mtb
9789  *   Pointer to DV meter table set.
9790  * @param[in] egress
9791  *   Table attribute.
9792  * @param[in] transfer
9793  *   Table attribute.
9794  * @param[in] color_reg_c_idx
9795  *   Reg C index for color match.
9796  *
9797  * @return
9798  *   0 on success, -1 otherwise and rte_errno is set.
9799  */
9800 static int
9801 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
9802                            struct mlx5_meter_domains_infos *mtb,
9803                            uint8_t egress, uint8_t transfer,
9804                            uint32_t color_reg_c_idx)
9805 {
9806         struct mlx5_priv *priv = dev->data->dev_private;
9807         struct mlx5_dev_ctx_shared *sh = priv->sh;
9808         struct mlx5_flow_dv_match_params mask = {
9809                 .size = sizeof(mask.buf),
9810         };
9811         struct mlx5_flow_dv_match_params value = {
9812                 .size = sizeof(value.buf),
9813         };
9814         struct mlx5dv_flow_matcher_attr dv_attr = {
9815                 .type = IBV_FLOW_ATTR_NORMAL,
9816                 .priority = 0,
9817                 .match_criteria_enable = 0,
9818                 .match_mask = (void *)&mask,
9819         };
9820         void *actions[METER_ACTIONS];
9821         struct mlx5_meter_domain_info *dtb;
9822         struct rte_flow_error error;
9823         int i = 0;
9824         int ret;
9825
9826         if (transfer)
9827                 dtb = &mtb->transfer;
9828         else if (egress)
9829                 dtb = &mtb->egress;
9830         else
9831                 dtb = &mtb->ingress;
9832         /* Create the meter table with METER level. */
9833         dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
9834                                             egress, transfer, &error);
9835         if (!dtb->tbl) {
9836                 DRV_LOG(ERR, "Failed to create meter policer table.");
9837                 return -1;
9838         }
9839         /* Create the meter suffix table with SUFFIX level. */
9840         dtb->sfx_tbl = flow_dv_tbl_resource_get(dev,
9841                                             MLX5_FLOW_TABLE_LEVEL_SUFFIX,
9842                                             egress, transfer, &error);
9843         if (!dtb->sfx_tbl) {
9844                 DRV_LOG(ERR, "Failed to create meter suffix table.");
9845                 return -1;
9846         }
9847         /* Create matchers, Any and Color. */
9848         dv_attr.priority = 3;
9849         dv_attr.match_criteria_enable = 0;
9850         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, dtb->tbl->obj,
9851                                                &dtb->any_matcher);
9852         if (ret) {
9853                 DRV_LOG(ERR, "Failed to create meter"
9854                              " policer default matcher.");
9855                 goto error_exit;
9856         }
9857         dv_attr.priority = 0;
9858         dv_attr.match_criteria_enable =
9859                                 1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
9860         flow_dv_match_meta_reg(mask.buf, value.buf, color_reg_c_idx,
9861                                rte_col_2_mlx5_col(RTE_COLORS), UINT8_MAX);
9862         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, dtb->tbl->obj,
9863                                                &dtb->color_matcher);
9864         if (ret) {
9865                 DRV_LOG(ERR, "Failed to create meter policer color matcher.");
9866                 goto error_exit;
9867         }
9868         if (mtb->count_actns[RTE_MTR_DROPPED])
9869                 actions[i++] = mtb->count_actns[RTE_MTR_DROPPED];
9870         actions[i++] = mtb->drop_actn;
9871         /* Default rule: lowest priority, match any, actions: drop. */
9872         ret = mlx5_flow_os_create_flow(dtb->any_matcher, (void *)&value, i,
9873                                        actions,
9874                                        &dtb->policer_rules[RTE_MTR_DROPPED]);
9875         if (ret) {
9876                 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
9877                 goto error_exit;
9878         }
9879         return 0;
9880 error_exit:
9881         return -1;
9882 }
9883
9884 /**
9885  * Create the needed meter and suffix tables.
9886  * Lock free, (mutex should be acquired by caller).
9887  *
9888  * @param[in] dev
9889  *   Pointer to Ethernet device.
9890  * @param[in] fm
9891  *   Pointer to the flow meter.
9892  *
9893  * @return
9894  *   Pointer to table set on success, NULL otherwise and rte_errno is set.
9895  */
9896 static struct mlx5_meter_domains_infos *
9897 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev,
9898                        const struct mlx5_flow_meter *fm)
9899 {
9900         struct mlx5_priv *priv = dev->data->dev_private;
9901         struct mlx5_meter_domains_infos *mtb;
9902         int ret;
9903         int i;
9904
9905         if (!priv->mtr_en) {
9906                 rte_errno = ENOTSUP;
9907                 return NULL;
9908         }
9909         mtb = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mtb), 0, SOCKET_ID_ANY);
9910         if (!mtb) {
9911                 DRV_LOG(ERR, "Failed to allocate memory for meter.");
9912                 return NULL;
9913         }
9914         /* Create meter count actions */
9915         for (i = 0; i <= RTE_MTR_DROPPED; i++) {
9916                 struct mlx5_flow_counter *cnt;
9917                 if (!fm->policer_stats.cnt[i])
9918                         continue;
9919                 cnt = flow_dv_counter_get_by_idx(dev,
9920                       fm->policer_stats.cnt[i], NULL);
9921                 mtb->count_actns[i] = cnt->action;
9922         }
9923         /* Create drop action. */
9924         ret = mlx5_flow_os_create_flow_action_drop(&mtb->drop_actn);
9925         if (ret) {
9926                 DRV_LOG(ERR, "Failed to create drop action.");
9927                 goto error_exit;
9928         }
9929         /* Egress meter table. */
9930         ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0, priv->mtr_color_reg);
9931         if (ret) {
9932                 DRV_LOG(ERR, "Failed to prepare egress meter table.");
9933                 goto error_exit;
9934         }
9935         /* Ingress meter table. */
9936         ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0, priv->mtr_color_reg);
9937         if (ret) {
9938                 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
9939                 goto error_exit;
9940         }
9941         /* FDB meter table. */
9942         if (priv->config.dv_esw_en) {
9943                 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1,
9944                                                  priv->mtr_color_reg);
9945                 if (ret) {
9946                         DRV_LOG(ERR, "Failed to prepare fdb meter table.");
9947                         goto error_exit;
9948                 }
9949         }
9950         return mtb;
9951 error_exit:
9952         flow_dv_destroy_mtr_tbl(dev, mtb);
9953         return NULL;
9954 }
9955
9956 /**
9957  * Destroy domain policer rule.
9958  *
9959  * @param[in] dt
9960  *   Pointer to domain table.
9961  */
9962 static void
9963 flow_dv_destroy_domain_policer_rule(struct mlx5_meter_domain_info *dt)
9964 {
9965         int i;
9966
9967         for (i = 0; i < RTE_MTR_DROPPED; i++) {
9968                 if (dt->policer_rules[i]) {
9969                         claim_zero(mlx5_flow_os_destroy_flow
9970                                    (dt->policer_rules[i]));
9971                         dt->policer_rules[i] = NULL;
9972                 }
9973         }
9974         if (dt->jump_actn) {
9975                 claim_zero(mlx5_flow_os_destroy_flow_action(dt->jump_actn));
9976                 dt->jump_actn = NULL;
9977         }
9978 }
9979
9980 /**
9981  * Destroy policer rules.
9982  *
9983  * @param[in] dev
9984  *   Pointer to Ethernet device.
9985  * @param[in] fm
9986  *   Pointer to flow meter structure.
9987  * @param[in] attr
9988  *   Pointer to flow attributes.
9989  *
9990  * @return
9991  *   Always 0.
9992  */
9993 static int
9994 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev __rte_unused,
9995                               const struct mlx5_flow_meter *fm,
9996                               const struct rte_flow_attr *attr)
9997 {
9998         struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
9999
10000         if (!mtb)
10001                 return 0;
10002         if (attr->egress)
10003                 flow_dv_destroy_domain_policer_rule(&mtb->egress);
10004         if (attr->ingress)
10005                 flow_dv_destroy_domain_policer_rule(&mtb->ingress);
10006         if (attr->transfer)
10007                 flow_dv_destroy_domain_policer_rule(&mtb->transfer);
10008         return 0;
10009 }
10010
10011 /**
10012  * Create specify domain meter policer rule.
10013  *
10014  * @param[in] fm
10015  *   Pointer to flow meter structure.
10016  * @param[in] mtb
10017  *   Pointer to DV meter table set.
10018  * @param[in] mtr_reg_c
10019  *   Color match REG_C.
10020  *
10021  * @return
10022  *   0 on success, -1 otherwise.
10023  */
10024 static int
10025 flow_dv_create_policer_forward_rule(struct mlx5_flow_meter *fm,
10026                                     struct mlx5_meter_domain_info *dtb,
10027                                     uint8_t mtr_reg_c)
10028 {
10029         struct mlx5_flow_dv_match_params matcher = {
10030                 .size = sizeof(matcher.buf),
10031         };
10032         struct mlx5_flow_dv_match_params value = {
10033                 .size = sizeof(value.buf),
10034         };
10035         struct mlx5_meter_domains_infos *mtb = fm->mfts;
10036         void *actions[METER_ACTIONS];
10037         int i;
10038         int ret = 0;
10039
10040         /* Create jump action. */
10041         if (!dtb->jump_actn)
10042                 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
10043                                 (dtb->sfx_tbl->obj, &dtb->jump_actn);
10044         if (ret) {
10045                 DRV_LOG(ERR, "Failed to create policer jump action.");
10046                 goto error;
10047         }
10048         for (i = 0; i < RTE_MTR_DROPPED; i++) {
10049                 int j = 0;
10050
10051                 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_reg_c,
10052                                        rte_col_2_mlx5_col(i), UINT8_MAX);
10053                 if (mtb->count_actns[i])
10054                         actions[j++] = mtb->count_actns[i];
10055                 if (fm->action[i] == MTR_POLICER_ACTION_DROP)
10056                         actions[j++] = mtb->drop_actn;
10057                 else
10058                         actions[j++] = dtb->jump_actn;
10059                 ret = mlx5_flow_os_create_flow(dtb->color_matcher,
10060                                                (void *)&value, j, actions,
10061                                                &dtb->policer_rules[i]);
10062                 if (ret) {
10063                         DRV_LOG(ERR, "Failed to create policer rule.");
10064                         goto error;
10065                 }
10066         }
10067         return 0;
10068 error:
10069         rte_errno = errno;
10070         return -1;
10071 }
10072
10073 /**
10074  * Create policer rules.
10075  *
10076  * @param[in] dev
10077  *   Pointer to Ethernet device.
10078  * @param[in] fm
10079  *   Pointer to flow meter structure.
10080  * @param[in] attr
10081  *   Pointer to flow attributes.
10082  *
10083  * @return
10084  *   0 on success, -1 otherwise.
10085  */
10086 static int
10087 flow_dv_create_policer_rules(struct rte_eth_dev *dev,
10088                              struct mlx5_flow_meter *fm,
10089                              const struct rte_flow_attr *attr)
10090 {
10091         struct mlx5_priv *priv = dev->data->dev_private;
10092         struct mlx5_meter_domains_infos *mtb = fm->mfts;
10093         int ret;
10094
10095         if (attr->egress) {
10096                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->egress,
10097                                                 priv->mtr_color_reg);
10098                 if (ret) {
10099                         DRV_LOG(ERR, "Failed to create egress policer.");
10100                         goto error;
10101                 }
10102         }
10103         if (attr->ingress) {
10104                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->ingress,
10105                                                 priv->mtr_color_reg);
10106                 if (ret) {
10107                         DRV_LOG(ERR, "Failed to create ingress policer.");
10108                         goto error;
10109                 }
10110         }
10111         if (attr->transfer) {
10112                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->transfer,
10113                                                 priv->mtr_color_reg);
10114                 if (ret) {
10115                         DRV_LOG(ERR, "Failed to create transfer policer.");
10116                         goto error;
10117                 }
10118         }
10119         return 0;
10120 error:
10121         flow_dv_destroy_policer_rules(dev, fm, attr);
10122         return -1;
10123 }
10124
10125 /**
10126  * Query a devx counter.
10127  *
10128  * @param[in] dev
10129  *   Pointer to the Ethernet device structure.
10130  * @param[in] cnt
10131  *   Index to the flow counter.
10132  * @param[in] clear
10133  *   Set to clear the counter statistics.
10134  * @param[out] pkts
10135  *   The statistics value of packets.
10136  * @param[out] bytes
10137  *   The statistics value of bytes.
10138  *
10139  * @return
10140  *   0 on success, otherwise return -1.
10141  */
10142 static int
10143 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
10144                       uint64_t *pkts, uint64_t *bytes)
10145 {
10146         struct mlx5_priv *priv = dev->data->dev_private;
10147         struct mlx5_flow_counter *cnt;
10148         uint64_t inn_pkts, inn_bytes;
10149         int ret;
10150
10151         if (!priv->config.devx)
10152                 return -1;
10153
10154         ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
10155         if (ret)
10156                 return -1;
10157         cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
10158         *pkts = inn_pkts - cnt->hits;
10159         *bytes = inn_bytes - cnt->bytes;
10160         if (clear) {
10161                 cnt->hits = inn_pkts;
10162                 cnt->bytes = inn_bytes;
10163         }
10164         return 0;
10165 }
10166
10167 /**
10168  * Get aged-out flows.
10169  *
10170  * @param[in] dev
10171  *   Pointer to the Ethernet device structure.
10172  * @param[in] context
10173  *   The address of an array of pointers to the aged-out flows contexts.
10174  * @param[in] nb_contexts
10175  *   The length of context array pointers.
10176  * @param[out] error
10177  *   Perform verbose error reporting if not NULL. Initialized in case of
10178  *   error only.
10179  *
10180  * @return
10181  *   how many contexts get in success, otherwise negative errno value.
10182  *   if nb_contexts is 0, return the amount of all aged contexts.
10183  *   if nb_contexts is not 0 , return the amount of aged flows reported
10184  *   in the context array.
10185  * @note: only stub for now
10186  */
10187 static int
10188 flow_get_aged_flows(struct rte_eth_dev *dev,
10189                     void **context,
10190                     uint32_t nb_contexts,
10191                     struct rte_flow_error *error)
10192 {
10193         struct mlx5_priv *priv = dev->data->dev_private;
10194         struct mlx5_age_info *age_info;
10195         struct mlx5_age_param *age_param;
10196         struct mlx5_flow_counter *counter;
10197         int nb_flows = 0;
10198
10199         if (nb_contexts && !context)
10200                 return rte_flow_error_set(error, EINVAL,
10201                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10202                                           NULL,
10203                                           "Should assign at least one flow or"
10204                                           " context to get if nb_contexts != 0");
10205         age_info = GET_PORT_AGE_INFO(priv);
10206         rte_spinlock_lock(&age_info->aged_sl);
10207         TAILQ_FOREACH(counter, &age_info->aged_counters, next) {
10208                 nb_flows++;
10209                 if (nb_contexts) {
10210                         age_param = MLX5_CNT_TO_AGE(counter);
10211                         context[nb_flows - 1] = age_param->context;
10212                         if (!(--nb_contexts))
10213                                 break;
10214                 }
10215         }
10216         rte_spinlock_unlock(&age_info->aged_sl);
10217         MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
10218         return nb_flows;
10219 }
10220
10221 /*
10222  * Mutex-protected thunk to lock-free  __flow_dv_translate().
10223  */
10224 static int
10225 flow_dv_translate(struct rte_eth_dev *dev,
10226                   struct mlx5_flow *dev_flow,
10227                   const struct rte_flow_attr *attr,
10228                   const struct rte_flow_item items[],
10229                   const struct rte_flow_action actions[],
10230                   struct rte_flow_error *error)
10231 {
10232         int ret;
10233
10234         flow_dv_shared_lock(dev);
10235         ret = __flow_dv_translate(dev, dev_flow, attr, items, actions, error);
10236         flow_dv_shared_unlock(dev);
10237         return ret;
10238 }
10239
10240 /*
10241  * Mutex-protected thunk to lock-free  __flow_dv_apply().
10242  */
10243 static int
10244 flow_dv_apply(struct rte_eth_dev *dev,
10245               struct rte_flow *flow,
10246               struct rte_flow_error *error)
10247 {
10248         int ret;
10249
10250         flow_dv_shared_lock(dev);
10251         ret = __flow_dv_apply(dev, flow, error);
10252         flow_dv_shared_unlock(dev);
10253         return ret;
10254 }
10255
10256 /*
10257  * Mutex-protected thunk to lock-free __flow_dv_remove().
10258  */
10259 static void
10260 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
10261 {
10262         flow_dv_shared_lock(dev);
10263         __flow_dv_remove(dev, flow);
10264         flow_dv_shared_unlock(dev);
10265 }
10266
10267 /*
10268  * Mutex-protected thunk to lock-free __flow_dv_destroy().
10269  */
10270 static void
10271 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
10272 {
10273         flow_dv_shared_lock(dev);
10274         __flow_dv_destroy(dev, flow);
10275         flow_dv_shared_unlock(dev);
10276 }
10277
10278 /*
10279  * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
10280  */
10281 static uint32_t
10282 flow_dv_counter_allocate(struct rte_eth_dev *dev)
10283 {
10284         uint32_t cnt;
10285
10286         flow_dv_shared_lock(dev);
10287         cnt = flow_dv_counter_alloc(dev, 0, 0, 1, 0);
10288         flow_dv_shared_unlock(dev);
10289         return cnt;
10290 }
10291
10292 /*
10293  * Mutex-protected thunk to lock-free flow_dv_counter_release().
10294  */
10295 static void
10296 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t cnt)
10297 {
10298         flow_dv_shared_lock(dev);
10299         flow_dv_counter_release(dev, cnt);
10300         flow_dv_shared_unlock(dev);
10301 }
10302
10303 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
10304         .validate = flow_dv_validate,
10305         .prepare = flow_dv_prepare,
10306         .translate = flow_dv_translate,
10307         .apply = flow_dv_apply,
10308         .remove = flow_dv_remove,
10309         .destroy = flow_dv_destroy,
10310         .query = flow_dv_query,
10311         .create_mtr_tbls = flow_dv_create_mtr_tbl,
10312         .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
10313         .create_policer_rules = flow_dv_create_policer_rules,
10314         .destroy_policer_rules = flow_dv_destroy_policer_rules,
10315         .counter_alloc = flow_dv_counter_allocate,
10316         .counter_free = flow_dv_counter_free,
10317         .counter_query = flow_dv_counter_query,
10318         .get_aged_flows = flow_get_aged_flows,
10319 };
10320
10321 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */
10322