1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
11 #include <rte_common.h>
12 #include <rte_ether.h>
13 #include <ethdev_driver.h>
15 #include <rte_flow_driver.h>
16 #include <rte_malloc.h>
17 #include <rte_cycles.h>
20 #include <rte_vxlan.h>
22 #include <rte_eal_paging.h>
25 #include <mlx5_glue.h>
26 #include <mlx5_devx_cmds.h>
28 #include <mlx5_malloc.h>
30 #include "mlx5_defs.h"
32 #include "mlx5_common_os.h"
33 #include "mlx5_flow.h"
34 #include "mlx5_flow_os.h"
37 #include "rte_pmd_mlx5.h"
39 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
41 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
42 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
45 #ifndef HAVE_MLX5DV_DR_ESWITCH
46 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
47 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
51 #ifndef HAVE_MLX5DV_DR
52 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
55 /* VLAN header definitions */
56 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
57 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
58 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
59 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
60 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
75 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
76 struct mlx5_flow_tbl_resource *tbl);
79 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
80 uint32_t encap_decap_idx);
83 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
86 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss);
89 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
93 * Initialize flow attributes structure according to flow items' types.
95 * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
96 * mode. For tunnel mode, the items to be modified are the outermost ones.
99 * Pointer to item specification.
101 * Pointer to flow attributes structure.
102 * @param[in] dev_flow
103 * Pointer to the sub flow.
104 * @param[in] tunnel_decap
105 * Whether action is after tunnel decapsulation.
108 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
109 struct mlx5_flow *dev_flow, bool tunnel_decap)
111 uint64_t layers = dev_flow->handle->layers;
114 * If layers is already initialized, it means this dev_flow is the
115 * suffix flow, the layers flags is set by the prefix flow. Need to
116 * use the layer flags from prefix flow as the suffix flow may not
117 * have the user defined items as the flow is split.
120 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
122 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
124 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
126 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
131 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
132 uint8_t next_protocol = 0xff;
133 switch (item->type) {
134 case RTE_FLOW_ITEM_TYPE_GRE:
135 case RTE_FLOW_ITEM_TYPE_NVGRE:
136 case RTE_FLOW_ITEM_TYPE_VXLAN:
137 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
138 case RTE_FLOW_ITEM_TYPE_GENEVE:
139 case RTE_FLOW_ITEM_TYPE_MPLS:
143 case RTE_FLOW_ITEM_TYPE_IPV4:
146 if (item->mask != NULL &&
147 ((const struct rte_flow_item_ipv4 *)
148 item->mask)->hdr.next_proto_id)
150 ((const struct rte_flow_item_ipv4 *)
151 (item->spec))->hdr.next_proto_id &
152 ((const struct rte_flow_item_ipv4 *)
153 (item->mask))->hdr.next_proto_id;
154 if ((next_protocol == IPPROTO_IPIP ||
155 next_protocol == IPPROTO_IPV6) && tunnel_decap)
158 case RTE_FLOW_ITEM_TYPE_IPV6:
161 if (item->mask != NULL &&
162 ((const struct rte_flow_item_ipv6 *)
163 item->mask)->hdr.proto)
165 ((const struct rte_flow_item_ipv6 *)
166 (item->spec))->hdr.proto &
167 ((const struct rte_flow_item_ipv6 *)
168 (item->mask))->hdr.proto;
169 if ((next_protocol == IPPROTO_IPIP ||
170 next_protocol == IPPROTO_IPV6) && tunnel_decap)
173 case RTE_FLOW_ITEM_TYPE_UDP:
177 case RTE_FLOW_ITEM_TYPE_TCP:
189 * Convert rte_mtr_color to mlx5 color.
198 rte_col_2_mlx5_col(enum rte_color rcol)
201 case RTE_COLOR_GREEN:
202 return MLX5_FLOW_COLOR_GREEN;
203 case RTE_COLOR_YELLOW:
204 return MLX5_FLOW_COLOR_YELLOW;
206 return MLX5_FLOW_COLOR_RED;
210 return MLX5_FLOW_COLOR_UNDEFINED;
213 struct field_modify_info {
214 uint32_t size; /* Size of field in protocol header, in bytes. */
215 uint32_t offset; /* Offset of field in protocol header, in bytes. */
216 enum mlx5_modification_field id;
219 struct field_modify_info modify_eth[] = {
220 {4, 0, MLX5_MODI_OUT_DMAC_47_16},
221 {2, 4, MLX5_MODI_OUT_DMAC_15_0},
222 {4, 6, MLX5_MODI_OUT_SMAC_47_16},
223 {2, 10, MLX5_MODI_OUT_SMAC_15_0},
227 struct field_modify_info modify_vlan_out_first_vid[] = {
228 /* Size in bits !!! */
229 {12, 0, MLX5_MODI_OUT_FIRST_VID},
233 struct field_modify_info modify_ipv4[] = {
234 {1, 1, MLX5_MODI_OUT_IP_DSCP},
235 {1, 8, MLX5_MODI_OUT_IPV4_TTL},
236 {4, 12, MLX5_MODI_OUT_SIPV4},
237 {4, 16, MLX5_MODI_OUT_DIPV4},
241 struct field_modify_info modify_ipv6[] = {
242 {1, 0, MLX5_MODI_OUT_IP_DSCP},
243 {1, 7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
244 {4, 8, MLX5_MODI_OUT_SIPV6_127_96},
245 {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
246 {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
247 {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
248 {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
249 {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
250 {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
251 {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
255 struct field_modify_info modify_udp[] = {
256 {2, 0, MLX5_MODI_OUT_UDP_SPORT},
257 {2, 2, MLX5_MODI_OUT_UDP_DPORT},
261 struct field_modify_info modify_tcp[] = {
262 {2, 0, MLX5_MODI_OUT_TCP_SPORT},
263 {2, 2, MLX5_MODI_OUT_TCP_DPORT},
264 {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
265 {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
270 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
271 uint8_t next_protocol, uint64_t *item_flags,
274 MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
275 item->type == RTE_FLOW_ITEM_TYPE_IPV6);
276 if (next_protocol == IPPROTO_IPIP) {
277 *item_flags |= MLX5_FLOW_LAYER_IPIP;
280 if (next_protocol == IPPROTO_IPV6) {
281 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
286 /* Update VLAN's VID/PCP based on input rte_flow_action.
289 * Pointer to struct rte_flow_action.
291 * Pointer to struct rte_vlan_hdr.
294 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
295 struct rte_vlan_hdr *vlan)
298 if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
300 ((const struct rte_flow_action_of_set_vlan_pcp *)
301 action->conf)->vlan_pcp;
302 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
303 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
304 vlan->vlan_tci |= vlan_tci;
305 } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
306 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
307 vlan->vlan_tci |= rte_be_to_cpu_16
308 (((const struct rte_flow_action_of_set_vlan_vid *)
309 action->conf)->vlan_vid);
314 * Fetch 1, 2, 3 or 4 byte field from the byte array
315 * and return as unsigned integer in host-endian format.
318 * Pointer to data array.
320 * Size of field to extract.
323 * converted field in host endian format.
325 static inline uint32_t
326 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
335 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
338 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
339 ret = (ret << 8) | *(data + sizeof(uint16_t));
342 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
353 * Convert modify-header action to DV specification.
355 * Data length of each action is determined by provided field description
356 * and the item mask. Data bit offset and width of each action is determined
357 * by provided item mask.
360 * Pointer to item specification.
362 * Pointer to field modification information.
363 * For MLX5_MODIFICATION_TYPE_SET specifies destination field.
364 * For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
365 * For MLX5_MODIFICATION_TYPE_COPY specifies source field.
367 * Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
368 * Negative offset value sets the same offset as source offset.
369 * size field is ignored, value is taken from source field.
370 * @param[in,out] resource
371 * Pointer to the modify-header resource.
373 * Type of modification.
375 * Pointer to the error structure.
378 * 0 on success, a negative errno value otherwise and rte_errno is set.
381 flow_dv_convert_modify_action(struct rte_flow_item *item,
382 struct field_modify_info *field,
383 struct field_modify_info *dcopy,
384 struct mlx5_flow_dv_modify_hdr_resource *resource,
385 uint32_t type, struct rte_flow_error *error)
387 uint32_t i = resource->actions_num;
388 struct mlx5_modification_cmd *actions = resource->actions;
391 * The item and mask are provided in big-endian format.
392 * The fields should be presented as in big-endian format either.
393 * Mask must be always present, it defines the actual field width.
395 MLX5_ASSERT(item->mask);
396 MLX5_ASSERT(field->size);
403 if (i >= MLX5_MAX_MODIFY_NUM)
404 return rte_flow_error_set(error, EINVAL,
405 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
406 "too many items to modify");
407 /* Fetch variable byte size mask from the array. */
408 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
409 field->offset, field->size);
414 /* Deduce actual data width in bits from mask value. */
415 off_b = rte_bsf32(mask);
416 size_b = sizeof(uint32_t) * CHAR_BIT -
417 off_b - __builtin_clz(mask);
419 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
420 actions[i] = (struct mlx5_modification_cmd) {
426 /* Convert entire record to expected big-endian format. */
427 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
428 if (type == MLX5_MODIFICATION_TYPE_COPY) {
430 actions[i].dst_field = dcopy->id;
431 actions[i].dst_offset =
432 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
433 /* Convert entire record to big-endian format. */
434 actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
437 MLX5_ASSERT(item->spec);
438 data = flow_dv_fetch_field((const uint8_t *)item->spec +
439 field->offset, field->size);
440 /* Shift out the trailing masked bits from data. */
441 data = (data & mask) >> off_b;
442 actions[i].data1 = rte_cpu_to_be_32(data);
446 } while (field->size);
447 if (resource->actions_num == i)
448 return rte_flow_error_set(error, EINVAL,
449 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
450 "invalid modification flow item");
451 resource->actions_num = i;
456 * Convert modify-header set IPv4 address action to DV specification.
458 * @param[in,out] resource
459 * Pointer to the modify-header resource.
461 * Pointer to action specification.
463 * Pointer to the error structure.
466 * 0 on success, a negative errno value otherwise and rte_errno is set.
469 flow_dv_convert_action_modify_ipv4
470 (struct mlx5_flow_dv_modify_hdr_resource *resource,
471 const struct rte_flow_action *action,
472 struct rte_flow_error *error)
474 const struct rte_flow_action_set_ipv4 *conf =
475 (const struct rte_flow_action_set_ipv4 *)(action->conf);
476 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
477 struct rte_flow_item_ipv4 ipv4;
478 struct rte_flow_item_ipv4 ipv4_mask;
480 memset(&ipv4, 0, sizeof(ipv4));
481 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
482 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
483 ipv4.hdr.src_addr = conf->ipv4_addr;
484 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
486 ipv4.hdr.dst_addr = conf->ipv4_addr;
487 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
490 item.mask = &ipv4_mask;
491 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
492 MLX5_MODIFICATION_TYPE_SET, error);
496 * Convert modify-header set IPv6 address action to DV specification.
498 * @param[in,out] resource
499 * Pointer to the modify-header resource.
501 * Pointer to action specification.
503 * Pointer to the error structure.
506 * 0 on success, a negative errno value otherwise and rte_errno is set.
509 flow_dv_convert_action_modify_ipv6
510 (struct mlx5_flow_dv_modify_hdr_resource *resource,
511 const struct rte_flow_action *action,
512 struct rte_flow_error *error)
514 const struct rte_flow_action_set_ipv6 *conf =
515 (const struct rte_flow_action_set_ipv6 *)(action->conf);
516 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
517 struct rte_flow_item_ipv6 ipv6;
518 struct rte_flow_item_ipv6 ipv6_mask;
520 memset(&ipv6, 0, sizeof(ipv6));
521 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
522 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
523 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
524 sizeof(ipv6.hdr.src_addr));
525 memcpy(&ipv6_mask.hdr.src_addr,
526 &rte_flow_item_ipv6_mask.hdr.src_addr,
527 sizeof(ipv6.hdr.src_addr));
529 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
530 sizeof(ipv6.hdr.dst_addr));
531 memcpy(&ipv6_mask.hdr.dst_addr,
532 &rte_flow_item_ipv6_mask.hdr.dst_addr,
533 sizeof(ipv6.hdr.dst_addr));
536 item.mask = &ipv6_mask;
537 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
538 MLX5_MODIFICATION_TYPE_SET, error);
542 * Convert modify-header set MAC address action to DV specification.
544 * @param[in,out] resource
545 * Pointer to the modify-header resource.
547 * Pointer to action specification.
549 * Pointer to the error structure.
552 * 0 on success, a negative errno value otherwise and rte_errno is set.
555 flow_dv_convert_action_modify_mac
556 (struct mlx5_flow_dv_modify_hdr_resource *resource,
557 const struct rte_flow_action *action,
558 struct rte_flow_error *error)
560 const struct rte_flow_action_set_mac *conf =
561 (const struct rte_flow_action_set_mac *)(action->conf);
562 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
563 struct rte_flow_item_eth eth;
564 struct rte_flow_item_eth eth_mask;
566 memset(ð, 0, sizeof(eth));
567 memset(ð_mask, 0, sizeof(eth_mask));
568 if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
569 memcpy(ð.src.addr_bytes, &conf->mac_addr,
570 sizeof(eth.src.addr_bytes));
571 memcpy(ð_mask.src.addr_bytes,
572 &rte_flow_item_eth_mask.src.addr_bytes,
573 sizeof(eth_mask.src.addr_bytes));
575 memcpy(ð.dst.addr_bytes, &conf->mac_addr,
576 sizeof(eth.dst.addr_bytes));
577 memcpy(ð_mask.dst.addr_bytes,
578 &rte_flow_item_eth_mask.dst.addr_bytes,
579 sizeof(eth_mask.dst.addr_bytes));
582 item.mask = ð_mask;
583 return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
584 MLX5_MODIFICATION_TYPE_SET, error);
588 * Convert modify-header set VLAN VID action to DV specification.
590 * @param[in,out] resource
591 * Pointer to the modify-header resource.
593 * Pointer to action specification.
595 * Pointer to the error structure.
598 * 0 on success, a negative errno value otherwise and rte_errno is set.
601 flow_dv_convert_action_modify_vlan_vid
602 (struct mlx5_flow_dv_modify_hdr_resource *resource,
603 const struct rte_flow_action *action,
604 struct rte_flow_error *error)
606 const struct rte_flow_action_of_set_vlan_vid *conf =
607 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
608 int i = resource->actions_num;
609 struct mlx5_modification_cmd *actions = resource->actions;
610 struct field_modify_info *field = modify_vlan_out_first_vid;
612 if (i >= MLX5_MAX_MODIFY_NUM)
613 return rte_flow_error_set(error, EINVAL,
614 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
615 "too many items to modify");
616 actions[i] = (struct mlx5_modification_cmd) {
617 .action_type = MLX5_MODIFICATION_TYPE_SET,
619 .length = field->size,
620 .offset = field->offset,
622 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
623 actions[i].data1 = conf->vlan_vid;
624 actions[i].data1 = actions[i].data1 << 16;
625 resource->actions_num = ++i;
630 * Convert modify-header set TP action to DV specification.
632 * @param[in,out] resource
633 * Pointer to the modify-header resource.
635 * Pointer to action specification.
637 * Pointer to rte_flow_item objects list.
639 * Pointer to flow attributes structure.
640 * @param[in] dev_flow
641 * Pointer to the sub flow.
642 * @param[in] tunnel_decap
643 * Whether action is after tunnel decapsulation.
645 * Pointer to the error structure.
648 * 0 on success, a negative errno value otherwise and rte_errno is set.
651 flow_dv_convert_action_modify_tp
652 (struct mlx5_flow_dv_modify_hdr_resource *resource,
653 const struct rte_flow_action *action,
654 const struct rte_flow_item *items,
655 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
656 bool tunnel_decap, struct rte_flow_error *error)
658 const struct rte_flow_action_set_tp *conf =
659 (const struct rte_flow_action_set_tp *)(action->conf);
660 struct rte_flow_item item;
661 struct rte_flow_item_udp udp;
662 struct rte_flow_item_udp udp_mask;
663 struct rte_flow_item_tcp tcp;
664 struct rte_flow_item_tcp tcp_mask;
665 struct field_modify_info *field;
668 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
670 memset(&udp, 0, sizeof(udp));
671 memset(&udp_mask, 0, sizeof(udp_mask));
672 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
673 udp.hdr.src_port = conf->port;
674 udp_mask.hdr.src_port =
675 rte_flow_item_udp_mask.hdr.src_port;
677 udp.hdr.dst_port = conf->port;
678 udp_mask.hdr.dst_port =
679 rte_flow_item_udp_mask.hdr.dst_port;
681 item.type = RTE_FLOW_ITEM_TYPE_UDP;
683 item.mask = &udp_mask;
686 MLX5_ASSERT(attr->tcp);
687 memset(&tcp, 0, sizeof(tcp));
688 memset(&tcp_mask, 0, sizeof(tcp_mask));
689 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
690 tcp.hdr.src_port = conf->port;
691 tcp_mask.hdr.src_port =
692 rte_flow_item_tcp_mask.hdr.src_port;
694 tcp.hdr.dst_port = conf->port;
695 tcp_mask.hdr.dst_port =
696 rte_flow_item_tcp_mask.hdr.dst_port;
698 item.type = RTE_FLOW_ITEM_TYPE_TCP;
700 item.mask = &tcp_mask;
703 return flow_dv_convert_modify_action(&item, field, NULL, resource,
704 MLX5_MODIFICATION_TYPE_SET, error);
708 * Convert modify-header set TTL action to DV specification.
710 * @param[in,out] resource
711 * Pointer to the modify-header resource.
713 * Pointer to action specification.
715 * Pointer to rte_flow_item objects list.
717 * Pointer to flow attributes structure.
718 * @param[in] dev_flow
719 * Pointer to the sub flow.
720 * @param[in] tunnel_decap
721 * Whether action is after tunnel decapsulation.
723 * Pointer to the error structure.
726 * 0 on success, a negative errno value otherwise and rte_errno is set.
729 flow_dv_convert_action_modify_ttl
730 (struct mlx5_flow_dv_modify_hdr_resource *resource,
731 const struct rte_flow_action *action,
732 const struct rte_flow_item *items,
733 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
734 bool tunnel_decap, struct rte_flow_error *error)
736 const struct rte_flow_action_set_ttl *conf =
737 (const struct rte_flow_action_set_ttl *)(action->conf);
738 struct rte_flow_item item;
739 struct rte_flow_item_ipv4 ipv4;
740 struct rte_flow_item_ipv4 ipv4_mask;
741 struct rte_flow_item_ipv6 ipv6;
742 struct rte_flow_item_ipv6 ipv6_mask;
743 struct field_modify_info *field;
746 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
748 memset(&ipv4, 0, sizeof(ipv4));
749 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
750 ipv4.hdr.time_to_live = conf->ttl_value;
751 ipv4_mask.hdr.time_to_live = 0xFF;
752 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
754 item.mask = &ipv4_mask;
757 MLX5_ASSERT(attr->ipv6);
758 memset(&ipv6, 0, sizeof(ipv6));
759 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
760 ipv6.hdr.hop_limits = conf->ttl_value;
761 ipv6_mask.hdr.hop_limits = 0xFF;
762 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
764 item.mask = &ipv6_mask;
767 return flow_dv_convert_modify_action(&item, field, NULL, resource,
768 MLX5_MODIFICATION_TYPE_SET, error);
772 * Convert modify-header decrement TTL action to DV specification.
774 * @param[in,out] resource
775 * Pointer to the modify-header resource.
777 * Pointer to action specification.
779 * Pointer to rte_flow_item objects list.
781 * Pointer to flow attributes structure.
782 * @param[in] dev_flow
783 * Pointer to the sub flow.
784 * @param[in] tunnel_decap
785 * Whether action is after tunnel decapsulation.
787 * Pointer to the error structure.
790 * 0 on success, a negative errno value otherwise and rte_errno is set.
793 flow_dv_convert_action_modify_dec_ttl
794 (struct mlx5_flow_dv_modify_hdr_resource *resource,
795 const struct rte_flow_item *items,
796 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
797 bool tunnel_decap, struct rte_flow_error *error)
799 struct rte_flow_item item;
800 struct rte_flow_item_ipv4 ipv4;
801 struct rte_flow_item_ipv4 ipv4_mask;
802 struct rte_flow_item_ipv6 ipv6;
803 struct rte_flow_item_ipv6 ipv6_mask;
804 struct field_modify_info *field;
807 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
809 memset(&ipv4, 0, sizeof(ipv4));
810 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
811 ipv4.hdr.time_to_live = 0xFF;
812 ipv4_mask.hdr.time_to_live = 0xFF;
813 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
815 item.mask = &ipv4_mask;
818 MLX5_ASSERT(attr->ipv6);
819 memset(&ipv6, 0, sizeof(ipv6));
820 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
821 ipv6.hdr.hop_limits = 0xFF;
822 ipv6_mask.hdr.hop_limits = 0xFF;
823 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
825 item.mask = &ipv6_mask;
828 return flow_dv_convert_modify_action(&item, field, NULL, resource,
829 MLX5_MODIFICATION_TYPE_ADD, error);
833 * Convert modify-header increment/decrement TCP Sequence number
834 * to DV specification.
836 * @param[in,out] resource
837 * Pointer to the modify-header resource.
839 * Pointer to action specification.
841 * Pointer to the error structure.
844 * 0 on success, a negative errno value otherwise and rte_errno is set.
847 flow_dv_convert_action_modify_tcp_seq
848 (struct mlx5_flow_dv_modify_hdr_resource *resource,
849 const struct rte_flow_action *action,
850 struct rte_flow_error *error)
852 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
853 uint64_t value = rte_be_to_cpu_32(*conf);
854 struct rte_flow_item item;
855 struct rte_flow_item_tcp tcp;
856 struct rte_flow_item_tcp tcp_mask;
858 memset(&tcp, 0, sizeof(tcp));
859 memset(&tcp_mask, 0, sizeof(tcp_mask));
860 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
862 * The HW has no decrement operation, only increment operation.
863 * To simulate decrement X from Y using increment operation
864 * we need to add UINT32_MAX X times to Y.
865 * Each adding of UINT32_MAX decrements Y by 1.
868 tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
869 tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
870 item.type = RTE_FLOW_ITEM_TYPE_TCP;
872 item.mask = &tcp_mask;
873 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
874 MLX5_MODIFICATION_TYPE_ADD, error);
878 * Convert modify-header increment/decrement TCP Acknowledgment number
879 * to DV specification.
881 * @param[in,out] resource
882 * Pointer to the modify-header resource.
884 * Pointer to action specification.
886 * Pointer to the error structure.
889 * 0 on success, a negative errno value otherwise and rte_errno is set.
892 flow_dv_convert_action_modify_tcp_ack
893 (struct mlx5_flow_dv_modify_hdr_resource *resource,
894 const struct rte_flow_action *action,
895 struct rte_flow_error *error)
897 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
898 uint64_t value = rte_be_to_cpu_32(*conf);
899 struct rte_flow_item item;
900 struct rte_flow_item_tcp tcp;
901 struct rte_flow_item_tcp tcp_mask;
903 memset(&tcp, 0, sizeof(tcp));
904 memset(&tcp_mask, 0, sizeof(tcp_mask));
905 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
907 * The HW has no decrement operation, only increment operation.
908 * To simulate decrement X from Y using increment operation
909 * we need to add UINT32_MAX X times to Y.
910 * Each adding of UINT32_MAX decrements Y by 1.
913 tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
914 tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
915 item.type = RTE_FLOW_ITEM_TYPE_TCP;
917 item.mask = &tcp_mask;
918 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
919 MLX5_MODIFICATION_TYPE_ADD, error);
922 static enum mlx5_modification_field reg_to_field[] = {
923 [REG_NON] = MLX5_MODI_OUT_NONE,
924 [REG_A] = MLX5_MODI_META_DATA_REG_A,
925 [REG_B] = MLX5_MODI_META_DATA_REG_B,
926 [REG_C_0] = MLX5_MODI_META_REG_C_0,
927 [REG_C_1] = MLX5_MODI_META_REG_C_1,
928 [REG_C_2] = MLX5_MODI_META_REG_C_2,
929 [REG_C_3] = MLX5_MODI_META_REG_C_3,
930 [REG_C_4] = MLX5_MODI_META_REG_C_4,
931 [REG_C_5] = MLX5_MODI_META_REG_C_5,
932 [REG_C_6] = MLX5_MODI_META_REG_C_6,
933 [REG_C_7] = MLX5_MODI_META_REG_C_7,
937 * Convert register set to DV specification.
939 * @param[in,out] resource
940 * Pointer to the modify-header resource.
942 * Pointer to action specification.
944 * Pointer to the error structure.
947 * 0 on success, a negative errno value otherwise and rte_errno is set.
950 flow_dv_convert_action_set_reg
951 (struct mlx5_flow_dv_modify_hdr_resource *resource,
952 const struct rte_flow_action *action,
953 struct rte_flow_error *error)
955 const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
956 struct mlx5_modification_cmd *actions = resource->actions;
957 uint32_t i = resource->actions_num;
959 if (i >= MLX5_MAX_MODIFY_NUM)
960 return rte_flow_error_set(error, EINVAL,
961 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
962 "too many items to modify");
963 MLX5_ASSERT(conf->id != REG_NON);
964 MLX5_ASSERT(conf->id < (enum modify_reg)RTE_DIM(reg_to_field));
965 actions[i] = (struct mlx5_modification_cmd) {
966 .action_type = MLX5_MODIFICATION_TYPE_SET,
967 .field = reg_to_field[conf->id],
968 .offset = conf->offset,
969 .length = conf->length,
971 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
972 actions[i].data1 = rte_cpu_to_be_32(conf->data);
974 resource->actions_num = i;
979 * Convert SET_TAG action to DV specification.
982 * Pointer to the rte_eth_dev structure.
983 * @param[in,out] resource
984 * Pointer to the modify-header resource.
986 * Pointer to action specification.
988 * Pointer to the error structure.
991 * 0 on success, a negative errno value otherwise and rte_errno is set.
994 flow_dv_convert_action_set_tag
995 (struct rte_eth_dev *dev,
996 struct mlx5_flow_dv_modify_hdr_resource *resource,
997 const struct rte_flow_action_set_tag *conf,
998 struct rte_flow_error *error)
1000 rte_be32_t data = rte_cpu_to_be_32(conf->data);
1001 rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
1002 struct rte_flow_item item = {
1006 struct field_modify_info reg_c_x[] = {
1009 enum mlx5_modification_field reg_type;
1012 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1015 MLX5_ASSERT(ret != REG_NON);
1016 MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1017 reg_type = reg_to_field[ret];
1018 MLX5_ASSERT(reg_type > 0);
1019 reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1020 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1021 MLX5_MODIFICATION_TYPE_SET, error);
1025 * Convert internal COPY_REG action to DV specification.
1028 * Pointer to the rte_eth_dev structure.
1029 * @param[in,out] res
1030 * Pointer to the modify-header resource.
1032 * Pointer to action specification.
1034 * Pointer to the error structure.
1037 * 0 on success, a negative errno value otherwise and rte_errno is set.
1040 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1041 struct mlx5_flow_dv_modify_hdr_resource *res,
1042 const struct rte_flow_action *action,
1043 struct rte_flow_error *error)
1045 const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1046 rte_be32_t mask = RTE_BE32(UINT32_MAX);
1047 struct rte_flow_item item = {
1051 struct field_modify_info reg_src[] = {
1052 {4, 0, reg_to_field[conf->src]},
1055 struct field_modify_info reg_dst = {
1057 .id = reg_to_field[conf->dst],
1059 /* Adjust reg_c[0] usage according to reported mask. */
1060 if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1061 struct mlx5_priv *priv = dev->data->dev_private;
1062 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1064 MLX5_ASSERT(reg_c0);
1065 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1066 if (conf->dst == REG_C_0) {
1067 /* Copy to reg_c[0], within mask only. */
1068 reg_dst.offset = rte_bsf32(reg_c0);
1070 * Mask is ignoring the enianness, because
1071 * there is no conversion in datapath.
1073 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1074 /* Copy from destination lower bits to reg_c[0]. */
1075 mask = reg_c0 >> reg_dst.offset;
1077 /* Copy from destination upper bits to reg_c[0]. */
1078 mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1079 rte_fls_u32(reg_c0));
1082 mask = rte_cpu_to_be_32(reg_c0);
1083 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1084 /* Copy from reg_c[0] to destination lower bits. */
1087 /* Copy from reg_c[0] to destination upper bits. */
1088 reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1089 (rte_fls_u32(reg_c0) -
1094 return flow_dv_convert_modify_action(&item,
1095 reg_src, ®_dst, res,
1096 MLX5_MODIFICATION_TYPE_COPY,
1101 * Convert MARK action to DV specification. This routine is used
1102 * in extensive metadata only and requires metadata register to be
1103 * handled. In legacy mode hardware tag resource is engaged.
1106 * Pointer to the rte_eth_dev structure.
1108 * Pointer to MARK action specification.
1109 * @param[in,out] resource
1110 * Pointer to the modify-header resource.
1112 * Pointer to the error structure.
1115 * 0 on success, a negative errno value otherwise and rte_errno is set.
1118 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1119 const struct rte_flow_action_mark *conf,
1120 struct mlx5_flow_dv_modify_hdr_resource *resource,
1121 struct rte_flow_error *error)
1123 struct mlx5_priv *priv = dev->data->dev_private;
1124 rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1125 priv->sh->dv_mark_mask);
1126 rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1127 struct rte_flow_item item = {
1131 struct field_modify_info reg_c_x[] = {
1137 return rte_flow_error_set(error, EINVAL,
1138 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1139 NULL, "zero mark action mask");
1140 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1143 MLX5_ASSERT(reg > 0);
1144 if (reg == REG_C_0) {
1145 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1146 uint32_t shl_c0 = rte_bsf32(msk_c0);
1148 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1149 mask = rte_cpu_to_be_32(mask) & msk_c0;
1150 mask = rte_cpu_to_be_32(mask << shl_c0);
1152 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1153 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1154 MLX5_MODIFICATION_TYPE_SET, error);
1158 * Get metadata register index for specified steering domain.
1161 * Pointer to the rte_eth_dev structure.
1163 * Attributes of flow to determine steering domain.
1165 * Pointer to the error structure.
1168 * positive index on success, a negative errno value otherwise
1169 * and rte_errno is set.
1171 static enum modify_reg
1172 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1173 const struct rte_flow_attr *attr,
1174 struct rte_flow_error *error)
1177 mlx5_flow_get_reg_id(dev, attr->transfer ?
1181 MLX5_METADATA_RX, 0, error);
1183 return rte_flow_error_set(error,
1184 ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1185 NULL, "unavailable "
1186 "metadata register");
1191 * Convert SET_META action to DV specification.
1194 * Pointer to the rte_eth_dev structure.
1195 * @param[in,out] resource
1196 * Pointer to the modify-header resource.
1198 * Attributes of flow that includes this item.
1200 * Pointer to action specification.
1202 * Pointer to the error structure.
1205 * 0 on success, a negative errno value otherwise and rte_errno is set.
1208 flow_dv_convert_action_set_meta
1209 (struct rte_eth_dev *dev,
1210 struct mlx5_flow_dv_modify_hdr_resource *resource,
1211 const struct rte_flow_attr *attr,
1212 const struct rte_flow_action_set_meta *conf,
1213 struct rte_flow_error *error)
1215 uint32_t data = conf->data;
1216 uint32_t mask = conf->mask;
1217 struct rte_flow_item item = {
1221 struct field_modify_info reg_c_x[] = {
1224 int reg = flow_dv_get_metadata_reg(dev, attr, error);
1228 MLX5_ASSERT(reg != REG_NON);
1230 * In datapath code there is no endianness
1231 * coversions for perfromance reasons, all
1232 * pattern conversions are done in rte_flow.
1234 if (reg == REG_C_0) {
1235 struct mlx5_priv *priv = dev->data->dev_private;
1236 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1239 MLX5_ASSERT(msk_c0);
1240 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1241 shl_c0 = rte_bsf32(msk_c0);
1243 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1247 MLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1249 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1250 /* The routine expects parameters in memory as big-endian ones. */
1251 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1252 MLX5_MODIFICATION_TYPE_SET, error);
1256 * Convert modify-header set IPv4 DSCP action to DV specification.
1258 * @param[in,out] resource
1259 * Pointer to the modify-header resource.
1261 * Pointer to action specification.
1263 * Pointer to the error structure.
1266 * 0 on success, a negative errno value otherwise and rte_errno is set.
1269 flow_dv_convert_action_modify_ipv4_dscp
1270 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1271 const struct rte_flow_action *action,
1272 struct rte_flow_error *error)
1274 const struct rte_flow_action_set_dscp *conf =
1275 (const struct rte_flow_action_set_dscp *)(action->conf);
1276 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1277 struct rte_flow_item_ipv4 ipv4;
1278 struct rte_flow_item_ipv4 ipv4_mask;
1280 memset(&ipv4, 0, sizeof(ipv4));
1281 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1282 ipv4.hdr.type_of_service = conf->dscp;
1283 ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1285 item.mask = &ipv4_mask;
1286 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1287 MLX5_MODIFICATION_TYPE_SET, error);
1291 * Convert modify-header set IPv6 DSCP action to DV specification.
1293 * @param[in,out] resource
1294 * Pointer to the modify-header resource.
1296 * Pointer to action specification.
1298 * Pointer to the error structure.
1301 * 0 on success, a negative errno value otherwise and rte_errno is set.
1304 flow_dv_convert_action_modify_ipv6_dscp
1305 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1306 const struct rte_flow_action *action,
1307 struct rte_flow_error *error)
1309 const struct rte_flow_action_set_dscp *conf =
1310 (const struct rte_flow_action_set_dscp *)(action->conf);
1311 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1312 struct rte_flow_item_ipv6 ipv6;
1313 struct rte_flow_item_ipv6 ipv6_mask;
1315 memset(&ipv6, 0, sizeof(ipv6));
1316 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1318 * Even though the DSCP bits offset of IPv6 is not byte aligned,
1319 * rdma-core only accept the DSCP bits byte aligned start from
1320 * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1321 * bits in IPv6 case as rdma-core requires byte aligned value.
1323 ipv6.hdr.vtc_flow = conf->dscp;
1324 ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1326 item.mask = &ipv6_mask;
1327 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1328 MLX5_MODIFICATION_TYPE_SET, error);
1332 mlx5_flow_item_field_width(enum rte_flow_field_id field)
1335 case RTE_FLOW_FIELD_START:
1337 case RTE_FLOW_FIELD_MAC_DST:
1338 case RTE_FLOW_FIELD_MAC_SRC:
1340 case RTE_FLOW_FIELD_VLAN_TYPE:
1342 case RTE_FLOW_FIELD_VLAN_ID:
1344 case RTE_FLOW_FIELD_MAC_TYPE:
1346 case RTE_FLOW_FIELD_IPV4_DSCP:
1348 case RTE_FLOW_FIELD_IPV4_TTL:
1350 case RTE_FLOW_FIELD_IPV4_SRC:
1351 case RTE_FLOW_FIELD_IPV4_DST:
1353 case RTE_FLOW_FIELD_IPV6_DSCP:
1355 case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
1357 case RTE_FLOW_FIELD_IPV6_SRC:
1358 case RTE_FLOW_FIELD_IPV6_DST:
1360 case RTE_FLOW_FIELD_TCP_PORT_SRC:
1361 case RTE_FLOW_FIELD_TCP_PORT_DST:
1363 case RTE_FLOW_FIELD_TCP_SEQ_NUM:
1364 case RTE_FLOW_FIELD_TCP_ACK_NUM:
1366 case RTE_FLOW_FIELD_TCP_FLAGS:
1368 case RTE_FLOW_FIELD_UDP_PORT_SRC:
1369 case RTE_FLOW_FIELD_UDP_PORT_DST:
1371 case RTE_FLOW_FIELD_VXLAN_VNI:
1372 case RTE_FLOW_FIELD_GENEVE_VNI:
1374 case RTE_FLOW_FIELD_GTP_TEID:
1375 case RTE_FLOW_FIELD_TAG:
1377 case RTE_FLOW_FIELD_MARK:
1379 case RTE_FLOW_FIELD_META:
1381 case RTE_FLOW_FIELD_POINTER:
1382 case RTE_FLOW_FIELD_VALUE:
1391 mlx5_flow_field_id_to_modify_info
1392 (const struct rte_flow_action_modify_data *data,
1393 struct field_modify_info *info,
1394 uint32_t *mask, uint32_t *value,
1395 uint32_t width, uint32_t dst_width,
1396 struct rte_eth_dev *dev,
1397 const struct rte_flow_attr *attr,
1398 struct rte_flow_error *error)
1402 switch (data->field) {
1403 case RTE_FLOW_FIELD_START:
1404 /* not supported yet */
1407 case RTE_FLOW_FIELD_MAC_DST:
1409 if (data->offset < 32) {
1410 info[idx] = (struct field_modify_info){4, 0,
1411 MLX5_MODI_OUT_DMAC_47_16};
1414 rte_cpu_to_be_32(0xffffffff >>
1418 mask[idx] = RTE_BE32(0xffffffff);
1425 info[idx] = (struct field_modify_info){2, 4 * idx,
1426 MLX5_MODI_OUT_DMAC_15_0};
1427 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1429 if (data->offset < 32)
1430 info[idx++] = (struct field_modify_info){4, 0,
1431 MLX5_MODI_OUT_DMAC_47_16};
1432 info[idx] = (struct field_modify_info){2, 0,
1433 MLX5_MODI_OUT_DMAC_15_0};
1436 case RTE_FLOW_FIELD_MAC_SRC:
1438 if (data->offset < 32) {
1439 info[idx] = (struct field_modify_info){4, 0,
1440 MLX5_MODI_OUT_SMAC_47_16};
1443 rte_cpu_to_be_32(0xffffffff >>
1447 mask[idx] = RTE_BE32(0xffffffff);
1454 info[idx] = (struct field_modify_info){2, 4 * idx,
1455 MLX5_MODI_OUT_SMAC_15_0};
1456 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1458 if (data->offset < 32)
1459 info[idx++] = (struct field_modify_info){4, 0,
1460 MLX5_MODI_OUT_SMAC_47_16};
1461 info[idx] = (struct field_modify_info){2, 0,
1462 MLX5_MODI_OUT_SMAC_15_0};
1465 case RTE_FLOW_FIELD_VLAN_TYPE:
1466 /* not supported yet */
1468 case RTE_FLOW_FIELD_VLAN_ID:
1469 info[idx] = (struct field_modify_info){2, 0,
1470 MLX5_MODI_OUT_FIRST_VID};
1472 mask[idx] = rte_cpu_to_be_16(0x0fff >> (12 - width));
1474 case RTE_FLOW_FIELD_MAC_TYPE:
1475 info[idx] = (struct field_modify_info){2, 0,
1476 MLX5_MODI_OUT_ETHERTYPE};
1478 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1480 case RTE_FLOW_FIELD_IPV4_DSCP:
1481 info[idx] = (struct field_modify_info){1, 0,
1482 MLX5_MODI_OUT_IP_DSCP};
1484 mask[idx] = 0x3f >> (6 - width);
1486 case RTE_FLOW_FIELD_IPV4_TTL:
1487 info[idx] = (struct field_modify_info){1, 0,
1488 MLX5_MODI_OUT_IPV4_TTL};
1490 mask[idx] = 0xff >> (8 - width);
1492 case RTE_FLOW_FIELD_IPV4_SRC:
1493 info[idx] = (struct field_modify_info){4, 0,
1494 MLX5_MODI_OUT_SIPV4};
1496 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1499 case RTE_FLOW_FIELD_IPV4_DST:
1500 info[idx] = (struct field_modify_info){4, 0,
1501 MLX5_MODI_OUT_DIPV4};
1503 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1506 case RTE_FLOW_FIELD_IPV6_DSCP:
1507 info[idx] = (struct field_modify_info){1, 0,
1508 MLX5_MODI_OUT_IP_DSCP};
1510 mask[idx] = 0x3f >> (6 - width);
1512 case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
1513 info[idx] = (struct field_modify_info){1, 0,
1514 MLX5_MODI_OUT_IPV6_HOPLIMIT};
1516 mask[idx] = 0xff >> (8 - width);
1518 case RTE_FLOW_FIELD_IPV6_SRC:
1520 if (data->offset < 32) {
1521 info[idx] = (struct field_modify_info){4,
1523 MLX5_MODI_OUT_SIPV6_31_0};
1526 rte_cpu_to_be_32(0xffffffff >>
1530 mask[idx] = RTE_BE32(0xffffffff);
1537 if (data->offset < 64) {
1538 info[idx] = (struct field_modify_info){4,
1540 MLX5_MODI_OUT_SIPV6_63_32};
1543 rte_cpu_to_be_32(0xffffffff >>
1547 mask[idx] = RTE_BE32(0xffffffff);
1554 if (data->offset < 96) {
1555 info[idx] = (struct field_modify_info){4,
1557 MLX5_MODI_OUT_SIPV6_95_64};
1560 rte_cpu_to_be_32(0xffffffff >>
1564 mask[idx] = RTE_BE32(0xffffffff);
1571 info[idx] = (struct field_modify_info){4, 4 * idx,
1572 MLX5_MODI_OUT_SIPV6_127_96};
1573 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1576 if (data->offset < 32)
1577 info[idx++] = (struct field_modify_info){4, 0,
1578 MLX5_MODI_OUT_SIPV6_31_0};
1579 if (data->offset < 64)
1580 info[idx++] = (struct field_modify_info){4, 0,
1581 MLX5_MODI_OUT_SIPV6_63_32};
1582 if (data->offset < 96)
1583 info[idx++] = (struct field_modify_info){4, 0,
1584 MLX5_MODI_OUT_SIPV6_95_64};
1585 if (data->offset < 128)
1586 info[idx++] = (struct field_modify_info){4, 0,
1587 MLX5_MODI_OUT_SIPV6_127_96};
1590 case RTE_FLOW_FIELD_IPV6_DST:
1592 if (data->offset < 32) {
1593 info[idx] = (struct field_modify_info){4,
1595 MLX5_MODI_OUT_DIPV6_31_0};
1598 rte_cpu_to_be_32(0xffffffff >>
1602 mask[idx] = RTE_BE32(0xffffffff);
1609 if (data->offset < 64) {
1610 info[idx] = (struct field_modify_info){4,
1612 MLX5_MODI_OUT_DIPV6_63_32};
1615 rte_cpu_to_be_32(0xffffffff >>
1619 mask[idx] = RTE_BE32(0xffffffff);
1626 if (data->offset < 96) {
1627 info[idx] = (struct field_modify_info){4,
1629 MLX5_MODI_OUT_DIPV6_95_64};
1632 rte_cpu_to_be_32(0xffffffff >>
1636 mask[idx] = RTE_BE32(0xffffffff);
1643 info[idx] = (struct field_modify_info){4, 4 * idx,
1644 MLX5_MODI_OUT_DIPV6_127_96};
1645 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1648 if (data->offset < 32)
1649 info[idx++] = (struct field_modify_info){4, 0,
1650 MLX5_MODI_OUT_DIPV6_31_0};
1651 if (data->offset < 64)
1652 info[idx++] = (struct field_modify_info){4, 0,
1653 MLX5_MODI_OUT_DIPV6_63_32};
1654 if (data->offset < 96)
1655 info[idx++] = (struct field_modify_info){4, 0,
1656 MLX5_MODI_OUT_DIPV6_95_64};
1657 if (data->offset < 128)
1658 info[idx++] = (struct field_modify_info){4, 0,
1659 MLX5_MODI_OUT_DIPV6_127_96};
1662 case RTE_FLOW_FIELD_TCP_PORT_SRC:
1663 info[idx] = (struct field_modify_info){2, 0,
1664 MLX5_MODI_OUT_TCP_SPORT};
1666 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1668 case RTE_FLOW_FIELD_TCP_PORT_DST:
1669 info[idx] = (struct field_modify_info){2, 0,
1670 MLX5_MODI_OUT_TCP_DPORT};
1672 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1674 case RTE_FLOW_FIELD_TCP_SEQ_NUM:
1675 info[idx] = (struct field_modify_info){4, 0,
1676 MLX5_MODI_OUT_TCP_SEQ_NUM};
1678 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1681 case RTE_FLOW_FIELD_TCP_ACK_NUM:
1682 info[idx] = (struct field_modify_info){4, 0,
1683 MLX5_MODI_OUT_TCP_ACK_NUM};
1685 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1688 case RTE_FLOW_FIELD_TCP_FLAGS:
1689 info[idx] = (struct field_modify_info){1, 0,
1690 MLX5_MODI_OUT_TCP_FLAGS};
1692 mask[idx] = 0x3f >> (6 - width);
1694 case RTE_FLOW_FIELD_UDP_PORT_SRC:
1695 info[idx] = (struct field_modify_info){2, 0,
1696 MLX5_MODI_OUT_UDP_SPORT};
1698 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1700 case RTE_FLOW_FIELD_UDP_PORT_DST:
1701 info[idx] = (struct field_modify_info){2, 0,
1702 MLX5_MODI_OUT_UDP_DPORT};
1704 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1706 case RTE_FLOW_FIELD_VXLAN_VNI:
1707 /* not supported yet */
1709 case RTE_FLOW_FIELD_GENEVE_VNI:
1710 /* not supported yet*/
1712 case RTE_FLOW_FIELD_GTP_TEID:
1713 info[idx] = (struct field_modify_info){4, 0,
1714 MLX5_MODI_GTP_TEID};
1716 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1719 case RTE_FLOW_FIELD_TAG:
1721 int reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG,
1722 data->level, error);
1725 MLX5_ASSERT(reg != REG_NON);
1726 MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1727 info[idx] = (struct field_modify_info){4, 0,
1731 rte_cpu_to_be_32(0xffffffff >>
1735 case RTE_FLOW_FIELD_MARK:
1737 int reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK,
1741 MLX5_ASSERT(reg != REG_NON);
1742 MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1743 info[idx] = (struct field_modify_info){4, 0,
1747 rte_cpu_to_be_32(0xffffffff >>
1751 case RTE_FLOW_FIELD_META:
1753 int reg = flow_dv_get_metadata_reg(dev, attr, error);
1756 MLX5_ASSERT(reg != REG_NON);
1757 MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1758 info[idx] = (struct field_modify_info){4, 0,
1762 rte_cpu_to_be_32(0xffffffff >>
1766 case RTE_FLOW_FIELD_POINTER:
1767 case RTE_FLOW_FIELD_VALUE:
1768 if (data->field == RTE_FLOW_FIELD_POINTER)
1769 memcpy(&val, (void *)(uintptr_t)data->value,
1773 for (idx = 0; idx < MLX5_ACT_MAX_MOD_FIELDS; idx++) {
1775 if (dst_width > 16) {
1776 value[idx] = rte_cpu_to_be_32(val);
1778 } else if (dst_width > 8) {
1779 value[idx] = rte_cpu_to_be_16(val);
1782 value[idx] = (uint8_t)val;
1797 * Convert modify_field action to DV specification.
1800 * Pointer to the rte_eth_dev structure.
1801 * @param[in,out] resource
1802 * Pointer to the modify-header resource.
1804 * Pointer to action specification.
1806 * Attributes of flow that includes this item.
1808 * Pointer to the error structure.
1811 * 0 on success, a negative errno value otherwise and rte_errno is set.
1814 flow_dv_convert_action_modify_field
1815 (struct rte_eth_dev *dev,
1816 struct mlx5_flow_dv_modify_hdr_resource *resource,
1817 const struct rte_flow_action *action,
1818 const struct rte_flow_attr *attr,
1819 struct rte_flow_error *error)
1821 const struct rte_flow_action_modify_field *conf =
1822 (const struct rte_flow_action_modify_field *)(action->conf);
1823 struct rte_flow_item item;
1824 struct field_modify_info field[MLX5_ACT_MAX_MOD_FIELDS] = {
1826 struct field_modify_info dcopy[MLX5_ACT_MAX_MOD_FIELDS] = {
1828 uint32_t mask[MLX5_ACT_MAX_MOD_FIELDS] = {0, 0, 0, 0, 0};
1829 uint32_t value[MLX5_ACT_MAX_MOD_FIELDS] = {0, 0, 0, 0, 0};
1831 uint32_t dst_width = mlx5_flow_item_field_width(conf->dst.field);
1833 if (conf->src.field == RTE_FLOW_FIELD_POINTER ||
1834 conf->src.field == RTE_FLOW_FIELD_VALUE) {
1835 type = MLX5_MODIFICATION_TYPE_SET;
1836 /** For SET fill the destination field (field) first. */
1837 mlx5_flow_field_id_to_modify_info(&conf->dst, field, mask,
1838 value, conf->width, dst_width, dev, attr, error);
1839 /** Then copy immediate value from source as per mask. */
1840 mlx5_flow_field_id_to_modify_info(&conf->src, dcopy, mask,
1841 value, conf->width, dst_width, dev, attr, error);
1844 type = MLX5_MODIFICATION_TYPE_COPY;
1845 /** For COPY fill the destination field (dcopy) without mask. */
1846 mlx5_flow_field_id_to_modify_info(&conf->dst, dcopy, NULL,
1847 value, conf->width, dst_width, dev, attr, error);
1848 /** Then construct the source field (field) with mask. */
1849 mlx5_flow_field_id_to_modify_info(&conf->src, field, mask,
1850 value, conf->width, dst_width, dev, attr, error);
1853 return flow_dv_convert_modify_action(&item,
1854 field, dcopy, resource, type, error);
1858 * Validate MARK item.
1861 * Pointer to the rte_eth_dev structure.
1863 * Item specification.
1865 * Attributes of flow that includes this item.
1867 * Pointer to error structure.
1870 * 0 on success, a negative errno value otherwise and rte_errno is set.
1873 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1874 const struct rte_flow_item *item,
1875 const struct rte_flow_attr *attr __rte_unused,
1876 struct rte_flow_error *error)
1878 struct mlx5_priv *priv = dev->data->dev_private;
1879 struct mlx5_dev_config *config = &priv->config;
1880 const struct rte_flow_item_mark *spec = item->spec;
1881 const struct rte_flow_item_mark *mask = item->mask;
1882 const struct rte_flow_item_mark nic_mask = {
1883 .id = priv->sh->dv_mark_mask,
1887 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1888 return rte_flow_error_set(error, ENOTSUP,
1889 RTE_FLOW_ERROR_TYPE_ITEM, item,
1890 "extended metadata feature"
1892 if (!mlx5_flow_ext_mreg_supported(dev))
1893 return rte_flow_error_set(error, ENOTSUP,
1894 RTE_FLOW_ERROR_TYPE_ITEM, item,
1895 "extended metadata register"
1896 " isn't supported");
1898 return rte_flow_error_set(error, ENOTSUP,
1899 RTE_FLOW_ERROR_TYPE_ITEM, item,
1900 "extended metadata register"
1901 " isn't available");
1902 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1906 return rte_flow_error_set(error, EINVAL,
1907 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1909 "data cannot be empty");
1910 if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1911 return rte_flow_error_set(error, EINVAL,
1912 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1914 "mark id exceeds the limit");
1918 return rte_flow_error_set(error, EINVAL,
1919 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1920 "mask cannot be zero");
1922 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1923 (const uint8_t *)&nic_mask,
1924 sizeof(struct rte_flow_item_mark),
1925 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1932 * Validate META item.
1935 * Pointer to the rte_eth_dev structure.
1937 * Item specification.
1939 * Attributes of flow that includes this item.
1941 * Pointer to error structure.
1944 * 0 on success, a negative errno value otherwise and rte_errno is set.
1947 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1948 const struct rte_flow_item *item,
1949 const struct rte_flow_attr *attr,
1950 struct rte_flow_error *error)
1952 struct mlx5_priv *priv = dev->data->dev_private;
1953 struct mlx5_dev_config *config = &priv->config;
1954 const struct rte_flow_item_meta *spec = item->spec;
1955 const struct rte_flow_item_meta *mask = item->mask;
1956 struct rte_flow_item_meta nic_mask = {
1963 return rte_flow_error_set(error, EINVAL,
1964 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1966 "data cannot be empty");
1967 if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1968 if (!mlx5_flow_ext_mreg_supported(dev))
1969 return rte_flow_error_set(error, ENOTSUP,
1970 RTE_FLOW_ERROR_TYPE_ITEM, item,
1971 "extended metadata register"
1972 " isn't supported");
1973 reg = flow_dv_get_metadata_reg(dev, attr, error);
1977 return rte_flow_error_set(error, ENOTSUP,
1978 RTE_FLOW_ERROR_TYPE_ITEM, item,
1979 "unavalable extended metadata register");
1981 return rte_flow_error_set(error, ENOTSUP,
1982 RTE_FLOW_ERROR_TYPE_ITEM, item,
1986 nic_mask.data = priv->sh->dv_meta_mask;
1989 return rte_flow_error_set(error, ENOTSUP,
1990 RTE_FLOW_ERROR_TYPE_ITEM, item,
1991 "extended metadata feature "
1992 "should be enabled when "
1993 "meta item is requested "
1994 "with e-switch mode ");
1996 return rte_flow_error_set(error, ENOTSUP,
1997 RTE_FLOW_ERROR_TYPE_ITEM, item,
1998 "match on metadata for ingress "
1999 "is not supported in legacy "
2003 mask = &rte_flow_item_meta_mask;
2005 return rte_flow_error_set(error, EINVAL,
2006 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2007 "mask cannot be zero");
2009 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2010 (const uint8_t *)&nic_mask,
2011 sizeof(struct rte_flow_item_meta),
2012 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2017 * Validate TAG item.
2020 * Pointer to the rte_eth_dev structure.
2022 * Item specification.
2024 * Attributes of flow that includes this item.
2026 * Pointer to error structure.
2029 * 0 on success, a negative errno value otherwise and rte_errno is set.
2032 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
2033 const struct rte_flow_item *item,
2034 const struct rte_flow_attr *attr __rte_unused,
2035 struct rte_flow_error *error)
2037 const struct rte_flow_item_tag *spec = item->spec;
2038 const struct rte_flow_item_tag *mask = item->mask;
2039 const struct rte_flow_item_tag nic_mask = {
2040 .data = RTE_BE32(UINT32_MAX),
2045 if (!mlx5_flow_ext_mreg_supported(dev))
2046 return rte_flow_error_set(error, ENOTSUP,
2047 RTE_FLOW_ERROR_TYPE_ITEM, item,
2048 "extensive metadata register"
2049 " isn't supported");
2051 return rte_flow_error_set(error, EINVAL,
2052 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
2054 "data cannot be empty");
2056 mask = &rte_flow_item_tag_mask;
2058 return rte_flow_error_set(error, EINVAL,
2059 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2060 "mask cannot be zero");
2062 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2063 (const uint8_t *)&nic_mask,
2064 sizeof(struct rte_flow_item_tag),
2065 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2068 if (mask->index != 0xff)
2069 return rte_flow_error_set(error, EINVAL,
2070 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2071 "partial mask for tag index"
2072 " is not supported");
2073 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
2076 MLX5_ASSERT(ret != REG_NON);
2081 * Validate vport item.
2084 * Pointer to the rte_eth_dev structure.
2086 * Item specification.
2088 * Attributes of flow that includes this item.
2089 * @param[in] item_flags
2090 * Bit-fields that holds the items detected until now.
2092 * Pointer to error structure.
2095 * 0 on success, a negative errno value otherwise and rte_errno is set.
2098 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
2099 const struct rte_flow_item *item,
2100 const struct rte_flow_attr *attr,
2101 uint64_t item_flags,
2102 struct rte_flow_error *error)
2104 const struct rte_flow_item_port_id *spec = item->spec;
2105 const struct rte_flow_item_port_id *mask = item->mask;
2106 const struct rte_flow_item_port_id switch_mask = {
2109 struct mlx5_priv *esw_priv;
2110 struct mlx5_priv *dev_priv;
2113 if (!attr->transfer)
2114 return rte_flow_error_set(error, EINVAL,
2115 RTE_FLOW_ERROR_TYPE_ITEM,
2117 "match on port id is valid only"
2118 " when transfer flag is enabled");
2119 if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
2120 return rte_flow_error_set(error, ENOTSUP,
2121 RTE_FLOW_ERROR_TYPE_ITEM, item,
2122 "multiple source ports are not"
2125 mask = &switch_mask;
2126 if (mask->id != 0xffffffff)
2127 return rte_flow_error_set(error, ENOTSUP,
2128 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2130 "no support for partial mask on"
2132 ret = mlx5_flow_item_acceptable
2133 (item, (const uint8_t *)mask,
2134 (const uint8_t *)&rte_flow_item_port_id_mask,
2135 sizeof(struct rte_flow_item_port_id),
2136 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2141 esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
2143 return rte_flow_error_set(error, rte_errno,
2144 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
2145 "failed to obtain E-Switch info for"
2147 dev_priv = mlx5_dev_to_eswitch_info(dev);
2149 return rte_flow_error_set(error, rte_errno,
2150 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2152 "failed to obtain E-Switch info");
2153 if (esw_priv->domain_id != dev_priv->domain_id)
2154 return rte_flow_error_set(error, EINVAL,
2155 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
2156 "cannot match on a port from a"
2157 " different E-Switch");
2162 * Validate VLAN item.
2165 * Item specification.
2166 * @param[in] item_flags
2167 * Bit-fields that holds the items detected until now.
2169 * Ethernet device flow is being created on.
2171 * Pointer to error structure.
2174 * 0 on success, a negative errno value otherwise and rte_errno is set.
2177 flow_dv_validate_item_vlan(const struct rte_flow_item *item,
2178 uint64_t item_flags,
2179 struct rte_eth_dev *dev,
2180 struct rte_flow_error *error)
2182 const struct rte_flow_item_vlan *mask = item->mask;
2183 const struct rte_flow_item_vlan nic_mask = {
2184 .tci = RTE_BE16(UINT16_MAX),
2185 .inner_type = RTE_BE16(UINT16_MAX),
2188 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2190 const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 |
2191 MLX5_FLOW_LAYER_INNER_L4) :
2192 (MLX5_FLOW_LAYER_OUTER_L3 |
2193 MLX5_FLOW_LAYER_OUTER_L4);
2194 const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
2195 MLX5_FLOW_LAYER_OUTER_VLAN;
2197 if (item_flags & vlanm)
2198 return rte_flow_error_set(error, EINVAL,
2199 RTE_FLOW_ERROR_TYPE_ITEM, item,
2200 "multiple VLAN layers not supported");
2201 else if ((item_flags & l34m) != 0)
2202 return rte_flow_error_set(error, EINVAL,
2203 RTE_FLOW_ERROR_TYPE_ITEM, item,
2204 "VLAN cannot follow L3/L4 layer");
2206 mask = &rte_flow_item_vlan_mask;
2207 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2208 (const uint8_t *)&nic_mask,
2209 sizeof(struct rte_flow_item_vlan),
2210 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2213 if (!tunnel && mask->tci != RTE_BE16(0x0fff)) {
2214 struct mlx5_priv *priv = dev->data->dev_private;
2216 if (priv->vmwa_context) {
2218 * Non-NULL context means we have a virtual machine
2219 * and SR-IOV enabled, we have to create VLAN interface
2220 * to make hypervisor to setup E-Switch vport
2221 * context correctly. We avoid creating the multiple
2222 * VLAN interfaces, so we cannot support VLAN tag mask.
2224 return rte_flow_error_set(error, EINVAL,
2225 RTE_FLOW_ERROR_TYPE_ITEM,
2227 "VLAN tag mask is not"
2228 " supported in virtual"
2236 * GTP flags are contained in 1 byte of the format:
2237 * -------------------------------------------
2238 * | bit | 0 - 2 | 3 | 4 | 5 | 6 | 7 |
2239 * |-----------------------------------------|
2240 * | value | Version | PT | Res | E | S | PN |
2241 * -------------------------------------------
2243 * Matching is supported only for GTP flags E, S, PN.
2245 #define MLX5_GTP_FLAGS_MASK 0x07
2248 * Validate GTP item.
2251 * Pointer to the rte_eth_dev structure.
2253 * Item specification.
2254 * @param[in] item_flags
2255 * Bit-fields that holds the items detected until now.
2257 * Pointer to error structure.
2260 * 0 on success, a negative errno value otherwise and rte_errno is set.
2263 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
2264 const struct rte_flow_item *item,
2265 uint64_t item_flags,
2266 struct rte_flow_error *error)
2268 struct mlx5_priv *priv = dev->data->dev_private;
2269 const struct rte_flow_item_gtp *spec = item->spec;
2270 const struct rte_flow_item_gtp *mask = item->mask;
2271 const struct rte_flow_item_gtp nic_mask = {
2272 .v_pt_rsv_flags = MLX5_GTP_FLAGS_MASK,
2274 .teid = RTE_BE32(0xffffffff),
2277 if (!priv->config.hca_attr.tunnel_stateless_gtp)
2278 return rte_flow_error_set(error, ENOTSUP,
2279 RTE_FLOW_ERROR_TYPE_ITEM, item,
2280 "GTP support is not enabled");
2281 if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
2282 return rte_flow_error_set(error, ENOTSUP,
2283 RTE_FLOW_ERROR_TYPE_ITEM, item,
2284 "multiple tunnel layers not"
2286 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
2287 return rte_flow_error_set(error, EINVAL,
2288 RTE_FLOW_ERROR_TYPE_ITEM, item,
2289 "no outer UDP layer found");
2291 mask = &rte_flow_item_gtp_mask;
2292 if (spec && spec->v_pt_rsv_flags & ~MLX5_GTP_FLAGS_MASK)
2293 return rte_flow_error_set(error, ENOTSUP,
2294 RTE_FLOW_ERROR_TYPE_ITEM, item,
2295 "Match is supported for GTP"
2297 return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2298 (const uint8_t *)&nic_mask,
2299 sizeof(struct rte_flow_item_gtp),
2300 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2304 * Validate GTP PSC item.
2307 * Item specification.
2308 * @param[in] last_item
2309 * Previous validated item in the pattern items.
2310 * @param[in] gtp_item
2311 * Previous GTP item specification.
2313 * Pointer to flow attributes.
2315 * Pointer to error structure.
2318 * 0 on success, a negative errno value otherwise and rte_errno is set.
2321 flow_dv_validate_item_gtp_psc(const struct rte_flow_item *item,
2323 const struct rte_flow_item *gtp_item,
2324 const struct rte_flow_attr *attr,
2325 struct rte_flow_error *error)
2327 const struct rte_flow_item_gtp *gtp_spec;
2328 const struct rte_flow_item_gtp *gtp_mask;
2329 const struct rte_flow_item_gtp_psc *spec;
2330 const struct rte_flow_item_gtp_psc *mask;
2331 const struct rte_flow_item_gtp_psc nic_mask = {
2336 if (!gtp_item || !(last_item & MLX5_FLOW_LAYER_GTP))
2337 return rte_flow_error_set
2338 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2339 "GTP PSC item must be preceded with GTP item");
2340 gtp_spec = gtp_item->spec;
2341 gtp_mask = gtp_item->mask ? gtp_item->mask : &rte_flow_item_gtp_mask;
2342 /* GTP spec and E flag is requested to match zero. */
2344 (gtp_mask->v_pt_rsv_flags &
2345 ~gtp_spec->v_pt_rsv_flags & MLX5_GTP_EXT_HEADER_FLAG))
2346 return rte_flow_error_set
2347 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2348 "GTP E flag must be 1 to match GTP PSC");
2349 /* Check the flow is not created in group zero. */
2350 if (!attr->transfer && !attr->group)
2351 return rte_flow_error_set
2352 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2353 "GTP PSC is not supported for group 0");
2354 /* GTP spec is here and E flag is requested to match zero. */
2358 mask = item->mask ? item->mask : &rte_flow_item_gtp_psc_mask;
2359 if (spec->pdu_type > MLX5_GTP_EXT_MAX_PDU_TYPE)
2360 return rte_flow_error_set
2361 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2362 "PDU type should be smaller than 16");
2363 return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2364 (const uint8_t *)&nic_mask,
2365 sizeof(struct rte_flow_item_gtp_psc),
2366 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2370 * Validate IPV4 item.
2371 * Use existing validation function mlx5_flow_validate_item_ipv4(), and
2372 * add specific validation of fragment_offset field,
2375 * Item specification.
2376 * @param[in] item_flags
2377 * Bit-fields that holds the items detected until now.
2379 * Pointer to error structure.
2382 * 0 on success, a negative errno value otherwise and rte_errno is set.
2385 flow_dv_validate_item_ipv4(const struct rte_flow_item *item,
2386 uint64_t item_flags,
2388 uint16_t ether_type,
2389 struct rte_flow_error *error)
2392 const struct rte_flow_item_ipv4 *spec = item->spec;
2393 const struct rte_flow_item_ipv4 *last = item->last;
2394 const struct rte_flow_item_ipv4 *mask = item->mask;
2395 rte_be16_t fragment_offset_spec = 0;
2396 rte_be16_t fragment_offset_last = 0;
2397 const struct rte_flow_item_ipv4 nic_ipv4_mask = {
2399 .src_addr = RTE_BE32(0xffffffff),
2400 .dst_addr = RTE_BE32(0xffffffff),
2401 .type_of_service = 0xff,
2402 .fragment_offset = RTE_BE16(0xffff),
2403 .next_proto_id = 0xff,
2404 .time_to_live = 0xff,
2408 ret = mlx5_flow_validate_item_ipv4(item, item_flags, last_item,
2409 ether_type, &nic_ipv4_mask,
2410 MLX5_ITEM_RANGE_ACCEPTED, error);
2414 fragment_offset_spec = spec->hdr.fragment_offset &
2415 mask->hdr.fragment_offset;
2416 if (!fragment_offset_spec)
2419 * spec and mask are valid, enforce using full mask to make sure the
2420 * complete value is used correctly.
2422 if ((mask->hdr.fragment_offset & RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2423 != RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2424 return rte_flow_error_set(error, EINVAL,
2425 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2426 item, "must use full mask for"
2427 " fragment_offset");
2429 * Match on fragment_offset 0x2000 means MF is 1 and frag-offset is 0,
2430 * indicating this is 1st fragment of fragmented packet.
2431 * This is not yet supported in MLX5, return appropriate error message.
2433 if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG))
2434 return rte_flow_error_set(error, ENOTSUP,
2435 RTE_FLOW_ERROR_TYPE_ITEM, item,
2436 "match on first fragment not "
2438 if (fragment_offset_spec && !last)
2439 return rte_flow_error_set(error, ENOTSUP,
2440 RTE_FLOW_ERROR_TYPE_ITEM, item,
2441 "specified value not supported");
2442 /* spec and last are valid, validate the specified range. */
2443 fragment_offset_last = last->hdr.fragment_offset &
2444 mask->hdr.fragment_offset;
2446 * Match on fragment_offset spec 0x2001 and last 0x3fff
2447 * means MF is 1 and frag-offset is > 0.
2448 * This packet is fragment 2nd and onward, excluding last.
2449 * This is not yet supported in MLX5, return appropriate
2452 if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG + 1) &&
2453 fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2454 return rte_flow_error_set(error, ENOTSUP,
2455 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2456 last, "match on following "
2457 "fragments not supported");
2459 * Match on fragment_offset spec 0x0001 and last 0x1fff
2460 * means MF is 0 and frag-offset is > 0.
2461 * This packet is last fragment of fragmented packet.
2462 * This is not yet supported in MLX5, return appropriate
2465 if (fragment_offset_spec == RTE_BE16(1) &&
2466 fragment_offset_last == RTE_BE16(RTE_IPV4_HDR_OFFSET_MASK))
2467 return rte_flow_error_set(error, ENOTSUP,
2468 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2469 last, "match on last "
2470 "fragment not supported");
2472 * Match on fragment_offset spec 0x0001 and last 0x3fff
2473 * means MF and/or frag-offset is not 0.
2474 * This is a fragmented packet.
2475 * Other range values are invalid and rejected.
2477 if (!(fragment_offset_spec == RTE_BE16(1) &&
2478 fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK)))
2479 return rte_flow_error_set(error, ENOTSUP,
2480 RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2481 "specified range not supported");
2486 * Validate IPV6 fragment extension item.
2489 * Item specification.
2490 * @param[in] item_flags
2491 * Bit-fields that holds the items detected until now.
2493 * Pointer to error structure.
2496 * 0 on success, a negative errno value otherwise and rte_errno is set.
2499 flow_dv_validate_item_ipv6_frag_ext(const struct rte_flow_item *item,
2500 uint64_t item_flags,
2501 struct rte_flow_error *error)
2503 const struct rte_flow_item_ipv6_frag_ext *spec = item->spec;
2504 const struct rte_flow_item_ipv6_frag_ext *last = item->last;
2505 const struct rte_flow_item_ipv6_frag_ext *mask = item->mask;
2506 rte_be16_t frag_data_spec = 0;
2507 rte_be16_t frag_data_last = 0;
2508 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2509 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 :
2510 MLX5_FLOW_LAYER_OUTER_L4;
2512 struct rte_flow_item_ipv6_frag_ext nic_mask = {
2514 .next_header = 0xff,
2515 .frag_data = RTE_BE16(0xffff),
2519 if (item_flags & l4m)
2520 return rte_flow_error_set(error, EINVAL,
2521 RTE_FLOW_ERROR_TYPE_ITEM, item,
2522 "ipv6 fragment extension item cannot "
2524 if ((tunnel && !(item_flags & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
2525 (!tunnel && !(item_flags & MLX5_FLOW_LAYER_OUTER_L3_IPV6)))
2526 return rte_flow_error_set(error, EINVAL,
2527 RTE_FLOW_ERROR_TYPE_ITEM, item,
2528 "ipv6 fragment extension item must "
2529 "follow ipv6 item");
2531 frag_data_spec = spec->hdr.frag_data & mask->hdr.frag_data;
2532 if (!frag_data_spec)
2535 * spec and mask are valid, enforce using full mask to make sure the
2536 * complete value is used correctly.
2538 if ((mask->hdr.frag_data & RTE_BE16(RTE_IPV6_FRAG_USED_MASK)) !=
2539 RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2540 return rte_flow_error_set(error, EINVAL,
2541 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2542 item, "must use full mask for"
2545 * Match on frag_data 0x00001 means M is 1 and frag-offset is 0.
2546 * This is 1st fragment of fragmented packet.
2548 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_MF_MASK))
2549 return rte_flow_error_set(error, ENOTSUP,
2550 RTE_FLOW_ERROR_TYPE_ITEM, item,
2551 "match on first fragment not "
2553 if (frag_data_spec && !last)
2554 return rte_flow_error_set(error, EINVAL,
2555 RTE_FLOW_ERROR_TYPE_ITEM, item,
2556 "specified value not supported");
2557 ret = mlx5_flow_item_acceptable
2558 (item, (const uint8_t *)mask,
2559 (const uint8_t *)&nic_mask,
2560 sizeof(struct rte_flow_item_ipv6_frag_ext),
2561 MLX5_ITEM_RANGE_ACCEPTED, error);
2564 /* spec and last are valid, validate the specified range. */
2565 frag_data_last = last->hdr.frag_data & mask->hdr.frag_data;
2567 * Match on frag_data spec 0x0009 and last 0xfff9
2568 * means M is 1 and frag-offset is > 0.
2569 * This packet is fragment 2nd and onward, excluding last.
2570 * This is not yet supported in MLX5, return appropriate
2573 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN |
2574 RTE_IPV6_EHDR_MF_MASK) &&
2575 frag_data_last == RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2576 return rte_flow_error_set(error, ENOTSUP,
2577 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2578 last, "match on following "
2579 "fragments not supported");
2581 * Match on frag_data spec 0x0008 and last 0xfff8
2582 * means M is 0 and frag-offset is > 0.
2583 * This packet is last fragment of fragmented packet.
2584 * This is not yet supported in MLX5, return appropriate
2587 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN) &&
2588 frag_data_last == RTE_BE16(RTE_IPV6_EHDR_FO_MASK))
2589 return rte_flow_error_set(error, ENOTSUP,
2590 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2591 last, "match on last "
2592 "fragment not supported");
2593 /* Other range values are invalid and rejected. */
2594 return rte_flow_error_set(error, EINVAL,
2595 RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2596 "specified range not supported");
2600 * Validate the pop VLAN action.
2603 * Pointer to the rte_eth_dev structure.
2604 * @param[in] action_flags
2605 * Holds the actions detected until now.
2607 * Pointer to the pop vlan action.
2608 * @param[in] item_flags
2609 * The items found in this flow rule.
2611 * Pointer to flow attributes.
2613 * Pointer to error structure.
2616 * 0 on success, a negative errno value otherwise and rte_errno is set.
2619 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
2620 uint64_t action_flags,
2621 const struct rte_flow_action *action,
2622 uint64_t item_flags,
2623 const struct rte_flow_attr *attr,
2624 struct rte_flow_error *error)
2626 const struct mlx5_priv *priv = dev->data->dev_private;
2630 if (!priv->sh->pop_vlan_action)
2631 return rte_flow_error_set(error, ENOTSUP,
2632 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2634 "pop vlan action is not supported");
2636 return rte_flow_error_set(error, ENOTSUP,
2637 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2639 "pop vlan action not supported for "
2641 if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
2642 return rte_flow_error_set(error, ENOTSUP,
2643 RTE_FLOW_ERROR_TYPE_ACTION, action,
2644 "no support for multiple VLAN "
2646 /* Pop VLAN with preceding Decap requires inner header with VLAN. */
2647 if ((action_flags & MLX5_FLOW_ACTION_DECAP) &&
2648 !(item_flags & MLX5_FLOW_LAYER_INNER_VLAN))
2649 return rte_flow_error_set(error, ENOTSUP,
2650 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2652 "cannot pop vlan after decap without "
2653 "match on inner vlan in the flow");
2654 /* Pop VLAN without preceding Decap requires outer header with VLAN. */
2655 if (!(action_flags & MLX5_FLOW_ACTION_DECAP) &&
2656 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2657 return rte_flow_error_set(error, ENOTSUP,
2658 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2660 "cannot pop vlan without a "
2661 "match on (outer) vlan in the flow");
2662 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2663 return rte_flow_error_set(error, EINVAL,
2664 RTE_FLOW_ERROR_TYPE_ACTION, action,
2665 "wrong action order, port_id should "
2666 "be after pop VLAN action");
2667 if (!attr->transfer && priv->representor)
2668 return rte_flow_error_set(error, ENOTSUP,
2669 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2670 "pop vlan action for VF representor "
2671 "not supported on NIC table");
2676 * Get VLAN default info from vlan match info.
2679 * the list of item specifications.
2681 * pointer VLAN info to fill to.
2684 * 0 on success, a negative errno value otherwise and rte_errno is set.
2687 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
2688 struct rte_vlan_hdr *vlan)
2690 const struct rte_flow_item_vlan nic_mask = {
2691 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
2692 MLX5DV_FLOW_VLAN_VID_MASK),
2693 .inner_type = RTE_BE16(0xffff),
2698 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2699 int type = items->type;
2701 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
2702 type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
2705 if (items->type != RTE_FLOW_ITEM_TYPE_END) {
2706 const struct rte_flow_item_vlan *vlan_m = items->mask;
2707 const struct rte_flow_item_vlan *vlan_v = items->spec;
2709 /* If VLAN item in pattern doesn't contain data, return here. */
2714 /* Only full match values are accepted */
2715 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
2716 MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
2717 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
2719 rte_be_to_cpu_16(vlan_v->tci &
2720 MLX5DV_FLOW_VLAN_PCP_MASK_BE);
2722 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
2723 MLX5DV_FLOW_VLAN_VID_MASK_BE) {
2724 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
2726 rte_be_to_cpu_16(vlan_v->tci &
2727 MLX5DV_FLOW_VLAN_VID_MASK_BE);
2729 if (vlan_m->inner_type == nic_mask.inner_type)
2730 vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
2731 vlan_m->inner_type);
2736 * Validate the push VLAN action.
2739 * Pointer to the rte_eth_dev structure.
2740 * @param[in] action_flags
2741 * Holds the actions detected until now.
2742 * @param[in] item_flags
2743 * The items found in this flow rule.
2745 * Pointer to the action structure.
2747 * Pointer to flow attributes
2749 * Pointer to error structure.
2752 * 0 on success, a negative errno value otherwise and rte_errno is set.
2755 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
2756 uint64_t action_flags,
2757 const struct rte_flow_item_vlan *vlan_m,
2758 const struct rte_flow_action *action,
2759 const struct rte_flow_attr *attr,
2760 struct rte_flow_error *error)
2762 const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
2763 const struct mlx5_priv *priv = dev->data->dev_private;
2765 if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
2766 push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
2767 return rte_flow_error_set(error, EINVAL,
2768 RTE_FLOW_ERROR_TYPE_ACTION, action,
2769 "invalid vlan ethertype");
2770 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2771 return rte_flow_error_set(error, EINVAL,
2772 RTE_FLOW_ERROR_TYPE_ACTION, action,
2773 "wrong action order, port_id should "
2774 "be after push VLAN");
2775 if (!attr->transfer && priv->representor)
2776 return rte_flow_error_set(error, ENOTSUP,
2777 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2778 "push vlan action for VF representor "
2779 "not supported on NIC table");
2781 (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
2782 (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
2783 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
2784 !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
2785 !(mlx5_flow_find_action
2786 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
2787 return rte_flow_error_set(error, EINVAL,
2788 RTE_FLOW_ERROR_TYPE_ACTION, action,
2789 "not full match mask on VLAN PCP and "
2790 "there is no of_set_vlan_pcp action, "
2791 "push VLAN action cannot figure out "
2794 (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
2795 (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
2796 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
2797 !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
2798 !(mlx5_flow_find_action
2799 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
2800 return rte_flow_error_set(error, EINVAL,
2801 RTE_FLOW_ERROR_TYPE_ACTION, action,
2802 "not full match mask on VLAN VID and "
2803 "there is no of_set_vlan_vid action, "
2804 "push VLAN action cannot figure out "
2811 * Validate the set VLAN PCP.
2813 * @param[in] action_flags
2814 * Holds the actions detected until now.
2815 * @param[in] actions
2816 * Pointer to the list of actions remaining in the flow rule.
2818 * Pointer to error structure.
2821 * 0 on success, a negative errno value otherwise and rte_errno is set.
2824 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
2825 const struct rte_flow_action actions[],
2826 struct rte_flow_error *error)
2828 const struct rte_flow_action *action = actions;
2829 const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
2831 if (conf->vlan_pcp > 7)
2832 return rte_flow_error_set(error, EINVAL,
2833 RTE_FLOW_ERROR_TYPE_ACTION, action,
2834 "VLAN PCP value is too big");
2835 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
2836 return rte_flow_error_set(error, ENOTSUP,
2837 RTE_FLOW_ERROR_TYPE_ACTION, action,
2838 "set VLAN PCP action must follow "
2839 "the push VLAN action");
2840 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
2841 return rte_flow_error_set(error, ENOTSUP,
2842 RTE_FLOW_ERROR_TYPE_ACTION, action,
2843 "Multiple VLAN PCP modification are "
2845 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2846 return rte_flow_error_set(error, EINVAL,
2847 RTE_FLOW_ERROR_TYPE_ACTION, action,
2848 "wrong action order, port_id should "
2849 "be after set VLAN PCP");
2854 * Validate the set VLAN VID.
2856 * @param[in] item_flags
2857 * Holds the items detected in this rule.
2858 * @param[in] action_flags
2859 * Holds the actions detected until now.
2860 * @param[in] actions
2861 * Pointer to the list of actions remaining in the flow rule.
2863 * Pointer to error structure.
2866 * 0 on success, a negative errno value otherwise and rte_errno is set.
2869 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
2870 uint64_t action_flags,
2871 const struct rte_flow_action actions[],
2872 struct rte_flow_error *error)
2874 const struct rte_flow_action *action = actions;
2875 const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
2877 if (rte_be_to_cpu_16(conf->vlan_vid) > 0xFFE)
2878 return rte_flow_error_set(error, EINVAL,
2879 RTE_FLOW_ERROR_TYPE_ACTION, action,
2880 "VLAN VID value is too big");
2881 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
2882 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2883 return rte_flow_error_set(error, ENOTSUP,
2884 RTE_FLOW_ERROR_TYPE_ACTION, action,
2885 "set VLAN VID action must follow push"
2886 " VLAN action or match on VLAN item");
2887 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
2888 return rte_flow_error_set(error, ENOTSUP,
2889 RTE_FLOW_ERROR_TYPE_ACTION, action,
2890 "Multiple VLAN VID modifications are "
2892 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2893 return rte_flow_error_set(error, EINVAL,
2894 RTE_FLOW_ERROR_TYPE_ACTION, action,
2895 "wrong action order, port_id should "
2896 "be after set VLAN VID");
2901 * Validate the FLAG action.
2904 * Pointer to the rte_eth_dev structure.
2905 * @param[in] action_flags
2906 * Holds the actions detected until now.
2908 * Pointer to flow attributes
2910 * Pointer to error structure.
2913 * 0 on success, a negative errno value otherwise and rte_errno is set.
2916 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
2917 uint64_t action_flags,
2918 const struct rte_flow_attr *attr,
2919 struct rte_flow_error *error)
2921 struct mlx5_priv *priv = dev->data->dev_private;
2922 struct mlx5_dev_config *config = &priv->config;
2925 /* Fall back if no extended metadata register support. */
2926 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2927 return mlx5_flow_validate_action_flag(action_flags, attr,
2929 /* Extensive metadata mode requires registers. */
2930 if (!mlx5_flow_ext_mreg_supported(dev))
2931 return rte_flow_error_set(error, ENOTSUP,
2932 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2933 "no metadata registers "
2934 "to support flag action");
2935 if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
2936 return rte_flow_error_set(error, ENOTSUP,
2937 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2938 "extended metadata register"
2939 " isn't available");
2940 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2943 MLX5_ASSERT(ret > 0);
2944 if (action_flags & MLX5_FLOW_ACTION_MARK)
2945 return rte_flow_error_set(error, EINVAL,
2946 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2947 "can't mark and flag in same flow");
2948 if (action_flags & MLX5_FLOW_ACTION_FLAG)
2949 return rte_flow_error_set(error, EINVAL,
2950 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2952 " actions in same flow");
2957 * Validate MARK action.
2960 * Pointer to the rte_eth_dev structure.
2962 * Pointer to action.
2963 * @param[in] action_flags
2964 * Holds the actions detected until now.
2966 * Pointer to flow attributes
2968 * Pointer to error structure.
2971 * 0 on success, a negative errno value otherwise and rte_errno is set.
2974 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
2975 const struct rte_flow_action *action,
2976 uint64_t action_flags,
2977 const struct rte_flow_attr *attr,
2978 struct rte_flow_error *error)
2980 struct mlx5_priv *priv = dev->data->dev_private;
2981 struct mlx5_dev_config *config = &priv->config;
2982 const struct rte_flow_action_mark *mark = action->conf;
2985 if (is_tunnel_offload_active(dev))
2986 return rte_flow_error_set(error, ENOTSUP,
2987 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2989 "if tunnel offload active");
2990 /* Fall back if no extended metadata register support. */
2991 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2992 return mlx5_flow_validate_action_mark(action, action_flags,
2994 /* Extensive metadata mode requires registers. */
2995 if (!mlx5_flow_ext_mreg_supported(dev))
2996 return rte_flow_error_set(error, ENOTSUP,
2997 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2998 "no metadata registers "
2999 "to support mark action");
3000 if (!priv->sh->dv_mark_mask)
3001 return rte_flow_error_set(error, ENOTSUP,
3002 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3003 "extended metadata register"
3004 " isn't available");
3005 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
3008 MLX5_ASSERT(ret > 0);
3010 return rte_flow_error_set(error, EINVAL,
3011 RTE_FLOW_ERROR_TYPE_ACTION, action,
3012 "configuration cannot be null");
3013 if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
3014 return rte_flow_error_set(error, EINVAL,
3015 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3017 "mark id exceeds the limit");
3018 if (action_flags & MLX5_FLOW_ACTION_FLAG)
3019 return rte_flow_error_set(error, EINVAL,
3020 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3021 "can't flag and mark in same flow");
3022 if (action_flags & MLX5_FLOW_ACTION_MARK)
3023 return rte_flow_error_set(error, EINVAL,
3024 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3025 "can't have 2 mark actions in same"
3031 * Validate SET_META action.
3034 * Pointer to the rte_eth_dev structure.
3036 * Pointer to the action structure.
3037 * @param[in] action_flags
3038 * Holds the actions detected until now.
3040 * Pointer to flow attributes
3042 * Pointer to error structure.
3045 * 0 on success, a negative errno value otherwise and rte_errno is set.
3048 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
3049 const struct rte_flow_action *action,
3050 uint64_t action_flags __rte_unused,
3051 const struct rte_flow_attr *attr,
3052 struct rte_flow_error *error)
3054 const struct rte_flow_action_set_meta *conf;
3055 uint32_t nic_mask = UINT32_MAX;
3058 if (!mlx5_flow_ext_mreg_supported(dev))
3059 return rte_flow_error_set(error, ENOTSUP,
3060 RTE_FLOW_ERROR_TYPE_ACTION, action,
3061 "extended metadata register"
3062 " isn't supported");
3063 reg = flow_dv_get_metadata_reg(dev, attr, error);
3067 return rte_flow_error_set(error, ENOTSUP,
3068 RTE_FLOW_ERROR_TYPE_ACTION, action,
3069 "unavalable extended metadata register");
3070 if (reg != REG_A && reg != REG_B) {
3071 struct mlx5_priv *priv = dev->data->dev_private;
3073 nic_mask = priv->sh->dv_meta_mask;
3075 if (!(action->conf))
3076 return rte_flow_error_set(error, EINVAL,
3077 RTE_FLOW_ERROR_TYPE_ACTION, action,
3078 "configuration cannot be null");
3079 conf = (const struct rte_flow_action_set_meta *)action->conf;
3081 return rte_flow_error_set(error, EINVAL,
3082 RTE_FLOW_ERROR_TYPE_ACTION, action,
3083 "zero mask doesn't have any effect");
3084 if (conf->mask & ~nic_mask)
3085 return rte_flow_error_set(error, EINVAL,
3086 RTE_FLOW_ERROR_TYPE_ACTION, action,
3087 "meta data must be within reg C0");
3092 * Validate SET_TAG action.
3095 * Pointer to the rte_eth_dev structure.
3097 * Pointer to the action structure.
3098 * @param[in] action_flags
3099 * Holds the actions detected until now.
3101 * Pointer to flow attributes
3103 * Pointer to error structure.
3106 * 0 on success, a negative errno value otherwise and rte_errno is set.
3109 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
3110 const struct rte_flow_action *action,
3111 uint64_t action_flags,
3112 const struct rte_flow_attr *attr,
3113 struct rte_flow_error *error)
3115 const struct rte_flow_action_set_tag *conf;
3116 const uint64_t terminal_action_flags =
3117 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
3118 MLX5_FLOW_ACTION_RSS;
3121 if (!mlx5_flow_ext_mreg_supported(dev))
3122 return rte_flow_error_set(error, ENOTSUP,
3123 RTE_FLOW_ERROR_TYPE_ACTION, action,
3124 "extensive metadata register"
3125 " isn't supported");
3126 if (!(action->conf))
3127 return rte_flow_error_set(error, EINVAL,
3128 RTE_FLOW_ERROR_TYPE_ACTION, action,
3129 "configuration cannot be null");
3130 conf = (const struct rte_flow_action_set_tag *)action->conf;
3132 return rte_flow_error_set(error, EINVAL,
3133 RTE_FLOW_ERROR_TYPE_ACTION, action,
3134 "zero mask doesn't have any effect");
3135 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
3138 if (!attr->transfer && attr->ingress &&
3139 (action_flags & terminal_action_flags))
3140 return rte_flow_error_set(error, EINVAL,
3141 RTE_FLOW_ERROR_TYPE_ACTION, action,
3142 "set_tag has no effect"
3143 " with terminal actions");
3148 * Validate count action.
3151 * Pointer to rte_eth_dev structure.
3153 * Pointer to the action structure.
3154 * @param[in] action_flags
3155 * Holds the actions detected until now.
3157 * Pointer to error structure.
3160 * 0 on success, a negative errno value otherwise and rte_errno is set.
3163 flow_dv_validate_action_count(struct rte_eth_dev *dev,
3164 const struct rte_flow_action *action,
3165 uint64_t action_flags,
3166 struct rte_flow_error *error)
3168 struct mlx5_priv *priv = dev->data->dev_private;
3169 const struct rte_flow_action_count *count;
3171 if (!priv->config.devx)
3173 if (action_flags & MLX5_FLOW_ACTION_COUNT)
3174 return rte_flow_error_set(error, EINVAL,
3175 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3176 "duplicate count actions set");
3177 count = (const struct rte_flow_action_count *)action->conf;
3178 if (count && count->shared && (action_flags & MLX5_FLOW_ACTION_AGE) &&
3179 !priv->sh->flow_hit_aso_en)
3180 return rte_flow_error_set(error, EINVAL,
3181 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3182 "old age and shared count combination is not supported");
3183 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
3187 return rte_flow_error_set
3189 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3191 "count action not supported");
3195 * Validate the L2 encap action.
3198 * Pointer to the rte_eth_dev structure.
3199 * @param[in] action_flags
3200 * Holds the actions detected until now.
3202 * Pointer to the action structure.
3204 * Pointer to flow attributes.
3206 * Pointer to error structure.
3209 * 0 on success, a negative errno value otherwise and rte_errno is set.
3212 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
3213 uint64_t action_flags,
3214 const struct rte_flow_action *action,
3215 const struct rte_flow_attr *attr,
3216 struct rte_flow_error *error)
3218 const struct mlx5_priv *priv = dev->data->dev_private;
3220 if (!(action->conf))
3221 return rte_flow_error_set(error, EINVAL,
3222 RTE_FLOW_ERROR_TYPE_ACTION, action,
3223 "configuration cannot be null");
3224 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3225 return rte_flow_error_set(error, EINVAL,
3226 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3227 "can only have a single encap action "
3229 if (!attr->transfer && priv->representor)
3230 return rte_flow_error_set(error, ENOTSUP,
3231 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3232 "encap action for VF representor "
3233 "not supported on NIC table");
3238 * Validate a decap action.
3241 * Pointer to the rte_eth_dev structure.
3242 * @param[in] action_flags
3243 * Holds the actions detected until now.
3245 * Pointer to the action structure.
3246 * @param[in] item_flags
3247 * Holds the items detected.
3249 * Pointer to flow attributes
3251 * Pointer to error structure.
3254 * 0 on success, a negative errno value otherwise and rte_errno is set.
3257 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
3258 uint64_t action_flags,
3259 const struct rte_flow_action *action,
3260 const uint64_t item_flags,
3261 const struct rte_flow_attr *attr,
3262 struct rte_flow_error *error)
3264 const struct mlx5_priv *priv = dev->data->dev_private;
3266 if (priv->config.hca_attr.scatter_fcs_w_decap_disable &&
3267 !priv->config.decap_en)
3268 return rte_flow_error_set(error, ENOTSUP,
3269 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3270 "decap is not enabled");
3271 if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
3272 return rte_flow_error_set(error, ENOTSUP,
3273 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3275 MLX5_FLOW_ACTION_DECAP ? "can only "
3276 "have a single decap action" : "decap "
3277 "after encap is not supported");
3278 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
3279 return rte_flow_error_set(error, EINVAL,
3280 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3281 "can't have decap action after"
3284 return rte_flow_error_set(error, ENOTSUP,
3285 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
3287 "decap action not supported for "
3289 if (!attr->transfer && priv->representor)
3290 return rte_flow_error_set(error, ENOTSUP,
3291 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3292 "decap action for VF representor "
3293 "not supported on NIC table");
3294 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_DECAP &&
3295 !(item_flags & MLX5_FLOW_LAYER_VXLAN))
3296 return rte_flow_error_set(error, ENOTSUP,
3297 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3298 "VXLAN item should be present for VXLAN decap");
3302 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
3305 * Validate the raw encap and decap actions.
3308 * Pointer to the rte_eth_dev structure.
3310 * Pointer to the decap action.
3312 * Pointer to the encap action.
3314 * Pointer to flow attributes
3315 * @param[in/out] action_flags
3316 * Holds the actions detected until now.
3317 * @param[out] actions_n
3318 * pointer to the number of actions counter.
3320 * Pointer to the action structure.
3321 * @param[in] item_flags
3322 * Holds the items detected.
3324 * Pointer to error structure.
3327 * 0 on success, a negative errno value otherwise and rte_errno is set.
3330 flow_dv_validate_action_raw_encap_decap
3331 (struct rte_eth_dev *dev,
3332 const struct rte_flow_action_raw_decap *decap,
3333 const struct rte_flow_action_raw_encap *encap,
3334 const struct rte_flow_attr *attr, uint64_t *action_flags,
3335 int *actions_n, const struct rte_flow_action *action,
3336 uint64_t item_flags, struct rte_flow_error *error)
3338 const struct mlx5_priv *priv = dev->data->dev_private;
3341 if (encap && (!encap->size || !encap->data))
3342 return rte_flow_error_set(error, EINVAL,
3343 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3344 "raw encap data cannot be empty");
3345 if (decap && encap) {
3346 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
3347 encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
3350 else if (encap->size <=
3351 MLX5_ENCAPSULATION_DECISION_SIZE &&
3353 MLX5_ENCAPSULATION_DECISION_SIZE)
3356 else if (encap->size >
3357 MLX5_ENCAPSULATION_DECISION_SIZE &&
3359 MLX5_ENCAPSULATION_DECISION_SIZE)
3360 /* 2 L2 actions: encap and decap. */
3363 return rte_flow_error_set(error,
3365 RTE_FLOW_ERROR_TYPE_ACTION,
3366 NULL, "unsupported too small "
3367 "raw decap and too small raw "
3368 "encap combination");
3371 ret = flow_dv_validate_action_decap(dev, *action_flags, action,
3372 item_flags, attr, error);
3375 *action_flags |= MLX5_FLOW_ACTION_DECAP;
3379 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
3380 return rte_flow_error_set(error, ENOTSUP,
3381 RTE_FLOW_ERROR_TYPE_ACTION,
3383 "small raw encap size");
3384 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
3385 return rte_flow_error_set(error, EINVAL,
3386 RTE_FLOW_ERROR_TYPE_ACTION,
3388 "more than one encap action");
3389 if (!attr->transfer && priv->representor)
3390 return rte_flow_error_set
3392 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3393 "encap action for VF representor "
3394 "not supported on NIC table");
3395 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
3402 * Match encap_decap resource.
3405 * Pointer to the hash list.
3407 * Pointer to exist resource entry object.
3409 * Key of the new entry.
3411 * Pointer to new encap_decap resource.
3414 * 0 on matching, none-zero otherwise.
3417 flow_dv_encap_decap_match_cb(struct mlx5_hlist *list __rte_unused,
3418 struct mlx5_hlist_entry *entry,
3419 uint64_t key __rte_unused, void *cb_ctx)
3421 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3422 struct mlx5_flow_dv_encap_decap_resource *resource = ctx->data;
3423 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
3425 cache_resource = container_of(entry,
3426 struct mlx5_flow_dv_encap_decap_resource,
3428 if (resource->reformat_type == cache_resource->reformat_type &&
3429 resource->ft_type == cache_resource->ft_type &&
3430 resource->flags == cache_resource->flags &&
3431 resource->size == cache_resource->size &&
3432 !memcmp((const void *)resource->buf,
3433 (const void *)cache_resource->buf,
3440 * Allocate encap_decap resource.
3443 * Pointer to the hash list.
3445 * Pointer to exist resource entry object.
3447 * Pointer to new encap_decap resource.
3450 * 0 on matching, none-zero otherwise.
3452 struct mlx5_hlist_entry *
3453 flow_dv_encap_decap_create_cb(struct mlx5_hlist *list,
3454 uint64_t key __rte_unused,
3457 struct mlx5_dev_ctx_shared *sh = list->ctx;
3458 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3459 struct mlx5dv_dr_domain *domain;
3460 struct mlx5_flow_dv_encap_decap_resource *resource = ctx->data;
3461 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
3465 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3466 domain = sh->fdb_domain;
3467 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3468 domain = sh->rx_domain;
3470 domain = sh->tx_domain;
3471 /* Register new encap/decap resource. */
3472 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
3474 if (!cache_resource) {
3475 rte_flow_error_set(ctx->error, ENOMEM,
3476 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3477 "cannot allocate resource memory");
3480 *cache_resource = *resource;
3481 cache_resource->idx = idx;
3482 ret = mlx5_flow_os_create_flow_action_packet_reformat
3483 (sh->ctx, domain, cache_resource,
3484 &cache_resource->action);
3486 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);
3487 rte_flow_error_set(ctx->error, ENOMEM,
3488 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3489 NULL, "cannot create action");
3493 return &cache_resource->entry;
3497 * Find existing encap/decap resource or create and register a new one.
3499 * @param[in, out] dev
3500 * Pointer to rte_eth_dev structure.
3501 * @param[in, out] resource
3502 * Pointer to encap/decap resource.
3503 * @parm[in, out] dev_flow
3504 * Pointer to the dev_flow.
3506 * pointer to error structure.
3509 * 0 on success otherwise -errno and errno is set.
3512 flow_dv_encap_decap_resource_register
3513 (struct rte_eth_dev *dev,
3514 struct mlx5_flow_dv_encap_decap_resource *resource,
3515 struct mlx5_flow *dev_flow,
3516 struct rte_flow_error *error)
3518 struct mlx5_priv *priv = dev->data->dev_private;
3519 struct mlx5_dev_ctx_shared *sh = priv->sh;
3520 struct mlx5_hlist_entry *entry;
3524 uint32_t refmt_type:8;
3526 * Header reformat actions can be shared between
3527 * non-root tables. One bit to indicate non-root
3531 uint32_t reserve:15;
3534 } encap_decap_key = {
3536 .ft_type = resource->ft_type,
3537 .refmt_type = resource->reformat_type,
3538 .is_root = !!dev_flow->dv.group,
3542 struct mlx5_flow_cb_ctx ctx = {
3548 resource->flags = dev_flow->dv.group ? 0 : 1;
3549 key64 = __rte_raw_cksum(&encap_decap_key.v32,
3550 sizeof(encap_decap_key.v32), 0);
3551 if (resource->reformat_type !=
3552 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2 &&
3554 key64 = __rte_raw_cksum(resource->buf, resource->size, key64);
3555 entry = mlx5_hlist_register(sh->encaps_decaps, key64, &ctx);
3558 resource = container_of(entry, typeof(*resource), entry);
3559 dev_flow->dv.encap_decap = resource;
3560 dev_flow->handle->dvh.rix_encap_decap = resource->idx;
3565 * Find existing table jump resource or create and register a new one.
3567 * @param[in, out] dev
3568 * Pointer to rte_eth_dev structure.
3569 * @param[in, out] tbl
3570 * Pointer to flow table resource.
3571 * @parm[in, out] dev_flow
3572 * Pointer to the dev_flow.
3574 * pointer to error structure.
3577 * 0 on success otherwise -errno and errno is set.
3580 flow_dv_jump_tbl_resource_register
3581 (struct rte_eth_dev *dev __rte_unused,
3582 struct mlx5_flow_tbl_resource *tbl,
3583 struct mlx5_flow *dev_flow,
3584 struct rte_flow_error *error __rte_unused)
3586 struct mlx5_flow_tbl_data_entry *tbl_data =
3587 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
3590 MLX5_ASSERT(tbl_data->jump.action);
3591 dev_flow->handle->rix_jump = tbl_data->idx;
3592 dev_flow->dv.jump = &tbl_data->jump;
3597 flow_dv_port_id_match_cb(struct mlx5_cache_list *list __rte_unused,
3598 struct mlx5_cache_entry *entry, void *cb_ctx)
3600 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3601 struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3602 struct mlx5_flow_dv_port_id_action_resource *res =
3603 container_of(entry, typeof(*res), entry);
3605 return ref->port_id != res->port_id;
3608 struct mlx5_cache_entry *
3609 flow_dv_port_id_create_cb(struct mlx5_cache_list *list,
3610 struct mlx5_cache_entry *entry __rte_unused,
3613 struct mlx5_dev_ctx_shared *sh = list->ctx;
3614 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3615 struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3616 struct mlx5_flow_dv_port_id_action_resource *cache;
3620 /* Register new port id action resource. */
3621 cache = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID], &idx);
3623 rte_flow_error_set(ctx->error, ENOMEM,
3624 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3625 "cannot allocate port_id action cache memory");
3629 ret = mlx5_flow_os_create_flow_action_dest_port(sh->fdb_domain,
3633 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], idx);
3634 rte_flow_error_set(ctx->error, ENOMEM,
3635 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3636 "cannot create action");
3640 return &cache->entry;
3644 * Find existing table port ID resource or create and register a new one.
3646 * @param[in, out] dev
3647 * Pointer to rte_eth_dev structure.
3648 * @param[in, out] resource
3649 * Pointer to port ID action resource.
3650 * @parm[in, out] dev_flow
3651 * Pointer to the dev_flow.
3653 * pointer to error structure.
3656 * 0 on success otherwise -errno and errno is set.
3659 flow_dv_port_id_action_resource_register
3660 (struct rte_eth_dev *dev,
3661 struct mlx5_flow_dv_port_id_action_resource *resource,
3662 struct mlx5_flow *dev_flow,
3663 struct rte_flow_error *error)
3665 struct mlx5_priv *priv = dev->data->dev_private;
3666 struct mlx5_cache_entry *entry;
3667 struct mlx5_flow_dv_port_id_action_resource *cache;
3668 struct mlx5_flow_cb_ctx ctx = {
3673 entry = mlx5_cache_register(&priv->sh->port_id_action_list, &ctx);
3676 cache = container_of(entry, typeof(*cache), entry);
3677 dev_flow->dv.port_id_action = cache;
3678 dev_flow->handle->rix_port_id_action = cache->idx;
3683 flow_dv_push_vlan_match_cb(struct mlx5_cache_list *list __rte_unused,
3684 struct mlx5_cache_entry *entry, void *cb_ctx)
3686 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3687 struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3688 struct mlx5_flow_dv_push_vlan_action_resource *res =
3689 container_of(entry, typeof(*res), entry);
3691 return ref->vlan_tag != res->vlan_tag || ref->ft_type != res->ft_type;
3694 struct mlx5_cache_entry *
3695 flow_dv_push_vlan_create_cb(struct mlx5_cache_list *list,
3696 struct mlx5_cache_entry *entry __rte_unused,
3699 struct mlx5_dev_ctx_shared *sh = list->ctx;
3700 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3701 struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3702 struct mlx5_flow_dv_push_vlan_action_resource *cache;
3703 struct mlx5dv_dr_domain *domain;
3707 /* Register new port id action resource. */
3708 cache = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN], &idx);
3710 rte_flow_error_set(ctx->error, ENOMEM,
3711 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3712 "cannot allocate push_vlan action cache memory");
3716 if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3717 domain = sh->fdb_domain;
3718 else if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3719 domain = sh->rx_domain;
3721 domain = sh->tx_domain;
3722 ret = mlx5_flow_os_create_flow_action_push_vlan(domain, ref->vlan_tag,
3725 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
3726 rte_flow_error_set(ctx->error, ENOMEM,
3727 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3728 "cannot create push vlan action");
3732 return &cache->entry;
3736 * Find existing push vlan resource or create and register a new one.
3738 * @param [in, out] dev
3739 * Pointer to rte_eth_dev structure.
3740 * @param[in, out] resource
3741 * Pointer to port ID action resource.
3742 * @parm[in, out] dev_flow
3743 * Pointer to the dev_flow.
3745 * pointer to error structure.
3748 * 0 on success otherwise -errno and errno is set.
3751 flow_dv_push_vlan_action_resource_register
3752 (struct rte_eth_dev *dev,
3753 struct mlx5_flow_dv_push_vlan_action_resource *resource,
3754 struct mlx5_flow *dev_flow,
3755 struct rte_flow_error *error)
3757 struct mlx5_priv *priv = dev->data->dev_private;
3758 struct mlx5_flow_dv_push_vlan_action_resource *cache;
3759 struct mlx5_cache_entry *entry;
3760 struct mlx5_flow_cb_ctx ctx = {
3765 entry = mlx5_cache_register(&priv->sh->push_vlan_action_list, &ctx);
3768 cache = container_of(entry, typeof(*cache), entry);
3770 dev_flow->handle->dvh.rix_push_vlan = cache->idx;
3771 dev_flow->dv.push_vlan_res = cache;
3776 * Get the size of specific rte_flow_item_type hdr size
3778 * @param[in] item_type
3779 * Tested rte_flow_item_type.
3782 * sizeof struct item_type, 0 if void or irrelevant.
3785 flow_dv_get_item_hdr_len(const enum rte_flow_item_type item_type)
3789 switch (item_type) {
3790 case RTE_FLOW_ITEM_TYPE_ETH:
3791 retval = sizeof(struct rte_ether_hdr);
3793 case RTE_FLOW_ITEM_TYPE_VLAN:
3794 retval = sizeof(struct rte_vlan_hdr);
3796 case RTE_FLOW_ITEM_TYPE_IPV4:
3797 retval = sizeof(struct rte_ipv4_hdr);
3799 case RTE_FLOW_ITEM_TYPE_IPV6:
3800 retval = sizeof(struct rte_ipv6_hdr);
3802 case RTE_FLOW_ITEM_TYPE_UDP:
3803 retval = sizeof(struct rte_udp_hdr);
3805 case RTE_FLOW_ITEM_TYPE_TCP:
3806 retval = sizeof(struct rte_tcp_hdr);
3808 case RTE_FLOW_ITEM_TYPE_VXLAN:
3809 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3810 retval = sizeof(struct rte_vxlan_hdr);
3812 case RTE_FLOW_ITEM_TYPE_GRE:
3813 case RTE_FLOW_ITEM_TYPE_NVGRE:
3814 retval = sizeof(struct rte_gre_hdr);
3816 case RTE_FLOW_ITEM_TYPE_MPLS:
3817 retval = sizeof(struct rte_mpls_hdr);
3819 case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
3827 #define MLX5_ENCAP_IPV4_VERSION 0x40
3828 #define MLX5_ENCAP_IPV4_IHL_MIN 0x05
3829 #define MLX5_ENCAP_IPV4_TTL_DEF 0x40
3830 #define MLX5_ENCAP_IPV6_VTC_FLOW 0x60000000
3831 #define MLX5_ENCAP_IPV6_HOP_LIMIT 0xff
3832 #define MLX5_ENCAP_VXLAN_FLAGS 0x08000000
3833 #define MLX5_ENCAP_VXLAN_GPE_FLAGS 0x04
3836 * Convert the encap action data from list of rte_flow_item to raw buffer
3839 * Pointer to rte_flow_item objects list.
3841 * Pointer to the output buffer.
3843 * Pointer to the output buffer size.
3845 * Pointer to the error structure.
3848 * 0 on success, a negative errno value otherwise and rte_errno is set.
3851 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
3852 size_t *size, struct rte_flow_error *error)
3854 struct rte_ether_hdr *eth = NULL;
3855 struct rte_vlan_hdr *vlan = NULL;
3856 struct rte_ipv4_hdr *ipv4 = NULL;
3857 struct rte_ipv6_hdr *ipv6 = NULL;
3858 struct rte_udp_hdr *udp = NULL;
3859 struct rte_vxlan_hdr *vxlan = NULL;
3860 struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
3861 struct rte_gre_hdr *gre = NULL;
3863 size_t temp_size = 0;
3866 return rte_flow_error_set(error, EINVAL,
3867 RTE_FLOW_ERROR_TYPE_ACTION,
3868 NULL, "invalid empty data");
3869 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
3870 len = flow_dv_get_item_hdr_len(items->type);
3871 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
3872 return rte_flow_error_set(error, EINVAL,
3873 RTE_FLOW_ERROR_TYPE_ACTION,
3874 (void *)items->type,
3875 "items total size is too big"
3876 " for encap action");
3877 rte_memcpy((void *)&buf[temp_size], items->spec, len);
3878 switch (items->type) {
3879 case RTE_FLOW_ITEM_TYPE_ETH:
3880 eth = (struct rte_ether_hdr *)&buf[temp_size];
3882 case RTE_FLOW_ITEM_TYPE_VLAN:
3883 vlan = (struct rte_vlan_hdr *)&buf[temp_size];
3885 return rte_flow_error_set(error, EINVAL,
3886 RTE_FLOW_ERROR_TYPE_ACTION,
3887 (void *)items->type,
3888 "eth header not found");
3889 if (!eth->ether_type)
3890 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
3892 case RTE_FLOW_ITEM_TYPE_IPV4:
3893 ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
3895 return rte_flow_error_set(error, EINVAL,
3896 RTE_FLOW_ERROR_TYPE_ACTION,
3897 (void *)items->type,
3898 "neither eth nor vlan"
3900 if (vlan && !vlan->eth_proto)
3901 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3902 else if (eth && !eth->ether_type)
3903 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3904 if (!ipv4->version_ihl)
3905 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
3906 MLX5_ENCAP_IPV4_IHL_MIN;
3907 if (!ipv4->time_to_live)
3908 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
3910 case RTE_FLOW_ITEM_TYPE_IPV6:
3911 ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
3913 return rte_flow_error_set(error, EINVAL,
3914 RTE_FLOW_ERROR_TYPE_ACTION,
3915 (void *)items->type,
3916 "neither eth nor vlan"
3918 if (vlan && !vlan->eth_proto)
3919 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3920 else if (eth && !eth->ether_type)
3921 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3922 if (!ipv6->vtc_flow)
3924 RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
3925 if (!ipv6->hop_limits)
3926 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
3928 case RTE_FLOW_ITEM_TYPE_UDP:
3929 udp = (struct rte_udp_hdr *)&buf[temp_size];
3931 return rte_flow_error_set(error, EINVAL,
3932 RTE_FLOW_ERROR_TYPE_ACTION,
3933 (void *)items->type,
3934 "ip header not found");
3935 if (ipv4 && !ipv4->next_proto_id)
3936 ipv4->next_proto_id = IPPROTO_UDP;
3937 else if (ipv6 && !ipv6->proto)
3938 ipv6->proto = IPPROTO_UDP;
3940 case RTE_FLOW_ITEM_TYPE_VXLAN:
3941 vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
3943 return rte_flow_error_set(error, EINVAL,
3944 RTE_FLOW_ERROR_TYPE_ACTION,
3945 (void *)items->type,
3946 "udp header not found");
3948 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
3949 if (!vxlan->vx_flags)
3951 RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
3953 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3954 vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
3956 return rte_flow_error_set(error, EINVAL,
3957 RTE_FLOW_ERROR_TYPE_ACTION,
3958 (void *)items->type,
3959 "udp header not found");
3960 if (!vxlan_gpe->proto)
3961 return rte_flow_error_set(error, EINVAL,
3962 RTE_FLOW_ERROR_TYPE_ACTION,
3963 (void *)items->type,
3964 "next protocol not found");
3967 RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
3968 if (!vxlan_gpe->vx_flags)
3969 vxlan_gpe->vx_flags =
3970 MLX5_ENCAP_VXLAN_GPE_FLAGS;
3972 case RTE_FLOW_ITEM_TYPE_GRE:
3973 case RTE_FLOW_ITEM_TYPE_NVGRE:
3974 gre = (struct rte_gre_hdr *)&buf[temp_size];
3976 return rte_flow_error_set(error, EINVAL,
3977 RTE_FLOW_ERROR_TYPE_ACTION,
3978 (void *)items->type,
3979 "next protocol not found");
3981 return rte_flow_error_set(error, EINVAL,
3982 RTE_FLOW_ERROR_TYPE_ACTION,
3983 (void *)items->type,
3984 "ip header not found");
3985 if (ipv4 && !ipv4->next_proto_id)
3986 ipv4->next_proto_id = IPPROTO_GRE;
3987 else if (ipv6 && !ipv6->proto)
3988 ipv6->proto = IPPROTO_GRE;
3990 case RTE_FLOW_ITEM_TYPE_VOID:
3993 return rte_flow_error_set(error, EINVAL,
3994 RTE_FLOW_ERROR_TYPE_ACTION,
3995 (void *)items->type,
3996 "unsupported item type");
4006 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
4008 struct rte_ether_hdr *eth = NULL;
4009 struct rte_vlan_hdr *vlan = NULL;
4010 struct rte_ipv6_hdr *ipv6 = NULL;
4011 struct rte_udp_hdr *udp = NULL;
4015 eth = (struct rte_ether_hdr *)data;
4016 next_hdr = (char *)(eth + 1);
4017 proto = RTE_BE16(eth->ether_type);
4020 while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
4021 vlan = (struct rte_vlan_hdr *)next_hdr;
4022 proto = RTE_BE16(vlan->eth_proto);
4023 next_hdr += sizeof(struct rte_vlan_hdr);
4026 /* HW calculates IPv4 csum. no need to proceed */
4027 if (proto == RTE_ETHER_TYPE_IPV4)
4030 /* non IPv4/IPv6 header. not supported */
4031 if (proto != RTE_ETHER_TYPE_IPV6) {
4032 return rte_flow_error_set(error, ENOTSUP,
4033 RTE_FLOW_ERROR_TYPE_ACTION,
4034 NULL, "Cannot offload non IPv4/IPv6");
4037 ipv6 = (struct rte_ipv6_hdr *)next_hdr;
4039 /* ignore non UDP */
4040 if (ipv6->proto != IPPROTO_UDP)
4043 udp = (struct rte_udp_hdr *)(ipv6 + 1);
4044 udp->dgram_cksum = 0;
4050 * Convert L2 encap action to DV specification.
4053 * Pointer to rte_eth_dev structure.
4055 * Pointer to action structure.
4056 * @param[in, out] dev_flow
4057 * Pointer to the mlx5_flow.
4058 * @param[in] transfer
4059 * Mark if the flow is E-Switch flow.
4061 * Pointer to the error structure.
4064 * 0 on success, a negative errno value otherwise and rte_errno is set.
4067 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
4068 const struct rte_flow_action *action,
4069 struct mlx5_flow *dev_flow,
4071 struct rte_flow_error *error)
4073 const struct rte_flow_item *encap_data;
4074 const struct rte_flow_action_raw_encap *raw_encap_data;
4075 struct mlx5_flow_dv_encap_decap_resource res = {
4077 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
4078 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
4079 MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
4082 if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
4084 (const struct rte_flow_action_raw_encap *)action->conf;
4085 res.size = raw_encap_data->size;
4086 memcpy(res.buf, raw_encap_data->data, res.size);
4088 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
4090 ((const struct rte_flow_action_vxlan_encap *)
4091 action->conf)->definition;
4094 ((const struct rte_flow_action_nvgre_encap *)
4095 action->conf)->definition;
4096 if (flow_dv_convert_encap_data(encap_data, res.buf,
4100 if (flow_dv_zero_encap_udp_csum(res.buf, error))
4102 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4103 return rte_flow_error_set(error, EINVAL,
4104 RTE_FLOW_ERROR_TYPE_ACTION,
4105 NULL, "can't create L2 encap action");
4110 * Convert L2 decap action to DV specification.
4113 * Pointer to rte_eth_dev structure.
4114 * @param[in, out] dev_flow
4115 * Pointer to the mlx5_flow.
4116 * @param[in] transfer
4117 * Mark if the flow is E-Switch flow.
4119 * Pointer to the error structure.
4122 * 0 on success, a negative errno value otherwise and rte_errno is set.
4125 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
4126 struct mlx5_flow *dev_flow,
4128 struct rte_flow_error *error)
4130 struct mlx5_flow_dv_encap_decap_resource res = {
4133 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
4134 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
4135 MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
4138 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4139 return rte_flow_error_set(error, EINVAL,
4140 RTE_FLOW_ERROR_TYPE_ACTION,
4141 NULL, "can't create L2 decap action");
4146 * Convert raw decap/encap (L3 tunnel) action to DV specification.
4149 * Pointer to rte_eth_dev structure.
4151 * Pointer to action structure.
4152 * @param[in, out] dev_flow
4153 * Pointer to the mlx5_flow.
4155 * Pointer to the flow attributes.
4157 * Pointer to the error structure.
4160 * 0 on success, a negative errno value otherwise and rte_errno is set.
4163 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
4164 const struct rte_flow_action *action,
4165 struct mlx5_flow *dev_flow,
4166 const struct rte_flow_attr *attr,
4167 struct rte_flow_error *error)
4169 const struct rte_flow_action_raw_encap *encap_data;
4170 struct mlx5_flow_dv_encap_decap_resource res;
4172 memset(&res, 0, sizeof(res));
4173 encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
4174 res.size = encap_data->size;
4175 memcpy(res.buf, encap_data->data, res.size);
4176 res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
4177 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
4178 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
4180 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
4182 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
4183 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
4184 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4185 return rte_flow_error_set(error, EINVAL,
4186 RTE_FLOW_ERROR_TYPE_ACTION,
4187 NULL, "can't create encap action");
4192 * Create action push VLAN.
4195 * Pointer to rte_eth_dev structure.
4197 * Pointer to the flow attributes.
4199 * Pointer to the vlan to push to the Ethernet header.
4200 * @param[in, out] dev_flow
4201 * Pointer to the mlx5_flow.
4203 * Pointer to the error structure.
4206 * 0 on success, a negative errno value otherwise and rte_errno is set.
4209 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
4210 const struct rte_flow_attr *attr,
4211 const struct rte_vlan_hdr *vlan,
4212 struct mlx5_flow *dev_flow,
4213 struct rte_flow_error *error)
4215 struct mlx5_flow_dv_push_vlan_action_resource res;
4217 memset(&res, 0, sizeof(res));
4219 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
4222 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
4224 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
4225 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
4226 return flow_dv_push_vlan_action_resource_register
4227 (dev, &res, dev_flow, error);
4231 * Validate the modify-header actions.
4233 * @param[in] action_flags
4234 * Holds the actions detected until now.
4236 * Pointer to the modify action.
4238 * Pointer to error structure.
4241 * 0 on success, a negative errno value otherwise and rte_errno is set.
4244 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
4245 const struct rte_flow_action *action,
4246 struct rte_flow_error *error)
4248 if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
4249 return rte_flow_error_set(error, EINVAL,
4250 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4251 NULL, "action configuration not set");
4252 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
4253 return rte_flow_error_set(error, EINVAL,
4254 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4255 "can't have encap action before"
4261 * Validate the modify-header MAC address actions.
4263 * @param[in] action_flags
4264 * Holds the actions detected until now.
4266 * Pointer to the modify action.
4267 * @param[in] item_flags
4268 * Holds the items detected.
4270 * Pointer to error structure.
4273 * 0 on success, a negative errno value otherwise and rte_errno is set.
4276 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
4277 const struct rte_flow_action *action,
4278 const uint64_t item_flags,
4279 struct rte_flow_error *error)
4283 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4285 if (!(item_flags & MLX5_FLOW_LAYER_L2))
4286 return rte_flow_error_set(error, EINVAL,
4287 RTE_FLOW_ERROR_TYPE_ACTION,
4289 "no L2 item in pattern");
4295 * Validate the modify-header IPv4 address actions.
4297 * @param[in] action_flags
4298 * Holds the actions detected until now.
4300 * Pointer to the modify action.
4301 * @param[in] item_flags
4302 * Holds the items detected.
4304 * Pointer to error structure.
4307 * 0 on success, a negative errno value otherwise and rte_errno is set.
4310 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
4311 const struct rte_flow_action *action,
4312 const uint64_t item_flags,
4313 struct rte_flow_error *error)
4318 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4320 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4321 MLX5_FLOW_LAYER_INNER_L3_IPV4 :
4322 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
4323 if (!(item_flags & layer))
4324 return rte_flow_error_set(error, EINVAL,
4325 RTE_FLOW_ERROR_TYPE_ACTION,
4327 "no ipv4 item in pattern");
4333 * Validate the modify-header IPv6 address actions.
4335 * @param[in] action_flags
4336 * Holds the actions detected until now.
4338 * Pointer to the modify action.
4339 * @param[in] item_flags
4340 * Holds the items detected.
4342 * Pointer to error structure.
4345 * 0 on success, a negative errno value otherwise and rte_errno is set.
4348 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
4349 const struct rte_flow_action *action,
4350 const uint64_t item_flags,
4351 struct rte_flow_error *error)
4356 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4358 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4359 MLX5_FLOW_LAYER_INNER_L3_IPV6 :
4360 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
4361 if (!(item_flags & layer))
4362 return rte_flow_error_set(error, EINVAL,
4363 RTE_FLOW_ERROR_TYPE_ACTION,
4365 "no ipv6 item in pattern");
4371 * Validate the modify-header TP actions.
4373 * @param[in] action_flags
4374 * Holds the actions detected until now.
4376 * Pointer to the modify action.
4377 * @param[in] item_flags
4378 * Holds the items detected.
4380 * Pointer to error structure.
4383 * 0 on success, a negative errno value otherwise and rte_errno is set.
4386 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
4387 const struct rte_flow_action *action,
4388 const uint64_t item_flags,
4389 struct rte_flow_error *error)
4394 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4396 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4397 MLX5_FLOW_LAYER_INNER_L4 :
4398 MLX5_FLOW_LAYER_OUTER_L4;
4399 if (!(item_flags & layer))
4400 return rte_flow_error_set(error, EINVAL,
4401 RTE_FLOW_ERROR_TYPE_ACTION,
4402 NULL, "no transport layer "
4409 * Validate the modify-header actions of increment/decrement
4410 * TCP Sequence-number.
4412 * @param[in] action_flags
4413 * Holds the actions detected until now.
4415 * Pointer to the modify action.
4416 * @param[in] item_flags
4417 * Holds the items detected.
4419 * Pointer to error structure.
4422 * 0 on success, a negative errno value otherwise and rte_errno is set.
4425 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
4426 const struct rte_flow_action *action,
4427 const uint64_t item_flags,
4428 struct rte_flow_error *error)
4433 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4435 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4436 MLX5_FLOW_LAYER_INNER_L4_TCP :
4437 MLX5_FLOW_LAYER_OUTER_L4_TCP;
4438 if (!(item_flags & layer))
4439 return rte_flow_error_set(error, EINVAL,
4440 RTE_FLOW_ERROR_TYPE_ACTION,
4441 NULL, "no TCP item in"
4443 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
4444 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
4445 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
4446 (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
4447 return rte_flow_error_set(error, EINVAL,
4448 RTE_FLOW_ERROR_TYPE_ACTION,
4450 "cannot decrease and increase"
4451 " TCP sequence number"
4452 " at the same time");
4458 * Validate the modify-header actions of increment/decrement
4459 * TCP Acknowledgment number.
4461 * @param[in] action_flags
4462 * Holds the actions detected until now.
4464 * Pointer to the modify action.
4465 * @param[in] item_flags
4466 * Holds the items detected.
4468 * Pointer to error structure.
4471 * 0 on success, a negative errno value otherwise and rte_errno is set.
4474 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
4475 const struct rte_flow_action *action,
4476 const uint64_t item_flags,
4477 struct rte_flow_error *error)
4482 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4484 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4485 MLX5_FLOW_LAYER_INNER_L4_TCP :
4486 MLX5_FLOW_LAYER_OUTER_L4_TCP;
4487 if (!(item_flags & layer))
4488 return rte_flow_error_set(error, EINVAL,
4489 RTE_FLOW_ERROR_TYPE_ACTION,
4490 NULL, "no TCP item in"
4492 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
4493 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
4494 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
4495 (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
4496 return rte_flow_error_set(error, EINVAL,
4497 RTE_FLOW_ERROR_TYPE_ACTION,
4499 "cannot decrease and increase"
4500 " TCP acknowledgment number"
4501 " at the same time");
4507 * Validate the modify-header TTL actions.
4509 * @param[in] action_flags
4510 * Holds the actions detected until now.
4512 * Pointer to the modify action.
4513 * @param[in] item_flags
4514 * Holds the items detected.
4516 * Pointer to error structure.
4519 * 0 on success, a negative errno value otherwise and rte_errno is set.
4522 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
4523 const struct rte_flow_action *action,
4524 const uint64_t item_flags,
4525 struct rte_flow_error *error)
4530 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4532 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4533 MLX5_FLOW_LAYER_INNER_L3 :
4534 MLX5_FLOW_LAYER_OUTER_L3;
4535 if (!(item_flags & layer))
4536 return rte_flow_error_set(error, EINVAL,
4537 RTE_FLOW_ERROR_TYPE_ACTION,
4539 "no IP protocol in pattern");
4545 * Validate the generic modify field actions.
4547 * Pointer to the rte_eth_dev structure.
4548 * @param[in] action_flags
4549 * Holds the actions detected until now.
4551 * Pointer to the modify action.
4553 * Pointer to the flow attributes.
4555 * Pointer to error structure.
4558 * Number of header fields to modify (0 or more) on success,
4559 * a negative errno value otherwise and rte_errno is set.
4562 flow_dv_validate_action_modify_field(struct rte_eth_dev *dev,
4563 const uint64_t action_flags,
4564 const struct rte_flow_action *action,
4565 const struct rte_flow_attr *attr,
4566 struct rte_flow_error *error)
4569 struct mlx5_priv *priv = dev->data->dev_private;
4570 struct mlx5_dev_config *config = &priv->config;
4571 const struct rte_flow_action_modify_field *action_modify_field =
4573 uint32_t dst_width =
4574 mlx5_flow_item_field_width(action_modify_field->dst.field);
4575 uint32_t src_width =
4576 mlx5_flow_item_field_width(action_modify_field->src.field);
4578 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4582 if (action_modify_field->width == 0)
4583 return rte_flow_error_set(error, EINVAL,
4584 RTE_FLOW_ERROR_TYPE_ACTION, action,
4585 "no bits are requested to be modified");
4586 else if (action_modify_field->width > dst_width ||
4587 action_modify_field->width > src_width)
4588 return rte_flow_error_set(error, EINVAL,
4589 RTE_FLOW_ERROR_TYPE_ACTION, action,
4590 "cannot modify more bits than"
4591 " the width of a field");
4592 if (action_modify_field->dst.field != RTE_FLOW_FIELD_VALUE &&
4593 action_modify_field->dst.field != RTE_FLOW_FIELD_POINTER) {
4594 if ((action_modify_field->dst.offset +
4595 action_modify_field->width > dst_width) ||
4596 (action_modify_field->dst.offset % 32))
4597 return rte_flow_error_set(error, EINVAL,
4598 RTE_FLOW_ERROR_TYPE_ACTION, action,
4599 "destination offset is too big"
4600 " or not aligned to 4 bytes");
4601 if (action_modify_field->dst.level &&
4602 action_modify_field->dst.field != RTE_FLOW_FIELD_TAG)
4603 return rte_flow_error_set(error, ENOTSUP,
4604 RTE_FLOW_ERROR_TYPE_ACTION, action,
4605 "inner header fields modification"
4606 " is not supported");
4608 if (action_modify_field->src.field != RTE_FLOW_FIELD_VALUE &&
4609 action_modify_field->src.field != RTE_FLOW_FIELD_POINTER) {
4610 if (!attr->transfer && !attr->group)
4611 return rte_flow_error_set(error, ENOTSUP,
4612 RTE_FLOW_ERROR_TYPE_ACTION, action,
4613 "modify field action is not"
4614 " supported for group 0");
4615 if ((action_modify_field->src.offset +
4616 action_modify_field->width > src_width) ||
4617 (action_modify_field->src.offset % 32))
4618 return rte_flow_error_set(error, EINVAL,
4619 RTE_FLOW_ERROR_TYPE_ACTION, action,
4620 "source offset is too big"
4621 " or not aligned to 4 bytes");
4622 if (action_modify_field->src.level &&
4623 action_modify_field->src.field != RTE_FLOW_FIELD_TAG)
4624 return rte_flow_error_set(error, ENOTSUP,
4625 RTE_FLOW_ERROR_TYPE_ACTION, action,
4626 "inner header fields modification"
4627 " is not supported");
4629 if (action_modify_field->dst.field ==
4630 action_modify_field->src.field)
4631 return rte_flow_error_set(error, EINVAL,
4632 RTE_FLOW_ERROR_TYPE_ACTION, action,
4633 "source and destination fields"
4634 " cannot be the same");
4635 if (action_modify_field->dst.field == RTE_FLOW_FIELD_VALUE ||
4636 action_modify_field->dst.field == RTE_FLOW_FIELD_POINTER)
4637 return rte_flow_error_set(error, EINVAL,
4638 RTE_FLOW_ERROR_TYPE_ACTION, action,
4639 "immediate value or a pointer to it"
4640 " cannot be used as a destination");
4641 if (action_modify_field->dst.field == RTE_FLOW_FIELD_START ||
4642 action_modify_field->src.field == RTE_FLOW_FIELD_START)
4643 return rte_flow_error_set(error, ENOTSUP,
4644 RTE_FLOW_ERROR_TYPE_ACTION, action,
4645 "modifications of an arbitrary"
4646 " place in a packet is not supported");
4647 if (action_modify_field->dst.field == RTE_FLOW_FIELD_VLAN_TYPE ||
4648 action_modify_field->src.field == RTE_FLOW_FIELD_VLAN_TYPE)
4649 return rte_flow_error_set(error, ENOTSUP,
4650 RTE_FLOW_ERROR_TYPE_ACTION, action,
4651 "modifications of the 802.1Q Tag"
4652 " Identifier is not supported");
4653 if (action_modify_field->dst.field == RTE_FLOW_FIELD_VXLAN_VNI ||
4654 action_modify_field->src.field == RTE_FLOW_FIELD_VXLAN_VNI)
4655 return rte_flow_error_set(error, ENOTSUP,
4656 RTE_FLOW_ERROR_TYPE_ACTION, action,
4657 "modifications of the VXLAN Network"
4658 " Identifier is not supported");
4659 if (action_modify_field->dst.field == RTE_FLOW_FIELD_GENEVE_VNI ||
4660 action_modify_field->src.field == RTE_FLOW_FIELD_GENEVE_VNI)
4661 return rte_flow_error_set(error, ENOTSUP,
4662 RTE_FLOW_ERROR_TYPE_ACTION, action,
4663 "modifications of the GENEVE Network"
4664 " Identifier is not supported");
4665 if (action_modify_field->dst.field == RTE_FLOW_FIELD_MARK ||
4666 action_modify_field->src.field == RTE_FLOW_FIELD_MARK ||
4667 action_modify_field->dst.field == RTE_FLOW_FIELD_META ||
4668 action_modify_field->src.field == RTE_FLOW_FIELD_META) {
4669 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY ||
4670 !mlx5_flow_ext_mreg_supported(dev))
4671 return rte_flow_error_set(error, ENOTSUP,
4672 RTE_FLOW_ERROR_TYPE_ACTION, action,
4673 "cannot modify mark or metadata without"
4674 " extended metadata register support");
4676 if (action_modify_field->operation != RTE_FLOW_MODIFY_SET)
4677 return rte_flow_error_set(error, ENOTSUP,
4678 RTE_FLOW_ERROR_TYPE_ACTION, action,
4679 "add and sub operations"
4680 " are not supported");
4681 return (action_modify_field->width / 32) +
4682 !!(action_modify_field->width % 32);
4686 * Validate jump action.
4689 * Pointer to the jump action.
4690 * @param[in] action_flags
4691 * Holds the actions detected until now.
4692 * @param[in] attributes
4693 * Pointer to flow attributes
4694 * @param[in] external
4695 * Action belongs to flow rule created by request external to PMD.
4697 * Pointer to error structure.
4700 * 0 on success, a negative errno value otherwise and rte_errno is set.
4703 flow_dv_validate_action_jump(struct rte_eth_dev *dev,
4704 const struct mlx5_flow_tunnel *tunnel,
4705 const struct rte_flow_action *action,
4706 uint64_t action_flags,
4707 const struct rte_flow_attr *attributes,
4708 bool external, struct rte_flow_error *error)
4710 uint32_t target_group, table;
4712 struct flow_grp_info grp_info = {
4713 .external = !!external,
4714 .transfer = !!attributes->transfer,
4718 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
4719 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4720 return rte_flow_error_set(error, EINVAL,
4721 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4722 "can't have 2 fate actions in"
4724 if (action_flags & MLX5_FLOW_ACTION_METER)
4725 return rte_flow_error_set(error, ENOTSUP,
4726 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4727 "jump with meter not support");
4729 return rte_flow_error_set(error, EINVAL,
4730 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4731 NULL, "action configuration not set");
4733 ((const struct rte_flow_action_jump *)action->conf)->group;
4734 ret = mlx5_flow_group_to_table(dev, tunnel, target_group, &table,
4738 if (attributes->group == target_group &&
4739 !(action_flags & (MLX5_FLOW_ACTION_TUNNEL_SET |
4740 MLX5_FLOW_ACTION_TUNNEL_MATCH)))
4741 return rte_flow_error_set(error, EINVAL,
4742 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4743 "target group must be other than"
4744 " the current flow group");
4749 * Validate the port_id action.
4752 * Pointer to rte_eth_dev structure.
4753 * @param[in] action_flags
4754 * Bit-fields that holds the actions detected until now.
4756 * Port_id RTE action structure.
4758 * Attributes of flow that includes this action.
4760 * Pointer to error structure.
4763 * 0 on success, a negative errno value otherwise and rte_errno is set.
4766 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
4767 uint64_t action_flags,
4768 const struct rte_flow_action *action,
4769 const struct rte_flow_attr *attr,
4770 struct rte_flow_error *error)
4772 const struct rte_flow_action_port_id *port_id;
4773 struct mlx5_priv *act_priv;
4774 struct mlx5_priv *dev_priv;
4777 if (!attr->transfer)
4778 return rte_flow_error_set(error, ENOTSUP,
4779 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4781 "port id action is valid in transfer"
4783 if (!action || !action->conf)
4784 return rte_flow_error_set(error, ENOTSUP,
4785 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4787 "port id action parameters must be"
4789 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
4790 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4791 return rte_flow_error_set(error, EINVAL,
4792 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4793 "can have only one fate actions in"
4795 dev_priv = mlx5_dev_to_eswitch_info(dev);
4797 return rte_flow_error_set(error, rte_errno,
4798 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4800 "failed to obtain E-Switch info");
4801 port_id = action->conf;
4802 port = port_id->original ? dev->data->port_id : port_id->id;
4803 act_priv = mlx5_port_to_eswitch_info(port, false);
4805 return rte_flow_error_set
4807 RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
4808 "failed to obtain E-Switch port id for port");
4809 if (act_priv->domain_id != dev_priv->domain_id)
4810 return rte_flow_error_set
4812 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4813 "port does not belong to"
4814 " E-Switch being configured");
4819 * Get the maximum number of modify header actions.
4822 * Pointer to rte_eth_dev structure.
4824 * Flags bits to check if root level.
4827 * Max number of modify header actions device can support.
4829 static inline unsigned int
4830 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev __rte_unused,
4834 * There's no way to directly query the max capacity from FW.
4835 * The maximal value on root table should be assumed to be supported.
4837 if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
4838 return MLX5_MAX_MODIFY_NUM;
4840 return MLX5_ROOT_TBL_MODIFY_NUM;
4844 * Validate the meter action.
4847 * Pointer to rte_eth_dev structure.
4848 * @param[in] action_flags
4849 * Bit-fields that holds the actions detected until now.
4851 * Pointer to the meter action.
4853 * Attributes of flow that includes this action.
4855 * Pointer to error structure.
4858 * 0 on success, a negative errno value otherwise and rte_ernno is set.
4861 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
4862 uint64_t action_flags,
4863 const struct rte_flow_action *action,
4864 const struct rte_flow_attr *attr,
4865 struct rte_flow_error *error)
4867 struct mlx5_priv *priv = dev->data->dev_private;
4868 const struct rte_flow_action_meter *am = action->conf;
4869 struct mlx5_flow_meter *fm;
4872 return rte_flow_error_set(error, EINVAL,
4873 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4874 "meter action conf is NULL");
4876 if (action_flags & MLX5_FLOW_ACTION_METER)
4877 return rte_flow_error_set(error, ENOTSUP,
4878 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4879 "meter chaining not support");
4880 if (action_flags & MLX5_FLOW_ACTION_JUMP)
4881 return rte_flow_error_set(error, ENOTSUP,
4882 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4883 "meter with jump not support");
4885 return rte_flow_error_set(error, ENOTSUP,
4886 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4888 "meter action not supported");
4889 fm = mlx5_flow_meter_find(priv, am->mtr_id);
4891 return rte_flow_error_set(error, EINVAL,
4892 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4894 if (fm->ref_cnt && (!(fm->transfer == attr->transfer ||
4895 (!fm->ingress && !attr->ingress && attr->egress) ||
4896 (!fm->egress && !attr->egress && attr->ingress))))
4897 return rte_flow_error_set(error, EINVAL,
4898 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4899 "Flow attributes are either invalid "
4900 "or have a conflict with current "
4901 "meter attributes");
4906 * Validate the age action.
4908 * @param[in] action_flags
4909 * Holds the actions detected until now.
4911 * Pointer to the age action.
4913 * Pointer to the Ethernet device structure.
4915 * Pointer to error structure.
4918 * 0 on success, a negative errno value otherwise and rte_errno is set.
4921 flow_dv_validate_action_age(uint64_t action_flags,
4922 const struct rte_flow_action *action,
4923 struct rte_eth_dev *dev,
4924 struct rte_flow_error *error)
4926 struct mlx5_priv *priv = dev->data->dev_private;
4927 const struct rte_flow_action_age *age = action->conf;
4929 if (!priv->config.devx || (priv->sh->cmng.counter_fallback &&
4930 !priv->sh->aso_age_mng))
4931 return rte_flow_error_set(error, ENOTSUP,
4932 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4934 "age action not supported");
4935 if (!(action->conf))
4936 return rte_flow_error_set(error, EINVAL,
4937 RTE_FLOW_ERROR_TYPE_ACTION, action,
4938 "configuration cannot be null");
4939 if (!(age->timeout))
4940 return rte_flow_error_set(error, EINVAL,
4941 RTE_FLOW_ERROR_TYPE_ACTION, action,
4942 "invalid timeout value 0");
4943 if (action_flags & MLX5_FLOW_ACTION_AGE)
4944 return rte_flow_error_set(error, EINVAL,
4945 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4946 "duplicate age actions set");
4951 * Validate the modify-header IPv4 DSCP actions.
4953 * @param[in] action_flags
4954 * Holds the actions detected until now.
4956 * Pointer to the modify action.
4957 * @param[in] item_flags
4958 * Holds the items detected.
4960 * Pointer to error structure.
4963 * 0 on success, a negative errno value otherwise and rte_errno is set.
4966 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
4967 const struct rte_flow_action *action,
4968 const uint64_t item_flags,
4969 struct rte_flow_error *error)
4973 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4975 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
4976 return rte_flow_error_set(error, EINVAL,
4977 RTE_FLOW_ERROR_TYPE_ACTION,
4979 "no ipv4 item in pattern");
4985 * Validate the modify-header IPv6 DSCP actions.
4987 * @param[in] action_flags
4988 * Holds the actions detected until now.
4990 * Pointer to the modify action.
4991 * @param[in] item_flags
4992 * Holds the items detected.
4994 * Pointer to error structure.
4997 * 0 on success, a negative errno value otherwise and rte_errno is set.
5000 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
5001 const struct rte_flow_action *action,
5002 const uint64_t item_flags,
5003 struct rte_flow_error *error)
5007 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
5009 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
5010 return rte_flow_error_set(error, EINVAL,
5011 RTE_FLOW_ERROR_TYPE_ACTION,
5013 "no ipv6 item in pattern");
5019 * Match modify-header resource.
5022 * Pointer to the hash list.
5024 * Pointer to exist resource entry object.
5026 * Key of the new entry.
5028 * Pointer to new modify-header resource.
5031 * 0 on matching, non-zero otherwise.
5034 flow_dv_modify_match_cb(struct mlx5_hlist *list __rte_unused,
5035 struct mlx5_hlist_entry *entry,
5036 uint64_t key __rte_unused, void *cb_ctx)
5038 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5039 struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5040 struct mlx5_flow_dv_modify_hdr_resource *resource =
5041 container_of(entry, typeof(*resource), entry);
5042 uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
5044 key_len += ref->actions_num * sizeof(ref->actions[0]);
5045 return ref->actions_num != resource->actions_num ||
5046 memcmp(&ref->ft_type, &resource->ft_type, key_len);
5049 struct mlx5_hlist_entry *
5050 flow_dv_modify_create_cb(struct mlx5_hlist *list, uint64_t key __rte_unused,
5053 struct mlx5_dev_ctx_shared *sh = list->ctx;
5054 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5055 struct mlx5dv_dr_domain *ns;
5056 struct mlx5_flow_dv_modify_hdr_resource *entry;
5057 struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5059 uint32_t data_len = ref->actions_num * sizeof(ref->actions[0]);
5060 uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
5062 entry = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*entry) + data_len, 0,
5065 rte_flow_error_set(ctx->error, ENOMEM,
5066 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5067 "cannot allocate resource memory");
5070 rte_memcpy(&entry->ft_type,
5071 RTE_PTR_ADD(ref, offsetof(typeof(*ref), ft_type)),
5072 key_len + data_len);
5073 if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
5074 ns = sh->fdb_domain;
5075 else if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
5079 ret = mlx5_flow_os_create_flow_action_modify_header
5080 (sh->ctx, ns, entry,
5081 data_len, &entry->action);
5084 rte_flow_error_set(ctx->error, ENOMEM,
5085 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5086 NULL, "cannot create modification action");
5089 return &entry->entry;
5093 * Validate the sample action.
5095 * @param[in, out] action_flags
5096 * Holds the actions detected until now.
5098 * Pointer to the sample action.
5100 * Pointer to the Ethernet device structure.
5102 * Attributes of flow that includes this action.
5103 * @param[in] item_flags
5104 * Holds the items detected.
5106 * Pointer to the RSS action.
5107 * @param[out] sample_rss
5108 * Pointer to the RSS action in sample action list.
5110 * Pointer to the COUNT action in sample action list.
5111 * @param[out] fdb_mirror_limit
5112 * Pointer to the FDB mirror limitation flag.
5114 * Pointer to error structure.
5117 * 0 on success, a negative errno value otherwise and rte_errno is set.
5120 flow_dv_validate_action_sample(uint64_t *action_flags,
5121 const struct rte_flow_action *action,
5122 struct rte_eth_dev *dev,
5123 const struct rte_flow_attr *attr,
5124 uint64_t item_flags,
5125 const struct rte_flow_action_rss *rss,
5126 const struct rte_flow_action_rss **sample_rss,
5127 const struct rte_flow_action_count **count,
5128 int *fdb_mirror_limit,
5129 struct rte_flow_error *error)
5131 struct mlx5_priv *priv = dev->data->dev_private;
5132 struct mlx5_dev_config *dev_conf = &priv->config;
5133 const struct rte_flow_action_sample *sample = action->conf;
5134 const struct rte_flow_action *act;
5135 uint64_t sub_action_flags = 0;
5136 uint16_t queue_index = 0xFFFF;
5141 return rte_flow_error_set(error, EINVAL,
5142 RTE_FLOW_ERROR_TYPE_ACTION, action,
5143 "configuration cannot be NULL");
5144 if (sample->ratio == 0)
5145 return rte_flow_error_set(error, EINVAL,
5146 RTE_FLOW_ERROR_TYPE_ACTION, action,
5147 "ratio value starts from 1");
5148 if (!priv->config.devx || (sample->ratio > 0 && !priv->sampler_en))
5149 return rte_flow_error_set(error, ENOTSUP,
5150 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5152 "sample action not supported");
5153 if (*action_flags & MLX5_FLOW_ACTION_SAMPLE)
5154 return rte_flow_error_set(error, EINVAL,
5155 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5156 "Multiple sample actions not "
5158 if (*action_flags & MLX5_FLOW_ACTION_METER)
5159 return rte_flow_error_set(error, EINVAL,
5160 RTE_FLOW_ERROR_TYPE_ACTION, action,
5161 "wrong action order, meter should "
5162 "be after sample action");
5163 if (*action_flags & MLX5_FLOW_ACTION_JUMP)
5164 return rte_flow_error_set(error, EINVAL,
5165 RTE_FLOW_ERROR_TYPE_ACTION, action,
5166 "wrong action order, jump should "
5167 "be after sample action");
5168 act = sample->actions;
5169 for (; act->type != RTE_FLOW_ACTION_TYPE_END; act++) {
5170 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
5171 return rte_flow_error_set(error, ENOTSUP,
5172 RTE_FLOW_ERROR_TYPE_ACTION,
5173 act, "too many actions");
5174 switch (act->type) {
5175 case RTE_FLOW_ACTION_TYPE_QUEUE:
5176 ret = mlx5_flow_validate_action_queue(act,
5182 queue_index = ((const struct rte_flow_action_queue *)
5183 (act->conf))->index;
5184 sub_action_flags |= MLX5_FLOW_ACTION_QUEUE;
5187 case RTE_FLOW_ACTION_TYPE_RSS:
5188 *sample_rss = act->conf;
5189 ret = mlx5_flow_validate_action_rss(act,
5196 if (rss && *sample_rss &&
5197 ((*sample_rss)->level != rss->level ||
5198 (*sample_rss)->types != rss->types))
5199 return rte_flow_error_set(error, ENOTSUP,
5200 RTE_FLOW_ERROR_TYPE_ACTION,
5202 "Can't use the different RSS types "
5203 "or level in the same flow");
5204 if (*sample_rss != NULL && (*sample_rss)->queue_num)
5205 queue_index = (*sample_rss)->queue[0];
5206 sub_action_flags |= MLX5_FLOW_ACTION_RSS;
5209 case RTE_FLOW_ACTION_TYPE_MARK:
5210 ret = flow_dv_validate_action_mark(dev, act,
5215 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY)
5216 sub_action_flags |= MLX5_FLOW_ACTION_MARK |
5217 MLX5_FLOW_ACTION_MARK_EXT;
5219 sub_action_flags |= MLX5_FLOW_ACTION_MARK;
5222 case RTE_FLOW_ACTION_TYPE_COUNT:
5223 ret = flow_dv_validate_action_count
5225 *action_flags | sub_action_flags,
5230 sub_action_flags |= MLX5_FLOW_ACTION_COUNT;
5231 *action_flags |= MLX5_FLOW_ACTION_COUNT;
5234 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5235 ret = flow_dv_validate_action_port_id(dev,
5242 sub_action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5245 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5246 ret = flow_dv_validate_action_raw_encap_decap
5247 (dev, NULL, act->conf, attr, &sub_action_flags,
5248 &actions_n, action, item_flags, error);
5253 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5254 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5255 ret = flow_dv_validate_action_l2_encap(dev,
5261 sub_action_flags |= MLX5_FLOW_ACTION_ENCAP;
5265 return rte_flow_error_set(error, ENOTSUP,
5266 RTE_FLOW_ERROR_TYPE_ACTION,
5268 "Doesn't support optional "
5272 if (attr->ingress && !attr->transfer) {
5273 if (!(sub_action_flags & (MLX5_FLOW_ACTION_QUEUE |
5274 MLX5_FLOW_ACTION_RSS)))
5275 return rte_flow_error_set(error, EINVAL,
5276 RTE_FLOW_ERROR_TYPE_ACTION,
5278 "Ingress must has a dest "
5279 "QUEUE for Sample");
5280 } else if (attr->egress && !attr->transfer) {
5281 return rte_flow_error_set(error, ENOTSUP,
5282 RTE_FLOW_ERROR_TYPE_ACTION,
5284 "Sample Only support Ingress "
5286 } else if (sample->actions->type != RTE_FLOW_ACTION_TYPE_END) {
5287 MLX5_ASSERT(attr->transfer);
5288 if (sample->ratio > 1)
5289 return rte_flow_error_set(error, ENOTSUP,
5290 RTE_FLOW_ERROR_TYPE_ACTION,
5292 "E-Switch doesn't support "
5293 "any optional action "
5295 if (sub_action_flags & MLX5_FLOW_ACTION_QUEUE)
5296 return rte_flow_error_set(error, ENOTSUP,
5297 RTE_FLOW_ERROR_TYPE_ACTION,
5299 "unsupported action QUEUE");
5300 if (sub_action_flags & MLX5_FLOW_ACTION_RSS)
5301 return rte_flow_error_set(error, ENOTSUP,
5302 RTE_FLOW_ERROR_TYPE_ACTION,
5304 "unsupported action QUEUE");
5305 if (!(sub_action_flags & MLX5_FLOW_ACTION_PORT_ID))
5306 return rte_flow_error_set(error, EINVAL,
5307 RTE_FLOW_ERROR_TYPE_ACTION,
5309 "E-Switch must has a dest "
5310 "port for mirroring");
5311 if (!priv->config.hca_attr.reg_c_preserve &&
5312 priv->representor_id != -1)
5313 *fdb_mirror_limit = 1;
5315 /* Continue validation for Xcap actions.*/
5316 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) &&
5317 (queue_index == 0xFFFF ||
5318 mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
5319 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
5320 MLX5_FLOW_XCAP_ACTIONS)
5321 return rte_flow_error_set(error, ENOTSUP,
5322 RTE_FLOW_ERROR_TYPE_ACTION,
5323 NULL, "encap and decap "
5324 "combination aren't "
5326 if (!attr->transfer && attr->ingress && (sub_action_flags &
5327 MLX5_FLOW_ACTION_ENCAP))
5328 return rte_flow_error_set(error, ENOTSUP,
5329 RTE_FLOW_ERROR_TYPE_ACTION,
5330 NULL, "encap is not supported"
5331 " for ingress traffic");
5337 * Find existing modify-header resource or create and register a new one.
5339 * @param dev[in, out]
5340 * Pointer to rte_eth_dev structure.
5341 * @param[in, out] resource
5342 * Pointer to modify-header resource.
5343 * @parm[in, out] dev_flow
5344 * Pointer to the dev_flow.
5346 * pointer to error structure.
5349 * 0 on success otherwise -errno and errno is set.
5352 flow_dv_modify_hdr_resource_register
5353 (struct rte_eth_dev *dev,
5354 struct mlx5_flow_dv_modify_hdr_resource *resource,
5355 struct mlx5_flow *dev_flow,
5356 struct rte_flow_error *error)
5358 struct mlx5_priv *priv = dev->data->dev_private;
5359 struct mlx5_dev_ctx_shared *sh = priv->sh;
5360 uint32_t key_len = sizeof(*resource) -
5361 offsetof(typeof(*resource), ft_type) +
5362 resource->actions_num * sizeof(resource->actions[0]);
5363 struct mlx5_hlist_entry *entry;
5364 struct mlx5_flow_cb_ctx ctx = {
5370 resource->flags = dev_flow->dv.group ? 0 :
5371 MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
5372 if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
5374 return rte_flow_error_set(error, EOVERFLOW,
5375 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5376 "too many modify header items");
5377 key64 = __rte_raw_cksum(&resource->ft_type, key_len, 0);
5378 entry = mlx5_hlist_register(sh->modify_cmds, key64, &ctx);
5381 resource = container_of(entry, typeof(*resource), entry);
5382 dev_flow->handle->dvh.modify_hdr = resource;
5387 * Get DV flow counter by index.
5390 * Pointer to the Ethernet device structure.
5392 * mlx5 flow counter index in the container.
5394 * mlx5 flow counter pool in the container,
5397 * Pointer to the counter, NULL otherwise.
5399 static struct mlx5_flow_counter *
5400 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
5402 struct mlx5_flow_counter_pool **ppool)
5404 struct mlx5_priv *priv = dev->data->dev_private;
5405 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5406 struct mlx5_flow_counter_pool *pool;
5408 /* Decrease to original index and clear shared bit. */
5409 idx = (idx - 1) & (MLX5_CNT_SHARED_OFFSET - 1);
5410 MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cmng->n);
5411 pool = cmng->pools[idx / MLX5_COUNTERS_PER_POOL];
5415 return MLX5_POOL_GET_CNT(pool, idx % MLX5_COUNTERS_PER_POOL);
5419 * Check the devx counter belongs to the pool.
5422 * Pointer to the counter pool.
5424 * The counter devx ID.
5427 * True if counter belongs to the pool, false otherwise.
5430 flow_dv_is_counter_in_pool(struct mlx5_flow_counter_pool *pool, int id)
5432 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
5433 MLX5_COUNTERS_PER_POOL;
5435 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
5441 * Get a pool by devx counter ID.
5444 * Pointer to the counter management.
5446 * The counter devx ID.
5449 * The counter pool pointer if exists, NULL otherwise,
5451 static struct mlx5_flow_counter_pool *
5452 flow_dv_find_pool_by_id(struct mlx5_flow_counter_mng *cmng, int id)
5455 struct mlx5_flow_counter_pool *pool = NULL;
5457 rte_spinlock_lock(&cmng->pool_update_sl);
5458 /* Check last used pool. */
5459 if (cmng->last_pool_idx != POOL_IDX_INVALID &&
5460 flow_dv_is_counter_in_pool(cmng->pools[cmng->last_pool_idx], id)) {
5461 pool = cmng->pools[cmng->last_pool_idx];
5464 /* ID out of range means no suitable pool in the container. */
5465 if (id > cmng->max_id || id < cmng->min_id)
5468 * Find the pool from the end of the container, since mostly counter
5469 * ID is sequence increasing, and the last pool should be the needed
5474 struct mlx5_flow_counter_pool *pool_tmp = cmng->pools[i];
5476 if (flow_dv_is_counter_in_pool(pool_tmp, id)) {
5482 rte_spinlock_unlock(&cmng->pool_update_sl);
5487 * Resize a counter container.
5490 * Pointer to the Ethernet device structure.
5493 * 0 on success, otherwise negative errno value and rte_errno is set.
5496 flow_dv_container_resize(struct rte_eth_dev *dev)
5498 struct mlx5_priv *priv = dev->data->dev_private;
5499 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5500 void *old_pools = cmng->pools;
5501 uint32_t resize = cmng->n + MLX5_CNT_CONTAINER_RESIZE;
5502 uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
5503 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
5510 memcpy(pools, old_pools, cmng->n *
5511 sizeof(struct mlx5_flow_counter_pool *));
5513 cmng->pools = pools;
5515 mlx5_free(old_pools);
5520 * Query a devx flow counter.
5523 * Pointer to the Ethernet device structure.
5525 * Index to the flow counter.
5527 * The statistics value of packets.
5529 * The statistics value of bytes.
5532 * 0 on success, otherwise a negative errno value and rte_errno is set.
5535 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
5538 struct mlx5_priv *priv = dev->data->dev_private;
5539 struct mlx5_flow_counter_pool *pool = NULL;
5540 struct mlx5_flow_counter *cnt;
5543 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
5545 if (priv->sh->cmng.counter_fallback)
5546 return mlx5_devx_cmd_flow_counter_query(cnt->dcs_when_active, 0,
5547 0, pkts, bytes, 0, NULL, NULL, 0);
5548 rte_spinlock_lock(&pool->sl);
5553 offset = MLX5_CNT_ARRAY_IDX(pool, cnt);
5554 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
5555 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
5557 rte_spinlock_unlock(&pool->sl);
5562 * Create and initialize a new counter pool.
5565 * Pointer to the Ethernet device structure.
5567 * The devX counter handle.
5569 * Whether the pool is for counter that was allocated for aging.
5570 * @param[in/out] cont_cur
5571 * Pointer to the container pointer, it will be update in pool resize.
5574 * The pool container pointer on success, NULL otherwise and rte_errno is set.
5576 static struct mlx5_flow_counter_pool *
5577 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
5580 struct mlx5_priv *priv = dev->data->dev_private;
5581 struct mlx5_flow_counter_pool *pool;
5582 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5583 bool fallback = priv->sh->cmng.counter_fallback;
5584 uint32_t size = sizeof(*pool);
5586 size += MLX5_COUNTERS_PER_POOL * MLX5_CNT_SIZE;
5587 size += (!age ? 0 : MLX5_COUNTERS_PER_POOL * MLX5_AGE_SIZE);
5588 pool = mlx5_malloc(MLX5_MEM_ZERO, size, 0, SOCKET_ID_ANY);
5594 pool->is_aged = !!age;
5595 pool->query_gen = 0;
5596 pool->min_dcs = dcs;
5597 rte_spinlock_init(&pool->sl);
5598 rte_spinlock_init(&pool->csl);
5599 TAILQ_INIT(&pool->counters[0]);
5600 TAILQ_INIT(&pool->counters[1]);
5601 pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
5602 rte_spinlock_lock(&cmng->pool_update_sl);
5603 pool->index = cmng->n_valid;
5604 if (pool->index == cmng->n && flow_dv_container_resize(dev)) {
5606 rte_spinlock_unlock(&cmng->pool_update_sl);
5609 cmng->pools[pool->index] = pool;
5611 if (unlikely(fallback)) {
5612 int base = RTE_ALIGN_FLOOR(dcs->id, MLX5_COUNTERS_PER_POOL);
5614 if (base < cmng->min_id)
5615 cmng->min_id = base;
5616 if (base > cmng->max_id)
5617 cmng->max_id = base + MLX5_COUNTERS_PER_POOL - 1;
5618 cmng->last_pool_idx = pool->index;
5620 rte_spinlock_unlock(&cmng->pool_update_sl);
5625 * Prepare a new counter and/or a new counter pool.
5628 * Pointer to the Ethernet device structure.
5629 * @param[out] cnt_free
5630 * Where to put the pointer of a new counter.
5632 * Whether the pool is for counter that was allocated for aging.
5635 * The counter pool pointer and @p cnt_free is set on success,
5636 * NULL otherwise and rte_errno is set.
5638 static struct mlx5_flow_counter_pool *
5639 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
5640 struct mlx5_flow_counter **cnt_free,
5643 struct mlx5_priv *priv = dev->data->dev_private;
5644 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5645 struct mlx5_flow_counter_pool *pool;
5646 struct mlx5_counters tmp_tq;
5647 struct mlx5_devx_obj *dcs = NULL;
5648 struct mlx5_flow_counter *cnt;
5649 enum mlx5_counter_type cnt_type =
5650 age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
5651 bool fallback = priv->sh->cmng.counter_fallback;
5655 /* bulk_bitmap must be 0 for single counter allocation. */
5656 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
5659 pool = flow_dv_find_pool_by_id(cmng, dcs->id);
5661 pool = flow_dv_pool_create(dev, dcs, age);
5663 mlx5_devx_cmd_destroy(dcs);
5667 i = dcs->id % MLX5_COUNTERS_PER_POOL;
5668 cnt = MLX5_POOL_GET_CNT(pool, i);
5670 cnt->dcs_when_free = dcs;
5674 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
5676 rte_errno = ENODATA;
5679 pool = flow_dv_pool_create(dev, dcs, age);
5681 mlx5_devx_cmd_destroy(dcs);
5684 TAILQ_INIT(&tmp_tq);
5685 for (i = 1; i < MLX5_COUNTERS_PER_POOL; ++i) {
5686 cnt = MLX5_POOL_GET_CNT(pool, i);
5688 TAILQ_INSERT_HEAD(&tmp_tq, cnt, next);
5690 rte_spinlock_lock(&cmng->csl[cnt_type]);
5691 TAILQ_CONCAT(&cmng->counters[cnt_type], &tmp_tq, next);
5692 rte_spinlock_unlock(&cmng->csl[cnt_type]);
5693 *cnt_free = MLX5_POOL_GET_CNT(pool, 0);
5694 (*cnt_free)->pool = pool;
5699 * Allocate a flow counter.
5702 * Pointer to the Ethernet device structure.
5704 * Whether the counter was allocated for aging.
5707 * Index to flow counter on success, 0 otherwise and rte_errno is set.
5710 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t age)
5712 struct mlx5_priv *priv = dev->data->dev_private;
5713 struct mlx5_flow_counter_pool *pool = NULL;
5714 struct mlx5_flow_counter *cnt_free = NULL;
5715 bool fallback = priv->sh->cmng.counter_fallback;
5716 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5717 enum mlx5_counter_type cnt_type =
5718 age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
5721 if (!priv->config.devx) {
5722 rte_errno = ENOTSUP;
5725 /* Get free counters from container. */
5726 rte_spinlock_lock(&cmng->csl[cnt_type]);
5727 cnt_free = TAILQ_FIRST(&cmng->counters[cnt_type]);
5729 TAILQ_REMOVE(&cmng->counters[cnt_type], cnt_free, next);
5730 rte_spinlock_unlock(&cmng->csl[cnt_type]);
5731 if (!cnt_free && !flow_dv_counter_pool_prepare(dev, &cnt_free, age))
5733 pool = cnt_free->pool;
5735 cnt_free->dcs_when_active = cnt_free->dcs_when_free;
5736 /* Create a DV counter action only in the first time usage. */
5737 if (!cnt_free->action) {
5739 struct mlx5_devx_obj *dcs;
5743 offset = MLX5_CNT_ARRAY_IDX(pool, cnt_free);
5744 dcs = pool->min_dcs;
5747 dcs = cnt_free->dcs_when_free;
5749 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, offset,
5756 cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
5757 MLX5_CNT_ARRAY_IDX(pool, cnt_free));
5758 /* Update the counter reset values. */
5759 if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
5762 if (!fallback && !priv->sh->cmng.query_thread_on)
5763 /* Start the asynchronous batch query by the host thread. */
5764 mlx5_set_query_alarm(priv->sh);
5768 cnt_free->pool = pool;
5770 cnt_free->dcs_when_free = cnt_free->dcs_when_active;
5771 rte_spinlock_lock(&cmng->csl[cnt_type]);
5772 TAILQ_INSERT_TAIL(&cmng->counters[cnt_type], cnt_free, next);
5773 rte_spinlock_unlock(&cmng->csl[cnt_type]);
5779 * Allocate a shared flow counter.
5782 * Pointer to the shared counter configuration.
5784 * Pointer to save the allocated counter index.
5787 * Index to flow counter on success, 0 otherwise and rte_errno is set.
5791 flow_dv_counter_alloc_shared_cb(void *ctx, union mlx5_l3t_data *data)
5793 struct mlx5_shared_counter_conf *conf = ctx;
5794 struct rte_eth_dev *dev = conf->dev;
5795 struct mlx5_flow_counter *cnt;
5797 data->dword = flow_dv_counter_alloc(dev, 0);
5798 data->dword |= MLX5_CNT_SHARED_OFFSET;
5799 cnt = flow_dv_counter_get_by_idx(dev, data->dword, NULL);
5800 cnt->shared_info.id = conf->id;
5805 * Get a shared flow counter.
5808 * Pointer to the Ethernet device structure.
5810 * Counter identifier.
5813 * Index to flow counter on success, 0 otherwise and rte_errno is set.
5816 flow_dv_counter_get_shared(struct rte_eth_dev *dev, uint32_t id)
5818 struct mlx5_priv *priv = dev->data->dev_private;
5819 struct mlx5_shared_counter_conf conf = {
5823 union mlx5_l3t_data data = {
5827 mlx5_l3t_prepare_entry(priv->sh->cnt_id_tbl, id, &data,
5828 flow_dv_counter_alloc_shared_cb, &conf);
5833 * Get age param from counter index.
5836 * Pointer to the Ethernet device structure.
5837 * @param[in] counter
5838 * Index to the counter handler.
5841 * The aging parameter specified for the counter index.
5843 static struct mlx5_age_param*
5844 flow_dv_counter_idx_get_age(struct rte_eth_dev *dev,
5847 struct mlx5_flow_counter *cnt;
5848 struct mlx5_flow_counter_pool *pool = NULL;
5850 flow_dv_counter_get_by_idx(dev, counter, &pool);
5851 counter = (counter - 1) % MLX5_COUNTERS_PER_POOL;
5852 cnt = MLX5_POOL_GET_CNT(pool, counter);
5853 return MLX5_CNT_TO_AGE(cnt);
5857 * Remove a flow counter from aged counter list.
5860 * Pointer to the Ethernet device structure.
5861 * @param[in] counter
5862 * Index to the counter handler.
5864 * Pointer to the counter handler.
5867 flow_dv_counter_remove_from_age(struct rte_eth_dev *dev,
5868 uint32_t counter, struct mlx5_flow_counter *cnt)
5870 struct mlx5_age_info *age_info;
5871 struct mlx5_age_param *age_param;
5872 struct mlx5_priv *priv = dev->data->dev_private;
5873 uint16_t expected = AGE_CANDIDATE;
5875 age_info = GET_PORT_AGE_INFO(priv);
5876 age_param = flow_dv_counter_idx_get_age(dev, counter);
5877 if (!__atomic_compare_exchange_n(&age_param->state, &expected,
5878 AGE_FREE, false, __ATOMIC_RELAXED,
5879 __ATOMIC_RELAXED)) {
5881 * We need the lock even it is age timeout,
5882 * since counter may still in process.
5884 rte_spinlock_lock(&age_info->aged_sl);
5885 TAILQ_REMOVE(&age_info->aged_counters, cnt, next);
5886 rte_spinlock_unlock(&age_info->aged_sl);
5887 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
5892 * Release a flow counter.
5895 * Pointer to the Ethernet device structure.
5896 * @param[in] counter
5897 * Index to the counter handler.
5900 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t counter)
5902 struct mlx5_priv *priv = dev->data->dev_private;
5903 struct mlx5_flow_counter_pool *pool = NULL;
5904 struct mlx5_flow_counter *cnt;
5905 enum mlx5_counter_type cnt_type;
5909 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
5911 if (IS_SHARED_CNT(counter) &&
5912 mlx5_l3t_clear_entry(priv->sh->cnt_id_tbl, cnt->shared_info.id))
5915 flow_dv_counter_remove_from_age(dev, counter, cnt);
5918 * Put the counter back to list to be updated in none fallback mode.
5919 * Currently, we are using two list alternately, while one is in query,
5920 * add the freed counter to the other list based on the pool query_gen
5921 * value. After query finishes, add counter the list to the global
5922 * container counter list. The list changes while query starts. In
5923 * this case, lock will not be needed as query callback and release
5924 * function both operate with the different list.
5927 if (!priv->sh->cmng.counter_fallback) {
5928 rte_spinlock_lock(&pool->csl);
5929 TAILQ_INSERT_TAIL(&pool->counters[pool->query_gen], cnt, next);
5930 rte_spinlock_unlock(&pool->csl);
5932 cnt->dcs_when_free = cnt->dcs_when_active;
5933 cnt_type = pool->is_aged ? MLX5_COUNTER_TYPE_AGE :
5934 MLX5_COUNTER_TYPE_ORIGIN;
5935 rte_spinlock_lock(&priv->sh->cmng.csl[cnt_type]);
5936 TAILQ_INSERT_TAIL(&priv->sh->cmng.counters[cnt_type],
5938 rte_spinlock_unlock(&priv->sh->cmng.csl[cnt_type]);
5943 * Verify the @p attributes will be correctly understood by the NIC and store
5944 * them in the @p flow if everything is correct.
5947 * Pointer to dev struct.
5948 * @param[in] attributes
5949 * Pointer to flow attributes
5950 * @param[in] external
5951 * This flow rule is created by request external to PMD.
5953 * Pointer to error structure.
5956 * - 0 on success and non root table.
5957 * - 1 on success and root table.
5958 * - a negative errno value otherwise and rte_errno is set.
5961 flow_dv_validate_attributes(struct rte_eth_dev *dev,
5962 const struct mlx5_flow_tunnel *tunnel,
5963 const struct rte_flow_attr *attributes,
5964 const struct flow_grp_info *grp_info,
5965 struct rte_flow_error *error)
5967 struct mlx5_priv *priv = dev->data->dev_private;
5968 uint32_t lowest_priority = mlx5_get_lowest_priority(dev, attributes);
5971 #ifndef HAVE_MLX5DV_DR
5972 RTE_SET_USED(tunnel);
5973 RTE_SET_USED(grp_info);
5974 if (attributes->group)
5975 return rte_flow_error_set(error, ENOTSUP,
5976 RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
5978 "groups are not supported");
5982 ret = mlx5_flow_group_to_table(dev, tunnel, attributes->group, &table,
5987 ret = MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
5989 if (attributes->priority != MLX5_FLOW_LOWEST_PRIO_INDICATOR &&
5990 attributes->priority > lowest_priority)
5991 return rte_flow_error_set(error, ENOTSUP,
5992 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
5994 "priority out of range");
5995 if (attributes->transfer) {
5996 if (!priv->config.dv_esw_en)
5997 return rte_flow_error_set
5999 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6000 "E-Switch dr is not supported");
6001 if (!(priv->representor || priv->master))
6002 return rte_flow_error_set
6003 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6004 NULL, "E-Switch configuration can only be"
6005 " done by a master or a representor device");
6006 if (attributes->egress)
6007 return rte_flow_error_set
6009 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
6010 "egress is not supported");
6012 if (!(attributes->egress ^ attributes->ingress))
6013 return rte_flow_error_set(error, ENOTSUP,
6014 RTE_FLOW_ERROR_TYPE_ATTR, NULL,
6015 "must specify exactly one of "
6016 "ingress or egress");
6021 * Internal validation function. For validating both actions and items.
6024 * Pointer to the rte_eth_dev structure.
6026 * Pointer to the flow attributes.
6028 * Pointer to the list of items.
6029 * @param[in] actions
6030 * Pointer to the list of actions.
6031 * @param[in] external
6032 * This flow rule is created by request external to PMD.
6033 * @param[in] hairpin
6034 * Number of hairpin TX actions, 0 means classic flow.
6036 * Pointer to the error structure.
6039 * 0 on success, a negative errno value otherwise and rte_errno is set.
6042 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
6043 const struct rte_flow_item items[],
6044 const struct rte_flow_action actions[],
6045 bool external, int hairpin, struct rte_flow_error *error)
6048 uint64_t action_flags = 0;
6049 uint64_t item_flags = 0;
6050 uint64_t last_item = 0;
6051 uint8_t next_protocol = 0xff;
6052 uint16_t ether_type = 0;
6054 uint8_t item_ipv6_proto = 0;
6055 int fdb_mirror_limit = 0;
6056 int modify_after_mirror = 0;
6057 const struct rte_flow_item *geneve_item = NULL;
6058 const struct rte_flow_item *gre_item = NULL;
6059 const struct rte_flow_item *gtp_item = NULL;
6060 const struct rte_flow_action_raw_decap *decap;
6061 const struct rte_flow_action_raw_encap *encap;
6062 const struct rte_flow_action_rss *rss = NULL;
6063 const struct rte_flow_action_rss *sample_rss = NULL;
6064 const struct rte_flow_action_count *count = NULL;
6065 const struct rte_flow_action_count *sample_count = NULL;
6066 const struct rte_flow_item_tcp nic_tcp_mask = {
6069 .src_port = RTE_BE16(UINT16_MAX),
6070 .dst_port = RTE_BE16(UINT16_MAX),
6073 const struct rte_flow_item_ipv6 nic_ipv6_mask = {
6076 "\xff\xff\xff\xff\xff\xff\xff\xff"
6077 "\xff\xff\xff\xff\xff\xff\xff\xff",
6079 "\xff\xff\xff\xff\xff\xff\xff\xff"
6080 "\xff\xff\xff\xff\xff\xff\xff\xff",
6081 .vtc_flow = RTE_BE32(0xffffffff),
6087 const struct rte_flow_item_ecpri nic_ecpri_mask = {
6091 RTE_BE32(((const struct rte_ecpri_common_hdr) {
6095 .dummy[0] = 0xffffffff,
6098 struct mlx5_priv *priv = dev->data->dev_private;
6099 struct mlx5_dev_config *dev_conf = &priv->config;
6100 uint16_t queue_index = 0xFFFF;
6101 const struct rte_flow_item_vlan *vlan_m = NULL;
6102 uint32_t rw_act_num = 0;
6104 const struct mlx5_flow_tunnel *tunnel;
6105 struct flow_grp_info grp_info = {
6106 .external = !!external,
6107 .transfer = !!attr->transfer,
6108 .fdb_def_rule = !!priv->fdb_def_rule,
6110 const struct rte_eth_hairpin_conf *conf;
6114 if (is_flow_tunnel_match_rule(dev, attr, items, actions)) {
6115 tunnel = flow_items_to_tunnel(items);
6116 action_flags |= MLX5_FLOW_ACTION_TUNNEL_MATCH |
6117 MLX5_FLOW_ACTION_DECAP;
6118 } else if (is_flow_tunnel_steer_rule(dev, attr, items, actions)) {
6119 tunnel = flow_actions_to_tunnel(actions);
6120 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
6124 if (tunnel && priv->representor)
6125 return rte_flow_error_set(error, ENOTSUP,
6126 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6127 "decap not supported "
6128 "for VF representor");
6129 grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
6130 (dev, tunnel, attr, items, actions);
6131 ret = flow_dv_validate_attributes(dev, tunnel, attr, &grp_info, error);
6134 is_root = (uint64_t)ret;
6135 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
6136 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
6137 int type = items->type;
6139 if (!mlx5_flow_os_item_supported(type))
6140 return rte_flow_error_set(error, ENOTSUP,
6141 RTE_FLOW_ERROR_TYPE_ITEM,
6142 NULL, "item not supported");
6144 case MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL:
6145 if (items[0].type != (typeof(items[0].type))
6146 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL)
6147 return rte_flow_error_set
6149 RTE_FLOW_ERROR_TYPE_ITEM,
6150 NULL, "MLX5 private items "
6151 "must be the first");
6153 case RTE_FLOW_ITEM_TYPE_VOID:
6155 case RTE_FLOW_ITEM_TYPE_PORT_ID:
6156 ret = flow_dv_validate_item_port_id
6157 (dev, items, attr, item_flags, error);
6160 last_item = MLX5_FLOW_ITEM_PORT_ID;
6162 case RTE_FLOW_ITEM_TYPE_ETH:
6163 ret = mlx5_flow_validate_item_eth(items, item_flags,
6167 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
6168 MLX5_FLOW_LAYER_OUTER_L2;
6169 if (items->mask != NULL && items->spec != NULL) {
6171 ((const struct rte_flow_item_eth *)
6174 ((const struct rte_flow_item_eth *)
6176 ether_type = rte_be_to_cpu_16(ether_type);
6181 case RTE_FLOW_ITEM_TYPE_VLAN:
6182 ret = flow_dv_validate_item_vlan(items, item_flags,
6186 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
6187 MLX5_FLOW_LAYER_OUTER_VLAN;
6188 if (items->mask != NULL && items->spec != NULL) {
6190 ((const struct rte_flow_item_vlan *)
6191 items->spec)->inner_type;
6193 ((const struct rte_flow_item_vlan *)
6194 items->mask)->inner_type;
6195 ether_type = rte_be_to_cpu_16(ether_type);
6199 /* Store outer VLAN mask for of_push_vlan action. */
6201 vlan_m = items->mask;
6203 case RTE_FLOW_ITEM_TYPE_IPV4:
6204 mlx5_flow_tunnel_ip_check(items, next_protocol,
6205 &item_flags, &tunnel);
6206 ret = flow_dv_validate_item_ipv4(items, item_flags,
6207 last_item, ether_type,
6211 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
6212 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
6213 if (items->mask != NULL &&
6214 ((const struct rte_flow_item_ipv4 *)
6215 items->mask)->hdr.next_proto_id) {
6217 ((const struct rte_flow_item_ipv4 *)
6218 (items->spec))->hdr.next_proto_id;
6220 ((const struct rte_flow_item_ipv4 *)
6221 (items->mask))->hdr.next_proto_id;
6223 /* Reset for inner layer. */
6224 next_protocol = 0xff;
6227 case RTE_FLOW_ITEM_TYPE_IPV6:
6228 mlx5_flow_tunnel_ip_check(items, next_protocol,
6229 &item_flags, &tunnel);
6230 ret = mlx5_flow_validate_item_ipv6(items, item_flags,
6237 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
6238 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
6239 if (items->mask != NULL &&
6240 ((const struct rte_flow_item_ipv6 *)
6241 items->mask)->hdr.proto) {
6243 ((const struct rte_flow_item_ipv6 *)
6244 items->spec)->hdr.proto;
6246 ((const struct rte_flow_item_ipv6 *)
6247 items->spec)->hdr.proto;
6249 ((const struct rte_flow_item_ipv6 *)
6250 items->mask)->hdr.proto;
6252 /* Reset for inner layer. */
6253 next_protocol = 0xff;
6256 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
6257 ret = flow_dv_validate_item_ipv6_frag_ext(items,
6262 last_item = tunnel ?
6263 MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
6264 MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
6265 if (items->mask != NULL &&
6266 ((const struct rte_flow_item_ipv6_frag_ext *)
6267 items->mask)->hdr.next_header) {
6269 ((const struct rte_flow_item_ipv6_frag_ext *)
6270 items->spec)->hdr.next_header;
6272 ((const struct rte_flow_item_ipv6_frag_ext *)
6273 items->mask)->hdr.next_header;
6275 /* Reset for inner layer. */
6276 next_protocol = 0xff;
6279 case RTE_FLOW_ITEM_TYPE_TCP:
6280 ret = mlx5_flow_validate_item_tcp
6287 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
6288 MLX5_FLOW_LAYER_OUTER_L4_TCP;
6290 case RTE_FLOW_ITEM_TYPE_UDP:
6291 ret = mlx5_flow_validate_item_udp(items, item_flags,
6296 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
6297 MLX5_FLOW_LAYER_OUTER_L4_UDP;
6299 case RTE_FLOW_ITEM_TYPE_GRE:
6300 ret = mlx5_flow_validate_item_gre(items, item_flags,
6301 next_protocol, error);
6305 last_item = MLX5_FLOW_LAYER_GRE;
6307 case RTE_FLOW_ITEM_TYPE_NVGRE:
6308 ret = mlx5_flow_validate_item_nvgre(items, item_flags,
6313 last_item = MLX5_FLOW_LAYER_NVGRE;
6315 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
6316 ret = mlx5_flow_validate_item_gre_key
6317 (items, item_flags, gre_item, error);
6320 last_item = MLX5_FLOW_LAYER_GRE_KEY;
6322 case RTE_FLOW_ITEM_TYPE_VXLAN:
6323 ret = mlx5_flow_validate_item_vxlan(items, item_flags,
6327 last_item = MLX5_FLOW_LAYER_VXLAN;
6329 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
6330 ret = mlx5_flow_validate_item_vxlan_gpe(items,
6335 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
6337 case RTE_FLOW_ITEM_TYPE_GENEVE:
6338 ret = mlx5_flow_validate_item_geneve(items,
6343 geneve_item = items;
6344 last_item = MLX5_FLOW_LAYER_GENEVE;
6346 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
6347 ret = mlx5_flow_validate_item_geneve_opt(items,
6354 last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
6356 case RTE_FLOW_ITEM_TYPE_MPLS:
6357 ret = mlx5_flow_validate_item_mpls(dev, items,
6362 last_item = MLX5_FLOW_LAYER_MPLS;
6365 case RTE_FLOW_ITEM_TYPE_MARK:
6366 ret = flow_dv_validate_item_mark(dev, items, attr,
6370 last_item = MLX5_FLOW_ITEM_MARK;
6372 case RTE_FLOW_ITEM_TYPE_META:
6373 ret = flow_dv_validate_item_meta(dev, items, attr,
6377 last_item = MLX5_FLOW_ITEM_METADATA;
6379 case RTE_FLOW_ITEM_TYPE_ICMP:
6380 ret = mlx5_flow_validate_item_icmp(items, item_flags,
6385 last_item = MLX5_FLOW_LAYER_ICMP;
6387 case RTE_FLOW_ITEM_TYPE_ICMP6:
6388 ret = mlx5_flow_validate_item_icmp6(items, item_flags,
6393 item_ipv6_proto = IPPROTO_ICMPV6;
6394 last_item = MLX5_FLOW_LAYER_ICMP6;
6396 case RTE_FLOW_ITEM_TYPE_TAG:
6397 ret = flow_dv_validate_item_tag(dev, items,
6401 last_item = MLX5_FLOW_ITEM_TAG;
6403 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
6404 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
6406 case RTE_FLOW_ITEM_TYPE_GTP:
6407 ret = flow_dv_validate_item_gtp(dev, items, item_flags,
6412 last_item = MLX5_FLOW_LAYER_GTP;
6414 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
6415 ret = flow_dv_validate_item_gtp_psc(items, last_item,
6420 last_item = MLX5_FLOW_LAYER_GTP_PSC;
6422 case RTE_FLOW_ITEM_TYPE_ECPRI:
6423 /* Capacity will be checked in the translate stage. */
6424 ret = mlx5_flow_validate_item_ecpri(items, item_flags,
6431 last_item = MLX5_FLOW_LAYER_ECPRI;
6434 return rte_flow_error_set(error, ENOTSUP,
6435 RTE_FLOW_ERROR_TYPE_ITEM,
6436 NULL, "item not supported");
6438 item_flags |= last_item;
6440 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
6441 int type = actions->type;
6443 if (!mlx5_flow_os_action_supported(type))
6444 return rte_flow_error_set(error, ENOTSUP,
6445 RTE_FLOW_ERROR_TYPE_ACTION,
6447 "action not supported");
6448 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
6449 return rte_flow_error_set(error, ENOTSUP,
6450 RTE_FLOW_ERROR_TYPE_ACTION,
6451 actions, "too many actions");
6453 case RTE_FLOW_ACTION_TYPE_VOID:
6455 case RTE_FLOW_ACTION_TYPE_PORT_ID:
6456 ret = flow_dv_validate_action_port_id(dev,
6463 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
6466 case RTE_FLOW_ACTION_TYPE_FLAG:
6467 ret = flow_dv_validate_action_flag(dev, action_flags,
6471 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
6472 /* Count all modify-header actions as one. */
6473 if (!(action_flags &
6474 MLX5_FLOW_MODIFY_HDR_ACTIONS))
6476 action_flags |= MLX5_FLOW_ACTION_FLAG |
6477 MLX5_FLOW_ACTION_MARK_EXT;
6478 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6479 modify_after_mirror = 1;
6482 action_flags |= MLX5_FLOW_ACTION_FLAG;
6485 rw_act_num += MLX5_ACT_NUM_SET_MARK;
6487 case RTE_FLOW_ACTION_TYPE_MARK:
6488 ret = flow_dv_validate_action_mark(dev, actions,
6493 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
6494 /* Count all modify-header actions as one. */
6495 if (!(action_flags &
6496 MLX5_FLOW_MODIFY_HDR_ACTIONS))
6498 action_flags |= MLX5_FLOW_ACTION_MARK |
6499 MLX5_FLOW_ACTION_MARK_EXT;
6500 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6501 modify_after_mirror = 1;
6503 action_flags |= MLX5_FLOW_ACTION_MARK;
6506 rw_act_num += MLX5_ACT_NUM_SET_MARK;
6508 case RTE_FLOW_ACTION_TYPE_SET_META:
6509 ret = flow_dv_validate_action_set_meta(dev, actions,
6514 /* Count all modify-header actions as one action. */
6515 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6517 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6518 modify_after_mirror = 1;
6519 action_flags |= MLX5_FLOW_ACTION_SET_META;
6520 rw_act_num += MLX5_ACT_NUM_SET_META;
6522 case RTE_FLOW_ACTION_TYPE_SET_TAG:
6523 ret = flow_dv_validate_action_set_tag(dev, actions,
6528 /* Count all modify-header actions as one action. */
6529 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6531 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6532 modify_after_mirror = 1;
6533 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
6534 rw_act_num += MLX5_ACT_NUM_SET_TAG;
6536 case RTE_FLOW_ACTION_TYPE_DROP:
6537 ret = mlx5_flow_validate_action_drop(action_flags,
6541 action_flags |= MLX5_FLOW_ACTION_DROP;
6544 case RTE_FLOW_ACTION_TYPE_QUEUE:
6545 ret = mlx5_flow_validate_action_queue(actions,
6550 queue_index = ((const struct rte_flow_action_queue *)
6551 (actions->conf))->index;
6552 action_flags |= MLX5_FLOW_ACTION_QUEUE;
6555 case RTE_FLOW_ACTION_TYPE_RSS:
6556 rss = actions->conf;
6557 ret = mlx5_flow_validate_action_rss(actions,
6563 if (rss && sample_rss &&
6564 (sample_rss->level != rss->level ||
6565 sample_rss->types != rss->types))
6566 return rte_flow_error_set(error, ENOTSUP,
6567 RTE_FLOW_ERROR_TYPE_ACTION,
6569 "Can't use the different RSS types "
6570 "or level in the same flow");
6571 if (rss != NULL && rss->queue_num)
6572 queue_index = rss->queue[0];
6573 action_flags |= MLX5_FLOW_ACTION_RSS;
6576 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
6578 mlx5_flow_validate_action_default_miss(action_flags,
6582 action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
6585 case RTE_FLOW_ACTION_TYPE_COUNT:
6586 ret = flow_dv_validate_action_count(dev, actions,
6591 count = actions->conf;
6592 action_flags |= MLX5_FLOW_ACTION_COUNT;
6595 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
6596 if (flow_dv_validate_action_pop_vlan(dev,
6602 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6603 modify_after_mirror = 1;
6604 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
6607 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
6608 ret = flow_dv_validate_action_push_vlan(dev,
6615 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6616 modify_after_mirror = 1;
6617 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
6620 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
6621 ret = flow_dv_validate_action_set_vlan_pcp
6622 (action_flags, actions, error);
6625 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6626 modify_after_mirror = 1;
6627 /* Count PCP with push_vlan command. */
6628 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
6630 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
6631 ret = flow_dv_validate_action_set_vlan_vid
6632 (item_flags, action_flags,
6636 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6637 modify_after_mirror = 1;
6638 /* Count VID with push_vlan command. */
6639 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
6640 rw_act_num += MLX5_ACT_NUM_MDF_VID;
6642 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
6643 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
6644 ret = flow_dv_validate_action_l2_encap(dev,
6650 action_flags |= MLX5_FLOW_ACTION_ENCAP;
6653 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
6654 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
6655 ret = flow_dv_validate_action_decap(dev, action_flags,
6656 actions, item_flags,
6660 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6661 modify_after_mirror = 1;
6662 action_flags |= MLX5_FLOW_ACTION_DECAP;
6665 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
6666 ret = flow_dv_validate_action_raw_encap_decap
6667 (dev, NULL, actions->conf, attr, &action_flags,
6668 &actions_n, actions, item_flags, error);
6672 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
6673 decap = actions->conf;
6674 while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
6676 if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
6680 encap = actions->conf;
6682 ret = flow_dv_validate_action_raw_encap_decap
6684 decap ? decap : &empty_decap, encap,
6685 attr, &action_flags, &actions_n,
6686 actions, item_flags, error);
6689 if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) &&
6690 (action_flags & MLX5_FLOW_ACTION_DECAP))
6691 modify_after_mirror = 1;
6693 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
6694 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
6695 ret = flow_dv_validate_action_modify_mac(action_flags,
6701 /* Count all modify-header actions as one action. */
6702 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6704 action_flags |= actions->type ==
6705 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
6706 MLX5_FLOW_ACTION_SET_MAC_SRC :
6707 MLX5_FLOW_ACTION_SET_MAC_DST;
6708 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6709 modify_after_mirror = 1;
6711 * Even if the source and destination MAC addresses have
6712 * overlap in the header with 4B alignment, the convert
6713 * function will handle them separately and 4 SW actions
6714 * will be created. And 2 actions will be added each
6715 * time no matter how many bytes of address will be set.
6717 rw_act_num += MLX5_ACT_NUM_MDF_MAC;
6719 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
6720 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
6721 ret = flow_dv_validate_action_modify_ipv4(action_flags,
6727 /* Count all modify-header actions as one action. */
6728 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6730 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6731 modify_after_mirror = 1;
6732 action_flags |= actions->type ==
6733 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
6734 MLX5_FLOW_ACTION_SET_IPV4_SRC :
6735 MLX5_FLOW_ACTION_SET_IPV4_DST;
6736 rw_act_num += MLX5_ACT_NUM_MDF_IPV4;
6738 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
6739 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
6740 ret = flow_dv_validate_action_modify_ipv6(action_flags,
6746 if (item_ipv6_proto == IPPROTO_ICMPV6)
6747 return rte_flow_error_set(error, ENOTSUP,
6748 RTE_FLOW_ERROR_TYPE_ACTION,
6750 "Can't change header "
6751 "with ICMPv6 proto");
6752 /* Count all modify-header actions as one action. */
6753 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6755 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6756 modify_after_mirror = 1;
6757 action_flags |= actions->type ==
6758 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
6759 MLX5_FLOW_ACTION_SET_IPV6_SRC :
6760 MLX5_FLOW_ACTION_SET_IPV6_DST;
6761 rw_act_num += MLX5_ACT_NUM_MDF_IPV6;
6763 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
6764 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
6765 ret = flow_dv_validate_action_modify_tp(action_flags,
6771 /* Count all modify-header actions as one action. */
6772 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6774 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6775 modify_after_mirror = 1;
6776 action_flags |= actions->type ==
6777 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
6778 MLX5_FLOW_ACTION_SET_TP_SRC :
6779 MLX5_FLOW_ACTION_SET_TP_DST;
6780 rw_act_num += MLX5_ACT_NUM_MDF_PORT;
6782 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
6783 case RTE_FLOW_ACTION_TYPE_SET_TTL:
6784 ret = flow_dv_validate_action_modify_ttl(action_flags,
6790 /* Count all modify-header actions as one action. */
6791 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6793 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6794 modify_after_mirror = 1;
6795 action_flags |= actions->type ==
6796 RTE_FLOW_ACTION_TYPE_SET_TTL ?
6797 MLX5_FLOW_ACTION_SET_TTL :
6798 MLX5_FLOW_ACTION_DEC_TTL;
6799 rw_act_num += MLX5_ACT_NUM_MDF_TTL;
6801 case RTE_FLOW_ACTION_TYPE_JUMP:
6802 ret = flow_dv_validate_action_jump(dev, tunnel, actions,
6808 if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) &&
6810 return rte_flow_error_set(error, EINVAL,
6811 RTE_FLOW_ERROR_TYPE_ACTION,
6813 "sample and jump action combination is not supported");
6815 action_flags |= MLX5_FLOW_ACTION_JUMP;
6817 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
6818 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
6819 ret = flow_dv_validate_action_modify_tcp_seq
6826 /* Count all modify-header actions as one action. */
6827 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6829 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6830 modify_after_mirror = 1;
6831 action_flags |= actions->type ==
6832 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
6833 MLX5_FLOW_ACTION_INC_TCP_SEQ :
6834 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
6835 rw_act_num += MLX5_ACT_NUM_MDF_TCPSEQ;
6837 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
6838 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
6839 ret = flow_dv_validate_action_modify_tcp_ack
6846 /* Count all modify-header actions as one action. */
6847 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6849 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6850 modify_after_mirror = 1;
6851 action_flags |= actions->type ==
6852 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
6853 MLX5_FLOW_ACTION_INC_TCP_ACK :
6854 MLX5_FLOW_ACTION_DEC_TCP_ACK;
6855 rw_act_num += MLX5_ACT_NUM_MDF_TCPACK;
6857 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
6859 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
6860 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
6861 rw_act_num += MLX5_ACT_NUM_SET_TAG;
6863 case RTE_FLOW_ACTION_TYPE_METER:
6864 ret = mlx5_flow_validate_action_meter(dev,
6870 action_flags |= MLX5_FLOW_ACTION_METER;
6872 /* Meter action will add one more TAG action. */
6873 rw_act_num += MLX5_ACT_NUM_SET_TAG;
6875 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
6876 if (!attr->transfer && !attr->group)
6877 return rte_flow_error_set(error, ENOTSUP,
6878 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6880 "Shared ASO age action is not supported for group 0");
6881 action_flags |= MLX5_FLOW_ACTION_AGE;
6884 case RTE_FLOW_ACTION_TYPE_AGE:
6885 ret = flow_dv_validate_action_age(action_flags,
6891 * Validate the regular AGE action (using counter)
6892 * mutual exclusion with share counter actions.
6894 if (!priv->sh->flow_hit_aso_en) {
6895 if (count && count->shared)
6896 return rte_flow_error_set
6898 RTE_FLOW_ERROR_TYPE_ACTION,
6900 "old age and shared count combination is not supported");
6902 return rte_flow_error_set
6904 RTE_FLOW_ERROR_TYPE_ACTION,
6906 "old age action and count must be in the same sub flow");
6908 action_flags |= MLX5_FLOW_ACTION_AGE;
6911 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
6912 ret = flow_dv_validate_action_modify_ipv4_dscp
6919 /* Count all modify-header actions as one action. */
6920 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6922 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6923 modify_after_mirror = 1;
6924 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
6925 rw_act_num += MLX5_ACT_NUM_SET_DSCP;
6927 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
6928 ret = flow_dv_validate_action_modify_ipv6_dscp
6935 /* Count all modify-header actions as one action. */
6936 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6938 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6939 modify_after_mirror = 1;
6940 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
6941 rw_act_num += MLX5_ACT_NUM_SET_DSCP;
6943 case RTE_FLOW_ACTION_TYPE_SAMPLE:
6944 ret = flow_dv_validate_action_sample(&action_flags,
6953 action_flags |= MLX5_FLOW_ACTION_SAMPLE;
6956 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
6957 if (actions[0].type != (typeof(actions[0].type))
6958 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET)
6959 return rte_flow_error_set
6961 RTE_FLOW_ERROR_TYPE_ACTION,
6962 NULL, "MLX5 private action "
6963 "must be the first");
6965 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
6967 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
6968 ret = flow_dv_validate_action_modify_field(dev,
6975 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6976 modify_after_mirror = 1;
6977 /* Count all modify-header actions as one action. */
6978 if (!(action_flags & MLX5_FLOW_ACTION_MODIFY_FIELD))
6980 action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
6984 return rte_flow_error_set(error, ENOTSUP,
6985 RTE_FLOW_ERROR_TYPE_ACTION,
6987 "action not supported");
6991 * Validate actions in flow rules
6992 * - Explicit decap action is prohibited by the tunnel offload API.
6993 * - Drop action in tunnel steer rule is prohibited by the API.
6994 * - Application cannot use MARK action because it's value can mask
6995 * tunnel default miss nitification.
6996 * - JUMP in tunnel match rule has no support in current PMD
6998 * - TAG & META are reserved for future uses.
7000 if (action_flags & MLX5_FLOW_ACTION_TUNNEL_SET) {
7001 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_DECAP |
7002 MLX5_FLOW_ACTION_MARK |
7003 MLX5_FLOW_ACTION_SET_TAG |
7004 MLX5_FLOW_ACTION_SET_META |
7005 MLX5_FLOW_ACTION_DROP;
7007 if (action_flags & bad_actions_mask)
7008 return rte_flow_error_set
7010 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7011 "Invalid RTE action in tunnel "
7013 if (!(action_flags & MLX5_FLOW_ACTION_JUMP))
7014 return rte_flow_error_set
7016 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7017 "tunnel set decap rule must terminate "
7020 return rte_flow_error_set
7022 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7023 "tunnel flows for ingress traffic only");
7025 if (action_flags & MLX5_FLOW_ACTION_TUNNEL_MATCH) {
7026 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_JUMP |
7027 MLX5_FLOW_ACTION_MARK |
7028 MLX5_FLOW_ACTION_SET_TAG |
7029 MLX5_FLOW_ACTION_SET_META;
7031 if (action_flags & bad_actions_mask)
7032 return rte_flow_error_set
7034 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7035 "Invalid RTE action in tunnel "
7039 * Validate the drop action mutual exclusion with other actions.
7040 * Drop action is mutually-exclusive with any other action, except for
7042 * Drop action compatibility with tunnel offload was already validated.
7044 if (action_flags & (MLX5_FLOW_ACTION_TUNNEL_MATCH |
7045 MLX5_FLOW_ACTION_TUNNEL_MATCH));
7046 else if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
7047 (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
7048 return rte_flow_error_set(error, EINVAL,
7049 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7050 "Drop action is mutually-exclusive "
7051 "with any other action, except for "
7053 /* Eswitch has few restrictions on using items and actions */
7054 if (attr->transfer) {
7055 if (!mlx5_flow_ext_mreg_supported(dev) &&
7056 action_flags & MLX5_FLOW_ACTION_FLAG)
7057 return rte_flow_error_set(error, ENOTSUP,
7058 RTE_FLOW_ERROR_TYPE_ACTION,
7060 "unsupported action FLAG");
7061 if (!mlx5_flow_ext_mreg_supported(dev) &&
7062 action_flags & MLX5_FLOW_ACTION_MARK)
7063 return rte_flow_error_set(error, ENOTSUP,
7064 RTE_FLOW_ERROR_TYPE_ACTION,
7066 "unsupported action MARK");
7067 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
7068 return rte_flow_error_set(error, ENOTSUP,
7069 RTE_FLOW_ERROR_TYPE_ACTION,
7071 "unsupported action QUEUE");
7072 if (action_flags & MLX5_FLOW_ACTION_RSS)
7073 return rte_flow_error_set(error, ENOTSUP,
7074 RTE_FLOW_ERROR_TYPE_ACTION,
7076 "unsupported action RSS");
7077 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
7078 return rte_flow_error_set(error, EINVAL,
7079 RTE_FLOW_ERROR_TYPE_ACTION,
7081 "no fate action is found");
7083 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
7084 return rte_flow_error_set(error, EINVAL,
7085 RTE_FLOW_ERROR_TYPE_ACTION,
7087 "no fate action is found");
7090 * Continue validation for Xcap and VLAN actions.
7091 * If hairpin is working in explicit TX rule mode, there is no actions
7092 * splitting and the validation of hairpin ingress flow should be the
7093 * same as other standard flows.
7095 if ((action_flags & (MLX5_FLOW_XCAP_ACTIONS |
7096 MLX5_FLOW_VLAN_ACTIONS)) &&
7097 (queue_index == 0xFFFF ||
7098 mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN ||
7099 ((conf = mlx5_rxq_get_hairpin_conf(dev, queue_index)) != NULL &&
7100 conf->tx_explicit != 0))) {
7101 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
7102 MLX5_FLOW_XCAP_ACTIONS)
7103 return rte_flow_error_set(error, ENOTSUP,
7104 RTE_FLOW_ERROR_TYPE_ACTION,
7105 NULL, "encap and decap "
7106 "combination aren't supported");
7107 if (!attr->transfer && attr->ingress) {
7108 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
7109 return rte_flow_error_set
7111 RTE_FLOW_ERROR_TYPE_ACTION,
7112 NULL, "encap is not supported"
7113 " for ingress traffic");
7114 else if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
7115 return rte_flow_error_set
7117 RTE_FLOW_ERROR_TYPE_ACTION,
7118 NULL, "push VLAN action not "
7119 "supported for ingress");
7120 else if ((action_flags & MLX5_FLOW_VLAN_ACTIONS) ==
7121 MLX5_FLOW_VLAN_ACTIONS)
7122 return rte_flow_error_set
7124 RTE_FLOW_ERROR_TYPE_ACTION,
7125 NULL, "no support for "
7126 "multiple VLAN actions");
7130 * Hairpin flow will add one more TAG action in TX implicit mode.
7131 * In TX explicit mode, there will be no hairpin flow ID.
7134 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7135 /* extra metadata enabled: one more TAG action will be add. */
7136 if (dev_conf->dv_flow_en &&
7137 dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
7138 mlx5_flow_ext_mreg_supported(dev))
7139 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7141 flow_dv_modify_hdr_action_max(dev, is_root)) {
7142 return rte_flow_error_set(error, ENOTSUP,
7143 RTE_FLOW_ERROR_TYPE_ACTION,
7144 NULL, "too many header modify"
7145 " actions to support");
7147 /* Eswitch egress mirror and modify flow has limitation on CX5 */
7148 if (fdb_mirror_limit && modify_after_mirror)
7149 return rte_flow_error_set(error, EINVAL,
7150 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7151 "sample before modify action is not supported");
7156 * Internal preparation function. Allocates the DV flow size,
7157 * this size is constant.
7160 * Pointer to the rte_eth_dev structure.
7162 * Pointer to the flow attributes.
7164 * Pointer to the list of items.
7165 * @param[in] actions
7166 * Pointer to the list of actions.
7168 * Pointer to the error structure.
7171 * Pointer to mlx5_flow object on success,
7172 * otherwise NULL and rte_errno is set.
7174 static struct mlx5_flow *
7175 flow_dv_prepare(struct rte_eth_dev *dev,
7176 const struct rte_flow_attr *attr __rte_unused,
7177 const struct rte_flow_item items[] __rte_unused,
7178 const struct rte_flow_action actions[] __rte_unused,
7179 struct rte_flow_error *error)
7181 uint32_t handle_idx = 0;
7182 struct mlx5_flow *dev_flow;
7183 struct mlx5_flow_handle *dev_handle;
7184 struct mlx5_priv *priv = dev->data->dev_private;
7185 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
7188 /* In case of corrupting the memory. */
7189 if (wks->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
7190 rte_flow_error_set(error, ENOSPC,
7191 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7192 "not free temporary device flow");
7195 dev_handle = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
7198 rte_flow_error_set(error, ENOMEM,
7199 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7200 "not enough memory to create flow handle");
7203 MLX5_ASSERT(wks->flow_idx < RTE_DIM(wks->flows));
7204 dev_flow = &wks->flows[wks->flow_idx++];
7205 memset(dev_flow, 0, sizeof(*dev_flow));
7206 dev_flow->handle = dev_handle;
7207 dev_flow->handle_idx = handle_idx;
7209 * In some old rdma-core releases, before continuing, a check of the
7210 * length of matching parameter will be done at first. It needs to use
7211 * the length without misc4 param. If the flow has misc4 support, then
7212 * the length needs to be adjusted accordingly. Each param member is
7213 * aligned with a 64B boundary naturally.
7215 dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param) -
7216 MLX5_ST_SZ_BYTES(fte_match_set_misc4);
7217 dev_flow->ingress = attr->ingress;
7218 dev_flow->dv.transfer = attr->transfer;
7222 #ifdef RTE_LIBRTE_MLX5_DEBUG
7224 * Sanity check for match mask and value. Similar to check_valid_spec() in
7225 * kernel driver. If unmasked bit is present in value, it returns failure.
7228 * pointer to match mask buffer.
7229 * @param match_value
7230 * pointer to match value buffer.
7233 * 0 if valid, -EINVAL otherwise.
7236 flow_dv_check_valid_spec(void *match_mask, void *match_value)
7238 uint8_t *m = match_mask;
7239 uint8_t *v = match_value;
7242 for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
7245 "match_value differs from match_criteria"
7246 " %p[%u] != %p[%u]",
7247 match_value, i, match_mask, i);
7256 * Add match of ip_version.
7260 * @param[in] headers_v
7261 * Values header pointer.
7262 * @param[in] headers_m
7263 * Masks header pointer.
7264 * @param[in] ip_version
7265 * The IP version to set.
7268 flow_dv_set_match_ip_version(uint32_t group,
7274 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
7276 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version,
7278 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, ip_version);
7279 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, 0);
7280 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype, 0);
7284 * Add Ethernet item to matcher and to the value.
7286 * @param[in, out] matcher
7288 * @param[in, out] key
7289 * Flow matcher value.
7291 * Flow pattern to translate.
7293 * Item is inner pattern.
7296 flow_dv_translate_item_eth(void *matcher, void *key,
7297 const struct rte_flow_item *item, int inner,
7300 const struct rte_flow_item_eth *eth_m = item->mask;
7301 const struct rte_flow_item_eth *eth_v = item->spec;
7302 const struct rte_flow_item_eth nic_mask = {
7303 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
7304 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
7305 .type = RTE_BE16(0xffff),
7318 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7320 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7322 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7324 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7326 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, dmac_47_16),
7327 ð_m->dst, sizeof(eth_m->dst));
7328 /* The value must be in the range of the mask. */
7329 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, dmac_47_16);
7330 for (i = 0; i < sizeof(eth_m->dst); ++i)
7331 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
7332 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, smac_47_16),
7333 ð_m->src, sizeof(eth_m->src));
7334 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, smac_47_16);
7335 /* The value must be in the range of the mask. */
7336 for (i = 0; i < sizeof(eth_m->dst); ++i)
7337 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
7339 * HW supports match on one Ethertype, the Ethertype following the last
7340 * VLAN tag of the packet (see PRM).
7341 * Set match on ethertype only if ETH header is not followed by VLAN.
7342 * HW is optimized for IPv4/IPv6. In such cases, avoid setting
7343 * ethertype, and use ip_version field instead.
7344 * eCPRI over Ether layer will use type value 0xAEFE.
7346 if (eth_m->type == 0xFFFF) {
7347 /* Set cvlan_tag mask for any single\multi\un-tagged case. */
7348 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
7349 switch (eth_v->type) {
7350 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
7351 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
7353 case RTE_BE16(RTE_ETHER_TYPE_QINQ):
7354 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
7355 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
7357 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
7358 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
7360 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
7361 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
7367 if (eth_m->has_vlan) {
7368 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
7369 if (eth_v->has_vlan) {
7371 * Here, when also has_more_vlan field in VLAN item is
7372 * not set, only single-tagged packets will be matched.
7374 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
7378 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
7379 rte_be_to_cpu_16(eth_m->type));
7380 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, ethertype);
7381 *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
7385 * Add VLAN item to matcher and to the value.
7387 * @param[in, out] dev_flow
7389 * @param[in, out] matcher
7391 * @param[in, out] key
7392 * Flow matcher value.
7394 * Flow pattern to translate.
7396 * Item is inner pattern.
7399 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
7400 void *matcher, void *key,
7401 const struct rte_flow_item *item,
7402 int inner, uint32_t group)
7404 const struct rte_flow_item_vlan *vlan_m = item->mask;
7405 const struct rte_flow_item_vlan *vlan_v = item->spec;
7412 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7414 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7416 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7418 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7420 * This is workaround, masks are not supported,
7421 * and pre-validated.
7424 dev_flow->handle->vf_vlan.tag =
7425 rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
7428 * When VLAN item exists in flow, mark packet as tagged,
7429 * even if TCI is not specified.
7431 if (!MLX5_GET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag)) {
7432 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
7433 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
7438 vlan_m = &rte_flow_item_vlan_mask;
7439 tci_m = rte_be_to_cpu_16(vlan_m->tci);
7440 tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
7441 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_vid, tci_m);
7442 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_vid, tci_v);
7443 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_cfi, tci_m >> 12);
7444 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_cfi, tci_v >> 12);
7445 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_prio, tci_m >> 13);
7446 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_prio, tci_v >> 13);
7448 * HW is optimized for IPv4/IPv6. In such cases, avoid setting
7449 * ethertype, and use ip_version field instead.
7451 if (vlan_m->inner_type == 0xFFFF) {
7452 switch (vlan_v->inner_type) {
7453 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
7454 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
7455 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
7456 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
7458 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
7459 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
7461 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
7462 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
7468 if (vlan_m->has_more_vlan && vlan_v->has_more_vlan) {
7469 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
7470 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
7471 /* Only one vlan_tag bit can be set. */
7472 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
7475 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
7476 rte_be_to_cpu_16(vlan_m->inner_type));
7477 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, ethertype,
7478 rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
7482 * Add IPV4 item to matcher and to the value.
7484 * @param[in, out] matcher
7486 * @param[in, out] key
7487 * Flow matcher value.
7489 * Flow pattern to translate.
7491 * Item is inner pattern.
7493 * The group to insert the rule.
7496 flow_dv_translate_item_ipv4(void *matcher, void *key,
7497 const struct rte_flow_item *item,
7498 int inner, uint32_t group)
7500 const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
7501 const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
7502 const struct rte_flow_item_ipv4 nic_mask = {
7504 .src_addr = RTE_BE32(0xffffffff),
7505 .dst_addr = RTE_BE32(0xffffffff),
7506 .type_of_service = 0xff,
7507 .next_proto_id = 0xff,
7508 .time_to_live = 0xff,
7518 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7520 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7522 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7524 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7526 flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
7531 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
7532 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
7533 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
7534 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
7535 *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
7536 *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
7537 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
7538 src_ipv4_src_ipv6.ipv4_layout.ipv4);
7539 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
7540 src_ipv4_src_ipv6.ipv4_layout.ipv4);
7541 *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
7542 *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
7543 tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
7544 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
7545 ipv4_m->hdr.type_of_service);
7546 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
7547 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
7548 ipv4_m->hdr.type_of_service >> 2);
7549 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
7550 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
7551 ipv4_m->hdr.next_proto_id);
7552 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
7553 ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
7554 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
7555 ipv4_m->hdr.time_to_live);
7556 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
7557 ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
7558 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
7559 !!(ipv4_m->hdr.fragment_offset));
7560 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
7561 !!(ipv4_v->hdr.fragment_offset & ipv4_m->hdr.fragment_offset));
7565 * Add IPV6 item to matcher and to the value.
7567 * @param[in, out] matcher
7569 * @param[in, out] key
7570 * Flow matcher value.
7572 * Flow pattern to translate.
7574 * Item is inner pattern.
7576 * The group to insert the rule.
7579 flow_dv_translate_item_ipv6(void *matcher, void *key,
7580 const struct rte_flow_item *item,
7581 int inner, uint32_t group)
7583 const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
7584 const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
7585 const struct rte_flow_item_ipv6 nic_mask = {
7588 "\xff\xff\xff\xff\xff\xff\xff\xff"
7589 "\xff\xff\xff\xff\xff\xff\xff\xff",
7591 "\xff\xff\xff\xff\xff\xff\xff\xff"
7592 "\xff\xff\xff\xff\xff\xff\xff\xff",
7593 .vtc_flow = RTE_BE32(0xffffffff),
7600 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7601 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7610 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7612 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7614 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7616 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7618 flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
7623 size = sizeof(ipv6_m->hdr.dst_addr);
7624 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
7625 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
7626 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
7627 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
7628 memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
7629 for (i = 0; i < size; ++i)
7630 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
7631 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
7632 src_ipv4_src_ipv6.ipv6_layout.ipv6);
7633 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
7634 src_ipv4_src_ipv6.ipv6_layout.ipv6);
7635 memcpy(l24_m, ipv6_m->hdr.src_addr, size);
7636 for (i = 0; i < size; ++i)
7637 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
7639 vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
7640 vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
7641 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
7642 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
7643 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
7644 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
7647 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
7649 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
7652 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
7654 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
7658 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
7660 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
7661 ipv6_v->hdr.proto & ipv6_m->hdr.proto);
7663 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
7664 ipv6_m->hdr.hop_limits);
7665 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
7666 ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
7667 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
7668 !!(ipv6_m->has_frag_ext));
7669 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
7670 !!(ipv6_v->has_frag_ext & ipv6_m->has_frag_ext));
7674 * Add IPV6 fragment extension item to matcher and to the value.
7676 * @param[in, out] matcher
7678 * @param[in, out] key
7679 * Flow matcher value.
7681 * Flow pattern to translate.
7683 * Item is inner pattern.
7686 flow_dv_translate_item_ipv6_frag_ext(void *matcher, void *key,
7687 const struct rte_flow_item *item,
7690 const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_m = item->mask;
7691 const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_v = item->spec;
7692 const struct rte_flow_item_ipv6_frag_ext nic_mask = {
7694 .next_header = 0xff,
7695 .frag_data = RTE_BE16(0xffff),
7702 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7704 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7706 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7708 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7710 /* IPv6 fragment extension item exists, so packet is IP fragment. */
7711 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
7712 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 1);
7713 if (!ipv6_frag_ext_v)
7715 if (!ipv6_frag_ext_m)
7716 ipv6_frag_ext_m = &nic_mask;
7717 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
7718 ipv6_frag_ext_m->hdr.next_header);
7719 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
7720 ipv6_frag_ext_v->hdr.next_header &
7721 ipv6_frag_ext_m->hdr.next_header);
7725 * Add TCP item to matcher and to the value.
7727 * @param[in, out] matcher
7729 * @param[in, out] key
7730 * Flow matcher value.
7732 * Flow pattern to translate.
7734 * Item is inner pattern.
7737 flow_dv_translate_item_tcp(void *matcher, void *key,
7738 const struct rte_flow_item *item,
7741 const struct rte_flow_item_tcp *tcp_m = item->mask;
7742 const struct rte_flow_item_tcp *tcp_v = item->spec;
7747 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7749 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7751 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7753 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7755 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7756 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
7760 tcp_m = &rte_flow_item_tcp_mask;
7761 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
7762 rte_be_to_cpu_16(tcp_m->hdr.src_port));
7763 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
7764 rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
7765 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
7766 rte_be_to_cpu_16(tcp_m->hdr.dst_port));
7767 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
7768 rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
7769 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
7770 tcp_m->hdr.tcp_flags);
7771 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
7772 (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
7776 * Add UDP item to matcher and to the value.
7778 * @param[in, out] matcher
7780 * @param[in, out] key
7781 * Flow matcher value.
7783 * Flow pattern to translate.
7785 * Item is inner pattern.
7788 flow_dv_translate_item_udp(void *matcher, void *key,
7789 const struct rte_flow_item *item,
7792 const struct rte_flow_item_udp *udp_m = item->mask;
7793 const struct rte_flow_item_udp *udp_v = item->spec;
7798 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7800 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7802 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7804 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7806 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7807 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
7811 udp_m = &rte_flow_item_udp_mask;
7812 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
7813 rte_be_to_cpu_16(udp_m->hdr.src_port));
7814 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
7815 rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
7816 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
7817 rte_be_to_cpu_16(udp_m->hdr.dst_port));
7818 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
7819 rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
7823 * Add GRE optional Key item to matcher and to the value.
7825 * @param[in, out] matcher
7827 * @param[in, out] key
7828 * Flow matcher value.
7830 * Flow pattern to translate.
7832 * Item is inner pattern.
7835 flow_dv_translate_item_gre_key(void *matcher, void *key,
7836 const struct rte_flow_item *item)
7838 const rte_be32_t *key_m = item->mask;
7839 const rte_be32_t *key_v = item->spec;
7840 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7841 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7842 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
7844 /* GRE K bit must be on and should already be validated */
7845 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
7846 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
7850 key_m = &gre_key_default_mask;
7851 MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
7852 rte_be_to_cpu_32(*key_m) >> 8);
7853 MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
7854 rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
7855 MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
7856 rte_be_to_cpu_32(*key_m) & 0xFF);
7857 MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
7858 rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
7862 * Add GRE item to matcher and to the value.
7864 * @param[in, out] matcher
7866 * @param[in, out] key
7867 * Flow matcher value.
7869 * Flow pattern to translate.
7871 * Item is inner pattern.
7874 flow_dv_translate_item_gre(void *matcher, void *key,
7875 const struct rte_flow_item *item,
7878 const struct rte_flow_item_gre *gre_m = item->mask;
7879 const struct rte_flow_item_gre *gre_v = item->spec;
7882 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7883 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7890 uint16_t s_present:1;
7891 uint16_t k_present:1;
7892 uint16_t rsvd_bit1:1;
7893 uint16_t c_present:1;
7897 } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
7900 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7902 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7904 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7906 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7908 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7909 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
7913 gre_m = &rte_flow_item_gre_mask;
7914 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
7915 rte_be_to_cpu_16(gre_m->protocol));
7916 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
7917 rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
7918 gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
7919 gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
7920 MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
7921 gre_crks_rsvd0_ver_m.c_present);
7922 MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
7923 gre_crks_rsvd0_ver_v.c_present &
7924 gre_crks_rsvd0_ver_m.c_present);
7925 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
7926 gre_crks_rsvd0_ver_m.k_present);
7927 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
7928 gre_crks_rsvd0_ver_v.k_present &
7929 gre_crks_rsvd0_ver_m.k_present);
7930 MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
7931 gre_crks_rsvd0_ver_m.s_present);
7932 MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
7933 gre_crks_rsvd0_ver_v.s_present &
7934 gre_crks_rsvd0_ver_m.s_present);
7938 * Add NVGRE item to matcher and to the value.
7940 * @param[in, out] matcher
7942 * @param[in, out] key
7943 * Flow matcher value.
7945 * Flow pattern to translate.
7947 * Item is inner pattern.
7950 flow_dv_translate_item_nvgre(void *matcher, void *key,
7951 const struct rte_flow_item *item,
7954 const struct rte_flow_item_nvgre *nvgre_m = item->mask;
7955 const struct rte_flow_item_nvgre *nvgre_v = item->spec;
7956 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7957 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7958 const char *tni_flow_id_m;
7959 const char *tni_flow_id_v;
7965 /* For NVGRE, GRE header fields must be set with defined values. */
7966 const struct rte_flow_item_gre gre_spec = {
7967 .c_rsvd0_ver = RTE_BE16(0x2000),
7968 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
7970 const struct rte_flow_item_gre gre_mask = {
7971 .c_rsvd0_ver = RTE_BE16(0xB000),
7972 .protocol = RTE_BE16(UINT16_MAX),
7974 const struct rte_flow_item gre_item = {
7979 flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
7983 nvgre_m = &rte_flow_item_nvgre_mask;
7984 tni_flow_id_m = (const char *)nvgre_m->tni;
7985 tni_flow_id_v = (const char *)nvgre_v->tni;
7986 size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
7987 gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
7988 gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
7989 memcpy(gre_key_m, tni_flow_id_m, size);
7990 for (i = 0; i < size; ++i)
7991 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
7995 * Add VXLAN item to matcher and to the value.
7997 * @param[in, out] matcher
7999 * @param[in, out] key
8000 * Flow matcher value.
8002 * Flow pattern to translate.
8004 * Item is inner pattern.
8007 flow_dv_translate_item_vxlan(void *matcher, void *key,
8008 const struct rte_flow_item *item,
8011 const struct rte_flow_item_vxlan *vxlan_m = item->mask;
8012 const struct rte_flow_item_vxlan *vxlan_v = item->spec;
8015 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8016 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8024 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8026 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8028 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8030 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8032 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
8033 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
8034 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8035 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8036 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8041 vxlan_m = &rte_flow_item_vxlan_mask;
8042 size = sizeof(vxlan_m->vni);
8043 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
8044 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
8045 memcpy(vni_m, vxlan_m->vni, size);
8046 for (i = 0; i < size; ++i)
8047 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
8051 * Add VXLAN-GPE item to matcher and to the value.
8053 * @param[in, out] matcher
8055 * @param[in, out] key
8056 * Flow matcher value.
8058 * Flow pattern to translate.
8060 * Item is inner pattern.
8064 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
8065 const struct rte_flow_item *item, int inner)
8067 const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
8068 const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
8072 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
8074 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8080 uint8_t flags_m = 0xff;
8081 uint8_t flags_v = 0xc;
8084 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8086 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8088 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8090 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8092 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
8093 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
8094 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8095 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8096 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8101 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
8102 size = sizeof(vxlan_m->vni);
8103 vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
8104 vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
8105 memcpy(vni_m, vxlan_m->vni, size);
8106 for (i = 0; i < size; ++i)
8107 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
8108 if (vxlan_m->flags) {
8109 flags_m = vxlan_m->flags;
8110 flags_v = vxlan_v->flags;
8112 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
8113 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
8114 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
8116 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
8121 * Add Geneve item to matcher and to the value.
8123 * @param[in, out] matcher
8125 * @param[in, out] key
8126 * Flow matcher value.
8128 * Flow pattern to translate.
8130 * Item is inner pattern.
8134 flow_dv_translate_item_geneve(void *matcher, void *key,
8135 const struct rte_flow_item *item, int inner)
8137 const struct rte_flow_item_geneve *geneve_m = item->mask;
8138 const struct rte_flow_item_geneve *geneve_v = item->spec;
8141 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8142 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8151 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8153 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8155 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8157 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8159 dport = MLX5_UDP_PORT_GENEVE;
8160 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8161 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8162 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8167 geneve_m = &rte_flow_item_geneve_mask;
8168 size = sizeof(geneve_m->vni);
8169 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
8170 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
8171 memcpy(vni_m, geneve_m->vni, size);
8172 for (i = 0; i < size; ++i)
8173 vni_v[i] = vni_m[i] & geneve_v->vni[i];
8174 MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
8175 rte_be_to_cpu_16(geneve_m->protocol));
8176 MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
8177 rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
8178 gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
8179 gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
8180 MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
8181 MLX5_GENEVE_OAMF_VAL(gbhdr_m));
8182 MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
8183 MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
8184 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
8185 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
8186 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
8187 MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
8188 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
8192 * Create Geneve TLV option resource.
8194 * @param dev[in, out]
8195 * Pointer to rte_eth_dev structure.
8196 * @param[in, out] tag_be24
8197 * Tag value in big endian then R-shift 8.
8198 * @parm[in, out] dev_flow
8199 * Pointer to the dev_flow.
8201 * pointer to error structure.
8204 * 0 on success otherwise -errno and errno is set.
8208 flow_dev_geneve_tlv_option_resource_register(struct rte_eth_dev *dev,
8209 const struct rte_flow_item *item,
8210 struct rte_flow_error *error)
8212 struct mlx5_priv *priv = dev->data->dev_private;
8213 struct mlx5_dev_ctx_shared *sh = priv->sh;
8214 struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
8215 sh->geneve_tlv_option_resource;
8216 struct mlx5_devx_obj *obj;
8217 const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
8222 rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
8223 if (geneve_opt_resource != NULL) {
8224 if (geneve_opt_resource->option_class ==
8225 geneve_opt_v->option_class &&
8226 geneve_opt_resource->option_type ==
8227 geneve_opt_v->option_type &&
8228 geneve_opt_resource->length ==
8229 geneve_opt_v->option_len) {
8230 /* We already have GENVE TLV option obj allocated. */
8231 __atomic_fetch_add(&geneve_opt_resource->refcnt, 1,
8234 ret = rte_flow_error_set(error, ENOMEM,
8235 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8236 "Only one GENEVE TLV option supported");
8240 /* Create a GENEVE TLV object and resource. */
8241 obj = mlx5_devx_cmd_create_geneve_tlv_option(sh->ctx,
8242 geneve_opt_v->option_class,
8243 geneve_opt_v->option_type,
8244 geneve_opt_v->option_len);
8246 ret = rte_flow_error_set(error, ENODATA,
8247 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8248 "Failed to create GENEVE TLV Devx object");
8251 sh->geneve_tlv_option_resource =
8252 mlx5_malloc(MLX5_MEM_ZERO,
8253 sizeof(*geneve_opt_resource),
8255 if (!sh->geneve_tlv_option_resource) {
8256 claim_zero(mlx5_devx_cmd_destroy(obj));
8257 ret = rte_flow_error_set(error, ENOMEM,
8258 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8259 "GENEVE TLV object memory allocation failed");
8262 geneve_opt_resource = sh->geneve_tlv_option_resource;
8263 geneve_opt_resource->obj = obj;
8264 geneve_opt_resource->option_class = geneve_opt_v->option_class;
8265 geneve_opt_resource->option_type = geneve_opt_v->option_type;
8266 geneve_opt_resource->length = geneve_opt_v->option_len;
8267 __atomic_store_n(&geneve_opt_resource->refcnt, 1,
8271 rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
8276 * Add Geneve TLV option item to matcher.
8278 * @param[in, out] dev
8279 * Pointer to rte_eth_dev structure.
8280 * @param[in, out] matcher
8282 * @param[in, out] key
8283 * Flow matcher value.
8285 * Flow pattern to translate.
8287 * Pointer to error structure.
8290 flow_dv_translate_item_geneve_opt(struct rte_eth_dev *dev, void *matcher,
8291 void *key, const struct rte_flow_item *item,
8292 struct rte_flow_error *error)
8294 const struct rte_flow_item_geneve_opt *geneve_opt_m = item->mask;
8295 const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
8296 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8297 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8298 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8300 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8301 rte_be32_t opt_data_key = 0, opt_data_mask = 0;
8307 geneve_opt_m = &rte_flow_item_geneve_opt_mask;
8308 ret = flow_dev_geneve_tlv_option_resource_register(dev, item,
8311 DRV_LOG(ERR, "Failed to create geneve_tlv_obj");
8315 * Set the option length in GENEVE header if not requested.
8316 * The GENEVE TLV option length is expressed by the option length field
8317 * in the GENEVE header.
8318 * If the option length was not requested but the GENEVE TLV option item
8319 * is present we set the option length field implicitly.
8321 if (!MLX5_GET16(fte_match_set_misc, misc_m, geneve_opt_len)) {
8322 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
8323 MLX5_GENEVE_OPTLEN_MASK);
8324 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
8325 geneve_opt_v->option_len + 1);
8328 if (geneve_opt_v->data) {
8329 memcpy(&opt_data_key, geneve_opt_v->data,
8330 RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
8331 sizeof(opt_data_key)));
8332 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
8333 sizeof(opt_data_key));
8334 memcpy(&opt_data_mask, geneve_opt_m->data,
8335 RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
8336 sizeof(opt_data_mask)));
8337 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
8338 sizeof(opt_data_mask));
8339 MLX5_SET(fte_match_set_misc3, misc3_m,
8340 geneve_tlv_option_0_data,
8341 rte_be_to_cpu_32(opt_data_mask));
8342 MLX5_SET(fte_match_set_misc3, misc3_v,
8343 geneve_tlv_option_0_data,
8344 rte_be_to_cpu_32(opt_data_key & opt_data_mask));
8350 * Add MPLS item to matcher and to the value.
8352 * @param[in, out] matcher
8354 * @param[in, out] key
8355 * Flow matcher value.
8357 * Flow pattern to translate.
8358 * @param[in] prev_layer
8359 * The protocol layer indicated in previous item.
8361 * Item is inner pattern.
8364 flow_dv_translate_item_mpls(void *matcher, void *key,
8365 const struct rte_flow_item *item,
8366 uint64_t prev_layer,
8369 const uint32_t *in_mpls_m = item->mask;
8370 const uint32_t *in_mpls_v = item->spec;
8371 uint32_t *out_mpls_m = 0;
8372 uint32_t *out_mpls_v = 0;
8373 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8374 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8375 void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
8377 void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
8378 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
8379 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8381 switch (prev_layer) {
8382 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
8383 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
8384 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
8385 MLX5_UDP_PORT_MPLS);
8387 case MLX5_FLOW_LAYER_GRE:
8388 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
8389 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
8390 RTE_ETHER_TYPE_MPLS);
8393 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
8394 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8401 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
8402 switch (prev_layer) {
8403 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
8405 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
8406 outer_first_mpls_over_udp);
8408 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
8409 outer_first_mpls_over_udp);
8411 case MLX5_FLOW_LAYER_GRE:
8413 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
8414 outer_first_mpls_over_gre);
8416 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
8417 outer_first_mpls_over_gre);
8420 /* Inner MPLS not over GRE is not supported. */
8423 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
8427 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
8433 if (out_mpls_m && out_mpls_v) {
8434 *out_mpls_m = *in_mpls_m;
8435 *out_mpls_v = *in_mpls_v & *in_mpls_m;
8440 * Add metadata register item to matcher
8442 * @param[in, out] matcher
8444 * @param[in, out] key
8445 * Flow matcher value.
8446 * @param[in] reg_type
8447 * Type of device metadata register
8454 flow_dv_match_meta_reg(void *matcher, void *key,
8455 enum modify_reg reg_type,
8456 uint32_t data, uint32_t mask)
8459 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
8461 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
8467 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
8468 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
8471 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
8472 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
8476 * The metadata register C0 field might be divided into
8477 * source vport index and META item value, we should set
8478 * this field according to specified mask, not as whole one.
8480 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
8482 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
8483 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
8486 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
8489 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
8490 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
8493 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
8494 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
8497 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
8498 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
8501 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
8502 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
8505 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
8506 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
8509 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
8510 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
8513 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
8514 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
8523 * Add MARK item to matcher
8526 * The device to configure through.
8527 * @param[in, out] matcher
8529 * @param[in, out] key
8530 * Flow matcher value.
8532 * Flow pattern to translate.
8535 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
8536 void *matcher, void *key,
8537 const struct rte_flow_item *item)
8539 struct mlx5_priv *priv = dev->data->dev_private;
8540 const struct rte_flow_item_mark *mark;
8544 mark = item->mask ? (const void *)item->mask :
8545 &rte_flow_item_mark_mask;
8546 mask = mark->id & priv->sh->dv_mark_mask;
8547 mark = (const void *)item->spec;
8549 value = mark->id & priv->sh->dv_mark_mask & mask;
8551 enum modify_reg reg;
8553 /* Get the metadata register index for the mark. */
8554 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
8555 MLX5_ASSERT(reg > 0);
8556 if (reg == REG_C_0) {
8557 struct mlx5_priv *priv = dev->data->dev_private;
8558 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
8559 uint32_t shl_c0 = rte_bsf32(msk_c0);
8565 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
8570 * Add META item to matcher
8573 * The devich to configure through.
8574 * @param[in, out] matcher
8576 * @param[in, out] key
8577 * Flow matcher value.
8579 * Attributes of flow that includes this item.
8581 * Flow pattern to translate.
8584 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
8585 void *matcher, void *key,
8586 const struct rte_flow_attr *attr,
8587 const struct rte_flow_item *item)
8589 const struct rte_flow_item_meta *meta_m;
8590 const struct rte_flow_item_meta *meta_v;
8592 meta_m = (const void *)item->mask;
8594 meta_m = &rte_flow_item_meta_mask;
8595 meta_v = (const void *)item->spec;
8598 uint32_t value = meta_v->data;
8599 uint32_t mask = meta_m->data;
8601 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
8604 MLX5_ASSERT(reg != REG_NON);
8606 * In datapath code there is no endianness
8607 * coversions for perfromance reasons, all
8608 * pattern conversions are done in rte_flow.
8610 value = rte_cpu_to_be_32(value);
8611 mask = rte_cpu_to_be_32(mask);
8612 if (reg == REG_C_0) {
8613 struct mlx5_priv *priv = dev->data->dev_private;
8614 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
8615 uint32_t shl_c0 = rte_bsf32(msk_c0);
8616 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
8617 uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
8624 MLX5_ASSERT(msk_c0);
8625 MLX5_ASSERT(!(~msk_c0 & mask));
8627 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
8632 * Add vport metadata Reg C0 item to matcher
8634 * @param[in, out] matcher
8636 * @param[in, out] key
8637 * Flow matcher value.
8639 * Flow pattern to translate.
8642 flow_dv_translate_item_meta_vport(void *matcher, void *key,
8643 uint32_t value, uint32_t mask)
8645 flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
8649 * Add tag item to matcher
8652 * The devich to configure through.
8653 * @param[in, out] matcher
8655 * @param[in, out] key
8656 * Flow matcher value.
8658 * Flow pattern to translate.
8661 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
8662 void *matcher, void *key,
8663 const struct rte_flow_item *item)
8665 const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
8666 const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
8667 uint32_t mask, value;
8670 value = tag_v->data;
8671 mask = tag_m ? tag_m->data : UINT32_MAX;
8672 if (tag_v->id == REG_C_0) {
8673 struct mlx5_priv *priv = dev->data->dev_private;
8674 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
8675 uint32_t shl_c0 = rte_bsf32(msk_c0);
8681 flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
8685 * Add TAG item to matcher
8688 * The devich to configure through.
8689 * @param[in, out] matcher
8691 * @param[in, out] key
8692 * Flow matcher value.
8694 * Flow pattern to translate.
8697 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
8698 void *matcher, void *key,
8699 const struct rte_flow_item *item)
8701 const struct rte_flow_item_tag *tag_v = item->spec;
8702 const struct rte_flow_item_tag *tag_m = item->mask;
8703 enum modify_reg reg;
8706 tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
8707 /* Get the metadata register index for the tag. */
8708 reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
8709 MLX5_ASSERT(reg > 0);
8710 flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
8714 * Add source vport match to the specified matcher.
8716 * @param[in, out] matcher
8718 * @param[in, out] key
8719 * Flow matcher value.
8721 * Source vport value to match
8726 flow_dv_translate_item_source_vport(void *matcher, void *key,
8727 int16_t port, uint16_t mask)
8729 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8730 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8732 MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
8733 MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
8737 * Translate port-id item to eswitch match on port-id.
8740 * The devich to configure through.
8741 * @param[in, out] matcher
8743 * @param[in, out] key
8744 * Flow matcher value.
8746 * Flow pattern to translate.
8751 * 0 on success, a negative errno value otherwise.
8754 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
8755 void *key, const struct rte_flow_item *item,
8756 const struct rte_flow_attr *attr)
8758 const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
8759 const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
8760 struct mlx5_priv *priv;
8763 mask = pid_m ? pid_m->id : 0xffff;
8764 id = pid_v ? pid_v->id : dev->data->port_id;
8765 priv = mlx5_port_to_eswitch_info(id, item == NULL);
8769 * Translate to vport field or to metadata, depending on mode.
8770 * Kernel can use either misc.source_port or half of C0 metadata
8773 if (priv->vport_meta_mask) {
8775 * Provide the hint for SW steering library
8776 * to insert the flow into ingress domain and
8777 * save the extra vport match.
8779 if (mask == 0xffff && priv->vport_id == 0xffff &&
8780 priv->pf_bond < 0 && attr->transfer)
8781 flow_dv_translate_item_source_vport
8782 (matcher, key, priv->vport_id, mask);
8784 * We should always set the vport metadata register,
8785 * otherwise the SW steering library can drop
8786 * the rule if wire vport metadata value is not zero,
8787 * it depends on kernel configuration.
8789 flow_dv_translate_item_meta_vport(matcher, key,
8790 priv->vport_meta_tag,
8791 priv->vport_meta_mask);
8793 flow_dv_translate_item_source_vport(matcher, key,
8794 priv->vport_id, mask);
8800 * Add ICMP6 item to matcher and to the value.
8802 * @param[in, out] matcher
8804 * @param[in, out] key
8805 * Flow matcher value.
8807 * Flow pattern to translate.
8809 * Item is inner pattern.
8812 flow_dv_translate_item_icmp6(void *matcher, void *key,
8813 const struct rte_flow_item *item,
8816 const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
8817 const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
8820 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8822 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8824 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8826 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8828 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8830 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8832 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
8833 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
8837 icmp6_m = &rte_flow_item_icmp6_mask;
8838 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
8839 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
8840 icmp6_v->type & icmp6_m->type);
8841 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
8842 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
8843 icmp6_v->code & icmp6_m->code);
8847 * Add ICMP item to matcher and to the value.
8849 * @param[in, out] matcher
8851 * @param[in, out] key
8852 * Flow matcher value.
8854 * Flow pattern to translate.
8856 * Item is inner pattern.
8859 flow_dv_translate_item_icmp(void *matcher, void *key,
8860 const struct rte_flow_item *item,
8863 const struct rte_flow_item_icmp *icmp_m = item->mask;
8864 const struct rte_flow_item_icmp *icmp_v = item->spec;
8865 uint32_t icmp_header_data_m = 0;
8866 uint32_t icmp_header_data_v = 0;
8869 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8871 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8873 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8875 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8877 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8879 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8881 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
8882 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
8886 icmp_m = &rte_flow_item_icmp_mask;
8887 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
8888 icmp_m->hdr.icmp_type);
8889 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
8890 icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
8891 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
8892 icmp_m->hdr.icmp_code);
8893 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
8894 icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
8895 icmp_header_data_m = rte_be_to_cpu_16(icmp_m->hdr.icmp_seq_nb);
8896 icmp_header_data_m |= rte_be_to_cpu_16(icmp_m->hdr.icmp_ident) << 16;
8897 if (icmp_header_data_m) {
8898 icmp_header_data_v = rte_be_to_cpu_16(icmp_v->hdr.icmp_seq_nb);
8899 icmp_header_data_v |=
8900 rte_be_to_cpu_16(icmp_v->hdr.icmp_ident) << 16;
8901 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_header_data,
8902 icmp_header_data_m);
8903 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_header_data,
8904 icmp_header_data_v & icmp_header_data_m);
8909 * Add GTP item to matcher and to the value.
8911 * @param[in, out] matcher
8913 * @param[in, out] key
8914 * Flow matcher value.
8916 * Flow pattern to translate.
8918 * Item is inner pattern.
8921 flow_dv_translate_item_gtp(void *matcher, void *key,
8922 const struct rte_flow_item *item, int inner)
8924 const struct rte_flow_item_gtp *gtp_m = item->mask;
8925 const struct rte_flow_item_gtp *gtp_v = item->spec;
8928 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8930 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8931 uint16_t dport = RTE_GTPU_UDP_PORT;
8934 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8936 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8938 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8940 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8942 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8943 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8944 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8949 gtp_m = &rte_flow_item_gtp_mask;
8950 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags,
8951 gtp_m->v_pt_rsv_flags);
8952 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags,
8953 gtp_v->v_pt_rsv_flags & gtp_m->v_pt_rsv_flags);
8954 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
8955 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
8956 gtp_v->msg_type & gtp_m->msg_type);
8957 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
8958 rte_be_to_cpu_32(gtp_m->teid));
8959 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
8960 rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
8964 * Add GTP PSC item to matcher.
8966 * @param[in, out] matcher
8968 * @param[in, out] key
8969 * Flow matcher value.
8971 * Flow pattern to translate.
8974 flow_dv_translate_item_gtp_psc(void *matcher, void *key,
8975 const struct rte_flow_item *item)
8977 const struct rte_flow_item_gtp_psc *gtp_psc_m = item->mask;
8978 const struct rte_flow_item_gtp_psc *gtp_psc_v = item->spec;
8979 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8981 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8987 uint8_t next_ext_header_type;
8992 /* Always set E-flag match on one, regardless of GTP item settings. */
8993 gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_m, gtpu_msg_flags);
8994 gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
8995 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags, gtp_flags);
8996 gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_v, gtpu_msg_flags);
8997 gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
8998 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags, gtp_flags);
8999 /*Set next extension header type. */
9002 dw_2.next_ext_header_type = 0xff;
9003 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_dw_2,
9004 rte_cpu_to_be_32(dw_2.w32));
9007 dw_2.next_ext_header_type = 0x85;
9008 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_dw_2,
9009 rte_cpu_to_be_32(dw_2.w32));
9021 /*Set extension header PDU type and Qos. */
9023 gtp_psc_m = &rte_flow_item_gtp_psc_mask;
9025 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_m->pdu_type);
9026 dw_0.qfi = gtp_psc_m->qfi;
9027 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_first_ext_dw_0,
9028 rte_cpu_to_be_32(dw_0.w32));
9030 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_v->pdu_type &
9031 gtp_psc_m->pdu_type);
9032 dw_0.qfi = gtp_psc_v->qfi & gtp_psc_m->qfi;
9033 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_first_ext_dw_0,
9034 rte_cpu_to_be_32(dw_0.w32));
9040 * Add eCPRI item to matcher and to the value.
9043 * The devich to configure through.
9044 * @param[in, out] matcher
9046 * @param[in, out] key
9047 * Flow matcher value.
9049 * Flow pattern to translate.
9050 * @param[in] samples
9051 * Sample IDs to be used in the matching.
9054 flow_dv_translate_item_ecpri(struct rte_eth_dev *dev, void *matcher,
9055 void *key, const struct rte_flow_item *item)
9057 struct mlx5_priv *priv = dev->data->dev_private;
9058 const struct rte_flow_item_ecpri *ecpri_m = item->mask;
9059 const struct rte_flow_item_ecpri *ecpri_v = item->spec;
9060 struct rte_ecpri_common_hdr common;
9061 void *misc4_m = MLX5_ADDR_OF(fte_match_param, matcher,
9063 void *misc4_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_4);
9071 ecpri_m = &rte_flow_item_ecpri_mask;
9073 * Maximal four DW samples are supported in a single matching now.
9074 * Two are used now for a eCPRI matching:
9075 * 1. Type: one byte, mask should be 0x00ff0000 in network order
9076 * 2. ID of a message: one or two bytes, mask 0xffff0000 or 0xff000000
9079 if (!ecpri_m->hdr.common.u32)
9081 samples = priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0].ids;
9082 /* Need to take the whole DW as the mask to fill the entry. */
9083 dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
9084 prog_sample_field_value_0);
9085 dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
9086 prog_sample_field_value_0);
9087 /* Already big endian (network order) in the header. */
9088 *(uint32_t *)dw_m = ecpri_m->hdr.common.u32;
9089 *(uint32_t *)dw_v = ecpri_v->hdr.common.u32 & ecpri_m->hdr.common.u32;
9090 /* Sample#0, used for matching type, offset 0. */
9091 MLX5_SET(fte_match_set_misc4, misc4_m,
9092 prog_sample_field_id_0, samples[0]);
9093 /* It makes no sense to set the sample ID in the mask field. */
9094 MLX5_SET(fte_match_set_misc4, misc4_v,
9095 prog_sample_field_id_0, samples[0]);
9097 * Checking if message body part needs to be matched.
9098 * Some wildcard rules only matching type field should be supported.
9100 if (ecpri_m->hdr.dummy[0]) {
9101 common.u32 = rte_be_to_cpu_32(ecpri_v->hdr.common.u32);
9102 switch (common.type) {
9103 case RTE_ECPRI_MSG_TYPE_IQ_DATA:
9104 case RTE_ECPRI_MSG_TYPE_RTC_CTRL:
9105 case RTE_ECPRI_MSG_TYPE_DLY_MSR:
9106 dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
9107 prog_sample_field_value_1);
9108 dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
9109 prog_sample_field_value_1);
9110 *(uint32_t *)dw_m = ecpri_m->hdr.dummy[0];
9111 *(uint32_t *)dw_v = ecpri_v->hdr.dummy[0] &
9112 ecpri_m->hdr.dummy[0];
9113 /* Sample#1, to match message body, offset 4. */
9114 MLX5_SET(fte_match_set_misc4, misc4_m,
9115 prog_sample_field_id_1, samples[1]);
9116 MLX5_SET(fte_match_set_misc4, misc4_v,
9117 prog_sample_field_id_1, samples[1]);
9120 /* Others, do not match any sample ID. */
9126 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
9128 #define HEADER_IS_ZERO(match_criteria, headers) \
9129 !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
9130 matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
9133 * Calculate flow matcher enable bitmap.
9135 * @param match_criteria
9136 * Pointer to flow matcher criteria.
9139 * Bitmap of enabled fields.
9142 flow_dv_matcher_enable(uint32_t *match_criteria)
9144 uint8_t match_criteria_enable;
9146 match_criteria_enable =
9147 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
9148 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
9149 match_criteria_enable |=
9150 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
9151 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
9152 match_criteria_enable |=
9153 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
9154 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
9155 match_criteria_enable |=
9156 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
9157 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
9158 match_criteria_enable |=
9159 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
9160 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
9161 match_criteria_enable |=
9162 (!HEADER_IS_ZERO(match_criteria, misc_parameters_4)) <<
9163 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT;
9164 return match_criteria_enable;
9167 struct mlx5_hlist_entry *
9168 flow_dv_tbl_create_cb(struct mlx5_hlist *list, uint64_t key64, void *cb_ctx)
9170 struct mlx5_dev_ctx_shared *sh = list->ctx;
9171 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9172 struct rte_eth_dev *dev = ctx->dev;
9173 struct mlx5_flow_tbl_data_entry *tbl_data;
9174 struct mlx5_flow_tbl_tunnel_prm *tt_prm = ctx->data;
9175 struct rte_flow_error *error = ctx->error;
9176 union mlx5_flow_tbl_key key = { .v64 = key64 };
9177 struct mlx5_flow_tbl_resource *tbl;
9182 tbl_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
9184 rte_flow_error_set(error, ENOMEM,
9185 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9187 "cannot allocate flow table data entry");
9190 tbl_data->idx = idx;
9191 tbl_data->tunnel = tt_prm->tunnel;
9192 tbl_data->group_id = tt_prm->group_id;
9193 tbl_data->external = !!tt_prm->external;
9194 tbl_data->tunnel_offload = is_tunnel_offload_active(dev);
9195 tbl_data->is_egress = !!key.direction;
9196 tbl_data->is_transfer = !!key.domain;
9197 tbl_data->dummy = !!key.dummy;
9198 tbl_data->table_id = key.table_id;
9199 tbl = &tbl_data->tbl;
9201 return &tbl_data->entry;
9203 domain = sh->fdb_domain;
9204 else if (key.direction)
9205 domain = sh->tx_domain;
9207 domain = sh->rx_domain;
9208 ret = mlx5_flow_os_create_flow_tbl(domain, key.table_id, &tbl->obj);
9210 rte_flow_error_set(error, ENOMEM,
9211 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9212 NULL, "cannot create flow table object");
9213 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
9217 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
9218 (tbl->obj, &tbl_data->jump.action);
9220 rte_flow_error_set(error, ENOMEM,
9221 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9223 "cannot create flow jump action");
9224 mlx5_flow_os_destroy_flow_tbl(tbl->obj);
9225 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
9229 MKSTR(matcher_name, "%s_%s_%u_matcher_cache",
9230 key.domain ? "FDB" : "NIC", key.direction ? "egress" : "ingress",
9232 mlx5_cache_list_init(&tbl_data->matchers, matcher_name, 0, sh,
9233 flow_dv_matcher_create_cb,
9234 flow_dv_matcher_match_cb,
9235 flow_dv_matcher_remove_cb);
9236 return &tbl_data->entry;
9240 flow_dv_tbl_match_cb(struct mlx5_hlist *list __rte_unused,
9241 struct mlx5_hlist_entry *entry, uint64_t key64,
9242 void *cb_ctx __rte_unused)
9244 struct mlx5_flow_tbl_data_entry *tbl_data =
9245 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
9246 union mlx5_flow_tbl_key key = { .v64 = key64 };
9248 return tbl_data->table_id != key.table_id ||
9249 tbl_data->dummy != key.dummy ||
9250 tbl_data->is_transfer != key.domain ||
9251 tbl_data->is_egress != key.direction;
9257 * @param[in, out] dev
9258 * Pointer to rte_eth_dev structure.
9259 * @param[in] table_id
9262 * Direction of the table.
9263 * @param[in] transfer
9264 * E-Switch or NIC flow.
9266 * Dummy entry for dv API.
9268 * pointer to error structure.
9271 * Returns tables resource based on the index, NULL in case of failed.
9273 struct mlx5_flow_tbl_resource *
9274 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
9275 uint32_t table_id, uint8_t egress,
9278 const struct mlx5_flow_tunnel *tunnel,
9279 uint32_t group_id, uint8_t dummy,
9280 struct rte_flow_error *error)
9282 struct mlx5_priv *priv = dev->data->dev_private;
9283 union mlx5_flow_tbl_key table_key = {
9285 .table_id = table_id,
9287 .domain = !!transfer,
9288 .direction = !!egress,
9291 struct mlx5_flow_tbl_tunnel_prm tt_prm = {
9293 .group_id = group_id,
9294 .external = external,
9296 struct mlx5_flow_cb_ctx ctx = {
9301 struct mlx5_hlist_entry *entry;
9302 struct mlx5_flow_tbl_data_entry *tbl_data;
9304 entry = mlx5_hlist_register(priv->sh->flow_tbls, table_key.v64, &ctx);
9306 rte_flow_error_set(error, ENOMEM,
9307 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9308 "cannot get table");
9311 DRV_LOG(DEBUG, "Table_id %u tunnel %u group %u registered.",
9312 table_id, tunnel ? tunnel->tunnel_id : 0, group_id);
9313 tbl_data = container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
9314 return &tbl_data->tbl;
9318 flow_dv_tbl_remove_cb(struct mlx5_hlist *list,
9319 struct mlx5_hlist_entry *entry)
9321 struct mlx5_dev_ctx_shared *sh = list->ctx;
9322 struct mlx5_flow_tbl_data_entry *tbl_data =
9323 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
9325 MLX5_ASSERT(entry && sh);
9326 if (tbl_data->jump.action)
9327 mlx5_flow_os_destroy_flow_action(tbl_data->jump.action);
9328 if (tbl_data->tbl.obj)
9329 mlx5_flow_os_destroy_flow_tbl(tbl_data->tbl.obj);
9330 if (tbl_data->tunnel_offload && tbl_data->external) {
9331 struct mlx5_hlist_entry *he;
9332 struct mlx5_hlist *tunnel_grp_hash;
9333 struct mlx5_flow_tunnel_hub *thub = sh->tunnel_hub;
9334 union tunnel_tbl_key tunnel_key = {
9335 .tunnel_id = tbl_data->tunnel ?
9336 tbl_data->tunnel->tunnel_id : 0,
9337 .group = tbl_data->group_id
9339 uint32_t table_id = tbl_data->table_id;
9341 tunnel_grp_hash = tbl_data->tunnel ?
9342 tbl_data->tunnel->groups :
9344 he = mlx5_hlist_lookup(tunnel_grp_hash, tunnel_key.val, NULL);
9346 mlx5_hlist_unregister(tunnel_grp_hash, he);
9348 "Table_id %u tunnel %u group %u released.",
9351 tbl_data->tunnel->tunnel_id : 0,
9352 tbl_data->group_id);
9354 mlx5_cache_list_destroy(&tbl_data->matchers);
9355 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], tbl_data->idx);
9359 * Release a flow table.
9362 * Pointer to device shared structure.
9364 * Table resource to be released.
9367 * Returns 0 if table was released, else return 1;
9370 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
9371 struct mlx5_flow_tbl_resource *tbl)
9373 struct mlx5_flow_tbl_data_entry *tbl_data =
9374 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
9378 return mlx5_hlist_unregister(sh->flow_tbls, &tbl_data->entry);
9382 flow_dv_matcher_match_cb(struct mlx5_cache_list *list __rte_unused,
9383 struct mlx5_cache_entry *entry, void *cb_ctx)
9385 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9386 struct mlx5_flow_dv_matcher *ref = ctx->data;
9387 struct mlx5_flow_dv_matcher *cur = container_of(entry, typeof(*cur),
9390 return cur->crc != ref->crc ||
9391 cur->priority != ref->priority ||
9392 memcmp((const void *)cur->mask.buf,
9393 (const void *)ref->mask.buf, ref->mask.size);
9396 struct mlx5_cache_entry *
9397 flow_dv_matcher_create_cb(struct mlx5_cache_list *list,
9398 struct mlx5_cache_entry *entry __rte_unused,
9401 struct mlx5_dev_ctx_shared *sh = list->ctx;
9402 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9403 struct mlx5_flow_dv_matcher *ref = ctx->data;
9404 struct mlx5_flow_dv_matcher *cache;
9405 struct mlx5dv_flow_matcher_attr dv_attr = {
9406 .type = IBV_FLOW_ATTR_NORMAL,
9407 .match_mask = (void *)&ref->mask,
9409 struct mlx5_flow_tbl_data_entry *tbl = container_of(ref->tbl,
9413 cache = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*cache), 0, SOCKET_ID_ANY);
9415 rte_flow_error_set(ctx->error, ENOMEM,
9416 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9417 "cannot create matcher");
9421 dv_attr.match_criteria_enable =
9422 flow_dv_matcher_enable(cache->mask.buf);
9423 dv_attr.priority = ref->priority;
9425 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
9426 ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->tbl.obj,
9427 &cache->matcher_object);
9430 rte_flow_error_set(ctx->error, ENOMEM,
9431 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9432 "cannot create matcher");
9435 return &cache->entry;
9439 * Register the flow matcher.
9441 * @param[in, out] dev
9442 * Pointer to rte_eth_dev structure.
9443 * @param[in, out] matcher
9444 * Pointer to flow matcher.
9445 * @param[in, out] key
9446 * Pointer to flow table key.
9447 * @parm[in, out] dev_flow
9448 * Pointer to the dev_flow.
9450 * pointer to error structure.
9453 * 0 on success otherwise -errno and errno is set.
9456 flow_dv_matcher_register(struct rte_eth_dev *dev,
9457 struct mlx5_flow_dv_matcher *ref,
9458 union mlx5_flow_tbl_key *key,
9459 struct mlx5_flow *dev_flow,
9460 const struct mlx5_flow_tunnel *tunnel,
9462 struct rte_flow_error *error)
9464 struct mlx5_cache_entry *entry;
9465 struct mlx5_flow_dv_matcher *cache;
9466 struct mlx5_flow_tbl_resource *tbl;
9467 struct mlx5_flow_tbl_data_entry *tbl_data;
9468 struct mlx5_flow_cb_ctx ctx = {
9474 * tunnel offload API requires this registration for cases when
9475 * tunnel match rule was inserted before tunnel set rule.
9477 tbl = flow_dv_tbl_resource_get(dev, key->table_id,
9478 key->direction, key->domain,
9479 dev_flow->external, tunnel,
9480 group_id, 0, error);
9482 return -rte_errno; /* No need to refill the error info */
9483 tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
9485 entry = mlx5_cache_register(&tbl_data->matchers, &ctx);
9487 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
9488 return rte_flow_error_set(error, ENOMEM,
9489 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9490 "cannot allocate ref memory");
9492 cache = container_of(entry, typeof(*cache), entry);
9493 dev_flow->handle->dvh.matcher = cache;
9497 struct mlx5_hlist_entry *
9498 flow_dv_tag_create_cb(struct mlx5_hlist *list, uint64_t key, void *ctx)
9500 struct mlx5_dev_ctx_shared *sh = list->ctx;
9501 struct rte_flow_error *error = ctx;
9502 struct mlx5_flow_dv_tag_resource *entry;
9506 entry = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_TAG], &idx);
9508 rte_flow_error_set(error, ENOMEM,
9509 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9510 "cannot allocate resource memory");
9514 entry->tag_id = key;
9515 ret = mlx5_flow_os_create_flow_action_tag(key,
9518 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], idx);
9519 rte_flow_error_set(error, ENOMEM,
9520 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9521 NULL, "cannot create action");
9524 return &entry->entry;
9528 flow_dv_tag_match_cb(struct mlx5_hlist *list __rte_unused,
9529 struct mlx5_hlist_entry *entry, uint64_t key,
9530 void *cb_ctx __rte_unused)
9532 struct mlx5_flow_dv_tag_resource *tag =
9533 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
9535 return key != tag->tag_id;
9539 * Find existing tag resource or create and register a new one.
9541 * @param dev[in, out]
9542 * Pointer to rte_eth_dev structure.
9543 * @param[in, out] tag_be24
9544 * Tag value in big endian then R-shift 8.
9545 * @parm[in, out] dev_flow
9546 * Pointer to the dev_flow.
9548 * pointer to error structure.
9551 * 0 on success otherwise -errno and errno is set.
9554 flow_dv_tag_resource_register
9555 (struct rte_eth_dev *dev,
9557 struct mlx5_flow *dev_flow,
9558 struct rte_flow_error *error)
9560 struct mlx5_priv *priv = dev->data->dev_private;
9561 struct mlx5_flow_dv_tag_resource *cache_resource;
9562 struct mlx5_hlist_entry *entry;
9564 entry = mlx5_hlist_register(priv->sh->tag_table, tag_be24, error);
9566 cache_resource = container_of
9567 (entry, struct mlx5_flow_dv_tag_resource, entry);
9568 dev_flow->handle->dvh.rix_tag = cache_resource->idx;
9569 dev_flow->dv.tag_resource = cache_resource;
9576 flow_dv_tag_remove_cb(struct mlx5_hlist *list,
9577 struct mlx5_hlist_entry *entry)
9579 struct mlx5_dev_ctx_shared *sh = list->ctx;
9580 struct mlx5_flow_dv_tag_resource *tag =
9581 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
9583 MLX5_ASSERT(tag && sh && tag->action);
9584 claim_zero(mlx5_flow_os_destroy_flow_action(tag->action));
9585 DRV_LOG(DEBUG, "Tag %p: removed.", (void *)tag);
9586 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], tag->idx);
9593 * Pointer to Ethernet device.
9598 * 1 while a reference on it exists, 0 when freed.
9601 flow_dv_tag_release(struct rte_eth_dev *dev,
9604 struct mlx5_priv *priv = dev->data->dev_private;
9605 struct mlx5_flow_dv_tag_resource *tag;
9607 tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
9610 DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
9611 dev->data->port_id, (void *)tag, tag->entry.ref_cnt);
9612 return mlx5_hlist_unregister(priv->sh->tag_table, &tag->entry);
9616 * Translate port ID action to vport.
9619 * Pointer to rte_eth_dev structure.
9621 * Pointer to the port ID action.
9622 * @param[out] dst_port_id
9623 * The target port ID.
9625 * Pointer to the error structure.
9628 * 0 on success, a negative errno value otherwise and rte_errno is set.
9631 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
9632 const struct rte_flow_action *action,
9633 uint32_t *dst_port_id,
9634 struct rte_flow_error *error)
9637 struct mlx5_priv *priv;
9638 const struct rte_flow_action_port_id *conf =
9639 (const struct rte_flow_action_port_id *)action->conf;
9641 port = conf->original ? dev->data->port_id : conf->id;
9642 priv = mlx5_port_to_eswitch_info(port, false);
9644 return rte_flow_error_set(error, -rte_errno,
9645 RTE_FLOW_ERROR_TYPE_ACTION,
9647 "No eswitch info was found for port");
9648 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
9650 * This parameter is transferred to
9651 * mlx5dv_dr_action_create_dest_ib_port().
9653 *dst_port_id = priv->dev_port;
9656 * Legacy mode, no LAG configurations is supported.
9657 * This parameter is transferred to
9658 * mlx5dv_dr_action_create_dest_vport().
9660 *dst_port_id = priv->vport_id;
9666 * Create a counter with aging configuration.
9669 * Pointer to rte_eth_dev structure.
9671 * Pointer to the counter action configuration.
9673 * Pointer to the aging action configuration.
9676 * Index to flow counter on success, 0 otherwise.
9679 flow_dv_translate_create_counter(struct rte_eth_dev *dev,
9680 struct mlx5_flow *dev_flow,
9681 const struct rte_flow_action_count *count,
9682 const struct rte_flow_action_age *age)
9685 struct mlx5_age_param *age_param;
9687 if (count && count->shared)
9688 counter = flow_dv_counter_get_shared(dev, count->id);
9690 counter = flow_dv_counter_alloc(dev, !!age);
9691 if (!counter || age == NULL)
9693 age_param = flow_dv_counter_idx_get_age(dev, counter);
9694 age_param->context = age->context ? age->context :
9695 (void *)(uintptr_t)(dev_flow->flow_idx);
9696 age_param->timeout = age->timeout;
9697 age_param->port_id = dev->data->port_id;
9698 __atomic_store_n(&age_param->sec_since_last_hit, 0, __ATOMIC_RELAXED);
9699 __atomic_store_n(&age_param->state, AGE_CANDIDATE, __ATOMIC_RELAXED);
9704 * Add Tx queue matcher
9707 * Pointer to the dev struct.
9708 * @param[in, out] matcher
9710 * @param[in, out] key
9711 * Flow matcher value.
9713 * Flow pattern to translate.
9715 * Item is inner pattern.
9718 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
9719 void *matcher, void *key,
9720 const struct rte_flow_item *item)
9722 const struct mlx5_rte_flow_item_tx_queue *queue_m;
9723 const struct mlx5_rte_flow_item_tx_queue *queue_v;
9725 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
9727 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
9728 struct mlx5_txq_ctrl *txq;
9732 queue_m = (const void *)item->mask;
9735 queue_v = (const void *)item->spec;
9738 txq = mlx5_txq_get(dev, queue_v->queue);
9741 queue = txq->obj->sq->id;
9742 MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
9743 MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
9744 queue & queue_m->queue);
9745 mlx5_txq_release(dev, queue_v->queue);
9749 * Set the hash fields according to the @p flow information.
9751 * @param[in] dev_flow
9752 * Pointer to the mlx5_flow.
9753 * @param[in] rss_desc
9754 * Pointer to the mlx5_flow_rss_desc.
9757 flow_dv_hashfields_set(struct mlx5_flow *dev_flow,
9758 struct mlx5_flow_rss_desc *rss_desc)
9760 uint64_t items = dev_flow->handle->layers;
9762 uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
9764 dev_flow->hash_fields = 0;
9765 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
9766 if (rss_desc->level >= 2) {
9767 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
9771 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
9772 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
9773 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
9774 if (rss_types & ETH_RSS_L3_SRC_ONLY)
9775 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
9776 else if (rss_types & ETH_RSS_L3_DST_ONLY)
9777 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
9779 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
9781 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
9782 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
9783 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
9784 if (rss_types & ETH_RSS_L3_SRC_ONLY)
9785 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
9786 else if (rss_types & ETH_RSS_L3_DST_ONLY)
9787 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
9789 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
9792 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
9793 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
9794 if (rss_types & ETH_RSS_UDP) {
9795 if (rss_types & ETH_RSS_L4_SRC_ONLY)
9796 dev_flow->hash_fields |=
9797 IBV_RX_HASH_SRC_PORT_UDP;
9798 else if (rss_types & ETH_RSS_L4_DST_ONLY)
9799 dev_flow->hash_fields |=
9800 IBV_RX_HASH_DST_PORT_UDP;
9802 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
9804 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
9805 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
9806 if (rss_types & ETH_RSS_TCP) {
9807 if (rss_types & ETH_RSS_L4_SRC_ONLY)
9808 dev_flow->hash_fields |=
9809 IBV_RX_HASH_SRC_PORT_TCP;
9810 else if (rss_types & ETH_RSS_L4_DST_ONLY)
9811 dev_flow->hash_fields |=
9812 IBV_RX_HASH_DST_PORT_TCP;
9814 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
9820 * Prepare an Rx Hash queue.
9823 * Pointer to Ethernet device.
9824 * @param[in] dev_flow
9825 * Pointer to the mlx5_flow.
9826 * @param[in] rss_desc
9827 * Pointer to the mlx5_flow_rss_desc.
9828 * @param[out] hrxq_idx
9829 * Hash Rx queue index.
9832 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
9834 static struct mlx5_hrxq *
9835 flow_dv_hrxq_prepare(struct rte_eth_dev *dev,
9836 struct mlx5_flow *dev_flow,
9837 struct mlx5_flow_rss_desc *rss_desc,
9840 struct mlx5_priv *priv = dev->data->dev_private;
9841 struct mlx5_flow_handle *dh = dev_flow->handle;
9842 struct mlx5_hrxq *hrxq;
9844 MLX5_ASSERT(rss_desc->queue_num);
9845 rss_desc->key_len = MLX5_RSS_HASH_KEY_LEN;
9846 rss_desc->hash_fields = dev_flow->hash_fields;
9847 rss_desc->tunnel = !!(dh->layers & MLX5_FLOW_LAYER_TUNNEL);
9848 rss_desc->shared_rss = 0;
9849 *hrxq_idx = mlx5_hrxq_get(dev, rss_desc);
9852 hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
9858 * Release sample sub action resource.
9860 * @param[in, out] dev
9861 * Pointer to rte_eth_dev structure.
9862 * @param[in] act_res
9863 * Pointer to sample sub action resource.
9866 flow_dv_sample_sub_actions_release(struct rte_eth_dev *dev,
9867 struct mlx5_flow_sub_actions_idx *act_res)
9869 if (act_res->rix_hrxq) {
9870 mlx5_hrxq_release(dev, act_res->rix_hrxq);
9871 act_res->rix_hrxq = 0;
9873 if (act_res->rix_encap_decap) {
9874 flow_dv_encap_decap_resource_release(dev,
9875 act_res->rix_encap_decap);
9876 act_res->rix_encap_decap = 0;
9878 if (act_res->rix_port_id_action) {
9879 flow_dv_port_id_action_resource_release(dev,
9880 act_res->rix_port_id_action);
9881 act_res->rix_port_id_action = 0;
9883 if (act_res->rix_tag) {
9884 flow_dv_tag_release(dev, act_res->rix_tag);
9885 act_res->rix_tag = 0;
9887 if (act_res->rix_jump) {
9888 flow_dv_jump_tbl_resource_release(dev, act_res->rix_jump);
9889 act_res->rix_jump = 0;
9894 flow_dv_sample_match_cb(struct mlx5_cache_list *list __rte_unused,
9895 struct mlx5_cache_entry *entry, void *cb_ctx)
9897 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9898 struct rte_eth_dev *dev = ctx->dev;
9899 struct mlx5_flow_dv_sample_resource *resource = ctx->data;
9900 struct mlx5_flow_dv_sample_resource *cache_resource =
9901 container_of(entry, typeof(*cache_resource), entry);
9903 if (resource->ratio == cache_resource->ratio &&
9904 resource->ft_type == cache_resource->ft_type &&
9905 resource->ft_id == cache_resource->ft_id &&
9906 resource->set_action == cache_resource->set_action &&
9907 !memcmp((void *)&resource->sample_act,
9908 (void *)&cache_resource->sample_act,
9909 sizeof(struct mlx5_flow_sub_actions_list))) {
9911 * Existing sample action should release the prepared
9912 * sub-actions reference counter.
9914 flow_dv_sample_sub_actions_release(dev,
9915 &resource->sample_idx);
9921 struct mlx5_cache_entry *
9922 flow_dv_sample_create_cb(struct mlx5_cache_list *list __rte_unused,
9923 struct mlx5_cache_entry *entry __rte_unused,
9926 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9927 struct rte_eth_dev *dev = ctx->dev;
9928 struct mlx5_flow_dv_sample_resource *resource = ctx->data;
9929 void **sample_dv_actions = resource->sub_actions;
9930 struct mlx5_flow_dv_sample_resource *cache_resource;
9931 struct mlx5dv_dr_flow_sampler_attr sampler_attr;
9932 struct mlx5_priv *priv = dev->data->dev_private;
9933 struct mlx5_dev_ctx_shared *sh = priv->sh;
9934 struct mlx5_flow_tbl_resource *tbl;
9936 const uint32_t next_ft_step = 1;
9937 uint32_t next_ft_id = resource->ft_id + next_ft_step;
9938 uint8_t is_egress = 0;
9939 uint8_t is_transfer = 0;
9940 struct rte_flow_error *error = ctx->error;
9942 /* Register new sample resource. */
9943 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_SAMPLE], &idx);
9944 if (!cache_resource) {
9945 rte_flow_error_set(error, ENOMEM,
9946 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9948 "cannot allocate resource memory");
9951 *cache_resource = *resource;
9952 /* Create normal path table level */
9953 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
9955 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
9957 tbl = flow_dv_tbl_resource_get(dev, next_ft_id,
9958 is_egress, is_transfer,
9959 true, NULL, 0, 0, error);
9961 rte_flow_error_set(error, ENOMEM,
9962 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9964 "fail to create normal path table "
9968 cache_resource->normal_path_tbl = tbl;
9969 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB) {
9970 if (!sh->default_miss_action) {
9971 rte_flow_error_set(error, ENOMEM,
9972 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9974 "default miss action was not "
9978 sample_dv_actions[resource->sample_act.actions_num++] =
9979 sh->default_miss_action;
9981 /* Create a DR sample action */
9982 sampler_attr.sample_ratio = cache_resource->ratio;
9983 sampler_attr.default_next_table = tbl->obj;
9984 sampler_attr.num_sample_actions = resource->sample_act.actions_num;
9985 sampler_attr.sample_actions = (struct mlx5dv_dr_action **)
9986 &sample_dv_actions[0];
9987 sampler_attr.action = cache_resource->set_action;
9988 if (mlx5_os_flow_dr_create_flow_action_sampler
9989 (&sampler_attr, &cache_resource->verbs_action)) {
9990 rte_flow_error_set(error, ENOMEM,
9991 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9992 NULL, "cannot create sample action");
9995 cache_resource->idx = idx;
9996 cache_resource->dev = dev;
9997 return &cache_resource->entry;
9999 if (cache_resource->ft_type != MLX5DV_FLOW_TABLE_TYPE_FDB)
10000 flow_dv_sample_sub_actions_release(dev,
10001 &cache_resource->sample_idx);
10002 if (cache_resource->normal_path_tbl)
10003 flow_dv_tbl_resource_release(MLX5_SH(dev),
10004 cache_resource->normal_path_tbl);
10005 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_SAMPLE], idx);
10011 * Find existing sample resource or create and register a new one.
10013 * @param[in, out] dev
10014 * Pointer to rte_eth_dev structure.
10015 * @param[in] resource
10016 * Pointer to sample resource.
10017 * @parm[in, out] dev_flow
10018 * Pointer to the dev_flow.
10019 * @param[out] error
10020 * pointer to error structure.
10023 * 0 on success otherwise -errno and errno is set.
10026 flow_dv_sample_resource_register(struct rte_eth_dev *dev,
10027 struct mlx5_flow_dv_sample_resource *resource,
10028 struct mlx5_flow *dev_flow,
10029 struct rte_flow_error *error)
10031 struct mlx5_flow_dv_sample_resource *cache_resource;
10032 struct mlx5_cache_entry *entry;
10033 struct mlx5_priv *priv = dev->data->dev_private;
10034 struct mlx5_flow_cb_ctx ctx = {
10040 entry = mlx5_cache_register(&priv->sh->sample_action_list, &ctx);
10043 cache_resource = container_of(entry, typeof(*cache_resource), entry);
10044 dev_flow->handle->dvh.rix_sample = cache_resource->idx;
10045 dev_flow->dv.sample_res = cache_resource;
10050 flow_dv_dest_array_match_cb(struct mlx5_cache_list *list __rte_unused,
10051 struct mlx5_cache_entry *entry, void *cb_ctx)
10053 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10054 struct mlx5_flow_dv_dest_array_resource *resource = ctx->data;
10055 struct rte_eth_dev *dev = ctx->dev;
10056 struct mlx5_flow_dv_dest_array_resource *cache_resource =
10057 container_of(entry, typeof(*cache_resource), entry);
10060 if (resource->num_of_dest == cache_resource->num_of_dest &&
10061 resource->ft_type == cache_resource->ft_type &&
10062 !memcmp((void *)cache_resource->sample_act,
10063 (void *)resource->sample_act,
10064 (resource->num_of_dest *
10065 sizeof(struct mlx5_flow_sub_actions_list)))) {
10067 * Existing sample action should release the prepared
10068 * sub-actions reference counter.
10070 for (idx = 0; idx < resource->num_of_dest; idx++)
10071 flow_dv_sample_sub_actions_release(dev,
10072 &resource->sample_idx[idx]);
10078 struct mlx5_cache_entry *
10079 flow_dv_dest_array_create_cb(struct mlx5_cache_list *list __rte_unused,
10080 struct mlx5_cache_entry *entry __rte_unused,
10083 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10084 struct rte_eth_dev *dev = ctx->dev;
10085 struct mlx5_flow_dv_dest_array_resource *cache_resource;
10086 struct mlx5_flow_dv_dest_array_resource *resource = ctx->data;
10087 struct mlx5dv_dr_action_dest_attr *dest_attr[MLX5_MAX_DEST_NUM] = { 0 };
10088 struct mlx5dv_dr_action_dest_reformat dest_reformat[MLX5_MAX_DEST_NUM];
10089 struct mlx5_priv *priv = dev->data->dev_private;
10090 struct mlx5_dev_ctx_shared *sh = priv->sh;
10091 struct mlx5_flow_sub_actions_list *sample_act;
10092 struct mlx5dv_dr_domain *domain;
10093 uint32_t idx = 0, res_idx = 0;
10094 struct rte_flow_error *error = ctx->error;
10095 uint64_t action_flags;
10098 /* Register new destination array resource. */
10099 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
10101 if (!cache_resource) {
10102 rte_flow_error_set(error, ENOMEM,
10103 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10105 "cannot allocate resource memory");
10108 *cache_resource = *resource;
10109 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
10110 domain = sh->fdb_domain;
10111 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
10112 domain = sh->rx_domain;
10114 domain = sh->tx_domain;
10115 for (idx = 0; idx < resource->num_of_dest; idx++) {
10116 dest_attr[idx] = (struct mlx5dv_dr_action_dest_attr *)
10117 mlx5_malloc(MLX5_MEM_ZERO,
10118 sizeof(struct mlx5dv_dr_action_dest_attr),
10120 if (!dest_attr[idx]) {
10121 rte_flow_error_set(error, ENOMEM,
10122 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10124 "cannot allocate resource memory");
10127 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST;
10128 sample_act = &resource->sample_act[idx];
10129 action_flags = sample_act->action_flags;
10130 switch (action_flags) {
10131 case MLX5_FLOW_ACTION_QUEUE:
10132 dest_attr[idx]->dest = sample_act->dr_queue_action;
10134 case (MLX5_FLOW_ACTION_PORT_ID | MLX5_FLOW_ACTION_ENCAP):
10135 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST_REFORMAT;
10136 dest_attr[idx]->dest_reformat = &dest_reformat[idx];
10137 dest_attr[idx]->dest_reformat->reformat =
10138 sample_act->dr_encap_action;
10139 dest_attr[idx]->dest_reformat->dest =
10140 sample_act->dr_port_id_action;
10142 case MLX5_FLOW_ACTION_PORT_ID:
10143 dest_attr[idx]->dest = sample_act->dr_port_id_action;
10145 case MLX5_FLOW_ACTION_JUMP:
10146 dest_attr[idx]->dest = sample_act->dr_jump_action;
10149 rte_flow_error_set(error, EINVAL,
10150 RTE_FLOW_ERROR_TYPE_ACTION,
10152 "unsupported actions type");
10156 /* create a dest array actioin */
10157 ret = mlx5_os_flow_dr_create_flow_action_dest_array
10159 cache_resource->num_of_dest,
10161 &cache_resource->action);
10163 rte_flow_error_set(error, ENOMEM,
10164 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10166 "cannot create destination array action");
10169 cache_resource->idx = res_idx;
10170 cache_resource->dev = dev;
10171 for (idx = 0; idx < resource->num_of_dest; idx++)
10172 mlx5_free(dest_attr[idx]);
10173 return &cache_resource->entry;
10175 for (idx = 0; idx < resource->num_of_dest; idx++) {
10176 flow_dv_sample_sub_actions_release(dev,
10177 &cache_resource->sample_idx[idx]);
10178 if (dest_attr[idx])
10179 mlx5_free(dest_attr[idx]);
10182 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DEST_ARRAY], res_idx);
10187 * Find existing destination array resource or create and register a new one.
10189 * @param[in, out] dev
10190 * Pointer to rte_eth_dev structure.
10191 * @param[in] resource
10192 * Pointer to destination array resource.
10193 * @parm[in, out] dev_flow
10194 * Pointer to the dev_flow.
10195 * @param[out] error
10196 * pointer to error structure.
10199 * 0 on success otherwise -errno and errno is set.
10202 flow_dv_dest_array_resource_register(struct rte_eth_dev *dev,
10203 struct mlx5_flow_dv_dest_array_resource *resource,
10204 struct mlx5_flow *dev_flow,
10205 struct rte_flow_error *error)
10207 struct mlx5_flow_dv_dest_array_resource *cache_resource;
10208 struct mlx5_priv *priv = dev->data->dev_private;
10209 struct mlx5_cache_entry *entry;
10210 struct mlx5_flow_cb_ctx ctx = {
10216 entry = mlx5_cache_register(&priv->sh->dest_array_list, &ctx);
10219 cache_resource = container_of(entry, typeof(*cache_resource), entry);
10220 dev_flow->handle->dvh.rix_dest_array = cache_resource->idx;
10221 dev_flow->dv.dest_array_res = cache_resource;
10226 * Convert Sample action to DV specification.
10229 * Pointer to rte_eth_dev structure.
10230 * @param[in] action
10231 * Pointer to sample action structure.
10232 * @param[in, out] dev_flow
10233 * Pointer to the mlx5_flow.
10235 * Pointer to the flow attributes.
10236 * @param[in, out] num_of_dest
10237 * Pointer to the num of destination.
10238 * @param[in, out] sample_actions
10239 * Pointer to sample actions list.
10240 * @param[in, out] res
10241 * Pointer to sample resource.
10242 * @param[out] error
10243 * Pointer to the error structure.
10246 * 0 on success, a negative errno value otherwise and rte_errno is set.
10249 flow_dv_translate_action_sample(struct rte_eth_dev *dev,
10250 const struct rte_flow_action_sample *action,
10251 struct mlx5_flow *dev_flow,
10252 const struct rte_flow_attr *attr,
10253 uint32_t *num_of_dest,
10254 void **sample_actions,
10255 struct mlx5_flow_dv_sample_resource *res,
10256 struct rte_flow_error *error)
10258 struct mlx5_priv *priv = dev->data->dev_private;
10259 const struct rte_flow_action *sub_actions;
10260 struct mlx5_flow_sub_actions_list *sample_act;
10261 struct mlx5_flow_sub_actions_idx *sample_idx;
10262 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
10263 struct rte_flow *flow = dev_flow->flow;
10264 struct mlx5_flow_rss_desc *rss_desc;
10265 uint64_t action_flags = 0;
10268 rss_desc = &wks->rss_desc;
10269 sample_act = &res->sample_act;
10270 sample_idx = &res->sample_idx;
10271 res->ratio = action->ratio;
10272 sub_actions = action->actions;
10273 for (; sub_actions->type != RTE_FLOW_ACTION_TYPE_END; sub_actions++) {
10274 int type = sub_actions->type;
10275 uint32_t pre_rix = 0;
10278 case RTE_FLOW_ACTION_TYPE_QUEUE:
10280 const struct rte_flow_action_queue *queue;
10281 struct mlx5_hrxq *hrxq;
10284 queue = sub_actions->conf;
10285 rss_desc->queue_num = 1;
10286 rss_desc->queue[0] = queue->index;
10287 hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
10288 rss_desc, &hrxq_idx);
10290 return rte_flow_error_set
10292 RTE_FLOW_ERROR_TYPE_ACTION,
10294 "cannot create fate queue");
10295 sample_act->dr_queue_action = hrxq->action;
10296 sample_idx->rix_hrxq = hrxq_idx;
10297 sample_actions[sample_act->actions_num++] =
10300 action_flags |= MLX5_FLOW_ACTION_QUEUE;
10301 if (action_flags & MLX5_FLOW_ACTION_MARK)
10302 dev_flow->handle->rix_hrxq = hrxq_idx;
10303 dev_flow->handle->fate_action =
10304 MLX5_FLOW_FATE_QUEUE;
10307 case RTE_FLOW_ACTION_TYPE_RSS:
10309 struct mlx5_hrxq *hrxq;
10311 const struct rte_flow_action_rss *rss;
10312 const uint8_t *rss_key;
10314 rss = sub_actions->conf;
10315 memcpy(rss_desc->queue, rss->queue,
10316 rss->queue_num * sizeof(uint16_t));
10317 rss_desc->queue_num = rss->queue_num;
10318 /* NULL RSS key indicates default RSS key. */
10319 rss_key = !rss->key ? rss_hash_default_key : rss->key;
10320 memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
10322 * rss->level and rss.types should be set in advance
10323 * when expanding items for RSS.
10325 flow_dv_hashfields_set(dev_flow, rss_desc);
10326 hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
10327 rss_desc, &hrxq_idx);
10329 return rte_flow_error_set
10331 RTE_FLOW_ERROR_TYPE_ACTION,
10333 "cannot create fate queue");
10334 sample_act->dr_queue_action = hrxq->action;
10335 sample_idx->rix_hrxq = hrxq_idx;
10336 sample_actions[sample_act->actions_num++] =
10339 action_flags |= MLX5_FLOW_ACTION_RSS;
10340 if (action_flags & MLX5_FLOW_ACTION_MARK)
10341 dev_flow->handle->rix_hrxq = hrxq_idx;
10342 dev_flow->handle->fate_action =
10343 MLX5_FLOW_FATE_QUEUE;
10346 case RTE_FLOW_ACTION_TYPE_MARK:
10348 uint32_t tag_be = mlx5_flow_mark_set
10349 (((const struct rte_flow_action_mark *)
10350 (sub_actions->conf))->id);
10352 dev_flow->handle->mark = 1;
10353 pre_rix = dev_flow->handle->dvh.rix_tag;
10354 /* Save the mark resource before sample */
10355 pre_r = dev_flow->dv.tag_resource;
10356 if (flow_dv_tag_resource_register(dev, tag_be,
10359 MLX5_ASSERT(dev_flow->dv.tag_resource);
10360 sample_act->dr_tag_action =
10361 dev_flow->dv.tag_resource->action;
10362 sample_idx->rix_tag =
10363 dev_flow->handle->dvh.rix_tag;
10364 sample_actions[sample_act->actions_num++] =
10365 sample_act->dr_tag_action;
10366 /* Recover the mark resource after sample */
10367 dev_flow->dv.tag_resource = pre_r;
10368 dev_flow->handle->dvh.rix_tag = pre_rix;
10369 action_flags |= MLX5_FLOW_ACTION_MARK;
10372 case RTE_FLOW_ACTION_TYPE_COUNT:
10374 if (!flow->counter) {
10376 flow_dv_translate_create_counter(dev,
10377 dev_flow, sub_actions->conf,
10379 if (!flow->counter)
10380 return rte_flow_error_set
10382 RTE_FLOW_ERROR_TYPE_ACTION,
10384 "cannot create counter"
10387 sample_act->dr_cnt_action =
10388 (flow_dv_counter_get_by_idx(dev,
10389 flow->counter, NULL))->action;
10390 sample_actions[sample_act->actions_num++] =
10391 sample_act->dr_cnt_action;
10392 action_flags |= MLX5_FLOW_ACTION_COUNT;
10395 case RTE_FLOW_ACTION_TYPE_PORT_ID:
10397 struct mlx5_flow_dv_port_id_action_resource
10399 uint32_t port_id = 0;
10401 memset(&port_id_resource, 0, sizeof(port_id_resource));
10402 /* Save the port id resource before sample */
10403 pre_rix = dev_flow->handle->rix_port_id_action;
10404 pre_r = dev_flow->dv.port_id_action;
10405 if (flow_dv_translate_action_port_id(dev, sub_actions,
10408 port_id_resource.port_id = port_id;
10409 if (flow_dv_port_id_action_resource_register
10410 (dev, &port_id_resource, dev_flow, error))
10412 sample_act->dr_port_id_action =
10413 dev_flow->dv.port_id_action->action;
10414 sample_idx->rix_port_id_action =
10415 dev_flow->handle->rix_port_id_action;
10416 sample_actions[sample_act->actions_num++] =
10417 sample_act->dr_port_id_action;
10418 /* Recover the port id resource after sample */
10419 dev_flow->dv.port_id_action = pre_r;
10420 dev_flow->handle->rix_port_id_action = pre_rix;
10422 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
10425 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
10426 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
10427 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
10428 /* Save the encap resource before sample */
10429 pre_rix = dev_flow->handle->dvh.rix_encap_decap;
10430 pre_r = dev_flow->dv.encap_decap;
10431 if (flow_dv_create_action_l2_encap(dev, sub_actions,
10436 sample_act->dr_encap_action =
10437 dev_flow->dv.encap_decap->action;
10438 sample_idx->rix_encap_decap =
10439 dev_flow->handle->dvh.rix_encap_decap;
10440 sample_actions[sample_act->actions_num++] =
10441 sample_act->dr_encap_action;
10442 /* Recover the encap resource after sample */
10443 dev_flow->dv.encap_decap = pre_r;
10444 dev_flow->handle->dvh.rix_encap_decap = pre_rix;
10445 action_flags |= MLX5_FLOW_ACTION_ENCAP;
10448 return rte_flow_error_set(error, EINVAL,
10449 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10451 "Not support for sampler action");
10454 sample_act->action_flags = action_flags;
10455 res->ft_id = dev_flow->dv.group;
10456 if (attr->transfer) {
10458 uint32_t action_in[MLX5_ST_SZ_DW(set_action_in)];
10459 uint64_t set_action;
10460 } action_ctx = { .set_action = 0 };
10462 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
10463 MLX5_SET(set_action_in, action_ctx.action_in, action_type,
10464 MLX5_MODIFICATION_TYPE_SET);
10465 MLX5_SET(set_action_in, action_ctx.action_in, field,
10466 MLX5_MODI_META_REG_C_0);
10467 MLX5_SET(set_action_in, action_ctx.action_in, data,
10468 priv->vport_meta_tag);
10469 res->set_action = action_ctx.set_action;
10470 } else if (attr->ingress) {
10471 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
10473 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_TX;
10479 * Convert Sample action to DV specification.
10482 * Pointer to rte_eth_dev structure.
10483 * @param[in, out] dev_flow
10484 * Pointer to the mlx5_flow.
10485 * @param[in] num_of_dest
10486 * The num of destination.
10487 * @param[in, out] res
10488 * Pointer to sample resource.
10489 * @param[in, out] mdest_res
10490 * Pointer to destination array resource.
10491 * @param[in] sample_actions
10492 * Pointer to sample path actions list.
10493 * @param[in] action_flags
10494 * Holds the actions detected until now.
10495 * @param[out] error
10496 * Pointer to the error structure.
10499 * 0 on success, a negative errno value otherwise and rte_errno is set.
10502 flow_dv_create_action_sample(struct rte_eth_dev *dev,
10503 struct mlx5_flow *dev_flow,
10504 uint32_t num_of_dest,
10505 struct mlx5_flow_dv_sample_resource *res,
10506 struct mlx5_flow_dv_dest_array_resource *mdest_res,
10507 void **sample_actions,
10508 uint64_t action_flags,
10509 struct rte_flow_error *error)
10511 /* update normal path action resource into last index of array */
10512 uint32_t dest_index = MLX5_MAX_DEST_NUM - 1;
10513 struct mlx5_flow_sub_actions_list *sample_act =
10514 &mdest_res->sample_act[dest_index];
10515 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
10516 struct mlx5_flow_rss_desc *rss_desc;
10517 uint32_t normal_idx = 0;
10518 struct mlx5_hrxq *hrxq;
10522 rss_desc = &wks->rss_desc;
10523 if (num_of_dest > 1) {
10524 if (sample_act->action_flags & MLX5_FLOW_ACTION_QUEUE) {
10525 /* Handle QP action for mirroring */
10526 hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
10527 rss_desc, &hrxq_idx);
10529 return rte_flow_error_set
10531 RTE_FLOW_ERROR_TYPE_ACTION,
10533 "cannot create rx queue");
10535 mdest_res->sample_idx[dest_index].rix_hrxq = hrxq_idx;
10536 sample_act->dr_queue_action = hrxq->action;
10537 if (action_flags & MLX5_FLOW_ACTION_MARK)
10538 dev_flow->handle->rix_hrxq = hrxq_idx;
10539 dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
10541 if (sample_act->action_flags & MLX5_FLOW_ACTION_ENCAP) {
10543 mdest_res->sample_idx[dest_index].rix_encap_decap =
10544 dev_flow->handle->dvh.rix_encap_decap;
10545 sample_act->dr_encap_action =
10546 dev_flow->dv.encap_decap->action;
10547 dev_flow->handle->dvh.rix_encap_decap = 0;
10549 if (sample_act->action_flags & MLX5_FLOW_ACTION_PORT_ID) {
10551 mdest_res->sample_idx[dest_index].rix_port_id_action =
10552 dev_flow->handle->rix_port_id_action;
10553 sample_act->dr_port_id_action =
10554 dev_flow->dv.port_id_action->action;
10555 dev_flow->handle->rix_port_id_action = 0;
10557 if (sample_act->action_flags & MLX5_FLOW_ACTION_JUMP) {
10559 mdest_res->sample_idx[dest_index].rix_jump =
10560 dev_flow->handle->rix_jump;
10561 sample_act->dr_jump_action =
10562 dev_flow->dv.jump->action;
10563 dev_flow->handle->rix_jump = 0;
10565 sample_act->actions_num = normal_idx;
10566 /* update sample action resource into first index of array */
10567 mdest_res->ft_type = res->ft_type;
10568 memcpy(&mdest_res->sample_idx[0], &res->sample_idx,
10569 sizeof(struct mlx5_flow_sub_actions_idx));
10570 memcpy(&mdest_res->sample_act[0], &res->sample_act,
10571 sizeof(struct mlx5_flow_sub_actions_list));
10572 mdest_res->num_of_dest = num_of_dest;
10573 if (flow_dv_dest_array_resource_register(dev, mdest_res,
10575 return rte_flow_error_set(error, EINVAL,
10576 RTE_FLOW_ERROR_TYPE_ACTION,
10577 NULL, "can't create sample "
10580 res->sub_actions = sample_actions;
10581 if (flow_dv_sample_resource_register(dev, res, dev_flow, error))
10582 return rte_flow_error_set(error, EINVAL,
10583 RTE_FLOW_ERROR_TYPE_ACTION,
10585 "can't create sample action");
10591 * Remove an ASO age action from age actions list.
10594 * Pointer to the Ethernet device structure.
10596 * Pointer to the aso age action handler.
10599 flow_dv_aso_age_remove_from_age(struct rte_eth_dev *dev,
10600 struct mlx5_aso_age_action *age)
10602 struct mlx5_age_info *age_info;
10603 struct mlx5_age_param *age_param = &age->age_params;
10604 struct mlx5_priv *priv = dev->data->dev_private;
10605 uint16_t expected = AGE_CANDIDATE;
10607 age_info = GET_PORT_AGE_INFO(priv);
10608 if (!__atomic_compare_exchange_n(&age_param->state, &expected,
10609 AGE_FREE, false, __ATOMIC_RELAXED,
10610 __ATOMIC_RELAXED)) {
10612 * We need the lock even it is age timeout,
10613 * since age action may still in process.
10615 rte_spinlock_lock(&age_info->aged_sl);
10616 LIST_REMOVE(age, next);
10617 rte_spinlock_unlock(&age_info->aged_sl);
10618 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
10623 * Release an ASO age action.
10626 * Pointer to the Ethernet device structure.
10627 * @param[in] age_idx
10628 * Index of ASO age action to release.
10630 * True if the release operation is during flow destroy operation.
10631 * False if the release operation is during action destroy operation.
10634 * 0 when age action was removed, otherwise the number of references.
10637 flow_dv_aso_age_release(struct rte_eth_dev *dev, uint32_t age_idx)
10639 struct mlx5_priv *priv = dev->data->dev_private;
10640 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
10641 struct mlx5_aso_age_action *age = flow_aso_age_get_by_idx(dev, age_idx);
10642 uint32_t ret = __atomic_sub_fetch(&age->refcnt, 1, __ATOMIC_RELAXED);
10645 flow_dv_aso_age_remove_from_age(dev, age);
10646 rte_spinlock_lock(&mng->free_sl);
10647 LIST_INSERT_HEAD(&mng->free, age, next);
10648 rte_spinlock_unlock(&mng->free_sl);
10654 * Resize the ASO age pools array by MLX5_CNT_CONTAINER_RESIZE pools.
10657 * Pointer to the Ethernet device structure.
10660 * 0 on success, otherwise negative errno value and rte_errno is set.
10663 flow_dv_aso_age_pools_resize(struct rte_eth_dev *dev)
10665 struct mlx5_priv *priv = dev->data->dev_private;
10666 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
10667 void *old_pools = mng->pools;
10668 uint32_t resize = mng->n + MLX5_CNT_CONTAINER_RESIZE;
10669 uint32_t mem_size = sizeof(struct mlx5_aso_age_pool *) * resize;
10670 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
10673 rte_errno = ENOMEM;
10677 memcpy(pools, old_pools,
10678 mng->n * sizeof(struct mlx5_flow_counter_pool *));
10679 mlx5_free(old_pools);
10681 /* First ASO flow hit allocation - starting ASO data-path. */
10682 int ret = mlx5_aso_queue_start(priv->sh);
10690 mng->pools = pools;
10695 * Create and initialize a new ASO aging pool.
10698 * Pointer to the Ethernet device structure.
10699 * @param[out] age_free
10700 * Where to put the pointer of a new age action.
10703 * The age actions pool pointer and @p age_free is set on success,
10704 * NULL otherwise and rte_errno is set.
10706 static struct mlx5_aso_age_pool *
10707 flow_dv_age_pool_create(struct rte_eth_dev *dev,
10708 struct mlx5_aso_age_action **age_free)
10710 struct mlx5_priv *priv = dev->data->dev_private;
10711 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
10712 struct mlx5_aso_age_pool *pool = NULL;
10713 struct mlx5_devx_obj *obj = NULL;
10716 obj = mlx5_devx_cmd_create_flow_hit_aso_obj(priv->sh->ctx,
10719 rte_errno = ENODATA;
10720 DRV_LOG(ERR, "Failed to create flow_hit_aso_obj using DevX.");
10723 pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
10725 claim_zero(mlx5_devx_cmd_destroy(obj));
10726 rte_errno = ENOMEM;
10729 pool->flow_hit_aso_obj = obj;
10730 pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
10731 rte_spinlock_lock(&mng->resize_sl);
10732 pool->index = mng->next;
10733 /* Resize pools array if there is no room for the new pool in it. */
10734 if (pool->index == mng->n && flow_dv_aso_age_pools_resize(dev)) {
10735 claim_zero(mlx5_devx_cmd_destroy(obj));
10737 rte_spinlock_unlock(&mng->resize_sl);
10740 mng->pools[pool->index] = pool;
10742 rte_spinlock_unlock(&mng->resize_sl);
10743 /* Assign the first action in the new pool, the rest go to free list. */
10744 *age_free = &pool->actions[0];
10745 for (i = 1; i < MLX5_ASO_AGE_ACTIONS_PER_POOL; i++) {
10746 pool->actions[i].offset = i;
10747 LIST_INSERT_HEAD(&mng->free, &pool->actions[i], next);
10753 * Allocate a ASO aging bit.
10756 * Pointer to the Ethernet device structure.
10757 * @param[out] error
10758 * Pointer to the error structure.
10761 * Index to ASO age action on success, 0 otherwise and rte_errno is set.
10764 flow_dv_aso_age_alloc(struct rte_eth_dev *dev, struct rte_flow_error *error)
10766 struct mlx5_priv *priv = dev->data->dev_private;
10767 const struct mlx5_aso_age_pool *pool;
10768 struct mlx5_aso_age_action *age_free = NULL;
10769 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
10772 /* Try to get the next free age action bit. */
10773 rte_spinlock_lock(&mng->free_sl);
10774 age_free = LIST_FIRST(&mng->free);
10776 LIST_REMOVE(age_free, next);
10777 } else if (!flow_dv_age_pool_create(dev, &age_free)) {
10778 rte_spinlock_unlock(&mng->free_sl);
10779 rte_flow_error_set(error, rte_errno, RTE_FLOW_ERROR_TYPE_ACTION,
10780 NULL, "failed to create ASO age pool");
10781 return 0; /* 0 is an error. */
10783 rte_spinlock_unlock(&mng->free_sl);
10784 pool = container_of
10785 ((const struct mlx5_aso_age_action (*)[MLX5_ASO_AGE_ACTIONS_PER_POOL])
10786 (age_free - age_free->offset), const struct mlx5_aso_age_pool,
10788 if (!age_free->dr_action) {
10789 int reg_c = mlx5_flow_get_reg_id(dev, MLX5_ASO_FLOW_HIT, 0,
10793 rte_flow_error_set(error, rte_errno,
10794 RTE_FLOW_ERROR_TYPE_ACTION,
10795 NULL, "failed to get reg_c "
10796 "for ASO flow hit");
10797 return 0; /* 0 is an error. */
10799 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
10800 age_free->dr_action = mlx5_glue->dv_create_flow_action_aso
10801 (priv->sh->rx_domain,
10802 pool->flow_hit_aso_obj->obj, age_free->offset,
10803 MLX5DV_DR_ACTION_FLAGS_ASO_FIRST_HIT_SET,
10804 (reg_c - REG_C_0));
10805 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
10806 if (!age_free->dr_action) {
10808 rte_spinlock_lock(&mng->free_sl);
10809 LIST_INSERT_HEAD(&mng->free, age_free, next);
10810 rte_spinlock_unlock(&mng->free_sl);
10811 rte_flow_error_set(error, rte_errno,
10812 RTE_FLOW_ERROR_TYPE_ACTION,
10813 NULL, "failed to create ASO "
10814 "flow hit action");
10815 return 0; /* 0 is an error. */
10818 __atomic_store_n(&age_free->refcnt, 1, __ATOMIC_RELAXED);
10819 return pool->index | ((age_free->offset + 1) << 16);
10823 * Create a age action using ASO mechanism.
10826 * Pointer to rte_eth_dev structure.
10828 * Pointer to the aging action configuration.
10829 * @param[out] error
10830 * Pointer to the error structure.
10833 * Index to flow counter on success, 0 otherwise.
10836 flow_dv_translate_create_aso_age(struct rte_eth_dev *dev,
10837 const struct rte_flow_action_age *age,
10838 struct rte_flow_error *error)
10840 uint32_t age_idx = 0;
10841 struct mlx5_aso_age_action *aso_age;
10843 age_idx = flow_dv_aso_age_alloc(dev, error);
10846 aso_age = flow_aso_age_get_by_idx(dev, age_idx);
10847 aso_age->age_params.context = age->context;
10848 aso_age->age_params.timeout = age->timeout;
10849 aso_age->age_params.port_id = dev->data->port_id;
10850 __atomic_store_n(&aso_age->age_params.sec_since_last_hit, 0,
10852 __atomic_store_n(&aso_age->age_params.state, AGE_CANDIDATE,
10858 * Fill the flow with DV spec, lock free
10859 * (mutex should be acquired by caller).
10862 * Pointer to rte_eth_dev structure.
10863 * @param[in, out] dev_flow
10864 * Pointer to the sub flow.
10866 * Pointer to the flow attributes.
10868 * Pointer to the list of items.
10869 * @param[in] actions
10870 * Pointer to the list of actions.
10871 * @param[out] error
10872 * Pointer to the error structure.
10875 * 0 on success, a negative errno value otherwise and rte_errno is set.
10878 flow_dv_translate(struct rte_eth_dev *dev,
10879 struct mlx5_flow *dev_flow,
10880 const struct rte_flow_attr *attr,
10881 const struct rte_flow_item items[],
10882 const struct rte_flow_action actions[],
10883 struct rte_flow_error *error)
10885 struct mlx5_priv *priv = dev->data->dev_private;
10886 struct mlx5_dev_config *dev_conf = &priv->config;
10887 struct rte_flow *flow = dev_flow->flow;
10888 struct mlx5_flow_handle *handle = dev_flow->handle;
10889 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
10890 struct mlx5_flow_rss_desc *rss_desc;
10891 uint64_t item_flags = 0;
10892 uint64_t last_item = 0;
10893 uint64_t action_flags = 0;
10894 struct mlx5_flow_dv_matcher matcher = {
10896 .size = sizeof(matcher.mask.buf) -
10897 MLX5_ST_SZ_BYTES(fte_match_set_misc4),
10901 bool actions_end = false;
10903 struct mlx5_flow_dv_modify_hdr_resource res;
10904 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
10905 sizeof(struct mlx5_modification_cmd) *
10906 (MLX5_MAX_MODIFY_NUM + 1)];
10908 struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
10909 const struct rte_flow_action_count *count = NULL;
10910 const struct rte_flow_action_age *age = NULL;
10911 union flow_dv_attr flow_attr = { .attr = 0 };
10913 union mlx5_flow_tbl_key tbl_key;
10914 uint32_t modify_action_position = UINT32_MAX;
10915 void *match_mask = matcher.mask.buf;
10916 void *match_value = dev_flow->dv.value.buf;
10917 uint8_t next_protocol = 0xff;
10918 struct rte_vlan_hdr vlan = { 0 };
10919 struct mlx5_flow_dv_dest_array_resource mdest_res;
10920 struct mlx5_flow_dv_sample_resource sample_res;
10921 void *sample_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
10922 const struct rte_flow_action_sample *sample = NULL;
10923 struct mlx5_flow_sub_actions_list *sample_act;
10924 uint32_t sample_act_pos = UINT32_MAX;
10925 uint32_t num_of_dest = 0;
10926 int tmp_actions_n = 0;
10929 const struct mlx5_flow_tunnel *tunnel;
10930 struct flow_grp_info grp_info = {
10931 .external = !!dev_flow->external,
10932 .transfer = !!attr->transfer,
10933 .fdb_def_rule = !!priv->fdb_def_rule,
10934 .skip_scale = dev_flow->skip_scale &
10935 (1 << MLX5_SCALE_FLOW_GROUP_BIT),
10939 return rte_flow_error_set(error, ENOMEM,
10940 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10942 "failed to push flow workspace");
10943 rss_desc = &wks->rss_desc;
10944 memset(&mdest_res, 0, sizeof(struct mlx5_flow_dv_dest_array_resource));
10945 memset(&sample_res, 0, sizeof(struct mlx5_flow_dv_sample_resource));
10946 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
10947 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
10948 /* update normal path action resource into last index of array */
10949 sample_act = &mdest_res.sample_act[MLX5_MAX_DEST_NUM - 1];
10950 tunnel = is_flow_tunnel_match_rule(dev, attr, items, actions) ?
10951 flow_items_to_tunnel(items) :
10952 is_flow_tunnel_steer_rule(dev, attr, items, actions) ?
10953 flow_actions_to_tunnel(actions) :
10954 dev_flow->tunnel ? dev_flow->tunnel : NULL;
10955 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
10956 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
10957 grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
10958 (dev, tunnel, attr, items, actions);
10959 ret = mlx5_flow_group_to_table(dev, tunnel, attr->group, &table,
10963 dev_flow->dv.group = table;
10964 if (attr->transfer)
10965 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
10966 /* number of actions must be set to 0 in case of dirty stack. */
10967 mhdr_res->actions_num = 0;
10968 if (is_flow_tunnel_match_rule(dev, attr, items, actions)) {
10970 * do not add decap action if match rule drops packet
10971 * HW rejects rules with decap & drop
10973 * if tunnel match rule was inserted before matching tunnel set
10974 * rule flow table used in the match rule must be registered.
10975 * current implementation handles that in the
10976 * flow_dv_match_register() at the function end.
10978 bool add_decap = true;
10979 const struct rte_flow_action *ptr = actions;
10981 for (; ptr->type != RTE_FLOW_ACTION_TYPE_END; ptr++) {
10982 if (ptr->type == RTE_FLOW_ACTION_TYPE_DROP) {
10988 if (flow_dv_create_action_l2_decap(dev, dev_flow,
10992 dev_flow->dv.actions[actions_n++] =
10993 dev_flow->dv.encap_decap->action;
10994 action_flags |= MLX5_FLOW_ACTION_DECAP;
10997 for (; !actions_end ; actions++) {
10998 const struct rte_flow_action_queue *queue;
10999 const struct rte_flow_action_rss *rss;
11000 const struct rte_flow_action *action = actions;
11001 const uint8_t *rss_key;
11002 struct mlx5_flow_tbl_resource *tbl;
11003 struct mlx5_aso_age_action *age_act;
11004 uint32_t port_id = 0;
11005 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
11006 int action_type = actions->type;
11007 const struct rte_flow_action *found_action = NULL;
11008 uint32_t jump_group = 0;
11010 if (!mlx5_flow_os_action_supported(action_type))
11011 return rte_flow_error_set(error, ENOTSUP,
11012 RTE_FLOW_ERROR_TYPE_ACTION,
11014 "action not supported");
11015 switch (action_type) {
11016 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
11017 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
11019 case RTE_FLOW_ACTION_TYPE_VOID:
11021 case RTE_FLOW_ACTION_TYPE_PORT_ID:
11022 if (flow_dv_translate_action_port_id(dev, action,
11025 port_id_resource.port_id = port_id;
11026 MLX5_ASSERT(!handle->rix_port_id_action);
11027 if (flow_dv_port_id_action_resource_register
11028 (dev, &port_id_resource, dev_flow, error))
11030 dev_flow->dv.actions[actions_n++] =
11031 dev_flow->dv.port_id_action->action;
11032 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
11033 dev_flow->handle->fate_action = MLX5_FLOW_FATE_PORT_ID;
11034 sample_act->action_flags |= MLX5_FLOW_ACTION_PORT_ID;
11037 case RTE_FLOW_ACTION_TYPE_FLAG:
11038 action_flags |= MLX5_FLOW_ACTION_FLAG;
11039 dev_flow->handle->mark = 1;
11040 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
11041 struct rte_flow_action_mark mark = {
11042 .id = MLX5_FLOW_MARK_DEFAULT,
11045 if (flow_dv_convert_action_mark(dev, &mark,
11049 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
11052 tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
11054 * Only one FLAG or MARK is supported per device flow
11055 * right now. So the pointer to the tag resource must be
11056 * zero before the register process.
11058 MLX5_ASSERT(!handle->dvh.rix_tag);
11059 if (flow_dv_tag_resource_register(dev, tag_be,
11062 MLX5_ASSERT(dev_flow->dv.tag_resource);
11063 dev_flow->dv.actions[actions_n++] =
11064 dev_flow->dv.tag_resource->action;
11066 case RTE_FLOW_ACTION_TYPE_MARK:
11067 action_flags |= MLX5_FLOW_ACTION_MARK;
11068 dev_flow->handle->mark = 1;
11069 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
11070 const struct rte_flow_action_mark *mark =
11071 (const struct rte_flow_action_mark *)
11074 if (flow_dv_convert_action_mark(dev, mark,
11078 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
11082 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
11083 /* Legacy (non-extensive) MARK action. */
11084 tag_be = mlx5_flow_mark_set
11085 (((const struct rte_flow_action_mark *)
11086 (actions->conf))->id);
11087 MLX5_ASSERT(!handle->dvh.rix_tag);
11088 if (flow_dv_tag_resource_register(dev, tag_be,
11091 MLX5_ASSERT(dev_flow->dv.tag_resource);
11092 dev_flow->dv.actions[actions_n++] =
11093 dev_flow->dv.tag_resource->action;
11095 case RTE_FLOW_ACTION_TYPE_SET_META:
11096 if (flow_dv_convert_action_set_meta
11097 (dev, mhdr_res, attr,
11098 (const struct rte_flow_action_set_meta *)
11099 actions->conf, error))
11101 action_flags |= MLX5_FLOW_ACTION_SET_META;
11103 case RTE_FLOW_ACTION_TYPE_SET_TAG:
11104 if (flow_dv_convert_action_set_tag
11106 (const struct rte_flow_action_set_tag *)
11107 actions->conf, error))
11109 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
11111 case RTE_FLOW_ACTION_TYPE_DROP:
11112 action_flags |= MLX5_FLOW_ACTION_DROP;
11113 dev_flow->handle->fate_action = MLX5_FLOW_FATE_DROP;
11115 case RTE_FLOW_ACTION_TYPE_QUEUE:
11116 queue = actions->conf;
11117 rss_desc->queue_num = 1;
11118 rss_desc->queue[0] = queue->index;
11119 action_flags |= MLX5_FLOW_ACTION_QUEUE;
11120 dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
11121 sample_act->action_flags |= MLX5_FLOW_ACTION_QUEUE;
11124 case RTE_FLOW_ACTION_TYPE_RSS:
11125 rss = actions->conf;
11126 memcpy(rss_desc->queue, rss->queue,
11127 rss->queue_num * sizeof(uint16_t));
11128 rss_desc->queue_num = rss->queue_num;
11129 /* NULL RSS key indicates default RSS key. */
11130 rss_key = !rss->key ? rss_hash_default_key : rss->key;
11131 memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
11133 * rss->level and rss.types should be set in advance
11134 * when expanding items for RSS.
11136 action_flags |= MLX5_FLOW_ACTION_RSS;
11137 dev_flow->handle->fate_action = rss_desc->shared_rss ?
11138 MLX5_FLOW_FATE_SHARED_RSS :
11139 MLX5_FLOW_FATE_QUEUE;
11141 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
11142 flow->age = (uint32_t)(uintptr_t)(action->conf);
11143 age_act = flow_aso_age_get_by_idx(dev, flow->age);
11144 __atomic_fetch_add(&age_act->refcnt, 1,
11146 dev_flow->dv.actions[actions_n++] = age_act->dr_action;
11147 action_flags |= MLX5_FLOW_ACTION_AGE;
11149 case RTE_FLOW_ACTION_TYPE_AGE:
11150 if (priv->sh->flow_hit_aso_en && attr->group) {
11152 * Create one shared age action, to be used
11153 * by all sub-flows.
11157 flow_dv_translate_create_aso_age
11158 (dev, action->conf,
11161 return rte_flow_error_set
11163 RTE_FLOW_ERROR_TYPE_ACTION,
11165 "can't create ASO age action");
11167 dev_flow->dv.actions[actions_n++] =
11168 (flow_aso_age_get_by_idx
11169 (dev, flow->age))->dr_action;
11170 action_flags |= MLX5_FLOW_ACTION_AGE;
11174 case RTE_FLOW_ACTION_TYPE_COUNT:
11175 if (!dev_conf->devx) {
11176 return rte_flow_error_set
11178 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11180 "count action not supported");
11182 /* Save information first, will apply later. */
11183 if (actions->type == RTE_FLOW_ACTION_TYPE_COUNT)
11184 count = action->conf;
11186 age = action->conf;
11187 action_flags |= MLX5_FLOW_ACTION_COUNT;
11189 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
11190 dev_flow->dv.actions[actions_n++] =
11191 priv->sh->pop_vlan_action;
11192 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
11194 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
11195 if (!(action_flags &
11196 MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
11197 flow_dev_get_vlan_info_from_items(items, &vlan);
11198 vlan.eth_proto = rte_be_to_cpu_16
11199 ((((const struct rte_flow_action_of_push_vlan *)
11200 actions->conf)->ethertype));
11201 found_action = mlx5_flow_find_action
11203 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
11205 mlx5_update_vlan_vid_pcp(found_action, &vlan);
11206 found_action = mlx5_flow_find_action
11208 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
11210 mlx5_update_vlan_vid_pcp(found_action, &vlan);
11211 if (flow_dv_create_action_push_vlan
11212 (dev, attr, &vlan, dev_flow, error))
11214 dev_flow->dv.actions[actions_n++] =
11215 dev_flow->dv.push_vlan_res->action;
11216 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
11218 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
11219 /* of_vlan_push action handled this action */
11220 MLX5_ASSERT(action_flags &
11221 MLX5_FLOW_ACTION_OF_PUSH_VLAN);
11223 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
11224 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
11226 flow_dev_get_vlan_info_from_items(items, &vlan);
11227 mlx5_update_vlan_vid_pcp(actions, &vlan);
11228 /* If no VLAN push - this is a modify header action */
11229 if (flow_dv_convert_action_modify_vlan_vid
11230 (mhdr_res, actions, error))
11232 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
11234 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
11235 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
11236 if (flow_dv_create_action_l2_encap(dev, actions,
11241 dev_flow->dv.actions[actions_n++] =
11242 dev_flow->dv.encap_decap->action;
11243 action_flags |= MLX5_FLOW_ACTION_ENCAP;
11244 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
11245 sample_act->action_flags |=
11246 MLX5_FLOW_ACTION_ENCAP;
11248 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
11249 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
11250 if (flow_dv_create_action_l2_decap(dev, dev_flow,
11254 dev_flow->dv.actions[actions_n++] =
11255 dev_flow->dv.encap_decap->action;
11256 action_flags |= MLX5_FLOW_ACTION_DECAP;
11258 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
11259 /* Handle encap with preceding decap. */
11260 if (action_flags & MLX5_FLOW_ACTION_DECAP) {
11261 if (flow_dv_create_action_raw_encap
11262 (dev, actions, dev_flow, attr, error))
11264 dev_flow->dv.actions[actions_n++] =
11265 dev_flow->dv.encap_decap->action;
11267 /* Handle encap without preceding decap. */
11268 if (flow_dv_create_action_l2_encap
11269 (dev, actions, dev_flow, attr->transfer,
11272 dev_flow->dv.actions[actions_n++] =
11273 dev_flow->dv.encap_decap->action;
11275 action_flags |= MLX5_FLOW_ACTION_ENCAP;
11276 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
11277 sample_act->action_flags |=
11278 MLX5_FLOW_ACTION_ENCAP;
11280 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
11281 while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
11283 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
11284 if (flow_dv_create_action_l2_decap
11285 (dev, dev_flow, attr->transfer, error))
11287 dev_flow->dv.actions[actions_n++] =
11288 dev_flow->dv.encap_decap->action;
11290 /* If decap is followed by encap, handle it at encap. */
11291 action_flags |= MLX5_FLOW_ACTION_DECAP;
11293 case RTE_FLOW_ACTION_TYPE_JUMP:
11294 jump_group = ((const struct rte_flow_action_jump *)
11295 action->conf)->group;
11296 grp_info.std_tbl_fix = 0;
11297 if (dev_flow->skip_scale &
11298 (1 << MLX5_SCALE_JUMP_FLOW_GROUP_BIT))
11299 grp_info.skip_scale = 1;
11301 grp_info.skip_scale = 0;
11302 ret = mlx5_flow_group_to_table(dev, tunnel,
11308 tbl = flow_dv_tbl_resource_get(dev, table, attr->egress,
11310 !!dev_flow->external,
11311 tunnel, jump_group, 0,
11314 return rte_flow_error_set
11316 RTE_FLOW_ERROR_TYPE_ACTION,
11318 "cannot create jump action.");
11319 if (flow_dv_jump_tbl_resource_register
11320 (dev, tbl, dev_flow, error)) {
11321 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
11322 return rte_flow_error_set
11324 RTE_FLOW_ERROR_TYPE_ACTION,
11326 "cannot create jump action.");
11328 dev_flow->dv.actions[actions_n++] =
11329 dev_flow->dv.jump->action;
11330 action_flags |= MLX5_FLOW_ACTION_JUMP;
11331 dev_flow->handle->fate_action = MLX5_FLOW_FATE_JUMP;
11332 sample_act->action_flags |= MLX5_FLOW_ACTION_JUMP;
11335 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
11336 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
11337 if (flow_dv_convert_action_modify_mac
11338 (mhdr_res, actions, error))
11340 action_flags |= actions->type ==
11341 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
11342 MLX5_FLOW_ACTION_SET_MAC_SRC :
11343 MLX5_FLOW_ACTION_SET_MAC_DST;
11345 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
11346 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
11347 if (flow_dv_convert_action_modify_ipv4
11348 (mhdr_res, actions, error))
11350 action_flags |= actions->type ==
11351 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
11352 MLX5_FLOW_ACTION_SET_IPV4_SRC :
11353 MLX5_FLOW_ACTION_SET_IPV4_DST;
11355 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
11356 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
11357 if (flow_dv_convert_action_modify_ipv6
11358 (mhdr_res, actions, error))
11360 action_flags |= actions->type ==
11361 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
11362 MLX5_FLOW_ACTION_SET_IPV6_SRC :
11363 MLX5_FLOW_ACTION_SET_IPV6_DST;
11365 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
11366 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
11367 if (flow_dv_convert_action_modify_tp
11368 (mhdr_res, actions, items,
11369 &flow_attr, dev_flow, !!(action_flags &
11370 MLX5_FLOW_ACTION_DECAP), error))
11372 action_flags |= actions->type ==
11373 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
11374 MLX5_FLOW_ACTION_SET_TP_SRC :
11375 MLX5_FLOW_ACTION_SET_TP_DST;
11377 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
11378 if (flow_dv_convert_action_modify_dec_ttl
11379 (mhdr_res, items, &flow_attr, dev_flow,
11381 MLX5_FLOW_ACTION_DECAP), error))
11383 action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
11385 case RTE_FLOW_ACTION_TYPE_SET_TTL:
11386 if (flow_dv_convert_action_modify_ttl
11387 (mhdr_res, actions, items, &flow_attr,
11388 dev_flow, !!(action_flags &
11389 MLX5_FLOW_ACTION_DECAP), error))
11391 action_flags |= MLX5_FLOW_ACTION_SET_TTL;
11393 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
11394 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
11395 if (flow_dv_convert_action_modify_tcp_seq
11396 (mhdr_res, actions, error))
11398 action_flags |= actions->type ==
11399 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
11400 MLX5_FLOW_ACTION_INC_TCP_SEQ :
11401 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
11404 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
11405 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
11406 if (flow_dv_convert_action_modify_tcp_ack
11407 (mhdr_res, actions, error))
11409 action_flags |= actions->type ==
11410 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
11411 MLX5_FLOW_ACTION_INC_TCP_ACK :
11412 MLX5_FLOW_ACTION_DEC_TCP_ACK;
11414 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
11415 if (flow_dv_convert_action_set_reg
11416 (mhdr_res, actions, error))
11418 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
11420 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
11421 if (flow_dv_convert_action_copy_mreg
11422 (dev, mhdr_res, actions, error))
11424 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
11426 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
11427 action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
11428 dev_flow->handle->fate_action =
11429 MLX5_FLOW_FATE_DEFAULT_MISS;
11431 case RTE_FLOW_ACTION_TYPE_METER:
11433 return rte_flow_error_set(error, rte_errno,
11434 RTE_FLOW_ERROR_TYPE_ACTION,
11435 NULL, "Failed to get meter in flow.");
11436 /* Set the meter action. */
11437 dev_flow->dv.actions[actions_n++] =
11438 wks->fm->mfts->meter_action;
11439 action_flags |= MLX5_FLOW_ACTION_METER;
11441 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
11442 if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
11445 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
11447 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
11448 if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
11451 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
11453 case RTE_FLOW_ACTION_TYPE_SAMPLE:
11454 sample_act_pos = actions_n;
11455 sample = (const struct rte_flow_action_sample *)
11458 action_flags |= MLX5_FLOW_ACTION_SAMPLE;
11459 /* put encap action into group if work with port id */
11460 if ((action_flags & MLX5_FLOW_ACTION_ENCAP) &&
11461 (action_flags & MLX5_FLOW_ACTION_PORT_ID))
11462 sample_act->action_flags |=
11463 MLX5_FLOW_ACTION_ENCAP;
11465 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
11466 if (flow_dv_convert_action_modify_field
11467 (dev, mhdr_res, actions, attr, error))
11469 action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
11471 case RTE_FLOW_ACTION_TYPE_END:
11472 actions_end = true;
11473 if (mhdr_res->actions_num) {
11474 /* create modify action if needed. */
11475 if (flow_dv_modify_hdr_resource_register
11476 (dev, mhdr_res, dev_flow, error))
11478 dev_flow->dv.actions[modify_action_position] =
11479 handle->dvh.modify_hdr->action;
11481 if (action_flags & MLX5_FLOW_ACTION_COUNT) {
11483 * Create one count action, to be used
11484 * by all sub-flows.
11486 if (!flow->counter) {
11488 flow_dv_translate_create_counter
11489 (dev, dev_flow, count,
11491 if (!flow->counter)
11492 return rte_flow_error_set
11494 RTE_FLOW_ERROR_TYPE_ACTION,
11495 NULL, "cannot create counter"
11498 dev_flow->dv.actions[actions_n] =
11499 (flow_dv_counter_get_by_idx(dev,
11500 flow->counter, NULL))->action;
11506 if (mhdr_res->actions_num &&
11507 modify_action_position == UINT32_MAX)
11508 modify_action_position = actions_n++;
11510 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
11511 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
11512 int item_type = items->type;
11514 if (!mlx5_flow_os_item_supported(item_type))
11515 return rte_flow_error_set(error, ENOTSUP,
11516 RTE_FLOW_ERROR_TYPE_ITEM,
11517 NULL, "item not supported");
11518 switch (item_type) {
11519 case RTE_FLOW_ITEM_TYPE_PORT_ID:
11520 flow_dv_translate_item_port_id
11521 (dev, match_mask, match_value, items, attr);
11522 last_item = MLX5_FLOW_ITEM_PORT_ID;
11524 case RTE_FLOW_ITEM_TYPE_ETH:
11525 flow_dv_translate_item_eth(match_mask, match_value,
11527 dev_flow->dv.group);
11528 matcher.priority = action_flags &
11529 MLX5_FLOW_ACTION_DEFAULT_MISS &&
11530 !dev_flow->external ?
11531 MLX5_PRIORITY_MAP_L3 :
11532 MLX5_PRIORITY_MAP_L2;
11533 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
11534 MLX5_FLOW_LAYER_OUTER_L2;
11536 case RTE_FLOW_ITEM_TYPE_VLAN:
11537 flow_dv_translate_item_vlan(dev_flow,
11538 match_mask, match_value,
11540 dev_flow->dv.group);
11541 matcher.priority = MLX5_PRIORITY_MAP_L2;
11542 last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
11543 MLX5_FLOW_LAYER_INNER_VLAN) :
11544 (MLX5_FLOW_LAYER_OUTER_L2 |
11545 MLX5_FLOW_LAYER_OUTER_VLAN);
11547 case RTE_FLOW_ITEM_TYPE_IPV4:
11548 mlx5_flow_tunnel_ip_check(items, next_protocol,
11549 &item_flags, &tunnel);
11550 flow_dv_translate_item_ipv4(match_mask, match_value,
11552 dev_flow->dv.group);
11553 matcher.priority = MLX5_PRIORITY_MAP_L3;
11554 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
11555 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
11556 if (items->mask != NULL &&
11557 ((const struct rte_flow_item_ipv4 *)
11558 items->mask)->hdr.next_proto_id) {
11560 ((const struct rte_flow_item_ipv4 *)
11561 (items->spec))->hdr.next_proto_id;
11563 ((const struct rte_flow_item_ipv4 *)
11564 (items->mask))->hdr.next_proto_id;
11566 /* Reset for inner layer. */
11567 next_protocol = 0xff;
11570 case RTE_FLOW_ITEM_TYPE_IPV6:
11571 mlx5_flow_tunnel_ip_check(items, next_protocol,
11572 &item_flags, &tunnel);
11573 flow_dv_translate_item_ipv6(match_mask, match_value,
11575 dev_flow->dv.group);
11576 matcher.priority = MLX5_PRIORITY_MAP_L3;
11577 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
11578 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
11579 if (items->mask != NULL &&
11580 ((const struct rte_flow_item_ipv6 *)
11581 items->mask)->hdr.proto) {
11583 ((const struct rte_flow_item_ipv6 *)
11584 items->spec)->hdr.proto;
11586 ((const struct rte_flow_item_ipv6 *)
11587 items->mask)->hdr.proto;
11589 /* Reset for inner layer. */
11590 next_protocol = 0xff;
11593 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
11594 flow_dv_translate_item_ipv6_frag_ext(match_mask,
11597 last_item = tunnel ?
11598 MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
11599 MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
11600 if (items->mask != NULL &&
11601 ((const struct rte_flow_item_ipv6_frag_ext *)
11602 items->mask)->hdr.next_header) {
11604 ((const struct rte_flow_item_ipv6_frag_ext *)
11605 items->spec)->hdr.next_header;
11607 ((const struct rte_flow_item_ipv6_frag_ext *)
11608 items->mask)->hdr.next_header;
11610 /* Reset for inner layer. */
11611 next_protocol = 0xff;
11614 case RTE_FLOW_ITEM_TYPE_TCP:
11615 flow_dv_translate_item_tcp(match_mask, match_value,
11617 matcher.priority = MLX5_PRIORITY_MAP_L4;
11618 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
11619 MLX5_FLOW_LAYER_OUTER_L4_TCP;
11621 case RTE_FLOW_ITEM_TYPE_UDP:
11622 flow_dv_translate_item_udp(match_mask, match_value,
11624 matcher.priority = MLX5_PRIORITY_MAP_L4;
11625 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
11626 MLX5_FLOW_LAYER_OUTER_L4_UDP;
11628 case RTE_FLOW_ITEM_TYPE_GRE:
11629 flow_dv_translate_item_gre(match_mask, match_value,
11631 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11632 last_item = MLX5_FLOW_LAYER_GRE;
11634 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
11635 flow_dv_translate_item_gre_key(match_mask,
11636 match_value, items);
11637 last_item = MLX5_FLOW_LAYER_GRE_KEY;
11639 case RTE_FLOW_ITEM_TYPE_NVGRE:
11640 flow_dv_translate_item_nvgre(match_mask, match_value,
11642 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11643 last_item = MLX5_FLOW_LAYER_GRE;
11645 case RTE_FLOW_ITEM_TYPE_VXLAN:
11646 flow_dv_translate_item_vxlan(match_mask, match_value,
11648 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11649 last_item = MLX5_FLOW_LAYER_VXLAN;
11651 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
11652 flow_dv_translate_item_vxlan_gpe(match_mask,
11653 match_value, items,
11655 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11656 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
11658 case RTE_FLOW_ITEM_TYPE_GENEVE:
11659 flow_dv_translate_item_geneve(match_mask, match_value,
11661 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11662 last_item = MLX5_FLOW_LAYER_GENEVE;
11664 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
11665 ret = flow_dv_translate_item_geneve_opt(dev, match_mask,
11669 return rte_flow_error_set(error, -ret,
11670 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
11671 "cannot create GENEVE TLV option");
11672 flow->geneve_tlv_option = 1;
11673 last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
11675 case RTE_FLOW_ITEM_TYPE_MPLS:
11676 flow_dv_translate_item_mpls(match_mask, match_value,
11677 items, last_item, tunnel);
11678 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11679 last_item = MLX5_FLOW_LAYER_MPLS;
11681 case RTE_FLOW_ITEM_TYPE_MARK:
11682 flow_dv_translate_item_mark(dev, match_mask,
11683 match_value, items);
11684 last_item = MLX5_FLOW_ITEM_MARK;
11686 case RTE_FLOW_ITEM_TYPE_META:
11687 flow_dv_translate_item_meta(dev, match_mask,
11688 match_value, attr, items);
11689 last_item = MLX5_FLOW_ITEM_METADATA;
11691 case RTE_FLOW_ITEM_TYPE_ICMP:
11692 flow_dv_translate_item_icmp(match_mask, match_value,
11694 last_item = MLX5_FLOW_LAYER_ICMP;
11696 case RTE_FLOW_ITEM_TYPE_ICMP6:
11697 flow_dv_translate_item_icmp6(match_mask, match_value,
11699 last_item = MLX5_FLOW_LAYER_ICMP6;
11701 case RTE_FLOW_ITEM_TYPE_TAG:
11702 flow_dv_translate_item_tag(dev, match_mask,
11703 match_value, items);
11704 last_item = MLX5_FLOW_ITEM_TAG;
11706 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
11707 flow_dv_translate_mlx5_item_tag(dev, match_mask,
11708 match_value, items);
11709 last_item = MLX5_FLOW_ITEM_TAG;
11711 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
11712 flow_dv_translate_item_tx_queue(dev, match_mask,
11715 last_item = MLX5_FLOW_ITEM_TX_QUEUE;
11717 case RTE_FLOW_ITEM_TYPE_GTP:
11718 flow_dv_translate_item_gtp(match_mask, match_value,
11720 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11721 last_item = MLX5_FLOW_LAYER_GTP;
11723 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
11724 ret = flow_dv_translate_item_gtp_psc(match_mask,
11728 return rte_flow_error_set(error, -ret,
11729 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
11730 "cannot create GTP PSC item");
11731 last_item = MLX5_FLOW_LAYER_GTP_PSC;
11733 case RTE_FLOW_ITEM_TYPE_ECPRI:
11734 if (!mlx5_flex_parser_ecpri_exist(dev)) {
11735 /* Create it only the first time to be used. */
11736 ret = mlx5_flex_parser_ecpri_alloc(dev);
11738 return rte_flow_error_set
11740 RTE_FLOW_ERROR_TYPE_ITEM,
11742 "cannot create eCPRI parser");
11744 /* Adjust the length matcher and device flow value. */
11745 matcher.mask.size = MLX5_ST_SZ_BYTES(fte_match_param);
11746 dev_flow->dv.value.size =
11747 MLX5_ST_SZ_BYTES(fte_match_param);
11748 flow_dv_translate_item_ecpri(dev, match_mask,
11749 match_value, items);
11750 /* No other protocol should follow eCPRI layer. */
11751 last_item = MLX5_FLOW_LAYER_ECPRI;
11756 item_flags |= last_item;
11759 * When E-Switch mode is enabled, we have two cases where we need to
11760 * set the source port manually.
11761 * The first one, is in case of Nic steering rule, and the second is
11762 * E-Switch rule where no port_id item was found. In both cases
11763 * the source port is set according the current port in use.
11765 if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
11766 (priv->representor || priv->master)) {
11767 if (flow_dv_translate_item_port_id(dev, match_mask,
11768 match_value, NULL, attr))
11771 #ifdef RTE_LIBRTE_MLX5_DEBUG
11772 MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
11773 dev_flow->dv.value.buf));
11776 * Layers may be already initialized from prefix flow if this dev_flow
11777 * is the suffix flow.
11779 handle->layers |= item_flags;
11780 if (action_flags & MLX5_FLOW_ACTION_RSS)
11781 flow_dv_hashfields_set(dev_flow, rss_desc);
11782 /* If has RSS action in the sample action, the Sample/Mirror resource
11783 * should be registered after the hash filed be update.
11785 if (action_flags & MLX5_FLOW_ACTION_SAMPLE) {
11786 ret = flow_dv_translate_action_sample(dev,
11795 ret = flow_dv_create_action_sample(dev,
11804 return rte_flow_error_set
11806 RTE_FLOW_ERROR_TYPE_ACTION,
11808 "cannot create sample action");
11809 if (num_of_dest > 1) {
11810 dev_flow->dv.actions[sample_act_pos] =
11811 dev_flow->dv.dest_array_res->action;
11813 dev_flow->dv.actions[sample_act_pos] =
11814 dev_flow->dv.sample_res->verbs_action;
11818 * For multiple destination (sample action with ratio=1), the encap
11819 * action and port id action will be combined into group action.
11820 * So need remove the original these actions in the flow and only
11821 * use the sample action instead of.
11823 if (num_of_dest > 1 &&
11824 (sample_act->dr_port_id_action || sample_act->dr_jump_action)) {
11826 void *temp_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
11828 for (i = 0; i < actions_n; i++) {
11829 if ((sample_act->dr_encap_action &&
11830 sample_act->dr_encap_action ==
11831 dev_flow->dv.actions[i]) ||
11832 (sample_act->dr_port_id_action &&
11833 sample_act->dr_port_id_action ==
11834 dev_flow->dv.actions[i]) ||
11835 (sample_act->dr_jump_action &&
11836 sample_act->dr_jump_action ==
11837 dev_flow->dv.actions[i]))
11839 temp_actions[tmp_actions_n++] = dev_flow->dv.actions[i];
11841 memcpy((void *)dev_flow->dv.actions,
11842 (void *)temp_actions,
11843 tmp_actions_n * sizeof(void *));
11844 actions_n = tmp_actions_n;
11846 dev_flow->dv.actions_n = actions_n;
11847 dev_flow->act_flags = action_flags;
11848 /* Register matcher. */
11849 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
11850 matcher.mask.size);
11851 matcher.priority = mlx5_get_matcher_priority(dev, attr,
11853 /* reserved field no needs to be set to 0 here. */
11854 tbl_key.domain = attr->transfer;
11855 tbl_key.direction = attr->egress;
11856 tbl_key.table_id = dev_flow->dv.group;
11857 if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow,
11858 tunnel, attr->group, error))
11864 * Set hash RX queue by hash fields (see enum ibv_rx_hash_fields)
11867 * @param[in, out] action
11868 * Shred RSS action holding hash RX queue objects.
11869 * @param[in] hash_fields
11870 * Defines combination of packet fields to participate in RX hash.
11871 * @param[in] tunnel
11873 * @param[in] hrxq_idx
11874 * Hash RX queue index to set.
11877 * 0 on success, otherwise negative errno value.
11880 __flow_dv_action_rss_hrxq_set(struct mlx5_shared_action_rss *action,
11881 const uint64_t hash_fields,
11884 uint32_t *hrxqs = action->hrxq;
11886 switch (hash_fields & ~IBV_RX_HASH_INNER) {
11887 case MLX5_RSS_HASH_IPV4:
11888 /* fall-through. */
11889 case MLX5_RSS_HASH_IPV4_DST_ONLY:
11890 /* fall-through. */
11891 case MLX5_RSS_HASH_IPV4_SRC_ONLY:
11892 hrxqs[0] = hrxq_idx;
11894 case MLX5_RSS_HASH_IPV4_TCP:
11895 /* fall-through. */
11896 case MLX5_RSS_HASH_IPV4_TCP_DST_ONLY:
11897 /* fall-through. */
11898 case MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY:
11899 hrxqs[1] = hrxq_idx;
11901 case MLX5_RSS_HASH_IPV4_UDP:
11902 /* fall-through. */
11903 case MLX5_RSS_HASH_IPV4_UDP_DST_ONLY:
11904 /* fall-through. */
11905 case MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY:
11906 hrxqs[2] = hrxq_idx;
11908 case MLX5_RSS_HASH_IPV6:
11909 /* fall-through. */
11910 case MLX5_RSS_HASH_IPV6_DST_ONLY:
11911 /* fall-through. */
11912 case MLX5_RSS_HASH_IPV6_SRC_ONLY:
11913 hrxqs[3] = hrxq_idx;
11915 case MLX5_RSS_HASH_IPV6_TCP:
11916 /* fall-through. */
11917 case MLX5_RSS_HASH_IPV6_TCP_DST_ONLY:
11918 /* fall-through. */
11919 case MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY:
11920 hrxqs[4] = hrxq_idx;
11922 case MLX5_RSS_HASH_IPV6_UDP:
11923 /* fall-through. */
11924 case MLX5_RSS_HASH_IPV6_UDP_DST_ONLY:
11925 /* fall-through. */
11926 case MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY:
11927 hrxqs[5] = hrxq_idx;
11929 case MLX5_RSS_HASH_NONE:
11930 hrxqs[6] = hrxq_idx;
11938 * Look up for hash RX queue by hash fields (see enum ibv_rx_hash_fields)
11942 * Pointer to the Ethernet device structure.
11944 * Shared RSS action ID holding hash RX queue objects.
11945 * @param[in] hash_fields
11946 * Defines combination of packet fields to participate in RX hash.
11947 * @param[in] tunnel
11951 * Valid hash RX queue index, otherwise 0.
11954 __flow_dv_action_rss_hrxq_lookup(struct rte_eth_dev *dev, uint32_t idx,
11955 const uint64_t hash_fields)
11957 struct mlx5_priv *priv = dev->data->dev_private;
11958 struct mlx5_shared_action_rss *shared_rss =
11959 mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
11960 const uint32_t *hrxqs = shared_rss->hrxq;
11962 switch (hash_fields & ~IBV_RX_HASH_INNER) {
11963 case MLX5_RSS_HASH_IPV4:
11964 /* fall-through. */
11965 case MLX5_RSS_HASH_IPV4_DST_ONLY:
11966 /* fall-through. */
11967 case MLX5_RSS_HASH_IPV4_SRC_ONLY:
11969 case MLX5_RSS_HASH_IPV4_TCP:
11970 /* fall-through. */
11971 case MLX5_RSS_HASH_IPV4_TCP_DST_ONLY:
11972 /* fall-through. */
11973 case MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY:
11975 case MLX5_RSS_HASH_IPV4_UDP:
11976 /* fall-through. */
11977 case MLX5_RSS_HASH_IPV4_UDP_DST_ONLY:
11978 /* fall-through. */
11979 case MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY:
11981 case MLX5_RSS_HASH_IPV6:
11982 /* fall-through. */
11983 case MLX5_RSS_HASH_IPV6_DST_ONLY:
11984 /* fall-through. */
11985 case MLX5_RSS_HASH_IPV6_SRC_ONLY:
11987 case MLX5_RSS_HASH_IPV6_TCP:
11988 /* fall-through. */
11989 case MLX5_RSS_HASH_IPV6_TCP_DST_ONLY:
11990 /* fall-through. */
11991 case MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY:
11993 case MLX5_RSS_HASH_IPV6_UDP:
11994 /* fall-through. */
11995 case MLX5_RSS_HASH_IPV6_UDP_DST_ONLY:
11996 /* fall-through. */
11997 case MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY:
11999 case MLX5_RSS_HASH_NONE:
12008 * Apply the flow to the NIC, lock free,
12009 * (mutex should be acquired by caller).
12012 * Pointer to the Ethernet device structure.
12013 * @param[in, out] flow
12014 * Pointer to flow structure.
12015 * @param[out] error
12016 * Pointer to error structure.
12019 * 0 on success, a negative errno value otherwise and rte_errno is set.
12022 flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
12023 struct rte_flow_error *error)
12025 struct mlx5_flow_dv_workspace *dv;
12026 struct mlx5_flow_handle *dh;
12027 struct mlx5_flow_handle_dv *dv_h;
12028 struct mlx5_flow *dev_flow;
12029 struct mlx5_priv *priv = dev->data->dev_private;
12030 uint32_t handle_idx;
12034 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
12035 struct mlx5_flow_rss_desc *rss_desc = &wks->rss_desc;
12038 for (idx = wks->flow_idx - 1; idx >= 0; idx--) {
12039 dev_flow = &wks->flows[idx];
12040 dv = &dev_flow->dv;
12041 dh = dev_flow->handle;
12044 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
12045 if (dv->transfer) {
12046 MLX5_ASSERT(priv->sh->dr_drop_action);
12047 dv->actions[n++] = priv->sh->dr_drop_action;
12049 #ifdef HAVE_MLX5DV_DR
12050 /* DR supports drop action placeholder. */
12051 MLX5_ASSERT(priv->sh->dr_drop_action);
12052 dv->actions[n++] = priv->sh->dr_drop_action;
12054 /* For DV we use the explicit drop queue. */
12055 MLX5_ASSERT(priv->drop_queue.hrxq);
12057 priv->drop_queue.hrxq->action;
12060 } else if ((dh->fate_action == MLX5_FLOW_FATE_QUEUE &&
12061 !dv_h->rix_sample && !dv_h->rix_dest_array)) {
12062 struct mlx5_hrxq *hrxq;
12065 hrxq = flow_dv_hrxq_prepare(dev, dev_flow, rss_desc,
12070 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12071 "cannot get hash queue");
12074 dh->rix_hrxq = hrxq_idx;
12075 dv->actions[n++] = hrxq->action;
12076 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
12077 struct mlx5_hrxq *hrxq = NULL;
12080 hrxq_idx = __flow_dv_action_rss_hrxq_lookup(dev,
12081 rss_desc->shared_rss,
12082 dev_flow->hash_fields);
12084 hrxq = mlx5_ipool_get
12085 (priv->sh->ipool[MLX5_IPOOL_HRXQ],
12090 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12091 "cannot get hash queue");
12094 dh->rix_srss = rss_desc->shared_rss;
12095 dv->actions[n++] = hrxq->action;
12096 } else if (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS) {
12097 if (!priv->sh->default_miss_action) {
12100 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12101 "default miss action not be created.");
12104 dv->actions[n++] = priv->sh->default_miss_action;
12106 err = mlx5_flow_os_create_flow(dv_h->matcher->matcher_object,
12107 (void *)&dv->value, n,
12108 dv->actions, &dh->drv_flow);
12110 rte_flow_error_set(error, errno,
12111 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12113 "hardware refuses to create flow");
12116 if (priv->vmwa_context &&
12117 dh->vf_vlan.tag && !dh->vf_vlan.created) {
12119 * The rule contains the VLAN pattern.
12120 * For VF we are going to create VLAN
12121 * interface to make hypervisor set correct
12122 * e-Switch vport context.
12124 mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
12129 err = rte_errno; /* Save rte_errno before cleanup. */
12130 SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles,
12131 handle_idx, dh, next) {
12132 /* hrxq is union, don't clear it if the flag is not set. */
12133 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE && dh->rix_hrxq) {
12134 mlx5_hrxq_release(dev, dh->rix_hrxq);
12136 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
12139 if (dh->vf_vlan.tag && dh->vf_vlan.created)
12140 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
12142 rte_errno = err; /* Restore rte_errno. */
12147 flow_dv_matcher_remove_cb(struct mlx5_cache_list *list __rte_unused,
12148 struct mlx5_cache_entry *entry)
12150 struct mlx5_flow_dv_matcher *cache = container_of(entry, typeof(*cache),
12153 claim_zero(mlx5_flow_os_destroy_flow_matcher(cache->matcher_object));
12158 * Release the flow matcher.
12161 * Pointer to Ethernet device.
12163 * Index to port ID action resource.
12166 * 1 while a reference on it exists, 0 when freed.
12169 flow_dv_matcher_release(struct rte_eth_dev *dev,
12170 struct mlx5_flow_handle *handle)
12172 struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
12173 struct mlx5_flow_tbl_data_entry *tbl = container_of(matcher->tbl,
12174 typeof(*tbl), tbl);
12177 MLX5_ASSERT(matcher->matcher_object);
12178 ret = mlx5_cache_unregister(&tbl->matchers, &matcher->entry);
12179 flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl->tbl);
12184 * Release encap_decap resource.
12187 * Pointer to the hash list.
12189 * Pointer to exist resource entry object.
12192 flow_dv_encap_decap_remove_cb(struct mlx5_hlist *list,
12193 struct mlx5_hlist_entry *entry)
12195 struct mlx5_dev_ctx_shared *sh = list->ctx;
12196 struct mlx5_flow_dv_encap_decap_resource *res =
12197 container_of(entry, typeof(*res), entry);
12199 claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
12200 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], res->idx);
12204 * Release an encap/decap resource.
12207 * Pointer to Ethernet device.
12208 * @param encap_decap_idx
12209 * Index of encap decap resource.
12212 * 1 while a reference on it exists, 0 when freed.
12215 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
12216 uint32_t encap_decap_idx)
12218 struct mlx5_priv *priv = dev->data->dev_private;
12219 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
12221 cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
12223 if (!cache_resource)
12225 MLX5_ASSERT(cache_resource->action);
12226 return mlx5_hlist_unregister(priv->sh->encaps_decaps,
12227 &cache_resource->entry);
12231 * Release an jump to table action resource.
12234 * Pointer to Ethernet device.
12236 * Index to the jump action resource.
12239 * 1 while a reference on it exists, 0 when freed.
12242 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
12245 struct mlx5_priv *priv = dev->data->dev_private;
12246 struct mlx5_flow_tbl_data_entry *tbl_data;
12248 tbl_data = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_JUMP],
12252 return flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl_data->tbl);
12256 flow_dv_modify_remove_cb(struct mlx5_hlist *list __rte_unused,
12257 struct mlx5_hlist_entry *entry)
12259 struct mlx5_flow_dv_modify_hdr_resource *res =
12260 container_of(entry, typeof(*res), entry);
12262 claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
12267 * Release a modify-header resource.
12270 * Pointer to Ethernet device.
12272 * Pointer to mlx5_flow_handle.
12275 * 1 while a reference on it exists, 0 when freed.
12278 flow_dv_modify_hdr_resource_release(struct rte_eth_dev *dev,
12279 struct mlx5_flow_handle *handle)
12281 struct mlx5_priv *priv = dev->data->dev_private;
12282 struct mlx5_flow_dv_modify_hdr_resource *entry = handle->dvh.modify_hdr;
12284 MLX5_ASSERT(entry->action);
12285 return mlx5_hlist_unregister(priv->sh->modify_cmds, &entry->entry);
12289 flow_dv_port_id_remove_cb(struct mlx5_cache_list *list,
12290 struct mlx5_cache_entry *entry)
12292 struct mlx5_dev_ctx_shared *sh = list->ctx;
12293 struct mlx5_flow_dv_port_id_action_resource *cache =
12294 container_of(entry, typeof(*cache), entry);
12296 claim_zero(mlx5_flow_os_destroy_flow_action(cache->action));
12297 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], cache->idx);
12301 * Release port ID action resource.
12304 * Pointer to Ethernet device.
12306 * Pointer to mlx5_flow_handle.
12309 * 1 while a reference on it exists, 0 when freed.
12312 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
12315 struct mlx5_priv *priv = dev->data->dev_private;
12316 struct mlx5_flow_dv_port_id_action_resource *cache;
12318 cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID], port_id);
12321 MLX5_ASSERT(cache->action);
12322 return mlx5_cache_unregister(&priv->sh->port_id_action_list,
12327 * Release shared RSS action resource.
12330 * Pointer to Ethernet device.
12332 * Shared RSS action index.
12335 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss)
12337 struct mlx5_priv *priv = dev->data->dev_private;
12338 struct mlx5_shared_action_rss *shared_rss;
12340 shared_rss = mlx5_ipool_get
12341 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], srss);
12342 __atomic_sub_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
12346 flow_dv_push_vlan_remove_cb(struct mlx5_cache_list *list,
12347 struct mlx5_cache_entry *entry)
12349 struct mlx5_dev_ctx_shared *sh = list->ctx;
12350 struct mlx5_flow_dv_push_vlan_action_resource *cache =
12351 container_of(entry, typeof(*cache), entry);
12353 claim_zero(mlx5_flow_os_destroy_flow_action(cache->action));
12354 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], cache->idx);
12358 * Release push vlan action resource.
12361 * Pointer to Ethernet device.
12363 * Pointer to mlx5_flow_handle.
12366 * 1 while a reference on it exists, 0 when freed.
12369 flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,
12370 struct mlx5_flow_handle *handle)
12372 struct mlx5_priv *priv = dev->data->dev_private;
12373 struct mlx5_flow_dv_push_vlan_action_resource *cache;
12374 uint32_t idx = handle->dvh.rix_push_vlan;
12376 cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
12379 MLX5_ASSERT(cache->action);
12380 return mlx5_cache_unregister(&priv->sh->push_vlan_action_list,
12385 * Release the fate resource.
12388 * Pointer to Ethernet device.
12390 * Pointer to mlx5_flow_handle.
12393 flow_dv_fate_resource_release(struct rte_eth_dev *dev,
12394 struct mlx5_flow_handle *handle)
12396 if (!handle->rix_fate)
12398 switch (handle->fate_action) {
12399 case MLX5_FLOW_FATE_QUEUE:
12400 if (!handle->dvh.rix_sample && !handle->dvh.rix_dest_array)
12401 mlx5_hrxq_release(dev, handle->rix_hrxq);
12403 case MLX5_FLOW_FATE_JUMP:
12404 flow_dv_jump_tbl_resource_release(dev, handle->rix_jump);
12406 case MLX5_FLOW_FATE_PORT_ID:
12407 flow_dv_port_id_action_resource_release(dev,
12408 handle->rix_port_id_action);
12411 DRV_LOG(DEBUG, "Incorrect fate action:%d", handle->fate_action);
12414 handle->rix_fate = 0;
12418 flow_dv_sample_remove_cb(struct mlx5_cache_list *list __rte_unused,
12419 struct mlx5_cache_entry *entry)
12421 struct mlx5_flow_dv_sample_resource *cache_resource =
12422 container_of(entry, typeof(*cache_resource), entry);
12423 struct rte_eth_dev *dev = cache_resource->dev;
12424 struct mlx5_priv *priv = dev->data->dev_private;
12426 if (cache_resource->verbs_action)
12427 claim_zero(mlx5_flow_os_destroy_flow_action
12428 (cache_resource->verbs_action));
12429 if (cache_resource->normal_path_tbl)
12430 flow_dv_tbl_resource_release(MLX5_SH(dev),
12431 cache_resource->normal_path_tbl);
12432 flow_dv_sample_sub_actions_release(dev,
12433 &cache_resource->sample_idx);
12434 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
12435 cache_resource->idx);
12436 DRV_LOG(DEBUG, "sample resource %p: removed",
12437 (void *)cache_resource);
12441 * Release an sample resource.
12444 * Pointer to Ethernet device.
12446 * Pointer to mlx5_flow_handle.
12449 * 1 while a reference on it exists, 0 when freed.
12452 flow_dv_sample_resource_release(struct rte_eth_dev *dev,
12453 struct mlx5_flow_handle *handle)
12455 struct mlx5_priv *priv = dev->data->dev_private;
12456 struct mlx5_flow_dv_sample_resource *cache_resource;
12458 cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
12459 handle->dvh.rix_sample);
12460 if (!cache_resource)
12462 MLX5_ASSERT(cache_resource->verbs_action);
12463 return mlx5_cache_unregister(&priv->sh->sample_action_list,
12464 &cache_resource->entry);
12468 flow_dv_dest_array_remove_cb(struct mlx5_cache_list *list __rte_unused,
12469 struct mlx5_cache_entry *entry)
12471 struct mlx5_flow_dv_dest_array_resource *cache_resource =
12472 container_of(entry, typeof(*cache_resource), entry);
12473 struct rte_eth_dev *dev = cache_resource->dev;
12474 struct mlx5_priv *priv = dev->data->dev_private;
12477 MLX5_ASSERT(cache_resource->action);
12478 if (cache_resource->action)
12479 claim_zero(mlx5_flow_os_destroy_flow_action
12480 (cache_resource->action));
12481 for (; i < cache_resource->num_of_dest; i++)
12482 flow_dv_sample_sub_actions_release(dev,
12483 &cache_resource->sample_idx[i]);
12484 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
12485 cache_resource->idx);
12486 DRV_LOG(DEBUG, "destination array resource %p: removed",
12487 (void *)cache_resource);
12491 * Release an destination array resource.
12494 * Pointer to Ethernet device.
12496 * Pointer to mlx5_flow_handle.
12499 * 1 while a reference on it exists, 0 when freed.
12502 flow_dv_dest_array_resource_release(struct rte_eth_dev *dev,
12503 struct mlx5_flow_handle *handle)
12505 struct mlx5_priv *priv = dev->data->dev_private;
12506 struct mlx5_flow_dv_dest_array_resource *cache;
12508 cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
12509 handle->dvh.rix_dest_array);
12512 MLX5_ASSERT(cache->action);
12513 return mlx5_cache_unregister(&priv->sh->dest_array_list,
12518 flow_dv_geneve_tlv_option_resource_release(struct rte_eth_dev *dev)
12520 struct mlx5_priv *priv = dev->data->dev_private;
12521 struct mlx5_dev_ctx_shared *sh = priv->sh;
12522 struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
12523 sh->geneve_tlv_option_resource;
12524 rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
12525 if (geneve_opt_resource) {
12526 if (!(__atomic_sub_fetch(&geneve_opt_resource->refcnt, 1,
12527 __ATOMIC_RELAXED))) {
12528 claim_zero(mlx5_devx_cmd_destroy
12529 (geneve_opt_resource->obj));
12530 mlx5_free(sh->geneve_tlv_option_resource);
12531 sh->geneve_tlv_option_resource = NULL;
12534 rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
12538 * Remove the flow from the NIC but keeps it in memory.
12539 * Lock free, (mutex should be acquired by caller).
12542 * Pointer to Ethernet device.
12543 * @param[in, out] flow
12544 * Pointer to flow structure.
12547 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
12549 struct mlx5_flow_handle *dh;
12550 uint32_t handle_idx;
12551 struct mlx5_priv *priv = dev->data->dev_private;
12555 handle_idx = flow->dev_handles;
12556 while (handle_idx) {
12557 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
12561 if (dh->drv_flow) {
12562 claim_zero(mlx5_flow_os_destroy_flow(dh->drv_flow));
12563 dh->drv_flow = NULL;
12565 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE)
12566 flow_dv_fate_resource_release(dev, dh);
12567 if (dh->vf_vlan.tag && dh->vf_vlan.created)
12568 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
12569 handle_idx = dh->next.next;
12574 * Remove the flow from the NIC and the memory.
12575 * Lock free, (mutex should be acquired by caller).
12578 * Pointer to the Ethernet device structure.
12579 * @param[in, out] flow
12580 * Pointer to flow structure.
12583 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
12585 struct mlx5_flow_handle *dev_handle;
12586 struct mlx5_priv *priv = dev->data->dev_private;
12587 struct mlx5_flow_meter *fm = NULL;
12592 flow_dv_remove(dev, flow);
12593 if (flow->counter) {
12594 flow_dv_counter_free(dev, flow->counter);
12598 fm = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MTR],
12601 mlx5_flow_meter_detach(fm);
12605 flow_dv_aso_age_release(dev, flow->age);
12606 if (flow->geneve_tlv_option) {
12607 flow_dv_geneve_tlv_option_resource_release(dev);
12608 flow->geneve_tlv_option = 0;
12610 while (flow->dev_handles) {
12611 uint32_t tmp_idx = flow->dev_handles;
12613 dev_handle = mlx5_ipool_get(priv->sh->ipool
12614 [MLX5_IPOOL_MLX5_FLOW], tmp_idx);
12617 flow->dev_handles = dev_handle->next.next;
12618 if (dev_handle->dvh.matcher)
12619 flow_dv_matcher_release(dev, dev_handle);
12620 if (dev_handle->dvh.rix_sample)
12621 flow_dv_sample_resource_release(dev, dev_handle);
12622 if (dev_handle->dvh.rix_dest_array)
12623 flow_dv_dest_array_resource_release(dev, dev_handle);
12624 if (dev_handle->dvh.rix_encap_decap)
12625 flow_dv_encap_decap_resource_release(dev,
12626 dev_handle->dvh.rix_encap_decap);
12627 if (dev_handle->dvh.modify_hdr)
12628 flow_dv_modify_hdr_resource_release(dev, dev_handle);
12629 if (dev_handle->dvh.rix_push_vlan)
12630 flow_dv_push_vlan_action_resource_release(dev,
12632 if (dev_handle->dvh.rix_tag)
12633 flow_dv_tag_release(dev,
12634 dev_handle->dvh.rix_tag);
12635 if (dev_handle->fate_action != MLX5_FLOW_FATE_SHARED_RSS)
12636 flow_dv_fate_resource_release(dev, dev_handle);
12638 srss = dev_handle->rix_srss;
12639 if (fm && dev_handle->is_meter_flow_id &&
12640 dev_handle->split_flow_id)
12641 mlx5_ipool_free(fm->flow_ipool,
12642 dev_handle->split_flow_id);
12643 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
12647 flow_dv_shared_rss_action_release(dev, srss);
12651 * Release array of hash RX queue objects.
12655 * Pointer to the Ethernet device structure.
12656 * @param[in, out] hrxqs
12657 * Array of hash RX queue objects.
12660 * Total number of references to hash RX queue objects in *hrxqs* array
12661 * after this operation.
12664 __flow_dv_hrxqs_release(struct rte_eth_dev *dev,
12665 uint32_t (*hrxqs)[MLX5_RSS_HASH_FIELDS_LEN])
12670 for (i = 0; i < RTE_DIM(*hrxqs); i++) {
12671 int ret = mlx5_hrxq_release(dev, (*hrxqs)[i]);
12681 * Release all hash RX queue objects representing shared RSS action.
12684 * Pointer to the Ethernet device structure.
12685 * @param[in, out] action
12686 * Shared RSS action to remove hash RX queue objects from.
12689 * Total number of references to hash RX queue objects stored in *action*
12690 * after this operation.
12691 * Expected to be 0 if no external references held.
12694 __flow_dv_action_rss_hrxqs_release(struct rte_eth_dev *dev,
12695 struct mlx5_shared_action_rss *shared_rss)
12697 return __flow_dv_hrxqs_release(dev, &shared_rss->hrxq);
12701 * Adjust L3/L4 hash value of pre-created shared RSS hrxq according to
12704 * Only one hash value is available for one L3+L4 combination:
12706 * MLX5_RSS_HASH_IPV4, MLX5_RSS_HASH_IPV4_SRC_ONLY, and
12707 * MLX5_RSS_HASH_IPV4_DST_ONLY are mutually exclusive so they can share
12708 * same slot in mlx5_rss_hash_fields.
12711 * Pointer to the shared action RSS conf.
12712 * @param[in, out] hash_field
12713 * hash_field variable needed to be adjusted.
12719 __flow_dv_action_rss_l34_hash_adjust(struct mlx5_shared_action_rss *rss,
12720 uint64_t *hash_field)
12722 uint64_t rss_types = rss->origin.types;
12724 switch (*hash_field & ~IBV_RX_HASH_INNER) {
12725 case MLX5_RSS_HASH_IPV4:
12726 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
12727 *hash_field &= ~MLX5_RSS_HASH_IPV4;
12728 if (rss_types & ETH_RSS_L3_DST_ONLY)
12729 *hash_field |= IBV_RX_HASH_DST_IPV4;
12730 else if (rss_types & ETH_RSS_L3_SRC_ONLY)
12731 *hash_field |= IBV_RX_HASH_SRC_IPV4;
12733 *hash_field |= MLX5_RSS_HASH_IPV4;
12736 case MLX5_RSS_HASH_IPV6:
12737 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
12738 *hash_field &= ~MLX5_RSS_HASH_IPV6;
12739 if (rss_types & ETH_RSS_L3_DST_ONLY)
12740 *hash_field |= IBV_RX_HASH_DST_IPV6;
12741 else if (rss_types & ETH_RSS_L3_SRC_ONLY)
12742 *hash_field |= IBV_RX_HASH_SRC_IPV6;
12744 *hash_field |= MLX5_RSS_HASH_IPV6;
12747 case MLX5_RSS_HASH_IPV4_UDP:
12748 /* fall-through. */
12749 case MLX5_RSS_HASH_IPV6_UDP:
12750 if (rss_types & ETH_RSS_UDP) {
12751 *hash_field &= ~MLX5_UDP_IBV_RX_HASH;
12752 if (rss_types & ETH_RSS_L4_DST_ONLY)
12753 *hash_field |= IBV_RX_HASH_DST_PORT_UDP;
12754 else if (rss_types & ETH_RSS_L4_SRC_ONLY)
12755 *hash_field |= IBV_RX_HASH_SRC_PORT_UDP;
12757 *hash_field |= MLX5_UDP_IBV_RX_HASH;
12760 case MLX5_RSS_HASH_IPV4_TCP:
12761 /* fall-through. */
12762 case MLX5_RSS_HASH_IPV6_TCP:
12763 if (rss_types & ETH_RSS_TCP) {
12764 *hash_field &= ~MLX5_TCP_IBV_RX_HASH;
12765 if (rss_types & ETH_RSS_L4_DST_ONLY)
12766 *hash_field |= IBV_RX_HASH_DST_PORT_TCP;
12767 else if (rss_types & ETH_RSS_L4_SRC_ONLY)
12768 *hash_field |= IBV_RX_HASH_SRC_PORT_TCP;
12770 *hash_field |= MLX5_TCP_IBV_RX_HASH;
12779 * Setup shared RSS action.
12780 * Prepare set of hash RX queue objects sufficient to handle all valid
12781 * hash_fields combinations (see enum ibv_rx_hash_fields).
12784 * Pointer to the Ethernet device structure.
12785 * @param[in] action_idx
12786 * Shared RSS action ipool index.
12787 * @param[in, out] action
12788 * Partially initialized shared RSS action.
12789 * @param[out] error
12790 * Perform verbose error reporting if not NULL. Initialized in case of
12794 * 0 on success, otherwise negative errno value.
12797 __flow_dv_action_rss_setup(struct rte_eth_dev *dev,
12798 uint32_t action_idx,
12799 struct mlx5_shared_action_rss *shared_rss,
12800 struct rte_flow_error *error)
12802 struct mlx5_flow_rss_desc rss_desc = { 0 };
12806 if (mlx5_ind_table_obj_setup(dev, shared_rss->ind_tbl)) {
12807 return rte_flow_error_set(error, rte_errno,
12808 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12809 "cannot setup indirection table");
12811 memcpy(rss_desc.key, shared_rss->origin.key, MLX5_RSS_HASH_KEY_LEN);
12812 rss_desc.key_len = MLX5_RSS_HASH_KEY_LEN;
12813 rss_desc.const_q = shared_rss->origin.queue;
12814 rss_desc.queue_num = shared_rss->origin.queue_num;
12815 /* Set non-zero value to indicate a shared RSS. */
12816 rss_desc.shared_rss = action_idx;
12817 rss_desc.ind_tbl = shared_rss->ind_tbl;
12818 for (i = 0; i < MLX5_RSS_HASH_FIELDS_LEN; i++) {
12820 uint64_t hash_fields = mlx5_rss_hash_fields[i];
12823 __flow_dv_action_rss_l34_hash_adjust(shared_rss, &hash_fields);
12824 if (shared_rss->origin.level > 1) {
12825 hash_fields |= IBV_RX_HASH_INNER;
12828 rss_desc.tunnel = tunnel;
12829 rss_desc.hash_fields = hash_fields;
12830 hrxq_idx = mlx5_hrxq_get(dev, &rss_desc);
12834 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12835 "cannot get hash queue");
12836 goto error_hrxq_new;
12838 err = __flow_dv_action_rss_hrxq_set
12839 (shared_rss, hash_fields, hrxq_idx);
12845 __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
12846 if (!mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl, true))
12847 shared_rss->ind_tbl = NULL;
12853 * Create shared RSS action.
12856 * Pointer to the Ethernet device structure.
12858 * Shared action configuration.
12860 * RSS action specification used to create shared action.
12861 * @param[out] error
12862 * Perform verbose error reporting if not NULL. Initialized in case of
12866 * A valid shared action ID in case of success, 0 otherwise and
12867 * rte_errno is set.
12870 __flow_dv_action_rss_create(struct rte_eth_dev *dev,
12871 const struct rte_flow_indir_action_conf *conf,
12872 const struct rte_flow_action_rss *rss,
12873 struct rte_flow_error *error)
12875 struct mlx5_priv *priv = dev->data->dev_private;
12876 struct mlx5_shared_action_rss *shared_rss = NULL;
12877 void *queue = NULL;
12878 struct rte_flow_action_rss *origin;
12879 const uint8_t *rss_key;
12880 uint32_t queue_size = rss->queue_num * sizeof(uint16_t);
12883 RTE_SET_USED(conf);
12884 queue = mlx5_malloc(0, RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
12886 shared_rss = mlx5_ipool_zmalloc
12887 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], &idx);
12888 if (!shared_rss || !queue) {
12889 rte_flow_error_set(error, ENOMEM,
12890 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12891 "cannot allocate resource memory");
12892 goto error_rss_init;
12894 if (idx > (1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET)) {
12895 rte_flow_error_set(error, E2BIG,
12896 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12897 "rss action number out of range");
12898 goto error_rss_init;
12900 shared_rss->ind_tbl = mlx5_malloc(MLX5_MEM_ZERO,
12901 sizeof(*shared_rss->ind_tbl),
12903 if (!shared_rss->ind_tbl) {
12904 rte_flow_error_set(error, ENOMEM,
12905 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12906 "cannot allocate resource memory");
12907 goto error_rss_init;
12909 memcpy(queue, rss->queue, queue_size);
12910 shared_rss->ind_tbl->queues = queue;
12911 shared_rss->ind_tbl->queues_n = rss->queue_num;
12912 origin = &shared_rss->origin;
12913 origin->func = rss->func;
12914 origin->level = rss->level;
12915 /* RSS type 0 indicates default RSS type (ETH_RSS_IP). */
12916 origin->types = !rss->types ? ETH_RSS_IP : rss->types;
12917 /* NULL RSS key indicates default RSS key. */
12918 rss_key = !rss->key ? rss_hash_default_key : rss->key;
12919 memcpy(shared_rss->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
12920 origin->key = &shared_rss->key[0];
12921 origin->key_len = MLX5_RSS_HASH_KEY_LEN;
12922 origin->queue = queue;
12923 origin->queue_num = rss->queue_num;
12924 if (__flow_dv_action_rss_setup(dev, idx, shared_rss, error))
12925 goto error_rss_init;
12926 rte_spinlock_init(&shared_rss->action_rss_sl);
12927 __atomic_add_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
12928 rte_spinlock_lock(&priv->shared_act_sl);
12929 ILIST_INSERT(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
12930 &priv->rss_shared_actions, idx, shared_rss, next);
12931 rte_spinlock_unlock(&priv->shared_act_sl);
12935 if (shared_rss->ind_tbl)
12936 mlx5_free(shared_rss->ind_tbl);
12937 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
12946 * Destroy the shared RSS action.
12947 * Release related hash RX queue objects.
12950 * Pointer to the Ethernet device structure.
12952 * The shared RSS action object ID to be removed.
12953 * @param[out] error
12954 * Perform verbose error reporting if not NULL. Initialized in case of
12958 * 0 on success, otherwise negative errno value.
12961 __flow_dv_action_rss_release(struct rte_eth_dev *dev, uint32_t idx,
12962 struct rte_flow_error *error)
12964 struct mlx5_priv *priv = dev->data->dev_private;
12965 struct mlx5_shared_action_rss *shared_rss =
12966 mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
12967 uint32_t old_refcnt = 1;
12969 uint16_t *queue = NULL;
12972 return rte_flow_error_set(error, EINVAL,
12973 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12974 "invalid shared action");
12975 remaining = __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
12977 return rte_flow_error_set(error, EBUSY,
12978 RTE_FLOW_ERROR_TYPE_ACTION,
12980 "shared rss hrxq has references");
12981 if (!__atomic_compare_exchange_n(&shared_rss->refcnt, &old_refcnt,
12982 0, 0, __ATOMIC_ACQUIRE,
12984 return rte_flow_error_set(error, EBUSY,
12985 RTE_FLOW_ERROR_TYPE_ACTION,
12987 "shared rss has references");
12988 queue = shared_rss->ind_tbl->queues;
12989 remaining = mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl, true);
12991 return rte_flow_error_set(error, EBUSY,
12992 RTE_FLOW_ERROR_TYPE_ACTION,
12994 "shared rss indirection table has"
12997 rte_spinlock_lock(&priv->shared_act_sl);
12998 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
12999 &priv->rss_shared_actions, idx, shared_rss, next);
13000 rte_spinlock_unlock(&priv->shared_act_sl);
13001 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
13007 * Create indirect action, lock free,
13008 * (mutex should be acquired by caller).
13009 * Dispatcher for action type specific call.
13012 * Pointer to the Ethernet device structure.
13014 * Shared action configuration.
13015 * @param[in] action
13016 * Action specification used to create indirect action.
13017 * @param[out] error
13018 * Perform verbose error reporting if not NULL. Initialized in case of
13022 * A valid shared action handle in case of success, NULL otherwise and
13023 * rte_errno is set.
13025 static struct rte_flow_action_handle *
13026 flow_dv_action_create(struct rte_eth_dev *dev,
13027 const struct rte_flow_indir_action_conf *conf,
13028 const struct rte_flow_action *action,
13029 struct rte_flow_error *err)
13034 switch (action->type) {
13035 case RTE_FLOW_ACTION_TYPE_RSS:
13036 ret = __flow_dv_action_rss_create(dev, conf, action->conf, err);
13037 idx = (MLX5_INDIRECT_ACTION_TYPE_RSS <<
13038 MLX5_INDIRECT_ACTION_TYPE_OFFSET) | ret;
13040 case RTE_FLOW_ACTION_TYPE_AGE:
13041 ret = flow_dv_translate_create_aso_age(dev, action->conf, err);
13042 idx = (MLX5_INDIRECT_ACTION_TYPE_AGE <<
13043 MLX5_INDIRECT_ACTION_TYPE_OFFSET) | ret;
13045 struct mlx5_aso_age_action *aso_age =
13046 flow_aso_age_get_by_idx(dev, ret);
13048 if (!aso_age->age_params.context)
13049 aso_age->age_params.context =
13050 (void *)(uintptr_t)idx;
13054 rte_flow_error_set(err, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION,
13055 NULL, "action type not supported");
13058 return ret ? (struct rte_flow_action_handle *)(uintptr_t)idx : NULL;
13062 * Destroy the indirect action.
13063 * Release action related resources on the NIC and the memory.
13064 * Lock free, (mutex should be acquired by caller).
13065 * Dispatcher for action type specific call.
13068 * Pointer to the Ethernet device structure.
13069 * @param[in] handle
13070 * The indirect action object handle to be removed.
13071 * @param[out] error
13072 * Perform verbose error reporting if not NULL. Initialized in case of
13076 * 0 on success, otherwise negative errno value.
13079 flow_dv_action_destroy(struct rte_eth_dev *dev,
13080 struct rte_flow_action_handle *handle,
13081 struct rte_flow_error *error)
13083 uint32_t act_idx = (uint32_t)(uintptr_t)handle;
13084 uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
13085 uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
13089 case MLX5_INDIRECT_ACTION_TYPE_RSS:
13090 return __flow_dv_action_rss_release(dev, idx, error);
13091 case MLX5_INDIRECT_ACTION_TYPE_AGE:
13092 ret = flow_dv_aso_age_release(dev, idx);
13095 * In this case, the last flow has a reference will
13096 * actually release the age action.
13098 DRV_LOG(DEBUG, "Indirect age action %" PRIu32 " was"
13099 " released with references %d.", idx, ret);
13102 return rte_flow_error_set(error, ENOTSUP,
13103 RTE_FLOW_ERROR_TYPE_ACTION,
13105 "action type not supported");
13110 * Updates in place shared RSS action configuration.
13113 * Pointer to the Ethernet device structure.
13115 * The shared RSS action object ID to be updated.
13116 * @param[in] action_conf
13117 * RSS action specification used to modify *shared_rss*.
13118 * @param[out] error
13119 * Perform verbose error reporting if not NULL. Initialized in case of
13123 * 0 on success, otherwise negative errno value.
13124 * @note: currently only support update of RSS queues.
13127 __flow_dv_action_rss_update(struct rte_eth_dev *dev, uint32_t idx,
13128 const struct rte_flow_action_rss *action_conf,
13129 struct rte_flow_error *error)
13131 struct mlx5_priv *priv = dev->data->dev_private;
13132 struct mlx5_shared_action_rss *shared_rss =
13133 mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
13135 void *queue = NULL;
13136 uint16_t *queue_old = NULL;
13137 uint32_t queue_size = action_conf->queue_num * sizeof(uint16_t);
13140 return rte_flow_error_set(error, EINVAL,
13141 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
13142 "invalid shared action to update");
13143 if (priv->obj_ops.ind_table_modify == NULL)
13144 return rte_flow_error_set(error, ENOTSUP,
13145 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
13146 "cannot modify indirection table");
13147 queue = mlx5_malloc(MLX5_MEM_ZERO,
13148 RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
13151 return rte_flow_error_set(error, ENOMEM,
13152 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13154 "cannot allocate resource memory");
13155 memcpy(queue, action_conf->queue, queue_size);
13156 MLX5_ASSERT(shared_rss->ind_tbl);
13157 rte_spinlock_lock(&shared_rss->action_rss_sl);
13158 queue_old = shared_rss->ind_tbl->queues;
13159 ret = mlx5_ind_table_obj_modify(dev, shared_rss->ind_tbl,
13160 queue, action_conf->queue_num, true);
13163 ret = rte_flow_error_set(error, rte_errno,
13164 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
13165 "cannot update indirection table");
13167 mlx5_free(queue_old);
13168 shared_rss->origin.queue = queue;
13169 shared_rss->origin.queue_num = action_conf->queue_num;
13171 rte_spinlock_unlock(&shared_rss->action_rss_sl);
13176 * Updates in place shared action configuration, lock free,
13177 * (mutex should be acquired by caller).
13180 * Pointer to the Ethernet device structure.
13181 * @param[in] handle
13182 * The indirect action object handle to be updated.
13183 * @param[in] update
13184 * Action specification used to modify the action pointed by *handle*.
13185 * *update* could be of same type with the action pointed by the *handle*
13186 * handle argument, or some other structures like a wrapper, depending on
13187 * the indirect action type.
13188 * @param[out] error
13189 * Perform verbose error reporting if not NULL. Initialized in case of
13193 * 0 on success, otherwise negative errno value.
13196 flow_dv_action_update(struct rte_eth_dev *dev,
13197 struct rte_flow_action_handle *handle,
13198 const void *update,
13199 struct rte_flow_error *err)
13201 uint32_t act_idx = (uint32_t)(uintptr_t)handle;
13202 uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
13203 uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
13204 const void *action_conf;
13207 case MLX5_INDIRECT_ACTION_TYPE_RSS:
13208 action_conf = ((const struct rte_flow_action *)update)->conf;
13209 return __flow_dv_action_rss_update(dev, idx, action_conf, err);
13211 return rte_flow_error_set(err, ENOTSUP,
13212 RTE_FLOW_ERROR_TYPE_ACTION,
13214 "action type update not supported");
13219 flow_dv_action_query(struct rte_eth_dev *dev,
13220 const struct rte_flow_action_handle *handle, void *data,
13221 struct rte_flow_error *error)
13223 struct mlx5_age_param *age_param;
13224 struct rte_flow_query_age *resp;
13225 uint32_t act_idx = (uint32_t)(uintptr_t)handle;
13226 uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
13227 uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
13230 case MLX5_INDIRECT_ACTION_TYPE_AGE:
13231 age_param = &flow_aso_age_get_by_idx(dev, idx)->age_params;
13233 resp->aged = __atomic_load_n(&age_param->state,
13234 __ATOMIC_RELAXED) == AGE_TMOUT ?
13236 resp->sec_since_last_hit_valid = !resp->aged;
13237 if (resp->sec_since_last_hit_valid)
13238 resp->sec_since_last_hit = __atomic_load_n
13239 (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
13242 return rte_flow_error_set(error, ENOTSUP,
13243 RTE_FLOW_ERROR_TYPE_ACTION,
13245 "action type query not supported");
13250 * Query a dv flow rule for its statistics via devx.
13253 * Pointer to Ethernet device.
13255 * Pointer to the sub flow.
13257 * data retrieved by the query.
13258 * @param[out] error
13259 * Perform verbose error reporting if not NULL.
13262 * 0 on success, a negative errno value otherwise and rte_errno is set.
13265 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
13266 void *data, struct rte_flow_error *error)
13268 struct mlx5_priv *priv = dev->data->dev_private;
13269 struct rte_flow_query_count *qc = data;
13271 if (!priv->config.devx)
13272 return rte_flow_error_set(error, ENOTSUP,
13273 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13275 "counters are not supported");
13276 if (flow->counter) {
13277 uint64_t pkts, bytes;
13278 struct mlx5_flow_counter *cnt;
13280 cnt = flow_dv_counter_get_by_idx(dev, flow->counter,
13282 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
13286 return rte_flow_error_set(error, -err,
13287 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13288 NULL, "cannot read counters");
13291 qc->hits = pkts - cnt->hits;
13292 qc->bytes = bytes - cnt->bytes;
13295 cnt->bytes = bytes;
13299 return rte_flow_error_set(error, EINVAL,
13300 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13302 "counters are not available");
13306 * Query a flow rule AGE action for aging information.
13309 * Pointer to Ethernet device.
13311 * Pointer to the sub flow.
13313 * data retrieved by the query.
13314 * @param[out] error
13315 * Perform verbose error reporting if not NULL.
13318 * 0 on success, a negative errno value otherwise and rte_errno is set.
13321 flow_dv_query_age(struct rte_eth_dev *dev, struct rte_flow *flow,
13322 void *data, struct rte_flow_error *error)
13324 struct rte_flow_query_age *resp = data;
13325 struct mlx5_age_param *age_param;
13328 struct mlx5_aso_age_action *act =
13329 flow_aso_age_get_by_idx(dev, flow->age);
13331 age_param = &act->age_params;
13332 } else if (flow->counter) {
13333 age_param = flow_dv_counter_idx_get_age(dev, flow->counter);
13335 if (!age_param || !age_param->timeout)
13336 return rte_flow_error_set
13338 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13339 NULL, "cannot read age data");
13341 return rte_flow_error_set(error, EINVAL,
13342 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13343 NULL, "age data not available");
13345 resp->aged = __atomic_load_n(&age_param->state, __ATOMIC_RELAXED) ==
13347 resp->sec_since_last_hit_valid = !resp->aged;
13348 if (resp->sec_since_last_hit_valid)
13349 resp->sec_since_last_hit = __atomic_load_n
13350 (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
13357 * @see rte_flow_query()
13358 * @see rte_flow_ops
13361 flow_dv_query(struct rte_eth_dev *dev,
13362 struct rte_flow *flow __rte_unused,
13363 const struct rte_flow_action *actions __rte_unused,
13364 void *data __rte_unused,
13365 struct rte_flow_error *error __rte_unused)
13369 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
13370 switch (actions->type) {
13371 case RTE_FLOW_ACTION_TYPE_VOID:
13373 case RTE_FLOW_ACTION_TYPE_COUNT:
13374 ret = flow_dv_query_count(dev, flow, data, error);
13376 case RTE_FLOW_ACTION_TYPE_AGE:
13377 ret = flow_dv_query_age(dev, flow, data, error);
13380 return rte_flow_error_set(error, ENOTSUP,
13381 RTE_FLOW_ERROR_TYPE_ACTION,
13383 "action not supported");
13390 * Destroy the meter table set.
13391 * Lock free, (mutex should be acquired by caller).
13394 * Pointer to Ethernet device.
13396 * Pointer to the meter table set.
13402 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
13403 struct mlx5_meter_domains_infos *tbl)
13405 struct mlx5_priv *priv = dev->data->dev_private;
13406 struct mlx5_meter_domains_infos *mtd =
13407 (struct mlx5_meter_domains_infos *)tbl;
13409 if (!mtd || !priv->config.dv_flow_en)
13411 if (mtd->egress.tbl)
13412 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->egress.tbl);
13413 if (mtd->egress.sfx_tbl)
13414 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->egress.sfx_tbl);
13415 if (mtd->ingress.tbl)
13416 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->ingress.tbl);
13417 if (mtd->ingress.sfx_tbl)
13418 flow_dv_tbl_resource_release(MLX5_SH(dev),
13419 mtd->ingress.sfx_tbl);
13420 if (mtd->transfer.tbl)
13421 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->transfer.tbl);
13422 if (mtd->transfer.sfx_tbl)
13423 flow_dv_tbl_resource_release(MLX5_SH(dev),
13424 mtd->transfer.sfx_tbl);
13429 /* Number of meter flow actions, count and jump or count and drop. */
13430 #define METER_ACTIONS 2
13433 * Create specify domain meter table and suffix table.
13436 * Pointer to Ethernet device.
13437 * @param[in,out] mtb
13438 * Pointer to DV meter table set.
13439 * @param[in] egress
13441 * @param[in] transfer
13445 * 0 on success, -1 otherwise.
13448 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
13449 struct mlx5_meter_domains_infos *mtb,
13450 uint8_t egress, uint8_t transfer)
13452 struct rte_flow_error error;
13453 struct mlx5_meter_domain_info *dtb;
13456 dtb = &mtb->transfer;
13458 dtb = &mtb->egress;
13460 dtb = &mtb->ingress;
13461 /* Create the meter table with METER level. */
13462 dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
13463 egress, transfer, false, NULL, 0,
13466 DRV_LOG(ERR, "Failed to create meter policer table.");
13469 /* Create the meter suffix table with SUFFIX level. */
13470 dtb->sfx_tbl = flow_dv_tbl_resource_get(dev,
13471 MLX5_FLOW_TABLE_LEVEL_SUFFIX,
13472 egress, transfer, false, NULL, 0,
13474 if (!dtb->sfx_tbl) {
13475 DRV_LOG(ERR, "Failed to create meter suffix table.");
13482 * Create the needed meter and suffix tables.
13483 * Lock free, (mutex should be acquired by caller).
13486 * Pointer to Ethernet device.
13489 * Pointer to table set on success, NULL otherwise and rte_errno is set.
13491 static struct mlx5_meter_domains_infos *
13492 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev)
13494 struct mlx5_priv *priv = dev->data->dev_private;
13495 struct mlx5_meter_domains_infos *mtb;
13498 if (!priv->mtr_en) {
13499 rte_errno = ENOTSUP;
13502 mtb = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mtb), 0, SOCKET_ID_ANY);
13504 DRV_LOG(ERR, "Failed to allocate memory for meter.");
13507 /* Egress meter table. */
13508 ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0);
13510 DRV_LOG(ERR, "Failed to prepare egress meter table.");
13513 /* Ingress meter table. */
13514 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0);
13516 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
13519 /* FDB meter table. */
13520 if (priv->config.dv_esw_en) {
13521 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1);
13523 DRV_LOG(ERR, "Failed to prepare fdb meter table.");
13529 flow_dv_destroy_mtr_tbl(dev, mtb);
13534 * Destroy the meter table matchers.
13535 * Lock free, (mutex should be acquired by caller).
13538 * Pointer to Ethernet device.
13539 * @param[in,out] dtb
13540 * Pointer to DV meter table.
13546 flow_dv_destroy_mtr_matchers(struct rte_eth_dev *dev,
13547 struct mlx5_meter_domain_info *dtb)
13549 struct mlx5_priv *priv = dev->data->dev_private;
13550 struct mlx5_flow_tbl_data_entry *tbl;
13552 if (!priv->config.dv_flow_en)
13554 if (dtb->drop_matcher) {
13555 tbl = container_of(dtb->drop_matcher->tbl, typeof(*tbl), tbl);
13556 mlx5_cache_unregister(&tbl->matchers,
13557 &dtb->drop_matcher->entry);
13558 dtb->drop_matcher = NULL;
13560 if (dtb->color_matcher) {
13561 tbl = container_of(dtb->color_matcher->tbl, typeof(*tbl), tbl);
13562 mlx5_cache_unregister(&tbl->matchers,
13563 &dtb->color_matcher->entry);
13564 dtb->color_matcher = NULL;
13570 * Create the matchers for meter table.
13573 * Pointer to Ethernet device.
13574 * @param[in] color_reg_c_idx
13575 * Reg C index for color match.
13576 * @param[in] mtr_id_reg_c_idx
13577 * Reg C index for meter_id match.
13578 * @param[in] mtr_id_mask
13579 * Mask for meter_id match criteria.
13580 * @param[in,out] dtb
13581 * Pointer to DV meter table.
13582 * @param[out] error
13583 * Perform verbose error reporting if not NULL.
13586 * 0 on success, a negative errno value otherwise and rte_errno is set.
13589 flow_dv_prepare_mtr_matchers(struct rte_eth_dev *dev,
13590 uint32_t color_reg_c_idx,
13591 uint32_t mtr_id_reg_c_idx,
13592 uint32_t mtr_id_mask,
13593 struct mlx5_meter_domain_info *dtb,
13594 struct rte_flow_error *error)
13596 struct mlx5_priv *priv = dev->data->dev_private;
13597 struct mlx5_flow_tbl_data_entry *tbl_data;
13598 struct mlx5_cache_entry *entry;
13599 struct mlx5_flow_dv_matcher matcher = {
13601 .size = sizeof(matcher.mask.buf) -
13602 MLX5_ST_SZ_BYTES(fte_match_set_misc4),
13606 struct mlx5_flow_dv_match_params value = {
13607 .size = sizeof(value.buf) -
13608 MLX5_ST_SZ_BYTES(fte_match_set_misc4),
13610 struct mlx5_flow_cb_ctx ctx = {
13614 uint32_t color_mask = (UINT32_C(1) << MLX5_MTR_COLOR_BITS) - 1;
13616 tbl_data = container_of(dtb->tbl, struct mlx5_flow_tbl_data_entry, tbl);
13617 if (!dtb->drop_matcher) {
13618 /* Create matchers for Drop. */
13619 flow_dv_match_meta_reg(matcher.mask.buf, value.buf,
13620 mtr_id_reg_c_idx, 0, mtr_id_mask);
13621 matcher.priority = MLX5_REG_BITS * 2 - priv->max_mtr_bits;
13622 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
13623 matcher.mask.size);
13624 entry = mlx5_cache_register(&tbl_data->matchers, &ctx);
13626 DRV_LOG(ERR, "Failed to register meter drop matcher.");
13629 dtb->drop_matcher =
13630 container_of(entry, struct mlx5_flow_dv_matcher, entry);
13632 if (!dtb->color_matcher) {
13633 /* Create matchers for Color + meter_id. */
13634 if (priv->mtr_reg_share) {
13635 flow_dv_match_meta_reg(matcher.mask.buf, value.buf,
13636 color_reg_c_idx, 0,
13637 (mtr_id_mask | color_mask));
13639 flow_dv_match_meta_reg(matcher.mask.buf, value.buf,
13640 color_reg_c_idx, 0, color_mask);
13641 flow_dv_match_meta_reg(matcher.mask.buf, value.buf,
13642 mtr_id_reg_c_idx, 0, mtr_id_mask);
13644 matcher.priority = MLX5_REG_BITS - priv->max_mtr_bits;
13645 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
13646 matcher.mask.size);
13647 entry = mlx5_cache_register(&tbl_data->matchers, &ctx);
13649 DRV_LOG(ERR, "Failed to register meter color matcher.");
13652 dtb->color_matcher =
13653 container_of(entry, struct mlx5_flow_dv_matcher, entry);
13659 * Destroy domain policer rule.
13662 * Pointer to Ethernet device.
13664 * Pointer to domain table.
13667 flow_dv_destroy_domain_policer_rule(struct rte_eth_dev *dev,
13668 struct mlx5_meter_domain_info *dt)
13670 if (dt->drop_rule) {
13671 claim_zero(mlx5_flow_os_destroy_flow(dt->drop_rule));
13672 dt->drop_rule = NULL;
13674 if (dt->green_rule) {
13675 claim_zero(mlx5_flow_os_destroy_flow(dt->green_rule));
13676 dt->green_rule = NULL;
13678 flow_dv_destroy_mtr_matchers(dev, dt);
13679 if (dt->jump_actn) {
13680 claim_zero(mlx5_flow_os_destroy_flow_action(dt->jump_actn));
13681 dt->jump_actn = NULL;
13686 * Destroy policer rules.
13689 * Pointer to Ethernet device.
13691 * Pointer to flow meter structure.
13693 * Pointer to flow attributes.
13699 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev,
13700 const struct mlx5_flow_meter *fm,
13701 const struct rte_flow_attr *attr)
13703 struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
13708 flow_dv_destroy_domain_policer_rule(dev, &mtb->egress);
13710 flow_dv_destroy_domain_policer_rule(dev, &mtb->ingress);
13711 if (attr->transfer)
13712 flow_dv_destroy_domain_policer_rule(dev, &mtb->transfer);
13717 * Create specify domain meter policer rule.
13720 * Pointer to Ethernet device.
13722 * Pointer to flow meter structure.
13724 * Pointer to DV meter table set.
13725 * @param[out] drop_rule
13726 * The address of pointer saving drop rule.
13727 * @param[out] color_rule
13728 * The address of pointer saving green rule.
13731 * 0 on success, -1 otherwise.
13734 flow_dv_create_policer_forward_rule(struct rte_eth_dev *dev,
13735 struct mlx5_flow_meter *fm,
13736 struct mlx5_meter_domain_info *dtb,
13740 struct mlx5_priv *priv = dev->data->dev_private;
13741 struct mlx5_flow_dv_match_params matcher = {
13742 .size = sizeof(matcher.buf) -
13743 MLX5_ST_SZ_BYTES(fte_match_set_misc4),
13745 struct mlx5_flow_dv_match_params value = {
13746 .size = sizeof(value.buf) -
13747 MLX5_ST_SZ_BYTES(fte_match_set_misc4),
13749 struct mlx5_meter_domains_infos *mtb = fm->mfts;
13750 struct rte_flow_error error;
13751 uint32_t color_reg_c = mlx5_flow_get_reg_id(dev, MLX5_MTR_COLOR,
13753 uint32_t mtr_id_reg_c = mlx5_flow_get_reg_id(dev, MLX5_MTR_ID,
13755 uint8_t mtr_id_offset = priv->mtr_reg_share ? MLX5_MTR_COLOR_BITS : 0;
13756 uint32_t mtr_id_mask =
13757 ((UINT32_C(1) << priv->max_mtr_bits) - 1) << mtr_id_offset;
13758 void *actions[METER_ACTIONS];
13762 /* Create jump action. */
13763 if (!dtb->jump_actn)
13764 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
13765 (dtb->sfx_tbl->obj, &dtb->jump_actn);
13767 DRV_LOG(ERR, "Failed to create policer jump action.");
13770 /* Prepare matchers. */
13771 if (!dtb->drop_matcher || !dtb->color_matcher) {
13772 ret = flow_dv_prepare_mtr_matchers(dev, color_reg_c,
13773 mtr_id_reg_c, mtr_id_mask,
13776 DRV_LOG(ERR, "Failed to setup matchers for mtr table.");
13780 /* Create Drop flow, matching meter_id only. */
13782 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_id_reg_c,
13783 (fm->idx << mtr_id_offset), UINT32_MAX);
13784 if (mtb->drop_count)
13785 actions[i++] = mtb->drop_count;
13786 actions[i++] = priv->sh->dr_drop_action;
13787 ret = mlx5_flow_os_create_flow(dtb->drop_matcher->matcher_object,
13788 (void *)&value, i, actions, drop_rule);
13790 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
13793 /* Create flow matching Green color + meter_id. */
13795 if (priv->mtr_reg_share) {
13796 flow_dv_match_meta_reg(matcher.buf, value.buf, color_reg_c,
13797 ((fm->idx << mtr_id_offset) |
13798 rte_col_2_mlx5_col(RTE_COLOR_GREEN)),
13801 flow_dv_match_meta_reg(matcher.buf, value.buf, color_reg_c,
13802 rte_col_2_mlx5_col(RTE_COLOR_GREEN),
13804 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_id_reg_c,
13805 fm->idx, UINT32_MAX);
13807 if (mtb->green_count)
13808 actions[i++] = mtb->green_count;
13809 actions[i++] = dtb->jump_actn;
13810 ret = mlx5_flow_os_create_flow(dtb->color_matcher->matcher_object,
13811 (void *)&value, i, actions, green_rule);
13813 DRV_LOG(ERR, "Failed to create meter policer color rule.");
13823 * Prepare policer rules for all domains.
13824 * If meter already initialized, this will replace all old rules with new ones.
13827 * Pointer to Ethernet device.
13829 * Pointer to flow meter structure.
13831 * Pointer to flow attributes.
13834 * 0 on success, -1 otherwise.
13837 flow_dv_prepare_policer_rules(struct rte_eth_dev *dev,
13838 struct mlx5_flow_meter *fm,
13839 const struct rte_flow_attr *attr)
13841 struct mlx5_meter_domains_infos *mtb = fm->mfts;
13842 bool initialized = false;
13843 struct mlx5_flow_counter *cnt;
13844 void *egress_drop_rule = NULL;
13845 void *egress_green_rule = NULL;
13846 void *ingress_drop_rule = NULL;
13847 void *ingress_green_rule = NULL;
13848 void *transfer_drop_rule = NULL;
13849 void *transfer_green_rule = NULL;
13852 /* Get the statistics counters for green/drop. */
13853 if (fm->policer_stats.pass_cnt) {
13854 cnt = flow_dv_counter_get_by_idx(dev,
13855 fm->policer_stats.pass_cnt,
13857 mtb->green_count = cnt->action;
13859 mtb->green_count = NULL;
13861 if (fm->policer_stats.drop_cnt) {
13862 cnt = flow_dv_counter_get_by_idx(dev,
13863 fm->policer_stats.drop_cnt,
13865 mtb->drop_count = cnt->action;
13867 mtb->drop_count = NULL;
13870 * If flow meter has been initialized, all policer rules
13871 * are created. So can get if meter initialized by checking
13872 * any policer rule.
13874 if (mtb->egress.drop_rule)
13875 initialized = true;
13876 if (attr->egress) {
13877 ret = flow_dv_create_policer_forward_rule(dev,
13879 &egress_drop_rule, &egress_green_rule);
13881 DRV_LOG(ERR, "Failed to create egress policer.");
13885 if (attr->ingress) {
13886 ret = flow_dv_create_policer_forward_rule(dev,
13888 &ingress_drop_rule, &ingress_green_rule);
13890 DRV_LOG(ERR, "Failed to create ingress policer.");
13894 if (attr->transfer) {
13895 ret = flow_dv_create_policer_forward_rule(dev,
13896 fm, &mtb->transfer,
13897 &transfer_drop_rule, &transfer_green_rule);
13899 DRV_LOG(ERR, "Failed to create transfer policer.");
13903 /* Replace old flows if existing. */
13904 if (mtb->egress.drop_rule)
13905 claim_zero(mlx5_flow_os_destroy_flow(mtb->egress.drop_rule));
13906 if (mtb->egress.green_rule)
13907 claim_zero(mlx5_flow_os_destroy_flow(mtb->egress.green_rule));
13908 if (mtb->ingress.drop_rule)
13909 claim_zero(mlx5_flow_os_destroy_flow(mtb->ingress.drop_rule));
13910 if (mtb->ingress.green_rule)
13911 claim_zero(mlx5_flow_os_destroy_flow(mtb->ingress.green_rule));
13912 if (mtb->transfer.drop_rule)
13913 claim_zero(mlx5_flow_os_destroy_flow(mtb->transfer.drop_rule));
13914 if (mtb->transfer.green_rule)
13915 claim_zero(mlx5_flow_os_destroy_flow(mtb->transfer.green_rule));
13916 mtb->egress.drop_rule = egress_drop_rule;
13917 mtb->egress.green_rule = egress_green_rule;
13918 mtb->ingress.drop_rule = ingress_drop_rule;
13919 mtb->ingress.green_rule = ingress_green_rule;
13920 mtb->transfer.drop_rule = transfer_drop_rule;
13921 mtb->transfer.green_rule = transfer_green_rule;
13924 if (egress_drop_rule)
13925 claim_zero(mlx5_flow_os_destroy_flow(egress_drop_rule));
13926 if (egress_green_rule)
13927 claim_zero(mlx5_flow_os_destroy_flow(egress_green_rule));
13928 if (ingress_drop_rule)
13929 claim_zero(mlx5_flow_os_destroy_flow(ingress_drop_rule));
13930 if (ingress_green_rule)
13931 claim_zero(mlx5_flow_os_destroy_flow(ingress_green_rule));
13932 if (transfer_drop_rule)
13933 claim_zero(mlx5_flow_os_destroy_flow(transfer_drop_rule));
13934 if (transfer_green_rule)
13935 claim_zero(mlx5_flow_os_destroy_flow(transfer_green_rule));
13937 flow_dv_destroy_policer_rules(dev, fm, attr);
13942 * Validate the batch counter support in root table.
13944 * Create a simple flow with invalid counter and drop action on root table to
13945 * validate if batch counter with offset on root table is supported or not.
13948 * Pointer to rte_eth_dev structure.
13951 * 0 on success, a negative errno value otherwise and rte_errno is set.
13954 mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev)
13956 struct mlx5_priv *priv = dev->data->dev_private;
13957 struct mlx5_dev_ctx_shared *sh = priv->sh;
13958 struct mlx5_flow_dv_match_params mask = {
13959 .size = sizeof(mask.buf),
13961 struct mlx5_flow_dv_match_params value = {
13962 .size = sizeof(value.buf),
13964 struct mlx5dv_flow_matcher_attr dv_attr = {
13965 .type = IBV_FLOW_ATTR_NORMAL,
13967 .match_criteria_enable = 0,
13968 .match_mask = (void *)&mask,
13970 void *actions[2] = { 0 };
13971 struct mlx5_flow_tbl_resource *tbl = NULL;
13972 struct mlx5_devx_obj *dcs = NULL;
13973 void *matcher = NULL;
13977 tbl = flow_dv_tbl_resource_get(dev, 0, 0, 0, false, NULL, 0, 0, NULL);
13980 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
13983 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, UINT16_MAX,
13987 actions[1] = sh->dr_drop_action ? sh->dr_drop_action :
13988 priv->drop_queue.hrxq->action;
13989 dv_attr.match_criteria_enable = flow_dv_matcher_enable(mask.buf);
13990 ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj,
13994 ret = mlx5_flow_os_create_flow(matcher, (void *)&value, 2,
13998 * If batch counter with offset is not supported, the driver will not
13999 * validate the invalid offset value, flow create should success.
14000 * In this case, it means batch counter is not supported in root table.
14002 * Otherwise, if flow create is failed, counter offset is supported.
14005 DRV_LOG(INFO, "Batch counter is not supported in root "
14006 "table. Switch to fallback mode.");
14007 rte_errno = ENOTSUP;
14009 claim_zero(mlx5_flow_os_destroy_flow(flow));
14011 /* Check matcher to make sure validate fail at flow create. */
14012 if (!matcher || (matcher && errno != EINVAL))
14013 DRV_LOG(ERR, "Unexpected error in counter offset "
14014 "support detection");
14018 claim_zero(mlx5_flow_os_destroy_flow_action(actions[0]));
14020 claim_zero(mlx5_flow_os_destroy_flow_matcher(matcher));
14022 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
14024 claim_zero(mlx5_devx_cmd_destroy(dcs));
14029 * Query a devx counter.
14032 * Pointer to the Ethernet device structure.
14034 * Index to the flow counter.
14036 * Set to clear the counter statistics.
14038 * The statistics value of packets.
14039 * @param[out] bytes
14040 * The statistics value of bytes.
14043 * 0 on success, otherwise return -1.
14046 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
14047 uint64_t *pkts, uint64_t *bytes)
14049 struct mlx5_priv *priv = dev->data->dev_private;
14050 struct mlx5_flow_counter *cnt;
14051 uint64_t inn_pkts, inn_bytes;
14054 if (!priv->config.devx)
14057 ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
14060 cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
14061 *pkts = inn_pkts - cnt->hits;
14062 *bytes = inn_bytes - cnt->bytes;
14064 cnt->hits = inn_pkts;
14065 cnt->bytes = inn_bytes;
14071 * Get aged-out flows.
14074 * Pointer to the Ethernet device structure.
14075 * @param[in] context
14076 * The address of an array of pointers to the aged-out flows contexts.
14077 * @param[in] nb_contexts
14078 * The length of context array pointers.
14079 * @param[out] error
14080 * Perform verbose error reporting if not NULL. Initialized in case of
14084 * how many contexts get in success, otherwise negative errno value.
14085 * if nb_contexts is 0, return the amount of all aged contexts.
14086 * if nb_contexts is not 0 , return the amount of aged flows reported
14087 * in the context array.
14088 * @note: only stub for now
14091 flow_get_aged_flows(struct rte_eth_dev *dev,
14093 uint32_t nb_contexts,
14094 struct rte_flow_error *error)
14096 struct mlx5_priv *priv = dev->data->dev_private;
14097 struct mlx5_age_info *age_info;
14098 struct mlx5_age_param *age_param;
14099 struct mlx5_flow_counter *counter;
14100 struct mlx5_aso_age_action *act;
14103 if (nb_contexts && !context)
14104 return rte_flow_error_set(error, EINVAL,
14105 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
14106 NULL, "empty context");
14107 age_info = GET_PORT_AGE_INFO(priv);
14108 rte_spinlock_lock(&age_info->aged_sl);
14109 LIST_FOREACH(act, &age_info->aged_aso, next) {
14112 context[nb_flows - 1] =
14113 act->age_params.context;
14114 if (!(--nb_contexts))
14118 TAILQ_FOREACH(counter, &age_info->aged_counters, next) {
14121 age_param = MLX5_CNT_TO_AGE(counter);
14122 context[nb_flows - 1] = age_param->context;
14123 if (!(--nb_contexts))
14127 rte_spinlock_unlock(&age_info->aged_sl);
14128 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
14133 * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
14136 flow_dv_counter_allocate(struct rte_eth_dev *dev)
14138 return flow_dv_counter_alloc(dev, 0);
14142 * Validate indirect action.
14143 * Dispatcher for action type specific validation.
14146 * Pointer to the Ethernet device structure.
14148 * Shared action configuration.
14149 * @param[in] action
14150 * The indirect action object to validate.
14151 * @param[out] error
14152 * Perform verbose error reporting if not NULL. Initialized in case of
14156 * 0 on success, otherwise negative errno value.
14159 flow_dv_action_validate(struct rte_eth_dev *dev,
14160 const struct rte_flow_indir_action_conf *conf,
14161 const struct rte_flow_action *action,
14162 struct rte_flow_error *err)
14164 struct mlx5_priv *priv = dev->data->dev_private;
14166 RTE_SET_USED(conf);
14167 switch (action->type) {
14168 case RTE_FLOW_ACTION_TYPE_RSS:
14170 * priv->obj_ops is set according to driver capabilities.
14171 * When DevX capabilities are
14172 * sufficient, it is set to devx_obj_ops.
14173 * Otherwise, it is set to ibv_obj_ops.
14174 * ibv_obj_ops doesn't support ind_table_modify operation.
14175 * In this case the shared RSS action can't be used.
14177 if (priv->obj_ops.ind_table_modify == NULL)
14178 return rte_flow_error_set
14180 RTE_FLOW_ERROR_TYPE_ACTION,
14182 "shared RSS action not supported");
14183 return mlx5_validate_action_rss(dev, action, err);
14184 case RTE_FLOW_ACTION_TYPE_AGE:
14185 if (!priv->sh->aso_age_mng)
14186 return rte_flow_error_set(err, ENOTSUP,
14187 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
14189 "shared age action not supported");
14190 return flow_dv_validate_action_age(0, action, dev, err);
14192 return rte_flow_error_set(err, ENOTSUP,
14193 RTE_FLOW_ERROR_TYPE_ACTION,
14195 "action type not supported");
14200 flow_dv_sync_domain(struct rte_eth_dev *dev, uint32_t domains, uint32_t flags)
14202 struct mlx5_priv *priv = dev->data->dev_private;
14205 if ((domains & MLX5_DOMAIN_BIT_NIC_RX) && priv->sh->rx_domain != NULL) {
14206 ret = mlx5_os_flow_dr_sync_domain(priv->sh->rx_domain,
14211 if ((domains & MLX5_DOMAIN_BIT_NIC_TX) && priv->sh->tx_domain != NULL) {
14212 ret = mlx5_os_flow_dr_sync_domain(priv->sh->tx_domain, flags);
14216 if ((domains & MLX5_DOMAIN_BIT_FDB) && priv->sh->fdb_domain != NULL) {
14217 ret = mlx5_os_flow_dr_sync_domain(priv->sh->fdb_domain, flags);
14224 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
14225 .validate = flow_dv_validate,
14226 .prepare = flow_dv_prepare,
14227 .translate = flow_dv_translate,
14228 .apply = flow_dv_apply,
14229 .remove = flow_dv_remove,
14230 .destroy = flow_dv_destroy,
14231 .query = flow_dv_query,
14232 .create_mtr_tbls = flow_dv_create_mtr_tbl,
14233 .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
14234 .prepare_policer_rules = flow_dv_prepare_policer_rules,
14235 .destroy_policer_rules = flow_dv_destroy_policer_rules,
14236 .counter_alloc = flow_dv_counter_allocate,
14237 .counter_free = flow_dv_counter_free,
14238 .counter_query = flow_dv_counter_query,
14239 .get_aged_flows = flow_get_aged_flows,
14240 .action_validate = flow_dv_action_validate,
14241 .action_create = flow_dv_action_create,
14242 .action_destroy = flow_dv_action_destroy,
14243 .action_update = flow_dv_action_update,
14244 .action_query = flow_dv_action_query,
14245 .sync_domain = flow_dv_sync_domain,
14248 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */