1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
14 #pragma GCC diagnostic ignored "-Wpedantic"
16 #include <infiniband/verbs.h>
18 #pragma GCC diagnostic error "-Wpedantic"
21 #include <rte_common.h>
22 #include <rte_ether.h>
23 #include <rte_ethdev_driver.h>
25 #include <rte_flow_driver.h>
26 #include <rte_malloc.h>
27 #include <rte_cycles.h>
30 #include <rte_vxlan.h>
33 #include <mlx5_glue.h>
34 #include <mlx5_devx_cmds.h>
37 #include "mlx5_defs.h"
39 #include "mlx5_flow.h"
40 #include "mlx5_rxtx.h"
42 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
44 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
45 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
48 #ifndef HAVE_MLX5DV_DR_ESWITCH
49 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
50 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
54 #ifndef HAVE_MLX5DV_DR
55 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
58 /* VLAN header definitions */
59 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
60 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
61 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
62 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
63 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
78 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
79 struct mlx5_flow_tbl_resource *tbl);
82 * Initialize flow attributes structure according to flow items' types.
84 * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
85 * mode. For tunnel mode, the items to be modified are the outermost ones.
88 * Pointer to item specification.
90 * Pointer to flow attributes structure.
92 * Pointer to the sub flow.
93 * @param[in] tunnel_decap
94 * Whether action is after tunnel decapsulation.
97 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
98 struct mlx5_flow *dev_flow, bool tunnel_decap)
100 uint64_t layers = dev_flow->handle->layers;
103 * If layers is already initialized, it means this dev_flow is the
104 * suffix flow, the layers flags is set by the prefix flow. Need to
105 * use the layer flags from prefix flow as the suffix flow may not
106 * have the user defined items as the flow is split.
109 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
111 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
113 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
115 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
120 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
121 uint8_t next_protocol = 0xff;
122 switch (item->type) {
123 case RTE_FLOW_ITEM_TYPE_GRE:
124 case RTE_FLOW_ITEM_TYPE_NVGRE:
125 case RTE_FLOW_ITEM_TYPE_VXLAN:
126 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
127 case RTE_FLOW_ITEM_TYPE_GENEVE:
128 case RTE_FLOW_ITEM_TYPE_MPLS:
132 case RTE_FLOW_ITEM_TYPE_IPV4:
135 if (item->mask != NULL &&
136 ((const struct rte_flow_item_ipv4 *)
137 item->mask)->hdr.next_proto_id)
139 ((const struct rte_flow_item_ipv4 *)
140 (item->spec))->hdr.next_proto_id &
141 ((const struct rte_flow_item_ipv4 *)
142 (item->mask))->hdr.next_proto_id;
143 if ((next_protocol == IPPROTO_IPIP ||
144 next_protocol == IPPROTO_IPV6) && tunnel_decap)
147 case RTE_FLOW_ITEM_TYPE_IPV6:
150 if (item->mask != NULL &&
151 ((const struct rte_flow_item_ipv6 *)
152 item->mask)->hdr.proto)
154 ((const struct rte_flow_item_ipv6 *)
155 (item->spec))->hdr.proto &
156 ((const struct rte_flow_item_ipv6 *)
157 (item->mask))->hdr.proto;
158 if ((next_protocol == IPPROTO_IPIP ||
159 next_protocol == IPPROTO_IPV6) && tunnel_decap)
162 case RTE_FLOW_ITEM_TYPE_UDP:
166 case RTE_FLOW_ITEM_TYPE_TCP:
178 * Convert rte_mtr_color to mlx5 color.
187 rte_col_2_mlx5_col(enum rte_color rcol)
190 case RTE_COLOR_GREEN:
191 return MLX5_FLOW_COLOR_GREEN;
192 case RTE_COLOR_YELLOW:
193 return MLX5_FLOW_COLOR_YELLOW;
195 return MLX5_FLOW_COLOR_RED;
199 return MLX5_FLOW_COLOR_UNDEFINED;
202 struct field_modify_info {
203 uint32_t size; /* Size of field in protocol header, in bytes. */
204 uint32_t offset; /* Offset of field in protocol header, in bytes. */
205 enum mlx5_modification_field id;
208 struct field_modify_info modify_eth[] = {
209 {4, 0, MLX5_MODI_OUT_DMAC_47_16},
210 {2, 4, MLX5_MODI_OUT_DMAC_15_0},
211 {4, 6, MLX5_MODI_OUT_SMAC_47_16},
212 {2, 10, MLX5_MODI_OUT_SMAC_15_0},
216 struct field_modify_info modify_vlan_out_first_vid[] = {
217 /* Size in bits !!! */
218 {12, 0, MLX5_MODI_OUT_FIRST_VID},
222 struct field_modify_info modify_ipv4[] = {
223 {1, 1, MLX5_MODI_OUT_IP_DSCP},
224 {1, 8, MLX5_MODI_OUT_IPV4_TTL},
225 {4, 12, MLX5_MODI_OUT_SIPV4},
226 {4, 16, MLX5_MODI_OUT_DIPV4},
230 struct field_modify_info modify_ipv6[] = {
231 {1, 0, MLX5_MODI_OUT_IP_DSCP},
232 {1, 7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
233 {4, 8, MLX5_MODI_OUT_SIPV6_127_96},
234 {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
235 {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
236 {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
237 {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
238 {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
239 {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
240 {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
244 struct field_modify_info modify_udp[] = {
245 {2, 0, MLX5_MODI_OUT_UDP_SPORT},
246 {2, 2, MLX5_MODI_OUT_UDP_DPORT},
250 struct field_modify_info modify_tcp[] = {
251 {2, 0, MLX5_MODI_OUT_TCP_SPORT},
252 {2, 2, MLX5_MODI_OUT_TCP_DPORT},
253 {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
254 {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
259 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
260 uint8_t next_protocol, uint64_t *item_flags,
263 MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
264 item->type == RTE_FLOW_ITEM_TYPE_IPV6);
265 if (next_protocol == IPPROTO_IPIP) {
266 *item_flags |= MLX5_FLOW_LAYER_IPIP;
269 if (next_protocol == IPPROTO_IPV6) {
270 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
276 * Acquire the synchronizing object to protect multithreaded access
277 * to shared dv context. Lock occurs only if context is actually
278 * shared, i.e. we have multiport IB device and representors are
282 * Pointer to the rte_eth_dev structure.
285 flow_dv_shared_lock(struct rte_eth_dev *dev)
287 struct mlx5_priv *priv = dev->data->dev_private;
288 struct mlx5_ibv_shared *sh = priv->sh;
290 if (sh->dv_refcnt > 1) {
293 ret = pthread_mutex_lock(&sh->dv_mutex);
300 flow_dv_shared_unlock(struct rte_eth_dev *dev)
302 struct mlx5_priv *priv = dev->data->dev_private;
303 struct mlx5_ibv_shared *sh = priv->sh;
305 if (sh->dv_refcnt > 1) {
308 ret = pthread_mutex_unlock(&sh->dv_mutex);
314 /* Update VLAN's VID/PCP based on input rte_flow_action.
317 * Pointer to struct rte_flow_action.
319 * Pointer to struct rte_vlan_hdr.
322 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
323 struct rte_vlan_hdr *vlan)
326 if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
328 ((const struct rte_flow_action_of_set_vlan_pcp *)
329 action->conf)->vlan_pcp;
330 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
331 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
332 vlan->vlan_tci |= vlan_tci;
333 } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
334 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
335 vlan->vlan_tci |= rte_be_to_cpu_16
336 (((const struct rte_flow_action_of_set_vlan_vid *)
337 action->conf)->vlan_vid);
342 * Fetch 1, 2, 3 or 4 byte field from the byte array
343 * and return as unsigned integer in host-endian format.
346 * Pointer to data array.
348 * Size of field to extract.
351 * converted field in host endian format.
353 static inline uint32_t
354 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
363 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
366 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
367 ret = (ret << 8) | *(data + sizeof(uint16_t));
370 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
381 * Convert modify-header action to DV specification.
383 * Data length of each action is determined by provided field description
384 * and the item mask. Data bit offset and width of each action is determined
385 * by provided item mask.
388 * Pointer to item specification.
390 * Pointer to field modification information.
391 * For MLX5_MODIFICATION_TYPE_SET specifies destination field.
392 * For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
393 * For MLX5_MODIFICATION_TYPE_COPY specifies source field.
395 * Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
396 * Negative offset value sets the same offset as source offset.
397 * size field is ignored, value is taken from source field.
398 * @param[in,out] resource
399 * Pointer to the modify-header resource.
401 * Type of modification.
403 * Pointer to the error structure.
406 * 0 on success, a negative errno value otherwise and rte_errno is set.
409 flow_dv_convert_modify_action(struct rte_flow_item *item,
410 struct field_modify_info *field,
411 struct field_modify_info *dcopy,
412 struct mlx5_flow_dv_modify_hdr_resource *resource,
413 uint32_t type, struct rte_flow_error *error)
415 uint32_t i = resource->actions_num;
416 struct mlx5_modification_cmd *actions = resource->actions;
419 * The item and mask are provided in big-endian format.
420 * The fields should be presented as in big-endian format either.
421 * Mask must be always present, it defines the actual field width.
423 MLX5_ASSERT(item->mask);
424 MLX5_ASSERT(field->size);
431 if (i >= MLX5_MAX_MODIFY_NUM)
432 return rte_flow_error_set(error, EINVAL,
433 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
434 "too many items to modify");
435 /* Fetch variable byte size mask from the array. */
436 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
437 field->offset, field->size);
442 /* Deduce actual data width in bits from mask value. */
443 off_b = rte_bsf32(mask);
444 size_b = sizeof(uint32_t) * CHAR_BIT -
445 off_b - __builtin_clz(mask);
447 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
448 actions[i] = (struct mlx5_modification_cmd) {
454 /* Convert entire record to expected big-endian format. */
455 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
456 if (type == MLX5_MODIFICATION_TYPE_COPY) {
458 actions[i].dst_field = dcopy->id;
459 actions[i].dst_offset =
460 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
461 /* Convert entire record to big-endian format. */
462 actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
464 MLX5_ASSERT(item->spec);
465 data = flow_dv_fetch_field((const uint8_t *)item->spec +
466 field->offset, field->size);
467 /* Shift out the trailing masked bits from data. */
468 data = (data & mask) >> off_b;
469 actions[i].data1 = rte_cpu_to_be_32(data);
473 } while (field->size);
474 if (resource->actions_num == i)
475 return rte_flow_error_set(error, EINVAL,
476 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
477 "invalid modification flow item");
478 resource->actions_num = i;
483 * Convert modify-header set IPv4 address action to DV specification.
485 * @param[in,out] resource
486 * Pointer to the modify-header resource.
488 * Pointer to action specification.
490 * Pointer to the error structure.
493 * 0 on success, a negative errno value otherwise and rte_errno is set.
496 flow_dv_convert_action_modify_ipv4
497 (struct mlx5_flow_dv_modify_hdr_resource *resource,
498 const struct rte_flow_action *action,
499 struct rte_flow_error *error)
501 const struct rte_flow_action_set_ipv4 *conf =
502 (const struct rte_flow_action_set_ipv4 *)(action->conf);
503 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
504 struct rte_flow_item_ipv4 ipv4;
505 struct rte_flow_item_ipv4 ipv4_mask;
507 memset(&ipv4, 0, sizeof(ipv4));
508 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
509 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
510 ipv4.hdr.src_addr = conf->ipv4_addr;
511 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
513 ipv4.hdr.dst_addr = conf->ipv4_addr;
514 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
517 item.mask = &ipv4_mask;
518 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
519 MLX5_MODIFICATION_TYPE_SET, error);
523 * Convert modify-header set IPv6 address action to DV specification.
525 * @param[in,out] resource
526 * Pointer to the modify-header resource.
528 * Pointer to action specification.
530 * Pointer to the error structure.
533 * 0 on success, a negative errno value otherwise and rte_errno is set.
536 flow_dv_convert_action_modify_ipv6
537 (struct mlx5_flow_dv_modify_hdr_resource *resource,
538 const struct rte_flow_action *action,
539 struct rte_flow_error *error)
541 const struct rte_flow_action_set_ipv6 *conf =
542 (const struct rte_flow_action_set_ipv6 *)(action->conf);
543 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
544 struct rte_flow_item_ipv6 ipv6;
545 struct rte_flow_item_ipv6 ipv6_mask;
547 memset(&ipv6, 0, sizeof(ipv6));
548 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
549 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
550 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
551 sizeof(ipv6.hdr.src_addr));
552 memcpy(&ipv6_mask.hdr.src_addr,
553 &rte_flow_item_ipv6_mask.hdr.src_addr,
554 sizeof(ipv6.hdr.src_addr));
556 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
557 sizeof(ipv6.hdr.dst_addr));
558 memcpy(&ipv6_mask.hdr.dst_addr,
559 &rte_flow_item_ipv6_mask.hdr.dst_addr,
560 sizeof(ipv6.hdr.dst_addr));
563 item.mask = &ipv6_mask;
564 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
565 MLX5_MODIFICATION_TYPE_SET, error);
569 * Convert modify-header set MAC address action to DV specification.
571 * @param[in,out] resource
572 * Pointer to the modify-header resource.
574 * Pointer to action specification.
576 * Pointer to the error structure.
579 * 0 on success, a negative errno value otherwise and rte_errno is set.
582 flow_dv_convert_action_modify_mac
583 (struct mlx5_flow_dv_modify_hdr_resource *resource,
584 const struct rte_flow_action *action,
585 struct rte_flow_error *error)
587 const struct rte_flow_action_set_mac *conf =
588 (const struct rte_flow_action_set_mac *)(action->conf);
589 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
590 struct rte_flow_item_eth eth;
591 struct rte_flow_item_eth eth_mask;
593 memset(ð, 0, sizeof(eth));
594 memset(ð_mask, 0, sizeof(eth_mask));
595 if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
596 memcpy(ð.src.addr_bytes, &conf->mac_addr,
597 sizeof(eth.src.addr_bytes));
598 memcpy(ð_mask.src.addr_bytes,
599 &rte_flow_item_eth_mask.src.addr_bytes,
600 sizeof(eth_mask.src.addr_bytes));
602 memcpy(ð.dst.addr_bytes, &conf->mac_addr,
603 sizeof(eth.dst.addr_bytes));
604 memcpy(ð_mask.dst.addr_bytes,
605 &rte_flow_item_eth_mask.dst.addr_bytes,
606 sizeof(eth_mask.dst.addr_bytes));
609 item.mask = ð_mask;
610 return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
611 MLX5_MODIFICATION_TYPE_SET, error);
615 * Convert modify-header set VLAN VID action to DV specification.
617 * @param[in,out] resource
618 * Pointer to the modify-header resource.
620 * Pointer to action specification.
622 * Pointer to the error structure.
625 * 0 on success, a negative errno value otherwise and rte_errno is set.
628 flow_dv_convert_action_modify_vlan_vid
629 (struct mlx5_flow_dv_modify_hdr_resource *resource,
630 const struct rte_flow_action *action,
631 struct rte_flow_error *error)
633 const struct rte_flow_action_of_set_vlan_vid *conf =
634 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
635 int i = resource->actions_num;
636 struct mlx5_modification_cmd *actions = resource->actions;
637 struct field_modify_info *field = modify_vlan_out_first_vid;
639 if (i >= MLX5_MAX_MODIFY_NUM)
640 return rte_flow_error_set(error, EINVAL,
641 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
642 "too many items to modify");
643 actions[i] = (struct mlx5_modification_cmd) {
644 .action_type = MLX5_MODIFICATION_TYPE_SET,
646 .length = field->size,
647 .offset = field->offset,
649 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
650 actions[i].data1 = conf->vlan_vid;
651 actions[i].data1 = actions[i].data1 << 16;
652 resource->actions_num = ++i;
657 * Convert modify-header set TP action to DV specification.
659 * @param[in,out] resource
660 * Pointer to the modify-header resource.
662 * Pointer to action specification.
664 * Pointer to rte_flow_item objects list.
666 * Pointer to flow attributes structure.
667 * @param[in] dev_flow
668 * Pointer to the sub flow.
669 * @param[in] tunnel_decap
670 * Whether action is after tunnel decapsulation.
672 * Pointer to the error structure.
675 * 0 on success, a negative errno value otherwise and rte_errno is set.
678 flow_dv_convert_action_modify_tp
679 (struct mlx5_flow_dv_modify_hdr_resource *resource,
680 const struct rte_flow_action *action,
681 const struct rte_flow_item *items,
682 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
683 bool tunnel_decap, struct rte_flow_error *error)
685 const struct rte_flow_action_set_tp *conf =
686 (const struct rte_flow_action_set_tp *)(action->conf);
687 struct rte_flow_item item;
688 struct rte_flow_item_udp udp;
689 struct rte_flow_item_udp udp_mask;
690 struct rte_flow_item_tcp tcp;
691 struct rte_flow_item_tcp tcp_mask;
692 struct field_modify_info *field;
695 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
697 memset(&udp, 0, sizeof(udp));
698 memset(&udp_mask, 0, sizeof(udp_mask));
699 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
700 udp.hdr.src_port = conf->port;
701 udp_mask.hdr.src_port =
702 rte_flow_item_udp_mask.hdr.src_port;
704 udp.hdr.dst_port = conf->port;
705 udp_mask.hdr.dst_port =
706 rte_flow_item_udp_mask.hdr.dst_port;
708 item.type = RTE_FLOW_ITEM_TYPE_UDP;
710 item.mask = &udp_mask;
713 MLX5_ASSERT(attr->tcp);
714 memset(&tcp, 0, sizeof(tcp));
715 memset(&tcp_mask, 0, sizeof(tcp_mask));
716 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
717 tcp.hdr.src_port = conf->port;
718 tcp_mask.hdr.src_port =
719 rte_flow_item_tcp_mask.hdr.src_port;
721 tcp.hdr.dst_port = conf->port;
722 tcp_mask.hdr.dst_port =
723 rte_flow_item_tcp_mask.hdr.dst_port;
725 item.type = RTE_FLOW_ITEM_TYPE_TCP;
727 item.mask = &tcp_mask;
730 return flow_dv_convert_modify_action(&item, field, NULL, resource,
731 MLX5_MODIFICATION_TYPE_SET, error);
735 * Convert modify-header set TTL action to DV specification.
737 * @param[in,out] resource
738 * Pointer to the modify-header resource.
740 * Pointer to action specification.
742 * Pointer to rte_flow_item objects list.
744 * Pointer to flow attributes structure.
745 * @param[in] dev_flow
746 * Pointer to the sub flow.
747 * @param[in] tunnel_decap
748 * Whether action is after tunnel decapsulation.
750 * Pointer to the error structure.
753 * 0 on success, a negative errno value otherwise and rte_errno is set.
756 flow_dv_convert_action_modify_ttl
757 (struct mlx5_flow_dv_modify_hdr_resource *resource,
758 const struct rte_flow_action *action,
759 const struct rte_flow_item *items,
760 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
761 bool tunnel_decap, struct rte_flow_error *error)
763 const struct rte_flow_action_set_ttl *conf =
764 (const struct rte_flow_action_set_ttl *)(action->conf);
765 struct rte_flow_item item;
766 struct rte_flow_item_ipv4 ipv4;
767 struct rte_flow_item_ipv4 ipv4_mask;
768 struct rte_flow_item_ipv6 ipv6;
769 struct rte_flow_item_ipv6 ipv6_mask;
770 struct field_modify_info *field;
773 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
775 memset(&ipv4, 0, sizeof(ipv4));
776 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
777 ipv4.hdr.time_to_live = conf->ttl_value;
778 ipv4_mask.hdr.time_to_live = 0xFF;
779 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
781 item.mask = &ipv4_mask;
784 MLX5_ASSERT(attr->ipv6);
785 memset(&ipv6, 0, sizeof(ipv6));
786 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
787 ipv6.hdr.hop_limits = conf->ttl_value;
788 ipv6_mask.hdr.hop_limits = 0xFF;
789 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
791 item.mask = &ipv6_mask;
794 return flow_dv_convert_modify_action(&item, field, NULL, resource,
795 MLX5_MODIFICATION_TYPE_SET, error);
799 * Convert modify-header decrement TTL action to DV specification.
801 * @param[in,out] resource
802 * Pointer to the modify-header resource.
804 * Pointer to action specification.
806 * Pointer to rte_flow_item objects list.
808 * Pointer to flow attributes structure.
809 * @param[in] dev_flow
810 * Pointer to the sub flow.
811 * @param[in] tunnel_decap
812 * Whether action is after tunnel decapsulation.
814 * Pointer to the error structure.
817 * 0 on success, a negative errno value otherwise and rte_errno is set.
820 flow_dv_convert_action_modify_dec_ttl
821 (struct mlx5_flow_dv_modify_hdr_resource *resource,
822 const struct rte_flow_item *items,
823 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
824 bool tunnel_decap, struct rte_flow_error *error)
826 struct rte_flow_item item;
827 struct rte_flow_item_ipv4 ipv4;
828 struct rte_flow_item_ipv4 ipv4_mask;
829 struct rte_flow_item_ipv6 ipv6;
830 struct rte_flow_item_ipv6 ipv6_mask;
831 struct field_modify_info *field;
834 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
836 memset(&ipv4, 0, sizeof(ipv4));
837 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
838 ipv4.hdr.time_to_live = 0xFF;
839 ipv4_mask.hdr.time_to_live = 0xFF;
840 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
842 item.mask = &ipv4_mask;
845 MLX5_ASSERT(attr->ipv6);
846 memset(&ipv6, 0, sizeof(ipv6));
847 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
848 ipv6.hdr.hop_limits = 0xFF;
849 ipv6_mask.hdr.hop_limits = 0xFF;
850 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
852 item.mask = &ipv6_mask;
855 return flow_dv_convert_modify_action(&item, field, NULL, resource,
856 MLX5_MODIFICATION_TYPE_ADD, error);
860 * Convert modify-header increment/decrement TCP Sequence number
861 * to DV specification.
863 * @param[in,out] resource
864 * Pointer to the modify-header resource.
866 * Pointer to action specification.
868 * Pointer to the error structure.
871 * 0 on success, a negative errno value otherwise and rte_errno is set.
874 flow_dv_convert_action_modify_tcp_seq
875 (struct mlx5_flow_dv_modify_hdr_resource *resource,
876 const struct rte_flow_action *action,
877 struct rte_flow_error *error)
879 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
880 uint64_t value = rte_be_to_cpu_32(*conf);
881 struct rte_flow_item item;
882 struct rte_flow_item_tcp tcp;
883 struct rte_flow_item_tcp tcp_mask;
885 memset(&tcp, 0, sizeof(tcp));
886 memset(&tcp_mask, 0, sizeof(tcp_mask));
887 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
889 * The HW has no decrement operation, only increment operation.
890 * To simulate decrement X from Y using increment operation
891 * we need to add UINT32_MAX X times to Y.
892 * Each adding of UINT32_MAX decrements Y by 1.
895 tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
896 tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
897 item.type = RTE_FLOW_ITEM_TYPE_TCP;
899 item.mask = &tcp_mask;
900 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
901 MLX5_MODIFICATION_TYPE_ADD, error);
905 * Convert modify-header increment/decrement TCP Acknowledgment number
906 * to DV specification.
908 * @param[in,out] resource
909 * Pointer to the modify-header resource.
911 * Pointer to action specification.
913 * Pointer to the error structure.
916 * 0 on success, a negative errno value otherwise and rte_errno is set.
919 flow_dv_convert_action_modify_tcp_ack
920 (struct mlx5_flow_dv_modify_hdr_resource *resource,
921 const struct rte_flow_action *action,
922 struct rte_flow_error *error)
924 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
925 uint64_t value = rte_be_to_cpu_32(*conf);
926 struct rte_flow_item item;
927 struct rte_flow_item_tcp tcp;
928 struct rte_flow_item_tcp tcp_mask;
930 memset(&tcp, 0, sizeof(tcp));
931 memset(&tcp_mask, 0, sizeof(tcp_mask));
932 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
934 * The HW has no decrement operation, only increment operation.
935 * To simulate decrement X from Y using increment operation
936 * we need to add UINT32_MAX X times to Y.
937 * Each adding of UINT32_MAX decrements Y by 1.
940 tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
941 tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
942 item.type = RTE_FLOW_ITEM_TYPE_TCP;
944 item.mask = &tcp_mask;
945 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
946 MLX5_MODIFICATION_TYPE_ADD, error);
949 static enum mlx5_modification_field reg_to_field[] = {
950 [REG_NONE] = MLX5_MODI_OUT_NONE,
951 [REG_A] = MLX5_MODI_META_DATA_REG_A,
952 [REG_B] = MLX5_MODI_META_DATA_REG_B,
953 [REG_C_0] = MLX5_MODI_META_REG_C_0,
954 [REG_C_1] = MLX5_MODI_META_REG_C_1,
955 [REG_C_2] = MLX5_MODI_META_REG_C_2,
956 [REG_C_3] = MLX5_MODI_META_REG_C_3,
957 [REG_C_4] = MLX5_MODI_META_REG_C_4,
958 [REG_C_5] = MLX5_MODI_META_REG_C_5,
959 [REG_C_6] = MLX5_MODI_META_REG_C_6,
960 [REG_C_7] = MLX5_MODI_META_REG_C_7,
964 * Convert register set to DV specification.
966 * @param[in,out] resource
967 * Pointer to the modify-header resource.
969 * Pointer to action specification.
971 * Pointer to the error structure.
974 * 0 on success, a negative errno value otherwise and rte_errno is set.
977 flow_dv_convert_action_set_reg
978 (struct mlx5_flow_dv_modify_hdr_resource *resource,
979 const struct rte_flow_action *action,
980 struct rte_flow_error *error)
982 const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
983 struct mlx5_modification_cmd *actions = resource->actions;
984 uint32_t i = resource->actions_num;
986 if (i >= MLX5_MAX_MODIFY_NUM)
987 return rte_flow_error_set(error, EINVAL,
988 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
989 "too many items to modify");
990 MLX5_ASSERT(conf->id != REG_NONE);
991 MLX5_ASSERT(conf->id < RTE_DIM(reg_to_field));
992 actions[i] = (struct mlx5_modification_cmd) {
993 .action_type = MLX5_MODIFICATION_TYPE_SET,
994 .field = reg_to_field[conf->id],
996 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
997 actions[i].data1 = rte_cpu_to_be_32(conf->data);
999 resource->actions_num = i;
1004 * Convert SET_TAG action to DV specification.
1007 * Pointer to the rte_eth_dev structure.
1008 * @param[in,out] resource
1009 * Pointer to the modify-header resource.
1011 * Pointer to action specification.
1013 * Pointer to the error structure.
1016 * 0 on success, a negative errno value otherwise and rte_errno is set.
1019 flow_dv_convert_action_set_tag
1020 (struct rte_eth_dev *dev,
1021 struct mlx5_flow_dv_modify_hdr_resource *resource,
1022 const struct rte_flow_action_set_tag *conf,
1023 struct rte_flow_error *error)
1025 rte_be32_t data = rte_cpu_to_be_32(conf->data);
1026 rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
1027 struct rte_flow_item item = {
1031 struct field_modify_info reg_c_x[] = {
1034 enum mlx5_modification_field reg_type;
1037 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1040 MLX5_ASSERT(ret != REG_NONE);
1041 MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1042 reg_type = reg_to_field[ret];
1043 MLX5_ASSERT(reg_type > 0);
1044 reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1045 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1046 MLX5_MODIFICATION_TYPE_SET, error);
1050 * Convert internal COPY_REG action to DV specification.
1053 * Pointer to the rte_eth_dev structure.
1054 * @param[in,out] res
1055 * Pointer to the modify-header resource.
1057 * Pointer to action specification.
1059 * Pointer to the error structure.
1062 * 0 on success, a negative errno value otherwise and rte_errno is set.
1065 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1066 struct mlx5_flow_dv_modify_hdr_resource *res,
1067 const struct rte_flow_action *action,
1068 struct rte_flow_error *error)
1070 const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1071 rte_be32_t mask = RTE_BE32(UINT32_MAX);
1072 struct rte_flow_item item = {
1076 struct field_modify_info reg_src[] = {
1077 {4, 0, reg_to_field[conf->src]},
1080 struct field_modify_info reg_dst = {
1082 .id = reg_to_field[conf->dst],
1084 /* Adjust reg_c[0] usage according to reported mask. */
1085 if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1086 struct mlx5_priv *priv = dev->data->dev_private;
1087 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1089 MLX5_ASSERT(reg_c0);
1090 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1091 if (conf->dst == REG_C_0) {
1092 /* Copy to reg_c[0], within mask only. */
1093 reg_dst.offset = rte_bsf32(reg_c0);
1095 * Mask is ignoring the enianness, because
1096 * there is no conversion in datapath.
1098 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1099 /* Copy from destination lower bits to reg_c[0]. */
1100 mask = reg_c0 >> reg_dst.offset;
1102 /* Copy from destination upper bits to reg_c[0]. */
1103 mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1104 rte_fls_u32(reg_c0));
1107 mask = rte_cpu_to_be_32(reg_c0);
1108 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1109 /* Copy from reg_c[0] to destination lower bits. */
1112 /* Copy from reg_c[0] to destination upper bits. */
1113 reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1114 (rte_fls_u32(reg_c0) -
1119 return flow_dv_convert_modify_action(&item,
1120 reg_src, ®_dst, res,
1121 MLX5_MODIFICATION_TYPE_COPY,
1126 * Convert MARK action to DV specification. This routine is used
1127 * in extensive metadata only and requires metadata register to be
1128 * handled. In legacy mode hardware tag resource is engaged.
1131 * Pointer to the rte_eth_dev structure.
1133 * Pointer to MARK action specification.
1134 * @param[in,out] resource
1135 * Pointer to the modify-header resource.
1137 * Pointer to the error structure.
1140 * 0 on success, a negative errno value otherwise and rte_errno is set.
1143 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1144 const struct rte_flow_action_mark *conf,
1145 struct mlx5_flow_dv_modify_hdr_resource *resource,
1146 struct rte_flow_error *error)
1148 struct mlx5_priv *priv = dev->data->dev_private;
1149 rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1150 priv->sh->dv_mark_mask);
1151 rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1152 struct rte_flow_item item = {
1156 struct field_modify_info reg_c_x[] = {
1157 {4, 0, 0}, /* dynamic instead of MLX5_MODI_META_REG_C_1. */
1163 return rte_flow_error_set(error, EINVAL,
1164 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1165 NULL, "zero mark action mask");
1166 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1169 MLX5_ASSERT(reg > 0);
1170 if (reg == REG_C_0) {
1171 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1172 uint32_t shl_c0 = rte_bsf32(msk_c0);
1174 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1175 mask = rte_cpu_to_be_32(mask) & msk_c0;
1176 mask = rte_cpu_to_be_32(mask << shl_c0);
1178 reg_c_x[0].id = reg_to_field[reg];
1179 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1180 MLX5_MODIFICATION_TYPE_SET, error);
1184 * Get metadata register index for specified steering domain.
1187 * Pointer to the rte_eth_dev structure.
1189 * Attributes of flow to determine steering domain.
1191 * Pointer to the error structure.
1194 * positive index on success, a negative errno value otherwise
1195 * and rte_errno is set.
1197 static enum modify_reg
1198 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1199 const struct rte_flow_attr *attr,
1200 struct rte_flow_error *error)
1203 mlx5_flow_get_reg_id(dev, attr->transfer ?
1207 MLX5_METADATA_RX, 0, error);
1209 return rte_flow_error_set(error,
1210 ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1211 NULL, "unavailable "
1212 "metadata register");
1217 * Convert SET_META action to DV specification.
1220 * Pointer to the rte_eth_dev structure.
1221 * @param[in,out] resource
1222 * Pointer to the modify-header resource.
1224 * Attributes of flow that includes this item.
1226 * Pointer to action specification.
1228 * Pointer to the error structure.
1231 * 0 on success, a negative errno value otherwise and rte_errno is set.
1234 flow_dv_convert_action_set_meta
1235 (struct rte_eth_dev *dev,
1236 struct mlx5_flow_dv_modify_hdr_resource *resource,
1237 const struct rte_flow_attr *attr,
1238 const struct rte_flow_action_set_meta *conf,
1239 struct rte_flow_error *error)
1241 uint32_t data = conf->data;
1242 uint32_t mask = conf->mask;
1243 struct rte_flow_item item = {
1247 struct field_modify_info reg_c_x[] = {
1250 int reg = flow_dv_get_metadata_reg(dev, attr, error);
1255 * In datapath code there is no endianness
1256 * coversions for perfromance reasons, all
1257 * pattern conversions are done in rte_flow.
1259 if (reg == REG_C_0) {
1260 struct mlx5_priv *priv = dev->data->dev_private;
1261 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1264 MLX5_ASSERT(msk_c0);
1265 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1266 shl_c0 = rte_bsf32(msk_c0);
1268 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1272 MLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1274 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1275 /* The routine expects parameters in memory as big-endian ones. */
1276 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1277 MLX5_MODIFICATION_TYPE_SET, error);
1281 * Convert modify-header set IPv4 DSCP action to DV specification.
1283 * @param[in,out] resource
1284 * Pointer to the modify-header resource.
1286 * Pointer to action specification.
1288 * Pointer to the error structure.
1291 * 0 on success, a negative errno value otherwise and rte_errno is set.
1294 flow_dv_convert_action_modify_ipv4_dscp
1295 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1296 const struct rte_flow_action *action,
1297 struct rte_flow_error *error)
1299 const struct rte_flow_action_set_dscp *conf =
1300 (const struct rte_flow_action_set_dscp *)(action->conf);
1301 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1302 struct rte_flow_item_ipv4 ipv4;
1303 struct rte_flow_item_ipv4 ipv4_mask;
1305 memset(&ipv4, 0, sizeof(ipv4));
1306 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1307 ipv4.hdr.type_of_service = conf->dscp;
1308 ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1310 item.mask = &ipv4_mask;
1311 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1312 MLX5_MODIFICATION_TYPE_SET, error);
1316 * Convert modify-header set IPv6 DSCP action to DV specification.
1318 * @param[in,out] resource
1319 * Pointer to the modify-header resource.
1321 * Pointer to action specification.
1323 * Pointer to the error structure.
1326 * 0 on success, a negative errno value otherwise and rte_errno is set.
1329 flow_dv_convert_action_modify_ipv6_dscp
1330 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1331 const struct rte_flow_action *action,
1332 struct rte_flow_error *error)
1334 const struct rte_flow_action_set_dscp *conf =
1335 (const struct rte_flow_action_set_dscp *)(action->conf);
1336 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1337 struct rte_flow_item_ipv6 ipv6;
1338 struct rte_flow_item_ipv6 ipv6_mask;
1340 memset(&ipv6, 0, sizeof(ipv6));
1341 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1343 * Even though the DSCP bits offset of IPv6 is not byte aligned,
1344 * rdma-core only accept the DSCP bits byte aligned start from
1345 * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1346 * bits in IPv6 case as rdma-core requires byte aligned value.
1348 ipv6.hdr.vtc_flow = conf->dscp;
1349 ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1351 item.mask = &ipv6_mask;
1352 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1353 MLX5_MODIFICATION_TYPE_SET, error);
1357 * Validate MARK item.
1360 * Pointer to the rte_eth_dev structure.
1362 * Item specification.
1364 * Attributes of flow that includes this item.
1366 * Pointer to error structure.
1369 * 0 on success, a negative errno value otherwise and rte_errno is set.
1372 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1373 const struct rte_flow_item *item,
1374 const struct rte_flow_attr *attr __rte_unused,
1375 struct rte_flow_error *error)
1377 struct mlx5_priv *priv = dev->data->dev_private;
1378 struct mlx5_dev_config *config = &priv->config;
1379 const struct rte_flow_item_mark *spec = item->spec;
1380 const struct rte_flow_item_mark *mask = item->mask;
1381 const struct rte_flow_item_mark nic_mask = {
1382 .id = priv->sh->dv_mark_mask,
1386 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1387 return rte_flow_error_set(error, ENOTSUP,
1388 RTE_FLOW_ERROR_TYPE_ITEM, item,
1389 "extended metadata feature"
1391 if (!mlx5_flow_ext_mreg_supported(dev))
1392 return rte_flow_error_set(error, ENOTSUP,
1393 RTE_FLOW_ERROR_TYPE_ITEM, item,
1394 "extended metadata register"
1395 " isn't supported");
1397 return rte_flow_error_set(error, ENOTSUP,
1398 RTE_FLOW_ERROR_TYPE_ITEM, item,
1399 "extended metadata register"
1400 " isn't available");
1401 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1405 return rte_flow_error_set(error, EINVAL,
1406 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1408 "data cannot be empty");
1409 if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1410 return rte_flow_error_set(error, EINVAL,
1411 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1413 "mark id exceeds the limit");
1417 return rte_flow_error_set(error, EINVAL,
1418 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1419 "mask cannot be zero");
1421 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1422 (const uint8_t *)&nic_mask,
1423 sizeof(struct rte_flow_item_mark),
1431 * Validate META item.
1434 * Pointer to the rte_eth_dev structure.
1436 * Item specification.
1438 * Attributes of flow that includes this item.
1440 * Pointer to error structure.
1443 * 0 on success, a negative errno value otherwise and rte_errno is set.
1446 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1447 const struct rte_flow_item *item,
1448 const struct rte_flow_attr *attr,
1449 struct rte_flow_error *error)
1451 struct mlx5_priv *priv = dev->data->dev_private;
1452 struct mlx5_dev_config *config = &priv->config;
1453 const struct rte_flow_item_meta *spec = item->spec;
1454 const struct rte_flow_item_meta *mask = item->mask;
1455 struct rte_flow_item_meta nic_mask = {
1462 return rte_flow_error_set(error, EINVAL,
1463 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1465 "data cannot be empty");
1466 if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1467 if (!mlx5_flow_ext_mreg_supported(dev))
1468 return rte_flow_error_set(error, ENOTSUP,
1469 RTE_FLOW_ERROR_TYPE_ITEM, item,
1470 "extended metadata register"
1471 " isn't supported");
1472 reg = flow_dv_get_metadata_reg(dev, attr, error);
1476 return rte_flow_error_set(error, ENOTSUP,
1477 RTE_FLOW_ERROR_TYPE_ITEM, item,
1481 nic_mask.data = priv->sh->dv_meta_mask;
1484 mask = &rte_flow_item_meta_mask;
1486 return rte_flow_error_set(error, EINVAL,
1487 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1488 "mask cannot be zero");
1490 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1491 (const uint8_t *)&nic_mask,
1492 sizeof(struct rte_flow_item_meta),
1498 * Validate TAG item.
1501 * Pointer to the rte_eth_dev structure.
1503 * Item specification.
1505 * Attributes of flow that includes this item.
1507 * Pointer to error structure.
1510 * 0 on success, a negative errno value otherwise and rte_errno is set.
1513 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
1514 const struct rte_flow_item *item,
1515 const struct rte_flow_attr *attr __rte_unused,
1516 struct rte_flow_error *error)
1518 const struct rte_flow_item_tag *spec = item->spec;
1519 const struct rte_flow_item_tag *mask = item->mask;
1520 const struct rte_flow_item_tag nic_mask = {
1521 .data = RTE_BE32(UINT32_MAX),
1526 if (!mlx5_flow_ext_mreg_supported(dev))
1527 return rte_flow_error_set(error, ENOTSUP,
1528 RTE_FLOW_ERROR_TYPE_ITEM, item,
1529 "extensive metadata register"
1530 " isn't supported");
1532 return rte_flow_error_set(error, EINVAL,
1533 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1535 "data cannot be empty");
1537 mask = &rte_flow_item_tag_mask;
1539 return rte_flow_error_set(error, EINVAL,
1540 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1541 "mask cannot be zero");
1543 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1544 (const uint8_t *)&nic_mask,
1545 sizeof(struct rte_flow_item_tag),
1549 if (mask->index != 0xff)
1550 return rte_flow_error_set(error, EINVAL,
1551 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1552 "partial mask for tag index"
1553 " is not supported");
1554 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
1557 MLX5_ASSERT(ret != REG_NONE);
1562 * Validate vport item.
1565 * Pointer to the rte_eth_dev structure.
1567 * Item specification.
1569 * Attributes of flow that includes this item.
1570 * @param[in] item_flags
1571 * Bit-fields that holds the items detected until now.
1573 * Pointer to error structure.
1576 * 0 on success, a negative errno value otherwise and rte_errno is set.
1579 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
1580 const struct rte_flow_item *item,
1581 const struct rte_flow_attr *attr,
1582 uint64_t item_flags,
1583 struct rte_flow_error *error)
1585 const struct rte_flow_item_port_id *spec = item->spec;
1586 const struct rte_flow_item_port_id *mask = item->mask;
1587 const struct rte_flow_item_port_id switch_mask = {
1590 struct mlx5_priv *esw_priv;
1591 struct mlx5_priv *dev_priv;
1594 if (!attr->transfer)
1595 return rte_flow_error_set(error, EINVAL,
1596 RTE_FLOW_ERROR_TYPE_ITEM,
1598 "match on port id is valid only"
1599 " when transfer flag is enabled");
1600 if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
1601 return rte_flow_error_set(error, ENOTSUP,
1602 RTE_FLOW_ERROR_TYPE_ITEM, item,
1603 "multiple source ports are not"
1606 mask = &switch_mask;
1607 if (mask->id != 0xffffffff)
1608 return rte_flow_error_set(error, ENOTSUP,
1609 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1611 "no support for partial mask on"
1613 ret = mlx5_flow_item_acceptable
1614 (item, (const uint8_t *)mask,
1615 (const uint8_t *)&rte_flow_item_port_id_mask,
1616 sizeof(struct rte_flow_item_port_id),
1622 esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
1624 return rte_flow_error_set(error, rte_errno,
1625 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1626 "failed to obtain E-Switch info for"
1628 dev_priv = mlx5_dev_to_eswitch_info(dev);
1630 return rte_flow_error_set(error, rte_errno,
1631 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1633 "failed to obtain E-Switch info");
1634 if (esw_priv->domain_id != dev_priv->domain_id)
1635 return rte_flow_error_set(error, EINVAL,
1636 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1637 "cannot match on a port from a"
1638 " different E-Switch");
1643 * Validate GTP item.
1646 * Pointer to the rte_eth_dev structure.
1648 * Item specification.
1649 * @param[in] item_flags
1650 * Bit-fields that holds the items detected until now.
1652 * Pointer to error structure.
1655 * 0 on success, a negative errno value otherwise and rte_errno is set.
1658 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
1659 const struct rte_flow_item *item,
1660 uint64_t item_flags,
1661 struct rte_flow_error *error)
1663 struct mlx5_priv *priv = dev->data->dev_private;
1664 const struct rte_flow_item_gtp *mask = item->mask;
1665 const struct rte_flow_item_gtp nic_mask = {
1667 .teid = RTE_BE32(0xffffffff),
1670 if (!priv->config.hca_attr.tunnel_stateless_gtp)
1671 return rte_flow_error_set(error, ENOTSUP,
1672 RTE_FLOW_ERROR_TYPE_ITEM, item,
1673 "GTP support is not enabled");
1674 if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
1675 return rte_flow_error_set(error, ENOTSUP,
1676 RTE_FLOW_ERROR_TYPE_ITEM, item,
1677 "multiple tunnel layers not"
1679 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
1680 return rte_flow_error_set(error, EINVAL,
1681 RTE_FLOW_ERROR_TYPE_ITEM, item,
1682 "no outer UDP layer found");
1684 mask = &rte_flow_item_gtp_mask;
1685 return mlx5_flow_item_acceptable
1686 (item, (const uint8_t *)mask,
1687 (const uint8_t *)&nic_mask,
1688 sizeof(struct rte_flow_item_gtp),
1693 * Validate the pop VLAN action.
1696 * Pointer to the rte_eth_dev structure.
1697 * @param[in] action_flags
1698 * Holds the actions detected until now.
1700 * Pointer to the pop vlan action.
1701 * @param[in] item_flags
1702 * The items found in this flow rule.
1704 * Pointer to flow attributes.
1706 * Pointer to error structure.
1709 * 0 on success, a negative errno value otherwise and rte_errno is set.
1712 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
1713 uint64_t action_flags,
1714 const struct rte_flow_action *action,
1715 uint64_t item_flags,
1716 const struct rte_flow_attr *attr,
1717 struct rte_flow_error *error)
1719 const struct mlx5_priv *priv = dev->data->dev_private;
1723 if (!priv->sh->pop_vlan_action)
1724 return rte_flow_error_set(error, ENOTSUP,
1725 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1727 "pop vlan action is not supported");
1729 return rte_flow_error_set(error, ENOTSUP,
1730 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1732 "pop vlan action not supported for "
1734 if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
1735 return rte_flow_error_set(error, ENOTSUP,
1736 RTE_FLOW_ERROR_TYPE_ACTION, action,
1737 "no support for multiple VLAN "
1739 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1740 return rte_flow_error_set(error, ENOTSUP,
1741 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1743 "cannot pop vlan without a "
1744 "match on (outer) vlan in the flow");
1745 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1746 return rte_flow_error_set(error, EINVAL,
1747 RTE_FLOW_ERROR_TYPE_ACTION, action,
1748 "wrong action order, port_id should "
1749 "be after pop VLAN action");
1750 if (!attr->transfer && priv->representor)
1751 return rte_flow_error_set(error, ENOTSUP,
1752 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1753 "pop vlan action for VF representor "
1754 "not supported on NIC table");
1759 * Get VLAN default info from vlan match info.
1762 * the list of item specifications.
1764 * pointer VLAN info to fill to.
1767 * 0 on success, a negative errno value otherwise and rte_errno is set.
1770 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
1771 struct rte_vlan_hdr *vlan)
1773 const struct rte_flow_item_vlan nic_mask = {
1774 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
1775 MLX5DV_FLOW_VLAN_VID_MASK),
1776 .inner_type = RTE_BE16(0xffff),
1781 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
1782 int type = items->type;
1784 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
1785 type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
1788 if (items->type != RTE_FLOW_ITEM_TYPE_END) {
1789 const struct rte_flow_item_vlan *vlan_m = items->mask;
1790 const struct rte_flow_item_vlan *vlan_v = items->spec;
1794 /* Only full match values are accepted */
1795 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
1796 MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
1797 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
1799 rte_be_to_cpu_16(vlan_v->tci &
1800 MLX5DV_FLOW_VLAN_PCP_MASK_BE);
1802 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
1803 MLX5DV_FLOW_VLAN_VID_MASK_BE) {
1804 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
1806 rte_be_to_cpu_16(vlan_v->tci &
1807 MLX5DV_FLOW_VLAN_VID_MASK_BE);
1809 if (vlan_m->inner_type == nic_mask.inner_type)
1810 vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
1811 vlan_m->inner_type);
1816 * Validate the push VLAN action.
1819 * Pointer to the rte_eth_dev structure.
1820 * @param[in] action_flags
1821 * Holds the actions detected until now.
1822 * @param[in] item_flags
1823 * The items found in this flow rule.
1825 * Pointer to the action structure.
1827 * Pointer to flow attributes
1829 * Pointer to error structure.
1832 * 0 on success, a negative errno value otherwise and rte_errno is set.
1835 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
1836 uint64_t action_flags,
1837 const struct rte_flow_item_vlan *vlan_m,
1838 const struct rte_flow_action *action,
1839 const struct rte_flow_attr *attr,
1840 struct rte_flow_error *error)
1842 const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
1843 const struct mlx5_priv *priv = dev->data->dev_private;
1845 if (!attr->transfer && attr->ingress)
1846 return rte_flow_error_set(error, ENOTSUP,
1847 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1849 "push VLAN action not supported for "
1851 if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
1852 push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
1853 return rte_flow_error_set(error, EINVAL,
1854 RTE_FLOW_ERROR_TYPE_ACTION, action,
1855 "invalid vlan ethertype");
1856 if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
1857 return rte_flow_error_set(error, ENOTSUP,
1858 RTE_FLOW_ERROR_TYPE_ACTION, action,
1859 "no support for multiple VLAN "
1861 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1862 return rte_flow_error_set(error, EINVAL,
1863 RTE_FLOW_ERROR_TYPE_ACTION, action,
1864 "wrong action order, port_id should "
1865 "be after push VLAN");
1866 if (!attr->transfer && priv->representor)
1867 return rte_flow_error_set(error, ENOTSUP,
1868 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1869 "push vlan action for VF representor "
1870 "not supported on NIC table");
1872 (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
1873 (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
1874 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
1875 !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
1876 !(mlx5_flow_find_action
1877 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
1878 return rte_flow_error_set(error, EINVAL,
1879 RTE_FLOW_ERROR_TYPE_ACTION, action,
1880 "not full match mask on VLAN PCP and "
1881 "there is no of_set_vlan_pcp action, "
1882 "push VLAN action cannot figure out "
1885 (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
1886 (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
1887 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
1888 !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
1889 !(mlx5_flow_find_action
1890 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
1891 return rte_flow_error_set(error, EINVAL,
1892 RTE_FLOW_ERROR_TYPE_ACTION, action,
1893 "not full match mask on VLAN VID and "
1894 "there is no of_set_vlan_vid action, "
1895 "push VLAN action cannot figure out "
1902 * Validate the set VLAN PCP.
1904 * @param[in] action_flags
1905 * Holds the actions detected until now.
1906 * @param[in] actions
1907 * Pointer to the list of actions remaining in the flow rule.
1909 * Pointer to error structure.
1912 * 0 on success, a negative errno value otherwise and rte_errno is set.
1915 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
1916 const struct rte_flow_action actions[],
1917 struct rte_flow_error *error)
1919 const struct rte_flow_action *action = actions;
1920 const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
1922 if (conf->vlan_pcp > 7)
1923 return rte_flow_error_set(error, EINVAL,
1924 RTE_FLOW_ERROR_TYPE_ACTION, action,
1925 "VLAN PCP value is too big");
1926 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
1927 return rte_flow_error_set(error, ENOTSUP,
1928 RTE_FLOW_ERROR_TYPE_ACTION, action,
1929 "set VLAN PCP action must follow "
1930 "the push VLAN action");
1931 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
1932 return rte_flow_error_set(error, ENOTSUP,
1933 RTE_FLOW_ERROR_TYPE_ACTION, action,
1934 "Multiple VLAN PCP modification are "
1936 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1937 return rte_flow_error_set(error, EINVAL,
1938 RTE_FLOW_ERROR_TYPE_ACTION, action,
1939 "wrong action order, port_id should "
1940 "be after set VLAN PCP");
1945 * Validate the set VLAN VID.
1947 * @param[in] item_flags
1948 * Holds the items detected in this rule.
1949 * @param[in] action_flags
1950 * Holds the actions detected until now.
1951 * @param[in] actions
1952 * Pointer to the list of actions remaining in the flow rule.
1954 * Pointer to error structure.
1957 * 0 on success, a negative errno value otherwise and rte_errno is set.
1960 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
1961 uint64_t action_flags,
1962 const struct rte_flow_action actions[],
1963 struct rte_flow_error *error)
1965 const struct rte_flow_action *action = actions;
1966 const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
1968 if (rte_be_to_cpu_16(conf->vlan_vid) > 0xFFE)
1969 return rte_flow_error_set(error, EINVAL,
1970 RTE_FLOW_ERROR_TYPE_ACTION, action,
1971 "VLAN VID value is too big");
1972 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
1973 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1974 return rte_flow_error_set(error, ENOTSUP,
1975 RTE_FLOW_ERROR_TYPE_ACTION, action,
1976 "set VLAN VID action must follow push"
1977 " VLAN action or match on VLAN item");
1978 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
1979 return rte_flow_error_set(error, ENOTSUP,
1980 RTE_FLOW_ERROR_TYPE_ACTION, action,
1981 "Multiple VLAN VID modifications are "
1983 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1984 return rte_flow_error_set(error, EINVAL,
1985 RTE_FLOW_ERROR_TYPE_ACTION, action,
1986 "wrong action order, port_id should "
1987 "be after set VLAN VID");
1992 * Validate the FLAG action.
1995 * Pointer to the rte_eth_dev structure.
1996 * @param[in] action_flags
1997 * Holds the actions detected until now.
1999 * Pointer to flow attributes
2001 * Pointer to error structure.
2004 * 0 on success, a negative errno value otherwise and rte_errno is set.
2007 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
2008 uint64_t action_flags,
2009 const struct rte_flow_attr *attr,
2010 struct rte_flow_error *error)
2012 struct mlx5_priv *priv = dev->data->dev_private;
2013 struct mlx5_dev_config *config = &priv->config;
2016 /* Fall back if no extended metadata register support. */
2017 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2018 return mlx5_flow_validate_action_flag(action_flags, attr,
2020 /* Extensive metadata mode requires registers. */
2021 if (!mlx5_flow_ext_mreg_supported(dev))
2022 return rte_flow_error_set(error, ENOTSUP,
2023 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2024 "no metadata registers "
2025 "to support flag action");
2026 if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
2027 return rte_flow_error_set(error, ENOTSUP,
2028 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2029 "extended metadata register"
2030 " isn't available");
2031 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2034 MLX5_ASSERT(ret > 0);
2035 if (action_flags & MLX5_FLOW_ACTION_MARK)
2036 return rte_flow_error_set(error, EINVAL,
2037 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2038 "can't mark and flag in same flow");
2039 if (action_flags & MLX5_FLOW_ACTION_FLAG)
2040 return rte_flow_error_set(error, EINVAL,
2041 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2043 " actions in same flow");
2048 * Validate MARK action.
2051 * Pointer to the rte_eth_dev structure.
2053 * Pointer to action.
2054 * @param[in] action_flags
2055 * Holds the actions detected until now.
2057 * Pointer to flow attributes
2059 * Pointer to error structure.
2062 * 0 on success, a negative errno value otherwise and rte_errno is set.
2065 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
2066 const struct rte_flow_action *action,
2067 uint64_t action_flags,
2068 const struct rte_flow_attr *attr,
2069 struct rte_flow_error *error)
2071 struct mlx5_priv *priv = dev->data->dev_private;
2072 struct mlx5_dev_config *config = &priv->config;
2073 const struct rte_flow_action_mark *mark = action->conf;
2076 /* Fall back if no extended metadata register support. */
2077 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2078 return mlx5_flow_validate_action_mark(action, action_flags,
2080 /* Extensive metadata mode requires registers. */
2081 if (!mlx5_flow_ext_mreg_supported(dev))
2082 return rte_flow_error_set(error, ENOTSUP,
2083 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2084 "no metadata registers "
2085 "to support mark action");
2086 if (!priv->sh->dv_mark_mask)
2087 return rte_flow_error_set(error, ENOTSUP,
2088 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2089 "extended metadata register"
2090 " isn't available");
2091 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2094 MLX5_ASSERT(ret > 0);
2096 return rte_flow_error_set(error, EINVAL,
2097 RTE_FLOW_ERROR_TYPE_ACTION, action,
2098 "configuration cannot be null");
2099 if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
2100 return rte_flow_error_set(error, EINVAL,
2101 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2103 "mark id exceeds the limit");
2104 if (action_flags & MLX5_FLOW_ACTION_FLAG)
2105 return rte_flow_error_set(error, EINVAL,
2106 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2107 "can't flag and mark in same flow");
2108 if (action_flags & MLX5_FLOW_ACTION_MARK)
2109 return rte_flow_error_set(error, EINVAL,
2110 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2111 "can't have 2 mark actions in same"
2117 * Validate SET_META action.
2120 * Pointer to the rte_eth_dev structure.
2122 * Pointer to the action structure.
2123 * @param[in] action_flags
2124 * Holds the actions detected until now.
2126 * Pointer to flow attributes
2128 * Pointer to error structure.
2131 * 0 on success, a negative errno value otherwise and rte_errno is set.
2134 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
2135 const struct rte_flow_action *action,
2136 uint64_t action_flags __rte_unused,
2137 const struct rte_flow_attr *attr,
2138 struct rte_flow_error *error)
2140 const struct rte_flow_action_set_meta *conf;
2141 uint32_t nic_mask = UINT32_MAX;
2144 if (!mlx5_flow_ext_mreg_supported(dev))
2145 return rte_flow_error_set(error, ENOTSUP,
2146 RTE_FLOW_ERROR_TYPE_ACTION, action,
2147 "extended metadata register"
2148 " isn't supported");
2149 reg = flow_dv_get_metadata_reg(dev, attr, error);
2152 if (reg != REG_A && reg != REG_B) {
2153 struct mlx5_priv *priv = dev->data->dev_private;
2155 nic_mask = priv->sh->dv_meta_mask;
2157 if (!(action->conf))
2158 return rte_flow_error_set(error, EINVAL,
2159 RTE_FLOW_ERROR_TYPE_ACTION, action,
2160 "configuration cannot be null");
2161 conf = (const struct rte_flow_action_set_meta *)action->conf;
2163 return rte_flow_error_set(error, EINVAL,
2164 RTE_FLOW_ERROR_TYPE_ACTION, action,
2165 "zero mask doesn't have any effect");
2166 if (conf->mask & ~nic_mask)
2167 return rte_flow_error_set(error, EINVAL,
2168 RTE_FLOW_ERROR_TYPE_ACTION, action,
2169 "meta data must be within reg C0");
2174 * Validate SET_TAG action.
2177 * Pointer to the rte_eth_dev structure.
2179 * Pointer to the action structure.
2180 * @param[in] action_flags
2181 * Holds the actions detected until now.
2183 * Pointer to flow attributes
2185 * Pointer to error structure.
2188 * 0 on success, a negative errno value otherwise and rte_errno is set.
2191 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
2192 const struct rte_flow_action *action,
2193 uint64_t action_flags,
2194 const struct rte_flow_attr *attr,
2195 struct rte_flow_error *error)
2197 const struct rte_flow_action_set_tag *conf;
2198 const uint64_t terminal_action_flags =
2199 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
2200 MLX5_FLOW_ACTION_RSS;
2203 if (!mlx5_flow_ext_mreg_supported(dev))
2204 return rte_flow_error_set(error, ENOTSUP,
2205 RTE_FLOW_ERROR_TYPE_ACTION, action,
2206 "extensive metadata register"
2207 " isn't supported");
2208 if (!(action->conf))
2209 return rte_flow_error_set(error, EINVAL,
2210 RTE_FLOW_ERROR_TYPE_ACTION, action,
2211 "configuration cannot be null");
2212 conf = (const struct rte_flow_action_set_tag *)action->conf;
2214 return rte_flow_error_set(error, EINVAL,
2215 RTE_FLOW_ERROR_TYPE_ACTION, action,
2216 "zero mask doesn't have any effect");
2217 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
2220 if (!attr->transfer && attr->ingress &&
2221 (action_flags & terminal_action_flags))
2222 return rte_flow_error_set(error, EINVAL,
2223 RTE_FLOW_ERROR_TYPE_ACTION, action,
2224 "set_tag has no effect"
2225 " with terminal actions");
2230 * Validate count action.
2233 * Pointer to rte_eth_dev structure.
2235 * Pointer to error structure.
2238 * 0 on success, a negative errno value otherwise and rte_errno is set.
2241 flow_dv_validate_action_count(struct rte_eth_dev *dev,
2242 struct rte_flow_error *error)
2244 struct mlx5_priv *priv = dev->data->dev_private;
2246 if (!priv->config.devx)
2248 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
2252 return rte_flow_error_set
2254 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2256 "count action not supported");
2260 * Validate the L2 encap action.
2263 * Pointer to the rte_eth_dev structure.
2264 * @param[in] action_flags
2265 * Holds the actions detected until now.
2267 * Pointer to the action structure.
2269 * Pointer to flow attributes.
2271 * Pointer to error structure.
2274 * 0 on success, a negative errno value otherwise and rte_errno is set.
2277 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
2278 uint64_t action_flags,
2279 const struct rte_flow_action *action,
2280 const struct rte_flow_attr *attr,
2281 struct rte_flow_error *error)
2283 const struct mlx5_priv *priv = dev->data->dev_private;
2285 if (!(action->conf))
2286 return rte_flow_error_set(error, EINVAL,
2287 RTE_FLOW_ERROR_TYPE_ACTION, action,
2288 "configuration cannot be null");
2289 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
2290 return rte_flow_error_set(error, EINVAL,
2291 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2292 "can only have a single encap action "
2294 if (!attr->transfer && priv->representor)
2295 return rte_flow_error_set(error, ENOTSUP,
2296 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2297 "encap action for VF representor "
2298 "not supported on NIC table");
2303 * Validate a decap action.
2306 * Pointer to the rte_eth_dev structure.
2307 * @param[in] action_flags
2308 * Holds the actions detected until now.
2310 * Pointer to flow attributes
2312 * Pointer to error structure.
2315 * 0 on success, a negative errno value otherwise and rte_errno is set.
2318 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
2319 uint64_t action_flags,
2320 const struct rte_flow_attr *attr,
2321 struct rte_flow_error *error)
2323 const struct mlx5_priv *priv = dev->data->dev_private;
2325 if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
2326 return rte_flow_error_set(error, ENOTSUP,
2327 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2329 MLX5_FLOW_ACTION_DECAP ? "can only "
2330 "have a single decap action" : "decap "
2331 "after encap is not supported");
2332 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
2333 return rte_flow_error_set(error, EINVAL,
2334 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2335 "can't have decap action after"
2338 return rte_flow_error_set(error, ENOTSUP,
2339 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2341 "decap action not supported for "
2343 if (!attr->transfer && priv->representor)
2344 return rte_flow_error_set(error, ENOTSUP,
2345 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2346 "decap action for VF representor "
2347 "not supported on NIC table");
2351 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
2354 * Validate the raw encap and decap actions.
2357 * Pointer to the rte_eth_dev structure.
2359 * Pointer to the decap action.
2361 * Pointer to the encap action.
2363 * Pointer to flow attributes
2364 * @param[in/out] action_flags
2365 * Holds the actions detected until now.
2366 * @param[out] actions_n
2367 * pointer to the number of actions counter.
2369 * Pointer to error structure.
2372 * 0 on success, a negative errno value otherwise and rte_errno is set.
2375 flow_dv_validate_action_raw_encap_decap
2376 (struct rte_eth_dev *dev,
2377 const struct rte_flow_action_raw_decap *decap,
2378 const struct rte_flow_action_raw_encap *encap,
2379 const struct rte_flow_attr *attr, uint64_t *action_flags,
2380 int *actions_n, struct rte_flow_error *error)
2382 const struct mlx5_priv *priv = dev->data->dev_private;
2385 if (encap && (!encap->size || !encap->data))
2386 return rte_flow_error_set(error, EINVAL,
2387 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2388 "raw encap data cannot be empty");
2389 if (decap && encap) {
2390 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
2391 encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
2394 else if (encap->size <=
2395 MLX5_ENCAPSULATION_DECISION_SIZE &&
2397 MLX5_ENCAPSULATION_DECISION_SIZE)
2400 else if (encap->size >
2401 MLX5_ENCAPSULATION_DECISION_SIZE &&
2403 MLX5_ENCAPSULATION_DECISION_SIZE)
2404 /* 2 L2 actions: encap and decap. */
2407 return rte_flow_error_set(error,
2409 RTE_FLOW_ERROR_TYPE_ACTION,
2410 NULL, "unsupported too small "
2411 "raw decap and too small raw "
2412 "encap combination");
2415 ret = flow_dv_validate_action_decap(dev, *action_flags, attr,
2419 *action_flags |= MLX5_FLOW_ACTION_DECAP;
2423 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
2424 return rte_flow_error_set(error, ENOTSUP,
2425 RTE_FLOW_ERROR_TYPE_ACTION,
2427 "small raw encap size");
2428 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
2429 return rte_flow_error_set(error, EINVAL,
2430 RTE_FLOW_ERROR_TYPE_ACTION,
2432 "more than one encap action");
2433 if (!attr->transfer && priv->representor)
2434 return rte_flow_error_set
2436 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2437 "encap action for VF representor "
2438 "not supported on NIC table");
2439 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
2446 * Find existing encap/decap resource or create and register a new one.
2448 * @param[in, out] dev
2449 * Pointer to rte_eth_dev structure.
2450 * @param[in, out] resource
2451 * Pointer to encap/decap resource.
2452 * @parm[in, out] dev_flow
2453 * Pointer to the dev_flow.
2455 * pointer to error structure.
2458 * 0 on success otherwise -errno and errno is set.
2461 flow_dv_encap_decap_resource_register
2462 (struct rte_eth_dev *dev,
2463 struct mlx5_flow_dv_encap_decap_resource *resource,
2464 struct mlx5_flow *dev_flow,
2465 struct rte_flow_error *error)
2467 struct mlx5_priv *priv = dev->data->dev_private;
2468 struct mlx5_ibv_shared *sh = priv->sh;
2469 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2470 struct mlx5dv_dr_domain *domain;
2473 resource->flags = dev_flow->dv.group ? 0 : 1;
2474 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2475 domain = sh->fdb_domain;
2476 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2477 domain = sh->rx_domain;
2479 domain = sh->tx_domain;
2480 /* Lookup a matching resource from cache. */
2481 ILIST_FOREACH(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], sh->encaps_decaps, idx,
2482 cache_resource, next) {
2483 if (resource->reformat_type == cache_resource->reformat_type &&
2484 resource->ft_type == cache_resource->ft_type &&
2485 resource->flags == cache_resource->flags &&
2486 resource->size == cache_resource->size &&
2487 !memcmp((const void *)resource->buf,
2488 (const void *)cache_resource->buf,
2490 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d++",
2491 (void *)cache_resource,
2492 rte_atomic32_read(&cache_resource->refcnt));
2493 rte_atomic32_inc(&cache_resource->refcnt);
2494 dev_flow->handle->dvh.rix_encap_decap = idx;
2495 dev_flow->dv.encap_decap = cache_resource;
2499 /* Register new encap/decap resource. */
2500 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
2501 &dev_flow->handle->dvh.rix_encap_decap);
2502 if (!cache_resource)
2503 return rte_flow_error_set(error, ENOMEM,
2504 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2505 "cannot allocate resource memory");
2506 *cache_resource = *resource;
2507 cache_resource->verbs_action =
2508 mlx5_glue->dv_create_flow_action_packet_reformat
2509 (sh->ctx, cache_resource->reformat_type,
2510 cache_resource->ft_type, domain, cache_resource->flags,
2511 cache_resource->size,
2512 (cache_resource->size ? cache_resource->buf : NULL));
2513 if (!cache_resource->verbs_action) {
2514 rte_free(cache_resource);
2515 return rte_flow_error_set(error, ENOMEM,
2516 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2517 NULL, "cannot create action");
2519 rte_atomic32_init(&cache_resource->refcnt);
2520 rte_atomic32_inc(&cache_resource->refcnt);
2521 ILIST_INSERT(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], &sh->encaps_decaps,
2522 dev_flow->handle->dvh.rix_encap_decap, cache_resource,
2524 dev_flow->dv.encap_decap = cache_resource;
2525 DRV_LOG(DEBUG, "new encap/decap resource %p: refcnt %d++",
2526 (void *)cache_resource,
2527 rte_atomic32_read(&cache_resource->refcnt));
2532 * Find existing table jump resource or create and register a new one.
2534 * @param[in, out] dev
2535 * Pointer to rte_eth_dev structure.
2536 * @param[in, out] tbl
2537 * Pointer to flow table resource.
2538 * @parm[in, out] dev_flow
2539 * Pointer to the dev_flow.
2541 * pointer to error structure.
2544 * 0 on success otherwise -errno and errno is set.
2547 flow_dv_jump_tbl_resource_register
2548 (struct rte_eth_dev *dev __rte_unused,
2549 struct mlx5_flow_tbl_resource *tbl,
2550 struct mlx5_flow *dev_flow,
2551 struct rte_flow_error *error)
2553 struct mlx5_flow_tbl_data_entry *tbl_data =
2554 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
2558 cnt = rte_atomic32_read(&tbl_data->jump.refcnt);
2560 tbl_data->jump.action =
2561 mlx5_glue->dr_create_flow_action_dest_flow_tbl
2563 if (!tbl_data->jump.action)
2564 return rte_flow_error_set(error, ENOMEM,
2565 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2566 NULL, "cannot create jump action");
2567 DRV_LOG(DEBUG, "new jump table resource %p: refcnt %d++",
2568 (void *)&tbl_data->jump, cnt);
2570 /* old jump should not make the table ref++. */
2571 flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
2572 MLX5_ASSERT(tbl_data->jump.action);
2573 DRV_LOG(DEBUG, "existed jump table resource %p: refcnt %d++",
2574 (void *)&tbl_data->jump, cnt);
2576 rte_atomic32_inc(&tbl_data->jump.refcnt);
2577 dev_flow->handle->rix_jump = tbl_data->idx;
2578 dev_flow->dv.jump = &tbl_data->jump;
2583 * Find existing table port ID resource or create and register a new one.
2585 * @param[in, out] dev
2586 * Pointer to rte_eth_dev structure.
2587 * @param[in, out] resource
2588 * Pointer to port ID action resource.
2589 * @parm[in, out] dev_flow
2590 * Pointer to the dev_flow.
2592 * pointer to error structure.
2595 * 0 on success otherwise -errno and errno is set.
2598 flow_dv_port_id_action_resource_register
2599 (struct rte_eth_dev *dev,
2600 struct mlx5_flow_dv_port_id_action_resource *resource,
2601 struct mlx5_flow *dev_flow,
2602 struct rte_flow_error *error)
2604 struct mlx5_priv *priv = dev->data->dev_private;
2605 struct mlx5_ibv_shared *sh = priv->sh;
2606 struct mlx5_flow_dv_port_id_action_resource *cache_resource;
2609 /* Lookup a matching resource from cache. */
2610 ILIST_FOREACH(sh->ipool[MLX5_IPOOL_PORT_ID], sh->port_id_action_list,
2611 idx, cache_resource, next) {
2612 if (resource->port_id == cache_resource->port_id) {
2613 DRV_LOG(DEBUG, "port id action resource resource %p: "
2615 (void *)cache_resource,
2616 rte_atomic32_read(&cache_resource->refcnt));
2617 rte_atomic32_inc(&cache_resource->refcnt);
2618 dev_flow->handle->rix_port_id_action = idx;
2619 dev_flow->dv.port_id_action = cache_resource;
2623 /* Register new port id action resource. */
2624 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID],
2625 &dev_flow->handle->rix_port_id_action);
2626 if (!cache_resource)
2627 return rte_flow_error_set(error, ENOMEM,
2628 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2629 "cannot allocate resource memory");
2630 *cache_resource = *resource;
2632 * Depending on rdma_core version the glue routine calls
2633 * either mlx5dv_dr_action_create_dest_ib_port(domain, ibv_port)
2634 * or mlx5dv_dr_action_create_dest_vport(domain, vport_id).
2636 cache_resource->action =
2637 mlx5_glue->dr_create_flow_action_dest_port
2638 (priv->sh->fdb_domain, resource->port_id);
2639 if (!cache_resource->action) {
2640 rte_free(cache_resource);
2641 return rte_flow_error_set(error, ENOMEM,
2642 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2643 NULL, "cannot create action");
2645 rte_atomic32_init(&cache_resource->refcnt);
2646 rte_atomic32_inc(&cache_resource->refcnt);
2647 ILIST_INSERT(sh->ipool[MLX5_IPOOL_PORT_ID], &sh->port_id_action_list,
2648 dev_flow->handle->rix_port_id_action, cache_resource,
2650 dev_flow->dv.port_id_action = cache_resource;
2651 DRV_LOG(DEBUG, "new port id action resource %p: refcnt %d++",
2652 (void *)cache_resource,
2653 rte_atomic32_read(&cache_resource->refcnt));
2658 * Find existing push vlan resource or create and register a new one.
2660 * @param [in, out] dev
2661 * Pointer to rte_eth_dev structure.
2662 * @param[in, out] resource
2663 * Pointer to port ID action resource.
2664 * @parm[in, out] dev_flow
2665 * Pointer to the dev_flow.
2667 * pointer to error structure.
2670 * 0 on success otherwise -errno and errno is set.
2673 flow_dv_push_vlan_action_resource_register
2674 (struct rte_eth_dev *dev,
2675 struct mlx5_flow_dv_push_vlan_action_resource *resource,
2676 struct mlx5_flow *dev_flow,
2677 struct rte_flow_error *error)
2679 struct mlx5_priv *priv = dev->data->dev_private;
2680 struct mlx5_ibv_shared *sh = priv->sh;
2681 struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
2682 struct mlx5dv_dr_domain *domain;
2685 /* Lookup a matching resource from cache. */
2686 ILIST_FOREACH(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2687 sh->push_vlan_action_list, idx, cache_resource, next) {
2688 if (resource->vlan_tag == cache_resource->vlan_tag &&
2689 resource->ft_type == cache_resource->ft_type) {
2690 DRV_LOG(DEBUG, "push-VLAN action resource resource %p: "
2692 (void *)cache_resource,
2693 rte_atomic32_read(&cache_resource->refcnt));
2694 rte_atomic32_inc(&cache_resource->refcnt);
2695 dev_flow->handle->dvh.rix_push_vlan = idx;
2696 dev_flow->dv.push_vlan_res = cache_resource;
2700 /* Register new push_vlan action resource. */
2701 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2702 &dev_flow->handle->dvh.rix_push_vlan);
2703 if (!cache_resource)
2704 return rte_flow_error_set(error, ENOMEM,
2705 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2706 "cannot allocate resource memory");
2707 *cache_resource = *resource;
2708 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2709 domain = sh->fdb_domain;
2710 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2711 domain = sh->rx_domain;
2713 domain = sh->tx_domain;
2714 cache_resource->action =
2715 mlx5_glue->dr_create_flow_action_push_vlan(domain,
2716 resource->vlan_tag);
2717 if (!cache_resource->action) {
2718 rte_free(cache_resource);
2719 return rte_flow_error_set(error, ENOMEM,
2720 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2721 NULL, "cannot create action");
2723 rte_atomic32_init(&cache_resource->refcnt);
2724 rte_atomic32_inc(&cache_resource->refcnt);
2725 ILIST_INSERT(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2726 &sh->push_vlan_action_list,
2727 dev_flow->handle->dvh.rix_push_vlan,
2728 cache_resource, next);
2729 dev_flow->dv.push_vlan_res = cache_resource;
2730 DRV_LOG(DEBUG, "new push vlan action resource %p: refcnt %d++",
2731 (void *)cache_resource,
2732 rte_atomic32_read(&cache_resource->refcnt));
2736 * Get the size of specific rte_flow_item_type
2738 * @param[in] item_type
2739 * Tested rte_flow_item_type.
2742 * sizeof struct item_type, 0 if void or irrelevant.
2745 flow_dv_get_item_len(const enum rte_flow_item_type item_type)
2749 switch (item_type) {
2750 case RTE_FLOW_ITEM_TYPE_ETH:
2751 retval = sizeof(struct rte_flow_item_eth);
2753 case RTE_FLOW_ITEM_TYPE_VLAN:
2754 retval = sizeof(struct rte_flow_item_vlan);
2756 case RTE_FLOW_ITEM_TYPE_IPV4:
2757 retval = sizeof(struct rte_flow_item_ipv4);
2759 case RTE_FLOW_ITEM_TYPE_IPV6:
2760 retval = sizeof(struct rte_flow_item_ipv6);
2762 case RTE_FLOW_ITEM_TYPE_UDP:
2763 retval = sizeof(struct rte_flow_item_udp);
2765 case RTE_FLOW_ITEM_TYPE_TCP:
2766 retval = sizeof(struct rte_flow_item_tcp);
2768 case RTE_FLOW_ITEM_TYPE_VXLAN:
2769 retval = sizeof(struct rte_flow_item_vxlan);
2771 case RTE_FLOW_ITEM_TYPE_GRE:
2772 retval = sizeof(struct rte_flow_item_gre);
2774 case RTE_FLOW_ITEM_TYPE_NVGRE:
2775 retval = sizeof(struct rte_flow_item_nvgre);
2777 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2778 retval = sizeof(struct rte_flow_item_vxlan_gpe);
2780 case RTE_FLOW_ITEM_TYPE_MPLS:
2781 retval = sizeof(struct rte_flow_item_mpls);
2783 case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
2791 #define MLX5_ENCAP_IPV4_VERSION 0x40
2792 #define MLX5_ENCAP_IPV4_IHL_MIN 0x05
2793 #define MLX5_ENCAP_IPV4_TTL_DEF 0x40
2794 #define MLX5_ENCAP_IPV6_VTC_FLOW 0x60000000
2795 #define MLX5_ENCAP_IPV6_HOP_LIMIT 0xff
2796 #define MLX5_ENCAP_VXLAN_FLAGS 0x08000000
2797 #define MLX5_ENCAP_VXLAN_GPE_FLAGS 0x04
2800 * Convert the encap action data from list of rte_flow_item to raw buffer
2803 * Pointer to rte_flow_item objects list.
2805 * Pointer to the output buffer.
2807 * Pointer to the output buffer size.
2809 * Pointer to the error structure.
2812 * 0 on success, a negative errno value otherwise and rte_errno is set.
2815 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
2816 size_t *size, struct rte_flow_error *error)
2818 struct rte_ether_hdr *eth = NULL;
2819 struct rte_vlan_hdr *vlan = NULL;
2820 struct rte_ipv4_hdr *ipv4 = NULL;
2821 struct rte_ipv6_hdr *ipv6 = NULL;
2822 struct rte_udp_hdr *udp = NULL;
2823 struct rte_vxlan_hdr *vxlan = NULL;
2824 struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
2825 struct rte_gre_hdr *gre = NULL;
2827 size_t temp_size = 0;
2830 return rte_flow_error_set(error, EINVAL,
2831 RTE_FLOW_ERROR_TYPE_ACTION,
2832 NULL, "invalid empty data");
2833 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2834 len = flow_dv_get_item_len(items->type);
2835 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
2836 return rte_flow_error_set(error, EINVAL,
2837 RTE_FLOW_ERROR_TYPE_ACTION,
2838 (void *)items->type,
2839 "items total size is too big"
2840 " for encap action");
2841 rte_memcpy((void *)&buf[temp_size], items->spec, len);
2842 switch (items->type) {
2843 case RTE_FLOW_ITEM_TYPE_ETH:
2844 eth = (struct rte_ether_hdr *)&buf[temp_size];
2846 case RTE_FLOW_ITEM_TYPE_VLAN:
2847 vlan = (struct rte_vlan_hdr *)&buf[temp_size];
2849 return rte_flow_error_set(error, EINVAL,
2850 RTE_FLOW_ERROR_TYPE_ACTION,
2851 (void *)items->type,
2852 "eth header not found");
2853 if (!eth->ether_type)
2854 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
2856 case RTE_FLOW_ITEM_TYPE_IPV4:
2857 ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
2859 return rte_flow_error_set(error, EINVAL,
2860 RTE_FLOW_ERROR_TYPE_ACTION,
2861 (void *)items->type,
2862 "neither eth nor vlan"
2864 if (vlan && !vlan->eth_proto)
2865 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2866 else if (eth && !eth->ether_type)
2867 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2868 if (!ipv4->version_ihl)
2869 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
2870 MLX5_ENCAP_IPV4_IHL_MIN;
2871 if (!ipv4->time_to_live)
2872 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
2874 case RTE_FLOW_ITEM_TYPE_IPV6:
2875 ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
2877 return rte_flow_error_set(error, EINVAL,
2878 RTE_FLOW_ERROR_TYPE_ACTION,
2879 (void *)items->type,
2880 "neither eth nor vlan"
2882 if (vlan && !vlan->eth_proto)
2883 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2884 else if (eth && !eth->ether_type)
2885 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2886 if (!ipv6->vtc_flow)
2888 RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
2889 if (!ipv6->hop_limits)
2890 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
2892 case RTE_FLOW_ITEM_TYPE_UDP:
2893 udp = (struct rte_udp_hdr *)&buf[temp_size];
2895 return rte_flow_error_set(error, EINVAL,
2896 RTE_FLOW_ERROR_TYPE_ACTION,
2897 (void *)items->type,
2898 "ip header not found");
2899 if (ipv4 && !ipv4->next_proto_id)
2900 ipv4->next_proto_id = IPPROTO_UDP;
2901 else if (ipv6 && !ipv6->proto)
2902 ipv6->proto = IPPROTO_UDP;
2904 case RTE_FLOW_ITEM_TYPE_VXLAN:
2905 vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
2907 return rte_flow_error_set(error, EINVAL,
2908 RTE_FLOW_ERROR_TYPE_ACTION,
2909 (void *)items->type,
2910 "udp header not found");
2912 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
2913 if (!vxlan->vx_flags)
2915 RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
2917 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2918 vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
2920 return rte_flow_error_set(error, EINVAL,
2921 RTE_FLOW_ERROR_TYPE_ACTION,
2922 (void *)items->type,
2923 "udp header not found");
2924 if (!vxlan_gpe->proto)
2925 return rte_flow_error_set(error, EINVAL,
2926 RTE_FLOW_ERROR_TYPE_ACTION,
2927 (void *)items->type,
2928 "next protocol not found");
2931 RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
2932 if (!vxlan_gpe->vx_flags)
2933 vxlan_gpe->vx_flags =
2934 MLX5_ENCAP_VXLAN_GPE_FLAGS;
2936 case RTE_FLOW_ITEM_TYPE_GRE:
2937 case RTE_FLOW_ITEM_TYPE_NVGRE:
2938 gre = (struct rte_gre_hdr *)&buf[temp_size];
2940 return rte_flow_error_set(error, EINVAL,
2941 RTE_FLOW_ERROR_TYPE_ACTION,
2942 (void *)items->type,
2943 "next protocol not found");
2945 return rte_flow_error_set(error, EINVAL,
2946 RTE_FLOW_ERROR_TYPE_ACTION,
2947 (void *)items->type,
2948 "ip header not found");
2949 if (ipv4 && !ipv4->next_proto_id)
2950 ipv4->next_proto_id = IPPROTO_GRE;
2951 else if (ipv6 && !ipv6->proto)
2952 ipv6->proto = IPPROTO_GRE;
2954 case RTE_FLOW_ITEM_TYPE_VOID:
2957 return rte_flow_error_set(error, EINVAL,
2958 RTE_FLOW_ERROR_TYPE_ACTION,
2959 (void *)items->type,
2960 "unsupported item type");
2970 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
2972 struct rte_ether_hdr *eth = NULL;
2973 struct rte_vlan_hdr *vlan = NULL;
2974 struct rte_ipv6_hdr *ipv6 = NULL;
2975 struct rte_udp_hdr *udp = NULL;
2979 eth = (struct rte_ether_hdr *)data;
2980 next_hdr = (char *)(eth + 1);
2981 proto = RTE_BE16(eth->ether_type);
2984 while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
2985 vlan = (struct rte_vlan_hdr *)next_hdr;
2986 proto = RTE_BE16(vlan->eth_proto);
2987 next_hdr += sizeof(struct rte_vlan_hdr);
2990 /* HW calculates IPv4 csum. no need to proceed */
2991 if (proto == RTE_ETHER_TYPE_IPV4)
2994 /* non IPv4/IPv6 header. not supported */
2995 if (proto != RTE_ETHER_TYPE_IPV6) {
2996 return rte_flow_error_set(error, ENOTSUP,
2997 RTE_FLOW_ERROR_TYPE_ACTION,
2998 NULL, "Cannot offload non IPv4/IPv6");
3001 ipv6 = (struct rte_ipv6_hdr *)next_hdr;
3003 /* ignore non UDP */
3004 if (ipv6->proto != IPPROTO_UDP)
3007 udp = (struct rte_udp_hdr *)(ipv6 + 1);
3008 udp->dgram_cksum = 0;
3014 * Convert L2 encap action to DV specification.
3017 * Pointer to rte_eth_dev structure.
3019 * Pointer to action structure.
3020 * @param[in, out] dev_flow
3021 * Pointer to the mlx5_flow.
3022 * @param[in] transfer
3023 * Mark if the flow is E-Switch flow.
3025 * Pointer to the error structure.
3028 * 0 on success, a negative errno value otherwise and rte_errno is set.
3031 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
3032 const struct rte_flow_action *action,
3033 struct mlx5_flow *dev_flow,
3035 struct rte_flow_error *error)
3037 const struct rte_flow_item *encap_data;
3038 const struct rte_flow_action_raw_encap *raw_encap_data;
3039 struct mlx5_flow_dv_encap_decap_resource res = {
3041 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
3042 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3043 MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
3046 if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
3048 (const struct rte_flow_action_raw_encap *)action->conf;
3049 res.size = raw_encap_data->size;
3050 memcpy(res.buf, raw_encap_data->data, res.size);
3052 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
3054 ((const struct rte_flow_action_vxlan_encap *)
3055 action->conf)->definition;
3058 ((const struct rte_flow_action_nvgre_encap *)
3059 action->conf)->definition;
3060 if (flow_dv_convert_encap_data(encap_data, res.buf,
3064 if (flow_dv_zero_encap_udp_csum(res.buf, error))
3066 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3067 return rte_flow_error_set(error, EINVAL,
3068 RTE_FLOW_ERROR_TYPE_ACTION,
3069 NULL, "can't create L2 encap action");
3074 * Convert L2 decap action to DV specification.
3077 * Pointer to rte_eth_dev structure.
3078 * @param[in, out] dev_flow
3079 * Pointer to the mlx5_flow.
3080 * @param[in] transfer
3081 * Mark if the flow is E-Switch flow.
3083 * Pointer to the error structure.
3086 * 0 on success, a negative errno value otherwise and rte_errno is set.
3089 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
3090 struct mlx5_flow *dev_flow,
3092 struct rte_flow_error *error)
3094 struct mlx5_flow_dv_encap_decap_resource res = {
3097 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
3098 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3099 MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
3102 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3103 return rte_flow_error_set(error, EINVAL,
3104 RTE_FLOW_ERROR_TYPE_ACTION,
3105 NULL, "can't create L2 decap action");
3110 * Convert raw decap/encap (L3 tunnel) action to DV specification.
3113 * Pointer to rte_eth_dev structure.
3115 * Pointer to action structure.
3116 * @param[in, out] dev_flow
3117 * Pointer to the mlx5_flow.
3119 * Pointer to the flow attributes.
3121 * Pointer to the error structure.
3124 * 0 on success, a negative errno value otherwise and rte_errno is set.
3127 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
3128 const struct rte_flow_action *action,
3129 struct mlx5_flow *dev_flow,
3130 const struct rte_flow_attr *attr,
3131 struct rte_flow_error *error)
3133 const struct rte_flow_action_raw_encap *encap_data;
3134 struct mlx5_flow_dv_encap_decap_resource res;
3136 memset(&res, 0, sizeof(res));
3137 encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
3138 res.size = encap_data->size;
3139 memcpy(res.buf, encap_data->data, res.size);
3140 res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
3141 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
3142 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
3144 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3146 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3147 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3148 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3149 return rte_flow_error_set(error, EINVAL,
3150 RTE_FLOW_ERROR_TYPE_ACTION,
3151 NULL, "can't create encap action");
3156 * Create action push VLAN.
3159 * Pointer to rte_eth_dev structure.
3161 * Pointer to the flow attributes.
3163 * Pointer to the vlan to push to the Ethernet header.
3164 * @param[in, out] dev_flow
3165 * Pointer to the mlx5_flow.
3167 * Pointer to the error structure.
3170 * 0 on success, a negative errno value otherwise and rte_errno is set.
3173 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
3174 const struct rte_flow_attr *attr,
3175 const struct rte_vlan_hdr *vlan,
3176 struct mlx5_flow *dev_flow,
3177 struct rte_flow_error *error)
3179 struct mlx5_flow_dv_push_vlan_action_resource res;
3181 memset(&res, 0, sizeof(res));
3183 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
3186 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3188 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3189 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3190 return flow_dv_push_vlan_action_resource_register
3191 (dev, &res, dev_flow, error);
3195 * Validate the modify-header actions.
3197 * @param[in] action_flags
3198 * Holds the actions detected until now.
3200 * Pointer to the modify action.
3202 * Pointer to error structure.
3205 * 0 on success, a negative errno value otherwise and rte_errno is set.
3208 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
3209 const struct rte_flow_action *action,
3210 struct rte_flow_error *error)
3212 if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
3213 return rte_flow_error_set(error, EINVAL,
3214 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3215 NULL, "action configuration not set");
3216 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3217 return rte_flow_error_set(error, EINVAL,
3218 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3219 "can't have encap action before"
3225 * Validate the modify-header MAC address actions.
3227 * @param[in] action_flags
3228 * Holds the actions detected until now.
3230 * Pointer to the modify action.
3231 * @param[in] item_flags
3232 * Holds the items detected.
3234 * Pointer to error structure.
3237 * 0 on success, a negative errno value otherwise and rte_errno is set.
3240 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
3241 const struct rte_flow_action *action,
3242 const uint64_t item_flags,
3243 struct rte_flow_error *error)
3247 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3249 if (!(item_flags & MLX5_FLOW_LAYER_L2))
3250 return rte_flow_error_set(error, EINVAL,
3251 RTE_FLOW_ERROR_TYPE_ACTION,
3253 "no L2 item in pattern");
3259 * Validate the modify-header IPv4 address actions.
3261 * @param[in] action_flags
3262 * Holds the actions detected until now.
3264 * Pointer to the modify action.
3265 * @param[in] item_flags
3266 * Holds the items detected.
3268 * Pointer to error structure.
3271 * 0 on success, a negative errno value otherwise and rte_errno is set.
3274 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
3275 const struct rte_flow_action *action,
3276 const uint64_t item_flags,
3277 struct rte_flow_error *error)
3282 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3284 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3285 MLX5_FLOW_LAYER_INNER_L3_IPV4 :
3286 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
3287 if (!(item_flags & layer))
3288 return rte_flow_error_set(error, EINVAL,
3289 RTE_FLOW_ERROR_TYPE_ACTION,
3291 "no ipv4 item in pattern");
3297 * Validate the modify-header IPv6 address actions.
3299 * @param[in] action_flags
3300 * Holds the actions detected until now.
3302 * Pointer to the modify action.
3303 * @param[in] item_flags
3304 * Holds the items detected.
3306 * Pointer to error structure.
3309 * 0 on success, a negative errno value otherwise and rte_errno is set.
3312 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
3313 const struct rte_flow_action *action,
3314 const uint64_t item_flags,
3315 struct rte_flow_error *error)
3320 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3322 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3323 MLX5_FLOW_LAYER_INNER_L3_IPV6 :
3324 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
3325 if (!(item_flags & layer))
3326 return rte_flow_error_set(error, EINVAL,
3327 RTE_FLOW_ERROR_TYPE_ACTION,
3329 "no ipv6 item in pattern");
3335 * Validate the modify-header TP actions.
3337 * @param[in] action_flags
3338 * Holds the actions detected until now.
3340 * Pointer to the modify action.
3341 * @param[in] item_flags
3342 * Holds the items detected.
3344 * Pointer to error structure.
3347 * 0 on success, a negative errno value otherwise and rte_errno is set.
3350 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
3351 const struct rte_flow_action *action,
3352 const uint64_t item_flags,
3353 struct rte_flow_error *error)
3358 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3360 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3361 MLX5_FLOW_LAYER_INNER_L4 :
3362 MLX5_FLOW_LAYER_OUTER_L4;
3363 if (!(item_flags & layer))
3364 return rte_flow_error_set(error, EINVAL,
3365 RTE_FLOW_ERROR_TYPE_ACTION,
3366 NULL, "no transport layer "
3373 * Validate the modify-header actions of increment/decrement
3374 * TCP Sequence-number.
3376 * @param[in] action_flags
3377 * Holds the actions detected until now.
3379 * Pointer to the modify action.
3380 * @param[in] item_flags
3381 * Holds the items detected.
3383 * Pointer to error structure.
3386 * 0 on success, a negative errno value otherwise and rte_errno is set.
3389 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
3390 const struct rte_flow_action *action,
3391 const uint64_t item_flags,
3392 struct rte_flow_error *error)
3397 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3399 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3400 MLX5_FLOW_LAYER_INNER_L4_TCP :
3401 MLX5_FLOW_LAYER_OUTER_L4_TCP;
3402 if (!(item_flags & layer))
3403 return rte_flow_error_set(error, EINVAL,
3404 RTE_FLOW_ERROR_TYPE_ACTION,
3405 NULL, "no TCP item in"
3407 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
3408 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
3409 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
3410 (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
3411 return rte_flow_error_set(error, EINVAL,
3412 RTE_FLOW_ERROR_TYPE_ACTION,
3414 "cannot decrease and increase"
3415 " TCP sequence number"
3416 " at the same time");
3422 * Validate the modify-header actions of increment/decrement
3423 * TCP Acknowledgment number.
3425 * @param[in] action_flags
3426 * Holds the actions detected until now.
3428 * Pointer to the modify action.
3429 * @param[in] item_flags
3430 * Holds the items detected.
3432 * Pointer to error structure.
3435 * 0 on success, a negative errno value otherwise and rte_errno is set.
3438 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
3439 const struct rte_flow_action *action,
3440 const uint64_t item_flags,
3441 struct rte_flow_error *error)
3446 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3448 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3449 MLX5_FLOW_LAYER_INNER_L4_TCP :
3450 MLX5_FLOW_LAYER_OUTER_L4_TCP;
3451 if (!(item_flags & layer))
3452 return rte_flow_error_set(error, EINVAL,
3453 RTE_FLOW_ERROR_TYPE_ACTION,
3454 NULL, "no TCP item in"
3456 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
3457 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
3458 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
3459 (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
3460 return rte_flow_error_set(error, EINVAL,
3461 RTE_FLOW_ERROR_TYPE_ACTION,
3463 "cannot decrease and increase"
3464 " TCP acknowledgment number"
3465 " at the same time");
3471 * Validate the modify-header TTL actions.
3473 * @param[in] action_flags
3474 * Holds the actions detected until now.
3476 * Pointer to the modify action.
3477 * @param[in] item_flags
3478 * Holds the items detected.
3480 * Pointer to error structure.
3483 * 0 on success, a negative errno value otherwise and rte_errno is set.
3486 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
3487 const struct rte_flow_action *action,
3488 const uint64_t item_flags,
3489 struct rte_flow_error *error)
3494 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3496 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3497 MLX5_FLOW_LAYER_INNER_L3 :
3498 MLX5_FLOW_LAYER_OUTER_L3;
3499 if (!(item_flags & layer))
3500 return rte_flow_error_set(error, EINVAL,
3501 RTE_FLOW_ERROR_TYPE_ACTION,
3503 "no IP protocol in pattern");
3509 * Validate jump action.
3512 * Pointer to the jump action.
3513 * @param[in] action_flags
3514 * Holds the actions detected until now.
3515 * @param[in] attributes
3516 * Pointer to flow attributes
3517 * @param[in] external
3518 * Action belongs to flow rule created by request external to PMD.
3520 * Pointer to error structure.
3523 * 0 on success, a negative errno value otherwise and rte_errno is set.
3526 flow_dv_validate_action_jump(const struct rte_flow_action *action,
3527 uint64_t action_flags,
3528 const struct rte_flow_attr *attributes,
3529 bool external, struct rte_flow_error *error)
3531 uint32_t target_group, table;
3534 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3535 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3536 return rte_flow_error_set(error, EINVAL,
3537 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3538 "can't have 2 fate actions in"
3540 if (action_flags & MLX5_FLOW_ACTION_METER)
3541 return rte_flow_error_set(error, ENOTSUP,
3542 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3543 "jump with meter not support");
3545 return rte_flow_error_set(error, EINVAL,
3546 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3547 NULL, "action configuration not set");
3549 ((const struct rte_flow_action_jump *)action->conf)->group;
3550 ret = mlx5_flow_group_to_table(attributes, external, target_group,
3551 true, &table, error);
3554 if (attributes->group == target_group)
3555 return rte_flow_error_set(error, EINVAL,
3556 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3557 "target group must be other than"
3558 " the current flow group");
3563 * Validate the port_id action.
3566 * Pointer to rte_eth_dev structure.
3567 * @param[in] action_flags
3568 * Bit-fields that holds the actions detected until now.
3570 * Port_id RTE action structure.
3572 * Attributes of flow that includes this action.
3574 * Pointer to error structure.
3577 * 0 on success, a negative errno value otherwise and rte_errno is set.
3580 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
3581 uint64_t action_flags,
3582 const struct rte_flow_action *action,
3583 const struct rte_flow_attr *attr,
3584 struct rte_flow_error *error)
3586 const struct rte_flow_action_port_id *port_id;
3587 struct mlx5_priv *act_priv;
3588 struct mlx5_priv *dev_priv;
3591 if (!attr->transfer)
3592 return rte_flow_error_set(error, ENOTSUP,
3593 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3595 "port id action is valid in transfer"
3597 if (!action || !action->conf)
3598 return rte_flow_error_set(error, ENOTSUP,
3599 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3601 "port id action parameters must be"
3603 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3604 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3605 return rte_flow_error_set(error, EINVAL,
3606 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3607 "can have only one fate actions in"
3609 dev_priv = mlx5_dev_to_eswitch_info(dev);
3611 return rte_flow_error_set(error, rte_errno,
3612 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3614 "failed to obtain E-Switch info");
3615 port_id = action->conf;
3616 port = port_id->original ? dev->data->port_id : port_id->id;
3617 act_priv = mlx5_port_to_eswitch_info(port, false);
3619 return rte_flow_error_set
3621 RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
3622 "failed to obtain E-Switch port id for port");
3623 if (act_priv->domain_id != dev_priv->domain_id)
3624 return rte_flow_error_set
3626 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3627 "port does not belong to"
3628 " E-Switch being configured");
3633 * Get the maximum number of modify header actions.
3636 * Pointer to rte_eth_dev structure.
3638 * Flags bits to check if root level.
3641 * Max number of modify header actions device can support.
3643 static inline unsigned int
3644 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev __rte_unused,
3648 * There's no way to directly query the max capacity from FW.
3649 * The maximal value on root table should be assumed to be supported.
3651 if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
3652 return MLX5_MAX_MODIFY_NUM;
3654 return MLX5_ROOT_TBL_MODIFY_NUM;
3658 * Validate the meter action.
3661 * Pointer to rte_eth_dev structure.
3662 * @param[in] action_flags
3663 * Bit-fields that holds the actions detected until now.
3665 * Pointer to the meter action.
3667 * Attributes of flow that includes this action.
3669 * Pointer to error structure.
3672 * 0 on success, a negative errno value otherwise and rte_ernno is set.
3675 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
3676 uint64_t action_flags,
3677 const struct rte_flow_action *action,
3678 const struct rte_flow_attr *attr,
3679 struct rte_flow_error *error)
3681 struct mlx5_priv *priv = dev->data->dev_private;
3682 const struct rte_flow_action_meter *am = action->conf;
3683 struct mlx5_flow_meter *fm;
3686 return rte_flow_error_set(error, EINVAL,
3687 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3688 "meter action conf is NULL");
3690 if (action_flags & MLX5_FLOW_ACTION_METER)
3691 return rte_flow_error_set(error, ENOTSUP,
3692 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3693 "meter chaining not support");
3694 if (action_flags & MLX5_FLOW_ACTION_JUMP)
3695 return rte_flow_error_set(error, ENOTSUP,
3696 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3697 "meter with jump not support");
3699 return rte_flow_error_set(error, ENOTSUP,
3700 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3702 "meter action not supported");
3703 fm = mlx5_flow_meter_find(priv, am->mtr_id);
3705 return rte_flow_error_set(error, EINVAL,
3706 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3708 if (fm->ref_cnt && (!(fm->transfer == attr->transfer ||
3709 (!fm->ingress && !attr->ingress && attr->egress) ||
3710 (!fm->egress && !attr->egress && attr->ingress))))
3711 return rte_flow_error_set(error, EINVAL,
3712 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3713 "Flow attributes are either invalid "
3714 "or have a conflict with current "
3715 "meter attributes");
3720 * Validate the age action.
3722 * @param[in] action_flags
3723 * Holds the actions detected until now.
3725 * Pointer to the age action.
3727 * Pointer to the Ethernet device structure.
3729 * Pointer to error structure.
3732 * 0 on success, a negative errno value otherwise and rte_errno is set.
3735 flow_dv_validate_action_age(uint64_t action_flags,
3736 const struct rte_flow_action *action,
3737 struct rte_eth_dev *dev,
3738 struct rte_flow_error *error)
3740 struct mlx5_priv *priv = dev->data->dev_private;
3741 const struct rte_flow_action_age *age = action->conf;
3743 if (!priv->config.devx || priv->counter_fallback)
3744 return rte_flow_error_set(error, ENOTSUP,
3745 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3747 "age action not supported");
3748 if (!(action->conf))
3749 return rte_flow_error_set(error, EINVAL,
3750 RTE_FLOW_ERROR_TYPE_ACTION, action,
3751 "configuration cannot be null");
3752 if (age->timeout >= UINT16_MAX / 2 / 10)
3753 return rte_flow_error_set(error, ENOTSUP,
3754 RTE_FLOW_ERROR_TYPE_ACTION, action,
3755 "Max age time: 3275 seconds");
3756 if (action_flags & MLX5_FLOW_ACTION_AGE)
3757 return rte_flow_error_set(error, EINVAL,
3758 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3759 "Duplicate age ctions set");
3764 * Validate the modify-header IPv4 DSCP actions.
3766 * @param[in] action_flags
3767 * Holds the actions detected until now.
3769 * Pointer to the modify action.
3770 * @param[in] item_flags
3771 * Holds the items detected.
3773 * Pointer to error structure.
3776 * 0 on success, a negative errno value otherwise and rte_errno is set.
3779 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
3780 const struct rte_flow_action *action,
3781 const uint64_t item_flags,
3782 struct rte_flow_error *error)
3786 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3788 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
3789 return rte_flow_error_set(error, EINVAL,
3790 RTE_FLOW_ERROR_TYPE_ACTION,
3792 "no ipv4 item in pattern");
3798 * Validate the modify-header IPv6 DSCP actions.
3800 * @param[in] action_flags
3801 * Holds the actions detected until now.
3803 * Pointer to the modify action.
3804 * @param[in] item_flags
3805 * Holds the items detected.
3807 * Pointer to error structure.
3810 * 0 on success, a negative errno value otherwise and rte_errno is set.
3813 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
3814 const struct rte_flow_action *action,
3815 const uint64_t item_flags,
3816 struct rte_flow_error *error)
3820 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3822 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
3823 return rte_flow_error_set(error, EINVAL,
3824 RTE_FLOW_ERROR_TYPE_ACTION,
3826 "no ipv6 item in pattern");
3832 * Find existing modify-header resource or create and register a new one.
3834 * @param dev[in, out]
3835 * Pointer to rte_eth_dev structure.
3836 * @param[in, out] resource
3837 * Pointer to modify-header resource.
3838 * @parm[in, out] dev_flow
3839 * Pointer to the dev_flow.
3841 * pointer to error structure.
3844 * 0 on success otherwise -errno and errno is set.
3847 flow_dv_modify_hdr_resource_register
3848 (struct rte_eth_dev *dev,
3849 struct mlx5_flow_dv_modify_hdr_resource *resource,
3850 struct mlx5_flow *dev_flow,
3851 struct rte_flow_error *error)
3853 struct mlx5_priv *priv = dev->data->dev_private;
3854 struct mlx5_ibv_shared *sh = priv->sh;
3855 struct mlx5_flow_dv_modify_hdr_resource *cache_resource;
3856 struct mlx5dv_dr_domain *ns;
3857 uint32_t actions_len;
3859 resource->flags = dev_flow->dv.group ? 0 :
3860 MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
3861 if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
3863 return rte_flow_error_set(error, EOVERFLOW,
3864 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3865 "too many modify header items");
3866 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3867 ns = sh->fdb_domain;
3868 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
3872 /* Lookup a matching resource from cache. */
3873 actions_len = resource->actions_num * sizeof(resource->actions[0]);
3874 LIST_FOREACH(cache_resource, &sh->modify_cmds, next) {
3875 if (resource->ft_type == cache_resource->ft_type &&
3876 resource->actions_num == cache_resource->actions_num &&
3877 resource->flags == cache_resource->flags &&
3878 !memcmp((const void *)resource->actions,
3879 (const void *)cache_resource->actions,
3881 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d++",
3882 (void *)cache_resource,
3883 rte_atomic32_read(&cache_resource->refcnt));
3884 rte_atomic32_inc(&cache_resource->refcnt);
3885 dev_flow->handle->dvh.modify_hdr = cache_resource;
3889 /* Register new modify-header resource. */
3890 cache_resource = rte_calloc(__func__, 1,
3891 sizeof(*cache_resource) + actions_len, 0);
3892 if (!cache_resource)
3893 return rte_flow_error_set(error, ENOMEM,
3894 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3895 "cannot allocate resource memory");
3896 *cache_resource = *resource;
3897 rte_memcpy(cache_resource->actions, resource->actions, actions_len);
3898 cache_resource->verbs_action =
3899 mlx5_glue->dv_create_flow_action_modify_header
3900 (sh->ctx, cache_resource->ft_type, ns,
3901 cache_resource->flags, actions_len,
3902 (uint64_t *)cache_resource->actions);
3903 if (!cache_resource->verbs_action) {
3904 rte_free(cache_resource);
3905 return rte_flow_error_set(error, ENOMEM,
3906 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3907 NULL, "cannot create action");
3909 rte_atomic32_init(&cache_resource->refcnt);
3910 rte_atomic32_inc(&cache_resource->refcnt);
3911 LIST_INSERT_HEAD(&sh->modify_cmds, cache_resource, next);
3912 dev_flow->handle->dvh.modify_hdr = cache_resource;
3913 DRV_LOG(DEBUG, "new modify-header resource %p: refcnt %d++",
3914 (void *)cache_resource,
3915 rte_atomic32_read(&cache_resource->refcnt));
3920 * Get DV flow counter by index.
3923 * Pointer to the Ethernet device structure.
3925 * mlx5 flow counter index in the container.
3927 * mlx5 flow counter pool in the container,
3930 * Pointer to the counter, NULL otherwise.
3932 static struct mlx5_flow_counter *
3933 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
3935 struct mlx5_flow_counter_pool **ppool)
3937 struct mlx5_priv *priv = dev->data->dev_private;
3938 struct mlx5_pools_container *cont;
3939 struct mlx5_flow_counter_pool *pool;
3940 uint32_t batch = 0, age = 0;
3943 age = MLX_CNT_IS_AGE(idx);
3944 idx = age ? idx - MLX5_CNT_AGE_OFFSET : idx;
3945 if (idx >= MLX5_CNT_BATCH_OFFSET) {
3946 idx -= MLX5_CNT_BATCH_OFFSET;
3949 cont = MLX5_CNT_CONTAINER(priv->sh, batch, 0, age);
3950 MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cont->n);
3951 pool = cont->pools[idx / MLX5_COUNTERS_PER_POOL];
3955 return MLX5_POOL_GET_CNT(pool, idx % MLX5_COUNTERS_PER_POOL);
3959 * Get a pool by devx counter ID.
3962 * Pointer to the counter container.
3964 * The counter devx ID.
3967 * The counter pool pointer if exists, NULL otherwise,
3969 static struct mlx5_flow_counter_pool *
3970 flow_dv_find_pool_by_id(struct mlx5_pools_container *cont, int id)
3973 uint32_t n_valid = rte_atomic16_read(&cont->n_valid);
3975 for (i = 0; i < n_valid; i++) {
3976 struct mlx5_flow_counter_pool *pool = cont->pools[i];
3977 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
3978 MLX5_COUNTERS_PER_POOL;
3980 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL) {
3982 * Move the pool to the head, as counter allocate
3983 * always gets the first pool in the container.
3985 if (pool != TAILQ_FIRST(&cont->pool_list)) {
3986 TAILQ_REMOVE(&cont->pool_list, pool, next);
3987 TAILQ_INSERT_HEAD(&cont->pool_list, pool, next);
3996 * Allocate a new memory for the counter values wrapped by all the needed
4000 * Pointer to the Ethernet device structure.
4002 * The raw memory areas - each one for MLX5_COUNTERS_PER_POOL counters.
4005 * The new memory management pointer on success, otherwise NULL and rte_errno
4008 static struct mlx5_counter_stats_mem_mng *
4009 flow_dv_create_counter_stat_mem_mng(struct rte_eth_dev *dev, int raws_n)
4011 struct mlx5_ibv_shared *sh = ((struct mlx5_priv *)
4012 (dev->data->dev_private))->sh;
4013 struct mlx5_devx_mkey_attr mkey_attr;
4014 struct mlx5_counter_stats_mem_mng *mem_mng;
4015 volatile struct flow_counter_stats *raw_data;
4016 int size = (sizeof(struct flow_counter_stats) *
4017 MLX5_COUNTERS_PER_POOL +
4018 sizeof(struct mlx5_counter_stats_raw)) * raws_n +
4019 sizeof(struct mlx5_counter_stats_mem_mng);
4020 uint8_t *mem = rte_calloc(__func__, 1, size, sysconf(_SC_PAGESIZE));
4027 mem_mng = (struct mlx5_counter_stats_mem_mng *)(mem + size) - 1;
4028 size = sizeof(*raw_data) * MLX5_COUNTERS_PER_POOL * raws_n;
4029 mem_mng->umem = mlx5_glue->devx_umem_reg(sh->ctx, mem, size,
4030 IBV_ACCESS_LOCAL_WRITE);
4031 if (!mem_mng->umem) {
4036 mkey_attr.addr = (uintptr_t)mem;
4037 mkey_attr.size = size;
4038 mkey_attr.umem_id = mem_mng->umem->umem_id;
4039 mkey_attr.pd = sh->pdn;
4040 mkey_attr.log_entity_size = 0;
4041 mkey_attr.pg_access = 0;
4042 mkey_attr.klm_array = NULL;
4043 mkey_attr.klm_num = 0;
4044 mkey_attr.relaxed_ordering = 1;
4045 mem_mng->dm = mlx5_devx_cmd_mkey_create(sh->ctx, &mkey_attr);
4047 mlx5_glue->devx_umem_dereg(mem_mng->umem);
4052 mem_mng->raws = (struct mlx5_counter_stats_raw *)(mem + size);
4053 raw_data = (volatile struct flow_counter_stats *)mem;
4054 for (i = 0; i < raws_n; ++i) {
4055 mem_mng->raws[i].mem_mng = mem_mng;
4056 mem_mng->raws[i].data = raw_data + i * MLX5_COUNTERS_PER_POOL;
4058 LIST_INSERT_HEAD(&sh->cmng.mem_mngs, mem_mng, next);
4063 * Resize a counter container.
4066 * Pointer to the Ethernet device structure.
4068 * Whether the pool is for counter that was allocated by batch command.
4070 * Whether the pool is for Aging counter.
4073 * The new container pointer on success, otherwise NULL and rte_errno is set.
4075 static struct mlx5_pools_container *
4076 flow_dv_container_resize(struct rte_eth_dev *dev,
4077 uint32_t batch, uint32_t age)
4079 struct mlx5_priv *priv = dev->data->dev_private;
4080 struct mlx5_pools_container *cont =
4081 MLX5_CNT_CONTAINER(priv->sh, batch, 0, age);
4082 struct mlx5_pools_container *new_cont =
4083 MLX5_CNT_CONTAINER_UNUSED(priv->sh, batch, 0, age);
4084 struct mlx5_counter_stats_mem_mng *mem_mng = NULL;
4085 uint32_t resize = cont->n + MLX5_CNT_CONTAINER_RESIZE;
4086 uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
4089 /* Fallback mode has no background thread. Skip the check. */
4090 if (!priv->counter_fallback &&
4091 cont != MLX5_CNT_CONTAINER(priv->sh, batch, 1, age)) {
4092 /* The last resize still hasn't detected by the host thread. */
4096 new_cont->pools = rte_calloc(__func__, 1, mem_size, 0);
4097 if (!new_cont->pools) {
4102 memcpy(new_cont->pools, cont->pools, cont->n *
4103 sizeof(struct mlx5_flow_counter_pool *));
4105 * Fallback mode query the counter directly, no background query
4106 * resources are needed.
4108 if (!priv->counter_fallback) {
4109 mem_mng = flow_dv_create_counter_stat_mem_mng(dev,
4110 MLX5_CNT_CONTAINER_RESIZE + MLX5_MAX_PENDING_QUERIES);
4112 rte_free(new_cont->pools);
4115 for (i = 0; i < MLX5_MAX_PENDING_QUERIES; ++i)
4116 LIST_INSERT_HEAD(&priv->sh->cmng.free_stat_raws,
4118 MLX5_CNT_CONTAINER_RESIZE +
4122 * Release the old container pools directly as no background
4123 * thread helps that.
4125 rte_free(cont->pools);
4127 new_cont->n = resize;
4128 rte_atomic16_set(&new_cont->n_valid, rte_atomic16_read(&cont->n_valid));
4129 TAILQ_INIT(&new_cont->pool_list);
4130 TAILQ_CONCAT(&new_cont->pool_list, &cont->pool_list, next);
4131 new_cont->init_mem_mng = mem_mng;
4133 /* Flip the master container. */
4134 priv->sh->cmng.mhi[batch][age] ^= (uint8_t)1;
4139 * Query a devx flow counter.
4142 * Pointer to the Ethernet device structure.
4144 * Index to the flow counter.
4146 * The statistics value of packets.
4148 * The statistics value of bytes.
4151 * 0 on success, otherwise a negative errno value and rte_errno is set.
4154 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
4157 struct mlx5_priv *priv = dev->data->dev_private;
4158 struct mlx5_flow_counter_pool *pool = NULL;
4159 struct mlx5_flow_counter *cnt;
4160 struct mlx5_flow_counter_ext *cnt_ext = NULL;
4163 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
4165 if (counter < MLX5_CNT_BATCH_OFFSET) {
4166 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt);
4167 if (priv->counter_fallback)
4168 return mlx5_devx_cmd_flow_counter_query(cnt_ext->dcs, 0,
4169 0, pkts, bytes, 0, NULL, NULL, 0);
4172 rte_spinlock_lock(&pool->sl);
4174 * The single counters allocation may allocate smaller ID than the
4175 * current allocated in parallel to the host reading.
4176 * In this case the new counter values must be reported as 0.
4178 if (unlikely(cnt_ext && cnt_ext->dcs->id < pool->raw->min_dcs_id)) {
4182 offset = MLX5_CNT_ARRAY_IDX(pool, cnt);
4183 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
4184 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
4186 rte_spinlock_unlock(&pool->sl);
4191 * Create and initialize a new counter pool.
4194 * Pointer to the Ethernet device structure.
4196 * The devX counter handle.
4198 * Whether the pool is for counter that was allocated by batch command.
4200 * Whether the pool is for counter that was allocated for aging.
4201 * @param[in/out] cont_cur
4202 * Pointer to the container pointer, it will be update in pool resize.
4205 * The pool container pointer on success, NULL otherwise and rte_errno is set.
4207 static struct mlx5_pools_container *
4208 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
4209 uint32_t batch, uint32_t age)
4211 struct mlx5_priv *priv = dev->data->dev_private;
4212 struct mlx5_flow_counter_pool *pool;
4213 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4215 int16_t n_valid = rte_atomic16_read(&cont->n_valid);
4216 uint32_t size = sizeof(*pool);
4218 if (cont->n == n_valid) {
4219 cont = flow_dv_container_resize(dev, batch, age);
4223 size += MLX5_COUNTERS_PER_POOL * CNT_SIZE;
4224 size += (batch ? 0 : MLX5_COUNTERS_PER_POOL * CNTEXT_SIZE);
4225 size += (!age ? 0 : MLX5_COUNTERS_PER_POOL * AGE_SIZE);
4226 pool = rte_calloc(__func__, 1, size, 0);
4231 pool->min_dcs = dcs;
4232 if (!priv->counter_fallback)
4233 pool->raw = cont->init_mem_mng->raws + n_valid %
4234 MLX5_CNT_CONTAINER_RESIZE;
4235 pool->raw_hw = NULL;
4237 pool->type |= (batch ? 0 : CNT_POOL_TYPE_EXT);
4238 pool->type |= (!age ? 0 : CNT_POOL_TYPE_AGE);
4239 rte_spinlock_init(&pool->sl);
4241 * The generation of the new allocated counters in this pool is 0, 2 in
4242 * the pool generation makes all the counters valid for allocation.
4243 * The start and end query generation protect the counters be released
4244 * between the query and update gap period will not be reallocated
4245 * without the last query finished and stats updated to the memory.
4247 rte_atomic64_set(&pool->start_query_gen, 0x2);
4249 * There's no background query thread for fallback mode, set the
4250 * end_query_gen to the maximum value since no need to wait for
4251 * statistics update.
4253 rte_atomic64_set(&pool->end_query_gen, priv->counter_fallback ?
4255 TAILQ_INIT(&pool->counters);
4256 TAILQ_INSERT_HEAD(&cont->pool_list, pool, next);
4257 pool->index = n_valid;
4258 cont->pools[n_valid] = pool;
4259 /* Pool initialization must be updated before host thread access. */
4261 rte_atomic16_add(&cont->n_valid, 1);
4266 * Update the minimum dcs-id for aged or no-aged counter pool.
4269 * Pointer to the Ethernet device structure.
4271 * Current counter pool.
4273 * Whether the pool is for counter that was allocated by batch command.
4275 * Whether the counter is for aging.
4278 flow_dv_counter_update_min_dcs(struct rte_eth_dev *dev,
4279 struct mlx5_flow_counter_pool *pool,
4280 uint32_t batch, uint32_t age)
4282 struct mlx5_priv *priv = dev->data->dev_private;
4283 struct mlx5_flow_counter_pool *other;
4284 struct mlx5_pools_container *cont;
4286 cont = MLX5_CNT_CONTAINER(priv->sh, batch, 0, (age ^ 0x1));
4287 other = flow_dv_find_pool_by_id(cont, pool->min_dcs->id);
4290 if (pool->min_dcs->id < other->min_dcs->id) {
4291 rte_atomic64_set(&other->a64_dcs,
4292 rte_atomic64_read(&pool->a64_dcs));
4294 rte_atomic64_set(&pool->a64_dcs,
4295 rte_atomic64_read(&other->a64_dcs));
4299 * Prepare a new counter and/or a new counter pool.
4302 * Pointer to the Ethernet device structure.
4303 * @param[out] cnt_free
4304 * Where to put the pointer of a new counter.
4306 * Whether the pool is for counter that was allocated by batch command.
4308 * Whether the pool is for counter that was allocated for aging.
4311 * The counter container pointer and @p cnt_free is set on success,
4312 * NULL otherwise and rte_errno is set.
4314 static struct mlx5_pools_container *
4315 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
4316 struct mlx5_flow_counter **cnt_free,
4317 uint32_t batch, uint32_t age)
4319 struct mlx5_priv *priv = dev->data->dev_private;
4320 struct mlx5_pools_container *cont;
4321 struct mlx5_flow_counter_pool *pool;
4322 struct mlx5_devx_obj *dcs = NULL;
4323 struct mlx5_flow_counter *cnt;
4326 cont = MLX5_CNT_CONTAINER(priv->sh, batch, 0, age);
4328 /* bulk_bitmap must be 0 for single counter allocation. */
4329 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
4332 pool = flow_dv_find_pool_by_id(cont, dcs->id);
4334 cont = flow_dv_pool_create(dev, dcs, batch, age);
4336 mlx5_devx_cmd_destroy(dcs);
4339 pool = TAILQ_FIRST(&cont->pool_list);
4340 } else if (dcs->id < pool->min_dcs->id) {
4341 rte_atomic64_set(&pool->a64_dcs,
4342 (int64_t)(uintptr_t)dcs);
4344 flow_dv_counter_update_min_dcs(dev,
4346 i = dcs->id % MLX5_COUNTERS_PER_POOL;
4347 cnt = MLX5_POOL_GET_CNT(pool, i);
4348 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
4349 MLX5_GET_POOL_CNT_EXT(pool, i)->dcs = dcs;
4353 /* bulk_bitmap is in 128 counters units. */
4354 if (priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4)
4355 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
4357 rte_errno = ENODATA;
4360 cont = flow_dv_pool_create(dev, dcs, batch, age);
4362 mlx5_devx_cmd_destroy(dcs);
4365 pool = TAILQ_FIRST(&cont->pool_list);
4366 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
4367 cnt = MLX5_POOL_GET_CNT(pool, i);
4368 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
4370 *cnt_free = MLX5_POOL_GET_CNT(pool, 0);
4375 * Search for existed shared counter.
4378 * Pointer to the relevant counter pool container.
4380 * The shared counter ID to search.
4382 * mlx5 flow counter pool in the container,
4385 * NULL if not existed, otherwise pointer to the shared extend counter.
4387 static struct mlx5_flow_counter_ext *
4388 flow_dv_counter_shared_search(struct mlx5_pools_container *cont, uint32_t id,
4389 struct mlx5_flow_counter_pool **ppool)
4391 static struct mlx5_flow_counter_ext *cnt;
4392 struct mlx5_flow_counter_pool *pool;
4394 uint32_t n_valid = rte_atomic16_read(&cont->n_valid);
4396 for (i = 0; i < n_valid; i++) {
4397 pool = cont->pools[i];
4398 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
4399 cnt = MLX5_GET_POOL_CNT_EXT(pool, i);
4400 if (cnt->ref_cnt && cnt->shared && cnt->id == id) {
4402 *ppool = cont->pools[i];
4411 * Allocate a flow counter.
4414 * Pointer to the Ethernet device structure.
4416 * Indicate if this counter is shared with other flows.
4418 * Counter identifier.
4420 * Counter flow group.
4422 * Whether the counter was allocated for aging.
4425 * Index to flow counter on success, 0 otherwise and rte_errno is set.
4428 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t shared, uint32_t id,
4429 uint16_t group, uint32_t age)
4431 struct mlx5_priv *priv = dev->data->dev_private;
4432 struct mlx5_flow_counter_pool *pool = NULL;
4433 struct mlx5_flow_counter *cnt_free = NULL;
4434 struct mlx5_flow_counter_ext *cnt_ext = NULL;
4436 * Currently group 0 flow counter cannot be assigned to a flow if it is
4437 * not the first one in the batch counter allocation, so it is better
4438 * to allocate counters one by one for these flows in a separate
4440 * A counter can be shared between different groups so need to take
4441 * shared counters from the single container.
4443 uint32_t batch = (group && !shared && !priv->counter_fallback) ? 1 : 0;
4444 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4448 if (!priv->config.devx) {
4449 rte_errno = ENOTSUP;
4453 cnt_ext = flow_dv_counter_shared_search(cont, id, &pool);
4455 if (cnt_ext->ref_cnt + 1 == 0) {
4460 cnt_idx = pool->index * MLX5_COUNTERS_PER_POOL +
4461 (cnt_ext->dcs->id % MLX5_COUNTERS_PER_POOL)
4466 /* Pools which has a free counters are in the start. */
4467 TAILQ_FOREACH(pool, &cont->pool_list, next) {
4469 * The free counter reset values must be updated between the
4470 * counter release to the counter allocation, so, at least one
4471 * query must be done in this time. ensure it by saving the
4472 * query generation in the release time.
4473 * The free list is sorted according to the generation - so if
4474 * the first one is not updated, all the others are not
4477 cnt_free = TAILQ_FIRST(&pool->counters);
4478 if (cnt_free && cnt_free->query_gen <
4479 rte_atomic64_read(&pool->end_query_gen))
4484 cont = flow_dv_counter_pool_prepare(dev, &cnt_free, batch, age);
4487 pool = TAILQ_FIRST(&cont->pool_list);
4490 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt_free);
4491 /* Create a DV counter action only in the first time usage. */
4492 if (!cnt_free->action) {
4494 struct mlx5_devx_obj *dcs;
4497 offset = MLX5_CNT_ARRAY_IDX(pool, cnt_free);
4498 dcs = pool->min_dcs;
4503 cnt_free->action = mlx5_glue->dv_create_flow_action_counter
4505 if (!cnt_free->action) {
4510 cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
4511 MLX5_CNT_ARRAY_IDX(pool, cnt_free));
4512 cnt_idx += batch * MLX5_CNT_BATCH_OFFSET;
4513 cnt_idx += age * MLX5_CNT_AGE_OFFSET;
4514 /* Update the counter reset values. */
4515 if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
4519 cnt_ext->shared = shared;
4520 cnt_ext->ref_cnt = 1;
4523 if (!priv->counter_fallback && !priv->sh->cmng.query_thread_on)
4524 /* Start the asynchronous batch query by the host thread. */
4525 mlx5_set_query_alarm(priv->sh);
4526 TAILQ_REMOVE(&pool->counters, cnt_free, next);
4527 if (TAILQ_EMPTY(&pool->counters)) {
4528 /* Move the pool to the end of the container pool list. */
4529 TAILQ_REMOVE(&cont->pool_list, pool, next);
4530 TAILQ_INSERT_TAIL(&cont->pool_list, pool, next);
4536 * Get age param from counter index.
4539 * Pointer to the Ethernet device structure.
4540 * @param[in] counter
4541 * Index to the counter handler.
4544 * The aging parameter specified for the counter index.
4546 static struct mlx5_age_param*
4547 flow_dv_counter_idx_get_age(struct rte_eth_dev *dev,
4550 struct mlx5_flow_counter *cnt;
4551 struct mlx5_flow_counter_pool *pool = NULL;
4553 flow_dv_counter_get_by_idx(dev, counter, &pool);
4554 counter = (counter - 1) % MLX5_COUNTERS_PER_POOL;
4555 cnt = MLX5_POOL_GET_CNT(pool, counter);
4556 return MLX5_CNT_TO_AGE(cnt);
4560 * Remove a flow counter from aged counter list.
4563 * Pointer to the Ethernet device structure.
4564 * @param[in] counter
4565 * Index to the counter handler.
4567 * Pointer to the counter handler.
4570 flow_dv_counter_remove_from_age(struct rte_eth_dev *dev,
4571 uint32_t counter, struct mlx5_flow_counter *cnt)
4573 struct mlx5_age_info *age_info;
4574 struct mlx5_age_param *age_param;
4575 struct mlx5_priv *priv = dev->data->dev_private;
4577 age_info = GET_PORT_AGE_INFO(priv);
4578 age_param = flow_dv_counter_idx_get_age(dev, counter);
4579 if (rte_atomic16_cmpset((volatile uint16_t *)
4581 AGE_CANDIDATE, AGE_FREE)
4584 * We need the lock even it is age timeout,
4585 * since counter may still in process.
4587 rte_spinlock_lock(&age_info->aged_sl);
4588 TAILQ_REMOVE(&age_info->aged_counters, cnt, next);
4589 rte_spinlock_unlock(&age_info->aged_sl);
4591 rte_atomic16_set(&age_param->state, AGE_FREE);
4594 * Release a flow counter.
4597 * Pointer to the Ethernet device structure.
4598 * @param[in] counter
4599 * Index to the counter handler.
4602 flow_dv_counter_release(struct rte_eth_dev *dev, uint32_t counter)
4604 struct mlx5_flow_counter_pool *pool = NULL;
4605 struct mlx5_flow_counter *cnt;
4606 struct mlx5_flow_counter_ext *cnt_ext = NULL;
4610 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
4612 if (counter < MLX5_CNT_BATCH_OFFSET) {
4613 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt);
4614 if (cnt_ext && --cnt_ext->ref_cnt)
4617 if (IS_AGE_POOL(pool))
4618 flow_dv_counter_remove_from_age(dev, counter, cnt);
4619 /* Put the counter in the end - the last updated one. */
4620 TAILQ_INSERT_TAIL(&pool->counters, cnt, next);
4622 * Counters released between query trigger and handler need
4623 * to wait the next round of query. Since the packets arrive
4624 * in the gap period will not be taken into account to the
4627 cnt->query_gen = rte_atomic64_read(&pool->start_query_gen);
4631 * Verify the @p attributes will be correctly understood by the NIC and store
4632 * them in the @p flow if everything is correct.
4635 * Pointer to dev struct.
4636 * @param[in] attributes
4637 * Pointer to flow attributes
4638 * @param[in] external
4639 * This flow rule is created by request external to PMD.
4641 * Pointer to error structure.
4644 * - 0 on success and non root table.
4645 * - 1 on success and root table.
4646 * - a negative errno value otherwise and rte_errno is set.
4649 flow_dv_validate_attributes(struct rte_eth_dev *dev,
4650 const struct rte_flow_attr *attributes,
4651 bool external __rte_unused,
4652 struct rte_flow_error *error)
4654 struct mlx5_priv *priv = dev->data->dev_private;
4655 uint32_t priority_max = priv->config.flow_prio - 1;
4658 #ifndef HAVE_MLX5DV_DR
4659 if (attributes->group)
4660 return rte_flow_error_set(error, ENOTSUP,
4661 RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
4663 "groups are not supported");
4667 ret = mlx5_flow_group_to_table(attributes, external,
4668 attributes->group, !!priv->fdb_def_rule,
4673 ret = MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
4675 if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
4676 attributes->priority >= priority_max)
4677 return rte_flow_error_set(error, ENOTSUP,
4678 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
4680 "priority out of range");
4681 if (attributes->transfer) {
4682 if (!priv->config.dv_esw_en)
4683 return rte_flow_error_set
4685 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4686 "E-Switch dr is not supported");
4687 if (!(priv->representor || priv->master))
4688 return rte_flow_error_set
4689 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4690 NULL, "E-Switch configuration can only be"
4691 " done by a master or a representor device");
4692 if (attributes->egress)
4693 return rte_flow_error_set
4695 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
4696 "egress is not supported");
4698 if (!(attributes->egress ^ attributes->ingress))
4699 return rte_flow_error_set(error, ENOTSUP,
4700 RTE_FLOW_ERROR_TYPE_ATTR, NULL,
4701 "must specify exactly one of "
4702 "ingress or egress");
4707 * Internal validation function. For validating both actions and items.
4710 * Pointer to the rte_eth_dev structure.
4712 * Pointer to the flow attributes.
4714 * Pointer to the list of items.
4715 * @param[in] actions
4716 * Pointer to the list of actions.
4717 * @param[in] external
4718 * This flow rule is created by request external to PMD.
4719 * @param[in] hairpin
4720 * Number of hairpin TX actions, 0 means classic flow.
4722 * Pointer to the error structure.
4725 * 0 on success, a negative errno value otherwise and rte_errno is set.
4728 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
4729 const struct rte_flow_item items[],
4730 const struct rte_flow_action actions[],
4731 bool external, int hairpin, struct rte_flow_error *error)
4734 uint64_t action_flags = 0;
4735 uint64_t item_flags = 0;
4736 uint64_t last_item = 0;
4737 uint8_t next_protocol = 0xff;
4738 uint16_t ether_type = 0;
4740 uint8_t item_ipv6_proto = 0;
4741 const struct rte_flow_item *gre_item = NULL;
4742 const struct rte_flow_action_raw_decap *decap;
4743 const struct rte_flow_action_raw_encap *encap;
4744 const struct rte_flow_action_rss *rss;
4745 const struct rte_flow_item_tcp nic_tcp_mask = {
4748 .src_port = RTE_BE16(UINT16_MAX),
4749 .dst_port = RTE_BE16(UINT16_MAX),
4752 const struct rte_flow_item_ipv4 nic_ipv4_mask = {
4754 .src_addr = RTE_BE32(0xffffffff),
4755 .dst_addr = RTE_BE32(0xffffffff),
4756 .type_of_service = 0xff,
4757 .next_proto_id = 0xff,
4758 .time_to_live = 0xff,
4761 const struct rte_flow_item_ipv6 nic_ipv6_mask = {
4764 "\xff\xff\xff\xff\xff\xff\xff\xff"
4765 "\xff\xff\xff\xff\xff\xff\xff\xff",
4767 "\xff\xff\xff\xff\xff\xff\xff\xff"
4768 "\xff\xff\xff\xff\xff\xff\xff\xff",
4769 .vtc_flow = RTE_BE32(0xffffffff),
4774 struct mlx5_priv *priv = dev->data->dev_private;
4775 struct mlx5_dev_config *dev_conf = &priv->config;
4776 uint16_t queue_index = 0xFFFF;
4777 const struct rte_flow_item_vlan *vlan_m = NULL;
4778 int16_t rw_act_num = 0;
4783 ret = flow_dv_validate_attributes(dev, attr, external, error);
4786 is_root = (uint64_t)ret;
4787 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
4788 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
4789 int type = items->type;
4792 case RTE_FLOW_ITEM_TYPE_VOID:
4794 case RTE_FLOW_ITEM_TYPE_PORT_ID:
4795 ret = flow_dv_validate_item_port_id
4796 (dev, items, attr, item_flags, error);
4799 last_item = MLX5_FLOW_ITEM_PORT_ID;
4801 case RTE_FLOW_ITEM_TYPE_ETH:
4802 ret = mlx5_flow_validate_item_eth(items, item_flags,
4806 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
4807 MLX5_FLOW_LAYER_OUTER_L2;
4808 if (items->mask != NULL && items->spec != NULL) {
4810 ((const struct rte_flow_item_eth *)
4813 ((const struct rte_flow_item_eth *)
4815 ether_type = rte_be_to_cpu_16(ether_type);
4820 case RTE_FLOW_ITEM_TYPE_VLAN:
4821 ret = mlx5_flow_validate_item_vlan(items, item_flags,
4825 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
4826 MLX5_FLOW_LAYER_OUTER_VLAN;
4827 if (items->mask != NULL && items->spec != NULL) {
4829 ((const struct rte_flow_item_vlan *)
4830 items->spec)->inner_type;
4832 ((const struct rte_flow_item_vlan *)
4833 items->mask)->inner_type;
4834 ether_type = rte_be_to_cpu_16(ether_type);
4838 /* Store outer VLAN mask for of_push_vlan action. */
4840 vlan_m = items->mask;
4842 case RTE_FLOW_ITEM_TYPE_IPV4:
4843 mlx5_flow_tunnel_ip_check(items, next_protocol,
4844 &item_flags, &tunnel);
4845 ret = mlx5_flow_validate_item_ipv4(items, item_flags,
4852 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
4853 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
4854 if (items->mask != NULL &&
4855 ((const struct rte_flow_item_ipv4 *)
4856 items->mask)->hdr.next_proto_id) {
4858 ((const struct rte_flow_item_ipv4 *)
4859 (items->spec))->hdr.next_proto_id;
4861 ((const struct rte_flow_item_ipv4 *)
4862 (items->mask))->hdr.next_proto_id;
4864 /* Reset for inner layer. */
4865 next_protocol = 0xff;
4868 case RTE_FLOW_ITEM_TYPE_IPV6:
4869 mlx5_flow_tunnel_ip_check(items, next_protocol,
4870 &item_flags, &tunnel);
4871 ret = mlx5_flow_validate_item_ipv6(items, item_flags,
4878 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
4879 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
4880 if (items->mask != NULL &&
4881 ((const struct rte_flow_item_ipv6 *)
4882 items->mask)->hdr.proto) {
4884 ((const struct rte_flow_item_ipv6 *)
4885 items->spec)->hdr.proto;
4887 ((const struct rte_flow_item_ipv6 *)
4888 items->spec)->hdr.proto;
4890 ((const struct rte_flow_item_ipv6 *)
4891 items->mask)->hdr.proto;
4893 /* Reset for inner layer. */
4894 next_protocol = 0xff;
4897 case RTE_FLOW_ITEM_TYPE_TCP:
4898 ret = mlx5_flow_validate_item_tcp
4905 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
4906 MLX5_FLOW_LAYER_OUTER_L4_TCP;
4908 case RTE_FLOW_ITEM_TYPE_UDP:
4909 ret = mlx5_flow_validate_item_udp(items, item_flags,
4914 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
4915 MLX5_FLOW_LAYER_OUTER_L4_UDP;
4917 case RTE_FLOW_ITEM_TYPE_GRE:
4918 ret = mlx5_flow_validate_item_gre(items, item_flags,
4919 next_protocol, error);
4923 last_item = MLX5_FLOW_LAYER_GRE;
4925 case RTE_FLOW_ITEM_TYPE_NVGRE:
4926 ret = mlx5_flow_validate_item_nvgre(items, item_flags,
4931 last_item = MLX5_FLOW_LAYER_NVGRE;
4933 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
4934 ret = mlx5_flow_validate_item_gre_key
4935 (items, item_flags, gre_item, error);
4938 last_item = MLX5_FLOW_LAYER_GRE_KEY;
4940 case RTE_FLOW_ITEM_TYPE_VXLAN:
4941 ret = mlx5_flow_validate_item_vxlan(items, item_flags,
4945 last_item = MLX5_FLOW_LAYER_VXLAN;
4947 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
4948 ret = mlx5_flow_validate_item_vxlan_gpe(items,
4953 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
4955 case RTE_FLOW_ITEM_TYPE_GENEVE:
4956 ret = mlx5_flow_validate_item_geneve(items,
4961 last_item = MLX5_FLOW_LAYER_GENEVE;
4963 case RTE_FLOW_ITEM_TYPE_MPLS:
4964 ret = mlx5_flow_validate_item_mpls(dev, items,
4969 last_item = MLX5_FLOW_LAYER_MPLS;
4972 case RTE_FLOW_ITEM_TYPE_MARK:
4973 ret = flow_dv_validate_item_mark(dev, items, attr,
4977 last_item = MLX5_FLOW_ITEM_MARK;
4979 case RTE_FLOW_ITEM_TYPE_META:
4980 ret = flow_dv_validate_item_meta(dev, items, attr,
4984 last_item = MLX5_FLOW_ITEM_METADATA;
4986 case RTE_FLOW_ITEM_TYPE_ICMP:
4987 ret = mlx5_flow_validate_item_icmp(items, item_flags,
4992 last_item = MLX5_FLOW_LAYER_ICMP;
4994 case RTE_FLOW_ITEM_TYPE_ICMP6:
4995 ret = mlx5_flow_validate_item_icmp6(items, item_flags,
5000 item_ipv6_proto = IPPROTO_ICMPV6;
5001 last_item = MLX5_FLOW_LAYER_ICMP6;
5003 case RTE_FLOW_ITEM_TYPE_TAG:
5004 ret = flow_dv_validate_item_tag(dev, items,
5008 last_item = MLX5_FLOW_ITEM_TAG;
5010 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
5011 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
5013 case RTE_FLOW_ITEM_TYPE_GTP:
5014 ret = flow_dv_validate_item_gtp(dev, items, item_flags,
5018 last_item = MLX5_FLOW_LAYER_GTP;
5021 return rte_flow_error_set(error, ENOTSUP,
5022 RTE_FLOW_ERROR_TYPE_ITEM,
5023 NULL, "item not supported");
5025 item_flags |= last_item;
5027 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
5028 int type = actions->type;
5029 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
5030 return rte_flow_error_set(error, ENOTSUP,
5031 RTE_FLOW_ERROR_TYPE_ACTION,
5032 actions, "too many actions");
5034 case RTE_FLOW_ACTION_TYPE_VOID:
5036 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5037 ret = flow_dv_validate_action_port_id(dev,
5044 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5047 case RTE_FLOW_ACTION_TYPE_FLAG:
5048 ret = flow_dv_validate_action_flag(dev, action_flags,
5052 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
5053 /* Count all modify-header actions as one. */
5054 if (!(action_flags &
5055 MLX5_FLOW_MODIFY_HDR_ACTIONS))
5057 action_flags |= MLX5_FLOW_ACTION_FLAG |
5058 MLX5_FLOW_ACTION_MARK_EXT;
5060 action_flags |= MLX5_FLOW_ACTION_FLAG;
5063 rw_act_num += MLX5_ACT_NUM_SET_MARK;
5065 case RTE_FLOW_ACTION_TYPE_MARK:
5066 ret = flow_dv_validate_action_mark(dev, actions,
5071 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
5072 /* Count all modify-header actions as one. */
5073 if (!(action_flags &
5074 MLX5_FLOW_MODIFY_HDR_ACTIONS))
5076 action_flags |= MLX5_FLOW_ACTION_MARK |
5077 MLX5_FLOW_ACTION_MARK_EXT;
5079 action_flags |= MLX5_FLOW_ACTION_MARK;
5082 rw_act_num += MLX5_ACT_NUM_SET_MARK;
5084 case RTE_FLOW_ACTION_TYPE_SET_META:
5085 ret = flow_dv_validate_action_set_meta(dev, actions,
5090 /* Count all modify-header actions as one action. */
5091 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5093 action_flags |= MLX5_FLOW_ACTION_SET_META;
5094 rw_act_num += MLX5_ACT_NUM_SET_META;
5096 case RTE_FLOW_ACTION_TYPE_SET_TAG:
5097 ret = flow_dv_validate_action_set_tag(dev, actions,
5102 /* Count all modify-header actions as one action. */
5103 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5105 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
5106 rw_act_num += MLX5_ACT_NUM_SET_TAG;
5108 case RTE_FLOW_ACTION_TYPE_DROP:
5109 ret = mlx5_flow_validate_action_drop(action_flags,
5113 action_flags |= MLX5_FLOW_ACTION_DROP;
5116 case RTE_FLOW_ACTION_TYPE_QUEUE:
5117 ret = mlx5_flow_validate_action_queue(actions,
5122 queue_index = ((const struct rte_flow_action_queue *)
5123 (actions->conf))->index;
5124 action_flags |= MLX5_FLOW_ACTION_QUEUE;
5127 case RTE_FLOW_ACTION_TYPE_RSS:
5128 rss = actions->conf;
5129 ret = mlx5_flow_validate_action_rss(actions,
5135 if (rss != NULL && rss->queue_num)
5136 queue_index = rss->queue[0];
5137 action_flags |= MLX5_FLOW_ACTION_RSS;
5140 case RTE_FLOW_ACTION_TYPE_COUNT:
5141 ret = flow_dv_validate_action_count(dev, error);
5144 action_flags |= MLX5_FLOW_ACTION_COUNT;
5147 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
5148 if (flow_dv_validate_action_pop_vlan(dev,
5154 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
5157 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
5158 ret = flow_dv_validate_action_push_vlan(dev,
5165 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
5168 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
5169 ret = flow_dv_validate_action_set_vlan_pcp
5170 (action_flags, actions, error);
5173 /* Count PCP with push_vlan command. */
5174 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
5176 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
5177 ret = flow_dv_validate_action_set_vlan_vid
5178 (item_flags, action_flags,
5182 /* Count VID with push_vlan command. */
5183 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
5184 rw_act_num += MLX5_ACT_NUM_MDF_VID;
5186 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5187 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5188 ret = flow_dv_validate_action_l2_encap(dev,
5194 action_flags |= MLX5_FLOW_ACTION_ENCAP;
5197 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
5198 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
5199 ret = flow_dv_validate_action_decap(dev, action_flags,
5203 action_flags |= MLX5_FLOW_ACTION_DECAP;
5206 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5207 ret = flow_dv_validate_action_raw_encap_decap
5208 (dev, NULL, actions->conf, attr, &action_flags,
5213 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
5214 decap = actions->conf;
5215 while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
5217 if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
5221 encap = actions->conf;
5223 ret = flow_dv_validate_action_raw_encap_decap
5225 decap ? decap : &empty_decap, encap,
5226 attr, &action_flags, &actions_n,
5231 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
5232 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
5233 ret = flow_dv_validate_action_modify_mac(action_flags,
5239 /* Count all modify-header actions as one action. */
5240 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5242 action_flags |= actions->type ==
5243 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
5244 MLX5_FLOW_ACTION_SET_MAC_SRC :
5245 MLX5_FLOW_ACTION_SET_MAC_DST;
5247 * Even if the source and destination MAC addresses have
5248 * overlap in the header with 4B alignment, the convert
5249 * function will handle them separately and 4 SW actions
5250 * will be created. And 2 actions will be added each
5251 * time no matter how many bytes of address will be set.
5253 rw_act_num += MLX5_ACT_NUM_MDF_MAC;
5255 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
5256 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
5257 ret = flow_dv_validate_action_modify_ipv4(action_flags,
5263 /* Count all modify-header actions as one action. */
5264 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5266 action_flags |= actions->type ==
5267 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
5268 MLX5_FLOW_ACTION_SET_IPV4_SRC :
5269 MLX5_FLOW_ACTION_SET_IPV4_DST;
5270 rw_act_num += MLX5_ACT_NUM_MDF_IPV4;
5272 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
5273 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
5274 ret = flow_dv_validate_action_modify_ipv6(action_flags,
5280 if (item_ipv6_proto == IPPROTO_ICMPV6)
5281 return rte_flow_error_set(error, ENOTSUP,
5282 RTE_FLOW_ERROR_TYPE_ACTION,
5284 "Can't change header "
5285 "with ICMPv6 proto");
5286 /* Count all modify-header actions as one action. */
5287 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5289 action_flags |= actions->type ==
5290 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
5291 MLX5_FLOW_ACTION_SET_IPV6_SRC :
5292 MLX5_FLOW_ACTION_SET_IPV6_DST;
5293 rw_act_num += MLX5_ACT_NUM_MDF_IPV6;
5295 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
5296 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
5297 ret = flow_dv_validate_action_modify_tp(action_flags,
5303 /* Count all modify-header actions as one action. */
5304 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5306 action_flags |= actions->type ==
5307 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
5308 MLX5_FLOW_ACTION_SET_TP_SRC :
5309 MLX5_FLOW_ACTION_SET_TP_DST;
5310 rw_act_num += MLX5_ACT_NUM_MDF_PORT;
5312 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
5313 case RTE_FLOW_ACTION_TYPE_SET_TTL:
5314 ret = flow_dv_validate_action_modify_ttl(action_flags,
5320 /* Count all modify-header actions as one action. */
5321 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5323 action_flags |= actions->type ==
5324 RTE_FLOW_ACTION_TYPE_SET_TTL ?
5325 MLX5_FLOW_ACTION_SET_TTL :
5326 MLX5_FLOW_ACTION_DEC_TTL;
5327 rw_act_num += MLX5_ACT_NUM_MDF_TTL;
5329 case RTE_FLOW_ACTION_TYPE_JUMP:
5330 ret = flow_dv_validate_action_jump(actions,
5337 action_flags |= MLX5_FLOW_ACTION_JUMP;
5339 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
5340 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
5341 ret = flow_dv_validate_action_modify_tcp_seq
5348 /* Count all modify-header actions as one action. */
5349 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5351 action_flags |= actions->type ==
5352 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
5353 MLX5_FLOW_ACTION_INC_TCP_SEQ :
5354 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
5355 rw_act_num += MLX5_ACT_NUM_MDF_TCPSEQ;
5357 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
5358 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
5359 ret = flow_dv_validate_action_modify_tcp_ack
5366 /* Count all modify-header actions as one action. */
5367 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5369 action_flags |= actions->type ==
5370 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
5371 MLX5_FLOW_ACTION_INC_TCP_ACK :
5372 MLX5_FLOW_ACTION_DEC_TCP_ACK;
5373 rw_act_num += MLX5_ACT_NUM_MDF_TCPACK;
5375 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
5377 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
5378 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
5379 rw_act_num += MLX5_ACT_NUM_SET_TAG;
5381 case RTE_FLOW_ACTION_TYPE_METER:
5382 ret = mlx5_flow_validate_action_meter(dev,
5388 action_flags |= MLX5_FLOW_ACTION_METER;
5390 /* Meter action will add one more TAG action. */
5391 rw_act_num += MLX5_ACT_NUM_SET_TAG;
5393 case RTE_FLOW_ACTION_TYPE_AGE:
5394 ret = flow_dv_validate_action_age(action_flags,
5399 action_flags |= MLX5_FLOW_ACTION_AGE;
5402 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
5403 ret = flow_dv_validate_action_modify_ipv4_dscp
5410 /* Count all modify-header actions as one action. */
5411 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5413 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
5414 rw_act_num += MLX5_ACT_NUM_SET_DSCP;
5416 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
5417 ret = flow_dv_validate_action_modify_ipv6_dscp
5424 /* Count all modify-header actions as one action. */
5425 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5427 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
5428 rw_act_num += MLX5_ACT_NUM_SET_DSCP;
5431 return rte_flow_error_set(error, ENOTSUP,
5432 RTE_FLOW_ERROR_TYPE_ACTION,
5434 "action not supported");
5438 * Validate the drop action mutual exclusion with other actions.
5439 * Drop action is mutually-exclusive with any other action, except for
5442 if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
5443 (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
5444 return rte_flow_error_set(error, EINVAL,
5445 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5446 "Drop action is mutually-exclusive "
5447 "with any other action, except for "
5449 /* Eswitch has few restrictions on using items and actions */
5450 if (attr->transfer) {
5451 if (!mlx5_flow_ext_mreg_supported(dev) &&
5452 action_flags & MLX5_FLOW_ACTION_FLAG)
5453 return rte_flow_error_set(error, ENOTSUP,
5454 RTE_FLOW_ERROR_TYPE_ACTION,
5456 "unsupported action FLAG");
5457 if (!mlx5_flow_ext_mreg_supported(dev) &&
5458 action_flags & MLX5_FLOW_ACTION_MARK)
5459 return rte_flow_error_set(error, ENOTSUP,
5460 RTE_FLOW_ERROR_TYPE_ACTION,
5462 "unsupported action MARK");
5463 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
5464 return rte_flow_error_set(error, ENOTSUP,
5465 RTE_FLOW_ERROR_TYPE_ACTION,
5467 "unsupported action QUEUE");
5468 if (action_flags & MLX5_FLOW_ACTION_RSS)
5469 return rte_flow_error_set(error, ENOTSUP,
5470 RTE_FLOW_ERROR_TYPE_ACTION,
5472 "unsupported action RSS");
5473 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
5474 return rte_flow_error_set(error, EINVAL,
5475 RTE_FLOW_ERROR_TYPE_ACTION,
5477 "no fate action is found");
5479 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
5480 return rte_flow_error_set(error, EINVAL,
5481 RTE_FLOW_ERROR_TYPE_ACTION,
5483 "no fate action is found");
5485 /* Continue validation for Xcap actions.*/
5486 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) && (queue_index == 0xFFFF ||
5487 mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
5488 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
5489 MLX5_FLOW_XCAP_ACTIONS)
5490 return rte_flow_error_set(error, ENOTSUP,
5491 RTE_FLOW_ERROR_TYPE_ACTION,
5492 NULL, "encap and decap "
5493 "combination aren't supported");
5494 if (!attr->transfer && attr->ingress && (action_flags &
5495 MLX5_FLOW_ACTION_ENCAP))
5496 return rte_flow_error_set(error, ENOTSUP,
5497 RTE_FLOW_ERROR_TYPE_ACTION,
5498 NULL, "encap is not supported"
5499 " for ingress traffic");
5501 /* Hairpin flow will add one more TAG action. */
5503 rw_act_num += MLX5_ACT_NUM_SET_TAG;
5504 /* extra metadata enabled: one more TAG action will be add. */
5505 if (dev_conf->dv_flow_en &&
5506 dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
5507 mlx5_flow_ext_mreg_supported(dev))
5508 rw_act_num += MLX5_ACT_NUM_SET_TAG;
5509 if ((uint32_t)rw_act_num >
5510 flow_dv_modify_hdr_action_max(dev, is_root)) {
5511 return rte_flow_error_set(error, ENOTSUP,
5512 RTE_FLOW_ERROR_TYPE_ACTION,
5513 NULL, "too many header modify"
5514 " actions to support");
5520 * Internal preparation function. Allocates the DV flow size,
5521 * this size is constant.
5524 * Pointer to the rte_eth_dev structure.
5526 * Pointer to the flow attributes.
5528 * Pointer to the list of items.
5529 * @param[in] actions
5530 * Pointer to the list of actions.
5532 * Pointer to the error structure.
5535 * Pointer to mlx5_flow object on success,
5536 * otherwise NULL and rte_errno is set.
5538 static struct mlx5_flow *
5539 flow_dv_prepare(struct rte_eth_dev *dev,
5540 const struct rte_flow_attr *attr __rte_unused,
5541 const struct rte_flow_item items[] __rte_unused,
5542 const struct rte_flow_action actions[] __rte_unused,
5543 struct rte_flow_error *error)
5545 uint32_t handle_idx = 0;
5546 struct mlx5_flow *dev_flow;
5547 struct mlx5_flow_handle *dev_handle;
5548 struct mlx5_priv *priv = dev->data->dev_private;
5550 /* In case of corrupting the memory. */
5551 if (priv->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
5552 rte_flow_error_set(error, ENOSPC,
5553 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5554 "not free temporary device flow");
5557 dev_handle = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
5560 rte_flow_error_set(error, ENOMEM,
5561 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5562 "not enough memory to create flow handle");
5565 /* No multi-thread supporting. */
5566 dev_flow = &((struct mlx5_flow *)priv->inter_flows)[priv->flow_idx++];
5567 dev_flow->handle = dev_handle;
5568 dev_flow->handle_idx = handle_idx;
5569 dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);
5571 * The matching value needs to be cleared to 0 before using. In the
5572 * past, it will be automatically cleared when using rte_*alloc
5573 * API. The time consumption will be almost the same as before.
5575 memset(dev_flow->dv.value.buf, 0, MLX5_ST_SZ_BYTES(fte_match_param));
5576 dev_flow->ingress = attr->ingress;
5577 dev_flow->dv.transfer = attr->transfer;
5581 #ifdef RTE_LIBRTE_MLX5_DEBUG
5583 * Sanity check for match mask and value. Similar to check_valid_spec() in
5584 * kernel driver. If unmasked bit is present in value, it returns failure.
5587 * pointer to match mask buffer.
5588 * @param match_value
5589 * pointer to match value buffer.
5592 * 0 if valid, -EINVAL otherwise.
5595 flow_dv_check_valid_spec(void *match_mask, void *match_value)
5597 uint8_t *m = match_mask;
5598 uint8_t *v = match_value;
5601 for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
5604 "match_value differs from match_criteria"
5605 " %p[%u] != %p[%u]",
5606 match_value, i, match_mask, i);
5615 * Add Ethernet item to matcher and to the value.
5617 * @param[in, out] matcher
5619 * @param[in, out] key
5620 * Flow matcher value.
5622 * Flow pattern to translate.
5624 * Item is inner pattern.
5627 flow_dv_translate_item_eth(void *matcher, void *key,
5628 const struct rte_flow_item *item, int inner)
5630 const struct rte_flow_item_eth *eth_m = item->mask;
5631 const struct rte_flow_item_eth *eth_v = item->spec;
5632 const struct rte_flow_item_eth nic_mask = {
5633 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5634 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5635 .type = RTE_BE16(0xffff),
5647 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5649 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5651 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5653 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5655 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, dmac_47_16),
5656 ð_m->dst, sizeof(eth_m->dst));
5657 /* The value must be in the range of the mask. */
5658 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, dmac_47_16);
5659 for (i = 0; i < sizeof(eth_m->dst); ++i)
5660 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
5661 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, smac_47_16),
5662 ð_m->src, sizeof(eth_m->src));
5663 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, smac_47_16);
5664 /* The value must be in the range of the mask. */
5665 for (i = 0; i < sizeof(eth_m->dst); ++i)
5666 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
5668 /* When ethertype is present set mask for tagged VLAN. */
5669 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5670 /* Set value for tagged VLAN if ethertype is 802.1Q. */
5671 if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_VLAN) ||
5672 eth_v->type == RTE_BE16(RTE_ETHER_TYPE_QINQ)) {
5673 MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag,
5675 /* Return here to avoid setting match on ethertype. */
5680 * HW supports match on one Ethertype, the Ethertype following the last
5681 * VLAN tag of the packet (see PRM).
5682 * Set match on ethertype only if ETH header is not followed by VLAN.
5684 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
5685 rte_be_to_cpu_16(eth_m->type));
5686 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, ethertype);
5687 *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
5691 * Add VLAN item to matcher and to the value.
5693 * @param[in, out] dev_flow
5695 * @param[in, out] matcher
5697 * @param[in, out] key
5698 * Flow matcher value.
5700 * Flow pattern to translate.
5702 * Item is inner pattern.
5705 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
5706 void *matcher, void *key,
5707 const struct rte_flow_item *item,
5710 const struct rte_flow_item_vlan *vlan_m = item->mask;
5711 const struct rte_flow_item_vlan *vlan_v = item->spec;
5720 vlan_m = &rte_flow_item_vlan_mask;
5722 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5724 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5726 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5728 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5730 * This is workaround, masks are not supported,
5731 * and pre-validated.
5733 dev_flow->handle->vf_vlan.tag =
5734 rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
5736 tci_m = rte_be_to_cpu_16(vlan_m->tci);
5737 tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
5738 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5739 MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
5740 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_vid, tci_m);
5741 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, tci_v);
5742 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_cfi, tci_m >> 12);
5743 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_cfi, tci_v >> 12);
5744 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_prio, tci_m >> 13);
5745 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, tci_v >> 13);
5746 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
5747 rte_be_to_cpu_16(vlan_m->inner_type));
5748 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
5749 rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
5753 * Add IPV4 item to matcher and to the value.
5755 * @param[in, out] matcher
5757 * @param[in, out] key
5758 * Flow matcher value.
5760 * Flow pattern to translate.
5761 * @param[in] item_flags
5762 * Bit-fields that holds the items detected until now.
5764 * Item is inner pattern.
5766 * The group to insert the rule.
5769 flow_dv_translate_item_ipv4(void *matcher, void *key,
5770 const struct rte_flow_item *item,
5771 const uint64_t item_flags,
5772 int inner, uint32_t group)
5774 const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
5775 const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
5776 const struct rte_flow_item_ipv4 nic_mask = {
5778 .src_addr = RTE_BE32(0xffffffff),
5779 .dst_addr = RTE_BE32(0xffffffff),
5780 .type_of_service = 0xff,
5781 .next_proto_id = 0xff,
5782 .time_to_live = 0xff,
5792 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5794 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5796 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5798 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5801 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
5803 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x4);
5804 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 4);
5806 * On outer header (which must contains L2), or inner header with L2,
5807 * set cvlan_tag mask bit to mark this packet as untagged.
5808 * This should be done even if item->spec is empty.
5810 if (!inner || item_flags & MLX5_FLOW_LAYER_INNER_L2)
5811 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5816 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5817 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
5818 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5819 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
5820 *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
5821 *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
5822 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5823 src_ipv4_src_ipv6.ipv4_layout.ipv4);
5824 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5825 src_ipv4_src_ipv6.ipv4_layout.ipv4);
5826 *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
5827 *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
5828 tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
5829 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
5830 ipv4_m->hdr.type_of_service);
5831 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
5832 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
5833 ipv4_m->hdr.type_of_service >> 2);
5834 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
5835 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
5836 ipv4_m->hdr.next_proto_id);
5837 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
5838 ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
5839 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
5840 ipv4_m->hdr.time_to_live);
5841 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
5842 ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
5846 * Add IPV6 item to matcher and to the value.
5848 * @param[in, out] matcher
5850 * @param[in, out] key
5851 * Flow matcher value.
5853 * Flow pattern to translate.
5854 * @param[in] item_flags
5855 * Bit-fields that holds the items detected until now.
5857 * Item is inner pattern.
5859 * The group to insert the rule.
5862 flow_dv_translate_item_ipv6(void *matcher, void *key,
5863 const struct rte_flow_item *item,
5864 const uint64_t item_flags,
5865 int inner, uint32_t group)
5867 const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
5868 const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
5869 const struct rte_flow_item_ipv6 nic_mask = {
5872 "\xff\xff\xff\xff\xff\xff\xff\xff"
5873 "\xff\xff\xff\xff\xff\xff\xff\xff",
5875 "\xff\xff\xff\xff\xff\xff\xff\xff"
5876 "\xff\xff\xff\xff\xff\xff\xff\xff",
5877 .vtc_flow = RTE_BE32(0xffffffff),
5884 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5885 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5894 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5896 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5898 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5900 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5903 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
5905 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x6);
5906 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 6);
5908 * On outer header (which must contains L2), or inner header with L2,
5909 * set cvlan_tag mask bit to mark this packet as untagged.
5910 * This should be done even if item->spec is empty.
5912 if (!inner || item_flags & MLX5_FLOW_LAYER_INNER_L2)
5913 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5918 size = sizeof(ipv6_m->hdr.dst_addr);
5919 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5920 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
5921 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5922 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
5923 memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
5924 for (i = 0; i < size; ++i)
5925 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
5926 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5927 src_ipv4_src_ipv6.ipv6_layout.ipv6);
5928 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5929 src_ipv4_src_ipv6.ipv6_layout.ipv6);
5930 memcpy(l24_m, ipv6_m->hdr.src_addr, size);
5931 for (i = 0; i < size; ++i)
5932 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
5934 vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
5935 vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
5936 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
5937 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
5938 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
5939 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
5942 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
5944 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
5947 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
5949 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
5953 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
5955 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
5956 ipv6_v->hdr.proto & ipv6_m->hdr.proto);
5958 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
5959 ipv6_m->hdr.hop_limits);
5960 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
5961 ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
5965 * Add TCP item to matcher and to the value.
5967 * @param[in, out] matcher
5969 * @param[in, out] key
5970 * Flow matcher value.
5972 * Flow pattern to translate.
5974 * Item is inner pattern.
5977 flow_dv_translate_item_tcp(void *matcher, void *key,
5978 const struct rte_flow_item *item,
5981 const struct rte_flow_item_tcp *tcp_m = item->mask;
5982 const struct rte_flow_item_tcp *tcp_v = item->spec;
5987 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5989 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5991 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5993 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5995 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5996 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
6000 tcp_m = &rte_flow_item_tcp_mask;
6001 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
6002 rte_be_to_cpu_16(tcp_m->hdr.src_port));
6003 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
6004 rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
6005 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
6006 rte_be_to_cpu_16(tcp_m->hdr.dst_port));
6007 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
6008 rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
6009 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
6010 tcp_m->hdr.tcp_flags);
6011 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
6012 (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
6016 * Add UDP item to matcher and to the value.
6018 * @param[in, out] matcher
6020 * @param[in, out] key
6021 * Flow matcher value.
6023 * Flow pattern to translate.
6025 * Item is inner pattern.
6028 flow_dv_translate_item_udp(void *matcher, void *key,
6029 const struct rte_flow_item *item,
6032 const struct rte_flow_item_udp *udp_m = item->mask;
6033 const struct rte_flow_item_udp *udp_v = item->spec;
6038 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6040 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6042 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6044 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6046 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6047 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
6051 udp_m = &rte_flow_item_udp_mask;
6052 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
6053 rte_be_to_cpu_16(udp_m->hdr.src_port));
6054 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
6055 rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
6056 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
6057 rte_be_to_cpu_16(udp_m->hdr.dst_port));
6058 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
6059 rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
6063 * Add GRE optional Key item to matcher and to the value.
6065 * @param[in, out] matcher
6067 * @param[in, out] key
6068 * Flow matcher value.
6070 * Flow pattern to translate.
6072 * Item is inner pattern.
6075 flow_dv_translate_item_gre_key(void *matcher, void *key,
6076 const struct rte_flow_item *item)
6078 const rte_be32_t *key_m = item->mask;
6079 const rte_be32_t *key_v = item->spec;
6080 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6081 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6082 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
6084 /* GRE K bit must be on and should already be validated */
6085 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
6086 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
6090 key_m = &gre_key_default_mask;
6091 MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
6092 rte_be_to_cpu_32(*key_m) >> 8);
6093 MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
6094 rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
6095 MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
6096 rte_be_to_cpu_32(*key_m) & 0xFF);
6097 MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
6098 rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
6102 * Add GRE item to matcher and to the value.
6104 * @param[in, out] matcher
6106 * @param[in, out] key
6107 * Flow matcher value.
6109 * Flow pattern to translate.
6111 * Item is inner pattern.
6114 flow_dv_translate_item_gre(void *matcher, void *key,
6115 const struct rte_flow_item *item,
6118 const struct rte_flow_item_gre *gre_m = item->mask;
6119 const struct rte_flow_item_gre *gre_v = item->spec;
6122 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6123 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6130 uint16_t s_present:1;
6131 uint16_t k_present:1;
6132 uint16_t rsvd_bit1:1;
6133 uint16_t c_present:1;
6137 } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
6140 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6142 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6144 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6146 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6148 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6149 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
6153 gre_m = &rte_flow_item_gre_mask;
6154 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
6155 rte_be_to_cpu_16(gre_m->protocol));
6156 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
6157 rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
6158 gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
6159 gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
6160 MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
6161 gre_crks_rsvd0_ver_m.c_present);
6162 MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
6163 gre_crks_rsvd0_ver_v.c_present &
6164 gre_crks_rsvd0_ver_m.c_present);
6165 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
6166 gre_crks_rsvd0_ver_m.k_present);
6167 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
6168 gre_crks_rsvd0_ver_v.k_present &
6169 gre_crks_rsvd0_ver_m.k_present);
6170 MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
6171 gre_crks_rsvd0_ver_m.s_present);
6172 MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
6173 gre_crks_rsvd0_ver_v.s_present &
6174 gre_crks_rsvd0_ver_m.s_present);
6178 * Add NVGRE item to matcher and to the value.
6180 * @param[in, out] matcher
6182 * @param[in, out] key
6183 * Flow matcher value.
6185 * Flow pattern to translate.
6187 * Item is inner pattern.
6190 flow_dv_translate_item_nvgre(void *matcher, void *key,
6191 const struct rte_flow_item *item,
6194 const struct rte_flow_item_nvgre *nvgre_m = item->mask;
6195 const struct rte_flow_item_nvgre *nvgre_v = item->spec;
6196 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6197 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6198 const char *tni_flow_id_m = (const char *)nvgre_m->tni;
6199 const char *tni_flow_id_v = (const char *)nvgre_v->tni;
6205 /* For NVGRE, GRE header fields must be set with defined values. */
6206 const struct rte_flow_item_gre gre_spec = {
6207 .c_rsvd0_ver = RTE_BE16(0x2000),
6208 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
6210 const struct rte_flow_item_gre gre_mask = {
6211 .c_rsvd0_ver = RTE_BE16(0xB000),
6212 .protocol = RTE_BE16(UINT16_MAX),
6214 const struct rte_flow_item gre_item = {
6219 flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
6223 nvgre_m = &rte_flow_item_nvgre_mask;
6224 size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
6225 gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
6226 gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
6227 memcpy(gre_key_m, tni_flow_id_m, size);
6228 for (i = 0; i < size; ++i)
6229 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
6233 * Add VXLAN item to matcher and to the value.
6235 * @param[in, out] matcher
6237 * @param[in, out] key
6238 * Flow matcher value.
6240 * Flow pattern to translate.
6242 * Item is inner pattern.
6245 flow_dv_translate_item_vxlan(void *matcher, void *key,
6246 const struct rte_flow_item *item,
6249 const struct rte_flow_item_vxlan *vxlan_m = item->mask;
6250 const struct rte_flow_item_vxlan *vxlan_v = item->spec;
6253 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6254 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6262 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6264 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6266 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6268 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6270 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
6271 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
6272 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6273 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6274 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6279 vxlan_m = &rte_flow_item_vxlan_mask;
6280 size = sizeof(vxlan_m->vni);
6281 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
6282 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
6283 memcpy(vni_m, vxlan_m->vni, size);
6284 for (i = 0; i < size; ++i)
6285 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
6289 * Add VXLAN-GPE item to matcher and to the value.
6291 * @param[in, out] matcher
6293 * @param[in, out] key
6294 * Flow matcher value.
6296 * Flow pattern to translate.
6298 * Item is inner pattern.
6302 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
6303 const struct rte_flow_item *item, int inner)
6305 const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
6306 const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
6310 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
6312 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6318 uint8_t flags_m = 0xff;
6319 uint8_t flags_v = 0xc;
6322 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6324 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6326 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6328 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6330 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
6331 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
6332 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6333 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6334 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6339 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
6340 size = sizeof(vxlan_m->vni);
6341 vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
6342 vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
6343 memcpy(vni_m, vxlan_m->vni, size);
6344 for (i = 0; i < size; ++i)
6345 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
6346 if (vxlan_m->flags) {
6347 flags_m = vxlan_m->flags;
6348 flags_v = vxlan_v->flags;
6350 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
6351 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
6352 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
6354 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
6359 * Add Geneve item to matcher and to the value.
6361 * @param[in, out] matcher
6363 * @param[in, out] key
6364 * Flow matcher value.
6366 * Flow pattern to translate.
6368 * Item is inner pattern.
6372 flow_dv_translate_item_geneve(void *matcher, void *key,
6373 const struct rte_flow_item *item, int inner)
6375 const struct rte_flow_item_geneve *geneve_m = item->mask;
6376 const struct rte_flow_item_geneve *geneve_v = item->spec;
6379 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6380 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6389 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6391 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6393 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6395 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6397 dport = MLX5_UDP_PORT_GENEVE;
6398 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6399 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6400 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6405 geneve_m = &rte_flow_item_geneve_mask;
6406 size = sizeof(geneve_m->vni);
6407 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
6408 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
6409 memcpy(vni_m, geneve_m->vni, size);
6410 for (i = 0; i < size; ++i)
6411 vni_v[i] = vni_m[i] & geneve_v->vni[i];
6412 MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
6413 rte_be_to_cpu_16(geneve_m->protocol));
6414 MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
6415 rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
6416 gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
6417 gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
6418 MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
6419 MLX5_GENEVE_OAMF_VAL(gbhdr_m));
6420 MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
6421 MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
6422 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
6423 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
6424 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
6425 MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
6426 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
6430 * Add MPLS item to matcher and to the value.
6432 * @param[in, out] matcher
6434 * @param[in, out] key
6435 * Flow matcher value.
6437 * Flow pattern to translate.
6438 * @param[in] prev_layer
6439 * The protocol layer indicated in previous item.
6441 * Item is inner pattern.
6444 flow_dv_translate_item_mpls(void *matcher, void *key,
6445 const struct rte_flow_item *item,
6446 uint64_t prev_layer,
6449 const uint32_t *in_mpls_m = item->mask;
6450 const uint32_t *in_mpls_v = item->spec;
6451 uint32_t *out_mpls_m = 0;
6452 uint32_t *out_mpls_v = 0;
6453 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6454 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6455 void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
6457 void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
6458 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
6459 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6461 switch (prev_layer) {
6462 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
6463 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
6464 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
6465 MLX5_UDP_PORT_MPLS);
6467 case MLX5_FLOW_LAYER_GRE:
6468 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
6469 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
6470 RTE_ETHER_TYPE_MPLS);
6473 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6474 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6481 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
6482 switch (prev_layer) {
6483 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
6485 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
6486 outer_first_mpls_over_udp);
6488 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
6489 outer_first_mpls_over_udp);
6491 case MLX5_FLOW_LAYER_GRE:
6493 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
6494 outer_first_mpls_over_gre);
6496 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
6497 outer_first_mpls_over_gre);
6500 /* Inner MPLS not over GRE is not supported. */
6503 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
6507 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
6513 if (out_mpls_m && out_mpls_v) {
6514 *out_mpls_m = *in_mpls_m;
6515 *out_mpls_v = *in_mpls_v & *in_mpls_m;
6520 * Add metadata register item to matcher
6522 * @param[in, out] matcher
6524 * @param[in, out] key
6525 * Flow matcher value.
6526 * @param[in] reg_type
6527 * Type of device metadata register
6534 flow_dv_match_meta_reg(void *matcher, void *key,
6535 enum modify_reg reg_type,
6536 uint32_t data, uint32_t mask)
6539 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
6541 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
6547 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
6548 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
6551 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
6552 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
6556 * The metadata register C0 field might be divided into
6557 * source vport index and META item value, we should set
6558 * this field according to specified mask, not as whole one.
6560 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
6562 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
6563 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
6566 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
6569 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
6570 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
6573 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
6574 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
6577 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
6578 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
6581 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
6582 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
6585 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
6586 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
6589 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
6590 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
6593 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
6594 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
6603 * Add MARK item to matcher
6606 * The device to configure through.
6607 * @param[in, out] matcher
6609 * @param[in, out] key
6610 * Flow matcher value.
6612 * Flow pattern to translate.
6615 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
6616 void *matcher, void *key,
6617 const struct rte_flow_item *item)
6619 struct mlx5_priv *priv = dev->data->dev_private;
6620 const struct rte_flow_item_mark *mark;
6624 mark = item->mask ? (const void *)item->mask :
6625 &rte_flow_item_mark_mask;
6626 mask = mark->id & priv->sh->dv_mark_mask;
6627 mark = (const void *)item->spec;
6629 value = mark->id & priv->sh->dv_mark_mask & mask;
6631 enum modify_reg reg;
6633 /* Get the metadata register index for the mark. */
6634 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
6635 MLX5_ASSERT(reg > 0);
6636 if (reg == REG_C_0) {
6637 struct mlx5_priv *priv = dev->data->dev_private;
6638 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6639 uint32_t shl_c0 = rte_bsf32(msk_c0);
6645 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6650 * Add META item to matcher
6653 * The devich to configure through.
6654 * @param[in, out] matcher
6656 * @param[in, out] key
6657 * Flow matcher value.
6659 * Attributes of flow that includes this item.
6661 * Flow pattern to translate.
6664 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
6665 void *matcher, void *key,
6666 const struct rte_flow_attr *attr,
6667 const struct rte_flow_item *item)
6669 const struct rte_flow_item_meta *meta_m;
6670 const struct rte_flow_item_meta *meta_v;
6672 meta_m = (const void *)item->mask;
6674 meta_m = &rte_flow_item_meta_mask;
6675 meta_v = (const void *)item->spec;
6678 uint32_t value = meta_v->data;
6679 uint32_t mask = meta_m->data;
6681 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
6685 * In datapath code there is no endianness
6686 * coversions for perfromance reasons, all
6687 * pattern conversions are done in rte_flow.
6689 value = rte_cpu_to_be_32(value);
6690 mask = rte_cpu_to_be_32(mask);
6691 if (reg == REG_C_0) {
6692 struct mlx5_priv *priv = dev->data->dev_private;
6693 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6694 uint32_t shl_c0 = rte_bsf32(msk_c0);
6695 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
6696 uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
6703 MLX5_ASSERT(msk_c0);
6704 MLX5_ASSERT(!(~msk_c0 & mask));
6706 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6711 * Add vport metadata Reg C0 item to matcher
6713 * @param[in, out] matcher
6715 * @param[in, out] key
6716 * Flow matcher value.
6718 * Flow pattern to translate.
6721 flow_dv_translate_item_meta_vport(void *matcher, void *key,
6722 uint32_t value, uint32_t mask)
6724 flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
6728 * Add tag item to matcher
6731 * The devich to configure through.
6732 * @param[in, out] matcher
6734 * @param[in, out] key
6735 * Flow matcher value.
6737 * Flow pattern to translate.
6740 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
6741 void *matcher, void *key,
6742 const struct rte_flow_item *item)
6744 const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
6745 const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
6746 uint32_t mask, value;
6749 value = tag_v->data;
6750 mask = tag_m ? tag_m->data : UINT32_MAX;
6751 if (tag_v->id == REG_C_0) {
6752 struct mlx5_priv *priv = dev->data->dev_private;
6753 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6754 uint32_t shl_c0 = rte_bsf32(msk_c0);
6760 flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
6764 * Add TAG item to matcher
6767 * The devich to configure through.
6768 * @param[in, out] matcher
6770 * @param[in, out] key
6771 * Flow matcher value.
6773 * Flow pattern to translate.
6776 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
6777 void *matcher, void *key,
6778 const struct rte_flow_item *item)
6780 const struct rte_flow_item_tag *tag_v = item->spec;
6781 const struct rte_flow_item_tag *tag_m = item->mask;
6782 enum modify_reg reg;
6785 tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
6786 /* Get the metadata register index for the tag. */
6787 reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
6788 MLX5_ASSERT(reg > 0);
6789 flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
6793 * Add source vport match to the specified matcher.
6795 * @param[in, out] matcher
6797 * @param[in, out] key
6798 * Flow matcher value.
6800 * Source vport value to match
6805 flow_dv_translate_item_source_vport(void *matcher, void *key,
6806 int16_t port, uint16_t mask)
6808 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6809 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6811 MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
6812 MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
6816 * Translate port-id item to eswitch match on port-id.
6819 * The devich to configure through.
6820 * @param[in, out] matcher
6822 * @param[in, out] key
6823 * Flow matcher value.
6825 * Flow pattern to translate.
6828 * 0 on success, a negative errno value otherwise.
6831 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
6832 void *key, const struct rte_flow_item *item)
6834 const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
6835 const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
6836 struct mlx5_priv *priv;
6839 mask = pid_m ? pid_m->id : 0xffff;
6840 id = pid_v ? pid_v->id : dev->data->port_id;
6841 priv = mlx5_port_to_eswitch_info(id, item == NULL);
6844 /* Translate to vport field or to metadata, depending on mode. */
6845 if (priv->vport_meta_mask)
6846 flow_dv_translate_item_meta_vport(matcher, key,
6847 priv->vport_meta_tag,
6848 priv->vport_meta_mask);
6850 flow_dv_translate_item_source_vport(matcher, key,
6851 priv->vport_id, mask);
6856 * Add ICMP6 item to matcher and to the value.
6858 * @param[in, out] matcher
6860 * @param[in, out] key
6861 * Flow matcher value.
6863 * Flow pattern to translate.
6865 * Item is inner pattern.
6868 flow_dv_translate_item_icmp6(void *matcher, void *key,
6869 const struct rte_flow_item *item,
6872 const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
6873 const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
6876 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
6878 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6880 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6882 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6884 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6886 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6888 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
6889 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
6893 icmp6_m = &rte_flow_item_icmp6_mask;
6895 * Force flow only to match the non-fragmented IPv6 ICMPv6 packets.
6896 * If only the protocol is specified, no need to match the frag.
6898 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
6899 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
6900 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
6901 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
6902 icmp6_v->type & icmp6_m->type);
6903 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
6904 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
6905 icmp6_v->code & icmp6_m->code);
6909 * Add ICMP item to matcher and to the value.
6911 * @param[in, out] matcher
6913 * @param[in, out] key
6914 * Flow matcher value.
6916 * Flow pattern to translate.
6918 * Item is inner pattern.
6921 flow_dv_translate_item_icmp(void *matcher, void *key,
6922 const struct rte_flow_item *item,
6925 const struct rte_flow_item_icmp *icmp_m = item->mask;
6926 const struct rte_flow_item_icmp *icmp_v = item->spec;
6929 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
6931 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6933 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6935 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6937 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6939 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6941 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
6942 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
6946 icmp_m = &rte_flow_item_icmp_mask;
6948 * Force flow only to match the non-fragmented IPv4 ICMP packets.
6949 * If only the protocol is specified, no need to match the frag.
6951 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
6952 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
6953 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
6954 icmp_m->hdr.icmp_type);
6955 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
6956 icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
6957 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
6958 icmp_m->hdr.icmp_code);
6959 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
6960 icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
6964 * Add GTP item to matcher and to the value.
6966 * @param[in, out] matcher
6968 * @param[in, out] key
6969 * Flow matcher value.
6971 * Flow pattern to translate.
6973 * Item is inner pattern.
6976 flow_dv_translate_item_gtp(void *matcher, void *key,
6977 const struct rte_flow_item *item, int inner)
6979 const struct rte_flow_item_gtp *gtp_m = item->mask;
6980 const struct rte_flow_item_gtp *gtp_v = item->spec;
6983 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
6985 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6986 uint16_t dport = RTE_GTPU_UDP_PORT;
6989 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6991 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6993 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6995 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6997 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6998 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6999 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7004 gtp_m = &rte_flow_item_gtp_mask;
7005 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
7006 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
7007 gtp_v->msg_type & gtp_m->msg_type);
7008 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
7009 rte_be_to_cpu_32(gtp_m->teid));
7010 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
7011 rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
7014 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
7016 #define HEADER_IS_ZERO(match_criteria, headers) \
7017 !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
7018 matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
7021 * Calculate flow matcher enable bitmap.
7023 * @param match_criteria
7024 * Pointer to flow matcher criteria.
7027 * Bitmap of enabled fields.
7030 flow_dv_matcher_enable(uint32_t *match_criteria)
7032 uint8_t match_criteria_enable;
7034 match_criteria_enable =
7035 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
7036 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
7037 match_criteria_enable |=
7038 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
7039 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
7040 match_criteria_enable |=
7041 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
7042 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
7043 match_criteria_enable |=
7044 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
7045 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
7046 match_criteria_enable |=
7047 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
7048 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
7049 return match_criteria_enable;
7056 * @param[in, out] dev
7057 * Pointer to rte_eth_dev structure.
7058 * @param[in] table_id
7061 * Direction of the table.
7062 * @param[in] transfer
7063 * E-Switch or NIC flow.
7065 * pointer to error structure.
7068 * Returns tables resource based on the index, NULL in case of failed.
7070 static struct mlx5_flow_tbl_resource *
7071 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
7072 uint32_t table_id, uint8_t egress,
7074 struct rte_flow_error *error)
7076 struct mlx5_priv *priv = dev->data->dev_private;
7077 struct mlx5_ibv_shared *sh = priv->sh;
7078 struct mlx5_flow_tbl_resource *tbl;
7079 union mlx5_flow_tbl_key table_key = {
7081 .table_id = table_id,
7083 .domain = !!transfer,
7084 .direction = !!egress,
7087 struct mlx5_hlist_entry *pos = mlx5_hlist_lookup(sh->flow_tbls,
7089 struct mlx5_flow_tbl_data_entry *tbl_data;
7095 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
7097 tbl = &tbl_data->tbl;
7098 rte_atomic32_inc(&tbl->refcnt);
7101 tbl_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
7103 rte_flow_error_set(error, ENOMEM,
7104 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7106 "cannot allocate flow table data entry");
7109 tbl_data->idx = idx;
7110 tbl = &tbl_data->tbl;
7111 pos = &tbl_data->entry;
7113 domain = sh->fdb_domain;
7115 domain = sh->tx_domain;
7117 domain = sh->rx_domain;
7118 tbl->obj = mlx5_glue->dr_create_flow_tbl(domain, table_id);
7120 rte_flow_error_set(error, ENOMEM,
7121 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7122 NULL, "cannot create flow table object");
7123 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
7127 * No multi-threads now, but still better to initialize the reference
7128 * count before insert it into the hash list.
7130 rte_atomic32_init(&tbl->refcnt);
7131 /* Jump action reference count is initialized here. */
7132 rte_atomic32_init(&tbl_data->jump.refcnt);
7133 pos->key = table_key.v64;
7134 ret = mlx5_hlist_insert(sh->flow_tbls, pos);
7136 rte_flow_error_set(error, -ret,
7137 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7138 "cannot insert flow table data entry");
7139 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
7140 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
7142 rte_atomic32_inc(&tbl->refcnt);
7147 * Release a flow table.
7150 * Pointer to rte_eth_dev structure.
7152 * Table resource to be released.
7155 * Returns 0 if table was released, else return 1;
7158 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
7159 struct mlx5_flow_tbl_resource *tbl)
7161 struct mlx5_priv *priv = dev->data->dev_private;
7162 struct mlx5_ibv_shared *sh = priv->sh;
7163 struct mlx5_flow_tbl_data_entry *tbl_data =
7164 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
7168 if (rte_atomic32_dec_and_test(&tbl->refcnt)) {
7169 struct mlx5_hlist_entry *pos = &tbl_data->entry;
7171 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
7173 /* remove the entry from the hash list and free memory. */
7174 mlx5_hlist_remove(sh->flow_tbls, pos);
7175 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_JUMP],
7183 * Register the flow matcher.
7185 * @param[in, out] dev
7186 * Pointer to rte_eth_dev structure.
7187 * @param[in, out] matcher
7188 * Pointer to flow matcher.
7189 * @param[in, out] key
7190 * Pointer to flow table key.
7191 * @parm[in, out] dev_flow
7192 * Pointer to the dev_flow.
7194 * pointer to error structure.
7197 * 0 on success otherwise -errno and errno is set.
7200 flow_dv_matcher_register(struct rte_eth_dev *dev,
7201 struct mlx5_flow_dv_matcher *matcher,
7202 union mlx5_flow_tbl_key *key,
7203 struct mlx5_flow *dev_flow,
7204 struct rte_flow_error *error)
7206 struct mlx5_priv *priv = dev->data->dev_private;
7207 struct mlx5_ibv_shared *sh = priv->sh;
7208 struct mlx5_flow_dv_matcher *cache_matcher;
7209 struct mlx5dv_flow_matcher_attr dv_attr = {
7210 .type = IBV_FLOW_ATTR_NORMAL,
7211 .match_mask = (void *)&matcher->mask,
7213 struct mlx5_flow_tbl_resource *tbl;
7214 struct mlx5_flow_tbl_data_entry *tbl_data;
7216 tbl = flow_dv_tbl_resource_get(dev, key->table_id, key->direction,
7217 key->domain, error);
7219 return -rte_errno; /* No need to refill the error info */
7220 tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
7221 /* Lookup from cache. */
7222 LIST_FOREACH(cache_matcher, &tbl_data->matchers, next) {
7223 if (matcher->crc == cache_matcher->crc &&
7224 matcher->priority == cache_matcher->priority &&
7225 !memcmp((const void *)matcher->mask.buf,
7226 (const void *)cache_matcher->mask.buf,
7227 cache_matcher->mask.size)) {
7229 "%s group %u priority %hd use %s "
7230 "matcher %p: refcnt %d++",
7231 key->domain ? "FDB" : "NIC", key->table_id,
7232 cache_matcher->priority,
7233 key->direction ? "tx" : "rx",
7234 (void *)cache_matcher,
7235 rte_atomic32_read(&cache_matcher->refcnt));
7236 rte_atomic32_inc(&cache_matcher->refcnt);
7237 dev_flow->handle->dvh.matcher = cache_matcher;
7238 /* old matcher should not make the table ref++. */
7239 flow_dv_tbl_resource_release(dev, tbl);
7243 /* Register new matcher. */
7244 cache_matcher = rte_calloc(__func__, 1, sizeof(*cache_matcher), 0);
7245 if (!cache_matcher) {
7246 flow_dv_tbl_resource_release(dev, tbl);
7247 return rte_flow_error_set(error, ENOMEM,
7248 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7249 "cannot allocate matcher memory");
7251 *cache_matcher = *matcher;
7252 dv_attr.match_criteria_enable =
7253 flow_dv_matcher_enable(cache_matcher->mask.buf);
7254 dv_attr.priority = matcher->priority;
7256 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
7257 cache_matcher->matcher_object =
7258 mlx5_glue->dv_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj);
7259 if (!cache_matcher->matcher_object) {
7260 rte_free(cache_matcher);
7261 #ifdef HAVE_MLX5DV_DR
7262 flow_dv_tbl_resource_release(dev, tbl);
7264 return rte_flow_error_set(error, ENOMEM,
7265 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7266 NULL, "cannot create matcher");
7268 /* Save the table information */
7269 cache_matcher->tbl = tbl;
7270 rte_atomic32_init(&cache_matcher->refcnt);
7271 /* only matcher ref++, table ref++ already done above in get API. */
7272 rte_atomic32_inc(&cache_matcher->refcnt);
7273 LIST_INSERT_HEAD(&tbl_data->matchers, cache_matcher, next);
7274 dev_flow->handle->dvh.matcher = cache_matcher;
7275 DRV_LOG(DEBUG, "%s group %u priority %hd new %s matcher %p: refcnt %d",
7276 key->domain ? "FDB" : "NIC", key->table_id,
7277 cache_matcher->priority,
7278 key->direction ? "tx" : "rx", (void *)cache_matcher,
7279 rte_atomic32_read(&cache_matcher->refcnt));
7284 * Find existing tag resource or create and register a new one.
7286 * @param dev[in, out]
7287 * Pointer to rte_eth_dev structure.
7288 * @param[in, out] tag_be24
7289 * Tag value in big endian then R-shift 8.
7290 * @parm[in, out] dev_flow
7291 * Pointer to the dev_flow.
7293 * pointer to error structure.
7296 * 0 on success otherwise -errno and errno is set.
7299 flow_dv_tag_resource_register
7300 (struct rte_eth_dev *dev,
7302 struct mlx5_flow *dev_flow,
7303 struct rte_flow_error *error)
7305 struct mlx5_priv *priv = dev->data->dev_private;
7306 struct mlx5_ibv_shared *sh = priv->sh;
7307 struct mlx5_flow_dv_tag_resource *cache_resource;
7308 struct mlx5_hlist_entry *entry;
7310 /* Lookup a matching resource from cache. */
7311 entry = mlx5_hlist_lookup(sh->tag_table, (uint64_t)tag_be24);
7313 cache_resource = container_of
7314 (entry, struct mlx5_flow_dv_tag_resource, entry);
7315 rte_atomic32_inc(&cache_resource->refcnt);
7316 dev_flow->handle->dvh.rix_tag = cache_resource->idx;
7317 dev_flow->dv.tag_resource = cache_resource;
7318 DRV_LOG(DEBUG, "cached tag resource %p: refcnt now %d++",
7319 (void *)cache_resource,
7320 rte_atomic32_read(&cache_resource->refcnt));
7323 /* Register new resource. */
7324 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_TAG],
7325 &dev_flow->handle->dvh.rix_tag);
7326 if (!cache_resource)
7327 return rte_flow_error_set(error, ENOMEM,
7328 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7329 "cannot allocate resource memory");
7330 cache_resource->entry.key = (uint64_t)tag_be24;
7331 cache_resource->action = mlx5_glue->dv_create_flow_action_tag(tag_be24);
7332 if (!cache_resource->action) {
7333 rte_free(cache_resource);
7334 return rte_flow_error_set(error, ENOMEM,
7335 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7336 NULL, "cannot create action");
7338 rte_atomic32_init(&cache_resource->refcnt);
7339 rte_atomic32_inc(&cache_resource->refcnt);
7340 if (mlx5_hlist_insert(sh->tag_table, &cache_resource->entry)) {
7341 mlx5_glue->destroy_flow_action(cache_resource->action);
7342 rte_free(cache_resource);
7343 return rte_flow_error_set(error, EEXIST,
7344 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7345 NULL, "cannot insert tag");
7347 dev_flow->dv.tag_resource = cache_resource;
7348 DRV_LOG(DEBUG, "new tag resource %p: refcnt now %d++",
7349 (void *)cache_resource,
7350 rte_atomic32_read(&cache_resource->refcnt));
7358 * Pointer to Ethernet device.
7363 * 1 while a reference on it exists, 0 when freed.
7366 flow_dv_tag_release(struct rte_eth_dev *dev,
7369 struct mlx5_priv *priv = dev->data->dev_private;
7370 struct mlx5_ibv_shared *sh = priv->sh;
7371 struct mlx5_flow_dv_tag_resource *tag;
7373 tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
7376 DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
7377 dev->data->port_id, (void *)tag,
7378 rte_atomic32_read(&tag->refcnt));
7379 if (rte_atomic32_dec_and_test(&tag->refcnt)) {
7380 claim_zero(mlx5_glue->destroy_flow_action(tag->action));
7381 mlx5_hlist_remove(sh->tag_table, &tag->entry);
7382 DRV_LOG(DEBUG, "port %u tag %p: removed",
7383 dev->data->port_id, (void *)tag);
7384 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
7391 * Translate port ID action to vport.
7394 * Pointer to rte_eth_dev structure.
7396 * Pointer to the port ID action.
7397 * @param[out] dst_port_id
7398 * The target port ID.
7400 * Pointer to the error structure.
7403 * 0 on success, a negative errno value otherwise and rte_errno is set.
7406 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
7407 const struct rte_flow_action *action,
7408 uint32_t *dst_port_id,
7409 struct rte_flow_error *error)
7412 struct mlx5_priv *priv;
7413 const struct rte_flow_action_port_id *conf =
7414 (const struct rte_flow_action_port_id *)action->conf;
7416 port = conf->original ? dev->data->port_id : conf->id;
7417 priv = mlx5_port_to_eswitch_info(port, false);
7419 return rte_flow_error_set(error, -rte_errno,
7420 RTE_FLOW_ERROR_TYPE_ACTION,
7422 "No eswitch info was found for port");
7423 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
7425 * This parameter is transferred to
7426 * mlx5dv_dr_action_create_dest_ib_port().
7428 *dst_port_id = priv->ibv_port;
7431 * Legacy mode, no LAG configurations is supported.
7432 * This parameter is transferred to
7433 * mlx5dv_dr_action_create_dest_vport().
7435 *dst_port_id = priv->vport_id;
7441 * Create a counter with aging configuration.
7444 * Pointer to rte_eth_dev structure.
7446 * Pointer to the counter action configuration.
7448 * Pointer to the aging action configuration.
7451 * Index to flow counter on success, 0 otherwise.
7454 flow_dv_translate_create_counter(struct rte_eth_dev *dev,
7455 struct mlx5_flow *dev_flow,
7456 const struct rte_flow_action_count *count,
7457 const struct rte_flow_action_age *age)
7460 struct mlx5_age_param *age_param;
7462 counter = flow_dv_counter_alloc(dev,
7463 count ? count->shared : 0,
7464 count ? count->id : 0,
7465 dev_flow->dv.group, !!age);
7466 if (!counter || age == NULL)
7468 age_param = flow_dv_counter_idx_get_age(dev, counter);
7470 * The counter age accuracy may have a bit delay. Have 3/4
7471 * second bias on the timeount in order to let it age in time.
7473 age_param->context = age->context ? age->context :
7474 (void *)(uintptr_t)(dev_flow->flow_idx);
7476 * The counter age accuracy may have a bit delay. Have 3/4
7477 * second bias on the timeount in order to let it age in time.
7479 age_param->timeout = age->timeout * 10 - MLX5_AGING_TIME_DELAY;
7480 /* Set expire time in unit of 0.1 sec. */
7481 age_param->port_id = dev->data->port_id;
7482 age_param->expire = age_param->timeout +
7483 rte_rdtsc() / (rte_get_tsc_hz() / 10);
7484 rte_atomic16_set(&age_param->state, AGE_CANDIDATE);
7488 * Add Tx queue matcher
7491 * Pointer to the dev struct.
7492 * @param[in, out] matcher
7494 * @param[in, out] key
7495 * Flow matcher value.
7497 * Flow pattern to translate.
7499 * Item is inner pattern.
7502 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
7503 void *matcher, void *key,
7504 const struct rte_flow_item *item)
7506 const struct mlx5_rte_flow_item_tx_queue *queue_m;
7507 const struct mlx5_rte_flow_item_tx_queue *queue_v;
7509 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7511 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7512 struct mlx5_txq_ctrl *txq;
7516 queue_m = (const void *)item->mask;
7519 queue_v = (const void *)item->spec;
7522 txq = mlx5_txq_get(dev, queue_v->queue);
7525 queue = txq->obj->sq->id;
7526 MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
7527 MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
7528 queue & queue_m->queue);
7529 mlx5_txq_release(dev, queue_v->queue);
7533 * Set the hash fields according to the @p flow information.
7535 * @param[in] dev_flow
7536 * Pointer to the mlx5_flow.
7537 * @param[in] rss_desc
7538 * Pointer to the mlx5_flow_rss_desc.
7541 flow_dv_hashfields_set(struct mlx5_flow *dev_flow,
7542 struct mlx5_flow_rss_desc *rss_desc)
7544 uint64_t items = dev_flow->handle->layers;
7546 uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
7548 dev_flow->hash_fields = 0;
7549 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
7550 if (rss_desc->level >= 2) {
7551 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
7555 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
7556 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
7557 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
7558 if (rss_types & ETH_RSS_L3_SRC_ONLY)
7559 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
7560 else if (rss_types & ETH_RSS_L3_DST_ONLY)
7561 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
7563 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
7565 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
7566 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
7567 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
7568 if (rss_types & ETH_RSS_L3_SRC_ONLY)
7569 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
7570 else if (rss_types & ETH_RSS_L3_DST_ONLY)
7571 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
7573 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
7576 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
7577 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
7578 if (rss_types & ETH_RSS_UDP) {
7579 if (rss_types & ETH_RSS_L4_SRC_ONLY)
7580 dev_flow->hash_fields |=
7581 IBV_RX_HASH_SRC_PORT_UDP;
7582 else if (rss_types & ETH_RSS_L4_DST_ONLY)
7583 dev_flow->hash_fields |=
7584 IBV_RX_HASH_DST_PORT_UDP;
7586 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
7588 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
7589 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
7590 if (rss_types & ETH_RSS_TCP) {
7591 if (rss_types & ETH_RSS_L4_SRC_ONLY)
7592 dev_flow->hash_fields |=
7593 IBV_RX_HASH_SRC_PORT_TCP;
7594 else if (rss_types & ETH_RSS_L4_DST_ONLY)
7595 dev_flow->hash_fields |=
7596 IBV_RX_HASH_DST_PORT_TCP;
7598 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
7604 * Fill the flow with DV spec, lock free
7605 * (mutex should be acquired by caller).
7608 * Pointer to rte_eth_dev structure.
7609 * @param[in, out] dev_flow
7610 * Pointer to the sub flow.
7612 * Pointer to the flow attributes.
7614 * Pointer to the list of items.
7615 * @param[in] actions
7616 * Pointer to the list of actions.
7618 * Pointer to the error structure.
7621 * 0 on success, a negative errno value otherwise and rte_errno is set.
7624 __flow_dv_translate(struct rte_eth_dev *dev,
7625 struct mlx5_flow *dev_flow,
7626 const struct rte_flow_attr *attr,
7627 const struct rte_flow_item items[],
7628 const struct rte_flow_action actions[],
7629 struct rte_flow_error *error)
7631 struct mlx5_priv *priv = dev->data->dev_private;
7632 struct mlx5_dev_config *dev_conf = &priv->config;
7633 struct rte_flow *flow = dev_flow->flow;
7634 struct mlx5_flow_handle *handle = dev_flow->handle;
7635 struct mlx5_flow_rss_desc *rss_desc = &((struct mlx5_flow_rss_desc *)
7637 [!!priv->flow_nested_idx];
7638 uint64_t item_flags = 0;
7639 uint64_t last_item = 0;
7640 uint64_t action_flags = 0;
7641 uint64_t priority = attr->priority;
7642 struct mlx5_flow_dv_matcher matcher = {
7644 .size = sizeof(matcher.mask.buf),
7648 bool actions_end = false;
7650 struct mlx5_flow_dv_modify_hdr_resource res;
7651 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
7652 sizeof(struct mlx5_modification_cmd) *
7653 (MLX5_MAX_MODIFY_NUM + 1)];
7655 struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
7656 const struct rte_flow_action_count *count = NULL;
7657 const struct rte_flow_action_age *age = NULL;
7658 union flow_dv_attr flow_attr = { .attr = 0 };
7660 union mlx5_flow_tbl_key tbl_key;
7661 uint32_t modify_action_position = UINT32_MAX;
7662 void *match_mask = matcher.mask.buf;
7663 void *match_value = dev_flow->dv.value.buf;
7664 uint8_t next_protocol = 0xff;
7665 struct rte_vlan_hdr vlan = { 0 };
7669 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
7670 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
7671 ret = mlx5_flow_group_to_table(attr, dev_flow->external, attr->group,
7672 !!priv->fdb_def_rule, &table, error);
7675 dev_flow->dv.group = table;
7677 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
7678 if (priority == MLX5_FLOW_PRIO_RSVD)
7679 priority = dev_conf->flow_prio - 1;
7680 /* number of actions must be set to 0 in case of dirty stack. */
7681 mhdr_res->actions_num = 0;
7682 for (; !actions_end ; actions++) {
7683 const struct rte_flow_action_queue *queue;
7684 const struct rte_flow_action_rss *rss;
7685 const struct rte_flow_action *action = actions;
7686 const uint8_t *rss_key;
7687 const struct rte_flow_action_jump *jump_data;
7688 const struct rte_flow_action_meter *mtr;
7689 struct mlx5_flow_tbl_resource *tbl;
7690 uint32_t port_id = 0;
7691 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
7692 int action_type = actions->type;
7693 const struct rte_flow_action *found_action = NULL;
7694 struct mlx5_flow_meter *fm = NULL;
7696 switch (action_type) {
7697 case RTE_FLOW_ACTION_TYPE_VOID:
7699 case RTE_FLOW_ACTION_TYPE_PORT_ID:
7700 if (flow_dv_translate_action_port_id(dev, action,
7703 memset(&port_id_resource, 0, sizeof(port_id_resource));
7704 port_id_resource.port_id = port_id;
7705 if (flow_dv_port_id_action_resource_register
7706 (dev, &port_id_resource, dev_flow, error))
7708 MLX5_ASSERT(!handle->rix_port_id_action);
7709 dev_flow->dv.actions[actions_n++] =
7710 dev_flow->dv.port_id_action->action;
7711 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
7712 dev_flow->handle->fate_action = MLX5_FLOW_FATE_PORT_ID;
7714 case RTE_FLOW_ACTION_TYPE_FLAG:
7715 action_flags |= MLX5_FLOW_ACTION_FLAG;
7716 dev_flow->handle->mark = 1;
7717 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7718 struct rte_flow_action_mark mark = {
7719 .id = MLX5_FLOW_MARK_DEFAULT,
7722 if (flow_dv_convert_action_mark(dev, &mark,
7726 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
7729 tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
7731 * Only one FLAG or MARK is supported per device flow
7732 * right now. So the pointer to the tag resource must be
7733 * zero before the register process.
7735 MLX5_ASSERT(!handle->dvh.rix_tag);
7736 if (flow_dv_tag_resource_register(dev, tag_be,
7739 MLX5_ASSERT(dev_flow->dv.tag_resource);
7740 dev_flow->dv.actions[actions_n++] =
7741 dev_flow->dv.tag_resource->action;
7743 case RTE_FLOW_ACTION_TYPE_MARK:
7744 action_flags |= MLX5_FLOW_ACTION_MARK;
7745 dev_flow->handle->mark = 1;
7746 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7747 const struct rte_flow_action_mark *mark =
7748 (const struct rte_flow_action_mark *)
7751 if (flow_dv_convert_action_mark(dev, mark,
7755 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
7759 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
7760 /* Legacy (non-extensive) MARK action. */
7761 tag_be = mlx5_flow_mark_set
7762 (((const struct rte_flow_action_mark *)
7763 (actions->conf))->id);
7764 MLX5_ASSERT(!handle->dvh.rix_tag);
7765 if (flow_dv_tag_resource_register(dev, tag_be,
7768 MLX5_ASSERT(dev_flow->dv.tag_resource);
7769 dev_flow->dv.actions[actions_n++] =
7770 dev_flow->dv.tag_resource->action;
7772 case RTE_FLOW_ACTION_TYPE_SET_META:
7773 if (flow_dv_convert_action_set_meta
7774 (dev, mhdr_res, attr,
7775 (const struct rte_flow_action_set_meta *)
7776 actions->conf, error))
7778 action_flags |= MLX5_FLOW_ACTION_SET_META;
7780 case RTE_FLOW_ACTION_TYPE_SET_TAG:
7781 if (flow_dv_convert_action_set_tag
7783 (const struct rte_flow_action_set_tag *)
7784 actions->conf, error))
7786 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7788 case RTE_FLOW_ACTION_TYPE_DROP:
7789 action_flags |= MLX5_FLOW_ACTION_DROP;
7790 dev_flow->handle->fate_action = MLX5_FLOW_FATE_DROP;
7792 case RTE_FLOW_ACTION_TYPE_QUEUE:
7793 queue = actions->conf;
7794 rss_desc->queue_num = 1;
7795 rss_desc->queue[0] = queue->index;
7796 action_flags |= MLX5_FLOW_ACTION_QUEUE;
7797 dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
7799 case RTE_FLOW_ACTION_TYPE_RSS:
7800 rss = actions->conf;
7801 memcpy(rss_desc->queue, rss->queue,
7802 rss->queue_num * sizeof(uint16_t));
7803 rss_desc->queue_num = rss->queue_num;
7804 /* NULL RSS key indicates default RSS key. */
7805 rss_key = !rss->key ? rss_hash_default_key : rss->key;
7806 memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
7808 * rss->level and rss.types should be set in advance
7809 * when expanding items for RSS.
7811 action_flags |= MLX5_FLOW_ACTION_RSS;
7812 dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
7814 case RTE_FLOW_ACTION_TYPE_AGE:
7815 case RTE_FLOW_ACTION_TYPE_COUNT:
7816 if (!dev_conf->devx) {
7817 return rte_flow_error_set
7819 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7821 "count action not supported");
7823 /* Save information first, will apply later. */
7824 if (actions->type == RTE_FLOW_ACTION_TYPE_COUNT)
7825 count = action->conf;
7828 action_flags |= MLX5_FLOW_ACTION_COUNT;
7830 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
7831 dev_flow->dv.actions[actions_n++] =
7832 priv->sh->pop_vlan_action;
7833 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
7835 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
7836 if (!(action_flags &
7837 MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
7838 flow_dev_get_vlan_info_from_items(items, &vlan);
7839 vlan.eth_proto = rte_be_to_cpu_16
7840 ((((const struct rte_flow_action_of_push_vlan *)
7841 actions->conf)->ethertype));
7842 found_action = mlx5_flow_find_action
7844 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
7846 mlx5_update_vlan_vid_pcp(found_action, &vlan);
7847 found_action = mlx5_flow_find_action
7849 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
7851 mlx5_update_vlan_vid_pcp(found_action, &vlan);
7852 if (flow_dv_create_action_push_vlan
7853 (dev, attr, &vlan, dev_flow, error))
7855 dev_flow->dv.actions[actions_n++] =
7856 dev_flow->dv.push_vlan_res->action;
7857 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
7859 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
7860 /* of_vlan_push action handled this action */
7861 MLX5_ASSERT(action_flags &
7862 MLX5_FLOW_ACTION_OF_PUSH_VLAN);
7864 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
7865 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
7867 flow_dev_get_vlan_info_from_items(items, &vlan);
7868 mlx5_update_vlan_vid_pcp(actions, &vlan);
7869 /* If no VLAN push - this is a modify header action */
7870 if (flow_dv_convert_action_modify_vlan_vid
7871 (mhdr_res, actions, error))
7873 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
7875 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
7876 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
7877 if (flow_dv_create_action_l2_encap(dev, actions,
7882 dev_flow->dv.actions[actions_n++] =
7883 dev_flow->dv.encap_decap->verbs_action;
7884 action_flags |= MLX5_FLOW_ACTION_ENCAP;
7886 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
7887 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
7888 if (flow_dv_create_action_l2_decap(dev, dev_flow,
7892 dev_flow->dv.actions[actions_n++] =
7893 dev_flow->dv.encap_decap->verbs_action;
7894 action_flags |= MLX5_FLOW_ACTION_DECAP;
7896 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
7897 /* Handle encap with preceding decap. */
7898 if (action_flags & MLX5_FLOW_ACTION_DECAP) {
7899 if (flow_dv_create_action_raw_encap
7900 (dev, actions, dev_flow, attr, error))
7902 dev_flow->dv.actions[actions_n++] =
7903 dev_flow->dv.encap_decap->verbs_action;
7905 /* Handle encap without preceding decap. */
7906 if (flow_dv_create_action_l2_encap
7907 (dev, actions, dev_flow, attr->transfer,
7910 dev_flow->dv.actions[actions_n++] =
7911 dev_flow->dv.encap_decap->verbs_action;
7913 action_flags |= MLX5_FLOW_ACTION_ENCAP;
7915 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
7916 while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
7918 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
7919 if (flow_dv_create_action_l2_decap
7920 (dev, dev_flow, attr->transfer, error))
7922 dev_flow->dv.actions[actions_n++] =
7923 dev_flow->dv.encap_decap->verbs_action;
7925 /* If decap is followed by encap, handle it at encap. */
7926 action_flags |= MLX5_FLOW_ACTION_DECAP;
7928 case RTE_FLOW_ACTION_TYPE_JUMP:
7929 jump_data = action->conf;
7930 ret = mlx5_flow_group_to_table(attr, dev_flow->external,
7932 !!priv->fdb_def_rule,
7936 tbl = flow_dv_tbl_resource_get(dev, table,
7938 attr->transfer, error);
7940 return rte_flow_error_set
7942 RTE_FLOW_ERROR_TYPE_ACTION,
7944 "cannot create jump action.");
7945 if (flow_dv_jump_tbl_resource_register
7946 (dev, tbl, dev_flow, error)) {
7947 flow_dv_tbl_resource_release(dev, tbl);
7948 return rte_flow_error_set
7950 RTE_FLOW_ERROR_TYPE_ACTION,
7952 "cannot create jump action.");
7954 dev_flow->dv.actions[actions_n++] =
7955 dev_flow->dv.jump->action;
7956 action_flags |= MLX5_FLOW_ACTION_JUMP;
7957 dev_flow->handle->fate_action = MLX5_FLOW_FATE_JUMP;
7959 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
7960 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
7961 if (flow_dv_convert_action_modify_mac
7962 (mhdr_res, actions, error))
7964 action_flags |= actions->type ==
7965 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
7966 MLX5_FLOW_ACTION_SET_MAC_SRC :
7967 MLX5_FLOW_ACTION_SET_MAC_DST;
7969 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
7970 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
7971 if (flow_dv_convert_action_modify_ipv4
7972 (mhdr_res, actions, error))
7974 action_flags |= actions->type ==
7975 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
7976 MLX5_FLOW_ACTION_SET_IPV4_SRC :
7977 MLX5_FLOW_ACTION_SET_IPV4_DST;
7979 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
7980 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
7981 if (flow_dv_convert_action_modify_ipv6
7982 (mhdr_res, actions, error))
7984 action_flags |= actions->type ==
7985 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
7986 MLX5_FLOW_ACTION_SET_IPV6_SRC :
7987 MLX5_FLOW_ACTION_SET_IPV6_DST;
7989 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
7990 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
7991 if (flow_dv_convert_action_modify_tp
7992 (mhdr_res, actions, items,
7993 &flow_attr, dev_flow, !!(action_flags &
7994 MLX5_FLOW_ACTION_DECAP), error))
7996 action_flags |= actions->type ==
7997 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
7998 MLX5_FLOW_ACTION_SET_TP_SRC :
7999 MLX5_FLOW_ACTION_SET_TP_DST;
8001 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
8002 if (flow_dv_convert_action_modify_dec_ttl
8003 (mhdr_res, items, &flow_attr, dev_flow,
8005 MLX5_FLOW_ACTION_DECAP), error))
8007 action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
8009 case RTE_FLOW_ACTION_TYPE_SET_TTL:
8010 if (flow_dv_convert_action_modify_ttl
8011 (mhdr_res, actions, items, &flow_attr,
8012 dev_flow, !!(action_flags &
8013 MLX5_FLOW_ACTION_DECAP), error))
8015 action_flags |= MLX5_FLOW_ACTION_SET_TTL;
8017 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
8018 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
8019 if (flow_dv_convert_action_modify_tcp_seq
8020 (mhdr_res, actions, error))
8022 action_flags |= actions->type ==
8023 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
8024 MLX5_FLOW_ACTION_INC_TCP_SEQ :
8025 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
8028 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
8029 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
8030 if (flow_dv_convert_action_modify_tcp_ack
8031 (mhdr_res, actions, error))
8033 action_flags |= actions->type ==
8034 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
8035 MLX5_FLOW_ACTION_INC_TCP_ACK :
8036 MLX5_FLOW_ACTION_DEC_TCP_ACK;
8038 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
8039 if (flow_dv_convert_action_set_reg
8040 (mhdr_res, actions, error))
8042 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
8044 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
8045 if (flow_dv_convert_action_copy_mreg
8046 (dev, mhdr_res, actions, error))
8048 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
8050 case RTE_FLOW_ACTION_TYPE_METER:
8051 mtr = actions->conf;
8053 fm = mlx5_flow_meter_attach(priv, mtr->mtr_id,
8056 return rte_flow_error_set(error,
8058 RTE_FLOW_ERROR_TYPE_ACTION,
8061 "or invalid parameters");
8062 flow->meter = fm->idx;
8064 /* Set the meter action. */
8066 fm = mlx5_ipool_get(priv->sh->ipool
8067 [MLX5_IPOOL_MTR], flow->meter);
8069 return rte_flow_error_set(error,
8071 RTE_FLOW_ERROR_TYPE_ACTION,
8074 "or invalid parameters");
8076 dev_flow->dv.actions[actions_n++] =
8077 fm->mfts->meter_action;
8078 action_flags |= MLX5_FLOW_ACTION_METER;
8080 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
8081 if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
8084 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
8086 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
8087 if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
8090 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
8092 case RTE_FLOW_ACTION_TYPE_END:
8094 if (mhdr_res->actions_num) {
8095 /* create modify action if needed. */
8096 if (flow_dv_modify_hdr_resource_register
8097 (dev, mhdr_res, dev_flow, error))
8099 dev_flow->dv.actions[modify_action_position] =
8100 handle->dvh.modify_hdr->verbs_action;
8102 if (action_flags & MLX5_FLOW_ACTION_COUNT) {
8104 flow_dv_translate_create_counter(dev,
8105 dev_flow, count, age);
8108 return rte_flow_error_set
8110 RTE_FLOW_ERROR_TYPE_ACTION,
8112 "cannot create counter"
8114 dev_flow->dv.actions[actions_n++] =
8115 (flow_dv_counter_get_by_idx(dev,
8116 flow->counter, NULL))->action;
8122 if (mhdr_res->actions_num &&
8123 modify_action_position == UINT32_MAX)
8124 modify_action_position = actions_n++;
8126 dev_flow->dv.actions_n = actions_n;
8127 dev_flow->act_flags = action_flags;
8128 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
8129 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
8130 int item_type = items->type;
8132 switch (item_type) {
8133 case RTE_FLOW_ITEM_TYPE_PORT_ID:
8134 flow_dv_translate_item_port_id(dev, match_mask,
8135 match_value, items);
8136 last_item = MLX5_FLOW_ITEM_PORT_ID;
8138 case RTE_FLOW_ITEM_TYPE_ETH:
8139 flow_dv_translate_item_eth(match_mask, match_value,
8141 matcher.priority = MLX5_PRIORITY_MAP_L2;
8142 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
8143 MLX5_FLOW_LAYER_OUTER_L2;
8145 case RTE_FLOW_ITEM_TYPE_VLAN:
8146 flow_dv_translate_item_vlan(dev_flow,
8147 match_mask, match_value,
8149 matcher.priority = MLX5_PRIORITY_MAP_L2;
8150 last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
8151 MLX5_FLOW_LAYER_INNER_VLAN) :
8152 (MLX5_FLOW_LAYER_OUTER_L2 |
8153 MLX5_FLOW_LAYER_OUTER_VLAN);
8155 case RTE_FLOW_ITEM_TYPE_IPV4:
8156 mlx5_flow_tunnel_ip_check(items, next_protocol,
8157 &item_flags, &tunnel);
8158 flow_dv_translate_item_ipv4(match_mask, match_value,
8159 items, item_flags, tunnel,
8160 dev_flow->dv.group);
8161 matcher.priority = MLX5_PRIORITY_MAP_L3;
8162 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
8163 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
8164 if (items->mask != NULL &&
8165 ((const struct rte_flow_item_ipv4 *)
8166 items->mask)->hdr.next_proto_id) {
8168 ((const struct rte_flow_item_ipv4 *)
8169 (items->spec))->hdr.next_proto_id;
8171 ((const struct rte_flow_item_ipv4 *)
8172 (items->mask))->hdr.next_proto_id;
8174 /* Reset for inner layer. */
8175 next_protocol = 0xff;
8178 case RTE_FLOW_ITEM_TYPE_IPV6:
8179 mlx5_flow_tunnel_ip_check(items, next_protocol,
8180 &item_flags, &tunnel);
8181 flow_dv_translate_item_ipv6(match_mask, match_value,
8182 items, item_flags, tunnel,
8183 dev_flow->dv.group);
8184 matcher.priority = MLX5_PRIORITY_MAP_L3;
8185 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
8186 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
8187 if (items->mask != NULL &&
8188 ((const struct rte_flow_item_ipv6 *)
8189 items->mask)->hdr.proto) {
8191 ((const struct rte_flow_item_ipv6 *)
8192 items->spec)->hdr.proto;
8194 ((const struct rte_flow_item_ipv6 *)
8195 items->mask)->hdr.proto;
8197 /* Reset for inner layer. */
8198 next_protocol = 0xff;
8201 case RTE_FLOW_ITEM_TYPE_TCP:
8202 flow_dv_translate_item_tcp(match_mask, match_value,
8204 matcher.priority = MLX5_PRIORITY_MAP_L4;
8205 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
8206 MLX5_FLOW_LAYER_OUTER_L4_TCP;
8208 case RTE_FLOW_ITEM_TYPE_UDP:
8209 flow_dv_translate_item_udp(match_mask, match_value,
8211 matcher.priority = MLX5_PRIORITY_MAP_L4;
8212 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
8213 MLX5_FLOW_LAYER_OUTER_L4_UDP;
8215 case RTE_FLOW_ITEM_TYPE_GRE:
8216 flow_dv_translate_item_gre(match_mask, match_value,
8218 matcher.priority = rss_desc->level >= 2 ?
8219 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8220 last_item = MLX5_FLOW_LAYER_GRE;
8222 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
8223 flow_dv_translate_item_gre_key(match_mask,
8224 match_value, items);
8225 last_item = MLX5_FLOW_LAYER_GRE_KEY;
8227 case RTE_FLOW_ITEM_TYPE_NVGRE:
8228 flow_dv_translate_item_nvgre(match_mask, match_value,
8230 matcher.priority = rss_desc->level >= 2 ?
8231 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8232 last_item = MLX5_FLOW_LAYER_GRE;
8234 case RTE_FLOW_ITEM_TYPE_VXLAN:
8235 flow_dv_translate_item_vxlan(match_mask, match_value,
8237 matcher.priority = rss_desc->level >= 2 ?
8238 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8239 last_item = MLX5_FLOW_LAYER_VXLAN;
8241 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
8242 flow_dv_translate_item_vxlan_gpe(match_mask,
8245 matcher.priority = rss_desc->level >= 2 ?
8246 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8247 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
8249 case RTE_FLOW_ITEM_TYPE_GENEVE:
8250 flow_dv_translate_item_geneve(match_mask, match_value,
8252 matcher.priority = rss_desc->level >= 2 ?
8253 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8254 last_item = MLX5_FLOW_LAYER_GENEVE;
8256 case RTE_FLOW_ITEM_TYPE_MPLS:
8257 flow_dv_translate_item_mpls(match_mask, match_value,
8258 items, last_item, tunnel);
8259 matcher.priority = rss_desc->level >= 2 ?
8260 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8261 last_item = MLX5_FLOW_LAYER_MPLS;
8263 case RTE_FLOW_ITEM_TYPE_MARK:
8264 flow_dv_translate_item_mark(dev, match_mask,
8265 match_value, items);
8266 last_item = MLX5_FLOW_ITEM_MARK;
8268 case RTE_FLOW_ITEM_TYPE_META:
8269 flow_dv_translate_item_meta(dev, match_mask,
8270 match_value, attr, items);
8271 last_item = MLX5_FLOW_ITEM_METADATA;
8273 case RTE_FLOW_ITEM_TYPE_ICMP:
8274 flow_dv_translate_item_icmp(match_mask, match_value,
8276 last_item = MLX5_FLOW_LAYER_ICMP;
8278 case RTE_FLOW_ITEM_TYPE_ICMP6:
8279 flow_dv_translate_item_icmp6(match_mask, match_value,
8281 last_item = MLX5_FLOW_LAYER_ICMP6;
8283 case RTE_FLOW_ITEM_TYPE_TAG:
8284 flow_dv_translate_item_tag(dev, match_mask,
8285 match_value, items);
8286 last_item = MLX5_FLOW_ITEM_TAG;
8288 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
8289 flow_dv_translate_mlx5_item_tag(dev, match_mask,
8290 match_value, items);
8291 last_item = MLX5_FLOW_ITEM_TAG;
8293 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
8294 flow_dv_translate_item_tx_queue(dev, match_mask,
8297 last_item = MLX5_FLOW_ITEM_TX_QUEUE;
8299 case RTE_FLOW_ITEM_TYPE_GTP:
8300 flow_dv_translate_item_gtp(match_mask, match_value,
8302 matcher.priority = rss_desc->level >= 2 ?
8303 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8304 last_item = MLX5_FLOW_LAYER_GTP;
8309 item_flags |= last_item;
8312 * When E-Switch mode is enabled, we have two cases where we need to
8313 * set the source port manually.
8314 * The first one, is in case of Nic steering rule, and the second is
8315 * E-Switch rule where no port_id item was found. In both cases
8316 * the source port is set according the current port in use.
8318 if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
8319 (priv->representor || priv->master)) {
8320 if (flow_dv_translate_item_port_id(dev, match_mask,
8324 #ifdef RTE_LIBRTE_MLX5_DEBUG
8325 MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
8326 dev_flow->dv.value.buf));
8329 * Layers may be already initialized from prefix flow if this dev_flow
8330 * is the suffix flow.
8332 handle->layers |= item_flags;
8333 if (action_flags & MLX5_FLOW_ACTION_RSS)
8334 flow_dv_hashfields_set(dev_flow, rss_desc);
8335 /* Register matcher. */
8336 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
8338 matcher.priority = mlx5_flow_adjust_priority(dev, priority,
8340 /* reserved field no needs to be set to 0 here. */
8341 tbl_key.domain = attr->transfer;
8342 tbl_key.direction = attr->egress;
8343 tbl_key.table_id = dev_flow->dv.group;
8344 if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow, error))
8350 * Apply the flow to the NIC, lock free,
8351 * (mutex should be acquired by caller).
8354 * Pointer to the Ethernet device structure.
8355 * @param[in, out] flow
8356 * Pointer to flow structure.
8358 * Pointer to error structure.
8361 * 0 on success, a negative errno value otherwise and rte_errno is set.
8364 __flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
8365 struct rte_flow_error *error)
8367 struct mlx5_flow_dv_workspace *dv;
8368 struct mlx5_flow_handle *dh;
8369 struct mlx5_flow_handle_dv *dv_h;
8370 struct mlx5_flow *dev_flow;
8371 struct mlx5_priv *priv = dev->data->dev_private;
8372 uint32_t handle_idx;
8377 for (idx = priv->flow_idx - 1; idx >= priv->flow_nested_idx; idx--) {
8378 dev_flow = &((struct mlx5_flow *)priv->inter_flows)[idx];
8380 dh = dev_flow->handle;
8383 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
8385 dv->actions[n++] = priv->sh->esw_drop_action;
8387 struct mlx5_hrxq *drop_hrxq;
8388 drop_hrxq = mlx5_hrxq_drop_new(dev);
8392 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8394 "cannot get drop hash queue");
8398 * Drop queues will be released by the specify
8399 * mlx5_hrxq_drop_release() function. Assign
8400 * the special index to hrxq to mark the queue
8401 * has been allocated.
8403 dh->rix_hrxq = UINT32_MAX;
8404 dv->actions[n++] = drop_hrxq->action;
8406 } else if (dh->fate_action == MLX5_FLOW_FATE_QUEUE) {
8407 struct mlx5_hrxq *hrxq;
8409 struct mlx5_flow_rss_desc *rss_desc =
8410 &((struct mlx5_flow_rss_desc *)priv->rss_desc)
8411 [!!priv->flow_nested_idx];
8413 MLX5_ASSERT(rss_desc->queue_num);
8414 hrxq_idx = mlx5_hrxq_get(dev, rss_desc->key,
8415 MLX5_RSS_HASH_KEY_LEN,
8416 dev_flow->hash_fields,
8418 rss_desc->queue_num);
8420 hrxq_idx = mlx5_hrxq_new
8421 (dev, rss_desc->key,
8422 MLX5_RSS_HASH_KEY_LEN,
8423 dev_flow->hash_fields,
8425 rss_desc->queue_num,
8427 MLX5_FLOW_LAYER_TUNNEL));
8429 hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
8434 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8435 "cannot get hash queue");
8438 dh->rix_hrxq = hrxq_idx;
8439 dv->actions[n++] = hrxq->action;
8442 mlx5_glue->dv_create_flow(dv_h->matcher->matcher_object,
8443 (void *)&dv->value, n,
8446 rte_flow_error_set(error, errno,
8447 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8449 "hardware refuses to create flow");
8452 if (priv->vmwa_context &&
8453 dh->vf_vlan.tag && !dh->vf_vlan.created) {
8455 * The rule contains the VLAN pattern.
8456 * For VF we are going to create VLAN
8457 * interface to make hypervisor set correct
8458 * e-Switch vport context.
8460 mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
8465 err = rte_errno; /* Save rte_errno before cleanup. */
8466 SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles,
8467 handle_idx, dh, next) {
8468 /* hrxq is union, don't clear it if the flag is not set. */
8470 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
8471 mlx5_hrxq_drop_release(dev);
8473 } else if (dh->fate_action == MLX5_FLOW_FATE_QUEUE) {
8474 mlx5_hrxq_release(dev, dh->rix_hrxq);
8478 if (dh->vf_vlan.tag && dh->vf_vlan.created)
8479 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
8481 rte_errno = err; /* Restore rte_errno. */
8486 * Release the flow matcher.
8489 * Pointer to Ethernet device.
8491 * Pointer to mlx5_flow_handle.
8494 * 1 while a reference on it exists, 0 when freed.
8497 flow_dv_matcher_release(struct rte_eth_dev *dev,
8498 struct mlx5_flow_handle *handle)
8500 struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
8502 MLX5_ASSERT(matcher->matcher_object);
8503 DRV_LOG(DEBUG, "port %u matcher %p: refcnt %d--",
8504 dev->data->port_id, (void *)matcher,
8505 rte_atomic32_read(&matcher->refcnt));
8506 if (rte_atomic32_dec_and_test(&matcher->refcnt)) {
8507 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8508 (matcher->matcher_object));
8509 LIST_REMOVE(matcher, next);
8510 /* table ref-- in release interface. */
8511 flow_dv_tbl_resource_release(dev, matcher->tbl);
8513 DRV_LOG(DEBUG, "port %u matcher %p: removed",
8514 dev->data->port_id, (void *)matcher);
8521 * Release an encap/decap resource.
8524 * Pointer to Ethernet device.
8526 * Pointer to mlx5_flow_handle.
8529 * 1 while a reference on it exists, 0 when freed.
8532 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
8533 struct mlx5_flow_handle *handle)
8535 struct mlx5_priv *priv = dev->data->dev_private;
8536 uint32_t idx = handle->dvh.rix_encap_decap;
8537 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
8539 cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
8541 if (!cache_resource)
8543 MLX5_ASSERT(cache_resource->verbs_action);
8544 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d--",
8545 (void *)cache_resource,
8546 rte_atomic32_read(&cache_resource->refcnt));
8547 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8548 claim_zero(mlx5_glue->destroy_flow_action
8549 (cache_resource->verbs_action));
8550 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
8551 &priv->sh->encaps_decaps, idx,
8552 cache_resource, next);
8553 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);
8554 DRV_LOG(DEBUG, "encap/decap resource %p: removed",
8555 (void *)cache_resource);
8562 * Release an jump to table action resource.
8565 * Pointer to Ethernet device.
8567 * Pointer to mlx5_flow_handle.
8570 * 1 while a reference on it exists, 0 when freed.
8573 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
8574 struct mlx5_flow_handle *handle)
8576 struct mlx5_priv *priv = dev->data->dev_private;
8577 struct mlx5_flow_dv_jump_tbl_resource *cache_resource;
8578 struct mlx5_flow_tbl_data_entry *tbl_data;
8580 tbl_data = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_JUMP],
8584 cache_resource = &tbl_data->jump;
8585 MLX5_ASSERT(cache_resource->action);
8586 DRV_LOG(DEBUG, "jump table resource %p: refcnt %d--",
8587 (void *)cache_resource,
8588 rte_atomic32_read(&cache_resource->refcnt));
8589 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8590 claim_zero(mlx5_glue->destroy_flow_action
8591 (cache_resource->action));
8592 /* jump action memory free is inside the table release. */
8593 flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
8594 DRV_LOG(DEBUG, "jump table resource %p: removed",
8595 (void *)cache_resource);
8602 * Release a modify-header resource.
8605 * Pointer to mlx5_flow_handle.
8608 * 1 while a reference on it exists, 0 when freed.
8611 flow_dv_modify_hdr_resource_release(struct mlx5_flow_handle *handle)
8613 struct mlx5_flow_dv_modify_hdr_resource *cache_resource =
8614 handle->dvh.modify_hdr;
8616 MLX5_ASSERT(cache_resource->verbs_action);
8617 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d--",
8618 (void *)cache_resource,
8619 rte_atomic32_read(&cache_resource->refcnt));
8620 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8621 claim_zero(mlx5_glue->destroy_flow_action
8622 (cache_resource->verbs_action));
8623 LIST_REMOVE(cache_resource, next);
8624 rte_free(cache_resource);
8625 DRV_LOG(DEBUG, "modify-header resource %p: removed",
8626 (void *)cache_resource);
8633 * Release port ID action resource.
8636 * Pointer to Ethernet device.
8638 * Pointer to mlx5_flow_handle.
8641 * 1 while a reference on it exists, 0 when freed.
8644 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
8645 struct mlx5_flow_handle *handle)
8647 struct mlx5_priv *priv = dev->data->dev_private;
8648 struct mlx5_flow_dv_port_id_action_resource *cache_resource;
8649 uint32_t idx = handle->rix_port_id_action;
8651 cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID],
8653 if (!cache_resource)
8655 MLX5_ASSERT(cache_resource->action);
8656 DRV_LOG(DEBUG, "port ID action resource %p: refcnt %d--",
8657 (void *)cache_resource,
8658 rte_atomic32_read(&cache_resource->refcnt));
8659 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8660 claim_zero(mlx5_glue->destroy_flow_action
8661 (cache_resource->action));
8662 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_PORT_ID],
8663 &priv->sh->port_id_action_list, idx,
8664 cache_resource, next);
8665 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_PORT_ID], idx);
8666 DRV_LOG(DEBUG, "port id action resource %p: removed",
8667 (void *)cache_resource);
8674 * Release push vlan action resource.
8677 * Pointer to Ethernet device.
8679 * Pointer to mlx5_flow_handle.
8682 * 1 while a reference on it exists, 0 when freed.
8685 flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,
8686 struct mlx5_flow_handle *handle)
8688 struct mlx5_priv *priv = dev->data->dev_private;
8689 uint32_t idx = handle->dvh.rix_push_vlan;
8690 struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
8692 cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN],
8694 if (!cache_resource)
8696 MLX5_ASSERT(cache_resource->action);
8697 DRV_LOG(DEBUG, "push VLAN action resource %p: refcnt %d--",
8698 (void *)cache_resource,
8699 rte_atomic32_read(&cache_resource->refcnt));
8700 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8701 claim_zero(mlx5_glue->destroy_flow_action
8702 (cache_resource->action));
8703 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN],
8704 &priv->sh->push_vlan_action_list, idx,
8705 cache_resource, next);
8706 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
8707 DRV_LOG(DEBUG, "push vlan action resource %p: removed",
8708 (void *)cache_resource);
8715 * Release the fate resource.
8718 * Pointer to Ethernet device.
8720 * Pointer to mlx5_flow_handle.
8723 flow_dv_fate_resource_release(struct rte_eth_dev *dev,
8724 struct mlx5_flow_handle *handle)
8726 if (!handle->rix_fate)
8728 if (handle->fate_action == MLX5_FLOW_FATE_DROP)
8729 mlx5_hrxq_drop_release(dev);
8730 else if (handle->fate_action == MLX5_FLOW_FATE_QUEUE)
8731 mlx5_hrxq_release(dev, handle->rix_hrxq);
8732 else if (handle->fate_action == MLX5_FLOW_FATE_JUMP)
8733 flow_dv_jump_tbl_resource_release(dev, handle);
8734 else if (handle->fate_action == MLX5_FLOW_FATE_PORT_ID)
8735 flow_dv_port_id_action_resource_release(dev, handle);
8737 DRV_LOG(DEBUG, "Incorrect fate action:%d", handle->fate_action);
8738 handle->rix_fate = 0;
8742 * Remove the flow from the NIC but keeps it in memory.
8743 * Lock free, (mutex should be acquired by caller).
8746 * Pointer to Ethernet device.
8747 * @param[in, out] flow
8748 * Pointer to flow structure.
8751 __flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
8753 struct mlx5_flow_handle *dh;
8754 uint32_t handle_idx;
8755 struct mlx5_priv *priv = dev->data->dev_private;
8759 handle_idx = flow->dev_handles;
8760 while (handle_idx) {
8761 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
8766 claim_zero(mlx5_glue->dv_destroy_flow(dh->ib_flow));
8769 if (dh->fate_action == MLX5_FLOW_FATE_DROP ||
8770 dh->fate_action == MLX5_FLOW_FATE_QUEUE)
8771 flow_dv_fate_resource_release(dev, dh);
8772 if (dh->vf_vlan.tag && dh->vf_vlan.created)
8773 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
8774 handle_idx = dh->next.next;
8779 * Remove the flow from the NIC and the memory.
8780 * Lock free, (mutex should be acquired by caller).
8783 * Pointer to the Ethernet device structure.
8784 * @param[in, out] flow
8785 * Pointer to flow structure.
8788 __flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
8790 struct mlx5_flow_handle *dev_handle;
8791 struct mlx5_priv *priv = dev->data->dev_private;
8795 __flow_dv_remove(dev, flow);
8796 if (flow->counter) {
8797 flow_dv_counter_release(dev, flow->counter);
8801 struct mlx5_flow_meter *fm;
8803 fm = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MTR],
8806 mlx5_flow_meter_detach(fm);
8809 while (flow->dev_handles) {
8810 uint32_t tmp_idx = flow->dev_handles;
8812 dev_handle = mlx5_ipool_get(priv->sh->ipool
8813 [MLX5_IPOOL_MLX5_FLOW], tmp_idx);
8816 flow->dev_handles = dev_handle->next.next;
8817 if (dev_handle->dvh.matcher)
8818 flow_dv_matcher_release(dev, dev_handle);
8819 if (dev_handle->dvh.rix_encap_decap)
8820 flow_dv_encap_decap_resource_release(dev, dev_handle);
8821 if (dev_handle->dvh.modify_hdr)
8822 flow_dv_modify_hdr_resource_release(dev_handle);
8823 if (dev_handle->dvh.rix_push_vlan)
8824 flow_dv_push_vlan_action_resource_release(dev,
8826 if (dev_handle->dvh.rix_tag)
8827 flow_dv_tag_release(dev,
8828 dev_handle->dvh.rix_tag);
8829 flow_dv_fate_resource_release(dev, dev_handle);
8830 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
8836 * Query a dv flow rule for its statistics via devx.
8839 * Pointer to Ethernet device.
8841 * Pointer to the sub flow.
8843 * data retrieved by the query.
8845 * Perform verbose error reporting if not NULL.
8848 * 0 on success, a negative errno value otherwise and rte_errno is set.
8851 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
8852 void *data, struct rte_flow_error *error)
8854 struct mlx5_priv *priv = dev->data->dev_private;
8855 struct rte_flow_query_count *qc = data;
8857 if (!priv->config.devx)
8858 return rte_flow_error_set(error, ENOTSUP,
8859 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8861 "counters are not supported");
8862 if (flow->counter) {
8863 uint64_t pkts, bytes;
8864 struct mlx5_flow_counter *cnt;
8866 cnt = flow_dv_counter_get_by_idx(dev, flow->counter,
8868 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
8872 return rte_flow_error_set(error, -err,
8873 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8874 NULL, "cannot read counters");
8877 qc->hits = pkts - cnt->hits;
8878 qc->bytes = bytes - cnt->bytes;
8885 return rte_flow_error_set(error, EINVAL,
8886 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8888 "counters are not available");
8894 * @see rte_flow_query()
8898 flow_dv_query(struct rte_eth_dev *dev,
8899 struct rte_flow *flow __rte_unused,
8900 const struct rte_flow_action *actions __rte_unused,
8901 void *data __rte_unused,
8902 struct rte_flow_error *error __rte_unused)
8906 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
8907 switch (actions->type) {
8908 case RTE_FLOW_ACTION_TYPE_VOID:
8910 case RTE_FLOW_ACTION_TYPE_COUNT:
8911 ret = flow_dv_query_count(dev, flow, data, error);
8914 return rte_flow_error_set(error, ENOTSUP,
8915 RTE_FLOW_ERROR_TYPE_ACTION,
8917 "action not supported");
8924 * Destroy the meter table set.
8925 * Lock free, (mutex should be acquired by caller).
8928 * Pointer to Ethernet device.
8930 * Pointer to the meter table set.
8936 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
8937 struct mlx5_meter_domains_infos *tbl)
8939 struct mlx5_priv *priv = dev->data->dev_private;
8940 struct mlx5_meter_domains_infos *mtd =
8941 (struct mlx5_meter_domains_infos *)tbl;
8943 if (!mtd || !priv->config.dv_flow_en)
8945 if (mtd->ingress.policer_rules[RTE_MTR_DROPPED])
8946 claim_zero(mlx5_glue->dv_destroy_flow
8947 (mtd->ingress.policer_rules[RTE_MTR_DROPPED]));
8948 if (mtd->egress.policer_rules[RTE_MTR_DROPPED])
8949 claim_zero(mlx5_glue->dv_destroy_flow
8950 (mtd->egress.policer_rules[RTE_MTR_DROPPED]));
8951 if (mtd->transfer.policer_rules[RTE_MTR_DROPPED])
8952 claim_zero(mlx5_glue->dv_destroy_flow
8953 (mtd->transfer.policer_rules[RTE_MTR_DROPPED]));
8954 if (mtd->egress.color_matcher)
8955 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8956 (mtd->egress.color_matcher));
8957 if (mtd->egress.any_matcher)
8958 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8959 (mtd->egress.any_matcher));
8960 if (mtd->egress.tbl)
8961 flow_dv_tbl_resource_release(dev, mtd->egress.tbl);
8962 if (mtd->egress.sfx_tbl)
8963 flow_dv_tbl_resource_release(dev, mtd->egress.sfx_tbl);
8964 if (mtd->ingress.color_matcher)
8965 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8966 (mtd->ingress.color_matcher));
8967 if (mtd->ingress.any_matcher)
8968 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8969 (mtd->ingress.any_matcher));
8970 if (mtd->ingress.tbl)
8971 flow_dv_tbl_resource_release(dev, mtd->ingress.tbl);
8972 if (mtd->ingress.sfx_tbl)
8973 flow_dv_tbl_resource_release(dev, mtd->ingress.sfx_tbl);
8974 if (mtd->transfer.color_matcher)
8975 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8976 (mtd->transfer.color_matcher));
8977 if (mtd->transfer.any_matcher)
8978 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8979 (mtd->transfer.any_matcher));
8980 if (mtd->transfer.tbl)
8981 flow_dv_tbl_resource_release(dev, mtd->transfer.tbl);
8982 if (mtd->transfer.sfx_tbl)
8983 flow_dv_tbl_resource_release(dev, mtd->transfer.sfx_tbl);
8985 claim_zero(mlx5_glue->destroy_flow_action(mtd->drop_actn));
8990 /* Number of meter flow actions, count and jump or count and drop. */
8991 #define METER_ACTIONS 2
8994 * Create specify domain meter table and suffix table.
8997 * Pointer to Ethernet device.
8998 * @param[in,out] mtb
8999 * Pointer to DV meter table set.
9002 * @param[in] transfer
9004 * @param[in] color_reg_c_idx
9005 * Reg C index for color match.
9008 * 0 on success, -1 otherwise and rte_errno is set.
9011 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
9012 struct mlx5_meter_domains_infos *mtb,
9013 uint8_t egress, uint8_t transfer,
9014 uint32_t color_reg_c_idx)
9016 struct mlx5_priv *priv = dev->data->dev_private;
9017 struct mlx5_ibv_shared *sh = priv->sh;
9018 struct mlx5_flow_dv_match_params mask = {
9019 .size = sizeof(mask.buf),
9021 struct mlx5_flow_dv_match_params value = {
9022 .size = sizeof(value.buf),
9024 struct mlx5dv_flow_matcher_attr dv_attr = {
9025 .type = IBV_FLOW_ATTR_NORMAL,
9027 .match_criteria_enable = 0,
9028 .match_mask = (void *)&mask,
9030 void *actions[METER_ACTIONS];
9031 struct mlx5_meter_domain_info *dtb;
9032 struct rte_flow_error error;
9036 dtb = &mtb->transfer;
9040 dtb = &mtb->ingress;
9041 /* Create the meter table with METER level. */
9042 dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
9043 egress, transfer, &error);
9045 DRV_LOG(ERR, "Failed to create meter policer table.");
9048 /* Create the meter suffix table with SUFFIX level. */
9049 dtb->sfx_tbl = flow_dv_tbl_resource_get(dev,
9050 MLX5_FLOW_TABLE_LEVEL_SUFFIX,
9051 egress, transfer, &error);
9052 if (!dtb->sfx_tbl) {
9053 DRV_LOG(ERR, "Failed to create meter suffix table.");
9056 /* Create matchers, Any and Color. */
9057 dv_attr.priority = 3;
9058 dv_attr.match_criteria_enable = 0;
9059 dtb->any_matcher = mlx5_glue->dv_create_flow_matcher(sh->ctx,
9062 if (!dtb->any_matcher) {
9063 DRV_LOG(ERR, "Failed to create meter"
9064 " policer default matcher.");
9067 dv_attr.priority = 0;
9068 dv_attr.match_criteria_enable =
9069 1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
9070 flow_dv_match_meta_reg(mask.buf, value.buf, color_reg_c_idx,
9071 rte_col_2_mlx5_col(RTE_COLORS), UINT8_MAX);
9072 dtb->color_matcher = mlx5_glue->dv_create_flow_matcher(sh->ctx,
9075 if (!dtb->color_matcher) {
9076 DRV_LOG(ERR, "Failed to create meter policer color matcher.");
9079 if (mtb->count_actns[RTE_MTR_DROPPED])
9080 actions[i++] = mtb->count_actns[RTE_MTR_DROPPED];
9081 actions[i++] = mtb->drop_actn;
9082 /* Default rule: lowest priority, match any, actions: drop. */
9083 dtb->policer_rules[RTE_MTR_DROPPED] =
9084 mlx5_glue->dv_create_flow(dtb->any_matcher,
9085 (void *)&value, i, actions);
9086 if (!dtb->policer_rules[RTE_MTR_DROPPED]) {
9087 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
9096 * Create the needed meter and suffix tables.
9097 * Lock free, (mutex should be acquired by caller).
9100 * Pointer to Ethernet device.
9102 * Pointer to the flow meter.
9105 * Pointer to table set on success, NULL otherwise and rte_errno is set.
9107 static struct mlx5_meter_domains_infos *
9108 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev,
9109 const struct mlx5_flow_meter *fm)
9111 struct mlx5_priv *priv = dev->data->dev_private;
9112 struct mlx5_meter_domains_infos *mtb;
9116 if (!priv->mtr_en) {
9117 rte_errno = ENOTSUP;
9120 mtb = rte_calloc(__func__, 1, sizeof(*mtb), 0);
9122 DRV_LOG(ERR, "Failed to allocate memory for meter.");
9125 /* Create meter count actions */
9126 for (i = 0; i <= RTE_MTR_DROPPED; i++) {
9127 struct mlx5_flow_counter *cnt;
9128 if (!fm->policer_stats.cnt[i])
9130 cnt = flow_dv_counter_get_by_idx(dev,
9131 fm->policer_stats.cnt[i], NULL);
9132 mtb->count_actns[i] = cnt->action;
9134 /* Create drop action. */
9135 mtb->drop_actn = mlx5_glue->dr_create_flow_action_drop();
9136 if (!mtb->drop_actn) {
9137 DRV_LOG(ERR, "Failed to create drop action.");
9140 /* Egress meter table. */
9141 ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0, priv->mtr_color_reg);
9143 DRV_LOG(ERR, "Failed to prepare egress meter table.");
9146 /* Ingress meter table. */
9147 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0, priv->mtr_color_reg);
9149 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
9152 /* FDB meter table. */
9153 if (priv->config.dv_esw_en) {
9154 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1,
9155 priv->mtr_color_reg);
9157 DRV_LOG(ERR, "Failed to prepare fdb meter table.");
9163 flow_dv_destroy_mtr_tbl(dev, mtb);
9168 * Destroy domain policer rule.
9171 * Pointer to domain table.
9174 flow_dv_destroy_domain_policer_rule(struct mlx5_meter_domain_info *dt)
9178 for (i = 0; i < RTE_MTR_DROPPED; i++) {
9179 if (dt->policer_rules[i]) {
9180 claim_zero(mlx5_glue->dv_destroy_flow
9181 (dt->policer_rules[i]));
9182 dt->policer_rules[i] = NULL;
9185 if (dt->jump_actn) {
9186 claim_zero(mlx5_glue->destroy_flow_action(dt->jump_actn));
9187 dt->jump_actn = NULL;
9192 * Destroy policer rules.
9195 * Pointer to Ethernet device.
9197 * Pointer to flow meter structure.
9199 * Pointer to flow attributes.
9205 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev __rte_unused,
9206 const struct mlx5_flow_meter *fm,
9207 const struct rte_flow_attr *attr)
9209 struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
9214 flow_dv_destroy_domain_policer_rule(&mtb->egress);
9216 flow_dv_destroy_domain_policer_rule(&mtb->ingress);
9218 flow_dv_destroy_domain_policer_rule(&mtb->transfer);
9223 * Create specify domain meter policer rule.
9226 * Pointer to flow meter structure.
9228 * Pointer to DV meter table set.
9229 * @param[in] mtr_reg_c
9230 * Color match REG_C.
9233 * 0 on success, -1 otherwise.
9236 flow_dv_create_policer_forward_rule(struct mlx5_flow_meter *fm,
9237 struct mlx5_meter_domain_info *dtb,
9240 struct mlx5_flow_dv_match_params matcher = {
9241 .size = sizeof(matcher.buf),
9243 struct mlx5_flow_dv_match_params value = {
9244 .size = sizeof(value.buf),
9246 struct mlx5_meter_domains_infos *mtb = fm->mfts;
9247 void *actions[METER_ACTIONS];
9250 /* Create jump action. */
9251 if (!dtb->jump_actn)
9253 mlx5_glue->dr_create_flow_action_dest_flow_tbl
9254 (dtb->sfx_tbl->obj);
9255 if (!dtb->jump_actn) {
9256 DRV_LOG(ERR, "Failed to create policer jump action.");
9259 for (i = 0; i < RTE_MTR_DROPPED; i++) {
9262 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_reg_c,
9263 rte_col_2_mlx5_col(i), UINT8_MAX);
9264 if (mtb->count_actns[i])
9265 actions[j++] = mtb->count_actns[i];
9266 if (fm->action[i] == MTR_POLICER_ACTION_DROP)
9267 actions[j++] = mtb->drop_actn;
9269 actions[j++] = dtb->jump_actn;
9270 dtb->policer_rules[i] =
9271 mlx5_glue->dv_create_flow(dtb->color_matcher,
9274 if (!dtb->policer_rules[i]) {
9275 DRV_LOG(ERR, "Failed to create policer rule.");
9286 * Create policer rules.
9289 * Pointer to Ethernet device.
9291 * Pointer to flow meter structure.
9293 * Pointer to flow attributes.
9296 * 0 on success, -1 otherwise.
9299 flow_dv_create_policer_rules(struct rte_eth_dev *dev,
9300 struct mlx5_flow_meter *fm,
9301 const struct rte_flow_attr *attr)
9303 struct mlx5_priv *priv = dev->data->dev_private;
9304 struct mlx5_meter_domains_infos *mtb = fm->mfts;
9308 ret = flow_dv_create_policer_forward_rule(fm, &mtb->egress,
9309 priv->mtr_color_reg);
9311 DRV_LOG(ERR, "Failed to create egress policer.");
9315 if (attr->ingress) {
9316 ret = flow_dv_create_policer_forward_rule(fm, &mtb->ingress,
9317 priv->mtr_color_reg);
9319 DRV_LOG(ERR, "Failed to create ingress policer.");
9323 if (attr->transfer) {
9324 ret = flow_dv_create_policer_forward_rule(fm, &mtb->transfer,
9325 priv->mtr_color_reg);
9327 DRV_LOG(ERR, "Failed to create transfer policer.");
9333 flow_dv_destroy_policer_rules(dev, fm, attr);
9338 * Query a devx counter.
9341 * Pointer to the Ethernet device structure.
9343 * Index to the flow counter.
9345 * Set to clear the counter statistics.
9347 * The statistics value of packets.
9349 * The statistics value of bytes.
9352 * 0 on success, otherwise return -1.
9355 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
9356 uint64_t *pkts, uint64_t *bytes)
9358 struct mlx5_priv *priv = dev->data->dev_private;
9359 struct mlx5_flow_counter *cnt;
9360 uint64_t inn_pkts, inn_bytes;
9363 if (!priv->config.devx)
9366 ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
9369 cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
9370 *pkts = inn_pkts - cnt->hits;
9371 *bytes = inn_bytes - cnt->bytes;
9373 cnt->hits = inn_pkts;
9374 cnt->bytes = inn_bytes;
9380 * Get aged-out flows.
9383 * Pointer to the Ethernet device structure.
9384 * @param[in] context
9385 * The address of an array of pointers to the aged-out flows contexts.
9386 * @param[in] nb_contexts
9387 * The length of context array pointers.
9389 * Perform verbose error reporting if not NULL. Initialized in case of
9393 * how many contexts get in success, otherwise negative errno value.
9394 * if nb_contexts is 0, return the amount of all aged contexts.
9395 * if nb_contexts is not 0 , return the amount of aged flows reported
9396 * in the context array.
9397 * @note: only stub for now
9400 flow_get_aged_flows(struct rte_eth_dev *dev,
9402 uint32_t nb_contexts,
9403 struct rte_flow_error *error)
9405 struct mlx5_priv *priv = dev->data->dev_private;
9406 struct mlx5_age_info *age_info;
9407 struct mlx5_age_param *age_param;
9408 struct mlx5_flow_counter *counter;
9411 if (nb_contexts && !context)
9412 return rte_flow_error_set(error, EINVAL,
9413 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9415 "Should assign at least one flow or"
9416 " context to get if nb_contexts != 0");
9417 age_info = GET_PORT_AGE_INFO(priv);
9418 rte_spinlock_lock(&age_info->aged_sl);
9419 TAILQ_FOREACH(counter, &age_info->aged_counters, next) {
9422 age_param = MLX5_CNT_TO_AGE(counter);
9423 context[nb_flows - 1] = age_param->context;
9424 if (!(--nb_contexts))
9428 rte_spinlock_unlock(&age_info->aged_sl);
9429 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
9434 * Mutex-protected thunk to lock-free __flow_dv_translate().
9437 flow_dv_translate(struct rte_eth_dev *dev,
9438 struct mlx5_flow *dev_flow,
9439 const struct rte_flow_attr *attr,
9440 const struct rte_flow_item items[],
9441 const struct rte_flow_action actions[],
9442 struct rte_flow_error *error)
9446 flow_dv_shared_lock(dev);
9447 ret = __flow_dv_translate(dev, dev_flow, attr, items, actions, error);
9448 flow_dv_shared_unlock(dev);
9453 * Mutex-protected thunk to lock-free __flow_dv_apply().
9456 flow_dv_apply(struct rte_eth_dev *dev,
9457 struct rte_flow *flow,
9458 struct rte_flow_error *error)
9462 flow_dv_shared_lock(dev);
9463 ret = __flow_dv_apply(dev, flow, error);
9464 flow_dv_shared_unlock(dev);
9469 * Mutex-protected thunk to lock-free __flow_dv_remove().
9472 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
9474 flow_dv_shared_lock(dev);
9475 __flow_dv_remove(dev, flow);
9476 flow_dv_shared_unlock(dev);
9480 * Mutex-protected thunk to lock-free __flow_dv_destroy().
9483 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
9485 flow_dv_shared_lock(dev);
9486 __flow_dv_destroy(dev, flow);
9487 flow_dv_shared_unlock(dev);
9491 * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
9494 flow_dv_counter_allocate(struct rte_eth_dev *dev)
9498 flow_dv_shared_lock(dev);
9499 cnt = flow_dv_counter_alloc(dev, 0, 0, 1, 0);
9500 flow_dv_shared_unlock(dev);
9505 * Mutex-protected thunk to lock-free flow_dv_counter_release().
9508 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t cnt)
9510 flow_dv_shared_lock(dev);
9511 flow_dv_counter_release(dev, cnt);
9512 flow_dv_shared_unlock(dev);
9515 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
9516 .validate = flow_dv_validate,
9517 .prepare = flow_dv_prepare,
9518 .translate = flow_dv_translate,
9519 .apply = flow_dv_apply,
9520 .remove = flow_dv_remove,
9521 .destroy = flow_dv_destroy,
9522 .query = flow_dv_query,
9523 .create_mtr_tbls = flow_dv_create_mtr_tbl,
9524 .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
9525 .create_policer_rules = flow_dv_create_policer_rules,
9526 .destroy_policer_rules = flow_dv_destroy_policer_rules,
9527 .counter_alloc = flow_dv_counter_allocate,
9528 .counter_free = flow_dv_counter_free,
9529 .counter_query = flow_dv_counter_query,
9530 .get_aged_flows = flow_get_aged_flows,
9533 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */