drivers/net/mlx5/mlx5_flow_dv.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2018 Mellanox Technologies, Ltd
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdalign.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10
  11 #include <rte_common.h>
  12 #include <rte_ether.h>
  13 #include <rte_ethdev_driver.h>
  14 #include <rte_flow.h>
  15 #include <rte_flow_driver.h>
  16 #include <rte_malloc.h>
  17 #include <rte_cycles.h>
  18 #include <rte_ip.h>
  19 #include <rte_gre.h>
  20 #include <rte_vxlan.h>
  21 #include <rte_gtp.h>
  22 #include <rte_eal_paging.h>
  23 #include <rte_mpls.h>
  24
  25 #include <mlx5_glue.h>
  26 #include <mlx5_devx_cmds.h>
  27 #include <mlx5_prm.h>
  28 #include <mlx5_malloc.h>
  29
  30 #include "mlx5_defs.h"
  31 #include "mlx5.h"
  32 #include "mlx5_common_os.h"
  33 #include "mlx5_flow.h"
  34 #include "mlx5_flow_os.h"
  35 #include "mlx5_rxtx.h"
  36 #include "rte_pmd_mlx5.h"
  37
  38 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
  39
  40 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
  41 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
  42 #endif
  43
  44 #ifndef HAVE_MLX5DV_DR_ESWITCH
  45 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
  46 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
  47 #endif
  48 #endif
  49
  50 #ifndef HAVE_MLX5DV_DR
  51 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
  52 #endif
  53
  54 /* VLAN header definitions */
  55 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
  56 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
  57 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
  58 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
  59 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
  60
  61 union flow_dv_attr {
  62         struct {
  63                 uint32_t valid:1;
  64                 uint32_t ipv4:1;
  65                 uint32_t ipv6:1;
  66                 uint32_t tcp:1;
  67                 uint32_t udp:1;
  68                 uint32_t reserved:27;
  69         };
  70         uint32_t attr;
  71 };
  72
  73 static int
  74 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
  75                              struct mlx5_flow_tbl_resource *tbl);
  76
  77 static int
  78 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
  79                                       uint32_t encap_decap_idx);
  80
  81 static int
  82 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
  83                                         uint32_t port_id);
  84 static void
  85 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss);
  86
  87 /**
  88  * Initialize flow attributes structure according to flow items' types.
  89  *
  90  * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
  91  * mode. For tunnel mode, the items to be modified are the outermost ones.
  92  *
  93  * @param[in] item
  94  *   Pointer to item specification.
  95  * @param[out] attr
  96  *   Pointer to flow attributes structure.
  97  * @param[in] dev_flow
  98  *   Pointer to the sub flow.
  99  * @param[in] tunnel_decap
 100  *   Whether action is after tunnel decapsulation.
 101  */
 102 static void
 103 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
 104                   struct mlx5_flow *dev_flow, bool tunnel_decap)
 105 {
 106         uint64_t layers = dev_flow->handle->layers;
 107
 108         /*
 109          * If layers is already initialized, it means this dev_flow is the
 110          * suffix flow, the layers flags is set by the prefix flow. Need to
 111          * use the layer flags from prefix flow as the suffix flow may not
 112          * have the user defined items as the flow is split.
 113          */
 114         if (layers) {
 115                 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
 116                         attr->ipv4 = 1;
 117                 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
 118                         attr->ipv6 = 1;
 119                 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
 120                         attr->tcp = 1;
 121                 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
 122                         attr->udp = 1;
 123                 attr->valid = 1;
 124                 return;
 125         }
 126         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
 127                 uint8_t next_protocol = 0xff;
 128                 switch (item->type) {
 129                 case RTE_FLOW_ITEM_TYPE_GRE:
 130                 case RTE_FLOW_ITEM_TYPE_NVGRE:
 131                 case RTE_FLOW_ITEM_TYPE_VXLAN:
 132                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
 133                 case RTE_FLOW_ITEM_TYPE_GENEVE:
 134                 case RTE_FLOW_ITEM_TYPE_MPLS:
 135                         if (tunnel_decap)
 136                                 attr->attr = 0;
 137                         break;
 138                 case RTE_FLOW_ITEM_TYPE_IPV4:
 139                         if (!attr->ipv6)
 140                                 attr->ipv4 = 1;
 141                         if (item->mask != NULL &&
 142                             ((const struct rte_flow_item_ipv4 *)
 143                             item->mask)->hdr.next_proto_id)
 144                                 next_protocol =
 145                                     ((const struct rte_flow_item_ipv4 *)
 146                                       (item->spec))->hdr.next_proto_id &
 147                                     ((const struct rte_flow_item_ipv4 *)
 148                                       (item->mask))->hdr.next_proto_id;
 149                         if ((next_protocol == IPPROTO_IPIP ||
 150                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 151                                 attr->attr = 0;
 152                         break;
 153                 case RTE_FLOW_ITEM_TYPE_IPV6:
 154                         if (!attr->ipv4)
 155                                 attr->ipv6 = 1;
 156                         if (item->mask != NULL &&
 157                             ((const struct rte_flow_item_ipv6 *)
 158                             item->mask)->hdr.proto)
 159                                 next_protocol =
 160                                     ((const struct rte_flow_item_ipv6 *)
 161                                       (item->spec))->hdr.proto &
 162                                     ((const struct rte_flow_item_ipv6 *)
 163                                       (item->mask))->hdr.proto;
 164                         if ((next_protocol == IPPROTO_IPIP ||
 165                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 166                                 attr->attr = 0;
 167                         break;
 168                 case RTE_FLOW_ITEM_TYPE_UDP:
 169                         if (!attr->tcp)
 170                                 attr->udp = 1;
 171                         break;
 172                 case RTE_FLOW_ITEM_TYPE_TCP:
 173                         if (!attr->udp)
 174                                 attr->tcp = 1;
 175                         break;
 176                 default:
 177                         break;
 178                 }
 179         }
 180         attr->valid = 1;
 181 }
 182
 183 /**
 184  * Convert rte_mtr_color to mlx5 color.
 185  *
 186  * @param[in] rcol
 187  *   rte_mtr_color.
 188  *
 189  * @return
 190  *   mlx5 color.
 191  */
 192 static int
 193 rte_col_2_mlx5_col(enum rte_color rcol)
 194 {
 195         switch (rcol) {
 196         case RTE_COLOR_GREEN:
 197                 return MLX5_FLOW_COLOR_GREEN;
 198         case RTE_COLOR_YELLOW:
 199                 return MLX5_FLOW_COLOR_YELLOW;
 200         case RTE_COLOR_RED:
 201                 return MLX5_FLOW_COLOR_RED;
 202         default:
 203                 break;
 204         }
 205         return MLX5_FLOW_COLOR_UNDEFINED;
 206 }
 207
 208 struct field_modify_info {
 209         uint32_t size; /* Size of field in protocol header, in bytes. */
 210         uint32_t offset; /* Offset of field in protocol header, in bytes. */
 211         enum mlx5_modification_field id;
 212 };
 213
 214 struct field_modify_info modify_eth[] = {
 215         {4,  0, MLX5_MODI_OUT_DMAC_47_16},
 216         {2,  4, MLX5_MODI_OUT_DMAC_15_0},
 217         {4,  6, MLX5_MODI_OUT_SMAC_47_16},
 218         {2, 10, MLX5_MODI_OUT_SMAC_15_0},
 219         {0, 0, 0},
 220 };
 221
 222 struct field_modify_info modify_vlan_out_first_vid[] = {
 223         /* Size in bits !!! */
 224         {12, 0, MLX5_MODI_OUT_FIRST_VID},
 225         {0, 0, 0},
 226 };
 227
 228 struct field_modify_info modify_ipv4[] = {
 229         {1,  1, MLX5_MODI_OUT_IP_DSCP},
 230         {1,  8, MLX5_MODI_OUT_IPV4_TTL},
 231         {4, 12, MLX5_MODI_OUT_SIPV4},
 232         {4, 16, MLX5_MODI_OUT_DIPV4},
 233         {0, 0, 0},
 234 };
 235
 236 struct field_modify_info modify_ipv6[] = {
 237         {1,  0, MLX5_MODI_OUT_IP_DSCP},
 238         {1,  7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
 239         {4,  8, MLX5_MODI_OUT_SIPV6_127_96},
 240         {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
 241         {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
 242         {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
 243         {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
 244         {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
 245         {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
 246         {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
 247         {0, 0, 0},
 248 };
 249
 250 struct field_modify_info modify_udp[] = {
 251         {2, 0, MLX5_MODI_OUT_UDP_SPORT},
 252         {2, 2, MLX5_MODI_OUT_UDP_DPORT},
 253         {0, 0, 0},
 254 };
 255
 256 struct field_modify_info modify_tcp[] = {
 257         {2, 0, MLX5_MODI_OUT_TCP_SPORT},
 258         {2, 2, MLX5_MODI_OUT_TCP_DPORT},
 259         {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
 260         {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
 261         {0, 0, 0},
 262 };
 263
 264 static void
 265 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
 266                           uint8_t next_protocol, uint64_t *item_flags,
 267                           int *tunnel)
 268 {
 269         MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
 270                     item->type == RTE_FLOW_ITEM_TYPE_IPV6);
 271         if (next_protocol == IPPROTO_IPIP) {
 272                 *item_flags |= MLX5_FLOW_LAYER_IPIP;
 273                 *tunnel = 1;
 274         }
 275         if (next_protocol == IPPROTO_IPV6) {
 276                 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
 277                 *tunnel = 1;
 278         }
 279 }
 280
 281 /* Update VLAN's VID/PCP based on input rte_flow_action.
 282  *
 283  * @param[in] action
 284  *   Pointer to struct rte_flow_action.
 285  * @param[out] vlan
 286  *   Pointer to struct rte_vlan_hdr.
 287  */
 288 static void
 289 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
 290                          struct rte_vlan_hdr *vlan)
 291 {
 292         uint16_t vlan_tci;
 293         if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
 294                 vlan_tci =
 295                     ((const struct rte_flow_action_of_set_vlan_pcp *)
 296                                                action->conf)->vlan_pcp;
 297                 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
 298                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
 299                 vlan->vlan_tci |= vlan_tci;
 300         } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
 301                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
 302                 vlan->vlan_tci |= rte_be_to_cpu_16
 303                     (((const struct rte_flow_action_of_set_vlan_vid *)
 304                                              action->conf)->vlan_vid);
 305         }
 306 }
 307
 308 /**
 309  * Fetch 1, 2, 3 or 4 byte field from the byte array
 310  * and return as unsigned integer in host-endian format.
 311  *
 312  * @param[in] data
 313  *   Pointer to data array.
 314  * @param[in] size
 315  *   Size of field to extract.
 316  *
 317  * @return
 318  *   converted field in host endian format.
 319  */
 320 static inline uint32_t
 321 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
 322 {
 323         uint32_t ret;
 324
 325         switch (size) {
 326         case 1:
 327                 ret = *data;
 328                 break;
 329         case 2:
 330                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 331                 break;
 332         case 3:
 333                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 334                 ret = (ret << 8) | *(data + sizeof(uint16_t));
 335                 break;
 336         case 4:
 337                 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
 338                 break;
 339         default:
 340                 MLX5_ASSERT(false);
 341                 ret = 0;
 342                 break;
 343         }
 344         return ret;
 345 }
 346
 347 /**
 348  * Convert modify-header action to DV specification.
 349  *
 350  * Data length of each action is determined by provided field description
 351  * and the item mask. Data bit offset and width of each action is determined
 352  * by provided item mask.
 353  *
 354  * @param[in] item
 355  *   Pointer to item specification.
 356  * @param[in] field
 357  *   Pointer to field modification information.
 358  *     For MLX5_MODIFICATION_TYPE_SET specifies destination field.
 359  *     For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
 360  *     For MLX5_MODIFICATION_TYPE_COPY specifies source field.
 361  * @param[in] dcopy
 362  *   Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
 363  *   Negative offset value sets the same offset as source offset.
 364  *   size field is ignored, value is taken from source field.
 365  * @param[in,out] resource
 366  *   Pointer to the modify-header resource.
 367  * @param[in] type
 368  *   Type of modification.
 369  * @param[out] error
 370  *   Pointer to the error structure.
 371  *
 372  * @return
 373  *   0 on success, a negative errno value otherwise and rte_errno is set.
 374  */
 375 static int
 376 flow_dv_convert_modify_action(struct rte_flow_item *item,
 377                               struct field_modify_info *field,
 378                               struct field_modify_info *dcopy,
 379                               struct mlx5_flow_dv_modify_hdr_resource *resource,
 380                               uint32_t type, struct rte_flow_error *error)
 381 {
 382         uint32_t i = resource->actions_num;
 383         struct mlx5_modification_cmd *actions = resource->actions;
 384
 385         /*
 386          * The item and mask are provided in big-endian format.
 387          * The fields should be presented as in big-endian format either.
 388          * Mask must be always present, it defines the actual field width.
 389          */
 390         MLX5_ASSERT(item->mask);
 391         MLX5_ASSERT(field->size);
 392         do {
 393                 unsigned int size_b;
 394                 unsigned int off_b;
 395                 uint32_t mask;
 396                 uint32_t data;
 397
 398                 if (i >= MLX5_MAX_MODIFY_NUM)
 399                         return rte_flow_error_set(error, EINVAL,
 400                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 401                                  "too many items to modify");
 402                 /* Fetch variable byte size mask from the array. */
 403                 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
 404                                            field->offset, field->size);
 405                 if (!mask) {
 406                         ++field;
 407                         continue;
 408                 }
 409                 /* Deduce actual data width in bits from mask value. */
 410                 off_b = rte_bsf32(mask);
 411                 size_b = sizeof(uint32_t) * CHAR_BIT -
 412                          off_b - __builtin_clz(mask);
 413                 MLX5_ASSERT(size_b);
 414                 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
 415                 actions[i] = (struct mlx5_modification_cmd) {
 416                         .action_type = type,
 417                         .field = field->id,
 418                         .offset = off_b,
 419                         .length = size_b,
 420                 };
 421                 /* Convert entire record to expected big-endian format. */
 422                 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 423                 if (type == MLX5_MODIFICATION_TYPE_COPY) {
 424                         MLX5_ASSERT(dcopy);
 425                         actions[i].dst_field = dcopy->id;
 426                         actions[i].dst_offset =
 427                                 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
 428                         /* Convert entire record to big-endian format. */
 429                         actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
 430                 } else {
 431                         MLX5_ASSERT(item->spec);
 432                         data = flow_dv_fetch_field((const uint8_t *)item->spec +
 433                                                    field->offset, field->size);
 434                         /* Shift out the trailing masked bits from data. */
 435                         data = (data & mask) >> off_b;
 436                         actions[i].data1 = rte_cpu_to_be_32(data);
 437                 }
 438                 ++i;
 439                 ++field;
 440         } while (field->size);
 441         if (resource->actions_num == i)
 442                 return rte_flow_error_set(error, EINVAL,
 443                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 444                                           "invalid modification flow item");
 445         resource->actions_num = i;
 446         return 0;
 447 }
 448
 449 /**
 450  * Convert modify-header set IPv4 address action to DV specification.
 451  *
 452  * @param[in,out] resource
 453  *   Pointer to the modify-header resource.
 454  * @param[in] action
 455  *   Pointer to action specification.
 456  * @param[out] error
 457  *   Pointer to the error structure.
 458  *
 459  * @return
 460  *   0 on success, a negative errno value otherwise and rte_errno is set.
 461  */
 462 static int
 463 flow_dv_convert_action_modify_ipv4
 464                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 465                          const struct rte_flow_action *action,
 466                          struct rte_flow_error *error)
 467 {
 468         const struct rte_flow_action_set_ipv4 *conf =
 469                 (const struct rte_flow_action_set_ipv4 *)(action->conf);
 470         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
 471         struct rte_flow_item_ipv4 ipv4;
 472         struct rte_flow_item_ipv4 ipv4_mask;
 473
 474         memset(&ipv4, 0, sizeof(ipv4));
 475         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 476         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
 477                 ipv4.hdr.src_addr = conf->ipv4_addr;
 478                 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
 479         } else {
 480                 ipv4.hdr.dst_addr = conf->ipv4_addr;
 481                 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
 482         }
 483         item.spec = &ipv4;
 484         item.mask = &ipv4_mask;
 485         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
 486                                              MLX5_MODIFICATION_TYPE_SET, error);
 487 }
 488
 489 /**
 490  * Convert modify-header set IPv6 address action to DV specification.
 491  *
 492  * @param[in,out] resource
 493  *   Pointer to the modify-header resource.
 494  * @param[in] action
 495  *   Pointer to action specification.
 496  * @param[out] error
 497  *   Pointer to the error structure.
 498  *
 499  * @return
 500  *   0 on success, a negative errno value otherwise and rte_errno is set.
 501  */
 502 static int
 503 flow_dv_convert_action_modify_ipv6
 504                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 505                          const struct rte_flow_action *action,
 506                          struct rte_flow_error *error)
 507 {
 508         const struct rte_flow_action_set_ipv6 *conf =
 509                 (const struct rte_flow_action_set_ipv6 *)(action->conf);
 510         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
 511         struct rte_flow_item_ipv6 ipv6;
 512         struct rte_flow_item_ipv6 ipv6_mask;
 513
 514         memset(&ipv6, 0, sizeof(ipv6));
 515         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 516         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
 517                 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
 518                        sizeof(ipv6.hdr.src_addr));
 519                 memcpy(&ipv6_mask.hdr.src_addr,
 520                        &rte_flow_item_ipv6_mask.hdr.src_addr,
 521                        sizeof(ipv6.hdr.src_addr));
 522         } else {
 523                 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
 524                        sizeof(ipv6.hdr.dst_addr));
 525                 memcpy(&ipv6_mask.hdr.dst_addr,
 526                        &rte_flow_item_ipv6_mask.hdr.dst_addr,
 527                        sizeof(ipv6.hdr.dst_addr));
 528         }
 529         item.spec = &ipv6;
 530         item.mask = &ipv6_mask;
 531         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
 532                                              MLX5_MODIFICATION_TYPE_SET, error);
 533 }
 534
 535 /**
 536  * Convert modify-header set MAC address action to DV specification.
 537  *
 538  * @param[in,out] resource
 539  *   Pointer to the modify-header resource.
 540  * @param[in] action
 541  *   Pointer to action specification.
 542  * @param[out] error
 543  *   Pointer to the error structure.
 544  *
 545  * @return
 546  *   0 on success, a negative errno value otherwise and rte_errno is set.
 547  */
 548 static int
 549 flow_dv_convert_action_modify_mac
 550                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 551                          const struct rte_flow_action *action,
 552                          struct rte_flow_error *error)
 553 {
 554         const struct rte_flow_action_set_mac *conf =
 555                 (const struct rte_flow_action_set_mac *)(action->conf);
 556         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
 557         struct rte_flow_item_eth eth;
 558         struct rte_flow_item_eth eth_mask;
 559
 560         memset(&eth, 0, sizeof(eth));
 561         memset(&eth_mask, 0, sizeof(eth_mask));
 562         if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
 563                 memcpy(&eth.src.addr_bytes, &conf->mac_addr,
 564                        sizeof(eth.src.addr_bytes));
 565                 memcpy(&eth_mask.src.addr_bytes,
 566                        &rte_flow_item_eth_mask.src.addr_bytes,
 567                        sizeof(eth_mask.src.addr_bytes));
 568         } else {
 569                 memcpy(&eth.dst.addr_bytes, &conf->mac_addr,
 570                        sizeof(eth.dst.addr_bytes));
 571                 memcpy(&eth_mask.dst.addr_bytes,
 572                        &rte_flow_item_eth_mask.dst.addr_bytes,
 573                        sizeof(eth_mask.dst.addr_bytes));
 574         }
 575         item.spec = &eth;
 576         item.mask = &eth_mask;
 577         return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
 578                                              MLX5_MODIFICATION_TYPE_SET, error);
 579 }
 580
 581 /**
 582  * Convert modify-header set VLAN VID action to DV specification.
 583  *
 584  * @param[in,out] resource
 585  *   Pointer to the modify-header resource.
 586  * @param[in] action
 587  *   Pointer to action specification.
 588  * @param[out] error
 589  *   Pointer to the error structure.
 590  *
 591  * @return
 592  *   0 on success, a negative errno value otherwise and rte_errno is set.
 593  */
 594 static int
 595 flow_dv_convert_action_modify_vlan_vid
 596                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 597                          const struct rte_flow_action *action,
 598                          struct rte_flow_error *error)
 599 {
 600         const struct rte_flow_action_of_set_vlan_vid *conf =
 601                 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
 602         int i = resource->actions_num;
 603         struct mlx5_modification_cmd *actions = resource->actions;
 604         struct field_modify_info *field = modify_vlan_out_first_vid;
 605
 606         if (i >= MLX5_MAX_MODIFY_NUM)
 607                 return rte_flow_error_set(error, EINVAL,
 608                          RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 609                          "too many items to modify");
 610         actions[i] = (struct mlx5_modification_cmd) {
 611                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 612                 .field = field->id,
 613                 .length = field->size,
 614                 .offset = field->offset,
 615         };
 616         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 617         actions[i].data1 = conf->vlan_vid;
 618         actions[i].data1 = actions[i].data1 << 16;
 619         resource->actions_num = ++i;
 620         return 0;
 621 }
 622
 623 /**
 624  * Convert modify-header set TP action to DV specification.
 625  *
 626  * @param[in,out] resource
 627  *   Pointer to the modify-header resource.
 628  * @param[in] action
 629  *   Pointer to action specification.
 630  * @param[in] items
 631  *   Pointer to rte_flow_item objects list.
 632  * @param[in] attr
 633  *   Pointer to flow attributes structure.
 634  * @param[in] dev_flow
 635  *   Pointer to the sub flow.
 636  * @param[in] tunnel_decap
 637  *   Whether action is after tunnel decapsulation.
 638  * @param[out] error
 639  *   Pointer to the error structure.
 640  *
 641  * @return
 642  *   0 on success, a negative errno value otherwise and rte_errno is set.
 643  */
 644 static int
 645 flow_dv_convert_action_modify_tp
 646                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 647                          const struct rte_flow_action *action,
 648                          const struct rte_flow_item *items,
 649                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 650                          bool tunnel_decap, struct rte_flow_error *error)
 651 {
 652         const struct rte_flow_action_set_tp *conf =
 653                 (const struct rte_flow_action_set_tp *)(action->conf);
 654         struct rte_flow_item item;
 655         struct rte_flow_item_udp udp;
 656         struct rte_flow_item_udp udp_mask;
 657         struct rte_flow_item_tcp tcp;
 658         struct rte_flow_item_tcp tcp_mask;
 659         struct field_modify_info *field;
 660
 661         if (!attr->valid)
 662                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 663         if (attr->udp) {
 664                 memset(&udp, 0, sizeof(udp));
 665                 memset(&udp_mask, 0, sizeof(udp_mask));
 666                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 667                         udp.hdr.src_port = conf->port;
 668                         udp_mask.hdr.src_port =
 669                                         rte_flow_item_udp_mask.hdr.src_port;
 670                 } else {
 671                         udp.hdr.dst_port = conf->port;
 672                         udp_mask.hdr.dst_port =
 673                                         rte_flow_item_udp_mask.hdr.dst_port;
 674                 }
 675                 item.type = RTE_FLOW_ITEM_TYPE_UDP;
 676                 item.spec = &udp;
 677                 item.mask = &udp_mask;
 678                 field = modify_udp;
 679         } else {
 680                 MLX5_ASSERT(attr->tcp);
 681                 memset(&tcp, 0, sizeof(tcp));
 682                 memset(&tcp_mask, 0, sizeof(tcp_mask));
 683                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 684                         tcp.hdr.src_port = conf->port;
 685                         tcp_mask.hdr.src_port =
 686                                         rte_flow_item_tcp_mask.hdr.src_port;
 687                 } else {
 688                         tcp.hdr.dst_port = conf->port;
 689                         tcp_mask.hdr.dst_port =
 690                                         rte_flow_item_tcp_mask.hdr.dst_port;
 691                 }
 692                 item.type = RTE_FLOW_ITEM_TYPE_TCP;
 693                 item.spec = &tcp;
 694                 item.mask = &tcp_mask;
 695                 field = modify_tcp;
 696         }
 697         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 698                                              MLX5_MODIFICATION_TYPE_SET, error);
 699 }
 700
 701 /**
 702  * Convert modify-header set TTL action to DV specification.
 703  *
 704  * @param[in,out] resource
 705  *   Pointer to the modify-header resource.
 706  * @param[in] action
 707  *   Pointer to action specification.
 708  * @param[in] items
 709  *   Pointer to rte_flow_item objects list.
 710  * @param[in] attr
 711  *   Pointer to flow attributes structure.
 712  * @param[in] dev_flow
 713  *   Pointer to the sub flow.
 714  * @param[in] tunnel_decap
 715  *   Whether action is after tunnel decapsulation.
 716  * @param[out] error
 717  *   Pointer to the error structure.
 718  *
 719  * @return
 720  *   0 on success, a negative errno value otherwise and rte_errno is set.
 721  */
 722 static int
 723 flow_dv_convert_action_modify_ttl
 724                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 725                          const struct rte_flow_action *action,
 726                          const struct rte_flow_item *items,
 727                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 728                          bool tunnel_decap, struct rte_flow_error *error)
 729 {
 730         const struct rte_flow_action_set_ttl *conf =
 731                 (const struct rte_flow_action_set_ttl *)(action->conf);
 732         struct rte_flow_item item;
 733         struct rte_flow_item_ipv4 ipv4;
 734         struct rte_flow_item_ipv4 ipv4_mask;
 735         struct rte_flow_item_ipv6 ipv6;
 736         struct rte_flow_item_ipv6 ipv6_mask;
 737         struct field_modify_info *field;
 738
 739         if (!attr->valid)
 740                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 741         if (attr->ipv4) {
 742                 memset(&ipv4, 0, sizeof(ipv4));
 743                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 744                 ipv4.hdr.time_to_live = conf->ttl_value;
 745                 ipv4_mask.hdr.time_to_live = 0xFF;
 746                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 747                 item.spec = &ipv4;
 748                 item.mask = &ipv4_mask;
 749                 field = modify_ipv4;
 750         } else {
 751                 MLX5_ASSERT(attr->ipv6);
 752                 memset(&ipv6, 0, sizeof(ipv6));
 753                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 754                 ipv6.hdr.hop_limits = conf->ttl_value;
 755                 ipv6_mask.hdr.hop_limits = 0xFF;
 756                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 757                 item.spec = &ipv6;
 758                 item.mask = &ipv6_mask;
 759                 field = modify_ipv6;
 760         }
 761         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 762                                              MLX5_MODIFICATION_TYPE_SET, error);
 763 }
 764
 765 /**
 766  * Convert modify-header decrement TTL action to DV specification.
 767  *
 768  * @param[in,out] resource
 769  *   Pointer to the modify-header resource.
 770  * @param[in] action
 771  *   Pointer to action specification.
 772  * @param[in] items
 773  *   Pointer to rte_flow_item objects list.
 774  * @param[in] attr
 775  *   Pointer to flow attributes structure.
 776  * @param[in] dev_flow
 777  *   Pointer to the sub flow.
 778  * @param[in] tunnel_decap
 779  *   Whether action is after tunnel decapsulation.
 780  * @param[out] error
 781  *   Pointer to the error structure.
 782  *
 783  * @return
 784  *   0 on success, a negative errno value otherwise and rte_errno is set.
 785  */
 786 static int
 787 flow_dv_convert_action_modify_dec_ttl
 788                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 789                          const struct rte_flow_item *items,
 790                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 791                          bool tunnel_decap, struct rte_flow_error *error)
 792 {
 793         struct rte_flow_item item;
 794         struct rte_flow_item_ipv4 ipv4;
 795         struct rte_flow_item_ipv4 ipv4_mask;
 796         struct rte_flow_item_ipv6 ipv6;
 797         struct rte_flow_item_ipv6 ipv6_mask;
 798         struct field_modify_info *field;
 799
 800         if (!attr->valid)
 801                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 802         if (attr->ipv4) {
 803                 memset(&ipv4, 0, sizeof(ipv4));
 804                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 805                 ipv4.hdr.time_to_live = 0xFF;
 806                 ipv4_mask.hdr.time_to_live = 0xFF;
 807                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 808                 item.spec = &ipv4;
 809                 item.mask = &ipv4_mask;
 810                 field = modify_ipv4;
 811         } else {
 812                 MLX5_ASSERT(attr->ipv6);
 813                 memset(&ipv6, 0, sizeof(ipv6));
 814                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 815                 ipv6.hdr.hop_limits = 0xFF;
 816                 ipv6_mask.hdr.hop_limits = 0xFF;
 817                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 818                 item.spec = &ipv6;
 819                 item.mask = &ipv6_mask;
 820                 field = modify_ipv6;
 821         }
 822         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 823                                              MLX5_MODIFICATION_TYPE_ADD, error);
 824 }
 825
 826 /**
 827  * Convert modify-header increment/decrement TCP Sequence number
 828  * to DV specification.
 829  *
 830  * @param[in,out] resource
 831  *   Pointer to the modify-header resource.
 832  * @param[in] action
 833  *   Pointer to action specification.
 834  * @param[out] error
 835  *   Pointer to the error structure.
 836  *
 837  * @return
 838  *   0 on success, a negative errno value otherwise and rte_errno is set.
 839  */
 840 static int
 841 flow_dv_convert_action_modify_tcp_seq
 842                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 843                          const struct rte_flow_action *action,
 844                          struct rte_flow_error *error)
 845 {
 846         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 847         uint64_t value = rte_be_to_cpu_32(*conf);
 848         struct rte_flow_item item;
 849         struct rte_flow_item_tcp tcp;
 850         struct rte_flow_item_tcp tcp_mask;
 851
 852         memset(&tcp, 0, sizeof(tcp));
 853         memset(&tcp_mask, 0, sizeof(tcp_mask));
 854         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
 855                 /*
 856                  * The HW has no decrement operation, only increment operation.
 857                  * To simulate decrement X from Y using increment operation
 858                  * we need to add UINT32_MAX X times to Y.
 859                  * Each adding of UINT32_MAX decrements Y by 1.
 860                  */
 861                 value *= UINT32_MAX;
 862         tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
 863         tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
 864         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 865         item.spec = &tcp;
 866         item.mask = &tcp_mask;
 867         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 868                                              MLX5_MODIFICATION_TYPE_ADD, error);
 869 }
 870
 871 /**
 872  * Convert modify-header increment/decrement TCP Acknowledgment number
 873  * to DV specification.
 874  *
 875  * @param[in,out] resource
 876  *   Pointer to the modify-header resource.
 877  * @param[in] action
 878  *   Pointer to action specification.
 879  * @param[out] error
 880  *   Pointer to the error structure.
 881  *
 882  * @return
 883  *   0 on success, a negative errno value otherwise and rte_errno is set.
 884  */
 885 static int
 886 flow_dv_convert_action_modify_tcp_ack
 887                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 888                          const struct rte_flow_action *action,
 889                          struct rte_flow_error *error)
 890 {
 891         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 892         uint64_t value = rte_be_to_cpu_32(*conf);
 893         struct rte_flow_item item;
 894         struct rte_flow_item_tcp tcp;
 895         struct rte_flow_item_tcp tcp_mask;
 896
 897         memset(&tcp, 0, sizeof(tcp));
 898         memset(&tcp_mask, 0, sizeof(tcp_mask));
 899         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
 900                 /*
 901                  * The HW has no decrement operation, only increment operation.
 902                  * To simulate decrement X from Y using increment operation
 903                  * we need to add UINT32_MAX X times to Y.
 904                  * Each adding of UINT32_MAX decrements Y by 1.
 905                  */
 906                 value *= UINT32_MAX;
 907         tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
 908         tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
 909         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 910         item.spec = &tcp;
 911         item.mask = &tcp_mask;
 912         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 913                                              MLX5_MODIFICATION_TYPE_ADD, error);
 914 }
 915
 916 static enum mlx5_modification_field reg_to_field[] = {
 917         [REG_NON] = MLX5_MODI_OUT_NONE,
 918         [REG_A] = MLX5_MODI_META_DATA_REG_A,
 919         [REG_B] = MLX5_MODI_META_DATA_REG_B,
 920         [REG_C_0] = MLX5_MODI_META_REG_C_0,
 921         [REG_C_1] = MLX5_MODI_META_REG_C_1,
 922         [REG_C_2] = MLX5_MODI_META_REG_C_2,
 923         [REG_C_3] = MLX5_MODI_META_REG_C_3,
 924         [REG_C_4] = MLX5_MODI_META_REG_C_4,
 925         [REG_C_5] = MLX5_MODI_META_REG_C_5,
 926         [REG_C_6] = MLX5_MODI_META_REG_C_6,
 927         [REG_C_7] = MLX5_MODI_META_REG_C_7,
 928 };
 929
 930 /**
 931  * Convert register set to DV specification.
 932  *
 933  * @param[in,out] resource
 934  *   Pointer to the modify-header resource.
 935  * @param[in] action
 936  *   Pointer to action specification.
 937  * @param[out] error
 938  *   Pointer to the error structure.
 939  *
 940  * @return
 941  *   0 on success, a negative errno value otherwise and rte_errno is set.
 942  */
 943 static int
 944 flow_dv_convert_action_set_reg
 945                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 946                          const struct rte_flow_action *action,
 947                          struct rte_flow_error *error)
 948 {
 949         const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
 950         struct mlx5_modification_cmd *actions = resource->actions;
 951         uint32_t i = resource->actions_num;
 952
 953         if (i >= MLX5_MAX_MODIFY_NUM)
 954                 return rte_flow_error_set(error, EINVAL,
 955                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 956                                           "too many items to modify");
 957         MLX5_ASSERT(conf->id != REG_NON);
 958         MLX5_ASSERT(conf->id < (enum modify_reg)RTE_DIM(reg_to_field));
 959         actions[i] = (struct mlx5_modification_cmd) {
 960                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 961                 .field = reg_to_field[conf->id],
 962         };
 963         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 964         actions[i].data1 = rte_cpu_to_be_32(conf->data);
 965         ++i;
 966         resource->actions_num = i;
 967         return 0;
 968 }
 969
 970 /**
 971  * Convert SET_TAG action to DV specification.
 972  *
 973  * @param[in] dev
 974  *   Pointer to the rte_eth_dev structure.
 975  * @param[in,out] resource
 976  *   Pointer to the modify-header resource.
 977  * @param[in] conf
 978  *   Pointer to action specification.
 979  * @param[out] error
 980  *   Pointer to the error structure.
 981  *
 982  * @return
 983  *   0 on success, a negative errno value otherwise and rte_errno is set.
 984  */
 985 static int
 986 flow_dv_convert_action_set_tag
 987                         (struct rte_eth_dev *dev,
 988                          struct mlx5_flow_dv_modify_hdr_resource *resource,
 989                          const struct rte_flow_action_set_tag *conf,
 990                          struct rte_flow_error *error)
 991 {
 992         rte_be32_t data = rte_cpu_to_be_32(conf->data);
 993         rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
 994         struct rte_flow_item item = {
 995                 .spec = &data,
 996                 .mask = &mask,
 997         };
 998         struct field_modify_info reg_c_x[] = {
 999                 [1] = {0, 0, 0},
1000         };
1001         enum mlx5_modification_field reg_type;
1002         int ret;
1003
1004         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1005         if (ret < 0)
1006                 return ret;
1007         MLX5_ASSERT(ret != REG_NON);
1008         MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1009         reg_type = reg_to_field[ret];
1010         MLX5_ASSERT(reg_type > 0);
1011         reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1012         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1013                                              MLX5_MODIFICATION_TYPE_SET, error);
1014 }
1015
1016 /**
1017  * Convert internal COPY_REG action to DV specification.
1018  *
1019  * @param[in] dev
1020  *   Pointer to the rte_eth_dev structure.
1021  * @param[in,out] res
1022  *   Pointer to the modify-header resource.
1023  * @param[in] action
1024  *   Pointer to action specification.
1025  * @param[out] error
1026  *   Pointer to the error structure.
1027  *
1028  * @return
1029  *   0 on success, a negative errno value otherwise and rte_errno is set.
1030  */
1031 static int
1032 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1033                                  struct mlx5_flow_dv_modify_hdr_resource *res,
1034                                  const struct rte_flow_action *action,
1035                                  struct rte_flow_error *error)
1036 {
1037         const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1038         rte_be32_t mask = RTE_BE32(UINT32_MAX);
1039         struct rte_flow_item item = {
1040                 .spec = NULL,
1041                 .mask = &mask,
1042         };
1043         struct field_modify_info reg_src[] = {
1044                 {4, 0, reg_to_field[conf->src]},
1045                 {0, 0, 0},
1046         };
1047         struct field_modify_info reg_dst = {
1048                 .offset = 0,
1049                 .id = reg_to_field[conf->dst],
1050         };
1051         /* Adjust reg_c[0] usage according to reported mask. */
1052         if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1053                 struct mlx5_priv *priv = dev->data->dev_private;
1054                 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1055
1056                 MLX5_ASSERT(reg_c0);
1057                 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1058                 if (conf->dst == REG_C_0) {
1059                         /* Copy to reg_c[0], within mask only. */
1060                         reg_dst.offset = rte_bsf32(reg_c0);
1061                         /*
1062                          * Mask is ignoring the enianness, because
1063                          * there is no conversion in datapath.
1064                          */
1065 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1066                         /* Copy from destination lower bits to reg_c[0]. */
1067                         mask = reg_c0 >> reg_dst.offset;
1068 #else
1069                         /* Copy from destination upper bits to reg_c[0]. */
1070                         mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1071                                           rte_fls_u32(reg_c0));
1072 #endif
1073                 } else {
1074                         mask = rte_cpu_to_be_32(reg_c0);
1075 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1076                         /* Copy from reg_c[0] to destination lower bits. */
1077                         reg_dst.offset = 0;
1078 #else
1079                         /* Copy from reg_c[0] to destination upper bits. */
1080                         reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1081                                          (rte_fls_u32(reg_c0) -
1082                                           rte_bsf32(reg_c0));
1083 #endif
1084                 }
1085         }
1086         return flow_dv_convert_modify_action(&item,
1087                                              reg_src, &reg_dst, res,
1088                                              MLX5_MODIFICATION_TYPE_COPY,
1089                                              error);
1090 }
1091
1092 /**
1093  * Convert MARK action to DV specification. This routine is used
1094  * in extensive metadata only and requires metadata register to be
1095  * handled. In legacy mode hardware tag resource is engaged.
1096  *
1097  * @param[in] dev
1098  *   Pointer to the rte_eth_dev structure.
1099  * @param[in] conf
1100  *   Pointer to MARK action specification.
1101  * @param[in,out] resource
1102  *   Pointer to the modify-header resource.
1103  * @param[out] error
1104  *   Pointer to the error structure.
1105  *
1106  * @return
1107  *   0 on success, a negative errno value otherwise and rte_errno is set.
1108  */
1109 static int
1110 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1111                             const struct rte_flow_action_mark *conf,
1112                             struct mlx5_flow_dv_modify_hdr_resource *resource,
1113                             struct rte_flow_error *error)
1114 {
1115         struct mlx5_priv *priv = dev->data->dev_private;
1116         rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1117                                            priv->sh->dv_mark_mask);
1118         rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1119         struct rte_flow_item item = {
1120                 .spec = &data,
1121                 .mask = &mask,
1122         };
1123         struct field_modify_info reg_c_x[] = {
1124                 [1] = {0, 0, 0},
1125         };
1126         int reg;
1127
1128         if (!mask)
1129                 return rte_flow_error_set(error, EINVAL,
1130                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1131                                           NULL, "zero mark action mask");
1132         reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1133         if (reg < 0)
1134                 return reg;
1135         MLX5_ASSERT(reg > 0);
1136         if (reg == REG_C_0) {
1137                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1138                 uint32_t shl_c0 = rte_bsf32(msk_c0);
1139
1140                 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1141                 mask = rte_cpu_to_be_32(mask) & msk_c0;
1142                 mask = rte_cpu_to_be_32(mask << shl_c0);
1143         }
1144         reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1145         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1146                                              MLX5_MODIFICATION_TYPE_SET, error);
1147 }
1148
1149 /**
1150  * Get metadata register index for specified steering domain.
1151  *
1152  * @param[in] dev
1153  *   Pointer to the rte_eth_dev structure.
1154  * @param[in] attr
1155  *   Attributes of flow to determine steering domain.
1156  * @param[out] error
1157  *   Pointer to the error structure.
1158  *
1159  * @return
1160  *   positive index on success, a negative errno value otherwise
1161  *   and rte_errno is set.
1162  */
1163 static enum modify_reg
1164 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1165                          const struct rte_flow_attr *attr,
1166                          struct rte_flow_error *error)
1167 {
1168         int reg =
1169                 mlx5_flow_get_reg_id(dev, attr->transfer ?
1170                                           MLX5_METADATA_FDB :
1171                                             attr->egress ?
1172                                             MLX5_METADATA_TX :
1173                                             MLX5_METADATA_RX, 0, error);
1174         if (reg < 0)
1175                 return rte_flow_error_set(error,
1176                                           ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1177                                           NULL, "unavailable "
1178                                           "metadata register");
1179         return reg;
1180 }
1181
1182 /**
1183  * Convert SET_META action to DV specification.
1184  *
1185  * @param[in] dev
1186  *   Pointer to the rte_eth_dev structure.
1187  * @param[in,out] resource
1188  *   Pointer to the modify-header resource.
1189  * @param[in] attr
1190  *   Attributes of flow that includes this item.
1191  * @param[in] conf
1192  *   Pointer to action specification.
1193  * @param[out] error
1194  *   Pointer to the error structure.
1195  *
1196  * @return
1197  *   0 on success, a negative errno value otherwise and rte_errno is set.
1198  */
1199 static int
1200 flow_dv_convert_action_set_meta
1201                         (struct rte_eth_dev *dev,
1202                          struct mlx5_flow_dv_modify_hdr_resource *resource,
1203                          const struct rte_flow_attr *attr,
1204                          const struct rte_flow_action_set_meta *conf,
1205                          struct rte_flow_error *error)
1206 {
1207         uint32_t data = conf->data;
1208         uint32_t mask = conf->mask;
1209         struct rte_flow_item item = {
1210                 .spec = &data,
1211                 .mask = &mask,
1212         };
1213         struct field_modify_info reg_c_x[] = {
1214                 [1] = {0, 0, 0},
1215         };
1216         int reg = flow_dv_get_metadata_reg(dev, attr, error);
1217
1218         if (reg < 0)
1219                 return reg;
1220         MLX5_ASSERT(reg != REG_NON);
1221         /*
1222          * In datapath code there is no endianness
1223          * coversions for perfromance reasons, all
1224          * pattern conversions are done in rte_flow.
1225          */
1226         if (reg == REG_C_0) {
1227                 struct mlx5_priv *priv = dev->data->dev_private;
1228                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1229                 uint32_t shl_c0;
1230
1231                 MLX5_ASSERT(msk_c0);
1232 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1233                 shl_c0 = rte_bsf32(msk_c0);
1234 #else
1235                 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1236 #endif
1237                 mask <<= shl_c0;
1238                 data <<= shl_c0;
1239                 MLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1240         }
1241         reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1242         /* The routine expects parameters in memory as big-endian ones. */
1243         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1244                                              MLX5_MODIFICATION_TYPE_SET, error);
1245 }
1246
1247 /**
1248  * Convert modify-header set IPv4 DSCP action to DV specification.
1249  *
1250  * @param[in,out] resource
1251  *   Pointer to the modify-header resource.
1252  * @param[in] action
1253  *   Pointer to action specification.
1254  * @param[out] error
1255  *   Pointer to the error structure.
1256  *
1257  * @return
1258  *   0 on success, a negative errno value otherwise and rte_errno is set.
1259  */
1260 static int
1261 flow_dv_convert_action_modify_ipv4_dscp
1262                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1263                          const struct rte_flow_action *action,
1264                          struct rte_flow_error *error)
1265 {
1266         const struct rte_flow_action_set_dscp *conf =
1267                 (const struct rte_flow_action_set_dscp *)(action->conf);
1268         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1269         struct rte_flow_item_ipv4 ipv4;
1270         struct rte_flow_item_ipv4 ipv4_mask;
1271
1272         memset(&ipv4, 0, sizeof(ipv4));
1273         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1274         ipv4.hdr.type_of_service = conf->dscp;
1275         ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1276         item.spec = &ipv4;
1277         item.mask = &ipv4_mask;
1278         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1279                                              MLX5_MODIFICATION_TYPE_SET, error);
1280 }
1281
1282 /**
1283  * Convert modify-header set IPv6 DSCP action to DV specification.
1284  *
1285  * @param[in,out] resource
1286  *   Pointer to the modify-header resource.
1287  * @param[in] action
1288  *   Pointer to action specification.
1289  * @param[out] error
1290  *   Pointer to the error structure.
1291  *
1292  * @return
1293  *   0 on success, a negative errno value otherwise and rte_errno is set.
1294  */
1295 static int
1296 flow_dv_convert_action_modify_ipv6_dscp
1297                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1298                          const struct rte_flow_action *action,
1299                          struct rte_flow_error *error)
1300 {
1301         const struct rte_flow_action_set_dscp *conf =
1302                 (const struct rte_flow_action_set_dscp *)(action->conf);
1303         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1304         struct rte_flow_item_ipv6 ipv6;
1305         struct rte_flow_item_ipv6 ipv6_mask;
1306
1307         memset(&ipv6, 0, sizeof(ipv6));
1308         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1309         /*
1310          * Even though the DSCP bits offset of IPv6 is not byte aligned,
1311          * rdma-core only accept the DSCP bits byte aligned start from
1312          * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1313          * bits in IPv6 case as rdma-core requires byte aligned value.
1314          */
1315         ipv6.hdr.vtc_flow = conf->dscp;
1316         ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1317         item.spec = &ipv6;
1318         item.mask = &ipv6_mask;
1319         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1320                                              MLX5_MODIFICATION_TYPE_SET, error);
1321 }
1322
1323 /**
1324  * Validate MARK item.
1325  *
1326  * @param[in] dev
1327  *   Pointer to the rte_eth_dev structure.
1328  * @param[in] item
1329  *   Item specification.
1330  * @param[in] attr
1331  *   Attributes of flow that includes this item.
1332  * @param[out] error
1333  *   Pointer to error structure.
1334  *
1335  * @return
1336  *   0 on success, a negative errno value otherwise and rte_errno is set.
1337  */
1338 static int
1339 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1340                            const struct rte_flow_item *item,
1341                            const struct rte_flow_attr *attr __rte_unused,
1342                            struct rte_flow_error *error)
1343 {
1344         struct mlx5_priv *priv = dev->data->dev_private;
1345         struct mlx5_dev_config *config = &priv->config;
1346         const struct rte_flow_item_mark *spec = item->spec;
1347         const struct rte_flow_item_mark *mask = item->mask;
1348         const struct rte_flow_item_mark nic_mask = {
1349                 .id = priv->sh->dv_mark_mask,
1350         };
1351         int ret;
1352
1353         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1354                 return rte_flow_error_set(error, ENOTSUP,
1355                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1356                                           "extended metadata feature"
1357                                           " isn't enabled");
1358         if (!mlx5_flow_ext_mreg_supported(dev))
1359                 return rte_flow_error_set(error, ENOTSUP,
1360                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1361                                           "extended metadata register"
1362                                           " isn't supported");
1363         if (!nic_mask.id)
1364                 return rte_flow_error_set(error, ENOTSUP,
1365                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1366                                           "extended metadata register"
1367                                           " isn't available");
1368         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1369         if (ret < 0)
1370                 return ret;
1371         if (!spec)
1372                 return rte_flow_error_set(error, EINVAL,
1373                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1374                                           item->spec,
1375                                           "data cannot be empty");
1376         if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1377                 return rte_flow_error_set(error, EINVAL,
1378                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1379                                           &spec->id,
1380                                           "mark id exceeds the limit");
1381         if (!mask)
1382                 mask = &nic_mask;
1383         if (!mask->id)
1384                 return rte_flow_error_set(error, EINVAL,
1385                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1386                                         "mask cannot be zero");
1387
1388         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1389                                         (const uint8_t *)&nic_mask,
1390                                         sizeof(struct rte_flow_item_mark),
1391                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1392         if (ret < 0)
1393                 return ret;
1394         return 0;
1395 }
1396
1397 /**
1398  * Validate META item.
1399  *
1400  * @param[in] dev
1401  *   Pointer to the rte_eth_dev structure.
1402  * @param[in] item
1403  *   Item specification.
1404  * @param[in] attr
1405  *   Attributes of flow that includes this item.
1406  * @param[out] error
1407  *   Pointer to error structure.
1408  *
1409  * @return
1410  *   0 on success, a negative errno value otherwise and rte_errno is set.
1411  */
1412 static int
1413 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1414                            const struct rte_flow_item *item,
1415                            const struct rte_flow_attr *attr,
1416                            struct rte_flow_error *error)
1417 {
1418         struct mlx5_priv *priv = dev->data->dev_private;
1419         struct mlx5_dev_config *config = &priv->config;
1420         const struct rte_flow_item_meta *spec = item->spec;
1421         const struct rte_flow_item_meta *mask = item->mask;
1422         struct rte_flow_item_meta nic_mask = {
1423                 .data = UINT32_MAX
1424         };
1425         int reg;
1426         int ret;
1427
1428         if (!spec)
1429                 return rte_flow_error_set(error, EINVAL,
1430                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1431                                           item->spec,
1432                                           "data cannot be empty");
1433         if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1434                 if (!mlx5_flow_ext_mreg_supported(dev))
1435                         return rte_flow_error_set(error, ENOTSUP,
1436                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1437                                           "extended metadata register"
1438                                           " isn't supported");
1439                 reg = flow_dv_get_metadata_reg(dev, attr, error);
1440                 if (reg < 0)
1441                         return reg;
1442                 if (reg == REG_NON)
1443                         return rte_flow_error_set(error, ENOTSUP,
1444                                         RTE_FLOW_ERROR_TYPE_ITEM, item,
1445                                         "unavalable extended metadata register");
1446                 if (reg == REG_B)
1447                         return rte_flow_error_set(error, ENOTSUP,
1448                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1449                                           "match on reg_b "
1450                                           "isn't supported");
1451                 if (reg != REG_A)
1452                         nic_mask.data = priv->sh->dv_meta_mask;
1453         } else if (attr->transfer) {
1454                 return rte_flow_error_set(error, ENOTSUP,
1455                                         RTE_FLOW_ERROR_TYPE_ITEM, item,
1456                                         "extended metadata feature "
1457                                         "should be enabled when "
1458                                         "meta item is requested "
1459                                         "with e-switch mode ");
1460         }
1461         if (!mask)
1462                 mask = &rte_flow_item_meta_mask;
1463         if (!mask->data)
1464                 return rte_flow_error_set(error, EINVAL,
1465                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1466                                         "mask cannot be zero");
1467
1468         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1469                                         (const uint8_t *)&nic_mask,
1470                                         sizeof(struct rte_flow_item_meta),
1471                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1472         return ret;
1473 }
1474
1475 /**
1476  * Validate TAG item.
1477  *
1478  * @param[in] dev
1479  *   Pointer to the rte_eth_dev structure.
1480  * @param[in] item
1481  *   Item specification.
1482  * @param[in] attr
1483  *   Attributes of flow that includes this item.
1484  * @param[out] error
1485  *   Pointer to error structure.
1486  *
1487  * @return
1488  *   0 on success, a negative errno value otherwise and rte_errno is set.
1489  */
1490 static int
1491 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
1492                           const struct rte_flow_item *item,
1493                           const struct rte_flow_attr *attr __rte_unused,
1494                           struct rte_flow_error *error)
1495 {
1496         const struct rte_flow_item_tag *spec = item->spec;
1497         const struct rte_flow_item_tag *mask = item->mask;
1498         const struct rte_flow_item_tag nic_mask = {
1499                 .data = RTE_BE32(UINT32_MAX),
1500                 .index = 0xff,
1501         };
1502         int ret;
1503
1504         if (!mlx5_flow_ext_mreg_supported(dev))
1505                 return rte_flow_error_set(error, ENOTSUP,
1506                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1507                                           "extensive metadata register"
1508                                           " isn't supported");
1509         if (!spec)
1510                 return rte_flow_error_set(error, EINVAL,
1511                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1512                                           item->spec,
1513                                           "data cannot be empty");
1514         if (!mask)
1515                 mask = &rte_flow_item_tag_mask;
1516         if (!mask->data)
1517                 return rte_flow_error_set(error, EINVAL,
1518                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1519                                         "mask cannot be zero");
1520
1521         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1522                                         (const uint8_t *)&nic_mask,
1523                                         sizeof(struct rte_flow_item_tag),
1524                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1525         if (ret < 0)
1526                 return ret;
1527         if (mask->index != 0xff)
1528                 return rte_flow_error_set(error, EINVAL,
1529                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1530                                           "partial mask for tag index"
1531                                           " is not supported");
1532         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
1533         if (ret < 0)
1534                 return ret;
1535         MLX5_ASSERT(ret != REG_NON);
1536         return 0;
1537 }
1538
1539 /**
1540  * Validate vport item.
1541  *
1542  * @param[in] dev
1543  *   Pointer to the rte_eth_dev structure.
1544  * @param[in] item
1545  *   Item specification.
1546  * @param[in] attr
1547  *   Attributes of flow that includes this item.
1548  * @param[in] item_flags
1549  *   Bit-fields that holds the items detected until now.
1550  * @param[out] error
1551  *   Pointer to error structure.
1552  *
1553  * @return
1554  *   0 on success, a negative errno value otherwise and rte_errno is set.
1555  */
1556 static int
1557 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
1558                               const struct rte_flow_item *item,
1559                               const struct rte_flow_attr *attr,
1560                               uint64_t item_flags,
1561                               struct rte_flow_error *error)
1562 {
1563         const struct rte_flow_item_port_id *spec = item->spec;
1564         const struct rte_flow_item_port_id *mask = item->mask;
1565         const struct rte_flow_item_port_id switch_mask = {
1566                         .id = 0xffffffff,
1567         };
1568         struct mlx5_priv *esw_priv;
1569         struct mlx5_priv *dev_priv;
1570         int ret;
1571
1572         if (!attr->transfer)
1573                 return rte_flow_error_set(error, EINVAL,
1574                                           RTE_FLOW_ERROR_TYPE_ITEM,
1575                                           NULL,
1576                                           "match on port id is valid only"
1577                                           " when transfer flag is enabled");
1578         if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
1579                 return rte_flow_error_set(error, ENOTSUP,
1580                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1581                                           "multiple source ports are not"
1582                                           " supported");
1583         if (!mask)
1584                 mask = &switch_mask;
1585         if (mask->id != 0xffffffff)
1586                 return rte_flow_error_set(error, ENOTSUP,
1587                                            RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1588                                            mask,
1589                                            "no support for partial mask on"
1590                                            " \"id\" field");
1591         ret = mlx5_flow_item_acceptable
1592                                 (item, (const uint8_t *)mask,
1593                                  (const uint8_t *)&rte_flow_item_port_id_mask,
1594                                  sizeof(struct rte_flow_item_port_id),
1595                                  MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1596         if (ret)
1597                 return ret;
1598         if (!spec)
1599                 return 0;
1600         esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
1601         if (!esw_priv)
1602                 return rte_flow_error_set(error, rte_errno,
1603                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1604                                           "failed to obtain E-Switch info for"
1605                                           " port");
1606         dev_priv = mlx5_dev_to_eswitch_info(dev);
1607         if (!dev_priv)
1608                 return rte_flow_error_set(error, rte_errno,
1609                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1610                                           NULL,
1611                                           "failed to obtain E-Switch info");
1612         if (esw_priv->domain_id != dev_priv->domain_id)
1613                 return rte_flow_error_set(error, EINVAL,
1614                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1615                                           "cannot match on a port from a"
1616                                           " different E-Switch");
1617         return 0;
1618 }
1619
1620 /**
1621  * Validate VLAN item.
1622  *
1623  * @param[in] item
1624  *   Item specification.
1625  * @param[in] item_flags
1626  *   Bit-fields that holds the items detected until now.
1627  * @param[in] dev
1628  *   Ethernet device flow is being created on.
1629  * @param[out] error
1630  *   Pointer to error structure.
1631  *
1632  * @return
1633  *   0 on success, a negative errno value otherwise and rte_errno is set.
1634  */
1635 static int
1636 flow_dv_validate_item_vlan(const struct rte_flow_item *item,
1637                            uint64_t item_flags,
1638                            struct rte_eth_dev *dev,
1639                            struct rte_flow_error *error)
1640 {
1641         const struct rte_flow_item_vlan *mask = item->mask;
1642         const struct rte_flow_item_vlan nic_mask = {
1643                 .tci = RTE_BE16(UINT16_MAX),
1644                 .inner_type = RTE_BE16(UINT16_MAX),
1645                 .has_more_vlan = 1,
1646         };
1647         const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
1648         int ret;
1649         const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 |
1650                                         MLX5_FLOW_LAYER_INNER_L4) :
1651                                        (MLX5_FLOW_LAYER_OUTER_L3 |
1652                                         MLX5_FLOW_LAYER_OUTER_L4);
1653         const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
1654                                         MLX5_FLOW_LAYER_OUTER_VLAN;
1655
1656         if (item_flags & vlanm)
1657                 return rte_flow_error_set(error, EINVAL,
1658                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1659                                           "multiple VLAN layers not supported");
1660         else if ((item_flags & l34m) != 0)
1661                 return rte_flow_error_set(error, EINVAL,
1662                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1663                                           "VLAN cannot follow L3/L4 layer");
1664         if (!mask)
1665                 mask = &rte_flow_item_vlan_mask;
1666         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1667                                         (const uint8_t *)&nic_mask,
1668                                         sizeof(struct rte_flow_item_vlan),
1669                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1670         if (ret)
1671                 return ret;
1672         if (!tunnel && mask->tci != RTE_BE16(0x0fff)) {
1673                 struct mlx5_priv *priv = dev->data->dev_private;
1674
1675                 if (priv->vmwa_context) {
1676                         /*
1677                          * Non-NULL context means we have a virtual machine
1678                          * and SR-IOV enabled, we have to create VLAN interface
1679                          * to make hypervisor to setup E-Switch vport
1680                          * context correctly. We avoid creating the multiple
1681                          * VLAN interfaces, so we cannot support VLAN tag mask.
1682                          */
1683                         return rte_flow_error_set(error, EINVAL,
1684                                                   RTE_FLOW_ERROR_TYPE_ITEM,
1685                                                   item,
1686                                                   "VLAN tag mask is not"
1687                                                   " supported in virtual"
1688                                                   " environment");
1689                 }
1690         }
1691         return 0;
1692 }
1693
1694 /*
1695  * GTP flags are contained in 1 byte of the format:
1696  * -------------------------------------------
1697  * | bit   | 0 - 2   | 3  | 4   | 5 | 6 | 7  |
1698  * |-----------------------------------------|
1699  * | value | Version | PT | Res | E | S | PN |
1700  * -------------------------------------------
1701  *
1702  * Matching is supported only for GTP flags E, S, PN.
1703  */
1704 #define MLX5_GTP_FLAGS_MASK     0x07
1705
1706 /**
1707  * Validate GTP item.
1708  *
1709  * @param[in] dev
1710  *   Pointer to the rte_eth_dev structure.
1711  * @param[in] item
1712  *   Item specification.
1713  * @param[in] item_flags
1714  *   Bit-fields that holds the items detected until now.
1715  * @param[out] error
1716  *   Pointer to error structure.
1717  *
1718  * @return
1719  *   0 on success, a negative errno value otherwise and rte_errno is set.
1720  */
1721 static int
1722 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
1723                           const struct rte_flow_item *item,
1724                           uint64_t item_flags,
1725                           struct rte_flow_error *error)
1726 {
1727         struct mlx5_priv *priv = dev->data->dev_private;
1728         const struct rte_flow_item_gtp *spec = item->spec;
1729         const struct rte_flow_item_gtp *mask = item->mask;
1730         const struct rte_flow_item_gtp nic_mask = {
1731                 .v_pt_rsv_flags = MLX5_GTP_FLAGS_MASK,
1732                 .msg_type = 0xff,
1733                 .teid = RTE_BE32(0xffffffff),
1734         };
1735
1736         if (!priv->config.hca_attr.tunnel_stateless_gtp)
1737                 return rte_flow_error_set(error, ENOTSUP,
1738                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1739                                           "GTP support is not enabled");
1740         if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
1741                 return rte_flow_error_set(error, ENOTSUP,
1742                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1743                                           "multiple tunnel layers not"
1744                                           " supported");
1745         if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
1746                 return rte_flow_error_set(error, EINVAL,
1747                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1748                                           "no outer UDP layer found");
1749         if (!mask)
1750                 mask = &rte_flow_item_gtp_mask;
1751         if (spec && spec->v_pt_rsv_flags & ~MLX5_GTP_FLAGS_MASK)
1752                 return rte_flow_error_set(error, ENOTSUP,
1753                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1754                                           "Match is supported for GTP"
1755                                           " flags only");
1756         return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1757                                          (const uint8_t *)&nic_mask,
1758                                          sizeof(struct rte_flow_item_gtp),
1759                                          MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1760 }
1761
1762 /**
1763  * Validate GTP PSC item.
1764  *
1765  * @param[in] item
1766  *   Item specification.
1767  * @param[in] last_item
1768  *   Previous validated item in the pattern items.
1769  * @param[in] gtp_item
1770  *   Previous GTP item specification.
1771  * @param[in] attr
1772  *   Pointer to flow attributes.
1773  * @param[out] error
1774  *   Pointer to error structure.
1775  *
1776  * @return
1777  *   0 on success, a negative errno value otherwise and rte_errno is set.
1778  */
1779 static int
1780 flow_dv_validate_item_gtp_psc(const struct rte_flow_item *item,
1781                               uint64_t last_item,
1782                               const struct rte_flow_item *gtp_item,
1783                               const struct rte_flow_attr *attr,
1784                               struct rte_flow_error *error)
1785 {
1786         const struct rte_flow_item_gtp *gtp_spec;
1787         const struct rte_flow_item_gtp *gtp_mask;
1788         const struct rte_flow_item_gtp_psc *spec;
1789         const struct rte_flow_item_gtp_psc *mask;
1790         const struct rte_flow_item_gtp_psc nic_mask = {
1791                 .pdu_type = 0xFF,
1792                 .qfi = 0xFF,
1793         };
1794
1795         if (!gtp_item || !(last_item & MLX5_FLOW_LAYER_GTP))
1796                 return rte_flow_error_set
1797                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
1798                          "GTP PSC item must be preceded with GTP item");
1799         gtp_spec = gtp_item->spec;
1800         gtp_mask = gtp_item->mask ? gtp_item->mask : &rte_flow_item_gtp_mask;
1801         /* GTP spec and E flag is requested to match zero. */
1802         if (gtp_spec &&
1803                 (gtp_mask->v_pt_rsv_flags &
1804                 ~gtp_spec->v_pt_rsv_flags & MLX5_GTP_EXT_HEADER_FLAG))
1805                 return rte_flow_error_set
1806                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
1807                          "GTP E flag must be 1 to match GTP PSC");
1808         /* Check the flow is not created in group zero. */
1809         if (!attr->transfer && !attr->group)
1810                 return rte_flow_error_set
1811                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1812                          "GTP PSC is not supported for group 0");
1813         /* GTP spec is here and E flag is requested to match zero. */
1814         if (!item->spec)
1815                 return 0;
1816         spec = item->spec;
1817         mask = item->mask ? item->mask : &rte_flow_item_gtp_psc_mask;
1818         if (spec->pdu_type > MLX5_GTP_EXT_MAX_PDU_TYPE)
1819                 return rte_flow_error_set
1820                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
1821                          "PDU type should be smaller than 16");
1822         return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1823                                          (const uint8_t *)&nic_mask,
1824                                          sizeof(struct rte_flow_item_gtp_psc),
1825                                          MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1826 }
1827
1828 /**
1829  * Validate IPV4 item.
1830  * Use existing validation function mlx5_flow_validate_item_ipv4(), and
1831  * add specific validation of fragment_offset field,
1832  *
1833  * @param[in] item
1834  *   Item specification.
1835  * @param[in] item_flags
1836  *   Bit-fields that holds the items detected until now.
1837  * @param[out] error
1838  *   Pointer to error structure.
1839  *
1840  * @return
1841  *   0 on success, a negative errno value otherwise and rte_errno is set.
1842  */
1843 static int
1844 flow_dv_validate_item_ipv4(const struct rte_flow_item *item,
1845                            uint64_t item_flags,
1846                            uint64_t last_item,
1847                            uint16_t ether_type,
1848                            struct rte_flow_error *error)
1849 {
1850         int ret;
1851         const struct rte_flow_item_ipv4 *spec = item->spec;
1852         const struct rte_flow_item_ipv4 *last = item->last;
1853         const struct rte_flow_item_ipv4 *mask = item->mask;
1854         rte_be16_t fragment_offset_spec = 0;
1855         rte_be16_t fragment_offset_last = 0;
1856         const struct rte_flow_item_ipv4 nic_ipv4_mask = {
1857                 .hdr = {
1858                         .src_addr = RTE_BE32(0xffffffff),
1859                         .dst_addr = RTE_BE32(0xffffffff),
1860                         .type_of_service = 0xff,
1861                         .fragment_offset = RTE_BE16(0xffff),
1862                         .next_proto_id = 0xff,
1863                         .time_to_live = 0xff,
1864                 },
1865         };
1866
1867         ret = mlx5_flow_validate_item_ipv4(item, item_flags, last_item,
1868                                            ether_type, &nic_ipv4_mask,
1869                                            MLX5_ITEM_RANGE_ACCEPTED, error);
1870         if (ret < 0)
1871                 return ret;
1872         if (spec && mask)
1873                 fragment_offset_spec = spec->hdr.fragment_offset &
1874                                        mask->hdr.fragment_offset;
1875         if (!fragment_offset_spec)
1876                 return 0;
1877         /*
1878          * spec and mask are valid, enforce using full mask to make sure the
1879          * complete value is used correctly.
1880          */
1881         if ((mask->hdr.fragment_offset & RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
1882                         != RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
1883                 return rte_flow_error_set(error, EINVAL,
1884                                           RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1885                                           item, "must use full mask for"
1886                                           " fragment_offset");
1887         /*
1888          * Match on fragment_offset 0x2000 means MF is 1 and frag-offset is 0,
1889          * indicating this is 1st fragment of fragmented packet.
1890          * This is not yet supported in MLX5, return appropriate error message.
1891          */
1892         if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG))
1893                 return rte_flow_error_set(error, ENOTSUP,
1894                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1895                                           "match on first fragment not "
1896                                           "supported");
1897         if (fragment_offset_spec && !last)
1898                 return rte_flow_error_set(error, ENOTSUP,
1899                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1900                                           "specified value not supported");
1901         /* spec and last are valid, validate the specified range. */
1902         fragment_offset_last = last->hdr.fragment_offset &
1903                                mask->hdr.fragment_offset;
1904         /*
1905          * Match on fragment_offset spec 0x2001 and last 0x3fff
1906          * means MF is 1 and frag-offset is > 0.
1907          * This packet is fragment 2nd and onward, excluding last.
1908          * This is not yet supported in MLX5, return appropriate
1909          * error message.
1910          */
1911         if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG + 1) &&
1912             fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
1913                 return rte_flow_error_set(error, ENOTSUP,
1914                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
1915                                           last, "match on following "
1916                                           "fragments not supported");
1917         /*
1918          * Match on fragment_offset spec 0x0001 and last 0x1fff
1919          * means MF is 0 and frag-offset is > 0.
1920          * This packet is last fragment of fragmented packet.
1921          * This is not yet supported in MLX5, return appropriate
1922          * error message.
1923          */
1924         if (fragment_offset_spec == RTE_BE16(1) &&
1925             fragment_offset_last == RTE_BE16(RTE_IPV4_HDR_OFFSET_MASK))
1926                 return rte_flow_error_set(error, ENOTSUP,
1927                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
1928                                           last, "match on last "
1929                                           "fragment not supported");
1930         /*
1931          * Match on fragment_offset spec 0x0001 and last 0x3fff
1932          * means MF and/or frag-offset is not 0.
1933          * This is a fragmented packet.
1934          * Other range values are invalid and rejected.
1935          */
1936         if (!(fragment_offset_spec == RTE_BE16(1) &&
1937               fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK)))
1938                 return rte_flow_error_set(error, ENOTSUP,
1939                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
1940                                           "specified range not supported");
1941         return 0;
1942 }
1943
1944 /**
1945  * Validate IPV6 fragment extension item.
1946  *
1947  * @param[in] item
1948  *   Item specification.
1949  * @param[in] item_flags
1950  *   Bit-fields that holds the items detected until now.
1951  * @param[out] error
1952  *   Pointer to error structure.
1953  *
1954  * @return
1955  *   0 on success, a negative errno value otherwise and rte_errno is set.
1956  */
1957 static int
1958 flow_dv_validate_item_ipv6_frag_ext(const struct rte_flow_item *item,
1959                                     uint64_t item_flags,
1960                                     struct rte_flow_error *error)
1961 {
1962         const struct rte_flow_item_ipv6_frag_ext *spec = item->spec;
1963         const struct rte_flow_item_ipv6_frag_ext *last = item->last;
1964         const struct rte_flow_item_ipv6_frag_ext *mask = item->mask;
1965         rte_be16_t frag_data_spec = 0;
1966         rte_be16_t frag_data_last = 0;
1967         const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
1968         const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 :
1969                                       MLX5_FLOW_LAYER_OUTER_L4;
1970         int ret = 0;
1971         struct rte_flow_item_ipv6_frag_ext nic_mask = {
1972                 .hdr = {
1973                         .next_header = 0xff,
1974                         .frag_data = RTE_BE16(0xffff),
1975                 },
1976         };
1977
1978         if (item_flags & l4m)
1979                 return rte_flow_error_set(error, EINVAL,
1980                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1981                                           "ipv6 fragment extension item cannot "
1982                                           "follow L4 item.");
1983         if ((tunnel && !(item_flags & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
1984             (!tunnel && !(item_flags & MLX5_FLOW_LAYER_OUTER_L3_IPV6)))
1985                 return rte_flow_error_set(error, EINVAL,
1986                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1987                                           "ipv6 fragment extension item must "
1988                                           "follow ipv6 item");
1989         if (spec && mask)
1990                 frag_data_spec = spec->hdr.frag_data & mask->hdr.frag_data;
1991         if (!frag_data_spec)
1992                 return 0;
1993         /*
1994          * spec and mask are valid, enforce using full mask to make sure the
1995          * complete value is used correctly.
1996          */
1997         if ((mask->hdr.frag_data & RTE_BE16(RTE_IPV6_FRAG_USED_MASK)) !=
1998                                 RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
1999                 return rte_flow_error_set(error, EINVAL,
2000                                           RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2001                                           item, "must use full mask for"
2002                                           " frag_data");
2003         /*
2004          * Match on frag_data 0x00001 means M is 1 and frag-offset is 0.
2005          * This is 1st fragment of fragmented packet.
2006          */
2007         if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_MF_MASK))
2008                 return rte_flow_error_set(error, ENOTSUP,
2009                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2010                                           "match on first fragment not "
2011                                           "supported");
2012         if (frag_data_spec && !last)
2013                 return rte_flow_error_set(error, EINVAL,
2014                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2015                                           "specified value not supported");
2016         ret = mlx5_flow_item_acceptable
2017                                 (item, (const uint8_t *)mask,
2018                                  (const uint8_t *)&nic_mask,
2019                                  sizeof(struct rte_flow_item_ipv6_frag_ext),
2020                                  MLX5_ITEM_RANGE_ACCEPTED, error);
2021         if (ret)
2022                 return ret;
2023         /* spec and last are valid, validate the specified range. */
2024         frag_data_last = last->hdr.frag_data & mask->hdr.frag_data;
2025         /*
2026          * Match on frag_data spec 0x0009 and last 0xfff9
2027          * means M is 1 and frag-offset is > 0.
2028          * This packet is fragment 2nd and onward, excluding last.
2029          * This is not yet supported in MLX5, return appropriate
2030          * error message.
2031          */
2032         if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN |
2033                                        RTE_IPV6_EHDR_MF_MASK) &&
2034             frag_data_last == RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2035                 return rte_flow_error_set(error, ENOTSUP,
2036                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2037                                           last, "match on following "
2038                                           "fragments not supported");
2039         /*
2040          * Match on frag_data spec 0x0008 and last 0xfff8
2041          * means M is 0 and frag-offset is > 0.
2042          * This packet is last fragment of fragmented packet.
2043          * This is not yet supported in MLX5, return appropriate
2044          * error message.
2045          */
2046         if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN) &&
2047             frag_data_last == RTE_BE16(RTE_IPV6_EHDR_FO_MASK))
2048                 return rte_flow_error_set(error, ENOTSUP,
2049                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2050                                           last, "match on last "
2051                                           "fragment not supported");
2052         /* Other range values are invalid and rejected. */
2053         return rte_flow_error_set(error, EINVAL,
2054                                   RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2055                                   "specified range not supported");
2056 }
2057
2058 /**
2059  * Validate the pop VLAN action.
2060  *
2061  * @param[in] dev
2062  *   Pointer to the rte_eth_dev structure.
2063  * @param[in] action_flags
2064  *   Holds the actions detected until now.
2065  * @param[in] action
2066  *   Pointer to the pop vlan action.
2067  * @param[in] item_flags
2068  *   The items found in this flow rule.
2069  * @param[in] attr
2070  *   Pointer to flow attributes.
2071  * @param[out] error
2072  *   Pointer to error structure.
2073  *
2074  * @return
2075  *   0 on success, a negative errno value otherwise and rte_errno is set.
2076  */
2077 static int
2078 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
2079                                  uint64_t action_flags,
2080                                  const struct rte_flow_action *action,
2081                                  uint64_t item_flags,
2082                                  const struct rte_flow_attr *attr,
2083                                  struct rte_flow_error *error)
2084 {
2085         const struct mlx5_priv *priv = dev->data->dev_private;
2086
2087         (void)action;
2088         (void)attr;
2089         if (!priv->sh->pop_vlan_action)
2090                 return rte_flow_error_set(error, ENOTSUP,
2091                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2092                                           NULL,
2093                                           "pop vlan action is not supported");
2094         if (attr->egress)
2095                 return rte_flow_error_set(error, ENOTSUP,
2096                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2097                                           NULL,
2098                                           "pop vlan action not supported for "
2099                                           "egress");
2100         if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
2101                 return rte_flow_error_set(error, ENOTSUP,
2102                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2103                                           "no support for multiple VLAN "
2104                                           "actions");
2105         /* Pop VLAN with preceding Decap requires inner header with VLAN. */
2106         if ((action_flags & MLX5_FLOW_ACTION_DECAP) &&
2107             !(item_flags & MLX5_FLOW_LAYER_INNER_VLAN))
2108                 return rte_flow_error_set(error, ENOTSUP,
2109                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2110                                           NULL,
2111                                           "cannot pop vlan after decap without "
2112                                           "match on inner vlan in the flow");
2113         /* Pop VLAN without preceding Decap requires outer header with VLAN. */
2114         if (!(action_flags & MLX5_FLOW_ACTION_DECAP) &&
2115             !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2116                 return rte_flow_error_set(error, ENOTSUP,
2117                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2118                                           NULL,
2119                                           "cannot pop vlan without a "
2120                                           "match on (outer) vlan in the flow");
2121         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2122                 return rte_flow_error_set(error, EINVAL,
2123                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2124                                           "wrong action order, port_id should "
2125                                           "be after pop VLAN action");
2126         if (!attr->transfer && priv->representor)
2127                 return rte_flow_error_set(error, ENOTSUP,
2128                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2129                                           "pop vlan action for VF representor "
2130                                           "not supported on NIC table");
2131         return 0;
2132 }
2133
2134 /**
2135  * Get VLAN default info from vlan match info.
2136  *
2137  * @param[in] items
2138  *   the list of item specifications.
2139  * @param[out] vlan
2140  *   pointer VLAN info to fill to.
2141  *
2142  * @return
2143  *   0 on success, a negative errno value otherwise and rte_errno is set.
2144  */
2145 static void
2146 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
2147                                   struct rte_vlan_hdr *vlan)
2148 {
2149         const struct rte_flow_item_vlan nic_mask = {
2150                 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
2151                                 MLX5DV_FLOW_VLAN_VID_MASK),
2152                 .inner_type = RTE_BE16(0xffff),
2153         };
2154
2155         if (items == NULL)
2156                 return;
2157         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2158                 int type = items->type;
2159
2160                 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
2161                     type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
2162                         break;
2163         }
2164         if (items->type != RTE_FLOW_ITEM_TYPE_END) {
2165                 const struct rte_flow_item_vlan *vlan_m = items->mask;
2166                 const struct rte_flow_item_vlan *vlan_v = items->spec;
2167
2168                 /* If VLAN item in pattern doesn't contain data, return here. */
2169                 if (!vlan_v)
2170                         return;
2171                 if (!vlan_m)
2172                         vlan_m = &nic_mask;
2173                 /* Only full match values are accepted */
2174                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
2175                      MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
2176                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
2177                         vlan->vlan_tci |=
2178                                 rte_be_to_cpu_16(vlan_v->tci &
2179                                                  MLX5DV_FLOW_VLAN_PCP_MASK_BE);
2180                 }
2181                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
2182                      MLX5DV_FLOW_VLAN_VID_MASK_BE) {
2183                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
2184                         vlan->vlan_tci |=
2185                                 rte_be_to_cpu_16(vlan_v->tci &
2186                                                  MLX5DV_FLOW_VLAN_VID_MASK_BE);
2187                 }
2188                 if (vlan_m->inner_type == nic_mask.inner_type)
2189                         vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
2190                                                            vlan_m->inner_type);
2191         }
2192 }
2193
2194 /**
2195  * Validate the push VLAN action.
2196  *
2197  * @param[in] dev
2198  *   Pointer to the rte_eth_dev structure.
2199  * @param[in] action_flags
2200  *   Holds the actions detected until now.
2201  * @param[in] item_flags
2202  *   The items found in this flow rule.
2203  * @param[in] action
2204  *   Pointer to the action structure.
2205  * @param[in] attr
2206  *   Pointer to flow attributes
2207  * @param[out] error
2208  *   Pointer to error structure.
2209  *
2210  * @return
2211  *   0 on success, a negative errno value otherwise and rte_errno is set.
2212  */
2213 static int
2214 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
2215                                   uint64_t action_flags,
2216                                   const struct rte_flow_item_vlan *vlan_m,
2217                                   const struct rte_flow_action *action,
2218                                   const struct rte_flow_attr *attr,
2219                                   struct rte_flow_error *error)
2220 {
2221         const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
2222         const struct mlx5_priv *priv = dev->data->dev_private;
2223
2224         if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
2225             push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
2226                 return rte_flow_error_set(error, EINVAL,
2227                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2228                                           "invalid vlan ethertype");
2229         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2230                 return rte_flow_error_set(error, EINVAL,
2231                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2232                                           "wrong action order, port_id should "
2233                                           "be after push VLAN");
2234         if (!attr->transfer && priv->representor)
2235                 return rte_flow_error_set(error, ENOTSUP,
2236                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2237                                           "push vlan action for VF representor "
2238                                           "not supported on NIC table");
2239         if (vlan_m &&
2240             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
2241             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
2242                 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
2243             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
2244             !(mlx5_flow_find_action
2245                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
2246                 return rte_flow_error_set(error, EINVAL,
2247                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2248                                           "not full match mask on VLAN PCP and "
2249                                           "there is no of_set_vlan_pcp action, "
2250                                           "push VLAN action cannot figure out "
2251                                           "PCP value");
2252         if (vlan_m &&
2253             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
2254             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
2255                 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
2256             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
2257             !(mlx5_flow_find_action
2258                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
2259                 return rte_flow_error_set(error, EINVAL,
2260                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2261                                           "not full match mask on VLAN VID and "
2262                                           "there is no of_set_vlan_vid action, "
2263                                           "push VLAN action cannot figure out "
2264                                           "VID value");
2265         (void)attr;
2266         return 0;
2267 }
2268
2269 /**
2270  * Validate the set VLAN PCP.
2271  *
2272  * @param[in] action_flags
2273  *   Holds the actions detected until now.
2274  * @param[in] actions
2275  *   Pointer to the list of actions remaining in the flow rule.
2276  * @param[out] error
2277  *   Pointer to error structure.
2278  *
2279  * @return
2280  *   0 on success, a negative errno value otherwise and rte_errno is set.
2281  */
2282 static int
2283 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
2284                                      const struct rte_flow_action actions[],
2285                                      struct rte_flow_error *error)
2286 {
2287         const struct rte_flow_action *action = actions;
2288         const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
2289
2290         if (conf->vlan_pcp > 7)
2291                 return rte_flow_error_set(error, EINVAL,
2292                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2293                                           "VLAN PCP value is too big");
2294         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
2295                 return rte_flow_error_set(error, ENOTSUP,
2296                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2297                                           "set VLAN PCP action must follow "
2298                                           "the push VLAN action");
2299         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
2300                 return rte_flow_error_set(error, ENOTSUP,
2301                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2302                                           "Multiple VLAN PCP modification are "
2303                                           "not supported");
2304         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2305                 return rte_flow_error_set(error, EINVAL,
2306                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2307                                           "wrong action order, port_id should "
2308                                           "be after set VLAN PCP");
2309         return 0;
2310 }
2311
2312 /**
2313  * Validate the set VLAN VID.
2314  *
2315  * @param[in] item_flags
2316  *   Holds the items detected in this rule.
2317  * @param[in] action_flags
2318  *   Holds the actions detected until now.
2319  * @param[in] actions
2320  *   Pointer to the list of actions remaining in the flow rule.
2321  * @param[out] error
2322  *   Pointer to error structure.
2323  *
2324  * @return
2325  *   0 on success, a negative errno value otherwise and rte_errno is set.
2326  */
2327 static int
2328 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
2329                                      uint64_t action_flags,
2330                                      const struct rte_flow_action actions[],
2331                                      struct rte_flow_error *error)
2332 {
2333         const struct rte_flow_action *action = actions;
2334         const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
2335
2336         if (rte_be_to_cpu_16(conf->vlan_vid) > 0xFFE)
2337                 return rte_flow_error_set(error, EINVAL,
2338                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2339                                           "VLAN VID value is too big");
2340         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
2341             !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2342                 return rte_flow_error_set(error, ENOTSUP,
2343                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2344                                           "set VLAN VID action must follow push"
2345                                           " VLAN action or match on VLAN item");
2346         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
2347                 return rte_flow_error_set(error, ENOTSUP,
2348                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2349                                           "Multiple VLAN VID modifications are "
2350                                           "not supported");
2351         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2352                 return rte_flow_error_set(error, EINVAL,
2353                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2354                                           "wrong action order, port_id should "
2355                                           "be after set VLAN VID");
2356         return 0;
2357 }
2358
2359 /*
2360  * Validate the FLAG action.
2361  *
2362  * @param[in] dev
2363  *   Pointer to the rte_eth_dev structure.
2364  * @param[in] action_flags
2365  *   Holds the actions detected until now.
2366  * @param[in] attr
2367  *   Pointer to flow attributes
2368  * @param[out] error
2369  *   Pointer to error structure.
2370  *
2371  * @return
2372  *   0 on success, a negative errno value otherwise and rte_errno is set.
2373  */
2374 static int
2375 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
2376                              uint64_t action_flags,
2377                              const struct rte_flow_attr *attr,
2378                              struct rte_flow_error *error)
2379 {
2380         struct mlx5_priv *priv = dev->data->dev_private;
2381         struct mlx5_dev_config *config = &priv->config;
2382         int ret;
2383
2384         /* Fall back if no extended metadata register support. */
2385         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2386                 return mlx5_flow_validate_action_flag(action_flags, attr,
2387                                                       error);
2388         /* Extensive metadata mode requires registers. */
2389         if (!mlx5_flow_ext_mreg_supported(dev))
2390                 return rte_flow_error_set(error, ENOTSUP,
2391                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2392                                           "no metadata registers "
2393                                           "to support flag action");
2394         if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
2395                 return rte_flow_error_set(error, ENOTSUP,
2396                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2397                                           "extended metadata register"
2398                                           " isn't available");
2399         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2400         if (ret < 0)
2401                 return ret;
2402         MLX5_ASSERT(ret > 0);
2403         if (action_flags & MLX5_FLOW_ACTION_MARK)
2404                 return rte_flow_error_set(error, EINVAL,
2405                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2406                                           "can't mark and flag in same flow");
2407         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2408                 return rte_flow_error_set(error, EINVAL,
2409                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2410                                           "can't have 2 flag"
2411                                           " actions in same flow");
2412         return 0;
2413 }
2414
2415 /**
2416  * Validate MARK action.
2417  *
2418  * @param[in] dev
2419  *   Pointer to the rte_eth_dev structure.
2420  * @param[in] action
2421  *   Pointer to action.
2422  * @param[in] action_flags
2423  *   Holds the actions detected until now.
2424  * @param[in] attr
2425  *   Pointer to flow attributes
2426  * @param[out] error
2427  *   Pointer to error structure.
2428  *
2429  * @return
2430  *   0 on success, a negative errno value otherwise and rte_errno is set.
2431  */
2432 static int
2433 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
2434                              const struct rte_flow_action *action,
2435                              uint64_t action_flags,
2436                              const struct rte_flow_attr *attr,
2437                              struct rte_flow_error *error)
2438 {
2439         struct mlx5_priv *priv = dev->data->dev_private;
2440         struct mlx5_dev_config *config = &priv->config;
2441         const struct rte_flow_action_mark *mark = action->conf;
2442         int ret;
2443
2444         /* Fall back if no extended metadata register support. */
2445         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2446                 return mlx5_flow_validate_action_mark(action, action_flags,
2447                                                       attr, error);
2448         /* Extensive metadata mode requires registers. */
2449         if (!mlx5_flow_ext_mreg_supported(dev))
2450                 return rte_flow_error_set(error, ENOTSUP,
2451                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2452                                           "no metadata registers "
2453                                           "to support mark action");
2454         if (!priv->sh->dv_mark_mask)
2455                 return rte_flow_error_set(error, ENOTSUP,
2456                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2457                                           "extended metadata register"
2458                                           " isn't available");
2459         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2460         if (ret < 0)
2461                 return ret;
2462         MLX5_ASSERT(ret > 0);
2463         if (!mark)
2464                 return rte_flow_error_set(error, EINVAL,
2465                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2466                                           "configuration cannot be null");
2467         if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
2468                 return rte_flow_error_set(error, EINVAL,
2469                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2470                                           &mark->id,
2471                                           "mark id exceeds the limit");
2472         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2473                 return rte_flow_error_set(error, EINVAL,
2474                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2475                                           "can't flag and mark in same flow");
2476         if (action_flags & MLX5_FLOW_ACTION_MARK)
2477                 return rte_flow_error_set(error, EINVAL,
2478                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2479                                           "can't have 2 mark actions in same"
2480                                           " flow");
2481         return 0;
2482 }
2483
2484 /**
2485  * Validate SET_META action.
2486  *
2487  * @param[in] dev
2488  *   Pointer to the rte_eth_dev structure.
2489  * @param[in] action
2490  *   Pointer to the action structure.
2491  * @param[in] action_flags
2492  *   Holds the actions detected until now.
2493  * @param[in] attr
2494  *   Pointer to flow attributes
2495  * @param[out] error
2496  *   Pointer to error structure.
2497  *
2498  * @return
2499  *   0 on success, a negative errno value otherwise and rte_errno is set.
2500  */
2501 static int
2502 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
2503                                  const struct rte_flow_action *action,
2504                                  uint64_t action_flags __rte_unused,
2505                                  const struct rte_flow_attr *attr,
2506                                  struct rte_flow_error *error)
2507 {
2508         const struct rte_flow_action_set_meta *conf;
2509         uint32_t nic_mask = UINT32_MAX;
2510         int reg;
2511
2512         if (!mlx5_flow_ext_mreg_supported(dev))
2513                 return rte_flow_error_set(error, ENOTSUP,
2514                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2515                                           "extended metadata register"
2516                                           " isn't supported");
2517         reg = flow_dv_get_metadata_reg(dev, attr, error);
2518         if (reg < 0)
2519                 return reg;
2520         if (reg == REG_NON)
2521                 return rte_flow_error_set(error, ENOTSUP,
2522                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2523                                           "unavalable extended metadata register");
2524         if (reg != REG_A && reg != REG_B) {
2525                 struct mlx5_priv *priv = dev->data->dev_private;
2526
2527                 nic_mask = priv->sh->dv_meta_mask;
2528         }
2529         if (!(action->conf))
2530                 return rte_flow_error_set(error, EINVAL,
2531                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2532                                           "configuration cannot be null");
2533         conf = (const struct rte_flow_action_set_meta *)action->conf;
2534         if (!conf->mask)
2535                 return rte_flow_error_set(error, EINVAL,
2536                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2537                                           "zero mask doesn't have any effect");
2538         if (conf->mask & ~nic_mask)
2539                 return rte_flow_error_set(error, EINVAL,
2540                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2541                                           "meta data must be within reg C0");
2542         return 0;
2543 }
2544
2545 /**
2546  * Validate SET_TAG action.
2547  *
2548  * @param[in] dev
2549  *   Pointer to the rte_eth_dev structure.
2550  * @param[in] action
2551  *   Pointer to the action structure.
2552  * @param[in] action_flags
2553  *   Holds the actions detected until now.
2554  * @param[in] attr
2555  *   Pointer to flow attributes
2556  * @param[out] error
2557  *   Pointer to error structure.
2558  *
2559  * @return
2560  *   0 on success, a negative errno value otherwise and rte_errno is set.
2561  */
2562 static int
2563 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
2564                                 const struct rte_flow_action *action,
2565                                 uint64_t action_flags,
2566                                 const struct rte_flow_attr *attr,
2567                                 struct rte_flow_error *error)
2568 {
2569         const struct rte_flow_action_set_tag *conf;
2570         const uint64_t terminal_action_flags =
2571                 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
2572                 MLX5_FLOW_ACTION_RSS;
2573         int ret;
2574
2575         if (!mlx5_flow_ext_mreg_supported(dev))
2576                 return rte_flow_error_set(error, ENOTSUP,
2577                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2578                                           "extensive metadata register"
2579                                           " isn't supported");
2580         if (!(action->conf))
2581                 return rte_flow_error_set(error, EINVAL,
2582                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2583                                           "configuration cannot be null");
2584         conf = (const struct rte_flow_action_set_tag *)action->conf;
2585         if (!conf->mask)
2586                 return rte_flow_error_set(error, EINVAL,
2587                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2588                                           "zero mask doesn't have any effect");
2589         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
2590         if (ret < 0)
2591                 return ret;
2592         if (!attr->transfer && attr->ingress &&
2593             (action_flags & terminal_action_flags))
2594                 return rte_flow_error_set(error, EINVAL,
2595                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2596                                           "set_tag has no effect"
2597                                           " with terminal actions");
2598         return 0;
2599 }
2600
2601 /**
2602  * Validate count action.
2603  *
2604  * @param[in] dev
2605  *   Pointer to rte_eth_dev structure.
2606  * @param[out] error
2607  *   Pointer to error structure.
2608  *
2609  * @return
2610  *   0 on success, a negative errno value otherwise and rte_errno is set.
2611  */
2612 static int
2613 flow_dv_validate_action_count(struct rte_eth_dev *dev,
2614                               struct rte_flow_error *error)
2615 {
2616         struct mlx5_priv *priv = dev->data->dev_private;
2617
2618         if (!priv->config.devx)
2619                 goto notsup_err;
2620 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
2621         return 0;
2622 #endif
2623 notsup_err:
2624         return rte_flow_error_set
2625                       (error, ENOTSUP,
2626                        RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2627                        NULL,
2628                        "count action not supported");
2629 }
2630
2631 /**
2632  * Validate the L2 encap action.
2633  *
2634  * @param[in] dev
2635  *   Pointer to the rte_eth_dev structure.
2636  * @param[in] action_flags
2637  *   Holds the actions detected until now.
2638  * @param[in] action
2639  *   Pointer to the action structure.
2640  * @param[in] attr
2641  *   Pointer to flow attributes.
2642  * @param[out] error
2643  *   Pointer to error structure.
2644  *
2645  * @return
2646  *   0 on success, a negative errno value otherwise and rte_errno is set.
2647  */
2648 static int
2649 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
2650                                  uint64_t action_flags,
2651                                  const struct rte_flow_action *action,
2652                                  const struct rte_flow_attr *attr,
2653                                  struct rte_flow_error *error)
2654 {
2655         const struct mlx5_priv *priv = dev->data->dev_private;
2656
2657         if (!(action->conf))
2658                 return rte_flow_error_set(error, EINVAL,
2659                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2660                                           "configuration cannot be null");
2661         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
2662                 return rte_flow_error_set(error, EINVAL,
2663                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2664                                           "can only have a single encap action "
2665                                           "in a flow");
2666         if (!attr->transfer && priv->representor)
2667                 return rte_flow_error_set(error, ENOTSUP,
2668                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2669                                           "encap action for VF representor "
2670                                           "not supported on NIC table");
2671         return 0;
2672 }
2673
2674 /**
2675  * Validate a decap action.
2676  *
2677  * @param[in] dev
2678  *   Pointer to the rte_eth_dev structure.
2679  * @param[in] action_flags
2680  *   Holds the actions detected until now.
2681  * @param[in] action
2682  *   Pointer to the action structure.
2683  * @param[in] item_flags
2684  *   Holds the items detected.
2685  * @param[in] attr
2686  *   Pointer to flow attributes
2687  * @param[out] error
2688  *   Pointer to error structure.
2689  *
2690  * @return
2691  *   0 on success, a negative errno value otherwise and rte_errno is set.
2692  */
2693 static int
2694 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
2695                               uint64_t action_flags,
2696                               const struct rte_flow_action *action,
2697                               const uint64_t item_flags,
2698                               const struct rte_flow_attr *attr,
2699                               struct rte_flow_error *error)
2700 {
2701         const struct mlx5_priv *priv = dev->data->dev_private;
2702
2703         if (priv->config.hca_attr.scatter_fcs_w_decap_disable &&
2704             !priv->config.decap_en)
2705                 return rte_flow_error_set(error, ENOTSUP,
2706                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2707                                           "decap is not enabled");
2708         if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
2709                 return rte_flow_error_set(error, ENOTSUP,
2710                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2711                                           action_flags &
2712                                           MLX5_FLOW_ACTION_DECAP ? "can only "
2713                                           "have a single decap action" : "decap "
2714                                           "after encap is not supported");
2715         if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
2716                 return rte_flow_error_set(error, EINVAL,
2717                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2718                                           "can't have decap action after"
2719                                           " modify action");
2720         if (attr->egress)
2721                 return rte_flow_error_set(error, ENOTSUP,
2722                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2723                                           NULL,
2724                                           "decap action not supported for "
2725                                           "egress");
2726         if (!attr->transfer && priv->representor)
2727                 return rte_flow_error_set(error, ENOTSUP,
2728                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2729                                           "decap action for VF representor "
2730                                           "not supported on NIC table");
2731         if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_DECAP &&
2732             !(item_flags & MLX5_FLOW_LAYER_VXLAN))
2733                 return rte_flow_error_set(error, ENOTSUP,
2734                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2735                                 "VXLAN item should be present for VXLAN decap");
2736         return 0;
2737 }
2738
2739 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
2740
2741 /**
2742  * Validate the raw encap and decap actions.
2743  *
2744  * @param[in] dev
2745  *   Pointer to the rte_eth_dev structure.
2746  * @param[in] decap
2747  *   Pointer to the decap action.
2748  * @param[in] encap
2749  *   Pointer to the encap action.
2750  * @param[in] attr
2751  *   Pointer to flow attributes
2752  * @param[in/out] action_flags
2753  *   Holds the actions detected until now.
2754  * @param[out] actions_n
2755  *   pointer to the number of actions counter.
2756  * @param[in] action
2757  *   Pointer to the action structure.
2758  * @param[in] item_flags
2759  *   Holds the items detected.
2760  * @param[out] error
2761  *   Pointer to error structure.
2762  *
2763  * @return
2764  *   0 on success, a negative errno value otherwise and rte_errno is set.
2765  */
2766 static int
2767 flow_dv_validate_action_raw_encap_decap
2768         (struct rte_eth_dev *dev,
2769          const struct rte_flow_action_raw_decap *decap,
2770          const struct rte_flow_action_raw_encap *encap,
2771          const struct rte_flow_attr *attr, uint64_t *action_flags,
2772          int *actions_n, const struct rte_flow_action *action,
2773          uint64_t item_flags, struct rte_flow_error *error)
2774 {
2775         const struct mlx5_priv *priv = dev->data->dev_private;
2776         int ret;
2777
2778         if (encap && (!encap->size || !encap->data))
2779                 return rte_flow_error_set(error, EINVAL,
2780                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2781                                           "raw encap data cannot be empty");
2782         if (decap && encap) {
2783                 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
2784                     encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
2785                         /* L3 encap. */
2786                         decap = NULL;
2787                 else if (encap->size <=
2788                            MLX5_ENCAPSULATION_DECISION_SIZE &&
2789                            decap->size >
2790                            MLX5_ENCAPSULATION_DECISION_SIZE)
2791                         /* L3 decap. */
2792                         encap = NULL;
2793                 else if (encap->size >
2794                            MLX5_ENCAPSULATION_DECISION_SIZE &&
2795                            decap->size >
2796                            MLX5_ENCAPSULATION_DECISION_SIZE)
2797                         /* 2 L2 actions: encap and decap. */
2798                         ;
2799                 else
2800                         return rte_flow_error_set(error,
2801                                 ENOTSUP,
2802                                 RTE_FLOW_ERROR_TYPE_ACTION,
2803                                 NULL, "unsupported too small "
2804                                 "raw decap and too small raw "
2805                                 "encap combination");
2806         }
2807         if (decap) {
2808                 ret = flow_dv_validate_action_decap(dev, *action_flags, action,
2809                                                     item_flags, attr, error);
2810                 if (ret < 0)
2811                         return ret;
2812                 *action_flags |= MLX5_FLOW_ACTION_DECAP;
2813                 ++(*actions_n);
2814         }
2815         if (encap) {
2816                 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
2817                         return rte_flow_error_set(error, ENOTSUP,
2818                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2819                                                   NULL,
2820                                                   "small raw encap size");
2821                 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
2822                         return rte_flow_error_set(error, EINVAL,
2823                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2824                                                   NULL,
2825                                                   "more than one encap action");
2826                 if (!attr->transfer && priv->representor)
2827                         return rte_flow_error_set
2828                                         (error, ENOTSUP,
2829                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2830                                          "encap action for VF representor "
2831                                          "not supported on NIC table");
2832                 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
2833                 ++(*actions_n);
2834         }
2835         return 0;
2836 }
2837
2838 /**
2839  * Match encap_decap resource.
2840  *
2841  * @param list
2842  *   Pointer to the hash list.
2843  * @param entry
2844  *   Pointer to exist resource entry object.
2845  * @param key
2846  *   Key of the new entry.
2847  * @param ctx_cb
2848  *   Pointer to new encap_decap resource.
2849  *
2850  * @return
2851  *   0 on matching, none-zero otherwise.
2852  */
2853 int
2854 flow_dv_encap_decap_match_cb(struct mlx5_hlist *list __rte_unused,
2855                              struct mlx5_hlist_entry *entry,
2856                              uint64_t key __rte_unused, void *cb_ctx)
2857 {
2858         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
2859         struct mlx5_flow_dv_encap_decap_resource *resource = ctx->data;
2860         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2861
2862         cache_resource = container_of(entry,
2863                                       struct mlx5_flow_dv_encap_decap_resource,
2864                                       entry);
2865         if (resource->reformat_type == cache_resource->reformat_type &&
2866             resource->ft_type == cache_resource->ft_type &&
2867             resource->flags == cache_resource->flags &&
2868             resource->size == cache_resource->size &&
2869             !memcmp((const void *)resource->buf,
2870                     (const void *)cache_resource->buf,
2871                     resource->size))
2872                 return 0;
2873         return -1;
2874 }
2875
2876 /**
2877  * Allocate encap_decap resource.
2878  *
2879  * @param list
2880  *   Pointer to the hash list.
2881  * @param entry
2882  *   Pointer to exist resource entry object.
2883  * @param ctx_cb
2884  *   Pointer to new encap_decap resource.
2885  *
2886  * @return
2887  *   0 on matching, none-zero otherwise.
2888  */
2889 struct mlx5_hlist_entry *
2890 flow_dv_encap_decap_create_cb(struct mlx5_hlist *list,
2891                               uint64_t key __rte_unused,
2892                               void *cb_ctx)
2893 {
2894         struct mlx5_dev_ctx_shared *sh = list->ctx;
2895         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
2896         struct mlx5dv_dr_domain *domain;
2897         struct mlx5_flow_dv_encap_decap_resource *resource = ctx->data;
2898         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2899         uint32_t idx;
2900         int ret;
2901
2902         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2903                 domain = sh->fdb_domain;
2904         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2905                 domain = sh->rx_domain;
2906         else
2907                 domain = sh->tx_domain;
2908         /* Register new encap/decap resource. */
2909         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
2910                                        &idx);
2911         if (!cache_resource) {
2912                 rte_flow_error_set(ctx->error, ENOMEM,
2913                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2914                                    "cannot allocate resource memory");
2915                 return NULL;
2916         }
2917         *cache_resource = *resource;
2918         cache_resource->idx = idx;
2919         ret = mlx5_flow_os_create_flow_action_packet_reformat
2920                                         (sh->ctx, domain, cache_resource,
2921                                          &cache_resource->action);
2922         if (ret) {
2923                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);
2924                 rte_flow_error_set(ctx->error, ENOMEM,
2925                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2926                                    NULL, "cannot create action");
2927                 return NULL;
2928         }
2929
2930         return &cache_resource->entry;
2931 }
2932
2933 /**
2934  * Find existing encap/decap resource or create and register a new one.
2935  *
2936  * @param[in, out] dev
2937  *   Pointer to rte_eth_dev structure.
2938  * @param[in, out] resource
2939  *   Pointer to encap/decap resource.
2940  * @parm[in, out] dev_flow
2941  *   Pointer to the dev_flow.
2942  * @param[out] error
2943  *   pointer to error structure.
2944  *
2945  * @return
2946  *   0 on success otherwise -errno and errno is set.
2947  */
2948 static int
2949 flow_dv_encap_decap_resource_register
2950                         (struct rte_eth_dev *dev,
2951                          struct mlx5_flow_dv_encap_decap_resource *resource,
2952                          struct mlx5_flow *dev_flow,
2953                          struct rte_flow_error *error)
2954 {
2955         struct mlx5_priv *priv = dev->data->dev_private;
2956         struct mlx5_dev_ctx_shared *sh = priv->sh;
2957         struct mlx5_hlist_entry *entry;
2958         union {
2959                 struct {
2960                         uint32_t ft_type:8;
2961                         uint32_t refmt_type:8;
2962                         /*
2963                          * Header reformat actions can be shared between
2964                          * non-root tables. One bit to indicate non-root
2965                          * table or not.
2966                          */
2967                         uint32_t is_root:1;
2968                         uint32_t reserve:15;
2969                 };
2970                 uint32_t v32;
2971         } encap_decap_key = {
2972                 {
2973                         .ft_type = resource->ft_type,
2974                         .refmt_type = resource->reformat_type,
2975                         .is_root = !!dev_flow->dv.group,
2976                         .reserve = 0,
2977                 }
2978         };
2979         struct mlx5_flow_cb_ctx ctx = {
2980                 .error = error,
2981                 .data = resource,
2982         };
2983         uint64_t key64;
2984
2985         resource->flags = dev_flow->dv.group ? 0 : 1;
2986         key64 =  __rte_raw_cksum(&encap_decap_key.v32,
2987                                  sizeof(encap_decap_key.v32), 0);
2988         if (resource->reformat_type !=
2989             MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2 &&
2990             resource->size)
2991                 key64 = __rte_raw_cksum(resource->buf, resource->size, key64);
2992         entry = mlx5_hlist_register(sh->encaps_decaps, key64, &ctx);
2993         if (!entry)
2994                 return -rte_errno;
2995         resource = container_of(entry, typeof(*resource), entry);
2996         dev_flow->dv.encap_decap = resource;
2997         dev_flow->handle->dvh.rix_encap_decap = resource->idx;
2998         return 0;
2999 }
3000
3001 /**
3002  * Find existing table jump resource or create and register a new one.
3003  *
3004  * @param[in, out] dev
3005  *   Pointer to rte_eth_dev structure.
3006  * @param[in, out] tbl
3007  *   Pointer to flow table resource.
3008  * @parm[in, out] dev_flow
3009  *   Pointer to the dev_flow.
3010  * @param[out] error
3011  *   pointer to error structure.
3012  *
3013  * @return
3014  *   0 on success otherwise -errno and errno is set.
3015  */
3016 static int
3017 flow_dv_jump_tbl_resource_register
3018                         (struct rte_eth_dev *dev __rte_unused,
3019                          struct mlx5_flow_tbl_resource *tbl,
3020                          struct mlx5_flow *dev_flow,
3021                          struct rte_flow_error *error __rte_unused)
3022 {
3023         struct mlx5_flow_tbl_data_entry *tbl_data =
3024                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
3025
3026         MLX5_ASSERT(tbl);
3027         MLX5_ASSERT(tbl_data->jump.action);
3028         dev_flow->handle->rix_jump = tbl_data->idx;
3029         dev_flow->dv.jump = &tbl_data->jump;
3030         return 0;
3031 }
3032
3033 int
3034 flow_dv_port_id_match_cb(struct mlx5_cache_list *list __rte_unused,
3035                          struct mlx5_cache_entry *entry, void *cb_ctx)
3036 {
3037         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3038         struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3039         struct mlx5_flow_dv_port_id_action_resource *res =
3040                         container_of(entry, typeof(*res), entry);
3041
3042         return ref->port_id != res->port_id;
3043 }
3044
3045 struct mlx5_cache_entry *
3046 flow_dv_port_id_create_cb(struct mlx5_cache_list *list,
3047                           struct mlx5_cache_entry *entry __rte_unused,
3048                           void *cb_ctx)
3049 {
3050         struct mlx5_dev_ctx_shared *sh = list->ctx;
3051         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3052         struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3053         struct mlx5_flow_dv_port_id_action_resource *cache;
3054         uint32_t idx;
3055         int ret;
3056
3057         /* Register new port id action resource. */
3058         cache = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID], &idx);
3059         if (!cache) {
3060                 rte_flow_error_set(ctx->error, ENOMEM,
3061                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3062                                    "cannot allocate port_id action cache memory");
3063                 return NULL;
3064         }
3065         *cache = *ref;
3066         ret = mlx5_flow_os_create_flow_action_dest_port(sh->fdb_domain,
3067                                                         ref->port_id,
3068                                                         &cache->action);
3069         if (ret) {
3070                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], idx);
3071                 rte_flow_error_set(ctx->error, ENOMEM,
3072                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3073                                    "cannot create action");
3074                 return NULL;
3075         }
3076         return &cache->entry;
3077 }
3078
3079 /**
3080  * Find existing table port ID resource or create and register a new one.
3081  *
3082  * @param[in, out] dev
3083  *   Pointer to rte_eth_dev structure.
3084  * @param[in, out] resource
3085  *   Pointer to port ID action resource.
3086  * @parm[in, out] dev_flow
3087  *   Pointer to the dev_flow.
3088  * @param[out] error
3089  *   pointer to error structure.
3090  *
3091  * @return
3092  *   0 on success otherwise -errno and errno is set.
3093  */
3094 static int
3095 flow_dv_port_id_action_resource_register
3096                         (struct rte_eth_dev *dev,
3097                          struct mlx5_flow_dv_port_id_action_resource *resource,
3098                          struct mlx5_flow *dev_flow,
3099                          struct rte_flow_error *error)
3100 {
3101         struct mlx5_priv *priv = dev->data->dev_private;
3102         struct mlx5_cache_entry *entry;
3103         struct mlx5_flow_dv_port_id_action_resource *cache;
3104         struct mlx5_flow_cb_ctx ctx = {
3105                 .error = error,
3106                 .data = resource,
3107         };
3108
3109         entry = mlx5_cache_register(&priv->sh->port_id_action_list, &ctx);
3110         if (!entry)
3111                 return -rte_errno;
3112         cache = container_of(entry, typeof(*cache), entry);
3113         dev_flow->dv.port_id_action = cache;
3114         dev_flow->handle->rix_port_id_action = cache->idx;
3115         return 0;
3116 }
3117
3118 int
3119 flow_dv_push_vlan_match_cb(struct mlx5_cache_list *list __rte_unused,
3120                          struct mlx5_cache_entry *entry, void *cb_ctx)
3121 {
3122         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3123         struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3124         struct mlx5_flow_dv_push_vlan_action_resource *res =
3125                         container_of(entry, typeof(*res), entry);
3126
3127         return ref->vlan_tag != res->vlan_tag || ref->ft_type != res->ft_type;
3128 }
3129
3130 struct mlx5_cache_entry *
3131 flow_dv_push_vlan_create_cb(struct mlx5_cache_list *list,
3132                           struct mlx5_cache_entry *entry __rte_unused,
3133                           void *cb_ctx)
3134 {
3135         struct mlx5_dev_ctx_shared *sh = list->ctx;
3136         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3137         struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3138         struct mlx5_flow_dv_push_vlan_action_resource *cache;
3139         struct mlx5dv_dr_domain *domain;
3140         uint32_t idx;
3141         int ret;
3142
3143         /* Register new port id action resource. */
3144         cache = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN], &idx);
3145         if (!cache) {
3146                 rte_flow_error_set(ctx->error, ENOMEM,
3147                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3148                                    "cannot allocate push_vlan action cache memory");
3149                 return NULL;
3150         }
3151         *cache = *ref;
3152         if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3153                 domain = sh->fdb_domain;
3154         else if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3155                 domain = sh->rx_domain;
3156         else
3157                 domain = sh->tx_domain;
3158         ret = mlx5_flow_os_create_flow_action_push_vlan(domain, ref->vlan_tag,
3159                                                         &cache->action);
3160         if (ret) {
3161                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
3162                 rte_flow_error_set(ctx->error, ENOMEM,
3163                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3164                                    "cannot create push vlan action");
3165                 return NULL;
3166         }
3167         return &cache->entry;
3168 }
3169
3170 /**
3171  * Find existing push vlan resource or create and register a new one.
3172  *
3173  * @param [in, out] dev
3174  *   Pointer to rte_eth_dev structure.
3175  * @param[in, out] resource
3176  *   Pointer to port ID action resource.
3177  * @parm[in, out] dev_flow
3178  *   Pointer to the dev_flow.
3179  * @param[out] error
3180  *   pointer to error structure.
3181  *
3182  * @return
3183  *   0 on success otherwise -errno and errno is set.
3184  */
3185 static int
3186 flow_dv_push_vlan_action_resource_register
3187                        (struct rte_eth_dev *dev,
3188                         struct mlx5_flow_dv_push_vlan_action_resource *resource,
3189                         struct mlx5_flow *dev_flow,
3190                         struct rte_flow_error *error)
3191 {
3192         struct mlx5_priv *priv = dev->data->dev_private;
3193         struct mlx5_flow_dv_push_vlan_action_resource *cache;
3194         struct mlx5_cache_entry *entry;
3195         struct mlx5_flow_cb_ctx ctx = {
3196                 .error = error,
3197                 .data = resource,
3198         };
3199
3200         entry = mlx5_cache_register(&priv->sh->push_vlan_action_list, &ctx);
3201         if (!entry)
3202                 return -rte_errno;
3203         cache = container_of(entry, typeof(*cache), entry);
3204
3205         dev_flow->handle->dvh.rix_push_vlan = cache->idx;
3206         dev_flow->dv.push_vlan_res = cache;
3207         return 0;
3208 }
3209
3210 /**
3211  * Get the size of specific rte_flow_item_type hdr size
3212  *
3213  * @param[in] item_type
3214  *   Tested rte_flow_item_type.
3215  *
3216  * @return
3217  *   sizeof struct item_type, 0 if void or irrelevant.
3218  */
3219 static size_t
3220 flow_dv_get_item_hdr_len(const enum rte_flow_item_type item_type)
3221 {
3222         size_t retval;
3223
3224         switch (item_type) {
3225         case RTE_FLOW_ITEM_TYPE_ETH:
3226                 retval = sizeof(struct rte_ether_hdr);
3227                 break;
3228         case RTE_FLOW_ITEM_TYPE_VLAN:
3229                 retval = sizeof(struct rte_vlan_hdr);
3230                 break;
3231         case RTE_FLOW_ITEM_TYPE_IPV4:
3232                 retval = sizeof(struct rte_ipv4_hdr);
3233                 break;
3234         case RTE_FLOW_ITEM_TYPE_IPV6:
3235                 retval = sizeof(struct rte_ipv6_hdr);
3236                 break;
3237         case RTE_FLOW_ITEM_TYPE_UDP:
3238                 retval = sizeof(struct rte_udp_hdr);
3239                 break;
3240         case RTE_FLOW_ITEM_TYPE_TCP:
3241                 retval = sizeof(struct rte_tcp_hdr);
3242                 break;
3243         case RTE_FLOW_ITEM_TYPE_VXLAN:
3244         case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3245                 retval = sizeof(struct rte_vxlan_hdr);
3246                 break;
3247         case RTE_FLOW_ITEM_TYPE_GRE:
3248         case RTE_FLOW_ITEM_TYPE_NVGRE:
3249                 retval = sizeof(struct rte_gre_hdr);
3250                 break;
3251         case RTE_FLOW_ITEM_TYPE_MPLS:
3252                 retval = sizeof(struct rte_mpls_hdr);
3253                 break;
3254         case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
3255         default:
3256                 retval = 0;
3257                 break;
3258         }
3259         return retval;
3260 }
3261
3262 #define MLX5_ENCAP_IPV4_VERSION         0x40
3263 #define MLX5_ENCAP_IPV4_IHL_MIN         0x05
3264 #define MLX5_ENCAP_IPV4_TTL_DEF         0x40
3265 #define MLX5_ENCAP_IPV6_VTC_FLOW        0x60000000
3266 #define MLX5_ENCAP_IPV6_HOP_LIMIT       0xff
3267 #define MLX5_ENCAP_VXLAN_FLAGS          0x08000000
3268 #define MLX5_ENCAP_VXLAN_GPE_FLAGS      0x04
3269
3270 /**
3271  * Convert the encap action data from list of rte_flow_item to raw buffer
3272  *
3273  * @param[in] items
3274  *   Pointer to rte_flow_item objects list.
3275  * @param[out] buf
3276  *   Pointer to the output buffer.
3277  * @param[out] size
3278  *   Pointer to the output buffer size.
3279  * @param[out] error
3280  *   Pointer to the error structure.
3281  *
3282  * @return
3283  *   0 on success, a negative errno value otherwise and rte_errno is set.
3284  */
3285 static int
3286 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
3287                            size_t *size, struct rte_flow_error *error)
3288 {
3289         struct rte_ether_hdr *eth = NULL;
3290         struct rte_vlan_hdr *vlan = NULL;
3291         struct rte_ipv4_hdr *ipv4 = NULL;
3292         struct rte_ipv6_hdr *ipv6 = NULL;
3293         struct rte_udp_hdr *udp = NULL;
3294         struct rte_vxlan_hdr *vxlan = NULL;
3295         struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
3296         struct rte_gre_hdr *gre = NULL;
3297         size_t len;
3298         size_t temp_size = 0;
3299
3300         if (!items)
3301                 return rte_flow_error_set(error, EINVAL,
3302                                           RTE_FLOW_ERROR_TYPE_ACTION,
3303                                           NULL, "invalid empty data");
3304         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
3305                 len = flow_dv_get_item_hdr_len(items->type);
3306                 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
3307                         return rte_flow_error_set(error, EINVAL,
3308                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3309                                                   (void *)items->type,
3310                                                   "items total size is too big"
3311                                                   " for encap action");
3312                 rte_memcpy((void *)&buf[temp_size], items->spec, len);
3313                 switch (items->type) {
3314                 case RTE_FLOW_ITEM_TYPE_ETH:
3315                         eth = (struct rte_ether_hdr *)&buf[temp_size];
3316                         break;
3317                 case RTE_FLOW_ITEM_TYPE_VLAN:
3318                         vlan = (struct rte_vlan_hdr *)&buf[temp_size];
3319                         if (!eth)
3320                                 return rte_flow_error_set(error, EINVAL,
3321                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3322                                                 (void *)items->type,
3323                                                 "eth header not found");
3324                         if (!eth->ether_type)
3325                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
3326                         break;
3327                 case RTE_FLOW_ITEM_TYPE_IPV4:
3328                         ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
3329                         if (!vlan && !eth)
3330                                 return rte_flow_error_set(error, EINVAL,
3331                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3332                                                 (void *)items->type,
3333                                                 "neither eth nor vlan"
3334                                                 " header found");
3335                         if (vlan && !vlan->eth_proto)
3336                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3337                         else if (eth && !eth->ether_type)
3338                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3339                         if (!ipv4->version_ihl)
3340                                 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
3341                                                     MLX5_ENCAP_IPV4_IHL_MIN;
3342                         if (!ipv4->time_to_live)
3343                                 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
3344                         break;
3345                 case RTE_FLOW_ITEM_TYPE_IPV6:
3346                         ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
3347                         if (!vlan && !eth)
3348                                 return rte_flow_error_set(error, EINVAL,
3349                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3350                                                 (void *)items->type,
3351                                                 "neither eth nor vlan"
3352                                                 " header found");
3353                         if (vlan && !vlan->eth_proto)
3354                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3355                         else if (eth && !eth->ether_type)
3356                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3357                         if (!ipv6->vtc_flow)
3358                                 ipv6->vtc_flow =
3359                                         RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
3360                         if (!ipv6->hop_limits)
3361                                 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
3362                         break;
3363                 case RTE_FLOW_ITEM_TYPE_UDP:
3364                         udp = (struct rte_udp_hdr *)&buf[temp_size];
3365                         if (!ipv4 && !ipv6)
3366                                 return rte_flow_error_set(error, EINVAL,
3367                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3368                                                 (void *)items->type,
3369                                                 "ip header not found");
3370                         if (ipv4 && !ipv4->next_proto_id)
3371                                 ipv4->next_proto_id = IPPROTO_UDP;
3372                         else if (ipv6 && !ipv6->proto)
3373                                 ipv6->proto = IPPROTO_UDP;
3374                         break;
3375                 case RTE_FLOW_ITEM_TYPE_VXLAN:
3376                         vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
3377                         if (!udp)
3378                                 return rte_flow_error_set(error, EINVAL,
3379                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3380                                                 (void *)items->type,
3381                                                 "udp header not found");
3382                         if (!udp->dst_port)
3383                                 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
3384                         if (!vxlan->vx_flags)
3385                                 vxlan->vx_flags =
3386                                         RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
3387                         break;
3388                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3389                         vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
3390                         if (!udp)
3391                                 return rte_flow_error_set(error, EINVAL,
3392                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3393                                                 (void *)items->type,
3394                                                 "udp header not found");
3395                         if (!vxlan_gpe->proto)
3396                                 return rte_flow_error_set(error, EINVAL,
3397                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3398                                                 (void *)items->type,
3399                                                 "next protocol not found");
3400                         if (!udp->dst_port)
3401                                 udp->dst_port =
3402                                         RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
3403                         if (!vxlan_gpe->vx_flags)
3404                                 vxlan_gpe->vx_flags =
3405                                                 MLX5_ENCAP_VXLAN_GPE_FLAGS;
3406                         break;
3407                 case RTE_FLOW_ITEM_TYPE_GRE:
3408                 case RTE_FLOW_ITEM_TYPE_NVGRE:
3409                         gre = (struct rte_gre_hdr *)&buf[temp_size];
3410                         if (!gre->proto)
3411                                 return rte_flow_error_set(error, EINVAL,
3412                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3413                                                 (void *)items->type,
3414                                                 "next protocol not found");
3415                         if (!ipv4 && !ipv6)
3416                                 return rte_flow_error_set(error, EINVAL,
3417                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3418                                                 (void *)items->type,
3419                                                 "ip header not found");
3420                         if (ipv4 && !ipv4->next_proto_id)
3421                                 ipv4->next_proto_id = IPPROTO_GRE;
3422                         else if (ipv6 && !ipv6->proto)
3423                                 ipv6->proto = IPPROTO_GRE;
3424                         break;
3425                 case RTE_FLOW_ITEM_TYPE_VOID:
3426                         break;
3427                 default:
3428                         return rte_flow_error_set(error, EINVAL,
3429                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3430                                                   (void *)items->type,
3431                                                   "unsupported item type");
3432                         break;
3433                 }
3434                 temp_size += len;
3435         }
3436         *size = temp_size;
3437         return 0;
3438 }
3439
3440 static int
3441 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
3442 {
3443         struct rte_ether_hdr *eth = NULL;
3444         struct rte_vlan_hdr *vlan = NULL;
3445         struct rte_ipv6_hdr *ipv6 = NULL;
3446         struct rte_udp_hdr *udp = NULL;
3447         char *next_hdr;
3448         uint16_t proto;
3449
3450         eth = (struct rte_ether_hdr *)data;
3451         next_hdr = (char *)(eth + 1);
3452         proto = RTE_BE16(eth->ether_type);
3453
3454         /* VLAN skipping */
3455         while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
3456                 vlan = (struct rte_vlan_hdr *)next_hdr;
3457                 proto = RTE_BE16(vlan->eth_proto);
3458                 next_hdr += sizeof(struct rte_vlan_hdr);
3459         }
3460
3461         /* HW calculates IPv4 csum. no need to proceed */
3462         if (proto == RTE_ETHER_TYPE_IPV4)
3463                 return 0;
3464
3465         /* non IPv4/IPv6 header. not supported */
3466         if (proto != RTE_ETHER_TYPE_IPV6) {
3467                 return rte_flow_error_set(error, ENOTSUP,
3468                                           RTE_FLOW_ERROR_TYPE_ACTION,
3469                                           NULL, "Cannot offload non IPv4/IPv6");
3470         }
3471
3472         ipv6 = (struct rte_ipv6_hdr *)next_hdr;
3473
3474         /* ignore non UDP */
3475         if (ipv6->proto != IPPROTO_UDP)
3476                 return 0;
3477
3478         udp = (struct rte_udp_hdr *)(ipv6 + 1);
3479         udp->dgram_cksum = 0;
3480
3481         return 0;
3482 }
3483
3484 /**
3485  * Convert L2 encap action to DV specification.
3486  *
3487  * @param[in] dev
3488  *   Pointer to rte_eth_dev structure.
3489  * @param[in] action
3490  *   Pointer to action structure.
3491  * @param[in, out] dev_flow
3492  *   Pointer to the mlx5_flow.
3493  * @param[in] transfer
3494  *   Mark if the flow is E-Switch flow.
3495  * @param[out] error
3496  *   Pointer to the error structure.
3497  *
3498  * @return
3499  *   0 on success, a negative errno value otherwise and rte_errno is set.
3500  */
3501 static int
3502 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
3503                                const struct rte_flow_action *action,
3504                                struct mlx5_flow *dev_flow,
3505                                uint8_t transfer,
3506                                struct rte_flow_error *error)
3507 {
3508         const struct rte_flow_item *encap_data;
3509         const struct rte_flow_action_raw_encap *raw_encap_data;
3510         struct mlx5_flow_dv_encap_decap_resource res = {
3511                 .reformat_type =
3512                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
3513                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3514                                       MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
3515         };
3516
3517         if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
3518                 raw_encap_data =
3519                         (const struct rte_flow_action_raw_encap *)action->conf;
3520                 res.size = raw_encap_data->size;
3521                 memcpy(res.buf, raw_encap_data->data, res.size);
3522         } else {
3523                 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
3524                         encap_data =
3525                                 ((const struct rte_flow_action_vxlan_encap *)
3526                                                 action->conf)->definition;
3527                 else
3528                         encap_data =
3529                                 ((const struct rte_flow_action_nvgre_encap *)
3530                                                 action->conf)->definition;
3531                 if (flow_dv_convert_encap_data(encap_data, res.buf,
3532                                                &res.size, error))
3533                         return -rte_errno;
3534         }
3535         if (flow_dv_zero_encap_udp_csum(res.buf, error))
3536                 return -rte_errno;
3537         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3538                 return rte_flow_error_set(error, EINVAL,
3539                                           RTE_FLOW_ERROR_TYPE_ACTION,
3540                                           NULL, "can't create L2 encap action");
3541         return 0;
3542 }
3543
3544 /**
3545  * Convert L2 decap action to DV specification.
3546  *
3547  * @param[in] dev
3548  *   Pointer to rte_eth_dev structure.
3549  * @param[in, out] dev_flow
3550  *   Pointer to the mlx5_flow.
3551  * @param[in] transfer
3552  *   Mark if the flow is E-Switch flow.
3553  * @param[out] error
3554  *   Pointer to the error structure.
3555  *
3556  * @return
3557  *   0 on success, a negative errno value otherwise and rte_errno is set.
3558  */
3559 static int
3560 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
3561                                struct mlx5_flow *dev_flow,
3562                                uint8_t transfer,
3563                                struct rte_flow_error *error)
3564 {
3565         struct mlx5_flow_dv_encap_decap_resource res = {
3566                 .size = 0,
3567                 .reformat_type =
3568                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
3569                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3570                                       MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
3571         };
3572
3573         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3574                 return rte_flow_error_set(error, EINVAL,
3575                                           RTE_FLOW_ERROR_TYPE_ACTION,
3576                                           NULL, "can't create L2 decap action");
3577         return 0;
3578 }
3579
3580 /**
3581  * Convert raw decap/encap (L3 tunnel) action to DV specification.
3582  *
3583  * @param[in] dev
3584  *   Pointer to rte_eth_dev structure.
3585  * @param[in] action
3586  *   Pointer to action structure.
3587  * @param[in, out] dev_flow
3588  *   Pointer to the mlx5_flow.
3589  * @param[in] attr
3590  *   Pointer to the flow attributes.
3591  * @param[out] error
3592  *   Pointer to the error structure.
3593  *
3594  * @return
3595  *   0 on success, a negative errno value otherwise and rte_errno is set.
3596  */
3597 static int
3598 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
3599                                 const struct rte_flow_action *action,
3600                                 struct mlx5_flow *dev_flow,
3601                                 const struct rte_flow_attr *attr,
3602                                 struct rte_flow_error *error)
3603 {
3604         const struct rte_flow_action_raw_encap *encap_data;
3605         struct mlx5_flow_dv_encap_decap_resource res;
3606
3607         memset(&res, 0, sizeof(res));
3608         encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
3609         res.size = encap_data->size;
3610         memcpy(res.buf, encap_data->data, res.size);
3611         res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
3612                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
3613                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
3614         if (attr->transfer)
3615                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3616         else
3617                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3618                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3619         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3620                 return rte_flow_error_set(error, EINVAL,
3621                                           RTE_FLOW_ERROR_TYPE_ACTION,
3622                                           NULL, "can't create encap action");
3623         return 0;
3624 }
3625
3626 /**
3627  * Create action push VLAN.
3628  *
3629  * @param[in] dev
3630  *   Pointer to rte_eth_dev structure.
3631  * @param[in] attr
3632  *   Pointer to the flow attributes.
3633  * @param[in] vlan
3634  *   Pointer to the vlan to push to the Ethernet header.
3635  * @param[in, out] dev_flow
3636  *   Pointer to the mlx5_flow.
3637  * @param[out] error
3638  *   Pointer to the error structure.
3639  *
3640  * @return
3641  *   0 on success, a negative errno value otherwise and rte_errno is set.
3642  */
3643 static int
3644 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
3645                                 const struct rte_flow_attr *attr,
3646                                 const struct rte_vlan_hdr *vlan,
3647                                 struct mlx5_flow *dev_flow,
3648                                 struct rte_flow_error *error)
3649 {
3650         struct mlx5_flow_dv_push_vlan_action_resource res;
3651
3652         memset(&res, 0, sizeof(res));
3653         res.vlan_tag =
3654                 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
3655                                  vlan->vlan_tci);
3656         if (attr->transfer)
3657                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3658         else
3659                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3660                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3661         return flow_dv_push_vlan_action_resource_register
3662                                             (dev, &res, dev_flow, error);
3663 }
3664
3665 static int fdb_mirror;
3666
3667 /**
3668  * Validate the modify-header actions.
3669  *
3670  * @param[in] action_flags
3671  *   Holds the actions detected until now.
3672  * @param[in] action
3673  *   Pointer to the modify action.
3674  * @param[out] error
3675  *   Pointer to error structure.
3676  *
3677  * @return
3678  *   0 on success, a negative errno value otherwise and rte_errno is set.
3679  */
3680 static int
3681 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
3682                                    const struct rte_flow_action *action,
3683                                    struct rte_flow_error *error)
3684 {
3685         if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
3686                 return rte_flow_error_set(error, EINVAL,
3687                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3688                                           NULL, "action configuration not set");
3689         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3690                 return rte_flow_error_set(error, EINVAL,
3691                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3692                                           "can't have encap action before"
3693                                           " modify action");
3694         if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) && fdb_mirror)
3695                 return rte_flow_error_set(error, EINVAL,
3696                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3697                                           "can't support sample action before"
3698                                           " modify action for E-Switch"
3699                                           " mirroring");
3700         return 0;
3701 }
3702
3703 /**
3704  * Validate the modify-header MAC address actions.
3705  *
3706  * @param[in] action_flags
3707  *   Holds the actions detected until now.
3708  * @param[in] action
3709  *   Pointer to the modify action.
3710  * @param[in] item_flags
3711  *   Holds the items detected.
3712  * @param[out] error
3713  *   Pointer to error structure.
3714  *
3715  * @return
3716  *   0 on success, a negative errno value otherwise and rte_errno is set.
3717  */
3718 static int
3719 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
3720                                    const struct rte_flow_action *action,
3721                                    const uint64_t item_flags,
3722                                    struct rte_flow_error *error)
3723 {
3724         int ret = 0;
3725
3726         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3727         if (!ret) {
3728                 if (!(item_flags & MLX5_FLOW_LAYER_L2))
3729                         return rte_flow_error_set(error, EINVAL,
3730                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3731                                                   NULL,
3732                                                   "no L2 item in pattern");
3733         }
3734         return ret;
3735 }
3736
3737 /**
3738  * Validate the modify-header IPv4 address actions.
3739  *
3740  * @param[in] action_flags
3741  *   Holds the actions detected until now.
3742  * @param[in] action
3743  *   Pointer to the modify action.
3744  * @param[in] item_flags
3745  *   Holds the items detected.
3746  * @param[out] error
3747  *   Pointer to error structure.
3748  *
3749  * @return
3750  *   0 on success, a negative errno value otherwise and rte_errno is set.
3751  */
3752 static int
3753 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
3754                                     const struct rte_flow_action *action,
3755                                     const uint64_t item_flags,
3756                                     struct rte_flow_error *error)
3757 {
3758         int ret = 0;
3759         uint64_t layer;
3760
3761         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3762         if (!ret) {
3763                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3764                                  MLX5_FLOW_LAYER_INNER_L3_IPV4 :
3765                                  MLX5_FLOW_LAYER_OUTER_L3_IPV4;
3766                 if (!(item_flags & layer))
3767                         return rte_flow_error_set(error, EINVAL,
3768                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3769                                                   NULL,
3770                                                   "no ipv4 item in pattern");
3771         }
3772         return ret;
3773 }
3774
3775 /**
3776  * Validate the modify-header IPv6 address actions.
3777  *
3778  * @param[in] action_flags
3779  *   Holds the actions detected until now.
3780  * @param[in] action
3781  *   Pointer to the modify action.
3782  * @param[in] item_flags
3783  *   Holds the items detected.
3784  * @param[out] error
3785  *   Pointer to error structure.
3786  *
3787  * @return
3788  *   0 on success, a negative errno value otherwise and rte_errno is set.
3789  */
3790 static int
3791 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
3792                                     const struct rte_flow_action *action,
3793                                     const uint64_t item_flags,
3794                                     struct rte_flow_error *error)
3795 {
3796         int ret = 0;
3797         uint64_t layer;
3798
3799         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3800         if (!ret) {
3801                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3802                                  MLX5_FLOW_LAYER_INNER_L3_IPV6 :
3803                                  MLX5_FLOW_LAYER_OUTER_L3_IPV6;
3804                 if (!(item_flags & layer))
3805                         return rte_flow_error_set(error, EINVAL,
3806                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3807                                                   NULL,
3808                                                   "no ipv6 item in pattern");
3809         }
3810         return ret;
3811 }
3812
3813 /**
3814  * Validate the modify-header TP actions.
3815  *
3816  * @param[in] action_flags
3817  *   Holds the actions detected until now.
3818  * @param[in] action
3819  *   Pointer to the modify action.
3820  * @param[in] item_flags
3821  *   Holds the items detected.
3822  * @param[out] error
3823  *   Pointer to error structure.
3824  *
3825  * @return
3826  *   0 on success, a negative errno value otherwise and rte_errno is set.
3827  */
3828 static int
3829 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
3830                                   const struct rte_flow_action *action,
3831                                   const uint64_t item_flags,
3832                                   struct rte_flow_error *error)
3833 {
3834         int ret = 0;
3835         uint64_t layer;
3836
3837         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3838         if (!ret) {
3839                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3840                                  MLX5_FLOW_LAYER_INNER_L4 :
3841                                  MLX5_FLOW_LAYER_OUTER_L4;
3842                 if (!(item_flags & layer))
3843                         return rte_flow_error_set(error, EINVAL,
3844                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3845                                                   NULL, "no transport layer "
3846                                                   "in pattern");
3847         }
3848         return ret;
3849 }
3850
3851 /**
3852  * Validate the modify-header actions of increment/decrement
3853  * TCP Sequence-number.
3854  *
3855  * @param[in] action_flags
3856  *   Holds the actions detected until now.
3857  * @param[in] action
3858  *   Pointer to the modify action.
3859  * @param[in] item_flags
3860  *   Holds the items detected.
3861  * @param[out] error
3862  *   Pointer to error structure.
3863  *
3864  * @return
3865  *   0 on success, a negative errno value otherwise and rte_errno is set.
3866  */
3867 static int
3868 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
3869                                        const struct rte_flow_action *action,
3870                                        const uint64_t item_flags,
3871                                        struct rte_flow_error *error)
3872 {
3873         int ret = 0;
3874         uint64_t layer;
3875
3876         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3877         if (!ret) {
3878                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3879                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
3880                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
3881                 if (!(item_flags & layer))
3882                         return rte_flow_error_set(error, EINVAL,
3883                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3884                                                   NULL, "no TCP item in"
3885                                                   " pattern");
3886                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
3887                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
3888                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
3889                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
3890                         return rte_flow_error_set(error, EINVAL,
3891                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3892                                                   NULL,
3893                                                   "cannot decrease and increase"
3894                                                   " TCP sequence number"
3895                                                   " at the same time");
3896         }
3897         return ret;
3898 }
3899
3900 /**
3901  * Validate the modify-header actions of increment/decrement
3902  * TCP Acknowledgment number.
3903  *
3904  * @param[in] action_flags
3905  *   Holds the actions detected until now.
3906  * @param[in] action
3907  *   Pointer to the modify action.
3908  * @param[in] item_flags
3909  *   Holds the items detected.
3910  * @param[out] error
3911  *   Pointer to error structure.
3912  *
3913  * @return
3914  *   0 on success, a negative errno value otherwise and rte_errno is set.
3915  */
3916 static int
3917 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
3918                                        const struct rte_flow_action *action,
3919                                        const uint64_t item_flags,
3920                                        struct rte_flow_error *error)
3921 {
3922         int ret = 0;
3923         uint64_t layer;
3924
3925         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3926         if (!ret) {
3927                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3928                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
3929                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
3930                 if (!(item_flags & layer))
3931                         return rte_flow_error_set(error, EINVAL,
3932                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3933                                                   NULL, "no TCP item in"
3934                                                   " pattern");
3935                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
3936                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
3937                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
3938                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
3939                         return rte_flow_error_set(error, EINVAL,
3940                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3941                                                   NULL,
3942                                                   "cannot decrease and increase"
3943                                                   " TCP acknowledgment number"
3944                                                   " at the same time");
3945         }
3946         return ret;
3947 }
3948
3949 /**
3950  * Validate the modify-header TTL actions.
3951  *
3952  * @param[in] action_flags
3953  *   Holds the actions detected until now.
3954  * @param[in] action
3955  *   Pointer to the modify action.
3956  * @param[in] item_flags
3957  *   Holds the items detected.
3958  * @param[out] error
3959  *   Pointer to error structure.
3960  *
3961  * @return
3962  *   0 on success, a negative errno value otherwise and rte_errno is set.
3963  */
3964 static int
3965 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
3966                                    const struct rte_flow_action *action,
3967                                    const uint64_t item_flags,
3968                                    struct rte_flow_error *error)
3969 {
3970         int ret = 0;
3971         uint64_t layer;
3972
3973         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3974         if (!ret) {
3975                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3976                                  MLX5_FLOW_LAYER_INNER_L3 :
3977                                  MLX5_FLOW_LAYER_OUTER_L3;
3978                 if (!(item_flags & layer))
3979                         return rte_flow_error_set(error, EINVAL,
3980                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3981                                                   NULL,
3982                                                   "no IP protocol in pattern");
3983         }
3984         return ret;
3985 }
3986
3987 /**
3988  * Validate jump action.
3989  *
3990  * @param[in] action
3991  *   Pointer to the jump action.
3992  * @param[in] action_flags
3993  *   Holds the actions detected until now.
3994  * @param[in] attributes
3995  *   Pointer to flow attributes
3996  * @param[in] external
3997  *   Action belongs to flow rule created by request external to PMD.
3998  * @param[out] error
3999  *   Pointer to error structure.
4000  *
4001  * @return
4002  *   0 on success, a negative errno value otherwise and rte_errno is set.
4003  */
4004 static int
4005 flow_dv_validate_action_jump(struct rte_eth_dev *dev,
4006                              const struct mlx5_flow_tunnel *tunnel,
4007                              const struct rte_flow_action *action,
4008                              uint64_t action_flags,
4009                              const struct rte_flow_attr *attributes,
4010                              bool external, struct rte_flow_error *error)
4011 {
4012         uint32_t target_group, table;
4013         int ret = 0;
4014         struct flow_grp_info grp_info = {
4015                 .external = !!external,
4016                 .transfer = !!attributes->transfer,
4017                 .fdb_def_rule = 1,
4018                 .std_tbl_fix = 0
4019         };
4020         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
4021                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4022                 return rte_flow_error_set(error, EINVAL,
4023                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4024                                           "can't have 2 fate actions in"
4025                                           " same flow");
4026         if (action_flags & MLX5_FLOW_ACTION_METER)
4027                 return rte_flow_error_set(error, ENOTSUP,
4028                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4029                                           "jump with meter not support");
4030         if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) && fdb_mirror)
4031                 return rte_flow_error_set(error, EINVAL,
4032                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4033                                           "E-Switch mirroring can't support"
4034                                           " Sample action and jump action in"
4035                                           " same flow now");
4036         if (!action->conf)
4037                 return rte_flow_error_set(error, EINVAL,
4038                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4039                                           NULL, "action configuration not set");
4040         target_group =
4041                 ((const struct rte_flow_action_jump *)action->conf)->group;
4042         ret = mlx5_flow_group_to_table(dev, tunnel, target_group, &table,
4043                                        &grp_info, error);
4044         if (ret)
4045                 return ret;
4046         if (attributes->group == target_group &&
4047             !(action_flags & (MLX5_FLOW_ACTION_TUNNEL_SET |
4048                               MLX5_FLOW_ACTION_TUNNEL_MATCH)))
4049                 return rte_flow_error_set(error, EINVAL,
4050                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4051                                           "target group must be other than"
4052                                           " the current flow group");
4053         return 0;
4054 }
4055
4056 /*
4057  * Validate the port_id action.
4058  *
4059  * @param[in] dev
4060  *   Pointer to rte_eth_dev structure.
4061  * @param[in] action_flags
4062  *   Bit-fields that holds the actions detected until now.
4063  * @param[in] action
4064  *   Port_id RTE action structure.
4065  * @param[in] attr
4066  *   Attributes of flow that includes this action.
4067  * @param[out] error
4068  *   Pointer to error structure.
4069  *
4070  * @return
4071  *   0 on success, a negative errno value otherwise and rte_errno is set.
4072  */
4073 static int
4074 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
4075                                 uint64_t action_flags,
4076                                 const struct rte_flow_action *action,
4077                                 const struct rte_flow_attr *attr,
4078                                 struct rte_flow_error *error)
4079 {
4080         const struct rte_flow_action_port_id *port_id;
4081         struct mlx5_priv *act_priv;
4082         struct mlx5_priv *dev_priv;
4083         uint16_t port;
4084
4085         if (!attr->transfer)
4086                 return rte_flow_error_set(error, ENOTSUP,
4087                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4088                                           NULL,
4089                                           "port id action is valid in transfer"
4090                                           " mode only");
4091         if (!action || !action->conf)
4092                 return rte_flow_error_set(error, ENOTSUP,
4093                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4094                                           NULL,
4095                                           "port id action parameters must be"
4096                                           " specified");
4097         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
4098                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4099                 return rte_flow_error_set(error, EINVAL,
4100                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4101                                           "can have only one fate actions in"
4102                                           " a flow");
4103         dev_priv = mlx5_dev_to_eswitch_info(dev);
4104         if (!dev_priv)
4105                 return rte_flow_error_set(error, rte_errno,
4106                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4107                                           NULL,
4108                                           "failed to obtain E-Switch info");
4109         port_id = action->conf;
4110         port = port_id->original ? dev->data->port_id : port_id->id;
4111         act_priv = mlx5_port_to_eswitch_info(port, false);
4112         if (!act_priv)
4113                 return rte_flow_error_set
4114                                 (error, rte_errno,
4115                                  RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
4116                                  "failed to obtain E-Switch port id for port");
4117         if (act_priv->domain_id != dev_priv->domain_id)
4118                 return rte_flow_error_set
4119                                 (error, EINVAL,
4120                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4121                                  "port does not belong to"
4122                                  " E-Switch being configured");
4123         return 0;
4124 }
4125
4126 /**
4127  * Get the maximum number of modify header actions.
4128  *
4129  * @param dev
4130  *   Pointer to rte_eth_dev structure.
4131  * @param flags
4132  *   Flags bits to check if root level.
4133  *
4134  * @return
4135  *   Max number of modify header actions device can support.
4136  */
4137 static inline unsigned int
4138 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev __rte_unused,
4139                               uint64_t flags)
4140 {
4141         /*
4142          * There's no way to directly query the max capacity from FW.
4143          * The maximal value on root table should be assumed to be supported.
4144          */
4145         if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
4146                 return MLX5_MAX_MODIFY_NUM;
4147         else
4148                 return MLX5_ROOT_TBL_MODIFY_NUM;
4149 }
4150
4151 /**
4152  * Validate the meter action.
4153  *
4154  * @param[in] dev
4155  *   Pointer to rte_eth_dev structure.
4156  * @param[in] action_flags
4157  *   Bit-fields that holds the actions detected until now.
4158  * @param[in] action
4159  *   Pointer to the meter action.
4160  * @param[in] attr
4161  *   Attributes of flow that includes this action.
4162  * @param[out] error
4163  *   Pointer to error structure.
4164  *
4165  * @return
4166  *   0 on success, a negative errno value otherwise and rte_ernno is set.
4167  */
4168 static int
4169 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
4170                                 uint64_t action_flags,
4171                                 const struct rte_flow_action *action,
4172                                 const struct rte_flow_attr *attr,
4173                                 struct rte_flow_error *error)
4174 {
4175         struct mlx5_priv *priv = dev->data->dev_private;
4176         const struct rte_flow_action_meter *am = action->conf;
4177         struct mlx5_flow_meter *fm;
4178
4179         if (!am)
4180                 return rte_flow_error_set(error, EINVAL,
4181                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4182                                           "meter action conf is NULL");
4183
4184         if (action_flags & MLX5_FLOW_ACTION_METER)
4185                 return rte_flow_error_set(error, ENOTSUP,
4186                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4187                                           "meter chaining not support");
4188         if (action_flags & MLX5_FLOW_ACTION_JUMP)
4189                 return rte_flow_error_set(error, ENOTSUP,
4190                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4191                                           "meter with jump not support");
4192         if (!priv->mtr_en)
4193                 return rte_flow_error_set(error, ENOTSUP,
4194                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4195                                           NULL,
4196                                           "meter action not supported");
4197         fm = mlx5_flow_meter_find(priv, am->mtr_id);
4198         if (!fm)
4199                 return rte_flow_error_set(error, EINVAL,
4200                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4201                                           "Meter not found");
4202         if (fm->ref_cnt && (!(fm->transfer == attr->transfer ||
4203               (!fm->ingress && !attr->ingress && attr->egress) ||
4204               (!fm->egress && !attr->egress && attr->ingress))))
4205                 return rte_flow_error_set(error, EINVAL,
4206                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4207                                           "Flow attributes are either invalid "
4208                                           "or have a conflict with current "
4209                                           "meter attributes");
4210         return 0;
4211 }
4212
4213 /**
4214  * Validate the age action.
4215  *
4216  * @param[in] action_flags
4217  *   Holds the actions detected until now.
4218  * @param[in] action
4219  *   Pointer to the age action.
4220  * @param[in] dev
4221  *   Pointer to the Ethernet device structure.
4222  * @param[out] error
4223  *   Pointer to error structure.
4224  *
4225  * @return
4226  *   0 on success, a negative errno value otherwise and rte_errno is set.
4227  */
4228 static int
4229 flow_dv_validate_action_age(uint64_t action_flags,
4230                             const struct rte_flow_action *action,
4231                             struct rte_eth_dev *dev,
4232                             struct rte_flow_error *error)
4233 {
4234         struct mlx5_priv *priv = dev->data->dev_private;
4235         const struct rte_flow_action_age *age = action->conf;
4236
4237         if (!priv->config.devx || (priv->sh->cmng.counter_fallback &&
4238             !priv->sh->aso_age_mng))
4239                 return rte_flow_error_set(error, ENOTSUP,
4240                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4241                                           NULL,
4242                                           "age action not supported");
4243         if (!(action->conf))
4244                 return rte_flow_error_set(error, EINVAL,
4245                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4246                                           "configuration cannot be null");
4247         if (!(age->timeout))
4248                 return rte_flow_error_set(error, EINVAL,
4249                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4250                                           "invalid timeout value 0");
4251         if (action_flags & MLX5_FLOW_ACTION_AGE)
4252                 return rte_flow_error_set(error, EINVAL,
4253                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4254                                           "duplicate age actions set");
4255         return 0;
4256 }
4257
4258 /**
4259  * Validate the modify-header IPv4 DSCP actions.
4260  *
4261  * @param[in] action_flags
4262  *   Holds the actions detected until now.
4263  * @param[in] action
4264  *   Pointer to the modify action.
4265  * @param[in] item_flags
4266  *   Holds the items detected.
4267  * @param[out] error
4268  *   Pointer to error structure.
4269  *
4270  * @return
4271  *   0 on success, a negative errno value otherwise and rte_errno is set.
4272  */
4273 static int
4274 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
4275                                          const struct rte_flow_action *action,
4276                                          const uint64_t item_flags,
4277                                          struct rte_flow_error *error)
4278 {
4279         int ret = 0;
4280
4281         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4282         if (!ret) {
4283                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
4284                         return rte_flow_error_set(error, EINVAL,
4285                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4286                                                   NULL,
4287                                                   "no ipv4 item in pattern");
4288         }
4289         return ret;
4290 }
4291
4292 /**
4293  * Validate the modify-header IPv6 DSCP actions.
4294  *
4295  * @param[in] action_flags
4296  *   Holds the actions detected until now.
4297  * @param[in] action
4298  *   Pointer to the modify action.
4299  * @param[in] item_flags
4300  *   Holds the items detected.
4301  * @param[out] error
4302  *   Pointer to error structure.
4303  *
4304  * @return
4305  *   0 on success, a negative errno value otherwise and rte_errno is set.
4306  */
4307 static int
4308 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
4309                                          const struct rte_flow_action *action,
4310                                          const uint64_t item_flags,
4311                                          struct rte_flow_error *error)
4312 {
4313         int ret = 0;
4314
4315         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4316         if (!ret) {
4317                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
4318                         return rte_flow_error_set(error, EINVAL,
4319                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4320                                                   NULL,
4321                                                   "no ipv6 item in pattern");
4322         }
4323         return ret;
4324 }
4325
4326 /**
4327  * Match modify-header resource.
4328  *
4329  * @param list
4330  *   Pointer to the hash list.
4331  * @param entry
4332  *   Pointer to exist resource entry object.
4333  * @param key
4334  *   Key of the new entry.
4335  * @param ctx
4336  *   Pointer to new modify-header resource.
4337  *
4338  * @return
4339  *   0 on matching, non-zero otherwise.
4340  */
4341 int
4342 flow_dv_modify_match_cb(struct mlx5_hlist *list __rte_unused,
4343                         struct mlx5_hlist_entry *entry,
4344                         uint64_t key __rte_unused, void *cb_ctx)
4345 {
4346         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
4347         struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
4348         struct mlx5_flow_dv_modify_hdr_resource *resource =
4349                         container_of(entry, typeof(*resource), entry);
4350         uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
4351
4352         key_len += ref->actions_num * sizeof(ref->actions[0]);
4353         return ref->actions_num != resource->actions_num ||
4354                memcmp(&ref->ft_type, &resource->ft_type, key_len);
4355 }
4356
4357 struct mlx5_hlist_entry *
4358 flow_dv_modify_create_cb(struct mlx5_hlist *list, uint64_t key __rte_unused,
4359                          void *cb_ctx)
4360 {
4361         struct mlx5_dev_ctx_shared *sh = list->ctx;
4362         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
4363         struct mlx5dv_dr_domain *ns;
4364         struct mlx5_flow_dv_modify_hdr_resource *entry;
4365         struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
4366         int ret;
4367         uint32_t data_len = ref->actions_num * sizeof(ref->actions[0]);
4368         uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
4369
4370         entry = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*entry) + data_len, 0,
4371                             SOCKET_ID_ANY);
4372         if (!entry) {
4373                 rte_flow_error_set(ctx->error, ENOMEM,
4374                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4375                                    "cannot allocate resource memory");
4376                 return NULL;
4377         }
4378         rte_memcpy(&entry->ft_type,
4379                    RTE_PTR_ADD(ref, offsetof(typeof(*ref), ft_type)),
4380                    key_len + data_len);
4381         if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
4382                 ns = sh->fdb_domain;
4383         else if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
4384                 ns = sh->tx_domain;
4385         else
4386                 ns = sh->rx_domain;
4387         ret = mlx5_flow_os_create_flow_action_modify_header
4388                                         (sh->ctx, ns, entry,
4389                                          data_len, &entry->action);
4390         if (ret) {
4391                 mlx5_free(entry);
4392                 rte_flow_error_set(ctx->error, ENOMEM,
4393                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4394                                    NULL, "cannot create modification action");
4395                 return NULL;
4396         }
4397         return &entry->entry;
4398 }
4399
4400 /**
4401  * Validate the sample action.
4402  *
4403  * @param[in] action_flags
4404  *   Holds the actions detected until now.
4405  * @param[in] action
4406  *   Pointer to the sample action.
4407  * @param[in] dev
4408  *   Pointer to the Ethernet device structure.
4409  * @param[in] attr
4410  *   Attributes of flow that includes this action.
4411  * @param[in] item_flags
4412  *   Holds the items detected.
4413  * @param[out] error
4414  *   Pointer to error structure.
4415  *
4416  * @return
4417  *   0 on success, a negative errno value otherwise and rte_errno is set.
4418  */
4419 static int
4420 flow_dv_validate_action_sample(uint64_t action_flags,
4421                                const struct rte_flow_action *action,
4422                                struct rte_eth_dev *dev,
4423                                const struct rte_flow_attr *attr,
4424                                const uint64_t item_flags,
4425                                struct rte_flow_error *error)
4426 {
4427         struct mlx5_priv *priv = dev->data->dev_private;
4428         struct mlx5_dev_config *dev_conf = &priv->config;
4429         const struct rte_flow_action_sample *sample = action->conf;
4430         const struct rte_flow_action *act;
4431         uint64_t sub_action_flags = 0;
4432         uint16_t queue_index = 0xFFFF;
4433         int actions_n = 0;
4434         int ret;
4435         fdb_mirror = 0;
4436
4437         if (!sample)
4438                 return rte_flow_error_set(error, EINVAL,
4439                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4440                                           "configuration cannot be NULL");
4441         if (sample->ratio == 0)
4442                 return rte_flow_error_set(error, EINVAL,
4443                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4444                                           "ratio value starts from 1");
4445         if (!priv->config.devx || (sample->ratio > 0 && !priv->sampler_en))
4446                 return rte_flow_error_set(error, ENOTSUP,
4447                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4448                                           NULL,
4449                                           "sample action not supported");
4450         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
4451                 return rte_flow_error_set(error, EINVAL,
4452                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4453                                           "Multiple sample actions not "
4454                                           "supported");
4455         if (action_flags & MLX5_FLOW_ACTION_METER)
4456                 return rte_flow_error_set(error, EINVAL,
4457                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4458                                           "wrong action order, meter should "
4459                                           "be after sample action");
4460         if (action_flags & MLX5_FLOW_ACTION_JUMP)
4461                 return rte_flow_error_set(error, EINVAL,
4462                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4463                                           "wrong action order, jump should "
4464                                           "be after sample action");
4465         act = sample->actions;
4466         for (; act->type != RTE_FLOW_ACTION_TYPE_END; act++) {
4467                 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
4468                         return rte_flow_error_set(error, ENOTSUP,
4469                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4470                                                   act, "too many actions");
4471                 switch (act->type) {
4472                 case RTE_FLOW_ACTION_TYPE_QUEUE:
4473                         ret = mlx5_flow_validate_action_queue(act,
4474                                                               sub_action_flags,
4475                                                               dev,
4476                                                               attr, error);
4477                         if (ret < 0)
4478                                 return ret;
4479                         queue_index = ((const struct rte_flow_action_queue *)
4480                                                         (act->conf))->index;
4481                         sub_action_flags |= MLX5_FLOW_ACTION_QUEUE;
4482                         ++actions_n;
4483                         break;
4484                 case RTE_FLOW_ACTION_TYPE_MARK:
4485                         ret = flow_dv_validate_action_mark(dev, act,
4486                                                            sub_action_flags,
4487                                                            attr, error);
4488                         if (ret < 0)
4489                                 return ret;
4490                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY)
4491                                 sub_action_flags |= MLX5_FLOW_ACTION_MARK |
4492                                                 MLX5_FLOW_ACTION_MARK_EXT;
4493                         else
4494                                 sub_action_flags |= MLX5_FLOW_ACTION_MARK;
4495                         ++actions_n;
4496                         break;
4497                 case RTE_FLOW_ACTION_TYPE_COUNT:
4498                         ret = flow_dv_validate_action_count(dev, error);
4499                         if (ret < 0)
4500                                 return ret;
4501                         sub_action_flags |= MLX5_FLOW_ACTION_COUNT;
4502                         ++actions_n;
4503                         break;
4504                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
4505                         ret = flow_dv_validate_action_port_id(dev,
4506                                                               sub_action_flags,
4507                                                               act,
4508                                                               attr,
4509                                                               error);
4510                         if (ret)
4511                                 return ret;
4512                         sub_action_flags |= MLX5_FLOW_ACTION_PORT_ID;
4513                         ++actions_n;
4514                         break;
4515                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
4516                         ret = flow_dv_validate_action_raw_encap_decap
4517                                 (dev, NULL, act->conf, attr, &sub_action_flags,
4518                                  &actions_n, action, item_flags, error);
4519                         if (ret < 0)
4520                                 return ret;
4521                         ++actions_n;
4522                         break;
4523                 default:
4524                         return rte_flow_error_set(error, ENOTSUP,
4525                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4526                                                   NULL,
4527                                                   "Doesn't support optional "
4528                                                   "action");
4529                 }
4530         }
4531         if (attr->ingress && !attr->transfer) {
4532                 if (!(sub_action_flags & MLX5_FLOW_ACTION_QUEUE))
4533                         return rte_flow_error_set(error, EINVAL,
4534                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4535                                                   NULL,
4536                                                   "Ingress must has a dest "
4537                                                   "QUEUE for Sample");
4538         } else if (attr->egress && !attr->transfer) {
4539                 return rte_flow_error_set(error, ENOTSUP,
4540                                           RTE_FLOW_ERROR_TYPE_ACTION,
4541                                           NULL,
4542                                           "Sample Only support Ingress "
4543                                           "or E-Switch");
4544         } else if (sample->actions->type != RTE_FLOW_ACTION_TYPE_END) {
4545                 MLX5_ASSERT(attr->transfer);
4546                 if (sample->ratio > 1)
4547                         return rte_flow_error_set(error, ENOTSUP,
4548                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4549                                                   NULL,
4550                                                   "E-Switch doesn't support "
4551                                                   "any optional action "
4552                                                   "for sampling");
4553                 fdb_mirror = 1;
4554                 if (sub_action_flags & MLX5_FLOW_ACTION_QUEUE)
4555                         return rte_flow_error_set(error, ENOTSUP,
4556                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4557                                                   NULL,
4558                                                   "unsupported action QUEUE");
4559                 if (!(sub_action_flags & MLX5_FLOW_ACTION_PORT_ID))
4560                         return rte_flow_error_set(error, EINVAL,
4561                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4562                                                   NULL,
4563                                                   "E-Switch must has a dest "
4564                                                   "port for mirroring");
4565         }
4566         /* Continue validation for Xcap actions.*/
4567         if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) &&
4568             (queue_index == 0xFFFF ||
4569              mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
4570                 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
4571                      MLX5_FLOW_XCAP_ACTIONS)
4572                         return rte_flow_error_set(error, ENOTSUP,
4573                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4574                                                   NULL, "encap and decap "
4575                                                   "combination aren't "
4576                                                   "supported");
4577                 if (!attr->transfer && attr->ingress && (sub_action_flags &
4578                                                         MLX5_FLOW_ACTION_ENCAP))
4579                         return rte_flow_error_set(error, ENOTSUP,
4580                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4581                                                   NULL, "encap is not supported"
4582                                                   " for ingress traffic");
4583         }
4584         return 0;
4585 }
4586
4587 /**
4588  * Find existing modify-header resource or create and register a new one.
4589  *
4590  * @param dev[in, out]
4591  *   Pointer to rte_eth_dev structure.
4592  * @param[in, out] resource
4593  *   Pointer to modify-header resource.
4594  * @parm[in, out] dev_flow
4595  *   Pointer to the dev_flow.
4596  * @param[out] error
4597  *   pointer to error structure.
4598  *
4599  * @return
4600  *   0 on success otherwise -errno and errno is set.
4601  */
4602 static int
4603 flow_dv_modify_hdr_resource_register
4604                         (struct rte_eth_dev *dev,
4605                          struct mlx5_flow_dv_modify_hdr_resource *resource,
4606                          struct mlx5_flow *dev_flow,
4607                          struct rte_flow_error *error)
4608 {
4609         struct mlx5_priv *priv = dev->data->dev_private;
4610         struct mlx5_dev_ctx_shared *sh = priv->sh;
4611         uint32_t key_len = sizeof(*resource) -
4612                            offsetof(typeof(*resource), ft_type) +
4613                            resource->actions_num * sizeof(resource->actions[0]);
4614         struct mlx5_hlist_entry *entry;
4615         struct mlx5_flow_cb_ctx ctx = {
4616                 .error = error,
4617                 .data = resource,
4618         };
4619         uint64_t key64;
4620
4621         resource->flags = dev_flow->dv.group ? 0 :
4622                           MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
4623         if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
4624                                     resource->flags))
4625                 return rte_flow_error_set(error, EOVERFLOW,
4626                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4627                                           "too many modify header items");
4628         key64 = __rte_raw_cksum(&resource->ft_type, key_len, 0);
4629         entry = mlx5_hlist_register(sh->modify_cmds, key64, &ctx);
4630         if (!entry)
4631                 return -rte_errno;
4632         resource = container_of(entry, typeof(*resource), entry);
4633         dev_flow->handle->dvh.modify_hdr = resource;
4634         return 0;
4635 }
4636
4637 /**
4638  * Get DV flow counter by index.
4639  *
4640  * @param[in] dev
4641  *   Pointer to the Ethernet device structure.
4642  * @param[in] idx
4643  *   mlx5 flow counter index in the container.
4644  * @param[out] ppool
4645  *   mlx5 flow counter pool in the container,
4646  *
4647  * @return
4648  *   Pointer to the counter, NULL otherwise.
4649  */
4650 static struct mlx5_flow_counter *
4651 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
4652                            uint32_t idx,
4653                            struct mlx5_flow_counter_pool **ppool)
4654 {
4655         struct mlx5_priv *priv = dev->data->dev_private;
4656         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4657         struct mlx5_flow_counter_pool *pool;
4658
4659         /* Decrease to original index and clear shared bit. */
4660         idx = (idx - 1) & (MLX5_CNT_SHARED_OFFSET - 1);
4661         MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cmng->n);
4662         pool = cmng->pools[idx / MLX5_COUNTERS_PER_POOL];
4663         MLX5_ASSERT(pool);
4664         if (ppool)
4665                 *ppool = pool;
4666         return MLX5_POOL_GET_CNT(pool, idx % MLX5_COUNTERS_PER_POOL);
4667 }
4668
4669 /**
4670  * Check the devx counter belongs to the pool.
4671  *
4672  * @param[in] pool
4673  *   Pointer to the counter pool.
4674  * @param[in] id
4675  *   The counter devx ID.
4676  *
4677  * @return
4678  *   True if counter belongs to the pool, false otherwise.
4679  */
4680 static bool
4681 flow_dv_is_counter_in_pool(struct mlx5_flow_counter_pool *pool, int id)
4682 {
4683         int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
4684                    MLX5_COUNTERS_PER_POOL;
4685
4686         if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
4687                 return true;
4688         return false;
4689 }
4690
4691 /**
4692  * Get a pool by devx counter ID.
4693  *
4694  * @param[in] cmng
4695  *   Pointer to the counter management.
4696  * @param[in] id
4697  *   The counter devx ID.
4698  *
4699  * @return
4700  *   The counter pool pointer if exists, NULL otherwise,
4701  */
4702 static struct mlx5_flow_counter_pool *
4703 flow_dv_find_pool_by_id(struct mlx5_flow_counter_mng *cmng, int id)
4704 {
4705         uint32_t i;
4706         struct mlx5_flow_counter_pool *pool = NULL;
4707
4708         rte_spinlock_lock(&cmng->pool_update_sl);
4709         /* Check last used pool. */
4710         if (cmng->last_pool_idx != POOL_IDX_INVALID &&
4711             flow_dv_is_counter_in_pool(cmng->pools[cmng->last_pool_idx], id)) {
4712                 pool = cmng->pools[cmng->last_pool_idx];
4713                 goto out;
4714         }
4715         /* ID out of range means no suitable pool in the container. */
4716         if (id > cmng->max_id || id < cmng->min_id)
4717                 goto out;
4718         /*
4719          * Find the pool from the end of the container, since mostly counter
4720          * ID is sequence increasing, and the last pool should be the needed
4721          * one.
4722          */
4723         i = cmng->n_valid;
4724         while (i--) {
4725                 struct mlx5_flow_counter_pool *pool_tmp = cmng->pools[i];
4726
4727                 if (flow_dv_is_counter_in_pool(pool_tmp, id)) {
4728                         pool = pool_tmp;
4729                         break;
4730                 }
4731         }
4732 out:
4733         rte_spinlock_unlock(&cmng->pool_update_sl);
4734         return pool;
4735 }
4736
4737 /**
4738  * Resize a counter container.
4739  *
4740  * @param[in] dev
4741  *   Pointer to the Ethernet device structure.
4742  *
4743  * @return
4744  *   0 on success, otherwise negative errno value and rte_errno is set.
4745  */
4746 static int
4747 flow_dv_container_resize(struct rte_eth_dev *dev)
4748 {
4749         struct mlx5_priv *priv = dev->data->dev_private;
4750         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4751         void *old_pools = cmng->pools;
4752         uint32_t resize = cmng->n + MLX5_CNT_CONTAINER_RESIZE;
4753         uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
4754         void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
4755
4756         if (!pools) {
4757                 rte_errno = ENOMEM;
4758                 return -ENOMEM;
4759         }
4760         if (old_pools)
4761                 memcpy(pools, old_pools, cmng->n *
4762                                        sizeof(struct mlx5_flow_counter_pool *));
4763         cmng->n = resize;
4764         cmng->pools = pools;
4765         if (old_pools)
4766                 mlx5_free(old_pools);
4767         return 0;
4768 }
4769
4770 /**
4771  * Query a devx flow counter.
4772  *
4773  * @param[in] dev
4774  *   Pointer to the Ethernet device structure.
4775  * @param[in] cnt
4776  *   Index to the flow counter.
4777  * @param[out] pkts
4778  *   The statistics value of packets.
4779  * @param[out] bytes
4780  *   The statistics value of bytes.
4781  *
4782  * @return
4783  *   0 on success, otherwise a negative errno value and rte_errno is set.
4784  */
4785 static inline int
4786 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
4787                      uint64_t *bytes)
4788 {
4789         struct mlx5_priv *priv = dev->data->dev_private;
4790         struct mlx5_flow_counter_pool *pool = NULL;
4791         struct mlx5_flow_counter *cnt;
4792         int offset;
4793
4794         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
4795         MLX5_ASSERT(pool);
4796         if (priv->sh->cmng.counter_fallback)
4797                 return mlx5_devx_cmd_flow_counter_query(cnt->dcs_when_active, 0,
4798                                         0, pkts, bytes, 0, NULL, NULL, 0);
4799         rte_spinlock_lock(&pool->sl);
4800         if (!pool->raw) {
4801                 *pkts = 0;
4802                 *bytes = 0;
4803         } else {
4804                 offset = MLX5_CNT_ARRAY_IDX(pool, cnt);
4805                 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
4806                 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
4807         }
4808         rte_spinlock_unlock(&pool->sl);
4809         return 0;
4810 }
4811
4812 /**
4813  * Create and initialize a new counter pool.
4814  *
4815  * @param[in] dev
4816  *   Pointer to the Ethernet device structure.
4817  * @param[out] dcs
4818  *   The devX counter handle.
4819  * @param[in] age
4820  *   Whether the pool is for counter that was allocated for aging.
4821  * @param[in/out] cont_cur
4822  *   Pointer to the container pointer, it will be update in pool resize.
4823  *
4824  * @return
4825  *   The pool container pointer on success, NULL otherwise and rte_errno is set.
4826  */
4827 static struct mlx5_flow_counter_pool *
4828 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
4829                     uint32_t age)
4830 {
4831         struct mlx5_priv *priv = dev->data->dev_private;
4832         struct mlx5_flow_counter_pool *pool;
4833         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4834         bool fallback = priv->sh->cmng.counter_fallback;
4835         uint32_t size = sizeof(*pool);
4836
4837         size += MLX5_COUNTERS_PER_POOL * MLX5_CNT_SIZE;
4838         size += (!age ? 0 : MLX5_COUNTERS_PER_POOL * MLX5_AGE_SIZE);
4839         pool = mlx5_malloc(MLX5_MEM_ZERO, size, 0, SOCKET_ID_ANY);
4840         if (!pool) {
4841                 rte_errno = ENOMEM;
4842                 return NULL;
4843         }
4844         pool->raw = NULL;
4845         pool->is_aged = !!age;
4846         pool->query_gen = 0;
4847         pool->min_dcs = dcs;
4848         rte_spinlock_init(&pool->sl);
4849         rte_spinlock_init(&pool->csl);
4850         TAILQ_INIT(&pool->counters[0]);
4851         TAILQ_INIT(&pool->counters[1]);
4852         pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
4853         rte_spinlock_lock(&cmng->pool_update_sl);
4854         pool->index = cmng->n_valid;
4855         if (pool->index == cmng->n && flow_dv_container_resize(dev)) {
4856                 mlx5_free(pool);
4857                 rte_spinlock_unlock(&cmng->pool_update_sl);
4858                 return NULL;
4859         }
4860         cmng->pools[pool->index] = pool;
4861         cmng->n_valid++;
4862         if (unlikely(fallback)) {
4863                 int base = RTE_ALIGN_FLOOR(dcs->id, MLX5_COUNTERS_PER_POOL);
4864
4865                 if (base < cmng->min_id)
4866                         cmng->min_id = base;
4867                 if (base > cmng->max_id)
4868                         cmng->max_id = base + MLX5_COUNTERS_PER_POOL - 1;
4869                 cmng->last_pool_idx = pool->index;
4870         }
4871         rte_spinlock_unlock(&cmng->pool_update_sl);
4872         return pool;
4873 }
4874
4875 /**
4876  * Prepare a new counter and/or a new counter pool.
4877  *
4878  * @param[in] dev
4879  *   Pointer to the Ethernet device structure.
4880  * @param[out] cnt_free
4881  *   Where to put the pointer of a new counter.
4882  * @param[in] age
4883  *   Whether the pool is for counter that was allocated for aging.
4884  *
4885  * @return
4886  *   The counter pool pointer and @p cnt_free is set on success,
4887  *   NULL otherwise and rte_errno is set.
4888  */
4889 static struct mlx5_flow_counter_pool *
4890 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
4891                              struct mlx5_flow_counter **cnt_free,
4892                              uint32_t age)
4893 {
4894         struct mlx5_priv *priv = dev->data->dev_private;
4895         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4896         struct mlx5_flow_counter_pool *pool;
4897         struct mlx5_counters tmp_tq;
4898         struct mlx5_devx_obj *dcs = NULL;
4899         struct mlx5_flow_counter *cnt;
4900         enum mlx5_counter_type cnt_type =
4901                         age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
4902         bool fallback = priv->sh->cmng.counter_fallback;
4903         uint32_t i;
4904
4905         if (fallback) {
4906                 /* bulk_bitmap must be 0 for single counter allocation. */
4907                 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
4908                 if (!dcs)
4909                         return NULL;
4910                 pool = flow_dv_find_pool_by_id(cmng, dcs->id);
4911                 if (!pool) {
4912                         pool = flow_dv_pool_create(dev, dcs, age);
4913                         if (!pool) {
4914                                 mlx5_devx_cmd_destroy(dcs);
4915                                 return NULL;
4916                         }
4917                 }
4918                 i = dcs->id % MLX5_COUNTERS_PER_POOL;
4919                 cnt = MLX5_POOL_GET_CNT(pool, i);
4920                 cnt->pool = pool;
4921                 cnt->dcs_when_free = dcs;
4922                 *cnt_free = cnt;
4923                 return pool;
4924         }
4925         dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
4926         if (!dcs) {
4927                 rte_errno = ENODATA;
4928                 return NULL;
4929         }
4930         pool = flow_dv_pool_create(dev, dcs, age);
4931         if (!pool) {
4932                 mlx5_devx_cmd_destroy(dcs);
4933                 return NULL;
4934         }
4935         TAILQ_INIT(&tmp_tq);
4936         for (i = 1; i < MLX5_COUNTERS_PER_POOL; ++i) {
4937                 cnt = MLX5_POOL_GET_CNT(pool, i);
4938                 cnt->pool = pool;
4939                 TAILQ_INSERT_HEAD(&tmp_tq, cnt, next);
4940         }
4941         rte_spinlock_lock(&cmng->csl[cnt_type]);
4942         TAILQ_CONCAT(&cmng->counters[cnt_type], &tmp_tq, next);
4943         rte_spinlock_unlock(&cmng->csl[cnt_type]);
4944         *cnt_free = MLX5_POOL_GET_CNT(pool, 0);
4945         (*cnt_free)->pool = pool;
4946         return pool;
4947 }
4948
4949 /**
4950  * Allocate a flow counter.
4951  *
4952  * @param[in] dev
4953  *   Pointer to the Ethernet device structure.
4954  * @param[in] age
4955  *   Whether the counter was allocated for aging.
4956  *
4957  * @return
4958  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
4959  */
4960 static uint32_t
4961 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t age)
4962 {
4963         struct mlx5_priv *priv = dev->data->dev_private;
4964         struct mlx5_flow_counter_pool *pool = NULL;
4965         struct mlx5_flow_counter *cnt_free = NULL;
4966         bool fallback = priv->sh->cmng.counter_fallback;
4967         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4968         enum mlx5_counter_type cnt_type =
4969                         age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
4970         uint32_t cnt_idx;
4971
4972         if (!priv->config.devx) {
4973                 rte_errno = ENOTSUP;
4974                 return 0;
4975         }
4976         /* Get free counters from container. */
4977         rte_spinlock_lock(&cmng->csl[cnt_type]);
4978         cnt_free = TAILQ_FIRST(&cmng->counters[cnt_type]);
4979         if (cnt_free)
4980                 TAILQ_REMOVE(&cmng->counters[cnt_type], cnt_free, next);
4981         rte_spinlock_unlock(&cmng->csl[cnt_type]);
4982         if (!cnt_free && !flow_dv_counter_pool_prepare(dev, &cnt_free, age))
4983                 goto err;
4984         pool = cnt_free->pool;
4985         if (fallback)
4986                 cnt_free->dcs_when_active = cnt_free->dcs_when_free;
4987         /* Create a DV counter action only in the first time usage. */
4988         if (!cnt_free->action) {
4989                 uint16_t offset;
4990                 struct mlx5_devx_obj *dcs;
4991                 int ret;
4992
4993                 if (!fallback) {
4994                         offset = MLX5_CNT_ARRAY_IDX(pool, cnt_free);
4995                         dcs = pool->min_dcs;
4996                 } else {
4997                         offset = 0;
4998                         dcs = cnt_free->dcs_when_free;
4999                 }
5000                 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, offset,
5001                                                             &cnt_free->action);
5002                 if (ret) {
5003                         rte_errno = errno;
5004                         goto err;
5005                 }
5006         }
5007         cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
5008                                 MLX5_CNT_ARRAY_IDX(pool, cnt_free));
5009         /* Update the counter reset values. */
5010         if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
5011                                  &cnt_free->bytes))
5012                 goto err;
5013         if (!fallback && !priv->sh->cmng.query_thread_on)
5014                 /* Start the asynchronous batch query by the host thread. */
5015                 mlx5_set_query_alarm(priv->sh);
5016         return cnt_idx;
5017 err:
5018         if (cnt_free) {
5019                 cnt_free->pool = pool;
5020                 if (fallback)
5021                         cnt_free->dcs_when_free = cnt_free->dcs_when_active;
5022                 rte_spinlock_lock(&cmng->csl[cnt_type]);
5023                 TAILQ_INSERT_TAIL(&cmng->counters[cnt_type], cnt_free, next);
5024                 rte_spinlock_unlock(&cmng->csl[cnt_type]);
5025         }
5026         return 0;
5027 }
5028
5029 /**
5030  * Allocate a shared flow counter.
5031  *
5032  * @param[in] ctx
5033  *   Pointer to the shared counter configuration.
5034  * @param[in] data
5035  *   Pointer to save the allocated counter index.
5036  *
5037  * @return
5038  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
5039  */
5040
5041 static int32_t
5042 flow_dv_counter_alloc_shared_cb(void *ctx, union mlx5_l3t_data *data)
5043 {
5044         struct mlx5_shared_counter_conf *conf = ctx;
5045         struct rte_eth_dev *dev = conf->dev;
5046         struct mlx5_flow_counter *cnt;
5047
5048         data->dword = flow_dv_counter_alloc(dev, 0);
5049         data->dword |= MLX5_CNT_SHARED_OFFSET;
5050         cnt = flow_dv_counter_get_by_idx(dev, data->dword, NULL);
5051         cnt->shared_info.id = conf->id;
5052         return 0;
5053 }
5054
5055 /**
5056  * Get a shared flow counter.
5057  *
5058  * @param[in] dev
5059  *   Pointer to the Ethernet device structure.
5060  * @param[in] id
5061  *   Counter identifier.
5062  *
5063  * @return
5064  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
5065  */
5066 static uint32_t
5067 flow_dv_counter_get_shared(struct rte_eth_dev *dev, uint32_t id)
5068 {
5069         struct mlx5_priv *priv = dev->data->dev_private;
5070         struct mlx5_shared_counter_conf conf = {
5071                 .dev = dev,
5072                 .id = id,
5073         };
5074         union mlx5_l3t_data data = {
5075                 .dword = 0,
5076         };
5077
5078         mlx5_l3t_prepare_entry(priv->sh->cnt_id_tbl, id, &data,
5079                                flow_dv_counter_alloc_shared_cb, &conf);
5080         return data.dword;
5081 }
5082
5083 /**
5084  * Get age param from counter index.
5085  *
5086  * @param[in] dev
5087  *   Pointer to the Ethernet device structure.
5088  * @param[in] counter
5089  *   Index to the counter handler.
5090  *
5091  * @return
5092  *   The aging parameter specified for the counter index.
5093  */
5094 static struct mlx5_age_param*
5095 flow_dv_counter_idx_get_age(struct rte_eth_dev *dev,
5096                                 uint32_t counter)
5097 {
5098         struct mlx5_flow_counter *cnt;
5099         struct mlx5_flow_counter_pool *pool = NULL;
5100
5101         flow_dv_counter_get_by_idx(dev, counter, &pool);
5102         counter = (counter - 1) % MLX5_COUNTERS_PER_POOL;
5103         cnt = MLX5_POOL_GET_CNT(pool, counter);
5104         return MLX5_CNT_TO_AGE(cnt);
5105 }
5106
5107 /**
5108  * Remove a flow counter from aged counter list.
5109  *
5110  * @param[in] dev
5111  *   Pointer to the Ethernet device structure.
5112  * @param[in] counter
5113  *   Index to the counter handler.
5114  * @param[in] cnt
5115  *   Pointer to the counter handler.
5116  */
5117 static void
5118 flow_dv_counter_remove_from_age(struct rte_eth_dev *dev,
5119                                 uint32_t counter, struct mlx5_flow_counter *cnt)
5120 {
5121         struct mlx5_age_info *age_info;
5122         struct mlx5_age_param *age_param;
5123         struct mlx5_priv *priv = dev->data->dev_private;
5124         uint16_t expected = AGE_CANDIDATE;
5125
5126         age_info = GET_PORT_AGE_INFO(priv);
5127         age_param = flow_dv_counter_idx_get_age(dev, counter);
5128         if (!__atomic_compare_exchange_n(&age_param->state, &expected,
5129                                          AGE_FREE, false, __ATOMIC_RELAXED,
5130                                          __ATOMIC_RELAXED)) {
5131                 /**
5132                  * We need the lock even it is age timeout,
5133                  * since counter may still in process.
5134                  */
5135                 rte_spinlock_lock(&age_info->aged_sl);
5136                 TAILQ_REMOVE(&age_info->aged_counters, cnt, next);
5137                 rte_spinlock_unlock(&age_info->aged_sl);
5138                 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
5139         }
5140 }
5141
5142 /**
5143  * Release a flow counter.
5144  *
5145  * @param[in] dev
5146  *   Pointer to the Ethernet device structure.
5147  * @param[in] counter
5148  *   Index to the counter handler.
5149  */
5150 static void
5151 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t counter)
5152 {
5153         struct mlx5_priv *priv = dev->data->dev_private;
5154         struct mlx5_flow_counter_pool *pool = NULL;
5155         struct mlx5_flow_counter *cnt;
5156         enum mlx5_counter_type cnt_type;
5157
5158         if (!counter)
5159                 return;
5160         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
5161         MLX5_ASSERT(pool);
5162         if (IS_SHARED_CNT(counter) &&
5163             mlx5_l3t_clear_entry(priv->sh->cnt_id_tbl, cnt->shared_info.id))
5164                 return;
5165         if (pool->is_aged)
5166                 flow_dv_counter_remove_from_age(dev, counter, cnt);
5167         cnt->pool = pool;
5168         /*
5169          * Put the counter back to list to be updated in none fallback mode.
5170          * Currently, we are using two list alternately, while one is in query,
5171          * add the freed counter to the other list based on the pool query_gen
5172          * value. After query finishes, add counter the list to the global
5173          * container counter list. The list changes while query starts. In
5174          * this case, lock will not be needed as query callback and release
5175          * function both operate with the different list.
5176          *
5177          */
5178         if (!priv->sh->cmng.counter_fallback) {
5179                 rte_spinlock_lock(&pool->csl);
5180                 TAILQ_INSERT_TAIL(&pool->counters[pool->query_gen], cnt, next);
5181                 rte_spinlock_unlock(&pool->csl);
5182         } else {
5183                 cnt->dcs_when_free = cnt->dcs_when_active;
5184                 cnt_type = pool->is_aged ? MLX5_COUNTER_TYPE_AGE :
5185                                            MLX5_COUNTER_TYPE_ORIGIN;
5186                 rte_spinlock_lock(&priv->sh->cmng.csl[cnt_type]);
5187                 TAILQ_INSERT_TAIL(&priv->sh->cmng.counters[cnt_type],
5188                                   cnt, next);
5189                 rte_spinlock_unlock(&priv->sh->cmng.csl[cnt_type]);
5190         }
5191 }
5192
5193 /**
5194  * Verify the @p attributes will be correctly understood by the NIC and store
5195  * them in the @p flow if everything is correct.
5196  *
5197  * @param[in] dev
5198  *   Pointer to dev struct.
5199  * @param[in] attributes
5200  *   Pointer to flow attributes
5201  * @param[in] external
5202  *   This flow rule is created by request external to PMD.
5203  * @param[out] error
5204  *   Pointer to error structure.
5205  *
5206  * @return
5207  *   - 0 on success and non root table.
5208  *   - 1 on success and root table.
5209  *   - a negative errno value otherwise and rte_errno is set.
5210  */
5211 static int
5212 flow_dv_validate_attributes(struct rte_eth_dev *dev,
5213                             const struct mlx5_flow_tunnel *tunnel,
5214                             const struct rte_flow_attr *attributes,
5215                             const struct flow_grp_info *grp_info,
5216                             struct rte_flow_error *error)
5217 {
5218         struct mlx5_priv *priv = dev->data->dev_private;
5219         uint32_t priority_max = priv->config.flow_prio - 1;
5220         int ret = 0;
5221
5222 #ifndef HAVE_MLX5DV_DR
5223         RTE_SET_USED(tunnel);
5224         RTE_SET_USED(grp_info);
5225         if (attributes->group)
5226                 return rte_flow_error_set(error, ENOTSUP,
5227                                           RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
5228                                           NULL,
5229                                           "groups are not supported");
5230 #else
5231         uint32_t table = 0;
5232
5233         ret = mlx5_flow_group_to_table(dev, tunnel, attributes->group, &table,
5234                                        grp_info, error);
5235         if (ret)
5236                 return ret;
5237         if (!table)
5238                 ret = MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
5239 #endif
5240         if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
5241             attributes->priority >= priority_max)
5242                 return rte_flow_error_set(error, ENOTSUP,
5243                                           RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
5244                                           NULL,
5245                                           "priority out of range");
5246         if (attributes->transfer) {
5247                 if (!priv->config.dv_esw_en)
5248                         return rte_flow_error_set
5249                                 (error, ENOTSUP,
5250                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5251                                  "E-Switch dr is not supported");
5252                 if (!(priv->representor || priv->master))
5253                         return rte_flow_error_set
5254                                 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5255                                  NULL, "E-Switch configuration can only be"
5256                                  " done by a master or a representor device");
5257                 if (attributes->egress)
5258                         return rte_flow_error_set
5259                                 (error, ENOTSUP,
5260                                  RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
5261                                  "egress is not supported");
5262         }
5263         if (!(attributes->egress ^ attributes->ingress))
5264                 return rte_flow_error_set(error, ENOTSUP,
5265                                           RTE_FLOW_ERROR_TYPE_ATTR, NULL,
5266                                           "must specify exactly one of "
5267                                           "ingress or egress");
5268         return ret;
5269 }
5270
5271 /**
5272  * Internal validation function. For validating both actions and items.
5273  *
5274  * @param[in] dev
5275  *   Pointer to the rte_eth_dev structure.
5276  * @param[in] attr
5277  *   Pointer to the flow attributes.
5278  * @param[in] items
5279  *   Pointer to the list of items.
5280  * @param[in] actions
5281  *   Pointer to the list of actions.
5282  * @param[in] external
5283  *   This flow rule is created by request external to PMD.
5284  * @param[in] hairpin
5285  *   Number of hairpin TX actions, 0 means classic flow.
5286  * @param[out] error
5287  *   Pointer to the error structure.
5288  *
5289  * @return
5290  *   0 on success, a negative errno value otherwise and rte_errno is set.
5291  */
5292 static int
5293 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
5294                  const struct rte_flow_item items[],
5295                  const struct rte_flow_action actions[],
5296                  bool external, int hairpin, struct rte_flow_error *error)
5297 {
5298         int ret;
5299         uint64_t action_flags = 0;
5300         uint64_t item_flags = 0;
5301         uint64_t last_item = 0;
5302         uint8_t next_protocol = 0xff;
5303         uint16_t ether_type = 0;
5304         int actions_n = 0;
5305         uint8_t item_ipv6_proto = 0;
5306         const struct rte_flow_item *gre_item = NULL;
5307         const struct rte_flow_item *gtp_item = NULL;
5308         const struct rte_flow_action_raw_decap *decap;
5309         const struct rte_flow_action_raw_encap *encap;
5310         const struct rte_flow_action_rss *rss;
5311         const struct rte_flow_item_tcp nic_tcp_mask = {
5312                 .hdr = {
5313                         .tcp_flags = 0xFF,
5314                         .src_port = RTE_BE16(UINT16_MAX),
5315                         .dst_port = RTE_BE16(UINT16_MAX),
5316                 }
5317         };
5318         const struct rte_flow_item_ipv6 nic_ipv6_mask = {
5319                 .hdr = {
5320                         .src_addr =
5321                         "\xff\xff\xff\xff\xff\xff\xff\xff"
5322                         "\xff\xff\xff\xff\xff\xff\xff\xff",
5323                         .dst_addr =
5324                         "\xff\xff\xff\xff\xff\xff\xff\xff"
5325                         "\xff\xff\xff\xff\xff\xff\xff\xff",
5326                         .vtc_flow = RTE_BE32(0xffffffff),
5327                         .proto = 0xff,
5328                         .hop_limits = 0xff,
5329                 },
5330                 .has_frag_ext = 1,
5331         };
5332         const struct rte_flow_item_ecpri nic_ecpri_mask = {
5333                 .hdr = {
5334                         .common = {
5335                                 .u32 =
5336                                 RTE_BE32(((const struct rte_ecpri_common_hdr) {
5337                                         .type = 0xFF,
5338                                         }).u32),
5339                         },
5340                         .dummy[0] = 0xffffffff,
5341                 },
5342         };
5343         struct mlx5_priv *priv = dev->data->dev_private;
5344         struct mlx5_dev_config *dev_conf = &priv->config;
5345         uint16_t queue_index = 0xFFFF;
5346         const struct rte_flow_item_vlan *vlan_m = NULL;
5347         int16_t rw_act_num = 0;
5348         uint64_t is_root;
5349         const struct mlx5_flow_tunnel *tunnel;
5350         struct flow_grp_info grp_info = {
5351                 .external = !!external,
5352                 .transfer = !!attr->transfer,
5353                 .fdb_def_rule = !!priv->fdb_def_rule,
5354         };
5355         const struct rte_eth_hairpin_conf *conf;
5356
5357         if (items == NULL)
5358                 return -1;
5359         if (is_flow_tunnel_match_rule(dev, attr, items, actions)) {
5360                 tunnel = flow_items_to_tunnel(items);
5361                 action_flags |= MLX5_FLOW_ACTION_TUNNEL_MATCH |
5362                                 MLX5_FLOW_ACTION_DECAP;
5363         } else if (is_flow_tunnel_steer_rule(dev, attr, items, actions)) {
5364                 tunnel = flow_actions_to_tunnel(actions);
5365                 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
5366         } else {
5367                 tunnel = NULL;
5368         }
5369         if (tunnel && priv->representor)
5370                 return rte_flow_error_set(error, ENOTSUP,
5371                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5372                                           "decap not supported "
5373                                           "for VF representor");
5374         grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
5375                                 (dev, tunnel, attr, items, actions);
5376         ret = flow_dv_validate_attributes(dev, tunnel, attr, &grp_info, error);
5377         if (ret < 0)
5378                 return ret;
5379         is_root = (uint64_t)ret;
5380         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
5381                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
5382                 int type = items->type;
5383
5384                 if (!mlx5_flow_os_item_supported(type))
5385                         return rte_flow_error_set(error, ENOTSUP,
5386                                                   RTE_FLOW_ERROR_TYPE_ITEM,
5387                                                   NULL, "item not supported");
5388                 switch (type) {
5389                 case MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL:
5390                         if (items[0].type != (typeof(items[0].type))
5391                                                 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL)
5392                                 return rte_flow_error_set
5393                                                 (error, EINVAL,
5394                                                 RTE_FLOW_ERROR_TYPE_ITEM,
5395                                                 NULL, "MLX5 private items "
5396                                                 "must be the first");
5397                         break;
5398                 case RTE_FLOW_ITEM_TYPE_VOID:
5399                         break;
5400                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
5401                         ret = flow_dv_validate_item_port_id
5402                                         (dev, items, attr, item_flags, error);
5403                         if (ret < 0)
5404                                 return ret;
5405                         last_item = MLX5_FLOW_ITEM_PORT_ID;
5406                         break;
5407                 case RTE_FLOW_ITEM_TYPE_ETH:
5408                         ret = mlx5_flow_validate_item_eth(items, item_flags,
5409                                                           true, error);
5410                         if (ret < 0)
5411                                 return ret;
5412                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
5413                                              MLX5_FLOW_LAYER_OUTER_L2;
5414                         if (items->mask != NULL && items->spec != NULL) {
5415                                 ether_type =
5416                                         ((const struct rte_flow_item_eth *)
5417                                          items->spec)->type;
5418                                 ether_type &=
5419                                         ((const struct rte_flow_item_eth *)
5420                                          items->mask)->type;
5421                                 ether_type = rte_be_to_cpu_16(ether_type);
5422                         } else {
5423                                 ether_type = 0;
5424                         }
5425                         break;
5426                 case RTE_FLOW_ITEM_TYPE_VLAN:
5427                         ret = flow_dv_validate_item_vlan(items, item_flags,
5428                                                          dev, error);
5429                         if (ret < 0)
5430                                 return ret;
5431                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
5432                                              MLX5_FLOW_LAYER_OUTER_VLAN;
5433                         if (items->mask != NULL && items->spec != NULL) {
5434                                 ether_type =
5435                                         ((const struct rte_flow_item_vlan *)
5436                                          items->spec)->inner_type;
5437                                 ether_type &=
5438                                         ((const struct rte_flow_item_vlan *)
5439                                          items->mask)->inner_type;
5440                                 ether_type = rte_be_to_cpu_16(ether_type);
5441                         } else {
5442                                 ether_type = 0;
5443                         }
5444                         /* Store outer VLAN mask for of_push_vlan action. */
5445                         if (!tunnel)
5446                                 vlan_m = items->mask;
5447                         break;
5448                 case RTE_FLOW_ITEM_TYPE_IPV4:
5449                         mlx5_flow_tunnel_ip_check(items, next_protocol,
5450                                                   &item_flags, &tunnel);
5451                         ret = flow_dv_validate_item_ipv4(items, item_flags,
5452                                                          last_item, ether_type,
5453                                                          error);
5454                         if (ret < 0)
5455                                 return ret;
5456                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
5457                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
5458                         if (items->mask != NULL &&
5459                             ((const struct rte_flow_item_ipv4 *)
5460                              items->mask)->hdr.next_proto_id) {
5461                                 next_protocol =
5462                                         ((const struct rte_flow_item_ipv4 *)
5463                                          (items->spec))->hdr.next_proto_id;
5464                                 next_protocol &=
5465                                         ((const struct rte_flow_item_ipv4 *)
5466                                          (items->mask))->hdr.next_proto_id;
5467                         } else {
5468                                 /* Reset for inner layer. */
5469                                 next_protocol = 0xff;
5470                         }
5471                         break;
5472                 case RTE_FLOW_ITEM_TYPE_IPV6:
5473                         mlx5_flow_tunnel_ip_check(items, next_protocol,
5474                                                   &item_flags, &tunnel);
5475                         ret = mlx5_flow_validate_item_ipv6(items, item_flags,
5476                                                            last_item,
5477                                                            ether_type,
5478                                                            &nic_ipv6_mask,
5479                                                            error);
5480                         if (ret < 0)
5481                                 return ret;
5482                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
5483                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
5484                         if (items->mask != NULL &&
5485                             ((const struct rte_flow_item_ipv6 *)
5486                              items->mask)->hdr.proto) {
5487                                 item_ipv6_proto =
5488                                         ((const struct rte_flow_item_ipv6 *)
5489                                          items->spec)->hdr.proto;
5490                                 next_protocol =
5491                                         ((const struct rte_flow_item_ipv6 *)
5492                                          items->spec)->hdr.proto;
5493                                 next_protocol &=
5494                                         ((const struct rte_flow_item_ipv6 *)
5495                                          items->mask)->hdr.proto;
5496                         } else {
5497                                 /* Reset for inner layer. */
5498                                 next_protocol = 0xff;
5499                         }
5500                         break;
5501                 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
5502                         ret = flow_dv_validate_item_ipv6_frag_ext(items,
5503                                                                   item_flags,
5504                                                                   error);
5505                         if (ret < 0)
5506                                 return ret;
5507                         last_item = tunnel ?
5508                                         MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
5509                                         MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
5510                         if (items->mask != NULL &&
5511                             ((const struct rte_flow_item_ipv6_frag_ext *)
5512                              items->mask)->hdr.next_header) {
5513                                 next_protocol =
5514                                 ((const struct rte_flow_item_ipv6_frag_ext *)
5515                                  items->spec)->hdr.next_header;
5516                                 next_protocol &=
5517                                 ((const struct rte_flow_item_ipv6_frag_ext *)
5518                                  items->mask)->hdr.next_header;
5519                         } else {
5520                                 /* Reset for inner layer. */
5521                                 next_protocol = 0xff;
5522                         }
5523                         break;
5524                 case RTE_FLOW_ITEM_TYPE_TCP:
5525                         ret = mlx5_flow_validate_item_tcp
5526                                                 (items, item_flags,
5527                                                  next_protocol,
5528                                                  &nic_tcp_mask,
5529                                                  error);
5530                         if (ret < 0)
5531                                 return ret;
5532                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
5533                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
5534                         break;
5535                 case RTE_FLOW_ITEM_TYPE_UDP:
5536                         ret = mlx5_flow_validate_item_udp(items, item_flags,
5537                                                           next_protocol,
5538                                                           error);
5539                         if (ret < 0)
5540                                 return ret;
5541                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
5542                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
5543                         break;
5544                 case RTE_FLOW_ITEM_TYPE_GRE:
5545                         ret = mlx5_flow_validate_item_gre(items, item_flags,
5546                                                           next_protocol, error);
5547                         if (ret < 0)
5548                                 return ret;
5549                         gre_item = items;
5550                         last_item = MLX5_FLOW_LAYER_GRE;
5551                         break;
5552                 case RTE_FLOW_ITEM_TYPE_NVGRE:
5553                         ret = mlx5_flow_validate_item_nvgre(items, item_flags,
5554                                                             next_protocol,
5555                                                             error);
5556                         if (ret < 0)
5557                                 return ret;
5558                         last_item = MLX5_FLOW_LAYER_NVGRE;
5559                         break;
5560                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
5561                         ret = mlx5_flow_validate_item_gre_key
5562                                 (items, item_flags, gre_item, error);
5563                         if (ret < 0)
5564                                 return ret;
5565                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
5566                         break;
5567                 case RTE_FLOW_ITEM_TYPE_VXLAN:
5568                         ret = mlx5_flow_validate_item_vxlan(items, item_flags,
5569                                                             error);
5570                         if (ret < 0)
5571                                 return ret;
5572                         last_item = MLX5_FLOW_LAYER_VXLAN;
5573                         break;
5574                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
5575                         ret = mlx5_flow_validate_item_vxlan_gpe(items,
5576                                                                 item_flags, dev,
5577                                                                 error);
5578                         if (ret < 0)
5579                                 return ret;
5580                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
5581                         break;
5582                 case RTE_FLOW_ITEM_TYPE_GENEVE:
5583                         ret = mlx5_flow_validate_item_geneve(items,
5584                                                              item_flags, dev,
5585                                                              error);
5586                         if (ret < 0)
5587                                 return ret;
5588                         last_item = MLX5_FLOW_LAYER_GENEVE;
5589                         break;
5590                 case RTE_FLOW_ITEM_TYPE_MPLS:
5591                         ret = mlx5_flow_validate_item_mpls(dev, items,
5592                                                            item_flags,
5593                                                            last_item, error);
5594                         if (ret < 0)
5595                                 return ret;
5596                         last_item = MLX5_FLOW_LAYER_MPLS;
5597                         break;
5598
5599                 case RTE_FLOW_ITEM_TYPE_MARK:
5600                         ret = flow_dv_validate_item_mark(dev, items, attr,
5601                                                          error);
5602                         if (ret < 0)
5603                                 return ret;
5604                         last_item = MLX5_FLOW_ITEM_MARK;
5605                         break;
5606                 case RTE_FLOW_ITEM_TYPE_META:
5607                         ret = flow_dv_validate_item_meta(dev, items, attr,
5608                                                          error);
5609                         if (ret < 0)
5610                                 return ret;
5611                         last_item = MLX5_FLOW_ITEM_METADATA;
5612                         break;
5613                 case RTE_FLOW_ITEM_TYPE_ICMP:
5614                         ret = mlx5_flow_validate_item_icmp(items, item_flags,
5615                                                            next_protocol,
5616                                                            error);
5617                         if (ret < 0)
5618                                 return ret;
5619                         last_item = MLX5_FLOW_LAYER_ICMP;
5620                         break;
5621                 case RTE_FLOW_ITEM_TYPE_ICMP6:
5622                         ret = mlx5_flow_validate_item_icmp6(items, item_flags,
5623                                                             next_protocol,
5624                                                             error);
5625                         if (ret < 0)
5626                                 return ret;
5627                         item_ipv6_proto = IPPROTO_ICMPV6;
5628                         last_item = MLX5_FLOW_LAYER_ICMP6;
5629                         break;
5630                 case RTE_FLOW_ITEM_TYPE_TAG:
5631                         ret = flow_dv_validate_item_tag(dev, items,
5632                                                         attr, error);
5633                         if (ret < 0)
5634                                 return ret;
5635                         last_item = MLX5_FLOW_ITEM_TAG;
5636                         break;
5637                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
5638                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
5639                         break;
5640                 case RTE_FLOW_ITEM_TYPE_GTP:
5641                         ret = flow_dv_validate_item_gtp(dev, items, item_flags,
5642                                                         error);
5643                         if (ret < 0)
5644                                 return ret;
5645                         gtp_item = items;
5646                         last_item = MLX5_FLOW_LAYER_GTP;
5647                         break;
5648                 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
5649                         ret = flow_dv_validate_item_gtp_psc(items, last_item,
5650                                                             gtp_item, attr,
5651                                                             error);
5652                         if (ret < 0)
5653                                 return ret;
5654                         last_item = MLX5_FLOW_LAYER_GTP_PSC;
5655                         break;
5656                 case RTE_FLOW_ITEM_TYPE_ECPRI:
5657                         /* Capacity will be checked in the translate stage. */
5658                         ret = mlx5_flow_validate_item_ecpri(items, item_flags,
5659                                                             last_item,
5660                                                             ether_type,
5661                                                             &nic_ecpri_mask,
5662                                                             error);
5663                         if (ret < 0)
5664                                 return ret;
5665                         last_item = MLX5_FLOW_LAYER_ECPRI;
5666                         break;
5667                 default:
5668                         return rte_flow_error_set(error, ENOTSUP,
5669                                                   RTE_FLOW_ERROR_TYPE_ITEM,
5670                                                   NULL, "item not supported");
5671                 }
5672                 item_flags |= last_item;
5673         }
5674         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
5675                 int type = actions->type;
5676
5677                 if (!mlx5_flow_os_action_supported(type))
5678                         return rte_flow_error_set(error, ENOTSUP,
5679                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5680                                                   actions,
5681                                                   "action not supported");
5682                 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
5683                         return rte_flow_error_set(error, ENOTSUP,
5684                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5685                                                   actions, "too many actions");
5686                 switch (type) {
5687                 case RTE_FLOW_ACTION_TYPE_VOID:
5688                         break;
5689                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5690                         ret = flow_dv_validate_action_port_id(dev,
5691                                                               action_flags,
5692                                                               actions,
5693                                                               attr,
5694                                                               error);
5695                         if (ret)
5696                                 return ret;
5697                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5698                         ++actions_n;
5699                         break;
5700                 case RTE_FLOW_ACTION_TYPE_FLAG:
5701                         ret = flow_dv_validate_action_flag(dev, action_flags,
5702                                                            attr, error);
5703                         if (ret < 0)
5704                                 return ret;
5705                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
5706                                 /* Count all modify-header actions as one. */
5707                                 if (!(action_flags &
5708                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
5709                                         ++actions_n;
5710                                 action_flags |= MLX5_FLOW_ACTION_FLAG |
5711                                                 MLX5_FLOW_ACTION_MARK_EXT;
5712                         } else {
5713                                 action_flags |= MLX5_FLOW_ACTION_FLAG;
5714                                 ++actions_n;
5715                         }
5716                         rw_act_num += MLX5_ACT_NUM_SET_MARK;
5717                         break;
5718                 case RTE_FLOW_ACTION_TYPE_MARK:
5719                         ret = flow_dv_validate_action_mark(dev, actions,
5720                                                            action_flags,
5721                                                            attr, error);
5722                         if (ret < 0)
5723                                 return ret;
5724                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
5725                                 /* Count all modify-header actions as one. */
5726                                 if (!(action_flags &
5727                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
5728                                         ++actions_n;
5729                                 action_flags |= MLX5_FLOW_ACTION_MARK |
5730                                                 MLX5_FLOW_ACTION_MARK_EXT;
5731                         } else {
5732                                 action_flags |= MLX5_FLOW_ACTION_MARK;
5733                                 ++actions_n;
5734                         }
5735                         rw_act_num += MLX5_ACT_NUM_SET_MARK;
5736                         break;
5737                 case RTE_FLOW_ACTION_TYPE_SET_META:
5738                         ret = flow_dv_validate_action_set_meta(dev, actions,
5739                                                                action_flags,
5740                                                                attr, error);
5741                         if (ret < 0)
5742                                 return ret;
5743                         /* Count all modify-header actions as one action. */
5744                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5745                                 ++actions_n;
5746                         action_flags |= MLX5_FLOW_ACTION_SET_META;
5747                         rw_act_num += MLX5_ACT_NUM_SET_META;
5748                         break;
5749                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
5750                         ret = flow_dv_validate_action_set_tag(dev, actions,
5751                                                               action_flags,
5752                                                               attr, error);
5753                         if (ret < 0)
5754                                 return ret;
5755                         /* Count all modify-header actions as one action. */
5756                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5757                                 ++actions_n;
5758                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
5759                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
5760                         break;
5761                 case RTE_FLOW_ACTION_TYPE_DROP:
5762                         ret = mlx5_flow_validate_action_drop(action_flags,
5763                                                              attr, error);
5764                         if (ret < 0)
5765                                 return ret;
5766                         action_flags |= MLX5_FLOW_ACTION_DROP;
5767                         ++actions_n;
5768                         break;
5769                 case RTE_FLOW_ACTION_TYPE_QUEUE:
5770                         ret = mlx5_flow_validate_action_queue(actions,
5771                                                               action_flags, dev,
5772                                                               attr, error);
5773                         if (ret < 0)
5774                                 return ret;
5775                         queue_index = ((const struct rte_flow_action_queue *)
5776                                                         (actions->conf))->index;
5777                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
5778                         ++actions_n;
5779                         break;
5780                 case RTE_FLOW_ACTION_TYPE_RSS:
5781                         rss = actions->conf;
5782                         ret = mlx5_flow_validate_action_rss(actions,
5783                                                             action_flags, dev,
5784                                                             attr, item_flags,
5785                                                             error);
5786                         if (ret < 0)
5787                                 return ret;
5788                         if (rss != NULL && rss->queue_num)
5789                                 queue_index = rss->queue[0];
5790                         action_flags |= MLX5_FLOW_ACTION_RSS;
5791                         ++actions_n;
5792                         break;
5793                 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
5794                         ret =
5795                         mlx5_flow_validate_action_default_miss(action_flags,
5796                                         attr, error);
5797                         if (ret < 0)
5798                                 return ret;
5799                         action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
5800                         ++actions_n;
5801                         break;
5802                 case RTE_FLOW_ACTION_TYPE_COUNT:
5803                         ret = flow_dv_validate_action_count(dev, error);
5804                         if (ret < 0)
5805                                 return ret;
5806                         action_flags |= MLX5_FLOW_ACTION_COUNT;
5807                         ++actions_n;
5808                         break;
5809                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
5810                         if (flow_dv_validate_action_pop_vlan(dev,
5811                                                              action_flags,
5812                                                              actions,
5813                                                              item_flags, attr,
5814                                                              error))
5815                                 return -rte_errno;
5816                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
5817                         ++actions_n;
5818                         break;
5819                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
5820                         ret = flow_dv_validate_action_push_vlan(dev,
5821                                                                 action_flags,
5822                                                                 vlan_m,
5823                                                                 actions, attr,
5824                                                                 error);
5825                         if (ret < 0)
5826                                 return ret;
5827                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
5828                         ++actions_n;
5829                         break;
5830                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
5831                         ret = flow_dv_validate_action_set_vlan_pcp
5832                                                 (action_flags, actions, error);
5833                         if (ret < 0)
5834                                 return ret;
5835                         /* Count PCP with push_vlan command. */
5836                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
5837                         break;
5838                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
5839                         ret = flow_dv_validate_action_set_vlan_vid
5840                                                 (item_flags, action_flags,
5841                                                  actions, error);
5842                         if (ret < 0)
5843                                 return ret;
5844                         /* Count VID with push_vlan command. */
5845                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
5846                         rw_act_num += MLX5_ACT_NUM_MDF_VID;
5847                         break;
5848                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5849                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5850                         ret = flow_dv_validate_action_l2_encap(dev,
5851                                                                action_flags,
5852                                                                actions, attr,
5853                                                                error);
5854                         if (ret < 0)
5855                                 return ret;
5856                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
5857                         ++actions_n;
5858                         break;
5859                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
5860                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
5861                         ret = flow_dv_validate_action_decap(dev, action_flags,
5862                                                             actions, item_flags,
5863                                                             attr, error);
5864                         if (ret < 0)
5865                                 return ret;
5866                         action_flags |= MLX5_FLOW_ACTION_DECAP;
5867                         ++actions_n;
5868                         break;
5869                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5870                         ret = flow_dv_validate_action_raw_encap_decap
5871                                 (dev, NULL, actions->conf, attr, &action_flags,
5872                                  &actions_n, actions, item_flags, error);
5873                         if (ret < 0)
5874                                 return ret;
5875                         break;
5876                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
5877                         decap = actions->conf;
5878                         while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
5879                                 ;
5880                         if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
5881                                 encap = NULL;
5882                                 actions--;
5883                         } else {
5884                                 encap = actions->conf;
5885                         }
5886                         ret = flow_dv_validate_action_raw_encap_decap
5887                                            (dev,
5888                                             decap ? decap : &empty_decap, encap,
5889                                             attr, &action_flags, &actions_n,
5890                                             actions, item_flags, error);
5891                         if (ret < 0)
5892                                 return ret;
5893                         break;
5894                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
5895                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
5896                         ret = flow_dv_validate_action_modify_mac(action_flags,
5897                                                                  actions,
5898                                                                  item_flags,
5899                                                                  error);
5900                         if (ret < 0)
5901                                 return ret;
5902                         /* Count all modify-header actions as one action. */
5903                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5904                                 ++actions_n;
5905                         action_flags |= actions->type ==
5906                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
5907                                                 MLX5_FLOW_ACTION_SET_MAC_SRC :
5908                                                 MLX5_FLOW_ACTION_SET_MAC_DST;
5909                         /*
5910                          * Even if the source and destination MAC addresses have
5911                          * overlap in the header with 4B alignment, the convert
5912                          * function will handle them separately and 4 SW actions
5913                          * will be created. And 2 actions will be added each
5914                          * time no matter how many bytes of address will be set.
5915                          */
5916                         rw_act_num += MLX5_ACT_NUM_MDF_MAC;
5917                         break;
5918                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
5919                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
5920                         ret = flow_dv_validate_action_modify_ipv4(action_flags,
5921                                                                   actions,
5922                                                                   item_flags,
5923                                                                   error);
5924                         if (ret < 0)
5925                                 return ret;
5926                         /* Count all modify-header actions as one action. */
5927                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5928                                 ++actions_n;
5929                         action_flags |= actions->type ==
5930                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
5931                                                 MLX5_FLOW_ACTION_SET_IPV4_SRC :
5932                                                 MLX5_FLOW_ACTION_SET_IPV4_DST;
5933                         rw_act_num += MLX5_ACT_NUM_MDF_IPV4;
5934                         break;
5935                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
5936                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
5937                         ret = flow_dv_validate_action_modify_ipv6(action_flags,
5938                                                                   actions,
5939                                                                   item_flags,
5940                                                                   error);
5941                         if (ret < 0)
5942                                 return ret;
5943                         if (item_ipv6_proto == IPPROTO_ICMPV6)
5944                                 return rte_flow_error_set(error, ENOTSUP,
5945                                         RTE_FLOW_ERROR_TYPE_ACTION,
5946                                         actions,
5947                                         "Can't change header "
5948                                         "with ICMPv6 proto");
5949                         /* Count all modify-header actions as one action. */
5950                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5951                                 ++actions_n;
5952                         action_flags |= actions->type ==
5953                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
5954                                                 MLX5_FLOW_ACTION_SET_IPV6_SRC :
5955                                                 MLX5_FLOW_ACTION_SET_IPV6_DST;
5956                         rw_act_num += MLX5_ACT_NUM_MDF_IPV6;
5957                         break;
5958                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
5959                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
5960                         ret = flow_dv_validate_action_modify_tp(action_flags,
5961                                                                 actions,
5962                                                                 item_flags,
5963                                                                 error);
5964                         if (ret < 0)
5965                                 return ret;
5966                         /* Count all modify-header actions as one action. */
5967                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5968                                 ++actions_n;
5969                         action_flags |= actions->type ==
5970                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
5971                                                 MLX5_FLOW_ACTION_SET_TP_SRC :
5972                                                 MLX5_FLOW_ACTION_SET_TP_DST;
5973                         rw_act_num += MLX5_ACT_NUM_MDF_PORT;
5974                         break;
5975                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
5976                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
5977                         ret = flow_dv_validate_action_modify_ttl(action_flags,
5978                                                                  actions,
5979                                                                  item_flags,
5980                                                                  error);
5981                         if (ret < 0)
5982                                 return ret;
5983                         /* Count all modify-header actions as one action. */
5984                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5985                                 ++actions_n;
5986                         action_flags |= actions->type ==
5987                                         RTE_FLOW_ACTION_TYPE_SET_TTL ?
5988                                                 MLX5_FLOW_ACTION_SET_TTL :
5989                                                 MLX5_FLOW_ACTION_DEC_TTL;
5990                         rw_act_num += MLX5_ACT_NUM_MDF_TTL;
5991                         break;
5992                 case RTE_FLOW_ACTION_TYPE_JUMP:
5993                         ret = flow_dv_validate_action_jump(dev, tunnel, actions,
5994                                                            action_flags,
5995                                                            attr, external,
5996                                                            error);
5997                         if (ret)
5998                                 return ret;
5999                         ++actions_n;
6000                         action_flags |= MLX5_FLOW_ACTION_JUMP;
6001                         break;
6002                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
6003                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
6004                         ret = flow_dv_validate_action_modify_tcp_seq
6005                                                                 (action_flags,
6006                                                                  actions,
6007                                                                  item_flags,
6008                                                                  error);
6009                         if (ret < 0)
6010                                 return ret;
6011                         /* Count all modify-header actions as one action. */
6012                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6013                                 ++actions_n;
6014                         action_flags |= actions->type ==
6015                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
6016                                                 MLX5_FLOW_ACTION_INC_TCP_SEQ :
6017                                                 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
6018                         rw_act_num += MLX5_ACT_NUM_MDF_TCPSEQ;
6019                         break;
6020                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
6021                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
6022                         ret = flow_dv_validate_action_modify_tcp_ack
6023                                                                 (action_flags,
6024                                                                  actions,
6025                                                                  item_flags,
6026                                                                  error);
6027                         if (ret < 0)
6028                                 return ret;
6029                         /* Count all modify-header actions as one action. */
6030                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6031                                 ++actions_n;
6032                         action_flags |= actions->type ==
6033                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
6034                                                 MLX5_FLOW_ACTION_INC_TCP_ACK :
6035                                                 MLX5_FLOW_ACTION_DEC_TCP_ACK;
6036                         rw_act_num += MLX5_ACT_NUM_MDF_TCPACK;
6037                         break;
6038                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
6039                         break;
6040                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
6041                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
6042                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
6043                         break;
6044                 case RTE_FLOW_ACTION_TYPE_METER:
6045                         ret = mlx5_flow_validate_action_meter(dev,
6046                                                               action_flags,
6047                                                               actions, attr,
6048                                                               error);
6049                         if (ret < 0)
6050                                 return ret;
6051                         action_flags |= MLX5_FLOW_ACTION_METER;
6052                         ++actions_n;
6053                         /* Meter action will add one more TAG action. */
6054                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
6055                         break;
6056                 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
6057                         if (!attr->transfer && !attr->group)
6058                                 return rte_flow_error_set(error, ENOTSUP,
6059                                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6060                                                                            NULL,
6061                           "Shared ASO age action is not supported for group 0");
6062                         action_flags |= MLX5_FLOW_ACTION_AGE;
6063                         ++actions_n;
6064                         break;
6065                 case RTE_FLOW_ACTION_TYPE_AGE:
6066                         ret = flow_dv_validate_action_age(action_flags,
6067                                                           actions, dev,
6068                                                           error);
6069                         if (ret < 0)
6070                                 return ret;
6071                         action_flags |= MLX5_FLOW_ACTION_AGE;
6072                         ++actions_n;
6073                         break;
6074                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
6075                         ret = flow_dv_validate_action_modify_ipv4_dscp
6076                                                          (action_flags,
6077                                                           actions,
6078                                                           item_flags,
6079                                                           error);
6080                         if (ret < 0)
6081                                 return ret;
6082                         /* Count all modify-header actions as one action. */
6083                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6084                                 ++actions_n;
6085                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
6086                         rw_act_num += MLX5_ACT_NUM_SET_DSCP;
6087                         break;
6088                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
6089                         ret = flow_dv_validate_action_modify_ipv6_dscp
6090                                                                 (action_flags,
6091                                                                  actions,
6092                                                                  item_flags,
6093                                                                  error);
6094                         if (ret < 0)
6095                                 return ret;
6096                         /* Count all modify-header actions as one action. */
6097                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6098                                 ++actions_n;
6099                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
6100                         rw_act_num += MLX5_ACT_NUM_SET_DSCP;
6101                         break;
6102                 case RTE_FLOW_ACTION_TYPE_SAMPLE:
6103                         ret = flow_dv_validate_action_sample(action_flags,
6104                                                              actions, dev,
6105                                                              attr, item_flags,
6106                                                              error);
6107                         if (ret < 0)
6108                                 return ret;
6109                         action_flags |= MLX5_FLOW_ACTION_SAMPLE;
6110                         ++actions_n;
6111                         break;
6112                 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
6113                         if (actions[0].type != (typeof(actions[0].type))
6114                                 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET)
6115                                 return rte_flow_error_set
6116                                                 (error, EINVAL,
6117                                                 RTE_FLOW_ERROR_TYPE_ACTION,
6118                                                 NULL, "MLX5 private action "
6119                                                 "must be the first");
6120
6121                         action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
6122                         break;
6123                 default:
6124                         return rte_flow_error_set(error, ENOTSUP,
6125                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6126                                                   actions,
6127                                                   "action not supported");
6128                 }
6129         }
6130         /*
6131          * Validate actions in flow rules
6132          * - Explicit decap action is prohibited by the tunnel offload API.
6133          * - Drop action in tunnel steer rule is prohibited by the API.
6134          * - Application cannot use MARK action because it's value can mask
6135          *   tunnel default miss nitification.
6136          * - JUMP in tunnel match rule has no support in current PMD
6137          *   implementation.
6138          * - TAG & META are reserved for future uses.
6139          */
6140         if (action_flags & MLX5_FLOW_ACTION_TUNNEL_SET) {
6141                 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_DECAP    |
6142                                             MLX5_FLOW_ACTION_MARK     |
6143                                             MLX5_FLOW_ACTION_SET_TAG  |
6144                                             MLX5_FLOW_ACTION_SET_META |
6145                                             MLX5_FLOW_ACTION_DROP;
6146
6147                 if (action_flags & bad_actions_mask)
6148                         return rte_flow_error_set
6149                                         (error, EINVAL,
6150                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6151                                         "Invalid RTE action in tunnel "
6152                                         "set decap rule");
6153                 if (!(action_flags & MLX5_FLOW_ACTION_JUMP))
6154                         return rte_flow_error_set
6155                                         (error, EINVAL,
6156                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6157                                         "tunnel set decap rule must terminate "
6158                                         "with JUMP");
6159                 if (!attr->ingress)
6160                         return rte_flow_error_set
6161                                         (error, EINVAL,
6162                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6163                                         "tunnel flows for ingress traffic only");
6164         }
6165         if (action_flags & MLX5_FLOW_ACTION_TUNNEL_MATCH) {
6166                 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_JUMP    |
6167                                             MLX5_FLOW_ACTION_MARK    |
6168                                             MLX5_FLOW_ACTION_SET_TAG |
6169                                             MLX5_FLOW_ACTION_SET_META;
6170
6171                 if (action_flags & bad_actions_mask)
6172                         return rte_flow_error_set
6173                                         (error, EINVAL,
6174                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6175                                         "Invalid RTE action in tunnel "
6176                                         "set match rule");
6177         }
6178         /*
6179          * Validate the drop action mutual exclusion with other actions.
6180          * Drop action is mutually-exclusive with any other action, except for
6181          * Count action.
6182          */
6183         if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
6184             (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
6185                 return rte_flow_error_set(error, EINVAL,
6186                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6187                                           "Drop action is mutually-exclusive "
6188                                           "with any other action, except for "
6189                                           "Count action");
6190         /* Eswitch has few restrictions on using items and actions */
6191         if (attr->transfer) {
6192                 if (!mlx5_flow_ext_mreg_supported(dev) &&
6193                     action_flags & MLX5_FLOW_ACTION_FLAG)
6194                         return rte_flow_error_set(error, ENOTSUP,
6195                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6196                                                   NULL,
6197                                                   "unsupported action FLAG");
6198                 if (!mlx5_flow_ext_mreg_supported(dev) &&
6199                     action_flags & MLX5_FLOW_ACTION_MARK)
6200                         return rte_flow_error_set(error, ENOTSUP,
6201                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6202                                                   NULL,
6203                                                   "unsupported action MARK");
6204                 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
6205                         return rte_flow_error_set(error, ENOTSUP,
6206                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6207                                                   NULL,
6208                                                   "unsupported action QUEUE");
6209                 if (action_flags & MLX5_FLOW_ACTION_RSS)
6210                         return rte_flow_error_set(error, ENOTSUP,
6211                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6212                                                   NULL,
6213                                                   "unsupported action RSS");
6214                 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
6215                         return rte_flow_error_set(error, EINVAL,
6216                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6217                                                   actions,
6218                                                   "no fate action is found");
6219         } else {
6220                 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
6221                         return rte_flow_error_set(error, EINVAL,
6222                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6223                                                   actions,
6224                                                   "no fate action is found");
6225         }
6226         /*
6227          * Continue validation for Xcap and VLAN actions.
6228          * If hairpin is working in explicit TX rule mode, there is no actions
6229          * splitting and the validation of hairpin ingress flow should be the
6230          * same as other standard flows.
6231          */
6232         if ((action_flags & (MLX5_FLOW_XCAP_ACTIONS |
6233                              MLX5_FLOW_VLAN_ACTIONS)) &&
6234             (queue_index == 0xFFFF ||
6235              mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN ||
6236              ((conf = mlx5_rxq_get_hairpin_conf(dev, queue_index)) != NULL &&
6237              conf->tx_explicit != 0))) {
6238                 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
6239                     MLX5_FLOW_XCAP_ACTIONS)
6240                         return rte_flow_error_set(error, ENOTSUP,
6241                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6242                                                   NULL, "encap and decap "
6243                                                   "combination aren't supported");
6244                 if (!attr->transfer && attr->ingress) {
6245                         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
6246                                 return rte_flow_error_set
6247                                                 (error, ENOTSUP,
6248                                                  RTE_FLOW_ERROR_TYPE_ACTION,
6249                                                  NULL, "encap is not supported"
6250                                                  " for ingress traffic");
6251                         else if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
6252                                 return rte_flow_error_set
6253                                                 (error, ENOTSUP,
6254                                                  RTE_FLOW_ERROR_TYPE_ACTION,
6255                                                  NULL, "push VLAN action not "
6256                                                  "supported for ingress");
6257                         else if ((action_flags & MLX5_FLOW_VLAN_ACTIONS) ==
6258                                         MLX5_FLOW_VLAN_ACTIONS)
6259                                 return rte_flow_error_set
6260                                                 (error, ENOTSUP,
6261                                                  RTE_FLOW_ERROR_TYPE_ACTION,
6262                                                  NULL, "no support for "
6263                                                  "multiple VLAN actions");
6264                 }
6265         }
6266         /*
6267          * Hairpin flow will add one more TAG action in TX implicit mode.
6268          * In TX explicit mode, there will be no hairpin flow ID.
6269          */
6270         if (hairpin > 0)
6271                 rw_act_num += MLX5_ACT_NUM_SET_TAG;
6272         /* extra metadata enabled: one more TAG action will be add. */
6273         if (dev_conf->dv_flow_en &&
6274             dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
6275             mlx5_flow_ext_mreg_supported(dev))
6276                 rw_act_num += MLX5_ACT_NUM_SET_TAG;
6277         if ((uint32_t)rw_act_num >
6278                         flow_dv_modify_hdr_action_max(dev, is_root)) {
6279                 return rte_flow_error_set(error, ENOTSUP,
6280                                           RTE_FLOW_ERROR_TYPE_ACTION,
6281                                           NULL, "too many header modify"
6282                                           " actions to support");
6283         }
6284         return 0;
6285 }
6286
6287 /**
6288  * Internal preparation function. Allocates the DV flow size,
6289  * this size is constant.
6290  *
6291  * @param[in] dev
6292  *   Pointer to the rte_eth_dev structure.
6293  * @param[in] attr
6294  *   Pointer to the flow attributes.
6295  * @param[in] items
6296  *   Pointer to the list of items.
6297  * @param[in] actions
6298  *   Pointer to the list of actions.
6299  * @param[out] error
6300  *   Pointer to the error structure.
6301  *
6302  * @return
6303  *   Pointer to mlx5_flow object on success,
6304  *   otherwise NULL and rte_errno is set.
6305  */
6306 static struct mlx5_flow *
6307 flow_dv_prepare(struct rte_eth_dev *dev,
6308                 const struct rte_flow_attr *attr __rte_unused,
6309                 const struct rte_flow_item items[] __rte_unused,
6310                 const struct rte_flow_action actions[] __rte_unused,
6311                 struct rte_flow_error *error)
6312 {
6313         uint32_t handle_idx = 0;
6314         struct mlx5_flow *dev_flow;
6315         struct mlx5_flow_handle *dev_handle;
6316         struct mlx5_priv *priv = dev->data->dev_private;
6317         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
6318
6319         MLX5_ASSERT(wks);
6320         /* In case of corrupting the memory. */
6321         if (wks->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
6322                 rte_flow_error_set(error, ENOSPC,
6323                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6324                                    "not free temporary device flow");
6325                 return NULL;
6326         }
6327         dev_handle = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
6328                                    &handle_idx);
6329         if (!dev_handle) {
6330                 rte_flow_error_set(error, ENOMEM,
6331                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6332                                    "not enough memory to create flow handle");
6333                 return NULL;
6334         }
6335         MLX5_ASSERT(wks->flow_idx < RTE_DIM(wks->flows));
6336         dev_flow = &wks->flows[wks->flow_idx++];
6337         memset(dev_flow, 0, sizeof(*dev_flow));
6338         dev_flow->handle = dev_handle;
6339         dev_flow->handle_idx = handle_idx;
6340         /*
6341          * In some old rdma-core releases, before continuing, a check of the
6342          * length of matching parameter will be done at first. It needs to use
6343          * the length without misc4 param. If the flow has misc4 support, then
6344          * the length needs to be adjusted accordingly. Each param member is
6345          * aligned with a 64B boundary naturally.
6346          */
6347         dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param) -
6348                                   MLX5_ST_SZ_BYTES(fte_match_set_misc4);
6349         dev_flow->ingress = attr->ingress;
6350         dev_flow->dv.transfer = attr->transfer;
6351         return dev_flow;
6352 }
6353
6354 #ifdef RTE_LIBRTE_MLX5_DEBUG
6355 /**
6356  * Sanity check for match mask and value. Similar to check_valid_spec() in
6357  * kernel driver. If unmasked bit is present in value, it returns failure.
6358  *
6359  * @param match_mask
6360  *   pointer to match mask buffer.
6361  * @param match_value
6362  *   pointer to match value buffer.
6363  *
6364  * @return
6365  *   0 if valid, -EINVAL otherwise.
6366  */
6367 static int
6368 flow_dv_check_valid_spec(void *match_mask, void *match_value)
6369 {
6370         uint8_t *m = match_mask;
6371         uint8_t *v = match_value;
6372         unsigned int i;
6373
6374         for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
6375                 if (v[i] & ~m[i]) {
6376                         DRV_LOG(ERR,
6377                                 "match_value differs from match_criteria"
6378                                 " %p[%u] != %p[%u]",
6379                                 match_value, i, match_mask, i);
6380                         return -EINVAL;
6381                 }
6382         }
6383         return 0;
6384 }
6385 #endif
6386
6387 /**
6388  * Add match of ip_version.
6389  *
6390  * @param[in] group
6391  *   Flow group.
6392  * @param[in] headers_v
6393  *   Values header pointer.
6394  * @param[in] headers_m
6395  *   Masks header pointer.
6396  * @param[in] ip_version
6397  *   The IP version to set.
6398  */
6399 static inline void
6400 flow_dv_set_match_ip_version(uint32_t group,
6401                              void *headers_v,
6402                              void *headers_m,
6403                              uint8_t ip_version)
6404 {
6405         if (group == 0)
6406                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
6407         else
6408                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version,
6409                          ip_version);
6410         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, ip_version);
6411         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, 0);
6412         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype, 0);
6413 }
6414
6415 /**
6416  * Add Ethernet item to matcher and to the value.
6417  *
6418  * @param[in, out] matcher
6419  *   Flow matcher.
6420  * @param[in, out] key
6421  *   Flow matcher value.
6422  * @param[in] item
6423  *   Flow pattern to translate.
6424  * @param[in] inner
6425  *   Item is inner pattern.
6426  */
6427 static void
6428 flow_dv_translate_item_eth(void *matcher, void *key,
6429                            const struct rte_flow_item *item, int inner,
6430                            uint32_t group)
6431 {
6432         const struct rte_flow_item_eth *eth_m = item->mask;
6433         const struct rte_flow_item_eth *eth_v = item->spec;
6434         const struct rte_flow_item_eth nic_mask = {
6435                 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
6436                 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
6437                 .type = RTE_BE16(0xffff),
6438                 .has_vlan = 0,
6439         };
6440         void *hdrs_m;
6441         void *hdrs_v;
6442         char *l24_v;
6443         unsigned int i;
6444
6445         if (!eth_v)
6446                 return;
6447         if (!eth_m)
6448                 eth_m = &nic_mask;
6449         if (inner) {
6450                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
6451                                          inner_headers);
6452                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6453         } else {
6454                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
6455                                          outer_headers);
6456                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6457         }
6458         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, dmac_47_16),
6459                &eth_m->dst, sizeof(eth_m->dst));
6460         /* The value must be in the range of the mask. */
6461         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, dmac_47_16);
6462         for (i = 0; i < sizeof(eth_m->dst); ++i)
6463                 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
6464         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, smac_47_16),
6465                &eth_m->src, sizeof(eth_m->src));
6466         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, smac_47_16);
6467         /* The value must be in the range of the mask. */
6468         for (i = 0; i < sizeof(eth_m->dst); ++i)
6469                 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
6470         /*
6471          * HW supports match on one Ethertype, the Ethertype following the last
6472          * VLAN tag of the packet (see PRM).
6473          * Set match on ethertype only if ETH header is not followed by VLAN.
6474          * HW is optimized for IPv4/IPv6. In such cases, avoid setting
6475          * ethertype, and use ip_version field instead.
6476          * eCPRI over Ether layer will use type value 0xAEFE.
6477          */
6478         if (eth_m->type == 0xFFFF) {
6479                 /* Set cvlan_tag mask for any single\multi\un-tagged case. */
6480                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
6481                 switch (eth_v->type) {
6482                 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
6483                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
6484                         return;
6485                 case RTE_BE16(RTE_ETHER_TYPE_QINQ):
6486                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
6487                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
6488                         return;
6489                 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
6490                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
6491                         return;
6492                 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
6493                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
6494                         return;
6495                 default:
6496                         break;
6497                 }
6498         }
6499         if (eth_m->has_vlan) {
6500                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
6501                 if (eth_v->has_vlan) {
6502                         /*
6503                          * Here, when also has_more_vlan field in VLAN item is
6504                          * not set, only single-tagged packets will be matched.
6505                          */
6506                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
6507                         return;
6508                 }
6509         }
6510         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
6511                  rte_be_to_cpu_16(eth_m->type));
6512         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, ethertype);
6513         *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
6514 }
6515
6516 /**
6517  * Add VLAN item to matcher and to the value.
6518  *
6519  * @param[in, out] dev_flow
6520  *   Flow descriptor.
6521  * @param[in, out] matcher
6522  *   Flow matcher.
6523  * @param[in, out] key
6524  *   Flow matcher value.
6525  * @param[in] item
6526  *   Flow pattern to translate.
6527  * @param[in] inner
6528  *   Item is inner pattern.
6529  */
6530 static void
6531 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
6532                             void *matcher, void *key,
6533                             const struct rte_flow_item *item,
6534                             int inner, uint32_t group)
6535 {
6536         const struct rte_flow_item_vlan *vlan_m = item->mask;
6537         const struct rte_flow_item_vlan *vlan_v = item->spec;
6538         void *hdrs_m;
6539         void *hdrs_v;
6540         uint16_t tci_m;
6541         uint16_t tci_v;
6542
6543         if (inner) {
6544                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
6545                                          inner_headers);
6546                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6547         } else {
6548                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
6549                                          outer_headers);
6550                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6551                 /*
6552                  * This is workaround, masks are not supported,
6553                  * and pre-validated.
6554                  */
6555                 if (vlan_v)
6556                         dev_flow->handle->vf_vlan.tag =
6557                                         rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
6558         }
6559         /*
6560          * When VLAN item exists in flow, mark packet as tagged,
6561          * even if TCI is not specified.
6562          */
6563         if (!MLX5_GET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag)) {
6564                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
6565                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
6566         }
6567         if (!vlan_v)
6568                 return;
6569         if (!vlan_m)
6570                 vlan_m = &rte_flow_item_vlan_mask;
6571         tci_m = rte_be_to_cpu_16(vlan_m->tci);
6572         tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
6573         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_vid, tci_m);
6574         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_vid, tci_v);
6575         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_cfi, tci_m >> 12);
6576         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_cfi, tci_v >> 12);
6577         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_prio, tci_m >> 13);
6578         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_prio, tci_v >> 13);
6579         /*
6580          * HW is optimized for IPv4/IPv6. In such cases, avoid setting
6581          * ethertype, and use ip_version field instead.
6582          */
6583         if (vlan_m->inner_type == 0xFFFF) {
6584                 switch (vlan_v->inner_type) {
6585                 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
6586                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
6587                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
6588                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
6589                         return;
6590                 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
6591                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
6592                         return;
6593                 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
6594                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
6595                         return;
6596                 default:
6597                         break;
6598                 }
6599         }
6600         if (vlan_m->has_more_vlan && vlan_v->has_more_vlan) {
6601                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
6602                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
6603                 /* Only one vlan_tag bit can be set. */
6604                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
6605                 return;
6606         }
6607         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
6608                  rte_be_to_cpu_16(vlan_m->inner_type));
6609         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, ethertype,
6610                  rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
6611 }
6612
6613 /**
6614  * Add IPV4 item to matcher and to the value.
6615  *
6616  * @param[in, out] matcher
6617  *   Flow matcher.
6618  * @param[in, out] key
6619  *   Flow matcher value.
6620  * @param[in] item
6621  *   Flow pattern to translate.
6622  * @param[in] inner
6623  *   Item is inner pattern.
6624  * @param[in] group
6625  *   The group to insert the rule.
6626  */
6627 static void
6628 flow_dv_translate_item_ipv4(void *matcher, void *key,
6629                             const struct rte_flow_item *item,
6630                             int inner, uint32_t group)
6631 {
6632         const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
6633         const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
6634         const struct rte_flow_item_ipv4 nic_mask = {
6635                 .hdr = {
6636                         .src_addr = RTE_BE32(0xffffffff),
6637                         .dst_addr = RTE_BE32(0xffffffff),
6638                         .type_of_service = 0xff,
6639                         .next_proto_id = 0xff,
6640                         .time_to_live = 0xff,
6641                 },
6642         };
6643         void *headers_m;
6644         void *headers_v;
6645         char *l24_m;
6646         char *l24_v;
6647         uint8_t tos;
6648
6649         if (inner) {
6650                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6651                                          inner_headers);
6652                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6653         } else {
6654                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6655                                          outer_headers);
6656                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6657         }
6658         flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
6659         if (!ipv4_v)
6660                 return;
6661         if (!ipv4_m)
6662                 ipv4_m = &nic_mask;
6663         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6664                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
6665         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6666                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
6667         *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
6668         *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
6669         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6670                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
6671         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6672                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
6673         *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
6674         *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
6675         tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
6676         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
6677                  ipv4_m->hdr.type_of_service);
6678         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
6679         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
6680                  ipv4_m->hdr.type_of_service >> 2);
6681         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
6682         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6683                  ipv4_m->hdr.next_proto_id);
6684         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6685                  ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
6686         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
6687                  ipv4_m->hdr.time_to_live);
6688         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
6689                  ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
6690         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
6691                  !!(ipv4_m->hdr.fragment_offset));
6692         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
6693                  !!(ipv4_v->hdr.fragment_offset & ipv4_m->hdr.fragment_offset));
6694 }
6695
6696 /**
6697  * Add IPV6 item to matcher and to the value.
6698  *
6699  * @param[in, out] matcher
6700  *   Flow matcher.
6701  * @param[in, out] key
6702  *   Flow matcher value.
6703  * @param[in] item
6704  *   Flow pattern to translate.
6705  * @param[in] inner
6706  *   Item is inner pattern.
6707  * @param[in] group
6708  *   The group to insert the rule.
6709  */
6710 static void
6711 flow_dv_translate_item_ipv6(void *matcher, void *key,
6712                             const struct rte_flow_item *item,
6713                             int inner, uint32_t group)
6714 {
6715         const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
6716         const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
6717         const struct rte_flow_item_ipv6 nic_mask = {
6718                 .hdr = {
6719                         .src_addr =
6720                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
6721                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
6722                         .dst_addr =
6723                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
6724                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
6725                         .vtc_flow = RTE_BE32(0xffffffff),
6726                         .proto = 0xff,
6727                         .hop_limits = 0xff,
6728                 },
6729         };
6730         void *headers_m;
6731         void *headers_v;
6732         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6733         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6734         char *l24_m;
6735         char *l24_v;
6736         uint32_t vtc_m;
6737         uint32_t vtc_v;
6738         int i;
6739         int size;
6740
6741         if (inner) {
6742                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6743                                          inner_headers);
6744                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6745         } else {
6746                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6747                                          outer_headers);
6748                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6749         }
6750         flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
6751         if (!ipv6_v)
6752                 return;
6753         if (!ipv6_m)
6754                 ipv6_m = &nic_mask;
6755         size = sizeof(ipv6_m->hdr.dst_addr);
6756         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6757                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
6758         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6759                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
6760         memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
6761         for (i = 0; i < size; ++i)
6762                 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
6763         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6764                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
6765         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6766                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
6767         memcpy(l24_m, ipv6_m->hdr.src_addr, size);
6768         for (i = 0; i < size; ++i)
6769                 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
6770         /* TOS. */
6771         vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
6772         vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
6773         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
6774         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
6775         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
6776         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
6777         /* Label. */
6778         if (inner) {
6779                 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
6780                          vtc_m);
6781                 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
6782                          vtc_v);
6783         } else {
6784                 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
6785                          vtc_m);
6786                 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
6787                          vtc_v);
6788         }
6789         /* Protocol. */
6790         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6791                  ipv6_m->hdr.proto);
6792         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6793                  ipv6_v->hdr.proto & ipv6_m->hdr.proto);
6794         /* Hop limit. */
6795         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
6796                  ipv6_m->hdr.hop_limits);
6797         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
6798                  ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
6799         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
6800                  !!(ipv6_m->has_frag_ext));
6801         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
6802                  !!(ipv6_v->has_frag_ext & ipv6_m->has_frag_ext));
6803 }
6804
6805 /**
6806  * Add IPV6 fragment extension item to matcher and to the value.
6807  *
6808  * @param[in, out] matcher
6809  *   Flow matcher.
6810  * @param[in, out] key
6811  *   Flow matcher value.
6812  * @param[in] item
6813  *   Flow pattern to translate.
6814  * @param[in] inner
6815  *   Item is inner pattern.
6816  */
6817 static void
6818 flow_dv_translate_item_ipv6_frag_ext(void *matcher, void *key,
6819                                      const struct rte_flow_item *item,
6820                                      int inner)
6821 {
6822         const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_m = item->mask;
6823         const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_v = item->spec;
6824         const struct rte_flow_item_ipv6_frag_ext nic_mask = {
6825                 .hdr = {
6826                         .next_header = 0xff,
6827                         .frag_data = RTE_BE16(0xffff),
6828                 },
6829         };
6830         void *headers_m;
6831         void *headers_v;
6832
6833         if (inner) {
6834                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6835                                          inner_headers);
6836                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6837         } else {
6838                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6839                                          outer_headers);
6840                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6841         }
6842         /* IPv6 fragment extension item exists, so packet is IP fragment. */
6843         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
6844         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 1);
6845         if (!ipv6_frag_ext_v)
6846                 return;
6847         if (!ipv6_frag_ext_m)
6848                 ipv6_frag_ext_m = &nic_mask;
6849         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6850                  ipv6_frag_ext_m->hdr.next_header);
6851         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6852                  ipv6_frag_ext_v->hdr.next_header &
6853                  ipv6_frag_ext_m->hdr.next_header);
6854 }
6855
6856 /**
6857  * Add TCP item to matcher and to the value.
6858  *
6859  * @param[in, out] matcher
6860  *   Flow matcher.
6861  * @param[in, out] key
6862  *   Flow matcher value.
6863  * @param[in] item
6864  *   Flow pattern to translate.
6865  * @param[in] inner
6866  *   Item is inner pattern.
6867  */
6868 static void
6869 flow_dv_translate_item_tcp(void *matcher, void *key,
6870                            const struct rte_flow_item *item,
6871                            int inner)
6872 {
6873         const struct rte_flow_item_tcp *tcp_m = item->mask;
6874         const struct rte_flow_item_tcp *tcp_v = item->spec;
6875         void *headers_m;
6876         void *headers_v;
6877
6878         if (inner) {
6879                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6880                                          inner_headers);
6881                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6882         } else {
6883                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6884                                          outer_headers);
6885                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6886         }
6887         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6888         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
6889         if (!tcp_v)
6890                 return;
6891         if (!tcp_m)
6892                 tcp_m = &rte_flow_item_tcp_mask;
6893         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
6894                  rte_be_to_cpu_16(tcp_m->hdr.src_port));
6895         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
6896                  rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
6897         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
6898                  rte_be_to_cpu_16(tcp_m->hdr.dst_port));
6899         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
6900                  rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
6901         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
6902                  tcp_m->hdr.tcp_flags);
6903         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
6904                  (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
6905 }
6906
6907 /**
6908  * Add UDP item to matcher and to the value.
6909  *
6910  * @param[in, out] matcher
6911  *   Flow matcher.
6912  * @param[in, out] key
6913  *   Flow matcher value.
6914  * @param[in] item
6915  *   Flow pattern to translate.
6916  * @param[in] inner
6917  *   Item is inner pattern.
6918  */
6919 static void
6920 flow_dv_translate_item_udp(void *matcher, void *key,
6921                            const struct rte_flow_item *item,
6922                            int inner)
6923 {
6924         const struct rte_flow_item_udp *udp_m = item->mask;
6925         const struct rte_flow_item_udp *udp_v = item->spec;
6926         void *headers_m;
6927         void *headers_v;
6928
6929         if (inner) {
6930                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6931                                          inner_headers);
6932                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6933         } else {
6934                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6935                                          outer_headers);
6936                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6937         }
6938         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6939         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
6940         if (!udp_v)
6941                 return;
6942         if (!udp_m)
6943                 udp_m = &rte_flow_item_udp_mask;
6944         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
6945                  rte_be_to_cpu_16(udp_m->hdr.src_port));
6946         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
6947                  rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
6948         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
6949                  rte_be_to_cpu_16(udp_m->hdr.dst_port));
6950         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
6951                  rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
6952 }
6953
6954 /**
6955  * Add GRE optional Key item to matcher and to the value.
6956  *
6957  * @param[in, out] matcher
6958  *   Flow matcher.
6959  * @param[in, out] key
6960  *   Flow matcher value.
6961  * @param[in] item
6962  *   Flow pattern to translate.
6963  * @param[in] inner
6964  *   Item is inner pattern.
6965  */
6966 static void
6967 flow_dv_translate_item_gre_key(void *matcher, void *key,
6968                                    const struct rte_flow_item *item)
6969 {
6970         const rte_be32_t *key_m = item->mask;
6971         const rte_be32_t *key_v = item->spec;
6972         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6973         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6974         rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
6975
6976         /* GRE K bit must be on and should already be validated */
6977         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
6978         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
6979         if (!key_v)
6980                 return;
6981         if (!key_m)
6982                 key_m = &gre_key_default_mask;
6983         MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
6984                  rte_be_to_cpu_32(*key_m) >> 8);
6985         MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
6986                  rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
6987         MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
6988                  rte_be_to_cpu_32(*key_m) & 0xFF);
6989         MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
6990                  rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
6991 }
6992
6993 /**
6994  * Add GRE item to matcher and to the value.
6995  *
6996  * @param[in, out] matcher
6997  *   Flow matcher.
6998  * @param[in, out] key
6999  *   Flow matcher value.
7000  * @param[in] item
7001  *   Flow pattern to translate.
7002  * @param[in] inner
7003  *   Item is inner pattern.
7004  */
7005 static void
7006 flow_dv_translate_item_gre(void *matcher, void *key,
7007                            const struct rte_flow_item *item,
7008                            int inner)
7009 {
7010         const struct rte_flow_item_gre *gre_m = item->mask;
7011         const struct rte_flow_item_gre *gre_v = item->spec;
7012         void *headers_m;
7013         void *headers_v;
7014         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7015         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7016         struct {
7017                 union {
7018                         __extension__
7019                         struct {
7020                                 uint16_t version:3;
7021                                 uint16_t rsvd0:9;
7022                                 uint16_t s_present:1;
7023                                 uint16_t k_present:1;
7024                                 uint16_t rsvd_bit1:1;
7025                                 uint16_t c_present:1;
7026                         };
7027                         uint16_t value;
7028                 };
7029         } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
7030
7031         if (inner) {
7032                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7033                                          inner_headers);
7034                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7035         } else {
7036                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7037                                          outer_headers);
7038                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7039         }
7040         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7041         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
7042         if (!gre_v)
7043                 return;
7044         if (!gre_m)
7045                 gre_m = &rte_flow_item_gre_mask;
7046         MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
7047                  rte_be_to_cpu_16(gre_m->protocol));
7048         MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
7049                  rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
7050         gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
7051         gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
7052         MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
7053                  gre_crks_rsvd0_ver_m.c_present);
7054         MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
7055                  gre_crks_rsvd0_ver_v.c_present &
7056                  gre_crks_rsvd0_ver_m.c_present);
7057         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
7058                  gre_crks_rsvd0_ver_m.k_present);
7059         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
7060                  gre_crks_rsvd0_ver_v.k_present &
7061                  gre_crks_rsvd0_ver_m.k_present);
7062         MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
7063                  gre_crks_rsvd0_ver_m.s_present);
7064         MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
7065                  gre_crks_rsvd0_ver_v.s_present &
7066                  gre_crks_rsvd0_ver_m.s_present);
7067 }
7068
7069 /**
7070  * Add NVGRE item to matcher and to the value.
7071  *
7072  * @param[in, out] matcher
7073  *   Flow matcher.
7074  * @param[in, out] key
7075  *   Flow matcher value.
7076  * @param[in] item
7077  *   Flow pattern to translate.
7078  * @param[in] inner
7079  *   Item is inner pattern.
7080  */
7081 static void
7082 flow_dv_translate_item_nvgre(void *matcher, void *key,
7083                              const struct rte_flow_item *item,
7084                              int inner)
7085 {
7086         const struct rte_flow_item_nvgre *nvgre_m = item->mask;
7087         const struct rte_flow_item_nvgre *nvgre_v = item->spec;
7088         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7089         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7090         const char *tni_flow_id_m;
7091         const char *tni_flow_id_v;
7092         char *gre_key_m;
7093         char *gre_key_v;
7094         int size;
7095         int i;
7096
7097         /* For NVGRE, GRE header fields must be set with defined values. */
7098         const struct rte_flow_item_gre gre_spec = {
7099                 .c_rsvd0_ver = RTE_BE16(0x2000),
7100                 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
7101         };
7102         const struct rte_flow_item_gre gre_mask = {
7103                 .c_rsvd0_ver = RTE_BE16(0xB000),
7104                 .protocol = RTE_BE16(UINT16_MAX),
7105         };
7106         const struct rte_flow_item gre_item = {
7107                 .spec = &gre_spec,
7108                 .mask = &gre_mask,
7109                 .last = NULL,
7110         };
7111         flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
7112         if (!nvgre_v)
7113                 return;
7114         if (!nvgre_m)
7115                 nvgre_m = &rte_flow_item_nvgre_mask;
7116         tni_flow_id_m = (const char *)nvgre_m->tni;
7117         tni_flow_id_v = (const char *)nvgre_v->tni;
7118         size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
7119         gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
7120         gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
7121         memcpy(gre_key_m, tni_flow_id_m, size);
7122         for (i = 0; i < size; ++i)
7123                 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
7124 }
7125
7126 /**
7127  * Add VXLAN item to matcher and to the value.
7128  *
7129  * @param[in, out] matcher
7130  *   Flow matcher.
7131  * @param[in, out] key
7132  *   Flow matcher value.
7133  * @param[in] item
7134  *   Flow pattern to translate.
7135  * @param[in] inner
7136  *   Item is inner pattern.
7137  */
7138 static void
7139 flow_dv_translate_item_vxlan(void *matcher, void *key,
7140                              const struct rte_flow_item *item,
7141                              int inner)
7142 {
7143         const struct rte_flow_item_vxlan *vxlan_m = item->mask;
7144         const struct rte_flow_item_vxlan *vxlan_v = item->spec;
7145         void *headers_m;
7146         void *headers_v;
7147         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7148         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7149         char *vni_m;
7150         char *vni_v;
7151         uint16_t dport;
7152         int size;
7153         int i;
7154
7155         if (inner) {
7156                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7157                                          inner_headers);
7158                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7159         } else {
7160                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7161                                          outer_headers);
7162                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7163         }
7164         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
7165                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
7166         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7167                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7168                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7169         }
7170         if (!vxlan_v)
7171                 return;
7172         if (!vxlan_m)
7173                 vxlan_m = &rte_flow_item_vxlan_mask;
7174         size = sizeof(vxlan_m->vni);
7175         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
7176         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
7177         memcpy(vni_m, vxlan_m->vni, size);
7178         for (i = 0; i < size; ++i)
7179                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
7180 }
7181
7182 /**
7183  * Add VXLAN-GPE item to matcher and to the value.
7184  *
7185  * @param[in, out] matcher
7186  *   Flow matcher.
7187  * @param[in, out] key
7188  *   Flow matcher value.
7189  * @param[in] item
7190  *   Flow pattern to translate.
7191  * @param[in] inner
7192  *   Item is inner pattern.
7193  */
7194
7195 static void
7196 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
7197                                  const struct rte_flow_item *item, int inner)
7198 {
7199         const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
7200         const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
7201         void *headers_m;
7202         void *headers_v;
7203         void *misc_m =
7204                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
7205         void *misc_v =
7206                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7207         char *vni_m;
7208         char *vni_v;
7209         uint16_t dport;
7210         int size;
7211         int i;
7212         uint8_t flags_m = 0xff;
7213         uint8_t flags_v = 0xc;
7214
7215         if (inner) {
7216                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7217                                          inner_headers);
7218                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7219         } else {
7220                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7221                                          outer_headers);
7222                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7223         }
7224         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
7225                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
7226         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7227                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7228                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7229         }
7230         if (!vxlan_v)
7231                 return;
7232         if (!vxlan_m)
7233                 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
7234         size = sizeof(vxlan_m->vni);
7235         vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
7236         vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
7237         memcpy(vni_m, vxlan_m->vni, size);
7238         for (i = 0; i < size; ++i)
7239                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
7240         if (vxlan_m->flags) {
7241                 flags_m = vxlan_m->flags;
7242                 flags_v = vxlan_v->flags;
7243         }
7244         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
7245         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
7246         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
7247                  vxlan_m->protocol);
7248         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
7249                  vxlan_v->protocol);
7250 }
7251
7252 /**
7253  * Add Geneve item to matcher and to the value.
7254  *
7255  * @param[in, out] matcher
7256  *   Flow matcher.
7257  * @param[in, out] key
7258  *   Flow matcher value.
7259  * @param[in] item
7260  *   Flow pattern to translate.
7261  * @param[in] inner
7262  *   Item is inner pattern.
7263  */
7264
7265 static void
7266 flow_dv_translate_item_geneve(void *matcher, void *key,
7267                               const struct rte_flow_item *item, int inner)
7268 {
7269         const struct rte_flow_item_geneve *geneve_m = item->mask;
7270         const struct rte_flow_item_geneve *geneve_v = item->spec;
7271         void *headers_m;
7272         void *headers_v;
7273         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7274         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7275         uint16_t dport;
7276         uint16_t gbhdr_m;
7277         uint16_t gbhdr_v;
7278         char *vni_m;
7279         char *vni_v;
7280         size_t size, i;
7281
7282         if (inner) {
7283                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7284                                          inner_headers);
7285                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7286         } else {
7287                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7288                                          outer_headers);
7289                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7290         }
7291         dport = MLX5_UDP_PORT_GENEVE;
7292         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7293                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7294                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7295         }
7296         if (!geneve_v)
7297                 return;
7298         if (!geneve_m)
7299                 geneve_m = &rte_flow_item_geneve_mask;
7300         size = sizeof(geneve_m->vni);
7301         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
7302         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
7303         memcpy(vni_m, geneve_m->vni, size);
7304         for (i = 0; i < size; ++i)
7305                 vni_v[i] = vni_m[i] & geneve_v->vni[i];
7306         MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
7307                  rte_be_to_cpu_16(geneve_m->protocol));
7308         MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
7309                  rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
7310         gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
7311         gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
7312         MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
7313                  MLX5_GENEVE_OAMF_VAL(gbhdr_m));
7314         MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
7315                  MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
7316         MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
7317                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
7318         MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
7319                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
7320                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
7321 }
7322
7323 /**
7324  * Create Geneve TLV option resource.
7325  *
7326  * @param dev[in, out]
7327  *   Pointer to rte_eth_dev structure.
7328  * @param[in, out] tag_be24
7329  *   Tag value in big endian then R-shift 8.
7330  * @parm[in, out] dev_flow
7331  *   Pointer to the dev_flow.
7332  * @param[out] error
7333  *   pointer to error structure.
7334  *
7335  * @return
7336  *   0 on success otherwise -errno and errno is set.
7337  */
7338
7339 int
7340 flow_dev_geneve_tlv_option_resource_register(struct rte_eth_dev *dev,
7341                                              const struct rte_flow_item *item,
7342                                              struct rte_flow_error *error)
7343 {
7344         struct mlx5_priv *priv = dev->data->dev_private;
7345         struct mlx5_dev_ctx_shared *sh = priv->sh;
7346         struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
7347                         sh->geneve_tlv_option_resource;
7348         struct mlx5_devx_obj *obj;
7349         const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
7350         int ret = 0;
7351
7352         if (!geneve_opt_v)
7353                 return -1;
7354         rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
7355         if (geneve_opt_resource != NULL) {
7356                 if (geneve_opt_resource->option_class ==
7357                         geneve_opt_v->option_class &&
7358                         geneve_opt_resource->option_type ==
7359                         geneve_opt_v->option_type &&
7360                         geneve_opt_resource->length ==
7361                         geneve_opt_v->option_len) {
7362                         /* We already have GENVE TLV option obj allocated. */
7363                         __atomic_fetch_add(&geneve_opt_resource->refcnt, 1,
7364                                            __ATOMIC_RELAXED);
7365                 } else {
7366                         ret = rte_flow_error_set(error, ENOMEM,
7367                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7368                                 "Only one GENEVE TLV option supported");
7369                         goto exit;
7370                 }
7371         } else {
7372                 /* Create a GENEVE TLV object and resource. */
7373                 obj = mlx5_devx_cmd_create_geneve_tlv_option(sh->ctx,
7374                                 geneve_opt_v->option_class,
7375                                 geneve_opt_v->option_type,
7376                                 geneve_opt_v->option_len);
7377                 if (!obj) {
7378                         ret = rte_flow_error_set(error, ENODATA,
7379                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7380                                 "Failed to create GENEVE TLV Devx object");
7381                         goto exit;
7382                 }
7383                 sh->geneve_tlv_option_resource =
7384                                 mlx5_malloc(MLX5_MEM_ZERO,
7385                                                 sizeof(*geneve_opt_resource),
7386                                                 0, SOCKET_ID_ANY);
7387                 if (!sh->geneve_tlv_option_resource) {
7388                         claim_zero(mlx5_devx_cmd_destroy(obj));
7389                         ret = rte_flow_error_set(error, ENOMEM,
7390                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7391                                 "GENEVE TLV object memory allocation failed");
7392                         goto exit;
7393                 }
7394                 geneve_opt_resource = sh->geneve_tlv_option_resource;
7395                 geneve_opt_resource->obj = obj;
7396                 geneve_opt_resource->option_class = geneve_opt_v->option_class;
7397                 geneve_opt_resource->option_type = geneve_opt_v->option_type;
7398                 geneve_opt_resource->length = geneve_opt_v->option_len;
7399                 __atomic_store_n(&geneve_opt_resource->refcnt, 1,
7400                                 __ATOMIC_RELAXED);
7401         }
7402 exit:
7403         rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
7404         return ret;
7405 }
7406
7407 /**
7408  * Add MPLS item to matcher and to the value.
7409  *
7410  * @param[in, out] matcher
7411  *   Flow matcher.
7412  * @param[in, out] key
7413  *   Flow matcher value.
7414  * @param[in] item
7415  *   Flow pattern to translate.
7416  * @param[in] prev_layer
7417  *   The protocol layer indicated in previous item.
7418  * @param[in] inner
7419  *   Item is inner pattern.
7420  */
7421 static void
7422 flow_dv_translate_item_mpls(void *matcher, void *key,
7423                             const struct rte_flow_item *item,
7424                             uint64_t prev_layer,
7425                             int inner)
7426 {
7427         const uint32_t *in_mpls_m = item->mask;
7428         const uint32_t *in_mpls_v = item->spec;
7429         uint32_t *out_mpls_m = 0;
7430         uint32_t *out_mpls_v = 0;
7431         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7432         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7433         void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
7434                                      misc_parameters_2);
7435         void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
7436         void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
7437         void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7438
7439         switch (prev_layer) {
7440         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
7441                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
7442                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
7443                          MLX5_UDP_PORT_MPLS);
7444                 break;
7445         case MLX5_FLOW_LAYER_GRE:
7446                 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
7447                 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
7448                          RTE_ETHER_TYPE_MPLS);
7449                 break;
7450         default:
7451                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7452                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
7453                          IPPROTO_MPLS);
7454                 break;
7455         }
7456         if (!in_mpls_v)
7457                 return;
7458         if (!in_mpls_m)
7459                 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
7460         switch (prev_layer) {
7461         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
7462                 out_mpls_m =
7463                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
7464                                                  outer_first_mpls_over_udp);
7465                 out_mpls_v =
7466                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
7467                                                  outer_first_mpls_over_udp);
7468                 break;
7469         case MLX5_FLOW_LAYER_GRE:
7470                 out_mpls_m =
7471                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
7472                                                  outer_first_mpls_over_gre);
7473                 out_mpls_v =
7474                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
7475                                                  outer_first_mpls_over_gre);
7476                 break;
7477         default:
7478                 /* Inner MPLS not over GRE is not supported. */
7479                 if (!inner) {
7480                         out_mpls_m =
7481                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
7482                                                          misc2_m,
7483                                                          outer_first_mpls);
7484                         out_mpls_v =
7485                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
7486                                                          misc2_v,
7487                                                          outer_first_mpls);
7488                 }
7489                 break;
7490         }
7491         if (out_mpls_m && out_mpls_v) {
7492                 *out_mpls_m = *in_mpls_m;
7493                 *out_mpls_v = *in_mpls_v & *in_mpls_m;
7494         }
7495 }
7496
7497 /**
7498  * Add metadata register item to matcher
7499  *
7500  * @param[in, out] matcher
7501  *   Flow matcher.
7502  * @param[in, out] key
7503  *   Flow matcher value.
7504  * @param[in] reg_type
7505  *   Type of device metadata register
7506  * @param[in] value
7507  *   Register value
7508  * @param[in] mask
7509  *   Register mask
7510  */
7511 static void
7512 flow_dv_match_meta_reg(void *matcher, void *key,
7513                        enum modify_reg reg_type,
7514                        uint32_t data, uint32_t mask)
7515 {
7516         void *misc2_m =
7517                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
7518         void *misc2_v =
7519                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
7520         uint32_t temp;
7521
7522         data &= mask;
7523         switch (reg_type) {
7524         case REG_A:
7525                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
7526                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
7527                 break;
7528         case REG_B:
7529                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
7530                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
7531                 break;
7532         case REG_C_0:
7533                 /*
7534                  * The metadata register C0 field might be divided into
7535                  * source vport index and META item value, we should set
7536                  * this field according to specified mask, not as whole one.
7537                  */
7538                 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
7539                 temp |= mask;
7540                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
7541                 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
7542                 temp &= ~mask;
7543                 temp |= data;
7544                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
7545                 break;
7546         case REG_C_1:
7547                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
7548                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
7549                 break;
7550         case REG_C_2:
7551                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
7552                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
7553                 break;
7554         case REG_C_3:
7555                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
7556                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
7557                 break;
7558         case REG_C_4:
7559                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
7560                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
7561                 break;
7562         case REG_C_5:
7563                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
7564                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
7565                 break;
7566         case REG_C_6:
7567                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
7568                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
7569                 break;
7570         case REG_C_7:
7571                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
7572                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
7573                 break;
7574         default:
7575                 MLX5_ASSERT(false);
7576                 break;
7577         }
7578 }
7579
7580 /**
7581  * Add MARK item to matcher
7582  *
7583  * @param[in] dev
7584  *   The device to configure through.
7585  * @param[in, out] matcher
7586  *   Flow matcher.
7587  * @param[in, out] key
7588  *   Flow matcher value.
7589  * @param[in] item
7590  *   Flow pattern to translate.
7591  */
7592 static void
7593 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
7594                             void *matcher, void *key,
7595                             const struct rte_flow_item *item)
7596 {
7597         struct mlx5_priv *priv = dev->data->dev_private;
7598         const struct rte_flow_item_mark *mark;
7599         uint32_t value;
7600         uint32_t mask;
7601
7602         mark = item->mask ? (const void *)item->mask :
7603                             &rte_flow_item_mark_mask;
7604         mask = mark->id & priv->sh->dv_mark_mask;
7605         mark = (const void *)item->spec;
7606         MLX5_ASSERT(mark);
7607         value = mark->id & priv->sh->dv_mark_mask & mask;
7608         if (mask) {
7609                 enum modify_reg reg;
7610
7611                 /* Get the metadata register index for the mark. */
7612                 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
7613                 MLX5_ASSERT(reg > 0);
7614                 if (reg == REG_C_0) {
7615                         struct mlx5_priv *priv = dev->data->dev_private;
7616                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
7617                         uint32_t shl_c0 = rte_bsf32(msk_c0);
7618
7619                         mask &= msk_c0;
7620                         mask <<= shl_c0;
7621                         value <<= shl_c0;
7622                 }
7623                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
7624         }
7625 }
7626
7627 /**
7628  * Add META item to matcher
7629  *
7630  * @param[in] dev
7631  *   The devich to configure through.
7632  * @param[in, out] matcher
7633  *   Flow matcher.
7634  * @param[in, out] key
7635  *   Flow matcher value.
7636  * @param[in] attr
7637  *   Attributes of flow that includes this item.
7638  * @param[in] item
7639  *   Flow pattern to translate.
7640  */
7641 static void
7642 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
7643                             void *matcher, void *key,
7644                             const struct rte_flow_attr *attr,
7645                             const struct rte_flow_item *item)
7646 {
7647         const struct rte_flow_item_meta *meta_m;
7648         const struct rte_flow_item_meta *meta_v;
7649
7650         meta_m = (const void *)item->mask;
7651         if (!meta_m)
7652                 meta_m = &rte_flow_item_meta_mask;
7653         meta_v = (const void *)item->spec;
7654         if (meta_v) {
7655                 int reg;
7656                 uint32_t value = meta_v->data;
7657                 uint32_t mask = meta_m->data;
7658
7659                 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
7660                 if (reg < 0)
7661                         return;
7662                 MLX5_ASSERT(reg != REG_NON);
7663                 /*
7664                  * In datapath code there is no endianness
7665                  * coversions for perfromance reasons, all
7666                  * pattern conversions are done in rte_flow.
7667                  */
7668                 value = rte_cpu_to_be_32(value);
7669                 mask = rte_cpu_to_be_32(mask);
7670                 if (reg == REG_C_0) {
7671                         struct mlx5_priv *priv = dev->data->dev_private;
7672                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
7673                         uint32_t shl_c0 = rte_bsf32(msk_c0);
7674 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
7675                         uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
7676
7677                         value >>= shr_c0;
7678                         mask >>= shr_c0;
7679 #endif
7680                         value <<= shl_c0;
7681                         mask <<= shl_c0;
7682                         MLX5_ASSERT(msk_c0);
7683                         MLX5_ASSERT(!(~msk_c0 & mask));
7684                 }
7685                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
7686         }
7687 }
7688
7689 /**
7690  * Add vport metadata Reg C0 item to matcher
7691  *
7692  * @param[in, out] matcher
7693  *   Flow matcher.
7694  * @param[in, out] key
7695  *   Flow matcher value.
7696  * @param[in] reg
7697  *   Flow pattern to translate.
7698  */
7699 static void
7700 flow_dv_translate_item_meta_vport(void *matcher, void *key,
7701                                   uint32_t value, uint32_t mask)
7702 {
7703         flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
7704 }
7705
7706 /**
7707  * Add tag item to matcher
7708  *
7709  * @param[in] dev
7710  *   The devich to configure through.
7711  * @param[in, out] matcher
7712  *   Flow matcher.
7713  * @param[in, out] key
7714  *   Flow matcher value.
7715  * @param[in] item
7716  *   Flow pattern to translate.
7717  */
7718 static void
7719 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
7720                                 void *matcher, void *key,
7721                                 const struct rte_flow_item *item)
7722 {
7723         const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
7724         const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
7725         uint32_t mask, value;
7726
7727         MLX5_ASSERT(tag_v);
7728         value = tag_v->data;
7729         mask = tag_m ? tag_m->data : UINT32_MAX;
7730         if (tag_v->id == REG_C_0) {
7731                 struct mlx5_priv *priv = dev->data->dev_private;
7732                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
7733                 uint32_t shl_c0 = rte_bsf32(msk_c0);
7734
7735                 mask &= msk_c0;
7736                 mask <<= shl_c0;
7737                 value <<= shl_c0;
7738         }
7739         flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
7740 }
7741
7742 /**
7743  * Add TAG item to matcher
7744  *
7745  * @param[in] dev
7746  *   The devich to configure through.
7747  * @param[in, out] matcher
7748  *   Flow matcher.
7749  * @param[in, out] key
7750  *   Flow matcher value.
7751  * @param[in] item
7752  *   Flow pattern to translate.
7753  */
7754 static void
7755 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
7756                            void *matcher, void *key,
7757                            const struct rte_flow_item *item)
7758 {
7759         const struct rte_flow_item_tag *tag_v = item->spec;
7760         const struct rte_flow_item_tag *tag_m = item->mask;
7761         enum modify_reg reg;
7762
7763         MLX5_ASSERT(tag_v);
7764         tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
7765         /* Get the metadata register index for the tag. */
7766         reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
7767         MLX5_ASSERT(reg > 0);
7768         flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
7769 }
7770
7771 /**
7772  * Add source vport match to the specified matcher.
7773  *
7774  * @param[in, out] matcher
7775  *   Flow matcher.
7776  * @param[in, out] key
7777  *   Flow matcher value.
7778  * @param[in] port
7779  *   Source vport value to match
7780  * @param[in] mask
7781  *   Mask
7782  */
7783 static void
7784 flow_dv_translate_item_source_vport(void *matcher, void *key,
7785                                     int16_t port, uint16_t mask)
7786 {
7787         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7788         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7789
7790         MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
7791         MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
7792 }
7793
7794 /**
7795  * Translate port-id item to eswitch match on  port-id.
7796  *
7797  * @param[in] dev
7798  *   The devich to configure through.
7799  * @param[in, out] matcher
7800  *   Flow matcher.
7801  * @param[in, out] key
7802  *   Flow matcher value.
7803  * @param[in] item
7804  *   Flow pattern to translate.
7805  * @param[in]
7806  *   Flow attributes.
7807  *
7808  * @return
7809  *   0 on success, a negative errno value otherwise.
7810  */
7811 static int
7812 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
7813                                void *key, const struct rte_flow_item *item,
7814                                const struct rte_flow_attr *attr)
7815 {
7816         const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
7817         const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
7818         struct mlx5_priv *priv;
7819         uint16_t mask, id;
7820
7821         mask = pid_m ? pid_m->id : 0xffff;
7822         id = pid_v ? pid_v->id : dev->data->port_id;
7823         priv = mlx5_port_to_eswitch_info(id, item == NULL);
7824         if (!priv)
7825                 return -rte_errno;
7826         /*
7827          * Translate to vport field or to metadata, depending on mode.
7828          * Kernel can use either misc.source_port or half of C0 metadata
7829          * register.
7830          */
7831         if (priv->vport_meta_mask) {
7832                 /*
7833                  * Provide the hint for SW steering library
7834                  * to insert the flow into ingress domain and
7835                  * save the extra vport match.
7836                  */
7837                 if (mask == 0xffff && priv->vport_id == 0xffff &&
7838                     priv->pf_bond < 0 && attr->transfer)
7839                         flow_dv_translate_item_source_vport
7840                                 (matcher, key, priv->vport_id, mask);
7841                 else
7842                         flow_dv_translate_item_meta_vport
7843                                 (matcher, key,
7844                                  priv->vport_meta_tag,
7845                                  priv->vport_meta_mask);
7846         } else {
7847                 flow_dv_translate_item_source_vport(matcher, key,
7848                                                     priv->vport_id, mask);
7849         }
7850         return 0;
7851 }
7852
7853 /**
7854  * Add ICMP6 item to matcher and to the value.
7855  *
7856  * @param[in, out] matcher
7857  *   Flow matcher.
7858  * @param[in, out] key
7859  *   Flow matcher value.
7860  * @param[in] item
7861  *   Flow pattern to translate.
7862  * @param[in] inner
7863  *   Item is inner pattern.
7864  */
7865 static void
7866 flow_dv_translate_item_icmp6(void *matcher, void *key,
7867                               const struct rte_flow_item *item,
7868                               int inner)
7869 {
7870         const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
7871         const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
7872         void *headers_m;
7873         void *headers_v;
7874         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7875                                      misc_parameters_3);
7876         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7877         if (inner) {
7878                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7879                                          inner_headers);
7880                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7881         } else {
7882                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7883                                          outer_headers);
7884                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7885         }
7886         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
7887         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
7888         if (!icmp6_v)
7889                 return;
7890         if (!icmp6_m)
7891                 icmp6_m = &rte_flow_item_icmp6_mask;
7892         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
7893         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
7894                  icmp6_v->type & icmp6_m->type);
7895         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
7896         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
7897                  icmp6_v->code & icmp6_m->code);
7898 }
7899
7900 /**
7901  * Add ICMP item to matcher and to the value.
7902  *
7903  * @param[in, out] matcher
7904  *   Flow matcher.
7905  * @param[in, out] key
7906  *   Flow matcher value.
7907  * @param[in] item
7908  *   Flow pattern to translate.
7909  * @param[in] inner
7910  *   Item is inner pattern.
7911  */
7912 static void
7913 flow_dv_translate_item_icmp(void *matcher, void *key,
7914                             const struct rte_flow_item *item,
7915                             int inner)
7916 {
7917         const struct rte_flow_item_icmp *icmp_m = item->mask;
7918         const struct rte_flow_item_icmp *icmp_v = item->spec;
7919         uint32_t icmp_header_data_m = 0;
7920         uint32_t icmp_header_data_v = 0;
7921         void *headers_m;
7922         void *headers_v;
7923         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7924                                      misc_parameters_3);
7925         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7926         if (inner) {
7927                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7928                                          inner_headers);
7929                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7930         } else {
7931                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7932                                          outer_headers);
7933                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7934         }
7935         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
7936         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
7937         if (!icmp_v)
7938                 return;
7939         if (!icmp_m)
7940                 icmp_m = &rte_flow_item_icmp_mask;
7941         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
7942                  icmp_m->hdr.icmp_type);
7943         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
7944                  icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
7945         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
7946                  icmp_m->hdr.icmp_code);
7947         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
7948                  icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
7949         icmp_header_data_m = rte_be_to_cpu_16(icmp_m->hdr.icmp_seq_nb);
7950         icmp_header_data_m |= rte_be_to_cpu_16(icmp_m->hdr.icmp_ident) << 16;
7951         if (icmp_header_data_m) {
7952                 icmp_header_data_v = rte_be_to_cpu_16(icmp_v->hdr.icmp_seq_nb);
7953                 icmp_header_data_v |=
7954                          rte_be_to_cpu_16(icmp_v->hdr.icmp_ident) << 16;
7955                 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_header_data,
7956                          icmp_header_data_m);
7957                 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_header_data,
7958                          icmp_header_data_v & icmp_header_data_m);
7959         }
7960 }
7961
7962 /**
7963  * Add GTP item to matcher and to the value.
7964  *
7965  * @param[in, out] matcher
7966  *   Flow matcher.
7967  * @param[in, out] key
7968  *   Flow matcher value.
7969  * @param[in] item
7970  *   Flow pattern to translate.
7971  * @param[in] inner
7972  *   Item is inner pattern.
7973  */
7974 static void
7975 flow_dv_translate_item_gtp(void *matcher, void *key,
7976                            const struct rte_flow_item *item, int inner)
7977 {
7978         const struct rte_flow_item_gtp *gtp_m = item->mask;
7979         const struct rte_flow_item_gtp *gtp_v = item->spec;
7980         void *headers_m;
7981         void *headers_v;
7982         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7983                                      misc_parameters_3);
7984         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7985         uint16_t dport = RTE_GTPU_UDP_PORT;
7986
7987         if (inner) {
7988                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7989                                          inner_headers);
7990                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7991         } else {
7992                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7993                                          outer_headers);
7994                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7995         }
7996         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7997                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7998                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7999         }
8000         if (!gtp_v)
8001                 return;
8002         if (!gtp_m)
8003                 gtp_m = &rte_flow_item_gtp_mask;
8004         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags,
8005                  gtp_m->v_pt_rsv_flags);
8006         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags,
8007                  gtp_v->v_pt_rsv_flags & gtp_m->v_pt_rsv_flags);
8008         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
8009         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
8010                  gtp_v->msg_type & gtp_m->msg_type);
8011         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
8012                  rte_be_to_cpu_32(gtp_m->teid));
8013         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
8014                  rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
8015 }
8016
8017 /**
8018  * Add GTP PSC item to matcher.
8019  *
8020  * @param[in, out] matcher
8021  *   Flow matcher.
8022  * @param[in, out] key
8023  *   Flow matcher value.
8024  * @param[in] item
8025  *   Flow pattern to translate.
8026  */
8027 static int
8028 flow_dv_translate_item_gtp_psc(void *matcher, void *key,
8029                                const struct rte_flow_item *item)
8030 {
8031         const struct rte_flow_item_gtp_psc *gtp_psc_m = item->mask;
8032         const struct rte_flow_item_gtp_psc *gtp_psc_v = item->spec;
8033         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8034                         misc_parameters_3);
8035         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8036         union {
8037                 uint32_t w32;
8038                 struct {
8039                         uint16_t seq_num;
8040                         uint8_t npdu_num;
8041                         uint8_t next_ext_header_type;
8042                 };
8043         } dw_2;
8044         uint8_t gtp_flags;
8045
8046         /* Always set E-flag match on one, regardless of GTP item settings. */
8047         gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_m, gtpu_msg_flags);
8048         gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
8049         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags, gtp_flags);
8050         gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_v, gtpu_msg_flags);
8051         gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
8052         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags, gtp_flags);
8053         /*Set next extension header type. */
8054         dw_2.seq_num = 0;
8055         dw_2.npdu_num = 0;
8056         dw_2.next_ext_header_type = 0xff;
8057         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_dw_2,
8058                  rte_cpu_to_be_32(dw_2.w32));
8059         dw_2.seq_num = 0;
8060         dw_2.npdu_num = 0;
8061         dw_2.next_ext_header_type = 0x85;
8062         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_dw_2,
8063                  rte_cpu_to_be_32(dw_2.w32));
8064         if (gtp_psc_v) {
8065                 union {
8066                         uint32_t w32;
8067                         struct {
8068                                 uint8_t len;
8069                                 uint8_t type_flags;
8070                                 uint8_t qfi;
8071                                 uint8_t reserved;
8072                         };
8073                 } dw_0;
8074
8075                 /*Set extension header PDU type and Qos. */
8076                 if (!gtp_psc_m)
8077                         gtp_psc_m = &rte_flow_item_gtp_psc_mask;
8078                 dw_0.w32 = 0;
8079                 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_m->pdu_type);
8080                 dw_0.qfi = gtp_psc_m->qfi;
8081                 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_first_ext_dw_0,
8082                          rte_cpu_to_be_32(dw_0.w32));
8083                 dw_0.w32 = 0;
8084                 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_v->pdu_type &
8085                                                         gtp_psc_m->pdu_type);
8086                 dw_0.qfi = gtp_psc_v->qfi & gtp_psc_m->qfi;
8087                 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_first_ext_dw_0,
8088                          rte_cpu_to_be_32(dw_0.w32));
8089         }
8090         return 0;
8091 }
8092
8093 /**
8094  * Add eCPRI item to matcher and to the value.
8095  *
8096  * @param[in] dev
8097  *   The devich to configure through.
8098  * @param[in, out] matcher
8099  *   Flow matcher.
8100  * @param[in, out] key
8101  *   Flow matcher value.
8102  * @param[in] item
8103  *   Flow pattern to translate.
8104  * @param[in] samples
8105  *   Sample IDs to be used in the matching.
8106  */
8107 static void
8108 flow_dv_translate_item_ecpri(struct rte_eth_dev *dev, void *matcher,
8109                              void *key, const struct rte_flow_item *item)
8110 {
8111         struct mlx5_priv *priv = dev->data->dev_private;
8112         const struct rte_flow_item_ecpri *ecpri_m = item->mask;
8113         const struct rte_flow_item_ecpri *ecpri_v = item->spec;
8114         struct rte_ecpri_common_hdr common;
8115         void *misc4_m = MLX5_ADDR_OF(fte_match_param, matcher,
8116                                      misc_parameters_4);
8117         void *misc4_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_4);
8118         uint32_t *samples;
8119         void *dw_m;
8120         void *dw_v;
8121
8122         if (!ecpri_v)
8123                 return;
8124         if (!ecpri_m)
8125                 ecpri_m = &rte_flow_item_ecpri_mask;
8126         /*
8127          * Maximal four DW samples are supported in a single matching now.
8128          * Two are used now for a eCPRI matching:
8129          * 1. Type: one byte, mask should be 0x00ff0000 in network order
8130          * 2. ID of a message: one or two bytes, mask 0xffff0000 or 0xff000000
8131          *    if any.
8132          */
8133         if (!ecpri_m->hdr.common.u32)
8134                 return;
8135         samples = priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0].ids;
8136         /* Need to take the whole DW as the mask to fill the entry. */
8137         dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
8138                             prog_sample_field_value_0);
8139         dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
8140                             prog_sample_field_value_0);
8141         /* Already big endian (network order) in the header. */
8142         *(uint32_t *)dw_m = ecpri_m->hdr.common.u32;
8143         *(uint32_t *)dw_v = ecpri_v->hdr.common.u32 & ecpri_m->hdr.common.u32;
8144         /* Sample#0, used for matching type, offset 0. */
8145         MLX5_SET(fte_match_set_misc4, misc4_m,
8146                  prog_sample_field_id_0, samples[0]);
8147         /* It makes no sense to set the sample ID in the mask field. */
8148         MLX5_SET(fte_match_set_misc4, misc4_v,
8149                  prog_sample_field_id_0, samples[0]);
8150         /*
8151          * Checking if message body part needs to be matched.
8152          * Some wildcard rules only matching type field should be supported.
8153          */
8154         if (ecpri_m->hdr.dummy[0]) {
8155                 common.u32 = rte_be_to_cpu_32(ecpri_v->hdr.common.u32);
8156                 switch (common.type) {
8157                 case RTE_ECPRI_MSG_TYPE_IQ_DATA:
8158                 case RTE_ECPRI_MSG_TYPE_RTC_CTRL:
8159                 case RTE_ECPRI_MSG_TYPE_DLY_MSR:
8160                         dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
8161                                             prog_sample_field_value_1);
8162                         dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
8163                                             prog_sample_field_value_1);
8164                         *(uint32_t *)dw_m = ecpri_m->hdr.dummy[0];
8165                         *(uint32_t *)dw_v = ecpri_v->hdr.dummy[0] &
8166                                             ecpri_m->hdr.dummy[0];
8167                         /* Sample#1, to match message body, offset 4. */
8168                         MLX5_SET(fte_match_set_misc4, misc4_m,
8169                                  prog_sample_field_id_1, samples[1]);
8170                         MLX5_SET(fte_match_set_misc4, misc4_v,
8171                                  prog_sample_field_id_1, samples[1]);
8172                         break;
8173                 default:
8174                         /* Others, do not match any sample ID. */
8175                         break;
8176                 }
8177         }
8178 }
8179
8180 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
8181
8182 #define HEADER_IS_ZERO(match_criteria, headers)                              \
8183         !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers),     \
8184                  matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
8185
8186 /**
8187  * Calculate flow matcher enable bitmap.
8188  *
8189  * @param match_criteria
8190  *   Pointer to flow matcher criteria.
8191  *
8192  * @return
8193  *   Bitmap of enabled fields.
8194  */
8195 static uint8_t
8196 flow_dv_matcher_enable(uint32_t *match_criteria)
8197 {
8198         uint8_t match_criteria_enable;
8199
8200         match_criteria_enable =
8201                 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
8202                 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
8203         match_criteria_enable |=
8204                 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
8205                 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
8206         match_criteria_enable |=
8207                 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
8208                 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
8209         match_criteria_enable |=
8210                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
8211                 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
8212         match_criteria_enable |=
8213                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
8214                 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
8215         match_criteria_enable |=
8216                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_4)) <<
8217                 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT;
8218         return match_criteria_enable;
8219 }
8220
8221 struct mlx5_hlist_entry *
8222 flow_dv_tbl_create_cb(struct mlx5_hlist *list, uint64_t key64, void *cb_ctx)
8223 {
8224         struct mlx5_dev_ctx_shared *sh = list->ctx;
8225         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
8226         struct rte_eth_dev *dev = ctx->dev;
8227         struct mlx5_flow_tbl_data_entry *tbl_data;
8228         struct mlx5_flow_tbl_tunnel_prm *tt_prm = ctx->data;
8229         struct rte_flow_error *error = ctx->error;
8230         union mlx5_flow_tbl_key key = { .v64 = key64 };
8231         struct mlx5_flow_tbl_resource *tbl;
8232         void *domain;
8233         uint32_t idx = 0;
8234         int ret;
8235
8236         tbl_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
8237         if (!tbl_data) {
8238                 rte_flow_error_set(error, ENOMEM,
8239                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8240                                    NULL,
8241                                    "cannot allocate flow table data entry");
8242                 return NULL;
8243         }
8244         tbl_data->idx = idx;
8245         tbl_data->tunnel = tt_prm->tunnel;
8246         tbl_data->group_id = tt_prm->group_id;
8247         tbl_data->external = !!tt_prm->external;
8248         tbl_data->tunnel_offload = is_tunnel_offload_active(dev);
8249         tbl_data->is_egress = !!key.direction;
8250         tbl_data->is_transfer = !!key.domain;
8251         tbl_data->dummy = !!key.dummy;
8252         tbl_data->table_id = key.table_id;
8253         tbl = &tbl_data->tbl;
8254         if (key.dummy)
8255                 return &tbl_data->entry;
8256         if (key.domain)
8257                 domain = sh->fdb_domain;
8258         else if (key.direction)
8259                 domain = sh->tx_domain;
8260         else
8261                 domain = sh->rx_domain;
8262         ret = mlx5_flow_os_create_flow_tbl(domain, key.table_id, &tbl->obj);
8263         if (ret) {
8264                 rte_flow_error_set(error, ENOMEM,
8265                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8266                                    NULL, "cannot create flow table object");
8267                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
8268                 return NULL;
8269         }
8270         if (key.table_id) {
8271                 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
8272                                         (tbl->obj, &tbl_data->jump.action);
8273                 if (ret) {
8274                         rte_flow_error_set(error, ENOMEM,
8275                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8276                                            NULL,
8277                                            "cannot create flow jump action");
8278                         mlx5_flow_os_destroy_flow_tbl(tbl->obj);
8279                         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
8280                         return NULL;
8281                 }
8282         }
8283         MKSTR(matcher_name, "%s_%s_%u_matcher_cache",
8284               key.domain ? "FDB" : "NIC", key.direction ? "egress" : "ingress",
8285               key.table_id);
8286         mlx5_cache_list_init(&tbl_data->matchers, matcher_name, 0, sh,
8287                              flow_dv_matcher_create_cb,
8288                              flow_dv_matcher_match_cb,
8289                              flow_dv_matcher_remove_cb);
8290         return &tbl_data->entry;
8291 }
8292
8293 int
8294 flow_dv_tbl_match_cb(struct mlx5_hlist *list __rte_unused,
8295                      struct mlx5_hlist_entry *entry, uint64_t key64,
8296                      void *cb_ctx __rte_unused)
8297 {
8298         struct mlx5_flow_tbl_data_entry *tbl_data =
8299                 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
8300         union mlx5_flow_tbl_key key = { .v64 = key64 };
8301
8302         return tbl_data->table_id != key.table_id ||
8303                tbl_data->dummy != key.dummy ||
8304                tbl_data->is_transfer != key.domain ||
8305                tbl_data->is_egress != key.direction;
8306 }
8307
8308 /**
8309  * Get a flow table.
8310  *
8311  * @param[in, out] dev
8312  *   Pointer to rte_eth_dev structure.
8313  * @param[in] table_id
8314  *   Table id to use.
8315  * @param[in] egress
8316  *   Direction of the table.
8317  * @param[in] transfer
8318  *   E-Switch or NIC flow.
8319  * @param[in] dummy
8320  *   Dummy entry for dv API.
8321  * @param[out] error
8322  *   pointer to error structure.
8323  *
8324  * @return
8325  *   Returns tables resource based on the index, NULL in case of failed.
8326  */
8327 struct mlx5_flow_tbl_resource *
8328 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
8329                          uint32_t table_id, uint8_t egress,
8330                          uint8_t transfer,
8331                          bool external,
8332                          const struct mlx5_flow_tunnel *tunnel,
8333                          uint32_t group_id, uint8_t dummy,
8334                          struct rte_flow_error *error)
8335 {
8336         struct mlx5_priv *priv = dev->data->dev_private;
8337         union mlx5_flow_tbl_key table_key = {
8338                 {
8339                         .table_id = table_id,
8340                         .dummy = dummy,
8341                         .domain = !!transfer,
8342                         .direction = !!egress,
8343                 }
8344         };
8345         struct mlx5_flow_tbl_tunnel_prm tt_prm = {
8346                 .tunnel = tunnel,
8347                 .group_id = group_id,
8348                 .external = external,
8349         };
8350         struct mlx5_flow_cb_ctx ctx = {
8351                 .dev = dev,
8352                 .error = error,
8353                 .data = &tt_prm,
8354         };
8355         struct mlx5_hlist_entry *entry;
8356         struct mlx5_flow_tbl_data_entry *tbl_data;
8357
8358         entry = mlx5_hlist_register(priv->sh->flow_tbls, table_key.v64, &ctx);
8359         if (!entry) {
8360                 rte_flow_error_set(error, ENOMEM,
8361                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8362                                    "cannot get table");
8363                 return NULL;
8364         }
8365         DRV_LOG(DEBUG, "Table_id %u tunnel %u group %u registered.",
8366                 table_id, tunnel ? tunnel->tunnel_id : 0, group_id);
8367         tbl_data = container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
8368         return &tbl_data->tbl;
8369 }
8370
8371 void
8372 flow_dv_tbl_remove_cb(struct mlx5_hlist *list,
8373                       struct mlx5_hlist_entry *entry)
8374 {
8375         struct mlx5_dev_ctx_shared *sh = list->ctx;
8376         struct mlx5_flow_tbl_data_entry *tbl_data =
8377                 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
8378
8379         MLX5_ASSERT(entry && sh);
8380         if (tbl_data->jump.action)
8381                 mlx5_flow_os_destroy_flow_action(tbl_data->jump.action);
8382         if (tbl_data->tbl.obj)
8383                 mlx5_flow_os_destroy_flow_tbl(tbl_data->tbl.obj);
8384         if (tbl_data->tunnel_offload && tbl_data->external) {
8385                 struct mlx5_hlist_entry *he;
8386                 struct mlx5_hlist *tunnel_grp_hash;
8387                 struct mlx5_flow_tunnel_hub *thub = sh->tunnel_hub;
8388                 union tunnel_tbl_key tunnel_key = {
8389                         .tunnel_id = tbl_data->tunnel ?
8390                                         tbl_data->tunnel->tunnel_id : 0,
8391                         .group = tbl_data->group_id
8392                 };
8393                 uint32_t table_id = tbl_data->table_id;
8394
8395                 tunnel_grp_hash = tbl_data->tunnel ?
8396                                         tbl_data->tunnel->groups :
8397                                         thub->groups;
8398                 he = mlx5_hlist_lookup(tunnel_grp_hash, tunnel_key.val, NULL);
8399                 if (he)
8400                         mlx5_hlist_unregister(tunnel_grp_hash, he);
8401                 DRV_LOG(DEBUG,
8402                         "Table_id %u tunnel %u group %u released.",
8403                         table_id,
8404                         tbl_data->tunnel ?
8405                         tbl_data->tunnel->tunnel_id : 0,
8406                         tbl_data->group_id);
8407         }
8408         mlx5_cache_list_destroy(&tbl_data->matchers);
8409         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], tbl_data->idx);
8410 }
8411
8412 /**
8413  * Release a flow table.
8414  *
8415  * @param[in] sh
8416  *   Pointer to device shared structure.
8417  * @param[in] tbl
8418  *   Table resource to be released.
8419  *
8420  * @return
8421  *   Returns 0 if table was released, else return 1;
8422  */
8423 static int
8424 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
8425                              struct mlx5_flow_tbl_resource *tbl)
8426 {
8427         struct mlx5_flow_tbl_data_entry *tbl_data =
8428                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
8429
8430         if (!tbl)
8431                 return 0;
8432         return mlx5_hlist_unregister(sh->flow_tbls, &tbl_data->entry);
8433 }
8434
8435 int
8436 flow_dv_matcher_match_cb(struct mlx5_cache_list *list __rte_unused,
8437                          struct mlx5_cache_entry *entry, void *cb_ctx)
8438 {
8439         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
8440         struct mlx5_flow_dv_matcher *ref = ctx->data;
8441         struct mlx5_flow_dv_matcher *cur = container_of(entry, typeof(*cur),
8442                                                         entry);
8443
8444         return cur->crc != ref->crc ||
8445                cur->priority != ref->priority ||
8446                memcmp((const void *)cur->mask.buf,
8447                       (const void *)ref->mask.buf, ref->mask.size);
8448 }
8449
8450 struct mlx5_cache_entry *
8451 flow_dv_matcher_create_cb(struct mlx5_cache_list *list,
8452                           struct mlx5_cache_entry *entry __rte_unused,
8453                           void *cb_ctx)
8454 {
8455         struct mlx5_dev_ctx_shared *sh = list->ctx;
8456         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
8457         struct mlx5_flow_dv_matcher *ref = ctx->data;
8458         struct mlx5_flow_dv_matcher *cache;
8459         struct mlx5dv_flow_matcher_attr dv_attr = {
8460                 .type = IBV_FLOW_ATTR_NORMAL,
8461                 .match_mask = (void *)&ref->mask,
8462         };
8463         struct mlx5_flow_tbl_data_entry *tbl = container_of(ref->tbl,
8464                                                             typeof(*tbl), tbl);
8465         int ret;
8466
8467         cache = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*cache), 0, SOCKET_ID_ANY);
8468         if (!cache) {
8469                 rte_flow_error_set(ctx->error, ENOMEM,
8470                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8471                                    "cannot create matcher");
8472                 return NULL;
8473         }
8474         *cache = *ref;
8475         dv_attr.match_criteria_enable =
8476                 flow_dv_matcher_enable(cache->mask.buf);
8477         dv_attr.priority = ref->priority;
8478         if (tbl->is_egress)
8479                 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
8480         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->tbl.obj,
8481                                                &cache->matcher_object);
8482         if (ret) {
8483                 mlx5_free(cache);
8484                 rte_flow_error_set(ctx->error, ENOMEM,
8485                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8486                                    "cannot create matcher");
8487                 return NULL;
8488         }
8489         return &cache->entry;
8490 }
8491
8492 /**
8493  * Register the flow matcher.
8494  *
8495  * @param[in, out] dev
8496  *   Pointer to rte_eth_dev structure.
8497  * @param[in, out] matcher
8498  *   Pointer to flow matcher.
8499  * @param[in, out] key
8500  *   Pointer to flow table key.
8501  * @parm[in, out] dev_flow
8502  *   Pointer to the dev_flow.
8503  * @param[out] error
8504  *   pointer to error structure.
8505  *
8506  * @return
8507  *   0 on success otherwise -errno and errno is set.
8508  */
8509 static int
8510 flow_dv_matcher_register(struct rte_eth_dev *dev,
8511                          struct mlx5_flow_dv_matcher *ref,
8512                          union mlx5_flow_tbl_key *key,
8513                          struct mlx5_flow *dev_flow,
8514                          const struct mlx5_flow_tunnel *tunnel,
8515                          uint32_t group_id,
8516                          struct rte_flow_error *error)
8517 {
8518         struct mlx5_cache_entry *entry;
8519         struct mlx5_flow_dv_matcher *cache;
8520         struct mlx5_flow_tbl_resource *tbl;
8521         struct mlx5_flow_tbl_data_entry *tbl_data;
8522         struct mlx5_flow_cb_ctx ctx = {
8523                 .error = error,
8524                 .data = ref,
8525         };
8526
8527         /**
8528          * tunnel offload API requires this registration for cases when
8529          * tunnel match rule was inserted before tunnel set rule.
8530          */
8531         tbl = flow_dv_tbl_resource_get(dev, key->table_id,
8532                                        key->direction, key->domain,
8533                                        dev_flow->external, tunnel,
8534                                        group_id, 0, error);
8535         if (!tbl)
8536                 return -rte_errno;      /* No need to refill the error info */
8537         tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
8538         ref->tbl = tbl;
8539         entry = mlx5_cache_register(&tbl_data->matchers, &ctx);
8540         if (!entry) {
8541                 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
8542                 return rte_flow_error_set(error, ENOMEM,
8543                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8544                                           "cannot allocate ref memory");
8545         }
8546         cache = container_of(entry, typeof(*cache), entry);
8547         dev_flow->handle->dvh.matcher = cache;
8548         return 0;
8549 }
8550
8551 struct mlx5_hlist_entry *
8552 flow_dv_tag_create_cb(struct mlx5_hlist *list, uint64_t key, void *ctx)
8553 {
8554         struct mlx5_dev_ctx_shared *sh = list->ctx;
8555         struct rte_flow_error *error = ctx;
8556         struct mlx5_flow_dv_tag_resource *entry;
8557         uint32_t idx = 0;
8558         int ret;
8559
8560         entry = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_TAG], &idx);
8561         if (!entry) {
8562                 rte_flow_error_set(error, ENOMEM,
8563                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8564                                    "cannot allocate resource memory");
8565                 return NULL;
8566         }
8567         entry->idx = idx;
8568         entry->tag_id = key;
8569         ret = mlx5_flow_os_create_flow_action_tag(key,
8570                                                   &entry->action);
8571         if (ret) {
8572                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], idx);
8573                 rte_flow_error_set(error, ENOMEM,
8574                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8575                                    NULL, "cannot create action");
8576                 return NULL;
8577         }
8578         return &entry->entry;
8579 }
8580
8581 int
8582 flow_dv_tag_match_cb(struct mlx5_hlist *list __rte_unused,
8583                      struct mlx5_hlist_entry *entry, uint64_t key,
8584                      void *cb_ctx __rte_unused)
8585 {
8586         struct mlx5_flow_dv_tag_resource *tag =
8587                 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
8588
8589         return key != tag->tag_id;
8590 }
8591
8592 /**
8593  * Find existing tag resource or create and register a new one.
8594  *
8595  * @param dev[in, out]
8596  *   Pointer to rte_eth_dev structure.
8597  * @param[in, out] tag_be24
8598  *   Tag value in big endian then R-shift 8.
8599  * @parm[in, out] dev_flow
8600  *   Pointer to the dev_flow.
8601  * @param[out] error
8602  *   pointer to error structure.
8603  *
8604  * @return
8605  *   0 on success otherwise -errno and errno is set.
8606  */
8607 static int
8608 flow_dv_tag_resource_register
8609                         (struct rte_eth_dev *dev,
8610                          uint32_t tag_be24,
8611                          struct mlx5_flow *dev_flow,
8612                          struct rte_flow_error *error)
8613 {
8614         struct mlx5_priv *priv = dev->data->dev_private;
8615         struct mlx5_flow_dv_tag_resource *cache_resource;
8616         struct mlx5_hlist_entry *entry;
8617
8618         entry = mlx5_hlist_register(priv->sh->tag_table, tag_be24, error);
8619         if (entry) {
8620                 cache_resource = container_of
8621                         (entry, struct mlx5_flow_dv_tag_resource, entry);
8622                 dev_flow->handle->dvh.rix_tag = cache_resource->idx;
8623                 dev_flow->dv.tag_resource = cache_resource;
8624                 return 0;
8625         }
8626         return -rte_errno;
8627 }
8628
8629 void
8630 flow_dv_tag_remove_cb(struct mlx5_hlist *list,
8631                       struct mlx5_hlist_entry *entry)
8632 {
8633         struct mlx5_dev_ctx_shared *sh = list->ctx;
8634         struct mlx5_flow_dv_tag_resource *tag =
8635                 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
8636
8637         MLX5_ASSERT(tag && sh && tag->action);
8638         claim_zero(mlx5_flow_os_destroy_flow_action(tag->action));
8639         DRV_LOG(DEBUG, "Tag %p: removed.", (void *)tag);
8640         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], tag->idx);
8641 }
8642
8643 /**
8644  * Release the tag.
8645  *
8646  * @param dev
8647  *   Pointer to Ethernet device.
8648  * @param tag_idx
8649  *   Tag index.
8650  *
8651  * @return
8652  *   1 while a reference on it exists, 0 when freed.
8653  */
8654 static int
8655 flow_dv_tag_release(struct rte_eth_dev *dev,
8656                     uint32_t tag_idx)
8657 {
8658         struct mlx5_priv *priv = dev->data->dev_private;
8659         struct mlx5_flow_dv_tag_resource *tag;
8660
8661         tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
8662         if (!tag)
8663                 return 0;
8664         DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
8665                 dev->data->port_id, (void *)tag, tag->entry.ref_cnt);
8666         return mlx5_hlist_unregister(priv->sh->tag_table, &tag->entry);
8667 }
8668
8669 /**
8670  * Translate port ID action to vport.
8671  *
8672  * @param[in] dev
8673  *   Pointer to rte_eth_dev structure.
8674  * @param[in] action
8675  *   Pointer to the port ID action.
8676  * @param[out] dst_port_id
8677  *   The target port ID.
8678  * @param[out] error
8679  *   Pointer to the error structure.
8680  *
8681  * @return
8682  *   0 on success, a negative errno value otherwise and rte_errno is set.
8683  */
8684 static int
8685 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
8686                                  const struct rte_flow_action *action,
8687                                  uint32_t *dst_port_id,
8688                                  struct rte_flow_error *error)
8689 {
8690         uint32_t port;
8691         struct mlx5_priv *priv;
8692         const struct rte_flow_action_port_id *conf =
8693                         (const struct rte_flow_action_port_id *)action->conf;
8694
8695         port = conf->original ? dev->data->port_id : conf->id;
8696         priv = mlx5_port_to_eswitch_info(port, false);
8697         if (!priv)
8698                 return rte_flow_error_set(error, -rte_errno,
8699                                           RTE_FLOW_ERROR_TYPE_ACTION,
8700                                           NULL,
8701                                           "No eswitch info was found for port");
8702 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
8703         /*
8704          * This parameter is transferred to
8705          * mlx5dv_dr_action_create_dest_ib_port().
8706          */
8707         *dst_port_id = priv->dev_port;
8708 #else
8709         /*
8710          * Legacy mode, no LAG configurations is supported.
8711          * This parameter is transferred to
8712          * mlx5dv_dr_action_create_dest_vport().
8713          */
8714         *dst_port_id = priv->vport_id;
8715 #endif
8716         return 0;
8717 }
8718
8719 /**
8720  * Create a counter with aging configuration.
8721  *
8722  * @param[in] dev
8723  *   Pointer to rte_eth_dev structure.
8724  * @param[out] count
8725  *   Pointer to the counter action configuration.
8726  * @param[in] age
8727  *   Pointer to the aging action configuration.
8728  *
8729  * @return
8730  *   Index to flow counter on success, 0 otherwise.
8731  */
8732 static uint32_t
8733 flow_dv_translate_create_counter(struct rte_eth_dev *dev,
8734                                 struct mlx5_flow *dev_flow,
8735                                 const struct rte_flow_action_count *count,
8736                                 const struct rte_flow_action_age *age)
8737 {
8738         uint32_t counter;
8739         struct mlx5_age_param *age_param;
8740
8741         if (count && count->shared)
8742                 counter = flow_dv_counter_get_shared(dev, count->id);
8743         else
8744                 counter = flow_dv_counter_alloc(dev, !!age);
8745         if (!counter || age == NULL)
8746                 return counter;
8747         age_param  = flow_dv_counter_idx_get_age(dev, counter);
8748         age_param->context = age->context ? age->context :
8749                 (void *)(uintptr_t)(dev_flow->flow_idx);
8750         age_param->timeout = age->timeout;
8751         age_param->port_id = dev->data->port_id;
8752         __atomic_store_n(&age_param->sec_since_last_hit, 0, __ATOMIC_RELAXED);
8753         __atomic_store_n(&age_param->state, AGE_CANDIDATE, __ATOMIC_RELAXED);
8754         return counter;
8755 }
8756
8757 /**
8758  * Add Tx queue matcher
8759  *
8760  * @param[in] dev
8761  *   Pointer to the dev struct.
8762  * @param[in, out] matcher
8763  *   Flow matcher.
8764  * @param[in, out] key
8765  *   Flow matcher value.
8766  * @param[in] item
8767  *   Flow pattern to translate.
8768  * @param[in] inner
8769  *   Item is inner pattern.
8770  */
8771 static void
8772 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
8773                                 void *matcher, void *key,
8774                                 const struct rte_flow_item *item)
8775 {
8776         const struct mlx5_rte_flow_item_tx_queue *queue_m;
8777         const struct mlx5_rte_flow_item_tx_queue *queue_v;
8778         void *misc_m =
8779                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8780         void *misc_v =
8781                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8782         struct mlx5_txq_ctrl *txq;
8783         uint32_t queue;
8784
8785
8786         queue_m = (const void *)item->mask;
8787         if (!queue_m)
8788                 return;
8789         queue_v = (const void *)item->spec;
8790         if (!queue_v)
8791                 return;
8792         txq = mlx5_txq_get(dev, queue_v->queue);
8793         if (!txq)
8794                 return;
8795         queue = txq->obj->sq->id;
8796         MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
8797         MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
8798                  queue & queue_m->queue);
8799         mlx5_txq_release(dev, queue_v->queue);
8800 }
8801
8802 /**
8803  * Set the hash fields according to the @p flow information.
8804  *
8805  * @param[in] dev_flow
8806  *   Pointer to the mlx5_flow.
8807  * @param[in] rss_desc
8808  *   Pointer to the mlx5_flow_rss_desc.
8809  */
8810 static void
8811 flow_dv_hashfields_set(struct mlx5_flow *dev_flow,
8812                        struct mlx5_flow_rss_desc *rss_desc)
8813 {
8814         uint64_t items = dev_flow->handle->layers;
8815         int rss_inner = 0;
8816         uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
8817
8818         dev_flow->hash_fields = 0;
8819 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
8820         if (rss_desc->level >= 2) {
8821                 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
8822                 rss_inner = 1;
8823         }
8824 #endif
8825         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
8826             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
8827                 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
8828                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
8829                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
8830                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
8831                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
8832                         else
8833                                 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
8834                 }
8835         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
8836                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
8837                 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
8838                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
8839                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
8840                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
8841                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
8842                         else
8843                                 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
8844                 }
8845         }
8846         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
8847             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
8848                 if (rss_types & ETH_RSS_UDP) {
8849                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
8850                                 dev_flow->hash_fields |=
8851                                                 IBV_RX_HASH_SRC_PORT_UDP;
8852                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
8853                                 dev_flow->hash_fields |=
8854                                                 IBV_RX_HASH_DST_PORT_UDP;
8855                         else
8856                                 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
8857                 }
8858         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
8859                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
8860                 if (rss_types & ETH_RSS_TCP) {
8861                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
8862                                 dev_flow->hash_fields |=
8863                                                 IBV_RX_HASH_SRC_PORT_TCP;
8864                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
8865                                 dev_flow->hash_fields |=
8866                                                 IBV_RX_HASH_DST_PORT_TCP;
8867                         else
8868                                 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
8869                 }
8870         }
8871 }
8872
8873 /**
8874  * Prepare an Rx Hash queue.
8875  *
8876  * @param dev
8877  *   Pointer to Ethernet device.
8878  * @param[in] dev_flow
8879  *   Pointer to the mlx5_flow.
8880  * @param[in] rss_desc
8881  *   Pointer to the mlx5_flow_rss_desc.
8882  * @param[out] hrxq_idx
8883  *   Hash Rx queue index.
8884  *
8885  * @return
8886  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
8887  */
8888 static struct mlx5_hrxq *
8889 flow_dv_hrxq_prepare(struct rte_eth_dev *dev,
8890                      struct mlx5_flow *dev_flow,
8891                      struct mlx5_flow_rss_desc *rss_desc,
8892                      uint32_t *hrxq_idx)
8893 {
8894         struct mlx5_priv *priv = dev->data->dev_private;
8895         struct mlx5_flow_handle *dh = dev_flow->handle;
8896         struct mlx5_hrxq *hrxq;
8897
8898         MLX5_ASSERT(rss_desc->queue_num);
8899         rss_desc->key_len = MLX5_RSS_HASH_KEY_LEN;
8900         rss_desc->hash_fields = dev_flow->hash_fields;
8901         rss_desc->tunnel = !!(dh->layers & MLX5_FLOW_LAYER_TUNNEL);
8902         rss_desc->shared_rss = 0;
8903         *hrxq_idx = mlx5_hrxq_get(dev, rss_desc);
8904         if (!*hrxq_idx)
8905                 return NULL;
8906         hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
8907                               *hrxq_idx);
8908         return hrxq;
8909 }
8910
8911 /**
8912  * Release sample sub action resource.
8913  *
8914  * @param[in, out] dev
8915  *   Pointer to rte_eth_dev structure.
8916  * @param[in] act_res
8917  *   Pointer to sample sub action resource.
8918  */
8919 static void
8920 flow_dv_sample_sub_actions_release(struct rte_eth_dev *dev,
8921                                    struct mlx5_flow_sub_actions_idx *act_res)
8922 {
8923         if (act_res->rix_hrxq) {
8924                 mlx5_hrxq_release(dev, act_res->rix_hrxq);
8925                 act_res->rix_hrxq = 0;
8926         }
8927         if (act_res->rix_encap_decap) {
8928                 flow_dv_encap_decap_resource_release(dev,
8929                                                      act_res->rix_encap_decap);
8930                 act_res->rix_encap_decap = 0;
8931         }
8932         if (act_res->rix_port_id_action) {
8933                 flow_dv_port_id_action_resource_release(dev,
8934                                                 act_res->rix_port_id_action);
8935                 act_res->rix_port_id_action = 0;
8936         }
8937         if (act_res->rix_tag) {
8938                 flow_dv_tag_release(dev, act_res->rix_tag);
8939                 act_res->rix_tag = 0;
8940         }
8941         if (act_res->cnt) {
8942                 flow_dv_counter_free(dev, act_res->cnt);
8943                 act_res->cnt = 0;
8944         }
8945 }
8946
8947 int
8948 flow_dv_sample_match_cb(struct mlx5_cache_list *list __rte_unused,
8949                         struct mlx5_cache_entry *entry, void *cb_ctx)
8950 {
8951         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
8952         struct rte_eth_dev *dev = ctx->dev;
8953         struct mlx5_flow_dv_sample_resource *resource = ctx->data;
8954         struct mlx5_flow_dv_sample_resource *cache_resource =
8955                         container_of(entry, typeof(*cache_resource), entry);
8956
8957         if (resource->ratio == cache_resource->ratio &&
8958             resource->ft_type == cache_resource->ft_type &&
8959             resource->ft_id == cache_resource->ft_id &&
8960             resource->set_action == cache_resource->set_action &&
8961             !memcmp((void *)&resource->sample_act,
8962                     (void *)&cache_resource->sample_act,
8963                     sizeof(struct mlx5_flow_sub_actions_list))) {
8964                 /*
8965                  * Existing sample action should release the prepared
8966                  * sub-actions reference counter.
8967                  */
8968                 flow_dv_sample_sub_actions_release(dev,
8969                                                 &resource->sample_idx);
8970                 return 0;
8971         }
8972         return 1;
8973 }
8974
8975 struct mlx5_cache_entry *
8976 flow_dv_sample_create_cb(struct mlx5_cache_list *list __rte_unused,
8977                          struct mlx5_cache_entry *entry __rte_unused,
8978                          void *cb_ctx)
8979 {
8980         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
8981         struct rte_eth_dev *dev = ctx->dev;
8982         struct mlx5_flow_dv_sample_resource *resource = ctx->data;
8983         void **sample_dv_actions = resource->sub_actions;
8984         struct mlx5_flow_dv_sample_resource *cache_resource;
8985         struct mlx5dv_dr_flow_sampler_attr sampler_attr;
8986         struct mlx5_priv *priv = dev->data->dev_private;
8987         struct mlx5_dev_ctx_shared *sh = priv->sh;
8988         struct mlx5_flow_tbl_resource *tbl;
8989         uint32_t idx = 0;
8990         const uint32_t next_ft_step = 1;
8991         uint32_t next_ft_id = resource->ft_id + next_ft_step;
8992         uint8_t is_egress = 0;
8993         uint8_t is_transfer = 0;
8994         struct rte_flow_error *error = ctx->error;
8995
8996         /* Register new sample resource. */
8997         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_SAMPLE], &idx);
8998         if (!cache_resource) {
8999                 rte_flow_error_set(error, ENOMEM,
9000                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9001                                           NULL,
9002                                           "cannot allocate resource memory");
9003                 return NULL;
9004         }
9005         *cache_resource = *resource;
9006         /* Create normal path table level */
9007         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
9008                 is_transfer = 1;
9009         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
9010                 is_egress = 1;
9011         tbl = flow_dv_tbl_resource_get(dev, next_ft_id,
9012                                         is_egress, is_transfer,
9013                                         true, NULL, 0, 0, error);
9014         if (!tbl) {
9015                 rte_flow_error_set(error, ENOMEM,
9016                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9017                                           NULL,
9018                                           "fail to create normal path table "
9019                                           "for sample");
9020                 goto error;
9021         }
9022         int ret;
9023
9024         cache_resource->normal_path_tbl = tbl;
9025         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB) {
9026                 ret = mlx5_flow_os_create_flow_action_default_miss
9027                         (&cache_resource->default_miss);
9028                 if (!ret) {
9029                         rte_flow_error_set(error, ENOMEM,
9030                                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9031                                                 NULL,
9032                                                 "cannot create default miss "
9033                                                 "action");
9034                         goto error;
9035                 }
9036                 sample_dv_actions[resource->sample_act.actions_num++] =
9037                                                 cache_resource->default_miss;
9038         }
9039         /* Create a DR sample action */
9040         sampler_attr.sample_ratio = cache_resource->ratio;
9041         sampler_attr.default_next_table = tbl->obj;
9042         sampler_attr.num_sample_actions = resource->sample_act.actions_num;
9043         sampler_attr.sample_actions = (struct mlx5dv_dr_action **)
9044                                                         &sample_dv_actions[0];
9045         sampler_attr.action = cache_resource->set_action;
9046         if (mlx5_os_flow_dr_create_flow_action_sampler
9047                         (&sampler_attr, &cache_resource->verbs_action)) {
9048                 rte_flow_error_set(error, ENOMEM,
9049                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9050                                         NULL, "cannot create sample action");
9051                 goto error;
9052         }
9053         cache_resource->idx = idx;
9054         cache_resource->dev = dev;
9055         return &cache_resource->entry;
9056 error:
9057         if (cache_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB &&
9058             cache_resource->default_miss)
9059                 claim_zero(mlx5_flow_os_destroy_flow_action
9060                                 (cache_resource->default_miss));
9061         else
9062                 flow_dv_sample_sub_actions_release(dev,
9063                                                    &cache_resource->sample_idx);
9064         if (cache_resource->normal_path_tbl)
9065                 flow_dv_tbl_resource_release(MLX5_SH(dev),
9066                                 cache_resource->normal_path_tbl);
9067         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_SAMPLE], idx);
9068         return NULL;
9069
9070 }
9071
9072 /**
9073  * Find existing sample resource or create and register a new one.
9074  *
9075  * @param[in, out] dev
9076  *   Pointer to rte_eth_dev structure.
9077  * @param[in] resource
9078  *   Pointer to sample resource.
9079  * @parm[in, out] dev_flow
9080  *   Pointer to the dev_flow.
9081  * @param[out] error
9082  *   pointer to error structure.
9083  *
9084  * @return
9085  *   0 on success otherwise -errno and errno is set.
9086  */
9087 static int
9088 flow_dv_sample_resource_register(struct rte_eth_dev *dev,
9089                          struct mlx5_flow_dv_sample_resource *resource,
9090                          struct mlx5_flow *dev_flow,
9091                          struct rte_flow_error *error)
9092 {
9093         struct mlx5_flow_dv_sample_resource *cache_resource;
9094         struct mlx5_cache_entry *entry;
9095         struct mlx5_priv *priv = dev->data->dev_private;
9096         struct mlx5_flow_cb_ctx ctx = {
9097                 .dev = dev,
9098                 .error = error,
9099                 .data = resource,
9100         };
9101
9102         entry = mlx5_cache_register(&priv->sh->sample_action_list, &ctx);
9103         if (!entry)
9104                 return -rte_errno;
9105         cache_resource = container_of(entry, typeof(*cache_resource), entry);
9106         dev_flow->handle->dvh.rix_sample = cache_resource->idx;
9107         dev_flow->dv.sample_res = cache_resource;
9108         return 0;
9109 }
9110
9111 int
9112 flow_dv_dest_array_match_cb(struct mlx5_cache_list *list __rte_unused,
9113                             struct mlx5_cache_entry *entry, void *cb_ctx)
9114 {
9115         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9116         struct mlx5_flow_dv_dest_array_resource *resource = ctx->data;
9117         struct rte_eth_dev *dev = ctx->dev;
9118         struct mlx5_flow_dv_dest_array_resource *cache_resource =
9119                         container_of(entry, typeof(*cache_resource), entry);
9120         uint32_t idx = 0;
9121
9122         if (resource->num_of_dest == cache_resource->num_of_dest &&
9123             resource->ft_type == cache_resource->ft_type &&
9124             !memcmp((void *)cache_resource->sample_act,
9125                     (void *)resource->sample_act,
9126                    (resource->num_of_dest *
9127                    sizeof(struct mlx5_flow_sub_actions_list)))) {
9128                 /*
9129                  * Existing sample action should release the prepared
9130                  * sub-actions reference counter.
9131                  */
9132                 for (idx = 0; idx < resource->num_of_dest; idx++)
9133                         flow_dv_sample_sub_actions_release(dev,
9134                                         &resource->sample_idx[idx]);
9135                 return 0;
9136         }
9137         return 1;
9138 }
9139
9140 struct mlx5_cache_entry *
9141 flow_dv_dest_array_create_cb(struct mlx5_cache_list *list __rte_unused,
9142                          struct mlx5_cache_entry *entry __rte_unused,
9143                          void *cb_ctx)
9144 {
9145         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9146         struct rte_eth_dev *dev = ctx->dev;
9147         struct mlx5_flow_dv_dest_array_resource *cache_resource;
9148         struct mlx5_flow_dv_dest_array_resource *resource = ctx->data;
9149         struct mlx5dv_dr_action_dest_attr *dest_attr[MLX5_MAX_DEST_NUM] = { 0 };
9150         struct mlx5dv_dr_action_dest_reformat dest_reformat[MLX5_MAX_DEST_NUM];
9151         struct mlx5_priv *priv = dev->data->dev_private;
9152         struct mlx5_dev_ctx_shared *sh = priv->sh;
9153         struct mlx5_flow_sub_actions_list *sample_act;
9154         struct mlx5dv_dr_domain *domain;
9155         uint32_t idx = 0, res_idx = 0;
9156         struct rte_flow_error *error = ctx->error;
9157         int ret;
9158
9159         /* Register new destination array resource. */
9160         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
9161                                             &res_idx);
9162         if (!cache_resource) {
9163                 rte_flow_error_set(error, ENOMEM,
9164                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9165                                           NULL,
9166                                           "cannot allocate resource memory");
9167                 return NULL;
9168         }
9169         *cache_resource = *resource;
9170         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
9171                 domain = sh->fdb_domain;
9172         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
9173                 domain = sh->rx_domain;
9174         else
9175                 domain = sh->tx_domain;
9176         for (idx = 0; idx < resource->num_of_dest; idx++) {
9177                 dest_attr[idx] = (struct mlx5dv_dr_action_dest_attr *)
9178                                  mlx5_malloc(MLX5_MEM_ZERO,
9179                                  sizeof(struct mlx5dv_dr_action_dest_attr),
9180                                  0, SOCKET_ID_ANY);
9181                 if (!dest_attr[idx]) {
9182                         rte_flow_error_set(error, ENOMEM,
9183                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9184                                            NULL,
9185                                            "cannot allocate resource memory");
9186                         goto error;
9187                 }
9188                 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST;
9189                 sample_act = &resource->sample_act[idx];
9190                 if (sample_act->action_flags == MLX5_FLOW_ACTION_QUEUE) {
9191                         dest_attr[idx]->dest = sample_act->dr_queue_action;
9192                 } else if (sample_act->action_flags ==
9193                           (MLX5_FLOW_ACTION_PORT_ID | MLX5_FLOW_ACTION_ENCAP)) {
9194                         dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST_REFORMAT;
9195                         dest_attr[idx]->dest_reformat = &dest_reformat[idx];
9196                         dest_attr[idx]->dest_reformat->reformat =
9197                                         sample_act->dr_encap_action;
9198                         dest_attr[idx]->dest_reformat->dest =
9199                                         sample_act->dr_port_id_action;
9200                 } else if (sample_act->action_flags ==
9201                            MLX5_FLOW_ACTION_PORT_ID) {
9202                         dest_attr[idx]->dest = sample_act->dr_port_id_action;
9203                 }
9204         }
9205         /* create a dest array actioin */
9206         ret = mlx5_os_flow_dr_create_flow_action_dest_array
9207                                                 (domain,
9208                                                  cache_resource->num_of_dest,
9209                                                  dest_attr,
9210                                                  &cache_resource->action);
9211         if (ret) {
9212                 rte_flow_error_set(error, ENOMEM,
9213                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9214                                    NULL,
9215                                    "cannot create destination array action");
9216                 goto error;
9217         }
9218         cache_resource->idx = res_idx;
9219         cache_resource->dev = dev;
9220         for (idx = 0; idx < resource->num_of_dest; idx++)
9221                 mlx5_free(dest_attr[idx]);
9222         return &cache_resource->entry;
9223 error:
9224         for (idx = 0; idx < resource->num_of_dest; idx++) {
9225                 struct mlx5_flow_sub_actions_idx *act_res =
9226                                         &cache_resource->sample_idx[idx];
9227                 if (act_res->rix_hrxq &&
9228                     !mlx5_hrxq_release(dev,
9229                                 act_res->rix_hrxq))
9230                         act_res->rix_hrxq = 0;
9231                 if (act_res->rix_encap_decap &&
9232                         !flow_dv_encap_decap_resource_release(dev,
9233                                 act_res->rix_encap_decap))
9234                         act_res->rix_encap_decap = 0;
9235                 if (act_res->rix_port_id_action &&
9236                         !flow_dv_port_id_action_resource_release(dev,
9237                                 act_res->rix_port_id_action))
9238                         act_res->rix_port_id_action = 0;
9239                 if (dest_attr[idx])
9240                         mlx5_free(dest_attr[idx]);
9241         }
9242
9243         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DEST_ARRAY], res_idx);
9244         return NULL;
9245 }
9246
9247 /**
9248  * Find existing destination array resource or create and register a new one.
9249  *
9250  * @param[in, out] dev
9251  *   Pointer to rte_eth_dev structure.
9252  * @param[in] resource
9253  *   Pointer to destination array resource.
9254  * @parm[in, out] dev_flow
9255  *   Pointer to the dev_flow.
9256  * @param[out] error
9257  *   pointer to error structure.
9258  *
9259  * @return
9260  *   0 on success otherwise -errno and errno is set.
9261  */
9262 static int
9263 flow_dv_dest_array_resource_register(struct rte_eth_dev *dev,
9264                          struct mlx5_flow_dv_dest_array_resource *resource,
9265                          struct mlx5_flow *dev_flow,
9266                          struct rte_flow_error *error)
9267 {
9268         struct mlx5_flow_dv_dest_array_resource *cache_resource;
9269         struct mlx5_priv *priv = dev->data->dev_private;
9270         struct mlx5_cache_entry *entry;
9271         struct mlx5_flow_cb_ctx ctx = {
9272                 .dev = dev,
9273                 .error = error,
9274                 .data = resource,
9275         };
9276
9277         entry = mlx5_cache_register(&priv->sh->dest_array_list, &ctx);
9278         if (!entry)
9279                 return -rte_errno;
9280         cache_resource = container_of(entry, typeof(*cache_resource), entry);
9281         dev_flow->handle->dvh.rix_dest_array = cache_resource->idx;
9282         dev_flow->dv.dest_array_res = cache_resource;
9283         return 0;
9284 }
9285
9286 /**
9287  * Convert Sample action to DV specification.
9288  *
9289  * @param[in] dev
9290  *   Pointer to rte_eth_dev structure.
9291  * @param[in] action
9292  *   Pointer to action structure.
9293  * @param[in, out] dev_flow
9294  *   Pointer to the mlx5_flow.
9295  * @param[in] attr
9296  *   Pointer to the flow attributes.
9297  * @param[in, out] num_of_dest
9298  *   Pointer to the num of destination.
9299  * @param[in, out] sample_actions
9300  *   Pointer to sample actions list.
9301  * @param[in, out] res
9302  *   Pointer to sample resource.
9303  * @param[out] error
9304  *   Pointer to the error structure.
9305  *
9306  * @return
9307  *   0 on success, a negative errno value otherwise and rte_errno is set.
9308  */
9309 static int
9310 flow_dv_translate_action_sample(struct rte_eth_dev *dev,
9311                                 const struct rte_flow_action *action,
9312                                 struct mlx5_flow *dev_flow,
9313                                 const struct rte_flow_attr *attr,
9314                                 uint32_t *num_of_dest,
9315                                 void **sample_actions,
9316                                 struct mlx5_flow_dv_sample_resource *res,
9317                                 struct rte_flow_error *error)
9318 {
9319         struct mlx5_priv *priv = dev->data->dev_private;
9320         const struct rte_flow_action_sample *sample_action;
9321         const struct rte_flow_action *sub_actions;
9322         const struct rte_flow_action_queue *queue;
9323         struct mlx5_flow_sub_actions_list *sample_act;
9324         struct mlx5_flow_sub_actions_idx *sample_idx;
9325         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
9326         struct mlx5_flow_rss_desc *rss_desc;
9327         uint64_t action_flags = 0;
9328
9329         MLX5_ASSERT(wks);
9330         rss_desc = &wks->rss_desc;
9331         sample_act = &res->sample_act;
9332         sample_idx = &res->sample_idx;
9333         sample_action = (const struct rte_flow_action_sample *)action->conf;
9334         res->ratio = sample_action->ratio;
9335         sub_actions = sample_action->actions;
9336         for (; sub_actions->type != RTE_FLOW_ACTION_TYPE_END; sub_actions++) {
9337                 int type = sub_actions->type;
9338                 uint32_t pre_rix = 0;
9339                 void *pre_r;
9340                 switch (type) {
9341                 case RTE_FLOW_ACTION_TYPE_QUEUE:
9342                 {
9343                         struct mlx5_hrxq *hrxq;
9344                         uint32_t hrxq_idx;
9345
9346                         queue = sub_actions->conf;
9347                         rss_desc->queue_num = 1;
9348                         rss_desc->queue[0] = queue->index;
9349                         hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
9350                                                     rss_desc, &hrxq_idx);
9351                         if (!hrxq)
9352                                 return rte_flow_error_set
9353                                         (error, rte_errno,
9354                                          RTE_FLOW_ERROR_TYPE_ACTION,
9355                                          NULL,
9356                                          "cannot create fate queue");
9357                         sample_act->dr_queue_action = hrxq->action;
9358                         sample_idx->rix_hrxq = hrxq_idx;
9359                         sample_actions[sample_act->actions_num++] =
9360                                                 hrxq->action;
9361                         (*num_of_dest)++;
9362                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
9363                         if (action_flags & MLX5_FLOW_ACTION_MARK)
9364                                 dev_flow->handle->rix_hrxq = hrxq_idx;
9365                         dev_flow->handle->fate_action =
9366                                         MLX5_FLOW_FATE_QUEUE;
9367                         break;
9368                 }
9369                 case RTE_FLOW_ACTION_TYPE_MARK:
9370                 {
9371                         uint32_t tag_be = mlx5_flow_mark_set
9372                                 (((const struct rte_flow_action_mark *)
9373                                 (sub_actions->conf))->id);
9374
9375                         dev_flow->handle->mark = 1;
9376                         pre_rix = dev_flow->handle->dvh.rix_tag;
9377                         /* Save the mark resource before sample */
9378                         pre_r = dev_flow->dv.tag_resource;
9379                         if (flow_dv_tag_resource_register(dev, tag_be,
9380                                                   dev_flow, error))
9381                                 return -rte_errno;
9382                         MLX5_ASSERT(dev_flow->dv.tag_resource);
9383                         sample_act->dr_tag_action =
9384                                 dev_flow->dv.tag_resource->action;
9385                         sample_idx->rix_tag =
9386                                 dev_flow->handle->dvh.rix_tag;
9387                         sample_actions[sample_act->actions_num++] =
9388                                                 sample_act->dr_tag_action;
9389                         /* Recover the mark resource after sample */
9390                         dev_flow->dv.tag_resource = pre_r;
9391                         dev_flow->handle->dvh.rix_tag = pre_rix;
9392                         action_flags |= MLX5_FLOW_ACTION_MARK;
9393                         break;
9394                 }
9395                 case RTE_FLOW_ACTION_TYPE_COUNT:
9396                 {
9397                         uint32_t counter;
9398
9399                         counter = flow_dv_translate_create_counter(dev,
9400                                         dev_flow, sub_actions->conf, 0);
9401                         if (!counter)
9402                                 return rte_flow_error_set
9403                                                 (error, rte_errno,
9404                                                  RTE_FLOW_ERROR_TYPE_ACTION,
9405                                                  NULL,
9406                                                  "cannot create counter"
9407                                                  " object.");
9408                         sample_idx->cnt = counter;
9409                         sample_act->dr_cnt_action =
9410                                   (flow_dv_counter_get_by_idx(dev,
9411                                   counter, NULL))->action;
9412                         sample_actions[sample_act->actions_num++] =
9413                                                 sample_act->dr_cnt_action;
9414                         action_flags |= MLX5_FLOW_ACTION_COUNT;
9415                         break;
9416                 }
9417                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
9418                 {
9419                         struct mlx5_flow_dv_port_id_action_resource
9420                                         port_id_resource;
9421                         uint32_t port_id = 0;
9422
9423                         memset(&port_id_resource, 0, sizeof(port_id_resource));
9424                         /* Save the port id resource before sample */
9425                         pre_rix = dev_flow->handle->rix_port_id_action;
9426                         pre_r = dev_flow->dv.port_id_action;
9427                         if (flow_dv_translate_action_port_id(dev, sub_actions,
9428                                                              &port_id, error))
9429                                 return -rte_errno;
9430                         port_id_resource.port_id = port_id;
9431                         if (flow_dv_port_id_action_resource_register
9432                             (dev, &port_id_resource, dev_flow, error))
9433                                 return -rte_errno;
9434                         sample_act->dr_port_id_action =
9435                                 dev_flow->dv.port_id_action->action;
9436                         sample_idx->rix_port_id_action =
9437                                 dev_flow->handle->rix_port_id_action;
9438                         sample_actions[sample_act->actions_num++] =
9439                                                 sample_act->dr_port_id_action;
9440                         /* Recover the port id resource after sample */
9441                         dev_flow->dv.port_id_action = pre_r;
9442                         dev_flow->handle->rix_port_id_action = pre_rix;
9443                         (*num_of_dest)++;
9444                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
9445                         break;
9446                 }
9447                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
9448                         /* Save the encap resource before sample */
9449                         pre_rix = dev_flow->handle->dvh.rix_encap_decap;
9450                         pre_r = dev_flow->dv.encap_decap;
9451                         if (flow_dv_create_action_l2_encap(dev, sub_actions,
9452                                                            dev_flow,
9453                                                            attr->transfer,
9454                                                            error))
9455                                 return -rte_errno;
9456                         sample_act->dr_encap_action =
9457                                 dev_flow->dv.encap_decap->action;
9458                         sample_idx->rix_encap_decap =
9459                                 dev_flow->handle->dvh.rix_encap_decap;
9460                         sample_actions[sample_act->actions_num++] =
9461                                                 sample_act->dr_encap_action;
9462                         /* Recover the encap resource after sample */
9463                         dev_flow->dv.encap_decap = pre_r;
9464                         dev_flow->handle->dvh.rix_encap_decap = pre_rix;
9465                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
9466                         break;
9467                 default:
9468                         return rte_flow_error_set(error, EINVAL,
9469                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9470                                 NULL,
9471                                 "Not support for sampler action");
9472                 }
9473         }
9474         sample_act->action_flags = action_flags;
9475         res->ft_id = dev_flow->dv.group;
9476         if (attr->transfer) {
9477                 union {
9478                         uint32_t action_in[MLX5_ST_SZ_DW(set_action_in)];
9479                         uint64_t set_action;
9480                 } action_ctx = { .set_action = 0 };
9481
9482                 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
9483                 MLX5_SET(set_action_in, action_ctx.action_in, action_type,
9484                          MLX5_MODIFICATION_TYPE_SET);
9485                 MLX5_SET(set_action_in, action_ctx.action_in, field,
9486                          MLX5_MODI_META_REG_C_0);
9487                 MLX5_SET(set_action_in, action_ctx.action_in, data,
9488                          priv->vport_meta_tag);
9489                 res->set_action = action_ctx.set_action;
9490         } else if (attr->ingress) {
9491                 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
9492         } else {
9493                 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_TX;
9494         }
9495         return 0;
9496 }
9497
9498 /**
9499  * Convert Sample action to DV specification.
9500  *
9501  * @param[in] dev
9502  *   Pointer to rte_eth_dev structure.
9503  * @param[in, out] dev_flow
9504  *   Pointer to the mlx5_flow.
9505  * @param[in] num_of_dest
9506  *   The num of destination.
9507  * @param[in, out] res
9508  *   Pointer to sample resource.
9509  * @param[in, out] mdest_res
9510  *   Pointer to destination array resource.
9511  * @param[in] sample_actions
9512  *   Pointer to sample path actions list.
9513  * @param[in] action_flags
9514  *   Holds the actions detected until now.
9515  * @param[out] error
9516  *   Pointer to the error structure.
9517  *
9518  * @return
9519  *   0 on success, a negative errno value otherwise and rte_errno is set.
9520  */
9521 static int
9522 flow_dv_create_action_sample(struct rte_eth_dev *dev,
9523                              struct mlx5_flow *dev_flow,
9524                              uint32_t num_of_dest,
9525                              struct mlx5_flow_dv_sample_resource *res,
9526                              struct mlx5_flow_dv_dest_array_resource *mdest_res,
9527                              void **sample_actions,
9528                              uint64_t action_flags,
9529                              struct rte_flow_error *error)
9530 {
9531         /* update normal path action resource into last index of array */
9532         uint32_t dest_index = MLX5_MAX_DEST_NUM - 1;
9533         struct mlx5_flow_sub_actions_list *sample_act =
9534                                         &mdest_res->sample_act[dest_index];
9535         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
9536         struct mlx5_flow_rss_desc *rss_desc;
9537         uint32_t normal_idx = 0;
9538         struct mlx5_hrxq *hrxq;
9539         uint32_t hrxq_idx;
9540
9541         MLX5_ASSERT(wks);
9542         rss_desc = &wks->rss_desc;
9543         if (num_of_dest > 1) {
9544                 if (sample_act->action_flags & MLX5_FLOW_ACTION_QUEUE) {
9545                         /* Handle QP action for mirroring */
9546                         hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
9547                                                     rss_desc, &hrxq_idx);
9548                         if (!hrxq)
9549                                 return rte_flow_error_set
9550                                      (error, rte_errno,
9551                                       RTE_FLOW_ERROR_TYPE_ACTION,
9552                                       NULL,
9553                                       "cannot create rx queue");
9554                         normal_idx++;
9555                         mdest_res->sample_idx[dest_index].rix_hrxq = hrxq_idx;
9556                         sample_act->dr_queue_action = hrxq->action;
9557                         if (action_flags & MLX5_FLOW_ACTION_MARK)
9558                                 dev_flow->handle->rix_hrxq = hrxq_idx;
9559                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
9560                 }
9561                 if (sample_act->action_flags & MLX5_FLOW_ACTION_ENCAP) {
9562                         normal_idx++;
9563                         mdest_res->sample_idx[dest_index].rix_encap_decap =
9564                                 dev_flow->handle->dvh.rix_encap_decap;
9565                         sample_act->dr_encap_action =
9566                                 dev_flow->dv.encap_decap->action;
9567                 }
9568                 if (sample_act->action_flags & MLX5_FLOW_ACTION_PORT_ID) {
9569                         normal_idx++;
9570                         mdest_res->sample_idx[dest_index].rix_port_id_action =
9571                                 dev_flow->handle->rix_port_id_action;
9572                         sample_act->dr_port_id_action =
9573                                 dev_flow->dv.port_id_action->action;
9574                 }
9575                 sample_act->actions_num = normal_idx;
9576                 /* update sample action resource into first index of array */
9577                 mdest_res->ft_type = res->ft_type;
9578                 memcpy(&mdest_res->sample_idx[0], &res->sample_idx,
9579                                 sizeof(struct mlx5_flow_sub_actions_idx));
9580                 memcpy(&mdest_res->sample_act[0], &res->sample_act,
9581                                 sizeof(struct mlx5_flow_sub_actions_list));
9582                 mdest_res->num_of_dest = num_of_dest;
9583                 if (flow_dv_dest_array_resource_register(dev, mdest_res,
9584                                                          dev_flow, error))
9585                         return rte_flow_error_set(error, EINVAL,
9586                                                   RTE_FLOW_ERROR_TYPE_ACTION,
9587                                                   NULL, "can't create sample "
9588                                                   "action");
9589         } else {
9590                 res->sub_actions = sample_actions;
9591                 if (flow_dv_sample_resource_register(dev, res, dev_flow, error))
9592                         return rte_flow_error_set(error, EINVAL,
9593                                                   RTE_FLOW_ERROR_TYPE_ACTION,
9594                                                   NULL,
9595                                                   "can't create sample action");
9596         }
9597         return 0;
9598 }
9599
9600 /**
9601  * Remove an ASO age action from age actions list.
9602  *
9603  * @param[in] dev
9604  *   Pointer to the Ethernet device structure.
9605  * @param[in] age
9606  *   Pointer to the aso age action handler.
9607  */
9608 static void
9609 flow_dv_aso_age_remove_from_age(struct rte_eth_dev *dev,
9610                                 struct mlx5_aso_age_action *age)
9611 {
9612         struct mlx5_age_info *age_info;
9613         struct mlx5_age_param *age_param = &age->age_params;
9614         struct mlx5_priv *priv = dev->data->dev_private;
9615         uint16_t expected = AGE_CANDIDATE;
9616
9617         age_info = GET_PORT_AGE_INFO(priv);
9618         if (!__atomic_compare_exchange_n(&age_param->state, &expected,
9619                                          AGE_FREE, false, __ATOMIC_RELAXED,
9620                                          __ATOMIC_RELAXED)) {
9621                 /**
9622                  * We need the lock even it is age timeout,
9623                  * since age action may still in process.
9624                  */
9625                 rte_spinlock_lock(&age_info->aged_sl);
9626                 LIST_REMOVE(age, next);
9627                 rte_spinlock_unlock(&age_info->aged_sl);
9628                 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
9629         }
9630 }
9631
9632 /**
9633  * Release an ASO age action.
9634  *
9635  * @param[in] dev
9636  *   Pointer to the Ethernet device structure.
9637  * @param[in] age_idx
9638  *   Index of ASO age action to release.
9639  * @param[in] flow
9640  *   True if the release operation is during flow destroy operation.
9641  *   False if the release operation is during action destroy operation.
9642  *
9643  * @return
9644  *   0 when age action was removed, otherwise the number of references.
9645  */
9646 static int
9647 flow_dv_aso_age_release(struct rte_eth_dev *dev, uint32_t age_idx)
9648 {
9649         struct mlx5_priv *priv = dev->data->dev_private;
9650         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
9651         struct mlx5_aso_age_action *age = flow_aso_age_get_by_idx(dev, age_idx);
9652         uint32_t ret = __atomic_sub_fetch(&age->refcnt, 1, __ATOMIC_RELAXED);
9653
9654         if (!ret) {
9655                 flow_dv_aso_age_remove_from_age(dev, age);
9656                 rte_spinlock_lock(&mng->free_sl);
9657                 LIST_INSERT_HEAD(&mng->free, age, next);
9658                 rte_spinlock_unlock(&mng->free_sl);
9659         }
9660         return ret;
9661 }
9662
9663 /**
9664  * Resize the ASO age pools array by MLX5_CNT_CONTAINER_RESIZE pools.
9665  *
9666  * @param[in] dev
9667  *   Pointer to the Ethernet device structure.
9668  *
9669  * @return
9670  *   0 on success, otherwise negative errno value and rte_errno is set.
9671  */
9672 static int
9673 flow_dv_aso_age_pools_resize(struct rte_eth_dev *dev)
9674 {
9675         struct mlx5_priv *priv = dev->data->dev_private;
9676         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
9677         void *old_pools = mng->pools;
9678         uint32_t resize = mng->n + MLX5_CNT_CONTAINER_RESIZE;
9679         uint32_t mem_size = sizeof(struct mlx5_aso_age_pool *) * resize;
9680         void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
9681
9682         if (!pools) {
9683                 rte_errno = ENOMEM;
9684                 return -ENOMEM;
9685         }
9686         if (old_pools) {
9687                 memcpy(pools, old_pools,
9688                        mng->n * sizeof(struct mlx5_flow_counter_pool *));
9689                 mlx5_free(old_pools);
9690         } else {
9691                 /* First ASO flow hit allocation - starting ASO data-path. */
9692                 int ret = mlx5_aso_queue_start(priv->sh);
9693
9694                 if (ret) {
9695                         mlx5_free(pools);
9696                         return ret;
9697                 }
9698         }
9699         mng->n = resize;
9700         mng->pools = pools;
9701         return 0;
9702 }
9703
9704 /**
9705  * Create and initialize a new ASO aging pool.
9706  *
9707  * @param[in] dev
9708  *   Pointer to the Ethernet device structure.
9709  * @param[out] age_free
9710  *   Where to put the pointer of a new age action.
9711  *
9712  * @return
9713  *   The age actions pool pointer and @p age_free is set on success,
9714  *   NULL otherwise and rte_errno is set.
9715  */
9716 static struct mlx5_aso_age_pool *
9717 flow_dv_age_pool_create(struct rte_eth_dev *dev,
9718                         struct mlx5_aso_age_action **age_free)
9719 {
9720         struct mlx5_priv *priv = dev->data->dev_private;
9721         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
9722         struct mlx5_aso_age_pool *pool = NULL;
9723         struct mlx5_devx_obj *obj = NULL;
9724         uint32_t i;
9725
9726         obj = mlx5_devx_cmd_create_flow_hit_aso_obj(priv->sh->ctx,
9727                                                     priv->sh->pdn);
9728         if (!obj) {
9729                 rte_errno = ENODATA;
9730                 DRV_LOG(ERR, "Failed to create flow_hit_aso_obj using DevX.");
9731                 return NULL;
9732         }
9733         pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
9734         if (!pool) {
9735                 claim_zero(mlx5_devx_cmd_destroy(obj));
9736                 rte_errno = ENOMEM;
9737                 return NULL;
9738         }
9739         pool->flow_hit_aso_obj = obj;
9740         pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
9741         rte_spinlock_lock(&mng->resize_sl);
9742         pool->index = mng->next;
9743         /* Resize pools array if there is no room for the new pool in it. */
9744         if (pool->index == mng->n && flow_dv_aso_age_pools_resize(dev)) {
9745                 claim_zero(mlx5_devx_cmd_destroy(obj));
9746                 mlx5_free(pool);
9747                 rte_spinlock_unlock(&mng->resize_sl);
9748                 return NULL;
9749         }
9750         mng->pools[pool->index] = pool;
9751         mng->next++;
9752         rte_spinlock_unlock(&mng->resize_sl);
9753         /* Assign the first action in the new pool, the rest go to free list. */
9754         *age_free = &pool->actions[0];
9755         for (i = 1; i < MLX5_ASO_AGE_ACTIONS_PER_POOL; i++) {
9756                 pool->actions[i].offset = i;
9757                 LIST_INSERT_HEAD(&mng->free, &pool->actions[i], next);
9758         }
9759         return pool;
9760 }
9761
9762 /**
9763  * Allocate a ASO aging bit.
9764  *
9765  * @param[in] dev
9766  *   Pointer to the Ethernet device structure.
9767  * @param[out] error
9768  *   Pointer to the error structure.
9769  *
9770  * @return
9771  *   Index to ASO age action on success, 0 otherwise and rte_errno is set.
9772  */
9773 static uint32_t
9774 flow_dv_aso_age_alloc(struct rte_eth_dev *dev, struct rte_flow_error *error)
9775 {
9776         struct mlx5_priv *priv = dev->data->dev_private;
9777         const struct mlx5_aso_age_pool *pool;
9778         struct mlx5_aso_age_action *age_free = NULL;
9779         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
9780
9781         MLX5_ASSERT(mng);
9782         /* Try to get the next free age action bit. */
9783         rte_spinlock_lock(&mng->free_sl);
9784         age_free = LIST_FIRST(&mng->free);
9785         if (age_free) {
9786                 LIST_REMOVE(age_free, next);
9787         } else if (!flow_dv_age_pool_create(dev, &age_free)) {
9788                 rte_spinlock_unlock(&mng->free_sl);
9789                 rte_flow_error_set(error, rte_errno, RTE_FLOW_ERROR_TYPE_ACTION,
9790                                    NULL, "failed to create ASO age pool");
9791                 return 0; /* 0 is an error. */
9792         }
9793         rte_spinlock_unlock(&mng->free_sl);
9794         pool = container_of
9795           ((const struct mlx5_aso_age_action (*)[MLX5_ASO_AGE_ACTIONS_PER_POOL])
9796                   (age_free - age_free->offset), const struct mlx5_aso_age_pool,
9797                                                                        actions);
9798         if (!age_free->dr_action) {
9799                 int reg_c = mlx5_flow_get_reg_id(dev, MLX5_ASO_FLOW_HIT, 0,
9800                                                  error);
9801
9802                 if (reg_c < 0) {
9803                         rte_flow_error_set(error, rte_errno,
9804                                            RTE_FLOW_ERROR_TYPE_ACTION,
9805                                            NULL, "failed to get reg_c "
9806                                            "for ASO flow hit");
9807                         return 0; /* 0 is an error. */
9808                 }
9809 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
9810                 age_free->dr_action = mlx5_glue->dv_create_flow_action_aso
9811                                 (priv->sh->rx_domain,
9812                                  pool->flow_hit_aso_obj->obj, age_free->offset,
9813                                  MLX5DV_DR_ACTION_FLAGS_ASO_FIRST_HIT_SET,
9814                                  (reg_c - REG_C_0));
9815 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
9816                 if (!age_free->dr_action) {
9817                         rte_errno = errno;
9818                         rte_spinlock_lock(&mng->free_sl);
9819                         LIST_INSERT_HEAD(&mng->free, age_free, next);
9820                         rte_spinlock_unlock(&mng->free_sl);
9821                         rte_flow_error_set(error, rte_errno,
9822                                            RTE_FLOW_ERROR_TYPE_ACTION,
9823                                            NULL, "failed to create ASO "
9824                                            "flow hit action");
9825                         return 0; /* 0 is an error. */
9826                 }
9827         }
9828         __atomic_store_n(&age_free->refcnt, 1, __ATOMIC_RELAXED);
9829         return pool->index | ((age_free->offset + 1) << 16);
9830 }
9831
9832 /**
9833  * Create a age action using ASO mechanism.
9834  *
9835  * @param[in] dev
9836  *   Pointer to rte_eth_dev structure.
9837  * @param[in] age
9838  *   Pointer to the aging action configuration.
9839  * @param[out] error
9840  *   Pointer to the error structure.
9841  *
9842  * @return
9843  *   Index to flow counter on success, 0 otherwise.
9844  */
9845 static uint32_t
9846 flow_dv_translate_create_aso_age(struct rte_eth_dev *dev,
9847                                  const struct rte_flow_action_age *age,
9848                                  struct rte_flow_error *error)
9849 {
9850         uint32_t age_idx = 0;
9851         struct mlx5_aso_age_action *aso_age;
9852
9853         age_idx = flow_dv_aso_age_alloc(dev, error);
9854         if (!age_idx)
9855                 return 0;
9856         aso_age = flow_aso_age_get_by_idx(dev, age_idx);
9857         aso_age->age_params.context = age->context;
9858         aso_age->age_params.timeout = age->timeout;
9859         aso_age->age_params.port_id = dev->data->port_id;
9860         __atomic_store_n(&aso_age->age_params.sec_since_last_hit, 0,
9861                          __ATOMIC_RELAXED);
9862         __atomic_store_n(&aso_age->age_params.state, AGE_CANDIDATE,
9863                          __ATOMIC_RELAXED);
9864         return age_idx;
9865 }
9866
9867 /**
9868  * Fill the flow with DV spec, lock free
9869  * (mutex should be acquired by caller).
9870  *
9871  * @param[in] dev
9872  *   Pointer to rte_eth_dev structure.
9873  * @param[in, out] dev_flow
9874  *   Pointer to the sub flow.
9875  * @param[in] attr
9876  *   Pointer to the flow attributes.
9877  * @param[in] items
9878  *   Pointer to the list of items.
9879  * @param[in] actions
9880  *   Pointer to the list of actions.
9881  * @param[out] error
9882  *   Pointer to the error structure.
9883  *
9884  * @return
9885  *   0 on success, a negative errno value otherwise and rte_errno is set.
9886  */
9887 static int
9888 flow_dv_translate(struct rte_eth_dev *dev,
9889                   struct mlx5_flow *dev_flow,
9890                   const struct rte_flow_attr *attr,
9891                   const struct rte_flow_item items[],
9892                   const struct rte_flow_action actions[],
9893                   struct rte_flow_error *error)
9894 {
9895         struct mlx5_priv *priv = dev->data->dev_private;
9896         struct mlx5_dev_config *dev_conf = &priv->config;
9897         struct rte_flow *flow = dev_flow->flow;
9898         struct mlx5_flow_handle *handle = dev_flow->handle;
9899         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
9900         struct mlx5_flow_rss_desc *rss_desc;
9901         uint64_t item_flags = 0;
9902         uint64_t last_item = 0;
9903         uint64_t action_flags = 0;
9904         uint64_t priority = attr->priority;
9905         struct mlx5_flow_dv_matcher matcher = {
9906                 .mask = {
9907                         .size = sizeof(matcher.mask.buf) -
9908                                 MLX5_ST_SZ_BYTES(fte_match_set_misc4),
9909                 },
9910         };
9911         int actions_n = 0;
9912         bool actions_end = false;
9913         union {
9914                 struct mlx5_flow_dv_modify_hdr_resource res;
9915                 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
9916                             sizeof(struct mlx5_modification_cmd) *
9917                             (MLX5_MAX_MODIFY_NUM + 1)];
9918         } mhdr_dummy;
9919         struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
9920         const struct rte_flow_action_count *count = NULL;
9921         const struct rte_flow_action_age *age = NULL;
9922         union flow_dv_attr flow_attr = { .attr = 0 };
9923         uint32_t tag_be;
9924         union mlx5_flow_tbl_key tbl_key;
9925         uint32_t modify_action_position = UINT32_MAX;
9926         void *match_mask = matcher.mask.buf;
9927         void *match_value = dev_flow->dv.value.buf;
9928         uint8_t next_protocol = 0xff;
9929         struct rte_vlan_hdr vlan = { 0 };
9930         struct mlx5_flow_dv_dest_array_resource mdest_res;
9931         struct mlx5_flow_dv_sample_resource sample_res;
9932         void *sample_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
9933         struct mlx5_flow_sub_actions_list *sample_act;
9934         uint32_t sample_act_pos = UINT32_MAX;
9935         uint32_t num_of_dest = 0;
9936         int tmp_actions_n = 0;
9937         uint32_t table;
9938         int ret = 0;
9939         const struct mlx5_flow_tunnel *tunnel;
9940         struct flow_grp_info grp_info = {
9941                 .external = !!dev_flow->external,
9942                 .transfer = !!attr->transfer,
9943                 .fdb_def_rule = !!priv->fdb_def_rule,
9944                 .skip_scale = !!dev_flow->skip_scale,
9945         };
9946
9947         if (!wks)
9948                 return rte_flow_error_set(error, ENOMEM,
9949                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9950                                           NULL,
9951                                           "failed to push flow workspace");
9952         rss_desc = &wks->rss_desc;
9953         memset(&mdest_res, 0, sizeof(struct mlx5_flow_dv_dest_array_resource));
9954         memset(&sample_res, 0, sizeof(struct mlx5_flow_dv_sample_resource));
9955         mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
9956                                            MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
9957         /* update normal path action resource into last index of array */
9958         sample_act = &mdest_res.sample_act[MLX5_MAX_DEST_NUM - 1];
9959         tunnel = is_flow_tunnel_match_rule(dev, attr, items, actions) ?
9960                  flow_items_to_tunnel(items) :
9961                  is_flow_tunnel_steer_rule(dev, attr, items, actions) ?
9962                  flow_actions_to_tunnel(actions) :
9963                  dev_flow->tunnel ? dev_flow->tunnel : NULL;
9964         mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
9965                                            MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
9966         grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
9967                                 (dev, tunnel, attr, items, actions);
9968         ret = mlx5_flow_group_to_table(dev, tunnel, attr->group, &table,
9969                                        &grp_info, error);
9970         if (ret)
9971                 return ret;
9972         dev_flow->dv.group = table;
9973         if (attr->transfer)
9974                 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
9975         if (priority == MLX5_FLOW_PRIO_RSVD)
9976                 priority = dev_conf->flow_prio - 1;
9977         /* number of actions must be set to 0 in case of dirty stack. */
9978         mhdr_res->actions_num = 0;
9979         if (is_flow_tunnel_match_rule(dev, attr, items, actions)) {
9980                 /*
9981                  * do not add decap action if match rule drops packet
9982                  * HW rejects rules with decap & drop
9983                  *
9984                  * if tunnel match rule was inserted before matching tunnel set
9985                  * rule flow table used in the match rule must be registered.
9986                  * current implementation handles that in the
9987                  * flow_dv_match_register() at the function end.
9988                  */
9989                 bool add_decap = true;
9990                 const struct rte_flow_action *ptr = actions;
9991
9992                 for (; ptr->type != RTE_FLOW_ACTION_TYPE_END; ptr++) {
9993                         if (ptr->type == RTE_FLOW_ACTION_TYPE_DROP) {
9994                                 add_decap = false;
9995                                 break;
9996                         }
9997                 }
9998                 if (add_decap) {
9999                         if (flow_dv_create_action_l2_decap(dev, dev_flow,
10000                                                            attr->transfer,
10001                                                            error))
10002                                 return -rte_errno;
10003                         dev_flow->dv.actions[actions_n++] =
10004                                         dev_flow->dv.encap_decap->action;
10005                         action_flags |= MLX5_FLOW_ACTION_DECAP;
10006                 }
10007         }
10008         for (; !actions_end ; actions++) {
10009                 const struct rte_flow_action_queue *queue;
10010                 const struct rte_flow_action_rss *rss;
10011                 const struct rte_flow_action *action = actions;
10012                 const uint8_t *rss_key;
10013                 const struct rte_flow_action_meter *mtr;
10014                 struct mlx5_flow_tbl_resource *tbl;
10015                 struct mlx5_aso_age_action *age_act;
10016                 uint32_t port_id = 0;
10017                 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
10018                 int action_type = actions->type;
10019                 const struct rte_flow_action *found_action = NULL;
10020                 struct mlx5_flow_meter *fm = NULL;
10021                 uint32_t jump_group = 0;
10022
10023                 if (!mlx5_flow_os_action_supported(action_type))
10024                         return rte_flow_error_set(error, ENOTSUP,
10025                                                   RTE_FLOW_ERROR_TYPE_ACTION,
10026                                                   actions,
10027                                                   "action not supported");
10028                 switch (action_type) {
10029                 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
10030                         action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
10031                         break;
10032                 case RTE_FLOW_ACTION_TYPE_VOID:
10033                         break;
10034                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
10035                         if (flow_dv_translate_action_port_id(dev, action,
10036                                                              &port_id, error))
10037                                 return -rte_errno;
10038                         port_id_resource.port_id = port_id;
10039                         MLX5_ASSERT(!handle->rix_port_id_action);
10040                         if (flow_dv_port_id_action_resource_register
10041                             (dev, &port_id_resource, dev_flow, error))
10042                                 return -rte_errno;
10043                         dev_flow->dv.actions[actions_n++] =
10044                                         dev_flow->dv.port_id_action->action;
10045                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
10046                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_PORT_ID;
10047                         sample_act->action_flags |= MLX5_FLOW_ACTION_PORT_ID;
10048                         num_of_dest++;
10049                         break;
10050                 case RTE_FLOW_ACTION_TYPE_FLAG:
10051                         action_flags |= MLX5_FLOW_ACTION_FLAG;
10052                         dev_flow->handle->mark = 1;
10053                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
10054                                 struct rte_flow_action_mark mark = {
10055                                         .id = MLX5_FLOW_MARK_DEFAULT,
10056                                 };
10057
10058                                 if (flow_dv_convert_action_mark(dev, &mark,
10059                                                                 mhdr_res,
10060                                                                 error))
10061                                         return -rte_errno;
10062                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
10063                                 break;
10064                         }
10065                         tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
10066                         /*
10067                          * Only one FLAG or MARK is supported per device flow
10068                          * right now. So the pointer to the tag resource must be
10069                          * zero before the register process.
10070                          */
10071                         MLX5_ASSERT(!handle->dvh.rix_tag);
10072                         if (flow_dv_tag_resource_register(dev, tag_be,
10073                                                           dev_flow, error))
10074                                 return -rte_errno;
10075                         MLX5_ASSERT(dev_flow->dv.tag_resource);
10076                         dev_flow->dv.actions[actions_n++] =
10077                                         dev_flow->dv.tag_resource->action;
10078                         break;
10079                 case RTE_FLOW_ACTION_TYPE_MARK:
10080                         action_flags |= MLX5_FLOW_ACTION_MARK;
10081                         dev_flow->handle->mark = 1;
10082                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
10083                                 const struct rte_flow_action_mark *mark =
10084                                         (const struct rte_flow_action_mark *)
10085                                                 actions->conf;
10086
10087                                 if (flow_dv_convert_action_mark(dev, mark,
10088                                                                 mhdr_res,
10089                                                                 error))
10090                                         return -rte_errno;
10091                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
10092                                 break;
10093                         }
10094                         /* Fall-through */
10095                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
10096                         /* Legacy (non-extensive) MARK action. */
10097                         tag_be = mlx5_flow_mark_set
10098                               (((const struct rte_flow_action_mark *)
10099                                (actions->conf))->id);
10100                         MLX5_ASSERT(!handle->dvh.rix_tag);
10101                         if (flow_dv_tag_resource_register(dev, tag_be,
10102                                                           dev_flow, error))
10103                                 return -rte_errno;
10104                         MLX5_ASSERT(dev_flow->dv.tag_resource);
10105                         dev_flow->dv.actions[actions_n++] =
10106                                         dev_flow->dv.tag_resource->action;
10107                         break;
10108                 case RTE_FLOW_ACTION_TYPE_SET_META:
10109                         if (flow_dv_convert_action_set_meta
10110                                 (dev, mhdr_res, attr,
10111                                  (const struct rte_flow_action_set_meta *)
10112                                   actions->conf, error))
10113                                 return -rte_errno;
10114                         action_flags |= MLX5_FLOW_ACTION_SET_META;
10115                         break;
10116                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
10117                         if (flow_dv_convert_action_set_tag
10118                                 (dev, mhdr_res,
10119                                  (const struct rte_flow_action_set_tag *)
10120                                   actions->conf, error))
10121                                 return -rte_errno;
10122                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
10123                         break;
10124                 case RTE_FLOW_ACTION_TYPE_DROP:
10125                         action_flags |= MLX5_FLOW_ACTION_DROP;
10126                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_DROP;
10127                         break;
10128                 case RTE_FLOW_ACTION_TYPE_QUEUE:
10129                         queue = actions->conf;
10130                         rss_desc->queue_num = 1;
10131                         rss_desc->queue[0] = queue->index;
10132                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
10133                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
10134                         sample_act->action_flags |= MLX5_FLOW_ACTION_QUEUE;
10135                         num_of_dest++;
10136                         break;
10137                 case RTE_FLOW_ACTION_TYPE_RSS:
10138                         rss = actions->conf;
10139                         memcpy(rss_desc->queue, rss->queue,
10140                                rss->queue_num * sizeof(uint16_t));
10141                         rss_desc->queue_num = rss->queue_num;
10142                         /* NULL RSS key indicates default RSS key. */
10143                         rss_key = !rss->key ? rss_hash_default_key : rss->key;
10144                         memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
10145                         /*
10146                          * rss->level and rss.types should be set in advance
10147                          * when expanding items for RSS.
10148                          */
10149                         action_flags |= MLX5_FLOW_ACTION_RSS;
10150                         dev_flow->handle->fate_action = rss_desc->shared_rss ?
10151                                 MLX5_FLOW_FATE_SHARED_RSS :
10152                                 MLX5_FLOW_FATE_QUEUE;
10153                         break;
10154                 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
10155                         flow->age = (uint32_t)(uintptr_t)(action->conf);
10156                         age_act = flow_aso_age_get_by_idx(dev, flow->age);
10157                         __atomic_fetch_add(&age_act->refcnt, 1,
10158                                            __ATOMIC_RELAXED);
10159                         dev_flow->dv.actions[actions_n++] = age_act->dr_action;
10160                         action_flags |= MLX5_FLOW_ACTION_AGE;
10161                         break;
10162                 case RTE_FLOW_ACTION_TYPE_AGE:
10163                         if (priv->sh->flow_hit_aso_en && attr->group) {
10164                                 flow->age = flow_dv_translate_create_aso_age
10165                                                 (dev, action->conf, error);
10166                                 if (!flow->age)
10167                                         return rte_flow_error_set
10168                                                 (error, rte_errno,
10169                                                  RTE_FLOW_ERROR_TYPE_ACTION,
10170                                                  NULL,
10171                                                  "can't create ASO age action");
10172                                 dev_flow->dv.actions[actions_n++] =
10173                                           (flow_aso_age_get_by_idx
10174                                                 (dev, flow->age))->dr_action;
10175                                 action_flags |= MLX5_FLOW_ACTION_AGE;
10176                                 break;
10177                         }
10178                         /* Fall-through */
10179                 case RTE_FLOW_ACTION_TYPE_COUNT:
10180                         if (!dev_conf->devx) {
10181                                 return rte_flow_error_set
10182                                               (error, ENOTSUP,
10183                                                RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10184                                                NULL,
10185                                                "count action not supported");
10186                         }
10187                         /* Save information first, will apply later. */
10188                         if (actions->type == RTE_FLOW_ACTION_TYPE_COUNT)
10189                                 count = action->conf;
10190                         else
10191                                 age = action->conf;
10192                         action_flags |= MLX5_FLOW_ACTION_COUNT;
10193                         break;
10194                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
10195                         dev_flow->dv.actions[actions_n++] =
10196                                                 priv->sh->pop_vlan_action;
10197                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
10198                         break;
10199                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
10200                         if (!(action_flags &
10201                               MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
10202                                 flow_dev_get_vlan_info_from_items(items, &vlan);
10203                         vlan.eth_proto = rte_be_to_cpu_16
10204                              ((((const struct rte_flow_action_of_push_vlan *)
10205                                                    actions->conf)->ethertype));
10206                         found_action = mlx5_flow_find_action
10207                                         (actions + 1,
10208                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
10209                         if (found_action)
10210                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
10211                         found_action = mlx5_flow_find_action
10212                                         (actions + 1,
10213                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
10214                         if (found_action)
10215                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
10216                         if (flow_dv_create_action_push_vlan
10217                                             (dev, attr, &vlan, dev_flow, error))
10218                                 return -rte_errno;
10219                         dev_flow->dv.actions[actions_n++] =
10220                                         dev_flow->dv.push_vlan_res->action;
10221                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
10222                         break;
10223                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
10224                         /* of_vlan_push action handled this action */
10225                         MLX5_ASSERT(action_flags &
10226                                     MLX5_FLOW_ACTION_OF_PUSH_VLAN);
10227                         break;
10228                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
10229                         if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
10230                                 break;
10231                         flow_dev_get_vlan_info_from_items(items, &vlan);
10232                         mlx5_update_vlan_vid_pcp(actions, &vlan);
10233                         /* If no VLAN push - this is a modify header action */
10234                         if (flow_dv_convert_action_modify_vlan_vid
10235                                                 (mhdr_res, actions, error))
10236                                 return -rte_errno;
10237                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
10238                         break;
10239                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
10240                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
10241                         if (flow_dv_create_action_l2_encap(dev, actions,
10242                                                            dev_flow,
10243                                                            attr->transfer,
10244                                                            error))
10245                                 return -rte_errno;
10246                         dev_flow->dv.actions[actions_n++] =
10247                                         dev_flow->dv.encap_decap->action;
10248                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
10249                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
10250                                 sample_act->action_flags |=
10251                                                         MLX5_FLOW_ACTION_ENCAP;
10252                         break;
10253                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
10254                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
10255                         if (flow_dv_create_action_l2_decap(dev, dev_flow,
10256                                                            attr->transfer,
10257                                                            error))
10258                                 return -rte_errno;
10259                         dev_flow->dv.actions[actions_n++] =
10260                                         dev_flow->dv.encap_decap->action;
10261                         action_flags |= MLX5_FLOW_ACTION_DECAP;
10262                         break;
10263                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
10264                         /* Handle encap with preceding decap. */
10265                         if (action_flags & MLX5_FLOW_ACTION_DECAP) {
10266                                 if (flow_dv_create_action_raw_encap
10267                                         (dev, actions, dev_flow, attr, error))
10268                                         return -rte_errno;
10269                                 dev_flow->dv.actions[actions_n++] =
10270                                         dev_flow->dv.encap_decap->action;
10271                         } else {
10272                                 /* Handle encap without preceding decap. */
10273                                 if (flow_dv_create_action_l2_encap
10274                                     (dev, actions, dev_flow, attr->transfer,
10275                                      error))
10276                                         return -rte_errno;
10277                                 dev_flow->dv.actions[actions_n++] =
10278                                         dev_flow->dv.encap_decap->action;
10279                         }
10280                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
10281                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
10282                                 sample_act->action_flags |=
10283                                                         MLX5_FLOW_ACTION_ENCAP;
10284                         break;
10285                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
10286                         while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
10287                                 ;
10288                         if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
10289                                 if (flow_dv_create_action_l2_decap
10290                                     (dev, dev_flow, attr->transfer, error))
10291                                         return -rte_errno;
10292                                 dev_flow->dv.actions[actions_n++] =
10293                                         dev_flow->dv.encap_decap->action;
10294                         }
10295                         /* If decap is followed by encap, handle it at encap. */
10296                         action_flags |= MLX5_FLOW_ACTION_DECAP;
10297                         break;
10298                 case RTE_FLOW_ACTION_TYPE_JUMP:
10299                         jump_group = ((const struct rte_flow_action_jump *)
10300                                                         action->conf)->group;
10301                         grp_info.std_tbl_fix = 0;
10302                         grp_info.skip_scale = 0;
10303                         ret = mlx5_flow_group_to_table(dev, tunnel,
10304                                                        jump_group,
10305                                                        &table,
10306                                                        &grp_info, error);
10307                         if (ret)
10308                                 return ret;
10309                         tbl = flow_dv_tbl_resource_get(dev, table, attr->egress,
10310                                                        attr->transfer,
10311                                                        !!dev_flow->external,
10312                                                        tunnel, jump_group, 0,
10313                                                        error);
10314                         if (!tbl)
10315                                 return rte_flow_error_set
10316                                                 (error, errno,
10317                                                  RTE_FLOW_ERROR_TYPE_ACTION,
10318                                                  NULL,
10319                                                  "cannot create jump action.");
10320                         if (flow_dv_jump_tbl_resource_register
10321                             (dev, tbl, dev_flow, error)) {
10322                                 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
10323                                 return rte_flow_error_set
10324                                                 (error, errno,
10325                                                  RTE_FLOW_ERROR_TYPE_ACTION,
10326                                                  NULL,
10327                                                  "cannot create jump action.");
10328                         }
10329                         dev_flow->dv.actions[actions_n++] =
10330                                         dev_flow->dv.jump->action;
10331                         action_flags |= MLX5_FLOW_ACTION_JUMP;
10332                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_JUMP;
10333                         break;
10334                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
10335                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
10336                         if (flow_dv_convert_action_modify_mac
10337                                         (mhdr_res, actions, error))
10338                                 return -rte_errno;
10339                         action_flags |= actions->type ==
10340                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
10341                                         MLX5_FLOW_ACTION_SET_MAC_SRC :
10342                                         MLX5_FLOW_ACTION_SET_MAC_DST;
10343                         break;
10344                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
10345                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
10346                         if (flow_dv_convert_action_modify_ipv4
10347                                         (mhdr_res, actions, error))
10348                                 return -rte_errno;
10349                         action_flags |= actions->type ==
10350                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
10351                                         MLX5_FLOW_ACTION_SET_IPV4_SRC :
10352                                         MLX5_FLOW_ACTION_SET_IPV4_DST;
10353                         break;
10354                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
10355                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
10356                         if (flow_dv_convert_action_modify_ipv6
10357                                         (mhdr_res, actions, error))
10358                                 return -rte_errno;
10359                         action_flags |= actions->type ==
10360                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
10361                                         MLX5_FLOW_ACTION_SET_IPV6_SRC :
10362                                         MLX5_FLOW_ACTION_SET_IPV6_DST;
10363                         break;
10364                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
10365                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
10366                         if (flow_dv_convert_action_modify_tp
10367                                         (mhdr_res, actions, items,
10368                                          &flow_attr, dev_flow, !!(action_flags &
10369                                          MLX5_FLOW_ACTION_DECAP), error))
10370                                 return -rte_errno;
10371                         action_flags |= actions->type ==
10372                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
10373                                         MLX5_FLOW_ACTION_SET_TP_SRC :
10374                                         MLX5_FLOW_ACTION_SET_TP_DST;
10375                         break;
10376                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
10377                         if (flow_dv_convert_action_modify_dec_ttl
10378                                         (mhdr_res, items, &flow_attr, dev_flow,
10379                                          !!(action_flags &
10380                                          MLX5_FLOW_ACTION_DECAP), error))
10381                                 return -rte_errno;
10382                         action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
10383                         break;
10384                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
10385                         if (flow_dv_convert_action_modify_ttl
10386                                         (mhdr_res, actions, items, &flow_attr,
10387                                          dev_flow, !!(action_flags &
10388                                          MLX5_FLOW_ACTION_DECAP), error))
10389                                 return -rte_errno;
10390                         action_flags |= MLX5_FLOW_ACTION_SET_TTL;
10391                         break;
10392                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
10393                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
10394                         if (flow_dv_convert_action_modify_tcp_seq
10395                                         (mhdr_res, actions, error))
10396                                 return -rte_errno;
10397                         action_flags |= actions->type ==
10398                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
10399                                         MLX5_FLOW_ACTION_INC_TCP_SEQ :
10400                                         MLX5_FLOW_ACTION_DEC_TCP_SEQ;
10401                         break;
10402
10403                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
10404                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
10405                         if (flow_dv_convert_action_modify_tcp_ack
10406                                         (mhdr_res, actions, error))
10407                                 return -rte_errno;
10408                         action_flags |= actions->type ==
10409                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
10410                                         MLX5_FLOW_ACTION_INC_TCP_ACK :
10411                                         MLX5_FLOW_ACTION_DEC_TCP_ACK;
10412                         break;
10413                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
10414                         if (flow_dv_convert_action_set_reg
10415                                         (mhdr_res, actions, error))
10416                                 return -rte_errno;
10417                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
10418                         break;
10419                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
10420                         if (flow_dv_convert_action_copy_mreg
10421                                         (dev, mhdr_res, actions, error))
10422                                 return -rte_errno;
10423                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
10424                         break;
10425                 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
10426                         action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
10427                         dev_flow->handle->fate_action =
10428                                         MLX5_FLOW_FATE_DEFAULT_MISS;
10429                         break;
10430                 case RTE_FLOW_ACTION_TYPE_METER:
10431                         mtr = actions->conf;
10432                         if (!flow->meter) {
10433                                 fm = mlx5_flow_meter_attach(priv, mtr->mtr_id,
10434                                                             attr, error);
10435                                 if (!fm)
10436                                         return rte_flow_error_set(error,
10437                                                 rte_errno,
10438                                                 RTE_FLOW_ERROR_TYPE_ACTION,
10439                                                 NULL,
10440                                                 "meter not found "
10441                                                 "or invalid parameters");
10442                                 flow->meter = fm->idx;
10443                         }
10444                         /* Set the meter action. */
10445                         if (!fm) {
10446                                 fm = mlx5_ipool_get(priv->sh->ipool
10447                                                 [MLX5_IPOOL_MTR], flow->meter);
10448                                 if (!fm)
10449                                         return rte_flow_error_set(error,
10450                                                 rte_errno,
10451                                                 RTE_FLOW_ERROR_TYPE_ACTION,
10452                                                 NULL,
10453                                                 "meter not found "
10454                                                 "or invalid parameters");
10455                         }
10456                         dev_flow->dv.actions[actions_n++] =
10457                                 fm->mfts->meter_action;
10458                         action_flags |= MLX5_FLOW_ACTION_METER;
10459                         break;
10460                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
10461                         if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
10462                                                               actions, error))
10463                                 return -rte_errno;
10464                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
10465                         break;
10466                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
10467                         if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
10468                                                               actions, error))
10469                                 return -rte_errno;
10470                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
10471                         break;
10472                 case RTE_FLOW_ACTION_TYPE_SAMPLE:
10473                         sample_act_pos = actions_n;
10474                         ret = flow_dv_translate_action_sample(dev,
10475                                                               actions,
10476                                                               dev_flow, attr,
10477                                                               &num_of_dest,
10478                                                               sample_actions,
10479                                                               &sample_res,
10480                                                               error);
10481                         if (ret < 0)
10482                                 return ret;
10483                         actions_n++;
10484                         action_flags |= MLX5_FLOW_ACTION_SAMPLE;
10485                         /* put encap action into group if work with port id */
10486                         if ((action_flags & MLX5_FLOW_ACTION_ENCAP) &&
10487                             (action_flags & MLX5_FLOW_ACTION_PORT_ID))
10488                                 sample_act->action_flags |=
10489                                                         MLX5_FLOW_ACTION_ENCAP;
10490                         break;
10491                 case RTE_FLOW_ACTION_TYPE_END:
10492                         actions_end = true;
10493                         if (mhdr_res->actions_num) {
10494                                 /* create modify action if needed. */
10495                                 if (flow_dv_modify_hdr_resource_register
10496                                         (dev, mhdr_res, dev_flow, error))
10497                                         return -rte_errno;
10498                                 dev_flow->dv.actions[modify_action_position] =
10499                                         handle->dvh.modify_hdr->action;
10500                         }
10501                         if (action_flags & MLX5_FLOW_ACTION_COUNT) {
10502                                 flow->counter =
10503                                         flow_dv_translate_create_counter(dev,
10504                                                 dev_flow, count, age);
10505
10506                                 if (!flow->counter)
10507                                         return rte_flow_error_set
10508                                                 (error, rte_errno,
10509                                                 RTE_FLOW_ERROR_TYPE_ACTION,
10510                                                 NULL,
10511                                                 "cannot create counter"
10512                                                 " object.");
10513                                 dev_flow->dv.actions[actions_n] =
10514                                           (flow_dv_counter_get_by_idx(dev,
10515                                           flow->counter, NULL))->action;
10516                                 actions_n++;
10517                         }
10518                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE) {
10519                                 ret = flow_dv_create_action_sample(dev,
10520                                                           dev_flow,
10521                                                           num_of_dest,
10522                                                           &sample_res,
10523                                                           &mdest_res,
10524                                                           sample_actions,
10525                                                           action_flags,
10526                                                           error);
10527                                 if (ret < 0)
10528                                         return rte_flow_error_set
10529                                                 (error, rte_errno,
10530                                                 RTE_FLOW_ERROR_TYPE_ACTION,
10531                                                 NULL,
10532                                                 "cannot create sample action");
10533                                 if (num_of_dest > 1) {
10534                                         dev_flow->dv.actions[sample_act_pos] =
10535                                         dev_flow->dv.dest_array_res->action;
10536                                 } else {
10537                                         dev_flow->dv.actions[sample_act_pos] =
10538                                         dev_flow->dv.sample_res->verbs_action;
10539                                 }
10540                         }
10541                         break;
10542                 default:
10543                         break;
10544                 }
10545                 if (mhdr_res->actions_num &&
10546                     modify_action_position == UINT32_MAX)
10547                         modify_action_position = actions_n++;
10548         }
10549         /*
10550          * For multiple destination (sample action with ratio=1), the encap
10551          * action and port id action will be combined into group action.
10552          * So need remove the original these actions in the flow and only
10553          * use the sample action instead of.
10554          */
10555         if (num_of_dest > 1 && sample_act->dr_port_id_action) {
10556                 int i;
10557                 void *temp_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
10558
10559                 for (i = 0; i < actions_n; i++) {
10560                         if ((sample_act->dr_encap_action &&
10561                                 sample_act->dr_encap_action ==
10562                                 dev_flow->dv.actions[i]) ||
10563                                 (sample_act->dr_port_id_action &&
10564                                 sample_act->dr_port_id_action ==
10565                                 dev_flow->dv.actions[i]))
10566                                 continue;
10567                         temp_actions[tmp_actions_n++] = dev_flow->dv.actions[i];
10568                 }
10569                 memcpy((void *)dev_flow->dv.actions,
10570                                 (void *)temp_actions,
10571                                 tmp_actions_n * sizeof(void *));
10572                 actions_n = tmp_actions_n;
10573         }
10574         dev_flow->dv.actions_n = actions_n;
10575         dev_flow->act_flags = action_flags;
10576         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
10577                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
10578                 int item_type = items->type;
10579
10580                 if (!mlx5_flow_os_item_supported(item_type))
10581                         return rte_flow_error_set(error, ENOTSUP,
10582                                                   RTE_FLOW_ERROR_TYPE_ITEM,
10583                                                   NULL, "item not supported");
10584                 switch (item_type) {
10585                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
10586                         flow_dv_translate_item_port_id
10587                                 (dev, match_mask, match_value, items, attr);
10588                         last_item = MLX5_FLOW_ITEM_PORT_ID;
10589                         break;
10590                 case RTE_FLOW_ITEM_TYPE_ETH:
10591                         flow_dv_translate_item_eth(match_mask, match_value,
10592                                                    items, tunnel,
10593                                                    dev_flow->dv.group);
10594                         matcher.priority = action_flags &
10595                                         MLX5_FLOW_ACTION_DEFAULT_MISS &&
10596                                         !dev_flow->external ?
10597                                         MLX5_PRIORITY_MAP_L3 :
10598                                         MLX5_PRIORITY_MAP_L2;
10599                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
10600                                              MLX5_FLOW_LAYER_OUTER_L2;
10601                         break;
10602                 case RTE_FLOW_ITEM_TYPE_VLAN:
10603                         flow_dv_translate_item_vlan(dev_flow,
10604                                                     match_mask, match_value,
10605                                                     items, tunnel,
10606                                                     dev_flow->dv.group);
10607                         matcher.priority = MLX5_PRIORITY_MAP_L2;
10608                         last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
10609                                               MLX5_FLOW_LAYER_INNER_VLAN) :
10610                                              (MLX5_FLOW_LAYER_OUTER_L2 |
10611                                               MLX5_FLOW_LAYER_OUTER_VLAN);
10612                         break;
10613                 case RTE_FLOW_ITEM_TYPE_IPV4:
10614                         mlx5_flow_tunnel_ip_check(items, next_protocol,
10615                                                   &item_flags, &tunnel);
10616                         flow_dv_translate_item_ipv4(match_mask, match_value,
10617                                                     items, tunnel,
10618                                                     dev_flow->dv.group);
10619                         matcher.priority = MLX5_PRIORITY_MAP_L3;
10620                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
10621                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
10622                         if (items->mask != NULL &&
10623                             ((const struct rte_flow_item_ipv4 *)
10624                              items->mask)->hdr.next_proto_id) {
10625                                 next_protocol =
10626                                         ((const struct rte_flow_item_ipv4 *)
10627                                          (items->spec))->hdr.next_proto_id;
10628                                 next_protocol &=
10629                                         ((const struct rte_flow_item_ipv4 *)
10630                                          (items->mask))->hdr.next_proto_id;
10631                         } else {
10632                                 /* Reset for inner layer. */
10633                                 next_protocol = 0xff;
10634                         }
10635                         break;
10636                 case RTE_FLOW_ITEM_TYPE_IPV6:
10637                         mlx5_flow_tunnel_ip_check(items, next_protocol,
10638                                                   &item_flags, &tunnel);
10639                         flow_dv_translate_item_ipv6(match_mask, match_value,
10640                                                     items, tunnel,
10641                                                     dev_flow->dv.group);
10642                         matcher.priority = MLX5_PRIORITY_MAP_L3;
10643                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
10644                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
10645                         if (items->mask != NULL &&
10646                             ((const struct rte_flow_item_ipv6 *)
10647                              items->mask)->hdr.proto) {
10648                                 next_protocol =
10649                                         ((const struct rte_flow_item_ipv6 *)
10650                                          items->spec)->hdr.proto;
10651                                 next_protocol &=
10652                                         ((const struct rte_flow_item_ipv6 *)
10653                                          items->mask)->hdr.proto;
10654                         } else {
10655                                 /* Reset for inner layer. */
10656                                 next_protocol = 0xff;
10657                         }
10658                         break;
10659                 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
10660                         flow_dv_translate_item_ipv6_frag_ext(match_mask,
10661                                                              match_value,
10662                                                              items, tunnel);
10663                         last_item = tunnel ?
10664                                         MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
10665                                         MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
10666                         if (items->mask != NULL &&
10667                             ((const struct rte_flow_item_ipv6_frag_ext *)
10668                              items->mask)->hdr.next_header) {
10669                                 next_protocol =
10670                                 ((const struct rte_flow_item_ipv6_frag_ext *)
10671                                  items->spec)->hdr.next_header;
10672                                 next_protocol &=
10673                                 ((const struct rte_flow_item_ipv6_frag_ext *)
10674                                  items->mask)->hdr.next_header;
10675                         } else {
10676                                 /* Reset for inner layer. */
10677                                 next_protocol = 0xff;
10678                         }
10679                         break;
10680                 case RTE_FLOW_ITEM_TYPE_TCP:
10681                         flow_dv_translate_item_tcp(match_mask, match_value,
10682                                                    items, tunnel);
10683                         matcher.priority = MLX5_PRIORITY_MAP_L4;
10684                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
10685                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
10686                         break;
10687                 case RTE_FLOW_ITEM_TYPE_UDP:
10688                         flow_dv_translate_item_udp(match_mask, match_value,
10689                                                    items, tunnel);
10690                         matcher.priority = MLX5_PRIORITY_MAP_L4;
10691                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
10692                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
10693                         break;
10694                 case RTE_FLOW_ITEM_TYPE_GRE:
10695                         flow_dv_translate_item_gre(match_mask, match_value,
10696                                                    items, tunnel);
10697                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10698                         last_item = MLX5_FLOW_LAYER_GRE;
10699                         break;
10700                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
10701                         flow_dv_translate_item_gre_key(match_mask,
10702                                                        match_value, items);
10703                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
10704                         break;
10705                 case RTE_FLOW_ITEM_TYPE_NVGRE:
10706                         flow_dv_translate_item_nvgre(match_mask, match_value,
10707                                                      items, tunnel);
10708                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10709                         last_item = MLX5_FLOW_LAYER_GRE;
10710                         break;
10711                 case RTE_FLOW_ITEM_TYPE_VXLAN:
10712                         flow_dv_translate_item_vxlan(match_mask, match_value,
10713                                                      items, tunnel);
10714                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10715                         last_item = MLX5_FLOW_LAYER_VXLAN;
10716                         break;
10717                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
10718                         flow_dv_translate_item_vxlan_gpe(match_mask,
10719                                                          match_value, items,
10720                                                          tunnel);
10721                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10722                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
10723                         break;
10724                 case RTE_FLOW_ITEM_TYPE_GENEVE:
10725                         flow_dv_translate_item_geneve(match_mask, match_value,
10726                                                       items, tunnel);
10727                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10728                         last_item = MLX5_FLOW_LAYER_GENEVE;
10729                         break;
10730                 case RTE_FLOW_ITEM_TYPE_MPLS:
10731                         flow_dv_translate_item_mpls(match_mask, match_value,
10732                                                     items, last_item, tunnel);
10733                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10734                         last_item = MLX5_FLOW_LAYER_MPLS;
10735                         break;
10736                 case RTE_FLOW_ITEM_TYPE_MARK:
10737                         flow_dv_translate_item_mark(dev, match_mask,
10738                                                     match_value, items);
10739                         last_item = MLX5_FLOW_ITEM_MARK;
10740                         break;
10741                 case RTE_FLOW_ITEM_TYPE_META:
10742                         flow_dv_translate_item_meta(dev, match_mask,
10743                                                     match_value, attr, items);
10744                         last_item = MLX5_FLOW_ITEM_METADATA;
10745                         break;
10746                 case RTE_FLOW_ITEM_TYPE_ICMP:
10747                         flow_dv_translate_item_icmp(match_mask, match_value,
10748                                                     items, tunnel);
10749                         last_item = MLX5_FLOW_LAYER_ICMP;
10750                         break;
10751                 case RTE_FLOW_ITEM_TYPE_ICMP6:
10752                         flow_dv_translate_item_icmp6(match_mask, match_value,
10753                                                       items, tunnel);
10754                         last_item = MLX5_FLOW_LAYER_ICMP6;
10755                         break;
10756                 case RTE_FLOW_ITEM_TYPE_TAG:
10757                         flow_dv_translate_item_tag(dev, match_mask,
10758                                                    match_value, items);
10759                         last_item = MLX5_FLOW_ITEM_TAG;
10760                         break;
10761                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
10762                         flow_dv_translate_mlx5_item_tag(dev, match_mask,
10763                                                         match_value, items);
10764                         last_item = MLX5_FLOW_ITEM_TAG;
10765                         break;
10766                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
10767                         flow_dv_translate_item_tx_queue(dev, match_mask,
10768                                                         match_value,
10769                                                         items);
10770                         last_item = MLX5_FLOW_ITEM_TX_QUEUE;
10771                         break;
10772                 case RTE_FLOW_ITEM_TYPE_GTP:
10773                         flow_dv_translate_item_gtp(match_mask, match_value,
10774                                                    items, tunnel);
10775                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10776                         last_item = MLX5_FLOW_LAYER_GTP;
10777                         break;
10778                 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
10779                         ret = flow_dv_translate_item_gtp_psc(match_mask,
10780                                                           match_value,
10781                                                           items);
10782                         if (ret)
10783                                 return rte_flow_error_set(error, -ret,
10784                                         RTE_FLOW_ERROR_TYPE_ITEM, NULL,
10785                                         "cannot create GTP PSC item");
10786                         last_item = MLX5_FLOW_LAYER_GTP_PSC;
10787                         break;
10788                 case RTE_FLOW_ITEM_TYPE_ECPRI:
10789                         if (!mlx5_flex_parser_ecpri_exist(dev)) {
10790                                 /* Create it only the first time to be used. */
10791                                 ret = mlx5_flex_parser_ecpri_alloc(dev);
10792                                 if (ret)
10793                                         return rte_flow_error_set
10794                                                 (error, -ret,
10795                                                 RTE_FLOW_ERROR_TYPE_ITEM,
10796                                                 NULL,
10797                                                 "cannot create eCPRI parser");
10798                         }
10799                         /* Adjust the length matcher and device flow value. */
10800                         matcher.mask.size = MLX5_ST_SZ_BYTES(fte_match_param);
10801                         dev_flow->dv.value.size =
10802                                         MLX5_ST_SZ_BYTES(fte_match_param);
10803                         flow_dv_translate_item_ecpri(dev, match_mask,
10804                                                      match_value, items);
10805                         /* No other protocol should follow eCPRI layer. */
10806                         last_item = MLX5_FLOW_LAYER_ECPRI;
10807                         break;
10808                 default:
10809                         break;
10810                 }
10811                 item_flags |= last_item;
10812         }
10813         /*
10814          * When E-Switch mode is enabled, we have two cases where we need to
10815          * set the source port manually.
10816          * The first one, is in case of Nic steering rule, and the second is
10817          * E-Switch rule where no port_id item was found. In both cases
10818          * the source port is set according the current port in use.
10819          */
10820         if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
10821             (priv->representor || priv->master)) {
10822                 if (flow_dv_translate_item_port_id(dev, match_mask,
10823                                                    match_value, NULL, attr))
10824                         return -rte_errno;
10825         }
10826 #ifdef RTE_LIBRTE_MLX5_DEBUG
10827         MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
10828                                               dev_flow->dv.value.buf));
10829 #endif
10830         /*
10831          * Layers may be already initialized from prefix flow if this dev_flow
10832          * is the suffix flow.
10833          */
10834         handle->layers |= item_flags;
10835         if (action_flags & MLX5_FLOW_ACTION_RSS)
10836                 flow_dv_hashfields_set(dev_flow, rss_desc);
10837         /* Register matcher. */
10838         matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
10839                                     matcher.mask.size);
10840         matcher.priority = mlx5_os_flow_adjust_priority(dev,
10841                                                         priority,
10842                                                         matcher.priority);
10843         /* reserved field no needs to be set to 0 here. */
10844         tbl_key.domain = attr->transfer;
10845         tbl_key.direction = attr->egress;
10846         tbl_key.table_id = dev_flow->dv.group;
10847         if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow,
10848                                      tunnel, attr->group, error))
10849                 return -rte_errno;
10850         return 0;
10851 }
10852
10853 /**
10854  * Set hash RX queue by hash fields (see enum ibv_rx_hash_fields)
10855  * and tunnel.
10856  *
10857  * @param[in, out] action
10858  *   Shred RSS action holding hash RX queue objects.
10859  * @param[in] hash_fields
10860  *   Defines combination of packet fields to participate in RX hash.
10861  * @param[in] tunnel
10862  *   Tunnel type
10863  * @param[in] hrxq_idx
10864  *   Hash RX queue index to set.
10865  *
10866  * @return
10867  *   0 on success, otherwise negative errno value.
10868  */
10869 static int
10870 __flow_dv_action_rss_hrxq_set(struct mlx5_shared_action_rss *action,
10871                               const uint64_t hash_fields,
10872                               const int tunnel,
10873                               uint32_t hrxq_idx)
10874 {
10875         uint32_t *hrxqs = tunnel ? action->hrxq : action->hrxq_tunnel;
10876
10877         switch (hash_fields & ~IBV_RX_HASH_INNER) {
10878         case MLX5_RSS_HASH_IPV4:
10879                 hrxqs[0] = hrxq_idx;
10880                 return 0;
10881         case MLX5_RSS_HASH_IPV4_TCP:
10882                 hrxqs[1] = hrxq_idx;
10883                 return 0;
10884         case MLX5_RSS_HASH_IPV4_UDP:
10885                 hrxqs[2] = hrxq_idx;
10886                 return 0;
10887         case MLX5_RSS_HASH_IPV6:
10888                 hrxqs[3] = hrxq_idx;
10889                 return 0;
10890         case MLX5_RSS_HASH_IPV6_TCP:
10891                 hrxqs[4] = hrxq_idx;
10892                 return 0;
10893         case MLX5_RSS_HASH_IPV6_UDP:
10894                 hrxqs[5] = hrxq_idx;
10895                 return 0;
10896         case MLX5_RSS_HASH_NONE:
10897                 hrxqs[6] = hrxq_idx;
10898                 return 0;
10899         default:
10900                 return -1;
10901         }
10902 }
10903
10904 /**
10905  * Look up for hash RX queue by hash fields (see enum ibv_rx_hash_fields)
10906  * and tunnel.
10907  *
10908  * @param[in] dev
10909  *   Pointer to the Ethernet device structure.
10910  * @param[in] idx
10911  *   Shared RSS action ID holding hash RX queue objects.
10912  * @param[in] hash_fields
10913  *   Defines combination of packet fields to participate in RX hash.
10914  * @param[in] tunnel
10915  *   Tunnel type
10916  *
10917  * @return
10918  *   Valid hash RX queue index, otherwise 0.
10919  */
10920 static uint32_t
10921 __flow_dv_action_rss_hrxq_lookup(struct rte_eth_dev *dev, uint32_t idx,
10922                                  const uint64_t hash_fields,
10923                                  const int tunnel)
10924 {
10925         struct mlx5_priv *priv = dev->data->dev_private;
10926         struct mlx5_shared_action_rss *shared_rss =
10927             mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
10928         const uint32_t *hrxqs = tunnel ? shared_rss->hrxq :
10929                                                         shared_rss->hrxq_tunnel;
10930
10931         switch (hash_fields & ~IBV_RX_HASH_INNER) {
10932         case MLX5_RSS_HASH_IPV4:
10933                 return hrxqs[0];
10934         case MLX5_RSS_HASH_IPV4_TCP:
10935                 return hrxqs[1];
10936         case MLX5_RSS_HASH_IPV4_UDP:
10937                 return hrxqs[2];
10938         case MLX5_RSS_HASH_IPV6:
10939                 return hrxqs[3];
10940         case MLX5_RSS_HASH_IPV6_TCP:
10941                 return hrxqs[4];
10942         case MLX5_RSS_HASH_IPV6_UDP:
10943                 return hrxqs[5];
10944         case MLX5_RSS_HASH_NONE:
10945                 return hrxqs[6];
10946         default:
10947                 return 0;
10948         }
10949 }
10950
10951 /**
10952  * Apply the flow to the NIC, lock free,
10953  * (mutex should be acquired by caller).
10954  *
10955  * @param[in] dev
10956  *   Pointer to the Ethernet device structure.
10957  * @param[in, out] flow
10958  *   Pointer to flow structure.
10959  * @param[out] error
10960  *   Pointer to error structure.
10961  *
10962  * @return
10963  *   0 on success, a negative errno value otherwise and rte_errno is set.
10964  */
10965 static int
10966 flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
10967               struct rte_flow_error *error)
10968 {
10969         struct mlx5_flow_dv_workspace *dv;
10970         struct mlx5_flow_handle *dh;
10971         struct mlx5_flow_handle_dv *dv_h;
10972         struct mlx5_flow *dev_flow;
10973         struct mlx5_priv *priv = dev->data->dev_private;
10974         uint32_t handle_idx;
10975         int n;
10976         int err;
10977         int idx;
10978         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
10979         struct mlx5_flow_rss_desc *rss_desc = &wks->rss_desc;
10980
10981         MLX5_ASSERT(wks);
10982         for (idx = wks->flow_idx - 1; idx >= 0; idx--) {
10983                 dev_flow = &wks->flows[idx];
10984                 dv = &dev_flow->dv;
10985                 dh = dev_flow->handle;
10986                 dv_h = &dh->dvh;
10987                 n = dv->actions_n;
10988                 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
10989                         if (dv->transfer) {
10990                                 dv->actions[n++] = priv->sh->esw_drop_action;
10991                         } else {
10992                                 MLX5_ASSERT(priv->drop_queue.hrxq);
10993                                 dv->actions[n++] =
10994                                                 priv->drop_queue.hrxq->action;
10995                         }
10996                 } else if ((dh->fate_action == MLX5_FLOW_FATE_QUEUE &&
10997                            !dv_h->rix_sample && !dv_h->rix_dest_array)) {
10998                         struct mlx5_hrxq *hrxq;
10999                         uint32_t hrxq_idx;
11000
11001                         hrxq = flow_dv_hrxq_prepare(dev, dev_flow, rss_desc,
11002                                                     &hrxq_idx);
11003                         if (!hrxq) {
11004                                 rte_flow_error_set
11005                                         (error, rte_errno,
11006                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11007                                          "cannot get hash queue");
11008                                 goto error;
11009                         }
11010                         dh->rix_hrxq = hrxq_idx;
11011                         dv->actions[n++] = hrxq->action;
11012                 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
11013                         struct mlx5_hrxq *hrxq = NULL;
11014                         uint32_t hrxq_idx;
11015
11016                         hrxq_idx = __flow_dv_action_rss_hrxq_lookup(dev,
11017                                                 rss_desc->shared_rss,
11018                                                 dev_flow->hash_fields,
11019                                                 !!(dh->layers &
11020                                                 MLX5_FLOW_LAYER_TUNNEL));
11021                         if (hrxq_idx)
11022                                 hrxq = mlx5_ipool_get
11023                                         (priv->sh->ipool[MLX5_IPOOL_HRXQ],
11024                                          hrxq_idx);
11025                         if (!hrxq) {
11026                                 rte_flow_error_set
11027                                         (error, rte_errno,
11028                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11029                                          "cannot get hash queue");
11030                                 goto error;
11031                         }
11032                         dh->rix_srss = rss_desc->shared_rss;
11033                         dv->actions[n++] = hrxq->action;
11034                 } else if (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS) {
11035                         if (!priv->sh->default_miss_action) {
11036                                 rte_flow_error_set
11037                                         (error, rte_errno,
11038                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11039                                          "default miss action not be created.");
11040                                 goto error;
11041                         }
11042                         dv->actions[n++] = priv->sh->default_miss_action;
11043                 }
11044                 err = mlx5_flow_os_create_flow(dv_h->matcher->matcher_object,
11045                                                (void *)&dv->value, n,
11046                                                dv->actions, &dh->drv_flow);
11047                 if (err) {
11048                         rte_flow_error_set(error, errno,
11049                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11050                                            NULL,
11051                                            "hardware refuses to create flow");
11052                         goto error;
11053                 }
11054                 if (priv->vmwa_context &&
11055                     dh->vf_vlan.tag && !dh->vf_vlan.created) {
11056                         /*
11057                          * The rule contains the VLAN pattern.
11058                          * For VF we are going to create VLAN
11059                          * interface to make hypervisor set correct
11060                          * e-Switch vport context.
11061                          */
11062                         mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
11063                 }
11064         }
11065         return 0;
11066 error:
11067         err = rte_errno; /* Save rte_errno before cleanup. */
11068         SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles,
11069                        handle_idx, dh, next) {
11070                 /* hrxq is union, don't clear it if the flag is not set. */
11071                 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE && dh->rix_hrxq) {
11072                         mlx5_hrxq_release(dev, dh->rix_hrxq);
11073                         dh->rix_hrxq = 0;
11074                 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
11075                         dh->rix_srss = 0;
11076                 }
11077                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
11078                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
11079         }
11080         rte_errno = err; /* Restore rte_errno. */
11081         return -rte_errno;
11082 }
11083
11084 void
11085 flow_dv_matcher_remove_cb(struct mlx5_cache_list *list __rte_unused,
11086                           struct mlx5_cache_entry *entry)
11087 {
11088         struct mlx5_flow_dv_matcher *cache = container_of(entry, typeof(*cache),
11089                                                           entry);
11090
11091         claim_zero(mlx5_flow_os_destroy_flow_matcher(cache->matcher_object));
11092         mlx5_free(cache);
11093 }
11094
11095 /**
11096  * Release the flow matcher.
11097  *
11098  * @param dev
11099  *   Pointer to Ethernet device.
11100  * @param handle
11101  *   Pointer to mlx5_flow_handle.
11102  *
11103  * @return
11104  *   1 while a reference on it exists, 0 when freed.
11105  */
11106 static int
11107 flow_dv_matcher_release(struct rte_eth_dev *dev,
11108                         struct mlx5_flow_handle *handle)
11109 {
11110         struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
11111         struct mlx5_flow_tbl_data_entry *tbl = container_of(matcher->tbl,
11112                                                             typeof(*tbl), tbl);
11113         int ret;
11114
11115         MLX5_ASSERT(matcher->matcher_object);
11116         ret = mlx5_cache_unregister(&tbl->matchers, &matcher->entry);
11117         flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl->tbl);
11118         return ret;
11119 }
11120
11121 /**
11122  * Release encap_decap resource.
11123  *
11124  * @param list
11125  *   Pointer to the hash list.
11126  * @param entry
11127  *   Pointer to exist resource entry object.
11128  */
11129 void
11130 flow_dv_encap_decap_remove_cb(struct mlx5_hlist *list,
11131                               struct mlx5_hlist_entry *entry)
11132 {
11133         struct mlx5_dev_ctx_shared *sh = list->ctx;
11134         struct mlx5_flow_dv_encap_decap_resource *res =
11135                 container_of(entry, typeof(*res), entry);
11136
11137         claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
11138         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], res->idx);
11139 }
11140
11141 /**
11142  * Release an encap/decap resource.
11143  *
11144  * @param dev
11145  *   Pointer to Ethernet device.
11146  * @param encap_decap_idx
11147  *   Index of encap decap resource.
11148  *
11149  * @return
11150  *   1 while a reference on it exists, 0 when freed.
11151  */
11152 static int
11153 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
11154                                      uint32_t encap_decap_idx)
11155 {
11156         struct mlx5_priv *priv = dev->data->dev_private;
11157         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
11158
11159         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
11160                                         encap_decap_idx);
11161         if (!cache_resource)
11162                 return 0;
11163         MLX5_ASSERT(cache_resource->action);
11164         return mlx5_hlist_unregister(priv->sh->encaps_decaps,
11165                                      &cache_resource->entry);
11166 }
11167
11168 /**
11169  * Release an jump to table action resource.
11170  *
11171  * @param dev
11172  *   Pointer to Ethernet device.
11173  * @param handle
11174  *   Pointer to mlx5_flow_handle.
11175  *
11176  * @return
11177  *   1 while a reference on it exists, 0 when freed.
11178  */
11179 static int
11180 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
11181                                   struct mlx5_flow_handle *handle)
11182 {
11183         struct mlx5_priv *priv = dev->data->dev_private;
11184         struct mlx5_flow_tbl_data_entry *tbl_data;
11185
11186         tbl_data = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_JUMP],
11187                              handle->rix_jump);
11188         if (!tbl_data)
11189                 return 0;
11190         return flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl_data->tbl);
11191 }
11192
11193 void
11194 flow_dv_modify_remove_cb(struct mlx5_hlist *list __rte_unused,
11195                          struct mlx5_hlist_entry *entry)
11196 {
11197         struct mlx5_flow_dv_modify_hdr_resource *res =
11198                 container_of(entry, typeof(*res), entry);
11199
11200         claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
11201         mlx5_free(entry);
11202 }
11203
11204 /**
11205  * Release a modify-header resource.
11206  *
11207  * @param dev
11208  *   Pointer to Ethernet device.
11209  * @param handle
11210  *   Pointer to mlx5_flow_handle.
11211  *
11212  * @return
11213  *   1 while a reference on it exists, 0 when freed.
11214  */
11215 static int
11216 flow_dv_modify_hdr_resource_release(struct rte_eth_dev *dev,
11217                                     struct mlx5_flow_handle *handle)
11218 {
11219         struct mlx5_priv *priv = dev->data->dev_private;
11220         struct mlx5_flow_dv_modify_hdr_resource *entry = handle->dvh.modify_hdr;
11221
11222         MLX5_ASSERT(entry->action);
11223         return mlx5_hlist_unregister(priv->sh->modify_cmds, &entry->entry);
11224 }
11225
11226 void
11227 flow_dv_port_id_remove_cb(struct mlx5_cache_list *list,
11228                           struct mlx5_cache_entry *entry)
11229 {
11230         struct mlx5_dev_ctx_shared *sh = list->ctx;
11231         struct mlx5_flow_dv_port_id_action_resource *cache =
11232                         container_of(entry, typeof(*cache), entry);
11233
11234         claim_zero(mlx5_flow_os_destroy_flow_action(cache->action));
11235         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], cache->idx);
11236 }
11237
11238 /**
11239  * Release port ID action resource.
11240  *
11241  * @param dev
11242  *   Pointer to Ethernet device.
11243  * @param handle
11244  *   Pointer to mlx5_flow_handle.
11245  *
11246  * @return
11247  *   1 while a reference on it exists, 0 when freed.
11248  */
11249 static int
11250 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
11251                                         uint32_t port_id)
11252 {
11253         struct mlx5_priv *priv = dev->data->dev_private;
11254         struct mlx5_flow_dv_port_id_action_resource *cache;
11255
11256         cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID], port_id);
11257         if (!cache)
11258                 return 0;
11259         MLX5_ASSERT(cache->action);
11260         return mlx5_cache_unregister(&priv->sh->port_id_action_list,
11261                                      &cache->entry);
11262 }
11263
11264 /**
11265  * Release shared RSS action resource.
11266  *
11267  * @param dev
11268  *   Pointer to Ethernet device.
11269  * @param srss
11270  *   Shared RSS action index.
11271  */
11272 static void
11273 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss)
11274 {
11275         struct mlx5_priv *priv = dev->data->dev_private;
11276         struct mlx5_shared_action_rss *shared_rss;
11277
11278         shared_rss = mlx5_ipool_get
11279                         (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], srss);
11280         __atomic_sub_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
11281 }
11282
11283 void
11284 flow_dv_push_vlan_remove_cb(struct mlx5_cache_list *list,
11285                             struct mlx5_cache_entry *entry)
11286 {
11287         struct mlx5_dev_ctx_shared *sh = list->ctx;
11288         struct mlx5_flow_dv_push_vlan_action_resource *cache =
11289                         container_of(entry, typeof(*cache), entry);
11290
11291         claim_zero(mlx5_flow_os_destroy_flow_action(cache->action));
11292         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], cache->idx);
11293 }
11294
11295 /**
11296  * Release push vlan action resource.
11297  *
11298  * @param dev
11299  *   Pointer to Ethernet device.
11300  * @param handle
11301  *   Pointer to mlx5_flow_handle.
11302  *
11303  * @return
11304  *   1 while a reference on it exists, 0 when freed.
11305  */
11306 static int
11307 flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,
11308                                           struct mlx5_flow_handle *handle)
11309 {
11310         struct mlx5_priv *priv = dev->data->dev_private;
11311         struct mlx5_flow_dv_push_vlan_action_resource *cache;
11312         uint32_t idx = handle->dvh.rix_push_vlan;
11313
11314         cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
11315         if (!cache)
11316                 return 0;
11317         MLX5_ASSERT(cache->action);
11318         return mlx5_cache_unregister(&priv->sh->push_vlan_action_list,
11319                                      &cache->entry);
11320 }
11321
11322 /**
11323  * Release the fate resource.
11324  *
11325  * @param dev
11326  *   Pointer to Ethernet device.
11327  * @param handle
11328  *   Pointer to mlx5_flow_handle.
11329  */
11330 static void
11331 flow_dv_fate_resource_release(struct rte_eth_dev *dev,
11332                                struct mlx5_flow_handle *handle)
11333 {
11334         if (!handle->rix_fate)
11335                 return;
11336         switch (handle->fate_action) {
11337         case MLX5_FLOW_FATE_QUEUE:
11338                 mlx5_hrxq_release(dev, handle->rix_hrxq);
11339                 break;
11340         case MLX5_FLOW_FATE_JUMP:
11341                 flow_dv_jump_tbl_resource_release(dev, handle);
11342                 break;
11343         case MLX5_FLOW_FATE_PORT_ID:
11344                 flow_dv_port_id_action_resource_release(dev,
11345                                 handle->rix_port_id_action);
11346                 break;
11347         default:
11348                 DRV_LOG(DEBUG, "Incorrect fate action:%d", handle->fate_action);
11349                 break;
11350         }
11351         handle->rix_fate = 0;
11352 }
11353
11354 void
11355 flow_dv_sample_remove_cb(struct mlx5_cache_list *list __rte_unused,
11356                          struct mlx5_cache_entry *entry)
11357 {
11358         struct mlx5_flow_dv_sample_resource *cache_resource =
11359                         container_of(entry, typeof(*cache_resource), entry);
11360         struct rte_eth_dev *dev = cache_resource->dev;
11361         struct mlx5_priv *priv = dev->data->dev_private;
11362
11363         if (cache_resource->verbs_action)
11364                 claim_zero(mlx5_flow_os_destroy_flow_action
11365                                 (cache_resource->verbs_action));
11366         if (cache_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB) {
11367                 if (cache_resource->default_miss)
11368                         claim_zero(mlx5_flow_os_destroy_flow_action
11369                           (cache_resource->default_miss));
11370         }
11371         if (cache_resource->normal_path_tbl)
11372                 flow_dv_tbl_resource_release(MLX5_SH(dev),
11373                         cache_resource->normal_path_tbl);
11374         flow_dv_sample_sub_actions_release(dev,
11375                                 &cache_resource->sample_idx);
11376         mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
11377                         cache_resource->idx);
11378         DRV_LOG(DEBUG, "sample resource %p: removed",
11379                 (void *)cache_resource);
11380 }
11381
11382 /**
11383  * Release an sample resource.
11384  *
11385  * @param dev
11386  *   Pointer to Ethernet device.
11387  * @param handle
11388  *   Pointer to mlx5_flow_handle.
11389  *
11390  * @return
11391  *   1 while a reference on it exists, 0 when freed.
11392  */
11393 static int
11394 flow_dv_sample_resource_release(struct rte_eth_dev *dev,
11395                                      struct mlx5_flow_handle *handle)
11396 {
11397         struct mlx5_priv *priv = dev->data->dev_private;
11398         struct mlx5_flow_dv_sample_resource *cache_resource;
11399
11400         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
11401                          handle->dvh.rix_sample);
11402         if (!cache_resource)
11403                 return 0;
11404         MLX5_ASSERT(cache_resource->verbs_action);
11405         return mlx5_cache_unregister(&priv->sh->sample_action_list,
11406                                      &cache_resource->entry);
11407 }
11408
11409 void
11410 flow_dv_dest_array_remove_cb(struct mlx5_cache_list *list __rte_unused,
11411                              struct mlx5_cache_entry *entry)
11412 {
11413         struct mlx5_flow_dv_dest_array_resource *cache_resource =
11414                         container_of(entry, typeof(*cache_resource), entry);
11415         struct rte_eth_dev *dev = cache_resource->dev;
11416         struct mlx5_priv *priv = dev->data->dev_private;
11417         uint32_t i = 0;
11418
11419         MLX5_ASSERT(cache_resource->action);
11420         if (cache_resource->action)
11421                 claim_zero(mlx5_flow_os_destroy_flow_action
11422                                         (cache_resource->action));
11423         for (; i < cache_resource->num_of_dest; i++)
11424                 flow_dv_sample_sub_actions_release(dev,
11425                                 &cache_resource->sample_idx[i]);
11426         mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
11427                         cache_resource->idx);
11428         DRV_LOG(DEBUG, "destination array resource %p: removed",
11429                 (void *)cache_resource);
11430 }
11431
11432 /**
11433  * Release an destination array resource.
11434  *
11435  * @param dev
11436  *   Pointer to Ethernet device.
11437  * @param handle
11438  *   Pointer to mlx5_flow_handle.
11439  *
11440  * @return
11441  *   1 while a reference on it exists, 0 when freed.
11442  */
11443 static int
11444 flow_dv_dest_array_resource_release(struct rte_eth_dev *dev,
11445                                     struct mlx5_flow_handle *handle)
11446 {
11447         struct mlx5_priv *priv = dev->data->dev_private;
11448         struct mlx5_flow_dv_dest_array_resource *cache;
11449
11450         cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
11451                                handle->dvh.rix_dest_array);
11452         if (!cache)
11453                 return 0;
11454         MLX5_ASSERT(cache->action);
11455         return mlx5_cache_unregister(&priv->sh->dest_array_list,
11456                                      &cache->entry);
11457 }
11458
11459 static void
11460 flow_dv_geneve_tlv_option_resource_release(struct rte_eth_dev *dev)
11461 {
11462         struct mlx5_priv *priv = dev->data->dev_private;
11463         struct mlx5_dev_ctx_shared *sh = priv->sh;
11464         struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
11465                                 sh->geneve_tlv_option_resource;
11466         rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
11467         if (geneve_opt_resource) {
11468                 if (!(__atomic_sub_fetch(&geneve_opt_resource->refcnt, 1,
11469                                          __ATOMIC_RELAXED))) {
11470                         claim_zero(mlx5_devx_cmd_destroy
11471                                         (geneve_opt_resource->obj));
11472                         mlx5_free(sh->geneve_tlv_option_resource);
11473                         sh->geneve_tlv_option_resource = NULL;
11474                 }
11475         }
11476         rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
11477 }
11478
11479 /**
11480  * Remove the flow from the NIC but keeps it in memory.
11481  * Lock free, (mutex should be acquired by caller).
11482  *
11483  * @param[in] dev
11484  *   Pointer to Ethernet device.
11485  * @param[in, out] flow
11486  *   Pointer to flow structure.
11487  */
11488 static void
11489 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
11490 {
11491         struct mlx5_flow_handle *dh;
11492         uint32_t handle_idx;
11493         struct mlx5_priv *priv = dev->data->dev_private;
11494
11495         if (!flow)
11496                 return;
11497         handle_idx = flow->dev_handles;
11498         while (handle_idx) {
11499                 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
11500                                     handle_idx);
11501                 if (!dh)
11502                         return;
11503                 if (dh->drv_flow) {
11504                         claim_zero(mlx5_flow_os_destroy_flow(dh->drv_flow));
11505                         dh->drv_flow = NULL;
11506                 }
11507                 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE)
11508                         flow_dv_fate_resource_release(dev, dh);
11509                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
11510                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
11511                 handle_idx = dh->next.next;
11512         }
11513 }
11514
11515 /**
11516  * Remove the flow from the NIC and the memory.
11517  * Lock free, (mutex should be acquired by caller).
11518  *
11519  * @param[in] dev
11520  *   Pointer to the Ethernet device structure.
11521  * @param[in, out] flow
11522  *   Pointer to flow structure.
11523  */
11524 static void
11525 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
11526 {
11527         struct mlx5_flow_handle *dev_handle;
11528         struct mlx5_priv *priv = dev->data->dev_private;
11529         uint32_t srss = 0;
11530
11531         if (!flow)
11532                 return;
11533         flow_dv_remove(dev, flow);
11534         if (flow->counter) {
11535                 flow_dv_counter_free(dev, flow->counter);
11536                 flow->counter = 0;
11537         }
11538         if (flow->meter) {
11539                 struct mlx5_flow_meter *fm;
11540
11541                 fm = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MTR],
11542                                     flow->meter);
11543                 if (fm)
11544                         mlx5_flow_meter_detach(fm);
11545                 flow->meter = 0;
11546         }
11547         if (flow->age)
11548                 flow_dv_aso_age_release(dev, flow->age);
11549         if (flow->geneve_tlv_option) {
11550                 flow_dv_geneve_tlv_option_resource_release(dev);
11551                 flow->geneve_tlv_option = 0;
11552         }
11553         while (flow->dev_handles) {
11554                 uint32_t tmp_idx = flow->dev_handles;
11555
11556                 dev_handle = mlx5_ipool_get(priv->sh->ipool
11557                                             [MLX5_IPOOL_MLX5_FLOW], tmp_idx);
11558                 if (!dev_handle)
11559                         return;
11560                 flow->dev_handles = dev_handle->next.next;
11561                 if (dev_handle->dvh.matcher)
11562                         flow_dv_matcher_release(dev, dev_handle);
11563                 if (dev_handle->dvh.rix_sample)
11564                         flow_dv_sample_resource_release(dev, dev_handle);
11565                 if (dev_handle->dvh.rix_dest_array)
11566                         flow_dv_dest_array_resource_release(dev, dev_handle);
11567                 if (dev_handle->dvh.rix_encap_decap)
11568                         flow_dv_encap_decap_resource_release(dev,
11569                                 dev_handle->dvh.rix_encap_decap);
11570                 if (dev_handle->dvh.modify_hdr)
11571                         flow_dv_modify_hdr_resource_release(dev, dev_handle);
11572                 if (dev_handle->dvh.rix_push_vlan)
11573                         flow_dv_push_vlan_action_resource_release(dev,
11574                                                                   dev_handle);
11575                 if (dev_handle->dvh.rix_tag)
11576                         flow_dv_tag_release(dev,
11577                                             dev_handle->dvh.rix_tag);
11578                 if (dev_handle->fate_action != MLX5_FLOW_FATE_SHARED_RSS)
11579                         flow_dv_fate_resource_release(dev, dev_handle);
11580                 else if (!srss)
11581                         srss = dev_handle->rix_srss;
11582                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
11583                            tmp_idx);
11584         }
11585         if (srss)
11586                 flow_dv_shared_rss_action_release(dev, srss);
11587 }
11588
11589 /**
11590  * Release array of hash RX queue objects.
11591  * Helper function.
11592  *
11593  * @param[in] dev
11594  *   Pointer to the Ethernet device structure.
11595  * @param[in, out] hrxqs
11596  *   Array of hash RX queue objects.
11597  *
11598  * @return
11599  *   Total number of references to hash RX queue objects in *hrxqs* array
11600  *   after this operation.
11601  */
11602 static int
11603 __flow_dv_hrxqs_release(struct rte_eth_dev *dev,
11604                         uint32_t (*hrxqs)[MLX5_RSS_HASH_FIELDS_LEN])
11605 {
11606         size_t i;
11607         int remaining = 0;
11608
11609         for (i = 0; i < RTE_DIM(*hrxqs); i++) {
11610                 int ret = mlx5_hrxq_release(dev, (*hrxqs)[i]);
11611
11612                 if (!ret)
11613                         (*hrxqs)[i] = 0;
11614                 remaining += ret;
11615         }
11616         return remaining;
11617 }
11618
11619 /**
11620  * Release all hash RX queue objects representing shared RSS action.
11621  *
11622  * @param[in] dev
11623  *   Pointer to the Ethernet device structure.
11624  * @param[in, out] action
11625  *   Shared RSS action to remove hash RX queue objects from.
11626  *
11627  * @return
11628  *   Total number of references to hash RX queue objects stored in *action*
11629  *   after this operation.
11630  *   Expected to be 0 if no external references held.
11631  */
11632 static int
11633 __flow_dv_action_rss_hrxqs_release(struct rte_eth_dev *dev,
11634                                  struct mlx5_shared_action_rss *action)
11635 {
11636         return __flow_dv_hrxqs_release(dev, &action->hrxq) +
11637                 __flow_dv_hrxqs_release(dev, &action->hrxq_tunnel);
11638 }
11639
11640 /**
11641  * Setup shared RSS action.
11642  * Prepare set of hash RX queue objects sufficient to handle all valid
11643  * hash_fields combinations (see enum ibv_rx_hash_fields).
11644  *
11645  * @param[in] dev
11646  *   Pointer to the Ethernet device structure.
11647  * @param[in] action_idx
11648  *   Shared RSS action ipool index.
11649  * @param[in, out] action
11650  *   Partially initialized shared RSS action.
11651  * @param[out] error
11652  *   Perform verbose error reporting if not NULL. Initialized in case of
11653  *   error only.
11654  *
11655  * @return
11656  *   0 on success, otherwise negative errno value.
11657  */
11658 static int
11659 __flow_dv_action_rss_setup(struct rte_eth_dev *dev,
11660                            uint32_t action_idx,
11661                            struct mlx5_shared_action_rss *action,
11662                            struct rte_flow_error *error)
11663 {
11664         struct mlx5_flow_rss_desc rss_desc = { 0 };
11665         size_t i;
11666         int err;
11667
11668         if (mlx5_ind_table_obj_setup(dev, action->ind_tbl)) {
11669                 return rte_flow_error_set(error, rte_errno,
11670                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11671                                           "cannot setup indirection table");
11672         }
11673         memcpy(rss_desc.key, action->origin.key, MLX5_RSS_HASH_KEY_LEN);
11674         rss_desc.key_len = MLX5_RSS_HASH_KEY_LEN;
11675         rss_desc.const_q = action->origin.queue;
11676         rss_desc.queue_num = action->origin.queue_num;
11677         /* Set non-zero value to indicate a shared RSS. */
11678         rss_desc.shared_rss = action_idx;
11679         rss_desc.ind_tbl = action->ind_tbl;
11680         for (i = 0; i < MLX5_RSS_HASH_FIELDS_LEN; i++) {
11681                 uint32_t hrxq_idx;
11682                 uint64_t hash_fields = mlx5_rss_hash_fields[i];
11683                 int tunnel;
11684
11685                 for (tunnel = 0; tunnel < 2; tunnel++) {
11686                         rss_desc.tunnel = tunnel;
11687                         rss_desc.hash_fields = hash_fields;
11688                         hrxq_idx = mlx5_hrxq_get(dev, &rss_desc);
11689                         if (!hrxq_idx) {
11690                                 rte_flow_error_set
11691                                         (error, rte_errno,
11692                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11693                                          "cannot get hash queue");
11694                                 goto error_hrxq_new;
11695                         }
11696                         err = __flow_dv_action_rss_hrxq_set
11697                                 (action, hash_fields, tunnel, hrxq_idx);
11698                         MLX5_ASSERT(!err);
11699                 }
11700         }
11701         return 0;
11702 error_hrxq_new:
11703         err = rte_errno;
11704         __flow_dv_action_rss_hrxqs_release(dev, action);
11705         if (!mlx5_ind_table_obj_release(dev, action->ind_tbl, true))
11706                 action->ind_tbl = NULL;
11707         rte_errno = err;
11708         return -rte_errno;
11709 }
11710
11711 /**
11712  * Create shared RSS action.
11713  *
11714  * @param[in] dev
11715  *   Pointer to the Ethernet device structure.
11716  * @param[in] conf
11717  *   Shared action configuration.
11718  * @param[in] rss
11719  *   RSS action specification used to create shared action.
11720  * @param[out] error
11721  *   Perform verbose error reporting if not NULL. Initialized in case of
11722  *   error only.
11723  *
11724  * @return
11725  *   A valid shared action ID in case of success, 0 otherwise and
11726  *   rte_errno is set.
11727  */
11728 static uint32_t
11729 __flow_dv_action_rss_create(struct rte_eth_dev *dev,
11730                             const struct rte_flow_shared_action_conf *conf,
11731                             const struct rte_flow_action_rss *rss,
11732                             struct rte_flow_error *error)
11733 {
11734         struct mlx5_priv *priv = dev->data->dev_private;
11735         struct mlx5_shared_action_rss *shared_action = NULL;
11736         void *queue = NULL;
11737         struct rte_flow_action_rss *origin;
11738         const uint8_t *rss_key;
11739         uint32_t queue_size = rss->queue_num * sizeof(uint16_t);
11740         uint32_t idx;
11741
11742         RTE_SET_USED(conf);
11743         queue = mlx5_malloc(0, RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
11744                             0, SOCKET_ID_ANY);
11745         shared_action = mlx5_ipool_zmalloc
11746                          (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], &idx);
11747         if (!shared_action || !queue) {
11748                 rte_flow_error_set(error, ENOMEM,
11749                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11750                                    "cannot allocate resource memory");
11751                 goto error_rss_init;
11752         }
11753         if (idx > (1u << MLX5_SHARED_ACTION_TYPE_OFFSET)) {
11754                 rte_flow_error_set(error, E2BIG,
11755                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11756                                    "rss action number out of range");
11757                 goto error_rss_init;
11758         }
11759         shared_action->ind_tbl = mlx5_malloc(MLX5_MEM_ZERO,
11760                                              sizeof(*shared_action->ind_tbl),
11761                                              0, SOCKET_ID_ANY);
11762         if (!shared_action->ind_tbl) {
11763                 rte_flow_error_set(error, ENOMEM,
11764                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11765                                    "cannot allocate resource memory");
11766                 goto error_rss_init;
11767         }
11768         memcpy(queue, rss->queue, queue_size);
11769         shared_action->ind_tbl->queues = queue;
11770         shared_action->ind_tbl->queues_n = rss->queue_num;
11771         origin = &shared_action->origin;
11772         origin->func = rss->func;
11773         origin->level = rss->level;
11774         /* RSS type 0 indicates default RSS type (ETH_RSS_IP). */
11775         origin->types = !rss->types ? ETH_RSS_IP : rss->types;
11776         /* NULL RSS key indicates default RSS key. */
11777         rss_key = !rss->key ? rss_hash_default_key : rss->key;
11778         memcpy(shared_action->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
11779         origin->key = &shared_action->key[0];
11780         origin->key_len = MLX5_RSS_HASH_KEY_LEN;
11781         origin->queue = queue;
11782         origin->queue_num = rss->queue_num;
11783         if (__flow_dv_action_rss_setup(dev, idx, shared_action, error))
11784                 goto error_rss_init;
11785         rte_spinlock_init(&shared_action->action_rss_sl);
11786         __atomic_add_fetch(&shared_action->refcnt, 1, __ATOMIC_RELAXED);
11787         rte_spinlock_lock(&priv->shared_act_sl);
11788         ILIST_INSERT(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
11789                      &priv->rss_shared_actions, idx, shared_action, next);
11790         rte_spinlock_unlock(&priv->shared_act_sl);
11791         return idx;
11792 error_rss_init:
11793         if (shared_action) {
11794                 if (shared_action->ind_tbl)
11795                         mlx5_free(shared_action->ind_tbl);
11796                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
11797                                 idx);
11798         }
11799         if (queue)
11800                 mlx5_free(queue);
11801         return 0;
11802 }
11803
11804 /**
11805  * Destroy the shared RSS action.
11806  * Release related hash RX queue objects.
11807  *
11808  * @param[in] dev
11809  *   Pointer to the Ethernet device structure.
11810  * @param[in] idx
11811  *   The shared RSS action object ID to be removed.
11812  * @param[out] error
11813  *   Perform verbose error reporting if not NULL. Initialized in case of
11814  *   error only.
11815  *
11816  * @return
11817  *   0 on success, otherwise negative errno value.
11818  */
11819 static int
11820 __flow_dv_action_rss_release(struct rte_eth_dev *dev, uint32_t idx,
11821                              struct rte_flow_error *error)
11822 {
11823         struct mlx5_priv *priv = dev->data->dev_private;
11824         struct mlx5_shared_action_rss *shared_rss =
11825             mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
11826         uint32_t old_refcnt = 1;
11827         int remaining;
11828         uint16_t *queue = NULL;
11829
11830         if (!shared_rss)
11831                 return rte_flow_error_set(error, EINVAL,
11832                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
11833                                           "invalid shared action");
11834         remaining = __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
11835         if (remaining)
11836                 return rte_flow_error_set(error, EBUSY,
11837                                           RTE_FLOW_ERROR_TYPE_ACTION,
11838                                           NULL,
11839                                           "shared rss hrxq has references");
11840         queue = shared_rss->ind_tbl->queues;
11841         remaining = mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl, true);
11842         if (remaining)
11843                 return rte_flow_error_set(error, EBUSY,
11844                                           RTE_FLOW_ERROR_TYPE_ACTION,
11845                                           NULL,
11846                                           "shared rss indirection table has"
11847                                           " references");
11848         if (!__atomic_compare_exchange_n(&shared_rss->refcnt, &old_refcnt,
11849                                          0, 0, __ATOMIC_ACQUIRE,
11850                                          __ATOMIC_RELAXED))
11851                 return rte_flow_error_set(error, EBUSY,
11852                                           RTE_FLOW_ERROR_TYPE_ACTION,
11853                                           NULL,
11854                                           "shared rss has references");
11855         mlx5_free(queue);
11856         rte_spinlock_lock(&priv->shared_act_sl);
11857         ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
11858                      &priv->rss_shared_actions, idx, shared_rss, next);
11859         rte_spinlock_unlock(&priv->shared_act_sl);
11860         mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
11861                         idx);
11862         return 0;
11863 }
11864
11865 /**
11866  * Create shared action, lock free,
11867  * (mutex should be acquired by caller).
11868  * Dispatcher for action type specific call.
11869  *
11870  * @param[in] dev
11871  *   Pointer to the Ethernet device structure.
11872  * @param[in] conf
11873  *   Shared action configuration.
11874  * @param[in] action
11875  *   Action specification used to create shared action.
11876  * @param[out] error
11877  *   Perform verbose error reporting if not NULL. Initialized in case of
11878  *   error only.
11879  *
11880  * @return
11881  *   A valid shared action handle in case of success, NULL otherwise and
11882  *   rte_errno is set.
11883  */
11884 static struct rte_flow_shared_action *
11885 flow_dv_action_create(struct rte_eth_dev *dev,
11886                       const struct rte_flow_shared_action_conf *conf,
11887                       const struct rte_flow_action *action,
11888                       struct rte_flow_error *err)
11889 {
11890         uint32_t idx = 0;
11891         uint32_t ret = 0;
11892
11893         switch (action->type) {
11894         case RTE_FLOW_ACTION_TYPE_RSS:
11895                 ret = __flow_dv_action_rss_create(dev, conf, action->conf, err);
11896                 idx = (MLX5_SHARED_ACTION_TYPE_RSS <<
11897                        MLX5_SHARED_ACTION_TYPE_OFFSET) | ret;
11898                 break;
11899         case RTE_FLOW_ACTION_TYPE_AGE:
11900                 ret = flow_dv_translate_create_aso_age(dev, action->conf, err);
11901                 idx = (MLX5_SHARED_ACTION_TYPE_AGE <<
11902                        MLX5_SHARED_ACTION_TYPE_OFFSET) | ret;
11903                 if (ret) {
11904                         struct mlx5_aso_age_action *aso_age =
11905                                               flow_aso_age_get_by_idx(dev, ret);
11906
11907                         if (!aso_age->age_params.context)
11908                                 aso_age->age_params.context =
11909                                                          (void *)(uintptr_t)idx;
11910                 }
11911                 break;
11912         default:
11913                 rte_flow_error_set(err, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION,
11914                                    NULL, "action type not supported");
11915                 break;
11916         }
11917         return ret ? (struct rte_flow_shared_action *)(uintptr_t)idx : NULL;
11918 }
11919
11920 /**
11921  * Destroy the shared action.
11922  * Release action related resources on the NIC and the memory.
11923  * Lock free, (mutex should be acquired by caller).
11924  * Dispatcher for action type specific call.
11925  *
11926  * @param[in] dev
11927  *   Pointer to the Ethernet device structure.
11928  * @param[in] action
11929  *   The shared action object to be removed.
11930  * @param[out] error
11931  *   Perform verbose error reporting if not NULL. Initialized in case of
11932  *   error only.
11933  *
11934  * @return
11935  *   0 on success, otherwise negative errno value.
11936  */
11937 static int
11938 flow_dv_action_destroy(struct rte_eth_dev *dev,
11939                        struct rte_flow_shared_action *action,
11940                        struct rte_flow_error *error)
11941 {
11942         uint32_t act_idx = (uint32_t)(uintptr_t)action;
11943         uint32_t type = act_idx >> MLX5_SHARED_ACTION_TYPE_OFFSET;
11944         uint32_t idx = act_idx & ((1u << MLX5_SHARED_ACTION_TYPE_OFFSET) - 1);
11945         int ret;
11946
11947         switch (type) {
11948         case MLX5_SHARED_ACTION_TYPE_RSS:
11949                 return __flow_dv_action_rss_release(dev, idx, error);
11950         case MLX5_SHARED_ACTION_TYPE_AGE:
11951                 ret = flow_dv_aso_age_release(dev, idx);
11952                 if (ret)
11953                         /*
11954                          * In this case, the last flow has a reference will
11955                          * actually release the age action.
11956                          */
11957                         DRV_LOG(DEBUG, "Shared age action %" PRIu32 " was"
11958                                 " released with references %d.", idx, ret);
11959                 return 0;
11960         default:
11961                 return rte_flow_error_set(error, ENOTSUP,
11962                                           RTE_FLOW_ERROR_TYPE_ACTION,
11963                                           NULL,
11964                                           "action type not supported");
11965         }
11966 }
11967
11968 /**
11969  * Updates in place shared RSS action configuration.
11970  *
11971  * @param[in] dev
11972  *   Pointer to the Ethernet device structure.
11973  * @param[in] idx
11974  *   The shared RSS action object ID to be updated.
11975  * @param[in] action_conf
11976  *   RSS action specification used to modify *shared_rss*.
11977  * @param[out] error
11978  *   Perform verbose error reporting if not NULL. Initialized in case of
11979  *   error only.
11980  *
11981  * @return
11982  *   0 on success, otherwise negative errno value.
11983  * @note: currently only support update of RSS queues.
11984  */
11985 static int
11986 __flow_dv_action_rss_update(struct rte_eth_dev *dev, uint32_t idx,
11987                             const struct rte_flow_action_rss *action_conf,
11988                             struct rte_flow_error *error)
11989 {
11990         struct mlx5_priv *priv = dev->data->dev_private;
11991         struct mlx5_shared_action_rss *shared_rss =
11992             mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
11993         int ret = 0;
11994         void *queue = NULL;
11995         uint16_t *queue_old = NULL;
11996         uint32_t queue_size = action_conf->queue_num * sizeof(uint16_t);
11997
11998         if (!shared_rss)
11999                 return rte_flow_error_set(error, EINVAL,
12000                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12001                                           "invalid shared action to update");
12002         queue = mlx5_malloc(MLX5_MEM_ZERO,
12003                             RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
12004                             0, SOCKET_ID_ANY);
12005         if (!queue)
12006                 return rte_flow_error_set(error, ENOMEM,
12007                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12008                                           NULL,
12009                                           "cannot allocate resource memory");
12010         memcpy(queue, action_conf->queue, queue_size);
12011         MLX5_ASSERT(shared_rss->ind_tbl);
12012         rte_spinlock_lock(&shared_rss->action_rss_sl);
12013         queue_old = shared_rss->ind_tbl->queues;
12014         ret = mlx5_ind_table_obj_modify(dev, shared_rss->ind_tbl,
12015                                         queue, action_conf->queue_num, true);
12016         if (ret) {
12017                 mlx5_free(queue);
12018                 ret = rte_flow_error_set(error, rte_errno,
12019                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12020                                           "cannot update indirection table");
12021         } else {
12022                 mlx5_free(queue_old);
12023                 shared_rss->origin.queue = queue;
12024                 shared_rss->origin.queue_num = action_conf->queue_num;
12025         }
12026         rte_spinlock_unlock(&shared_rss->action_rss_sl);
12027         return ret;
12028 }
12029
12030 /**
12031  * Updates in place shared action configuration, lock free,
12032  * (mutex should be acquired by caller).
12033  *
12034  * @param[in] dev
12035  *   Pointer to the Ethernet device structure.
12036  * @param[in] action
12037  *   The shared action object to be updated.
12038  * @param[in] action_conf
12039  *   Action specification used to modify *action*.
12040  *   *action_conf* should be of type correlating with type of the *action*,
12041  *   otherwise considered as invalid.
12042  * @param[out] error
12043  *   Perform verbose error reporting if not NULL. Initialized in case of
12044  *   error only.
12045  *
12046  * @return
12047  *   0 on success, otherwise negative errno value.
12048  */
12049 static int
12050 flow_dv_action_update(struct rte_eth_dev *dev,
12051                         struct rte_flow_shared_action *action,
12052                         const void *action_conf,
12053                         struct rte_flow_error *err)
12054 {
12055         uint32_t act_idx = (uint32_t)(uintptr_t)action;
12056         uint32_t type = act_idx >> MLX5_SHARED_ACTION_TYPE_OFFSET;
12057         uint32_t idx = act_idx & ((1u << MLX5_SHARED_ACTION_TYPE_OFFSET) - 1);
12058
12059         switch (type) {
12060         case MLX5_SHARED_ACTION_TYPE_RSS:
12061                 return __flow_dv_action_rss_update(dev, idx, action_conf, err);
12062         default:
12063                 return rte_flow_error_set(err, ENOTSUP,
12064                                           RTE_FLOW_ERROR_TYPE_ACTION,
12065                                           NULL,
12066                                           "action type update not supported");
12067         }
12068 }
12069
12070 static int
12071 flow_dv_action_query(struct rte_eth_dev *dev,
12072                      const struct rte_flow_shared_action *action, void *data,
12073                      struct rte_flow_error *error)
12074 {
12075         struct mlx5_age_param *age_param;
12076         struct rte_flow_query_age *resp;
12077         uint32_t act_idx = (uint32_t)(uintptr_t)action;
12078         uint32_t type = act_idx >> MLX5_SHARED_ACTION_TYPE_OFFSET;
12079         uint32_t idx = act_idx & ((1u << MLX5_SHARED_ACTION_TYPE_OFFSET) - 1);
12080
12081         switch (type) {
12082         case MLX5_SHARED_ACTION_TYPE_AGE:
12083                 age_param = &flow_aso_age_get_by_idx(dev, idx)->age_params;
12084                 resp = data;
12085                 resp->aged = __atomic_load_n(&age_param->state,
12086                                               __ATOMIC_RELAXED) == AGE_TMOUT ?
12087                                                                           1 : 0;
12088                 resp->sec_since_last_hit_valid = !resp->aged;
12089                 if (resp->sec_since_last_hit_valid)
12090                         resp->sec_since_last_hit = __atomic_load_n
12091                              (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
12092                 return 0;
12093         default:
12094                 return rte_flow_error_set(error, ENOTSUP,
12095                                           RTE_FLOW_ERROR_TYPE_ACTION,
12096                                           NULL,
12097                                           "action type query not supported");
12098         }
12099 }
12100
12101 /**
12102  * Query a dv flow  rule for its statistics via devx.
12103  *
12104  * @param[in] dev
12105  *   Pointer to Ethernet device.
12106  * @param[in] flow
12107  *   Pointer to the sub flow.
12108  * @param[out] data
12109  *   data retrieved by the query.
12110  * @param[out] error
12111  *   Perform verbose error reporting if not NULL.
12112  *
12113  * @return
12114  *   0 on success, a negative errno value otherwise and rte_errno is set.
12115  */
12116 static int
12117 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
12118                     void *data, struct rte_flow_error *error)
12119 {
12120         struct mlx5_priv *priv = dev->data->dev_private;
12121         struct rte_flow_query_count *qc = data;
12122
12123         if (!priv->config.devx)
12124                 return rte_flow_error_set(error, ENOTSUP,
12125                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12126                                           NULL,
12127                                           "counters are not supported");
12128         if (flow->counter) {
12129                 uint64_t pkts, bytes;
12130                 struct mlx5_flow_counter *cnt;
12131
12132                 cnt = flow_dv_counter_get_by_idx(dev, flow->counter,
12133                                                  NULL);
12134                 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
12135                                                &bytes);
12136
12137                 if (err)
12138                         return rte_flow_error_set(error, -err,
12139                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12140                                         NULL, "cannot read counters");
12141                 qc->hits_set = 1;
12142                 qc->bytes_set = 1;
12143                 qc->hits = pkts - cnt->hits;
12144                 qc->bytes = bytes - cnt->bytes;
12145                 if (qc->reset) {
12146                         cnt->hits = pkts;
12147                         cnt->bytes = bytes;
12148                 }
12149                 return 0;
12150         }
12151         return rte_flow_error_set(error, EINVAL,
12152                                   RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12153                                   NULL,
12154                                   "counters are not available");
12155 }
12156
12157 /**
12158  * Query a flow rule AGE action for aging information.
12159  *
12160  * @param[in] dev
12161  *   Pointer to Ethernet device.
12162  * @param[in] flow
12163  *   Pointer to the sub flow.
12164  * @param[out] data
12165  *   data retrieved by the query.
12166  * @param[out] error
12167  *   Perform verbose error reporting if not NULL.
12168  *
12169  * @return
12170  *   0 on success, a negative errno value otherwise and rte_errno is set.
12171  */
12172 static int
12173 flow_dv_query_age(struct rte_eth_dev *dev, struct rte_flow *flow,
12174                   void *data, struct rte_flow_error *error)
12175 {
12176         struct rte_flow_query_age *resp = data;
12177         struct mlx5_age_param *age_param;
12178
12179         if (flow->age) {
12180                 struct mlx5_aso_age_action *act =
12181                                      flow_aso_age_get_by_idx(dev, flow->age);
12182
12183                 age_param = &act->age_params;
12184         } else if (flow->counter) {
12185                 age_param = flow_dv_counter_idx_get_age(dev, flow->counter);
12186
12187                 if (!age_param || !age_param->timeout)
12188                         return rte_flow_error_set
12189                                         (error, EINVAL,
12190                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12191                                          NULL, "cannot read age data");
12192         } else {
12193                 return rte_flow_error_set(error, EINVAL,
12194                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12195                                           NULL, "age data not available");
12196         }
12197         resp->aged = __atomic_load_n(&age_param->state, __ATOMIC_RELAXED) ==
12198                                      AGE_TMOUT ? 1 : 0;
12199         resp->sec_since_last_hit_valid = !resp->aged;
12200         if (resp->sec_since_last_hit_valid)
12201                 resp->sec_since_last_hit = __atomic_load_n
12202                              (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
12203         return 0;
12204 }
12205
12206 /**
12207  * Query a flow.
12208  *
12209  * @see rte_flow_query()
12210  * @see rte_flow_ops
12211  */
12212 static int
12213 flow_dv_query(struct rte_eth_dev *dev,
12214               struct rte_flow *flow __rte_unused,
12215               const struct rte_flow_action *actions __rte_unused,
12216               void *data __rte_unused,
12217               struct rte_flow_error *error __rte_unused)
12218 {
12219         int ret = -EINVAL;
12220
12221         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
12222                 switch (actions->type) {
12223                 case RTE_FLOW_ACTION_TYPE_VOID:
12224                         break;
12225                 case RTE_FLOW_ACTION_TYPE_COUNT:
12226                         ret = flow_dv_query_count(dev, flow, data, error);
12227                         break;
12228                 case RTE_FLOW_ACTION_TYPE_AGE:
12229                         ret = flow_dv_query_age(dev, flow, data, error);
12230                         break;
12231                 default:
12232                         return rte_flow_error_set(error, ENOTSUP,
12233                                                   RTE_FLOW_ERROR_TYPE_ACTION,
12234                                                   actions,
12235                                                   "action not supported");
12236                 }
12237         }
12238         return ret;
12239 }
12240
12241 /**
12242  * Destroy the meter table set.
12243  * Lock free, (mutex should be acquired by caller).
12244  *
12245  * @param[in] dev
12246  *   Pointer to Ethernet device.
12247  * @param[in] tbl
12248  *   Pointer to the meter table set.
12249  *
12250  * @return
12251  *   Always 0.
12252  */
12253 static int
12254 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
12255                         struct mlx5_meter_domains_infos *tbl)
12256 {
12257         struct mlx5_priv *priv = dev->data->dev_private;
12258         struct mlx5_meter_domains_infos *mtd =
12259                                 (struct mlx5_meter_domains_infos *)tbl;
12260
12261         if (!mtd || !priv->config.dv_flow_en)
12262                 return 0;
12263         if (mtd->ingress.policer_rules[RTE_MTR_DROPPED])
12264                 claim_zero(mlx5_flow_os_destroy_flow
12265                            (mtd->ingress.policer_rules[RTE_MTR_DROPPED]));
12266         if (mtd->egress.policer_rules[RTE_MTR_DROPPED])
12267                 claim_zero(mlx5_flow_os_destroy_flow
12268                            (mtd->egress.policer_rules[RTE_MTR_DROPPED]));
12269         if (mtd->transfer.policer_rules[RTE_MTR_DROPPED])
12270                 claim_zero(mlx5_flow_os_destroy_flow
12271                            (mtd->transfer.policer_rules[RTE_MTR_DROPPED]));
12272         if (mtd->egress.color_matcher)
12273                 claim_zero(mlx5_flow_os_destroy_flow_matcher
12274                            (mtd->egress.color_matcher));
12275         if (mtd->egress.any_matcher)
12276                 claim_zero(mlx5_flow_os_destroy_flow_matcher
12277                            (mtd->egress.any_matcher));
12278         if (mtd->egress.tbl)
12279                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->egress.tbl);
12280         if (mtd->egress.sfx_tbl)
12281                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->egress.sfx_tbl);
12282         if (mtd->ingress.color_matcher)
12283                 claim_zero(mlx5_flow_os_destroy_flow_matcher
12284                            (mtd->ingress.color_matcher));
12285         if (mtd->ingress.any_matcher)
12286                 claim_zero(mlx5_flow_os_destroy_flow_matcher
12287                            (mtd->ingress.any_matcher));
12288         if (mtd->ingress.tbl)
12289                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->ingress.tbl);
12290         if (mtd->ingress.sfx_tbl)
12291                 flow_dv_tbl_resource_release(MLX5_SH(dev),
12292                                              mtd->ingress.sfx_tbl);
12293         if (mtd->transfer.color_matcher)
12294                 claim_zero(mlx5_flow_os_destroy_flow_matcher
12295                            (mtd->transfer.color_matcher));
12296         if (mtd->transfer.any_matcher)
12297                 claim_zero(mlx5_flow_os_destroy_flow_matcher
12298                            (mtd->transfer.any_matcher));
12299         if (mtd->transfer.tbl)
12300                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->transfer.tbl);
12301         if (mtd->transfer.sfx_tbl)
12302                 flow_dv_tbl_resource_release(MLX5_SH(dev),
12303                                              mtd->transfer.sfx_tbl);
12304         if (mtd->drop_actn)
12305                 claim_zero(mlx5_flow_os_destroy_flow_action(mtd->drop_actn));
12306         mlx5_free(mtd);
12307         return 0;
12308 }
12309
12310 /* Number of meter flow actions, count and jump or count and drop. */
12311 #define METER_ACTIONS 2
12312
12313 /**
12314  * Create specify domain meter table and suffix table.
12315  *
12316  * @param[in] dev
12317  *   Pointer to Ethernet device.
12318  * @param[in,out] mtb
12319  *   Pointer to DV meter table set.
12320  * @param[in] egress
12321  *   Table attribute.
12322  * @param[in] transfer
12323  *   Table attribute.
12324  * @param[in] color_reg_c_idx
12325  *   Reg C index for color match.
12326  *
12327  * @return
12328  *   0 on success, -1 otherwise and rte_errno is set.
12329  */
12330 static int
12331 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
12332                            struct mlx5_meter_domains_infos *mtb,
12333                            uint8_t egress, uint8_t transfer,
12334                            uint32_t color_reg_c_idx)
12335 {
12336         struct mlx5_priv *priv = dev->data->dev_private;
12337         struct mlx5_dev_ctx_shared *sh = priv->sh;
12338         struct mlx5_flow_dv_match_params mask = {
12339                 .size = sizeof(mask.buf),
12340         };
12341         struct mlx5_flow_dv_match_params value = {
12342                 .size = sizeof(value.buf),
12343         };
12344         struct mlx5dv_flow_matcher_attr dv_attr = {
12345                 .type = IBV_FLOW_ATTR_NORMAL,
12346                 .priority = 0,
12347                 .match_criteria_enable = 0,
12348                 .match_mask = (void *)&mask,
12349         };
12350         void *actions[METER_ACTIONS];
12351         struct mlx5_meter_domain_info *dtb;
12352         struct rte_flow_error error;
12353         int i = 0;
12354         int ret;
12355
12356         if (transfer)
12357                 dtb = &mtb->transfer;
12358         else if (egress)
12359                 dtb = &mtb->egress;
12360         else
12361                 dtb = &mtb->ingress;
12362         /* Create the meter table with METER level. */
12363         dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
12364                                             egress, transfer, false, NULL, 0,
12365                                             0, &error);
12366         if (!dtb->tbl) {
12367                 DRV_LOG(ERR, "Failed to create meter policer table.");
12368                 return -1;
12369         }
12370         /* Create the meter suffix table with SUFFIX level. */
12371         dtb->sfx_tbl = flow_dv_tbl_resource_get(dev,
12372                                             MLX5_FLOW_TABLE_LEVEL_SUFFIX,
12373                                             egress, transfer, false, NULL, 0,
12374                                             0, &error);
12375         if (!dtb->sfx_tbl) {
12376                 DRV_LOG(ERR, "Failed to create meter suffix table.");
12377                 return -1;
12378         }
12379         /* Create matchers, Any and Color. */
12380         dv_attr.priority = 3;
12381         dv_attr.match_criteria_enable = 0;
12382         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, dtb->tbl->obj,
12383                                                &dtb->any_matcher);
12384         if (ret) {
12385                 DRV_LOG(ERR, "Failed to create meter"
12386                              " policer default matcher.");
12387                 goto error_exit;
12388         }
12389         dv_attr.priority = 0;
12390         dv_attr.match_criteria_enable =
12391                                 1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
12392         flow_dv_match_meta_reg(mask.buf, value.buf, color_reg_c_idx,
12393                                rte_col_2_mlx5_col(RTE_COLORS), UINT8_MAX);
12394         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, dtb->tbl->obj,
12395                                                &dtb->color_matcher);
12396         if (ret) {
12397                 DRV_LOG(ERR, "Failed to create meter policer color matcher.");
12398                 goto error_exit;
12399         }
12400         if (mtb->count_actns[RTE_MTR_DROPPED])
12401                 actions[i++] = mtb->count_actns[RTE_MTR_DROPPED];
12402         actions[i++] = mtb->drop_actn;
12403         /* Default rule: lowest priority, match any, actions: drop. */
12404         ret = mlx5_flow_os_create_flow(dtb->any_matcher, (void *)&value, i,
12405                                        actions,
12406                                        &dtb->policer_rules[RTE_MTR_DROPPED]);
12407         if (ret) {
12408                 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
12409                 goto error_exit;
12410         }
12411         return 0;
12412 error_exit:
12413         return -1;
12414 }
12415
12416 /**
12417  * Create the needed meter and suffix tables.
12418  * Lock free, (mutex should be acquired by caller).
12419  *
12420  * @param[in] dev
12421  *   Pointer to Ethernet device.
12422  * @param[in] fm
12423  *   Pointer to the flow meter.
12424  *
12425  * @return
12426  *   Pointer to table set on success, NULL otherwise and rte_errno is set.
12427  */
12428 static struct mlx5_meter_domains_infos *
12429 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev,
12430                        const struct mlx5_flow_meter *fm)
12431 {
12432         struct mlx5_priv *priv = dev->data->dev_private;
12433         struct mlx5_meter_domains_infos *mtb;
12434         int ret;
12435         int i;
12436
12437         if (!priv->mtr_en) {
12438                 rte_errno = ENOTSUP;
12439                 return NULL;
12440         }
12441         mtb = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mtb), 0, SOCKET_ID_ANY);
12442         if (!mtb) {
12443                 DRV_LOG(ERR, "Failed to allocate memory for meter.");
12444                 return NULL;
12445         }
12446         /* Create meter count actions */
12447         for (i = 0; i <= RTE_MTR_DROPPED; i++) {
12448                 struct mlx5_flow_counter *cnt;
12449                 if (!fm->policer_stats.cnt[i])
12450                         continue;
12451                 cnt = flow_dv_counter_get_by_idx(dev,
12452                       fm->policer_stats.cnt[i], NULL);
12453                 mtb->count_actns[i] = cnt->action;
12454         }
12455         /* Create drop action. */
12456         ret = mlx5_flow_os_create_flow_action_drop(&mtb->drop_actn);
12457         if (ret) {
12458                 DRV_LOG(ERR, "Failed to create drop action.");
12459                 goto error_exit;
12460         }
12461         /* Egress meter table. */
12462         ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0, priv->mtr_color_reg);
12463         if (ret) {
12464                 DRV_LOG(ERR, "Failed to prepare egress meter table.");
12465                 goto error_exit;
12466         }
12467         /* Ingress meter table. */
12468         ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0, priv->mtr_color_reg);
12469         if (ret) {
12470                 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
12471                 goto error_exit;
12472         }
12473         /* FDB meter table. */
12474         if (priv->config.dv_esw_en) {
12475                 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1,
12476                                                  priv->mtr_color_reg);
12477                 if (ret) {
12478                         DRV_LOG(ERR, "Failed to prepare fdb meter table.");
12479                         goto error_exit;
12480                 }
12481         }
12482         return mtb;
12483 error_exit:
12484         flow_dv_destroy_mtr_tbl(dev, mtb);
12485         return NULL;
12486 }
12487
12488 /**
12489  * Destroy domain policer rule.
12490  *
12491  * @param[in] dt
12492  *   Pointer to domain table.
12493  */
12494 static void
12495 flow_dv_destroy_domain_policer_rule(struct mlx5_meter_domain_info *dt)
12496 {
12497         int i;
12498
12499         for (i = 0; i < RTE_MTR_DROPPED; i++) {
12500                 if (dt->policer_rules[i]) {
12501                         claim_zero(mlx5_flow_os_destroy_flow
12502                                    (dt->policer_rules[i]));
12503                         dt->policer_rules[i] = NULL;
12504                 }
12505         }
12506         if (dt->jump_actn) {
12507                 claim_zero(mlx5_flow_os_destroy_flow_action(dt->jump_actn));
12508                 dt->jump_actn = NULL;
12509         }
12510 }
12511
12512 /**
12513  * Destroy policer rules.
12514  *
12515  * @param[in] dev
12516  *   Pointer to Ethernet device.
12517  * @param[in] fm
12518  *   Pointer to flow meter structure.
12519  * @param[in] attr
12520  *   Pointer to flow attributes.
12521  *
12522  * @return
12523  *   Always 0.
12524  */
12525 static int
12526 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev __rte_unused,
12527                               const struct mlx5_flow_meter *fm,
12528                               const struct rte_flow_attr *attr)
12529 {
12530         struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
12531
12532         if (!mtb)
12533                 return 0;
12534         if (attr->egress)
12535                 flow_dv_destroy_domain_policer_rule(&mtb->egress);
12536         if (attr->ingress)
12537                 flow_dv_destroy_domain_policer_rule(&mtb->ingress);
12538         if (attr->transfer)
12539                 flow_dv_destroy_domain_policer_rule(&mtb->transfer);
12540         return 0;
12541 }
12542
12543 /**
12544  * Create specify domain meter policer rule.
12545  *
12546  * @param[in] fm
12547  *   Pointer to flow meter structure.
12548  * @param[in] mtb
12549  *   Pointer to DV meter table set.
12550  * @param[in] mtr_reg_c
12551  *   Color match REG_C.
12552  *
12553  * @return
12554  *   0 on success, -1 otherwise.
12555  */
12556 static int
12557 flow_dv_create_policer_forward_rule(struct mlx5_flow_meter *fm,
12558                                     struct mlx5_meter_domain_info *dtb,
12559                                     uint8_t mtr_reg_c)
12560 {
12561         struct mlx5_flow_dv_match_params matcher = {
12562                 .size = sizeof(matcher.buf),
12563         };
12564         struct mlx5_flow_dv_match_params value = {
12565                 .size = sizeof(value.buf),
12566         };
12567         struct mlx5_meter_domains_infos *mtb = fm->mfts;
12568         void *actions[METER_ACTIONS];
12569         int i;
12570         int ret = 0;
12571
12572         /* Create jump action. */
12573         if (!dtb->jump_actn)
12574                 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
12575                                 (dtb->sfx_tbl->obj, &dtb->jump_actn);
12576         if (ret) {
12577                 DRV_LOG(ERR, "Failed to create policer jump action.");
12578                 goto error;
12579         }
12580         for (i = 0; i < RTE_MTR_DROPPED; i++) {
12581                 int j = 0;
12582
12583                 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_reg_c,
12584                                        rte_col_2_mlx5_col(i), UINT8_MAX);
12585                 if (mtb->count_actns[i])
12586                         actions[j++] = mtb->count_actns[i];
12587                 if (fm->action[i] == MTR_POLICER_ACTION_DROP)
12588                         actions[j++] = mtb->drop_actn;
12589                 else
12590                         actions[j++] = dtb->jump_actn;
12591                 ret = mlx5_flow_os_create_flow(dtb->color_matcher,
12592                                                (void *)&value, j, actions,
12593                                                &dtb->policer_rules[i]);
12594                 if (ret) {
12595                         DRV_LOG(ERR, "Failed to create policer rule.");
12596                         goto error;
12597                 }
12598         }
12599         return 0;
12600 error:
12601         rte_errno = errno;
12602         return -1;
12603 }
12604
12605 /**
12606  * Create policer rules.
12607  *
12608  * @param[in] dev
12609  *   Pointer to Ethernet device.
12610  * @param[in] fm
12611  *   Pointer to flow meter structure.
12612  * @param[in] attr
12613  *   Pointer to flow attributes.
12614  *
12615  * @return
12616  *   0 on success, -1 otherwise.
12617  */
12618 static int
12619 flow_dv_create_policer_rules(struct rte_eth_dev *dev,
12620                              struct mlx5_flow_meter *fm,
12621                              const struct rte_flow_attr *attr)
12622 {
12623         struct mlx5_priv *priv = dev->data->dev_private;
12624         struct mlx5_meter_domains_infos *mtb = fm->mfts;
12625         int ret;
12626
12627         if (attr->egress) {
12628                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->egress,
12629                                                 priv->mtr_color_reg);
12630                 if (ret) {
12631                         DRV_LOG(ERR, "Failed to create egress policer.");
12632                         goto error;
12633                 }
12634         }
12635         if (attr->ingress) {
12636                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->ingress,
12637                                                 priv->mtr_color_reg);
12638                 if (ret) {
12639                         DRV_LOG(ERR, "Failed to create ingress policer.");
12640                         goto error;
12641                 }
12642         }
12643         if (attr->transfer) {
12644                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->transfer,
12645                                                 priv->mtr_color_reg);
12646                 if (ret) {
12647                         DRV_LOG(ERR, "Failed to create transfer policer.");
12648                         goto error;
12649                 }
12650         }
12651         return 0;
12652 error:
12653         flow_dv_destroy_policer_rules(dev, fm, attr);
12654         return -1;
12655 }
12656
12657 /**
12658  * Validate the batch counter support in root table.
12659  *
12660  * Create a simple flow with invalid counter and drop action on root table to
12661  * validate if batch counter with offset on root table is supported or not.
12662  *
12663  * @param[in] dev
12664  *   Pointer to rte_eth_dev structure.
12665  *
12666  * @return
12667  *   0 on success, a negative errno value otherwise and rte_errno is set.
12668  */
12669 int
12670 mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev)
12671 {
12672         struct mlx5_priv *priv = dev->data->dev_private;
12673         struct mlx5_dev_ctx_shared *sh = priv->sh;
12674         struct mlx5_flow_dv_match_params mask = {
12675                 .size = sizeof(mask.buf),
12676         };
12677         struct mlx5_flow_dv_match_params value = {
12678                 .size = sizeof(value.buf),
12679         };
12680         struct mlx5dv_flow_matcher_attr dv_attr = {
12681                 .type = IBV_FLOW_ATTR_NORMAL,
12682                 .priority = 0,
12683                 .match_criteria_enable = 0,
12684                 .match_mask = (void *)&mask,
12685         };
12686         void *actions[2] = { 0 };
12687         struct mlx5_flow_tbl_resource *tbl = NULL;
12688         struct mlx5_devx_obj *dcs = NULL;
12689         void *matcher = NULL;
12690         void *flow = NULL;
12691         int ret = -1;
12692
12693         tbl = flow_dv_tbl_resource_get(dev, 0, 0, 0, false, NULL, 0, 0, NULL);
12694         if (!tbl)
12695                 goto err;
12696         dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
12697         if (!dcs)
12698                 goto err;
12699         ret = mlx5_flow_os_create_flow_action_count(dcs->obj, UINT16_MAX,
12700                                                     &actions[0]);
12701         if (ret)
12702                 goto err;
12703         actions[1] = priv->drop_queue.hrxq->action;
12704         dv_attr.match_criteria_enable = flow_dv_matcher_enable(mask.buf);
12705         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj,
12706                                                &matcher);
12707         if (ret)
12708                 goto err;
12709         ret = mlx5_flow_os_create_flow(matcher, (void *)&value, 2,
12710                                        actions, &flow);
12711 err:
12712         /*
12713          * If batch counter with offset is not supported, the driver will not
12714          * validate the invalid offset value, flow create should success.
12715          * In this case, it means batch counter is not supported in root table.
12716          *
12717          * Otherwise, if flow create is failed, counter offset is supported.
12718          */
12719         if (flow) {
12720                 DRV_LOG(INFO, "Batch counter is not supported in root "
12721                               "table. Switch to fallback mode.");
12722                 rte_errno = ENOTSUP;
12723                 ret = -rte_errno;
12724                 claim_zero(mlx5_flow_os_destroy_flow(flow));
12725         } else {
12726                 /* Check matcher to make sure validate fail at flow create. */
12727                 if (!matcher || (matcher && errno != EINVAL))
12728                         DRV_LOG(ERR, "Unexpected error in counter offset "
12729                                      "support detection");
12730                 ret = 0;
12731         }
12732         if (actions[0])
12733                 claim_zero(mlx5_flow_os_destroy_flow_action(actions[0]));
12734         if (matcher)
12735                 claim_zero(mlx5_flow_os_destroy_flow_matcher(matcher));
12736         if (tbl)
12737                 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
12738         if (dcs)
12739                 claim_zero(mlx5_devx_cmd_destroy(dcs));
12740         return ret;
12741 }
12742
12743 /**
12744  * Query a devx counter.
12745  *
12746  * @param[in] dev
12747  *   Pointer to the Ethernet device structure.
12748  * @param[in] cnt
12749  *   Index to the flow counter.
12750  * @param[in] clear
12751  *   Set to clear the counter statistics.
12752  * @param[out] pkts
12753  *   The statistics value of packets.
12754  * @param[out] bytes
12755  *   The statistics value of bytes.
12756  *
12757  * @return
12758  *   0 on success, otherwise return -1.
12759  */
12760 static int
12761 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
12762                       uint64_t *pkts, uint64_t *bytes)
12763 {
12764         struct mlx5_priv *priv = dev->data->dev_private;
12765         struct mlx5_flow_counter *cnt;
12766         uint64_t inn_pkts, inn_bytes;
12767         int ret;
12768
12769         if (!priv->config.devx)
12770                 return -1;
12771
12772         ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
12773         if (ret)
12774                 return -1;
12775         cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
12776         *pkts = inn_pkts - cnt->hits;
12777         *bytes = inn_bytes - cnt->bytes;
12778         if (clear) {
12779                 cnt->hits = inn_pkts;
12780                 cnt->bytes = inn_bytes;
12781         }
12782         return 0;
12783 }
12784
12785 /**
12786  * Get aged-out flows.
12787  *
12788  * @param[in] dev
12789  *   Pointer to the Ethernet device structure.
12790  * @param[in] context
12791  *   The address of an array of pointers to the aged-out flows contexts.
12792  * @param[in] nb_contexts
12793  *   The length of context array pointers.
12794  * @param[out] error
12795  *   Perform verbose error reporting if not NULL. Initialized in case of
12796  *   error only.
12797  *
12798  * @return
12799  *   how many contexts get in success, otherwise negative errno value.
12800  *   if nb_contexts is 0, return the amount of all aged contexts.
12801  *   if nb_contexts is not 0 , return the amount of aged flows reported
12802  *   in the context array.
12803  * @note: only stub for now
12804  */
12805 static int
12806 flow_get_aged_flows(struct rte_eth_dev *dev,
12807                     void **context,
12808                     uint32_t nb_contexts,
12809                     struct rte_flow_error *error)
12810 {
12811         struct mlx5_priv *priv = dev->data->dev_private;
12812         struct mlx5_age_info *age_info;
12813         struct mlx5_age_param *age_param;
12814         struct mlx5_flow_counter *counter;
12815         struct mlx5_aso_age_action *act;
12816         int nb_flows = 0;
12817
12818         if (nb_contexts && !context)
12819                 return rte_flow_error_set(error, EINVAL,
12820                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12821                                           NULL, "empty context");
12822         age_info = GET_PORT_AGE_INFO(priv);
12823         rte_spinlock_lock(&age_info->aged_sl);
12824         LIST_FOREACH(act, &age_info->aged_aso, next) {
12825                 nb_flows++;
12826                 if (nb_contexts) {
12827                         context[nb_flows - 1] =
12828                                                 act->age_params.context;
12829                         if (!(--nb_contexts))
12830                                 break;
12831                 }
12832         }
12833         TAILQ_FOREACH(counter, &age_info->aged_counters, next) {
12834                 nb_flows++;
12835                 if (nb_contexts) {
12836                         age_param = MLX5_CNT_TO_AGE(counter);
12837                         context[nb_flows - 1] = age_param->context;
12838                         if (!(--nb_contexts))
12839                                 break;
12840                 }
12841         }
12842         rte_spinlock_unlock(&age_info->aged_sl);
12843         MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
12844         return nb_flows;
12845 }
12846
12847 /*
12848  * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
12849  */
12850 static uint32_t
12851 flow_dv_counter_allocate(struct rte_eth_dev *dev)
12852 {
12853         return flow_dv_counter_alloc(dev, 0);
12854 }
12855
12856 /**
12857  * Validate shared action.
12858  * Dispatcher for action type specific validation.
12859  *
12860  * @param[in] dev
12861  *   Pointer to the Ethernet device structure.
12862  * @param[in] conf
12863  *   Shared action configuration.
12864  * @param[in] action
12865  *   The shared action object to validate.
12866  * @param[out] error
12867  *   Perform verbose error reporting if not NULL. Initialized in case of
12868  *   error only.
12869  *
12870  * @return
12871  *   0 on success, otherwise negative errno value.
12872  */
12873 static int
12874 flow_dv_action_validate(struct rte_eth_dev *dev,
12875                         const struct rte_flow_shared_action_conf *conf,
12876                         const struct rte_flow_action *action,
12877                         struct rte_flow_error *err)
12878 {
12879         struct mlx5_priv *priv = dev->data->dev_private;
12880
12881         RTE_SET_USED(conf);
12882         switch (action->type) {
12883         case RTE_FLOW_ACTION_TYPE_RSS:
12884                 return mlx5_validate_action_rss(dev, action, err);
12885         case RTE_FLOW_ACTION_TYPE_AGE:
12886                 if (!priv->sh->aso_age_mng)
12887                         return rte_flow_error_set(err, ENOTSUP,
12888                                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12889                                                 NULL,
12890                                              "shared age action not supported");
12891                 return flow_dv_validate_action_age(0, action, dev, err);
12892         default:
12893                 return rte_flow_error_set(err, ENOTSUP,
12894                                           RTE_FLOW_ERROR_TYPE_ACTION,
12895                                           NULL,
12896                                           "action type not supported");
12897         }
12898 }
12899
12900 static int
12901 flow_dv_sync_domain(struct rte_eth_dev *dev, uint32_t domains, uint32_t flags)
12902 {
12903         struct mlx5_priv *priv = dev->data->dev_private;
12904         int ret = 0;
12905
12906         if ((domains & MLX5_DOMAIN_BIT_NIC_RX) && priv->sh->rx_domain != NULL) {
12907                 ret = mlx5_os_flow_dr_sync_domain(priv->sh->rx_domain,
12908                                                 flags);
12909                 if (ret != 0)
12910                         return ret;
12911         }
12912         if ((domains & MLX5_DOMAIN_BIT_NIC_TX) && priv->sh->tx_domain != NULL) {
12913                 ret = mlx5_os_flow_dr_sync_domain(priv->sh->tx_domain, flags);
12914                 if (ret != 0)
12915                         return ret;
12916         }
12917         if ((domains & MLX5_DOMAIN_BIT_FDB) && priv->sh->fdb_domain != NULL) {
12918                 ret = mlx5_os_flow_dr_sync_domain(priv->sh->fdb_domain, flags);
12919                 if (ret != 0)
12920                         return ret;
12921         }
12922         return 0;
12923 }
12924
12925 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
12926         .validate = flow_dv_validate,
12927         .prepare = flow_dv_prepare,
12928         .translate = flow_dv_translate,
12929         .apply = flow_dv_apply,
12930         .remove = flow_dv_remove,
12931         .destroy = flow_dv_destroy,
12932         .query = flow_dv_query,
12933         .create_mtr_tbls = flow_dv_create_mtr_tbl,
12934         .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
12935         .create_policer_rules = flow_dv_create_policer_rules,
12936         .destroy_policer_rules = flow_dv_destroy_policer_rules,
12937         .counter_alloc = flow_dv_counter_allocate,
12938         .counter_free = flow_dv_counter_free,
12939         .counter_query = flow_dv_counter_query,
12940         .get_aged_flows = flow_get_aged_flows,
12941         .action_validate = flow_dv_action_validate,
12942         .action_create = flow_dv_action_create,
12943         .action_destroy = flow_dv_action_destroy,
12944         .action_update = flow_dv_action_update,
12945         .action_query = flow_dv_action_query,
12946         .sync_domain = flow_dv_sync_domain,
12947 };
12948
12949 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */
12950