1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2016 6WIND S.A.
3 * Copyright 2016 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_PRM_H_
7 #define RTE_PMD_MLX5_PRM_H_
12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
14 #pragma GCC diagnostic ignored "-Wpedantic"
16 #include <infiniband/mlx5dv.h>
18 #pragma GCC diagnostic error "-Wpedantic"
22 #include "mlx5_autoconf.h"
24 /* RSS hash key size. */
25 #define MLX5_RSS_HASH_KEY_LEN 40
27 /* Get CQE owner bit. */
28 #define MLX5_CQE_OWNER(op_own) ((op_own) & MLX5_CQE_OWNER_MASK)
31 #define MLX5_CQE_FORMAT(op_own) (((op_own) & MLX5E_CQE_FORMAT_MASK) >> 2)
34 #define MLX5_CQE_OPCODE(op_own) (((op_own) & 0xf0) >> 4)
36 /* Get CQE solicited event. */
37 #define MLX5_CQE_SE(op_own) (((op_own) >> 1) & 1)
39 /* Invalidate a CQE. */
40 #define MLX5_CQE_INVALIDATE (MLX5_CQE_INVALID << 4)
42 /* Maximum number of packets a multi-packet WQE can handle. */
43 #define MLX5_MPW_DSEG_MAX 5
46 #define MLX5_WQE_DWORD_SIZE 16
49 #define MLX5_WQE_SIZE (4 * MLX5_WQE_DWORD_SIZE)
51 /* Max size of a WQE session. */
52 #define MLX5_WQE_SIZE_MAX 960U
54 /* Compute the number of DS. */
55 #define MLX5_WQE_DS(n) \
56 (((n) + MLX5_WQE_DWORD_SIZE - 1) / MLX5_WQE_DWORD_SIZE)
58 /* Room for inline data in multi-packet WQE. */
59 #define MLX5_MWQE64_INL_DATA 28
61 /* Default minimum number of Tx queues for inlining packets. */
62 #define MLX5_EMPW_MIN_TXQS 8
64 /* Default max packet length to be inlined. */
65 #define MLX5_EMPW_MAX_INLINE_LEN (4U * MLX5_WQE_SIZE)
68 #define MLX5_OPC_MOD_ENHANCED_MPSW 0
69 #define MLX5_OPCODE_ENHANCED_MPSW 0x29
71 /* CQE value to inform that VLAN is stripped. */
72 #define MLX5_CQE_VLAN_STRIPPED (1u << 0)
75 #define MLX5_CQE_RX_IP_EXT_OPTS_PACKET (1u << 1)
78 #define MLX5_CQE_RX_IPV6_PACKET (1u << 2)
81 #define MLX5_CQE_RX_IPV4_PACKET (1u << 3)
84 #define MLX5_CQE_RX_TCP_PACKET (1u << 4)
87 #define MLX5_CQE_RX_UDP_PACKET (1u << 5)
89 /* IP is fragmented. */
90 #define MLX5_CQE_RX_IP_FRAG_PACKET (1u << 7)
92 /* L2 header is valid. */
93 #define MLX5_CQE_RX_L2_HDR_VALID (1u << 8)
95 /* L3 header is valid. */
96 #define MLX5_CQE_RX_L3_HDR_VALID (1u << 9)
98 /* L4 header is valid. */
99 #define MLX5_CQE_RX_L4_HDR_VALID (1u << 10)
101 /* Outer packet, 0 IPv4, 1 IPv6. */
102 #define MLX5_CQE_RX_OUTER_PACKET (1u << 1)
104 /* Tunnel packet bit in the CQE. */
105 #define MLX5_CQE_RX_TUNNEL_PACKET (1u << 0)
107 /* Inner L3 checksum offload (Tunneled packets only). */
108 #define MLX5_ETH_WQE_L3_INNER_CSUM (1u << 4)
110 /* Inner L4 checksum offload (Tunneled packets only). */
111 #define MLX5_ETH_WQE_L4_INNER_CSUM (1u << 5)
113 /* Outer L4 type is TCP. */
114 #define MLX5_ETH_WQE_L4_OUTER_TCP (0u << 5)
116 /* Outer L4 type is UDP. */
117 #define MLX5_ETH_WQE_L4_OUTER_UDP (1u << 5)
119 /* Outer L3 type is IPV4. */
120 #define MLX5_ETH_WQE_L3_OUTER_IPV4 (0u << 4)
122 /* Outer L3 type is IPV6. */
123 #define MLX5_ETH_WQE_L3_OUTER_IPV6 (1u << 4)
125 /* Inner L4 type is TCP. */
126 #define MLX5_ETH_WQE_L4_INNER_TCP (0u << 1)
128 /* Inner L4 type is UDP. */
129 #define MLX5_ETH_WQE_L4_INNER_UDP (1u << 1)
131 /* Inner L3 type is IPV4. */
132 #define MLX5_ETH_WQE_L3_INNER_IPV4 (0u << 0)
134 /* Inner L3 type is IPV6. */
135 #define MLX5_ETH_WQE_L3_INNER_IPV6 (1u << 0)
137 /* Is flow mark valid. */
138 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
139 #define MLX5_FLOW_MARK_IS_VALID(val) ((val) & 0xffffff00)
141 #define MLX5_FLOW_MARK_IS_VALID(val) ((val) & 0xffffff)
144 /* INVALID is used by packets matching no flow rules. */
145 #define MLX5_FLOW_MARK_INVALID 0
147 /* Maximum allowed value to mark a packet. */
148 #define MLX5_FLOW_MARK_MAX 0xfffff0
150 /* Default mark value used when none is provided. */
151 #define MLX5_FLOW_MARK_DEFAULT 0xffffff
153 /* Maximum number of DS in WQE. */
154 #define MLX5_DSEG_MAX 63
156 /* The completion mode offset in the WQE control segment line 2. */
157 #define MLX5_COMP_MODE_OFFSET 2
159 /* Completion mode. */
160 enum mlx5_completion_mode {
161 MLX5_COMP_ONLY_ERR = 0x0,
162 MLX5_COMP_ONLY_FIRST_ERR = 0x1,
163 MLX5_COMP_ALWAYS = 0x2,
164 MLX5_COMP_CQE_AND_EQE = 0x3,
167 /* Subset of struct mlx5_wqe_eth_seg. */
168 struct mlx5_wqe_eth_seg_small {
173 uint32_t flow_table_metadata;
174 uint16_t inline_hdr_sz;
175 uint8_t inline_hdr[2];
176 } __rte_aligned(MLX5_WQE_DWORD_SIZE);
178 struct mlx5_wqe_inl_small {
181 } __rte_aligned(MLX5_WQE_DWORD_SIZE);
183 struct mlx5_wqe_ctrl {
188 } __rte_aligned(MLX5_WQE_DWORD_SIZE);
190 /* Small common part of the WQE. */
193 struct mlx5_wqe_eth_seg_small eseg;
196 /* Vectorize WQE header. */
206 } __rte_aligned(MLX5_WQE_SIZE);
212 MLX5_MPW_ENHANCED, /* Enhanced Multi-Packet Send WQE, a.k.a MPWv2. */
215 /* MPW session status. */
216 enum mlx5_mpw_state {
217 MLX5_MPW_STATE_OPENED,
218 MLX5_MPW_INL_STATE_OPENED,
219 MLX5_MPW_ENHANCED_STATE_OPENED,
220 MLX5_MPW_STATE_CLOSED,
223 /* MPW session descriptor. */
225 enum mlx5_mpw_state state;
228 unsigned int total_len;
229 volatile struct mlx5_wqe *wqe;
231 volatile struct mlx5_wqe_data_seg *dseg[MLX5_MPW_DSEG_MAX];
232 volatile uint8_t *raw;
236 /* WQE for Multi-Packet RQ. */
237 struct mlx5_wqe_mprq {
238 struct mlx5_wqe_srq_next_seg next_seg;
239 struct mlx5_wqe_data_seg dseg;
242 #define MLX5_MPRQ_LEN_MASK 0x000ffff
243 #define MLX5_MPRQ_LEN_SHIFT 0
244 #define MLX5_MPRQ_STRIDE_NUM_MASK 0x3fff0000
245 #define MLX5_MPRQ_STRIDE_NUM_SHIFT 16
246 #define MLX5_MPRQ_FILLER_MASK 0x80000000
247 #define MLX5_MPRQ_FILLER_SHIFT 31
249 #define MLX5_MPRQ_STRIDE_SHIFT_BYTE 2
251 /* CQ element structure - should be equal to the cache line size */
253 #if (RTE_CACHE_LINE_SIZE == 128)
260 uint32_t rx_hash_res;
261 uint8_t rx_hash_type;
263 uint16_t hdr_type_etc;
268 uint32_t sop_drop_qpn;
269 uint16_t wqe_counter;
274 /* Adding direct verbs to data-path. */
276 /* CQ sequence number mask. */
277 #define MLX5_CQ_SQN_MASK 0x3
279 /* CQ sequence number index. */
280 #define MLX5_CQ_SQN_OFFSET 28
282 /* CQ doorbell index mask. */
283 #define MLX5_CI_MASK 0xffffff
285 /* CQ doorbell offset. */
286 #define MLX5_CQ_ARM_DB 1
288 /* CQ doorbell offset*/
289 #define MLX5_CQ_DOORBELL 0x20
291 /* CQE format value. */
292 #define MLX5_COMPRESSED 0x3
294 /* Write a specific data value to a field. */
295 #define MLX5_MODIFICATION_TYPE_SET 1
297 /* Add a specific data value to a field. */
298 #define MLX5_MODIFICATION_TYPE_ADD 2
300 /* The field of packet to be modified. */
301 enum mlx5_modification_field {
302 MLX5_MODI_OUT_SMAC_47_16 = 1,
303 MLX5_MODI_OUT_SMAC_15_0,
304 MLX5_MODI_OUT_ETHERTYPE,
305 MLX5_MODI_OUT_DMAC_47_16,
306 MLX5_MODI_OUT_DMAC_15_0,
307 MLX5_MODI_OUT_IP_DSCP,
308 MLX5_MODI_OUT_TCP_FLAGS,
309 MLX5_MODI_OUT_TCP_SPORT,
310 MLX5_MODI_OUT_TCP_DPORT,
311 MLX5_MODI_OUT_IPV4_TTL,
312 MLX5_MODI_OUT_UDP_SPORT,
313 MLX5_MODI_OUT_UDP_DPORT,
314 MLX5_MODI_OUT_SIPV6_127_96,
315 MLX5_MODI_OUT_SIPV6_95_64,
316 MLX5_MODI_OUT_SIPV6_63_32,
317 MLX5_MODI_OUT_SIPV6_31_0,
318 MLX5_MODI_OUT_DIPV6_127_96,
319 MLX5_MODI_OUT_DIPV6_95_64,
320 MLX5_MODI_OUT_DIPV6_63_32,
321 MLX5_MODI_OUT_DIPV6_31_0,
324 MLX5_MODI_IN_SMAC_47_16 = 0x31,
325 MLX5_MODI_IN_SMAC_15_0,
326 MLX5_MODI_IN_ETHERTYPE,
327 MLX5_MODI_IN_DMAC_47_16,
328 MLX5_MODI_IN_DMAC_15_0,
329 MLX5_MODI_IN_IP_DSCP,
330 MLX5_MODI_IN_TCP_FLAGS,
331 MLX5_MODI_IN_TCP_SPORT,
332 MLX5_MODI_IN_TCP_DPORT,
333 MLX5_MODI_IN_IPV4_TTL,
334 MLX5_MODI_IN_UDP_SPORT,
335 MLX5_MODI_IN_UDP_DPORT,
336 MLX5_MODI_IN_SIPV6_127_96,
337 MLX5_MODI_IN_SIPV6_95_64,
338 MLX5_MODI_IN_SIPV6_63_32,
339 MLX5_MODI_IN_SIPV6_31_0,
340 MLX5_MODI_IN_DIPV6_127_96,
341 MLX5_MODI_IN_DIPV6_95_64,
342 MLX5_MODI_IN_DIPV6_63_32,
343 MLX5_MODI_IN_DIPV6_31_0,
346 MLX5_MODI_OUT_IPV6_HOPLIMIT,
347 MLX5_MODI_IN_IPV6_HOPLIMIT,
348 MLX5_MODI_META_DATA_REG_A,
349 MLX5_MODI_META_DATA_REG_B = 0x50,
350 MLX5_MODI_META_REG_C_0,
351 MLX5_MODI_META_REG_C_1,
352 MLX5_MODI_META_REG_C_2,
353 MLX5_MODI_META_REG_C_3,
354 MLX5_MODI_META_REG_C_4,
355 MLX5_MODI_META_REG_C_5,
356 MLX5_MODI_META_REG_C_6,
357 MLX5_MODI_META_REG_C_7,
358 MLX5_MODI_OUT_TCP_SEQ_NUM,
359 MLX5_MODI_IN_TCP_SEQ_NUM,
360 MLX5_MODI_OUT_TCP_ACK_NUM,
361 MLX5_MODI_IN_TCP_ACK_NUM = 0x5C,
364 /* Modification sub command. */
365 struct mlx5_modification_cmd {
369 unsigned int length:5;
370 unsigned int rsvd0:3;
371 unsigned int offset:5;
372 unsigned int rsvd1:3;
373 unsigned int field:12;
374 unsigned int action_type:4;
383 typedef uint32_t u32;
384 typedef uint16_t u16;
387 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
388 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
389 #define __mlx5_bit_off(typ, fld) ((unsigned int)(unsigned long) \
390 (&(__mlx5_nullp(typ)->fld)))
391 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - \
392 (__mlx5_bit_off(typ, fld) & 0x1f))
393 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
394 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
395 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << \
396 __mlx5_dw_bit_off(typ, fld))
397 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
398 #define __mlx5_16_off(typ, fld) (__mlx5_bit_off(typ, fld) / 16)
399 #define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - \
400 (__mlx5_bit_off(typ, fld) & 0xf))
401 #define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
402 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
403 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
404 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
405 #define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld))
407 /* insert a value to a struct */
408 #define MLX5_SET(typ, p, fld, v) \
411 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
412 rte_cpu_to_be_32((rte_be_to_cpu_32(*((u32 *)(p) + \
413 __mlx5_dw_off(typ, fld))) & \
414 (~__mlx5_dw_mask(typ, fld))) | \
415 (((_v) & __mlx5_mask(typ, fld)) << \
416 __mlx5_dw_bit_off(typ, fld))); \
419 #define MLX5_SET64(typ, p, fld, v) \
421 assert(__mlx5_bit_sz(typ, fld) == 64); \
422 *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = \
423 rte_cpu_to_be_64(v); \
426 #define MLX5_GET(typ, p, fld) \
427 ((rte_be_to_cpu_32(*((__be32 *)(p) +\
428 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
429 __mlx5_mask(typ, fld))
430 #define MLX5_GET16(typ, p, fld) \
431 ((rte_be_to_cpu_16(*((__be16 *)(p) + \
432 __mlx5_16_off(typ, fld))) >> __mlx5_16_bit_off(typ, fld)) & \
433 __mlx5_mask16(typ, fld))
434 #define MLX5_GET64(typ, p, fld) rte_be_to_cpu_64(*((__be64 *)(p) + \
435 __mlx5_64_off(typ, fld)))
436 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
438 struct mlx5_ifc_fte_match_set_misc_bits {
439 u8 gre_c_present[0x1];
440 u8 reserved_at_1[0x1];
441 u8 gre_k_present[0x1];
442 u8 gre_s_present[0x1];
443 u8 source_vhci_port[0x4];
445 u8 reserved_at_20[0x10];
446 u8 source_port[0x10];
447 u8 outer_second_prio[0x3];
448 u8 outer_second_cfi[0x1];
449 u8 outer_second_vid[0xc];
450 u8 inner_second_prio[0x3];
451 u8 inner_second_cfi[0x1];
452 u8 inner_second_vid[0xc];
453 u8 outer_second_cvlan_tag[0x1];
454 u8 inner_second_cvlan_tag[0x1];
455 u8 outer_second_svlan_tag[0x1];
456 u8 inner_second_svlan_tag[0x1];
457 u8 reserved_at_64[0xc];
458 u8 gre_protocol[0x10];
462 u8 reserved_at_b8[0x8];
463 u8 reserved_at_c0[0x20];
464 u8 reserved_at_e0[0xc];
465 u8 outer_ipv6_flow_label[0x14];
466 u8 reserved_at_100[0xc];
467 u8 inner_ipv6_flow_label[0x14];
468 u8 reserved_at_120[0xe0];
471 struct mlx5_ifc_ipv4_layout_bits {
472 u8 reserved_at_0[0x60];
476 struct mlx5_ifc_ipv6_layout_bits {
480 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
481 struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
482 struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
483 u8 reserved_at_0[0x80];
486 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
505 u8 reserved_at_c0[0x20];
508 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
509 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
512 struct mlx5_ifc_fte_match_mpls_bits {
519 struct mlx5_ifc_fte_match_set_misc2_bits {
520 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
521 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
522 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
523 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
524 u8 reserved_at_80[0x100];
525 u8 metadata_reg_a[0x20];
526 u8 reserved_at_1a0[0x60];
529 struct mlx5_ifc_fte_match_set_misc3_bits {
530 u8 inner_tcp_seq_num[0x20];
531 u8 outer_tcp_seq_num[0x20];
532 u8 inner_tcp_ack_num[0x20];
533 u8 outer_tcp_ack_num[0x20];
534 u8 reserved_at_auto1[0x8];
535 u8 outer_vxlan_gpe_vni[0x18];
536 u8 outer_vxlan_gpe_next_protocol[0x8];
537 u8 outer_vxlan_gpe_flags[0x8];
538 u8 reserved_at_a8[0x10];
539 u8 icmp_header_data[0x20];
540 u8 icmpv6_header_data[0x20];
545 u8 reserved_at_1a0[0xe0];
549 struct mlx5_ifc_fte_match_param_bits {
550 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
551 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
552 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
553 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
554 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
558 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT,
559 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT,
560 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT,
561 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT,
562 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT
566 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
567 MLX5_CMD_OP_CREATE_MKEY = 0x200,
568 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
569 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
573 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
577 struct mlx5_ifc_alloc_flow_counter_out_bits {
579 u8 reserved_at_8[0x18];
581 u8 flow_counter_id[0x20];
582 u8 reserved_at_60[0x20];
585 struct mlx5_ifc_alloc_flow_counter_in_bits {
587 u8 reserved_at_10[0x10];
588 u8 reserved_at_20[0x10];
590 u8 flow_counter_id[0x20];
591 u8 reserved_at_40[0x18];
592 u8 flow_counter_bulk[0x8];
595 struct mlx5_ifc_dealloc_flow_counter_out_bits {
597 u8 reserved_at_8[0x18];
599 u8 reserved_at_40[0x40];
602 struct mlx5_ifc_dealloc_flow_counter_in_bits {
604 u8 reserved_at_10[0x10];
605 u8 reserved_at_20[0x10];
607 u8 flow_counter_id[0x20];
608 u8 reserved_at_60[0x20];
611 struct mlx5_ifc_traffic_counter_bits {
616 struct mlx5_ifc_query_flow_counter_out_bits {
618 u8 reserved_at_8[0x18];
620 u8 reserved_at_40[0x40];
621 struct mlx5_ifc_traffic_counter_bits flow_statistics[];
624 struct mlx5_ifc_query_flow_counter_in_bits {
626 u8 reserved_at_10[0x10];
627 u8 reserved_at_20[0x10];
629 u8 reserved_at_40[0x20];
633 u8 dump_to_memory[0x1];
634 u8 num_of_counters[0x1e];
635 u8 flow_counter_id[0x20];
638 struct mlx5_ifc_mkc_bits {
639 u8 reserved_at_0[0x1];
641 u8 reserved_at_2[0x1];
642 u8 access_mode_4_2[0x3];
643 u8 reserved_at_6[0x7];
644 u8 relaxed_ordering_write[0x1];
645 u8 reserved_at_e[0x1];
646 u8 small_fence_on_rdma_read_response[0x1];
653 u8 access_mode_1_0[0x2];
654 u8 reserved_at_18[0x8];
659 u8 reserved_at_40[0x20];
664 u8 reserved_at_63[0x2];
665 u8 expected_sigerr_count[0x1];
666 u8 reserved_at_66[0x1];
674 u8 bsf_octword_size[0x20];
676 u8 reserved_at_120[0x80];
678 u8 translations_octword_size[0x20];
680 u8 reserved_at_1c0[0x1b];
681 u8 log_page_size[0x5];
683 u8 reserved_at_1e0[0x20];
686 struct mlx5_ifc_create_mkey_out_bits {
688 u8 reserved_at_8[0x18];
692 u8 reserved_at_40[0x8];
695 u8 reserved_at_60[0x20];
698 struct mlx5_ifc_create_mkey_in_bits {
700 u8 reserved_at_10[0x10];
702 u8 reserved_at_20[0x10];
705 u8 reserved_at_40[0x20];
708 u8 reserved_at_61[0x1f];
710 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
712 u8 reserved_at_280[0x80];
714 u8 translations_octword_actual_size[0x20];
716 u8 mkey_umem_id[0x20];
718 u8 mkey_umem_offset[0x40];
720 u8 reserved_at_380[0x500];
722 u8 klm_pas_mtt[][0x20];
726 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0 << 1,
727 MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP = 0xc << 1,
731 MLX5_HCA_CAP_OPMOD_GET_MAX = 0,
732 MLX5_HCA_CAP_OPMOD_GET_CUR = 1,
735 struct mlx5_ifc_cmd_hca_cap_bits {
736 u8 reserved_at_0[0x30];
738 u8 reserved_at_40[0x40];
739 u8 log_max_srq_sz[0x8];
740 u8 log_max_qp_sz[0x8];
741 u8 reserved_at_90[0xb];
743 u8 reserved_at_a0[0xb];
745 u8 reserved_at_b0[0x10];
746 u8 reserved_at_c0[0x8];
747 u8 log_max_cq_sz[0x8];
748 u8 reserved_at_d0[0xb];
750 u8 log_max_eq_sz[0x8];
751 u8 reserved_at_e8[0x2];
752 u8 log_max_mkey[0x6];
753 u8 reserved_at_f0[0x8];
754 u8 dump_fill_mkey[0x1];
755 u8 reserved_at_f9[0x3];
757 u8 max_indirection[0x8];
758 u8 fixed_buffer_size[0x1];
759 u8 log_max_mrw_sz[0x7];
760 u8 force_teardown[0x1];
761 u8 reserved_at_111[0x1];
762 u8 log_max_bsf_list_size[0x6];
763 u8 umr_extended_translation_offset[0x1];
765 u8 log_max_klm_list_size[0x6];
766 u8 reserved_at_120[0xa];
767 u8 log_max_ra_req_dc[0x6];
768 u8 reserved_at_130[0xa];
769 u8 log_max_ra_res_dc[0x6];
770 u8 reserved_at_140[0xa];
771 u8 log_max_ra_req_qp[0x6];
772 u8 reserved_at_150[0xa];
773 u8 log_max_ra_res_qp[0x6];
775 u8 cc_query_allowed[0x1];
776 u8 cc_modify_allowed[0x1];
778 u8 cache_line_128byte[0x1];
779 u8 reserved_at_165[0xa];
781 u8 gid_table_size[0x10];
782 u8 out_of_seq_cnt[0x1];
783 u8 vport_counters[0x1];
784 u8 retransmission_q_counters[0x1];
786 u8 modify_rq_counter_set_id[0x1];
787 u8 rq_delay_drop[0x1];
789 u8 pkey_table_size[0x10];
790 u8 vport_group_manager[0x1];
791 u8 vhca_group_manager[0x1];
794 u8 vnic_env_queue_counters[0x1];
796 u8 nic_flow_table[0x1];
797 u8 eswitch_manager[0x1];
798 u8 device_memory[0x1];
801 u8 local_ca_ack_delay[0x5];
802 u8 port_module_event[0x1];
803 u8 enhanced_error_q_counters[0x1];
805 u8 reserved_at_1b3[0x1];
806 u8 disable_link_up[0x1];
810 u8 reserved_at_1c0[0x1];
814 u8 reserved_at_1c8[0x4];
816 u8 temp_warn_event[0x1];
818 u8 general_notification_event[0x1];
819 u8 reserved_at_1d3[0x2];
823 u8 reserved_at_1d8[0x1];
831 u8 stat_rate_support[0x10];
832 u8 reserved_at_1f0[0xc];
834 u8 compact_address_vector[0x1];
836 u8 reserved_at_202[0x1];
837 u8 ipoib_enhanced_offloads[0x1];
838 u8 ipoib_basic_offloads[0x1];
839 u8 reserved_at_205[0x1];
840 u8 repeated_block_disabled[0x1];
841 u8 umr_modify_entity_size_disabled[0x1];
842 u8 umr_modify_atomic_disabled[0x1];
843 u8 umr_indirect_mkey_disabled[0x1];
845 u8 reserved_at_20c[0x3];
846 u8 drain_sigerr[0x1];
847 u8 cmdif_checksum[0x2];
849 u8 reserved_at_213[0x1];
850 u8 wq_signature[0x1];
851 u8 sctr_data_cqe[0x1];
852 u8 reserved_at_216[0x1];
858 u8 eth_net_offloads[0x1];
861 u8 reserved_at_21f[0x1];
864 u8 cq_moderation[0x1];
865 u8 reserved_at_223[0x3];
869 u8 reserved_at_229[0x1];
870 u8 scqe_break_moderation[0x1];
871 u8 cq_period_start_from_cqe[0x1];
873 u8 reserved_at_22d[0x1];
876 u8 umr_ptr_rlky[0x1];
878 u8 reserved_at_232[0x4];
881 u8 set_deth_sqpn[0x1];
882 u8 reserved_at_239[0x3];
888 u8 reserved_at_241[0x9];
890 u8 reserved_at_250[0x8];
893 u8 driver_version[0x1];
894 u8 pad_tx_eth_packet[0x1];
895 u8 reserved_at_263[0x8];
896 u8 log_bf_reg_size[0x5];
897 u8 reserved_at_270[0xb];
899 u8 num_lag_ports[0x4];
900 u8 reserved_at_280[0x10];
901 u8 max_wqe_sz_sq[0x10];
902 u8 reserved_at_2a0[0x10];
903 u8 max_wqe_sz_rq[0x10];
904 u8 max_flow_counter_31_16[0x10];
905 u8 max_wqe_sz_sq_dc[0x10];
906 u8 reserved_at_2e0[0x7];
908 u8 reserved_at_300[0x10];
909 u8 flow_counter_bulk_alloc[0x08];
911 u8 reserved_at_320[0x3];
912 u8 log_max_transport_domain[0x5];
913 u8 reserved_at_328[0x3];
915 u8 reserved_at_330[0xb];
916 u8 log_max_xrcd[0x5];
917 u8 nic_receive_steering_discard[0x1];
918 u8 receive_discard_vport_down[0x1];
919 u8 transmit_discard_vport_down[0x1];
920 u8 reserved_at_343[0x5];
921 u8 log_max_flow_counter_bulk[0x8];
922 u8 max_flow_counter_15_0[0x10];
923 u8 reserved_at_360[0x3];
925 u8 reserved_at_368[0x3];
927 u8 reserved_at_370[0x3];
929 u8 reserved_at_378[0x3];
931 u8 basic_cyclic_rcv_wqe[0x1];
932 u8 reserved_at_381[0x2];
934 u8 reserved_at_388[0x3];
936 u8 reserved_at_390[0x3];
937 u8 log_max_rqt_size[0x5];
938 u8 reserved_at_398[0x3];
939 u8 log_max_tis_per_sq[0x5];
940 u8 ext_stride_num_range[0x1];
941 u8 reserved_at_3a1[0x2];
942 u8 log_max_stride_sz_rq[0x5];
943 u8 reserved_at_3a8[0x3];
944 u8 log_min_stride_sz_rq[0x5];
945 u8 reserved_at_3b0[0x3];
946 u8 log_max_stride_sz_sq[0x5];
947 u8 reserved_at_3b8[0x3];
948 u8 log_min_stride_sz_sq[0x5];
950 u8 reserved_at_3c1[0x2];
951 u8 log_max_hairpin_queues[0x5];
952 u8 reserved_at_3c8[0x3];
953 u8 log_max_hairpin_wq_data_sz[0x5];
954 u8 reserved_at_3d0[0x3];
955 u8 log_max_hairpin_num_packets[0x5];
956 u8 reserved_at_3d8[0x3];
957 u8 log_max_wq_sz[0x5];
958 u8 nic_vport_change_event[0x1];
959 u8 disable_local_lb_uc[0x1];
960 u8 disable_local_lb_mc[0x1];
961 u8 log_min_hairpin_wq_data_sz[0x5];
962 u8 reserved_at_3e8[0x3];
963 u8 log_max_vlan_list[0x5];
964 u8 reserved_at_3f0[0x3];
965 u8 log_max_current_mc_list[0x5];
966 u8 reserved_at_3f8[0x3];
967 u8 log_max_current_uc_list[0x5];
968 u8 general_obj_types[0x40];
969 u8 reserved_at_440[0x20];
970 u8 reserved_at_460[0x10];
971 u8 max_num_eqs[0x10];
972 u8 reserved_at_480[0x3];
973 u8 log_max_l2_table[0x5];
974 u8 reserved_at_488[0x8];
975 u8 log_uar_page_sz[0x10];
976 u8 reserved_at_4a0[0x20];
977 u8 device_frequency_mhz[0x20];
978 u8 device_frequency_khz[0x20];
979 u8 reserved_at_500[0x20];
980 u8 num_of_uars_per_page[0x20];
981 u8 flex_parser_protocols[0x20];
982 u8 reserved_at_560[0x20];
983 u8 reserved_at_580[0x3c];
984 u8 mini_cqe_resp_stride_index[0x1];
985 u8 cqe_128_always[0x1];
986 u8 cqe_compression_128[0x1];
987 u8 cqe_compression[0x1];
988 u8 cqe_compression_timeout[0x10];
989 u8 cqe_compression_max_num[0x10];
990 u8 reserved_at_5e0[0x10];
991 u8 tag_matching[0x1];
992 u8 rndv_offload_rc[0x1];
993 u8 rndv_offload_dc[0x1];
994 u8 log_tag_matching_list_sz[0x5];
995 u8 reserved_at_5f8[0x3];
997 u8 affiliate_nic_vport_criteria[0x8];
998 u8 native_port_num[0x8];
999 u8 num_vhca_ports[0x8];
1000 u8 reserved_at_618[0x6];
1001 u8 sw_owner_id[0x1];
1002 u8 reserved_at_61f[0x1e1];
1005 struct mlx5_ifc_qos_cap_bits {
1006 u8 packet_pacing[0x1];
1007 u8 esw_scheduling[0x1];
1008 u8 esw_bw_share[0x1];
1009 u8 esw_rate_limit[0x1];
1010 u8 reserved_at_4[0x1];
1011 u8 packet_pacing_burst_bound[0x1];
1012 u8 packet_pacing_typical_size[0x1];
1013 u8 flow_meter_srtcm[0x1];
1014 u8 reserved_at_8[0x8];
1015 u8 log_max_flow_meter[0x8];
1016 u8 flow_meter_reg_id[0x8];
1017 u8 reserved_at_25[0x20];
1018 u8 packet_pacing_max_rate[0x20];
1019 u8 packet_pacing_min_rate[0x20];
1020 u8 reserved_at_80[0x10];
1021 u8 packet_pacing_rate_table_size[0x10];
1022 u8 esw_element_type[0x10];
1023 u8 esw_tsar_type[0x10];
1024 u8 reserved_at_c0[0x10];
1025 u8 max_qos_para_vport[0x10];
1026 u8 max_tsar_bw_share[0x20];
1027 u8 reserved_at_100[0x6e8];
1030 union mlx5_ifc_hca_cap_union_bits {
1031 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
1032 struct mlx5_ifc_qos_cap_bits qos_cap;
1033 u8 reserved_at_0[0x8000];
1036 struct mlx5_ifc_query_hca_cap_out_bits {
1038 u8 reserved_at_8[0x18];
1040 u8 reserved_at_40[0x40];
1041 union mlx5_ifc_hca_cap_union_bits capability;
1044 struct mlx5_ifc_query_hca_cap_in_bits {
1046 u8 reserved_at_10[0x10];
1047 u8 reserved_at_20[0x10];
1049 u8 reserved_at_40[0x40];
1052 /* CQE format mask. */
1053 #define MLX5E_CQE_FORMAT_MASK 0xc
1056 #define MLX5_OPC_MOD_MPW 0x01
1058 /* Compressed Rx CQE structure. */
1059 struct mlx5_mini_cqe8 {
1061 uint32_t rx_hash_result;
1064 uint16_t stride_idx;
1067 uint16_t wqe_counter;
1068 uint8_t s_wqe_opcode;
1076 * Convert a user mark to flow mark.
1079 * Mark value to convert.
1082 * Converted mark value.
1084 static inline uint32_t
1085 mlx5_flow_mark_set(uint32_t val)
1090 * Add one to the user value to differentiate un-marked flows from
1091 * marked flows, if the ID is equal to MLX5_FLOW_MARK_DEFAULT it
1092 * remains untouched.
1094 if (val != MLX5_FLOW_MARK_DEFAULT)
1096 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
1098 * Mark is 24 bits (minus reserved values) but is stored on a 32 bit
1099 * word, byte-swapped by the kernel on little-endian systems. In this
1100 * case, left-shifting the resulting big-endian value ensures the
1101 * least significant 24 bits are retained when converting it back.
1103 ret = rte_cpu_to_be_32(val) >> 8;
1111 * Convert a mark to user mark.
1114 * Mark value to convert.
1117 * Converted mark value.
1119 static inline uint32_t
1120 mlx5_flow_mark_get(uint32_t val)
1123 * Subtract one from the retrieved value. It was added by
1124 * mlx5_flow_mark_set() to distinguish unmarked flows.
1126 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
1127 return (val >> 8) - 1;
1133 #endif /* RTE_PMD_MLX5_PRM_H_ */