1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2021 6WIND S.A.
3 * Copyright 2021 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_RX_H_
7 #define RTE_PMD_MLX5_RX_H_
10 #include <sys/queue.h>
13 #include <rte_mempool.h>
14 #include <rte_common.h>
15 #include <rte_spinlock.h>
17 #include <mlx5_common_mr.h>
20 #include "mlx5_autoconf.h"
22 /* Support tunnel matching. */
23 #define MLX5_FLOW_TUNNEL 10
25 /* First entry must be NULL for comparison. */
26 #define mlx5_mr_btree_len(bt) ((bt)->len - 1)
28 struct mlx5_rxq_stats {
29 #ifdef MLX5_PMD_SOFT_COUNTERS
30 uint64_t ipackets; /**< Total of successfully received packets. */
31 uint64_t ibytes; /**< Total of successfully received bytes. */
33 uint64_t idropped; /**< Total of packets dropped when RX ring full. */
34 uint64_t rx_nombuf; /**< Total of RX mbuf allocation failures. */
37 /* Compressed CQE context. */
39 uint16_t ai; /* Array index. */
40 uint16_t ca; /* Current array index. */
41 uint16_t na; /* Next array index. */
42 uint16_t cq_ci; /* The next CQE. */
43 uint32_t cqe_cnt; /* Number of CQEs. */
46 /* Get pointer to the first stride. */
47 #define mlx5_mprq_buf_addr(ptr, strd_n) (RTE_PTR_ADD((ptr), \
48 sizeof(struct mlx5_mprq_buf) + \
50 sizeof(struct rte_mbuf_ext_shared_info) + \
51 RTE_PKTMBUF_HEADROOM))
53 #define MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES 6
54 #define MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES 9
56 enum mlx5_rxq_err_state {
57 MLX5_RXQ_ERR_STATE_NO_ERROR = 0,
58 MLX5_RXQ_ERR_STATE_NEED_RESET,
59 MLX5_RXQ_ERR_STATE_NEED_READY,
63 MLX5_RXQ_CODE_EXIT = 0,
65 MLX5_RXQ_CODE_DROPPED,
68 struct mlx5_eth_rxseg {
69 struct rte_mempool *mp; /**< Memory pool to allocate segment from. */
70 uint16_t length; /**< Segment data length, configures split point. */
71 uint16_t offset; /**< Data offset from beginning of mbuf data buffer. */
72 uint32_t reserved; /**< Reserved field. */
75 /* RX queue descriptor. */
76 struct mlx5_rxq_data {
77 unsigned int csum:1; /* Enable checksum offloading. */
78 unsigned int hw_timestamp:1; /* Enable HW timestamp. */
79 unsigned int rt_timestamp:1; /* Realtime timestamp format. */
80 unsigned int vlan_strip:1; /* Enable VLAN stripping. */
81 unsigned int crc_present:1; /* CRC must be subtracted. */
82 unsigned int sges_n:3; /* Log 2 of SGEs (max buffers per packet). */
83 unsigned int cqe_n:4; /* Log 2 of CQ elements. */
84 unsigned int elts_n:4; /* Log 2 of Mbufs. */
85 unsigned int rss_hash:1; /* RSS hash result is enabled. */
86 unsigned int mark:1; /* Marked flow available on the queue. */
87 unsigned int strd_num_n:5; /* Log 2 of the number of stride. */
88 unsigned int strd_sz_n:4; /* Log 2 of stride size. */
89 unsigned int strd_shift_en:1; /* Enable 2bytes shift on a stride. */
90 unsigned int err_state:2; /* enum mlx5_rxq_err_state. */
91 unsigned int strd_scatter_en:1; /* Scattered packets from a stride. */
92 unsigned int lro:1; /* Enable LRO. */
93 unsigned int dynf_meta:1; /* Dynamic metadata is configured. */
94 unsigned int mcqe_format:3; /* CQE compression format. */
95 volatile uint32_t *rq_db;
96 volatile uint32_t *cq_db;
100 uint16_t consumed_strd; /* Number of consumed strides in WQE. */
103 uint16_t rq_repl_thresh; /* Threshold for buffer replenishment. */
106 struct rxq_zip zip; /* Compressed context. */
107 uint16_t decompressed;
108 /* Number of ready mbufs decompressed from the CQ. */
110 struct mlx5_mr_ctrl mr_ctrl; /* MR control descriptor. */
111 uint16_t mprq_max_memcpy_len; /* Maximum size of packet to memcpy. */
113 volatile struct mlx5_cqe(*cqes)[];
114 struct rte_mbuf *(*elts)[];
115 struct mlx5_mprq_buf *(*mprq_bufs)[];
116 struct rte_mempool *mp;
117 struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */
118 struct mlx5_mprq_buf *mprq_repl; /* Stashed mbuf for replenish. */
119 struct mlx5_dev_ctx_shared *sh; /* Shared context. */
120 uint16_t idx; /* Queue index. */
121 struct mlx5_rxq_stats stats;
122 rte_xmm_t mbuf_initializer; /* Default rearm/flags for vectorized Rx. */
123 struct rte_mbuf fake_mbuf; /* elts padding for vectorized Rx. */
124 void *cq_uar; /* Verbs CQ user access region. */
125 uint32_t cqn; /* CQ number. */
126 uint8_t cq_arm_sn; /* CQ arm seq number. */
128 rte_spinlock_t *uar_lock_cq;
129 /* CQ (UAR) access lock required for 32bit implementations */
131 uint32_t tunnel; /* Tunnel information. */
132 int timestamp_offset; /* Dynamic mbuf field for timestamp. */
133 uint64_t timestamp_rx_flag; /* Dynamic mbuf flag for timestamp. */
134 uint64_t flow_meta_mask;
135 int32_t flow_meta_offset;
136 uint32_t flow_meta_port_mask;
137 uint32_t rxseg_n; /* Number of split segment descriptions. */
138 struct mlx5_eth_rxseg rxseg[MLX5_MAX_RXQ_NSEG];
139 /* Buffer split segment descriptions - sizes, offsets, pools. */
140 } __rte_cache_aligned;
143 MLX5_RXQ_TYPE_STANDARD, /* Standard Rx queue. */
144 MLX5_RXQ_TYPE_HAIRPIN, /* Hairpin Rx queue. */
145 MLX5_RXQ_TYPE_UNDEFINED,
148 /* RX queue control descriptor. */
149 struct mlx5_rxq_ctrl {
150 struct mlx5_rxq_data rxq; /* Data path structure. */
151 LIST_ENTRY(mlx5_rxq_ctrl) next; /* Pointer to the next element. */
152 LIST_HEAD(priv, mlx5_rxq_priv) owners; /* Owner rxq list. */
153 struct mlx5_rxq_obj *obj; /* Verbs/DevX elements. */
154 struct mlx5_dev_ctx_shared *sh; /* Shared context. */
155 struct mlx5_priv *priv; /* Back pointer to private data. */
156 enum mlx5_rxq_type type; /* Rxq type. */
157 unsigned int socket; /* CPU socket ID for allocations. */
158 uint32_t share_group; /* Group ID of shared RXQ. */
159 uint16_t share_qid; /* Shared RxQ ID in group. */
160 unsigned int irq:1; /* Whether IRQ is enabled. */
161 uint32_t flow_mark_n; /* Number of Mark/Flag flows using this Queue. */
162 uint32_t flow_tunnels_n[MLX5_FLOW_TUNNEL]; /* Tunnels counters. */
163 uint32_t wqn; /* WQ number. */
164 uint16_t dump_file_n; /* Number of dump files. */
167 /* RX queue private data. */
168 struct mlx5_rxq_priv {
169 uint16_t idx; /* Queue index. */
170 uint32_t refcnt; /* Reference counter. */
171 struct mlx5_rxq_ctrl *ctrl; /* Shared Rx Queue. */
172 LIST_ENTRY(mlx5_rxq_priv) owner_entry; /* Entry in shared rxq_ctrl. */
173 struct mlx5_priv *priv; /* Back pointer to private data. */
174 struct rte_eth_hairpin_conf hairpin_conf; /* Hairpin configuration. */
175 uint32_t hairpin_status; /* Hairpin binding status. */
180 extern uint8_t rss_hash_default_key[];
182 unsigned int mlx5_rxq_cqe_num(struct mlx5_rxq_data *rxq_data);
183 int mlx5_mprq_free_mp(struct rte_eth_dev *dev);
184 int mlx5_mprq_alloc_mp(struct rte_eth_dev *dev);
185 int mlx5_rx_queue_start(struct rte_eth_dev *dev, uint16_t queue_id);
186 int mlx5_rx_queue_stop(struct rte_eth_dev *dev, uint16_t queue_id);
187 int mlx5_rx_queue_start_primary(struct rte_eth_dev *dev, uint16_t queue_id);
188 int mlx5_rx_queue_stop_primary(struct rte_eth_dev *dev, uint16_t queue_id);
189 int mlx5_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
190 unsigned int socket, const struct rte_eth_rxconf *conf,
191 struct rte_mempool *mp);
192 int mlx5_rx_hairpin_queue_setup
193 (struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
194 const struct rte_eth_hairpin_conf *hairpin_conf);
195 void mlx5_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid);
196 int mlx5_rx_intr_vec_enable(struct rte_eth_dev *dev);
197 void mlx5_rx_intr_vec_disable(struct rte_eth_dev *dev);
198 int mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id);
199 int mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id);
200 int mlx5_rxq_obj_verify(struct rte_eth_dev *dev);
201 struct mlx5_rxq_ctrl *mlx5_rxq_new(struct rte_eth_dev *dev,
202 struct mlx5_rxq_priv *rxq,
203 uint16_t desc, unsigned int socket,
204 const struct rte_eth_rxconf *conf,
205 const struct rte_eth_rxseg_split *rx_seg,
207 struct mlx5_rxq_ctrl *mlx5_rxq_hairpin_new
208 (struct rte_eth_dev *dev, struct mlx5_rxq_priv *rxq, uint16_t desc,
209 const struct rte_eth_hairpin_conf *hairpin_conf);
210 struct mlx5_rxq_priv *mlx5_rxq_ref(struct rte_eth_dev *dev, uint16_t idx);
211 uint32_t mlx5_rxq_deref(struct rte_eth_dev *dev, uint16_t idx);
212 struct mlx5_rxq_priv *mlx5_rxq_get(struct rte_eth_dev *dev, uint16_t idx);
213 struct mlx5_rxq_ctrl *mlx5_rxq_ctrl_get(struct rte_eth_dev *dev, uint16_t idx);
214 struct mlx5_rxq_data *mlx5_rxq_data_get(struct rte_eth_dev *dev, uint16_t idx);
215 int mlx5_rxq_release(struct rte_eth_dev *dev, uint16_t idx);
216 int mlx5_rxq_verify(struct rte_eth_dev *dev);
217 int rxq_alloc_elts(struct mlx5_rxq_ctrl *rxq_ctrl);
218 int mlx5_ind_table_obj_verify(struct rte_eth_dev *dev);
219 struct mlx5_ind_table_obj *mlx5_ind_table_obj_get(struct rte_eth_dev *dev,
220 const uint16_t *queues,
222 int mlx5_ind_table_obj_release(struct rte_eth_dev *dev,
223 struct mlx5_ind_table_obj *ind_tbl,
225 int mlx5_ind_table_obj_setup(struct rte_eth_dev *dev,
226 struct mlx5_ind_table_obj *ind_tbl);
227 int mlx5_ind_table_obj_modify(struct rte_eth_dev *dev,
228 struct mlx5_ind_table_obj *ind_tbl,
229 uint16_t *queues, const uint32_t queues_n,
231 int mlx5_ind_table_obj_attach(struct rte_eth_dev *dev,
232 struct mlx5_ind_table_obj *ind_tbl);
233 int mlx5_ind_table_obj_detach(struct rte_eth_dev *dev,
234 struct mlx5_ind_table_obj *ind_tbl);
235 struct mlx5_list_entry *mlx5_hrxq_create_cb(void *tool_ctx, void *cb_ctx);
236 int mlx5_hrxq_match_cb(void *tool_ctx, struct mlx5_list_entry *entry,
238 void mlx5_hrxq_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry);
239 struct mlx5_list_entry *mlx5_hrxq_clone_cb(void *tool_ctx,
240 struct mlx5_list_entry *entry,
241 void *cb_ctx __rte_unused);
242 void mlx5_hrxq_clone_free_cb(void *tool_ctx __rte_unused,
243 struct mlx5_list_entry *entry);
244 uint32_t mlx5_hrxq_get(struct rte_eth_dev *dev,
245 struct mlx5_flow_rss_desc *rss_desc);
246 int mlx5_hrxq_release(struct rte_eth_dev *dev, uint32_t hxrq_idx);
247 uint32_t mlx5_hrxq_verify(struct rte_eth_dev *dev);
248 enum mlx5_rxq_type mlx5_rxq_get_type(struct rte_eth_dev *dev, uint16_t idx);
249 const struct rte_eth_hairpin_conf *mlx5_rxq_get_hairpin_conf
250 (struct rte_eth_dev *dev, uint16_t idx);
251 struct mlx5_hrxq *mlx5_drop_action_create(struct rte_eth_dev *dev);
252 void mlx5_drop_action_destroy(struct rte_eth_dev *dev);
253 uint64_t mlx5_get_rx_port_offloads(void);
254 uint64_t mlx5_get_rx_queue_offloads(struct rte_eth_dev *dev);
255 void mlx5_rxq_timestamp_set(struct rte_eth_dev *dev);
256 int mlx5_hrxq_modify(struct rte_eth_dev *dev, uint32_t hxrq_idx,
257 const uint8_t *rss_key, uint32_t rss_key_len,
258 uint64_t hash_fields,
259 const uint16_t *queues, uint32_t queues_n);
263 uint16_t mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n);
264 void mlx5_rxq_initialize(struct mlx5_rxq_data *rxq);
265 __rte_noinline int mlx5_rx_err_handle(struct mlx5_rxq_data *rxq, uint8_t vec);
266 void mlx5_mprq_buf_free(struct mlx5_mprq_buf *buf);
267 uint16_t mlx5_rx_burst_mprq(void *dpdk_rxq, struct rte_mbuf **pkts,
269 uint16_t removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts,
271 int mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset);
272 uint32_t mlx5_rx_queue_count(void *rx_queue);
273 void mlx5_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
274 struct rte_eth_rxq_info *qinfo);
275 int mlx5_rx_burst_mode_get(struct rte_eth_dev *dev, uint16_t rx_queue_id,
276 struct rte_eth_burst_mode *mode);
277 int mlx5_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc);
279 /* Vectorized version of mlx5_rx.c */
280 int mlx5_rxq_check_vec_support(struct mlx5_rxq_data *rxq_data);
281 int mlx5_check_vec_rx_support(struct rte_eth_dev *dev);
282 uint16_t mlx5_rx_burst_vec(void *dpdk_rxq, struct rte_mbuf **pkts,
284 uint16_t mlx5_rx_burst_mprq_vec(void *dpdk_rxq, struct rte_mbuf **pkts,
287 static int mlx5_rxq_mprq_enabled(struct mlx5_rxq_data *rxq);
290 * Query LKey from a packet buffer for Rx. No need to flush local caches
291 * as the Rx mempool database entries are valid for the lifetime of the queue.
294 * Pointer to Rx queue structure.
299 * Searched LKey on success, UINT32_MAX on no match.
300 * This function always succeeds on valid input.
302 static __rte_always_inline uint32_t
303 mlx5_rx_addr2mr(struct mlx5_rxq_data *rxq, uintptr_t addr)
305 struct mlx5_mr_ctrl *mr_ctrl = &rxq->mr_ctrl;
306 struct mlx5_rxq_ctrl *rxq_ctrl;
307 struct rte_mempool *mp;
310 /* Linear search on MR cache array. */
311 lkey = mlx5_mr_lookup_lkey(mr_ctrl->cache, &mr_ctrl->mru,
312 MLX5_MR_CACHE_N, addr);
313 if (likely(lkey != UINT32_MAX))
316 * Slower search in the mempool database on miss.
317 * During queue creation rxq->sh is not yet set, so we use rxq_ctrl.
319 rxq_ctrl = container_of(rxq, struct mlx5_rxq_ctrl, rxq);
320 mp = mlx5_rxq_mprq_enabled(rxq) ? rxq->mprq_mp : rxq->mp;
321 return mlx5_mr_mempool2mr_bh(&rxq_ctrl->priv->sh->cdev->mr_scache,
325 #define mlx5_rx_mb2mr(rxq, mb) mlx5_rx_addr2mr(rxq, (uintptr_t)((mb)->buf_addr))
328 * Convert timestamp from HW format to linear counter
329 * from Packet Pacing Clock Queue CQE timestamp format.
332 * Pointer to the device shared context. Might be needed
333 * to convert according current device configuration.
335 * Timestamp from CQE to convert.
339 static __rte_always_inline uint64_t
340 mlx5_txpp_convert_rx_ts(struct mlx5_dev_ctx_shared *sh, uint64_t ts)
343 return (ts & UINT32_MAX) + (ts >> 32) * NS_PER_S;
347 * Set timestamp in mbuf dynamic field.
350 * Structure to write into.
352 * Dynamic field offset in mbuf structure.
356 static __rte_always_inline void
357 mlx5_timestamp_set(struct rte_mbuf *mbuf, int offset,
358 rte_mbuf_timestamp_t timestamp)
360 *RTE_MBUF_DYNFIELD(mbuf, offset, rte_mbuf_timestamp_t *) = timestamp;
364 * Replace MPRQ buffer.
367 * Pointer to Rx queue structure.
369 * RQ index to replace.
371 static __rte_always_inline void
372 mprq_buf_replace(struct mlx5_rxq_data *rxq, uint16_t rq_idx)
374 const uint32_t strd_n = 1 << rxq->strd_num_n;
375 struct mlx5_mprq_buf *rep = rxq->mprq_repl;
376 volatile struct mlx5_wqe_data_seg *wqe =
377 &((volatile struct mlx5_wqe_mprq *)rxq->wqes)[rq_idx].dseg;
378 struct mlx5_mprq_buf *buf = (*rxq->mprq_bufs)[rq_idx];
381 if (__atomic_load_n(&buf->refcnt, __ATOMIC_RELAXED) > 1) {
382 MLX5_ASSERT(rep != NULL);
383 /* Replace MPRQ buf. */
384 (*rxq->mprq_bufs)[rq_idx] = rep;
386 addr = mlx5_mprq_buf_addr(rep, strd_n);
387 wqe->addr = rte_cpu_to_be_64((uintptr_t)addr);
388 /* If there's only one MR, no need to replace LKey in WQE. */
389 if (unlikely(mlx5_mr_btree_len(&rxq->mr_ctrl.cache_bh) > 1))
390 wqe->lkey = mlx5_rx_addr2mr(rxq, (uintptr_t)addr);
391 /* Stash a mbuf for next replacement. */
392 if (likely(!rte_mempool_get(rxq->mprq_mp, (void **)&rep)))
393 rxq->mprq_repl = rep;
395 rxq->mprq_repl = NULL;
396 /* Release the old buffer. */
397 mlx5_mprq_buf_free(buf);
398 } else if (unlikely(rxq->mprq_repl == NULL)) {
399 struct mlx5_mprq_buf *rep;
402 * Currently, the MPRQ mempool is out of buffer
403 * and doing memcpy regardless of the size of Rx
404 * packet. Retry allocation to get back to
407 if (!rte_mempool_get(rxq->mprq_mp, (void **)&rep))
408 rxq->mprq_repl = rep;
413 * Attach or copy MPRQ buffer content to a packet.
416 * Pointer to Rx queue structure.
418 * Pointer to a packet to fill.
422 * Pointer to a MPRQ buffer to take the data from.
424 * Stride index to start from.
426 * Number of strides to consume.
428 static __rte_always_inline enum mlx5_rqx_code
429 mprq_buf_to_pkt(struct mlx5_rxq_data *rxq, struct rte_mbuf *pkt, uint32_t len,
430 struct mlx5_mprq_buf *buf, uint16_t strd_idx, uint16_t strd_cnt)
432 const uint32_t strd_n = 1 << rxq->strd_num_n;
433 const uint16_t strd_sz = 1 << rxq->strd_sz_n;
434 const uint16_t strd_shift =
435 MLX5_MPRQ_STRIDE_SHIFT_BYTE * rxq->strd_shift_en;
436 const int32_t hdrm_overlap =
437 len + RTE_PKTMBUF_HEADROOM - strd_cnt * strd_sz;
438 const uint32_t offset = strd_idx * strd_sz + strd_shift;
439 void *addr = RTE_PTR_ADD(mlx5_mprq_buf_addr(buf, strd_n), offset);
442 * Memcpy packets to the target mbuf if:
443 * - The size of packet is smaller than mprq_max_memcpy_len.
444 * - Out of buffer in the Mempool for Multi-Packet RQ.
445 * - The packet's stride overlaps a headroom and scatter is off.
447 if (len <= rxq->mprq_max_memcpy_len ||
448 rxq->mprq_repl == NULL ||
449 (hdrm_overlap > 0 && !rxq->strd_scatter_en)) {
451 (uint32_t)(pkt->buf_len - RTE_PKTMBUF_HEADROOM))) {
452 rte_memcpy(rte_pktmbuf_mtod(pkt, void *),
455 } else if (rxq->strd_scatter_en) {
456 struct rte_mbuf *prev = pkt;
457 uint32_t seg_len = RTE_MIN(len, (uint32_t)
458 (pkt->buf_len - RTE_PKTMBUF_HEADROOM));
459 uint32_t rem_len = len - seg_len;
461 rte_memcpy(rte_pktmbuf_mtod(pkt, void *),
463 DATA_LEN(pkt) = seg_len;
465 struct rte_mbuf *next =
466 rte_pktmbuf_alloc(rxq->mp);
468 if (unlikely(next == NULL))
469 return MLX5_RXQ_CODE_NOMBUF;
471 SET_DATA_OFF(next, 0);
472 addr = RTE_PTR_ADD(addr, seg_len);
473 seg_len = RTE_MIN(rem_len, (uint32_t)
474 (next->buf_len - RTE_PKTMBUF_HEADROOM));
476 (rte_pktmbuf_mtod(next, void *),
478 DATA_LEN(next) = seg_len;
484 return MLX5_RXQ_CODE_DROPPED;
488 struct rte_mbuf_ext_shared_info *shinfo;
489 uint16_t buf_len = strd_cnt * strd_sz;
492 /* Increment the refcnt of the whole chunk. */
493 __atomic_add_fetch(&buf->refcnt, 1, __ATOMIC_RELAXED);
494 MLX5_ASSERT(__atomic_load_n(&buf->refcnt,
495 __ATOMIC_RELAXED) <= strd_n + 1);
496 buf_addr = RTE_PTR_SUB(addr, RTE_PKTMBUF_HEADROOM);
498 * MLX5 device doesn't use iova but it is necessary in a
499 * case where the Rx packet is transmitted via a
502 buf_iova = rte_mempool_virt2iova(buf) +
503 RTE_PTR_DIFF(buf_addr, buf);
504 shinfo = &buf->shinfos[strd_idx];
505 rte_mbuf_ext_refcnt_set(shinfo, 1);
507 * RTE_MBUF_F_EXTERNAL will be set to pkt->ol_flags when
508 * attaching the stride to mbuf and more offload flags
509 * will be added below by calling rxq_cq_to_mbuf().
510 * Other fields will be overwritten.
512 rte_pktmbuf_attach_extbuf(pkt, buf_addr, buf_iova,
514 /* Set mbuf head-room. */
515 SET_DATA_OFF(pkt, RTE_PKTMBUF_HEADROOM);
516 MLX5_ASSERT(pkt->ol_flags == RTE_MBUF_F_EXTERNAL);
517 MLX5_ASSERT(rte_pktmbuf_tailroom(pkt) >=
518 len - (hdrm_overlap > 0 ? hdrm_overlap : 0));
521 * Copy the last fragment of a packet (up to headroom
522 * size bytes) in case there is a stride overlap with
523 * a next packet's headroom. Allocate a separate mbuf
524 * to store this fragment and link it. Scatter is on.
526 if (hdrm_overlap > 0) {
527 MLX5_ASSERT(rxq->strd_scatter_en);
528 struct rte_mbuf *seg =
529 rte_pktmbuf_alloc(rxq->mp);
531 if (unlikely(seg == NULL))
532 return MLX5_RXQ_CODE_NOMBUF;
533 SET_DATA_OFF(seg, 0);
534 rte_memcpy(rte_pktmbuf_mtod(seg, void *),
535 RTE_PTR_ADD(addr, len - hdrm_overlap),
537 DATA_LEN(seg) = hdrm_overlap;
538 DATA_LEN(pkt) = len - hdrm_overlap;
543 return MLX5_RXQ_CODE_EXIT;
547 * Check whether Multi-Packet RQ can be enabled for the device.
550 * Pointer to Ethernet device.
553 * 1 if supported, negative errno value if not.
555 static __rte_always_inline int
556 mlx5_check_mprq_support(struct rte_eth_dev *dev)
558 struct mlx5_priv *priv = dev->data->dev_private;
560 if (priv->config.mprq.enabled &&
561 priv->rxqs_n >= priv->config.mprq.min_rxqs_num)
567 * Check whether Multi-Packet RQ is enabled for the Rx queue.
570 * Pointer to receive queue structure.
573 * 0 if disabled, otherwise enabled.
575 static __rte_always_inline int
576 mlx5_rxq_mprq_enabled(struct mlx5_rxq_data *rxq)
578 return rxq->strd_num_n > 0;
582 * Check whether Multi-Packet RQ is enabled for the device.
585 * Pointer to Ethernet device.
588 * 0 if disabled, otherwise enabled.
590 static __rte_always_inline int
591 mlx5_mprq_enabled(struct rte_eth_dev *dev)
593 struct mlx5_priv *priv = dev->data->dev_private;
598 if (mlx5_check_mprq_support(dev) < 0)
600 /* All the configured queues should be enabled. */
601 for (i = 0; i < priv->rxqs_n; ++i) {
602 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
603 struct mlx5_rxq_ctrl *rxq_ctrl = container_of
604 (rxq, struct mlx5_rxq_ctrl, rxq);
606 if (rxq == NULL || rxq_ctrl->type != MLX5_RXQ_TYPE_STANDARD)
609 if (mlx5_rxq_mprq_enabled(rxq))
612 /* Multi-Packet RQ can't be partially configured. */
613 MLX5_ASSERT(n == 0 || n == n_ibv);
617 #endif /* RTE_PMD_MLX5_RX_H_ */