drivers/net/mlx5/mlx5_rxq.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <stddef.h>
   7 #include <assert.h>
   8 #include <errno.h>
   9 #include <string.h>
  10 #include <stdint.h>
  11 #include <fcntl.h>
  12 #include <sys/queue.h>
  13
  14 /* Verbs header. */
  15 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  16 #ifdef PEDANTIC
  17 #pragma GCC diagnostic ignored "-Wpedantic"
  18 #endif
  19 #include <infiniband/verbs.h>
  20 #include <infiniband/mlx5dv.h>
  21 #ifdef PEDANTIC
  22 #pragma GCC diagnostic error "-Wpedantic"
  23 #endif
  24
  25 #include <rte_mbuf.h>
  26 #include <rte_malloc.h>
  27 #include <rte_ethdev_driver.h>
  28 #include <rte_common.h>
  29 #include <rte_interrupts.h>
  30 #include <rte_debug.h>
  31 #include <rte_io.h>
  32
  33 #include "mlx5.h"
  34 #include "mlx5_rxtx.h"
  35 #include "mlx5_utils.h"
  36 #include "mlx5_autoconf.h"
  37 #include "mlx5_defs.h"
  38 #include "mlx5_glue.h"
  39
  40 /* Default RSS hash key also used for ConnectX-3. */
  41 uint8_t rss_hash_default_key[] = {
  42         0x2c, 0xc6, 0x81, 0xd1,
  43         0x5b, 0xdb, 0xf4, 0xf7,
  44         0xfc, 0xa2, 0x83, 0x19,
  45         0xdb, 0x1a, 0x3e, 0x94,
  46         0x6b, 0x9e, 0x38, 0xd9,
  47         0x2c, 0x9c, 0x03, 0xd1,
  48         0xad, 0x99, 0x44, 0xa7,
  49         0xd9, 0x56, 0x3d, 0x59,
  50         0x06, 0x3c, 0x25, 0xf3,
  51         0xfc, 0x1f, 0xdc, 0x2a,
  52 };
  53
  54 /* Length of the default RSS hash key. */
  55 static_assert(MLX5_RSS_HASH_KEY_LEN ==
  56               (unsigned int)sizeof(rss_hash_default_key),
  57               "wrong RSS default key size.");
  58
  59 /**
  60  * Check whether Multi-Packet RQ can be enabled for the device.
  61  *
  62  * @param dev
  63  *   Pointer to Ethernet device.
  64  *
  65  * @return
  66  *   1 if supported, negative errno value if not.
  67  */
  68 inline int
  69 mlx5_check_mprq_support(struct rte_eth_dev *dev)
  70 {
  71         struct mlx5_priv *priv = dev->data->dev_private;
  72
  73         if (priv->config.mprq.enabled &&
  74             priv->rxqs_n >= priv->config.mprq.min_rxqs_num)
  75                 return 1;
  76         return -ENOTSUP;
  77 }
  78
  79 /**
  80  * Check whether Multi-Packet RQ is enabled for the Rx queue.
  81  *
  82  *  @param rxq
  83  *     Pointer to receive queue structure.
  84  *
  85  * @return
  86  *   0 if disabled, otherwise enabled.
  87  */
  88 inline int
  89 mlx5_rxq_mprq_enabled(struct mlx5_rxq_data *rxq)
  90 {
  91         return rxq->strd_num_n > 0;
  92 }
  93
  94 /**
  95  * Check whether Multi-Packet RQ is enabled for the device.
  96  *
  97  * @param dev
  98  *   Pointer to Ethernet device.
  99  *
 100  * @return
 101  *   0 if disabled, otherwise enabled.
 102  */
 103 inline int
 104 mlx5_mprq_enabled(struct rte_eth_dev *dev)
 105 {
 106         struct mlx5_priv *priv = dev->data->dev_private;
 107         uint16_t i;
 108         uint16_t n = 0;
 109
 110         if (mlx5_check_mprq_support(dev) < 0)
 111                 return 0;
 112         /* All the configured queues should be enabled. */
 113         for (i = 0; i < priv->rxqs_n; ++i) {
 114                 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
 115
 116                 if (!rxq)
 117                         continue;
 118                 if (mlx5_rxq_mprq_enabled(rxq))
 119                         ++n;
 120         }
 121         /* Multi-Packet RQ can't be partially configured. */
 122         assert(n == 0 || n == priv->rxqs_n);
 123         return n == priv->rxqs_n;
 124 }
 125
 126 /**
 127  * Allocate RX queue elements for Multi-Packet RQ.
 128  *
 129  * @param rxq_ctrl
 130  *   Pointer to RX queue structure.
 131  *
 132  * @return
 133  *   0 on success, a negative errno value otherwise and rte_errno is set.
 134  */
 135 static int
 136 rxq_alloc_elts_mprq(struct mlx5_rxq_ctrl *rxq_ctrl)
 137 {
 138         struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
 139         unsigned int wqe_n = 1 << rxq->elts_n;
 140         unsigned int i;
 141         int err;
 142
 143         /* Iterate on segments. */
 144         for (i = 0; i <= wqe_n; ++i) {
 145                 struct mlx5_mprq_buf *buf;
 146
 147                 if (rte_mempool_get(rxq->mprq_mp, (void **)&buf) < 0) {
 148                         DRV_LOG(ERR, "port %u empty mbuf pool", rxq->port_id);
 149                         rte_errno = ENOMEM;
 150                         goto error;
 151                 }
 152                 if (i < wqe_n)
 153                         (*rxq->mprq_bufs)[i] = buf;
 154                 else
 155                         rxq->mprq_repl = buf;
 156         }
 157         DRV_LOG(DEBUG,
 158                 "port %u Rx queue %u allocated and configured %u segments",
 159                 rxq->port_id, rxq->idx, wqe_n);
 160         return 0;
 161 error:
 162         err = rte_errno; /* Save rte_errno before cleanup. */
 163         wqe_n = i;
 164         for (i = 0; (i != wqe_n); ++i) {
 165                 if ((*rxq->mprq_bufs)[i] != NULL)
 166                         rte_mempool_put(rxq->mprq_mp,
 167                                         (*rxq->mprq_bufs)[i]);
 168                 (*rxq->mprq_bufs)[i] = NULL;
 169         }
 170         DRV_LOG(DEBUG, "port %u Rx queue %u failed, freed everything",
 171                 rxq->port_id, rxq->idx);
 172         rte_errno = err; /* Restore rte_errno. */
 173         return -rte_errno;
 174 }
 175
 176 /**
 177  * Allocate RX queue elements for Single-Packet RQ.
 178  *
 179  * @param rxq_ctrl
 180  *   Pointer to RX queue structure.
 181  *
 182  * @return
 183  *   0 on success, errno value on failure.
 184  */
 185 static int
 186 rxq_alloc_elts_sprq(struct mlx5_rxq_ctrl *rxq_ctrl)
 187 {
 188         const unsigned int sges_n = 1 << rxq_ctrl->rxq.sges_n;
 189         unsigned int elts_n = 1 << rxq_ctrl->rxq.elts_n;
 190         unsigned int i;
 191         int err;
 192
 193         /* Iterate on segments. */
 194         for (i = 0; (i != elts_n); ++i) {
 195                 struct rte_mbuf *buf;
 196
 197                 buf = rte_pktmbuf_alloc(rxq_ctrl->rxq.mp);
 198                 if (buf == NULL) {
 199                         DRV_LOG(ERR, "port %u empty mbuf pool",
 200                                 PORT_ID(rxq_ctrl->priv));
 201                         rte_errno = ENOMEM;
 202                         goto error;
 203                 }
 204                 /* Headroom is reserved by rte_pktmbuf_alloc(). */
 205                 assert(DATA_OFF(buf) == RTE_PKTMBUF_HEADROOM);
 206                 /* Buffer is supposed to be empty. */
 207                 assert(rte_pktmbuf_data_len(buf) == 0);
 208                 assert(rte_pktmbuf_pkt_len(buf) == 0);
 209                 assert(!buf->next);
 210                 /* Only the first segment keeps headroom. */
 211                 if (i % sges_n)
 212                         SET_DATA_OFF(buf, 0);
 213                 PORT(buf) = rxq_ctrl->rxq.port_id;
 214                 DATA_LEN(buf) = rte_pktmbuf_tailroom(buf);
 215                 PKT_LEN(buf) = DATA_LEN(buf);
 216                 NB_SEGS(buf) = 1;
 217                 (*rxq_ctrl->rxq.elts)[i] = buf;
 218         }
 219         /* If Rx vector is activated. */
 220         if (mlx5_rxq_check_vec_support(&rxq_ctrl->rxq) > 0) {
 221                 struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
 222                 struct rte_mbuf *mbuf_init = &rxq->fake_mbuf;
 223                 int j;
 224
 225                 /* Initialize default rearm_data for vPMD. */
 226                 mbuf_init->data_off = RTE_PKTMBUF_HEADROOM;
 227                 rte_mbuf_refcnt_set(mbuf_init, 1);
 228                 mbuf_init->nb_segs = 1;
 229                 mbuf_init->port = rxq->port_id;
 230                 /*
 231                  * prevent compiler reordering:
 232                  * rearm_data covers previous fields.
 233                  */
 234                 rte_compiler_barrier();
 235                 rxq->mbuf_initializer =
 236                         *(uint64_t *)&mbuf_init->rearm_data;
 237                 /* Padding with a fake mbuf for vectorized Rx. */
 238                 for (j = 0; j < MLX5_VPMD_DESCS_PER_LOOP; ++j)
 239                         (*rxq->elts)[elts_n + j] = &rxq->fake_mbuf;
 240         }
 241         DRV_LOG(DEBUG,
 242                 "port %u Rx queue %u allocated and configured %u segments"
 243                 " (max %u packets)",
 244                 PORT_ID(rxq_ctrl->priv), rxq_ctrl->rxq.idx, elts_n,
 245                 elts_n / (1 << rxq_ctrl->rxq.sges_n));
 246         return 0;
 247 error:
 248         err = rte_errno; /* Save rte_errno before cleanup. */
 249         elts_n = i;
 250         for (i = 0; (i != elts_n); ++i) {
 251                 if ((*rxq_ctrl->rxq.elts)[i] != NULL)
 252                         rte_pktmbuf_free_seg((*rxq_ctrl->rxq.elts)[i]);
 253                 (*rxq_ctrl->rxq.elts)[i] = NULL;
 254         }
 255         DRV_LOG(DEBUG, "port %u Rx queue %u failed, freed everything",
 256                 PORT_ID(rxq_ctrl->priv), rxq_ctrl->rxq.idx);
 257         rte_errno = err; /* Restore rte_errno. */
 258         return -rte_errno;
 259 }
 260
 261 /**
 262  * Allocate RX queue elements.
 263  *
 264  * @param rxq_ctrl
 265  *   Pointer to RX queue structure.
 266  *
 267  * @return
 268  *   0 on success, errno value on failure.
 269  */
 270 int
 271 rxq_alloc_elts(struct mlx5_rxq_ctrl *rxq_ctrl)
 272 {
 273         return mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq) ?
 274                rxq_alloc_elts_mprq(rxq_ctrl) : rxq_alloc_elts_sprq(rxq_ctrl);
 275 }
 276
 277 /**
 278  * Free RX queue elements for Multi-Packet RQ.
 279  *
 280  * @param rxq_ctrl
 281  *   Pointer to RX queue structure.
 282  */
 283 static void
 284 rxq_free_elts_mprq(struct mlx5_rxq_ctrl *rxq_ctrl)
 285 {
 286         struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
 287         uint16_t i;
 288
 289         DRV_LOG(DEBUG, "port %u Multi-Packet Rx queue %u freeing WRs",
 290                 rxq->port_id, rxq->idx);
 291         if (rxq->mprq_bufs == NULL)
 292                 return;
 293         assert(mlx5_rxq_check_vec_support(rxq) < 0);
 294         for (i = 0; (i != (1u << rxq->elts_n)); ++i) {
 295                 if ((*rxq->mprq_bufs)[i] != NULL)
 296                         mlx5_mprq_buf_free((*rxq->mprq_bufs)[i]);
 297                 (*rxq->mprq_bufs)[i] = NULL;
 298         }
 299         if (rxq->mprq_repl != NULL) {
 300                 mlx5_mprq_buf_free(rxq->mprq_repl);
 301                 rxq->mprq_repl = NULL;
 302         }
 303 }
 304
 305 /**
 306  * Free RX queue elements for Single-Packet RQ.
 307  *
 308  * @param rxq_ctrl
 309  *   Pointer to RX queue structure.
 310  */
 311 static void
 312 rxq_free_elts_sprq(struct mlx5_rxq_ctrl *rxq_ctrl)
 313 {
 314         struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
 315         const uint16_t q_n = (1 << rxq->elts_n);
 316         const uint16_t q_mask = q_n - 1;
 317         uint16_t used = q_n - (rxq->rq_ci - rxq->rq_pi);
 318         uint16_t i;
 319
 320         DRV_LOG(DEBUG, "port %u Rx queue %u freeing WRs",
 321                 PORT_ID(rxq_ctrl->priv), rxq->idx);
 322         if (rxq->elts == NULL)
 323                 return;
 324         /**
 325          * Some mbuf in the Ring belongs to the application.  They cannot be
 326          * freed.
 327          */
 328         if (mlx5_rxq_check_vec_support(rxq) > 0) {
 329                 for (i = 0; i < used; ++i)
 330                         (*rxq->elts)[(rxq->rq_ci + i) & q_mask] = NULL;
 331                 rxq->rq_pi = rxq->rq_ci;
 332         }
 333         for (i = 0; (i != (1u << rxq->elts_n)); ++i) {
 334                 if ((*rxq->elts)[i] != NULL)
 335                         rte_pktmbuf_free_seg((*rxq->elts)[i]);
 336                 (*rxq->elts)[i] = NULL;
 337         }
 338 }
 339
 340 /**
 341  * Free RX queue elements.
 342  *
 343  * @param rxq_ctrl
 344  *   Pointer to RX queue structure.
 345  */
 346 static void
 347 rxq_free_elts(struct mlx5_rxq_ctrl *rxq_ctrl)
 348 {
 349         if (mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq))
 350                 rxq_free_elts_mprq(rxq_ctrl);
 351         else
 352                 rxq_free_elts_sprq(rxq_ctrl);
 353 }
 354
 355 /**
 356  * Returns the per-queue supported offloads.
 357  *
 358  * @param dev
 359  *   Pointer to Ethernet device.
 360  *
 361  * @return
 362  *   Supported Rx offloads.
 363  */
 364 uint64_t
 365 mlx5_get_rx_queue_offloads(struct rte_eth_dev *dev)
 366 {
 367         struct mlx5_priv *priv = dev->data->dev_private;
 368         struct mlx5_dev_config *config = &priv->config;
 369         uint64_t offloads = (DEV_RX_OFFLOAD_SCATTER |
 370                              DEV_RX_OFFLOAD_TIMESTAMP |
 371                              DEV_RX_OFFLOAD_JUMBO_FRAME);
 372
 373         if (config->hw_fcs_strip)
 374                 offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
 375
 376         if (config->hw_csum)
 377                 offloads |= (DEV_RX_OFFLOAD_IPV4_CKSUM |
 378                              DEV_RX_OFFLOAD_UDP_CKSUM |
 379                              DEV_RX_OFFLOAD_TCP_CKSUM);
 380         if (config->hw_vlan_strip)
 381                 offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
 382         return offloads;
 383 }
 384
 385
 386 /**
 387  * Returns the per-port supported offloads.
 388  *
 389  * @return
 390  *   Supported Rx offloads.
 391  */
 392 uint64_t
 393 mlx5_get_rx_port_offloads(void)
 394 {
 395         uint64_t offloads = DEV_RX_OFFLOAD_VLAN_FILTER;
 396
 397         return offloads;
 398 }
 399
 400 /**
 401  * Verify if the queue can be released.
 402  *
 403  * @param dev
 404  *   Pointer to Ethernet device.
 405  * @param idx
 406  *   RX queue index.
 407  *
 408  * @return
 409  *   1 if the queue can be released
 410  *   0 if the queue can not be released, there are references to it.
 411  *   Negative errno and rte_errno is set if queue doesn't exist.
 412  */
 413 static int
 414 mlx5_rxq_releasable(struct rte_eth_dev *dev, uint16_t idx)
 415 {
 416         struct mlx5_priv *priv = dev->data->dev_private;
 417         struct mlx5_rxq_ctrl *rxq_ctrl;
 418
 419         if (!(*priv->rxqs)[idx]) {
 420                 rte_errno = EINVAL;
 421                 return -rte_errno;
 422         }
 423         rxq_ctrl = container_of((*priv->rxqs)[idx], struct mlx5_rxq_ctrl, rxq);
 424         return (rte_atomic32_read(&rxq_ctrl->refcnt) == 1);
 425 }
 426
 427 /**
 428  *
 429  * @param dev
 430  *   Pointer to Ethernet device structure.
 431  * @param idx
 432  *   RX queue index.
 433  * @param desc
 434  *   Number of descriptors to configure in queue.
 435  * @param socket
 436  *   NUMA socket on which memory must be allocated.
 437  * @param[in] conf
 438  *   Thresholds parameters.
 439  * @param mp
 440  *   Memory pool for buffer allocations.
 441  *
 442  * @return
 443  *   0 on success, a negative errno value otherwise and rte_errno is set.
 444  */
 445 int
 446 mlx5_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
 447                     unsigned int socket, const struct rte_eth_rxconf *conf,
 448                     struct rte_mempool *mp)
 449 {
 450         struct mlx5_priv *priv = dev->data->dev_private;
 451         struct mlx5_rxq_data *rxq = (*priv->rxqs)[idx];
 452         struct mlx5_rxq_ctrl *rxq_ctrl =
 453                 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
 454
 455         if (!rte_is_power_of_2(desc)) {
 456                 desc = 1 << log2above(desc);
 457                 DRV_LOG(WARNING,
 458                         "port %u increased number of descriptors in Rx queue %u"
 459                         " to the next power of two (%d)",
 460                         dev->data->port_id, idx, desc);
 461         }
 462         DRV_LOG(DEBUG, "port %u configuring Rx queue %u for %u descriptors",
 463                 dev->data->port_id, idx, desc);
 464         if (idx >= priv->rxqs_n) {
 465                 DRV_LOG(ERR, "port %u Rx queue index out of range (%u >= %u)",
 466                         dev->data->port_id, idx, priv->rxqs_n);
 467                 rte_errno = EOVERFLOW;
 468                 return -rte_errno;
 469         }
 470         if (!mlx5_rxq_releasable(dev, idx)) {
 471                 DRV_LOG(ERR, "port %u unable to release queue index %u",
 472                         dev->data->port_id, idx);
 473                 rte_errno = EBUSY;
 474                 return -rte_errno;
 475         }
 476         mlx5_rxq_release(dev, idx);
 477         rxq_ctrl = mlx5_rxq_new(dev, idx, desc, socket, conf, mp);
 478         if (!rxq_ctrl) {
 479                 DRV_LOG(ERR, "port %u unable to allocate queue index %u",
 480                         dev->data->port_id, idx);
 481                 rte_errno = ENOMEM;
 482                 return -rte_errno;
 483         }
 484         DRV_LOG(DEBUG, "port %u adding Rx queue %u to list",
 485                 dev->data->port_id, idx);
 486         (*priv->rxqs)[idx] = &rxq_ctrl->rxq;
 487         return 0;
 488 }
 489
 490 /**
 491  * DPDK callback to release a RX queue.
 492  *
 493  * @param dpdk_rxq
 494  *   Generic RX queue pointer.
 495  */
 496 void
 497 mlx5_rx_queue_release(void *dpdk_rxq)
 498 {
 499         struct mlx5_rxq_data *rxq = (struct mlx5_rxq_data *)dpdk_rxq;
 500         struct mlx5_rxq_ctrl *rxq_ctrl;
 501         struct mlx5_priv *priv;
 502
 503         if (rxq == NULL)
 504                 return;
 505         rxq_ctrl = container_of(rxq, struct mlx5_rxq_ctrl, rxq);
 506         priv = rxq_ctrl->priv;
 507         if (!mlx5_rxq_releasable(ETH_DEV(priv), rxq_ctrl->rxq.idx))
 508                 rte_panic("port %u Rx queue %u is still used by a flow and"
 509                           " cannot be removed\n",
 510                           PORT_ID(priv), rxq->idx);
 511         mlx5_rxq_release(ETH_DEV(priv), rxq_ctrl->rxq.idx);
 512 }
 513
 514 /**
 515  * Get an Rx queue Verbs object.
 516  *
 517  * @param dev
 518  *   Pointer to Ethernet device.
 519  * @param idx
 520  *   Queue index in DPDK Rx queue array
 521  *
 522  * @return
 523  *   The Verbs object if it exists.
 524  */
 525 static struct mlx5_rxq_ibv *
 526 mlx5_rxq_ibv_get(struct rte_eth_dev *dev, uint16_t idx)
 527 {
 528         struct mlx5_priv *priv = dev->data->dev_private;
 529         struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
 530         struct mlx5_rxq_ctrl *rxq_ctrl;
 531
 532         if (idx >= priv->rxqs_n)
 533                 return NULL;
 534         if (!rxq_data)
 535                 return NULL;
 536         rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
 537         if (rxq_ctrl->ibv)
 538                 rte_atomic32_inc(&rxq_ctrl->ibv->refcnt);
 539         return rxq_ctrl->ibv;
 540 }
 541
 542 /**
 543  * Release an Rx verbs queue object.
 544  *
 545  * @param rxq_ibv
 546  *   Verbs Rx queue object.
 547  *
 548  * @return
 549  *   1 while a reference on it exists, 0 when freed.
 550  */
 551 static int
 552 mlx5_rxq_ibv_release(struct mlx5_rxq_ibv *rxq_ibv)
 553 {
 554         assert(rxq_ibv);
 555         assert(rxq_ibv->wq);
 556         assert(rxq_ibv->cq);
 557         if (rte_atomic32_dec_and_test(&rxq_ibv->refcnt)) {
 558                 rxq_free_elts(rxq_ibv->rxq_ctrl);
 559                 claim_zero(mlx5_glue->destroy_wq(rxq_ibv->wq));
 560                 claim_zero(mlx5_glue->destroy_cq(rxq_ibv->cq));
 561                 if (rxq_ibv->channel)
 562                         claim_zero(mlx5_glue->destroy_comp_channel
 563                                    (rxq_ibv->channel));
 564                 LIST_REMOVE(rxq_ibv, next);
 565                 rte_free(rxq_ibv);
 566                 return 0;
 567         }
 568         return 1;
 569 }
 570
 571 /**
 572  * Allocate queue vector and fill epoll fd list for Rx interrupts.
 573  *
 574  * @param dev
 575  *   Pointer to Ethernet device.
 576  *
 577  * @return
 578  *   0 on success, a negative errno value otherwise and rte_errno is set.
 579  */
 580 int
 581 mlx5_rx_intr_vec_enable(struct rte_eth_dev *dev)
 582 {
 583         struct mlx5_priv *priv = dev->data->dev_private;
 584         unsigned int i;
 585         unsigned int rxqs_n = priv->rxqs_n;
 586         unsigned int n = RTE_MIN(rxqs_n, (uint32_t)RTE_MAX_RXTX_INTR_VEC_ID);
 587         unsigned int count = 0;
 588         struct rte_intr_handle *intr_handle = dev->intr_handle;
 589
 590         if (!dev->data->dev_conf.intr_conf.rxq)
 591                 return 0;
 592         mlx5_rx_intr_vec_disable(dev);
 593         intr_handle->intr_vec = malloc(n * sizeof(intr_handle->intr_vec[0]));
 594         if (intr_handle->intr_vec == NULL) {
 595                 DRV_LOG(ERR,
 596                         "port %u failed to allocate memory for interrupt"
 597                         " vector, Rx interrupts will not be supported",
 598                         dev->data->port_id);
 599                 rte_errno = ENOMEM;
 600                 return -rte_errno;
 601         }
 602         intr_handle->type = RTE_INTR_HANDLE_EXT;
 603         for (i = 0; i != n; ++i) {
 604                 /* This rxq ibv must not be released in this function. */
 605                 struct mlx5_rxq_ibv *rxq_ibv = mlx5_rxq_ibv_get(dev, i);
 606                 int fd;
 607                 int flags;
 608                 int rc;
 609
 610                 /* Skip queues that cannot request interrupts. */
 611                 if (!rxq_ibv || !rxq_ibv->channel) {
 612                         /* Use invalid intr_vec[] index to disable entry. */
 613                         intr_handle->intr_vec[i] =
 614                                 RTE_INTR_VEC_RXTX_OFFSET +
 615                                 RTE_MAX_RXTX_INTR_VEC_ID;
 616                         continue;
 617                 }
 618                 if (count >= RTE_MAX_RXTX_INTR_VEC_ID) {
 619                         DRV_LOG(ERR,
 620                                 "port %u too many Rx queues for interrupt"
 621                                 " vector size (%d), Rx interrupts cannot be"
 622                                 " enabled",
 623                                 dev->data->port_id, RTE_MAX_RXTX_INTR_VEC_ID);
 624                         mlx5_rx_intr_vec_disable(dev);
 625                         rte_errno = ENOMEM;
 626                         return -rte_errno;
 627                 }
 628                 fd = rxq_ibv->channel->fd;
 629                 flags = fcntl(fd, F_GETFL);
 630                 rc = fcntl(fd, F_SETFL, flags | O_NONBLOCK);
 631                 if (rc < 0) {
 632                         rte_errno = errno;
 633                         DRV_LOG(ERR,
 634                                 "port %u failed to make Rx interrupt file"
 635                                 " descriptor %d non-blocking for queue index"
 636                                 " %d",
 637                                 dev->data->port_id, fd, i);
 638                         mlx5_rx_intr_vec_disable(dev);
 639                         return -rte_errno;
 640                 }
 641                 intr_handle->intr_vec[i] = RTE_INTR_VEC_RXTX_OFFSET + count;
 642                 intr_handle->efds[count] = fd;
 643                 count++;
 644         }
 645         if (!count)
 646                 mlx5_rx_intr_vec_disable(dev);
 647         else
 648                 intr_handle->nb_efd = count;
 649         return 0;
 650 }
 651
 652 /**
 653  * Clean up Rx interrupts handler.
 654  *
 655  * @param dev
 656  *   Pointer to Ethernet device.
 657  */
 658 void
 659 mlx5_rx_intr_vec_disable(struct rte_eth_dev *dev)
 660 {
 661         struct mlx5_priv *priv = dev->data->dev_private;
 662         struct rte_intr_handle *intr_handle = dev->intr_handle;
 663         unsigned int i;
 664         unsigned int rxqs_n = priv->rxqs_n;
 665         unsigned int n = RTE_MIN(rxqs_n, (uint32_t)RTE_MAX_RXTX_INTR_VEC_ID);
 666
 667         if (!dev->data->dev_conf.intr_conf.rxq)
 668                 return;
 669         if (!intr_handle->intr_vec)
 670                 goto free;
 671         for (i = 0; i != n; ++i) {
 672                 struct mlx5_rxq_ctrl *rxq_ctrl;
 673                 struct mlx5_rxq_data *rxq_data;
 674
 675                 if (intr_handle->intr_vec[i] == RTE_INTR_VEC_RXTX_OFFSET +
 676                     RTE_MAX_RXTX_INTR_VEC_ID)
 677                         continue;
 678                 /**
 679                  * Need to access directly the queue to release the reference
 680                  * kept in mlx5_rx_intr_vec_enable().
 681                  */
 682                 rxq_data = (*priv->rxqs)[i];
 683                 rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
 684                 if (rxq_ctrl->ibv)
 685                         mlx5_rxq_ibv_release(rxq_ctrl->ibv);
 686         }
 687 free:
 688         rte_intr_free_epoll_fd(intr_handle);
 689         if (intr_handle->intr_vec)
 690                 free(intr_handle->intr_vec);
 691         intr_handle->nb_efd = 0;
 692         intr_handle->intr_vec = NULL;
 693 }
 694
 695 /**
 696  *  MLX5 CQ notification .
 697  *
 698  *  @param rxq
 699  *     Pointer to receive queue structure.
 700  *  @param sq_n_rxq
 701  *     Sequence number per receive queue .
 702  */
 703 static inline void
 704 mlx5_arm_cq(struct mlx5_rxq_data *rxq, int sq_n_rxq)
 705 {
 706         int sq_n = 0;
 707         uint32_t doorbell_hi;
 708         uint64_t doorbell;
 709         void *cq_db_reg = (char *)rxq->cq_uar + MLX5_CQ_DOORBELL;
 710
 711         sq_n = sq_n_rxq & MLX5_CQ_SQN_MASK;
 712         doorbell_hi = sq_n << MLX5_CQ_SQN_OFFSET | (rxq->cq_ci & MLX5_CI_MASK);
 713         doorbell = (uint64_t)doorbell_hi << 32;
 714         doorbell |=  rxq->cqn;
 715         rxq->cq_db[MLX5_CQ_ARM_DB] = rte_cpu_to_be_32(doorbell_hi);
 716         mlx5_uar_write64(rte_cpu_to_be_64(doorbell),
 717                          cq_db_reg, rxq->uar_lock_cq);
 718 }
 719
 720 /**
 721  * DPDK callback for Rx queue interrupt enable.
 722  *
 723  * @param dev
 724  *   Pointer to Ethernet device structure.
 725  * @param rx_queue_id
 726  *   Rx queue number.
 727  *
 728  * @return
 729  *   0 on success, a negative errno value otherwise and rte_errno is set.
 730  */
 731 int
 732 mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 733 {
 734         struct mlx5_priv *priv = dev->data->dev_private;
 735         struct mlx5_rxq_data *rxq_data;
 736         struct mlx5_rxq_ctrl *rxq_ctrl;
 737
 738         rxq_data = (*priv->rxqs)[rx_queue_id];
 739         if (!rxq_data) {
 740                 rte_errno = EINVAL;
 741                 return -rte_errno;
 742         }
 743         rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
 744         if (rxq_ctrl->irq) {
 745                 struct mlx5_rxq_ibv *rxq_ibv;
 746
 747                 rxq_ibv = mlx5_rxq_ibv_get(dev, rx_queue_id);
 748                 if (!rxq_ibv) {
 749                         rte_errno = EINVAL;
 750                         return -rte_errno;
 751                 }
 752                 mlx5_arm_cq(rxq_data, rxq_data->cq_arm_sn);
 753                 mlx5_rxq_ibv_release(rxq_ibv);
 754         }
 755         return 0;
 756 }
 757
 758 /**
 759  * DPDK callback for Rx queue interrupt disable.
 760  *
 761  * @param dev
 762  *   Pointer to Ethernet device structure.
 763  * @param rx_queue_id
 764  *   Rx queue number.
 765  *
 766  * @return
 767  *   0 on success, a negative errno value otherwise and rte_errno is set.
 768  */
 769 int
 770 mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 771 {
 772         struct mlx5_priv *priv = dev->data->dev_private;
 773         struct mlx5_rxq_data *rxq_data;
 774         struct mlx5_rxq_ctrl *rxq_ctrl;
 775         struct mlx5_rxq_ibv *rxq_ibv = NULL;
 776         struct ibv_cq *ev_cq;
 777         void *ev_ctx;
 778         int ret;
 779
 780         rxq_data = (*priv->rxqs)[rx_queue_id];
 781         if (!rxq_data) {
 782                 rte_errno = EINVAL;
 783                 return -rte_errno;
 784         }
 785         rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
 786         if (!rxq_ctrl->irq)
 787                 return 0;
 788         rxq_ibv = mlx5_rxq_ibv_get(dev, rx_queue_id);
 789         if (!rxq_ibv) {
 790                 rte_errno = EINVAL;
 791                 return -rte_errno;
 792         }
 793         ret = mlx5_glue->get_cq_event(rxq_ibv->channel, &ev_cq, &ev_ctx);
 794         if (ret || ev_cq != rxq_ibv->cq) {
 795                 rte_errno = EINVAL;
 796                 goto exit;
 797         }
 798         rxq_data->cq_arm_sn++;
 799         mlx5_glue->ack_cq_events(rxq_ibv->cq, 1);
 800         mlx5_rxq_ibv_release(rxq_ibv);
 801         return 0;
 802 exit:
 803         ret = rte_errno; /* Save rte_errno before cleanup. */
 804         if (rxq_ibv)
 805                 mlx5_rxq_ibv_release(rxq_ibv);
 806         DRV_LOG(WARNING, "port %u unable to disable interrupt on Rx queue %d",
 807                 dev->data->port_id, rx_queue_id);
 808         rte_errno = ret; /* Restore rte_errno. */
 809         return -rte_errno;
 810 }
 811
 812 /**
 813  * Create the Rx queue Verbs object.
 814  *
 815  * @param dev
 816  *   Pointer to Ethernet device.
 817  * @param idx
 818  *   Queue index in DPDK Rx queue array
 819  *
 820  * @return
 821  *   The Verbs object initialised, NULL otherwise and rte_errno is set.
 822  */
 823 struct mlx5_rxq_ibv *
 824 mlx5_rxq_ibv_new(struct rte_eth_dev *dev, uint16_t idx)
 825 {
 826         struct mlx5_priv *priv = dev->data->dev_private;
 827         struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
 828         struct mlx5_rxq_ctrl *rxq_ctrl =
 829                 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
 830         struct ibv_wq_attr mod;
 831         union {
 832                 struct {
 833                         struct ibv_cq_init_attr_ex ibv;
 834                         struct mlx5dv_cq_init_attr mlx5;
 835                 } cq;
 836                 struct {
 837                         struct ibv_wq_init_attr ibv;
 838 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
 839                         struct mlx5dv_wq_init_attr mlx5;
 840 #endif
 841                 } wq;
 842                 struct ibv_cq_ex cq_attr;
 843         } attr;
 844         unsigned int cqe_n;
 845         unsigned int wqe_n = 1 << rxq_data->elts_n;
 846         struct mlx5_rxq_ibv *tmpl = NULL;
 847         struct mlx5dv_cq cq_info;
 848         struct mlx5dv_rwq rwq;
 849         int ret = 0;
 850         struct mlx5dv_obj obj;
 851         struct mlx5_dev_config *config = &priv->config;
 852         const int mprq_en = mlx5_rxq_mprq_enabled(rxq_data);
 853
 854         assert(rxq_data);
 855         assert(!rxq_ctrl->ibv);
 856         priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_RX_QUEUE;
 857         priv->verbs_alloc_ctx.obj = rxq_ctrl;
 858         tmpl = rte_calloc_socket(__func__, 1, sizeof(*tmpl), 0,
 859                                  rxq_ctrl->socket);
 860         if (!tmpl) {
 861                 DRV_LOG(ERR,
 862                         "port %u Rx queue %u cannot allocate verbs resources",
 863                         dev->data->port_id, rxq_data->idx);
 864                 rte_errno = ENOMEM;
 865                 goto error;
 866         }
 867         tmpl->rxq_ctrl = rxq_ctrl;
 868         if (rxq_ctrl->irq) {
 869                 tmpl->channel = mlx5_glue->create_comp_channel(priv->sh->ctx);
 870                 if (!tmpl->channel) {
 871                         DRV_LOG(ERR, "port %u: comp channel creation failure",
 872                                 dev->data->port_id);
 873                         rte_errno = ENOMEM;
 874                         goto error;
 875                 }
 876         }
 877         if (mprq_en)
 878                 cqe_n = wqe_n * (1 << rxq_data->strd_num_n) - 1;
 879         else
 880                 cqe_n = wqe_n  - 1;
 881         attr.cq.ibv = (struct ibv_cq_init_attr_ex){
 882                 .cqe = cqe_n,
 883                 .channel = tmpl->channel,
 884                 .comp_mask = 0,
 885         };
 886         attr.cq.mlx5 = (struct mlx5dv_cq_init_attr){
 887                 .comp_mask = 0,
 888         };
 889         if (config->cqe_comp && !rxq_data->hw_timestamp) {
 890                 attr.cq.mlx5.comp_mask |=
 891                         MLX5DV_CQ_INIT_ATTR_MASK_COMPRESSED_CQE;
 892 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
 893                 attr.cq.mlx5.cqe_comp_res_format =
 894                         mprq_en ? MLX5DV_CQE_RES_FORMAT_CSUM_STRIDX :
 895                                   MLX5DV_CQE_RES_FORMAT_HASH;
 896 #else
 897                 attr.cq.mlx5.cqe_comp_res_format = MLX5DV_CQE_RES_FORMAT_HASH;
 898 #endif
 899                 /*
 900                  * For vectorized Rx, it must not be doubled in order to
 901                  * make cq_ci and rq_ci aligned.
 902                  */
 903                 if (mlx5_rxq_check_vec_support(rxq_data) < 0)
 904                         attr.cq.ibv.cqe *= 2;
 905         } else if (config->cqe_comp && rxq_data->hw_timestamp) {
 906                 DRV_LOG(DEBUG,
 907                         "port %u Rx CQE compression is disabled for HW"
 908                         " timestamp",
 909                         dev->data->port_id);
 910         }
 911 #ifdef HAVE_IBV_MLX5_MOD_CQE_128B_PAD
 912         if (config->cqe_pad) {
 913                 attr.cq.mlx5.comp_mask |= MLX5DV_CQ_INIT_ATTR_MASK_FLAGS;
 914                 attr.cq.mlx5.flags |= MLX5DV_CQ_INIT_ATTR_FLAGS_CQE_PAD;
 915         }
 916 #endif
 917         tmpl->cq = mlx5_glue->cq_ex_to_cq
 918                 (mlx5_glue->dv_create_cq(priv->sh->ctx, &attr.cq.ibv,
 919                                          &attr.cq.mlx5));
 920         if (tmpl->cq == NULL) {
 921                 DRV_LOG(ERR, "port %u Rx queue %u CQ creation failure",
 922                         dev->data->port_id, idx);
 923                 rte_errno = ENOMEM;
 924                 goto error;
 925         }
 926         DRV_LOG(DEBUG, "port %u device_attr.max_qp_wr is %d",
 927                 dev->data->port_id, priv->sh->device_attr.orig_attr.max_qp_wr);
 928         DRV_LOG(DEBUG, "port %u device_attr.max_sge is %d",
 929                 dev->data->port_id, priv->sh->device_attr.orig_attr.max_sge);
 930         attr.wq.ibv = (struct ibv_wq_init_attr){
 931                 .wq_context = NULL, /* Could be useful in the future. */
 932                 .wq_type = IBV_WQT_RQ,
 933                 /* Max number of outstanding WRs. */
 934                 .max_wr = wqe_n >> rxq_data->sges_n,
 935                 /* Max number of scatter/gather elements in a WR. */
 936                 .max_sge = 1 << rxq_data->sges_n,
 937                 .pd = priv->sh->pd,
 938                 .cq = tmpl->cq,
 939                 .comp_mask =
 940                         IBV_WQ_FLAGS_CVLAN_STRIPPING |
 941                         0,
 942                 .create_flags = (rxq_data->vlan_strip ?
 943                                  IBV_WQ_FLAGS_CVLAN_STRIPPING :
 944                                  0),
 945         };
 946         /* By default, FCS (CRC) is stripped by hardware. */
 947         if (rxq_data->crc_present) {
 948                 attr.wq.ibv.create_flags |= IBV_WQ_FLAGS_SCATTER_FCS;
 949                 attr.wq.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
 950         }
 951         if (config->hw_padding) {
 952 #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING)
 953                 attr.wq.ibv.create_flags |= IBV_WQ_FLAG_RX_END_PADDING;
 954                 attr.wq.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
 955 #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING)
 956                 attr.wq.ibv.create_flags |= IBV_WQ_FLAGS_PCI_WRITE_END_PADDING;
 957                 attr.wq.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
 958 #endif
 959         }
 960 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
 961         attr.wq.mlx5 = (struct mlx5dv_wq_init_attr){
 962                 .comp_mask = 0,
 963         };
 964         if (mprq_en) {
 965                 struct mlx5dv_striding_rq_init_attr *mprq_attr =
 966                         &attr.wq.mlx5.striding_rq_attrs;
 967
 968                 attr.wq.mlx5.comp_mask |= MLX5DV_WQ_INIT_ATTR_MASK_STRIDING_RQ;
 969                 *mprq_attr = (struct mlx5dv_striding_rq_init_attr){
 970                         .single_stride_log_num_of_bytes = rxq_data->strd_sz_n,
 971                         .single_wqe_log_num_of_strides = rxq_data->strd_num_n,
 972                         .two_byte_shift_en = MLX5_MPRQ_TWO_BYTE_SHIFT,
 973                 };
 974         }
 975         tmpl->wq = mlx5_glue->dv_create_wq(priv->sh->ctx, &attr.wq.ibv,
 976                                            &attr.wq.mlx5);
 977 #else
 978         tmpl->wq = mlx5_glue->create_wq(priv->sh->ctx, &attr.wq.ibv);
 979 #endif
 980         if (tmpl->wq == NULL) {
 981                 DRV_LOG(ERR, "port %u Rx queue %u WQ creation failure",
 982                         dev->data->port_id, idx);
 983                 rte_errno = ENOMEM;
 984                 goto error;
 985         }
 986         /*
 987          * Make sure number of WRs*SGEs match expectations since a queue
 988          * cannot allocate more than "desc" buffers.
 989          */
 990         if (attr.wq.ibv.max_wr != (wqe_n >> rxq_data->sges_n) ||
 991             attr.wq.ibv.max_sge != (1u << rxq_data->sges_n)) {
 992                 DRV_LOG(ERR,
 993                         "port %u Rx queue %u requested %u*%u but got %u*%u"
 994                         " WRs*SGEs",
 995                         dev->data->port_id, idx,
 996                         wqe_n >> rxq_data->sges_n, (1 << rxq_data->sges_n),
 997                         attr.wq.ibv.max_wr, attr.wq.ibv.max_sge);
 998                 rte_errno = EINVAL;
 999                 goto error;
1000         }
1001         /* Change queue state to ready. */
1002         mod = (struct ibv_wq_attr){
1003                 .attr_mask = IBV_WQ_ATTR_STATE,
1004                 .wq_state = IBV_WQS_RDY,
1005         };
1006         ret = mlx5_glue->modify_wq(tmpl->wq, &mod);
1007         if (ret) {
1008                 DRV_LOG(ERR,
1009                         "port %u Rx queue %u WQ state to IBV_WQS_RDY failed",
1010                         dev->data->port_id, idx);
1011                 rte_errno = ret;
1012                 goto error;
1013         }
1014         obj.cq.in = tmpl->cq;
1015         obj.cq.out = &cq_info;
1016         obj.rwq.in = tmpl->wq;
1017         obj.rwq.out = &rwq;
1018         ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_CQ | MLX5DV_OBJ_RWQ);
1019         if (ret) {
1020                 rte_errno = ret;
1021                 goto error;
1022         }
1023         if (cq_info.cqe_size != RTE_CACHE_LINE_SIZE) {
1024                 DRV_LOG(ERR,
1025                         "port %u wrong MLX5_CQE_SIZE environment variable"
1026                         " value: it should be set to %u",
1027                         dev->data->port_id, RTE_CACHE_LINE_SIZE);
1028                 rte_errno = EINVAL;
1029                 goto error;
1030         }
1031         /* Fill the rings. */
1032         rxq_data->wqes = rwq.buf;
1033         rxq_data->rq_db = rwq.dbrec;
1034         rxq_data->cqe_n = log2above(cq_info.cqe_cnt);
1035         rxq_data->cq_db = cq_info.dbrec;
1036         rxq_data->cqes = (volatile struct mlx5_cqe (*)[])(uintptr_t)cq_info.buf;
1037         rxq_data->cq_uar = cq_info.cq_uar;
1038         rxq_data->cqn = cq_info.cqn;
1039         rxq_data->cq_arm_sn = 0;
1040         mlx5_rxq_initialize(rxq_data);
1041         rxq_data->cq_ci = 0;
1042         DRV_LOG(DEBUG, "port %u rxq %u updated with %p", dev->data->port_id,
1043                 idx, (void *)&tmpl);
1044         rte_atomic32_inc(&tmpl->refcnt);
1045         LIST_INSERT_HEAD(&priv->rxqsibv, tmpl, next);
1046         priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
1047         return tmpl;
1048 error:
1049         if (tmpl) {
1050                 ret = rte_errno; /* Save rte_errno before cleanup. */
1051                 if (tmpl->wq)
1052                         claim_zero(mlx5_glue->destroy_wq(tmpl->wq));
1053                 if (tmpl->cq)
1054                         claim_zero(mlx5_glue->destroy_cq(tmpl->cq));
1055                 if (tmpl->channel)
1056                         claim_zero(mlx5_glue->destroy_comp_channel
1057                                                         (tmpl->channel));
1058                 rte_free(tmpl);
1059                 rte_errno = ret; /* Restore rte_errno. */
1060         }
1061         priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
1062         return NULL;
1063 }
1064
1065 /**
1066  * Verify the Verbs Rx queue list is empty
1067  *
1068  * @param dev
1069  *   Pointer to Ethernet device.
1070  *
1071  * @return
1072  *   The number of object not released.
1073  */
1074 int
1075 mlx5_rxq_ibv_verify(struct rte_eth_dev *dev)
1076 {
1077         struct mlx5_priv *priv = dev->data->dev_private;
1078         int ret = 0;
1079         struct mlx5_rxq_ibv *rxq_ibv;
1080
1081         LIST_FOREACH(rxq_ibv, &priv->rxqsibv, next) {
1082                 DRV_LOG(DEBUG, "port %u Verbs Rx queue %u still referenced",
1083                         dev->data->port_id, rxq_ibv->rxq_ctrl->rxq.idx);
1084                 ++ret;
1085         }
1086         return ret;
1087 }
1088
1089 /**
1090  * Callback function to initialize mbufs for Multi-Packet RQ.
1091  */
1092 static inline void
1093 mlx5_mprq_buf_init(struct rte_mempool *mp, void *opaque_arg __rte_unused,
1094                     void *_m, unsigned int i __rte_unused)
1095 {
1096         struct mlx5_mprq_buf *buf = _m;
1097
1098         memset(_m, 0, sizeof(*buf));
1099         buf->mp = mp;
1100         rte_atomic16_set(&buf->refcnt, 1);
1101 }
1102
1103 /**
1104  * Free mempool of Multi-Packet RQ.
1105  *
1106  * @param dev
1107  *   Pointer to Ethernet device.
1108  *
1109  * @return
1110  *   0 on success, negative errno value on failure.
1111  */
1112 int
1113 mlx5_mprq_free_mp(struct rte_eth_dev *dev)
1114 {
1115         struct mlx5_priv *priv = dev->data->dev_private;
1116         struct rte_mempool *mp = priv->mprq_mp;
1117         unsigned int i;
1118
1119         if (mp == NULL)
1120                 return 0;
1121         DRV_LOG(DEBUG, "port %u freeing mempool (%s) for Multi-Packet RQ",
1122                 dev->data->port_id, mp->name);
1123         /*
1124          * If a buffer in the pool has been externally attached to a mbuf and it
1125          * is still in use by application, destroying the Rx qeueue can spoil
1126          * the packet. It is unlikely to happen but if application dynamically
1127          * creates and destroys with holding Rx packets, this can happen.
1128          *
1129          * TODO: It is unavoidable for now because the mempool for Multi-Packet
1130          * RQ isn't provided by application but managed by PMD.
1131          */
1132         if (!rte_mempool_full(mp)) {
1133                 DRV_LOG(ERR,
1134                         "port %u mempool for Multi-Packet RQ is still in use",
1135                         dev->data->port_id);
1136                 rte_errno = EBUSY;
1137                 return -rte_errno;
1138         }
1139         rte_mempool_free(mp);
1140         /* Unset mempool for each Rx queue. */
1141         for (i = 0; i != priv->rxqs_n; ++i) {
1142                 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
1143
1144                 if (rxq == NULL)
1145                         continue;
1146                 rxq->mprq_mp = NULL;
1147         }
1148         priv->mprq_mp = NULL;
1149         return 0;
1150 }
1151
1152 /**
1153  * Allocate a mempool for Multi-Packet RQ. All configured Rx queues share the
1154  * mempool. If already allocated, reuse it if there're enough elements.
1155  * Otherwise, resize it.
1156  *
1157  * @param dev
1158  *   Pointer to Ethernet device.
1159  *
1160  * @return
1161  *   0 on success, negative errno value on failure.
1162  */
1163 int
1164 mlx5_mprq_alloc_mp(struct rte_eth_dev *dev)
1165 {
1166         struct mlx5_priv *priv = dev->data->dev_private;
1167         struct rte_mempool *mp = priv->mprq_mp;
1168         char name[RTE_MEMPOOL_NAMESIZE];
1169         unsigned int desc = 0;
1170         unsigned int buf_len;
1171         unsigned int obj_num;
1172         unsigned int obj_size;
1173         unsigned int strd_num_n = 0;
1174         unsigned int strd_sz_n = 0;
1175         unsigned int i;
1176
1177         if (!mlx5_mprq_enabled(dev))
1178                 return 0;
1179         /* Count the total number of descriptors configured. */
1180         for (i = 0; i != priv->rxqs_n; ++i) {
1181                 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
1182
1183                 if (rxq == NULL)
1184                         continue;
1185                 desc += 1 << rxq->elts_n;
1186                 /* Get the max number of strides. */
1187                 if (strd_num_n < rxq->strd_num_n)
1188                         strd_num_n = rxq->strd_num_n;
1189                 /* Get the max size of a stride. */
1190                 if (strd_sz_n < rxq->strd_sz_n)
1191                         strd_sz_n = rxq->strd_sz_n;
1192         }
1193         assert(strd_num_n && strd_sz_n);
1194         buf_len = (1 << strd_num_n) * (1 << strd_sz_n);
1195         obj_size = buf_len + sizeof(struct mlx5_mprq_buf);
1196         /*
1197          * Received packets can be either memcpy'd or externally referenced. In
1198          * case that the packet is attached to an mbuf as an external buffer, as
1199          * it isn't possible to predict how the buffers will be queued by
1200          * application, there's no option to exactly pre-allocate needed buffers
1201          * in advance but to speculatively prepares enough buffers.
1202          *
1203          * In the data path, if this Mempool is depleted, PMD will try to memcpy
1204          * received packets to buffers provided by application (rxq->mp) until
1205          * this Mempool gets available again.
1206          */
1207         desc *= 4;
1208         obj_num = desc + MLX5_MPRQ_MP_CACHE_SZ * priv->rxqs_n;
1209         /*
1210          * rte_mempool_create_empty() has sanity check to refuse large cache
1211          * size compared to the number of elements.
1212          * CACHE_FLUSHTHRESH_MULTIPLIER is defined in a C file, so using a
1213          * constant number 2 instead.
1214          */
1215         obj_num = RTE_MAX(obj_num, MLX5_MPRQ_MP_CACHE_SZ * 2);
1216         /* Check a mempool is already allocated and if it can be resued. */
1217         if (mp != NULL && mp->elt_size >= obj_size && mp->size >= obj_num) {
1218                 DRV_LOG(DEBUG, "port %u mempool %s is being reused",
1219                         dev->data->port_id, mp->name);
1220                 /* Reuse. */
1221                 goto exit;
1222         } else if (mp != NULL) {
1223                 DRV_LOG(DEBUG, "port %u mempool %s should be resized, freeing it",
1224                         dev->data->port_id, mp->name);
1225                 /*
1226                  * If failed to free, which means it may be still in use, no way
1227                  * but to keep using the existing one. On buffer underrun,
1228                  * packets will be memcpy'd instead of external buffer
1229                  * attachment.
1230                  */
1231                 if (mlx5_mprq_free_mp(dev)) {
1232                         if (mp->elt_size >= obj_size)
1233                                 goto exit;
1234                         else
1235                                 return -rte_errno;
1236                 }
1237         }
1238         snprintf(name, sizeof(name), "port-%u-mprq", dev->data->port_id);
1239         mp = rte_mempool_create(name, obj_num, obj_size, MLX5_MPRQ_MP_CACHE_SZ,
1240                                 0, NULL, NULL, mlx5_mprq_buf_init, NULL,
1241                                 dev->device->numa_node, 0);
1242         if (mp == NULL) {
1243                 DRV_LOG(ERR,
1244                         "port %u failed to allocate a mempool for"
1245                         " Multi-Packet RQ, count=%u, size=%u",
1246                         dev->data->port_id, obj_num, obj_size);
1247                 rte_errno = ENOMEM;
1248                 return -rte_errno;
1249         }
1250         priv->mprq_mp = mp;
1251 exit:
1252         /* Set mempool for each Rx queue. */
1253         for (i = 0; i != priv->rxqs_n; ++i) {
1254                 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
1255
1256                 if (rxq == NULL)
1257                         continue;
1258                 rxq->mprq_mp = mp;
1259         }
1260         DRV_LOG(INFO, "port %u Multi-Packet RQ is configured",
1261                 dev->data->port_id);
1262         return 0;
1263 }
1264
1265 /**
1266  * Create a DPDK Rx queue.
1267  *
1268  * @param dev
1269  *   Pointer to Ethernet device.
1270  * @param idx
1271  *   RX queue index.
1272  * @param desc
1273  *   Number of descriptors to configure in queue.
1274  * @param socket
1275  *   NUMA socket on which memory must be allocated.
1276  *
1277  * @return
1278  *   A DPDK queue object on success, NULL otherwise and rte_errno is set.
1279  */
1280 struct mlx5_rxq_ctrl *
1281 mlx5_rxq_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1282              unsigned int socket, const struct rte_eth_rxconf *conf,
1283              struct rte_mempool *mp)
1284 {
1285         struct mlx5_priv *priv = dev->data->dev_private;
1286         struct mlx5_rxq_ctrl *tmpl;
1287         unsigned int mb_len = rte_pktmbuf_data_room_size(mp);
1288         unsigned int mprq_stride_size;
1289         struct mlx5_dev_config *config = &priv->config;
1290         /*
1291          * Always allocate extra slots, even if eventually
1292          * the vector Rx will not be used.
1293          */
1294         uint16_t desc_n =
1295                 desc + config->rx_vec_en * MLX5_VPMD_DESCS_PER_LOOP;
1296         uint64_t offloads = conf->offloads |
1297                            dev->data->dev_conf.rxmode.offloads;
1298         const int mprq_en = mlx5_check_mprq_support(dev) > 0;
1299
1300         tmpl = rte_calloc_socket("RXQ", 1,
1301                                  sizeof(*tmpl) +
1302                                  desc_n * sizeof(struct rte_mbuf *),
1303                                  0, socket);
1304         if (!tmpl) {
1305                 rte_errno = ENOMEM;
1306                 return NULL;
1307         }
1308         if (mlx5_mr_btree_init(&tmpl->rxq.mr_ctrl.cache_bh,
1309                                MLX5_MR_BTREE_CACHE_N, socket)) {
1310                 /* rte_errno is already set. */
1311                 goto error;
1312         }
1313         tmpl->socket = socket;
1314         if (dev->data->dev_conf.intr_conf.rxq)
1315                 tmpl->irq = 1;
1316         /*
1317          * This Rx queue can be configured as a Multi-Packet RQ if all of the
1318          * following conditions are met:
1319          *  - MPRQ is enabled.
1320          *  - The number of descs is more than the number of strides.
1321          *  - max_rx_pkt_len plus overhead is less than the max size of a
1322          *    stride.
1323          *  Otherwise, enable Rx scatter if necessary.
1324          */
1325         assert(mb_len >= RTE_PKTMBUF_HEADROOM);
1326         mprq_stride_size =
1327                 dev->data->dev_conf.rxmode.max_rx_pkt_len +
1328                 sizeof(struct rte_mbuf_ext_shared_info) +
1329                 RTE_PKTMBUF_HEADROOM;
1330         if (mprq_en &&
1331             desc > (1U << config->mprq.stride_num_n) &&
1332             mprq_stride_size <= (1U << config->mprq.max_stride_size_n)) {
1333                 /* TODO: Rx scatter isn't supported yet. */
1334                 tmpl->rxq.sges_n = 0;
1335                 /* Trim the number of descs needed. */
1336                 desc >>= config->mprq.stride_num_n;
1337                 tmpl->rxq.strd_num_n = config->mprq.stride_num_n;
1338                 tmpl->rxq.strd_sz_n = RTE_MAX(log2above(mprq_stride_size),
1339                                               config->mprq.min_stride_size_n);
1340                 tmpl->rxq.strd_shift_en = MLX5_MPRQ_TWO_BYTE_SHIFT;
1341                 tmpl->rxq.mprq_max_memcpy_len =
1342                         RTE_MIN(mb_len - RTE_PKTMBUF_HEADROOM,
1343                                 config->mprq.max_memcpy_len);
1344                 DRV_LOG(DEBUG,
1345                         "port %u Rx queue %u: Multi-Packet RQ is enabled"
1346                         " strd_num_n = %u, strd_sz_n = %u",
1347                         dev->data->port_id, idx,
1348                         tmpl->rxq.strd_num_n, tmpl->rxq.strd_sz_n);
1349         } else if (dev->data->dev_conf.rxmode.max_rx_pkt_len <=
1350                    (mb_len - RTE_PKTMBUF_HEADROOM)) {
1351                 tmpl->rxq.sges_n = 0;
1352         } else if (offloads & DEV_RX_OFFLOAD_SCATTER) {
1353                 unsigned int size =
1354                         RTE_PKTMBUF_HEADROOM +
1355                         dev->data->dev_conf.rxmode.max_rx_pkt_len;
1356                 unsigned int sges_n;
1357
1358                 /*
1359                  * Determine the number of SGEs needed for a full packet
1360                  * and round it to the next power of two.
1361                  */
1362                 sges_n = log2above((size / mb_len) + !!(size % mb_len));
1363                 tmpl->rxq.sges_n = sges_n;
1364                 /* Make sure rxq.sges_n did not overflow. */
1365                 size = mb_len * (1 << tmpl->rxq.sges_n);
1366                 size -= RTE_PKTMBUF_HEADROOM;
1367                 if (size < dev->data->dev_conf.rxmode.max_rx_pkt_len) {
1368                         DRV_LOG(ERR,
1369                                 "port %u too many SGEs (%u) needed to handle"
1370                                 " requested maximum packet size %u",
1371                                 dev->data->port_id,
1372                                 1 << sges_n,
1373                                 dev->data->dev_conf.rxmode.max_rx_pkt_len);
1374                         rte_errno = EOVERFLOW;
1375                         goto error;
1376                 }
1377         } else {
1378                 DRV_LOG(WARNING,
1379                         "port %u the requested maximum Rx packet size (%u) is"
1380                         " larger than a single mbuf (%u) and scattered mode has"
1381                         " not been requested",
1382                         dev->data->port_id,
1383                         dev->data->dev_conf.rxmode.max_rx_pkt_len,
1384                         mb_len - RTE_PKTMBUF_HEADROOM);
1385         }
1386         if (mprq_en && !mlx5_rxq_mprq_enabled(&tmpl->rxq))
1387                 DRV_LOG(WARNING,
1388                         "port %u MPRQ is requested but cannot be enabled"
1389                         " (requested: desc = %u, stride_sz = %u,"
1390                         " supported: min_stride_num = %u, max_stride_sz = %u).",
1391                         dev->data->port_id, desc, mprq_stride_size,
1392                         (1 << config->mprq.stride_num_n),
1393                         (1 << config->mprq.max_stride_size_n));
1394         DRV_LOG(DEBUG, "port %u maximum number of segments per packet: %u",
1395                 dev->data->port_id, 1 << tmpl->rxq.sges_n);
1396         if (desc % (1 << tmpl->rxq.sges_n)) {
1397                 DRV_LOG(ERR,
1398                         "port %u number of Rx queue descriptors (%u) is not a"
1399                         " multiple of SGEs per packet (%u)",
1400                         dev->data->port_id,
1401                         desc,
1402                         1 << tmpl->rxq.sges_n);
1403                 rte_errno = EINVAL;
1404                 goto error;
1405         }
1406         /* Toggle RX checksum offload if hardware supports it. */
1407         tmpl->rxq.csum = !!(offloads & DEV_RX_OFFLOAD_CHECKSUM);
1408         tmpl->rxq.hw_timestamp = !!(offloads & DEV_RX_OFFLOAD_TIMESTAMP);
1409         /* Configure VLAN stripping. */
1410         tmpl->rxq.vlan_strip = !!(offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
1411         /* By default, FCS (CRC) is stripped by hardware. */
1412         tmpl->rxq.crc_present = 0;
1413         if (offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
1414                 if (config->hw_fcs_strip) {
1415                         tmpl->rxq.crc_present = 1;
1416                 } else {
1417                         DRV_LOG(WARNING,
1418                                 "port %u CRC stripping has been disabled but will"
1419                                 " still be performed by hardware, make sure MLNX_OFED"
1420                                 " and firmware are up to date",
1421                                 dev->data->port_id);
1422                 }
1423         }
1424         DRV_LOG(DEBUG,
1425                 "port %u CRC stripping is %s, %u bytes will be subtracted from"
1426                 " incoming frames to hide it",
1427                 dev->data->port_id,
1428                 tmpl->rxq.crc_present ? "disabled" : "enabled",
1429                 tmpl->rxq.crc_present << 2);
1430         /* Save port ID. */
1431         tmpl->rxq.rss_hash = !!priv->rss_conf.rss_hf &&
1432                 (!!(dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS));
1433         tmpl->rxq.port_id = dev->data->port_id;
1434         tmpl->priv = priv;
1435         tmpl->rxq.mp = mp;
1436         tmpl->rxq.elts_n = log2above(desc);
1437         tmpl->rxq.rq_repl_thresh =
1438                 MLX5_VPMD_RXQ_RPLNSH_THRESH(1 << tmpl->rxq.elts_n);
1439         tmpl->rxq.elts =
1440                 (struct rte_mbuf *(*)[1 << tmpl->rxq.elts_n])(tmpl + 1);
1441 #ifndef RTE_ARCH_64
1442         tmpl->rxq.uar_lock_cq = &priv->uar_lock_cq;
1443 #endif
1444         tmpl->rxq.idx = idx;
1445         rte_atomic32_inc(&tmpl->refcnt);
1446         LIST_INSERT_HEAD(&priv->rxqsctrl, tmpl, next);
1447         return tmpl;
1448 error:
1449         rte_free(tmpl);
1450         return NULL;
1451 }
1452
1453 /**
1454  * Get a Rx queue.
1455  *
1456  * @param dev
1457  *   Pointer to Ethernet device.
1458  * @param idx
1459  *   RX queue index.
1460  *
1461  * @return
1462  *   A pointer to the queue if it exists, NULL otherwise.
1463  */
1464 struct mlx5_rxq_ctrl *
1465 mlx5_rxq_get(struct rte_eth_dev *dev, uint16_t idx)
1466 {
1467         struct mlx5_priv *priv = dev->data->dev_private;
1468         struct mlx5_rxq_ctrl *rxq_ctrl = NULL;
1469
1470         if ((*priv->rxqs)[idx]) {
1471                 rxq_ctrl = container_of((*priv->rxqs)[idx],
1472                                         struct mlx5_rxq_ctrl,
1473                                         rxq);
1474                 mlx5_rxq_ibv_get(dev, idx);
1475                 rte_atomic32_inc(&rxq_ctrl->refcnt);
1476         }
1477         return rxq_ctrl;
1478 }
1479
1480 /**
1481  * Release a Rx queue.
1482  *
1483  * @param dev
1484  *   Pointer to Ethernet device.
1485  * @param idx
1486  *   RX queue index.
1487  *
1488  * @return
1489  *   1 while a reference on it exists, 0 when freed.
1490  */
1491 int
1492 mlx5_rxq_release(struct rte_eth_dev *dev, uint16_t idx)
1493 {
1494         struct mlx5_priv *priv = dev->data->dev_private;
1495         struct mlx5_rxq_ctrl *rxq_ctrl;
1496
1497         if (!(*priv->rxqs)[idx])
1498                 return 0;
1499         rxq_ctrl = container_of((*priv->rxqs)[idx], struct mlx5_rxq_ctrl, rxq);
1500         assert(rxq_ctrl->priv);
1501         if (rxq_ctrl->ibv && !mlx5_rxq_ibv_release(rxq_ctrl->ibv))
1502                 rxq_ctrl->ibv = NULL;
1503         if (rte_atomic32_dec_and_test(&rxq_ctrl->refcnt)) {
1504                 mlx5_mr_btree_free(&rxq_ctrl->rxq.mr_ctrl.cache_bh);
1505                 LIST_REMOVE(rxq_ctrl, next);
1506                 rte_free(rxq_ctrl);
1507                 (*priv->rxqs)[idx] = NULL;
1508                 return 0;
1509         }
1510         return 1;
1511 }
1512
1513 /**
1514  * Verify the Rx Queue list is empty
1515  *
1516  * @param dev
1517  *   Pointer to Ethernet device.
1518  *
1519  * @return
1520  *   The number of object not released.
1521  */
1522 int
1523 mlx5_rxq_verify(struct rte_eth_dev *dev)
1524 {
1525         struct mlx5_priv *priv = dev->data->dev_private;
1526         struct mlx5_rxq_ctrl *rxq_ctrl;
1527         int ret = 0;
1528
1529         LIST_FOREACH(rxq_ctrl, &priv->rxqsctrl, next) {
1530                 DRV_LOG(DEBUG, "port %u Rx Queue %u still referenced",
1531                         dev->data->port_id, rxq_ctrl->rxq.idx);
1532                 ++ret;
1533         }
1534         return ret;
1535 }
1536
1537 /**
1538  * Create an indirection table.
1539  *
1540  * @param dev
1541  *   Pointer to Ethernet device.
1542  * @param queues
1543  *   Queues entering in the indirection table.
1544  * @param queues_n
1545  *   Number of queues in the array.
1546  *
1547  * @return
1548  *   The Verbs object initialised, NULL otherwise and rte_errno is set.
1549  */
1550 static struct mlx5_ind_table_ibv *
1551 mlx5_ind_table_ibv_new(struct rte_eth_dev *dev, const uint16_t *queues,
1552                        uint32_t queues_n)
1553 {
1554         struct mlx5_priv *priv = dev->data->dev_private;
1555         struct mlx5_ind_table_ibv *ind_tbl;
1556         const unsigned int wq_n = rte_is_power_of_2(queues_n) ?
1557                 log2above(queues_n) :
1558                 log2above(priv->config.ind_table_max_size);
1559         struct ibv_wq *wq[1 << wq_n];
1560         unsigned int i;
1561         unsigned int j;
1562
1563         ind_tbl = rte_calloc(__func__, 1, sizeof(*ind_tbl) +
1564                              queues_n * sizeof(uint16_t), 0);
1565         if (!ind_tbl) {
1566                 rte_errno = ENOMEM;
1567                 return NULL;
1568         }
1569         for (i = 0; i != queues_n; ++i) {
1570                 struct mlx5_rxq_ctrl *rxq = mlx5_rxq_get(dev, queues[i]);
1571
1572                 if (!rxq)
1573                         goto error;
1574                 wq[i] = rxq->ibv->wq;
1575                 ind_tbl->queues[i] = queues[i];
1576         }
1577         ind_tbl->queues_n = queues_n;
1578         /* Finalise indirection table. */
1579         for (j = 0; i != (unsigned int)(1 << wq_n); ++i, ++j)
1580                 wq[i] = wq[j];
1581         ind_tbl->ind_table = mlx5_glue->create_rwq_ind_table
1582                 (priv->sh->ctx,
1583                  &(struct ibv_rwq_ind_table_init_attr){
1584                         .log_ind_tbl_size = wq_n,
1585                         .ind_tbl = wq,
1586                         .comp_mask = 0,
1587                  });
1588         if (!ind_tbl->ind_table) {
1589                 rte_errno = errno;
1590                 goto error;
1591         }
1592         rte_atomic32_inc(&ind_tbl->refcnt);
1593         LIST_INSERT_HEAD(&priv->ind_tbls, ind_tbl, next);
1594         return ind_tbl;
1595 error:
1596         rte_free(ind_tbl);
1597         DEBUG("port %u cannot create indirection table", dev->data->port_id);
1598         return NULL;
1599 }
1600
1601 /**
1602  * Get an indirection table.
1603  *
1604  * @param dev
1605  *   Pointer to Ethernet device.
1606  * @param queues
1607  *   Queues entering in the indirection table.
1608  * @param queues_n
1609  *   Number of queues in the array.
1610  *
1611  * @return
1612  *   An indirection table if found.
1613  */
1614 static struct mlx5_ind_table_ibv *
1615 mlx5_ind_table_ibv_get(struct rte_eth_dev *dev, const uint16_t *queues,
1616                        uint32_t queues_n)
1617 {
1618         struct mlx5_priv *priv = dev->data->dev_private;
1619         struct mlx5_ind_table_ibv *ind_tbl;
1620
1621         LIST_FOREACH(ind_tbl, &priv->ind_tbls, next) {
1622                 if ((ind_tbl->queues_n == queues_n) &&
1623                     (memcmp(ind_tbl->queues, queues,
1624                             ind_tbl->queues_n * sizeof(ind_tbl->queues[0]))
1625                      == 0))
1626                         break;
1627         }
1628         if (ind_tbl) {
1629                 unsigned int i;
1630
1631                 rte_atomic32_inc(&ind_tbl->refcnt);
1632                 for (i = 0; i != ind_tbl->queues_n; ++i)
1633                         mlx5_rxq_get(dev, ind_tbl->queues[i]);
1634         }
1635         return ind_tbl;
1636 }
1637
1638 /**
1639  * Release an indirection table.
1640  *
1641  * @param dev
1642  *   Pointer to Ethernet device.
1643  * @param ind_table
1644  *   Indirection table to release.
1645  *
1646  * @return
1647  *   1 while a reference on it exists, 0 when freed.
1648  */
1649 static int
1650 mlx5_ind_table_ibv_release(struct rte_eth_dev *dev,
1651                            struct mlx5_ind_table_ibv *ind_tbl)
1652 {
1653         unsigned int i;
1654
1655         if (rte_atomic32_dec_and_test(&ind_tbl->refcnt))
1656                 claim_zero(mlx5_glue->destroy_rwq_ind_table
1657                            (ind_tbl->ind_table));
1658         for (i = 0; i != ind_tbl->queues_n; ++i)
1659                 claim_nonzero(mlx5_rxq_release(dev, ind_tbl->queues[i]));
1660         if (!rte_atomic32_read(&ind_tbl->refcnt)) {
1661                 LIST_REMOVE(ind_tbl, next);
1662                 rte_free(ind_tbl);
1663                 return 0;
1664         }
1665         return 1;
1666 }
1667
1668 /**
1669  * Verify the Rx Queue list is empty
1670  *
1671  * @param dev
1672  *   Pointer to Ethernet device.
1673  *
1674  * @return
1675  *   The number of object not released.
1676  */
1677 int
1678 mlx5_ind_table_ibv_verify(struct rte_eth_dev *dev)
1679 {
1680         struct mlx5_priv *priv = dev->data->dev_private;
1681         struct mlx5_ind_table_ibv *ind_tbl;
1682         int ret = 0;
1683
1684         LIST_FOREACH(ind_tbl, &priv->ind_tbls, next) {
1685                 DRV_LOG(DEBUG,
1686                         "port %u Verbs indirection table %p still referenced",
1687                         dev->data->port_id, (void *)ind_tbl);
1688                 ++ret;
1689         }
1690         return ret;
1691 }
1692
1693 /**
1694  * Create an Rx Hash queue.
1695  *
1696  * @param dev
1697  *   Pointer to Ethernet device.
1698  * @param rss_key
1699  *   RSS key for the Rx hash queue.
1700  * @param rss_key_len
1701  *   RSS key length.
1702  * @param hash_fields
1703  *   Verbs protocol hash field to make the RSS on.
1704  * @param queues
1705  *   Queues entering in hash queue. In case of empty hash_fields only the
1706  *   first queue index will be taken for the indirection table.
1707  * @param queues_n
1708  *   Number of queues.
1709  * @param tunnel
1710  *   Tunnel type.
1711  *
1712  * @return
1713  *   The Verbs object initialised, NULL otherwise and rte_errno is set.
1714  */
1715 struct mlx5_hrxq *
1716 mlx5_hrxq_new(struct rte_eth_dev *dev,
1717               const uint8_t *rss_key, uint32_t rss_key_len,
1718               uint64_t hash_fields,
1719               const uint16_t *queues, uint32_t queues_n,
1720               int tunnel __rte_unused)
1721 {
1722         struct mlx5_priv *priv = dev->data->dev_private;
1723         struct mlx5_hrxq *hrxq;
1724         struct mlx5_ind_table_ibv *ind_tbl;
1725         struct ibv_qp *qp;
1726 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
1727         struct mlx5dv_qp_init_attr qp_init_attr;
1728 #endif
1729         int err;
1730
1731         queues_n = hash_fields ? queues_n : 1;
1732         ind_tbl = mlx5_ind_table_ibv_get(dev, queues, queues_n);
1733         if (!ind_tbl)
1734                 ind_tbl = mlx5_ind_table_ibv_new(dev, queues, queues_n);
1735         if (!ind_tbl) {
1736                 rte_errno = ENOMEM;
1737                 return NULL;
1738         }
1739 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
1740         memset(&qp_init_attr, 0, sizeof(qp_init_attr));
1741         if (tunnel) {
1742                 qp_init_attr.comp_mask =
1743                                 MLX5DV_QP_INIT_ATTR_MASK_QP_CREATE_FLAGS;
1744                 qp_init_attr.create_flags = MLX5DV_QP_CREATE_TUNNEL_OFFLOADS;
1745         }
1746 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
1747         if (dev->data->dev_conf.lpbk_mode) {
1748                 /* Allow packet sent from NIC loop back w/o source MAC check. */
1749                 qp_init_attr.comp_mask |=
1750                                 MLX5DV_QP_INIT_ATTR_MASK_QP_CREATE_FLAGS;
1751                 qp_init_attr.create_flags |=
1752                                 MLX5DV_QP_CREATE_TIR_ALLOW_SELF_LOOPBACK_UC;
1753         }
1754 #endif
1755         qp = mlx5_glue->dv_create_qp
1756                 (priv->sh->ctx,
1757                  &(struct ibv_qp_init_attr_ex){
1758                         .qp_type = IBV_QPT_RAW_PACKET,
1759                         .comp_mask =
1760                                 IBV_QP_INIT_ATTR_PD |
1761                                 IBV_QP_INIT_ATTR_IND_TABLE |
1762                                 IBV_QP_INIT_ATTR_RX_HASH,
1763                         .rx_hash_conf = (struct ibv_rx_hash_conf){
1764                                 .rx_hash_function = IBV_RX_HASH_FUNC_TOEPLITZ,
1765                                 .rx_hash_key_len = rss_key_len,
1766                                 .rx_hash_key = (void *)(uintptr_t)rss_key,
1767                                 .rx_hash_fields_mask = hash_fields,
1768                         },
1769                         .rwq_ind_tbl = ind_tbl->ind_table,
1770                         .pd = priv->sh->pd,
1771                  },
1772                  &qp_init_attr);
1773 #else
1774         qp = mlx5_glue->create_qp_ex
1775                 (priv->sh->ctx,
1776                  &(struct ibv_qp_init_attr_ex){
1777                         .qp_type = IBV_QPT_RAW_PACKET,
1778                         .comp_mask =
1779                                 IBV_QP_INIT_ATTR_PD |
1780                                 IBV_QP_INIT_ATTR_IND_TABLE |
1781                                 IBV_QP_INIT_ATTR_RX_HASH,
1782                         .rx_hash_conf = (struct ibv_rx_hash_conf){
1783                                 .rx_hash_function = IBV_RX_HASH_FUNC_TOEPLITZ,
1784                                 .rx_hash_key_len = rss_key_len,
1785                                 .rx_hash_key = (void *)(uintptr_t)rss_key,
1786                                 .rx_hash_fields_mask = hash_fields,
1787                         },
1788                         .rwq_ind_tbl = ind_tbl->ind_table,
1789                         .pd = priv->sh->pd,
1790                  });
1791 #endif
1792         if (!qp) {
1793                 rte_errno = errno;
1794                 goto error;
1795         }
1796         hrxq = rte_calloc(__func__, 1, sizeof(*hrxq) + rss_key_len, 0);
1797         if (!hrxq)
1798                 goto error;
1799         hrxq->ind_table = ind_tbl;
1800         hrxq->qp = qp;
1801         hrxq->rss_key_len = rss_key_len;
1802         hrxq->hash_fields = hash_fields;
1803         memcpy(hrxq->rss_key, rss_key, rss_key_len);
1804 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
1805         hrxq->action = mlx5_glue->dv_create_flow_action_dest_ibv_qp(hrxq->qp);
1806         if (!hrxq->action) {
1807                 rte_errno = errno;
1808                 goto error;
1809         }
1810 #endif
1811         rte_atomic32_inc(&hrxq->refcnt);
1812         LIST_INSERT_HEAD(&priv->hrxqs, hrxq, next);
1813         return hrxq;
1814 error:
1815         err = rte_errno; /* Save rte_errno before cleanup. */
1816         mlx5_ind_table_ibv_release(dev, ind_tbl);
1817         if (qp)
1818                 claim_zero(mlx5_glue->destroy_qp(qp));
1819         rte_errno = err; /* Restore rte_errno. */
1820         return NULL;
1821 }
1822
1823 /**
1824  * Get an Rx Hash queue.
1825  *
1826  * @param dev
1827  *   Pointer to Ethernet device.
1828  * @param rss_conf
1829  *   RSS configuration for the Rx hash queue.
1830  * @param queues
1831  *   Queues entering in hash queue. In case of empty hash_fields only the
1832  *   first queue index will be taken for the indirection table.
1833  * @param queues_n
1834  *   Number of queues.
1835  *
1836  * @return
1837  *   An hash Rx queue on success.
1838  */
1839 struct mlx5_hrxq *
1840 mlx5_hrxq_get(struct rte_eth_dev *dev,
1841               const uint8_t *rss_key, uint32_t rss_key_len,
1842               uint64_t hash_fields,
1843               const uint16_t *queues, uint32_t queues_n)
1844 {
1845         struct mlx5_priv *priv = dev->data->dev_private;
1846         struct mlx5_hrxq *hrxq;
1847
1848         queues_n = hash_fields ? queues_n : 1;
1849         LIST_FOREACH(hrxq, &priv->hrxqs, next) {
1850                 struct mlx5_ind_table_ibv *ind_tbl;
1851
1852                 if (hrxq->rss_key_len != rss_key_len)
1853                         continue;
1854                 if (memcmp(hrxq->rss_key, rss_key, rss_key_len))
1855                         continue;
1856                 if (hrxq->hash_fields != hash_fields)
1857                         continue;
1858                 ind_tbl = mlx5_ind_table_ibv_get(dev, queues, queues_n);
1859                 if (!ind_tbl)
1860                         continue;
1861                 if (ind_tbl != hrxq->ind_table) {
1862                         mlx5_ind_table_ibv_release(dev, ind_tbl);
1863                         continue;
1864                 }
1865                 rte_atomic32_inc(&hrxq->refcnt);
1866                 return hrxq;
1867         }
1868         return NULL;
1869 }
1870
1871 /**
1872  * Release the hash Rx queue.
1873  *
1874  * @param dev
1875  *   Pointer to Ethernet device.
1876  * @param hrxq
1877  *   Pointer to Hash Rx queue to release.
1878  *
1879  * @return
1880  *   1 while a reference on it exists, 0 when freed.
1881  */
1882 int
1883 mlx5_hrxq_release(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq)
1884 {
1885         if (rte_atomic32_dec_and_test(&hrxq->refcnt)) {
1886 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
1887                 mlx5_glue->destroy_flow_action(hrxq->action);
1888 #endif
1889                 claim_zero(mlx5_glue->destroy_qp(hrxq->qp));
1890                 mlx5_ind_table_ibv_release(dev, hrxq->ind_table);
1891                 LIST_REMOVE(hrxq, next);
1892                 rte_free(hrxq);
1893                 return 0;
1894         }
1895         claim_nonzero(mlx5_ind_table_ibv_release(dev, hrxq->ind_table));
1896         return 1;
1897 }
1898
1899 /**
1900  * Verify the Rx Queue list is empty
1901  *
1902  * @param dev
1903  *   Pointer to Ethernet device.
1904  *
1905  * @return
1906  *   The number of object not released.
1907  */
1908 int
1909 mlx5_hrxq_ibv_verify(struct rte_eth_dev *dev)
1910 {
1911         struct mlx5_priv *priv = dev->data->dev_private;
1912         struct mlx5_hrxq *hrxq;
1913         int ret = 0;
1914
1915         LIST_FOREACH(hrxq, &priv->hrxqs, next) {
1916                 DRV_LOG(DEBUG,
1917                         "port %u Verbs hash Rx queue %p still referenced",
1918                         dev->data->port_id, (void *)hrxq);
1919                 ++ret;
1920         }
1921         return ret;
1922 }
1923
1924 /**
1925  * Create a drop Rx queue Verbs object.
1926  *
1927  * @param dev
1928  *   Pointer to Ethernet device.
1929  *
1930  * @return
1931  *   The Verbs object initialised, NULL otherwise and rte_errno is set.
1932  */
1933 static struct mlx5_rxq_ibv *
1934 mlx5_rxq_ibv_drop_new(struct rte_eth_dev *dev)
1935 {
1936         struct mlx5_priv *priv = dev->data->dev_private;
1937         struct ibv_context *ctx = priv->sh->ctx;
1938         struct ibv_cq *cq;
1939         struct ibv_wq *wq = NULL;
1940         struct mlx5_rxq_ibv *rxq;
1941
1942         if (priv->drop_queue.rxq)
1943                 return priv->drop_queue.rxq;
1944         cq = mlx5_glue->create_cq(ctx, 1, NULL, NULL, 0);
1945         if (!cq) {
1946                 DEBUG("port %u cannot allocate CQ for drop queue",
1947                       dev->data->port_id);
1948                 rte_errno = errno;
1949                 goto error;
1950         }
1951         wq = mlx5_glue->create_wq(ctx,
1952                  &(struct ibv_wq_init_attr){
1953                         .wq_type = IBV_WQT_RQ,
1954                         .max_wr = 1,
1955                         .max_sge = 1,
1956                         .pd = priv->sh->pd,
1957                         .cq = cq,
1958                  });
1959         if (!wq) {
1960                 DEBUG("port %u cannot allocate WQ for drop queue",
1961                       dev->data->port_id);
1962                 rte_errno = errno;
1963                 goto error;
1964         }
1965         rxq = rte_calloc(__func__, 1, sizeof(*rxq), 0);
1966         if (!rxq) {
1967                 DEBUG("port %u cannot allocate drop Rx queue memory",
1968                       dev->data->port_id);
1969                 rte_errno = ENOMEM;
1970                 goto error;
1971         }
1972         rxq->cq = cq;
1973         rxq->wq = wq;
1974         priv->drop_queue.rxq = rxq;
1975         return rxq;
1976 error:
1977         if (wq)
1978                 claim_zero(mlx5_glue->destroy_wq(wq));
1979         if (cq)
1980                 claim_zero(mlx5_glue->destroy_cq(cq));
1981         return NULL;
1982 }
1983
1984 /**
1985  * Release a drop Rx queue Verbs object.
1986  *
1987  * @param dev
1988  *   Pointer to Ethernet device.
1989  *
1990  * @return
1991  *   The Verbs object initialised, NULL otherwise and rte_errno is set.
1992  */
1993 static void
1994 mlx5_rxq_ibv_drop_release(struct rte_eth_dev *dev)
1995 {
1996         struct mlx5_priv *priv = dev->data->dev_private;
1997         struct mlx5_rxq_ibv *rxq = priv->drop_queue.rxq;
1998
1999         if (rxq->wq)
2000                 claim_zero(mlx5_glue->destroy_wq(rxq->wq));
2001         if (rxq->cq)
2002                 claim_zero(mlx5_glue->destroy_cq(rxq->cq));
2003         rte_free(rxq);
2004         priv->drop_queue.rxq = NULL;
2005 }
2006
2007 /**
2008  * Create a drop indirection table.
2009  *
2010  * @param dev
2011  *   Pointer to Ethernet device.
2012  *
2013  * @return
2014  *   The Verbs object initialised, NULL otherwise and rte_errno is set.
2015  */
2016 static struct mlx5_ind_table_ibv *
2017 mlx5_ind_table_ibv_drop_new(struct rte_eth_dev *dev)
2018 {
2019         struct mlx5_priv *priv = dev->data->dev_private;
2020         struct mlx5_ind_table_ibv *ind_tbl;
2021         struct mlx5_rxq_ibv *rxq;
2022         struct mlx5_ind_table_ibv tmpl;
2023
2024         rxq = mlx5_rxq_ibv_drop_new(dev);
2025         if (!rxq)
2026                 return NULL;
2027         tmpl.ind_table = mlx5_glue->create_rwq_ind_table
2028                 (priv->sh->ctx,
2029                  &(struct ibv_rwq_ind_table_init_attr){
2030                         .log_ind_tbl_size = 0,
2031                         .ind_tbl = &rxq->wq,
2032                         .comp_mask = 0,
2033                  });
2034         if (!tmpl.ind_table) {
2035                 DEBUG("port %u cannot allocate indirection table for drop"
2036                       " queue",
2037                       dev->data->port_id);
2038                 rte_errno = errno;
2039                 goto error;
2040         }
2041         ind_tbl = rte_calloc(__func__, 1, sizeof(*ind_tbl), 0);
2042         if (!ind_tbl) {
2043                 rte_errno = ENOMEM;
2044                 goto error;
2045         }
2046         ind_tbl->ind_table = tmpl.ind_table;
2047         return ind_tbl;
2048 error:
2049         mlx5_rxq_ibv_drop_release(dev);
2050         return NULL;
2051 }
2052
2053 /**
2054  * Release a drop indirection table.
2055  *
2056  * @param dev
2057  *   Pointer to Ethernet device.
2058  */
2059 static void
2060 mlx5_ind_table_ibv_drop_release(struct rte_eth_dev *dev)
2061 {
2062         struct mlx5_priv *priv = dev->data->dev_private;
2063         struct mlx5_ind_table_ibv *ind_tbl = priv->drop_queue.hrxq->ind_table;
2064
2065         claim_zero(mlx5_glue->destroy_rwq_ind_table(ind_tbl->ind_table));
2066         mlx5_rxq_ibv_drop_release(dev);
2067         rte_free(ind_tbl);
2068         priv->drop_queue.hrxq->ind_table = NULL;
2069 }
2070
2071 /**
2072  * Create a drop Rx Hash queue.
2073  *
2074  * @param dev
2075  *   Pointer to Ethernet device.
2076  *
2077  * @return
2078  *   The Verbs object initialised, NULL otherwise and rte_errno is set.
2079  */
2080 struct mlx5_hrxq *
2081 mlx5_hrxq_drop_new(struct rte_eth_dev *dev)
2082 {
2083         struct mlx5_priv *priv = dev->data->dev_private;
2084         struct mlx5_ind_table_ibv *ind_tbl;
2085         struct ibv_qp *qp;
2086         struct mlx5_hrxq *hrxq;
2087
2088         if (priv->drop_queue.hrxq) {
2089                 rte_atomic32_inc(&priv->drop_queue.hrxq->refcnt);
2090                 return priv->drop_queue.hrxq;
2091         }
2092         ind_tbl = mlx5_ind_table_ibv_drop_new(dev);
2093         if (!ind_tbl)
2094                 return NULL;
2095         qp = mlx5_glue->create_qp_ex(priv->sh->ctx,
2096                  &(struct ibv_qp_init_attr_ex){
2097                         .qp_type = IBV_QPT_RAW_PACKET,
2098                         .comp_mask =
2099                                 IBV_QP_INIT_ATTR_PD |
2100                                 IBV_QP_INIT_ATTR_IND_TABLE |
2101                                 IBV_QP_INIT_ATTR_RX_HASH,
2102                         .rx_hash_conf = (struct ibv_rx_hash_conf){
2103                                 .rx_hash_function =
2104                                         IBV_RX_HASH_FUNC_TOEPLITZ,
2105                                 .rx_hash_key_len = MLX5_RSS_HASH_KEY_LEN,
2106                                 .rx_hash_key = rss_hash_default_key,
2107                                 .rx_hash_fields_mask = 0,
2108                                 },
2109                         .rwq_ind_tbl = ind_tbl->ind_table,
2110                         .pd = priv->sh->pd
2111                  });
2112         if (!qp) {
2113                 DEBUG("port %u cannot allocate QP for drop queue",
2114                       dev->data->port_id);
2115                 rte_errno = errno;
2116                 goto error;
2117         }
2118         hrxq = rte_calloc(__func__, 1, sizeof(*hrxq), 0);
2119         if (!hrxq) {
2120                 DRV_LOG(WARNING,
2121                         "port %u cannot allocate memory for drop queue",
2122                         dev->data->port_id);
2123                 rte_errno = ENOMEM;
2124                 goto error;
2125         }
2126         hrxq->ind_table = ind_tbl;
2127         hrxq->qp = qp;
2128 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2129         hrxq->action = mlx5_glue->dv_create_flow_action_dest_ibv_qp(hrxq->qp);
2130         if (!hrxq->action) {
2131                 rte_errno = errno;
2132                 goto error;
2133         }
2134 #endif
2135         priv->drop_queue.hrxq = hrxq;
2136         rte_atomic32_set(&hrxq->refcnt, 1);
2137         return hrxq;
2138 error:
2139         if (ind_tbl)
2140                 mlx5_ind_table_ibv_drop_release(dev);
2141         return NULL;
2142 }
2143
2144 /**
2145  * Release a drop hash Rx queue.
2146  *
2147  * @param dev
2148  *   Pointer to Ethernet device.
2149  */
2150 void
2151 mlx5_hrxq_drop_release(struct rte_eth_dev *dev)
2152 {
2153         struct mlx5_priv *priv = dev->data->dev_private;
2154         struct mlx5_hrxq *hrxq = priv->drop_queue.hrxq;
2155
2156         if (rte_atomic32_dec_and_test(&hrxq->refcnt)) {
2157 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2158                 mlx5_glue->destroy_flow_action(hrxq->action);
2159 #endif
2160                 claim_zero(mlx5_glue->destroy_qp(hrxq->qp));
2161                 mlx5_ind_table_ibv_drop_release(dev);
2162                 rte_free(hrxq);
2163                 priv->drop_queue.hrxq = NULL;
2164         }
2165 }