drivers/net/mlx5/mlx5_rxq.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <stddef.h>
   7 #include <assert.h>
   8 #include <errno.h>
   9 #include <string.h>
  10 #include <stdint.h>
  11 #include <fcntl.h>
  12 #include <sys/queue.h>
  13
  14 /* Verbs header. */
  15 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  16 #ifdef PEDANTIC
  17 #pragma GCC diagnostic ignored "-Wpedantic"
  18 #endif
  19 #include <infiniband/verbs.h>
  20 #include <infiniband/mlx5dv.h>
  21 #ifdef PEDANTIC
  22 #pragma GCC diagnostic error "-Wpedantic"
  23 #endif
  24
  25 #include <rte_mbuf.h>
  26 #include <rte_malloc.h>
  27 #include <rte_ethdev_driver.h>
  28 #include <rte_common.h>
  29 #include <rte_interrupts.h>
  30 #include <rte_debug.h>
  31 #include <rte_io.h>
  32
  33 #include "mlx5.h"
  34 #include "mlx5_rxtx.h"
  35 #include "mlx5_utils.h"
  36 #include "mlx5_autoconf.h"
  37 #include "mlx5_defs.h"
  38 #include "mlx5_glue.h"
  39 #include "mlx5_flow.h"
  40
  41 /* Default RSS hash key also used for ConnectX-3. */
  42 uint8_t rss_hash_default_key[] = {
  43         0x2c, 0xc6, 0x81, 0xd1,
  44         0x5b, 0xdb, 0xf4, 0xf7,
  45         0xfc, 0xa2, 0x83, 0x19,
  46         0xdb, 0x1a, 0x3e, 0x94,
  47         0x6b, 0x9e, 0x38, 0xd9,
  48         0x2c, 0x9c, 0x03, 0xd1,
  49         0xad, 0x99, 0x44, 0xa7,
  50         0xd9, 0x56, 0x3d, 0x59,
  51         0x06, 0x3c, 0x25, 0xf3,
  52         0xfc, 0x1f, 0xdc, 0x2a,
  53 };
  54
  55 /* Length of the default RSS hash key. */
  56 static_assert(MLX5_RSS_HASH_KEY_LEN ==
  57               (unsigned int)sizeof(rss_hash_default_key),
  58               "wrong RSS default key size.");
  59
  60 /**
  61  * Check whether Multi-Packet RQ can be enabled for the device.
  62  *
  63  * @param dev
  64  *   Pointer to Ethernet device.
  65  *
  66  * @return
  67  *   1 if supported, negative errno value if not.
  68  */
  69 inline int
  70 mlx5_check_mprq_support(struct rte_eth_dev *dev)
  71 {
  72         struct mlx5_priv *priv = dev->data->dev_private;
  73
  74         if (priv->config.mprq.enabled &&
  75             priv->rxqs_n >= priv->config.mprq.min_rxqs_num)
  76                 return 1;
  77         return -ENOTSUP;
  78 }
  79
  80 /**
  81  * Check whether Multi-Packet RQ is enabled for the Rx queue.
  82  *
  83  *  @param rxq
  84  *     Pointer to receive queue structure.
  85  *
  86  * @return
  87  *   0 if disabled, otherwise enabled.
  88  */
  89 inline int
  90 mlx5_rxq_mprq_enabled(struct mlx5_rxq_data *rxq)
  91 {
  92         return rxq->strd_num_n > 0;
  93 }
  94
  95 /**
  96  * Check whether Multi-Packet RQ is enabled for the device.
  97  *
  98  * @param dev
  99  *   Pointer to Ethernet device.
 100  *
 101  * @return
 102  *   0 if disabled, otherwise enabled.
 103  */
 104 inline int
 105 mlx5_mprq_enabled(struct rte_eth_dev *dev)
 106 {
 107         struct mlx5_priv *priv = dev->data->dev_private;
 108         uint16_t i;
 109         uint16_t n = 0;
 110         uint16_t n_ibv = 0;
 111
 112         if (mlx5_check_mprq_support(dev) < 0)
 113                 return 0;
 114         /* All the configured queues should be enabled. */
 115         for (i = 0; i < priv->rxqs_n; ++i) {
 116                 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
 117                 struct mlx5_rxq_ctrl *rxq_ctrl = container_of
 118                         (rxq, struct mlx5_rxq_ctrl, rxq);
 119
 120                 if (rxq == NULL || rxq_ctrl->type != MLX5_RXQ_TYPE_STANDARD)
 121                         continue;
 122                 n_ibv++;
 123                 if (mlx5_rxq_mprq_enabled(rxq))
 124                         ++n;
 125         }
 126         /* Multi-Packet RQ can't be partially configured. */
 127         assert(n == 0 || n == n_ibv);
 128         return n == n_ibv;
 129 }
 130
 131 /**
 132  * Allocate RX queue elements for Multi-Packet RQ.
 133  *
 134  * @param rxq_ctrl
 135  *   Pointer to RX queue structure.
 136  *
 137  * @return
 138  *   0 on success, a negative errno value otherwise and rte_errno is set.
 139  */
 140 static int
 141 rxq_alloc_elts_mprq(struct mlx5_rxq_ctrl *rxq_ctrl)
 142 {
 143         struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
 144         unsigned int wqe_n = 1 << rxq->elts_n;
 145         unsigned int i;
 146         int err;
 147
 148         /* Iterate on segments. */
 149         for (i = 0; i <= wqe_n; ++i) {
 150                 struct mlx5_mprq_buf *buf;
 151
 152                 if (rte_mempool_get(rxq->mprq_mp, (void **)&buf) < 0) {
 153                         DRV_LOG(ERR, "port %u empty mbuf pool", rxq->port_id);
 154                         rte_errno = ENOMEM;
 155                         goto error;
 156                 }
 157                 if (i < wqe_n)
 158                         (*rxq->mprq_bufs)[i] = buf;
 159                 else
 160                         rxq->mprq_repl = buf;
 161         }
 162         DRV_LOG(DEBUG,
 163                 "port %u Rx queue %u allocated and configured %u segments",
 164                 rxq->port_id, rxq->idx, wqe_n);
 165         return 0;
 166 error:
 167         err = rte_errno; /* Save rte_errno before cleanup. */
 168         wqe_n = i;
 169         for (i = 0; (i != wqe_n); ++i) {
 170                 if ((*rxq->mprq_bufs)[i] != NULL)
 171                         rte_mempool_put(rxq->mprq_mp,
 172                                         (*rxq->mprq_bufs)[i]);
 173                 (*rxq->mprq_bufs)[i] = NULL;
 174         }
 175         DRV_LOG(DEBUG, "port %u Rx queue %u failed, freed everything",
 176                 rxq->port_id, rxq->idx);
 177         rte_errno = err; /* Restore rte_errno. */
 178         return -rte_errno;
 179 }
 180
 181 /**
 182  * Allocate RX queue elements for Single-Packet RQ.
 183  *
 184  * @param rxq_ctrl
 185  *   Pointer to RX queue structure.
 186  *
 187  * @return
 188  *   0 on success, errno value on failure.
 189  */
 190 static int
 191 rxq_alloc_elts_sprq(struct mlx5_rxq_ctrl *rxq_ctrl)
 192 {
 193         const unsigned int sges_n = 1 << rxq_ctrl->rxq.sges_n;
 194         unsigned int elts_n = 1 << rxq_ctrl->rxq.elts_n;
 195         unsigned int i;
 196         int err;
 197
 198         /* Iterate on segments. */
 199         for (i = 0; (i != elts_n); ++i) {
 200                 struct rte_mbuf *buf;
 201
 202                 buf = rte_pktmbuf_alloc(rxq_ctrl->rxq.mp);
 203                 if (buf == NULL) {
 204                         DRV_LOG(ERR, "port %u empty mbuf pool",
 205                                 PORT_ID(rxq_ctrl->priv));
 206                         rte_errno = ENOMEM;
 207                         goto error;
 208                 }
 209                 /* Headroom is reserved by rte_pktmbuf_alloc(). */
 210                 assert(DATA_OFF(buf) == RTE_PKTMBUF_HEADROOM);
 211                 /* Buffer is supposed to be empty. */
 212                 assert(rte_pktmbuf_data_len(buf) == 0);
 213                 assert(rte_pktmbuf_pkt_len(buf) == 0);
 214                 assert(!buf->next);
 215                 /* Only the first segment keeps headroom. */
 216                 if (i % sges_n)
 217                         SET_DATA_OFF(buf, 0);
 218                 PORT(buf) = rxq_ctrl->rxq.port_id;
 219                 DATA_LEN(buf) = rte_pktmbuf_tailroom(buf);
 220                 PKT_LEN(buf) = DATA_LEN(buf);
 221                 NB_SEGS(buf) = 1;
 222                 (*rxq_ctrl->rxq.elts)[i] = buf;
 223         }
 224         /* If Rx vector is activated. */
 225         if (mlx5_rxq_check_vec_support(&rxq_ctrl->rxq) > 0) {
 226                 struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
 227                 struct rte_mbuf *mbuf_init = &rxq->fake_mbuf;
 228                 int j;
 229
 230                 /* Initialize default rearm_data for vPMD. */
 231                 mbuf_init->data_off = RTE_PKTMBUF_HEADROOM;
 232                 rte_mbuf_refcnt_set(mbuf_init, 1);
 233                 mbuf_init->nb_segs = 1;
 234                 mbuf_init->port = rxq->port_id;
 235                 /*
 236                  * prevent compiler reordering:
 237                  * rearm_data covers previous fields.
 238                  */
 239                 rte_compiler_barrier();
 240                 rxq->mbuf_initializer =
 241                         *(uint64_t *)&mbuf_init->rearm_data;
 242                 /* Padding with a fake mbuf for vectorized Rx. */
 243                 for (j = 0; j < MLX5_VPMD_DESCS_PER_LOOP; ++j)
 244                         (*rxq->elts)[elts_n + j] = &rxq->fake_mbuf;
 245         }
 246         DRV_LOG(DEBUG,
 247                 "port %u Rx queue %u allocated and configured %u segments"
 248                 " (max %u packets)",
 249                 PORT_ID(rxq_ctrl->priv), rxq_ctrl->rxq.idx, elts_n,
 250                 elts_n / (1 << rxq_ctrl->rxq.sges_n));
 251         return 0;
 252 error:
 253         err = rte_errno; /* Save rte_errno before cleanup. */
 254         elts_n = i;
 255         for (i = 0; (i != elts_n); ++i) {
 256                 if ((*rxq_ctrl->rxq.elts)[i] != NULL)
 257                         rte_pktmbuf_free_seg((*rxq_ctrl->rxq.elts)[i]);
 258                 (*rxq_ctrl->rxq.elts)[i] = NULL;
 259         }
 260         DRV_LOG(DEBUG, "port %u Rx queue %u failed, freed everything",
 261                 PORT_ID(rxq_ctrl->priv), rxq_ctrl->rxq.idx);
 262         rte_errno = err; /* Restore rte_errno. */
 263         return -rte_errno;
 264 }
 265
 266 /**
 267  * Allocate RX queue elements.
 268  *
 269  * @param rxq_ctrl
 270  *   Pointer to RX queue structure.
 271  *
 272  * @return
 273  *   0 on success, errno value on failure.
 274  */
 275 int
 276 rxq_alloc_elts(struct mlx5_rxq_ctrl *rxq_ctrl)
 277 {
 278         return mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq) ?
 279                rxq_alloc_elts_mprq(rxq_ctrl) : rxq_alloc_elts_sprq(rxq_ctrl);
 280 }
 281
 282 /**
 283  * Free RX queue elements for Multi-Packet RQ.
 284  *
 285  * @param rxq_ctrl
 286  *   Pointer to RX queue structure.
 287  */
 288 static void
 289 rxq_free_elts_mprq(struct mlx5_rxq_ctrl *rxq_ctrl)
 290 {
 291         struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
 292         uint16_t i;
 293
 294         DRV_LOG(DEBUG, "port %u Multi-Packet Rx queue %u freeing WRs",
 295                 rxq->port_id, rxq->idx);
 296         if (rxq->mprq_bufs == NULL)
 297                 return;
 298         assert(mlx5_rxq_check_vec_support(rxq) < 0);
 299         for (i = 0; (i != (1u << rxq->elts_n)); ++i) {
 300                 if ((*rxq->mprq_bufs)[i] != NULL)
 301                         mlx5_mprq_buf_free((*rxq->mprq_bufs)[i]);
 302                 (*rxq->mprq_bufs)[i] = NULL;
 303         }
 304         if (rxq->mprq_repl != NULL) {
 305                 mlx5_mprq_buf_free(rxq->mprq_repl);
 306                 rxq->mprq_repl = NULL;
 307         }
 308 }
 309
 310 /**
 311  * Free RX queue elements for Single-Packet RQ.
 312  *
 313  * @param rxq_ctrl
 314  *   Pointer to RX queue structure.
 315  */
 316 static void
 317 rxq_free_elts_sprq(struct mlx5_rxq_ctrl *rxq_ctrl)
 318 {
 319         struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
 320         const uint16_t q_n = (1 << rxq->elts_n);
 321         const uint16_t q_mask = q_n - 1;
 322         uint16_t used = q_n - (rxq->rq_ci - rxq->rq_pi);
 323         uint16_t i;
 324
 325         DRV_LOG(DEBUG, "port %u Rx queue %u freeing WRs",
 326                 PORT_ID(rxq_ctrl->priv), rxq->idx);
 327         if (rxq->elts == NULL)
 328                 return;
 329         /**
 330          * Some mbuf in the Ring belongs to the application.  They cannot be
 331          * freed.
 332          */
 333         if (mlx5_rxq_check_vec_support(rxq) > 0) {
 334                 for (i = 0; i < used; ++i)
 335                         (*rxq->elts)[(rxq->rq_ci + i) & q_mask] = NULL;
 336                 rxq->rq_pi = rxq->rq_ci;
 337         }
 338         for (i = 0; (i != (1u << rxq->elts_n)); ++i) {
 339                 if ((*rxq->elts)[i] != NULL)
 340                         rte_pktmbuf_free_seg((*rxq->elts)[i]);
 341                 (*rxq->elts)[i] = NULL;
 342         }
 343 }
 344
 345 /**
 346  * Free RX queue elements.
 347  *
 348  * @param rxq_ctrl
 349  *   Pointer to RX queue structure.
 350  */
 351 static void
 352 rxq_free_elts(struct mlx5_rxq_ctrl *rxq_ctrl)
 353 {
 354         if (mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq))
 355                 rxq_free_elts_mprq(rxq_ctrl);
 356         else
 357                 rxq_free_elts_sprq(rxq_ctrl);
 358 }
 359
 360 /**
 361  * Returns the per-queue supported offloads.
 362  *
 363  * @param dev
 364  *   Pointer to Ethernet device.
 365  *
 366  * @return
 367  *   Supported Rx offloads.
 368  */
 369 uint64_t
 370 mlx5_get_rx_queue_offloads(struct rte_eth_dev *dev)
 371 {
 372         struct mlx5_priv *priv = dev->data->dev_private;
 373         struct mlx5_dev_config *config = &priv->config;
 374         uint64_t offloads = (DEV_RX_OFFLOAD_SCATTER |
 375                              DEV_RX_OFFLOAD_TIMESTAMP |
 376                              DEV_RX_OFFLOAD_JUMBO_FRAME |
 377                              DEV_RX_OFFLOAD_RSS_HASH);
 378
 379         if (config->hw_fcs_strip)
 380                 offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
 381
 382         if (config->hw_csum)
 383                 offloads |= (DEV_RX_OFFLOAD_IPV4_CKSUM |
 384                              DEV_RX_OFFLOAD_UDP_CKSUM |
 385                              DEV_RX_OFFLOAD_TCP_CKSUM);
 386         if (config->hw_vlan_strip)
 387                 offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
 388         if (MLX5_LRO_SUPPORTED(dev))
 389                 offloads |= DEV_RX_OFFLOAD_TCP_LRO;
 390         return offloads;
 391 }
 392
 393
 394 /**
 395  * Returns the per-port supported offloads.
 396  *
 397  * @return
 398  *   Supported Rx offloads.
 399  */
 400 uint64_t
 401 mlx5_get_rx_port_offloads(void)
 402 {
 403         uint64_t offloads = DEV_RX_OFFLOAD_VLAN_FILTER;
 404
 405         return offloads;
 406 }
 407
 408 /**
 409  * Verify if the queue can be released.
 410  *
 411  * @param dev
 412  *   Pointer to Ethernet device.
 413  * @param idx
 414  *   RX queue index.
 415  *
 416  * @return
 417  *   1 if the queue can be released
 418  *   0 if the queue can not be released, there are references to it.
 419  *   Negative errno and rte_errno is set if queue doesn't exist.
 420  */
 421 static int
 422 mlx5_rxq_releasable(struct rte_eth_dev *dev, uint16_t idx)
 423 {
 424         struct mlx5_priv *priv = dev->data->dev_private;
 425         struct mlx5_rxq_ctrl *rxq_ctrl;
 426
 427         if (!(*priv->rxqs)[idx]) {
 428                 rte_errno = EINVAL;
 429                 return -rte_errno;
 430         }
 431         rxq_ctrl = container_of((*priv->rxqs)[idx], struct mlx5_rxq_ctrl, rxq);
 432         return (rte_atomic32_read(&rxq_ctrl->refcnt) == 1);
 433 }
 434
 435 /**
 436  * Rx queue presetup checks.
 437  *
 438  * @param dev
 439  *   Pointer to Ethernet device structure.
 440  * @param idx
 441  *   RX queue index.
 442  * @param desc
 443  *   Number of descriptors to configure in queue.
 444  *
 445  * @return
 446  *   0 on success, a negative errno value otherwise and rte_errno is set.
 447  */
 448 static int
 449 mlx5_rx_queue_pre_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc)
 450 {
 451         struct mlx5_priv *priv = dev->data->dev_private;
 452
 453         if (!rte_is_power_of_2(desc)) {
 454                 desc = 1 << log2above(desc);
 455                 DRV_LOG(WARNING,
 456                         "port %u increased number of descriptors in Rx queue %u"
 457                         " to the next power of two (%d)",
 458                         dev->data->port_id, idx, desc);
 459         }
 460         DRV_LOG(DEBUG, "port %u configuring Rx queue %u for %u descriptors",
 461                 dev->data->port_id, idx, desc);
 462         if (idx >= priv->rxqs_n) {
 463                 DRV_LOG(ERR, "port %u Rx queue index out of range (%u >= %u)",
 464                         dev->data->port_id, idx, priv->rxqs_n);
 465                 rte_errno = EOVERFLOW;
 466                 return -rte_errno;
 467         }
 468         if (!mlx5_rxq_releasable(dev, idx)) {
 469                 DRV_LOG(ERR, "port %u unable to release queue index %u",
 470                         dev->data->port_id, idx);
 471                 rte_errno = EBUSY;
 472                 return -rte_errno;
 473         }
 474         mlx5_rxq_release(dev, idx);
 475         return 0;
 476 }
 477
 478 /**
 479  *
 480  * @param dev
 481  *   Pointer to Ethernet device structure.
 482  * @param idx
 483  *   RX queue index.
 484  * @param desc
 485  *   Number of descriptors to configure in queue.
 486  * @param socket
 487  *   NUMA socket on which memory must be allocated.
 488  * @param[in] conf
 489  *   Thresholds parameters.
 490  * @param mp
 491  *   Memory pool for buffer allocations.
 492  *
 493  * @return
 494  *   0 on success, a negative errno value otherwise and rte_errno is set.
 495  */
 496 int
 497 mlx5_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
 498                     unsigned int socket, const struct rte_eth_rxconf *conf,
 499                     struct rte_mempool *mp)
 500 {
 501         struct mlx5_priv *priv = dev->data->dev_private;
 502         struct mlx5_rxq_data *rxq = (*priv->rxqs)[idx];
 503         struct mlx5_rxq_ctrl *rxq_ctrl =
 504                 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
 505         int res;
 506
 507         res = mlx5_rx_queue_pre_setup(dev, idx, desc);
 508         if (res)
 509                 return res;
 510         rxq_ctrl = mlx5_rxq_new(dev, idx, desc, socket, conf, mp);
 511         if (!rxq_ctrl) {
 512                 DRV_LOG(ERR, "port %u unable to allocate queue index %u",
 513                         dev->data->port_id, idx);
 514                 rte_errno = ENOMEM;
 515                 return -rte_errno;
 516         }
 517         DRV_LOG(DEBUG, "port %u adding Rx queue %u to list",
 518                 dev->data->port_id, idx);
 519         (*priv->rxqs)[idx] = &rxq_ctrl->rxq;
 520         return 0;
 521 }
 522
 523 /**
 524  *
 525  * @param dev
 526  *   Pointer to Ethernet device structure.
 527  * @param idx
 528  *   RX queue index.
 529  * @param desc
 530  *   Number of descriptors to configure in queue.
 531  * @param hairpin_conf
 532  *   Hairpin configuration parameters.
 533  *
 534  * @return
 535  *   0 on success, a negative errno value otherwise and rte_errno is set.
 536  */
 537 int
 538 mlx5_rx_hairpin_queue_setup(struct rte_eth_dev *dev, uint16_t idx,
 539                             uint16_t desc,
 540                             const struct rte_eth_hairpin_conf *hairpin_conf)
 541 {
 542         struct mlx5_priv *priv = dev->data->dev_private;
 543         struct mlx5_rxq_data *rxq = (*priv->rxqs)[idx];
 544         struct mlx5_rxq_ctrl *rxq_ctrl =
 545                 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
 546         int res;
 547
 548         res = mlx5_rx_queue_pre_setup(dev, idx, desc);
 549         if (res)
 550                 return res;
 551         if (hairpin_conf->peer_count != 1 ||
 552             hairpin_conf->peers[0].port != dev->data->port_id ||
 553             hairpin_conf->peers[0].queue >= priv->txqs_n) {
 554                 DRV_LOG(ERR, "port %u unable to setup hairpin queue index %u "
 555                         " invalid hairpind configuration", dev->data->port_id,
 556                         idx);
 557                 rte_errno = EINVAL;
 558                 return -rte_errno;
 559         }
 560         rxq_ctrl = mlx5_rxq_hairpin_new(dev, idx, desc, hairpin_conf);
 561         if (!rxq_ctrl) {
 562                 DRV_LOG(ERR, "port %u unable to allocate queue index %u",
 563                         dev->data->port_id, idx);
 564                 rte_errno = ENOMEM;
 565                 return -rte_errno;
 566         }
 567         DRV_LOG(DEBUG, "port %u adding Rx queue %u to list",
 568                 dev->data->port_id, idx);
 569         (*priv->rxqs)[idx] = &rxq_ctrl->rxq;
 570         return 0;
 571 }
 572
 573 /**
 574  * DPDK callback to release a RX queue.
 575  *
 576  * @param dpdk_rxq
 577  *   Generic RX queue pointer.
 578  */
 579 void
 580 mlx5_rx_queue_release(void *dpdk_rxq)
 581 {
 582         struct mlx5_rxq_data *rxq = (struct mlx5_rxq_data *)dpdk_rxq;
 583         struct mlx5_rxq_ctrl *rxq_ctrl;
 584         struct mlx5_priv *priv;
 585
 586         if (rxq == NULL)
 587                 return;
 588         rxq_ctrl = container_of(rxq, struct mlx5_rxq_ctrl, rxq);
 589         priv = rxq_ctrl->priv;
 590         if (!mlx5_rxq_releasable(ETH_DEV(priv), rxq_ctrl->rxq.idx))
 591                 rte_panic("port %u Rx queue %u is still used by a flow and"
 592                           " cannot be removed\n",
 593                           PORT_ID(priv), rxq->idx);
 594         mlx5_rxq_release(ETH_DEV(priv), rxq_ctrl->rxq.idx);
 595 }
 596
 597 /**
 598  * Get an Rx queue Verbs/DevX object.
 599  *
 600  * @param dev
 601  *   Pointer to Ethernet device.
 602  * @param idx
 603  *   Queue index in DPDK Rx queue array
 604  *
 605  * @return
 606  *   The Verbs/DevX object if it exists.
 607  */
 608 static struct mlx5_rxq_obj *
 609 mlx5_rxq_obj_get(struct rte_eth_dev *dev, uint16_t idx)
 610 {
 611         struct mlx5_priv *priv = dev->data->dev_private;
 612         struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
 613         struct mlx5_rxq_ctrl *rxq_ctrl;
 614
 615         if (idx >= priv->rxqs_n)
 616                 return NULL;
 617         if (!rxq_data)
 618                 return NULL;
 619         rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
 620         if (rxq_ctrl->obj)
 621                 rte_atomic32_inc(&rxq_ctrl->obj->refcnt);
 622         return rxq_ctrl->obj;
 623 }
 624
 625 /**
 626  * Release the resources allocated for an RQ DevX object.
 627  *
 628  * @param rxq_ctrl
 629  *   DevX Rx queue object.
 630  */
 631 static void
 632 rxq_release_rq_resources(struct mlx5_rxq_ctrl *rxq_ctrl)
 633 {
 634         if (rxq_ctrl->rxq.wqes) {
 635                 rte_free((void *)(uintptr_t)rxq_ctrl->rxq.wqes);
 636                 rxq_ctrl->rxq.wqes = NULL;
 637         }
 638         if (rxq_ctrl->wq_umem) {
 639                 mlx5_glue->devx_umem_dereg(rxq_ctrl->wq_umem);
 640                 rxq_ctrl->wq_umem = NULL;
 641         }
 642 }
 643
 644 /**
 645  * Release an Rx hairpin related resources.
 646  *
 647  * @param rxq_obj
 648  *   Hairpin Rx queue object.
 649  */
 650 static void
 651 rxq_obj_hairpin_release(struct mlx5_rxq_obj *rxq_obj)
 652 {
 653         struct mlx5_devx_modify_rq_attr rq_attr = { 0 };
 654
 655         assert(rxq_obj);
 656         rq_attr.state = MLX5_RQC_STATE_RST;
 657         rq_attr.rq_state = MLX5_RQC_STATE_RDY;
 658         mlx5_devx_cmd_modify_rq(rxq_obj->rq, &rq_attr);
 659         claim_zero(mlx5_devx_cmd_destroy(rxq_obj->rq));
 660 }
 661
 662 /**
 663  * Release an Rx verbs/DevX queue object.
 664  *
 665  * @param rxq_obj
 666  *   Verbs/DevX Rx queue object.
 667  *
 668  * @return
 669  *   1 while a reference on it exists, 0 when freed.
 670  */
 671 static int
 672 mlx5_rxq_obj_release(struct mlx5_rxq_obj *rxq_obj)
 673 {
 674         assert(rxq_obj);
 675         if (rte_atomic32_dec_and_test(&rxq_obj->refcnt)) {
 676                 switch (rxq_obj->type) {
 677                 case MLX5_RXQ_OBJ_TYPE_IBV:
 678                         assert(rxq_obj->wq);
 679                         assert(rxq_obj->cq);
 680                         rxq_free_elts(rxq_obj->rxq_ctrl);
 681                         claim_zero(mlx5_glue->destroy_wq(rxq_obj->wq));
 682                         claim_zero(mlx5_glue->destroy_cq(rxq_obj->cq));
 683                         break;
 684                 case MLX5_RXQ_OBJ_TYPE_DEVX_RQ:
 685                         assert(rxq_obj->cq);
 686                         assert(rxq_obj->rq);
 687                         rxq_free_elts(rxq_obj->rxq_ctrl);
 688                         claim_zero(mlx5_devx_cmd_destroy(rxq_obj->rq));
 689                         rxq_release_rq_resources(rxq_obj->rxq_ctrl);
 690                         claim_zero(mlx5_glue->destroy_cq(rxq_obj->cq));
 691                         break;
 692                 case MLX5_RXQ_OBJ_TYPE_DEVX_HAIRPIN:
 693                         assert(rxq_obj->rq);
 694                         rxq_obj_hairpin_release(rxq_obj);
 695                         break;
 696                 }
 697                 if (rxq_obj->channel)
 698                         claim_zero(mlx5_glue->destroy_comp_channel
 699                                    (rxq_obj->channel));
 700                 LIST_REMOVE(rxq_obj, next);
 701                 rte_free(rxq_obj);
 702                 return 0;
 703         }
 704         return 1;
 705 }
 706
 707 /**
 708  * Allocate queue vector and fill epoll fd list for Rx interrupts.
 709  *
 710  * @param dev
 711  *   Pointer to Ethernet device.
 712  *
 713  * @return
 714  *   0 on success, a negative errno value otherwise and rte_errno is set.
 715  */
 716 int
 717 mlx5_rx_intr_vec_enable(struct rte_eth_dev *dev)
 718 {
 719         struct mlx5_priv *priv = dev->data->dev_private;
 720         unsigned int i;
 721         unsigned int rxqs_n = priv->rxqs_n;
 722         unsigned int n = RTE_MIN(rxqs_n, (uint32_t)RTE_MAX_RXTX_INTR_VEC_ID);
 723         unsigned int count = 0;
 724         struct rte_intr_handle *intr_handle = dev->intr_handle;
 725
 726         if (!dev->data->dev_conf.intr_conf.rxq)
 727                 return 0;
 728         mlx5_rx_intr_vec_disable(dev);
 729         intr_handle->intr_vec = malloc(n * sizeof(intr_handle->intr_vec[0]));
 730         if (intr_handle->intr_vec == NULL) {
 731                 DRV_LOG(ERR,
 732                         "port %u failed to allocate memory for interrupt"
 733                         " vector, Rx interrupts will not be supported",
 734                         dev->data->port_id);
 735                 rte_errno = ENOMEM;
 736                 return -rte_errno;
 737         }
 738         intr_handle->type = RTE_INTR_HANDLE_EXT;
 739         for (i = 0; i != n; ++i) {
 740                 /* This rxq obj must not be released in this function. */
 741                 struct mlx5_rxq_obj *rxq_obj = mlx5_rxq_obj_get(dev, i);
 742                 int fd;
 743                 int flags;
 744                 int rc;
 745
 746                 /* Skip queues that cannot request interrupts. */
 747                 if (!rxq_obj || !rxq_obj->channel) {
 748                         /* Use invalid intr_vec[] index to disable entry. */
 749                         intr_handle->intr_vec[i] =
 750                                 RTE_INTR_VEC_RXTX_OFFSET +
 751                                 RTE_MAX_RXTX_INTR_VEC_ID;
 752                         continue;
 753                 }
 754                 if (count >= RTE_MAX_RXTX_INTR_VEC_ID) {
 755                         DRV_LOG(ERR,
 756                                 "port %u too many Rx queues for interrupt"
 757                                 " vector size (%d), Rx interrupts cannot be"
 758                                 " enabled",
 759                                 dev->data->port_id, RTE_MAX_RXTX_INTR_VEC_ID);
 760                         mlx5_rx_intr_vec_disable(dev);
 761                         rte_errno = ENOMEM;
 762                         return -rte_errno;
 763                 }
 764                 fd = rxq_obj->channel->fd;
 765                 flags = fcntl(fd, F_GETFL);
 766                 rc = fcntl(fd, F_SETFL, flags | O_NONBLOCK);
 767                 if (rc < 0) {
 768                         rte_errno = errno;
 769                         DRV_LOG(ERR,
 770                                 "port %u failed to make Rx interrupt file"
 771                                 " descriptor %d non-blocking for queue index"
 772                                 " %d",
 773                                 dev->data->port_id, fd, i);
 774                         mlx5_rx_intr_vec_disable(dev);
 775                         return -rte_errno;
 776                 }
 777                 intr_handle->intr_vec[i] = RTE_INTR_VEC_RXTX_OFFSET + count;
 778                 intr_handle->efds[count] = fd;
 779                 count++;
 780         }
 781         if (!count)
 782                 mlx5_rx_intr_vec_disable(dev);
 783         else
 784                 intr_handle->nb_efd = count;
 785         return 0;
 786 }
 787
 788 /**
 789  * Clean up Rx interrupts handler.
 790  *
 791  * @param dev
 792  *   Pointer to Ethernet device.
 793  */
 794 void
 795 mlx5_rx_intr_vec_disable(struct rte_eth_dev *dev)
 796 {
 797         struct mlx5_priv *priv = dev->data->dev_private;
 798         struct rte_intr_handle *intr_handle = dev->intr_handle;
 799         unsigned int i;
 800         unsigned int rxqs_n = priv->rxqs_n;
 801         unsigned int n = RTE_MIN(rxqs_n, (uint32_t)RTE_MAX_RXTX_INTR_VEC_ID);
 802
 803         if (!dev->data->dev_conf.intr_conf.rxq)
 804                 return;
 805         if (!intr_handle->intr_vec)
 806                 goto free;
 807         for (i = 0; i != n; ++i) {
 808                 struct mlx5_rxq_ctrl *rxq_ctrl;
 809                 struct mlx5_rxq_data *rxq_data;
 810
 811                 if (intr_handle->intr_vec[i] == RTE_INTR_VEC_RXTX_OFFSET +
 812                     RTE_MAX_RXTX_INTR_VEC_ID)
 813                         continue;
 814                 /**
 815                  * Need to access directly the queue to release the reference
 816                  * kept in mlx5_rx_intr_vec_enable().
 817                  */
 818                 rxq_data = (*priv->rxqs)[i];
 819                 rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
 820                 if (rxq_ctrl->obj)
 821                         mlx5_rxq_obj_release(rxq_ctrl->obj);
 822         }
 823 free:
 824         rte_intr_free_epoll_fd(intr_handle);
 825         if (intr_handle->intr_vec)
 826                 free(intr_handle->intr_vec);
 827         intr_handle->nb_efd = 0;
 828         intr_handle->intr_vec = NULL;
 829 }
 830
 831 /**
 832  *  MLX5 CQ notification .
 833  *
 834  *  @param rxq
 835  *     Pointer to receive queue structure.
 836  *  @param sq_n_rxq
 837  *     Sequence number per receive queue .
 838  */
 839 static inline void
 840 mlx5_arm_cq(struct mlx5_rxq_data *rxq, int sq_n_rxq)
 841 {
 842         int sq_n = 0;
 843         uint32_t doorbell_hi;
 844         uint64_t doorbell;
 845         void *cq_db_reg = (char *)rxq->cq_uar + MLX5_CQ_DOORBELL;
 846
 847         sq_n = sq_n_rxq & MLX5_CQ_SQN_MASK;
 848         doorbell_hi = sq_n << MLX5_CQ_SQN_OFFSET | (rxq->cq_ci & MLX5_CI_MASK);
 849         doorbell = (uint64_t)doorbell_hi << 32;
 850         doorbell |=  rxq->cqn;
 851         rxq->cq_db[MLX5_CQ_ARM_DB] = rte_cpu_to_be_32(doorbell_hi);
 852         mlx5_uar_write64(rte_cpu_to_be_64(doorbell),
 853                          cq_db_reg, rxq->uar_lock_cq);
 854 }
 855
 856 /**
 857  * DPDK callback for Rx queue interrupt enable.
 858  *
 859  * @param dev
 860  *   Pointer to Ethernet device structure.
 861  * @param rx_queue_id
 862  *   Rx queue number.
 863  *
 864  * @return
 865  *   0 on success, a negative errno value otherwise and rte_errno is set.
 866  */
 867 int
 868 mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 869 {
 870         struct mlx5_priv *priv = dev->data->dev_private;
 871         struct mlx5_rxq_data *rxq_data;
 872         struct mlx5_rxq_ctrl *rxq_ctrl;
 873
 874         rxq_data = (*priv->rxqs)[rx_queue_id];
 875         if (!rxq_data) {
 876                 rte_errno = EINVAL;
 877                 return -rte_errno;
 878         }
 879         rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
 880         if (rxq_ctrl->irq) {
 881                 struct mlx5_rxq_obj *rxq_obj;
 882
 883                 rxq_obj = mlx5_rxq_obj_get(dev, rx_queue_id);
 884                 if (!rxq_obj) {
 885                         rte_errno = EINVAL;
 886                         return -rte_errno;
 887                 }
 888                 mlx5_arm_cq(rxq_data, rxq_data->cq_arm_sn);
 889                 mlx5_rxq_obj_release(rxq_obj);
 890         }
 891         return 0;
 892 }
 893
 894 /**
 895  * DPDK callback for Rx queue interrupt disable.
 896  *
 897  * @param dev
 898  *   Pointer to Ethernet device structure.
 899  * @param rx_queue_id
 900  *   Rx queue number.
 901  *
 902  * @return
 903  *   0 on success, a negative errno value otherwise and rte_errno is set.
 904  */
 905 int
 906 mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 907 {
 908         struct mlx5_priv *priv = dev->data->dev_private;
 909         struct mlx5_rxq_data *rxq_data;
 910         struct mlx5_rxq_ctrl *rxq_ctrl;
 911         struct mlx5_rxq_obj *rxq_obj = NULL;
 912         struct ibv_cq *ev_cq;
 913         void *ev_ctx;
 914         int ret;
 915
 916         rxq_data = (*priv->rxqs)[rx_queue_id];
 917         if (!rxq_data) {
 918                 rte_errno = EINVAL;
 919                 return -rte_errno;
 920         }
 921         rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
 922         if (!rxq_ctrl->irq)
 923                 return 0;
 924         rxq_obj = mlx5_rxq_obj_get(dev, rx_queue_id);
 925         if (!rxq_obj) {
 926                 rte_errno = EINVAL;
 927                 return -rte_errno;
 928         }
 929         ret = mlx5_glue->get_cq_event(rxq_obj->channel, &ev_cq, &ev_ctx);
 930         if (ret || ev_cq != rxq_obj->cq) {
 931                 rte_errno = EINVAL;
 932                 goto exit;
 933         }
 934         rxq_data->cq_arm_sn++;
 935         mlx5_glue->ack_cq_events(rxq_obj->cq, 1);
 936         mlx5_rxq_obj_release(rxq_obj);
 937         return 0;
 938 exit:
 939         ret = rte_errno; /* Save rte_errno before cleanup. */
 940         if (rxq_obj)
 941                 mlx5_rxq_obj_release(rxq_obj);
 942         DRV_LOG(WARNING, "port %u unable to disable interrupt on Rx queue %d",
 943                 dev->data->port_id, rx_queue_id);
 944         rte_errno = ret; /* Restore rte_errno. */
 945         return -rte_errno;
 946 }
 947
 948 /**
 949  * Create a CQ Verbs object.
 950  *
 951  * @param dev
 952  *   Pointer to Ethernet device.
 953  * @param priv
 954  *   Pointer to device private data.
 955  * @param rxq_data
 956  *   Pointer to Rx queue data.
 957  * @param cqe_n
 958  *   Number of CQEs in CQ.
 959  * @param rxq_obj
 960  *   Pointer to Rx queue object data.
 961  *
 962  * @return
 963  *   The Verbs object initialised, NULL otherwise and rte_errno is set.
 964  */
 965 static struct ibv_cq *
 966 mlx5_ibv_cq_new(struct rte_eth_dev *dev, struct mlx5_priv *priv,
 967                 struct mlx5_rxq_data *rxq_data,
 968                 unsigned int cqe_n, struct mlx5_rxq_obj *rxq_obj)
 969 {
 970         struct {
 971                 struct ibv_cq_init_attr_ex ibv;
 972                 struct mlx5dv_cq_init_attr mlx5;
 973         } cq_attr;
 974
 975         cq_attr.ibv = (struct ibv_cq_init_attr_ex){
 976                 .cqe = cqe_n,
 977                 .channel = rxq_obj->channel,
 978                 .comp_mask = 0,
 979         };
 980         cq_attr.mlx5 = (struct mlx5dv_cq_init_attr){
 981                 .comp_mask = 0,
 982         };
 983         if (priv->config.cqe_comp && !rxq_data->hw_timestamp &&
 984             !rxq_data->lro) {
 985                 cq_attr.mlx5.comp_mask |=
 986                                 MLX5DV_CQ_INIT_ATTR_MASK_COMPRESSED_CQE;
 987 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
 988                 cq_attr.mlx5.cqe_comp_res_format =
 989                                 mlx5_rxq_mprq_enabled(rxq_data) ?
 990                                 MLX5DV_CQE_RES_FORMAT_CSUM_STRIDX :
 991                                 MLX5DV_CQE_RES_FORMAT_HASH;
 992 #else
 993                 cq_attr.mlx5.cqe_comp_res_format = MLX5DV_CQE_RES_FORMAT_HASH;
 994 #endif
 995                 /*
 996                  * For vectorized Rx, it must not be doubled in order to
 997                  * make cq_ci and rq_ci aligned.
 998                  */
 999                 if (mlx5_rxq_check_vec_support(rxq_data) < 0)
1000                         cq_attr.ibv.cqe *= 2;
1001         } else if (priv->config.cqe_comp && rxq_data->hw_timestamp) {
1002                 DRV_LOG(DEBUG,
1003                         "port %u Rx CQE compression is disabled for HW"
1004                         " timestamp",
1005                         dev->data->port_id);
1006         } else if (priv->config.cqe_comp && rxq_data->lro) {
1007                 DRV_LOG(DEBUG,
1008                         "port %u Rx CQE compression is disabled for LRO",
1009                         dev->data->port_id);
1010         }
1011 #ifdef HAVE_IBV_MLX5_MOD_CQE_128B_PAD
1012         if (priv->config.cqe_pad) {
1013                 cq_attr.mlx5.comp_mask |= MLX5DV_CQ_INIT_ATTR_MASK_FLAGS;
1014                 cq_attr.mlx5.flags |= MLX5DV_CQ_INIT_ATTR_FLAGS_CQE_PAD;
1015         }
1016 #endif
1017         return mlx5_glue->cq_ex_to_cq(mlx5_glue->dv_create_cq(priv->sh->ctx,
1018                                                               &cq_attr.ibv,
1019                                                               &cq_attr.mlx5));
1020 }
1021
1022 /**
1023  * Create a WQ Verbs object.
1024  *
1025  * @param dev
1026  *   Pointer to Ethernet device.
1027  * @param priv
1028  *   Pointer to device private data.
1029  * @param rxq_data
1030  *   Pointer to Rx queue data.
1031  * @param idx
1032  *   Queue index in DPDK Rx queue array
1033  * @param wqe_n
1034  *   Number of WQEs in WQ.
1035  * @param rxq_obj
1036  *   Pointer to Rx queue object data.
1037  *
1038  * @return
1039  *   The Verbs object initialised, NULL otherwise and rte_errno is set.
1040  */
1041 static struct ibv_wq *
1042 mlx5_ibv_wq_new(struct rte_eth_dev *dev, struct mlx5_priv *priv,
1043                 struct mlx5_rxq_data *rxq_data, uint16_t idx,
1044                 unsigned int wqe_n, struct mlx5_rxq_obj *rxq_obj)
1045 {
1046         struct {
1047                 struct ibv_wq_init_attr ibv;
1048 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
1049                 struct mlx5dv_wq_init_attr mlx5;
1050 #endif
1051         } wq_attr;
1052
1053         wq_attr.ibv = (struct ibv_wq_init_attr){
1054                 .wq_context = NULL, /* Could be useful in the future. */
1055                 .wq_type = IBV_WQT_RQ,
1056                 /* Max number of outstanding WRs. */
1057                 .max_wr = wqe_n >> rxq_data->sges_n,
1058                 /* Max number of scatter/gather elements in a WR. */
1059                 .max_sge = 1 << rxq_data->sges_n,
1060                 .pd = priv->sh->pd,
1061                 .cq = rxq_obj->cq,
1062                 .comp_mask = IBV_WQ_FLAGS_CVLAN_STRIPPING | 0,
1063                 .create_flags = (rxq_data->vlan_strip ?
1064                                  IBV_WQ_FLAGS_CVLAN_STRIPPING : 0),
1065         };
1066         /* By default, FCS (CRC) is stripped by hardware. */
1067         if (rxq_data->crc_present) {
1068                 wq_attr.ibv.create_flags |= IBV_WQ_FLAGS_SCATTER_FCS;
1069                 wq_attr.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
1070         }
1071         if (priv->config.hw_padding) {
1072 #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING)
1073                 wq_attr.ibv.create_flags |= IBV_WQ_FLAG_RX_END_PADDING;
1074                 wq_attr.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
1075 #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING)
1076                 wq_attr.ibv.create_flags |= IBV_WQ_FLAGS_PCI_WRITE_END_PADDING;
1077                 wq_attr.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
1078 #endif
1079         }
1080 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
1081         wq_attr.mlx5 = (struct mlx5dv_wq_init_attr){
1082                 .comp_mask = 0,
1083         };
1084         if (mlx5_rxq_mprq_enabled(rxq_data)) {
1085                 struct mlx5dv_striding_rq_init_attr *mprq_attr =
1086                                                 &wq_attr.mlx5.striding_rq_attrs;
1087
1088                 wq_attr.mlx5.comp_mask |= MLX5DV_WQ_INIT_ATTR_MASK_STRIDING_RQ;
1089                 *mprq_attr = (struct mlx5dv_striding_rq_init_attr){
1090                         .single_stride_log_num_of_bytes = rxq_data->strd_sz_n,
1091                         .single_wqe_log_num_of_strides = rxq_data->strd_num_n,
1092                         .two_byte_shift_en = MLX5_MPRQ_TWO_BYTE_SHIFT,
1093                 };
1094         }
1095         rxq_obj->wq = mlx5_glue->dv_create_wq(priv->sh->ctx, &wq_attr.ibv,
1096                                               &wq_attr.mlx5);
1097 #else
1098         rxq_obj->wq = mlx5_glue->create_wq(priv->sh->ctx, &wq_attr.ibv);
1099 #endif
1100         if (rxq_obj->wq) {
1101                 /*
1102                  * Make sure number of WRs*SGEs match expectations since a queue
1103                  * cannot allocate more than "desc" buffers.
1104                  */
1105                 if (wq_attr.ibv.max_wr != (wqe_n >> rxq_data->sges_n) ||
1106                     wq_attr.ibv.max_sge != (1u << rxq_data->sges_n)) {
1107                         DRV_LOG(ERR,
1108                                 "port %u Rx queue %u requested %u*%u but got"
1109                                 " %u*%u WRs*SGEs",
1110                                 dev->data->port_id, idx,
1111                                 wqe_n >> rxq_data->sges_n,
1112                                 (1 << rxq_data->sges_n),
1113                                 wq_attr.ibv.max_wr, wq_attr.ibv.max_sge);
1114                         claim_zero(mlx5_glue->destroy_wq(rxq_obj->wq));
1115                         rxq_obj->wq = NULL;
1116                         rte_errno = EINVAL;
1117                 }
1118         }
1119         return rxq_obj->wq;
1120 }
1121
1122 /**
1123  * Fill common fields of create RQ attributes structure.
1124  *
1125  * @param rxq_data
1126  *   Pointer to Rx queue data.
1127  * @param cqn
1128  *   CQ number to use with this RQ.
1129  * @param rq_attr
1130  *   RQ attributes structure to fill..
1131  */
1132 static void
1133 mlx5_devx_create_rq_attr_fill(struct mlx5_rxq_data *rxq_data, uint32_t cqn,
1134                               struct mlx5_devx_create_rq_attr *rq_attr)
1135 {
1136         rq_attr->state = MLX5_RQC_STATE_RST;
1137         rq_attr->vsd = (rxq_data->vlan_strip) ? 0 : 1;
1138         rq_attr->cqn = cqn;
1139         rq_attr->scatter_fcs = (rxq_data->crc_present) ? 1 : 0;
1140 }
1141
1142 /**
1143  * Fill common fields of DevX WQ attributes structure.
1144  *
1145  * @param priv
1146  *   Pointer to device private data.
1147  * @param rxq_ctrl
1148  *   Pointer to Rx queue control structure.
1149  * @param wq_attr
1150  *   WQ attributes structure to fill..
1151  */
1152 static void
1153 mlx5_devx_wq_attr_fill(struct mlx5_priv *priv, struct mlx5_rxq_ctrl *rxq_ctrl,
1154                        struct mlx5_devx_wq_attr *wq_attr)
1155 {
1156         wq_attr->end_padding_mode = priv->config.cqe_pad ?
1157                                         MLX5_WQ_END_PAD_MODE_ALIGN :
1158                                         MLX5_WQ_END_PAD_MODE_NONE;
1159         wq_attr->pd = priv->sh->pdn;
1160         wq_attr->dbr_addr = rxq_ctrl->dbr_offset;
1161         wq_attr->dbr_umem_id = rxq_ctrl->dbr_umem_id;
1162         wq_attr->dbr_umem_valid = 1;
1163         wq_attr->wq_umem_id = rxq_ctrl->wq_umem->umem_id;
1164         wq_attr->wq_umem_valid = 1;
1165 }
1166
1167 /**
1168  * Create a RQ object using DevX.
1169  *
1170  * @param dev
1171  *   Pointer to Ethernet device.
1172  * @param idx
1173  *   Queue index in DPDK Rx queue array
1174  * @param cqn
1175  *   CQ number to use with this RQ.
1176  *
1177  * @return
1178  *   The DevX object initialised, NULL otherwise and rte_errno is set.
1179  */
1180 static struct mlx5_devx_obj *
1181 mlx5_devx_rq_new(struct rte_eth_dev *dev, uint16_t idx, uint32_t cqn)
1182 {
1183         struct mlx5_priv *priv = dev->data->dev_private;
1184         struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
1185         struct mlx5_rxq_ctrl *rxq_ctrl =
1186                 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
1187         struct mlx5_devx_create_rq_attr rq_attr;
1188         uint32_t wqe_n = 1 << (rxq_data->elts_n - rxq_data->sges_n);
1189         uint32_t wq_size = 0;
1190         uint32_t wqe_size = 0;
1191         uint32_t log_wqe_size = 0;
1192         void *buf = NULL;
1193         struct mlx5_devx_obj *rq;
1194
1195         memset(&rq_attr, 0, sizeof(rq_attr));
1196         /* Fill RQ attributes. */
1197         rq_attr.mem_rq_type = MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE;
1198         rq_attr.flush_in_error_en = 1;
1199         mlx5_devx_create_rq_attr_fill(rxq_data, cqn, &rq_attr);
1200         /* Fill WQ attributes for this RQ. */
1201         if (mlx5_rxq_mprq_enabled(rxq_data)) {
1202                 rq_attr.wq_attr.wq_type = MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ;
1203                 /*
1204                  * Number of strides in each WQE:
1205                  * 512*2^single_wqe_log_num_of_strides.
1206                  */
1207                 rq_attr.wq_attr.single_wqe_log_num_of_strides =
1208                                 rxq_data->strd_num_n -
1209                                 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1210                 /* Stride size = (2^single_stride_log_num_of_bytes)*64B. */
1211                 rq_attr.wq_attr.single_stride_log_num_of_bytes =
1212                                 rxq_data->strd_sz_n -
1213                                 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
1214                 wqe_size = sizeof(struct mlx5_wqe_mprq);
1215         } else {
1216                 rq_attr.wq_attr.wq_type = MLX5_WQ_TYPE_CYCLIC;
1217                 wqe_size = sizeof(struct mlx5_wqe_data_seg);
1218         }
1219         log_wqe_size = log2above(wqe_size) + rxq_data->sges_n;
1220         rq_attr.wq_attr.log_wq_stride = log_wqe_size;
1221         rq_attr.wq_attr.log_wq_sz = rxq_data->elts_n - rxq_data->sges_n;
1222         /* Calculate and allocate WQ memory space. */
1223         wqe_size = 1 << log_wqe_size; /* round up power of two.*/
1224         wq_size = wqe_n * wqe_size;
1225         buf = rte_calloc_socket(__func__, 1, wq_size, MLX5_WQE_BUF_ALIGNMENT,
1226                                 rxq_ctrl->socket);
1227         if (!buf)
1228                 return NULL;
1229         rxq_data->wqes = buf;
1230         rxq_ctrl->wq_umem = mlx5_glue->devx_umem_reg(priv->sh->ctx,
1231                                                      buf, wq_size, 0);
1232         if (!rxq_ctrl->wq_umem) {
1233                 rte_free(buf);
1234                 return NULL;
1235         }
1236         mlx5_devx_wq_attr_fill(priv, rxq_ctrl, &rq_attr.wq_attr);
1237         rq = mlx5_devx_cmd_create_rq(priv->sh->ctx, &rq_attr, rxq_ctrl->socket);
1238         if (!rq)
1239                 rxq_release_rq_resources(rxq_ctrl);
1240         return rq;
1241 }
1242
1243 /**
1244  * Create the Rx hairpin queue object.
1245  *
1246  * @param dev
1247  *   Pointer to Ethernet device.
1248  * @param idx
1249  *   Queue index in DPDK Rx queue array
1250  *
1251  * @return
1252  *   The hairpin DevX object initialised, NULL otherwise and rte_errno is set.
1253  */
1254 static struct mlx5_rxq_obj *
1255 mlx5_rxq_obj_hairpin_new(struct rte_eth_dev *dev, uint16_t idx)
1256 {
1257         struct mlx5_priv *priv = dev->data->dev_private;
1258         struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
1259         struct mlx5_rxq_ctrl *rxq_ctrl =
1260                 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
1261         struct mlx5_devx_create_rq_attr attr = { 0 };
1262         struct mlx5_rxq_obj *tmpl = NULL;
1263         int ret = 0;
1264
1265         assert(rxq_data);
1266         assert(!rxq_ctrl->obj);
1267         tmpl = rte_calloc_socket(__func__, 1, sizeof(*tmpl), 0,
1268                                  rxq_ctrl->socket);
1269         if (!tmpl) {
1270                 DRV_LOG(ERR,
1271                         "port %u Rx queue %u cannot allocate verbs resources",
1272                         dev->data->port_id, rxq_data->idx);
1273                 rte_errno = ENOMEM;
1274                 goto error;
1275         }
1276         tmpl->type = MLX5_RXQ_OBJ_TYPE_DEVX_HAIRPIN;
1277         tmpl->rxq_ctrl = rxq_ctrl;
1278         attr.hairpin = 1;
1279         /* Workaround for hairpin startup */
1280         attr.wq_attr.log_hairpin_num_packets = log2above(32);
1281         /* Workaround for packets larger than 1KB */
1282         attr.wq_attr.log_hairpin_data_sz =
1283                         priv->config.hca_attr.log_max_hairpin_wq_data_sz;
1284         tmpl->rq = mlx5_devx_cmd_create_rq(priv->sh->ctx, &attr,
1285                                            rxq_ctrl->socket);
1286         if (!tmpl->rq) {
1287                 DRV_LOG(ERR,
1288                         "port %u Rx hairpin queue %u can't create rq object",
1289                         dev->data->port_id, idx);
1290                 rte_errno = errno;
1291                 goto error;
1292         }
1293         DRV_LOG(DEBUG, "port %u rxq %u updated with %p", dev->data->port_id,
1294                 idx, (void *)&tmpl);
1295         rte_atomic32_inc(&tmpl->refcnt);
1296         LIST_INSERT_HEAD(&priv->rxqsobj, tmpl, next);
1297         priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
1298         return tmpl;
1299 error:
1300         ret = rte_errno; /* Save rte_errno before cleanup. */
1301         if (tmpl->rq)
1302                 mlx5_devx_cmd_destroy(tmpl->rq);
1303         rte_errno = ret; /* Restore rte_errno. */
1304         return NULL;
1305 }
1306
1307 /**
1308  * Create the Rx queue Verbs/DevX object.
1309  *
1310  * @param dev
1311  *   Pointer to Ethernet device.
1312  * @param idx
1313  *   Queue index in DPDK Rx queue array
1314  * @param type
1315  *   Type of Rx queue object to create.
1316  *
1317  * @return
1318  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
1319  */
1320 struct mlx5_rxq_obj *
1321 mlx5_rxq_obj_new(struct rte_eth_dev *dev, uint16_t idx,
1322                  enum mlx5_rxq_obj_type type)
1323 {
1324         struct mlx5_priv *priv = dev->data->dev_private;
1325         struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
1326         struct mlx5_rxq_ctrl *rxq_ctrl =
1327                 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
1328         struct ibv_wq_attr mod;
1329         unsigned int cqe_n;
1330         unsigned int wqe_n = 1 << rxq_data->elts_n;
1331         struct mlx5_rxq_obj *tmpl = NULL;
1332         struct mlx5dv_cq cq_info;
1333         struct mlx5dv_rwq rwq;
1334         int ret = 0;
1335         struct mlx5dv_obj obj;
1336
1337         assert(rxq_data);
1338         assert(!rxq_ctrl->obj);
1339         if (type == MLX5_RXQ_OBJ_TYPE_DEVX_HAIRPIN)
1340                 return mlx5_rxq_obj_hairpin_new(dev, idx);
1341         priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_RX_QUEUE;
1342         priv->verbs_alloc_ctx.obj = rxq_ctrl;
1343         tmpl = rte_calloc_socket(__func__, 1, sizeof(*tmpl), 0,
1344                                  rxq_ctrl->socket);
1345         if (!tmpl) {
1346                 DRV_LOG(ERR,
1347                         "port %u Rx queue %u cannot allocate verbs resources",
1348                         dev->data->port_id, rxq_data->idx);
1349                 rte_errno = ENOMEM;
1350                 goto error;
1351         }
1352         tmpl->type = type;
1353         tmpl->rxq_ctrl = rxq_ctrl;
1354         if (rxq_ctrl->irq) {
1355                 tmpl->channel = mlx5_glue->create_comp_channel(priv->sh->ctx);
1356                 if (!tmpl->channel) {
1357                         DRV_LOG(ERR, "port %u: comp channel creation failure",
1358                                 dev->data->port_id);
1359                         rte_errno = ENOMEM;
1360                         goto error;
1361                 }
1362         }
1363         if (mlx5_rxq_mprq_enabled(rxq_data))
1364                 cqe_n = wqe_n * (1 << rxq_data->strd_num_n) - 1;
1365         else
1366                 cqe_n = wqe_n  - 1;
1367         tmpl->cq = mlx5_ibv_cq_new(dev, priv, rxq_data, cqe_n, tmpl);
1368         if (!tmpl->cq) {
1369                 DRV_LOG(ERR, "port %u Rx queue %u CQ creation failure",
1370                         dev->data->port_id, idx);
1371                 rte_errno = ENOMEM;
1372                 goto error;
1373         }
1374         obj.cq.in = tmpl->cq;
1375         obj.cq.out = &cq_info;
1376         ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_CQ);
1377         if (ret) {
1378                 rte_errno = ret;
1379                 goto error;
1380         }
1381         if (cq_info.cqe_size != RTE_CACHE_LINE_SIZE) {
1382                 DRV_LOG(ERR,
1383                         "port %u wrong MLX5_CQE_SIZE environment variable"
1384                         " value: it should be set to %u",
1385                         dev->data->port_id, RTE_CACHE_LINE_SIZE);
1386                 rte_errno = EINVAL;
1387                 goto error;
1388         }
1389         DRV_LOG(DEBUG, "port %u device_attr.max_qp_wr is %d",
1390                 dev->data->port_id, priv->sh->device_attr.orig_attr.max_qp_wr);
1391         DRV_LOG(DEBUG, "port %u device_attr.max_sge is %d",
1392                 dev->data->port_id, priv->sh->device_attr.orig_attr.max_sge);
1393         /* Allocate door-bell for types created with DevX. */
1394         if (tmpl->type != MLX5_RXQ_OBJ_TYPE_IBV) {
1395                 struct mlx5_devx_dbr_page *dbr_page;
1396                 int64_t dbr_offset;
1397
1398                 dbr_offset = mlx5_get_dbr(dev, &dbr_page);
1399                 if (dbr_offset < 0)
1400                         goto error;
1401                 rxq_ctrl->dbr_offset = dbr_offset;
1402                 rxq_ctrl->dbr_umem_id = dbr_page->umem->umem_id;
1403                 rxq_ctrl->dbr_umem_id_valid = 1;
1404                 rxq_data->rq_db = (uint32_t *)((uintptr_t)dbr_page->dbrs +
1405                                                (uintptr_t)rxq_ctrl->dbr_offset);
1406         }
1407         if (tmpl->type == MLX5_RXQ_OBJ_TYPE_IBV) {
1408                 tmpl->wq = mlx5_ibv_wq_new(dev, priv, rxq_data, idx, wqe_n,
1409                                            tmpl);
1410                 if (!tmpl->wq) {
1411                         DRV_LOG(ERR, "port %u Rx queue %u WQ creation failure",
1412                                 dev->data->port_id, idx);
1413                         rte_errno = ENOMEM;
1414                         goto error;
1415                 }
1416                 /* Change queue state to ready. */
1417                 mod = (struct ibv_wq_attr){
1418                         .attr_mask = IBV_WQ_ATTR_STATE,
1419                         .wq_state = IBV_WQS_RDY,
1420                 };
1421                 ret = mlx5_glue->modify_wq(tmpl->wq, &mod);
1422                 if (ret) {
1423                         DRV_LOG(ERR,
1424                                 "port %u Rx queue %u WQ state to IBV_WQS_RDY"
1425                                 " failed", dev->data->port_id, idx);
1426                         rte_errno = ret;
1427                         goto error;
1428                 }
1429                 obj.rwq.in = tmpl->wq;
1430                 obj.rwq.out = &rwq;
1431                 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_RWQ);
1432                 if (ret) {
1433                         rte_errno = ret;
1434                         goto error;
1435                 }
1436                 rxq_data->wqes = rwq.buf;
1437                 rxq_data->rq_db = rwq.dbrec;
1438         } else if (tmpl->type == MLX5_RXQ_OBJ_TYPE_DEVX_RQ) {
1439                 struct mlx5_devx_modify_rq_attr rq_attr;
1440
1441                 memset(&rq_attr, 0, sizeof(rq_attr));
1442                 tmpl->rq = mlx5_devx_rq_new(dev, idx, cq_info.cqn);
1443                 if (!tmpl->rq) {
1444                         DRV_LOG(ERR, "port %u Rx queue %u RQ creation failure",
1445                                 dev->data->port_id, idx);
1446                         rte_errno = ENOMEM;
1447                         goto error;
1448                 }
1449                 /* Change queue state to ready. */
1450                 rq_attr.rq_state = MLX5_RQC_STATE_RST;
1451                 rq_attr.state = MLX5_RQC_STATE_RDY;
1452                 ret = mlx5_devx_cmd_modify_rq(tmpl->rq, &rq_attr);
1453                 if (ret)
1454                         goto error;
1455         }
1456         /* Fill the rings. */
1457         rxq_data->cqe_n = log2above(cq_info.cqe_cnt);
1458         rxq_data->cq_db = cq_info.dbrec;
1459         rxq_data->cqes = (volatile struct mlx5_cqe (*)[])(uintptr_t)cq_info.buf;
1460         rxq_data->cq_uar = cq_info.cq_uar;
1461         rxq_data->cqn = cq_info.cqn;
1462         rxq_data->cq_arm_sn = 0;
1463         mlx5_rxq_initialize(rxq_data);
1464         rxq_data->cq_ci = 0;
1465         DRV_LOG(DEBUG, "port %u rxq %u updated with %p", dev->data->port_id,
1466                 idx, (void *)&tmpl);
1467         rte_atomic32_inc(&tmpl->refcnt);
1468         LIST_INSERT_HEAD(&priv->rxqsobj, tmpl, next);
1469         priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
1470         return tmpl;
1471 error:
1472         if (tmpl) {
1473                 ret = rte_errno; /* Save rte_errno before cleanup. */
1474                 if (tmpl->type == MLX5_RXQ_OBJ_TYPE_IBV && tmpl->wq)
1475                         claim_zero(mlx5_glue->destroy_wq(tmpl->wq));
1476                 else if (tmpl->type == MLX5_RXQ_OBJ_TYPE_DEVX_RQ && tmpl->rq)
1477                         claim_zero(mlx5_devx_cmd_destroy(tmpl->rq));
1478                 if (tmpl->cq)
1479                         claim_zero(mlx5_glue->destroy_cq(tmpl->cq));
1480                 if (tmpl->channel)
1481                         claim_zero(mlx5_glue->destroy_comp_channel
1482                                                         (tmpl->channel));
1483                 rte_free(tmpl);
1484                 rte_errno = ret; /* Restore rte_errno. */
1485         }
1486         if (type == MLX5_RXQ_OBJ_TYPE_DEVX_RQ)
1487                 rxq_release_rq_resources(rxq_ctrl);
1488         priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
1489         return NULL;
1490 }
1491
1492 /**
1493  * Verify the Rx queue objects list is empty
1494  *
1495  * @param dev
1496  *   Pointer to Ethernet device.
1497  *
1498  * @return
1499  *   The number of objects not released.
1500  */
1501 int
1502 mlx5_rxq_obj_verify(struct rte_eth_dev *dev)
1503 {
1504         struct mlx5_priv *priv = dev->data->dev_private;
1505         int ret = 0;
1506         struct mlx5_rxq_obj *rxq_obj;
1507
1508         LIST_FOREACH(rxq_obj, &priv->rxqsobj, next) {
1509                 DRV_LOG(DEBUG, "port %u Rx queue %u still referenced",
1510                         dev->data->port_id, rxq_obj->rxq_ctrl->rxq.idx);
1511                 ++ret;
1512         }
1513         return ret;
1514 }
1515
1516 /**
1517  * Callback function to initialize mbufs for Multi-Packet RQ.
1518  */
1519 static inline void
1520 mlx5_mprq_buf_init(struct rte_mempool *mp, void *opaque_arg,
1521                     void *_m, unsigned int i __rte_unused)
1522 {
1523         struct mlx5_mprq_buf *buf = _m;
1524         struct rte_mbuf_ext_shared_info *shinfo;
1525         unsigned int strd_n = (unsigned int)(uintptr_t)opaque_arg;
1526         unsigned int j;
1527
1528         memset(_m, 0, sizeof(*buf));
1529         buf->mp = mp;
1530         rte_atomic16_set(&buf->refcnt, 1);
1531         for (j = 0; j != strd_n; ++j) {
1532                 shinfo = &buf->shinfos[j];
1533                 shinfo->free_cb = mlx5_mprq_buf_free_cb;
1534                 shinfo->fcb_opaque = buf;
1535         }
1536 }
1537
1538 /**
1539  * Free mempool of Multi-Packet RQ.
1540  *
1541  * @param dev
1542  *   Pointer to Ethernet device.
1543  *
1544  * @return
1545  *   0 on success, negative errno value on failure.
1546  */
1547 int
1548 mlx5_mprq_free_mp(struct rte_eth_dev *dev)
1549 {
1550         struct mlx5_priv *priv = dev->data->dev_private;
1551         struct rte_mempool *mp = priv->mprq_mp;
1552         unsigned int i;
1553
1554         if (mp == NULL)
1555                 return 0;
1556         DRV_LOG(DEBUG, "port %u freeing mempool (%s) for Multi-Packet RQ",
1557                 dev->data->port_id, mp->name);
1558         /*
1559          * If a buffer in the pool has been externally attached to a mbuf and it
1560          * is still in use by application, destroying the Rx queue can spoil
1561          * the packet. It is unlikely to happen but if application dynamically
1562          * creates and destroys with holding Rx packets, this can happen.
1563          *
1564          * TODO: It is unavoidable for now because the mempool for Multi-Packet
1565          * RQ isn't provided by application but managed by PMD.
1566          */
1567         if (!rte_mempool_full(mp)) {
1568                 DRV_LOG(ERR,
1569                         "port %u mempool for Multi-Packet RQ is still in use",
1570                         dev->data->port_id);
1571                 rte_errno = EBUSY;
1572                 return -rte_errno;
1573         }
1574         rte_mempool_free(mp);
1575         /* Unset mempool for each Rx queue. */
1576         for (i = 0; i != priv->rxqs_n; ++i) {
1577                 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
1578
1579                 if (rxq == NULL)
1580                         continue;
1581                 rxq->mprq_mp = NULL;
1582         }
1583         priv->mprq_mp = NULL;
1584         return 0;
1585 }
1586
1587 /**
1588  * Allocate a mempool for Multi-Packet RQ. All configured Rx queues share the
1589  * mempool. If already allocated, reuse it if there're enough elements.
1590  * Otherwise, resize it.
1591  *
1592  * @param dev
1593  *   Pointer to Ethernet device.
1594  *
1595  * @return
1596  *   0 on success, negative errno value on failure.
1597  */
1598 int
1599 mlx5_mprq_alloc_mp(struct rte_eth_dev *dev)
1600 {
1601         struct mlx5_priv *priv = dev->data->dev_private;
1602         struct rte_mempool *mp = priv->mprq_mp;
1603         char name[RTE_MEMPOOL_NAMESIZE];
1604         unsigned int desc = 0;
1605         unsigned int buf_len;
1606         unsigned int obj_num;
1607         unsigned int obj_size;
1608         unsigned int strd_num_n = 0;
1609         unsigned int strd_sz_n = 0;
1610         unsigned int i;
1611         unsigned int n_ibv = 0;
1612
1613         if (!mlx5_mprq_enabled(dev))
1614                 return 0;
1615         /* Count the total number of descriptors configured. */
1616         for (i = 0; i != priv->rxqs_n; ++i) {
1617                 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
1618                 struct mlx5_rxq_ctrl *rxq_ctrl = container_of
1619                         (rxq, struct mlx5_rxq_ctrl, rxq);
1620
1621                 if (rxq == NULL || rxq_ctrl->type != MLX5_RXQ_TYPE_STANDARD)
1622                         continue;
1623                 n_ibv++;
1624                 desc += 1 << rxq->elts_n;
1625                 /* Get the max number of strides. */
1626                 if (strd_num_n < rxq->strd_num_n)
1627                         strd_num_n = rxq->strd_num_n;
1628                 /* Get the max size of a stride. */
1629                 if (strd_sz_n < rxq->strd_sz_n)
1630                         strd_sz_n = rxq->strd_sz_n;
1631         }
1632         assert(strd_num_n && strd_sz_n);
1633         buf_len = (1 << strd_num_n) * (1 << strd_sz_n);
1634         obj_size = sizeof(struct mlx5_mprq_buf) + buf_len + (1 << strd_num_n) *
1635                 sizeof(struct rte_mbuf_ext_shared_info) + RTE_PKTMBUF_HEADROOM;
1636         /*
1637          * Received packets can be either memcpy'd or externally referenced. In
1638          * case that the packet is attached to an mbuf as an external buffer, as
1639          * it isn't possible to predict how the buffers will be queued by
1640          * application, there's no option to exactly pre-allocate needed buffers
1641          * in advance but to speculatively prepares enough buffers.
1642          *
1643          * In the data path, if this Mempool is depleted, PMD will try to memcpy
1644          * received packets to buffers provided by application (rxq->mp) until
1645          * this Mempool gets available again.
1646          */
1647         desc *= 4;
1648         obj_num = desc + MLX5_MPRQ_MP_CACHE_SZ * n_ibv;
1649         /*
1650          * rte_mempool_create_empty() has sanity check to refuse large cache
1651          * size compared to the number of elements.
1652          * CACHE_FLUSHTHRESH_MULTIPLIER is defined in a C file, so using a
1653          * constant number 2 instead.
1654          */
1655         obj_num = RTE_MAX(obj_num, MLX5_MPRQ_MP_CACHE_SZ * 2);
1656         /* Check a mempool is already allocated and if it can be resued. */
1657         if (mp != NULL && mp->elt_size >= obj_size && mp->size >= obj_num) {
1658                 DRV_LOG(DEBUG, "port %u mempool %s is being reused",
1659                         dev->data->port_id, mp->name);
1660                 /* Reuse. */
1661                 goto exit;
1662         } else if (mp != NULL) {
1663                 DRV_LOG(DEBUG, "port %u mempool %s should be resized, freeing it",
1664                         dev->data->port_id, mp->name);
1665                 /*
1666                  * If failed to free, which means it may be still in use, no way
1667                  * but to keep using the existing one. On buffer underrun,
1668                  * packets will be memcpy'd instead of external buffer
1669                  * attachment.
1670                  */
1671                 if (mlx5_mprq_free_mp(dev)) {
1672                         if (mp->elt_size >= obj_size)
1673                                 goto exit;
1674                         else
1675                                 return -rte_errno;
1676                 }
1677         }
1678         snprintf(name, sizeof(name), "port-%u-mprq", dev->data->port_id);
1679         mp = rte_mempool_create(name, obj_num, obj_size, MLX5_MPRQ_MP_CACHE_SZ,
1680                                 0, NULL, NULL, mlx5_mprq_buf_init,
1681                                 (void *)(uintptr_t)(1 << strd_num_n),
1682                                 dev->device->numa_node, 0);
1683         if (mp == NULL) {
1684                 DRV_LOG(ERR,
1685                         "port %u failed to allocate a mempool for"
1686                         " Multi-Packet RQ, count=%u, size=%u",
1687                         dev->data->port_id, obj_num, obj_size);
1688                 rte_errno = ENOMEM;
1689                 return -rte_errno;
1690         }
1691         priv->mprq_mp = mp;
1692 exit:
1693         /* Set mempool for each Rx queue. */
1694         for (i = 0; i != priv->rxqs_n; ++i) {
1695                 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
1696                 struct mlx5_rxq_ctrl *rxq_ctrl = container_of
1697                         (rxq, struct mlx5_rxq_ctrl, rxq);
1698
1699                 if (rxq == NULL || rxq_ctrl->type != MLX5_RXQ_TYPE_STANDARD)
1700                         continue;
1701                 rxq->mprq_mp = mp;
1702         }
1703         DRV_LOG(INFO, "port %u Multi-Packet RQ is configured",
1704                 dev->data->port_id);
1705         return 0;
1706 }
1707
1708 #define MLX5_MAX_TCP_HDR_OFFSET ((unsigned int)(sizeof(struct rte_ether_hdr) + \
1709                                         sizeof(struct rte_vlan_hdr) * 2 + \
1710                                         sizeof(struct rte_ipv6_hdr)))
1711 #define MAX_TCP_OPTION_SIZE 40u
1712 #define MLX5_MAX_LRO_HEADER_FIX ((unsigned int)(MLX5_MAX_TCP_HDR_OFFSET + \
1713                                  sizeof(struct rte_tcp_hdr) + \
1714                                  MAX_TCP_OPTION_SIZE))
1715
1716 /**
1717  * Adjust the maximum LRO massage size.
1718  *
1719  * @param dev
1720  *   Pointer to Ethernet device.
1721  * @param idx
1722  *   RX queue index.
1723  * @param max_lro_size
1724  *   The maximum size for LRO packet.
1725  */
1726 static void
1727 mlx5_max_lro_msg_size_adjust(struct rte_eth_dev *dev, uint16_t idx,
1728                              uint32_t max_lro_size)
1729 {
1730         struct mlx5_priv *priv = dev->data->dev_private;
1731
1732         if (priv->config.hca_attr.lro_max_msg_sz_mode ==
1733             MLX5_LRO_MAX_MSG_SIZE_START_FROM_L4 && max_lro_size >
1734             MLX5_MAX_TCP_HDR_OFFSET)
1735                 max_lro_size -= MLX5_MAX_TCP_HDR_OFFSET;
1736         max_lro_size = RTE_MIN(max_lro_size, MLX5_MAX_LRO_SIZE);
1737         assert(max_lro_size >= MLX5_LRO_SEG_CHUNK_SIZE);
1738         max_lro_size /= MLX5_LRO_SEG_CHUNK_SIZE;
1739         if (priv->max_lro_msg_size)
1740                 priv->max_lro_msg_size =
1741                         RTE_MIN((uint32_t)priv->max_lro_msg_size, max_lro_size);
1742         else
1743                 priv->max_lro_msg_size = max_lro_size;
1744         DRV_LOG(DEBUG,
1745                 "port %u Rx Queue %u max LRO message size adjusted to %u bytes",
1746                 dev->data->port_id, idx,
1747                 priv->max_lro_msg_size * MLX5_LRO_SEG_CHUNK_SIZE);
1748 }
1749
1750 /**
1751  * Create a DPDK Rx queue.
1752  *
1753  * @param dev
1754  *   Pointer to Ethernet device.
1755  * @param idx
1756  *   RX queue index.
1757  * @param desc
1758  *   Number of descriptors to configure in queue.
1759  * @param socket
1760  *   NUMA socket on which memory must be allocated.
1761  *
1762  * @return
1763  *   A DPDK queue object on success, NULL otherwise and rte_errno is set.
1764  */
1765 struct mlx5_rxq_ctrl *
1766 mlx5_rxq_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1767              unsigned int socket, const struct rte_eth_rxconf *conf,
1768              struct rte_mempool *mp)
1769 {
1770         struct mlx5_priv *priv = dev->data->dev_private;
1771         struct mlx5_rxq_ctrl *tmpl;
1772         unsigned int mb_len = rte_pktmbuf_data_room_size(mp);
1773         unsigned int mprq_stride_size;
1774         struct mlx5_dev_config *config = &priv->config;
1775         unsigned int strd_headroom_en;
1776         /*
1777          * Always allocate extra slots, even if eventually
1778          * the vector Rx will not be used.
1779          */
1780         uint16_t desc_n =
1781                 desc + config->rx_vec_en * MLX5_VPMD_DESCS_PER_LOOP;
1782         uint64_t offloads = conf->offloads |
1783                            dev->data->dev_conf.rxmode.offloads;
1784         unsigned int lro_on_queue = !!(offloads & DEV_RX_OFFLOAD_TCP_LRO);
1785         const int mprq_en = mlx5_check_mprq_support(dev) > 0;
1786         unsigned int max_rx_pkt_len = lro_on_queue ?
1787                         dev->data->dev_conf.rxmode.max_lro_pkt_size :
1788                         dev->data->dev_conf.rxmode.max_rx_pkt_len;
1789         unsigned int non_scatter_min_mbuf_size = max_rx_pkt_len +
1790                                                         RTE_PKTMBUF_HEADROOM;
1791         unsigned int max_lro_size = 0;
1792         unsigned int first_mb_free_size = mb_len - RTE_PKTMBUF_HEADROOM;
1793
1794         if (non_scatter_min_mbuf_size > mb_len && !(offloads &
1795                                                     DEV_RX_OFFLOAD_SCATTER)) {
1796                 DRV_LOG(ERR, "port %u Rx queue %u: Scatter offload is not"
1797                         " configured and no enough mbuf space(%u) to contain "
1798                         "the maximum RX packet length(%u) with head-room(%u)",
1799                         dev->data->port_id, idx, mb_len, max_rx_pkt_len,
1800                         RTE_PKTMBUF_HEADROOM);
1801                 rte_errno = ENOSPC;
1802                 return NULL;
1803         }
1804         tmpl = rte_calloc_socket("RXQ", 1,
1805                                  sizeof(*tmpl) +
1806                                  desc_n * sizeof(struct rte_mbuf *),
1807                                  0, socket);
1808         if (!tmpl) {
1809                 rte_errno = ENOMEM;
1810                 return NULL;
1811         }
1812         tmpl->type = MLX5_RXQ_TYPE_STANDARD;
1813         if (mlx5_mr_btree_init(&tmpl->rxq.mr_ctrl.cache_bh,
1814                                MLX5_MR_BTREE_CACHE_N, socket)) {
1815                 /* rte_errno is already set. */
1816                 goto error;
1817         }
1818         tmpl->socket = socket;
1819         if (dev->data->dev_conf.intr_conf.rxq)
1820                 tmpl->irq = 1;
1821         /*
1822          * LRO packet may consume all the stride memory, hence we cannot
1823          * guaranty head-room near the packet memory in the stride.
1824          * In this case scatter is, for sure, enabled and an empty mbuf may be
1825          * added in the start for the head-room.
1826          */
1827         if (lro_on_queue && RTE_PKTMBUF_HEADROOM > 0 &&
1828             non_scatter_min_mbuf_size > mb_len) {
1829                 strd_headroom_en = 0;
1830                 mprq_stride_size = RTE_MIN(max_rx_pkt_len,
1831                                         1u << config->mprq.max_stride_size_n);
1832         } else {
1833                 strd_headroom_en = 1;
1834                 mprq_stride_size = non_scatter_min_mbuf_size;
1835         }
1836         /*
1837          * This Rx queue can be configured as a Multi-Packet RQ if all of the
1838          * following conditions are met:
1839          *  - MPRQ is enabled.
1840          *  - The number of descs is more than the number of strides.
1841          *  - max_rx_pkt_len plus overhead is less than the max size of a
1842          *    stride.
1843          *  Otherwise, enable Rx scatter if necessary.
1844          */
1845         if (mprq_en &&
1846             desc > (1U << config->mprq.stride_num_n) &&
1847             mprq_stride_size <= (1U << config->mprq.max_stride_size_n)) {
1848                 /* TODO: Rx scatter isn't supported yet. */
1849                 tmpl->rxq.sges_n = 0;
1850                 /* Trim the number of descs needed. */
1851                 desc >>= config->mprq.stride_num_n;
1852                 tmpl->rxq.strd_num_n = config->mprq.stride_num_n;
1853                 tmpl->rxq.strd_sz_n = RTE_MAX(log2above(mprq_stride_size),
1854                                               config->mprq.min_stride_size_n);
1855                 tmpl->rxq.strd_shift_en = MLX5_MPRQ_TWO_BYTE_SHIFT;
1856                 tmpl->rxq.strd_headroom_en = strd_headroom_en;
1857                 tmpl->rxq.mprq_max_memcpy_len = RTE_MIN(first_mb_free_size,
1858                                 config->mprq.max_memcpy_len);
1859                 max_lro_size = RTE_MIN(max_rx_pkt_len,
1860                                        (1u << tmpl->rxq.strd_num_n) *
1861                                        (1u << tmpl->rxq.strd_sz_n));
1862                 DRV_LOG(DEBUG,
1863                         "port %u Rx queue %u: Multi-Packet RQ is enabled"
1864                         " strd_num_n = %u, strd_sz_n = %u",
1865                         dev->data->port_id, idx,
1866                         tmpl->rxq.strd_num_n, tmpl->rxq.strd_sz_n);
1867         } else if (max_rx_pkt_len <= first_mb_free_size) {
1868                 tmpl->rxq.sges_n = 0;
1869                 max_lro_size = max_rx_pkt_len;
1870         } else if (offloads & DEV_RX_OFFLOAD_SCATTER) {
1871                 unsigned int size = non_scatter_min_mbuf_size;
1872                 unsigned int sges_n;
1873
1874                 if (lro_on_queue && first_mb_free_size <
1875                     MLX5_MAX_LRO_HEADER_FIX) {
1876                         DRV_LOG(ERR, "Not enough space in the first segment(%u)"
1877                                 " to include the max header size(%u) for LRO",
1878                                 first_mb_free_size, MLX5_MAX_LRO_HEADER_FIX);
1879                         rte_errno = ENOTSUP;
1880                         goto error;
1881                 }
1882                 /*
1883                  * Determine the number of SGEs needed for a full packet
1884                  * and round it to the next power of two.
1885                  */
1886                 sges_n = log2above((size / mb_len) + !!(size % mb_len));
1887                 if (sges_n > MLX5_MAX_LOG_RQ_SEGS) {
1888                         DRV_LOG(ERR,
1889                                 "port %u too many SGEs (%u) needed to handle"
1890                                 " requested maximum packet size %u, the maximum"
1891                                 " supported are %u", dev->data->port_id,
1892                                 1 << sges_n, max_rx_pkt_len,
1893                                 1u << MLX5_MAX_LOG_RQ_SEGS);
1894                         rte_errno = ENOTSUP;
1895                         goto error;
1896                 }
1897                 tmpl->rxq.sges_n = sges_n;
1898                 max_lro_size = max_rx_pkt_len;
1899         }
1900         if (mprq_en && !mlx5_rxq_mprq_enabled(&tmpl->rxq))
1901                 DRV_LOG(WARNING,
1902                         "port %u MPRQ is requested but cannot be enabled"
1903                         " (requested: desc = %u, stride_sz = %u,"
1904                         " supported: min_stride_num = %u, max_stride_sz = %u).",
1905                         dev->data->port_id, desc, mprq_stride_size,
1906                         (1 << config->mprq.stride_num_n),
1907                         (1 << config->mprq.max_stride_size_n));
1908         DRV_LOG(DEBUG, "port %u maximum number of segments per packet: %u",
1909                 dev->data->port_id, 1 << tmpl->rxq.sges_n);
1910         if (desc % (1 << tmpl->rxq.sges_n)) {
1911                 DRV_LOG(ERR,
1912                         "port %u number of Rx queue descriptors (%u) is not a"
1913                         " multiple of SGEs per packet (%u)",
1914                         dev->data->port_id,
1915                         desc,
1916                         1 << tmpl->rxq.sges_n);
1917                 rte_errno = EINVAL;
1918                 goto error;
1919         }
1920         mlx5_max_lro_msg_size_adjust(dev, idx, max_lro_size);
1921         /* Toggle RX checksum offload if hardware supports it. */
1922         tmpl->rxq.csum = !!(offloads & DEV_RX_OFFLOAD_CHECKSUM);
1923         tmpl->rxq.hw_timestamp = !!(offloads & DEV_RX_OFFLOAD_TIMESTAMP);
1924         /* Configure VLAN stripping. */
1925         tmpl->rxq.vlan_strip = !!(offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
1926         /* By default, FCS (CRC) is stripped by hardware. */
1927         tmpl->rxq.crc_present = 0;
1928         tmpl->rxq.lro = lro_on_queue;
1929         if (offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
1930                 if (config->hw_fcs_strip) {
1931                         /*
1932                          * RQs used for LRO-enabled TIRs should not be
1933                          * configured to scatter the FCS.
1934                          */
1935                         if (lro_on_queue)
1936                                 DRV_LOG(WARNING,
1937                                         "port %u CRC stripping has been "
1938                                         "disabled but will still be performed "
1939                                         "by hardware, because LRO is enabled",
1940                                         dev->data->port_id);
1941                         else
1942                                 tmpl->rxq.crc_present = 1;
1943                 } else {
1944                         DRV_LOG(WARNING,
1945                                 "port %u CRC stripping has been disabled but will"
1946                                 " still be performed by hardware, make sure MLNX_OFED"
1947                                 " and firmware are up to date",
1948                                 dev->data->port_id);
1949                 }
1950         }
1951         DRV_LOG(DEBUG,
1952                 "port %u CRC stripping is %s, %u bytes will be subtracted from"
1953                 " incoming frames to hide it",
1954                 dev->data->port_id,
1955                 tmpl->rxq.crc_present ? "disabled" : "enabled",
1956                 tmpl->rxq.crc_present << 2);
1957         /* Save port ID. */
1958         tmpl->rxq.rss_hash = !!priv->rss_conf.rss_hf &&
1959                 (!!(dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS));
1960         tmpl->rxq.port_id = dev->data->port_id;
1961         tmpl->priv = priv;
1962         tmpl->rxq.mp = mp;
1963         tmpl->rxq.elts_n = log2above(desc);
1964         tmpl->rxq.rq_repl_thresh =
1965                 MLX5_VPMD_RXQ_RPLNSH_THRESH(1 << tmpl->rxq.elts_n);
1966         tmpl->rxq.elts =
1967                 (struct rte_mbuf *(*)[1 << tmpl->rxq.elts_n])(tmpl + 1);
1968 #ifndef RTE_ARCH_64
1969         tmpl->rxq.uar_lock_cq = &priv->uar_lock_cq;
1970 #endif
1971         tmpl->rxq.idx = idx;
1972         rte_atomic32_inc(&tmpl->refcnt);
1973         LIST_INSERT_HEAD(&priv->rxqsctrl, tmpl, next);
1974         return tmpl;
1975 error:
1976         rte_free(tmpl);
1977         return NULL;
1978 }
1979
1980 /**
1981  * Create a DPDK Rx hairpin queue.
1982  *
1983  * @param dev
1984  *   Pointer to Ethernet device.
1985  * @param idx
1986  *   RX queue index.
1987  * @param desc
1988  *   Number of descriptors to configure in queue.
1989  * @param hairpin_conf
1990  *   The hairpin binding configuration.
1991  *
1992  * @return
1993  *   A DPDK queue object on success, NULL otherwise and rte_errno is set.
1994  */
1995 struct mlx5_rxq_ctrl *
1996 mlx5_rxq_hairpin_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1997                      const struct rte_eth_hairpin_conf *hairpin_conf)
1998 {
1999         struct mlx5_priv *priv = dev->data->dev_private;
2000         struct mlx5_rxq_ctrl *tmpl;
2001
2002         tmpl = rte_calloc_socket("RXQ", 1, sizeof(*tmpl), 0, SOCKET_ID_ANY);
2003         if (!tmpl) {
2004                 rte_errno = ENOMEM;
2005                 return NULL;
2006         }
2007         tmpl->type = MLX5_RXQ_TYPE_HAIRPIN;
2008         tmpl->socket = SOCKET_ID_ANY;
2009         tmpl->rxq.rss_hash = 0;
2010         tmpl->rxq.port_id = dev->data->port_id;
2011         tmpl->priv = priv;
2012         tmpl->rxq.mp = NULL;
2013         tmpl->rxq.elts_n = log2above(desc);
2014         tmpl->rxq.elts = NULL;
2015         tmpl->rxq.mr_ctrl.cache_bh = (struct mlx5_mr_btree) { 0 };
2016         tmpl->hairpin_conf = *hairpin_conf;
2017         tmpl->rxq.idx = idx;
2018         rte_atomic32_inc(&tmpl->refcnt);
2019         LIST_INSERT_HEAD(&priv->rxqsctrl, tmpl, next);
2020         return tmpl;
2021 }
2022
2023 /**
2024  * Get a Rx queue.
2025  *
2026  * @param dev
2027  *   Pointer to Ethernet device.
2028  * @param idx
2029  *   RX queue index.
2030  *
2031  * @return
2032  *   A pointer to the queue if it exists, NULL otherwise.
2033  */
2034 struct mlx5_rxq_ctrl *
2035 mlx5_rxq_get(struct rte_eth_dev *dev, uint16_t idx)
2036 {
2037         struct mlx5_priv *priv = dev->data->dev_private;
2038         struct mlx5_rxq_ctrl *rxq_ctrl = NULL;
2039
2040         if ((*priv->rxqs)[idx]) {
2041                 rxq_ctrl = container_of((*priv->rxqs)[idx],
2042                                         struct mlx5_rxq_ctrl,
2043                                         rxq);
2044                 mlx5_rxq_obj_get(dev, idx);
2045                 rte_atomic32_inc(&rxq_ctrl->refcnt);
2046         }
2047         return rxq_ctrl;
2048 }
2049
2050 /**
2051  * Release a Rx queue.
2052  *
2053  * @param dev
2054  *   Pointer to Ethernet device.
2055  * @param idx
2056  *   RX queue index.
2057  *
2058  * @return
2059  *   1 while a reference on it exists, 0 when freed.
2060  */
2061 int
2062 mlx5_rxq_release(struct rte_eth_dev *dev, uint16_t idx)
2063 {
2064         struct mlx5_priv *priv = dev->data->dev_private;
2065         struct mlx5_rxq_ctrl *rxq_ctrl;
2066
2067         if (!(*priv->rxqs)[idx])
2068                 return 0;
2069         rxq_ctrl = container_of((*priv->rxqs)[idx], struct mlx5_rxq_ctrl, rxq);
2070         assert(rxq_ctrl->priv);
2071         if (rxq_ctrl->obj && !mlx5_rxq_obj_release(rxq_ctrl->obj))
2072                 rxq_ctrl->obj = NULL;
2073         if (rte_atomic32_dec_and_test(&rxq_ctrl->refcnt)) {
2074                 if (rxq_ctrl->dbr_umem_id_valid)
2075                         claim_zero(mlx5_release_dbr(dev, rxq_ctrl->dbr_umem_id,
2076                                                     rxq_ctrl->dbr_offset));
2077                 if (rxq_ctrl->type == MLX5_RXQ_TYPE_STANDARD)
2078                         mlx5_mr_btree_free(&rxq_ctrl->rxq.mr_ctrl.cache_bh);
2079                 LIST_REMOVE(rxq_ctrl, next);
2080                 rte_free(rxq_ctrl);
2081                 (*priv->rxqs)[idx] = NULL;
2082                 return 0;
2083         }
2084         return 1;
2085 }
2086
2087 /**
2088  * Verify the Rx Queue list is empty
2089  *
2090  * @param dev
2091  *   Pointer to Ethernet device.
2092  *
2093  * @return
2094  *   The number of object not released.
2095  */
2096 int
2097 mlx5_rxq_verify(struct rte_eth_dev *dev)
2098 {
2099         struct mlx5_priv *priv = dev->data->dev_private;
2100         struct mlx5_rxq_ctrl *rxq_ctrl;
2101         int ret = 0;
2102
2103         LIST_FOREACH(rxq_ctrl, &priv->rxqsctrl, next) {
2104                 DRV_LOG(DEBUG, "port %u Rx Queue %u still referenced",
2105                         dev->data->port_id, rxq_ctrl->rxq.idx);
2106                 ++ret;
2107         }
2108         return ret;
2109 }
2110
2111 /**
2112  * Get a Rx queue type.
2113  *
2114  * @param dev
2115  *   Pointer to Ethernet device.
2116  * @param idx
2117  *   Rx queue index.
2118  *
2119  * @return
2120  *   The Rx queue type.
2121  */
2122 enum mlx5_rxq_type
2123 mlx5_rxq_get_type(struct rte_eth_dev *dev, uint16_t idx)
2124 {
2125         struct mlx5_priv *priv = dev->data->dev_private;
2126         struct mlx5_rxq_ctrl *rxq_ctrl = NULL;
2127
2128         if (idx < priv->rxqs_n && (*priv->rxqs)[idx]) {
2129                 rxq_ctrl = container_of((*priv->rxqs)[idx],
2130                                         struct mlx5_rxq_ctrl,
2131                                         rxq);
2132                 return rxq_ctrl->type;
2133         }
2134         return MLX5_RXQ_TYPE_UNDEFINED;
2135 }
2136
2137 /**
2138  * Create an indirection table.
2139  *
2140  * @param dev
2141  *   Pointer to Ethernet device.
2142  * @param queues
2143  *   Queues entering in the indirection table.
2144  * @param queues_n
2145  *   Number of queues in the array.
2146  *
2147  * @return
2148  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2149  */
2150 static struct mlx5_ind_table_obj *
2151 mlx5_ind_table_obj_new(struct rte_eth_dev *dev, const uint16_t *queues,
2152                        uint32_t queues_n, enum mlx5_ind_tbl_type type)
2153 {
2154         struct mlx5_priv *priv = dev->data->dev_private;
2155         struct mlx5_ind_table_obj *ind_tbl;
2156         unsigned int i = 0, j = 0, k = 0;
2157
2158         ind_tbl = rte_calloc(__func__, 1, sizeof(*ind_tbl) +
2159                              queues_n * sizeof(uint16_t), 0);
2160         if (!ind_tbl) {
2161                 rte_errno = ENOMEM;
2162                 return NULL;
2163         }
2164         ind_tbl->type = type;
2165         if (ind_tbl->type == MLX5_IND_TBL_TYPE_IBV) {
2166                 const unsigned int wq_n = rte_is_power_of_2(queues_n) ?
2167                         log2above(queues_n) :
2168                         log2above(priv->config.ind_table_max_size);
2169                 struct ibv_wq *wq[1 << wq_n];
2170
2171                 for (i = 0; i != queues_n; ++i) {
2172                         struct mlx5_rxq_ctrl *rxq = mlx5_rxq_get(dev,
2173                                                                  queues[i]);
2174                         if (!rxq)
2175                                 goto error;
2176                         wq[i] = rxq->obj->wq;
2177                         ind_tbl->queues[i] = queues[i];
2178                 }
2179                 ind_tbl->queues_n = queues_n;
2180                 /* Finalise indirection table. */
2181                 k = i; /* Retain value of i for use in error case. */
2182                 for (j = 0; k != (unsigned int)(1 << wq_n); ++k, ++j)
2183                         wq[k] = wq[j];
2184                 ind_tbl->ind_table = mlx5_glue->create_rwq_ind_table
2185                         (priv->sh->ctx,
2186                          &(struct ibv_rwq_ind_table_init_attr){
2187                                 .log_ind_tbl_size = wq_n,
2188                                 .ind_tbl = wq,
2189                                 .comp_mask = 0,
2190                         });
2191                 if (!ind_tbl->ind_table) {
2192                         rte_errno = errno;
2193                         goto error;
2194                 }
2195         } else { /* ind_tbl->type == MLX5_IND_TBL_TYPE_DEVX */
2196                 struct mlx5_devx_rqt_attr *rqt_attr = NULL;
2197                 const unsigned int rqt_n =
2198                         1 << (rte_is_power_of_2(queues_n) ?
2199                               log2above(queues_n) :
2200                               log2above(priv->config.ind_table_max_size));
2201
2202                 rqt_attr = rte_calloc(__func__, 1, sizeof(*rqt_attr) +
2203                                       rqt_n * sizeof(uint32_t), 0);
2204                 if (!rqt_attr) {
2205                         DRV_LOG(ERR, "port %u cannot allocate RQT resources",
2206                                 dev->data->port_id);
2207                         rte_errno = ENOMEM;
2208                         goto error;
2209                 }
2210                 rqt_attr->rqt_max_size = priv->config.ind_table_max_size;
2211                 rqt_attr->rqt_actual_size = rqt_n;
2212                 for (i = 0; i != queues_n; ++i) {
2213                         struct mlx5_rxq_ctrl *rxq = mlx5_rxq_get(dev,
2214                                                                  queues[i]);
2215                         if (!rxq)
2216                                 goto error;
2217                         rqt_attr->rq_list[i] = rxq->obj->rq->id;
2218                         ind_tbl->queues[i] = queues[i];
2219                 }
2220                 k = i; /* Retain value of i for use in error case. */
2221                 for (j = 0; k != rqt_n; ++k, ++j)
2222                         rqt_attr->rq_list[k] = rqt_attr->rq_list[j];
2223                 ind_tbl->rqt = mlx5_devx_cmd_create_rqt(priv->sh->ctx,
2224                                                         rqt_attr);
2225                 rte_free(rqt_attr);
2226                 if (!ind_tbl->rqt) {
2227                         DRV_LOG(ERR, "port %u cannot create DevX RQT",
2228                                 dev->data->port_id);
2229                         rte_errno = errno;
2230                         goto error;
2231                 }
2232                 ind_tbl->queues_n = queues_n;
2233         }
2234         rte_atomic32_inc(&ind_tbl->refcnt);
2235         LIST_INSERT_HEAD(&priv->ind_tbls, ind_tbl, next);
2236         return ind_tbl;
2237 error:
2238         for (j = 0; j < i; j++)
2239                 mlx5_rxq_release(dev, ind_tbl->queues[j]);
2240         rte_free(ind_tbl);
2241         DEBUG("port %u cannot create indirection table", dev->data->port_id);
2242         return NULL;
2243 }
2244
2245 /**
2246  * Get an indirection table.
2247  *
2248  * @param dev
2249  *   Pointer to Ethernet device.
2250  * @param queues
2251  *   Queues entering in the indirection table.
2252  * @param queues_n
2253  *   Number of queues in the array.
2254  *
2255  * @return
2256  *   An indirection table if found.
2257  */
2258 static struct mlx5_ind_table_obj *
2259 mlx5_ind_table_obj_get(struct rte_eth_dev *dev, const uint16_t *queues,
2260                        uint32_t queues_n)
2261 {
2262         struct mlx5_priv *priv = dev->data->dev_private;
2263         struct mlx5_ind_table_obj *ind_tbl;
2264
2265         LIST_FOREACH(ind_tbl, &priv->ind_tbls, next) {
2266                 if ((ind_tbl->queues_n == queues_n) &&
2267                     (memcmp(ind_tbl->queues, queues,
2268                             ind_tbl->queues_n * sizeof(ind_tbl->queues[0]))
2269                      == 0))
2270                         break;
2271         }
2272         if (ind_tbl) {
2273                 unsigned int i;
2274
2275                 rte_atomic32_inc(&ind_tbl->refcnt);
2276                 for (i = 0; i != ind_tbl->queues_n; ++i)
2277                         mlx5_rxq_get(dev, ind_tbl->queues[i]);
2278         }
2279         return ind_tbl;
2280 }
2281
2282 /**
2283  * Release an indirection table.
2284  *
2285  * @param dev
2286  *   Pointer to Ethernet device.
2287  * @param ind_table
2288  *   Indirection table to release.
2289  *
2290  * @return
2291  *   1 while a reference on it exists, 0 when freed.
2292  */
2293 static int
2294 mlx5_ind_table_obj_release(struct rte_eth_dev *dev,
2295                            struct mlx5_ind_table_obj *ind_tbl)
2296 {
2297         unsigned int i;
2298
2299         if (rte_atomic32_dec_and_test(&ind_tbl->refcnt)) {
2300                 if (ind_tbl->type == MLX5_IND_TBL_TYPE_IBV)
2301                         claim_zero(mlx5_glue->destroy_rwq_ind_table
2302                                                         (ind_tbl->ind_table));
2303                 else if (ind_tbl->type == MLX5_IND_TBL_TYPE_DEVX)
2304                         claim_zero(mlx5_devx_cmd_destroy(ind_tbl->rqt));
2305         }
2306         for (i = 0; i != ind_tbl->queues_n; ++i)
2307                 claim_nonzero(mlx5_rxq_release(dev, ind_tbl->queues[i]));
2308         if (!rte_atomic32_read(&ind_tbl->refcnt)) {
2309                 LIST_REMOVE(ind_tbl, next);
2310                 rte_free(ind_tbl);
2311                 return 0;
2312         }
2313         return 1;
2314 }
2315
2316 /**
2317  * Verify the Rx Queue list is empty
2318  *
2319  * @param dev
2320  *   Pointer to Ethernet device.
2321  *
2322  * @return
2323  *   The number of object not released.
2324  */
2325 int
2326 mlx5_ind_table_obj_verify(struct rte_eth_dev *dev)
2327 {
2328         struct mlx5_priv *priv = dev->data->dev_private;
2329         struct mlx5_ind_table_obj *ind_tbl;
2330         int ret = 0;
2331
2332         LIST_FOREACH(ind_tbl, &priv->ind_tbls, next) {
2333                 DRV_LOG(DEBUG,
2334                         "port %u indirection table obj %p still referenced",
2335                         dev->data->port_id, (void *)ind_tbl);
2336                 ++ret;
2337         }
2338         return ret;
2339 }
2340
2341 /**
2342  * Create an Rx Hash queue.
2343  *
2344  * @param dev
2345  *   Pointer to Ethernet device.
2346  * @param rss_key
2347  *   RSS key for the Rx hash queue.
2348  * @param rss_key_len
2349  *   RSS key length.
2350  * @param hash_fields
2351  *   Verbs protocol hash field to make the RSS on.
2352  * @param queues
2353  *   Queues entering in hash queue. In case of empty hash_fields only the
2354  *   first queue index will be taken for the indirection table.
2355  * @param queues_n
2356  *   Number of queues.
2357  * @param tunnel
2358  *   Tunnel type.
2359  *
2360  * @return
2361  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2362  */
2363 struct mlx5_hrxq *
2364 mlx5_hrxq_new(struct rte_eth_dev *dev,
2365               const uint8_t *rss_key, uint32_t rss_key_len,
2366               uint64_t hash_fields,
2367               const uint16_t *queues, uint32_t queues_n,
2368               int tunnel __rte_unused)
2369 {
2370         struct mlx5_priv *priv = dev->data->dev_private;
2371         struct mlx5_hrxq *hrxq;
2372         struct ibv_qp *qp = NULL;
2373         struct mlx5_ind_table_obj *ind_tbl;
2374         int err;
2375         struct mlx5_devx_obj *tir = NULL;
2376         struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[queues[0]];
2377         struct mlx5_rxq_ctrl *rxq_ctrl =
2378                 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
2379
2380         queues_n = hash_fields ? queues_n : 1;
2381         ind_tbl = mlx5_ind_table_obj_get(dev, queues, queues_n);
2382         if (!ind_tbl) {
2383                 enum mlx5_ind_tbl_type type;
2384
2385                 type = rxq_ctrl->obj->type == MLX5_RXQ_OBJ_TYPE_IBV ?
2386                                 MLX5_IND_TBL_TYPE_IBV : MLX5_IND_TBL_TYPE_DEVX;
2387                 ind_tbl = mlx5_ind_table_obj_new(dev, queues, queues_n, type);
2388         }
2389         if (!ind_tbl) {
2390                 rte_errno = ENOMEM;
2391                 return NULL;
2392         }
2393         if (ind_tbl->type == MLX5_IND_TBL_TYPE_IBV) {
2394 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
2395                 struct mlx5dv_qp_init_attr qp_init_attr;
2396
2397                 memset(&qp_init_attr, 0, sizeof(qp_init_attr));
2398                 if (tunnel) {
2399                         qp_init_attr.comp_mask =
2400                                 MLX5DV_QP_INIT_ATTR_MASK_QP_CREATE_FLAGS;
2401                         qp_init_attr.create_flags =
2402                                 MLX5DV_QP_CREATE_TUNNEL_OFFLOADS;
2403                 }
2404 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2405                 if (dev->data->dev_conf.lpbk_mode) {
2406                         /*
2407                          * Allow packet sent from NIC loop back
2408                          * w/o source MAC check.
2409                          */
2410                         qp_init_attr.comp_mask |=
2411                                 MLX5DV_QP_INIT_ATTR_MASK_QP_CREATE_FLAGS;
2412                         qp_init_attr.create_flags |=
2413                                 MLX5DV_QP_CREATE_TIR_ALLOW_SELF_LOOPBACK_UC;
2414                 }
2415 #endif
2416                 qp = mlx5_glue->dv_create_qp
2417                         (priv->sh->ctx,
2418                          &(struct ibv_qp_init_attr_ex){
2419                                 .qp_type = IBV_QPT_RAW_PACKET,
2420                                 .comp_mask =
2421                                         IBV_QP_INIT_ATTR_PD |
2422                                         IBV_QP_INIT_ATTR_IND_TABLE |
2423                                         IBV_QP_INIT_ATTR_RX_HASH,
2424                                 .rx_hash_conf = (struct ibv_rx_hash_conf){
2425                                         .rx_hash_function =
2426                                                 IBV_RX_HASH_FUNC_TOEPLITZ,
2427                                         .rx_hash_key_len = rss_key_len,
2428                                         .rx_hash_key =
2429                                                 (void *)(uintptr_t)rss_key,
2430                                         .rx_hash_fields_mask = hash_fields,
2431                                 },
2432                                 .rwq_ind_tbl = ind_tbl->ind_table,
2433                                 .pd = priv->sh->pd,
2434                           },
2435                           &qp_init_attr);
2436 #else
2437                 qp = mlx5_glue->create_qp_ex
2438                         (priv->sh->ctx,
2439                          &(struct ibv_qp_init_attr_ex){
2440                                 .qp_type = IBV_QPT_RAW_PACKET,
2441                                 .comp_mask =
2442                                         IBV_QP_INIT_ATTR_PD |
2443                                         IBV_QP_INIT_ATTR_IND_TABLE |
2444                                         IBV_QP_INIT_ATTR_RX_HASH,
2445                                 .rx_hash_conf = (struct ibv_rx_hash_conf){
2446                                         .rx_hash_function =
2447                                                 IBV_RX_HASH_FUNC_TOEPLITZ,
2448                                         .rx_hash_key_len = rss_key_len,
2449                                         .rx_hash_key =
2450                                                 (void *)(uintptr_t)rss_key,
2451                                         .rx_hash_fields_mask = hash_fields,
2452                                 },
2453                                 .rwq_ind_tbl = ind_tbl->ind_table,
2454                                 .pd = priv->sh->pd,
2455                          });
2456 #endif
2457                 if (!qp) {
2458                         rte_errno = errno;
2459                         goto error;
2460                 }
2461         } else { /* ind_tbl->type == MLX5_IND_TBL_TYPE_DEVX */
2462                 struct mlx5_devx_tir_attr tir_attr;
2463                 struct mlx5_rx_hash_field_select *rx_hash_field_select;
2464                 uint32_t i;
2465                 uint32_t lro = 1;
2466
2467                 /* Enable TIR LRO only if all the queues were configured for. */
2468                 for (i = 0; i < queues_n; ++i) {
2469                         if (!(*priv->rxqs)[queues[i]]->lro) {
2470                                 lro = 0;
2471                                 break;
2472                         }
2473                 }
2474                 memset(&tir_attr, 0, sizeof(tir_attr));
2475                 tir_attr.disp_type = MLX5_TIRC_DISP_TYPE_INDIRECT;
2476                 tir_attr.rx_hash_fn = MLX5_RX_HASH_FN_TOEPLITZ;
2477 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
2478                 tir_attr.tunneled_offload_en = !!tunnel;
2479                 /* Translate hash_fields bitmap to PRM format. */
2480                 rx_hash_field_select = hash_fields & IBV_RX_HASH_INNER ?
2481                                        &tir_attr.rx_hash_field_selector_inner :
2482                                        &tir_attr.rx_hash_field_selector_outer;
2483 #else
2484                 rx_hash_field_select = &tir_attr.rx_hash_field_selector_outer;
2485 #endif
2486                 /* 1 bit: 0: IPv4, 1: IPv6. */
2487                 rx_hash_field_select->l3_prot_type =
2488                         !!(hash_fields & MLX5_IPV6_IBV_RX_HASH);
2489                 /* 1 bit: 0: TCP, 1: UDP. */
2490                 rx_hash_field_select->l4_prot_type =
2491                         !!(hash_fields & MLX5_UDP_IBV_RX_HASH);
2492                 /* Bitmask which sets which fields to use in RX Hash. */
2493                 rx_hash_field_select->selected_fields =
2494                         ((!!(hash_fields & MLX5_L3_SRC_IBV_RX_HASH)) <<
2495                          MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP) |
2496                         (!!(hash_fields & MLX5_L3_DST_IBV_RX_HASH)) <<
2497                          MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP |
2498                         (!!(hash_fields & MLX5_L4_SRC_IBV_RX_HASH)) <<
2499                          MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT |
2500                         (!!(hash_fields & MLX5_L4_DST_IBV_RX_HASH)) <<
2501                          MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT;
2502                 if (rxq_ctrl->obj->type == MLX5_RXQ_OBJ_TYPE_DEVX_HAIRPIN)
2503                         tir_attr.transport_domain = priv->sh->td->id;
2504                 else
2505                         tir_attr.transport_domain = priv->sh->tdn;
2506                 memcpy(tir_attr.rx_hash_toeplitz_key, rss_key, rss_key_len);
2507                 tir_attr.indirect_table = ind_tbl->rqt->id;
2508                 if (dev->data->dev_conf.lpbk_mode)
2509                         tir_attr.self_lb_block =
2510                                         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
2511                 if (lro) {
2512                         tir_attr.lro_timeout_period_usecs =
2513                                         priv->config.lro.timeout;
2514                         tir_attr.lro_max_msg_sz = priv->max_lro_msg_size;
2515                         tir_attr.lro_enable_mask =
2516                                         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2517                                         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO;
2518                 }
2519                 tir = mlx5_devx_cmd_create_tir(priv->sh->ctx, &tir_attr);
2520                 if (!tir) {
2521                         DRV_LOG(ERR, "port %u cannot create DevX TIR",
2522                                 dev->data->port_id);
2523                         rte_errno = errno;
2524                         goto error;
2525                 }
2526         }
2527         hrxq = rte_calloc(__func__, 1, sizeof(*hrxq) + rss_key_len, 0);
2528         if (!hrxq)
2529                 goto error;
2530         hrxq->ind_table = ind_tbl;
2531         if (ind_tbl->type == MLX5_IND_TBL_TYPE_IBV) {
2532                 hrxq->qp = qp;
2533 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2534                 hrxq->action =
2535                         mlx5_glue->dv_create_flow_action_dest_ibv_qp(hrxq->qp);
2536                 if (!hrxq->action) {
2537                         rte_errno = errno;
2538                         goto error;
2539                 }
2540 #endif
2541         } else { /* ind_tbl->type == MLX5_IND_TBL_TYPE_DEVX */
2542                 hrxq->tir = tir;
2543 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2544                 hrxq->action = mlx5_glue->dv_create_flow_action_dest_devx_tir
2545                                                         (hrxq->tir->obj);
2546                 if (!hrxq->action) {
2547                         rte_errno = errno;
2548                         goto error;
2549                 }
2550 #endif
2551         }
2552         hrxq->rss_key_len = rss_key_len;
2553         hrxq->hash_fields = hash_fields;
2554         memcpy(hrxq->rss_key, rss_key, rss_key_len);
2555         rte_atomic32_inc(&hrxq->refcnt);
2556         LIST_INSERT_HEAD(&priv->hrxqs, hrxq, next);
2557         return hrxq;
2558 error:
2559         err = rte_errno; /* Save rte_errno before cleanup. */
2560         mlx5_ind_table_obj_release(dev, ind_tbl);
2561         if (qp)
2562                 claim_zero(mlx5_glue->destroy_qp(qp));
2563         else if (tir)
2564                 claim_zero(mlx5_devx_cmd_destroy(tir));
2565         rte_errno = err; /* Restore rte_errno. */
2566         return NULL;
2567 }
2568
2569 /**
2570  * Get an Rx Hash queue.
2571  *
2572  * @param dev
2573  *   Pointer to Ethernet device.
2574  * @param rss_conf
2575  *   RSS configuration for the Rx hash queue.
2576  * @param queues
2577  *   Queues entering in hash queue. In case of empty hash_fields only the
2578  *   first queue index will be taken for the indirection table.
2579  * @param queues_n
2580  *   Number of queues.
2581  *
2582  * @return
2583  *   An hash Rx queue on success.
2584  */
2585 struct mlx5_hrxq *
2586 mlx5_hrxq_get(struct rte_eth_dev *dev,
2587               const uint8_t *rss_key, uint32_t rss_key_len,
2588               uint64_t hash_fields,
2589               const uint16_t *queues, uint32_t queues_n)
2590 {
2591         struct mlx5_priv *priv = dev->data->dev_private;
2592         struct mlx5_hrxq *hrxq;
2593
2594         queues_n = hash_fields ? queues_n : 1;
2595         LIST_FOREACH(hrxq, &priv->hrxqs, next) {
2596                 struct mlx5_ind_table_obj *ind_tbl;
2597
2598                 if (hrxq->rss_key_len != rss_key_len)
2599                         continue;
2600                 if (memcmp(hrxq->rss_key, rss_key, rss_key_len))
2601                         continue;
2602                 if (hrxq->hash_fields != hash_fields)
2603                         continue;
2604                 ind_tbl = mlx5_ind_table_obj_get(dev, queues, queues_n);
2605                 if (!ind_tbl)
2606                         continue;
2607                 if (ind_tbl != hrxq->ind_table) {
2608                         mlx5_ind_table_obj_release(dev, ind_tbl);
2609                         continue;
2610                 }
2611                 rte_atomic32_inc(&hrxq->refcnt);
2612                 return hrxq;
2613         }
2614         return NULL;
2615 }
2616
2617 /**
2618  * Release the hash Rx queue.
2619  *
2620  * @param dev
2621  *   Pointer to Ethernet device.
2622  * @param hrxq
2623  *   Pointer to Hash Rx queue to release.
2624  *
2625  * @return
2626  *   1 while a reference on it exists, 0 when freed.
2627  */
2628 int
2629 mlx5_hrxq_release(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq)
2630 {
2631         if (rte_atomic32_dec_and_test(&hrxq->refcnt)) {
2632 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2633                 mlx5_glue->destroy_flow_action(hrxq->action);
2634 #endif
2635                 if (hrxq->ind_table->type == MLX5_IND_TBL_TYPE_IBV)
2636                         claim_zero(mlx5_glue->destroy_qp(hrxq->qp));
2637                 else /* hrxq->ind_table->type == MLX5_IND_TBL_TYPE_DEVX */
2638                         claim_zero(mlx5_devx_cmd_destroy(hrxq->tir));
2639                 mlx5_ind_table_obj_release(dev, hrxq->ind_table);
2640                 LIST_REMOVE(hrxq, next);
2641                 rte_free(hrxq);
2642                 return 0;
2643         }
2644         claim_nonzero(mlx5_ind_table_obj_release(dev, hrxq->ind_table));
2645         return 1;
2646 }
2647
2648 /**
2649  * Verify the Rx Queue list is empty
2650  *
2651  * @param dev
2652  *   Pointer to Ethernet device.
2653  *
2654  * @return
2655  *   The number of object not released.
2656  */
2657 int
2658 mlx5_hrxq_verify(struct rte_eth_dev *dev)
2659 {
2660         struct mlx5_priv *priv = dev->data->dev_private;
2661         struct mlx5_hrxq *hrxq;
2662         int ret = 0;
2663
2664         LIST_FOREACH(hrxq, &priv->hrxqs, next) {
2665                 DRV_LOG(DEBUG,
2666                         "port %u hash Rx queue %p still referenced",
2667                         dev->data->port_id, (void *)hrxq);
2668                 ++ret;
2669         }
2670         return ret;
2671 }
2672
2673 /**
2674  * Create a drop Rx queue Verbs/DevX object.
2675  *
2676  * @param dev
2677  *   Pointer to Ethernet device.
2678  *
2679  * @return
2680  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2681  */
2682 static struct mlx5_rxq_obj *
2683 mlx5_rxq_obj_drop_new(struct rte_eth_dev *dev)
2684 {
2685         struct mlx5_priv *priv = dev->data->dev_private;
2686         struct ibv_context *ctx = priv->sh->ctx;
2687         struct ibv_cq *cq;
2688         struct ibv_wq *wq = NULL;
2689         struct mlx5_rxq_obj *rxq;
2690
2691         if (priv->drop_queue.rxq)
2692                 return priv->drop_queue.rxq;
2693         cq = mlx5_glue->create_cq(ctx, 1, NULL, NULL, 0);
2694         if (!cq) {
2695                 DEBUG("port %u cannot allocate CQ for drop queue",
2696                       dev->data->port_id);
2697                 rte_errno = errno;
2698                 goto error;
2699         }
2700         wq = mlx5_glue->create_wq(ctx,
2701                  &(struct ibv_wq_init_attr){
2702                         .wq_type = IBV_WQT_RQ,
2703                         .max_wr = 1,
2704                         .max_sge = 1,
2705                         .pd = priv->sh->pd,
2706                         .cq = cq,
2707                  });
2708         if (!wq) {
2709                 DEBUG("port %u cannot allocate WQ for drop queue",
2710                       dev->data->port_id);
2711                 rte_errno = errno;
2712                 goto error;
2713         }
2714         rxq = rte_calloc(__func__, 1, sizeof(*rxq), 0);
2715         if (!rxq) {
2716                 DEBUG("port %u cannot allocate drop Rx queue memory",
2717                       dev->data->port_id);
2718                 rte_errno = ENOMEM;
2719                 goto error;
2720         }
2721         rxq->cq = cq;
2722         rxq->wq = wq;
2723         priv->drop_queue.rxq = rxq;
2724         return rxq;
2725 error:
2726         if (wq)
2727                 claim_zero(mlx5_glue->destroy_wq(wq));
2728         if (cq)
2729                 claim_zero(mlx5_glue->destroy_cq(cq));
2730         return NULL;
2731 }
2732
2733 /**
2734  * Release a drop Rx queue Verbs/DevX object.
2735  *
2736  * @param dev
2737  *   Pointer to Ethernet device.
2738  *
2739  * @return
2740  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2741  */
2742 static void
2743 mlx5_rxq_obj_drop_release(struct rte_eth_dev *dev)
2744 {
2745         struct mlx5_priv *priv = dev->data->dev_private;
2746         struct mlx5_rxq_obj *rxq = priv->drop_queue.rxq;
2747
2748         if (rxq->wq)
2749                 claim_zero(mlx5_glue->destroy_wq(rxq->wq));
2750         if (rxq->cq)
2751                 claim_zero(mlx5_glue->destroy_cq(rxq->cq));
2752         rte_free(rxq);
2753         priv->drop_queue.rxq = NULL;
2754 }
2755
2756 /**
2757  * Create a drop indirection table.
2758  *
2759  * @param dev
2760  *   Pointer to Ethernet device.
2761  *
2762  * @return
2763  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2764  */
2765 static struct mlx5_ind_table_obj *
2766 mlx5_ind_table_obj_drop_new(struct rte_eth_dev *dev)
2767 {
2768         struct mlx5_priv *priv = dev->data->dev_private;
2769         struct mlx5_ind_table_obj *ind_tbl;
2770         struct mlx5_rxq_obj *rxq;
2771         struct mlx5_ind_table_obj tmpl;
2772
2773         rxq = mlx5_rxq_obj_drop_new(dev);
2774         if (!rxq)
2775                 return NULL;
2776         tmpl.ind_table = mlx5_glue->create_rwq_ind_table
2777                 (priv->sh->ctx,
2778                  &(struct ibv_rwq_ind_table_init_attr){
2779                         .log_ind_tbl_size = 0,
2780                         .ind_tbl = &rxq->wq,
2781                         .comp_mask = 0,
2782                  });
2783         if (!tmpl.ind_table) {
2784                 DEBUG("port %u cannot allocate indirection table for drop"
2785                       " queue",
2786                       dev->data->port_id);
2787                 rte_errno = errno;
2788                 goto error;
2789         }
2790         ind_tbl = rte_calloc(__func__, 1, sizeof(*ind_tbl), 0);
2791         if (!ind_tbl) {
2792                 rte_errno = ENOMEM;
2793                 goto error;
2794         }
2795         ind_tbl->ind_table = tmpl.ind_table;
2796         return ind_tbl;
2797 error:
2798         mlx5_rxq_obj_drop_release(dev);
2799         return NULL;
2800 }
2801
2802 /**
2803  * Release a drop indirection table.
2804  *
2805  * @param dev
2806  *   Pointer to Ethernet device.
2807  */
2808 static void
2809 mlx5_ind_table_obj_drop_release(struct rte_eth_dev *dev)
2810 {
2811         struct mlx5_priv *priv = dev->data->dev_private;
2812         struct mlx5_ind_table_obj *ind_tbl = priv->drop_queue.hrxq->ind_table;
2813
2814         claim_zero(mlx5_glue->destroy_rwq_ind_table(ind_tbl->ind_table));
2815         mlx5_rxq_obj_drop_release(dev);
2816         rte_free(ind_tbl);
2817         priv->drop_queue.hrxq->ind_table = NULL;
2818 }
2819
2820 /**
2821  * Create a drop Rx Hash queue.
2822  *
2823  * @param dev
2824  *   Pointer to Ethernet device.
2825  *
2826  * @return
2827  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2828  */
2829 struct mlx5_hrxq *
2830 mlx5_hrxq_drop_new(struct rte_eth_dev *dev)
2831 {
2832         struct mlx5_priv *priv = dev->data->dev_private;
2833         struct mlx5_ind_table_obj *ind_tbl = NULL;
2834         struct ibv_qp *qp = NULL;
2835         struct mlx5_hrxq *hrxq = NULL;
2836
2837         if (priv->drop_queue.hrxq) {
2838                 rte_atomic32_inc(&priv->drop_queue.hrxq->refcnt);
2839                 return priv->drop_queue.hrxq;
2840         }
2841         hrxq = rte_calloc(__func__, 1, sizeof(*hrxq), 0);
2842         if (!hrxq) {
2843                 DRV_LOG(WARNING,
2844                         "port %u cannot allocate memory for drop queue",
2845                         dev->data->port_id);
2846                 rte_errno = ENOMEM;
2847                 goto error;
2848         }
2849         priv->drop_queue.hrxq = hrxq;
2850         ind_tbl = mlx5_ind_table_obj_drop_new(dev);
2851         if (!ind_tbl)
2852                 goto error;
2853         hrxq->ind_table = ind_tbl;
2854         qp = mlx5_glue->create_qp_ex(priv->sh->ctx,
2855                  &(struct ibv_qp_init_attr_ex){
2856                         .qp_type = IBV_QPT_RAW_PACKET,
2857                         .comp_mask =
2858                                 IBV_QP_INIT_ATTR_PD |
2859                                 IBV_QP_INIT_ATTR_IND_TABLE |
2860                                 IBV_QP_INIT_ATTR_RX_HASH,
2861                         .rx_hash_conf = (struct ibv_rx_hash_conf){
2862                                 .rx_hash_function =
2863                                         IBV_RX_HASH_FUNC_TOEPLITZ,
2864                                 .rx_hash_key_len = MLX5_RSS_HASH_KEY_LEN,
2865                                 .rx_hash_key = rss_hash_default_key,
2866                                 .rx_hash_fields_mask = 0,
2867                                 },
2868                         .rwq_ind_tbl = ind_tbl->ind_table,
2869                         .pd = priv->sh->pd
2870                  });
2871         if (!qp) {
2872                 DEBUG("port %u cannot allocate QP for drop queue",
2873                       dev->data->port_id);
2874                 rte_errno = errno;
2875                 goto error;
2876         }
2877         hrxq->qp = qp;
2878 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2879         hrxq->action = mlx5_glue->dv_create_flow_action_dest_ibv_qp(hrxq->qp);
2880         if (!hrxq->action) {
2881                 rte_errno = errno;
2882                 goto error;
2883         }
2884 #endif
2885         rte_atomic32_set(&hrxq->refcnt, 1);
2886         return hrxq;
2887 error:
2888 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2889         if (hrxq && hrxq->action)
2890                 mlx5_glue->destroy_flow_action(hrxq->action);
2891 #endif
2892         if (qp)
2893                 claim_zero(mlx5_glue->destroy_qp(hrxq->qp));
2894         if (ind_tbl)
2895                 mlx5_ind_table_obj_drop_release(dev);
2896         if (hrxq) {
2897                 priv->drop_queue.hrxq = NULL;
2898                 rte_free(hrxq);
2899         }
2900         return NULL;
2901 }
2902
2903 /**
2904  * Release a drop hash Rx queue.
2905  *
2906  * @param dev
2907  *   Pointer to Ethernet device.
2908  */
2909 void
2910 mlx5_hrxq_drop_release(struct rte_eth_dev *dev)
2911 {
2912         struct mlx5_priv *priv = dev->data->dev_private;
2913         struct mlx5_hrxq *hrxq = priv->drop_queue.hrxq;
2914
2915         if (rte_atomic32_dec_and_test(&hrxq->refcnt)) {
2916 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2917                 mlx5_glue->destroy_flow_action(hrxq->action);
2918 #endif
2919                 claim_zero(mlx5_glue->destroy_qp(hrxq->qp));
2920                 mlx5_ind_table_obj_drop_release(dev);
2921                 rte_free(hrxq);
2922                 priv->drop_queue.hrxq = NULL;
2923         }
2924 }