drivers/net/mlx5/mlx5_rxq.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <stddef.h>
   7 #include <errno.h>
   8 #include <string.h>
   9 #include <stdint.h>
  10 #include <fcntl.h>
  11 #include <sys/queue.h>
  12
  13 #include <rte_mbuf.h>
  14 #include <rte_malloc.h>
  15 #include <rte_ethdev_driver.h>
  16 #include <rte_common.h>
  17 #include <rte_interrupts.h>
  18 #include <rte_debug.h>
  19 #include <rte_io.h>
  20 #include <rte_eal_paging.h>
  21
  22 #include <mlx5_glue.h>
  23 #include <mlx5_devx_cmds.h>
  24 #include <mlx5_malloc.h>
  25
  26 #include "mlx5_defs.h"
  27 #include "mlx5.h"
  28 #include "mlx5_common_os.h"
  29 #include "mlx5_rxtx.h"
  30 #include "mlx5_utils.h"
  31 #include "mlx5_autoconf.h"
  32 #include "mlx5_flow.h"
  33
  34
  35 /* Default RSS hash key also used for ConnectX-3. */
  36 uint8_t rss_hash_default_key[] = {
  37         0x2c, 0xc6, 0x81, 0xd1,
  38         0x5b, 0xdb, 0xf4, 0xf7,
  39         0xfc, 0xa2, 0x83, 0x19,
  40         0xdb, 0x1a, 0x3e, 0x94,
  41         0x6b, 0x9e, 0x38, 0xd9,
  42         0x2c, 0x9c, 0x03, 0xd1,
  43         0xad, 0x99, 0x44, 0xa7,
  44         0xd9, 0x56, 0x3d, 0x59,
  45         0x06, 0x3c, 0x25, 0xf3,
  46         0xfc, 0x1f, 0xdc, 0x2a,
  47 };
  48
  49 /* Length of the default RSS hash key. */
  50 static_assert(MLX5_RSS_HASH_KEY_LEN ==
  51               (unsigned int)sizeof(rss_hash_default_key),
  52               "wrong RSS default key size.");
  53
  54 /**
  55  * Check whether Multi-Packet RQ can be enabled for the device.
  56  *
  57  * @param dev
  58  *   Pointer to Ethernet device.
  59  *
  60  * @return
  61  *   1 if supported, negative errno value if not.
  62  */
  63 inline int
  64 mlx5_check_mprq_support(struct rte_eth_dev *dev)
  65 {
  66         struct mlx5_priv *priv = dev->data->dev_private;
  67
  68         if (priv->config.mprq.enabled &&
  69             priv->rxqs_n >= priv->config.mprq.min_rxqs_num)
  70                 return 1;
  71         return -ENOTSUP;
  72 }
  73
  74 /**
  75  * Check whether Multi-Packet RQ is enabled for the Rx queue.
  76  *
  77  *  @param rxq
  78  *     Pointer to receive queue structure.
  79  *
  80  * @return
  81  *   0 if disabled, otherwise enabled.
  82  */
  83 inline int
  84 mlx5_rxq_mprq_enabled(struct mlx5_rxq_data *rxq)
  85 {
  86         return rxq->strd_num_n > 0;
  87 }
  88
  89 /**
  90  * Check whether Multi-Packet RQ is enabled for the device.
  91  *
  92  * @param dev
  93  *   Pointer to Ethernet device.
  94  *
  95  * @return
  96  *   0 if disabled, otherwise enabled.
  97  */
  98 inline int
  99 mlx5_mprq_enabled(struct rte_eth_dev *dev)
 100 {
 101         struct mlx5_priv *priv = dev->data->dev_private;
 102         uint32_t i;
 103         uint16_t n = 0;
 104         uint16_t n_ibv = 0;
 105
 106         if (mlx5_check_mprq_support(dev) < 0)
 107                 return 0;
 108         /* All the configured queues should be enabled. */
 109         for (i = 0; i < priv->rxqs_n; ++i) {
 110                 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
 111                 struct mlx5_rxq_ctrl *rxq_ctrl = container_of
 112                         (rxq, struct mlx5_rxq_ctrl, rxq);
 113
 114                 if (rxq == NULL || rxq_ctrl->type != MLX5_RXQ_TYPE_STANDARD)
 115                         continue;
 116                 n_ibv++;
 117                 if (mlx5_rxq_mprq_enabled(rxq))
 118                         ++n;
 119         }
 120         /* Multi-Packet RQ can't be partially configured. */
 121         MLX5_ASSERT(n == 0 || n == n_ibv);
 122         return n == n_ibv;
 123 }
 124
 125 /**
 126  * Allocate RX queue elements for Multi-Packet RQ.
 127  *
 128  * @param rxq_ctrl
 129  *   Pointer to RX queue structure.
 130  *
 131  * @return
 132  *   0 on success, a negative errno value otherwise and rte_errno is set.
 133  */
 134 static int
 135 rxq_alloc_elts_mprq(struct mlx5_rxq_ctrl *rxq_ctrl)
 136 {
 137         struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
 138         unsigned int wqe_n = 1 << rxq->elts_n;
 139         unsigned int i;
 140         int err;
 141
 142         /* Iterate on segments. */
 143         for (i = 0; i <= wqe_n; ++i) {
 144                 struct mlx5_mprq_buf *buf;
 145
 146                 if (rte_mempool_get(rxq->mprq_mp, (void **)&buf) < 0) {
 147                         DRV_LOG(ERR, "port %u empty mbuf pool", rxq->port_id);
 148                         rte_errno = ENOMEM;
 149                         goto error;
 150                 }
 151                 if (i < wqe_n)
 152                         (*rxq->mprq_bufs)[i] = buf;
 153                 else
 154                         rxq->mprq_repl = buf;
 155         }
 156         DRV_LOG(DEBUG,
 157                 "port %u Rx queue %u allocated and configured %u segments",
 158                 rxq->port_id, rxq->idx, wqe_n);
 159         return 0;
 160 error:
 161         err = rte_errno; /* Save rte_errno before cleanup. */
 162         wqe_n = i;
 163         for (i = 0; (i != wqe_n); ++i) {
 164                 if ((*rxq->mprq_bufs)[i] != NULL)
 165                         rte_mempool_put(rxq->mprq_mp,
 166                                         (*rxq->mprq_bufs)[i]);
 167                 (*rxq->mprq_bufs)[i] = NULL;
 168         }
 169         DRV_LOG(DEBUG, "port %u Rx queue %u failed, freed everything",
 170                 rxq->port_id, rxq->idx);
 171         rte_errno = err; /* Restore rte_errno. */
 172         return -rte_errno;
 173 }
 174
 175 /**
 176  * Allocate RX queue elements for Single-Packet RQ.
 177  *
 178  * @param rxq_ctrl
 179  *   Pointer to RX queue structure.
 180  *
 181  * @return
 182  *   0 on success, errno value on failure.
 183  */
 184 static int
 185 rxq_alloc_elts_sprq(struct mlx5_rxq_ctrl *rxq_ctrl)
 186 {
 187         const unsigned int sges_n = 1 << rxq_ctrl->rxq.sges_n;
 188         unsigned int elts_n = 1 << rxq_ctrl->rxq.elts_n;
 189         unsigned int i;
 190         int err;
 191
 192         /* Iterate on segments. */
 193         for (i = 0; (i != elts_n); ++i) {
 194                 struct rte_mbuf *buf;
 195
 196                 buf = rte_pktmbuf_alloc(rxq_ctrl->rxq.mp);
 197                 if (buf == NULL) {
 198                         DRV_LOG(ERR, "port %u empty mbuf pool",
 199                                 PORT_ID(rxq_ctrl->priv));
 200                         rte_errno = ENOMEM;
 201                         goto error;
 202                 }
 203                 /* Headroom is reserved by rte_pktmbuf_alloc(). */
 204                 MLX5_ASSERT(DATA_OFF(buf) == RTE_PKTMBUF_HEADROOM);
 205                 /* Buffer is supposed to be empty. */
 206                 MLX5_ASSERT(rte_pktmbuf_data_len(buf) == 0);
 207                 MLX5_ASSERT(rte_pktmbuf_pkt_len(buf) == 0);
 208                 MLX5_ASSERT(!buf->next);
 209                 /* Only the first segment keeps headroom. */
 210                 if (i % sges_n)
 211                         SET_DATA_OFF(buf, 0);
 212                 PORT(buf) = rxq_ctrl->rxq.port_id;
 213                 DATA_LEN(buf) = rte_pktmbuf_tailroom(buf);
 214                 PKT_LEN(buf) = DATA_LEN(buf);
 215                 NB_SEGS(buf) = 1;
 216                 (*rxq_ctrl->rxq.elts)[i] = buf;
 217         }
 218         /* If Rx vector is activated. */
 219         if (mlx5_rxq_check_vec_support(&rxq_ctrl->rxq) > 0) {
 220                 struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
 221                 struct rte_mbuf *mbuf_init = &rxq->fake_mbuf;
 222                 struct rte_pktmbuf_pool_private *priv =
 223                         (struct rte_pktmbuf_pool_private *)
 224                                 rte_mempool_get_priv(rxq_ctrl->rxq.mp);
 225                 int j;
 226
 227                 /* Initialize default rearm_data for vPMD. */
 228                 mbuf_init->data_off = RTE_PKTMBUF_HEADROOM;
 229                 rte_mbuf_refcnt_set(mbuf_init, 1);
 230                 mbuf_init->nb_segs = 1;
 231                 mbuf_init->port = rxq->port_id;
 232                 if (priv->flags & RTE_PKTMBUF_POOL_F_PINNED_EXT_BUF)
 233                         mbuf_init->ol_flags = EXT_ATTACHED_MBUF;
 234                 /*
 235                  * prevent compiler reordering:
 236                  * rearm_data covers previous fields.
 237                  */
 238                 rte_compiler_barrier();
 239                 rxq->mbuf_initializer =
 240                         *(rte_xmm_t *)&mbuf_init->rearm_data;
 241                 /* Padding with a fake mbuf for vectorized Rx. */
 242                 for (j = 0; j < MLX5_VPMD_DESCS_PER_LOOP; ++j)
 243                         (*rxq->elts)[elts_n + j] = &rxq->fake_mbuf;
 244         }
 245         DRV_LOG(DEBUG,
 246                 "port %u Rx queue %u allocated and configured %u segments"
 247                 " (max %u packets)",
 248                 PORT_ID(rxq_ctrl->priv), rxq_ctrl->rxq.idx, elts_n,
 249                 elts_n / (1 << rxq_ctrl->rxq.sges_n));
 250         return 0;
 251 error:
 252         err = rte_errno; /* Save rte_errno before cleanup. */
 253         elts_n = i;
 254         for (i = 0; (i != elts_n); ++i) {
 255                 if ((*rxq_ctrl->rxq.elts)[i] != NULL)
 256                         rte_pktmbuf_free_seg((*rxq_ctrl->rxq.elts)[i]);
 257                 (*rxq_ctrl->rxq.elts)[i] = NULL;
 258         }
 259         DRV_LOG(DEBUG, "port %u Rx queue %u failed, freed everything",
 260                 PORT_ID(rxq_ctrl->priv), rxq_ctrl->rxq.idx);
 261         rte_errno = err; /* Restore rte_errno. */
 262         return -rte_errno;
 263 }
 264
 265 /**
 266  * Allocate RX queue elements.
 267  *
 268  * @param rxq_ctrl
 269  *   Pointer to RX queue structure.
 270  *
 271  * @return
 272  *   0 on success, errno value on failure.
 273  */
 274 int
 275 rxq_alloc_elts(struct mlx5_rxq_ctrl *rxq_ctrl)
 276 {
 277         return mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq) ?
 278                rxq_alloc_elts_mprq(rxq_ctrl) : rxq_alloc_elts_sprq(rxq_ctrl);
 279 }
 280
 281 /**
 282  * Free RX queue elements for Multi-Packet RQ.
 283  *
 284  * @param rxq_ctrl
 285  *   Pointer to RX queue structure.
 286  */
 287 static void
 288 rxq_free_elts_mprq(struct mlx5_rxq_ctrl *rxq_ctrl)
 289 {
 290         struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
 291         uint16_t i;
 292
 293         DRV_LOG(DEBUG, "port %u Multi-Packet Rx queue %u freeing WRs",
 294                 rxq->port_id, rxq->idx);
 295         if (rxq->mprq_bufs == NULL)
 296                 return;
 297         MLX5_ASSERT(mlx5_rxq_check_vec_support(rxq) < 0);
 298         for (i = 0; (i != (1u << rxq->elts_n)); ++i) {
 299                 if ((*rxq->mprq_bufs)[i] != NULL)
 300                         mlx5_mprq_buf_free((*rxq->mprq_bufs)[i]);
 301                 (*rxq->mprq_bufs)[i] = NULL;
 302         }
 303         if (rxq->mprq_repl != NULL) {
 304                 mlx5_mprq_buf_free(rxq->mprq_repl);
 305                 rxq->mprq_repl = NULL;
 306         }
 307 }
 308
 309 /**
 310  * Free RX queue elements for Single-Packet RQ.
 311  *
 312  * @param rxq_ctrl
 313  *   Pointer to RX queue structure.
 314  */
 315 static void
 316 rxq_free_elts_sprq(struct mlx5_rxq_ctrl *rxq_ctrl)
 317 {
 318         struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
 319         const uint16_t q_n = (1 << rxq->elts_n);
 320         const uint16_t q_mask = q_n - 1;
 321         uint16_t used = q_n - (rxq->rq_ci - rxq->rq_pi);
 322         uint16_t i;
 323
 324         DRV_LOG(DEBUG, "port %u Rx queue %u freeing WRs",
 325                 PORT_ID(rxq_ctrl->priv), rxq->idx);
 326         if (rxq->elts == NULL)
 327                 return;
 328         /**
 329          * Some mbuf in the Ring belongs to the application.  They cannot be
 330          * freed.
 331          */
 332         if (mlx5_rxq_check_vec_support(rxq) > 0) {
 333                 for (i = 0; i < used; ++i)
 334                         (*rxq->elts)[(rxq->rq_ci + i) & q_mask] = NULL;
 335                 rxq->rq_pi = rxq->rq_ci;
 336         }
 337         for (i = 0; (i != (1u << rxq->elts_n)); ++i) {
 338                 if ((*rxq->elts)[i] != NULL)
 339                         rte_pktmbuf_free_seg((*rxq->elts)[i]);
 340                 (*rxq->elts)[i] = NULL;
 341         }
 342 }
 343
 344 /**
 345  * Free RX queue elements.
 346  *
 347  * @param rxq_ctrl
 348  *   Pointer to RX queue structure.
 349  */
 350 void
 351 rxq_free_elts(struct mlx5_rxq_ctrl *rxq_ctrl)
 352 {
 353         if (mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq))
 354                 rxq_free_elts_mprq(rxq_ctrl);
 355         else
 356                 rxq_free_elts_sprq(rxq_ctrl);
 357 }
 358
 359 /**
 360  * Returns the per-queue supported offloads.
 361  *
 362  * @param dev
 363  *   Pointer to Ethernet device.
 364  *
 365  * @return
 366  *   Supported Rx offloads.
 367  */
 368 uint64_t
 369 mlx5_get_rx_queue_offloads(struct rte_eth_dev *dev)
 370 {
 371         struct mlx5_priv *priv = dev->data->dev_private;
 372         struct mlx5_dev_config *config = &priv->config;
 373         uint64_t offloads = (DEV_RX_OFFLOAD_SCATTER |
 374                              DEV_RX_OFFLOAD_TIMESTAMP |
 375                              DEV_RX_OFFLOAD_JUMBO_FRAME |
 376                              DEV_RX_OFFLOAD_RSS_HASH);
 377
 378         if (config->hw_fcs_strip)
 379                 offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
 380
 381         if (config->hw_csum)
 382                 offloads |= (DEV_RX_OFFLOAD_IPV4_CKSUM |
 383                              DEV_RX_OFFLOAD_UDP_CKSUM |
 384                              DEV_RX_OFFLOAD_TCP_CKSUM);
 385         if (config->hw_vlan_strip)
 386                 offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
 387         if (MLX5_LRO_SUPPORTED(dev))
 388                 offloads |= DEV_RX_OFFLOAD_TCP_LRO;
 389         return offloads;
 390 }
 391
 392
 393 /**
 394  * Returns the per-port supported offloads.
 395  *
 396  * @return
 397  *   Supported Rx offloads.
 398  */
 399 uint64_t
 400 mlx5_get_rx_port_offloads(void)
 401 {
 402         uint64_t offloads = DEV_RX_OFFLOAD_VLAN_FILTER;
 403
 404         return offloads;
 405 }
 406
 407 /**
 408  * Verify if the queue can be released.
 409  *
 410  * @param dev
 411  *   Pointer to Ethernet device.
 412  * @param idx
 413  *   RX queue index.
 414  *
 415  * @return
 416  *   1 if the queue can be released
 417  *   0 if the queue can not be released, there are references to it.
 418  *   Negative errno and rte_errno is set if queue doesn't exist.
 419  */
 420 static int
 421 mlx5_rxq_releasable(struct rte_eth_dev *dev, uint16_t idx)
 422 {
 423         struct mlx5_priv *priv = dev->data->dev_private;
 424         struct mlx5_rxq_ctrl *rxq_ctrl;
 425
 426         if (!(*priv->rxqs)[idx]) {
 427                 rte_errno = EINVAL;
 428                 return -rte_errno;
 429         }
 430         rxq_ctrl = container_of((*priv->rxqs)[idx], struct mlx5_rxq_ctrl, rxq);
 431         return (rte_atomic32_read(&rxq_ctrl->refcnt) == 1);
 432 }
 433
 434 /* Fetches and drops all SW-owned and error CQEs to synchronize CQ. */
 435 static void
 436 rxq_sync_cq(struct mlx5_rxq_data *rxq)
 437 {
 438         const uint16_t cqe_n = 1 << rxq->cqe_n;
 439         const uint16_t cqe_mask = cqe_n - 1;
 440         volatile struct mlx5_cqe *cqe;
 441         int ret, i;
 442
 443         i = cqe_n;
 444         do {
 445                 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_mask];
 446                 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
 447                 if (ret == MLX5_CQE_STATUS_HW_OWN)
 448                         break;
 449                 if (ret == MLX5_CQE_STATUS_ERR) {
 450                         rxq->cq_ci++;
 451                         continue;
 452                 }
 453                 MLX5_ASSERT(ret == MLX5_CQE_STATUS_SW_OWN);
 454                 if (MLX5_CQE_FORMAT(cqe->op_own) != MLX5_COMPRESSED) {
 455                         rxq->cq_ci++;
 456                         continue;
 457                 }
 458                 /* Compute the next non compressed CQE. */
 459                 rxq->cq_ci += rte_be_to_cpu_32(cqe->byte_cnt);
 460
 461         } while (--i);
 462         /* Move all CQEs to HW ownership, including possible MiniCQEs. */
 463         for (i = 0; i < cqe_n; i++) {
 464                 cqe = &(*rxq->cqes)[i];
 465                 cqe->op_own = MLX5_CQE_INVALIDATE;
 466         }
 467         /* Resync CQE and WQE (WQ in RESET state). */
 468         rte_cio_wmb();
 469         *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
 470         rte_cio_wmb();
 471         *rxq->rq_db = rte_cpu_to_be_32(0);
 472         rte_cio_wmb();
 473 }
 474
 475 /**
 476  * Rx queue stop. Device queue goes to the RESET state,
 477  * all involved mbufs are freed from WQ.
 478  *
 479  * @param dev
 480  *   Pointer to Ethernet device structure.
 481  * @param idx
 482  *   RX queue index.
 483  *
 484  * @return
 485  *   0 on success, a negative errno value otherwise and rte_errno is set.
 486  */
 487 int
 488 mlx5_rx_queue_stop_primary(struct rte_eth_dev *dev, uint16_t idx)
 489 {
 490         struct mlx5_priv *priv = dev->data->dev_private;
 491         struct mlx5_rxq_data *rxq = (*priv->rxqs)[idx];
 492         struct mlx5_rxq_ctrl *rxq_ctrl =
 493                         container_of(rxq, struct mlx5_rxq_ctrl, rxq);
 494         int ret;
 495
 496         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 497         if (rxq_ctrl->obj->type == MLX5_RXQ_OBJ_TYPE_IBV) {
 498                 struct ibv_wq_attr mod = {
 499                         .attr_mask = IBV_WQ_ATTR_STATE,
 500                         .wq_state = IBV_WQS_RESET,
 501                 };
 502
 503                 ret = mlx5_glue->modify_wq(rxq_ctrl->obj->wq, &mod);
 504         } else { /* rxq_ctrl->obj->type == MLX5_RXQ_OBJ_TYPE_DEVX_RQ. */
 505                 struct mlx5_devx_modify_rq_attr rq_attr;
 506
 507                 memset(&rq_attr, 0, sizeof(rq_attr));
 508                 rq_attr.rq_state = MLX5_RQC_STATE_RDY;
 509                 rq_attr.state = MLX5_RQC_STATE_RST;
 510                 ret = mlx5_devx_cmd_modify_rq(rxq_ctrl->obj->rq, &rq_attr);
 511         }
 512         if (ret) {
 513                 DRV_LOG(ERR, "Cannot change Rx WQ state to RESET:  %s",
 514                         strerror(errno));
 515                 rte_errno = errno;
 516                 return ret;
 517         }
 518         /* Remove all processes CQEs. */
 519         rxq_sync_cq(rxq);
 520         /* Free all involved mbufs. */
 521         rxq_free_elts(rxq_ctrl);
 522         /* Set the actual queue state. */
 523         dev->data->rx_queue_state[idx] = RTE_ETH_QUEUE_STATE_STOPPED;
 524         return 0;
 525 }
 526
 527 /**
 528  * Rx queue stop. Device queue goes to the RESET state,
 529  * all involved mbufs are freed from WQ.
 530  *
 531  * @param dev
 532  *   Pointer to Ethernet device structure.
 533  * @param idx
 534  *   RX queue index.
 535  *
 536  * @return
 537  *   0 on success, a negative errno value otherwise and rte_errno is set.
 538  */
 539 int
 540 mlx5_rx_queue_stop(struct rte_eth_dev *dev, uint16_t idx)
 541 {
 542         eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
 543         int ret;
 544
 545         if (dev->data->rx_queue_state[idx] == RTE_ETH_QUEUE_STATE_HAIRPIN) {
 546                 DRV_LOG(ERR, "Hairpin queue can't be stopped");
 547                 rte_errno = EINVAL;
 548                 return -EINVAL;
 549         }
 550         if (dev->data->rx_queue_state[idx] == RTE_ETH_QUEUE_STATE_STOPPED)
 551                 return 0;
 552         /*
 553          * Vectorized Rx burst requires the CQ and RQ indices
 554          * synchronized, that might be broken on RQ restart
 555          * and cause Rx malfunction, so queue stopping is
 556          * not supported if vectorized Rx burst is engaged.
 557          * The routine pointer depends on the process
 558          * type, should perform check there.
 559          */
 560         if (pkt_burst == mlx5_rx_burst) {
 561                 DRV_LOG(ERR, "Rx queue stop is not supported "
 562                         "for vectorized Rx");
 563                 rte_errno = EINVAL;
 564                 return -EINVAL;
 565         }
 566         if (rte_eal_process_type() ==  RTE_PROC_SECONDARY) {
 567                 ret = mlx5_mp_os_req_queue_control(dev, idx,
 568                                                    MLX5_MP_REQ_QUEUE_RX_STOP);
 569         } else {
 570                 ret = mlx5_rx_queue_stop_primary(dev, idx);
 571         }
 572         return ret;
 573 }
 574
 575 /**
 576  * Rx queue start. Device queue goes to the ready state,
 577  * all required mbufs are allocated and WQ is replenished.
 578  *
 579  * @param dev
 580  *   Pointer to Ethernet device structure.
 581  * @param idx
 582  *   RX queue index.
 583  *
 584  * @return
 585  *   0 on success, a negative errno value otherwise and rte_errno is set.
 586  */
 587 int
 588 mlx5_rx_queue_start_primary(struct rte_eth_dev *dev, uint16_t idx)
 589 {
 590         struct mlx5_priv *priv = dev->data->dev_private;
 591         struct mlx5_rxq_data *rxq = (*priv->rxqs)[idx];
 592         struct mlx5_rxq_ctrl *rxq_ctrl =
 593                         container_of(rxq, struct mlx5_rxq_ctrl, rxq);
 594         int ret;
 595
 596         MLX5_ASSERT(rte_eal_process_type() ==  RTE_PROC_PRIMARY);
 597         /* Allocate needed buffers. */
 598         ret = rxq_alloc_elts(rxq_ctrl);
 599         if (ret) {
 600                 DRV_LOG(ERR, "Cannot reallocate buffers for Rx WQ");
 601                 rte_errno = errno;
 602                 return ret;
 603         }
 604         rte_cio_wmb();
 605         *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
 606         rte_cio_wmb();
 607         /* Reset RQ consumer before moving queue to READY state. */
 608         *rxq->rq_db = rte_cpu_to_be_32(0);
 609         rte_cio_wmb();
 610         if (rxq_ctrl->obj->type == MLX5_RXQ_OBJ_TYPE_IBV) {
 611                 struct ibv_wq_attr mod = {
 612                         .attr_mask = IBV_WQ_ATTR_STATE,
 613                         .wq_state = IBV_WQS_RDY,
 614                 };
 615
 616                 ret = mlx5_glue->modify_wq(rxq_ctrl->obj->wq, &mod);
 617         } else { /* rxq_ctrl->obj->type == MLX5_RXQ_OBJ_TYPE_DEVX_RQ. */
 618                 struct mlx5_devx_modify_rq_attr rq_attr;
 619
 620                 memset(&rq_attr, 0, sizeof(rq_attr));
 621                 rq_attr.rq_state = MLX5_RQC_STATE_RST;
 622                 rq_attr.state = MLX5_RQC_STATE_RDY;
 623                 ret = mlx5_devx_cmd_modify_rq(rxq_ctrl->obj->rq, &rq_attr);
 624         }
 625         if (ret) {
 626                 DRV_LOG(ERR, "Cannot change Rx WQ state to READY:  %s",
 627                         strerror(errno));
 628                 rte_errno = errno;
 629                 return ret;
 630         }
 631         /* Reinitialize RQ - set WQEs. */
 632         mlx5_rxq_initialize(rxq);
 633         rxq->err_state = MLX5_RXQ_ERR_STATE_NO_ERROR;
 634         /* Set actual queue state. */
 635         dev->data->rx_queue_state[idx] = RTE_ETH_QUEUE_STATE_STARTED;
 636         return 0;
 637 }
 638
 639 /**
 640  * Rx queue start. Device queue goes to the ready state,
 641  * all required mbufs are allocated and WQ is replenished.
 642  *
 643  * @param dev
 644  *   Pointer to Ethernet device structure.
 645  * @param idx
 646  *   RX queue index.
 647  *
 648  * @return
 649  *   0 on success, a negative errno value otherwise and rte_errno is set.
 650  */
 651 int
 652 mlx5_rx_queue_start(struct rte_eth_dev *dev, uint16_t idx)
 653 {
 654         int ret;
 655
 656         if (dev->data->rx_queue_state[idx] == RTE_ETH_QUEUE_STATE_HAIRPIN) {
 657                 DRV_LOG(ERR, "Hairpin queue can't be started");
 658                 rte_errno = EINVAL;
 659                 return -EINVAL;
 660         }
 661         if (dev->data->rx_queue_state[idx] == RTE_ETH_QUEUE_STATE_STARTED)
 662                 return 0;
 663         if (rte_eal_process_type() ==  RTE_PROC_SECONDARY) {
 664                 ret = mlx5_mp_os_req_queue_control(dev, idx,
 665                                                    MLX5_MP_REQ_QUEUE_RX_START);
 666         } else {
 667                 ret = mlx5_rx_queue_start_primary(dev, idx);
 668         }
 669         return ret;
 670 }
 671
 672 /**
 673  * Rx queue presetup checks.
 674  *
 675  * @param dev
 676  *   Pointer to Ethernet device structure.
 677  * @param idx
 678  *   RX queue index.
 679  * @param desc
 680  *   Number of descriptors to configure in queue.
 681  *
 682  * @return
 683  *   0 on success, a negative errno value otherwise and rte_errno is set.
 684  */
 685 static int
 686 mlx5_rx_queue_pre_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t *desc)
 687 {
 688         struct mlx5_priv *priv = dev->data->dev_private;
 689
 690         if (!rte_is_power_of_2(*desc)) {
 691                 *desc = 1 << log2above(*desc);
 692                 DRV_LOG(WARNING,
 693                         "port %u increased number of descriptors in Rx queue %u"
 694                         " to the next power of two (%d)",
 695                         dev->data->port_id, idx, *desc);
 696         }
 697         DRV_LOG(DEBUG, "port %u configuring Rx queue %u for %u descriptors",
 698                 dev->data->port_id, idx, *desc);
 699         if (idx >= priv->rxqs_n) {
 700                 DRV_LOG(ERR, "port %u Rx queue index out of range (%u >= %u)",
 701                         dev->data->port_id, idx, priv->rxqs_n);
 702                 rte_errno = EOVERFLOW;
 703                 return -rte_errno;
 704         }
 705         if (!mlx5_rxq_releasable(dev, idx)) {
 706                 DRV_LOG(ERR, "port %u unable to release queue index %u",
 707                         dev->data->port_id, idx);
 708                 rte_errno = EBUSY;
 709                 return -rte_errno;
 710         }
 711         mlx5_rxq_release(dev, idx);
 712         return 0;
 713 }
 714
 715 /**
 716  *
 717  * @param dev
 718  *   Pointer to Ethernet device structure.
 719  * @param idx
 720  *   RX queue index.
 721  * @param desc
 722  *   Number of descriptors to configure in queue.
 723  * @param socket
 724  *   NUMA socket on which memory must be allocated.
 725  * @param[in] conf
 726  *   Thresholds parameters.
 727  * @param mp
 728  *   Memory pool for buffer allocations.
 729  *
 730  * @return
 731  *   0 on success, a negative errno value otherwise and rte_errno is set.
 732  */
 733 int
 734 mlx5_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
 735                     unsigned int socket, const struct rte_eth_rxconf *conf,
 736                     struct rte_mempool *mp)
 737 {
 738         struct mlx5_priv *priv = dev->data->dev_private;
 739         struct mlx5_rxq_data *rxq = (*priv->rxqs)[idx];
 740         struct mlx5_rxq_ctrl *rxq_ctrl =
 741                 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
 742         int res;
 743
 744         res = mlx5_rx_queue_pre_setup(dev, idx, &desc);
 745         if (res)
 746                 return res;
 747         rxq_ctrl = mlx5_rxq_new(dev, idx, desc, socket, conf, mp);
 748         if (!rxq_ctrl) {
 749                 DRV_LOG(ERR, "port %u unable to allocate queue index %u",
 750                         dev->data->port_id, idx);
 751                 rte_errno = ENOMEM;
 752                 return -rte_errno;
 753         }
 754         DRV_LOG(DEBUG, "port %u adding Rx queue %u to list",
 755                 dev->data->port_id, idx);
 756         (*priv->rxqs)[idx] = &rxq_ctrl->rxq;
 757         return 0;
 758 }
 759
 760 /**
 761  *
 762  * @param dev
 763  *   Pointer to Ethernet device structure.
 764  * @param idx
 765  *   RX queue index.
 766  * @param desc
 767  *   Number of descriptors to configure in queue.
 768  * @param hairpin_conf
 769  *   Hairpin configuration parameters.
 770  *
 771  * @return
 772  *   0 on success, a negative errno value otherwise and rte_errno is set.
 773  */
 774 int
 775 mlx5_rx_hairpin_queue_setup(struct rte_eth_dev *dev, uint16_t idx,
 776                             uint16_t desc,
 777                             const struct rte_eth_hairpin_conf *hairpin_conf)
 778 {
 779         struct mlx5_priv *priv = dev->data->dev_private;
 780         struct mlx5_rxq_data *rxq = (*priv->rxqs)[idx];
 781         struct mlx5_rxq_ctrl *rxq_ctrl =
 782                 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
 783         int res;
 784
 785         res = mlx5_rx_queue_pre_setup(dev, idx, &desc);
 786         if (res)
 787                 return res;
 788         if (hairpin_conf->peer_count != 1 ||
 789             hairpin_conf->peers[0].port != dev->data->port_id ||
 790             hairpin_conf->peers[0].queue >= priv->txqs_n) {
 791                 DRV_LOG(ERR, "port %u unable to setup hairpin queue index %u "
 792                         " invalid hairpind configuration", dev->data->port_id,
 793                         idx);
 794                 rte_errno = EINVAL;
 795                 return -rte_errno;
 796         }
 797         rxq_ctrl = mlx5_rxq_hairpin_new(dev, idx, desc, hairpin_conf);
 798         if (!rxq_ctrl) {
 799                 DRV_LOG(ERR, "port %u unable to allocate queue index %u",
 800                         dev->data->port_id, idx);
 801                 rte_errno = ENOMEM;
 802                 return -rte_errno;
 803         }
 804         DRV_LOG(DEBUG, "port %u adding Rx queue %u to list",
 805                 dev->data->port_id, idx);
 806         (*priv->rxqs)[idx] = &rxq_ctrl->rxq;
 807         return 0;
 808 }
 809
 810 /**
 811  * DPDK callback to release a RX queue.
 812  *
 813  * @param dpdk_rxq
 814  *   Generic RX queue pointer.
 815  */
 816 void
 817 mlx5_rx_queue_release(void *dpdk_rxq)
 818 {
 819         struct mlx5_rxq_data *rxq = (struct mlx5_rxq_data *)dpdk_rxq;
 820         struct mlx5_rxq_ctrl *rxq_ctrl;
 821         struct mlx5_priv *priv;
 822
 823         if (rxq == NULL)
 824                 return;
 825         rxq_ctrl = container_of(rxq, struct mlx5_rxq_ctrl, rxq);
 826         priv = rxq_ctrl->priv;
 827         if (!mlx5_rxq_releasable(ETH_DEV(priv), rxq_ctrl->rxq.idx))
 828                 rte_panic("port %u Rx queue %u is still used by a flow and"
 829                           " cannot be removed\n",
 830                           PORT_ID(priv), rxq->idx);
 831         mlx5_rxq_release(ETH_DEV(priv), rxq_ctrl->rxq.idx);
 832 }
 833
 834 /**
 835  * Allocate queue vector and fill epoll fd list for Rx interrupts.
 836  *
 837  * @param dev
 838  *   Pointer to Ethernet device.
 839  *
 840  * @return
 841  *   0 on success, a negative errno value otherwise and rte_errno is set.
 842  */
 843 int
 844 mlx5_rx_intr_vec_enable(struct rte_eth_dev *dev)
 845 {
 846         struct mlx5_priv *priv = dev->data->dev_private;
 847         unsigned int i;
 848         unsigned int rxqs_n = priv->rxqs_n;
 849         unsigned int n = RTE_MIN(rxqs_n, (uint32_t)RTE_MAX_RXTX_INTR_VEC_ID);
 850         unsigned int count = 0;
 851         struct rte_intr_handle *intr_handle = dev->intr_handle;
 852
 853         if (!dev->data->dev_conf.intr_conf.rxq)
 854                 return 0;
 855         mlx5_rx_intr_vec_disable(dev);
 856         intr_handle->intr_vec = mlx5_malloc(0,
 857                                 n * sizeof(intr_handle->intr_vec[0]),
 858                                 0, SOCKET_ID_ANY);
 859         if (intr_handle->intr_vec == NULL) {
 860                 DRV_LOG(ERR,
 861                         "port %u failed to allocate memory for interrupt"
 862                         " vector, Rx interrupts will not be supported",
 863                         dev->data->port_id);
 864                 rte_errno = ENOMEM;
 865                 return -rte_errno;
 866         }
 867         intr_handle->type = RTE_INTR_HANDLE_EXT;
 868         for (i = 0; i != n; ++i) {
 869                 /* This rxq obj must not be released in this function. */
 870                 struct mlx5_rxq_ctrl *rxq_ctrl = mlx5_rxq_get(dev, i);
 871                 struct mlx5_rxq_obj *rxq_obj = rxq_ctrl ? rxq_ctrl->obj : NULL;
 872                 int rc;
 873
 874                 /* Skip queues that cannot request interrupts. */
 875                 if (!rxq_obj || (!rxq_obj->ibv_channel &&
 876                                  !rxq_obj->devx_channel)) {
 877                         /* Use invalid intr_vec[] index to disable entry. */
 878                         intr_handle->intr_vec[i] =
 879                                 RTE_INTR_VEC_RXTX_OFFSET +
 880                                 RTE_MAX_RXTX_INTR_VEC_ID;
 881                         /* Decrease the rxq_ctrl's refcnt */
 882                         if (rxq_ctrl)
 883                                 mlx5_rxq_release(dev, i);
 884                         continue;
 885                 }
 886                 if (count >= RTE_MAX_RXTX_INTR_VEC_ID) {
 887                         DRV_LOG(ERR,
 888                                 "port %u too many Rx queues for interrupt"
 889                                 " vector size (%d), Rx interrupts cannot be"
 890                                 " enabled",
 891                                 dev->data->port_id, RTE_MAX_RXTX_INTR_VEC_ID);
 892                         mlx5_rx_intr_vec_disable(dev);
 893                         rte_errno = ENOMEM;
 894                         return -rte_errno;
 895                 }
 896                 rc = mlx5_os_set_nonblock_channel_fd(rxq_obj->fd);
 897                 if (rc < 0) {
 898                         rte_errno = errno;
 899                         DRV_LOG(ERR,
 900                                 "port %u failed to make Rx interrupt file"
 901                                 " descriptor %d non-blocking for queue index"
 902                                 " %d",
 903                                 dev->data->port_id, rxq_obj->fd, i);
 904                         mlx5_rx_intr_vec_disable(dev);
 905                         return -rte_errno;
 906                 }
 907                 intr_handle->intr_vec[i] = RTE_INTR_VEC_RXTX_OFFSET + count;
 908                 intr_handle->efds[count] = rxq_obj->fd;
 909                 count++;
 910         }
 911         if (!count)
 912                 mlx5_rx_intr_vec_disable(dev);
 913         else
 914                 intr_handle->nb_efd = count;
 915         return 0;
 916 }
 917
 918 /**
 919  * Clean up Rx interrupts handler.
 920  *
 921  * @param dev
 922  *   Pointer to Ethernet device.
 923  */
 924 void
 925 mlx5_rx_intr_vec_disable(struct rte_eth_dev *dev)
 926 {
 927         struct mlx5_priv *priv = dev->data->dev_private;
 928         struct rte_intr_handle *intr_handle = dev->intr_handle;
 929         unsigned int i;
 930         unsigned int rxqs_n = priv->rxqs_n;
 931         unsigned int n = RTE_MIN(rxqs_n, (uint32_t)RTE_MAX_RXTX_INTR_VEC_ID);
 932
 933         if (!dev->data->dev_conf.intr_conf.rxq)
 934                 return;
 935         if (!intr_handle->intr_vec)
 936                 goto free;
 937         for (i = 0; i != n; ++i) {
 938                 if (intr_handle->intr_vec[i] == RTE_INTR_VEC_RXTX_OFFSET +
 939                     RTE_MAX_RXTX_INTR_VEC_ID)
 940                         continue;
 941                 /**
 942                  * Need to access directly the queue to release the reference
 943                  * kept in mlx5_rx_intr_vec_enable().
 944                  */
 945                 mlx5_rxq_release(dev, i);
 946         }
 947 free:
 948         rte_intr_free_epoll_fd(intr_handle);
 949         if (intr_handle->intr_vec)
 950                 mlx5_free(intr_handle->intr_vec);
 951         intr_handle->nb_efd = 0;
 952         intr_handle->intr_vec = NULL;
 953 }
 954
 955 /**
 956  *  MLX5 CQ notification .
 957  *
 958  *  @param rxq
 959  *     Pointer to receive queue structure.
 960  *  @param sq_n_rxq
 961  *     Sequence number per receive queue .
 962  */
 963 static inline void
 964 mlx5_arm_cq(struct mlx5_rxq_data *rxq, int sq_n_rxq)
 965 {
 966         int sq_n = 0;
 967         uint32_t doorbell_hi;
 968         uint64_t doorbell;
 969         void *cq_db_reg = (char *)rxq->cq_uar + MLX5_CQ_DOORBELL;
 970
 971         sq_n = sq_n_rxq & MLX5_CQ_SQN_MASK;
 972         doorbell_hi = sq_n << MLX5_CQ_SQN_OFFSET | (rxq->cq_ci & MLX5_CI_MASK);
 973         doorbell = (uint64_t)doorbell_hi << 32;
 974         doorbell |= rxq->cqn;
 975         rxq->cq_db[MLX5_CQ_ARM_DB] = rte_cpu_to_be_32(doorbell_hi);
 976         mlx5_uar_write64(rte_cpu_to_be_64(doorbell),
 977                          cq_db_reg, rxq->uar_lock_cq);
 978 }
 979
 980 /**
 981  * DPDK callback for Rx queue interrupt enable.
 982  *
 983  * @param dev
 984  *   Pointer to Ethernet device structure.
 985  * @param rx_queue_id
 986  *   Rx queue number.
 987  *
 988  * @return
 989  *   0 on success, a negative errno value otherwise and rte_errno is set.
 990  */
 991 int
 992 mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 993 {
 994         struct mlx5_rxq_ctrl *rxq_ctrl;
 995
 996         rxq_ctrl = mlx5_rxq_get(dev, rx_queue_id);
 997         if (!rxq_ctrl)
 998                 goto error;
 999         if (rxq_ctrl->irq) {
1000                 if (!rxq_ctrl->obj) {
1001                         mlx5_rxq_release(dev, rx_queue_id);
1002                         goto error;
1003                 }
1004                 mlx5_arm_cq(&rxq_ctrl->rxq, rxq_ctrl->rxq.cq_arm_sn);
1005         }
1006         mlx5_rxq_release(dev, rx_queue_id);
1007         return 0;
1008 error:
1009         rte_errno = EINVAL;
1010         return -rte_errno;
1011 }
1012
1013 /**
1014  * DPDK callback for Rx queue interrupt disable.
1015  *
1016  * @param dev
1017  *   Pointer to Ethernet device structure.
1018  * @param rx_queue_id
1019  *   Rx queue number.
1020  *
1021  * @return
1022  *   0 on success, a negative errno value otherwise and rte_errno is set.
1023  */
1024 int
1025 mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1026 {
1027         struct mlx5_priv *priv = dev->data->dev_private;
1028         struct mlx5_rxq_ctrl *rxq_ctrl;
1029         int ret = 0;
1030
1031         rxq_ctrl = mlx5_rxq_get(dev, rx_queue_id);
1032         if (!rxq_ctrl) {
1033                 rte_errno = EINVAL;
1034                 return -rte_errno;
1035         }
1036         if (!rxq_ctrl->obj)
1037                 goto error;
1038         if (rxq_ctrl->irq) {
1039                 ret = priv->obj_ops->rxq_event_get(rxq_ctrl->obj);
1040                 if (ret < 0)
1041                         goto error;
1042                 rxq_ctrl->rxq.cq_arm_sn++;
1043         }
1044         mlx5_rxq_release(dev, rx_queue_id);
1045         return 0;
1046 error:
1047         /**
1048          * The ret variable may be EAGAIN which means the get_event function was
1049          * called before receiving one.
1050          */
1051         if (ret < 0)
1052                 rte_errno = errno;
1053         else
1054                 rte_errno = EINVAL;
1055         ret = rte_errno; /* Save rte_errno before cleanup. */
1056         mlx5_rxq_release(dev, rx_queue_id);
1057         if (ret != EAGAIN)
1058                 DRV_LOG(WARNING, "port %u unable to disable interrupt on Rx queue %d",
1059                         dev->data->port_id, rx_queue_id);
1060         rte_errno = ret; /* Restore rte_errno. */
1061         return -rte_errno;
1062 }
1063
1064 /**
1065  * Verify the Rx queue objects list is empty
1066  *
1067  * @param dev
1068  *   Pointer to Ethernet device.
1069  *
1070  * @return
1071  *   The number of objects not released.
1072  */
1073 int
1074 mlx5_rxq_obj_verify(struct rte_eth_dev *dev)
1075 {
1076         struct mlx5_priv *priv = dev->data->dev_private;
1077         int ret = 0;
1078         struct mlx5_rxq_obj *rxq_obj;
1079
1080         LIST_FOREACH(rxq_obj, &priv->rxqsobj, next) {
1081                 DRV_LOG(DEBUG, "port %u Rx queue %u still referenced",
1082                         dev->data->port_id, rxq_obj->rxq_ctrl->rxq.idx);
1083                 ++ret;
1084         }
1085         return ret;
1086 }
1087
1088 /**
1089  * Callback function to initialize mbufs for Multi-Packet RQ.
1090  */
1091 static inline void
1092 mlx5_mprq_buf_init(struct rte_mempool *mp, void *opaque_arg,
1093                     void *_m, unsigned int i __rte_unused)
1094 {
1095         struct mlx5_mprq_buf *buf = _m;
1096         struct rte_mbuf_ext_shared_info *shinfo;
1097         unsigned int strd_n = (unsigned int)(uintptr_t)opaque_arg;
1098         unsigned int j;
1099
1100         memset(_m, 0, sizeof(*buf));
1101         buf->mp = mp;
1102         rte_atomic16_set(&buf->refcnt, 1);
1103         for (j = 0; j != strd_n; ++j) {
1104                 shinfo = &buf->shinfos[j];
1105                 shinfo->free_cb = mlx5_mprq_buf_free_cb;
1106                 shinfo->fcb_opaque = buf;
1107         }
1108 }
1109
1110 /**
1111  * Free mempool of Multi-Packet RQ.
1112  *
1113  * @param dev
1114  *   Pointer to Ethernet device.
1115  *
1116  * @return
1117  *   0 on success, negative errno value on failure.
1118  */
1119 int
1120 mlx5_mprq_free_mp(struct rte_eth_dev *dev)
1121 {
1122         struct mlx5_priv *priv = dev->data->dev_private;
1123         struct rte_mempool *mp = priv->mprq_mp;
1124         unsigned int i;
1125
1126         if (mp == NULL)
1127                 return 0;
1128         DRV_LOG(DEBUG, "port %u freeing mempool (%s) for Multi-Packet RQ",
1129                 dev->data->port_id, mp->name);
1130         /*
1131          * If a buffer in the pool has been externally attached to a mbuf and it
1132          * is still in use by application, destroying the Rx queue can spoil
1133          * the packet. It is unlikely to happen but if application dynamically
1134          * creates and destroys with holding Rx packets, this can happen.
1135          *
1136          * TODO: It is unavoidable for now because the mempool for Multi-Packet
1137          * RQ isn't provided by application but managed by PMD.
1138          */
1139         if (!rte_mempool_full(mp)) {
1140                 DRV_LOG(ERR,
1141                         "port %u mempool for Multi-Packet RQ is still in use",
1142                         dev->data->port_id);
1143                 rte_errno = EBUSY;
1144                 return -rte_errno;
1145         }
1146         rte_mempool_free(mp);
1147         /* Unset mempool for each Rx queue. */
1148         for (i = 0; i != priv->rxqs_n; ++i) {
1149                 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
1150
1151                 if (rxq == NULL)
1152                         continue;
1153                 rxq->mprq_mp = NULL;
1154         }
1155         priv->mprq_mp = NULL;
1156         return 0;
1157 }
1158
1159 /**
1160  * Allocate a mempool for Multi-Packet RQ. All configured Rx queues share the
1161  * mempool. If already allocated, reuse it if there're enough elements.
1162  * Otherwise, resize it.
1163  *
1164  * @param dev
1165  *   Pointer to Ethernet device.
1166  *
1167  * @return
1168  *   0 on success, negative errno value on failure.
1169  */
1170 int
1171 mlx5_mprq_alloc_mp(struct rte_eth_dev *dev)
1172 {
1173         struct mlx5_priv *priv = dev->data->dev_private;
1174         struct rte_mempool *mp = priv->mprq_mp;
1175         char name[RTE_MEMPOOL_NAMESIZE];
1176         unsigned int desc = 0;
1177         unsigned int buf_len;
1178         unsigned int obj_num;
1179         unsigned int obj_size;
1180         unsigned int strd_num_n = 0;
1181         unsigned int strd_sz_n = 0;
1182         unsigned int i;
1183         unsigned int n_ibv = 0;
1184
1185         if (!mlx5_mprq_enabled(dev))
1186                 return 0;
1187         /* Count the total number of descriptors configured. */
1188         for (i = 0; i != priv->rxqs_n; ++i) {
1189                 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
1190                 struct mlx5_rxq_ctrl *rxq_ctrl = container_of
1191                         (rxq, struct mlx5_rxq_ctrl, rxq);
1192
1193                 if (rxq == NULL || rxq_ctrl->type != MLX5_RXQ_TYPE_STANDARD)
1194                         continue;
1195                 n_ibv++;
1196                 desc += 1 << rxq->elts_n;
1197                 /* Get the max number of strides. */
1198                 if (strd_num_n < rxq->strd_num_n)
1199                         strd_num_n = rxq->strd_num_n;
1200                 /* Get the max size of a stride. */
1201                 if (strd_sz_n < rxq->strd_sz_n)
1202                         strd_sz_n = rxq->strd_sz_n;
1203         }
1204         MLX5_ASSERT(strd_num_n && strd_sz_n);
1205         buf_len = (1 << strd_num_n) * (1 << strd_sz_n);
1206         obj_size = sizeof(struct mlx5_mprq_buf) + buf_len + (1 << strd_num_n) *
1207                 sizeof(struct rte_mbuf_ext_shared_info) + RTE_PKTMBUF_HEADROOM;
1208         /*
1209          * Received packets can be either memcpy'd or externally referenced. In
1210          * case that the packet is attached to an mbuf as an external buffer, as
1211          * it isn't possible to predict how the buffers will be queued by
1212          * application, there's no option to exactly pre-allocate needed buffers
1213          * in advance but to speculatively prepares enough buffers.
1214          *
1215          * In the data path, if this Mempool is depleted, PMD will try to memcpy
1216          * received packets to buffers provided by application (rxq->mp) until
1217          * this Mempool gets available again.
1218          */
1219         desc *= 4;
1220         obj_num = desc + MLX5_MPRQ_MP_CACHE_SZ * n_ibv;
1221         /*
1222          * rte_mempool_create_empty() has sanity check to refuse large cache
1223          * size compared to the number of elements.
1224          * CACHE_FLUSHTHRESH_MULTIPLIER is defined in a C file, so using a
1225          * constant number 2 instead.
1226          */
1227         obj_num = RTE_MAX(obj_num, MLX5_MPRQ_MP_CACHE_SZ * 2);
1228         /* Check a mempool is already allocated and if it can be resued. */
1229         if (mp != NULL && mp->elt_size >= obj_size && mp->size >= obj_num) {
1230                 DRV_LOG(DEBUG, "port %u mempool %s is being reused",
1231                         dev->data->port_id, mp->name);
1232                 /* Reuse. */
1233                 goto exit;
1234         } else if (mp != NULL) {
1235                 DRV_LOG(DEBUG, "port %u mempool %s should be resized, freeing it",
1236                         dev->data->port_id, mp->name);
1237                 /*
1238                  * If failed to free, which means it may be still in use, no way
1239                  * but to keep using the existing one. On buffer underrun,
1240                  * packets will be memcpy'd instead of external buffer
1241                  * attachment.
1242                  */
1243                 if (mlx5_mprq_free_mp(dev)) {
1244                         if (mp->elt_size >= obj_size)
1245                                 goto exit;
1246                         else
1247                                 return -rte_errno;
1248                 }
1249         }
1250         snprintf(name, sizeof(name), "port-%u-mprq", dev->data->port_id);
1251         mp = rte_mempool_create(name, obj_num, obj_size, MLX5_MPRQ_MP_CACHE_SZ,
1252                                 0, NULL, NULL, mlx5_mprq_buf_init,
1253                                 (void *)(uintptr_t)(1 << strd_num_n),
1254                                 dev->device->numa_node, 0);
1255         if (mp == NULL) {
1256                 DRV_LOG(ERR,
1257                         "port %u failed to allocate a mempool for"
1258                         " Multi-Packet RQ, count=%u, size=%u",
1259                         dev->data->port_id, obj_num, obj_size);
1260                 rte_errno = ENOMEM;
1261                 return -rte_errno;
1262         }
1263         priv->mprq_mp = mp;
1264 exit:
1265         /* Set mempool for each Rx queue. */
1266         for (i = 0; i != priv->rxqs_n; ++i) {
1267                 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
1268                 struct mlx5_rxq_ctrl *rxq_ctrl = container_of
1269                         (rxq, struct mlx5_rxq_ctrl, rxq);
1270
1271                 if (rxq == NULL || rxq_ctrl->type != MLX5_RXQ_TYPE_STANDARD)
1272                         continue;
1273                 rxq->mprq_mp = mp;
1274         }
1275         DRV_LOG(INFO, "port %u Multi-Packet RQ is configured",
1276                 dev->data->port_id);
1277         return 0;
1278 }
1279
1280 #define MLX5_MAX_TCP_HDR_OFFSET ((unsigned int)(sizeof(struct rte_ether_hdr) + \
1281                                         sizeof(struct rte_vlan_hdr) * 2 + \
1282                                         sizeof(struct rte_ipv6_hdr)))
1283 #define MAX_TCP_OPTION_SIZE 40u
1284 #define MLX5_MAX_LRO_HEADER_FIX ((unsigned int)(MLX5_MAX_TCP_HDR_OFFSET + \
1285                                  sizeof(struct rte_tcp_hdr) + \
1286                                  MAX_TCP_OPTION_SIZE))
1287
1288 /**
1289  * Adjust the maximum LRO massage size.
1290  *
1291  * @param dev
1292  *   Pointer to Ethernet device.
1293  * @param idx
1294  *   RX queue index.
1295  * @param max_lro_size
1296  *   The maximum size for LRO packet.
1297  */
1298 static void
1299 mlx5_max_lro_msg_size_adjust(struct rte_eth_dev *dev, uint16_t idx,
1300                              uint32_t max_lro_size)
1301 {
1302         struct mlx5_priv *priv = dev->data->dev_private;
1303
1304         if (priv->config.hca_attr.lro_max_msg_sz_mode ==
1305             MLX5_LRO_MAX_MSG_SIZE_START_FROM_L4 && max_lro_size >
1306             MLX5_MAX_TCP_HDR_OFFSET)
1307                 max_lro_size -= MLX5_MAX_TCP_HDR_OFFSET;
1308         max_lro_size = RTE_MIN(max_lro_size, MLX5_MAX_LRO_SIZE);
1309         MLX5_ASSERT(max_lro_size >= MLX5_LRO_SEG_CHUNK_SIZE);
1310         max_lro_size /= MLX5_LRO_SEG_CHUNK_SIZE;
1311         if (priv->max_lro_msg_size)
1312                 priv->max_lro_msg_size =
1313                         RTE_MIN((uint32_t)priv->max_lro_msg_size, max_lro_size);
1314         else
1315                 priv->max_lro_msg_size = max_lro_size;
1316         DRV_LOG(DEBUG,
1317                 "port %u Rx Queue %u max LRO message size adjusted to %u bytes",
1318                 dev->data->port_id, idx,
1319                 priv->max_lro_msg_size * MLX5_LRO_SEG_CHUNK_SIZE);
1320 }
1321
1322 /**
1323  * Create a DPDK Rx queue.
1324  *
1325  * @param dev
1326  *   Pointer to Ethernet device.
1327  * @param idx
1328  *   RX queue index.
1329  * @param desc
1330  *   Number of descriptors to configure in queue.
1331  * @param socket
1332  *   NUMA socket on which memory must be allocated.
1333  *
1334  * @return
1335  *   A DPDK queue object on success, NULL otherwise and rte_errno is set.
1336  */
1337 struct mlx5_rxq_ctrl *
1338 mlx5_rxq_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1339              unsigned int socket, const struct rte_eth_rxconf *conf,
1340              struct rte_mempool *mp)
1341 {
1342         struct mlx5_priv *priv = dev->data->dev_private;
1343         struct mlx5_rxq_ctrl *tmpl;
1344         unsigned int mb_len = rte_pktmbuf_data_room_size(mp);
1345         unsigned int mprq_stride_nums;
1346         unsigned int mprq_stride_size;
1347         unsigned int mprq_stride_cap;
1348         struct mlx5_dev_config *config = &priv->config;
1349         /*
1350          * Always allocate extra slots, even if eventually
1351          * the vector Rx will not be used.
1352          */
1353         uint16_t desc_n =
1354                 desc + config->rx_vec_en * MLX5_VPMD_DESCS_PER_LOOP;
1355         uint64_t offloads = conf->offloads |
1356                            dev->data->dev_conf.rxmode.offloads;
1357         unsigned int lro_on_queue = !!(offloads & DEV_RX_OFFLOAD_TCP_LRO);
1358         const int mprq_en = mlx5_check_mprq_support(dev) > 0;
1359         unsigned int max_rx_pkt_len = lro_on_queue ?
1360                         dev->data->dev_conf.rxmode.max_lro_pkt_size :
1361                         dev->data->dev_conf.rxmode.max_rx_pkt_len;
1362         unsigned int non_scatter_min_mbuf_size = max_rx_pkt_len +
1363                                                         RTE_PKTMBUF_HEADROOM;
1364         unsigned int max_lro_size = 0;
1365         unsigned int first_mb_free_size = mb_len - RTE_PKTMBUF_HEADROOM;
1366
1367         if (non_scatter_min_mbuf_size > mb_len && !(offloads &
1368                                                     DEV_RX_OFFLOAD_SCATTER)) {
1369                 DRV_LOG(ERR, "port %u Rx queue %u: Scatter offload is not"
1370                         " configured and no enough mbuf space(%u) to contain "
1371                         "the maximum RX packet length(%u) with head-room(%u)",
1372                         dev->data->port_id, idx, mb_len, max_rx_pkt_len,
1373                         RTE_PKTMBUF_HEADROOM);
1374                 rte_errno = ENOSPC;
1375                 return NULL;
1376         }
1377         tmpl = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, sizeof(*tmpl) +
1378                            desc_n * sizeof(struct rte_mbuf *), 0, socket);
1379         if (!tmpl) {
1380                 rte_errno = ENOMEM;
1381                 return NULL;
1382         }
1383         tmpl->type = MLX5_RXQ_TYPE_STANDARD;
1384         if (mlx5_mr_btree_init(&tmpl->rxq.mr_ctrl.cache_bh,
1385                                MLX5_MR_BTREE_CACHE_N, socket)) {
1386                 /* rte_errno is already set. */
1387                 goto error;
1388         }
1389         tmpl->socket = socket;
1390         if (dev->data->dev_conf.intr_conf.rxq)
1391                 tmpl->irq = 1;
1392         mprq_stride_nums = config->mprq.stride_num_n ?
1393                 config->mprq.stride_num_n : MLX5_MPRQ_STRIDE_NUM_N;
1394         mprq_stride_size = non_scatter_min_mbuf_size <=
1395                 (1U << config->mprq.max_stride_size_n) ?
1396                 log2above(non_scatter_min_mbuf_size) : MLX5_MPRQ_STRIDE_SIZE_N;
1397         mprq_stride_cap = (config->mprq.stride_num_n ?
1398                 (1U << config->mprq.stride_num_n) : (1U << mprq_stride_nums)) *
1399                         (config->mprq.stride_size_n ?
1400                 (1U << config->mprq.stride_size_n) : (1U << mprq_stride_size));
1401         /*
1402          * This Rx queue can be configured as a Multi-Packet RQ if all of the
1403          * following conditions are met:
1404          *  - MPRQ is enabled.
1405          *  - The number of descs is more than the number of strides.
1406          *  - max_rx_pkt_len plus overhead is less than the max size
1407          *    of a stride or mprq_stride_size is specified by a user.
1408          *    Need to nake sure that there are enough stides to encap
1409          *    the maximum packet size in case mprq_stride_size is set.
1410          *  Otherwise, enable Rx scatter if necessary.
1411          */
1412         if (mprq_en && desc > (1U << mprq_stride_nums) &&
1413             (non_scatter_min_mbuf_size <=
1414              (1U << config->mprq.max_stride_size_n) ||
1415              (config->mprq.stride_size_n &&
1416               non_scatter_min_mbuf_size <= mprq_stride_cap))) {
1417                 /* TODO: Rx scatter isn't supported yet. */
1418                 tmpl->rxq.sges_n = 0;
1419                 /* Trim the number of descs needed. */
1420                 desc >>= mprq_stride_nums;
1421                 tmpl->rxq.strd_num_n = config->mprq.stride_num_n ?
1422                         config->mprq.stride_num_n : mprq_stride_nums;
1423                 tmpl->rxq.strd_sz_n = config->mprq.stride_size_n ?
1424                         config->mprq.stride_size_n : mprq_stride_size;
1425                 tmpl->rxq.strd_shift_en = MLX5_MPRQ_TWO_BYTE_SHIFT;
1426                 tmpl->rxq.strd_scatter_en =
1427                                 !!(offloads & DEV_RX_OFFLOAD_SCATTER);
1428                 tmpl->rxq.mprq_max_memcpy_len = RTE_MIN(first_mb_free_size,
1429                                 config->mprq.max_memcpy_len);
1430                 max_lro_size = RTE_MIN(max_rx_pkt_len,
1431                                        (1u << tmpl->rxq.strd_num_n) *
1432                                        (1u << tmpl->rxq.strd_sz_n));
1433                 DRV_LOG(DEBUG,
1434                         "port %u Rx queue %u: Multi-Packet RQ is enabled"
1435                         " strd_num_n = %u, strd_sz_n = %u",
1436                         dev->data->port_id, idx,
1437                         tmpl->rxq.strd_num_n, tmpl->rxq.strd_sz_n);
1438         } else if (max_rx_pkt_len <= first_mb_free_size) {
1439                 tmpl->rxq.sges_n = 0;
1440                 max_lro_size = max_rx_pkt_len;
1441         } else if (offloads & DEV_RX_OFFLOAD_SCATTER) {
1442                 unsigned int size = non_scatter_min_mbuf_size;
1443                 unsigned int sges_n;
1444
1445                 if (lro_on_queue && first_mb_free_size <
1446                     MLX5_MAX_LRO_HEADER_FIX) {
1447                         DRV_LOG(ERR, "Not enough space in the first segment(%u)"
1448                                 " to include the max header size(%u) for LRO",
1449                                 first_mb_free_size, MLX5_MAX_LRO_HEADER_FIX);
1450                         rte_errno = ENOTSUP;
1451                         goto error;
1452                 }
1453                 /*
1454                  * Determine the number of SGEs needed for a full packet
1455                  * and round it to the next power of two.
1456                  */
1457                 sges_n = log2above((size / mb_len) + !!(size % mb_len));
1458                 if (sges_n > MLX5_MAX_LOG_RQ_SEGS) {
1459                         DRV_LOG(ERR,
1460                                 "port %u too many SGEs (%u) needed to handle"
1461                                 " requested maximum packet size %u, the maximum"
1462                                 " supported are %u", dev->data->port_id,
1463                                 1 << sges_n, max_rx_pkt_len,
1464                                 1u << MLX5_MAX_LOG_RQ_SEGS);
1465                         rte_errno = ENOTSUP;
1466                         goto error;
1467                 }
1468                 tmpl->rxq.sges_n = sges_n;
1469                 max_lro_size = max_rx_pkt_len;
1470         }
1471         if (config->mprq.enabled && !mlx5_rxq_mprq_enabled(&tmpl->rxq))
1472                 DRV_LOG(WARNING,
1473                         "port %u MPRQ is requested but cannot be enabled\n"
1474                         " (requested: pkt_sz = %u, desc_num = %u,"
1475                         " rxq_num = %u, stride_sz = %u, stride_num = %u\n"
1476                         "  supported: min_rxqs_num = %u,"
1477                         " min_stride_sz = %u, max_stride_sz = %u).",
1478                         dev->data->port_id, non_scatter_min_mbuf_size,
1479                         desc, priv->rxqs_n,
1480                         config->mprq.stride_size_n ?
1481                                 (1U << config->mprq.stride_size_n) :
1482                                 (1U << mprq_stride_size),
1483                         config->mprq.stride_num_n ?
1484                                 (1U << config->mprq.stride_num_n) :
1485                                 (1U << mprq_stride_nums),
1486                         config->mprq.min_rxqs_num,
1487                         (1U << config->mprq.min_stride_size_n),
1488                         (1U << config->mprq.max_stride_size_n));
1489         DRV_LOG(DEBUG, "port %u maximum number of segments per packet: %u",
1490                 dev->data->port_id, 1 << tmpl->rxq.sges_n);
1491         if (desc % (1 << tmpl->rxq.sges_n)) {
1492                 DRV_LOG(ERR,
1493                         "port %u number of Rx queue descriptors (%u) is not a"
1494                         " multiple of SGEs per packet (%u)",
1495                         dev->data->port_id,
1496                         desc,
1497                         1 << tmpl->rxq.sges_n);
1498                 rte_errno = EINVAL;
1499                 goto error;
1500         }
1501         mlx5_max_lro_msg_size_adjust(dev, idx, max_lro_size);
1502         /* Toggle RX checksum offload if hardware supports it. */
1503         tmpl->rxq.csum = !!(offloads & DEV_RX_OFFLOAD_CHECKSUM);
1504         tmpl->rxq.hw_timestamp = !!(offloads & DEV_RX_OFFLOAD_TIMESTAMP);
1505         /* Configure VLAN stripping. */
1506         tmpl->rxq.vlan_strip = !!(offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
1507         /* By default, FCS (CRC) is stripped by hardware. */
1508         tmpl->rxq.crc_present = 0;
1509         tmpl->rxq.lro = lro_on_queue;
1510         if (offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
1511                 if (config->hw_fcs_strip) {
1512                         /*
1513                          * RQs used for LRO-enabled TIRs should not be
1514                          * configured to scatter the FCS.
1515                          */
1516                         if (lro_on_queue)
1517                                 DRV_LOG(WARNING,
1518                                         "port %u CRC stripping has been "
1519                                         "disabled but will still be performed "
1520                                         "by hardware, because LRO is enabled",
1521                                         dev->data->port_id);
1522                         else
1523                                 tmpl->rxq.crc_present = 1;
1524                 } else {
1525                         DRV_LOG(WARNING,
1526                                 "port %u CRC stripping has been disabled but will"
1527                                 " still be performed by hardware, make sure MLNX_OFED"
1528                                 " and firmware are up to date",
1529                                 dev->data->port_id);
1530                 }
1531         }
1532         DRV_LOG(DEBUG,
1533                 "port %u CRC stripping is %s, %u bytes will be subtracted from"
1534                 " incoming frames to hide it",
1535                 dev->data->port_id,
1536                 tmpl->rxq.crc_present ? "disabled" : "enabled",
1537                 tmpl->rxq.crc_present << 2);
1538         /* Save port ID. */
1539         tmpl->rxq.rss_hash = !!priv->rss_conf.rss_hf &&
1540                 (!!(dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS));
1541         tmpl->rxq.port_id = dev->data->port_id;
1542         tmpl->priv = priv;
1543         tmpl->rxq.mp = mp;
1544         tmpl->rxq.elts_n = log2above(desc);
1545         tmpl->rxq.rq_repl_thresh =
1546                 MLX5_VPMD_RXQ_RPLNSH_THRESH(1 << tmpl->rxq.elts_n);
1547         tmpl->rxq.elts =
1548                 (struct rte_mbuf *(*)[1 << tmpl->rxq.elts_n])(tmpl + 1);
1549 #ifndef RTE_ARCH_64
1550         tmpl->rxq.uar_lock_cq = &priv->sh->uar_lock_cq;
1551 #endif
1552         tmpl->rxq.idx = idx;
1553         rte_atomic32_inc(&tmpl->refcnt);
1554         LIST_INSERT_HEAD(&priv->rxqsctrl, tmpl, next);
1555         return tmpl;
1556 error:
1557         mlx5_free(tmpl);
1558         return NULL;
1559 }
1560
1561 /**
1562  * Create a DPDK Rx hairpin queue.
1563  *
1564  * @param dev
1565  *   Pointer to Ethernet device.
1566  * @param idx
1567  *   RX queue index.
1568  * @param desc
1569  *   Number of descriptors to configure in queue.
1570  * @param hairpin_conf
1571  *   The hairpin binding configuration.
1572  *
1573  * @return
1574  *   A DPDK queue object on success, NULL otherwise and rte_errno is set.
1575  */
1576 struct mlx5_rxq_ctrl *
1577 mlx5_rxq_hairpin_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1578                      const struct rte_eth_hairpin_conf *hairpin_conf)
1579 {
1580         struct mlx5_priv *priv = dev->data->dev_private;
1581         struct mlx5_rxq_ctrl *tmpl;
1582
1583         tmpl = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, sizeof(*tmpl), 0,
1584                            SOCKET_ID_ANY);
1585         if (!tmpl) {
1586                 rte_errno = ENOMEM;
1587                 return NULL;
1588         }
1589         tmpl->type = MLX5_RXQ_TYPE_HAIRPIN;
1590         tmpl->socket = SOCKET_ID_ANY;
1591         tmpl->rxq.rss_hash = 0;
1592         tmpl->rxq.port_id = dev->data->port_id;
1593         tmpl->priv = priv;
1594         tmpl->rxq.mp = NULL;
1595         tmpl->rxq.elts_n = log2above(desc);
1596         tmpl->rxq.elts = NULL;
1597         tmpl->rxq.mr_ctrl.cache_bh = (struct mlx5_mr_btree) { 0 };
1598         tmpl->hairpin_conf = *hairpin_conf;
1599         tmpl->rxq.idx = idx;
1600         rte_atomic32_inc(&tmpl->refcnt);
1601         LIST_INSERT_HEAD(&priv->rxqsctrl, tmpl, next);
1602         return tmpl;
1603 }
1604
1605 /**
1606  * Get a Rx queue.
1607  *
1608  * @param dev
1609  *   Pointer to Ethernet device.
1610  * @param idx
1611  *   RX queue index.
1612  *
1613  * @return
1614  *   A pointer to the queue if it exists, NULL otherwise.
1615  */
1616 struct mlx5_rxq_ctrl *
1617 mlx5_rxq_get(struct rte_eth_dev *dev, uint16_t idx)
1618 {
1619         struct mlx5_priv *priv = dev->data->dev_private;
1620         struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
1621         struct mlx5_rxq_ctrl *rxq_ctrl = NULL;
1622
1623         if (rxq_data) {
1624                 rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
1625                 rte_atomic32_inc(&rxq_ctrl->refcnt);
1626         }
1627         return rxq_ctrl;
1628 }
1629
1630 /**
1631  * Release a Rx queue.
1632  *
1633  * @param dev
1634  *   Pointer to Ethernet device.
1635  * @param idx
1636  *   RX queue index.
1637  *
1638  * @return
1639  *   1 while a reference on it exists, 0 when freed.
1640  */
1641 int
1642 mlx5_rxq_release(struct rte_eth_dev *dev, uint16_t idx)
1643 {
1644         struct mlx5_priv *priv = dev->data->dev_private;
1645         struct mlx5_rxq_ctrl *rxq_ctrl;
1646
1647         if (!(*priv->rxqs)[idx])
1648                 return 0;
1649         rxq_ctrl = container_of((*priv->rxqs)[idx], struct mlx5_rxq_ctrl, rxq);
1650         if (!rte_atomic32_dec_and_test(&rxq_ctrl->refcnt))
1651                 return 1;
1652         if (rxq_ctrl->obj) {
1653                 priv->obj_ops->rxq_obj_release(rxq_ctrl->obj);
1654                 rxq_ctrl->obj = NULL;
1655         }
1656         if (rxq_ctrl->type == MLX5_RXQ_TYPE_STANDARD)
1657                 mlx5_mr_btree_free(&rxq_ctrl->rxq.mr_ctrl.cache_bh);
1658         LIST_REMOVE(rxq_ctrl, next);
1659         mlx5_free(rxq_ctrl);
1660         (*priv->rxqs)[idx] = NULL;
1661         return 0;
1662 }
1663
1664 /**
1665  * Verify the Rx Queue list is empty
1666  *
1667  * @param dev
1668  *   Pointer to Ethernet device.
1669  *
1670  * @return
1671  *   The number of object not released.
1672  */
1673 int
1674 mlx5_rxq_verify(struct rte_eth_dev *dev)
1675 {
1676         struct mlx5_priv *priv = dev->data->dev_private;
1677         struct mlx5_rxq_ctrl *rxq_ctrl;
1678         int ret = 0;
1679
1680         LIST_FOREACH(rxq_ctrl, &priv->rxqsctrl, next) {
1681                 DRV_LOG(DEBUG, "port %u Rx Queue %u still referenced",
1682                         dev->data->port_id, rxq_ctrl->rxq.idx);
1683                 ++ret;
1684         }
1685         return ret;
1686 }
1687
1688 /**
1689  * Get a Rx queue type.
1690  *
1691  * @param dev
1692  *   Pointer to Ethernet device.
1693  * @param idx
1694  *   Rx queue index.
1695  *
1696  * @return
1697  *   The Rx queue type.
1698  */
1699 enum mlx5_rxq_type
1700 mlx5_rxq_get_type(struct rte_eth_dev *dev, uint16_t idx)
1701 {
1702         struct mlx5_priv *priv = dev->data->dev_private;
1703         struct mlx5_rxq_ctrl *rxq_ctrl = NULL;
1704
1705         if (idx < priv->rxqs_n && (*priv->rxqs)[idx]) {
1706                 rxq_ctrl = container_of((*priv->rxqs)[idx],
1707                                         struct mlx5_rxq_ctrl,
1708                                         rxq);
1709                 return rxq_ctrl->type;
1710         }
1711         return MLX5_RXQ_TYPE_UNDEFINED;
1712 }
1713
1714 /**
1715  * Create an indirection table.
1716  *
1717  * @param dev
1718  *   Pointer to Ethernet device.
1719  * @param queues
1720  *   Queues entering in the indirection table.
1721  * @param queues_n
1722  *   Number of queues in the array.
1723  *
1724  * @return
1725  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
1726  */
1727 static struct mlx5_ind_table_obj *
1728 mlx5_ind_table_obj_new(struct rte_eth_dev *dev, const uint16_t *queues,
1729                        uint32_t queues_n, enum mlx5_ind_tbl_type type)
1730 {
1731         struct mlx5_priv *priv = dev->data->dev_private;
1732         struct mlx5_ind_table_obj *ind_tbl;
1733         unsigned int i = 0, j = 0, k = 0;
1734
1735         ind_tbl = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ind_tbl) +
1736                               queues_n * sizeof(uint16_t), 0, SOCKET_ID_ANY);
1737         if (!ind_tbl) {
1738                 rte_errno = ENOMEM;
1739                 return NULL;
1740         }
1741         ind_tbl->type = type;
1742         if (ind_tbl->type == MLX5_IND_TBL_TYPE_IBV) {
1743                 const unsigned int wq_n = rte_is_power_of_2(queues_n) ?
1744                         log2above(queues_n) :
1745                         log2above(priv->config.ind_table_max_size);
1746                 struct ibv_wq *wq[1 << wq_n];
1747
1748                 for (i = 0; i != queues_n; ++i) {
1749                         struct mlx5_rxq_ctrl *rxq = mlx5_rxq_get(dev,
1750                                                                  queues[i]);
1751                         if (!rxq)
1752                                 goto error;
1753                         wq[i] = rxq->obj->wq;
1754                         ind_tbl->queues[i] = queues[i];
1755                 }
1756                 ind_tbl->queues_n = queues_n;
1757                 /* Finalise indirection table. */
1758                 k = i; /* Retain value of i for use in error case. */
1759                 for (j = 0; k != (unsigned int)(1 << wq_n); ++k, ++j)
1760                         wq[k] = wq[j];
1761                 ind_tbl->ind_table = mlx5_glue->create_rwq_ind_table
1762                         (priv->sh->ctx,
1763                          &(struct ibv_rwq_ind_table_init_attr){
1764                                 .log_ind_tbl_size = wq_n,
1765                                 .ind_tbl = wq,
1766                                 .comp_mask = 0,
1767                         });
1768                 if (!ind_tbl->ind_table) {
1769                         rte_errno = errno;
1770                         goto error;
1771                 }
1772         } else { /* ind_tbl->type == MLX5_IND_TBL_TYPE_DEVX */
1773                 struct mlx5_devx_rqt_attr *rqt_attr = NULL;
1774                 const unsigned int rqt_n =
1775                         1 << (rte_is_power_of_2(queues_n) ?
1776                               log2above(queues_n) :
1777                               log2above(priv->config.ind_table_max_size));
1778
1779                 rqt_attr = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rqt_attr) +
1780                                       rqt_n * sizeof(uint32_t), 0,
1781                                       SOCKET_ID_ANY);
1782                 if (!rqt_attr) {
1783                         DRV_LOG(ERR, "port %u cannot allocate RQT resources",
1784                                 dev->data->port_id);
1785                         rte_errno = ENOMEM;
1786                         goto error;
1787                 }
1788                 rqt_attr->rqt_max_size = priv->config.ind_table_max_size;
1789                 rqt_attr->rqt_actual_size = rqt_n;
1790                 for (i = 0; i != queues_n; ++i) {
1791                         struct mlx5_rxq_ctrl *rxq = mlx5_rxq_get(dev,
1792                                                                  queues[i]);
1793                         if (!rxq)
1794                                 goto error;
1795                         rqt_attr->rq_list[i] = rxq->obj->rq->id;
1796                         ind_tbl->queues[i] = queues[i];
1797                 }
1798                 k = i; /* Retain value of i for use in error case. */
1799                 for (j = 0; k != rqt_n; ++k, ++j)
1800                         rqt_attr->rq_list[k] = rqt_attr->rq_list[j];
1801                 ind_tbl->rqt = mlx5_devx_cmd_create_rqt(priv->sh->ctx,
1802                                                         rqt_attr);
1803                 mlx5_free(rqt_attr);
1804                 if (!ind_tbl->rqt) {
1805                         DRV_LOG(ERR, "port %u cannot create DevX RQT",
1806                                 dev->data->port_id);
1807                         rte_errno = errno;
1808                         goto error;
1809                 }
1810                 ind_tbl->queues_n = queues_n;
1811         }
1812         rte_atomic32_inc(&ind_tbl->refcnt);
1813         LIST_INSERT_HEAD(&priv->ind_tbls, ind_tbl, next);
1814         return ind_tbl;
1815 error:
1816         for (j = 0; j < i; j++)
1817                 mlx5_rxq_release(dev, ind_tbl->queues[j]);
1818         mlx5_free(ind_tbl);
1819         DEBUG("port %u cannot create indirection table", dev->data->port_id);
1820         return NULL;
1821 }
1822
1823 /**
1824  * Get an indirection table.
1825  *
1826  * @param dev
1827  *   Pointer to Ethernet device.
1828  * @param queues
1829  *   Queues entering in the indirection table.
1830  * @param queues_n
1831  *   Number of queues in the array.
1832  *
1833  * @return
1834  *   An indirection table if found.
1835  */
1836 static struct mlx5_ind_table_obj *
1837 mlx5_ind_table_obj_get(struct rte_eth_dev *dev, const uint16_t *queues,
1838                        uint32_t queues_n)
1839 {
1840         struct mlx5_priv *priv = dev->data->dev_private;
1841         struct mlx5_ind_table_obj *ind_tbl;
1842
1843         LIST_FOREACH(ind_tbl, &priv->ind_tbls, next) {
1844                 if ((ind_tbl->queues_n == queues_n) &&
1845                     (memcmp(ind_tbl->queues, queues,
1846                             ind_tbl->queues_n * sizeof(ind_tbl->queues[0]))
1847                      == 0))
1848                         break;
1849         }
1850         if (ind_tbl) {
1851                 unsigned int i;
1852
1853                 rte_atomic32_inc(&ind_tbl->refcnt);
1854                 for (i = 0; i != ind_tbl->queues_n; ++i)
1855                         mlx5_rxq_get(dev, ind_tbl->queues[i]);
1856         }
1857         return ind_tbl;
1858 }
1859
1860 /**
1861  * Release an indirection table.
1862  *
1863  * @param dev
1864  *   Pointer to Ethernet device.
1865  * @param ind_table
1866  *   Indirection table to release.
1867  *
1868  * @return
1869  *   1 while a reference on it exists, 0 when freed.
1870  */
1871 static int
1872 mlx5_ind_table_obj_release(struct rte_eth_dev *dev,
1873                            struct mlx5_ind_table_obj *ind_tbl)
1874 {
1875         unsigned int i;
1876
1877         if (rte_atomic32_dec_and_test(&ind_tbl->refcnt)) {
1878                 if (ind_tbl->type == MLX5_IND_TBL_TYPE_IBV)
1879                         claim_zero(mlx5_glue->destroy_rwq_ind_table
1880                                                         (ind_tbl->ind_table));
1881                 else if (ind_tbl->type == MLX5_IND_TBL_TYPE_DEVX)
1882                         claim_zero(mlx5_devx_cmd_destroy(ind_tbl->rqt));
1883         }
1884         for (i = 0; i != ind_tbl->queues_n; ++i)
1885                 claim_nonzero(mlx5_rxq_release(dev, ind_tbl->queues[i]));
1886         if (!rte_atomic32_read(&ind_tbl->refcnt)) {
1887                 LIST_REMOVE(ind_tbl, next);
1888                 mlx5_free(ind_tbl);
1889                 return 0;
1890         }
1891         return 1;
1892 }
1893
1894 /**
1895  * Verify the Rx Queue list is empty
1896  *
1897  * @param dev
1898  *   Pointer to Ethernet device.
1899  *
1900  * @return
1901  *   The number of object not released.
1902  */
1903 int
1904 mlx5_ind_table_obj_verify(struct rte_eth_dev *dev)
1905 {
1906         struct mlx5_priv *priv = dev->data->dev_private;
1907         struct mlx5_ind_table_obj *ind_tbl;
1908         int ret = 0;
1909
1910         LIST_FOREACH(ind_tbl, &priv->ind_tbls, next) {
1911                 DRV_LOG(DEBUG,
1912                         "port %u indirection table obj %p still referenced",
1913                         dev->data->port_id, (void *)ind_tbl);
1914                 ++ret;
1915         }
1916         return ret;
1917 }
1918
1919 /**
1920  * Create an Rx Hash queue.
1921  *
1922  * @param dev
1923  *   Pointer to Ethernet device.
1924  * @param rss_key
1925  *   RSS key for the Rx hash queue.
1926  * @param rss_key_len
1927  *   RSS key length.
1928  * @param hash_fields
1929  *   Verbs protocol hash field to make the RSS on.
1930  * @param queues
1931  *   Queues entering in hash queue. In case of empty hash_fields only the
1932  *   first queue index will be taken for the indirection table.
1933  * @param queues_n
1934  *   Number of queues.
1935  * @param tunnel
1936  *   Tunnel type.
1937  *
1938  * @return
1939  *   The Verbs/DevX object initialised index, 0 otherwise and rte_errno is set.
1940  */
1941 uint32_t
1942 mlx5_hrxq_new(struct rte_eth_dev *dev,
1943               const uint8_t *rss_key, uint32_t rss_key_len,
1944               uint64_t hash_fields,
1945               const uint16_t *queues, uint32_t queues_n,
1946               int tunnel __rte_unused)
1947 {
1948         struct mlx5_priv *priv = dev->data->dev_private;
1949         struct mlx5_hrxq *hrxq = NULL;
1950         uint32_t hrxq_idx = 0;
1951         struct ibv_qp *qp = NULL;
1952         struct mlx5_ind_table_obj *ind_tbl;
1953         int err;
1954         struct mlx5_devx_obj *tir = NULL;
1955         struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[queues[0]];
1956         struct mlx5_rxq_ctrl *rxq_ctrl =
1957                 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
1958
1959         queues_n = hash_fields ? queues_n : 1;
1960         ind_tbl = mlx5_ind_table_obj_get(dev, queues, queues_n);
1961         if (!ind_tbl) {
1962                 enum mlx5_ind_tbl_type type;
1963
1964                 type = rxq_ctrl->obj->type == MLX5_RXQ_OBJ_TYPE_IBV ?
1965                                 MLX5_IND_TBL_TYPE_IBV : MLX5_IND_TBL_TYPE_DEVX;
1966                 ind_tbl = mlx5_ind_table_obj_new(dev, queues, queues_n, type);
1967         }
1968         if (!ind_tbl) {
1969                 rte_errno = ENOMEM;
1970                 return 0;
1971         }
1972         if (ind_tbl->type == MLX5_IND_TBL_TYPE_IBV) {
1973 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
1974                 struct mlx5dv_qp_init_attr qp_init_attr;
1975
1976                 memset(&qp_init_attr, 0, sizeof(qp_init_attr));
1977                 if (tunnel) {
1978                         qp_init_attr.comp_mask =
1979                                 MLX5DV_QP_INIT_ATTR_MASK_QP_CREATE_FLAGS;
1980                         qp_init_attr.create_flags =
1981                                 MLX5DV_QP_CREATE_TUNNEL_OFFLOADS;
1982                 }
1983 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
1984                 if (dev->data->dev_conf.lpbk_mode) {
1985                         /*
1986                          * Allow packet sent from NIC loop back
1987                          * w/o source MAC check.
1988                          */
1989                         qp_init_attr.comp_mask |=
1990                                 MLX5DV_QP_INIT_ATTR_MASK_QP_CREATE_FLAGS;
1991                         qp_init_attr.create_flags |=
1992                                 MLX5DV_QP_CREATE_TIR_ALLOW_SELF_LOOPBACK_UC;
1993                 }
1994 #endif
1995                 qp = mlx5_glue->dv_create_qp
1996                         (priv->sh->ctx,
1997                          &(struct ibv_qp_init_attr_ex){
1998                                 .qp_type = IBV_QPT_RAW_PACKET,
1999                                 .comp_mask =
2000                                         IBV_QP_INIT_ATTR_PD |
2001                                         IBV_QP_INIT_ATTR_IND_TABLE |
2002                                         IBV_QP_INIT_ATTR_RX_HASH,
2003                                 .rx_hash_conf = (struct ibv_rx_hash_conf){
2004                                         .rx_hash_function =
2005                                                 IBV_RX_HASH_FUNC_TOEPLITZ,
2006                                         .rx_hash_key_len = rss_key_len,
2007                                         .rx_hash_key =
2008                                                 (void *)(uintptr_t)rss_key,
2009                                         .rx_hash_fields_mask = hash_fields,
2010                                 },
2011                                 .rwq_ind_tbl = ind_tbl->ind_table,
2012                                 .pd = priv->sh->pd,
2013                           },
2014                           &qp_init_attr);
2015 #else
2016                 qp = mlx5_glue->create_qp_ex
2017                         (priv->sh->ctx,
2018                          &(struct ibv_qp_init_attr_ex){
2019                                 .qp_type = IBV_QPT_RAW_PACKET,
2020                                 .comp_mask =
2021                                         IBV_QP_INIT_ATTR_PD |
2022                                         IBV_QP_INIT_ATTR_IND_TABLE |
2023                                         IBV_QP_INIT_ATTR_RX_HASH,
2024                                 .rx_hash_conf = (struct ibv_rx_hash_conf){
2025                                         .rx_hash_function =
2026                                                 IBV_RX_HASH_FUNC_TOEPLITZ,
2027                                         .rx_hash_key_len = rss_key_len,
2028                                         .rx_hash_key =
2029                                                 (void *)(uintptr_t)rss_key,
2030                                         .rx_hash_fields_mask = hash_fields,
2031                                 },
2032                                 .rwq_ind_tbl = ind_tbl->ind_table,
2033                                 .pd = priv->sh->pd,
2034                          });
2035 #endif
2036                 if (!qp) {
2037                         rte_errno = errno;
2038                         goto error;
2039                 }
2040         } else { /* ind_tbl->type == MLX5_IND_TBL_TYPE_DEVX */
2041                 struct mlx5_devx_tir_attr tir_attr;
2042                 uint32_t i;
2043                 uint32_t lro = 1;
2044
2045                 /* Enable TIR LRO only if all the queues were configured for. */
2046                 for (i = 0; i < queues_n; ++i) {
2047                         if (!(*priv->rxqs)[queues[i]]->lro) {
2048                                 lro = 0;
2049                                 break;
2050                         }
2051                 }
2052                 memset(&tir_attr, 0, sizeof(tir_attr));
2053                 tir_attr.disp_type = MLX5_TIRC_DISP_TYPE_INDIRECT;
2054                 tir_attr.rx_hash_fn = MLX5_RX_HASH_FN_TOEPLITZ;
2055                 tir_attr.tunneled_offload_en = !!tunnel;
2056                 /* If needed, translate hash_fields bitmap to PRM format. */
2057                 if (hash_fields) {
2058 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
2059                         struct mlx5_rx_hash_field_select *rx_hash_field_select =
2060                                         hash_fields & IBV_RX_HASH_INNER ?
2061                                         &tir_attr.rx_hash_field_selector_inner :
2062                                         &tir_attr.rx_hash_field_selector_outer;
2063 #else
2064                         struct mlx5_rx_hash_field_select *rx_hash_field_select =
2065                                         &tir_attr.rx_hash_field_selector_outer;
2066 #endif
2067
2068                         /* 1 bit: 0: IPv4, 1: IPv6. */
2069                         rx_hash_field_select->l3_prot_type =
2070                                 !!(hash_fields & MLX5_IPV6_IBV_RX_HASH);
2071                         /* 1 bit: 0: TCP, 1: UDP. */
2072                         rx_hash_field_select->l4_prot_type =
2073                                 !!(hash_fields & MLX5_UDP_IBV_RX_HASH);
2074                         /* Bitmask which sets which fields to use in RX Hash. */
2075                         rx_hash_field_select->selected_fields =
2076                         ((!!(hash_fields & MLX5_L3_SRC_IBV_RX_HASH)) <<
2077                          MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP) |
2078                         (!!(hash_fields & MLX5_L3_DST_IBV_RX_HASH)) <<
2079                          MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP |
2080                         (!!(hash_fields & MLX5_L4_SRC_IBV_RX_HASH)) <<
2081                          MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT |
2082                         (!!(hash_fields & MLX5_L4_DST_IBV_RX_HASH)) <<
2083                          MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT;
2084                 }
2085                 if (rxq_ctrl->obj->type == MLX5_RXQ_OBJ_TYPE_DEVX_HAIRPIN)
2086                         tir_attr.transport_domain = priv->sh->td->id;
2087                 else
2088                         tir_attr.transport_domain = priv->sh->tdn;
2089                 memcpy(tir_attr.rx_hash_toeplitz_key, rss_key,
2090                        MLX5_RSS_HASH_KEY_LEN);
2091                 tir_attr.indirect_table = ind_tbl->rqt->id;
2092                 if (dev->data->dev_conf.lpbk_mode)
2093                         tir_attr.self_lb_block =
2094                                         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
2095                 if (lro) {
2096                         tir_attr.lro_timeout_period_usecs =
2097                                         priv->config.lro.timeout;
2098                         tir_attr.lro_max_msg_sz = priv->max_lro_msg_size;
2099                         tir_attr.lro_enable_mask =
2100                                         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2101                                         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO;
2102                 }
2103                 tir = mlx5_devx_cmd_create_tir(priv->sh->ctx, &tir_attr);
2104                 if (!tir) {
2105                         DRV_LOG(ERR, "port %u cannot create DevX TIR",
2106                                 dev->data->port_id);
2107                         rte_errno = errno;
2108                         goto error;
2109                 }
2110         }
2111         hrxq = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_HRXQ], &hrxq_idx);
2112         if (!hrxq)
2113                 goto error;
2114         hrxq->ind_table = ind_tbl;
2115         if (ind_tbl->type == MLX5_IND_TBL_TYPE_IBV) {
2116                 hrxq->qp = qp;
2117 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2118                 hrxq->action =
2119                         mlx5_glue->dv_create_flow_action_dest_ibv_qp(hrxq->qp);
2120                 if (!hrxq->action) {
2121                         rte_errno = errno;
2122                         goto error;
2123                 }
2124 #endif
2125         } else { /* ind_tbl->type == MLX5_IND_TBL_TYPE_DEVX */
2126                 hrxq->tir = tir;
2127 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2128                 hrxq->action = mlx5_glue->dv_create_flow_action_dest_devx_tir
2129                                                         (hrxq->tir->obj);
2130                 if (!hrxq->action) {
2131                         rte_errno = errno;
2132                         goto error;
2133                 }
2134 #endif
2135         }
2136         hrxq->rss_key_len = rss_key_len;
2137         hrxq->hash_fields = hash_fields;
2138         memcpy(hrxq->rss_key, rss_key, rss_key_len);
2139         rte_atomic32_inc(&hrxq->refcnt);
2140         ILIST_INSERT(priv->sh->ipool[MLX5_IPOOL_HRXQ], &priv->hrxqs, hrxq_idx,
2141                      hrxq, next);
2142         return hrxq_idx;
2143 error:
2144         err = rte_errno; /* Save rte_errno before cleanup. */
2145         mlx5_ind_table_obj_release(dev, ind_tbl);
2146         if (qp)
2147                 claim_zero(mlx5_glue->destroy_qp(qp));
2148         else if (tir)
2149                 claim_zero(mlx5_devx_cmd_destroy(tir));
2150         if (hrxq)
2151                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_HRXQ], hrxq_idx);
2152         rte_errno = err; /* Restore rte_errno. */
2153         return 0;
2154 }
2155
2156 /**
2157  * Get an Rx Hash queue.
2158  *
2159  * @param dev
2160  *   Pointer to Ethernet device.
2161  * @param rss_conf
2162  *   RSS configuration for the Rx hash queue.
2163  * @param queues
2164  *   Queues entering in hash queue. In case of empty hash_fields only the
2165  *   first queue index will be taken for the indirection table.
2166  * @param queues_n
2167  *   Number of queues.
2168  *
2169  * @return
2170  *   An hash Rx queue index on success.
2171  */
2172 uint32_t
2173 mlx5_hrxq_get(struct rte_eth_dev *dev,
2174               const uint8_t *rss_key, uint32_t rss_key_len,
2175               uint64_t hash_fields,
2176               const uint16_t *queues, uint32_t queues_n)
2177 {
2178         struct mlx5_priv *priv = dev->data->dev_private;
2179         struct mlx5_hrxq *hrxq;
2180         uint32_t idx;
2181
2182         queues_n = hash_fields ? queues_n : 1;
2183         ILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_HRXQ], priv->hrxqs, idx,
2184                       hrxq, next) {
2185                 struct mlx5_ind_table_obj *ind_tbl;
2186
2187                 if (hrxq->rss_key_len != rss_key_len)
2188                         continue;
2189                 if (memcmp(hrxq->rss_key, rss_key, rss_key_len))
2190                         continue;
2191                 if (hrxq->hash_fields != hash_fields)
2192                         continue;
2193                 ind_tbl = mlx5_ind_table_obj_get(dev, queues, queues_n);
2194                 if (!ind_tbl)
2195                         continue;
2196                 if (ind_tbl != hrxq->ind_table) {
2197                         mlx5_ind_table_obj_release(dev, ind_tbl);
2198                         continue;
2199                 }
2200                 rte_atomic32_inc(&hrxq->refcnt);
2201                 return idx;
2202         }
2203         return 0;
2204 }
2205
2206 /**
2207  * Release the hash Rx queue.
2208  *
2209  * @param dev
2210  *   Pointer to Ethernet device.
2211  * @param hrxq
2212  *   Index to Hash Rx queue to release.
2213  *
2214  * @return
2215  *   1 while a reference on it exists, 0 when freed.
2216  */
2217 int
2218 mlx5_hrxq_release(struct rte_eth_dev *dev, uint32_t hrxq_idx)
2219 {
2220         struct mlx5_priv *priv = dev->data->dev_private;
2221         struct mlx5_hrxq *hrxq;
2222
2223         hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ], hrxq_idx);
2224         if (!hrxq)
2225                 return 0;
2226         if (rte_atomic32_dec_and_test(&hrxq->refcnt)) {
2227 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2228                 mlx5_glue->destroy_flow_action(hrxq->action);
2229 #endif
2230                 if (hrxq->ind_table->type == MLX5_IND_TBL_TYPE_IBV)
2231                         claim_zero(mlx5_glue->destroy_qp(hrxq->qp));
2232                 else /* hrxq->ind_table->type == MLX5_IND_TBL_TYPE_DEVX */
2233                         claim_zero(mlx5_devx_cmd_destroy(hrxq->tir));
2234                 mlx5_ind_table_obj_release(dev, hrxq->ind_table);
2235                 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_HRXQ], &priv->hrxqs,
2236                              hrxq_idx, hrxq, next);
2237                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_HRXQ], hrxq_idx);
2238                 return 0;
2239         }
2240         claim_nonzero(mlx5_ind_table_obj_release(dev, hrxq->ind_table));
2241         return 1;
2242 }
2243
2244 /**
2245  * Verify the Rx Queue list is empty
2246  *
2247  * @param dev
2248  *   Pointer to Ethernet device.
2249  *
2250  * @return
2251  *   The number of object not released.
2252  */
2253 int
2254 mlx5_hrxq_verify(struct rte_eth_dev *dev)
2255 {
2256         struct mlx5_priv *priv = dev->data->dev_private;
2257         struct mlx5_hrxq *hrxq;
2258         uint32_t idx;
2259         int ret = 0;
2260
2261         ILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_HRXQ], priv->hrxqs, idx,
2262                       hrxq, next) {
2263                 DRV_LOG(DEBUG,
2264                         "port %u hash Rx queue %p still referenced",
2265                         dev->data->port_id, (void *)hrxq);
2266                 ++ret;
2267         }
2268         return ret;
2269 }
2270
2271 /**
2272  * Create a drop Rx queue Verbs/DevX object.
2273  *
2274  * @param dev
2275  *   Pointer to Ethernet device.
2276  *
2277  * @return
2278  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2279  */
2280 static struct mlx5_rxq_obj *
2281 mlx5_rxq_obj_drop_new(struct rte_eth_dev *dev)
2282 {
2283         struct mlx5_priv *priv = dev->data->dev_private;
2284         struct ibv_context *ctx = priv->sh->ctx;
2285         struct ibv_cq *cq;
2286         struct ibv_wq *wq = NULL;
2287         struct mlx5_rxq_obj *rxq;
2288
2289         if (priv->drop_queue.rxq)
2290                 return priv->drop_queue.rxq;
2291         cq = mlx5_glue->create_cq(ctx, 1, NULL, NULL, 0);
2292         if (!cq) {
2293                 DEBUG("port %u cannot allocate CQ for drop queue",
2294                       dev->data->port_id);
2295                 rte_errno = errno;
2296                 goto error;
2297         }
2298         wq = mlx5_glue->create_wq(ctx,
2299                  &(struct ibv_wq_init_attr){
2300                         .wq_type = IBV_WQT_RQ,
2301                         .max_wr = 1,
2302                         .max_sge = 1,
2303                         .pd = priv->sh->pd,
2304                         .cq = cq,
2305                  });
2306         if (!wq) {
2307                 DEBUG("port %u cannot allocate WQ for drop queue",
2308                       dev->data->port_id);
2309                 rte_errno = errno;
2310                 goto error;
2311         }
2312         rxq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rxq), 0, SOCKET_ID_ANY);
2313         if (!rxq) {
2314                 DEBUG("port %u cannot allocate drop Rx queue memory",
2315                       dev->data->port_id);
2316                 rte_errno = ENOMEM;
2317                 goto error;
2318         }
2319         rxq->ibv_cq = cq;
2320         rxq->wq = wq;
2321         priv->drop_queue.rxq = rxq;
2322         return rxq;
2323 error:
2324         if (wq)
2325                 claim_zero(mlx5_glue->destroy_wq(wq));
2326         if (cq)
2327                 claim_zero(mlx5_glue->destroy_cq(cq));
2328         return NULL;
2329 }
2330
2331 /**
2332  * Release a drop Rx queue Verbs/DevX object.
2333  *
2334  * @param dev
2335  *   Pointer to Ethernet device.
2336  *
2337  * @return
2338  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2339  */
2340 static void
2341 mlx5_rxq_obj_drop_release(struct rte_eth_dev *dev)
2342 {
2343         struct mlx5_priv *priv = dev->data->dev_private;
2344         struct mlx5_rxq_obj *rxq = priv->drop_queue.rxq;
2345
2346         if (rxq->wq)
2347                 claim_zero(mlx5_glue->destroy_wq(rxq->wq));
2348         if (rxq->ibv_cq)
2349                 claim_zero(mlx5_glue->destroy_cq(rxq->ibv_cq));
2350         mlx5_free(rxq);
2351         priv->drop_queue.rxq = NULL;
2352 }
2353
2354 /**
2355  * Create a drop indirection table.
2356  *
2357  * @param dev
2358  *   Pointer to Ethernet device.
2359  *
2360  * @return
2361  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2362  */
2363 static struct mlx5_ind_table_obj *
2364 mlx5_ind_table_obj_drop_new(struct rte_eth_dev *dev)
2365 {
2366         struct mlx5_priv *priv = dev->data->dev_private;
2367         struct mlx5_ind_table_obj *ind_tbl;
2368         struct mlx5_rxq_obj *rxq;
2369         struct mlx5_ind_table_obj tmpl;
2370
2371         rxq = mlx5_rxq_obj_drop_new(dev);
2372         if (!rxq)
2373                 return NULL;
2374         tmpl.ind_table = mlx5_glue->create_rwq_ind_table
2375                 (priv->sh->ctx,
2376                  &(struct ibv_rwq_ind_table_init_attr){
2377                         .log_ind_tbl_size = 0,
2378                         .ind_tbl = (struct ibv_wq **)&rxq->wq,
2379                         .comp_mask = 0,
2380                  });
2381         if (!tmpl.ind_table) {
2382                 DEBUG("port %u cannot allocate indirection table for drop"
2383                       " queue",
2384                       dev->data->port_id);
2385                 rte_errno = errno;
2386                 goto error;
2387         }
2388         ind_tbl = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ind_tbl), 0,
2389                               SOCKET_ID_ANY);
2390         if (!ind_tbl) {
2391                 rte_errno = ENOMEM;
2392                 goto error;
2393         }
2394         ind_tbl->ind_table = tmpl.ind_table;
2395         return ind_tbl;
2396 error:
2397         mlx5_rxq_obj_drop_release(dev);
2398         return NULL;
2399 }
2400
2401 /**
2402  * Release a drop indirection table.
2403  *
2404  * @param dev
2405  *   Pointer to Ethernet device.
2406  */
2407 static void
2408 mlx5_ind_table_obj_drop_release(struct rte_eth_dev *dev)
2409 {
2410         struct mlx5_priv *priv = dev->data->dev_private;
2411         struct mlx5_ind_table_obj *ind_tbl = priv->drop_queue.hrxq->ind_table;
2412
2413         claim_zero(mlx5_glue->destroy_rwq_ind_table(ind_tbl->ind_table));
2414         mlx5_rxq_obj_drop_release(dev);
2415         mlx5_free(ind_tbl);
2416         priv->drop_queue.hrxq->ind_table = NULL;
2417 }
2418
2419 /**
2420  * Create a drop Rx Hash queue.
2421  *
2422  * @param dev
2423  *   Pointer to Ethernet device.
2424  *
2425  * @return
2426  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2427  */
2428 struct mlx5_hrxq *
2429 mlx5_hrxq_drop_new(struct rte_eth_dev *dev)
2430 {
2431         struct mlx5_priv *priv = dev->data->dev_private;
2432         struct mlx5_ind_table_obj *ind_tbl = NULL;
2433         struct ibv_qp *qp = NULL;
2434         struct mlx5_hrxq *hrxq = NULL;
2435
2436         if (priv->drop_queue.hrxq) {
2437                 rte_atomic32_inc(&priv->drop_queue.hrxq->refcnt);
2438                 return priv->drop_queue.hrxq;
2439         }
2440         hrxq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*hrxq), 0, SOCKET_ID_ANY);
2441         if (!hrxq) {
2442                 DRV_LOG(WARNING,
2443                         "port %u cannot allocate memory for drop queue",
2444                         dev->data->port_id);
2445                 rte_errno = ENOMEM;
2446                 goto error;
2447         }
2448         priv->drop_queue.hrxq = hrxq;
2449         ind_tbl = mlx5_ind_table_obj_drop_new(dev);
2450         if (!ind_tbl)
2451                 goto error;
2452         hrxq->ind_table = ind_tbl;
2453         qp = mlx5_glue->create_qp_ex(priv->sh->ctx,
2454                  &(struct ibv_qp_init_attr_ex){
2455                         .qp_type = IBV_QPT_RAW_PACKET,
2456                         .comp_mask =
2457                                 IBV_QP_INIT_ATTR_PD |
2458                                 IBV_QP_INIT_ATTR_IND_TABLE |
2459                                 IBV_QP_INIT_ATTR_RX_HASH,
2460                         .rx_hash_conf = (struct ibv_rx_hash_conf){
2461                                 .rx_hash_function =
2462                                         IBV_RX_HASH_FUNC_TOEPLITZ,
2463                                 .rx_hash_key_len = MLX5_RSS_HASH_KEY_LEN,
2464                                 .rx_hash_key = rss_hash_default_key,
2465                                 .rx_hash_fields_mask = 0,
2466                                 },
2467                         .rwq_ind_tbl = ind_tbl->ind_table,
2468                         .pd = priv->sh->pd
2469                  });
2470         if (!qp) {
2471                 DEBUG("port %u cannot allocate QP for drop queue",
2472                       dev->data->port_id);
2473                 rte_errno = errno;
2474                 goto error;
2475         }
2476         hrxq->qp = qp;
2477 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2478         hrxq->action = mlx5_glue->dv_create_flow_action_dest_ibv_qp(hrxq->qp);
2479         if (!hrxq->action) {
2480                 rte_errno = errno;
2481                 goto error;
2482         }
2483 #endif
2484         rte_atomic32_set(&hrxq->refcnt, 1);
2485         return hrxq;
2486 error:
2487 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2488         if (hrxq && hrxq->action)
2489                 mlx5_glue->destroy_flow_action(hrxq->action);
2490 #endif
2491         if (qp)
2492                 claim_zero(mlx5_glue->destroy_qp(hrxq->qp));
2493         if (ind_tbl)
2494                 mlx5_ind_table_obj_drop_release(dev);
2495         if (hrxq) {
2496                 priv->drop_queue.hrxq = NULL;
2497                 mlx5_free(hrxq);
2498         }
2499         return NULL;
2500 }
2501
2502 /**
2503  * Release a drop hash Rx queue.
2504  *
2505  * @param dev
2506  *   Pointer to Ethernet device.
2507  */
2508 void
2509 mlx5_hrxq_drop_release(struct rte_eth_dev *dev)
2510 {
2511         struct mlx5_priv *priv = dev->data->dev_private;
2512         struct mlx5_hrxq *hrxq = priv->drop_queue.hrxq;
2513
2514         if (rte_atomic32_dec_and_test(&hrxq->refcnt)) {
2515 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2516                 mlx5_glue->destroy_flow_action(hrxq->action);
2517 #endif
2518                 claim_zero(mlx5_glue->destroy_qp(hrxq->qp));
2519                 mlx5_ind_table_obj_drop_release(dev);
2520                 mlx5_free(hrxq);
2521                 priv->drop_queue.hrxq = NULL;
2522         }
2523 }
2524
2525
2526 /**
2527  * Set the Rx queue timestamp conversion parameters
2528  *
2529  * @param[in] dev
2530  *   Pointer to the Ethernet device structure.
2531  */
2532 void
2533 mlx5_rxq_timestamp_set(struct rte_eth_dev *dev)
2534 {
2535         struct mlx5_priv *priv = dev->data->dev_private;
2536         struct mlx5_dev_ctx_shared *sh = priv->sh;
2537         struct mlx5_rxq_data *data;
2538         unsigned int i;
2539
2540         for (i = 0; i != priv->rxqs_n; ++i) {
2541                 if (!(*priv->rxqs)[i])
2542                         continue;
2543                 data = (*priv->rxqs)[i];
2544                 data->sh = sh;
2545                 data->rt_timestamp = priv->config.rt_timestamp;
2546         }
2547 }