1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
11 #include <sys/queue.h>
14 #include <rte_malloc.h>
15 #include <ethdev_driver.h>
16 #include <rte_common.h>
17 #include <rte_interrupts.h>
18 #include <rte_debug.h>
20 #include <rte_eal_paging.h>
22 #include <mlx5_glue.h>
23 #include <mlx5_malloc.h>
25 #include "mlx5_defs.h"
29 #include "mlx5_utils.h"
30 #include "mlx5_autoconf.h"
33 /* Default RSS hash key also used for ConnectX-3. */
34 uint8_t rss_hash_default_key[] = {
35 0x2c, 0xc6, 0x81, 0xd1,
36 0x5b, 0xdb, 0xf4, 0xf7,
37 0xfc, 0xa2, 0x83, 0x19,
38 0xdb, 0x1a, 0x3e, 0x94,
39 0x6b, 0x9e, 0x38, 0xd9,
40 0x2c, 0x9c, 0x03, 0xd1,
41 0xad, 0x99, 0x44, 0xa7,
42 0xd9, 0x56, 0x3d, 0x59,
43 0x06, 0x3c, 0x25, 0xf3,
44 0xfc, 0x1f, 0xdc, 0x2a,
47 /* Length of the default RSS hash key. */
48 static_assert(MLX5_RSS_HASH_KEY_LEN ==
49 (unsigned int)sizeof(rss_hash_default_key),
50 "wrong RSS default key size.");
53 * Calculate the number of CQEs in CQ for the Rx queue.
56 * Pointer to receive queue structure.
59 * Number of CQEs in CQ.
62 mlx5_rxq_cqe_num(struct mlx5_rxq_data *rxq_data)
65 unsigned int wqe_n = 1 << rxq_data->elts_n;
67 if (mlx5_rxq_mprq_enabled(rxq_data))
68 cqe_n = wqe_n * (1 << rxq_data->strd_num_n) - 1;
75 * Allocate RX queue elements for Multi-Packet RQ.
78 * Pointer to RX queue structure.
81 * 0 on success, a negative errno value otherwise and rte_errno is set.
84 rxq_alloc_elts_mprq(struct mlx5_rxq_ctrl *rxq_ctrl)
86 struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
87 unsigned int wqe_n = 1 << rxq->elts_n;
91 /* Iterate on segments. */
92 for (i = 0; i <= wqe_n; ++i) {
93 struct mlx5_mprq_buf *buf;
95 if (rte_mempool_get(rxq->mprq_mp, (void **)&buf) < 0) {
96 DRV_LOG(ERR, "port %u empty mbuf pool", rxq->port_id);
101 (*rxq->mprq_bufs)[i] = buf;
103 rxq->mprq_repl = buf;
106 "port %u MPRQ queue %u allocated and configured %u segments",
107 rxq->port_id, rxq->idx, wqe_n);
110 err = rte_errno; /* Save rte_errno before cleanup. */
112 for (i = 0; (i != wqe_n); ++i) {
113 if ((*rxq->mprq_bufs)[i] != NULL)
114 rte_mempool_put(rxq->mprq_mp,
115 (*rxq->mprq_bufs)[i]);
116 (*rxq->mprq_bufs)[i] = NULL;
118 DRV_LOG(DEBUG, "port %u MPRQ queue %u failed, freed everything",
119 rxq->port_id, rxq->idx);
120 rte_errno = err; /* Restore rte_errno. */
125 * Allocate RX queue elements for Single-Packet RQ.
128 * Pointer to RX queue structure.
131 * 0 on success, errno value on failure.
134 rxq_alloc_elts_sprq(struct mlx5_rxq_ctrl *rxq_ctrl)
136 const unsigned int sges_n = 1 << rxq_ctrl->rxq.sges_n;
137 unsigned int elts_n = mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq) ?
138 (1 << rxq_ctrl->rxq.elts_n) * (1 << rxq_ctrl->rxq.strd_num_n) :
139 (1 << rxq_ctrl->rxq.elts_n);
143 /* Iterate on segments. */
144 for (i = 0; (i != elts_n); ++i) {
145 struct mlx5_eth_rxseg *seg = &rxq_ctrl->rxq.rxseg[i % sges_n];
146 struct rte_mbuf *buf;
148 buf = rte_pktmbuf_alloc(seg->mp);
150 DRV_LOG(ERR, "port %u empty mbuf pool",
151 PORT_ID(rxq_ctrl->priv));
155 /* Headroom is reserved by rte_pktmbuf_alloc(). */
156 MLX5_ASSERT(DATA_OFF(buf) == RTE_PKTMBUF_HEADROOM);
157 /* Buffer is supposed to be empty. */
158 MLX5_ASSERT(rte_pktmbuf_data_len(buf) == 0);
159 MLX5_ASSERT(rte_pktmbuf_pkt_len(buf) == 0);
160 MLX5_ASSERT(!buf->next);
161 SET_DATA_OFF(buf, seg->offset);
162 PORT(buf) = rxq_ctrl->rxq.port_id;
163 DATA_LEN(buf) = seg->length;
164 PKT_LEN(buf) = seg->length;
166 (*rxq_ctrl->rxq.elts)[i] = buf;
168 /* If Rx vector is activated. */
169 if (mlx5_rxq_check_vec_support(&rxq_ctrl->rxq) > 0) {
170 struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
171 struct rte_mbuf *mbuf_init = &rxq->fake_mbuf;
172 struct rte_pktmbuf_pool_private *priv =
173 (struct rte_pktmbuf_pool_private *)
174 rte_mempool_get_priv(rxq_ctrl->rxq.mp);
177 /* Initialize default rearm_data for vPMD. */
178 mbuf_init->data_off = RTE_PKTMBUF_HEADROOM;
179 rte_mbuf_refcnt_set(mbuf_init, 1);
180 mbuf_init->nb_segs = 1;
181 mbuf_init->port = rxq->port_id;
182 if (priv->flags & RTE_PKTMBUF_POOL_F_PINNED_EXT_BUF)
183 mbuf_init->ol_flags = EXT_ATTACHED_MBUF;
185 * prevent compiler reordering:
186 * rearm_data covers previous fields.
188 rte_compiler_barrier();
189 rxq->mbuf_initializer =
190 *(rte_xmm_t *)&mbuf_init->rearm_data;
191 /* Padding with a fake mbuf for vectorized Rx. */
192 for (j = 0; j < MLX5_VPMD_DESCS_PER_LOOP; ++j)
193 (*rxq->elts)[elts_n + j] = &rxq->fake_mbuf;
196 "port %u SPRQ queue %u allocated and configured %u segments"
198 PORT_ID(rxq_ctrl->priv), rxq_ctrl->rxq.idx, elts_n,
199 elts_n / (1 << rxq_ctrl->rxq.sges_n));
202 err = rte_errno; /* Save rte_errno before cleanup. */
204 for (i = 0; (i != elts_n); ++i) {
205 if ((*rxq_ctrl->rxq.elts)[i] != NULL)
206 rte_pktmbuf_free_seg((*rxq_ctrl->rxq.elts)[i]);
207 (*rxq_ctrl->rxq.elts)[i] = NULL;
209 DRV_LOG(DEBUG, "port %u SPRQ queue %u failed, freed everything",
210 PORT_ID(rxq_ctrl->priv), rxq_ctrl->rxq.idx);
211 rte_errno = err; /* Restore rte_errno. */
216 * Allocate RX queue elements.
219 * Pointer to RX queue structure.
222 * 0 on success, errno value on failure.
225 rxq_alloc_elts(struct mlx5_rxq_ctrl *rxq_ctrl)
230 * For MPRQ we need to allocate both MPRQ buffers
231 * for WQEs and simple mbufs for vector processing.
233 if (mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq))
234 ret = rxq_alloc_elts_mprq(rxq_ctrl);
235 return (ret || rxq_alloc_elts_sprq(rxq_ctrl));
239 * Free RX queue elements for Multi-Packet RQ.
242 * Pointer to RX queue structure.
245 rxq_free_elts_mprq(struct mlx5_rxq_ctrl *rxq_ctrl)
247 struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
250 DRV_LOG(DEBUG, "port %u Multi-Packet Rx queue %u freeing %d WRs",
251 rxq->port_id, rxq->idx, (1u << rxq->elts_n));
252 if (rxq->mprq_bufs == NULL)
254 for (i = 0; (i != (1u << rxq->elts_n)); ++i) {
255 if ((*rxq->mprq_bufs)[i] != NULL)
256 mlx5_mprq_buf_free((*rxq->mprq_bufs)[i]);
257 (*rxq->mprq_bufs)[i] = NULL;
259 if (rxq->mprq_repl != NULL) {
260 mlx5_mprq_buf_free(rxq->mprq_repl);
261 rxq->mprq_repl = NULL;
266 * Free RX queue elements for Single-Packet RQ.
269 * Pointer to RX queue structure.
272 rxq_free_elts_sprq(struct mlx5_rxq_ctrl *rxq_ctrl)
274 struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
275 const uint16_t q_n = mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq) ?
276 (1 << rxq->elts_n) * (1 << rxq->strd_num_n) :
278 const uint16_t q_mask = q_n - 1;
279 uint16_t elts_ci = mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq) ?
280 rxq->elts_ci : rxq->rq_ci;
281 uint16_t used = q_n - (elts_ci - rxq->rq_pi);
284 DRV_LOG(DEBUG, "port %u Rx queue %u freeing %d WRs",
285 PORT_ID(rxq_ctrl->priv), rxq->idx, q_n);
286 if (rxq->elts == NULL)
289 * Some mbuf in the Ring belongs to the application.
290 * They cannot be freed.
292 if (mlx5_rxq_check_vec_support(rxq) > 0) {
293 for (i = 0; i < used; ++i)
294 (*rxq->elts)[(elts_ci + i) & q_mask] = NULL;
295 rxq->rq_pi = elts_ci;
297 for (i = 0; i != q_n; ++i) {
298 if ((*rxq->elts)[i] != NULL)
299 rte_pktmbuf_free_seg((*rxq->elts)[i]);
300 (*rxq->elts)[i] = NULL;
305 * Free RX queue elements.
308 * Pointer to RX queue structure.
311 rxq_free_elts(struct mlx5_rxq_ctrl *rxq_ctrl)
314 * For MPRQ we need to allocate both MPRQ buffers
315 * for WQEs and simple mbufs for vector processing.
317 if (mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq))
318 rxq_free_elts_mprq(rxq_ctrl);
319 rxq_free_elts_sprq(rxq_ctrl);
323 * Returns the per-queue supported offloads.
326 * Pointer to Ethernet device.
329 * Supported Rx offloads.
332 mlx5_get_rx_queue_offloads(struct rte_eth_dev *dev)
334 struct mlx5_priv *priv = dev->data->dev_private;
335 struct mlx5_dev_config *config = &priv->config;
336 uint64_t offloads = (DEV_RX_OFFLOAD_SCATTER |
337 DEV_RX_OFFLOAD_TIMESTAMP |
338 DEV_RX_OFFLOAD_RSS_HASH);
340 if (!config->mprq.enabled)
341 offloads |= RTE_ETH_RX_OFFLOAD_BUFFER_SPLIT;
342 if (config->hw_fcs_strip)
343 offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
345 offloads |= (DEV_RX_OFFLOAD_IPV4_CKSUM |
346 DEV_RX_OFFLOAD_UDP_CKSUM |
347 DEV_RX_OFFLOAD_TCP_CKSUM);
348 if (config->hw_vlan_strip)
349 offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
350 if (MLX5_LRO_SUPPORTED(dev))
351 offloads |= DEV_RX_OFFLOAD_TCP_LRO;
357 * Returns the per-port supported offloads.
360 * Supported Rx offloads.
363 mlx5_get_rx_port_offloads(void)
365 uint64_t offloads = DEV_RX_OFFLOAD_VLAN_FILTER;
371 * Verify if the queue can be released.
374 * Pointer to Ethernet device.
379 * 1 if the queue can be released
380 * 0 if the queue can not be released, there are references to it.
381 * Negative errno and rte_errno is set if queue doesn't exist.
384 mlx5_rxq_releasable(struct rte_eth_dev *dev, uint16_t idx)
386 struct mlx5_priv *priv = dev->data->dev_private;
387 struct mlx5_rxq_ctrl *rxq_ctrl;
389 if (!(*priv->rxqs)[idx]) {
393 rxq_ctrl = container_of((*priv->rxqs)[idx], struct mlx5_rxq_ctrl, rxq);
394 return (__atomic_load_n(&rxq_ctrl->refcnt, __ATOMIC_RELAXED) == 1);
397 /* Fetches and drops all SW-owned and error CQEs to synchronize CQ. */
399 rxq_sync_cq(struct mlx5_rxq_data *rxq)
401 const uint16_t cqe_n = 1 << rxq->cqe_n;
402 const uint16_t cqe_mask = cqe_n - 1;
403 volatile struct mlx5_cqe *cqe;
408 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_mask];
409 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
410 if (ret == MLX5_CQE_STATUS_HW_OWN)
412 if (ret == MLX5_CQE_STATUS_ERR) {
416 MLX5_ASSERT(ret == MLX5_CQE_STATUS_SW_OWN);
417 if (MLX5_CQE_FORMAT(cqe->op_own) != MLX5_COMPRESSED) {
421 /* Compute the next non compressed CQE. */
422 rxq->cq_ci += rte_be_to_cpu_32(cqe->byte_cnt);
425 /* Move all CQEs to HW ownership, including possible MiniCQEs. */
426 for (i = 0; i < cqe_n; i++) {
427 cqe = &(*rxq->cqes)[i];
428 cqe->op_own = MLX5_CQE_INVALIDATE;
430 /* Resync CQE and WQE (WQ in RESET state). */
432 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
434 *rxq->rq_db = rte_cpu_to_be_32(0);
439 * Rx queue stop. Device queue goes to the RESET state,
440 * all involved mbufs are freed from WQ.
443 * Pointer to Ethernet device structure.
448 * 0 on success, a negative errno value otherwise and rte_errno is set.
451 mlx5_rx_queue_stop_primary(struct rte_eth_dev *dev, uint16_t idx)
453 struct mlx5_priv *priv = dev->data->dev_private;
454 struct mlx5_rxq_data *rxq = (*priv->rxqs)[idx];
455 struct mlx5_rxq_ctrl *rxq_ctrl =
456 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
459 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
460 ret = priv->obj_ops.rxq_obj_modify(rxq_ctrl->obj, MLX5_RXQ_MOD_RDY2RST);
462 DRV_LOG(ERR, "Cannot change Rx WQ state to RESET: %s",
467 /* Remove all processes CQEs. */
469 /* Free all involved mbufs. */
470 rxq_free_elts(rxq_ctrl);
471 /* Set the actual queue state. */
472 dev->data->rx_queue_state[idx] = RTE_ETH_QUEUE_STATE_STOPPED;
477 * Rx queue stop. Device queue goes to the RESET state,
478 * all involved mbufs are freed from WQ.
481 * Pointer to Ethernet device structure.
486 * 0 on success, a negative errno value otherwise and rte_errno is set.
489 mlx5_rx_queue_stop(struct rte_eth_dev *dev, uint16_t idx)
491 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
494 if (rte_eth_dev_is_rx_hairpin_queue(dev, idx)) {
495 DRV_LOG(ERR, "Hairpin queue can't be stopped");
499 if (dev->data->rx_queue_state[idx] == RTE_ETH_QUEUE_STATE_STOPPED)
502 * Vectorized Rx burst requires the CQ and RQ indices
503 * synchronized, that might be broken on RQ restart
504 * and cause Rx malfunction, so queue stopping is
505 * not supported if vectorized Rx burst is engaged.
506 * The routine pointer depends on the process
507 * type, should perform check there.
509 if (pkt_burst == mlx5_rx_burst_vec) {
510 DRV_LOG(ERR, "Rx queue stop is not supported "
511 "for vectorized Rx");
515 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
516 ret = mlx5_mp_os_req_queue_control(dev, idx,
517 MLX5_MP_REQ_QUEUE_RX_STOP);
519 ret = mlx5_rx_queue_stop_primary(dev, idx);
525 * Rx queue start. Device queue goes to the ready state,
526 * all required mbufs are allocated and WQ is replenished.
529 * Pointer to Ethernet device structure.
534 * 0 on success, a negative errno value otherwise and rte_errno is set.
537 mlx5_rx_queue_start_primary(struct rte_eth_dev *dev, uint16_t idx)
539 struct mlx5_priv *priv = dev->data->dev_private;
540 struct mlx5_rxq_data *rxq = (*priv->rxqs)[idx];
541 struct mlx5_rxq_ctrl *rxq_ctrl =
542 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
545 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
546 /* Allocate needed buffers. */
547 ret = rxq_alloc_elts(rxq_ctrl);
549 DRV_LOG(ERR, "Cannot reallocate buffers for Rx WQ");
554 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
556 /* Reset RQ consumer before moving queue to READY state. */
557 *rxq->rq_db = rte_cpu_to_be_32(0);
559 ret = priv->obj_ops.rxq_obj_modify(rxq_ctrl->obj, MLX5_RXQ_MOD_RST2RDY);
561 DRV_LOG(ERR, "Cannot change Rx WQ state to READY: %s",
566 /* Reinitialize RQ - set WQEs. */
567 mlx5_rxq_initialize(rxq);
568 rxq->err_state = MLX5_RXQ_ERR_STATE_NO_ERROR;
569 /* Set actual queue state. */
570 dev->data->rx_queue_state[idx] = RTE_ETH_QUEUE_STATE_STARTED;
575 * Rx queue start. Device queue goes to the ready state,
576 * all required mbufs are allocated and WQ is replenished.
579 * Pointer to Ethernet device structure.
584 * 0 on success, a negative errno value otherwise and rte_errno is set.
587 mlx5_rx_queue_start(struct rte_eth_dev *dev, uint16_t idx)
591 if (rte_eth_dev_is_rx_hairpin_queue(dev, idx)) {
592 DRV_LOG(ERR, "Hairpin queue can't be started");
596 if (dev->data->rx_queue_state[idx] == RTE_ETH_QUEUE_STATE_STARTED)
598 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
599 ret = mlx5_mp_os_req_queue_control(dev, idx,
600 MLX5_MP_REQ_QUEUE_RX_START);
602 ret = mlx5_rx_queue_start_primary(dev, idx);
608 * Rx queue presetup checks.
611 * Pointer to Ethernet device structure.
615 * Number of descriptors to configure in queue.
618 * 0 on success, a negative errno value otherwise and rte_errno is set.
621 mlx5_rx_queue_pre_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t *desc)
623 struct mlx5_priv *priv = dev->data->dev_private;
625 if (!rte_is_power_of_2(*desc)) {
626 *desc = 1 << log2above(*desc);
628 "port %u increased number of descriptors in Rx queue %u"
629 " to the next power of two (%d)",
630 dev->data->port_id, idx, *desc);
632 DRV_LOG(DEBUG, "port %u configuring Rx queue %u for %u descriptors",
633 dev->data->port_id, idx, *desc);
634 if (idx >= priv->rxqs_n) {
635 DRV_LOG(ERR, "port %u Rx queue index out of range (%u >= %u)",
636 dev->data->port_id, idx, priv->rxqs_n);
637 rte_errno = EOVERFLOW;
640 if (!mlx5_rxq_releasable(dev, idx)) {
641 DRV_LOG(ERR, "port %u unable to release queue index %u",
642 dev->data->port_id, idx);
646 mlx5_rxq_release(dev, idx);
653 * Pointer to Ethernet device structure.
657 * Number of descriptors to configure in queue.
659 * NUMA socket on which memory must be allocated.
661 * Thresholds parameters.
663 * Memory pool for buffer allocations.
666 * 0 on success, a negative errno value otherwise and rte_errno is set.
669 mlx5_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
670 unsigned int socket, const struct rte_eth_rxconf *conf,
671 struct rte_mempool *mp)
673 struct mlx5_priv *priv = dev->data->dev_private;
674 struct mlx5_rxq_data *rxq = (*priv->rxqs)[idx];
675 struct mlx5_rxq_ctrl *rxq_ctrl =
676 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
677 struct rte_eth_rxseg_split *rx_seg =
678 (struct rte_eth_rxseg_split *)conf->rx_seg;
679 struct rte_eth_rxseg_split rx_single = {.mp = mp};
680 uint16_t n_seg = conf->rx_nseg;
685 * The parameters should be checked on rte_eth_dev layer.
686 * If mp is specified it means the compatible configuration
687 * without buffer split feature tuning.
693 uint64_t offloads = conf->offloads |
694 dev->data->dev_conf.rxmode.offloads;
696 /* The offloads should be checked on rte_eth_dev layer. */
697 MLX5_ASSERT(offloads & DEV_RX_OFFLOAD_SCATTER);
698 if (!(offloads & RTE_ETH_RX_OFFLOAD_BUFFER_SPLIT)) {
699 DRV_LOG(ERR, "port %u queue index %u split "
700 "offload not configured",
701 dev->data->port_id, idx);
705 MLX5_ASSERT(n_seg < MLX5_MAX_RXQ_NSEG);
707 res = mlx5_rx_queue_pre_setup(dev, idx, &desc);
710 rxq_ctrl = mlx5_rxq_new(dev, idx, desc, socket, conf, rx_seg, n_seg);
712 DRV_LOG(ERR, "port %u unable to allocate queue index %u",
713 dev->data->port_id, idx);
717 DRV_LOG(DEBUG, "port %u adding Rx queue %u to list",
718 dev->data->port_id, idx);
719 (*priv->rxqs)[idx] = &rxq_ctrl->rxq;
726 * Pointer to Ethernet device structure.
730 * Number of descriptors to configure in queue.
731 * @param hairpin_conf
732 * Hairpin configuration parameters.
735 * 0 on success, a negative errno value otherwise and rte_errno is set.
738 mlx5_rx_hairpin_queue_setup(struct rte_eth_dev *dev, uint16_t idx,
740 const struct rte_eth_hairpin_conf *hairpin_conf)
742 struct mlx5_priv *priv = dev->data->dev_private;
743 struct mlx5_rxq_data *rxq = (*priv->rxqs)[idx];
744 struct mlx5_rxq_ctrl *rxq_ctrl =
745 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
748 res = mlx5_rx_queue_pre_setup(dev, idx, &desc);
751 if (hairpin_conf->peer_count != 1) {
753 DRV_LOG(ERR, "port %u unable to setup Rx hairpin queue index %u"
754 " peer count is %u", dev->data->port_id,
755 idx, hairpin_conf->peer_count);
758 if (hairpin_conf->peers[0].port == dev->data->port_id) {
759 if (hairpin_conf->peers[0].queue >= priv->txqs_n) {
761 DRV_LOG(ERR, "port %u unable to setup Rx hairpin queue"
762 " index %u, Tx %u is larger than %u",
763 dev->data->port_id, idx,
764 hairpin_conf->peers[0].queue, priv->txqs_n);
768 if (hairpin_conf->manual_bind == 0 ||
769 hairpin_conf->tx_explicit == 0) {
771 DRV_LOG(ERR, "port %u unable to setup Rx hairpin queue"
772 " index %u peer port %u with attributes %u %u",
773 dev->data->port_id, idx,
774 hairpin_conf->peers[0].port,
775 hairpin_conf->manual_bind,
776 hairpin_conf->tx_explicit);
780 rxq_ctrl = mlx5_rxq_hairpin_new(dev, idx, desc, hairpin_conf);
782 DRV_LOG(ERR, "port %u unable to allocate queue index %u",
783 dev->data->port_id, idx);
787 DRV_LOG(DEBUG, "port %u adding Rx queue %u to list",
788 dev->data->port_id, idx);
789 (*priv->rxqs)[idx] = &rxq_ctrl->rxq;
794 * DPDK callback to release a RX queue.
797 * Pointer to Ethernet device structure.
799 * Receive queue index.
802 mlx5_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
804 struct mlx5_rxq_data *rxq = dev->data->rx_queues[qid];
808 if (!mlx5_rxq_releasable(dev, qid))
809 rte_panic("port %u Rx queue %u is still used by a flow and"
810 " cannot be removed\n", dev->data->port_id, qid);
811 mlx5_rxq_release(dev, qid);
815 * Allocate queue vector and fill epoll fd list for Rx interrupts.
818 * Pointer to Ethernet device.
821 * 0 on success, a negative errno value otherwise and rte_errno is set.
824 mlx5_rx_intr_vec_enable(struct rte_eth_dev *dev)
826 struct mlx5_priv *priv = dev->data->dev_private;
828 unsigned int rxqs_n = priv->rxqs_n;
829 unsigned int n = RTE_MIN(rxqs_n, (uint32_t)RTE_MAX_RXTX_INTR_VEC_ID);
830 unsigned int count = 0;
831 struct rte_intr_handle *intr_handle = dev->intr_handle;
833 if (!dev->data->dev_conf.intr_conf.rxq)
835 mlx5_rx_intr_vec_disable(dev);
836 intr_handle->intr_vec = mlx5_malloc(0,
837 n * sizeof(intr_handle->intr_vec[0]),
839 if (intr_handle->intr_vec == NULL) {
841 "port %u failed to allocate memory for interrupt"
842 " vector, Rx interrupts will not be supported",
847 intr_handle->type = RTE_INTR_HANDLE_EXT;
848 for (i = 0; i != n; ++i) {
849 /* This rxq obj must not be released in this function. */
850 struct mlx5_rxq_ctrl *rxq_ctrl = mlx5_rxq_get(dev, i);
851 struct mlx5_rxq_obj *rxq_obj = rxq_ctrl ? rxq_ctrl->obj : NULL;
854 /* Skip queues that cannot request interrupts. */
855 if (!rxq_obj || (!rxq_obj->ibv_channel &&
856 !rxq_obj->devx_channel)) {
857 /* Use invalid intr_vec[] index to disable entry. */
858 intr_handle->intr_vec[i] =
859 RTE_INTR_VEC_RXTX_OFFSET +
860 RTE_MAX_RXTX_INTR_VEC_ID;
861 /* Decrease the rxq_ctrl's refcnt */
863 mlx5_rxq_release(dev, i);
866 if (count >= RTE_MAX_RXTX_INTR_VEC_ID) {
868 "port %u too many Rx queues for interrupt"
869 " vector size (%d), Rx interrupts cannot be"
871 dev->data->port_id, RTE_MAX_RXTX_INTR_VEC_ID);
872 mlx5_rx_intr_vec_disable(dev);
876 rc = mlx5_os_set_nonblock_channel_fd(rxq_obj->fd);
880 "port %u failed to make Rx interrupt file"
881 " descriptor %d non-blocking for queue index"
883 dev->data->port_id, rxq_obj->fd, i);
884 mlx5_rx_intr_vec_disable(dev);
887 intr_handle->intr_vec[i] = RTE_INTR_VEC_RXTX_OFFSET + count;
888 intr_handle->efds[count] = rxq_obj->fd;
892 mlx5_rx_intr_vec_disable(dev);
894 intr_handle->nb_efd = count;
899 * Clean up Rx interrupts handler.
902 * Pointer to Ethernet device.
905 mlx5_rx_intr_vec_disable(struct rte_eth_dev *dev)
907 struct mlx5_priv *priv = dev->data->dev_private;
908 struct rte_intr_handle *intr_handle = dev->intr_handle;
910 unsigned int rxqs_n = priv->rxqs_n;
911 unsigned int n = RTE_MIN(rxqs_n, (uint32_t)RTE_MAX_RXTX_INTR_VEC_ID);
913 if (!dev->data->dev_conf.intr_conf.rxq)
915 if (!intr_handle->intr_vec)
917 for (i = 0; i != n; ++i) {
918 if (intr_handle->intr_vec[i] == RTE_INTR_VEC_RXTX_OFFSET +
919 RTE_MAX_RXTX_INTR_VEC_ID)
922 * Need to access directly the queue to release the reference
923 * kept in mlx5_rx_intr_vec_enable().
925 mlx5_rxq_release(dev, i);
928 rte_intr_free_epoll_fd(intr_handle);
929 if (intr_handle->intr_vec)
930 mlx5_free(intr_handle->intr_vec);
931 intr_handle->nb_efd = 0;
932 intr_handle->intr_vec = NULL;
936 * MLX5 CQ notification .
939 * Pointer to receive queue structure.
941 * Sequence number per receive queue .
944 mlx5_arm_cq(struct mlx5_rxq_data *rxq, int sq_n_rxq)
947 uint32_t doorbell_hi;
949 void *cq_db_reg = (char *)rxq->cq_uar + MLX5_CQ_DOORBELL;
951 sq_n = sq_n_rxq & MLX5_CQ_SQN_MASK;
952 doorbell_hi = sq_n << MLX5_CQ_SQN_OFFSET | (rxq->cq_ci & MLX5_CI_MASK);
953 doorbell = (uint64_t)doorbell_hi << 32;
954 doorbell |= rxq->cqn;
955 rxq->cq_db[MLX5_CQ_ARM_DB] = rte_cpu_to_be_32(doorbell_hi);
956 mlx5_uar_write64(rte_cpu_to_be_64(doorbell),
957 cq_db_reg, rxq->uar_lock_cq);
961 * DPDK callback for Rx queue interrupt enable.
964 * Pointer to Ethernet device structure.
969 * 0 on success, a negative errno value otherwise and rte_errno is set.
972 mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id)
974 struct mlx5_rxq_ctrl *rxq_ctrl;
976 rxq_ctrl = mlx5_rxq_get(dev, rx_queue_id);
980 if (!rxq_ctrl->obj) {
981 mlx5_rxq_release(dev, rx_queue_id);
984 mlx5_arm_cq(&rxq_ctrl->rxq, rxq_ctrl->rxq.cq_arm_sn);
986 mlx5_rxq_release(dev, rx_queue_id);
994 * DPDK callback for Rx queue interrupt disable.
997 * Pointer to Ethernet device structure.
1002 * 0 on success, a negative errno value otherwise and rte_errno is set.
1005 mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1007 struct mlx5_priv *priv = dev->data->dev_private;
1008 struct mlx5_rxq_ctrl *rxq_ctrl;
1011 rxq_ctrl = mlx5_rxq_get(dev, rx_queue_id);
1018 if (rxq_ctrl->irq) {
1019 ret = priv->obj_ops.rxq_event_get(rxq_ctrl->obj);
1022 rxq_ctrl->rxq.cq_arm_sn++;
1024 mlx5_rxq_release(dev, rx_queue_id);
1028 * The ret variable may be EAGAIN which means the get_event function was
1029 * called before receiving one.
1035 ret = rte_errno; /* Save rte_errno before cleanup. */
1036 mlx5_rxq_release(dev, rx_queue_id);
1038 DRV_LOG(WARNING, "port %u unable to disable interrupt on Rx queue %d",
1039 dev->data->port_id, rx_queue_id);
1040 rte_errno = ret; /* Restore rte_errno. */
1045 * Verify the Rx queue objects list is empty
1048 * Pointer to Ethernet device.
1051 * The number of objects not released.
1054 mlx5_rxq_obj_verify(struct rte_eth_dev *dev)
1056 struct mlx5_priv *priv = dev->data->dev_private;
1058 struct mlx5_rxq_obj *rxq_obj;
1060 LIST_FOREACH(rxq_obj, &priv->rxqsobj, next) {
1061 DRV_LOG(DEBUG, "port %u Rx queue %u still referenced",
1062 dev->data->port_id, rxq_obj->rxq_ctrl->rxq.idx);
1069 * Callback function to initialize mbufs for Multi-Packet RQ.
1072 mlx5_mprq_buf_init(struct rte_mempool *mp, void *opaque_arg,
1073 void *_m, unsigned int i __rte_unused)
1075 struct mlx5_mprq_buf *buf = _m;
1076 struct rte_mbuf_ext_shared_info *shinfo;
1077 unsigned int strd_n = (unsigned int)(uintptr_t)opaque_arg;
1080 memset(_m, 0, sizeof(*buf));
1082 __atomic_store_n(&buf->refcnt, 1, __ATOMIC_RELAXED);
1083 for (j = 0; j != strd_n; ++j) {
1084 shinfo = &buf->shinfos[j];
1085 shinfo->free_cb = mlx5_mprq_buf_free_cb;
1086 shinfo->fcb_opaque = buf;
1091 * Free mempool of Multi-Packet RQ.
1094 * Pointer to Ethernet device.
1097 * 0 on success, negative errno value on failure.
1100 mlx5_mprq_free_mp(struct rte_eth_dev *dev)
1102 struct mlx5_priv *priv = dev->data->dev_private;
1103 struct rte_mempool *mp = priv->mprq_mp;
1108 DRV_LOG(DEBUG, "port %u freeing mempool (%s) for Multi-Packet RQ",
1109 dev->data->port_id, mp->name);
1111 * If a buffer in the pool has been externally attached to a mbuf and it
1112 * is still in use by application, destroying the Rx queue can spoil
1113 * the packet. It is unlikely to happen but if application dynamically
1114 * creates and destroys with holding Rx packets, this can happen.
1116 * TODO: It is unavoidable for now because the mempool for Multi-Packet
1117 * RQ isn't provided by application but managed by PMD.
1119 if (!rte_mempool_full(mp)) {
1121 "port %u mempool for Multi-Packet RQ is still in use",
1122 dev->data->port_id);
1126 rte_mempool_free(mp);
1127 /* Unset mempool for each Rx queue. */
1128 for (i = 0; i != priv->rxqs_n; ++i) {
1129 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
1133 rxq->mprq_mp = NULL;
1135 priv->mprq_mp = NULL;
1140 * Allocate a mempool for Multi-Packet RQ. All configured Rx queues share the
1141 * mempool. If already allocated, reuse it if there're enough elements.
1142 * Otherwise, resize it.
1145 * Pointer to Ethernet device.
1148 * 0 on success, negative errno value on failure.
1151 mlx5_mprq_alloc_mp(struct rte_eth_dev *dev)
1153 struct mlx5_priv *priv = dev->data->dev_private;
1154 struct rte_mempool *mp = priv->mprq_mp;
1155 char name[RTE_MEMPOOL_NAMESIZE];
1156 unsigned int desc = 0;
1157 unsigned int buf_len;
1158 unsigned int obj_num;
1159 unsigned int obj_size;
1160 unsigned int strd_num_n = 0;
1161 unsigned int strd_sz_n = 0;
1163 unsigned int n_ibv = 0;
1166 if (!mlx5_mprq_enabled(dev))
1168 /* Count the total number of descriptors configured. */
1169 for (i = 0; i != priv->rxqs_n; ++i) {
1170 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
1171 struct mlx5_rxq_ctrl *rxq_ctrl = container_of
1172 (rxq, struct mlx5_rxq_ctrl, rxq);
1174 if (rxq == NULL || rxq_ctrl->type != MLX5_RXQ_TYPE_STANDARD)
1177 desc += 1 << rxq->elts_n;
1178 /* Get the max number of strides. */
1179 if (strd_num_n < rxq->strd_num_n)
1180 strd_num_n = rxq->strd_num_n;
1181 /* Get the max size of a stride. */
1182 if (strd_sz_n < rxq->strd_sz_n)
1183 strd_sz_n = rxq->strd_sz_n;
1185 MLX5_ASSERT(strd_num_n && strd_sz_n);
1186 buf_len = (1 << strd_num_n) * (1 << strd_sz_n);
1187 obj_size = sizeof(struct mlx5_mprq_buf) + buf_len + (1 << strd_num_n) *
1188 sizeof(struct rte_mbuf_ext_shared_info) + RTE_PKTMBUF_HEADROOM;
1190 * Received packets can be either memcpy'd or externally referenced. In
1191 * case that the packet is attached to an mbuf as an external buffer, as
1192 * it isn't possible to predict how the buffers will be queued by
1193 * application, there's no option to exactly pre-allocate needed buffers
1194 * in advance but to speculatively prepares enough buffers.
1196 * In the data path, if this Mempool is depleted, PMD will try to memcpy
1197 * received packets to buffers provided by application (rxq->mp) until
1198 * this Mempool gets available again.
1201 obj_num = desc + MLX5_MPRQ_MP_CACHE_SZ * n_ibv;
1203 * rte_mempool_create_empty() has sanity check to refuse large cache
1204 * size compared to the number of elements.
1205 * CACHE_FLUSHTHRESH_MULTIPLIER is defined in a C file, so using a
1206 * constant number 2 instead.
1208 obj_num = RTE_MAX(obj_num, MLX5_MPRQ_MP_CACHE_SZ * 2);
1209 /* Check a mempool is already allocated and if it can be resued. */
1210 if (mp != NULL && mp->elt_size >= obj_size && mp->size >= obj_num) {
1211 DRV_LOG(DEBUG, "port %u mempool %s is being reused",
1212 dev->data->port_id, mp->name);
1215 } else if (mp != NULL) {
1216 DRV_LOG(DEBUG, "port %u mempool %s should be resized, freeing it",
1217 dev->data->port_id, mp->name);
1219 * If failed to free, which means it may be still in use, no way
1220 * but to keep using the existing one. On buffer underrun,
1221 * packets will be memcpy'd instead of external buffer
1224 if (mlx5_mprq_free_mp(dev)) {
1225 if (mp->elt_size >= obj_size)
1231 snprintf(name, sizeof(name), "port-%u-mprq", dev->data->port_id);
1232 mp = rte_mempool_create(name, obj_num, obj_size, MLX5_MPRQ_MP_CACHE_SZ,
1233 0, NULL, NULL, mlx5_mprq_buf_init,
1234 (void *)((uintptr_t)1 << strd_num_n),
1235 dev->device->numa_node, 0);
1238 "port %u failed to allocate a mempool for"
1239 " Multi-Packet RQ, count=%u, size=%u",
1240 dev->data->port_id, obj_num, obj_size);
1244 ret = mlx5_mr_mempool_register(&priv->sh->share_cache,
1245 priv->sh->cdev->pd, mp, &priv->mp_id);
1246 if (ret < 0 && rte_errno != EEXIST) {
1248 DRV_LOG(ERR, "port %u failed to register a mempool for Multi-Packet RQ",
1249 dev->data->port_id);
1250 rte_mempool_free(mp);
1256 /* Set mempool for each Rx queue. */
1257 for (i = 0; i != priv->rxqs_n; ++i) {
1258 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
1259 struct mlx5_rxq_ctrl *rxq_ctrl = container_of
1260 (rxq, struct mlx5_rxq_ctrl, rxq);
1262 if (rxq == NULL || rxq_ctrl->type != MLX5_RXQ_TYPE_STANDARD)
1266 DRV_LOG(INFO, "port %u Multi-Packet RQ is configured",
1267 dev->data->port_id);
1271 #define MLX5_MAX_TCP_HDR_OFFSET ((unsigned int)(sizeof(struct rte_ether_hdr) + \
1272 sizeof(struct rte_vlan_hdr) * 2 + \
1273 sizeof(struct rte_ipv6_hdr)))
1274 #define MAX_TCP_OPTION_SIZE 40u
1275 #define MLX5_MAX_LRO_HEADER_FIX ((unsigned int)(MLX5_MAX_TCP_HDR_OFFSET + \
1276 sizeof(struct rte_tcp_hdr) + \
1277 MAX_TCP_OPTION_SIZE))
1280 * Adjust the maximum LRO massage size.
1283 * Pointer to Ethernet device.
1286 * @param max_lro_size
1287 * The maximum size for LRO packet.
1290 mlx5_max_lro_msg_size_adjust(struct rte_eth_dev *dev, uint16_t idx,
1291 uint32_t max_lro_size)
1293 struct mlx5_priv *priv = dev->data->dev_private;
1295 if (priv->config.hca_attr.lro_max_msg_sz_mode ==
1296 MLX5_LRO_MAX_MSG_SIZE_START_FROM_L4 && max_lro_size >
1297 MLX5_MAX_TCP_HDR_OFFSET)
1298 max_lro_size -= MLX5_MAX_TCP_HDR_OFFSET;
1299 max_lro_size = RTE_MIN(max_lro_size, MLX5_MAX_LRO_SIZE);
1300 MLX5_ASSERT(max_lro_size >= MLX5_LRO_SEG_CHUNK_SIZE);
1301 max_lro_size /= MLX5_LRO_SEG_CHUNK_SIZE;
1302 if (priv->max_lro_msg_size)
1303 priv->max_lro_msg_size =
1304 RTE_MIN((uint32_t)priv->max_lro_msg_size, max_lro_size);
1306 priv->max_lro_msg_size = max_lro_size;
1308 "port %u Rx Queue %u max LRO message size adjusted to %u bytes",
1309 dev->data->port_id, idx,
1310 priv->max_lro_msg_size * MLX5_LRO_SEG_CHUNK_SIZE);
1314 * Create a DPDK Rx queue.
1317 * Pointer to Ethernet device.
1321 * Number of descriptors to configure in queue.
1323 * NUMA socket on which memory must be allocated.
1326 * A DPDK queue object on success, NULL otherwise and rte_errno is set.
1328 struct mlx5_rxq_ctrl *
1329 mlx5_rxq_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1330 unsigned int socket, const struct rte_eth_rxconf *conf,
1331 const struct rte_eth_rxseg_split *rx_seg, uint16_t n_seg)
1333 struct mlx5_priv *priv = dev->data->dev_private;
1334 struct mlx5_rxq_ctrl *tmpl;
1335 unsigned int mb_len = rte_pktmbuf_data_room_size(rx_seg[0].mp);
1336 struct mlx5_dev_config *config = &priv->config;
1337 uint64_t offloads = conf->offloads |
1338 dev->data->dev_conf.rxmode.offloads;
1339 unsigned int lro_on_queue = !!(offloads & DEV_RX_OFFLOAD_TCP_LRO);
1340 unsigned int max_rx_pktlen = lro_on_queue ?
1341 dev->data->dev_conf.rxmode.max_lro_pkt_size :
1342 dev->data->mtu + (unsigned int)RTE_ETHER_HDR_LEN +
1344 unsigned int non_scatter_min_mbuf_size = max_rx_pktlen +
1345 RTE_PKTMBUF_HEADROOM;
1346 unsigned int max_lro_size = 0;
1347 unsigned int first_mb_free_size = mb_len - RTE_PKTMBUF_HEADROOM;
1348 const int mprq_en = mlx5_check_mprq_support(dev) > 0 && n_seg == 1 &&
1349 !rx_seg[0].offset && !rx_seg[0].length;
1350 unsigned int mprq_stride_nums = config->mprq.stride_num_n ?
1351 config->mprq.stride_num_n : MLX5_MPRQ_STRIDE_NUM_N;
1352 unsigned int mprq_stride_size = non_scatter_min_mbuf_size <=
1353 (1U << config->mprq.max_stride_size_n) ?
1354 log2above(non_scatter_min_mbuf_size) : MLX5_MPRQ_STRIDE_SIZE_N;
1355 unsigned int mprq_stride_cap = (config->mprq.stride_num_n ?
1356 (1U << config->mprq.stride_num_n) : (1U << mprq_stride_nums)) *
1357 (config->mprq.stride_size_n ?
1358 (1U << config->mprq.stride_size_n) : (1U << mprq_stride_size));
1360 * Always allocate extra slots, even if eventually
1361 * the vector Rx will not be used.
1363 uint16_t desc_n = desc + config->rx_vec_en * MLX5_VPMD_DESCS_PER_LOOP;
1364 const struct rte_eth_rxseg_split *qs_seg = rx_seg;
1365 unsigned int tail_len;
1367 tmpl = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO,
1368 sizeof(*tmpl) + desc_n * sizeof(struct rte_mbuf *) +
1370 (desc >> mprq_stride_nums) * sizeof(struct mlx5_mprq_buf *),
1376 MLX5_ASSERT(n_seg && n_seg <= MLX5_MAX_RXQ_NSEG);
1378 * Build the array of actual buffer offsets and lengths.
1379 * Pad with the buffers from the last memory pool if
1380 * needed to handle max size packets, replace zero length
1381 * with the buffer length from the pool.
1383 tail_len = max_rx_pktlen;
1385 struct mlx5_eth_rxseg *hw_seg =
1386 &tmpl->rxq.rxseg[tmpl->rxq.rxseg_n];
1387 uint32_t buf_len, offset, seg_len;
1390 * For the buffers beyond descriptions offset is zero,
1391 * the first buffer contains head room.
1393 buf_len = rte_pktmbuf_data_room_size(qs_seg->mp);
1394 offset = (tmpl->rxq.rxseg_n >= n_seg ? 0 : qs_seg->offset) +
1395 (tmpl->rxq.rxseg_n ? 0 : RTE_PKTMBUF_HEADROOM);
1397 * For the buffers beyond descriptions the length is
1398 * pool buffer length, zero lengths are replaced with
1399 * pool buffer length either.
1401 seg_len = tmpl->rxq.rxseg_n >= n_seg ? buf_len :
1405 /* Check is done in long int, now overflows. */
1406 if (buf_len < seg_len + offset) {
1407 DRV_LOG(ERR, "port %u Rx queue %u: Split offset/length "
1408 "%u/%u can't be satisfied",
1409 dev->data->port_id, idx,
1410 qs_seg->length, qs_seg->offset);
1414 if (seg_len > tail_len)
1415 seg_len = buf_len - offset;
1416 if (++tmpl->rxq.rxseg_n > MLX5_MAX_RXQ_NSEG) {
1418 "port %u too many SGEs (%u) needed to handle"
1419 " requested maximum packet size %u, the maximum"
1420 " supported are %u", dev->data->port_id,
1421 tmpl->rxq.rxseg_n, max_rx_pktlen,
1423 rte_errno = ENOTSUP;
1426 /* Build the actual scattering element in the queue object. */
1427 hw_seg->mp = qs_seg->mp;
1428 MLX5_ASSERT(offset <= UINT16_MAX);
1429 MLX5_ASSERT(seg_len <= UINT16_MAX);
1430 hw_seg->offset = (uint16_t)offset;
1431 hw_seg->length = (uint16_t)seg_len;
1433 * Advance the segment descriptor, the padding is the based
1434 * on the attributes of the last descriptor.
1436 if (tmpl->rxq.rxseg_n < n_seg)
1438 tail_len -= RTE_MIN(tail_len, seg_len);
1439 } while (tail_len || !rte_is_power_of_2(tmpl->rxq.rxseg_n));
1440 MLX5_ASSERT(tmpl->rxq.rxseg_n &&
1441 tmpl->rxq.rxseg_n <= MLX5_MAX_RXQ_NSEG);
1442 if (tmpl->rxq.rxseg_n > 1 && !(offloads & DEV_RX_OFFLOAD_SCATTER)) {
1443 DRV_LOG(ERR, "port %u Rx queue %u: Scatter offload is not"
1444 " configured and no enough mbuf space(%u) to contain "
1445 "the maximum RX packet length(%u) with head-room(%u)",
1446 dev->data->port_id, idx, mb_len, max_rx_pktlen,
1447 RTE_PKTMBUF_HEADROOM);
1451 tmpl->type = MLX5_RXQ_TYPE_STANDARD;
1452 if (mlx5_mr_ctrl_init(&tmpl->rxq.mr_ctrl,
1453 &priv->sh->share_cache.dev_gen, socket)) {
1454 /* rte_errno is already set. */
1457 tmpl->socket = socket;
1458 if (dev->data->dev_conf.intr_conf.rxq)
1461 * This Rx queue can be configured as a Multi-Packet RQ if all of the
1462 * following conditions are met:
1463 * - MPRQ is enabled.
1464 * - The number of descs is more than the number of strides.
1465 * - max_rx_pktlen plus overhead is less than the max size
1466 * of a stride or mprq_stride_size is specified by a user.
1467 * Need to make sure that there are enough strides to encap
1468 * the maximum packet size in case mprq_stride_size is set.
1469 * Otherwise, enable Rx scatter if necessary.
1471 if (mprq_en && desc > (1U << mprq_stride_nums) &&
1472 (non_scatter_min_mbuf_size <=
1473 (1U << config->mprq.max_stride_size_n) ||
1474 (config->mprq.stride_size_n &&
1475 non_scatter_min_mbuf_size <= mprq_stride_cap))) {
1476 /* TODO: Rx scatter isn't supported yet. */
1477 tmpl->rxq.sges_n = 0;
1478 /* Trim the number of descs needed. */
1479 desc >>= mprq_stride_nums;
1480 tmpl->rxq.strd_num_n = config->mprq.stride_num_n ?
1481 config->mprq.stride_num_n : mprq_stride_nums;
1482 tmpl->rxq.strd_sz_n = config->mprq.stride_size_n ?
1483 config->mprq.stride_size_n : mprq_stride_size;
1484 tmpl->rxq.strd_shift_en = MLX5_MPRQ_TWO_BYTE_SHIFT;
1485 tmpl->rxq.strd_scatter_en =
1486 !!(offloads & DEV_RX_OFFLOAD_SCATTER);
1487 tmpl->rxq.mprq_max_memcpy_len = RTE_MIN(first_mb_free_size,
1488 config->mprq.max_memcpy_len);
1489 max_lro_size = RTE_MIN(max_rx_pktlen,
1490 (1u << tmpl->rxq.strd_num_n) *
1491 (1u << tmpl->rxq.strd_sz_n));
1493 "port %u Rx queue %u: Multi-Packet RQ is enabled"
1494 " strd_num_n = %u, strd_sz_n = %u",
1495 dev->data->port_id, idx,
1496 tmpl->rxq.strd_num_n, tmpl->rxq.strd_sz_n);
1497 } else if (tmpl->rxq.rxseg_n == 1) {
1498 MLX5_ASSERT(max_rx_pktlen <= first_mb_free_size);
1499 tmpl->rxq.sges_n = 0;
1500 max_lro_size = max_rx_pktlen;
1501 } else if (offloads & DEV_RX_OFFLOAD_SCATTER) {
1502 unsigned int sges_n;
1504 if (lro_on_queue && first_mb_free_size <
1505 MLX5_MAX_LRO_HEADER_FIX) {
1506 DRV_LOG(ERR, "Not enough space in the first segment(%u)"
1507 " to include the max header size(%u) for LRO",
1508 first_mb_free_size, MLX5_MAX_LRO_HEADER_FIX);
1509 rte_errno = ENOTSUP;
1513 * Determine the number of SGEs needed for a full packet
1514 * and round it to the next power of two.
1516 sges_n = log2above(tmpl->rxq.rxseg_n);
1517 if (sges_n > MLX5_MAX_LOG_RQ_SEGS) {
1519 "port %u too many SGEs (%u) needed to handle"
1520 " requested maximum packet size %u, the maximum"
1521 " supported are %u", dev->data->port_id,
1522 1 << sges_n, max_rx_pktlen,
1523 1u << MLX5_MAX_LOG_RQ_SEGS);
1524 rte_errno = ENOTSUP;
1527 tmpl->rxq.sges_n = sges_n;
1528 max_lro_size = max_rx_pktlen;
1530 if (config->mprq.enabled && !mlx5_rxq_mprq_enabled(&tmpl->rxq))
1532 "port %u MPRQ is requested but cannot be enabled\n"
1533 " (requested: pkt_sz = %u, desc_num = %u,"
1534 " rxq_num = %u, stride_sz = %u, stride_num = %u\n"
1535 " supported: min_rxqs_num = %u,"
1536 " min_stride_sz = %u, max_stride_sz = %u).",
1537 dev->data->port_id, non_scatter_min_mbuf_size,
1539 config->mprq.stride_size_n ?
1540 (1U << config->mprq.stride_size_n) :
1541 (1U << mprq_stride_size),
1542 config->mprq.stride_num_n ?
1543 (1U << config->mprq.stride_num_n) :
1544 (1U << mprq_stride_nums),
1545 config->mprq.min_rxqs_num,
1546 (1U << config->mprq.min_stride_size_n),
1547 (1U << config->mprq.max_stride_size_n));
1548 DRV_LOG(DEBUG, "port %u maximum number of segments per packet: %u",
1549 dev->data->port_id, 1 << tmpl->rxq.sges_n);
1550 if (desc % (1 << tmpl->rxq.sges_n)) {
1552 "port %u number of Rx queue descriptors (%u) is not a"
1553 " multiple of SGEs per packet (%u)",
1556 1 << tmpl->rxq.sges_n);
1560 mlx5_max_lro_msg_size_adjust(dev, idx, max_lro_size);
1561 /* Toggle RX checksum offload if hardware supports it. */
1562 tmpl->rxq.csum = !!(offloads & DEV_RX_OFFLOAD_CHECKSUM);
1563 /* Configure Rx timestamp. */
1564 tmpl->rxq.hw_timestamp = !!(offloads & DEV_RX_OFFLOAD_TIMESTAMP);
1565 tmpl->rxq.timestamp_rx_flag = 0;
1566 if (tmpl->rxq.hw_timestamp && rte_mbuf_dyn_rx_timestamp_register(
1567 &tmpl->rxq.timestamp_offset,
1568 &tmpl->rxq.timestamp_rx_flag) != 0) {
1569 DRV_LOG(ERR, "Cannot register Rx timestamp field/flag");
1572 /* Configure VLAN stripping. */
1573 tmpl->rxq.vlan_strip = !!(offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
1574 /* By default, FCS (CRC) is stripped by hardware. */
1575 tmpl->rxq.crc_present = 0;
1576 tmpl->rxq.lro = lro_on_queue;
1577 if (offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
1578 if (config->hw_fcs_strip) {
1580 * RQs used for LRO-enabled TIRs should not be
1581 * configured to scatter the FCS.
1585 "port %u CRC stripping has been "
1586 "disabled but will still be performed "
1587 "by hardware, because LRO is enabled",
1588 dev->data->port_id);
1590 tmpl->rxq.crc_present = 1;
1593 "port %u CRC stripping has been disabled but will"
1594 " still be performed by hardware, make sure MLNX_OFED"
1595 " and firmware are up to date",
1596 dev->data->port_id);
1600 "port %u CRC stripping is %s, %u bytes will be subtracted from"
1601 " incoming frames to hide it",
1603 tmpl->rxq.crc_present ? "disabled" : "enabled",
1604 tmpl->rxq.crc_present << 2);
1606 tmpl->rxq.rss_hash = !!priv->rss_conf.rss_hf &&
1607 (!!(dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS));
1608 tmpl->rxq.port_id = dev->data->port_id;
1610 tmpl->rxq.mp = rx_seg[0].mp;
1611 tmpl->rxq.elts_n = log2above(desc);
1612 tmpl->rxq.rq_repl_thresh =
1613 MLX5_VPMD_RXQ_RPLNSH_THRESH(desc_n);
1615 (struct rte_mbuf *(*)[desc_n])(tmpl + 1);
1616 tmpl->rxq.mprq_bufs =
1617 (struct mlx5_mprq_buf *(*)[desc])(*tmpl->rxq.elts + desc_n);
1619 tmpl->rxq.uar_lock_cq = &priv->sh->uar_lock_cq;
1621 tmpl->rxq.idx = idx;
1622 __atomic_fetch_add(&tmpl->refcnt, 1, __ATOMIC_RELAXED);
1623 LIST_INSERT_HEAD(&priv->rxqsctrl, tmpl, next);
1626 mlx5_mr_btree_free(&tmpl->rxq.mr_ctrl.cache_bh);
1632 * Create a DPDK Rx hairpin queue.
1635 * Pointer to Ethernet device.
1639 * Number of descriptors to configure in queue.
1640 * @param hairpin_conf
1641 * The hairpin binding configuration.
1644 * A DPDK queue object on success, NULL otherwise and rte_errno is set.
1646 struct mlx5_rxq_ctrl *
1647 mlx5_rxq_hairpin_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1648 const struct rte_eth_hairpin_conf *hairpin_conf)
1650 struct mlx5_priv *priv = dev->data->dev_private;
1651 struct mlx5_rxq_ctrl *tmpl;
1653 tmpl = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, sizeof(*tmpl), 0,
1659 tmpl->type = MLX5_RXQ_TYPE_HAIRPIN;
1660 tmpl->socket = SOCKET_ID_ANY;
1661 tmpl->rxq.rss_hash = 0;
1662 tmpl->rxq.port_id = dev->data->port_id;
1664 tmpl->rxq.mp = NULL;
1665 tmpl->rxq.elts_n = log2above(desc);
1666 tmpl->rxq.elts = NULL;
1667 tmpl->rxq.mr_ctrl.cache_bh = (struct mlx5_mr_btree) { 0 };
1668 tmpl->hairpin_conf = *hairpin_conf;
1669 tmpl->rxq.idx = idx;
1670 __atomic_fetch_add(&tmpl->refcnt, 1, __ATOMIC_RELAXED);
1671 LIST_INSERT_HEAD(&priv->rxqsctrl, tmpl, next);
1679 * Pointer to Ethernet device.
1684 * A pointer to the queue if it exists, NULL otherwise.
1686 struct mlx5_rxq_ctrl *
1687 mlx5_rxq_get(struct rte_eth_dev *dev, uint16_t idx)
1689 struct mlx5_priv *priv = dev->data->dev_private;
1690 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
1691 struct mlx5_rxq_ctrl *rxq_ctrl = NULL;
1694 rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
1695 __atomic_fetch_add(&rxq_ctrl->refcnt, 1, __ATOMIC_RELAXED);
1701 * Release a Rx queue.
1704 * Pointer to Ethernet device.
1709 * 1 while a reference on it exists, 0 when freed.
1712 mlx5_rxq_release(struct rte_eth_dev *dev, uint16_t idx)
1714 struct mlx5_priv *priv = dev->data->dev_private;
1715 struct mlx5_rxq_ctrl *rxq_ctrl;
1717 if (priv->rxqs == NULL || (*priv->rxqs)[idx] == NULL)
1719 rxq_ctrl = container_of((*priv->rxqs)[idx], struct mlx5_rxq_ctrl, rxq);
1720 if (__atomic_sub_fetch(&rxq_ctrl->refcnt, 1, __ATOMIC_RELAXED) > 1)
1722 if (rxq_ctrl->obj) {
1723 priv->obj_ops.rxq_obj_release(rxq_ctrl->obj);
1724 LIST_REMOVE(rxq_ctrl->obj, next);
1725 mlx5_free(rxq_ctrl->obj);
1726 rxq_ctrl->obj = NULL;
1728 if (rxq_ctrl->type == MLX5_RXQ_TYPE_STANDARD) {
1729 rxq_free_elts(rxq_ctrl);
1730 dev->data->rx_queue_state[idx] = RTE_ETH_QUEUE_STATE_STOPPED;
1732 if (!__atomic_load_n(&rxq_ctrl->refcnt, __ATOMIC_RELAXED)) {
1733 if (rxq_ctrl->type == MLX5_RXQ_TYPE_STANDARD)
1734 mlx5_mr_btree_free(&rxq_ctrl->rxq.mr_ctrl.cache_bh);
1735 LIST_REMOVE(rxq_ctrl, next);
1736 mlx5_free(rxq_ctrl);
1737 (*priv->rxqs)[idx] = NULL;
1743 * Verify the Rx Queue list is empty
1746 * Pointer to Ethernet device.
1749 * The number of object not released.
1752 mlx5_rxq_verify(struct rte_eth_dev *dev)
1754 struct mlx5_priv *priv = dev->data->dev_private;
1755 struct mlx5_rxq_ctrl *rxq_ctrl;
1758 LIST_FOREACH(rxq_ctrl, &priv->rxqsctrl, next) {
1759 DRV_LOG(DEBUG, "port %u Rx Queue %u still referenced",
1760 dev->data->port_id, rxq_ctrl->rxq.idx);
1767 * Get a Rx queue type.
1770 * Pointer to Ethernet device.
1775 * The Rx queue type.
1778 mlx5_rxq_get_type(struct rte_eth_dev *dev, uint16_t idx)
1780 struct mlx5_priv *priv = dev->data->dev_private;
1781 struct mlx5_rxq_ctrl *rxq_ctrl = NULL;
1783 if (idx < priv->rxqs_n && (*priv->rxqs)[idx]) {
1784 rxq_ctrl = container_of((*priv->rxqs)[idx],
1785 struct mlx5_rxq_ctrl,
1787 return rxq_ctrl->type;
1789 return MLX5_RXQ_TYPE_UNDEFINED;
1793 * Get a Rx hairpin queue configuration.
1796 * Pointer to Ethernet device.
1801 * Pointer to the configuration if a hairpin RX queue, otherwise NULL.
1803 const struct rte_eth_hairpin_conf *
1804 mlx5_rxq_get_hairpin_conf(struct rte_eth_dev *dev, uint16_t idx)
1806 struct mlx5_priv *priv = dev->data->dev_private;
1807 struct mlx5_rxq_ctrl *rxq_ctrl = NULL;
1809 if (idx < priv->rxqs_n && (*priv->rxqs)[idx]) {
1810 rxq_ctrl = container_of((*priv->rxqs)[idx],
1811 struct mlx5_rxq_ctrl,
1813 if (rxq_ctrl->type == MLX5_RXQ_TYPE_HAIRPIN)
1814 return &rxq_ctrl->hairpin_conf;
1820 * Match queues listed in arguments to queues contained in indirection table
1824 * Pointer to indirection table to match.
1826 * Queues to match to ques in indirection table.
1828 * Number of queues in the array.
1831 * 1 if all queues in indirection table match 0 othrwise.
1834 mlx5_ind_table_obj_match_queues(const struct mlx5_ind_table_obj *ind_tbl,
1835 const uint16_t *queues, uint32_t queues_n)
1837 return (ind_tbl->queues_n == queues_n) &&
1838 (!memcmp(ind_tbl->queues, queues,
1839 ind_tbl->queues_n * sizeof(ind_tbl->queues[0])));
1843 * Get an indirection table.
1846 * Pointer to Ethernet device.
1848 * Queues entering in the indirection table.
1850 * Number of queues in the array.
1853 * An indirection table if found.
1855 struct mlx5_ind_table_obj *
1856 mlx5_ind_table_obj_get(struct rte_eth_dev *dev, const uint16_t *queues,
1859 struct mlx5_priv *priv = dev->data->dev_private;
1860 struct mlx5_ind_table_obj *ind_tbl;
1862 rte_rwlock_read_lock(&priv->ind_tbls_lock);
1863 LIST_FOREACH(ind_tbl, &priv->ind_tbls, next) {
1864 if ((ind_tbl->queues_n == queues_n) &&
1865 (memcmp(ind_tbl->queues, queues,
1866 ind_tbl->queues_n * sizeof(ind_tbl->queues[0]))
1868 __atomic_fetch_add(&ind_tbl->refcnt, 1,
1873 rte_rwlock_read_unlock(&priv->ind_tbls_lock);
1878 * Release an indirection table.
1881 * Pointer to Ethernet device.
1883 * Indirection table to release.
1885 * Indirection table for Standalone queue.
1888 * 1 while a reference on it exists, 0 when freed.
1891 mlx5_ind_table_obj_release(struct rte_eth_dev *dev,
1892 struct mlx5_ind_table_obj *ind_tbl,
1895 struct mlx5_priv *priv = dev->data->dev_private;
1896 unsigned int i, ret;
1898 rte_rwlock_write_lock(&priv->ind_tbls_lock);
1899 ret = __atomic_sub_fetch(&ind_tbl->refcnt, 1, __ATOMIC_RELAXED);
1900 if (!ret && !standalone)
1901 LIST_REMOVE(ind_tbl, next);
1902 rte_rwlock_write_unlock(&priv->ind_tbls_lock);
1905 priv->obj_ops.ind_table_destroy(ind_tbl);
1906 for (i = 0; i != ind_tbl->queues_n; ++i)
1907 claim_nonzero(mlx5_rxq_release(dev, ind_tbl->queues[i]));
1913 * Verify the Rx Queue list is empty
1916 * Pointer to Ethernet device.
1919 * The number of object not released.
1922 mlx5_ind_table_obj_verify(struct rte_eth_dev *dev)
1924 struct mlx5_priv *priv = dev->data->dev_private;
1925 struct mlx5_ind_table_obj *ind_tbl;
1928 rte_rwlock_read_lock(&priv->ind_tbls_lock);
1929 LIST_FOREACH(ind_tbl, &priv->ind_tbls, next) {
1931 "port %u indirection table obj %p still referenced",
1932 dev->data->port_id, (void *)ind_tbl);
1935 rte_rwlock_read_unlock(&priv->ind_tbls_lock);
1940 * Setup an indirection table structure fields.
1943 * Pointer to Ethernet device.
1945 * Indirection table to modify.
1948 * 0 on success, a negative errno value otherwise and rte_errno is set.
1951 mlx5_ind_table_obj_setup(struct rte_eth_dev *dev,
1952 struct mlx5_ind_table_obj *ind_tbl)
1954 struct mlx5_priv *priv = dev->data->dev_private;
1955 uint32_t queues_n = ind_tbl->queues_n;
1956 uint16_t *queues = ind_tbl->queues;
1959 const unsigned int n = rte_is_power_of_2(queues_n) ?
1960 log2above(queues_n) :
1961 log2above(priv->config.ind_table_max_size);
1963 for (i = 0; i != queues_n; ++i) {
1964 if (!mlx5_rxq_get(dev, queues[i])) {
1969 ret = priv->obj_ops.ind_table_new(dev, n, ind_tbl);
1972 __atomic_fetch_add(&ind_tbl->refcnt, 1, __ATOMIC_RELAXED);
1976 for (j = 0; j < i; j++)
1977 mlx5_rxq_release(dev, ind_tbl->queues[j]);
1979 DRV_LOG(DEBUG, "Port %u cannot setup indirection table.",
1980 dev->data->port_id);
1985 * Create an indirection table.
1988 * Pointer to Ethernet device.
1990 * Queues entering in the indirection table.
1992 * Number of queues in the array.
1994 * Indirection table for Standalone queue.
1997 * The Verbs/DevX object initialized, NULL otherwise and rte_errno is set.
1999 static struct mlx5_ind_table_obj *
2000 mlx5_ind_table_obj_new(struct rte_eth_dev *dev, const uint16_t *queues,
2001 uint32_t queues_n, bool standalone)
2003 struct mlx5_priv *priv = dev->data->dev_private;
2004 struct mlx5_ind_table_obj *ind_tbl;
2007 ind_tbl = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ind_tbl) +
2008 queues_n * sizeof(uint16_t), 0, SOCKET_ID_ANY);
2013 ind_tbl->queues_n = queues_n;
2014 ind_tbl->queues = (uint16_t *)(ind_tbl + 1);
2015 memcpy(ind_tbl->queues, queues, queues_n * sizeof(*queues));
2016 ret = mlx5_ind_table_obj_setup(dev, ind_tbl);
2022 rte_rwlock_write_lock(&priv->ind_tbls_lock);
2023 LIST_INSERT_HEAD(&priv->ind_tbls, ind_tbl, next);
2024 rte_rwlock_write_unlock(&priv->ind_tbls_lock);
2030 * Modify an indirection table.
2033 * Pointer to Ethernet device.
2035 * Indirection table to modify.
2037 * Queues replacement for the indirection table.
2039 * Number of queues in the array.
2041 * Indirection table for Standalone queue.
2044 * 0 on success, a negative errno value otherwise and rte_errno is set.
2047 mlx5_ind_table_obj_modify(struct rte_eth_dev *dev,
2048 struct mlx5_ind_table_obj *ind_tbl,
2049 uint16_t *queues, const uint32_t queues_n,
2052 struct mlx5_priv *priv = dev->data->dev_private;
2055 const unsigned int n = rte_is_power_of_2(queues_n) ?
2056 log2above(queues_n) :
2057 log2above(priv->config.ind_table_max_size);
2059 MLX5_ASSERT(standalone);
2060 RTE_SET_USED(standalone);
2061 if (__atomic_load_n(&ind_tbl->refcnt, __ATOMIC_RELAXED) > 1) {
2063 * Modification of indirection ntables having more than 1
2064 * reference unsupported. Intended for standalone indirection
2068 "Port %u cannot modify indirection table (refcnt> 1).",
2069 dev->data->port_id);
2073 for (i = 0; i != queues_n; ++i) {
2074 if (!mlx5_rxq_get(dev, queues[i])) {
2079 MLX5_ASSERT(priv->obj_ops.ind_table_modify);
2080 ret = priv->obj_ops.ind_table_modify(dev, n, queues, queues_n, ind_tbl);
2083 for (j = 0; j < ind_tbl->queues_n; j++)
2084 mlx5_rxq_release(dev, ind_tbl->queues[j]);
2085 ind_tbl->queues_n = queues_n;
2086 ind_tbl->queues = queues;
2090 for (j = 0; j < i; j++)
2091 mlx5_rxq_release(dev, queues[j]);
2093 DRV_LOG(DEBUG, "Port %u cannot setup indirection table.",
2094 dev->data->port_id);
2099 mlx5_hrxq_match_cb(void *tool_ctx __rte_unused, struct mlx5_list_entry *entry,
2102 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
2103 struct mlx5_flow_rss_desc *rss_desc = ctx->data;
2104 struct mlx5_hrxq *hrxq = container_of(entry, typeof(*hrxq), entry);
2106 return (hrxq->rss_key_len != rss_desc->key_len ||
2107 memcmp(hrxq->rss_key, rss_desc->key, rss_desc->key_len) ||
2108 hrxq->hash_fields != rss_desc->hash_fields ||
2109 hrxq->ind_table->queues_n != rss_desc->queue_num ||
2110 memcmp(hrxq->ind_table->queues, rss_desc->queue,
2111 rss_desc->queue_num * sizeof(rss_desc->queue[0])));
2115 * Modify an Rx Hash queue configuration.
2118 * Pointer to Ethernet device.
2120 * Index to Hash Rx queue to modify.
2122 * RSS key for the Rx hash queue.
2123 * @param rss_key_len
2125 * @param hash_fields
2126 * Verbs protocol hash field to make the RSS on.
2128 * Queues entering in hash queue. In case of empty hash_fields only the
2129 * first queue index will be taken for the indirection table.
2134 * 0 on success, a negative errno value otherwise and rte_errno is set.
2137 mlx5_hrxq_modify(struct rte_eth_dev *dev, uint32_t hrxq_idx,
2138 const uint8_t *rss_key, uint32_t rss_key_len,
2139 uint64_t hash_fields,
2140 const uint16_t *queues, uint32_t queues_n)
2143 struct mlx5_ind_table_obj *ind_tbl = NULL;
2144 struct mlx5_priv *priv = dev->data->dev_private;
2145 struct mlx5_hrxq *hrxq =
2146 mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ], hrxq_idx);
2154 if (hrxq->rss_key_len != rss_key_len) {
2155 /* rss_key_len is fixed size 40 byte & not supposed to change */
2159 queues_n = hash_fields ? queues_n : 1;
2160 if (mlx5_ind_table_obj_match_queues(hrxq->ind_table,
2161 queues, queues_n)) {
2162 ind_tbl = hrxq->ind_table;
2164 if (hrxq->standalone) {
2166 * Replacement of indirection table unsupported for
2167 * stanalone hrxq objects (used by shared RSS).
2169 rte_errno = ENOTSUP;
2172 ind_tbl = mlx5_ind_table_obj_get(dev, queues, queues_n);
2174 ind_tbl = mlx5_ind_table_obj_new(dev, queues, queues_n,
2181 MLX5_ASSERT(priv->obj_ops.hrxq_modify);
2182 ret = priv->obj_ops.hrxq_modify(dev, hrxq, rss_key,
2183 hash_fields, ind_tbl);
2188 if (ind_tbl != hrxq->ind_table) {
2189 MLX5_ASSERT(!hrxq->standalone);
2190 mlx5_ind_table_obj_release(dev, hrxq->ind_table,
2192 hrxq->ind_table = ind_tbl;
2194 hrxq->hash_fields = hash_fields;
2195 memcpy(hrxq->rss_key, rss_key, rss_key_len);
2199 if (ind_tbl != hrxq->ind_table) {
2200 MLX5_ASSERT(!hrxq->standalone);
2201 mlx5_ind_table_obj_release(dev, ind_tbl, hrxq->standalone);
2208 __mlx5_hrxq_remove(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq)
2210 struct mlx5_priv *priv = dev->data->dev_private;
2212 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2213 mlx5_glue->destroy_flow_action(hrxq->action);
2215 priv->obj_ops.hrxq_destroy(hrxq);
2216 if (!hrxq->standalone) {
2217 mlx5_ind_table_obj_release(dev, hrxq->ind_table,
2220 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_HRXQ], hrxq->idx);
2224 * Release the hash Rx queue.
2227 * Pointer to Ethernet device.
2229 * Index to Hash Rx queue to release.
2232 * mlx5 list pointer.
2234 * Hash queue entry pointer.
2237 mlx5_hrxq_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
2239 struct rte_eth_dev *dev = tool_ctx;
2240 struct mlx5_hrxq *hrxq = container_of(entry, typeof(*hrxq), entry);
2242 __mlx5_hrxq_remove(dev, hrxq);
2245 static struct mlx5_hrxq *
2246 __mlx5_hrxq_create(struct rte_eth_dev *dev,
2247 struct mlx5_flow_rss_desc *rss_desc)
2249 struct mlx5_priv *priv = dev->data->dev_private;
2250 const uint8_t *rss_key = rss_desc->key;
2251 uint32_t rss_key_len = rss_desc->key_len;
2252 bool standalone = !!rss_desc->shared_rss;
2253 const uint16_t *queues =
2254 standalone ? rss_desc->const_q : rss_desc->queue;
2255 uint32_t queues_n = rss_desc->queue_num;
2256 struct mlx5_hrxq *hrxq = NULL;
2257 uint32_t hrxq_idx = 0;
2258 struct mlx5_ind_table_obj *ind_tbl = rss_desc->ind_tbl;
2261 queues_n = rss_desc->hash_fields ? queues_n : 1;
2263 ind_tbl = mlx5_ind_table_obj_get(dev, queues, queues_n);
2265 ind_tbl = mlx5_ind_table_obj_new(dev, queues, queues_n,
2269 hrxq = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_HRXQ], &hrxq_idx);
2272 hrxq->standalone = standalone;
2273 hrxq->idx = hrxq_idx;
2274 hrxq->ind_table = ind_tbl;
2275 hrxq->rss_key_len = rss_key_len;
2276 hrxq->hash_fields = rss_desc->hash_fields;
2277 memcpy(hrxq->rss_key, rss_key, rss_key_len);
2278 ret = priv->obj_ops.hrxq_new(dev, hrxq, rss_desc->tunnel);
2283 if (!rss_desc->ind_tbl)
2284 mlx5_ind_table_obj_release(dev, ind_tbl, standalone);
2286 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_HRXQ], hrxq_idx);
2290 struct mlx5_list_entry *
2291 mlx5_hrxq_create_cb(void *tool_ctx, void *cb_ctx)
2293 struct rte_eth_dev *dev = tool_ctx;
2294 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
2295 struct mlx5_flow_rss_desc *rss_desc = ctx->data;
2296 struct mlx5_hrxq *hrxq;
2298 hrxq = __mlx5_hrxq_create(dev, rss_desc);
2299 return hrxq ? &hrxq->entry : NULL;
2302 struct mlx5_list_entry *
2303 mlx5_hrxq_clone_cb(void *tool_ctx, struct mlx5_list_entry *entry,
2304 void *cb_ctx __rte_unused)
2306 struct rte_eth_dev *dev = tool_ctx;
2307 struct mlx5_priv *priv = dev->data->dev_private;
2308 struct mlx5_hrxq *hrxq;
2309 uint32_t hrxq_idx = 0;
2311 hrxq = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_HRXQ], &hrxq_idx);
2314 memcpy(hrxq, entry, sizeof(*hrxq) + MLX5_RSS_HASH_KEY_LEN);
2315 hrxq->idx = hrxq_idx;
2316 return &hrxq->entry;
2320 mlx5_hrxq_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
2322 struct rte_eth_dev *dev = tool_ctx;
2323 struct mlx5_priv *priv = dev->data->dev_private;
2324 struct mlx5_hrxq *hrxq = container_of(entry, typeof(*hrxq), entry);
2326 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_HRXQ], hrxq->idx);
2330 * Get an Rx Hash queue.
2333 * Pointer to Ethernet device.
2335 * RSS configuration for the Rx hash queue.
2338 * An hash Rx queue index on success.
2340 uint32_t mlx5_hrxq_get(struct rte_eth_dev *dev,
2341 struct mlx5_flow_rss_desc *rss_desc)
2343 struct mlx5_priv *priv = dev->data->dev_private;
2344 struct mlx5_hrxq *hrxq;
2345 struct mlx5_list_entry *entry;
2346 struct mlx5_flow_cb_ctx ctx = {
2350 if (rss_desc->shared_rss) {
2351 hrxq = __mlx5_hrxq_create(dev, rss_desc);
2353 entry = mlx5_list_register(priv->hrxqs, &ctx);
2356 hrxq = container_of(entry, typeof(*hrxq), entry);
2364 * Release the hash Rx queue.
2367 * Pointer to Ethernet device.
2369 * Index to Hash Rx queue to release.
2372 * 1 while a reference on it exists, 0 when freed.
2374 int mlx5_hrxq_release(struct rte_eth_dev *dev, uint32_t hrxq_idx)
2376 struct mlx5_priv *priv = dev->data->dev_private;
2377 struct mlx5_hrxq *hrxq;
2379 hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ], hrxq_idx);
2382 if (!hrxq->standalone)
2383 return mlx5_list_unregister(priv->hrxqs, &hrxq->entry);
2384 __mlx5_hrxq_remove(dev, hrxq);
2389 * Create a drop Rx Hash queue.
2392 * Pointer to Ethernet device.
2395 * The Verbs/DevX object initialized, NULL otherwise and rte_errno is set.
2398 mlx5_drop_action_create(struct rte_eth_dev *dev)
2400 struct mlx5_priv *priv = dev->data->dev_private;
2401 struct mlx5_hrxq *hrxq = NULL;
2404 if (priv->drop_queue.hrxq)
2405 return priv->drop_queue.hrxq;
2406 hrxq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*hrxq), 0, SOCKET_ID_ANY);
2409 "Port %u cannot allocate memory for drop queue.",
2410 dev->data->port_id);
2414 priv->drop_queue.hrxq = hrxq;
2415 hrxq->ind_table = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*hrxq->ind_table),
2417 if (!hrxq->ind_table) {
2421 ret = priv->obj_ops.drop_action_create(dev);
2427 if (hrxq->ind_table)
2428 mlx5_free(hrxq->ind_table);
2429 priv->drop_queue.hrxq = NULL;
2436 * Release a drop hash Rx queue.
2439 * Pointer to Ethernet device.
2442 mlx5_drop_action_destroy(struct rte_eth_dev *dev)
2444 struct mlx5_priv *priv = dev->data->dev_private;
2445 struct mlx5_hrxq *hrxq = priv->drop_queue.hrxq;
2447 if (!priv->drop_queue.hrxq)
2449 priv->obj_ops.drop_action_destroy(dev);
2450 mlx5_free(priv->drop_queue.rxq);
2451 mlx5_free(hrxq->ind_table);
2453 priv->drop_queue.rxq = NULL;
2454 priv->drop_queue.hrxq = NULL;
2458 * Verify the Rx Queue list is empty
2461 * Pointer to Ethernet device.
2464 * The number of object not released.
2467 mlx5_hrxq_verify(struct rte_eth_dev *dev)
2469 struct mlx5_priv *priv = dev->data->dev_private;
2471 return mlx5_list_get_entry_num(priv->hrxqs);
2475 * Set the Rx queue timestamp conversion parameters
2478 * Pointer to the Ethernet device structure.
2481 mlx5_rxq_timestamp_set(struct rte_eth_dev *dev)
2483 struct mlx5_priv *priv = dev->data->dev_private;
2484 struct mlx5_dev_ctx_shared *sh = priv->sh;
2485 struct mlx5_rxq_data *data;
2488 for (i = 0; i != priv->rxqs_n; ++i) {
2489 if (!(*priv->rxqs)[i])
2491 data = (*priv->rxqs)[i];
2493 data->rt_timestamp = priv->config.rt_timestamp;