drivers/net/mlx5/mlx5_rxq.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <stddef.h>
   7 #include <assert.h>
   8 #include <errno.h>
   9 #include <string.h>
  10 #include <stdint.h>
  11 #include <fcntl.h>
  12 #include <sys/queue.h>
  13
  14 /* Verbs header. */
  15 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  16 #ifdef PEDANTIC
  17 #pragma GCC diagnostic ignored "-Wpedantic"
  18 #endif
  19 #include <infiniband/verbs.h>
  20 #include <infiniband/mlx5dv.h>
  21 #ifdef PEDANTIC
  22 #pragma GCC diagnostic error "-Wpedantic"
  23 #endif
  24
  25 #include <rte_mbuf.h>
  26 #include <rte_malloc.h>
  27 #include <rte_ethdev_driver.h>
  28 #include <rte_common.h>
  29 #include <rte_interrupts.h>
  30 #include <rte_debug.h>
  31 #include <rte_io.h>
  32
  33 #include "mlx5.h"
  34 #include "mlx5_rxtx.h"
  35 #include "mlx5_utils.h"
  36 #include "mlx5_autoconf.h"
  37 #include "mlx5_defs.h"
  38 #include "mlx5_glue.h"
  39
  40 /* Default RSS hash key also used for ConnectX-3. */
  41 uint8_t rss_hash_default_key[] = {
  42         0x2c, 0xc6, 0x81, 0xd1,
  43         0x5b, 0xdb, 0xf4, 0xf7,
  44         0xfc, 0xa2, 0x83, 0x19,
  45         0xdb, 0x1a, 0x3e, 0x94,
  46         0x6b, 0x9e, 0x38, 0xd9,
  47         0x2c, 0x9c, 0x03, 0xd1,
  48         0xad, 0x99, 0x44, 0xa7,
  49         0xd9, 0x56, 0x3d, 0x59,
  50         0x06, 0x3c, 0x25, 0xf3,
  51         0xfc, 0x1f, 0xdc, 0x2a,
  52 };
  53
  54 /* Length of the default RSS hash key. */
  55 static_assert(MLX5_RSS_HASH_KEY_LEN ==
  56               (unsigned int)sizeof(rss_hash_default_key),
  57               "wrong RSS default key size.");
  58
  59 /**
  60  * Check whether Multi-Packet RQ can be enabled for the device.
  61  *
  62  * @param dev
  63  *   Pointer to Ethernet device.
  64  *
  65  * @return
  66  *   1 if supported, negative errno value if not.
  67  */
  68 inline int
  69 mlx5_check_mprq_support(struct rte_eth_dev *dev)
  70 {
  71         struct mlx5_priv *priv = dev->data->dev_private;
  72
  73         if (priv->config.mprq.enabled &&
  74             priv->rxqs_n >= priv->config.mprq.min_rxqs_num)
  75                 return 1;
  76         return -ENOTSUP;
  77 }
  78
  79 /**
  80  * Check whether Multi-Packet RQ is enabled for the Rx queue.
  81  *
  82  *  @param rxq
  83  *     Pointer to receive queue structure.
  84  *
  85  * @return
  86  *   0 if disabled, otherwise enabled.
  87  */
  88 inline int
  89 mlx5_rxq_mprq_enabled(struct mlx5_rxq_data *rxq)
  90 {
  91         return rxq->strd_num_n > 0;
  92 }
  93
  94 /**
  95  * Check whether Multi-Packet RQ is enabled for the device.
  96  * MPRQ can be enabled explicitly, or implicitly by enabling LRO.
  97  *
  98  * @param dev
  99  *   Pointer to Ethernet device.
 100  *
 101  * @return
 102  *   0 if disabled, otherwise enabled.
 103  */
 104 inline int
 105 mlx5_mprq_enabled(struct rte_eth_dev *dev)
 106 {
 107         struct mlx5_priv *priv = dev->data->dev_private;
 108         uint16_t i;
 109         uint16_t n = 0;
 110
 111         if (mlx5_check_mprq_support(dev) < 0)
 112                 return 0;
 113         /* All the configured queues should be enabled. */
 114         for (i = 0; i < priv->rxqs_n; ++i) {
 115                 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
 116
 117                 if (!rxq)
 118                         continue;
 119                 if (mlx5_rxq_mprq_enabled(rxq))
 120                         ++n;
 121         }
 122         /* Multi-Packet RQ can't be partially configured. */
 123         assert(n == 0 || n == priv->rxqs_n);
 124         return n == priv->rxqs_n;
 125 }
 126
 127 /**
 128  * Check whether LRO is supported and enabled for the device.
 129  *
 130  * @param dev
 131  *   Pointer to Ethernet device.
 132  *
 133  * @return
 134  *   0 if disabled, 1 if enabled.
 135  */
 136 inline int
 137 mlx5_lro_on(struct rte_eth_dev *dev)
 138 {
 139         return (MLX5_LRO_SUPPORTED(dev) && MLX5_LRO_ENABLED(dev));
 140 }
 141
 142 /**
 143  * Allocate RX queue elements for Multi-Packet RQ.
 144  *
 145  * @param rxq_ctrl
 146  *   Pointer to RX queue structure.
 147  *
 148  * @return
 149  *   0 on success, a negative errno value otherwise and rte_errno is set.
 150  */
 151 static int
 152 rxq_alloc_elts_mprq(struct mlx5_rxq_ctrl *rxq_ctrl)
 153 {
 154         struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
 155         unsigned int wqe_n = 1 << rxq->elts_n;
 156         unsigned int i;
 157         int err;
 158
 159         /* Iterate on segments. */
 160         for (i = 0; i <= wqe_n; ++i) {
 161                 struct mlx5_mprq_buf *buf;
 162
 163                 if (rte_mempool_get(rxq->mprq_mp, (void **)&buf) < 0) {
 164                         DRV_LOG(ERR, "port %u empty mbuf pool", rxq->port_id);
 165                         rte_errno = ENOMEM;
 166                         goto error;
 167                 }
 168                 if (i < wqe_n)
 169                         (*rxq->mprq_bufs)[i] = buf;
 170                 else
 171                         rxq->mprq_repl = buf;
 172         }
 173         DRV_LOG(DEBUG,
 174                 "port %u Rx queue %u allocated and configured %u segments",
 175                 rxq->port_id, rxq->idx, wqe_n);
 176         return 0;
 177 error:
 178         err = rte_errno; /* Save rte_errno before cleanup. */
 179         wqe_n = i;
 180         for (i = 0; (i != wqe_n); ++i) {
 181                 if ((*rxq->mprq_bufs)[i] != NULL)
 182                         rte_mempool_put(rxq->mprq_mp,
 183                                         (*rxq->mprq_bufs)[i]);
 184                 (*rxq->mprq_bufs)[i] = NULL;
 185         }
 186         DRV_LOG(DEBUG, "port %u Rx queue %u failed, freed everything",
 187                 rxq->port_id, rxq->idx);
 188         rte_errno = err; /* Restore rte_errno. */
 189         return -rte_errno;
 190 }
 191
 192 /**
 193  * Allocate RX queue elements for Single-Packet RQ.
 194  *
 195  * @param rxq_ctrl
 196  *   Pointer to RX queue structure.
 197  *
 198  * @return
 199  *   0 on success, errno value on failure.
 200  */
 201 static int
 202 rxq_alloc_elts_sprq(struct mlx5_rxq_ctrl *rxq_ctrl)
 203 {
 204         const unsigned int sges_n = 1 << rxq_ctrl->rxq.sges_n;
 205         unsigned int elts_n = 1 << rxq_ctrl->rxq.elts_n;
 206         unsigned int i;
 207         int err;
 208
 209         /* Iterate on segments. */
 210         for (i = 0; (i != elts_n); ++i) {
 211                 struct rte_mbuf *buf;
 212
 213                 buf = rte_pktmbuf_alloc(rxq_ctrl->rxq.mp);
 214                 if (buf == NULL) {
 215                         DRV_LOG(ERR, "port %u empty mbuf pool",
 216                                 PORT_ID(rxq_ctrl->priv));
 217                         rte_errno = ENOMEM;
 218                         goto error;
 219                 }
 220                 /* Headroom is reserved by rte_pktmbuf_alloc(). */
 221                 assert(DATA_OFF(buf) == RTE_PKTMBUF_HEADROOM);
 222                 /* Buffer is supposed to be empty. */
 223                 assert(rte_pktmbuf_data_len(buf) == 0);
 224                 assert(rte_pktmbuf_pkt_len(buf) == 0);
 225                 assert(!buf->next);
 226                 /* Only the first segment keeps headroom. */
 227                 if (i % sges_n)
 228                         SET_DATA_OFF(buf, 0);
 229                 PORT(buf) = rxq_ctrl->rxq.port_id;
 230                 DATA_LEN(buf) = rte_pktmbuf_tailroom(buf);
 231                 PKT_LEN(buf) = DATA_LEN(buf);
 232                 NB_SEGS(buf) = 1;
 233                 (*rxq_ctrl->rxq.elts)[i] = buf;
 234         }
 235         /* If Rx vector is activated. */
 236         if (mlx5_rxq_check_vec_support(&rxq_ctrl->rxq) > 0) {
 237                 struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
 238                 struct rte_mbuf *mbuf_init = &rxq->fake_mbuf;
 239                 int j;
 240
 241                 /* Initialize default rearm_data for vPMD. */
 242                 mbuf_init->data_off = RTE_PKTMBUF_HEADROOM;
 243                 rte_mbuf_refcnt_set(mbuf_init, 1);
 244                 mbuf_init->nb_segs = 1;
 245                 mbuf_init->port = rxq->port_id;
 246                 /*
 247                  * prevent compiler reordering:
 248                  * rearm_data covers previous fields.
 249                  */
 250                 rte_compiler_barrier();
 251                 rxq->mbuf_initializer =
 252                         *(uint64_t *)&mbuf_init->rearm_data;
 253                 /* Padding with a fake mbuf for vectorized Rx. */
 254                 for (j = 0; j < MLX5_VPMD_DESCS_PER_LOOP; ++j)
 255                         (*rxq->elts)[elts_n + j] = &rxq->fake_mbuf;
 256         }
 257         DRV_LOG(DEBUG,
 258                 "port %u Rx queue %u allocated and configured %u segments"
 259                 " (max %u packets)",
 260                 PORT_ID(rxq_ctrl->priv), rxq_ctrl->rxq.idx, elts_n,
 261                 elts_n / (1 << rxq_ctrl->rxq.sges_n));
 262         return 0;
 263 error:
 264         err = rte_errno; /* Save rte_errno before cleanup. */
 265         elts_n = i;
 266         for (i = 0; (i != elts_n); ++i) {
 267                 if ((*rxq_ctrl->rxq.elts)[i] != NULL)
 268                         rte_pktmbuf_free_seg((*rxq_ctrl->rxq.elts)[i]);
 269                 (*rxq_ctrl->rxq.elts)[i] = NULL;
 270         }
 271         DRV_LOG(DEBUG, "port %u Rx queue %u failed, freed everything",
 272                 PORT_ID(rxq_ctrl->priv), rxq_ctrl->rxq.idx);
 273         rte_errno = err; /* Restore rte_errno. */
 274         return -rte_errno;
 275 }
 276
 277 /**
 278  * Allocate RX queue elements.
 279  *
 280  * @param rxq_ctrl
 281  *   Pointer to RX queue structure.
 282  *
 283  * @return
 284  *   0 on success, errno value on failure.
 285  */
 286 int
 287 rxq_alloc_elts(struct mlx5_rxq_ctrl *rxq_ctrl)
 288 {
 289         return mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq) ?
 290                rxq_alloc_elts_mprq(rxq_ctrl) : rxq_alloc_elts_sprq(rxq_ctrl);
 291 }
 292
 293 /**
 294  * Free RX queue elements for Multi-Packet RQ.
 295  *
 296  * @param rxq_ctrl
 297  *   Pointer to RX queue structure.
 298  */
 299 static void
 300 rxq_free_elts_mprq(struct mlx5_rxq_ctrl *rxq_ctrl)
 301 {
 302         struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
 303         uint16_t i;
 304
 305         DRV_LOG(DEBUG, "port %u Multi-Packet Rx queue %u freeing WRs",
 306                 rxq->port_id, rxq->idx);
 307         if (rxq->mprq_bufs == NULL)
 308                 return;
 309         assert(mlx5_rxq_check_vec_support(rxq) < 0);
 310         for (i = 0; (i != (1u << rxq->elts_n)); ++i) {
 311                 if ((*rxq->mprq_bufs)[i] != NULL)
 312                         mlx5_mprq_buf_free((*rxq->mprq_bufs)[i]);
 313                 (*rxq->mprq_bufs)[i] = NULL;
 314         }
 315         if (rxq->mprq_repl != NULL) {
 316                 mlx5_mprq_buf_free(rxq->mprq_repl);
 317                 rxq->mprq_repl = NULL;
 318         }
 319 }
 320
 321 /**
 322  * Free RX queue elements for Single-Packet RQ.
 323  *
 324  * @param rxq_ctrl
 325  *   Pointer to RX queue structure.
 326  */
 327 static void
 328 rxq_free_elts_sprq(struct mlx5_rxq_ctrl *rxq_ctrl)
 329 {
 330         struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
 331         const uint16_t q_n = (1 << rxq->elts_n);
 332         const uint16_t q_mask = q_n - 1;
 333         uint16_t used = q_n - (rxq->rq_ci - rxq->rq_pi);
 334         uint16_t i;
 335
 336         DRV_LOG(DEBUG, "port %u Rx queue %u freeing WRs",
 337                 PORT_ID(rxq_ctrl->priv), rxq->idx);
 338         if (rxq->elts == NULL)
 339                 return;
 340         /**
 341          * Some mbuf in the Ring belongs to the application.  They cannot be
 342          * freed.
 343          */
 344         if (mlx5_rxq_check_vec_support(rxq) > 0) {
 345                 for (i = 0; i < used; ++i)
 346                         (*rxq->elts)[(rxq->rq_ci + i) & q_mask] = NULL;
 347                 rxq->rq_pi = rxq->rq_ci;
 348         }
 349         for (i = 0; (i != (1u << rxq->elts_n)); ++i) {
 350                 if ((*rxq->elts)[i] != NULL)
 351                         rte_pktmbuf_free_seg((*rxq->elts)[i]);
 352                 (*rxq->elts)[i] = NULL;
 353         }
 354 }
 355
 356 /**
 357  * Free RX queue elements.
 358  *
 359  * @param rxq_ctrl
 360  *   Pointer to RX queue structure.
 361  */
 362 static void
 363 rxq_free_elts(struct mlx5_rxq_ctrl *rxq_ctrl)
 364 {
 365         if (mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq))
 366                 rxq_free_elts_mprq(rxq_ctrl);
 367         else
 368                 rxq_free_elts_sprq(rxq_ctrl);
 369 }
 370
 371 /**
 372  * Returns the per-queue supported offloads.
 373  *
 374  * @param dev
 375  *   Pointer to Ethernet device.
 376  *
 377  * @return
 378  *   Supported Rx offloads.
 379  */
 380 uint64_t
 381 mlx5_get_rx_queue_offloads(struct rte_eth_dev *dev)
 382 {
 383         struct mlx5_priv *priv = dev->data->dev_private;
 384         struct mlx5_dev_config *config = &priv->config;
 385         uint64_t offloads = (DEV_RX_OFFLOAD_SCATTER |
 386                              DEV_RX_OFFLOAD_TIMESTAMP |
 387                              DEV_RX_OFFLOAD_JUMBO_FRAME);
 388
 389         if (config->hw_fcs_strip)
 390                 offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
 391
 392         if (config->hw_csum)
 393                 offloads |= (DEV_RX_OFFLOAD_IPV4_CKSUM |
 394                              DEV_RX_OFFLOAD_UDP_CKSUM |
 395                              DEV_RX_OFFLOAD_TCP_CKSUM);
 396         if (config->hw_vlan_strip)
 397                 offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
 398         return offloads;
 399 }
 400
 401
 402 /**
 403  * Returns the per-port supported offloads.
 404  *
 405  * @param dev
 406  *   Pointer to Ethernet device.
 407  *
 408  * @return
 409  *   Supported Rx offloads.
 410  */
 411 uint64_t
 412 mlx5_get_rx_port_offloads(struct rte_eth_dev *dev)
 413 {
 414         uint64_t offloads = DEV_RX_OFFLOAD_VLAN_FILTER;
 415
 416         if (MLX5_LRO_SUPPORTED(dev))
 417                 offloads |= DEV_RX_OFFLOAD_TCP_LRO;
 418         return offloads;
 419 }
 420
 421 /**
 422  * Verify if the queue can be released.
 423  *
 424  * @param dev
 425  *   Pointer to Ethernet device.
 426  * @param idx
 427  *   RX queue index.
 428  *
 429  * @return
 430  *   1 if the queue can be released
 431  *   0 if the queue can not be released, there are references to it.
 432  *   Negative errno and rte_errno is set if queue doesn't exist.
 433  */
 434 static int
 435 mlx5_rxq_releasable(struct rte_eth_dev *dev, uint16_t idx)
 436 {
 437         struct mlx5_priv *priv = dev->data->dev_private;
 438         struct mlx5_rxq_ctrl *rxq_ctrl;
 439
 440         if (!(*priv->rxqs)[idx]) {
 441                 rte_errno = EINVAL;
 442                 return -rte_errno;
 443         }
 444         rxq_ctrl = container_of((*priv->rxqs)[idx], struct mlx5_rxq_ctrl, rxq);
 445         return (rte_atomic32_read(&rxq_ctrl->refcnt) == 1);
 446 }
 447
 448 /**
 449  *
 450  * @param dev
 451  *   Pointer to Ethernet device structure.
 452  * @param idx
 453  *   RX queue index.
 454  * @param desc
 455  *   Number of descriptors to configure in queue.
 456  * @param socket
 457  *   NUMA socket on which memory must be allocated.
 458  * @param[in] conf
 459  *   Thresholds parameters.
 460  * @param mp
 461  *   Memory pool for buffer allocations.
 462  *
 463  * @return
 464  *   0 on success, a negative errno value otherwise and rte_errno is set.
 465  */
 466 int
 467 mlx5_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
 468                     unsigned int socket, const struct rte_eth_rxconf *conf,
 469                     struct rte_mempool *mp)
 470 {
 471         struct mlx5_priv *priv = dev->data->dev_private;
 472         struct mlx5_rxq_data *rxq = (*priv->rxqs)[idx];
 473         struct mlx5_rxq_ctrl *rxq_ctrl =
 474                 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
 475
 476         if (!rte_is_power_of_2(desc)) {
 477                 desc = 1 << log2above(desc);
 478                 DRV_LOG(WARNING,
 479                         "port %u increased number of descriptors in Rx queue %u"
 480                         " to the next power of two (%d)",
 481                         dev->data->port_id, idx, desc);
 482         }
 483         DRV_LOG(DEBUG, "port %u configuring Rx queue %u for %u descriptors",
 484                 dev->data->port_id, idx, desc);
 485         if (idx >= priv->rxqs_n) {
 486                 DRV_LOG(ERR, "port %u Rx queue index out of range (%u >= %u)",
 487                         dev->data->port_id, idx, priv->rxqs_n);
 488                 rte_errno = EOVERFLOW;
 489                 return -rte_errno;
 490         }
 491         if (!mlx5_rxq_releasable(dev, idx)) {
 492                 DRV_LOG(ERR, "port %u unable to release queue index %u",
 493                         dev->data->port_id, idx);
 494                 rte_errno = EBUSY;
 495                 return -rte_errno;
 496         }
 497         mlx5_rxq_release(dev, idx);
 498         rxq_ctrl = mlx5_rxq_new(dev, idx, desc, socket, conf, mp);
 499         if (!rxq_ctrl) {
 500                 DRV_LOG(ERR, "port %u unable to allocate queue index %u",
 501                         dev->data->port_id, idx);
 502                 rte_errno = ENOMEM;
 503                 return -rte_errno;
 504         }
 505         DRV_LOG(DEBUG, "port %u adding Rx queue %u to list",
 506                 dev->data->port_id, idx);
 507         (*priv->rxqs)[idx] = &rxq_ctrl->rxq;
 508         return 0;
 509 }
 510
 511 /**
 512  * DPDK callback to release a RX queue.
 513  *
 514  * @param dpdk_rxq
 515  *   Generic RX queue pointer.
 516  */
 517 void
 518 mlx5_rx_queue_release(void *dpdk_rxq)
 519 {
 520         struct mlx5_rxq_data *rxq = (struct mlx5_rxq_data *)dpdk_rxq;
 521         struct mlx5_rxq_ctrl *rxq_ctrl;
 522         struct mlx5_priv *priv;
 523
 524         if (rxq == NULL)
 525                 return;
 526         rxq_ctrl = container_of(rxq, struct mlx5_rxq_ctrl, rxq);
 527         priv = rxq_ctrl->priv;
 528         if (!mlx5_rxq_releasable(ETH_DEV(priv), rxq_ctrl->rxq.idx))
 529                 rte_panic("port %u Rx queue %u is still used by a flow and"
 530                           " cannot be removed\n",
 531                           PORT_ID(priv), rxq->idx);
 532         mlx5_rxq_release(ETH_DEV(priv), rxq_ctrl->rxq.idx);
 533 }
 534
 535 /**
 536  * Get an Rx queue Verbs/DevX object.
 537  *
 538  * @param dev
 539  *   Pointer to Ethernet device.
 540  * @param idx
 541  *   Queue index in DPDK Rx queue array
 542  *
 543  * @return
 544  *   The Verbs/DevX object if it exists.
 545  */
 546 static struct mlx5_rxq_obj *
 547 mlx5_rxq_obj_get(struct rte_eth_dev *dev, uint16_t idx)
 548 {
 549         struct mlx5_priv *priv = dev->data->dev_private;
 550         struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
 551         struct mlx5_rxq_ctrl *rxq_ctrl;
 552
 553         if (idx >= priv->rxqs_n)
 554                 return NULL;
 555         if (!rxq_data)
 556                 return NULL;
 557         rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
 558         if (rxq_ctrl->obj)
 559                 rte_atomic32_inc(&rxq_ctrl->obj->refcnt);
 560         return rxq_ctrl->obj;
 561 }
 562
 563 /**
 564  * Release the resources allocated for an RQ DevX object.
 565  *
 566  * @param rxq_ctrl
 567  *   DevX Rx queue object.
 568  */
 569 static void
 570 rxq_release_rq_resources(struct mlx5_rxq_ctrl *rxq_ctrl)
 571 {
 572         if (rxq_ctrl->rxq.wqes) {
 573                 rte_free((void *)(uintptr_t)rxq_ctrl->rxq.wqes);
 574                 rxq_ctrl->rxq.wqes = NULL;
 575         }
 576         if (rxq_ctrl->wq_umem)
 577                 mlx5_glue->devx_umem_dereg(rxq_ctrl->wq_umem);
 578 }
 579
 580 /**
 581  * Release an Rx verbs/DevX queue object.
 582  *
 583  * @param rxq_obj
 584  *   Verbs/DevX Rx queue object.
 585  *
 586  * @return
 587  *   1 while a reference on it exists, 0 when freed.
 588  */
 589 static int
 590 mlx5_rxq_obj_release(struct mlx5_rxq_obj *rxq_obj)
 591 {
 592         assert(rxq_obj);
 593         if (rxq_obj->type == MLX5_RXQ_OBJ_TYPE_IBV)
 594                 assert(rxq_obj->wq);
 595         assert(rxq_obj->cq);
 596         if (rte_atomic32_dec_and_test(&rxq_obj->refcnt)) {
 597                 rxq_free_elts(rxq_obj->rxq_ctrl);
 598                 if (rxq_obj->type == MLX5_RXQ_OBJ_TYPE_IBV) {
 599                         claim_zero(mlx5_glue->destroy_wq(rxq_obj->wq));
 600                 } else if (rxq_obj->type == MLX5_RXQ_OBJ_TYPE_DEVX_RQ) {
 601                         claim_zero(mlx5_devx_cmd_destroy(rxq_obj->rq));
 602                         rxq_release_rq_resources(rxq_obj->rxq_ctrl);
 603                 }
 604                 claim_zero(mlx5_glue->destroy_cq(rxq_obj->cq));
 605                 if (rxq_obj->channel)
 606                         claim_zero(mlx5_glue->destroy_comp_channel
 607                                    (rxq_obj->channel));
 608                 LIST_REMOVE(rxq_obj, next);
 609                 rte_free(rxq_obj);
 610                 return 0;
 611         }
 612         return 1;
 613 }
 614
 615 /**
 616  * Allocate queue vector and fill epoll fd list for Rx interrupts.
 617  *
 618  * @param dev
 619  *   Pointer to Ethernet device.
 620  *
 621  * @return
 622  *   0 on success, a negative errno value otherwise and rte_errno is set.
 623  */
 624 int
 625 mlx5_rx_intr_vec_enable(struct rte_eth_dev *dev)
 626 {
 627         struct mlx5_priv *priv = dev->data->dev_private;
 628         unsigned int i;
 629         unsigned int rxqs_n = priv->rxqs_n;
 630         unsigned int n = RTE_MIN(rxqs_n, (uint32_t)RTE_MAX_RXTX_INTR_VEC_ID);
 631         unsigned int count = 0;
 632         struct rte_intr_handle *intr_handle = dev->intr_handle;
 633
 634         if (!dev->data->dev_conf.intr_conf.rxq)
 635                 return 0;
 636         mlx5_rx_intr_vec_disable(dev);
 637         intr_handle->intr_vec = malloc(n * sizeof(intr_handle->intr_vec[0]));
 638         if (intr_handle->intr_vec == NULL) {
 639                 DRV_LOG(ERR,
 640                         "port %u failed to allocate memory for interrupt"
 641                         " vector, Rx interrupts will not be supported",
 642                         dev->data->port_id);
 643                 rte_errno = ENOMEM;
 644                 return -rte_errno;
 645         }
 646         intr_handle->type = RTE_INTR_HANDLE_EXT;
 647         for (i = 0; i != n; ++i) {
 648                 /* This rxq obj must not be released in this function. */
 649                 struct mlx5_rxq_obj *rxq_obj = mlx5_rxq_obj_get(dev, i);
 650                 int fd;
 651                 int flags;
 652                 int rc;
 653
 654                 /* Skip queues that cannot request interrupts. */
 655                 if (!rxq_obj || !rxq_obj->channel) {
 656                         /* Use invalid intr_vec[] index to disable entry. */
 657                         intr_handle->intr_vec[i] =
 658                                 RTE_INTR_VEC_RXTX_OFFSET +
 659                                 RTE_MAX_RXTX_INTR_VEC_ID;
 660                         continue;
 661                 }
 662                 if (count >= RTE_MAX_RXTX_INTR_VEC_ID) {
 663                         DRV_LOG(ERR,
 664                                 "port %u too many Rx queues for interrupt"
 665                                 " vector size (%d), Rx interrupts cannot be"
 666                                 " enabled",
 667                                 dev->data->port_id, RTE_MAX_RXTX_INTR_VEC_ID);
 668                         mlx5_rx_intr_vec_disable(dev);
 669                         rte_errno = ENOMEM;
 670                         return -rte_errno;
 671                 }
 672                 fd = rxq_obj->channel->fd;
 673                 flags = fcntl(fd, F_GETFL);
 674                 rc = fcntl(fd, F_SETFL, flags | O_NONBLOCK);
 675                 if (rc < 0) {
 676                         rte_errno = errno;
 677                         DRV_LOG(ERR,
 678                                 "port %u failed to make Rx interrupt file"
 679                                 " descriptor %d non-blocking for queue index"
 680                                 " %d",
 681                                 dev->data->port_id, fd, i);
 682                         mlx5_rx_intr_vec_disable(dev);
 683                         return -rte_errno;
 684                 }
 685                 intr_handle->intr_vec[i] = RTE_INTR_VEC_RXTX_OFFSET + count;
 686                 intr_handle->efds[count] = fd;
 687                 count++;
 688         }
 689         if (!count)
 690                 mlx5_rx_intr_vec_disable(dev);
 691         else
 692                 intr_handle->nb_efd = count;
 693         return 0;
 694 }
 695
 696 /**
 697  * Clean up Rx interrupts handler.
 698  *
 699  * @param dev
 700  *   Pointer to Ethernet device.
 701  */
 702 void
 703 mlx5_rx_intr_vec_disable(struct rte_eth_dev *dev)
 704 {
 705         struct mlx5_priv *priv = dev->data->dev_private;
 706         struct rte_intr_handle *intr_handle = dev->intr_handle;
 707         unsigned int i;
 708         unsigned int rxqs_n = priv->rxqs_n;
 709         unsigned int n = RTE_MIN(rxqs_n, (uint32_t)RTE_MAX_RXTX_INTR_VEC_ID);
 710
 711         if (!dev->data->dev_conf.intr_conf.rxq)
 712                 return;
 713         if (!intr_handle->intr_vec)
 714                 goto free;
 715         for (i = 0; i != n; ++i) {
 716                 struct mlx5_rxq_ctrl *rxq_ctrl;
 717                 struct mlx5_rxq_data *rxq_data;
 718
 719                 if (intr_handle->intr_vec[i] == RTE_INTR_VEC_RXTX_OFFSET +
 720                     RTE_MAX_RXTX_INTR_VEC_ID)
 721                         continue;
 722                 /**
 723                  * Need to access directly the queue to release the reference
 724                  * kept in mlx5_rx_intr_vec_enable().
 725                  */
 726                 rxq_data = (*priv->rxqs)[i];
 727                 rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
 728                 if (rxq_ctrl->obj)
 729                         mlx5_rxq_obj_release(rxq_ctrl->obj);
 730         }
 731 free:
 732         rte_intr_free_epoll_fd(intr_handle);
 733         if (intr_handle->intr_vec)
 734                 free(intr_handle->intr_vec);
 735         intr_handle->nb_efd = 0;
 736         intr_handle->intr_vec = NULL;
 737 }
 738
 739 /**
 740  *  MLX5 CQ notification .
 741  *
 742  *  @param rxq
 743  *     Pointer to receive queue structure.
 744  *  @param sq_n_rxq
 745  *     Sequence number per receive queue .
 746  */
 747 static inline void
 748 mlx5_arm_cq(struct mlx5_rxq_data *rxq, int sq_n_rxq)
 749 {
 750         int sq_n = 0;
 751         uint32_t doorbell_hi;
 752         uint64_t doorbell;
 753         void *cq_db_reg = (char *)rxq->cq_uar + MLX5_CQ_DOORBELL;
 754
 755         sq_n = sq_n_rxq & MLX5_CQ_SQN_MASK;
 756         doorbell_hi = sq_n << MLX5_CQ_SQN_OFFSET | (rxq->cq_ci & MLX5_CI_MASK);
 757         doorbell = (uint64_t)doorbell_hi << 32;
 758         doorbell |=  rxq->cqn;
 759         rxq->cq_db[MLX5_CQ_ARM_DB] = rte_cpu_to_be_32(doorbell_hi);
 760         mlx5_uar_write64(rte_cpu_to_be_64(doorbell),
 761                          cq_db_reg, rxq->uar_lock_cq);
 762 }
 763
 764 /**
 765  * DPDK callback for Rx queue interrupt enable.
 766  *
 767  * @param dev
 768  *   Pointer to Ethernet device structure.
 769  * @param rx_queue_id
 770  *   Rx queue number.
 771  *
 772  * @return
 773  *   0 on success, a negative errno value otherwise and rte_errno is set.
 774  */
 775 int
 776 mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 777 {
 778         struct mlx5_priv *priv = dev->data->dev_private;
 779         struct mlx5_rxq_data *rxq_data;
 780         struct mlx5_rxq_ctrl *rxq_ctrl;
 781
 782         rxq_data = (*priv->rxqs)[rx_queue_id];
 783         if (!rxq_data) {
 784                 rte_errno = EINVAL;
 785                 return -rte_errno;
 786         }
 787         rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
 788         if (rxq_ctrl->irq) {
 789                 struct mlx5_rxq_obj *rxq_obj;
 790
 791                 rxq_obj = mlx5_rxq_obj_get(dev, rx_queue_id);
 792                 if (!rxq_obj) {
 793                         rte_errno = EINVAL;
 794                         return -rte_errno;
 795                 }
 796                 mlx5_arm_cq(rxq_data, rxq_data->cq_arm_sn);
 797                 mlx5_rxq_obj_release(rxq_obj);
 798         }
 799         return 0;
 800 }
 801
 802 /**
 803  * DPDK callback for Rx queue interrupt disable.
 804  *
 805  * @param dev
 806  *   Pointer to Ethernet device structure.
 807  * @param rx_queue_id
 808  *   Rx queue number.
 809  *
 810  * @return
 811  *   0 on success, a negative errno value otherwise and rte_errno is set.
 812  */
 813 int
 814 mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 815 {
 816         struct mlx5_priv *priv = dev->data->dev_private;
 817         struct mlx5_rxq_data *rxq_data;
 818         struct mlx5_rxq_ctrl *rxq_ctrl;
 819         struct mlx5_rxq_obj *rxq_obj = NULL;
 820         struct ibv_cq *ev_cq;
 821         void *ev_ctx;
 822         int ret;
 823
 824         rxq_data = (*priv->rxqs)[rx_queue_id];
 825         if (!rxq_data) {
 826                 rte_errno = EINVAL;
 827                 return -rte_errno;
 828         }
 829         rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
 830         if (!rxq_ctrl->irq)
 831                 return 0;
 832         rxq_obj = mlx5_rxq_obj_get(dev, rx_queue_id);
 833         if (!rxq_obj) {
 834                 rte_errno = EINVAL;
 835                 return -rte_errno;
 836         }
 837         ret = mlx5_glue->get_cq_event(rxq_obj->channel, &ev_cq, &ev_ctx);
 838         if (ret || ev_cq != rxq_obj->cq) {
 839                 rte_errno = EINVAL;
 840                 goto exit;
 841         }
 842         rxq_data->cq_arm_sn++;
 843         mlx5_glue->ack_cq_events(rxq_obj->cq, 1);
 844         mlx5_rxq_obj_release(rxq_obj);
 845         return 0;
 846 exit:
 847         ret = rte_errno; /* Save rte_errno before cleanup. */
 848         if (rxq_obj)
 849                 mlx5_rxq_obj_release(rxq_obj);
 850         DRV_LOG(WARNING, "port %u unable to disable interrupt on Rx queue %d",
 851                 dev->data->port_id, rx_queue_id);
 852         rte_errno = ret; /* Restore rte_errno. */
 853         return -rte_errno;
 854 }
 855
 856 /**
 857  * Create a CQ Verbs object.
 858  *
 859  * @param dev
 860  *   Pointer to Ethernet device.
 861  * @param priv
 862  *   Pointer to device private data.
 863  * @param rxq_data
 864  *   Pointer to Rx queue data.
 865  * @param cqe_n
 866  *   Number of CQEs in CQ.
 867  * @param rxq_obj
 868  *   Pointer to Rx queue object data.
 869  *
 870  * @return
 871  *   The Verbs object initialised, NULL otherwise and rte_errno is set.
 872  */
 873 static struct ibv_cq *
 874 mlx5_ibv_cq_new(struct rte_eth_dev *dev, struct mlx5_priv *priv,
 875                 struct mlx5_rxq_data *rxq_data,
 876                 unsigned int cqe_n, struct mlx5_rxq_obj *rxq_obj)
 877 {
 878         struct {
 879                 struct ibv_cq_init_attr_ex ibv;
 880                 struct mlx5dv_cq_init_attr mlx5;
 881         } cq_attr;
 882
 883         cq_attr.ibv = (struct ibv_cq_init_attr_ex){
 884                 .cqe = cqe_n,
 885                 .channel = rxq_obj->channel,
 886                 .comp_mask = 0,
 887         };
 888         cq_attr.mlx5 = (struct mlx5dv_cq_init_attr){
 889                 .comp_mask = 0,
 890         };
 891         if (priv->config.cqe_comp && !rxq_data->hw_timestamp) {
 892                 cq_attr.mlx5.comp_mask |=
 893                                 MLX5DV_CQ_INIT_ATTR_MASK_COMPRESSED_CQE;
 894 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
 895                 cq_attr.mlx5.cqe_comp_res_format =
 896                                 mlx5_rxq_mprq_enabled(rxq_data) ?
 897                                 MLX5DV_CQE_RES_FORMAT_CSUM_STRIDX :
 898                                 MLX5DV_CQE_RES_FORMAT_HASH;
 899 #else
 900                 cq_attr.mlx5.cqe_comp_res_format = MLX5DV_CQE_RES_FORMAT_HASH;
 901 #endif
 902                 /*
 903                  * For vectorized Rx, it must not be doubled in order to
 904                  * make cq_ci and rq_ci aligned.
 905                  */
 906                 if (mlx5_rxq_check_vec_support(rxq_data) < 0)
 907                         cq_attr.ibv.cqe *= 2;
 908         } else if (priv->config.cqe_comp && rxq_data->hw_timestamp) {
 909                 DRV_LOG(DEBUG,
 910                         "port %u Rx CQE compression is disabled for HW"
 911                         " timestamp",
 912                         dev->data->port_id);
 913         }
 914 #ifdef HAVE_IBV_MLX5_MOD_CQE_128B_PAD
 915         if (priv->config.cqe_pad) {
 916                 cq_attr.mlx5.comp_mask |= MLX5DV_CQ_INIT_ATTR_MASK_FLAGS;
 917                 cq_attr.mlx5.flags |= MLX5DV_CQ_INIT_ATTR_FLAGS_CQE_PAD;
 918         }
 919 #endif
 920         return mlx5_glue->cq_ex_to_cq(mlx5_glue->dv_create_cq(priv->sh->ctx,
 921                                                               &cq_attr.ibv,
 922                                                               &cq_attr.mlx5));
 923 }
 924
 925 /**
 926  * Create a WQ Verbs object.
 927  *
 928  * @param dev
 929  *   Pointer to Ethernet device.
 930  * @param priv
 931  *   Pointer to device private data.
 932  * @param rxq_data
 933  *   Pointer to Rx queue data.
 934  * @param idx
 935  *   Queue index in DPDK Rx queue array
 936  * @param wqe_n
 937  *   Number of WQEs in WQ.
 938  * @param rxq_obj
 939  *   Pointer to Rx queue object data.
 940  *
 941  * @return
 942  *   The Verbs object initialised, NULL otherwise and rte_errno is set.
 943  */
 944 static struct ibv_wq *
 945 mlx5_ibv_wq_new(struct rte_eth_dev *dev, struct mlx5_priv *priv,
 946                 struct mlx5_rxq_data *rxq_data, uint16_t idx,
 947                 unsigned int wqe_n, struct mlx5_rxq_obj *rxq_obj)
 948 {
 949         struct {
 950                 struct ibv_wq_init_attr ibv;
 951 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
 952                 struct mlx5dv_wq_init_attr mlx5;
 953 #endif
 954         } wq_attr;
 955
 956         wq_attr.ibv = (struct ibv_wq_init_attr){
 957                 .wq_context = NULL, /* Could be useful in the future. */
 958                 .wq_type = IBV_WQT_RQ,
 959                 /* Max number of outstanding WRs. */
 960                 .max_wr = wqe_n >> rxq_data->sges_n,
 961                 /* Max number of scatter/gather elements in a WR. */
 962                 .max_sge = 1 << rxq_data->sges_n,
 963                 .pd = priv->sh->pd,
 964                 .cq = rxq_obj->cq,
 965                 .comp_mask = IBV_WQ_FLAGS_CVLAN_STRIPPING | 0,
 966                 .create_flags = (rxq_data->vlan_strip ?
 967                                  IBV_WQ_FLAGS_CVLAN_STRIPPING : 0),
 968         };
 969         /* By default, FCS (CRC) is stripped by hardware. */
 970         if (rxq_data->crc_present) {
 971                 wq_attr.ibv.create_flags |= IBV_WQ_FLAGS_SCATTER_FCS;
 972                 wq_attr.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
 973         }
 974         if (priv->config.hw_padding) {
 975 #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING)
 976                 wq_attr.ibv.create_flags |= IBV_WQ_FLAG_RX_END_PADDING;
 977                 wq_attr.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
 978 #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING)
 979                 wq_attr.ibv.create_flags |= IBV_WQ_FLAGS_PCI_WRITE_END_PADDING;
 980                 wq_attr.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
 981 #endif
 982         }
 983 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
 984         wq_attr.mlx5 = (struct mlx5dv_wq_init_attr){
 985                 .comp_mask = 0,
 986         };
 987         if (mlx5_rxq_mprq_enabled(rxq_data)) {
 988                 struct mlx5dv_striding_rq_init_attr *mprq_attr =
 989                                                 &wq_attr.mlx5.striding_rq_attrs;
 990
 991                 wq_attr.mlx5.comp_mask |= MLX5DV_WQ_INIT_ATTR_MASK_STRIDING_RQ;
 992                 *mprq_attr = (struct mlx5dv_striding_rq_init_attr){
 993                         .single_stride_log_num_of_bytes = rxq_data->strd_sz_n,
 994                         .single_wqe_log_num_of_strides = rxq_data->strd_num_n,
 995                         .two_byte_shift_en = MLX5_MPRQ_TWO_BYTE_SHIFT,
 996                 };
 997         }
 998         rxq_obj->wq = mlx5_glue->dv_create_wq(priv->sh->ctx, &wq_attr.ibv,
 999                                               &wq_attr.mlx5);
1000 #else
1001         rxq_obj->wq = mlx5_glue->create_wq(priv->sh->ctx, &wq_attr.ibv);
1002 #endif
1003         if (rxq_obj->wq) {
1004                 /*
1005                  * Make sure number of WRs*SGEs match expectations since a queue
1006                  * cannot allocate more than "desc" buffers.
1007                  */
1008                 if (wq_attr.ibv.max_wr != (wqe_n >> rxq_data->sges_n) ||
1009                     wq_attr.ibv.max_sge != (1u << rxq_data->sges_n)) {
1010                         DRV_LOG(ERR,
1011                                 "port %u Rx queue %u requested %u*%u but got"
1012                                 " %u*%u WRs*SGEs",
1013                                 dev->data->port_id, idx,
1014                                 wqe_n >> rxq_data->sges_n,
1015                                 (1 << rxq_data->sges_n),
1016                                 wq_attr.ibv.max_wr, wq_attr.ibv.max_sge);
1017                         claim_zero(mlx5_glue->destroy_wq(rxq_obj->wq));
1018                         rxq_obj->wq = NULL;
1019                         rte_errno = EINVAL;
1020                 }
1021         }
1022         return rxq_obj->wq;
1023 }
1024
1025 /**
1026  * Fill common fields of create RQ attributes structure.
1027  *
1028  * @param rxq_data
1029  *   Pointer to Rx queue data.
1030  * @param cqn
1031  *   CQ number to use with this RQ.
1032  * @param rq_attr
1033  *   RQ attributes structure to fill..
1034  */
1035 static void
1036 mlx5_devx_create_rq_attr_fill(struct mlx5_rxq_data *rxq_data, uint32_t cqn,
1037                               struct mlx5_devx_create_rq_attr *rq_attr)
1038 {
1039         rq_attr->state = MLX5_RQC_STATE_RST;
1040         rq_attr->vsd = (rxq_data->vlan_strip) ? 0 : 1;
1041         rq_attr->cqn = cqn;
1042         rq_attr->scatter_fcs = (rxq_data->crc_present) ? 1 : 0;
1043 }
1044
1045 /**
1046  * Fill common fields of DevX WQ attributes structure.
1047  *
1048  * @param priv
1049  *   Pointer to device private data.
1050  * @param rxq_ctrl
1051  *   Pointer to Rx queue control structure.
1052  * @param wq_attr
1053  *   WQ attributes structure to fill..
1054  */
1055 static void
1056 mlx5_devx_wq_attr_fill(struct mlx5_priv *priv, struct mlx5_rxq_ctrl *rxq_ctrl,
1057                        struct mlx5_devx_wq_attr *wq_attr)
1058 {
1059         wq_attr->end_padding_mode = priv->config.cqe_pad ?
1060                                         MLX5_WQ_END_PAD_MODE_ALIGN :
1061                                         MLX5_WQ_END_PAD_MODE_NONE;
1062         wq_attr->pd = priv->sh->pdn;
1063         wq_attr->dbr_addr = rxq_ctrl->dbr_offset;
1064         wq_attr->dbr_umem_id = rxq_ctrl->dbr_umem_id;
1065         wq_attr->dbr_umem_valid = 1;
1066         wq_attr->wq_umem_id = rxq_ctrl->wq_umem->umem_id;
1067         wq_attr->wq_umem_valid = 1;
1068 }
1069
1070 /**
1071  * Create a RQ object using DevX.
1072  *
1073  * @param dev
1074  *   Pointer to Ethernet device.
1075  * @param idx
1076  *   Queue index in DPDK Rx queue array
1077  * @param cqn
1078  *   CQ number to use with this RQ.
1079  *
1080  * @return
1081  *   The DevX object initialised, NULL otherwise and rte_errno is set.
1082  */
1083 static struct mlx5_devx_obj *
1084 mlx5_devx_rq_new(struct rte_eth_dev *dev, uint16_t idx, uint32_t cqn)
1085 {
1086         struct mlx5_priv *priv = dev->data->dev_private;
1087         struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
1088         struct mlx5_rxq_ctrl *rxq_ctrl =
1089                 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
1090         struct mlx5_devx_create_rq_attr rq_attr;
1091         uint32_t wqe_n = 1 << rxq_data->elts_n;
1092         uint32_t wq_size = 0;
1093         uint32_t wqe_size = 0;
1094         uint32_t log_wqe_size = 0;
1095         void *buf = NULL;
1096         struct mlx5_devx_obj *rq;
1097
1098         memset(&rq_attr, 0, sizeof(rq_attr));
1099         /* Fill RQ attributes. */
1100         rq_attr.mem_rq_type = MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE;
1101         rq_attr.flush_in_error_en = 1;
1102         mlx5_devx_create_rq_attr_fill(rxq_data, cqn, &rq_attr);
1103         /* Fill WQ attributes for this RQ. */
1104         if (mlx5_rxq_mprq_enabled(rxq_data)) {
1105                 rq_attr.wq_attr.wq_type = MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ;
1106                 /*
1107                  * Number of strides in each WQE:
1108                  * 512*2^single_wqe_log_num_of_strides.
1109                  */
1110                 rq_attr.wq_attr.single_wqe_log_num_of_strides =
1111                                 rxq_data->strd_num_n -
1112                                 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1113                 /* Stride size = (2^single_stride_log_num_of_bytes)*64B. */
1114                 rq_attr.wq_attr.single_stride_log_num_of_bytes =
1115                                 rxq_data->strd_sz_n -
1116                                 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
1117                 wqe_size = sizeof(struct mlx5_wqe_mprq);
1118         } else {
1119                 int max_sge = 0;
1120                 int num_scatter = 0;
1121
1122                 rq_attr.wq_attr.wq_type = MLX5_WQ_TYPE_CYCLIC;
1123                 max_sge = 1 << rxq_data->sges_n;
1124                 num_scatter = RTE_MAX(max_sge, 1);
1125                 wqe_size = sizeof(struct mlx5_wqe_data_seg) * num_scatter;
1126         }
1127         log_wqe_size = log2above(wqe_size);
1128         rq_attr.wq_attr.log_wq_stride = log_wqe_size;
1129         rq_attr.wq_attr.log_wq_sz = rxq_data->elts_n;
1130         /* Calculate and allocate WQ memory space. */
1131         wqe_size = 1 << log_wqe_size; /* round up power of two.*/
1132         wq_size = wqe_n * wqe_size;
1133         buf = rte_calloc_socket(__func__, 1, wq_size, RTE_CACHE_LINE_SIZE,
1134                                 rxq_ctrl->socket);
1135         if (!buf)
1136                 return NULL;
1137         rxq_data->wqes = buf;
1138         rxq_ctrl->wq_umem = mlx5_glue->devx_umem_reg(priv->sh->ctx,
1139                                                      buf, wq_size, 0);
1140         if (!rxq_ctrl->wq_umem) {
1141                 rte_free(buf);
1142                 return NULL;
1143         }
1144         mlx5_devx_wq_attr_fill(priv, rxq_ctrl, &rq_attr.wq_attr);
1145         rq = mlx5_devx_cmd_create_rq(priv->sh->ctx, &rq_attr, rxq_ctrl->socket);
1146         if (!rq)
1147                 rxq_release_rq_resources(rxq_ctrl);
1148         return rq;
1149 }
1150
1151 /**
1152  * Create the Rx queue Verbs/DevX object.
1153  *
1154  * @param dev
1155  *   Pointer to Ethernet device.
1156  * @param idx
1157  *   Queue index in DPDK Rx queue array
1158  * @param type
1159  *   Type of Rx queue object to create.
1160  *
1161  * @return
1162  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
1163  */
1164 struct mlx5_rxq_obj *
1165 mlx5_rxq_obj_new(struct rte_eth_dev *dev, uint16_t idx,
1166                  enum mlx5_rxq_obj_type type)
1167 {
1168         struct mlx5_priv *priv = dev->data->dev_private;
1169         struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
1170         struct mlx5_rxq_ctrl *rxq_ctrl =
1171                 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
1172         struct ibv_wq_attr mod;
1173         unsigned int cqe_n;
1174         unsigned int wqe_n = 1 << rxq_data->elts_n;
1175         struct mlx5_rxq_obj *tmpl = NULL;
1176         struct mlx5dv_cq cq_info;
1177         struct mlx5dv_rwq rwq;
1178         int ret = 0;
1179         struct mlx5dv_obj obj;
1180
1181         assert(rxq_data);
1182         assert(!rxq_ctrl->obj);
1183         priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_RX_QUEUE;
1184         priv->verbs_alloc_ctx.obj = rxq_ctrl;
1185         tmpl = rte_calloc_socket(__func__, 1, sizeof(*tmpl), 0,
1186                                  rxq_ctrl->socket);
1187         if (!tmpl) {
1188                 DRV_LOG(ERR,
1189                         "port %u Rx queue %u cannot allocate verbs resources",
1190                         dev->data->port_id, rxq_data->idx);
1191                 rte_errno = ENOMEM;
1192                 goto error;
1193         }
1194         tmpl->type = type;
1195         tmpl->rxq_ctrl = rxq_ctrl;
1196         if (rxq_ctrl->irq) {
1197                 tmpl->channel = mlx5_glue->create_comp_channel(priv->sh->ctx);
1198                 if (!tmpl->channel) {
1199                         DRV_LOG(ERR, "port %u: comp channel creation failure",
1200                                 dev->data->port_id);
1201                         rte_errno = ENOMEM;
1202                         goto error;
1203                 }
1204         }
1205         if (mlx5_rxq_mprq_enabled(rxq_data))
1206                 cqe_n = wqe_n * (1 << rxq_data->strd_num_n) - 1;
1207         else
1208                 cqe_n = wqe_n  - 1;
1209         tmpl->cq = mlx5_ibv_cq_new(dev, priv, rxq_data, cqe_n, tmpl);
1210         if (!tmpl->cq) {
1211                 DRV_LOG(ERR, "port %u Rx queue %u CQ creation failure",
1212                         dev->data->port_id, idx);
1213                 rte_errno = ENOMEM;
1214                 goto error;
1215         }
1216         obj.cq.in = tmpl->cq;
1217         obj.cq.out = &cq_info;
1218         ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_CQ);
1219         if (ret) {
1220                 rte_errno = ret;
1221                 goto error;
1222         }
1223         if (cq_info.cqe_size != RTE_CACHE_LINE_SIZE) {
1224                 DRV_LOG(ERR,
1225                         "port %u wrong MLX5_CQE_SIZE environment variable"
1226                         " value: it should be set to %u",
1227                         dev->data->port_id, RTE_CACHE_LINE_SIZE);
1228                 rte_errno = EINVAL;
1229                 goto error;
1230         }
1231         DRV_LOG(DEBUG, "port %u device_attr.max_qp_wr is %d",
1232                 dev->data->port_id, priv->sh->device_attr.orig_attr.max_qp_wr);
1233         DRV_LOG(DEBUG, "port %u device_attr.max_sge is %d",
1234                 dev->data->port_id, priv->sh->device_attr.orig_attr.max_sge);
1235         /* Allocate door-bell for types created with DevX. */
1236         if (tmpl->type != MLX5_RXQ_OBJ_TYPE_IBV) {
1237                 struct mlx5_devx_dbr_page *dbr_page;
1238                 int64_t dbr_offset;
1239
1240                 dbr_offset = mlx5_get_dbr(dev, &dbr_page);
1241                 if (dbr_offset < 0)
1242                         goto error;
1243                 rxq_ctrl->dbr_offset = dbr_offset;
1244                 rxq_ctrl->dbr_umem_id = dbr_page->umem->umem_id;
1245                 rxq_data->rq_db = (uint32_t *)((uintptr_t)dbr_page->dbrs +
1246                                                (uintptr_t)rxq_ctrl->dbr_offset);
1247         }
1248         if (tmpl->type == MLX5_RXQ_OBJ_TYPE_IBV) {
1249                 tmpl->wq = mlx5_ibv_wq_new(dev, priv, rxq_data, idx, wqe_n,
1250                                            tmpl);
1251                 if (!tmpl->wq) {
1252                         DRV_LOG(ERR, "port %u Rx queue %u WQ creation failure",
1253                                 dev->data->port_id, idx);
1254                         rte_errno = ENOMEM;
1255                         goto error;
1256                 }
1257                 /* Change queue state to ready. */
1258                 mod = (struct ibv_wq_attr){
1259                         .attr_mask = IBV_WQ_ATTR_STATE,
1260                         .wq_state = IBV_WQS_RDY,
1261                 };
1262                 ret = mlx5_glue->modify_wq(tmpl->wq, &mod);
1263                 if (ret) {
1264                         DRV_LOG(ERR,
1265                                 "port %u Rx queue %u WQ state to IBV_WQS_RDY"
1266                                 " failed", dev->data->port_id, idx);
1267                         rte_errno = ret;
1268                         goto error;
1269                 }
1270                 obj.rwq.in = tmpl->wq;
1271                 obj.rwq.out = &rwq;
1272                 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_RWQ);
1273                 if (ret) {
1274                         rte_errno = ret;
1275                         goto error;
1276                 }
1277                 rxq_data->wqes = rwq.buf;
1278                 rxq_data->rq_db = rwq.dbrec;
1279         } else if (tmpl->type == MLX5_RXQ_OBJ_TYPE_DEVX_RQ) {
1280                 struct mlx5_devx_modify_rq_attr rq_attr;
1281
1282                 memset(&rq_attr, 0, sizeof(rq_attr));
1283                 tmpl->rq = mlx5_devx_rq_new(dev, idx, cq_info.cqn);
1284                 if (!tmpl->rq) {
1285                         DRV_LOG(ERR, "port %u Rx queue %u RQ creation failure",
1286                                 dev->data->port_id, idx);
1287                         rte_errno = ENOMEM;
1288                         goto error;
1289                 }
1290                 /* Change queue state to ready. */
1291                 rq_attr.rq_state = MLX5_RQC_STATE_RST;
1292                 rq_attr.state = MLX5_RQC_STATE_RDY;
1293                 ret = mlx5_devx_cmd_modify_rq(tmpl->rq, &rq_attr);
1294                 if (ret)
1295                         goto error;
1296         }
1297         /* Fill the rings. */
1298         rxq_data->cqe_n = log2above(cq_info.cqe_cnt);
1299         rxq_data->cq_db = cq_info.dbrec;
1300         rxq_data->cqes = (volatile struct mlx5_cqe (*)[])(uintptr_t)cq_info.buf;
1301         rxq_data->cq_uar = cq_info.cq_uar;
1302         rxq_data->cqn = cq_info.cqn;
1303         rxq_data->cq_arm_sn = 0;
1304         mlx5_rxq_initialize(rxq_data);
1305         rxq_data->cq_ci = 0;
1306         DRV_LOG(DEBUG, "port %u rxq %u updated with %p", dev->data->port_id,
1307                 idx, (void *)&tmpl);
1308         rte_atomic32_inc(&tmpl->refcnt);
1309         LIST_INSERT_HEAD(&priv->rxqsobj, tmpl, next);
1310         priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
1311         return tmpl;
1312 error:
1313         if (tmpl) {
1314                 ret = rte_errno; /* Save rte_errno before cleanup. */
1315                 if (tmpl->type == MLX5_RXQ_OBJ_TYPE_IBV && tmpl->wq)
1316                         claim_zero(mlx5_glue->destroy_wq(tmpl->wq));
1317                 else if (tmpl->type == MLX5_RXQ_OBJ_TYPE_DEVX_RQ && tmpl->rq)
1318                         claim_zero(mlx5_devx_cmd_destroy(tmpl->rq));
1319                 if (tmpl->cq)
1320                         claim_zero(mlx5_glue->destroy_cq(tmpl->cq));
1321                 if (tmpl->channel)
1322                         claim_zero(mlx5_glue->destroy_comp_channel
1323                                                         (tmpl->channel));
1324                 rte_free(tmpl);
1325                 rte_errno = ret; /* Restore rte_errno. */
1326         }
1327         if (type == MLX5_RXQ_OBJ_TYPE_DEVX_RQ)
1328                 rxq_release_rq_resources(rxq_ctrl);
1329         priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
1330         return NULL;
1331 }
1332
1333 /**
1334  * Verify the Rx queue objects list is empty
1335  *
1336  * @param dev
1337  *   Pointer to Ethernet device.
1338  *
1339  * @return
1340  *   The number of objects not released.
1341  */
1342 int
1343 mlx5_rxq_obj_verify(struct rte_eth_dev *dev)
1344 {
1345         struct mlx5_priv *priv = dev->data->dev_private;
1346         int ret = 0;
1347         struct mlx5_rxq_obj *rxq_obj;
1348
1349         LIST_FOREACH(rxq_obj, &priv->rxqsobj, next) {
1350                 DRV_LOG(DEBUG, "port %u Rx queue %u still referenced",
1351                         dev->data->port_id, rxq_obj->rxq_ctrl->rxq.idx);
1352                 ++ret;
1353         }
1354         return ret;
1355 }
1356
1357 /**
1358  * Callback function to initialize mbufs for Multi-Packet RQ.
1359  */
1360 static inline void
1361 mlx5_mprq_buf_init(struct rte_mempool *mp, void *opaque_arg,
1362                     void *_m, unsigned int i __rte_unused)
1363 {
1364         struct mlx5_mprq_buf *buf = _m;
1365         struct rte_mbuf_ext_shared_info *shinfo;
1366         unsigned int strd_n = (unsigned int)(uintptr_t)opaque_arg;
1367         unsigned int j;
1368
1369         memset(_m, 0, sizeof(*buf));
1370         buf->mp = mp;
1371         rte_atomic16_set(&buf->refcnt, 1);
1372         for (j = 0; j != strd_n; ++j) {
1373                 shinfo = &buf->shinfos[j];
1374                 shinfo->free_cb = mlx5_mprq_buf_free_cb;
1375                 shinfo->fcb_opaque = buf;
1376         }
1377 }
1378
1379 /**
1380  * Free mempool of Multi-Packet RQ.
1381  *
1382  * @param dev
1383  *   Pointer to Ethernet device.
1384  *
1385  * @return
1386  *   0 on success, negative errno value on failure.
1387  */
1388 int
1389 mlx5_mprq_free_mp(struct rte_eth_dev *dev)
1390 {
1391         struct mlx5_priv *priv = dev->data->dev_private;
1392         struct rte_mempool *mp = priv->mprq_mp;
1393         unsigned int i;
1394
1395         if (mp == NULL)
1396                 return 0;
1397         DRV_LOG(DEBUG, "port %u freeing mempool (%s) for Multi-Packet RQ",
1398                 dev->data->port_id, mp->name);
1399         /*
1400          * If a buffer in the pool has been externally attached to a mbuf and it
1401          * is still in use by application, destroying the Rx queue can spoil
1402          * the packet. It is unlikely to happen but if application dynamically
1403          * creates and destroys with holding Rx packets, this can happen.
1404          *
1405          * TODO: It is unavoidable for now because the mempool for Multi-Packet
1406          * RQ isn't provided by application but managed by PMD.
1407          */
1408         if (!rte_mempool_full(mp)) {
1409                 DRV_LOG(ERR,
1410                         "port %u mempool for Multi-Packet RQ is still in use",
1411                         dev->data->port_id);
1412                 rte_errno = EBUSY;
1413                 return -rte_errno;
1414         }
1415         rte_mempool_free(mp);
1416         /* Unset mempool for each Rx queue. */
1417         for (i = 0; i != priv->rxqs_n; ++i) {
1418                 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
1419
1420                 if (rxq == NULL)
1421                         continue;
1422                 rxq->mprq_mp = NULL;
1423         }
1424         priv->mprq_mp = NULL;
1425         return 0;
1426 }
1427
1428 /**
1429  * Allocate a mempool for Multi-Packet RQ. All configured Rx queues share the
1430  * mempool. If already allocated, reuse it if there're enough elements.
1431  * Otherwise, resize it.
1432  *
1433  * @param dev
1434  *   Pointer to Ethernet device.
1435  *
1436  * @return
1437  *   0 on success, negative errno value on failure.
1438  */
1439 int
1440 mlx5_mprq_alloc_mp(struct rte_eth_dev *dev)
1441 {
1442         struct mlx5_priv *priv = dev->data->dev_private;
1443         struct rte_mempool *mp = priv->mprq_mp;
1444         char name[RTE_MEMPOOL_NAMESIZE];
1445         unsigned int desc = 0;
1446         unsigned int buf_len;
1447         unsigned int obj_num;
1448         unsigned int obj_size;
1449         unsigned int strd_num_n = 0;
1450         unsigned int strd_sz_n = 0;
1451         unsigned int i;
1452
1453         if (!mlx5_mprq_enabled(dev))
1454                 return 0;
1455         /* Count the total number of descriptors configured. */
1456         for (i = 0; i != priv->rxqs_n; ++i) {
1457                 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
1458
1459                 if (rxq == NULL)
1460                         continue;
1461                 desc += 1 << rxq->elts_n;
1462                 /* Get the max number of strides. */
1463                 if (strd_num_n < rxq->strd_num_n)
1464                         strd_num_n = rxq->strd_num_n;
1465                 /* Get the max size of a stride. */
1466                 if (strd_sz_n < rxq->strd_sz_n)
1467                         strd_sz_n = rxq->strd_sz_n;
1468         }
1469         assert(strd_num_n && strd_sz_n);
1470         buf_len = (1 << strd_num_n) * (1 << strd_sz_n);
1471         obj_size = sizeof(struct mlx5_mprq_buf) + buf_len + (1 << strd_num_n) *
1472                 sizeof(struct rte_mbuf_ext_shared_info) + RTE_PKTMBUF_HEADROOM;
1473         /*
1474          * Received packets can be either memcpy'd or externally referenced. In
1475          * case that the packet is attached to an mbuf as an external buffer, as
1476          * it isn't possible to predict how the buffers will be queued by
1477          * application, there's no option to exactly pre-allocate needed buffers
1478          * in advance but to speculatively prepares enough buffers.
1479          *
1480          * In the data path, if this Mempool is depleted, PMD will try to memcpy
1481          * received packets to buffers provided by application (rxq->mp) until
1482          * this Mempool gets available again.
1483          */
1484         desc *= 4;
1485         obj_num = desc + MLX5_MPRQ_MP_CACHE_SZ * priv->rxqs_n;
1486         /*
1487          * rte_mempool_create_empty() has sanity check to refuse large cache
1488          * size compared to the number of elements.
1489          * CACHE_FLUSHTHRESH_MULTIPLIER is defined in a C file, so using a
1490          * constant number 2 instead.
1491          */
1492         obj_num = RTE_MAX(obj_num, MLX5_MPRQ_MP_CACHE_SZ * 2);
1493         /* Check a mempool is already allocated and if it can be resued. */
1494         if (mp != NULL && mp->elt_size >= obj_size && mp->size >= obj_num) {
1495                 DRV_LOG(DEBUG, "port %u mempool %s is being reused",
1496                         dev->data->port_id, mp->name);
1497                 /* Reuse. */
1498                 goto exit;
1499         } else if (mp != NULL) {
1500                 DRV_LOG(DEBUG, "port %u mempool %s should be resized, freeing it",
1501                         dev->data->port_id, mp->name);
1502                 /*
1503                  * If failed to free, which means it may be still in use, no way
1504                  * but to keep using the existing one. On buffer underrun,
1505                  * packets will be memcpy'd instead of external buffer
1506                  * attachment.
1507                  */
1508                 if (mlx5_mprq_free_mp(dev)) {
1509                         if (mp->elt_size >= obj_size)
1510                                 goto exit;
1511                         else
1512                                 return -rte_errno;
1513                 }
1514         }
1515         snprintf(name, sizeof(name), "port-%u-mprq", dev->data->port_id);
1516         mp = rte_mempool_create(name, obj_num, obj_size, MLX5_MPRQ_MP_CACHE_SZ,
1517                                 0, NULL, NULL, mlx5_mprq_buf_init,
1518                                 (void *)(uintptr_t)(1 << strd_num_n),
1519                                 dev->device->numa_node, 0);
1520         if (mp == NULL) {
1521                 DRV_LOG(ERR,
1522                         "port %u failed to allocate a mempool for"
1523                         " Multi-Packet RQ, count=%u, size=%u",
1524                         dev->data->port_id, obj_num, obj_size);
1525                 rte_errno = ENOMEM;
1526                 return -rte_errno;
1527         }
1528         priv->mprq_mp = mp;
1529 exit:
1530         /* Set mempool for each Rx queue. */
1531         for (i = 0; i != priv->rxqs_n; ++i) {
1532                 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
1533
1534                 if (rxq == NULL)
1535                         continue;
1536                 rxq->mprq_mp = mp;
1537         }
1538         DRV_LOG(INFO, "port %u Multi-Packet RQ is configured",
1539                 dev->data->port_id);
1540         return 0;
1541 }
1542
1543 /**
1544  * Create a DPDK Rx queue.
1545  *
1546  * @param dev
1547  *   Pointer to Ethernet device.
1548  * @param idx
1549  *   RX queue index.
1550  * @param desc
1551  *   Number of descriptors to configure in queue.
1552  * @param socket
1553  *   NUMA socket on which memory must be allocated.
1554  *
1555  * @return
1556  *   A DPDK queue object on success, NULL otherwise and rte_errno is set.
1557  */
1558 struct mlx5_rxq_ctrl *
1559 mlx5_rxq_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1560              unsigned int socket, const struct rte_eth_rxconf *conf,
1561              struct rte_mempool *mp)
1562 {
1563         struct mlx5_priv *priv = dev->data->dev_private;
1564         struct mlx5_rxq_ctrl *tmpl;
1565         unsigned int mb_len = rte_pktmbuf_data_room_size(mp);
1566         unsigned int mprq_stride_size;
1567         struct mlx5_dev_config *config = &priv->config;
1568         /*
1569          * LRO packet may consume all the stride memory, hence we cannot
1570          * guaranty head-room. A new striding RQ feature may be added in CX6 DX
1571          * to allow head-room and tail-room for the LRO packets.
1572          */
1573         unsigned int strd_headroom_en = mlx5_lro_on(dev) ? 0 : 1;
1574         /*
1575          * Always allocate extra slots, even if eventually
1576          * the vector Rx will not be used.
1577          */
1578         uint16_t desc_n =
1579                 desc + config->rx_vec_en * MLX5_VPMD_DESCS_PER_LOOP;
1580         uint64_t offloads = conf->offloads |
1581                            dev->data->dev_conf.rxmode.offloads;
1582         const int mprq_en = mlx5_check_mprq_support(dev) > 0;
1583
1584         tmpl = rte_calloc_socket("RXQ", 1,
1585                                  sizeof(*tmpl) +
1586                                  desc_n * sizeof(struct rte_mbuf *),
1587                                  0, socket);
1588         if (!tmpl) {
1589                 rte_errno = ENOMEM;
1590                 return NULL;
1591         }
1592         if (mlx5_mr_btree_init(&tmpl->rxq.mr_ctrl.cache_bh,
1593                                MLX5_MR_BTREE_CACHE_N, socket)) {
1594                 /* rte_errno is already set. */
1595                 goto error;
1596         }
1597         tmpl->socket = socket;
1598         if (dev->data->dev_conf.intr_conf.rxq)
1599                 tmpl->irq = 1;
1600         /*
1601          * This Rx queue can be configured as a Multi-Packet RQ if all of the
1602          * following conditions are met:
1603          *  - MPRQ is enabled.
1604          *  - The number of descs is more than the number of strides.
1605          *  - max_rx_pkt_len plus overhead is less than the max size of a
1606          *    stride.
1607          *  Otherwise, enable Rx scatter if necessary.
1608          */
1609         assert(mb_len >= RTE_PKTMBUF_HEADROOM * strd_headroom_en);
1610         mprq_stride_size = dev->data->dev_conf.rxmode.max_rx_pkt_len +
1611                                 RTE_PKTMBUF_HEADROOM * strd_headroom_en;
1612         if (mprq_en &&
1613             desc > (1U << config->mprq.stride_num_n) &&
1614             mprq_stride_size <= (1U << config->mprq.max_stride_size_n)) {
1615                 /* TODO: Rx scatter isn't supported yet. */
1616                 tmpl->rxq.sges_n = 0;
1617                 /* Trim the number of descs needed. */
1618                 desc >>= config->mprq.stride_num_n;
1619                 tmpl->rxq.strd_num_n = config->mprq.stride_num_n;
1620                 tmpl->rxq.strd_sz_n = RTE_MAX(log2above(mprq_stride_size),
1621                                               config->mprq.min_stride_size_n);
1622                 tmpl->rxq.strd_shift_en = MLX5_MPRQ_TWO_BYTE_SHIFT;
1623                 tmpl->rxq.strd_headroom_en = strd_headroom_en;
1624                 tmpl->rxq.mprq_max_memcpy_len = RTE_MIN(mb_len -
1625                             RTE_PKTMBUF_HEADROOM, config->mprq.max_memcpy_len);
1626                 DRV_LOG(DEBUG,
1627                         "port %u Rx queue %u: Multi-Packet RQ is enabled"
1628                         " strd_num_n = %u, strd_sz_n = %u",
1629                         dev->data->port_id, idx,
1630                         tmpl->rxq.strd_num_n, tmpl->rxq.strd_sz_n);
1631         } else if (dev->data->dev_conf.rxmode.max_rx_pkt_len <=
1632                    (mb_len - RTE_PKTMBUF_HEADROOM)) {
1633                 tmpl->rxq.sges_n = 0;
1634         } else if (offloads & DEV_RX_OFFLOAD_SCATTER) {
1635                 unsigned int size =
1636                         RTE_PKTMBUF_HEADROOM +
1637                         dev->data->dev_conf.rxmode.max_rx_pkt_len;
1638                 unsigned int sges_n;
1639
1640                 /*
1641                  * Determine the number of SGEs needed for a full packet
1642                  * and round it to the next power of two.
1643                  */
1644                 sges_n = log2above((size / mb_len) + !!(size % mb_len));
1645                 tmpl->rxq.sges_n = sges_n;
1646                 /* Make sure rxq.sges_n did not overflow. */
1647                 size = mb_len * (1 << tmpl->rxq.sges_n);
1648                 size -= RTE_PKTMBUF_HEADROOM;
1649                 if (size < dev->data->dev_conf.rxmode.max_rx_pkt_len) {
1650                         DRV_LOG(ERR,
1651                                 "port %u too many SGEs (%u) needed to handle"
1652                                 " requested maximum packet size %u",
1653                                 dev->data->port_id,
1654                                 1 << sges_n,
1655                                 dev->data->dev_conf.rxmode.max_rx_pkt_len);
1656                         rte_errno = EOVERFLOW;
1657                         goto error;
1658                 }
1659         } else {
1660                 DRV_LOG(WARNING,
1661                         "port %u the requested maximum Rx packet size (%u) is"
1662                         " larger than a single mbuf (%u) and scattered mode has"
1663                         " not been requested",
1664                         dev->data->port_id,
1665                         dev->data->dev_conf.rxmode.max_rx_pkt_len,
1666                         mb_len - RTE_PKTMBUF_HEADROOM);
1667         }
1668         if (mprq_en && !mlx5_rxq_mprq_enabled(&tmpl->rxq))
1669                 DRV_LOG(WARNING,
1670                         "port %u MPRQ is requested but cannot be enabled"
1671                         " (requested: desc = %u, stride_sz = %u,"
1672                         " supported: min_stride_num = %u, max_stride_sz = %u).",
1673                         dev->data->port_id, desc, mprq_stride_size,
1674                         (1 << config->mprq.stride_num_n),
1675                         (1 << config->mprq.max_stride_size_n));
1676         DRV_LOG(DEBUG, "port %u maximum number of segments per packet: %u",
1677                 dev->data->port_id, 1 << tmpl->rxq.sges_n);
1678         if (desc % (1 << tmpl->rxq.sges_n)) {
1679                 DRV_LOG(ERR,
1680                         "port %u number of Rx queue descriptors (%u) is not a"
1681                         " multiple of SGEs per packet (%u)",
1682                         dev->data->port_id,
1683                         desc,
1684                         1 << tmpl->rxq.sges_n);
1685                 rte_errno = EINVAL;
1686                 goto error;
1687         }
1688         /* Toggle RX checksum offload if hardware supports it. */
1689         tmpl->rxq.csum = !!(offloads & DEV_RX_OFFLOAD_CHECKSUM);
1690         tmpl->rxq.hw_timestamp = !!(offloads & DEV_RX_OFFLOAD_TIMESTAMP);
1691         /* Configure VLAN stripping. */
1692         tmpl->rxq.vlan_strip = !!(offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
1693         /* By default, FCS (CRC) is stripped by hardware. */
1694         tmpl->rxq.crc_present = 0;
1695         if (offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
1696                 if (config->hw_fcs_strip) {
1697                         /*
1698                          * RQs used for LRO-enabled TIRs should not be
1699                          * configured to scatter the FCS.
1700                          */
1701                         if (mlx5_lro_on(dev))
1702                                 DRV_LOG(WARNING,
1703                                         "port %u CRC stripping has been "
1704                                         "disabled but will still be performed "
1705                                         "by hardware, because LRO is enabled",
1706                                         dev->data->port_id);
1707                         else
1708                                 tmpl->rxq.crc_present = 1;
1709                 } else {
1710                         DRV_LOG(WARNING,
1711                                 "port %u CRC stripping has been disabled but will"
1712                                 " still be performed by hardware, make sure MLNX_OFED"
1713                                 " and firmware are up to date",
1714                                 dev->data->port_id);
1715                 }
1716         }
1717         DRV_LOG(DEBUG,
1718                 "port %u CRC stripping is %s, %u bytes will be subtracted from"
1719                 " incoming frames to hide it",
1720                 dev->data->port_id,
1721                 tmpl->rxq.crc_present ? "disabled" : "enabled",
1722                 tmpl->rxq.crc_present << 2);
1723         /* Save port ID. */
1724         tmpl->rxq.rss_hash = !!priv->rss_conf.rss_hf &&
1725                 (!!(dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS));
1726         tmpl->rxq.port_id = dev->data->port_id;
1727         tmpl->priv = priv;
1728         tmpl->rxq.mp = mp;
1729         tmpl->rxq.elts_n = log2above(desc);
1730         tmpl->rxq.rq_repl_thresh =
1731                 MLX5_VPMD_RXQ_RPLNSH_THRESH(1 << tmpl->rxq.elts_n);
1732         tmpl->rxq.elts =
1733                 (struct rte_mbuf *(*)[1 << tmpl->rxq.elts_n])(tmpl + 1);
1734 #ifndef RTE_ARCH_64
1735         tmpl->rxq.uar_lock_cq = &priv->uar_lock_cq;
1736 #endif
1737         tmpl->rxq.idx = idx;
1738         rte_atomic32_inc(&tmpl->refcnt);
1739         LIST_INSERT_HEAD(&priv->rxqsctrl, tmpl, next);
1740         return tmpl;
1741 error:
1742         rte_free(tmpl);
1743         return NULL;
1744 }
1745
1746 /**
1747  * Get a Rx queue.
1748  *
1749  * @param dev
1750  *   Pointer to Ethernet device.
1751  * @param idx
1752  *   RX queue index.
1753  *
1754  * @return
1755  *   A pointer to the queue if it exists, NULL otherwise.
1756  */
1757 struct mlx5_rxq_ctrl *
1758 mlx5_rxq_get(struct rte_eth_dev *dev, uint16_t idx)
1759 {
1760         struct mlx5_priv *priv = dev->data->dev_private;
1761         struct mlx5_rxq_ctrl *rxq_ctrl = NULL;
1762
1763         if ((*priv->rxqs)[idx]) {
1764                 rxq_ctrl = container_of((*priv->rxqs)[idx],
1765                                         struct mlx5_rxq_ctrl,
1766                                         rxq);
1767                 mlx5_rxq_obj_get(dev, idx);
1768                 rte_atomic32_inc(&rxq_ctrl->refcnt);
1769         }
1770         return rxq_ctrl;
1771 }
1772
1773 /**
1774  * Release a Rx queue.
1775  *
1776  * @param dev
1777  *   Pointer to Ethernet device.
1778  * @param idx
1779  *   RX queue index.
1780  *
1781  * @return
1782  *   1 while a reference on it exists, 0 when freed.
1783  */
1784 int
1785 mlx5_rxq_release(struct rte_eth_dev *dev, uint16_t idx)
1786 {
1787         struct mlx5_priv *priv = dev->data->dev_private;
1788         struct mlx5_rxq_ctrl *rxq_ctrl;
1789
1790         if (!(*priv->rxqs)[idx])
1791                 return 0;
1792         rxq_ctrl = container_of((*priv->rxqs)[idx], struct mlx5_rxq_ctrl, rxq);
1793         assert(rxq_ctrl->priv);
1794         if (rxq_ctrl->obj && !mlx5_rxq_obj_release(rxq_ctrl->obj))
1795                 rxq_ctrl->obj = NULL;
1796         if (rte_atomic32_dec_and_test(&rxq_ctrl->refcnt)) {
1797                 claim_zero(mlx5_release_dbr(dev, rxq_ctrl->dbr_umem_id,
1798                                             rxq_ctrl->dbr_offset));
1799                 mlx5_mr_btree_free(&rxq_ctrl->rxq.mr_ctrl.cache_bh);
1800                 LIST_REMOVE(rxq_ctrl, next);
1801                 rte_free(rxq_ctrl);
1802                 (*priv->rxqs)[idx] = NULL;
1803                 return 0;
1804         }
1805         return 1;
1806 }
1807
1808 /**
1809  * Verify the Rx Queue list is empty
1810  *
1811  * @param dev
1812  *   Pointer to Ethernet device.
1813  *
1814  * @return
1815  *   The number of object not released.
1816  */
1817 int
1818 mlx5_rxq_verify(struct rte_eth_dev *dev)
1819 {
1820         struct mlx5_priv *priv = dev->data->dev_private;
1821         struct mlx5_rxq_ctrl *rxq_ctrl;
1822         int ret = 0;
1823
1824         LIST_FOREACH(rxq_ctrl, &priv->rxqsctrl, next) {
1825                 DRV_LOG(DEBUG, "port %u Rx Queue %u still referenced",
1826                         dev->data->port_id, rxq_ctrl->rxq.idx);
1827                 ++ret;
1828         }
1829         return ret;
1830 }
1831
1832 /**
1833  * Create an indirection table.
1834  *
1835  * @param dev
1836  *   Pointer to Ethernet device.
1837  * @param queues
1838  *   Queues entering in the indirection table.
1839  * @param queues_n
1840  *   Number of queues in the array.
1841  *
1842  * @return
1843  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
1844  */
1845 static struct mlx5_ind_table_obj *
1846 mlx5_ind_table_obj_new(struct rte_eth_dev *dev, const uint16_t *queues,
1847                        uint32_t queues_n, enum mlx5_ind_tbl_type type)
1848 {
1849         struct mlx5_priv *priv = dev->data->dev_private;
1850         struct mlx5_ind_table_obj *ind_tbl;
1851         unsigned int i = 0, j = 0, k = 0;
1852
1853         ind_tbl = rte_calloc(__func__, 1, sizeof(*ind_tbl) +
1854                              queues_n * sizeof(uint16_t), 0);
1855         if (!ind_tbl) {
1856                 rte_errno = ENOMEM;
1857                 return NULL;
1858         }
1859         ind_tbl->type = type;
1860         if (ind_tbl->type == MLX5_IND_TBL_TYPE_IBV) {
1861                 const unsigned int wq_n = rte_is_power_of_2(queues_n) ?
1862                         log2above(queues_n) :
1863                         log2above(priv->config.ind_table_max_size);
1864                 struct ibv_wq *wq[1 << wq_n];
1865
1866                 for (i = 0; i != queues_n; ++i) {
1867                         struct mlx5_rxq_ctrl *rxq = mlx5_rxq_get(dev,
1868                                                                  queues[i]);
1869                         if (!rxq)
1870                                 goto error;
1871                         wq[i] = rxq->obj->wq;
1872                         ind_tbl->queues[i] = queues[i];
1873                 }
1874                 ind_tbl->queues_n = queues_n;
1875                 /* Finalise indirection table. */
1876                 k = i; /* Retain value of i for use in error case. */
1877                 for (j = 0; k != (unsigned int)(1 << wq_n); ++k, ++j)
1878                         wq[k] = wq[j];
1879                 ind_tbl->ind_table = mlx5_glue->create_rwq_ind_table
1880                         (priv->sh->ctx,
1881                          &(struct ibv_rwq_ind_table_init_attr){
1882                                 .log_ind_tbl_size = wq_n,
1883                                 .ind_tbl = wq,
1884                                 .comp_mask = 0,
1885                         });
1886                 if (!ind_tbl->ind_table) {
1887                         rte_errno = errno;
1888                         goto error;
1889                 }
1890         } else { /* ind_tbl->type == MLX5_IND_TBL_TYPE_DEVX */
1891                 struct mlx5_devx_rqt_attr *rqt_attr = NULL;
1892
1893                 rqt_attr = rte_calloc(__func__, 1, sizeof(*rqt_attr) +
1894                                       queues_n * sizeof(uint16_t), 0);
1895                 if (!rqt_attr) {
1896                         DRV_LOG(ERR, "port %u cannot allocate RQT resources",
1897                                 dev->data->port_id);
1898                         rte_errno = ENOMEM;
1899                         goto error;
1900                 }
1901                 rqt_attr->rqt_max_size = priv->config.ind_table_max_size;
1902                 rqt_attr->rqt_actual_size = queues_n;
1903                 for (i = 0; i != queues_n; ++i) {
1904                         struct mlx5_rxq_ctrl *rxq = mlx5_rxq_get(dev,
1905                                                                  queues[i]);
1906                         if (!rxq)
1907                                 goto error;
1908                         rqt_attr->rq_list[i] = rxq->obj->rq->id;
1909                         ind_tbl->queues[i] = queues[i];
1910                 }
1911                 ind_tbl->rqt = mlx5_devx_cmd_create_rqt(priv->sh->ctx,
1912                                                         rqt_attr);
1913                 rte_free(rqt_attr);
1914                 if (!ind_tbl->rqt) {
1915                         DRV_LOG(ERR, "port %u cannot create DevX RQT",
1916                                 dev->data->port_id);
1917                         rte_errno = errno;
1918                         goto error;
1919                 }
1920                 ind_tbl->queues_n = queues_n;
1921         }
1922         rte_atomic32_inc(&ind_tbl->refcnt);
1923         LIST_INSERT_HEAD(&priv->ind_tbls, ind_tbl, next);
1924         return ind_tbl;
1925 error:
1926         for (j = 0; j < i; j++)
1927                 mlx5_rxq_release(dev, ind_tbl->queues[j]);
1928         rte_free(ind_tbl);
1929         DEBUG("port %u cannot create indirection table", dev->data->port_id);
1930         return NULL;
1931 }
1932
1933 /**
1934  * Get an indirection table.
1935  *
1936  * @param dev
1937  *   Pointer to Ethernet device.
1938  * @param queues
1939  *   Queues entering in the indirection table.
1940  * @param queues_n
1941  *   Number of queues in the array.
1942  *
1943  * @return
1944  *   An indirection table if found.
1945  */
1946 static struct mlx5_ind_table_obj *
1947 mlx5_ind_table_obj_get(struct rte_eth_dev *dev, const uint16_t *queues,
1948                        uint32_t queues_n)
1949 {
1950         struct mlx5_priv *priv = dev->data->dev_private;
1951         struct mlx5_ind_table_obj *ind_tbl;
1952
1953         LIST_FOREACH(ind_tbl, &priv->ind_tbls, next) {
1954                 if ((ind_tbl->queues_n == queues_n) &&
1955                     (memcmp(ind_tbl->queues, queues,
1956                             ind_tbl->queues_n * sizeof(ind_tbl->queues[0]))
1957                      == 0))
1958                         break;
1959         }
1960         if (ind_tbl) {
1961                 unsigned int i;
1962
1963                 rte_atomic32_inc(&ind_tbl->refcnt);
1964                 for (i = 0; i != ind_tbl->queues_n; ++i)
1965                         mlx5_rxq_get(dev, ind_tbl->queues[i]);
1966         }
1967         return ind_tbl;
1968 }
1969
1970 /**
1971  * Release an indirection table.
1972  *
1973  * @param dev
1974  *   Pointer to Ethernet device.
1975  * @param ind_table
1976  *   Indirection table to release.
1977  *
1978  * @return
1979  *   1 while a reference on it exists, 0 when freed.
1980  */
1981 static int
1982 mlx5_ind_table_obj_release(struct rte_eth_dev *dev,
1983                            struct mlx5_ind_table_obj *ind_tbl)
1984 {
1985         unsigned int i;
1986
1987         if (rte_atomic32_dec_and_test(&ind_tbl->refcnt)) {
1988                 if (ind_tbl->type == MLX5_IND_TBL_TYPE_IBV)
1989                         claim_zero(mlx5_glue->destroy_rwq_ind_table
1990                                                         (ind_tbl->ind_table));
1991                 else if (ind_tbl->type == MLX5_IND_TBL_TYPE_DEVX)
1992                         claim_zero(mlx5_devx_cmd_destroy(ind_tbl->rqt));
1993         }
1994         for (i = 0; i != ind_tbl->queues_n; ++i)
1995                 claim_nonzero(mlx5_rxq_release(dev, ind_tbl->queues[i]));
1996         if (!rte_atomic32_read(&ind_tbl->refcnt)) {
1997                 LIST_REMOVE(ind_tbl, next);
1998                 rte_free(ind_tbl);
1999                 return 0;
2000         }
2001         return 1;
2002 }
2003
2004 /**
2005  * Verify the Rx Queue list is empty
2006  *
2007  * @param dev
2008  *   Pointer to Ethernet device.
2009  *
2010  * @return
2011  *   The number of object not released.
2012  */
2013 int
2014 mlx5_ind_table_obj_verify(struct rte_eth_dev *dev)
2015 {
2016         struct mlx5_priv *priv = dev->data->dev_private;
2017         struct mlx5_ind_table_obj *ind_tbl;
2018         int ret = 0;
2019
2020         LIST_FOREACH(ind_tbl, &priv->ind_tbls, next) {
2021                 DRV_LOG(DEBUG,
2022                         "port %u indirection table obj %p still referenced",
2023                         dev->data->port_id, (void *)ind_tbl);
2024                 ++ret;
2025         }
2026         return ret;
2027 }
2028
2029 /**
2030  * Create an Rx Hash queue.
2031  *
2032  * @param dev
2033  *   Pointer to Ethernet device.
2034  * @param rss_key
2035  *   RSS key for the Rx hash queue.
2036  * @param rss_key_len
2037  *   RSS key length.
2038  * @param hash_fields
2039  *   Verbs protocol hash field to make the RSS on.
2040  * @param queues
2041  *   Queues entering in hash queue. In case of empty hash_fields only the
2042  *   first queue index will be taken for the indirection table.
2043  * @param queues_n
2044  *   Number of queues.
2045  * @param tunnel
2046  *   Tunnel type.
2047  * @param lro
2048  *   Flow rule is relevant for LRO, i.e. contains IPv4/IPv6 and TCP.
2049  *
2050  * @return
2051  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2052  */
2053 struct mlx5_hrxq *
2054 mlx5_hrxq_new(struct rte_eth_dev *dev,
2055               const uint8_t *rss_key, uint32_t rss_key_len,
2056               uint64_t hash_fields,
2057               const uint16_t *queues, uint32_t queues_n,
2058               int tunnel __rte_unused, int lro)
2059 {
2060         struct mlx5_priv *priv = dev->data->dev_private;
2061         struct mlx5_hrxq *hrxq;
2062         struct ibv_qp *qp = NULL;
2063         struct mlx5_ind_table_obj *ind_tbl;
2064         int err;
2065         struct mlx5_devx_obj *tir = NULL;
2066
2067         queues_n = hash_fields ? queues_n : 1;
2068         ind_tbl = mlx5_ind_table_obj_get(dev, queues, queues_n);
2069         if (!ind_tbl) {
2070                 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[queues[0]];
2071                 struct mlx5_rxq_ctrl *rxq_ctrl =
2072                         container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
2073                 enum mlx5_ind_tbl_type type;
2074
2075                 type = rxq_ctrl->obj->type == MLX5_RXQ_OBJ_TYPE_IBV ?
2076                                 MLX5_IND_TBL_TYPE_IBV : MLX5_IND_TBL_TYPE_DEVX;
2077                 ind_tbl = mlx5_ind_table_obj_new(dev, queues, queues_n, type);
2078         }
2079         if (!ind_tbl) {
2080                 rte_errno = ENOMEM;
2081                 return NULL;
2082         }
2083         if (ind_tbl->type == MLX5_IND_TBL_TYPE_IBV) {
2084 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
2085                 struct mlx5dv_qp_init_attr qp_init_attr;
2086
2087                 memset(&qp_init_attr, 0, sizeof(qp_init_attr));
2088                 if (tunnel) {
2089                         qp_init_attr.comp_mask =
2090                                 MLX5DV_QP_INIT_ATTR_MASK_QP_CREATE_FLAGS;
2091                         qp_init_attr.create_flags =
2092                                 MLX5DV_QP_CREATE_TUNNEL_OFFLOADS;
2093                 }
2094 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2095                 if (dev->data->dev_conf.lpbk_mode) {
2096                         /*
2097                          * Allow packet sent from NIC loop back
2098                          * w/o source MAC check.
2099                          */
2100                         qp_init_attr.comp_mask |=
2101                                 MLX5DV_QP_INIT_ATTR_MASK_QP_CREATE_FLAGS;
2102                         qp_init_attr.create_flags |=
2103                                 MLX5DV_QP_CREATE_TIR_ALLOW_SELF_LOOPBACK_UC;
2104                 }
2105 #endif
2106                 qp = mlx5_glue->dv_create_qp
2107                         (priv->sh->ctx,
2108                          &(struct ibv_qp_init_attr_ex){
2109                                 .qp_type = IBV_QPT_RAW_PACKET,
2110                                 .comp_mask =
2111                                         IBV_QP_INIT_ATTR_PD |
2112                                         IBV_QP_INIT_ATTR_IND_TABLE |
2113                                         IBV_QP_INIT_ATTR_RX_HASH,
2114                                 .rx_hash_conf = (struct ibv_rx_hash_conf){
2115                                         .rx_hash_function =
2116                                                 IBV_RX_HASH_FUNC_TOEPLITZ,
2117                                         .rx_hash_key_len = rss_key_len,
2118                                         .rx_hash_key =
2119                                                 (void *)(uintptr_t)rss_key,
2120                                         .rx_hash_fields_mask = hash_fields,
2121                                 },
2122                                 .rwq_ind_tbl = ind_tbl->ind_table,
2123                                 .pd = priv->sh->pd,
2124                           },
2125                           &qp_init_attr);
2126 #else
2127                 qp = mlx5_glue->create_qp_ex
2128                         (priv->sh->ctx,
2129                          &(struct ibv_qp_init_attr_ex){
2130                                 .qp_type = IBV_QPT_RAW_PACKET,
2131                                 .comp_mask =
2132                                         IBV_QP_INIT_ATTR_PD |
2133                                         IBV_QP_INIT_ATTR_IND_TABLE |
2134                                         IBV_QP_INIT_ATTR_RX_HASH,
2135                                 .rx_hash_conf = (struct ibv_rx_hash_conf){
2136                                         .rx_hash_function =
2137                                                 IBV_RX_HASH_FUNC_TOEPLITZ,
2138                                         .rx_hash_key_len = rss_key_len,
2139                                         .rx_hash_key =
2140                                                 (void *)(uintptr_t)rss_key,
2141                                         .rx_hash_fields_mask = hash_fields,
2142                                 },
2143                                 .rwq_ind_tbl = ind_tbl->ind_table,
2144                                 .pd = priv->sh->pd,
2145                          });
2146 #endif
2147                 if (!qp) {
2148                         rte_errno = errno;
2149                         goto error;
2150                 }
2151         } else { /* ind_tbl->type == MLX5_IND_TBL_TYPE_DEVX */
2152                 struct mlx5_devx_tir_attr tir_attr;
2153
2154                 memset(&tir_attr, 0, sizeof(tir_attr));
2155                 tir_attr.disp_type = MLX5_TIRC_DISP_TYPE_INDIRECT;
2156                 tir_attr.rx_hash_fn = MLX5_RX_HASH_FN_TOEPLITZ;
2157                 memcpy(&tir_attr.rx_hash_field_selector_outer, &hash_fields,
2158                        sizeof(uint64_t));
2159                 tir_attr.transport_domain = priv->sh->tdn;
2160                 memcpy(tir_attr.rx_hash_toeplitz_key, rss_key, rss_key_len);
2161                 tir_attr.indirect_table = ind_tbl->rqt->id;
2162                 if (dev->data->dev_conf.lpbk_mode)
2163                         tir_attr.self_lb_block =
2164                                         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
2165                 if (lro) {
2166                         tir_attr.lro_timeout_period_usecs =
2167                                         priv->config.lro.timeout;
2168                         tir_attr.lro_max_msg_sz = 0xff;
2169                         tir_attr.lro_enable_mask = lro;
2170                 }
2171                 tir = mlx5_devx_cmd_create_tir(priv->sh->ctx, &tir_attr);
2172                 if (!tir) {
2173                         DRV_LOG(ERR, "port %u cannot create DevX TIR",
2174                                 dev->data->port_id);
2175                         rte_errno = errno;
2176                         goto error;
2177                 }
2178         }
2179         hrxq = rte_calloc(__func__, 1, sizeof(*hrxq) + rss_key_len, 0);
2180         if (!hrxq)
2181                 goto error;
2182         hrxq->ind_table = ind_tbl;
2183         if (ind_tbl->type == MLX5_IND_TBL_TYPE_IBV) {
2184                 hrxq->qp = qp;
2185 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2186                 hrxq->action =
2187                         mlx5_glue->dv_create_flow_action_dest_ibv_qp(hrxq->qp);
2188                 if (!hrxq->action) {
2189                         rte_errno = errno;
2190                         goto error;
2191                 }
2192 #endif
2193         } else { /* ind_tbl->type == MLX5_IND_TBL_TYPE_DEVX */
2194                 hrxq->tir = tir;
2195 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2196                 hrxq->action = mlx5_glue->dv_create_flow_action_dest_devx_tir
2197                                                         (hrxq->tir->obj);
2198                 if (!hrxq->action) {
2199                         rte_errno = errno;
2200                         goto error;
2201                 }
2202 #endif
2203         }
2204         hrxq->rss_key_len = rss_key_len;
2205         hrxq->hash_fields = hash_fields;
2206         memcpy(hrxq->rss_key, rss_key, rss_key_len);
2207         rte_atomic32_inc(&hrxq->refcnt);
2208         LIST_INSERT_HEAD(&priv->hrxqs, hrxq, next);
2209         return hrxq;
2210 error:
2211         err = rte_errno; /* Save rte_errno before cleanup. */
2212         mlx5_ind_table_obj_release(dev, ind_tbl);
2213         if (qp)
2214                 claim_zero(mlx5_glue->destroy_qp(qp));
2215         else if (tir)
2216                 claim_zero(mlx5_devx_cmd_destroy(tir));
2217         rte_errno = err; /* Restore rte_errno. */
2218         return NULL;
2219 }
2220
2221 /**
2222  * Get an Rx Hash queue.
2223  *
2224  * @param dev
2225  *   Pointer to Ethernet device.
2226  * @param rss_conf
2227  *   RSS configuration for the Rx hash queue.
2228  * @param queues
2229  *   Queues entering in hash queue. In case of empty hash_fields only the
2230  *   first queue index will be taken for the indirection table.
2231  * @param queues_n
2232  *   Number of queues.
2233  *
2234  * @return
2235  *   An hash Rx queue on success.
2236  */
2237 struct mlx5_hrxq *
2238 mlx5_hrxq_get(struct rte_eth_dev *dev,
2239               const uint8_t *rss_key, uint32_t rss_key_len,
2240               uint64_t hash_fields,
2241               const uint16_t *queues, uint32_t queues_n)
2242 {
2243         struct mlx5_priv *priv = dev->data->dev_private;
2244         struct mlx5_hrxq *hrxq;
2245
2246         queues_n = hash_fields ? queues_n : 1;
2247         LIST_FOREACH(hrxq, &priv->hrxqs, next) {
2248                 struct mlx5_ind_table_obj *ind_tbl;
2249
2250                 if (hrxq->rss_key_len != rss_key_len)
2251                         continue;
2252                 if (memcmp(hrxq->rss_key, rss_key, rss_key_len))
2253                         continue;
2254                 if (hrxq->hash_fields != hash_fields)
2255                         continue;
2256                 ind_tbl = mlx5_ind_table_obj_get(dev, queues, queues_n);
2257                 if (!ind_tbl)
2258                         continue;
2259                 if (ind_tbl != hrxq->ind_table) {
2260                         mlx5_ind_table_obj_release(dev, ind_tbl);
2261                         continue;
2262                 }
2263                 rte_atomic32_inc(&hrxq->refcnt);
2264                 return hrxq;
2265         }
2266         return NULL;
2267 }
2268
2269 /**
2270  * Release the hash Rx queue.
2271  *
2272  * @param dev
2273  *   Pointer to Ethernet device.
2274  * @param hrxq
2275  *   Pointer to Hash Rx queue to release.
2276  *
2277  * @return
2278  *   1 while a reference on it exists, 0 when freed.
2279  */
2280 int
2281 mlx5_hrxq_release(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq)
2282 {
2283         if (rte_atomic32_dec_and_test(&hrxq->refcnt)) {
2284 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2285                 mlx5_glue->destroy_flow_action(hrxq->action);
2286 #endif
2287                 if (hrxq->ind_table->type == MLX5_IND_TBL_TYPE_IBV)
2288                         claim_zero(mlx5_glue->destroy_qp(hrxq->qp));
2289                 else /* hrxq->ind_table->type == MLX5_IND_TBL_TYPE_DEVX */
2290                         claim_zero(mlx5_devx_cmd_destroy(hrxq->tir));
2291                 mlx5_ind_table_obj_release(dev, hrxq->ind_table);
2292                 LIST_REMOVE(hrxq, next);
2293                 rte_free(hrxq);
2294                 return 0;
2295         }
2296         claim_nonzero(mlx5_ind_table_obj_release(dev, hrxq->ind_table));
2297         return 1;
2298 }
2299
2300 /**
2301  * Verify the Rx Queue list is empty
2302  *
2303  * @param dev
2304  *   Pointer to Ethernet device.
2305  *
2306  * @return
2307  *   The number of object not released.
2308  */
2309 int
2310 mlx5_hrxq_verify(struct rte_eth_dev *dev)
2311 {
2312         struct mlx5_priv *priv = dev->data->dev_private;
2313         struct mlx5_hrxq *hrxq;
2314         int ret = 0;
2315
2316         LIST_FOREACH(hrxq, &priv->hrxqs, next) {
2317                 DRV_LOG(DEBUG,
2318                         "port %u hash Rx queue %p still referenced",
2319                         dev->data->port_id, (void *)hrxq);
2320                 ++ret;
2321         }
2322         return ret;
2323 }
2324
2325 /**
2326  * Create a drop Rx queue Verbs/DevX object.
2327  *
2328  * @param dev
2329  *   Pointer to Ethernet device.
2330  *
2331  * @return
2332  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2333  */
2334 static struct mlx5_rxq_obj *
2335 mlx5_rxq_obj_drop_new(struct rte_eth_dev *dev)
2336 {
2337         struct mlx5_priv *priv = dev->data->dev_private;
2338         struct ibv_context *ctx = priv->sh->ctx;
2339         struct ibv_cq *cq;
2340         struct ibv_wq *wq = NULL;
2341         struct mlx5_rxq_obj *rxq;
2342
2343         if (priv->drop_queue.rxq)
2344                 return priv->drop_queue.rxq;
2345         cq = mlx5_glue->create_cq(ctx, 1, NULL, NULL, 0);
2346         if (!cq) {
2347                 DEBUG("port %u cannot allocate CQ for drop queue",
2348                       dev->data->port_id);
2349                 rte_errno = errno;
2350                 goto error;
2351         }
2352         wq = mlx5_glue->create_wq(ctx,
2353                  &(struct ibv_wq_init_attr){
2354                         .wq_type = IBV_WQT_RQ,
2355                         .max_wr = 1,
2356                         .max_sge = 1,
2357                         .pd = priv->sh->pd,
2358                         .cq = cq,
2359                  });
2360         if (!wq) {
2361                 DEBUG("port %u cannot allocate WQ for drop queue",
2362                       dev->data->port_id);
2363                 rte_errno = errno;
2364                 goto error;
2365         }
2366         rxq = rte_calloc(__func__, 1, sizeof(*rxq), 0);
2367         if (!rxq) {
2368                 DEBUG("port %u cannot allocate drop Rx queue memory",
2369                       dev->data->port_id);
2370                 rte_errno = ENOMEM;
2371                 goto error;
2372         }
2373         rxq->cq = cq;
2374         rxq->wq = wq;
2375         priv->drop_queue.rxq = rxq;
2376         return rxq;
2377 error:
2378         if (wq)
2379                 claim_zero(mlx5_glue->destroy_wq(wq));
2380         if (cq)
2381                 claim_zero(mlx5_glue->destroy_cq(cq));
2382         return NULL;
2383 }
2384
2385 /**
2386  * Release a drop Rx queue Verbs/DevX object.
2387  *
2388  * @param dev
2389  *   Pointer to Ethernet device.
2390  *
2391  * @return
2392  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2393  */
2394 static void
2395 mlx5_rxq_obj_drop_release(struct rte_eth_dev *dev)
2396 {
2397         struct mlx5_priv *priv = dev->data->dev_private;
2398         struct mlx5_rxq_obj *rxq = priv->drop_queue.rxq;
2399
2400         if (rxq->wq)
2401                 claim_zero(mlx5_glue->destroy_wq(rxq->wq));
2402         if (rxq->cq)
2403                 claim_zero(mlx5_glue->destroy_cq(rxq->cq));
2404         rte_free(rxq);
2405         priv->drop_queue.rxq = NULL;
2406 }
2407
2408 /**
2409  * Create a drop indirection table.
2410  *
2411  * @param dev
2412  *   Pointer to Ethernet device.
2413  *
2414  * @return
2415  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2416  */
2417 static struct mlx5_ind_table_obj *
2418 mlx5_ind_table_obj_drop_new(struct rte_eth_dev *dev)
2419 {
2420         struct mlx5_priv *priv = dev->data->dev_private;
2421         struct mlx5_ind_table_obj *ind_tbl;
2422         struct mlx5_rxq_obj *rxq;
2423         struct mlx5_ind_table_obj tmpl;
2424
2425         rxq = mlx5_rxq_obj_drop_new(dev);
2426         if (!rxq)
2427                 return NULL;
2428         tmpl.ind_table = mlx5_glue->create_rwq_ind_table
2429                 (priv->sh->ctx,
2430                  &(struct ibv_rwq_ind_table_init_attr){
2431                         .log_ind_tbl_size = 0,
2432                         .ind_tbl = &rxq->wq,
2433                         .comp_mask = 0,
2434                  });
2435         if (!tmpl.ind_table) {
2436                 DEBUG("port %u cannot allocate indirection table for drop"
2437                       " queue",
2438                       dev->data->port_id);
2439                 rte_errno = errno;
2440                 goto error;
2441         }
2442         ind_tbl = rte_calloc(__func__, 1, sizeof(*ind_tbl), 0);
2443         if (!ind_tbl) {
2444                 rte_errno = ENOMEM;
2445                 goto error;
2446         }
2447         ind_tbl->ind_table = tmpl.ind_table;
2448         return ind_tbl;
2449 error:
2450         mlx5_rxq_obj_drop_release(dev);
2451         return NULL;
2452 }
2453
2454 /**
2455  * Release a drop indirection table.
2456  *
2457  * @param dev
2458  *   Pointer to Ethernet device.
2459  */
2460 static void
2461 mlx5_ind_table_obj_drop_release(struct rte_eth_dev *dev)
2462 {
2463         struct mlx5_priv *priv = dev->data->dev_private;
2464         struct mlx5_ind_table_obj *ind_tbl = priv->drop_queue.hrxq->ind_table;
2465
2466         claim_zero(mlx5_glue->destroy_rwq_ind_table(ind_tbl->ind_table));
2467         mlx5_rxq_obj_drop_release(dev);
2468         rte_free(ind_tbl);
2469         priv->drop_queue.hrxq->ind_table = NULL;
2470 }
2471
2472 /**
2473  * Create a drop Rx Hash queue.
2474  *
2475  * @param dev
2476  *   Pointer to Ethernet device.
2477  *
2478  * @return
2479  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2480  */
2481 struct mlx5_hrxq *
2482 mlx5_hrxq_drop_new(struct rte_eth_dev *dev)
2483 {
2484         struct mlx5_priv *priv = dev->data->dev_private;
2485         struct mlx5_ind_table_obj *ind_tbl;
2486         struct ibv_qp *qp;
2487         struct mlx5_hrxq *hrxq;
2488
2489         if (priv->drop_queue.hrxq) {
2490                 rte_atomic32_inc(&priv->drop_queue.hrxq->refcnt);
2491                 return priv->drop_queue.hrxq;
2492         }
2493         ind_tbl = mlx5_ind_table_obj_drop_new(dev);
2494         if (!ind_tbl)
2495                 return NULL;
2496         qp = mlx5_glue->create_qp_ex(priv->sh->ctx,
2497                  &(struct ibv_qp_init_attr_ex){
2498                         .qp_type = IBV_QPT_RAW_PACKET,
2499                         .comp_mask =
2500                                 IBV_QP_INIT_ATTR_PD |
2501                                 IBV_QP_INIT_ATTR_IND_TABLE |
2502                                 IBV_QP_INIT_ATTR_RX_HASH,
2503                         .rx_hash_conf = (struct ibv_rx_hash_conf){
2504                                 .rx_hash_function =
2505                                         IBV_RX_HASH_FUNC_TOEPLITZ,
2506                                 .rx_hash_key_len = MLX5_RSS_HASH_KEY_LEN,
2507                                 .rx_hash_key = rss_hash_default_key,
2508                                 .rx_hash_fields_mask = 0,
2509                                 },
2510                         .rwq_ind_tbl = ind_tbl->ind_table,
2511                         .pd = priv->sh->pd
2512                  });
2513         if (!qp) {
2514                 DEBUG("port %u cannot allocate QP for drop queue",
2515                       dev->data->port_id);
2516                 rte_errno = errno;
2517                 goto error;
2518         }
2519         hrxq = rte_calloc(__func__, 1, sizeof(*hrxq), 0);
2520         if (!hrxq) {
2521                 DRV_LOG(WARNING,
2522                         "port %u cannot allocate memory for drop queue",
2523                         dev->data->port_id);
2524                 rte_errno = ENOMEM;
2525                 goto error;
2526         }
2527         hrxq->ind_table = ind_tbl;
2528         hrxq->qp = qp;
2529 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2530         hrxq->action = mlx5_glue->dv_create_flow_action_dest_ibv_qp(hrxq->qp);
2531         if (!hrxq->action) {
2532                 rte_errno = errno;
2533                 goto error;
2534         }
2535 #endif
2536         priv->drop_queue.hrxq = hrxq;
2537         rte_atomic32_set(&hrxq->refcnt, 1);
2538         return hrxq;
2539 error:
2540         if (ind_tbl)
2541                 mlx5_ind_table_obj_drop_release(dev);
2542         return NULL;
2543 }
2544
2545 /**
2546  * Release a drop hash Rx queue.
2547  *
2548  * @param dev
2549  *   Pointer to Ethernet device.
2550  */
2551 void
2552 mlx5_hrxq_drop_release(struct rte_eth_dev *dev)
2553 {
2554         struct mlx5_priv *priv = dev->data->dev_private;
2555         struct mlx5_hrxq *hrxq = priv->drop_queue.hrxq;
2556
2557         if (rte_atomic32_dec_and_test(&hrxq->refcnt)) {
2558 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2559                 mlx5_glue->destroy_flow_action(hrxq->action);
2560 #endif
2561                 claim_zero(mlx5_glue->destroy_qp(hrxq->qp));
2562                 mlx5_ind_table_obj_drop_release(dev);
2563                 rte_free(hrxq);
2564                 priv->drop_queue.hrxq = NULL;
2565         }
2566 }