drivers/net/mlx5/mlx5_rxq.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <stddef.h>
   7 #include <errno.h>
   8 #include <string.h>
   9 #include <stdint.h>
  10 #include <fcntl.h>
  11 #include <sys/queue.h>
  12
  13 #include <rte_mbuf.h>
  14 #include <rte_malloc.h>
  15 #include <rte_ethdev_driver.h>
  16 #include <rte_common.h>
  17 #include <rte_interrupts.h>
  18 #include <rte_debug.h>
  19 #include <rte_io.h>
  20 #include <rte_eal_paging.h>
  21
  22 #include <mlx5_glue.h>
  23 #include <mlx5_devx_cmds.h>
  24 #include <mlx5_malloc.h>
  25
  26 #include "mlx5_defs.h"
  27 #include "mlx5.h"
  28 #include "mlx5_common_os.h"
  29 #include "mlx5_rxtx.h"
  30 #include "mlx5_utils.h"
  31 #include "mlx5_autoconf.h"
  32 #include "mlx5_flow.h"
  33
  34
  35 /* Default RSS hash key also used for ConnectX-3. */
  36 uint8_t rss_hash_default_key[] = {
  37         0x2c, 0xc6, 0x81, 0xd1,
  38         0x5b, 0xdb, 0xf4, 0xf7,
  39         0xfc, 0xa2, 0x83, 0x19,
  40         0xdb, 0x1a, 0x3e, 0x94,
  41         0x6b, 0x9e, 0x38, 0xd9,
  42         0x2c, 0x9c, 0x03, 0xd1,
  43         0xad, 0x99, 0x44, 0xa7,
  44         0xd9, 0x56, 0x3d, 0x59,
  45         0x06, 0x3c, 0x25, 0xf3,
  46         0xfc, 0x1f, 0xdc, 0x2a,
  47 };
  48
  49 /* Length of the default RSS hash key. */
  50 static_assert(MLX5_RSS_HASH_KEY_LEN ==
  51               (unsigned int)sizeof(rss_hash_default_key),
  52               "wrong RSS default key size.");
  53
  54 /**
  55  * Check whether Multi-Packet RQ can be enabled for the device.
  56  *
  57  * @param dev
  58  *   Pointer to Ethernet device.
  59  *
  60  * @return
  61  *   1 if supported, negative errno value if not.
  62  */
  63 inline int
  64 mlx5_check_mprq_support(struct rte_eth_dev *dev)
  65 {
  66         struct mlx5_priv *priv = dev->data->dev_private;
  67
  68         if (priv->config.mprq.enabled &&
  69             priv->rxqs_n >= priv->config.mprq.min_rxqs_num)
  70                 return 1;
  71         return -ENOTSUP;
  72 }
  73
  74 /**
  75  * Check whether Multi-Packet RQ is enabled for the Rx queue.
  76  *
  77  *  @param rxq
  78  *     Pointer to receive queue structure.
  79  *
  80  * @return
  81  *   0 if disabled, otherwise enabled.
  82  */
  83 inline int
  84 mlx5_rxq_mprq_enabled(struct mlx5_rxq_data *rxq)
  85 {
  86         return rxq->strd_num_n > 0;
  87 }
  88
  89 /**
  90  * Check whether Multi-Packet RQ is enabled for the device.
  91  *
  92  * @param dev
  93  *   Pointer to Ethernet device.
  94  *
  95  * @return
  96  *   0 if disabled, otherwise enabled.
  97  */
  98 inline int
  99 mlx5_mprq_enabled(struct rte_eth_dev *dev)
 100 {
 101         struct mlx5_priv *priv = dev->data->dev_private;
 102         uint32_t i;
 103         uint16_t n = 0;
 104         uint16_t n_ibv = 0;
 105
 106         if (mlx5_check_mprq_support(dev) < 0)
 107                 return 0;
 108         /* All the configured queues should be enabled. */
 109         for (i = 0; i < priv->rxqs_n; ++i) {
 110                 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
 111                 struct mlx5_rxq_ctrl *rxq_ctrl = container_of
 112                         (rxq, struct mlx5_rxq_ctrl, rxq);
 113
 114                 if (rxq == NULL || rxq_ctrl->type != MLX5_RXQ_TYPE_STANDARD)
 115                         continue;
 116                 n_ibv++;
 117                 if (mlx5_rxq_mprq_enabled(rxq))
 118                         ++n;
 119         }
 120         /* Multi-Packet RQ can't be partially configured. */
 121         MLX5_ASSERT(n == 0 || n == n_ibv);
 122         return n == n_ibv;
 123 }
 124
 125 /**
 126  * Calculate the number of CQEs in CQ for the Rx queue.
 127  *
 128  *  @param rxq_data
 129  *     Pointer to receive queue structure.
 130  *
 131  * @return
 132  *   Number of CQEs in CQ.
 133  */
 134 unsigned int
 135 mlx5_rxq_cqe_num(struct mlx5_rxq_data *rxq_data)
 136 {
 137         unsigned int cqe_n;
 138         unsigned int wqe_n = 1 << rxq_data->elts_n;
 139
 140         if (mlx5_rxq_mprq_enabled(rxq_data))
 141                 cqe_n = wqe_n * (1 << rxq_data->strd_num_n) - 1;
 142         else
 143                 cqe_n = wqe_n - 1;
 144         return cqe_n;
 145 }
 146
 147 /**
 148  * Allocate RX queue elements for Multi-Packet RQ.
 149  *
 150  * @param rxq_ctrl
 151  *   Pointer to RX queue structure.
 152  *
 153  * @return
 154  *   0 on success, a negative errno value otherwise and rte_errno is set.
 155  */
 156 static int
 157 rxq_alloc_elts_mprq(struct mlx5_rxq_ctrl *rxq_ctrl)
 158 {
 159         struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
 160         unsigned int wqe_n = 1 << rxq->elts_n;
 161         unsigned int i;
 162         int err;
 163
 164         /* Iterate on segments. */
 165         for (i = 0; i <= wqe_n; ++i) {
 166                 struct mlx5_mprq_buf *buf;
 167
 168                 if (rte_mempool_get(rxq->mprq_mp, (void **)&buf) < 0) {
 169                         DRV_LOG(ERR, "port %u empty mbuf pool", rxq->port_id);
 170                         rte_errno = ENOMEM;
 171                         goto error;
 172                 }
 173                 if (i < wqe_n)
 174                         (*rxq->mprq_bufs)[i] = buf;
 175                 else
 176                         rxq->mprq_repl = buf;
 177         }
 178         DRV_LOG(DEBUG,
 179                 "port %u Rx queue %u allocated and configured %u segments",
 180                 rxq->port_id, rxq->idx, wqe_n);
 181         return 0;
 182 error:
 183         err = rte_errno; /* Save rte_errno before cleanup. */
 184         wqe_n = i;
 185         for (i = 0; (i != wqe_n); ++i) {
 186                 if ((*rxq->mprq_bufs)[i] != NULL)
 187                         rte_mempool_put(rxq->mprq_mp,
 188                                         (*rxq->mprq_bufs)[i]);
 189                 (*rxq->mprq_bufs)[i] = NULL;
 190         }
 191         DRV_LOG(DEBUG, "port %u Rx queue %u failed, freed everything",
 192                 rxq->port_id, rxq->idx);
 193         rte_errno = err; /* Restore rte_errno. */
 194         return -rte_errno;
 195 }
 196
 197 /**
 198  * Allocate RX queue elements for Single-Packet RQ.
 199  *
 200  * @param rxq_ctrl
 201  *   Pointer to RX queue structure.
 202  *
 203  * @return
 204  *   0 on success, errno value on failure.
 205  */
 206 static int
 207 rxq_alloc_elts_sprq(struct mlx5_rxq_ctrl *rxq_ctrl)
 208 {
 209         const unsigned int sges_n = 1 << rxq_ctrl->rxq.sges_n;
 210         unsigned int elts_n = 1 << rxq_ctrl->rxq.elts_n;
 211         unsigned int i;
 212         int err;
 213
 214         /* Iterate on segments. */
 215         for (i = 0; (i != elts_n); ++i) {
 216                 struct rte_mbuf *buf;
 217
 218                 buf = rte_pktmbuf_alloc(rxq_ctrl->rxq.mp);
 219                 if (buf == NULL) {
 220                         DRV_LOG(ERR, "port %u empty mbuf pool",
 221                                 PORT_ID(rxq_ctrl->priv));
 222                         rte_errno = ENOMEM;
 223                         goto error;
 224                 }
 225                 /* Headroom is reserved by rte_pktmbuf_alloc(). */
 226                 MLX5_ASSERT(DATA_OFF(buf) == RTE_PKTMBUF_HEADROOM);
 227                 /* Buffer is supposed to be empty. */
 228                 MLX5_ASSERT(rte_pktmbuf_data_len(buf) == 0);
 229                 MLX5_ASSERT(rte_pktmbuf_pkt_len(buf) == 0);
 230                 MLX5_ASSERT(!buf->next);
 231                 /* Only the first segment keeps headroom. */
 232                 if (i % sges_n)
 233                         SET_DATA_OFF(buf, 0);
 234                 PORT(buf) = rxq_ctrl->rxq.port_id;
 235                 DATA_LEN(buf) = rte_pktmbuf_tailroom(buf);
 236                 PKT_LEN(buf) = DATA_LEN(buf);
 237                 NB_SEGS(buf) = 1;
 238                 (*rxq_ctrl->rxq.elts)[i] = buf;
 239         }
 240         /* If Rx vector is activated. */
 241         if (mlx5_rxq_check_vec_support(&rxq_ctrl->rxq) > 0) {
 242                 struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
 243                 struct rte_mbuf *mbuf_init = &rxq->fake_mbuf;
 244                 struct rte_pktmbuf_pool_private *priv =
 245                         (struct rte_pktmbuf_pool_private *)
 246                                 rte_mempool_get_priv(rxq_ctrl->rxq.mp);
 247                 int j;
 248
 249                 /* Initialize default rearm_data for vPMD. */
 250                 mbuf_init->data_off = RTE_PKTMBUF_HEADROOM;
 251                 rte_mbuf_refcnt_set(mbuf_init, 1);
 252                 mbuf_init->nb_segs = 1;
 253                 mbuf_init->port = rxq->port_id;
 254                 if (priv->flags & RTE_PKTMBUF_POOL_F_PINNED_EXT_BUF)
 255                         mbuf_init->ol_flags = EXT_ATTACHED_MBUF;
 256                 /*
 257                  * prevent compiler reordering:
 258                  * rearm_data covers previous fields.
 259                  */
 260                 rte_compiler_barrier();
 261                 rxq->mbuf_initializer =
 262                         *(rte_xmm_t *)&mbuf_init->rearm_data;
 263                 /* Padding with a fake mbuf for vectorized Rx. */
 264                 for (j = 0; j < MLX5_VPMD_DESCS_PER_LOOP; ++j)
 265                         (*rxq->elts)[elts_n + j] = &rxq->fake_mbuf;
 266         }
 267         DRV_LOG(DEBUG,
 268                 "port %u Rx queue %u allocated and configured %u segments"
 269                 " (max %u packets)",
 270                 PORT_ID(rxq_ctrl->priv), rxq_ctrl->rxq.idx, elts_n,
 271                 elts_n / (1 << rxq_ctrl->rxq.sges_n));
 272         return 0;
 273 error:
 274         err = rte_errno; /* Save rte_errno before cleanup. */
 275         elts_n = i;
 276         for (i = 0; (i != elts_n); ++i) {
 277                 if ((*rxq_ctrl->rxq.elts)[i] != NULL)
 278                         rte_pktmbuf_free_seg((*rxq_ctrl->rxq.elts)[i]);
 279                 (*rxq_ctrl->rxq.elts)[i] = NULL;
 280         }
 281         DRV_LOG(DEBUG, "port %u Rx queue %u failed, freed everything",
 282                 PORT_ID(rxq_ctrl->priv), rxq_ctrl->rxq.idx);
 283         rte_errno = err; /* Restore rte_errno. */
 284         return -rte_errno;
 285 }
 286
 287 /**
 288  * Allocate RX queue elements.
 289  *
 290  * @param rxq_ctrl
 291  *   Pointer to RX queue structure.
 292  *
 293  * @return
 294  *   0 on success, errno value on failure.
 295  */
 296 int
 297 rxq_alloc_elts(struct mlx5_rxq_ctrl *rxq_ctrl)
 298 {
 299         return mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq) ?
 300                rxq_alloc_elts_mprq(rxq_ctrl) : rxq_alloc_elts_sprq(rxq_ctrl);
 301 }
 302
 303 /**
 304  * Free RX queue elements for Multi-Packet RQ.
 305  *
 306  * @param rxq_ctrl
 307  *   Pointer to RX queue structure.
 308  */
 309 static void
 310 rxq_free_elts_mprq(struct mlx5_rxq_ctrl *rxq_ctrl)
 311 {
 312         struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
 313         uint16_t i;
 314
 315         DRV_LOG(DEBUG, "port %u Multi-Packet Rx queue %u freeing WRs",
 316                 rxq->port_id, rxq->idx);
 317         if (rxq->mprq_bufs == NULL)
 318                 return;
 319         MLX5_ASSERT(mlx5_rxq_check_vec_support(rxq) < 0);
 320         for (i = 0; (i != (1u << rxq->elts_n)); ++i) {
 321                 if ((*rxq->mprq_bufs)[i] != NULL)
 322                         mlx5_mprq_buf_free((*rxq->mprq_bufs)[i]);
 323                 (*rxq->mprq_bufs)[i] = NULL;
 324         }
 325         if (rxq->mprq_repl != NULL) {
 326                 mlx5_mprq_buf_free(rxq->mprq_repl);
 327                 rxq->mprq_repl = NULL;
 328         }
 329 }
 330
 331 /**
 332  * Free RX queue elements for Single-Packet RQ.
 333  *
 334  * @param rxq_ctrl
 335  *   Pointer to RX queue structure.
 336  */
 337 static void
 338 rxq_free_elts_sprq(struct mlx5_rxq_ctrl *rxq_ctrl)
 339 {
 340         struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
 341         const uint16_t q_n = (1 << rxq->elts_n);
 342         const uint16_t q_mask = q_n - 1;
 343         uint16_t used = q_n - (rxq->rq_ci - rxq->rq_pi);
 344         uint16_t i;
 345
 346         DRV_LOG(DEBUG, "port %u Rx queue %u freeing WRs",
 347                 PORT_ID(rxq_ctrl->priv), rxq->idx);
 348         if (rxq->elts == NULL)
 349                 return;
 350         /**
 351          * Some mbuf in the Ring belongs to the application.  They cannot be
 352          * freed.
 353          */
 354         if (mlx5_rxq_check_vec_support(rxq) > 0) {
 355                 for (i = 0; i < used; ++i)
 356                         (*rxq->elts)[(rxq->rq_ci + i) & q_mask] = NULL;
 357                 rxq->rq_pi = rxq->rq_ci;
 358         }
 359         for (i = 0; (i != (1u << rxq->elts_n)); ++i) {
 360                 if ((*rxq->elts)[i] != NULL)
 361                         rte_pktmbuf_free_seg((*rxq->elts)[i]);
 362                 (*rxq->elts)[i] = NULL;
 363         }
 364 }
 365
 366 /**
 367  * Free RX queue elements.
 368  *
 369  * @param rxq_ctrl
 370  *   Pointer to RX queue structure.
 371  */
 372 static void
 373 rxq_free_elts(struct mlx5_rxq_ctrl *rxq_ctrl)
 374 {
 375         if (mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq))
 376                 rxq_free_elts_mprq(rxq_ctrl);
 377         else
 378                 rxq_free_elts_sprq(rxq_ctrl);
 379 }
 380
 381 /**
 382  * Returns the per-queue supported offloads.
 383  *
 384  * @param dev
 385  *   Pointer to Ethernet device.
 386  *
 387  * @return
 388  *   Supported Rx offloads.
 389  */
 390 uint64_t
 391 mlx5_get_rx_queue_offloads(struct rte_eth_dev *dev)
 392 {
 393         struct mlx5_priv *priv = dev->data->dev_private;
 394         struct mlx5_dev_config *config = &priv->config;
 395         uint64_t offloads = (DEV_RX_OFFLOAD_SCATTER |
 396                              DEV_RX_OFFLOAD_TIMESTAMP |
 397                              DEV_RX_OFFLOAD_JUMBO_FRAME |
 398                              DEV_RX_OFFLOAD_RSS_HASH);
 399
 400         if (config->hw_fcs_strip)
 401                 offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
 402
 403         if (config->hw_csum)
 404                 offloads |= (DEV_RX_OFFLOAD_IPV4_CKSUM |
 405                              DEV_RX_OFFLOAD_UDP_CKSUM |
 406                              DEV_RX_OFFLOAD_TCP_CKSUM);
 407         if (config->hw_vlan_strip)
 408                 offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
 409         if (MLX5_LRO_SUPPORTED(dev))
 410                 offloads |= DEV_RX_OFFLOAD_TCP_LRO;
 411         return offloads;
 412 }
 413
 414
 415 /**
 416  * Returns the per-port supported offloads.
 417  *
 418  * @return
 419  *   Supported Rx offloads.
 420  */
 421 uint64_t
 422 mlx5_get_rx_port_offloads(void)
 423 {
 424         uint64_t offloads = DEV_RX_OFFLOAD_VLAN_FILTER;
 425
 426         return offloads;
 427 }
 428
 429 /**
 430  * Verify if the queue can be released.
 431  *
 432  * @param dev
 433  *   Pointer to Ethernet device.
 434  * @param idx
 435  *   RX queue index.
 436  *
 437  * @return
 438  *   1 if the queue can be released
 439  *   0 if the queue can not be released, there are references to it.
 440  *   Negative errno and rte_errno is set if queue doesn't exist.
 441  */
 442 static int
 443 mlx5_rxq_releasable(struct rte_eth_dev *dev, uint16_t idx)
 444 {
 445         struct mlx5_priv *priv = dev->data->dev_private;
 446         struct mlx5_rxq_ctrl *rxq_ctrl;
 447
 448         if (!(*priv->rxqs)[idx]) {
 449                 rte_errno = EINVAL;
 450                 return -rte_errno;
 451         }
 452         rxq_ctrl = container_of((*priv->rxqs)[idx], struct mlx5_rxq_ctrl, rxq);
 453         return (rte_atomic32_read(&rxq_ctrl->refcnt) == 1);
 454 }
 455
 456 /* Fetches and drops all SW-owned and error CQEs to synchronize CQ. */
 457 static void
 458 rxq_sync_cq(struct mlx5_rxq_data *rxq)
 459 {
 460         const uint16_t cqe_n = 1 << rxq->cqe_n;
 461         const uint16_t cqe_mask = cqe_n - 1;
 462         volatile struct mlx5_cqe *cqe;
 463         int ret, i;
 464
 465         i = cqe_n;
 466         do {
 467                 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_mask];
 468                 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
 469                 if (ret == MLX5_CQE_STATUS_HW_OWN)
 470                         break;
 471                 if (ret == MLX5_CQE_STATUS_ERR) {
 472                         rxq->cq_ci++;
 473                         continue;
 474                 }
 475                 MLX5_ASSERT(ret == MLX5_CQE_STATUS_SW_OWN);
 476                 if (MLX5_CQE_FORMAT(cqe->op_own) != MLX5_COMPRESSED) {
 477                         rxq->cq_ci++;
 478                         continue;
 479                 }
 480                 /* Compute the next non compressed CQE. */
 481                 rxq->cq_ci += rte_be_to_cpu_32(cqe->byte_cnt);
 482
 483         } while (--i);
 484         /* Move all CQEs to HW ownership, including possible MiniCQEs. */
 485         for (i = 0; i < cqe_n; i++) {
 486                 cqe = &(*rxq->cqes)[i];
 487                 cqe->op_own = MLX5_CQE_INVALIDATE;
 488         }
 489         /* Resync CQE and WQE (WQ in RESET state). */
 490         rte_cio_wmb();
 491         *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
 492         rte_cio_wmb();
 493         *rxq->rq_db = rte_cpu_to_be_32(0);
 494         rte_cio_wmb();
 495 }
 496
 497 /**
 498  * Rx queue stop. Device queue goes to the RESET state,
 499  * all involved mbufs are freed from WQ.
 500  *
 501  * @param dev
 502  *   Pointer to Ethernet device structure.
 503  * @param idx
 504  *   RX queue index.
 505  *
 506  * @return
 507  *   0 on success, a negative errno value otherwise and rte_errno is set.
 508  */
 509 int
 510 mlx5_rx_queue_stop_primary(struct rte_eth_dev *dev, uint16_t idx)
 511 {
 512         struct mlx5_priv *priv = dev->data->dev_private;
 513         struct mlx5_rxq_data *rxq = (*priv->rxqs)[idx];
 514         struct mlx5_rxq_ctrl *rxq_ctrl =
 515                         container_of(rxq, struct mlx5_rxq_ctrl, rxq);
 516         int ret;
 517
 518         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 519         ret = priv->obj_ops->rxq_obj_modify(rxq_ctrl->obj, false);
 520         if (ret) {
 521                 DRV_LOG(ERR, "Cannot change Rx WQ state to RESET:  %s",
 522                         strerror(errno));
 523                 rte_errno = errno;
 524                 return ret;
 525         }
 526         /* Remove all processes CQEs. */
 527         rxq_sync_cq(rxq);
 528         /* Free all involved mbufs. */
 529         rxq_free_elts(rxq_ctrl);
 530         /* Set the actual queue state. */
 531         dev->data->rx_queue_state[idx] = RTE_ETH_QUEUE_STATE_STOPPED;
 532         return 0;
 533 }
 534
 535 /**
 536  * Rx queue stop. Device queue goes to the RESET state,
 537  * all involved mbufs are freed from WQ.
 538  *
 539  * @param dev
 540  *   Pointer to Ethernet device structure.
 541  * @param idx
 542  *   RX queue index.
 543  *
 544  * @return
 545  *   0 on success, a negative errno value otherwise and rte_errno is set.
 546  */
 547 int
 548 mlx5_rx_queue_stop(struct rte_eth_dev *dev, uint16_t idx)
 549 {
 550         eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
 551         int ret;
 552
 553         if (dev->data->rx_queue_state[idx] == RTE_ETH_QUEUE_STATE_HAIRPIN) {
 554                 DRV_LOG(ERR, "Hairpin queue can't be stopped");
 555                 rte_errno = EINVAL;
 556                 return -EINVAL;
 557         }
 558         if (dev->data->rx_queue_state[idx] == RTE_ETH_QUEUE_STATE_STOPPED)
 559                 return 0;
 560         /*
 561          * Vectorized Rx burst requires the CQ and RQ indices
 562          * synchronized, that might be broken on RQ restart
 563          * and cause Rx malfunction, so queue stopping is
 564          * not supported if vectorized Rx burst is engaged.
 565          * The routine pointer depends on the process
 566          * type, should perform check there.
 567          */
 568         if (pkt_burst == mlx5_rx_burst) {
 569                 DRV_LOG(ERR, "Rx queue stop is not supported "
 570                         "for vectorized Rx");
 571                 rte_errno = EINVAL;
 572                 return -EINVAL;
 573         }
 574         if (rte_eal_process_type() ==  RTE_PROC_SECONDARY) {
 575                 ret = mlx5_mp_os_req_queue_control(dev, idx,
 576                                                    MLX5_MP_REQ_QUEUE_RX_STOP);
 577         } else {
 578                 ret = mlx5_rx_queue_stop_primary(dev, idx);
 579         }
 580         return ret;
 581 }
 582
 583 /**
 584  * Rx queue start. Device queue goes to the ready state,
 585  * all required mbufs are allocated and WQ is replenished.
 586  *
 587  * @param dev
 588  *   Pointer to Ethernet device structure.
 589  * @param idx
 590  *   RX queue index.
 591  *
 592  * @return
 593  *   0 on success, a negative errno value otherwise and rte_errno is set.
 594  */
 595 int
 596 mlx5_rx_queue_start_primary(struct rte_eth_dev *dev, uint16_t idx)
 597 {
 598         struct mlx5_priv *priv = dev->data->dev_private;
 599         struct mlx5_rxq_data *rxq = (*priv->rxqs)[idx];
 600         struct mlx5_rxq_ctrl *rxq_ctrl =
 601                         container_of(rxq, struct mlx5_rxq_ctrl, rxq);
 602         int ret;
 603
 604         MLX5_ASSERT(rte_eal_process_type() ==  RTE_PROC_PRIMARY);
 605         /* Allocate needed buffers. */
 606         ret = rxq_alloc_elts(rxq_ctrl);
 607         if (ret) {
 608                 DRV_LOG(ERR, "Cannot reallocate buffers for Rx WQ");
 609                 rte_errno = errno;
 610                 return ret;
 611         }
 612         rte_cio_wmb();
 613         *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
 614         rte_cio_wmb();
 615         /* Reset RQ consumer before moving queue to READY state. */
 616         *rxq->rq_db = rte_cpu_to_be_32(0);
 617         rte_cio_wmb();
 618         ret = priv->obj_ops->rxq_obj_modify(rxq_ctrl->obj, true);
 619         if (ret) {
 620                 DRV_LOG(ERR, "Cannot change Rx WQ state to READY:  %s",
 621                         strerror(errno));
 622                 rte_errno = errno;
 623                 return ret;
 624         }
 625         /* Reinitialize RQ - set WQEs. */
 626         mlx5_rxq_initialize(rxq);
 627         rxq->err_state = MLX5_RXQ_ERR_STATE_NO_ERROR;
 628         /* Set actual queue state. */
 629         dev->data->rx_queue_state[idx] = RTE_ETH_QUEUE_STATE_STARTED;
 630         return 0;
 631 }
 632
 633 /**
 634  * Rx queue start. Device queue goes to the ready state,
 635  * all required mbufs are allocated and WQ is replenished.
 636  *
 637  * @param dev
 638  *   Pointer to Ethernet device structure.
 639  * @param idx
 640  *   RX queue index.
 641  *
 642  * @return
 643  *   0 on success, a negative errno value otherwise and rte_errno is set.
 644  */
 645 int
 646 mlx5_rx_queue_start(struct rte_eth_dev *dev, uint16_t idx)
 647 {
 648         int ret;
 649
 650         if (dev->data->rx_queue_state[idx] == RTE_ETH_QUEUE_STATE_HAIRPIN) {
 651                 DRV_LOG(ERR, "Hairpin queue can't be started");
 652                 rte_errno = EINVAL;
 653                 return -EINVAL;
 654         }
 655         if (dev->data->rx_queue_state[idx] == RTE_ETH_QUEUE_STATE_STARTED)
 656                 return 0;
 657         if (rte_eal_process_type() ==  RTE_PROC_SECONDARY) {
 658                 ret = mlx5_mp_os_req_queue_control(dev, idx,
 659                                                    MLX5_MP_REQ_QUEUE_RX_START);
 660         } else {
 661                 ret = mlx5_rx_queue_start_primary(dev, idx);
 662         }
 663         return ret;
 664 }
 665
 666 /**
 667  * Rx queue presetup checks.
 668  *
 669  * @param dev
 670  *   Pointer to Ethernet device structure.
 671  * @param idx
 672  *   RX queue index.
 673  * @param desc
 674  *   Number of descriptors to configure in queue.
 675  *
 676  * @return
 677  *   0 on success, a negative errno value otherwise and rte_errno is set.
 678  */
 679 static int
 680 mlx5_rx_queue_pre_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t *desc)
 681 {
 682         struct mlx5_priv *priv = dev->data->dev_private;
 683
 684         if (!rte_is_power_of_2(*desc)) {
 685                 *desc = 1 << log2above(*desc);
 686                 DRV_LOG(WARNING,
 687                         "port %u increased number of descriptors in Rx queue %u"
 688                         " to the next power of two (%d)",
 689                         dev->data->port_id, idx, *desc);
 690         }
 691         DRV_LOG(DEBUG, "port %u configuring Rx queue %u for %u descriptors",
 692                 dev->data->port_id, idx, *desc);
 693         if (idx >= priv->rxqs_n) {
 694                 DRV_LOG(ERR, "port %u Rx queue index out of range (%u >= %u)",
 695                         dev->data->port_id, idx, priv->rxqs_n);
 696                 rte_errno = EOVERFLOW;
 697                 return -rte_errno;
 698         }
 699         if (!mlx5_rxq_releasable(dev, idx)) {
 700                 DRV_LOG(ERR, "port %u unable to release queue index %u",
 701                         dev->data->port_id, idx);
 702                 rte_errno = EBUSY;
 703                 return -rte_errno;
 704         }
 705         mlx5_rxq_release(dev, idx);
 706         return 0;
 707 }
 708
 709 /**
 710  *
 711  * @param dev
 712  *   Pointer to Ethernet device structure.
 713  * @param idx
 714  *   RX queue index.
 715  * @param desc
 716  *   Number of descriptors to configure in queue.
 717  * @param socket
 718  *   NUMA socket on which memory must be allocated.
 719  * @param[in] conf
 720  *   Thresholds parameters.
 721  * @param mp
 722  *   Memory pool for buffer allocations.
 723  *
 724  * @return
 725  *   0 on success, a negative errno value otherwise and rte_errno is set.
 726  */
 727 int
 728 mlx5_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
 729                     unsigned int socket, const struct rte_eth_rxconf *conf,
 730                     struct rte_mempool *mp)
 731 {
 732         struct mlx5_priv *priv = dev->data->dev_private;
 733         struct mlx5_rxq_data *rxq = (*priv->rxqs)[idx];
 734         struct mlx5_rxq_ctrl *rxq_ctrl =
 735                 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
 736         int res;
 737
 738         res = mlx5_rx_queue_pre_setup(dev, idx, &desc);
 739         if (res)
 740                 return res;
 741         rxq_ctrl = mlx5_rxq_new(dev, idx, desc, socket, conf, mp);
 742         if (!rxq_ctrl) {
 743                 DRV_LOG(ERR, "port %u unable to allocate queue index %u",
 744                         dev->data->port_id, idx);
 745                 rte_errno = ENOMEM;
 746                 return -rte_errno;
 747         }
 748         DRV_LOG(DEBUG, "port %u adding Rx queue %u to list",
 749                 dev->data->port_id, idx);
 750         (*priv->rxqs)[idx] = &rxq_ctrl->rxq;
 751         return 0;
 752 }
 753
 754 /**
 755  *
 756  * @param dev
 757  *   Pointer to Ethernet device structure.
 758  * @param idx
 759  *   RX queue index.
 760  * @param desc
 761  *   Number of descriptors to configure in queue.
 762  * @param hairpin_conf
 763  *   Hairpin configuration parameters.
 764  *
 765  * @return
 766  *   0 on success, a negative errno value otherwise and rte_errno is set.
 767  */
 768 int
 769 mlx5_rx_hairpin_queue_setup(struct rte_eth_dev *dev, uint16_t idx,
 770                             uint16_t desc,
 771                             const struct rte_eth_hairpin_conf *hairpin_conf)
 772 {
 773         struct mlx5_priv *priv = dev->data->dev_private;
 774         struct mlx5_rxq_data *rxq = (*priv->rxqs)[idx];
 775         struct mlx5_rxq_ctrl *rxq_ctrl =
 776                 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
 777         int res;
 778
 779         res = mlx5_rx_queue_pre_setup(dev, idx, &desc);
 780         if (res)
 781                 return res;
 782         if (hairpin_conf->peer_count != 1 ||
 783             hairpin_conf->peers[0].port != dev->data->port_id ||
 784             hairpin_conf->peers[0].queue >= priv->txqs_n) {
 785                 DRV_LOG(ERR, "port %u unable to setup hairpin queue index %u "
 786                         " invalid hairpind configuration", dev->data->port_id,
 787                         idx);
 788                 rte_errno = EINVAL;
 789                 return -rte_errno;
 790         }
 791         rxq_ctrl = mlx5_rxq_hairpin_new(dev, idx, desc, hairpin_conf);
 792         if (!rxq_ctrl) {
 793                 DRV_LOG(ERR, "port %u unable to allocate queue index %u",
 794                         dev->data->port_id, idx);
 795                 rte_errno = ENOMEM;
 796                 return -rte_errno;
 797         }
 798         DRV_LOG(DEBUG, "port %u adding Rx queue %u to list",
 799                 dev->data->port_id, idx);
 800         (*priv->rxqs)[idx] = &rxq_ctrl->rxq;
 801         return 0;
 802 }
 803
 804 /**
 805  * DPDK callback to release a RX queue.
 806  *
 807  * @param dpdk_rxq
 808  *   Generic RX queue pointer.
 809  */
 810 void
 811 mlx5_rx_queue_release(void *dpdk_rxq)
 812 {
 813         struct mlx5_rxq_data *rxq = (struct mlx5_rxq_data *)dpdk_rxq;
 814         struct mlx5_rxq_ctrl *rxq_ctrl;
 815         struct mlx5_priv *priv;
 816
 817         if (rxq == NULL)
 818                 return;
 819         rxq_ctrl = container_of(rxq, struct mlx5_rxq_ctrl, rxq);
 820         priv = rxq_ctrl->priv;
 821         if (!mlx5_rxq_releasable(ETH_DEV(priv), rxq_ctrl->rxq.idx))
 822                 rte_panic("port %u Rx queue %u is still used by a flow and"
 823                           " cannot be removed\n",
 824                           PORT_ID(priv), rxq->idx);
 825         mlx5_rxq_release(ETH_DEV(priv), rxq_ctrl->rxq.idx);
 826 }
 827
 828 /**
 829  * Allocate queue vector and fill epoll fd list for Rx interrupts.
 830  *
 831  * @param dev
 832  *   Pointer to Ethernet device.
 833  *
 834  * @return
 835  *   0 on success, a negative errno value otherwise and rte_errno is set.
 836  */
 837 int
 838 mlx5_rx_intr_vec_enable(struct rte_eth_dev *dev)
 839 {
 840         struct mlx5_priv *priv = dev->data->dev_private;
 841         unsigned int i;
 842         unsigned int rxqs_n = priv->rxqs_n;
 843         unsigned int n = RTE_MIN(rxqs_n, (uint32_t)RTE_MAX_RXTX_INTR_VEC_ID);
 844         unsigned int count = 0;
 845         struct rte_intr_handle *intr_handle = dev->intr_handle;
 846
 847         if (!dev->data->dev_conf.intr_conf.rxq)
 848                 return 0;
 849         mlx5_rx_intr_vec_disable(dev);
 850         intr_handle->intr_vec = mlx5_malloc(0,
 851                                 n * sizeof(intr_handle->intr_vec[0]),
 852                                 0, SOCKET_ID_ANY);
 853         if (intr_handle->intr_vec == NULL) {
 854                 DRV_LOG(ERR,
 855                         "port %u failed to allocate memory for interrupt"
 856                         " vector, Rx interrupts will not be supported",
 857                         dev->data->port_id);
 858                 rte_errno = ENOMEM;
 859                 return -rte_errno;
 860         }
 861         intr_handle->type = RTE_INTR_HANDLE_EXT;
 862         for (i = 0; i != n; ++i) {
 863                 /* This rxq obj must not be released in this function. */
 864                 struct mlx5_rxq_ctrl *rxq_ctrl = mlx5_rxq_get(dev, i);
 865                 struct mlx5_rxq_obj *rxq_obj = rxq_ctrl ? rxq_ctrl->obj : NULL;
 866                 int rc;
 867
 868                 /* Skip queues that cannot request interrupts. */
 869                 if (!rxq_obj || (!rxq_obj->ibv_channel &&
 870                                  !rxq_obj->devx_channel)) {
 871                         /* Use invalid intr_vec[] index to disable entry. */
 872                         intr_handle->intr_vec[i] =
 873                                 RTE_INTR_VEC_RXTX_OFFSET +
 874                                 RTE_MAX_RXTX_INTR_VEC_ID;
 875                         /* Decrease the rxq_ctrl's refcnt */
 876                         if (rxq_ctrl)
 877                                 mlx5_rxq_release(dev, i);
 878                         continue;
 879                 }
 880                 if (count >= RTE_MAX_RXTX_INTR_VEC_ID) {
 881                         DRV_LOG(ERR,
 882                                 "port %u too many Rx queues for interrupt"
 883                                 " vector size (%d), Rx interrupts cannot be"
 884                                 " enabled",
 885                                 dev->data->port_id, RTE_MAX_RXTX_INTR_VEC_ID);
 886                         mlx5_rx_intr_vec_disable(dev);
 887                         rte_errno = ENOMEM;
 888                         return -rte_errno;
 889                 }
 890                 rc = mlx5_os_set_nonblock_channel_fd(rxq_obj->fd);
 891                 if (rc < 0) {
 892                         rte_errno = errno;
 893                         DRV_LOG(ERR,
 894                                 "port %u failed to make Rx interrupt file"
 895                                 " descriptor %d non-blocking for queue index"
 896                                 " %d",
 897                                 dev->data->port_id, rxq_obj->fd, i);
 898                         mlx5_rx_intr_vec_disable(dev);
 899                         return -rte_errno;
 900                 }
 901                 intr_handle->intr_vec[i] = RTE_INTR_VEC_RXTX_OFFSET + count;
 902                 intr_handle->efds[count] = rxq_obj->fd;
 903                 count++;
 904         }
 905         if (!count)
 906                 mlx5_rx_intr_vec_disable(dev);
 907         else
 908                 intr_handle->nb_efd = count;
 909         return 0;
 910 }
 911
 912 /**
 913  * Clean up Rx interrupts handler.
 914  *
 915  * @param dev
 916  *   Pointer to Ethernet device.
 917  */
 918 void
 919 mlx5_rx_intr_vec_disable(struct rte_eth_dev *dev)
 920 {
 921         struct mlx5_priv *priv = dev->data->dev_private;
 922         struct rte_intr_handle *intr_handle = dev->intr_handle;
 923         unsigned int i;
 924         unsigned int rxqs_n = priv->rxqs_n;
 925         unsigned int n = RTE_MIN(rxqs_n, (uint32_t)RTE_MAX_RXTX_INTR_VEC_ID);
 926
 927         if (!dev->data->dev_conf.intr_conf.rxq)
 928                 return;
 929         if (!intr_handle->intr_vec)
 930                 goto free;
 931         for (i = 0; i != n; ++i) {
 932                 if (intr_handle->intr_vec[i] == RTE_INTR_VEC_RXTX_OFFSET +
 933                     RTE_MAX_RXTX_INTR_VEC_ID)
 934                         continue;
 935                 /**
 936                  * Need to access directly the queue to release the reference
 937                  * kept in mlx5_rx_intr_vec_enable().
 938                  */
 939                 mlx5_rxq_release(dev, i);
 940         }
 941 free:
 942         rte_intr_free_epoll_fd(intr_handle);
 943         if (intr_handle->intr_vec)
 944                 mlx5_free(intr_handle->intr_vec);
 945         intr_handle->nb_efd = 0;
 946         intr_handle->intr_vec = NULL;
 947 }
 948
 949 /**
 950  *  MLX5 CQ notification .
 951  *
 952  *  @param rxq
 953  *     Pointer to receive queue structure.
 954  *  @param sq_n_rxq
 955  *     Sequence number per receive queue .
 956  */
 957 static inline void
 958 mlx5_arm_cq(struct mlx5_rxq_data *rxq, int sq_n_rxq)
 959 {
 960         int sq_n = 0;
 961         uint32_t doorbell_hi;
 962         uint64_t doorbell;
 963         void *cq_db_reg = (char *)rxq->cq_uar + MLX5_CQ_DOORBELL;
 964
 965         sq_n = sq_n_rxq & MLX5_CQ_SQN_MASK;
 966         doorbell_hi = sq_n << MLX5_CQ_SQN_OFFSET | (rxq->cq_ci & MLX5_CI_MASK);
 967         doorbell = (uint64_t)doorbell_hi << 32;
 968         doorbell |= rxq->cqn;
 969         rxq->cq_db[MLX5_CQ_ARM_DB] = rte_cpu_to_be_32(doorbell_hi);
 970         mlx5_uar_write64(rte_cpu_to_be_64(doorbell),
 971                          cq_db_reg, rxq->uar_lock_cq);
 972 }
 973
 974 /**
 975  * DPDK callback for Rx queue interrupt enable.
 976  *
 977  * @param dev
 978  *   Pointer to Ethernet device structure.
 979  * @param rx_queue_id
 980  *   Rx queue number.
 981  *
 982  * @return
 983  *   0 on success, a negative errno value otherwise and rte_errno is set.
 984  */
 985 int
 986 mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 987 {
 988         struct mlx5_rxq_ctrl *rxq_ctrl;
 989
 990         rxq_ctrl = mlx5_rxq_get(dev, rx_queue_id);
 991         if (!rxq_ctrl)
 992                 goto error;
 993         if (rxq_ctrl->irq) {
 994                 if (!rxq_ctrl->obj) {
 995                         mlx5_rxq_release(dev, rx_queue_id);
 996                         goto error;
 997                 }
 998                 mlx5_arm_cq(&rxq_ctrl->rxq, rxq_ctrl->rxq.cq_arm_sn);
 999         }
1000         mlx5_rxq_release(dev, rx_queue_id);
1001         return 0;
1002 error:
1003         rte_errno = EINVAL;
1004         return -rte_errno;
1005 }
1006
1007 /**
1008  * DPDK callback for Rx queue interrupt disable.
1009  *
1010  * @param dev
1011  *   Pointer to Ethernet device structure.
1012  * @param rx_queue_id
1013  *   Rx queue number.
1014  *
1015  * @return
1016  *   0 on success, a negative errno value otherwise and rte_errno is set.
1017  */
1018 int
1019 mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1020 {
1021         struct mlx5_priv *priv = dev->data->dev_private;
1022         struct mlx5_rxq_ctrl *rxq_ctrl;
1023         int ret = 0;
1024
1025         rxq_ctrl = mlx5_rxq_get(dev, rx_queue_id);
1026         if (!rxq_ctrl) {
1027                 rte_errno = EINVAL;
1028                 return -rte_errno;
1029         }
1030         if (!rxq_ctrl->obj)
1031                 goto error;
1032         if (rxq_ctrl->irq) {
1033                 ret = priv->obj_ops->rxq_event_get(rxq_ctrl->obj);
1034                 if (ret < 0)
1035                         goto error;
1036                 rxq_ctrl->rxq.cq_arm_sn++;
1037         }
1038         mlx5_rxq_release(dev, rx_queue_id);
1039         return 0;
1040 error:
1041         /**
1042          * The ret variable may be EAGAIN which means the get_event function was
1043          * called before receiving one.
1044          */
1045         if (ret < 0)
1046                 rte_errno = errno;
1047         else
1048                 rte_errno = EINVAL;
1049         ret = rte_errno; /* Save rte_errno before cleanup. */
1050         mlx5_rxq_release(dev, rx_queue_id);
1051         if (ret != EAGAIN)
1052                 DRV_LOG(WARNING, "port %u unable to disable interrupt on Rx queue %d",
1053                         dev->data->port_id, rx_queue_id);
1054         rte_errno = ret; /* Restore rte_errno. */
1055         return -rte_errno;
1056 }
1057
1058 /**
1059  * Verify the Rx queue objects list is empty
1060  *
1061  * @param dev
1062  *   Pointer to Ethernet device.
1063  *
1064  * @return
1065  *   The number of objects not released.
1066  */
1067 int
1068 mlx5_rxq_obj_verify(struct rte_eth_dev *dev)
1069 {
1070         struct mlx5_priv *priv = dev->data->dev_private;
1071         int ret = 0;
1072         struct mlx5_rxq_obj *rxq_obj;
1073
1074         LIST_FOREACH(rxq_obj, &priv->rxqsobj, next) {
1075                 DRV_LOG(DEBUG, "port %u Rx queue %u still referenced",
1076                         dev->data->port_id, rxq_obj->rxq_ctrl->rxq.idx);
1077                 ++ret;
1078         }
1079         return ret;
1080 }
1081
1082 /**
1083  * Callback function to initialize mbufs for Multi-Packet RQ.
1084  */
1085 static inline void
1086 mlx5_mprq_buf_init(struct rte_mempool *mp, void *opaque_arg,
1087                     void *_m, unsigned int i __rte_unused)
1088 {
1089         struct mlx5_mprq_buf *buf = _m;
1090         struct rte_mbuf_ext_shared_info *shinfo;
1091         unsigned int strd_n = (unsigned int)(uintptr_t)opaque_arg;
1092         unsigned int j;
1093
1094         memset(_m, 0, sizeof(*buf));
1095         buf->mp = mp;
1096         rte_atomic16_set(&buf->refcnt, 1);
1097         for (j = 0; j != strd_n; ++j) {
1098                 shinfo = &buf->shinfos[j];
1099                 shinfo->free_cb = mlx5_mprq_buf_free_cb;
1100                 shinfo->fcb_opaque = buf;
1101         }
1102 }
1103
1104 /**
1105  * Free mempool of Multi-Packet RQ.
1106  *
1107  * @param dev
1108  *   Pointer to Ethernet device.
1109  *
1110  * @return
1111  *   0 on success, negative errno value on failure.
1112  */
1113 int
1114 mlx5_mprq_free_mp(struct rte_eth_dev *dev)
1115 {
1116         struct mlx5_priv *priv = dev->data->dev_private;
1117         struct rte_mempool *mp = priv->mprq_mp;
1118         unsigned int i;
1119
1120         if (mp == NULL)
1121                 return 0;
1122         DRV_LOG(DEBUG, "port %u freeing mempool (%s) for Multi-Packet RQ",
1123                 dev->data->port_id, mp->name);
1124         /*
1125          * If a buffer in the pool has been externally attached to a mbuf and it
1126          * is still in use by application, destroying the Rx queue can spoil
1127          * the packet. It is unlikely to happen but if application dynamically
1128          * creates and destroys with holding Rx packets, this can happen.
1129          *
1130          * TODO: It is unavoidable for now because the mempool for Multi-Packet
1131          * RQ isn't provided by application but managed by PMD.
1132          */
1133         if (!rte_mempool_full(mp)) {
1134                 DRV_LOG(ERR,
1135                         "port %u mempool for Multi-Packet RQ is still in use",
1136                         dev->data->port_id);
1137                 rte_errno = EBUSY;
1138                 return -rte_errno;
1139         }
1140         rte_mempool_free(mp);
1141         /* Unset mempool for each Rx queue. */
1142         for (i = 0; i != priv->rxqs_n; ++i) {
1143                 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
1144
1145                 if (rxq == NULL)
1146                         continue;
1147                 rxq->mprq_mp = NULL;
1148         }
1149         priv->mprq_mp = NULL;
1150         return 0;
1151 }
1152
1153 /**
1154  * Allocate a mempool for Multi-Packet RQ. All configured Rx queues share the
1155  * mempool. If already allocated, reuse it if there're enough elements.
1156  * Otherwise, resize it.
1157  *
1158  * @param dev
1159  *   Pointer to Ethernet device.
1160  *
1161  * @return
1162  *   0 on success, negative errno value on failure.
1163  */
1164 int
1165 mlx5_mprq_alloc_mp(struct rte_eth_dev *dev)
1166 {
1167         struct mlx5_priv *priv = dev->data->dev_private;
1168         struct rte_mempool *mp = priv->mprq_mp;
1169         char name[RTE_MEMPOOL_NAMESIZE];
1170         unsigned int desc = 0;
1171         unsigned int buf_len;
1172         unsigned int obj_num;
1173         unsigned int obj_size;
1174         unsigned int strd_num_n = 0;
1175         unsigned int strd_sz_n = 0;
1176         unsigned int i;
1177         unsigned int n_ibv = 0;
1178
1179         if (!mlx5_mprq_enabled(dev))
1180                 return 0;
1181         /* Count the total number of descriptors configured. */
1182         for (i = 0; i != priv->rxqs_n; ++i) {
1183                 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
1184                 struct mlx5_rxq_ctrl *rxq_ctrl = container_of
1185                         (rxq, struct mlx5_rxq_ctrl, rxq);
1186
1187                 if (rxq == NULL || rxq_ctrl->type != MLX5_RXQ_TYPE_STANDARD)
1188                         continue;
1189                 n_ibv++;
1190                 desc += 1 << rxq->elts_n;
1191                 /* Get the max number of strides. */
1192                 if (strd_num_n < rxq->strd_num_n)
1193                         strd_num_n = rxq->strd_num_n;
1194                 /* Get the max size of a stride. */
1195                 if (strd_sz_n < rxq->strd_sz_n)
1196                         strd_sz_n = rxq->strd_sz_n;
1197         }
1198         MLX5_ASSERT(strd_num_n && strd_sz_n);
1199         buf_len = (1 << strd_num_n) * (1 << strd_sz_n);
1200         obj_size = sizeof(struct mlx5_mprq_buf) + buf_len + (1 << strd_num_n) *
1201                 sizeof(struct rte_mbuf_ext_shared_info) + RTE_PKTMBUF_HEADROOM;
1202         /*
1203          * Received packets can be either memcpy'd or externally referenced. In
1204          * case that the packet is attached to an mbuf as an external buffer, as
1205          * it isn't possible to predict how the buffers will be queued by
1206          * application, there's no option to exactly pre-allocate needed buffers
1207          * in advance but to speculatively prepares enough buffers.
1208          *
1209          * In the data path, if this Mempool is depleted, PMD will try to memcpy
1210          * received packets to buffers provided by application (rxq->mp) until
1211          * this Mempool gets available again.
1212          */
1213         desc *= 4;
1214         obj_num = desc + MLX5_MPRQ_MP_CACHE_SZ * n_ibv;
1215         /*
1216          * rte_mempool_create_empty() has sanity check to refuse large cache
1217          * size compared to the number of elements.
1218          * CACHE_FLUSHTHRESH_MULTIPLIER is defined in a C file, so using a
1219          * constant number 2 instead.
1220          */
1221         obj_num = RTE_MAX(obj_num, MLX5_MPRQ_MP_CACHE_SZ * 2);
1222         /* Check a mempool is already allocated and if it can be resued. */
1223         if (mp != NULL && mp->elt_size >= obj_size && mp->size >= obj_num) {
1224                 DRV_LOG(DEBUG, "port %u mempool %s is being reused",
1225                         dev->data->port_id, mp->name);
1226                 /* Reuse. */
1227                 goto exit;
1228         } else if (mp != NULL) {
1229                 DRV_LOG(DEBUG, "port %u mempool %s should be resized, freeing it",
1230                         dev->data->port_id, mp->name);
1231                 /*
1232                  * If failed to free, which means it may be still in use, no way
1233                  * but to keep using the existing one. On buffer underrun,
1234                  * packets will be memcpy'd instead of external buffer
1235                  * attachment.
1236                  */
1237                 if (mlx5_mprq_free_mp(dev)) {
1238                         if (mp->elt_size >= obj_size)
1239                                 goto exit;
1240                         else
1241                                 return -rte_errno;
1242                 }
1243         }
1244         snprintf(name, sizeof(name), "port-%u-mprq", dev->data->port_id);
1245         mp = rte_mempool_create(name, obj_num, obj_size, MLX5_MPRQ_MP_CACHE_SZ,
1246                                 0, NULL, NULL, mlx5_mprq_buf_init,
1247                                 (void *)(uintptr_t)(1 << strd_num_n),
1248                                 dev->device->numa_node, 0);
1249         if (mp == NULL) {
1250                 DRV_LOG(ERR,
1251                         "port %u failed to allocate a mempool for"
1252                         " Multi-Packet RQ, count=%u, size=%u",
1253                         dev->data->port_id, obj_num, obj_size);
1254                 rte_errno = ENOMEM;
1255                 return -rte_errno;
1256         }
1257         priv->mprq_mp = mp;
1258 exit:
1259         /* Set mempool for each Rx queue. */
1260         for (i = 0; i != priv->rxqs_n; ++i) {
1261                 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
1262                 struct mlx5_rxq_ctrl *rxq_ctrl = container_of
1263                         (rxq, struct mlx5_rxq_ctrl, rxq);
1264
1265                 if (rxq == NULL || rxq_ctrl->type != MLX5_RXQ_TYPE_STANDARD)
1266                         continue;
1267                 rxq->mprq_mp = mp;
1268         }
1269         DRV_LOG(INFO, "port %u Multi-Packet RQ is configured",
1270                 dev->data->port_id);
1271         return 0;
1272 }
1273
1274 #define MLX5_MAX_TCP_HDR_OFFSET ((unsigned int)(sizeof(struct rte_ether_hdr) + \
1275                                         sizeof(struct rte_vlan_hdr) * 2 + \
1276                                         sizeof(struct rte_ipv6_hdr)))
1277 #define MAX_TCP_OPTION_SIZE 40u
1278 #define MLX5_MAX_LRO_HEADER_FIX ((unsigned int)(MLX5_MAX_TCP_HDR_OFFSET + \
1279                                  sizeof(struct rte_tcp_hdr) + \
1280                                  MAX_TCP_OPTION_SIZE))
1281
1282 /**
1283  * Adjust the maximum LRO massage size.
1284  *
1285  * @param dev
1286  *   Pointer to Ethernet device.
1287  * @param idx
1288  *   RX queue index.
1289  * @param max_lro_size
1290  *   The maximum size for LRO packet.
1291  */
1292 static void
1293 mlx5_max_lro_msg_size_adjust(struct rte_eth_dev *dev, uint16_t idx,
1294                              uint32_t max_lro_size)
1295 {
1296         struct mlx5_priv *priv = dev->data->dev_private;
1297
1298         if (priv->config.hca_attr.lro_max_msg_sz_mode ==
1299             MLX5_LRO_MAX_MSG_SIZE_START_FROM_L4 && max_lro_size >
1300             MLX5_MAX_TCP_HDR_OFFSET)
1301                 max_lro_size -= MLX5_MAX_TCP_HDR_OFFSET;
1302         max_lro_size = RTE_MIN(max_lro_size, MLX5_MAX_LRO_SIZE);
1303         MLX5_ASSERT(max_lro_size >= MLX5_LRO_SEG_CHUNK_SIZE);
1304         max_lro_size /= MLX5_LRO_SEG_CHUNK_SIZE;
1305         if (priv->max_lro_msg_size)
1306                 priv->max_lro_msg_size =
1307                         RTE_MIN((uint32_t)priv->max_lro_msg_size, max_lro_size);
1308         else
1309                 priv->max_lro_msg_size = max_lro_size;
1310         DRV_LOG(DEBUG,
1311                 "port %u Rx Queue %u max LRO message size adjusted to %u bytes",
1312                 dev->data->port_id, idx,
1313                 priv->max_lro_msg_size * MLX5_LRO_SEG_CHUNK_SIZE);
1314 }
1315
1316 /**
1317  * Create a DPDK Rx queue.
1318  *
1319  * @param dev
1320  *   Pointer to Ethernet device.
1321  * @param idx
1322  *   RX queue index.
1323  * @param desc
1324  *   Number of descriptors to configure in queue.
1325  * @param socket
1326  *   NUMA socket on which memory must be allocated.
1327  *
1328  * @return
1329  *   A DPDK queue object on success, NULL otherwise and rte_errno is set.
1330  */
1331 struct mlx5_rxq_ctrl *
1332 mlx5_rxq_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1333              unsigned int socket, const struct rte_eth_rxconf *conf,
1334              struct rte_mempool *mp)
1335 {
1336         struct mlx5_priv *priv = dev->data->dev_private;
1337         struct mlx5_rxq_ctrl *tmpl;
1338         unsigned int mb_len = rte_pktmbuf_data_room_size(mp);
1339         unsigned int mprq_stride_nums;
1340         unsigned int mprq_stride_size;
1341         unsigned int mprq_stride_cap;
1342         struct mlx5_dev_config *config = &priv->config;
1343         /*
1344          * Always allocate extra slots, even if eventually
1345          * the vector Rx will not be used.
1346          */
1347         uint16_t desc_n =
1348                 desc + config->rx_vec_en * MLX5_VPMD_DESCS_PER_LOOP;
1349         uint64_t offloads = conf->offloads |
1350                            dev->data->dev_conf.rxmode.offloads;
1351         unsigned int lro_on_queue = !!(offloads & DEV_RX_OFFLOAD_TCP_LRO);
1352         const int mprq_en = mlx5_check_mprq_support(dev) > 0;
1353         unsigned int max_rx_pkt_len = lro_on_queue ?
1354                         dev->data->dev_conf.rxmode.max_lro_pkt_size :
1355                         dev->data->dev_conf.rxmode.max_rx_pkt_len;
1356         unsigned int non_scatter_min_mbuf_size = max_rx_pkt_len +
1357                                                         RTE_PKTMBUF_HEADROOM;
1358         unsigned int max_lro_size = 0;
1359         unsigned int first_mb_free_size = mb_len - RTE_PKTMBUF_HEADROOM;
1360
1361         if (non_scatter_min_mbuf_size > mb_len && !(offloads &
1362                                                     DEV_RX_OFFLOAD_SCATTER)) {
1363                 DRV_LOG(ERR, "port %u Rx queue %u: Scatter offload is not"
1364                         " configured and no enough mbuf space(%u) to contain "
1365                         "the maximum RX packet length(%u) with head-room(%u)",
1366                         dev->data->port_id, idx, mb_len, max_rx_pkt_len,
1367                         RTE_PKTMBUF_HEADROOM);
1368                 rte_errno = ENOSPC;
1369                 return NULL;
1370         }
1371         tmpl = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, sizeof(*tmpl) +
1372                            desc_n * sizeof(struct rte_mbuf *), 0, socket);
1373         if (!tmpl) {
1374                 rte_errno = ENOMEM;
1375                 return NULL;
1376         }
1377         tmpl->type = MLX5_RXQ_TYPE_STANDARD;
1378         if (mlx5_mr_btree_init(&tmpl->rxq.mr_ctrl.cache_bh,
1379                                MLX5_MR_BTREE_CACHE_N, socket)) {
1380                 /* rte_errno is already set. */
1381                 goto error;
1382         }
1383         tmpl->socket = socket;
1384         if (dev->data->dev_conf.intr_conf.rxq)
1385                 tmpl->irq = 1;
1386         mprq_stride_nums = config->mprq.stride_num_n ?
1387                 config->mprq.stride_num_n : MLX5_MPRQ_STRIDE_NUM_N;
1388         mprq_stride_size = non_scatter_min_mbuf_size <=
1389                 (1U << config->mprq.max_stride_size_n) ?
1390                 log2above(non_scatter_min_mbuf_size) : MLX5_MPRQ_STRIDE_SIZE_N;
1391         mprq_stride_cap = (config->mprq.stride_num_n ?
1392                 (1U << config->mprq.stride_num_n) : (1U << mprq_stride_nums)) *
1393                         (config->mprq.stride_size_n ?
1394                 (1U << config->mprq.stride_size_n) : (1U << mprq_stride_size));
1395         /*
1396          * This Rx queue can be configured as a Multi-Packet RQ if all of the
1397          * following conditions are met:
1398          *  - MPRQ is enabled.
1399          *  - The number of descs is more than the number of strides.
1400          *  - max_rx_pkt_len plus overhead is less than the max size
1401          *    of a stride or mprq_stride_size is specified by a user.
1402          *    Need to nake sure that there are enough stides to encap
1403          *    the maximum packet size in case mprq_stride_size is set.
1404          *  Otherwise, enable Rx scatter if necessary.
1405          */
1406         if (mprq_en && desc > (1U << mprq_stride_nums) &&
1407             (non_scatter_min_mbuf_size <=
1408              (1U << config->mprq.max_stride_size_n) ||
1409              (config->mprq.stride_size_n &&
1410               non_scatter_min_mbuf_size <= mprq_stride_cap))) {
1411                 /* TODO: Rx scatter isn't supported yet. */
1412                 tmpl->rxq.sges_n = 0;
1413                 /* Trim the number of descs needed. */
1414                 desc >>= mprq_stride_nums;
1415                 tmpl->rxq.strd_num_n = config->mprq.stride_num_n ?
1416                         config->mprq.stride_num_n : mprq_stride_nums;
1417                 tmpl->rxq.strd_sz_n = config->mprq.stride_size_n ?
1418                         config->mprq.stride_size_n : mprq_stride_size;
1419                 tmpl->rxq.strd_shift_en = MLX5_MPRQ_TWO_BYTE_SHIFT;
1420                 tmpl->rxq.strd_scatter_en =
1421                                 !!(offloads & DEV_RX_OFFLOAD_SCATTER);
1422                 tmpl->rxq.mprq_max_memcpy_len = RTE_MIN(first_mb_free_size,
1423                                 config->mprq.max_memcpy_len);
1424                 max_lro_size = RTE_MIN(max_rx_pkt_len,
1425                                        (1u << tmpl->rxq.strd_num_n) *
1426                                        (1u << tmpl->rxq.strd_sz_n));
1427                 DRV_LOG(DEBUG,
1428                         "port %u Rx queue %u: Multi-Packet RQ is enabled"
1429                         " strd_num_n = %u, strd_sz_n = %u",
1430                         dev->data->port_id, idx,
1431                         tmpl->rxq.strd_num_n, tmpl->rxq.strd_sz_n);
1432         } else if (max_rx_pkt_len <= first_mb_free_size) {
1433                 tmpl->rxq.sges_n = 0;
1434                 max_lro_size = max_rx_pkt_len;
1435         } else if (offloads & DEV_RX_OFFLOAD_SCATTER) {
1436                 unsigned int size = non_scatter_min_mbuf_size;
1437                 unsigned int sges_n;
1438
1439                 if (lro_on_queue && first_mb_free_size <
1440                     MLX5_MAX_LRO_HEADER_FIX) {
1441                         DRV_LOG(ERR, "Not enough space in the first segment(%u)"
1442                                 " to include the max header size(%u) for LRO",
1443                                 first_mb_free_size, MLX5_MAX_LRO_HEADER_FIX);
1444                         rte_errno = ENOTSUP;
1445                         goto error;
1446                 }
1447                 /*
1448                  * Determine the number of SGEs needed for a full packet
1449                  * and round it to the next power of two.
1450                  */
1451                 sges_n = log2above((size / mb_len) + !!(size % mb_len));
1452                 if (sges_n > MLX5_MAX_LOG_RQ_SEGS) {
1453                         DRV_LOG(ERR,
1454                                 "port %u too many SGEs (%u) needed to handle"
1455                                 " requested maximum packet size %u, the maximum"
1456                                 " supported are %u", dev->data->port_id,
1457                                 1 << sges_n, max_rx_pkt_len,
1458                                 1u << MLX5_MAX_LOG_RQ_SEGS);
1459                         rte_errno = ENOTSUP;
1460                         goto error;
1461                 }
1462                 tmpl->rxq.sges_n = sges_n;
1463                 max_lro_size = max_rx_pkt_len;
1464         }
1465         if (config->mprq.enabled && !mlx5_rxq_mprq_enabled(&tmpl->rxq))
1466                 DRV_LOG(WARNING,
1467                         "port %u MPRQ is requested but cannot be enabled\n"
1468                         " (requested: pkt_sz = %u, desc_num = %u,"
1469                         " rxq_num = %u, stride_sz = %u, stride_num = %u\n"
1470                         "  supported: min_rxqs_num = %u,"
1471                         " min_stride_sz = %u, max_stride_sz = %u).",
1472                         dev->data->port_id, non_scatter_min_mbuf_size,
1473                         desc, priv->rxqs_n,
1474                         config->mprq.stride_size_n ?
1475                                 (1U << config->mprq.stride_size_n) :
1476                                 (1U << mprq_stride_size),
1477                         config->mprq.stride_num_n ?
1478                                 (1U << config->mprq.stride_num_n) :
1479                                 (1U << mprq_stride_nums),
1480                         config->mprq.min_rxqs_num,
1481                         (1U << config->mprq.min_stride_size_n),
1482                         (1U << config->mprq.max_stride_size_n));
1483         DRV_LOG(DEBUG, "port %u maximum number of segments per packet: %u",
1484                 dev->data->port_id, 1 << tmpl->rxq.sges_n);
1485         if (desc % (1 << tmpl->rxq.sges_n)) {
1486                 DRV_LOG(ERR,
1487                         "port %u number of Rx queue descriptors (%u) is not a"
1488                         " multiple of SGEs per packet (%u)",
1489                         dev->data->port_id,
1490                         desc,
1491                         1 << tmpl->rxq.sges_n);
1492                 rte_errno = EINVAL;
1493                 goto error;
1494         }
1495         mlx5_max_lro_msg_size_adjust(dev, idx, max_lro_size);
1496         /* Toggle RX checksum offload if hardware supports it. */
1497         tmpl->rxq.csum = !!(offloads & DEV_RX_OFFLOAD_CHECKSUM);
1498         tmpl->rxq.hw_timestamp = !!(offloads & DEV_RX_OFFLOAD_TIMESTAMP);
1499         /* Configure VLAN stripping. */
1500         tmpl->rxq.vlan_strip = !!(offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
1501         /* By default, FCS (CRC) is stripped by hardware. */
1502         tmpl->rxq.crc_present = 0;
1503         tmpl->rxq.lro = lro_on_queue;
1504         if (offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
1505                 if (config->hw_fcs_strip) {
1506                         /*
1507                          * RQs used for LRO-enabled TIRs should not be
1508                          * configured to scatter the FCS.
1509                          */
1510                         if (lro_on_queue)
1511                                 DRV_LOG(WARNING,
1512                                         "port %u CRC stripping has been "
1513                                         "disabled but will still be performed "
1514                                         "by hardware, because LRO is enabled",
1515                                         dev->data->port_id);
1516                         else
1517                                 tmpl->rxq.crc_present = 1;
1518                 } else {
1519                         DRV_LOG(WARNING,
1520                                 "port %u CRC stripping has been disabled but will"
1521                                 " still be performed by hardware, make sure MLNX_OFED"
1522                                 " and firmware are up to date",
1523                                 dev->data->port_id);
1524                 }
1525         }
1526         DRV_LOG(DEBUG,
1527                 "port %u CRC stripping is %s, %u bytes will be subtracted from"
1528                 " incoming frames to hide it",
1529                 dev->data->port_id,
1530                 tmpl->rxq.crc_present ? "disabled" : "enabled",
1531                 tmpl->rxq.crc_present << 2);
1532         /* Save port ID. */
1533         tmpl->rxq.rss_hash = !!priv->rss_conf.rss_hf &&
1534                 (!!(dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS));
1535         tmpl->rxq.port_id = dev->data->port_id;
1536         tmpl->priv = priv;
1537         tmpl->rxq.mp = mp;
1538         tmpl->rxq.elts_n = log2above(desc);
1539         tmpl->rxq.rq_repl_thresh =
1540                 MLX5_VPMD_RXQ_RPLNSH_THRESH(1 << tmpl->rxq.elts_n);
1541         tmpl->rxq.elts =
1542                 (struct rte_mbuf *(*)[1 << tmpl->rxq.elts_n])(tmpl + 1);
1543 #ifndef RTE_ARCH_64
1544         tmpl->rxq.uar_lock_cq = &priv->sh->uar_lock_cq;
1545 #endif
1546         tmpl->rxq.idx = idx;
1547         rte_atomic32_inc(&tmpl->refcnt);
1548         LIST_INSERT_HEAD(&priv->rxqsctrl, tmpl, next);
1549         return tmpl;
1550 error:
1551         mlx5_free(tmpl);
1552         return NULL;
1553 }
1554
1555 /**
1556  * Create a DPDK Rx hairpin queue.
1557  *
1558  * @param dev
1559  *   Pointer to Ethernet device.
1560  * @param idx
1561  *   RX queue index.
1562  * @param desc
1563  *   Number of descriptors to configure in queue.
1564  * @param hairpin_conf
1565  *   The hairpin binding configuration.
1566  *
1567  * @return
1568  *   A DPDK queue object on success, NULL otherwise and rte_errno is set.
1569  */
1570 struct mlx5_rxq_ctrl *
1571 mlx5_rxq_hairpin_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1572                      const struct rte_eth_hairpin_conf *hairpin_conf)
1573 {
1574         struct mlx5_priv *priv = dev->data->dev_private;
1575         struct mlx5_rxq_ctrl *tmpl;
1576
1577         tmpl = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, sizeof(*tmpl), 0,
1578                            SOCKET_ID_ANY);
1579         if (!tmpl) {
1580                 rte_errno = ENOMEM;
1581                 return NULL;
1582         }
1583         tmpl->type = MLX5_RXQ_TYPE_HAIRPIN;
1584         tmpl->socket = SOCKET_ID_ANY;
1585         tmpl->rxq.rss_hash = 0;
1586         tmpl->rxq.port_id = dev->data->port_id;
1587         tmpl->priv = priv;
1588         tmpl->rxq.mp = NULL;
1589         tmpl->rxq.elts_n = log2above(desc);
1590         tmpl->rxq.elts = NULL;
1591         tmpl->rxq.mr_ctrl.cache_bh = (struct mlx5_mr_btree) { 0 };
1592         tmpl->hairpin_conf = *hairpin_conf;
1593         tmpl->rxq.idx = idx;
1594         rte_atomic32_inc(&tmpl->refcnt);
1595         LIST_INSERT_HEAD(&priv->rxqsctrl, tmpl, next);
1596         return tmpl;
1597 }
1598
1599 /**
1600  * Get a Rx queue.
1601  *
1602  * @param dev
1603  *   Pointer to Ethernet device.
1604  * @param idx
1605  *   RX queue index.
1606  *
1607  * @return
1608  *   A pointer to the queue if it exists, NULL otherwise.
1609  */
1610 struct mlx5_rxq_ctrl *
1611 mlx5_rxq_get(struct rte_eth_dev *dev, uint16_t idx)
1612 {
1613         struct mlx5_priv *priv = dev->data->dev_private;
1614         struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
1615         struct mlx5_rxq_ctrl *rxq_ctrl = NULL;
1616
1617         if (rxq_data) {
1618                 rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
1619                 rte_atomic32_inc(&rxq_ctrl->refcnt);
1620         }
1621         return rxq_ctrl;
1622 }
1623
1624 /**
1625  * Release a Rx queue.
1626  *
1627  * @param dev
1628  *   Pointer to Ethernet device.
1629  * @param idx
1630  *   RX queue index.
1631  *
1632  * @return
1633  *   1 while a reference on it exists, 0 when freed.
1634  */
1635 int
1636 mlx5_rxq_release(struct rte_eth_dev *dev, uint16_t idx)
1637 {
1638         struct mlx5_priv *priv = dev->data->dev_private;
1639         struct mlx5_rxq_ctrl *rxq_ctrl;
1640
1641         if (!(*priv->rxqs)[idx])
1642                 return 0;
1643         rxq_ctrl = container_of((*priv->rxqs)[idx], struct mlx5_rxq_ctrl, rxq);
1644         if (!rte_atomic32_dec_and_test(&rxq_ctrl->refcnt))
1645                 return 1;
1646         if (rxq_ctrl->obj) {
1647                 priv->obj_ops->rxq_obj_release(rxq_ctrl->obj);
1648                 LIST_REMOVE(rxq_ctrl->obj, next);
1649                 mlx5_free(rxq_ctrl->obj);
1650                 rxq_ctrl->obj = NULL;
1651         }
1652         if (rxq_ctrl->type == MLX5_RXQ_TYPE_STANDARD) {
1653                 mlx5_mr_btree_free(&rxq_ctrl->rxq.mr_ctrl.cache_bh);
1654                 rxq_free_elts(rxq_ctrl);
1655         }
1656         LIST_REMOVE(rxq_ctrl, next);
1657         mlx5_free(rxq_ctrl);
1658         (*priv->rxqs)[idx] = NULL;
1659         return 0;
1660 }
1661
1662 /**
1663  * Verify the Rx Queue list is empty
1664  *
1665  * @param dev
1666  *   Pointer to Ethernet device.
1667  *
1668  * @return
1669  *   The number of object not released.
1670  */
1671 int
1672 mlx5_rxq_verify(struct rte_eth_dev *dev)
1673 {
1674         struct mlx5_priv *priv = dev->data->dev_private;
1675         struct mlx5_rxq_ctrl *rxq_ctrl;
1676         int ret = 0;
1677
1678         LIST_FOREACH(rxq_ctrl, &priv->rxqsctrl, next) {
1679                 DRV_LOG(DEBUG, "port %u Rx Queue %u still referenced",
1680                         dev->data->port_id, rxq_ctrl->rxq.idx);
1681                 ++ret;
1682         }
1683         return ret;
1684 }
1685
1686 /**
1687  * Get a Rx queue type.
1688  *
1689  * @param dev
1690  *   Pointer to Ethernet device.
1691  * @param idx
1692  *   Rx queue index.
1693  *
1694  * @return
1695  *   The Rx queue type.
1696  */
1697 enum mlx5_rxq_type
1698 mlx5_rxq_get_type(struct rte_eth_dev *dev, uint16_t idx)
1699 {
1700         struct mlx5_priv *priv = dev->data->dev_private;
1701         struct mlx5_rxq_ctrl *rxq_ctrl = NULL;
1702
1703         if (idx < priv->rxqs_n && (*priv->rxqs)[idx]) {
1704                 rxq_ctrl = container_of((*priv->rxqs)[idx],
1705                                         struct mlx5_rxq_ctrl,
1706                                         rxq);
1707                 return rxq_ctrl->type;
1708         }
1709         return MLX5_RXQ_TYPE_UNDEFINED;
1710 }
1711
1712 /**
1713  * Create an indirection table.
1714  *
1715  * @param dev
1716  *   Pointer to Ethernet device.
1717  * @param queues
1718  *   Queues entering in the indirection table.
1719  * @param queues_n
1720  *   Number of queues in the array.
1721  *
1722  * @return
1723  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
1724  */
1725 static struct mlx5_ind_table_obj *
1726 mlx5_ind_table_obj_new(struct rte_eth_dev *dev, const uint16_t *queues,
1727                        uint32_t queues_n, enum mlx5_ind_tbl_type type)
1728 {
1729         struct mlx5_priv *priv = dev->data->dev_private;
1730         struct mlx5_ind_table_obj *ind_tbl;
1731         unsigned int i = 0, j = 0, k = 0;
1732
1733         ind_tbl = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ind_tbl) +
1734                               queues_n * sizeof(uint16_t), 0, SOCKET_ID_ANY);
1735         if (!ind_tbl) {
1736                 rte_errno = ENOMEM;
1737                 return NULL;
1738         }
1739         ind_tbl->type = type;
1740         if (ind_tbl->type == MLX5_IND_TBL_TYPE_IBV) {
1741                 const unsigned int wq_n = rte_is_power_of_2(queues_n) ?
1742                         log2above(queues_n) :
1743                         log2above(priv->config.ind_table_max_size);
1744                 struct ibv_wq *wq[1 << wq_n];
1745
1746                 for (i = 0; i != queues_n; ++i) {
1747                         struct mlx5_rxq_ctrl *rxq = mlx5_rxq_get(dev,
1748                                                                  queues[i]);
1749                         if (!rxq)
1750                                 goto error;
1751                         wq[i] = rxq->obj->wq;
1752                         ind_tbl->queues[i] = queues[i];
1753                 }
1754                 ind_tbl->queues_n = queues_n;
1755                 /* Finalise indirection table. */
1756                 k = i; /* Retain value of i for use in error case. */
1757                 for (j = 0; k != (unsigned int)(1 << wq_n); ++k, ++j)
1758                         wq[k] = wq[j];
1759                 ind_tbl->ind_table = mlx5_glue->create_rwq_ind_table
1760                         (priv->sh->ctx,
1761                          &(struct ibv_rwq_ind_table_init_attr){
1762                                 .log_ind_tbl_size = wq_n,
1763                                 .ind_tbl = wq,
1764                                 .comp_mask = 0,
1765                         });
1766                 if (!ind_tbl->ind_table) {
1767                         rte_errno = errno;
1768                         goto error;
1769                 }
1770         } else { /* ind_tbl->type == MLX5_IND_TBL_TYPE_DEVX */
1771                 struct mlx5_devx_rqt_attr *rqt_attr = NULL;
1772                 const unsigned int rqt_n =
1773                         1 << (rte_is_power_of_2(queues_n) ?
1774                               log2above(queues_n) :
1775                               log2above(priv->config.ind_table_max_size));
1776
1777                 rqt_attr = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rqt_attr) +
1778                                       rqt_n * sizeof(uint32_t), 0,
1779                                       SOCKET_ID_ANY);
1780                 if (!rqt_attr) {
1781                         DRV_LOG(ERR, "port %u cannot allocate RQT resources",
1782                                 dev->data->port_id);
1783                         rte_errno = ENOMEM;
1784                         goto error;
1785                 }
1786                 rqt_attr->rqt_max_size = priv->config.ind_table_max_size;
1787                 rqt_attr->rqt_actual_size = rqt_n;
1788                 for (i = 0; i != queues_n; ++i) {
1789                         struct mlx5_rxq_ctrl *rxq = mlx5_rxq_get(dev,
1790                                                                  queues[i]);
1791                         if (!rxq)
1792                                 goto error;
1793                         rqt_attr->rq_list[i] = rxq->obj->rq->id;
1794                         ind_tbl->queues[i] = queues[i];
1795                 }
1796                 k = i; /* Retain value of i for use in error case. */
1797                 for (j = 0; k != rqt_n; ++k, ++j)
1798                         rqt_attr->rq_list[k] = rqt_attr->rq_list[j];
1799                 ind_tbl->rqt = mlx5_devx_cmd_create_rqt(priv->sh->ctx,
1800                                                         rqt_attr);
1801                 mlx5_free(rqt_attr);
1802                 if (!ind_tbl->rqt) {
1803                         DRV_LOG(ERR, "port %u cannot create DevX RQT",
1804                                 dev->data->port_id);
1805                         rte_errno = errno;
1806                         goto error;
1807                 }
1808                 ind_tbl->queues_n = queues_n;
1809         }
1810         rte_atomic32_inc(&ind_tbl->refcnt);
1811         LIST_INSERT_HEAD(&priv->ind_tbls, ind_tbl, next);
1812         return ind_tbl;
1813 error:
1814         for (j = 0; j < i; j++)
1815                 mlx5_rxq_release(dev, ind_tbl->queues[j]);
1816         mlx5_free(ind_tbl);
1817         DEBUG("port %u cannot create indirection table", dev->data->port_id);
1818         return NULL;
1819 }
1820
1821 /**
1822  * Get an indirection table.
1823  *
1824  * @param dev
1825  *   Pointer to Ethernet device.
1826  * @param queues
1827  *   Queues entering in the indirection table.
1828  * @param queues_n
1829  *   Number of queues in the array.
1830  *
1831  * @return
1832  *   An indirection table if found.
1833  */
1834 static struct mlx5_ind_table_obj *
1835 mlx5_ind_table_obj_get(struct rte_eth_dev *dev, const uint16_t *queues,
1836                        uint32_t queues_n)
1837 {
1838         struct mlx5_priv *priv = dev->data->dev_private;
1839         struct mlx5_ind_table_obj *ind_tbl;
1840
1841         LIST_FOREACH(ind_tbl, &priv->ind_tbls, next) {
1842                 if ((ind_tbl->queues_n == queues_n) &&
1843                     (memcmp(ind_tbl->queues, queues,
1844                             ind_tbl->queues_n * sizeof(ind_tbl->queues[0]))
1845                      == 0))
1846                         break;
1847         }
1848         if (ind_tbl) {
1849                 unsigned int i;
1850
1851                 rte_atomic32_inc(&ind_tbl->refcnt);
1852                 for (i = 0; i != ind_tbl->queues_n; ++i)
1853                         mlx5_rxq_get(dev, ind_tbl->queues[i]);
1854         }
1855         return ind_tbl;
1856 }
1857
1858 /**
1859  * Release an indirection table.
1860  *
1861  * @param dev
1862  *   Pointer to Ethernet device.
1863  * @param ind_table
1864  *   Indirection table to release.
1865  *
1866  * @return
1867  *   1 while a reference on it exists, 0 when freed.
1868  */
1869 static int
1870 mlx5_ind_table_obj_release(struct rte_eth_dev *dev,
1871                            struct mlx5_ind_table_obj *ind_tbl)
1872 {
1873         unsigned int i;
1874
1875         if (rte_atomic32_dec_and_test(&ind_tbl->refcnt)) {
1876                 if (ind_tbl->type == MLX5_IND_TBL_TYPE_IBV)
1877                         claim_zero(mlx5_glue->destroy_rwq_ind_table
1878                                                         (ind_tbl->ind_table));
1879                 else if (ind_tbl->type == MLX5_IND_TBL_TYPE_DEVX)
1880                         claim_zero(mlx5_devx_cmd_destroy(ind_tbl->rqt));
1881         }
1882         for (i = 0; i != ind_tbl->queues_n; ++i)
1883                 claim_nonzero(mlx5_rxq_release(dev, ind_tbl->queues[i]));
1884         if (!rte_atomic32_read(&ind_tbl->refcnt)) {
1885                 LIST_REMOVE(ind_tbl, next);
1886                 mlx5_free(ind_tbl);
1887                 return 0;
1888         }
1889         return 1;
1890 }
1891
1892 /**
1893  * Verify the Rx Queue list is empty
1894  *
1895  * @param dev
1896  *   Pointer to Ethernet device.
1897  *
1898  * @return
1899  *   The number of object not released.
1900  */
1901 int
1902 mlx5_ind_table_obj_verify(struct rte_eth_dev *dev)
1903 {
1904         struct mlx5_priv *priv = dev->data->dev_private;
1905         struct mlx5_ind_table_obj *ind_tbl;
1906         int ret = 0;
1907
1908         LIST_FOREACH(ind_tbl, &priv->ind_tbls, next) {
1909                 DRV_LOG(DEBUG,
1910                         "port %u indirection table obj %p still referenced",
1911                         dev->data->port_id, (void *)ind_tbl);
1912                 ++ret;
1913         }
1914         return ret;
1915 }
1916
1917 /**
1918  * Create an Rx Hash queue.
1919  *
1920  * @param dev
1921  *   Pointer to Ethernet device.
1922  * @param rss_key
1923  *   RSS key for the Rx hash queue.
1924  * @param rss_key_len
1925  *   RSS key length.
1926  * @param hash_fields
1927  *   Verbs protocol hash field to make the RSS on.
1928  * @param queues
1929  *   Queues entering in hash queue. In case of empty hash_fields only the
1930  *   first queue index will be taken for the indirection table.
1931  * @param queues_n
1932  *   Number of queues.
1933  * @param tunnel
1934  *   Tunnel type.
1935  *
1936  * @return
1937  *   The Verbs/DevX object initialised index, 0 otherwise and rte_errno is set.
1938  */
1939 uint32_t
1940 mlx5_hrxq_new(struct rte_eth_dev *dev,
1941               const uint8_t *rss_key, uint32_t rss_key_len,
1942               uint64_t hash_fields,
1943               const uint16_t *queues, uint32_t queues_n,
1944               int tunnel __rte_unused)
1945 {
1946         struct mlx5_priv *priv = dev->data->dev_private;
1947         struct mlx5_hrxq *hrxq = NULL;
1948         uint32_t hrxq_idx = 0;
1949         struct ibv_qp *qp = NULL;
1950         struct mlx5_ind_table_obj *ind_tbl;
1951         int err;
1952         struct mlx5_devx_obj *tir = NULL;
1953         struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[queues[0]];
1954         struct mlx5_rxq_ctrl *rxq_ctrl =
1955                 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
1956
1957         queues_n = hash_fields ? queues_n : 1;
1958         ind_tbl = mlx5_ind_table_obj_get(dev, queues, queues_n);
1959         if (!ind_tbl) {
1960                 enum mlx5_ind_tbl_type type;
1961
1962                 type = rxq_ctrl->obj->type == MLX5_RXQ_OBJ_TYPE_IBV ?
1963                                 MLX5_IND_TBL_TYPE_IBV : MLX5_IND_TBL_TYPE_DEVX;
1964                 ind_tbl = mlx5_ind_table_obj_new(dev, queues, queues_n, type);
1965         }
1966         if (!ind_tbl) {
1967                 rte_errno = ENOMEM;
1968                 return 0;
1969         }
1970         if (ind_tbl->type == MLX5_IND_TBL_TYPE_IBV) {
1971 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
1972                 struct mlx5dv_qp_init_attr qp_init_attr;
1973
1974                 memset(&qp_init_attr, 0, sizeof(qp_init_attr));
1975                 if (tunnel) {
1976                         qp_init_attr.comp_mask =
1977                                 MLX5DV_QP_INIT_ATTR_MASK_QP_CREATE_FLAGS;
1978                         qp_init_attr.create_flags =
1979                                 MLX5DV_QP_CREATE_TUNNEL_OFFLOADS;
1980                 }
1981 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
1982                 if (dev->data->dev_conf.lpbk_mode) {
1983                         /*
1984                          * Allow packet sent from NIC loop back
1985                          * w/o source MAC check.
1986                          */
1987                         qp_init_attr.comp_mask |=
1988                                 MLX5DV_QP_INIT_ATTR_MASK_QP_CREATE_FLAGS;
1989                         qp_init_attr.create_flags |=
1990                                 MLX5DV_QP_CREATE_TIR_ALLOW_SELF_LOOPBACK_UC;
1991                 }
1992 #endif
1993                 qp = mlx5_glue->dv_create_qp
1994                         (priv->sh->ctx,
1995                          &(struct ibv_qp_init_attr_ex){
1996                                 .qp_type = IBV_QPT_RAW_PACKET,
1997                                 .comp_mask =
1998                                         IBV_QP_INIT_ATTR_PD |
1999                                         IBV_QP_INIT_ATTR_IND_TABLE |
2000                                         IBV_QP_INIT_ATTR_RX_HASH,
2001                                 .rx_hash_conf = (struct ibv_rx_hash_conf){
2002                                         .rx_hash_function =
2003                                                 IBV_RX_HASH_FUNC_TOEPLITZ,
2004                                         .rx_hash_key_len = rss_key_len,
2005                                         .rx_hash_key =
2006                                                 (void *)(uintptr_t)rss_key,
2007                                         .rx_hash_fields_mask = hash_fields,
2008                                 },
2009                                 .rwq_ind_tbl = ind_tbl->ind_table,
2010                                 .pd = priv->sh->pd,
2011                           },
2012                           &qp_init_attr);
2013 #else
2014                 qp = mlx5_glue->create_qp_ex
2015                         (priv->sh->ctx,
2016                          &(struct ibv_qp_init_attr_ex){
2017                                 .qp_type = IBV_QPT_RAW_PACKET,
2018                                 .comp_mask =
2019                                         IBV_QP_INIT_ATTR_PD |
2020                                         IBV_QP_INIT_ATTR_IND_TABLE |
2021                                         IBV_QP_INIT_ATTR_RX_HASH,
2022                                 .rx_hash_conf = (struct ibv_rx_hash_conf){
2023                                         .rx_hash_function =
2024                                                 IBV_RX_HASH_FUNC_TOEPLITZ,
2025                                         .rx_hash_key_len = rss_key_len,
2026                                         .rx_hash_key =
2027                                                 (void *)(uintptr_t)rss_key,
2028                                         .rx_hash_fields_mask = hash_fields,
2029                                 },
2030                                 .rwq_ind_tbl = ind_tbl->ind_table,
2031                                 .pd = priv->sh->pd,
2032                          });
2033 #endif
2034                 if (!qp) {
2035                         rte_errno = errno;
2036                         goto error;
2037                 }
2038         } else { /* ind_tbl->type == MLX5_IND_TBL_TYPE_DEVX */
2039                 struct mlx5_devx_tir_attr tir_attr;
2040                 uint32_t i;
2041                 uint32_t lro = 1;
2042
2043                 /* Enable TIR LRO only if all the queues were configured for. */
2044                 for (i = 0; i < queues_n; ++i) {
2045                         if (!(*priv->rxqs)[queues[i]]->lro) {
2046                                 lro = 0;
2047                                 break;
2048                         }
2049                 }
2050                 memset(&tir_attr, 0, sizeof(tir_attr));
2051                 tir_attr.disp_type = MLX5_TIRC_DISP_TYPE_INDIRECT;
2052                 tir_attr.rx_hash_fn = MLX5_RX_HASH_FN_TOEPLITZ;
2053                 tir_attr.tunneled_offload_en = !!tunnel;
2054                 /* If needed, translate hash_fields bitmap to PRM format. */
2055                 if (hash_fields) {
2056 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
2057                         struct mlx5_rx_hash_field_select *rx_hash_field_select =
2058                                         hash_fields & IBV_RX_HASH_INNER ?
2059                                         &tir_attr.rx_hash_field_selector_inner :
2060                                         &tir_attr.rx_hash_field_selector_outer;
2061 #else
2062                         struct mlx5_rx_hash_field_select *rx_hash_field_select =
2063                                         &tir_attr.rx_hash_field_selector_outer;
2064 #endif
2065
2066                         /* 1 bit: 0: IPv4, 1: IPv6. */
2067                         rx_hash_field_select->l3_prot_type =
2068                                 !!(hash_fields & MLX5_IPV6_IBV_RX_HASH);
2069                         /* 1 bit: 0: TCP, 1: UDP. */
2070                         rx_hash_field_select->l4_prot_type =
2071                                 !!(hash_fields & MLX5_UDP_IBV_RX_HASH);
2072                         /* Bitmask which sets which fields to use in RX Hash. */
2073                         rx_hash_field_select->selected_fields =
2074                         ((!!(hash_fields & MLX5_L3_SRC_IBV_RX_HASH)) <<
2075                          MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP) |
2076                         (!!(hash_fields & MLX5_L3_DST_IBV_RX_HASH)) <<
2077                          MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP |
2078                         (!!(hash_fields & MLX5_L4_SRC_IBV_RX_HASH)) <<
2079                          MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT |
2080                         (!!(hash_fields & MLX5_L4_DST_IBV_RX_HASH)) <<
2081                          MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT;
2082                 }
2083                 if (rxq_ctrl->obj->type == MLX5_RXQ_OBJ_TYPE_DEVX_HAIRPIN)
2084                         tir_attr.transport_domain = priv->sh->td->id;
2085                 else
2086                         tir_attr.transport_domain = priv->sh->tdn;
2087                 memcpy(tir_attr.rx_hash_toeplitz_key, rss_key,
2088                        MLX5_RSS_HASH_KEY_LEN);
2089                 tir_attr.indirect_table = ind_tbl->rqt->id;
2090                 if (dev->data->dev_conf.lpbk_mode)
2091                         tir_attr.self_lb_block =
2092                                         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
2093                 if (lro) {
2094                         tir_attr.lro_timeout_period_usecs =
2095                                         priv->config.lro.timeout;
2096                         tir_attr.lro_max_msg_sz = priv->max_lro_msg_size;
2097                         tir_attr.lro_enable_mask =
2098                                         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2099                                         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO;
2100                 }
2101                 tir = mlx5_devx_cmd_create_tir(priv->sh->ctx, &tir_attr);
2102                 if (!tir) {
2103                         DRV_LOG(ERR, "port %u cannot create DevX TIR",
2104                                 dev->data->port_id);
2105                         rte_errno = errno;
2106                         goto error;
2107                 }
2108         }
2109         hrxq = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_HRXQ], &hrxq_idx);
2110         if (!hrxq)
2111                 goto error;
2112         hrxq->ind_table = ind_tbl;
2113         if (ind_tbl->type == MLX5_IND_TBL_TYPE_IBV) {
2114                 hrxq->qp = qp;
2115 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2116                 hrxq->action =
2117                         mlx5_glue->dv_create_flow_action_dest_ibv_qp(hrxq->qp);
2118                 if (!hrxq->action) {
2119                         rte_errno = errno;
2120                         goto error;
2121                 }
2122 #endif
2123         } else { /* ind_tbl->type == MLX5_IND_TBL_TYPE_DEVX */
2124                 hrxq->tir = tir;
2125 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2126                 hrxq->action = mlx5_glue->dv_create_flow_action_dest_devx_tir
2127                                                         (hrxq->tir->obj);
2128                 if (!hrxq->action) {
2129                         rte_errno = errno;
2130                         goto error;
2131                 }
2132 #endif
2133         }
2134         hrxq->rss_key_len = rss_key_len;
2135         hrxq->hash_fields = hash_fields;
2136         memcpy(hrxq->rss_key, rss_key, rss_key_len);
2137         rte_atomic32_inc(&hrxq->refcnt);
2138         ILIST_INSERT(priv->sh->ipool[MLX5_IPOOL_HRXQ], &priv->hrxqs, hrxq_idx,
2139                      hrxq, next);
2140         return hrxq_idx;
2141 error:
2142         err = rte_errno; /* Save rte_errno before cleanup. */
2143         mlx5_ind_table_obj_release(dev, ind_tbl);
2144         if (qp)
2145                 claim_zero(mlx5_glue->destroy_qp(qp));
2146         else if (tir)
2147                 claim_zero(mlx5_devx_cmd_destroy(tir));
2148         if (hrxq)
2149                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_HRXQ], hrxq_idx);
2150         rte_errno = err; /* Restore rte_errno. */
2151         return 0;
2152 }
2153
2154 /**
2155  * Get an Rx Hash queue.
2156  *
2157  * @param dev
2158  *   Pointer to Ethernet device.
2159  * @param rss_conf
2160  *   RSS configuration for the Rx hash queue.
2161  * @param queues
2162  *   Queues entering in hash queue. In case of empty hash_fields only the
2163  *   first queue index will be taken for the indirection table.
2164  * @param queues_n
2165  *   Number of queues.
2166  *
2167  * @return
2168  *   An hash Rx queue index on success.
2169  */
2170 uint32_t
2171 mlx5_hrxq_get(struct rte_eth_dev *dev,
2172               const uint8_t *rss_key, uint32_t rss_key_len,
2173               uint64_t hash_fields,
2174               const uint16_t *queues, uint32_t queues_n)
2175 {
2176         struct mlx5_priv *priv = dev->data->dev_private;
2177         struct mlx5_hrxq *hrxq;
2178         uint32_t idx;
2179
2180         queues_n = hash_fields ? queues_n : 1;
2181         ILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_HRXQ], priv->hrxqs, idx,
2182                       hrxq, next) {
2183                 struct mlx5_ind_table_obj *ind_tbl;
2184
2185                 if (hrxq->rss_key_len != rss_key_len)
2186                         continue;
2187                 if (memcmp(hrxq->rss_key, rss_key, rss_key_len))
2188                         continue;
2189                 if (hrxq->hash_fields != hash_fields)
2190                         continue;
2191                 ind_tbl = mlx5_ind_table_obj_get(dev, queues, queues_n);
2192                 if (!ind_tbl)
2193                         continue;
2194                 if (ind_tbl != hrxq->ind_table) {
2195                         mlx5_ind_table_obj_release(dev, ind_tbl);
2196                         continue;
2197                 }
2198                 rte_atomic32_inc(&hrxq->refcnt);
2199                 return idx;
2200         }
2201         return 0;
2202 }
2203
2204 /**
2205  * Release the hash Rx queue.
2206  *
2207  * @param dev
2208  *   Pointer to Ethernet device.
2209  * @param hrxq
2210  *   Index to Hash Rx queue to release.
2211  *
2212  * @return
2213  *   1 while a reference on it exists, 0 when freed.
2214  */
2215 int
2216 mlx5_hrxq_release(struct rte_eth_dev *dev, uint32_t hrxq_idx)
2217 {
2218         struct mlx5_priv *priv = dev->data->dev_private;
2219         struct mlx5_hrxq *hrxq;
2220
2221         hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ], hrxq_idx);
2222         if (!hrxq)
2223                 return 0;
2224         if (rte_atomic32_dec_and_test(&hrxq->refcnt)) {
2225 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2226                 mlx5_glue->destroy_flow_action(hrxq->action);
2227 #endif
2228                 if (hrxq->ind_table->type == MLX5_IND_TBL_TYPE_IBV)
2229                         claim_zero(mlx5_glue->destroy_qp(hrxq->qp));
2230                 else /* hrxq->ind_table->type == MLX5_IND_TBL_TYPE_DEVX */
2231                         claim_zero(mlx5_devx_cmd_destroy(hrxq->tir));
2232                 mlx5_ind_table_obj_release(dev, hrxq->ind_table);
2233                 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_HRXQ], &priv->hrxqs,
2234                              hrxq_idx, hrxq, next);
2235                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_HRXQ], hrxq_idx);
2236                 return 0;
2237         }
2238         claim_nonzero(mlx5_ind_table_obj_release(dev, hrxq->ind_table));
2239         return 1;
2240 }
2241
2242 /**
2243  * Verify the Rx Queue list is empty
2244  *
2245  * @param dev
2246  *   Pointer to Ethernet device.
2247  *
2248  * @return
2249  *   The number of object not released.
2250  */
2251 int
2252 mlx5_hrxq_verify(struct rte_eth_dev *dev)
2253 {
2254         struct mlx5_priv *priv = dev->data->dev_private;
2255         struct mlx5_hrxq *hrxq;
2256         uint32_t idx;
2257         int ret = 0;
2258
2259         ILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_HRXQ], priv->hrxqs, idx,
2260                       hrxq, next) {
2261                 DRV_LOG(DEBUG,
2262                         "port %u hash Rx queue %p still referenced",
2263                         dev->data->port_id, (void *)hrxq);
2264                 ++ret;
2265         }
2266         return ret;
2267 }
2268
2269 /**
2270  * Create a drop Rx queue Verbs/DevX object.
2271  *
2272  * @param dev
2273  *   Pointer to Ethernet device.
2274  *
2275  * @return
2276  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2277  */
2278 static struct mlx5_rxq_obj *
2279 mlx5_rxq_obj_drop_new(struct rte_eth_dev *dev)
2280 {
2281         struct mlx5_priv *priv = dev->data->dev_private;
2282         struct ibv_context *ctx = priv->sh->ctx;
2283         struct ibv_cq *cq;
2284         struct ibv_wq *wq = NULL;
2285         struct mlx5_rxq_obj *rxq;
2286
2287         if (priv->drop_queue.rxq)
2288                 return priv->drop_queue.rxq;
2289         cq = mlx5_glue->create_cq(ctx, 1, NULL, NULL, 0);
2290         if (!cq) {
2291                 DEBUG("port %u cannot allocate CQ for drop queue",
2292                       dev->data->port_id);
2293                 rte_errno = errno;
2294                 goto error;
2295         }
2296         wq = mlx5_glue->create_wq(ctx,
2297                  &(struct ibv_wq_init_attr){
2298                         .wq_type = IBV_WQT_RQ,
2299                         .max_wr = 1,
2300                         .max_sge = 1,
2301                         .pd = priv->sh->pd,
2302                         .cq = cq,
2303                  });
2304         if (!wq) {
2305                 DEBUG("port %u cannot allocate WQ for drop queue",
2306                       dev->data->port_id);
2307                 rte_errno = errno;
2308                 goto error;
2309         }
2310         rxq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rxq), 0, SOCKET_ID_ANY);
2311         if (!rxq) {
2312                 DEBUG("port %u cannot allocate drop Rx queue memory",
2313                       dev->data->port_id);
2314                 rte_errno = ENOMEM;
2315                 goto error;
2316         }
2317         rxq->ibv_cq = cq;
2318         rxq->wq = wq;
2319         priv->drop_queue.rxq = rxq;
2320         return rxq;
2321 error:
2322         if (wq)
2323                 claim_zero(mlx5_glue->destroy_wq(wq));
2324         if (cq)
2325                 claim_zero(mlx5_glue->destroy_cq(cq));
2326         return NULL;
2327 }
2328
2329 /**
2330  * Release a drop Rx queue Verbs/DevX object.
2331  *
2332  * @param dev
2333  *   Pointer to Ethernet device.
2334  *
2335  * @return
2336  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2337  */
2338 static void
2339 mlx5_rxq_obj_drop_release(struct rte_eth_dev *dev)
2340 {
2341         struct mlx5_priv *priv = dev->data->dev_private;
2342         struct mlx5_rxq_obj *rxq = priv->drop_queue.rxq;
2343
2344         if (rxq->wq)
2345                 claim_zero(mlx5_glue->destroy_wq(rxq->wq));
2346         if (rxq->ibv_cq)
2347                 claim_zero(mlx5_glue->destroy_cq(rxq->ibv_cq));
2348         mlx5_free(rxq);
2349         priv->drop_queue.rxq = NULL;
2350 }
2351
2352 /**
2353  * Create a drop indirection table.
2354  *
2355  * @param dev
2356  *   Pointer to Ethernet device.
2357  *
2358  * @return
2359  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2360  */
2361 static struct mlx5_ind_table_obj *
2362 mlx5_ind_table_obj_drop_new(struct rte_eth_dev *dev)
2363 {
2364         struct mlx5_priv *priv = dev->data->dev_private;
2365         struct mlx5_ind_table_obj *ind_tbl;
2366         struct mlx5_rxq_obj *rxq;
2367         struct mlx5_ind_table_obj tmpl;
2368
2369         rxq = mlx5_rxq_obj_drop_new(dev);
2370         if (!rxq)
2371                 return NULL;
2372         tmpl.ind_table = mlx5_glue->create_rwq_ind_table
2373                 (priv->sh->ctx,
2374                  &(struct ibv_rwq_ind_table_init_attr){
2375                         .log_ind_tbl_size = 0,
2376                         .ind_tbl = (struct ibv_wq **)&rxq->wq,
2377                         .comp_mask = 0,
2378                  });
2379         if (!tmpl.ind_table) {
2380                 DEBUG("port %u cannot allocate indirection table for drop"
2381                       " queue",
2382                       dev->data->port_id);
2383                 rte_errno = errno;
2384                 goto error;
2385         }
2386         ind_tbl = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ind_tbl), 0,
2387                               SOCKET_ID_ANY);
2388         if (!ind_tbl) {
2389                 rte_errno = ENOMEM;
2390                 goto error;
2391         }
2392         ind_tbl->ind_table = tmpl.ind_table;
2393         return ind_tbl;
2394 error:
2395         mlx5_rxq_obj_drop_release(dev);
2396         return NULL;
2397 }
2398
2399 /**
2400  * Release a drop indirection table.
2401  *
2402  * @param dev
2403  *   Pointer to Ethernet device.
2404  */
2405 static void
2406 mlx5_ind_table_obj_drop_release(struct rte_eth_dev *dev)
2407 {
2408         struct mlx5_priv *priv = dev->data->dev_private;
2409         struct mlx5_ind_table_obj *ind_tbl = priv->drop_queue.hrxq->ind_table;
2410
2411         claim_zero(mlx5_glue->destroy_rwq_ind_table(ind_tbl->ind_table));
2412         mlx5_rxq_obj_drop_release(dev);
2413         mlx5_free(ind_tbl);
2414         priv->drop_queue.hrxq->ind_table = NULL;
2415 }
2416
2417 /**
2418  * Create a drop Rx Hash queue.
2419  *
2420  * @param dev
2421  *   Pointer to Ethernet device.
2422  *
2423  * @return
2424  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2425  */
2426 struct mlx5_hrxq *
2427 mlx5_hrxq_drop_new(struct rte_eth_dev *dev)
2428 {
2429         struct mlx5_priv *priv = dev->data->dev_private;
2430         struct mlx5_ind_table_obj *ind_tbl = NULL;
2431         struct ibv_qp *qp = NULL;
2432         struct mlx5_hrxq *hrxq = NULL;
2433
2434         if (priv->drop_queue.hrxq) {
2435                 rte_atomic32_inc(&priv->drop_queue.hrxq->refcnt);
2436                 return priv->drop_queue.hrxq;
2437         }
2438         hrxq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*hrxq), 0, SOCKET_ID_ANY);
2439         if (!hrxq) {
2440                 DRV_LOG(WARNING,
2441                         "port %u cannot allocate memory for drop queue",
2442                         dev->data->port_id);
2443                 rte_errno = ENOMEM;
2444                 goto error;
2445         }
2446         priv->drop_queue.hrxq = hrxq;
2447         ind_tbl = mlx5_ind_table_obj_drop_new(dev);
2448         if (!ind_tbl)
2449                 goto error;
2450         hrxq->ind_table = ind_tbl;
2451         qp = mlx5_glue->create_qp_ex(priv->sh->ctx,
2452                  &(struct ibv_qp_init_attr_ex){
2453                         .qp_type = IBV_QPT_RAW_PACKET,
2454                         .comp_mask =
2455                                 IBV_QP_INIT_ATTR_PD |
2456                                 IBV_QP_INIT_ATTR_IND_TABLE |
2457                                 IBV_QP_INIT_ATTR_RX_HASH,
2458                         .rx_hash_conf = (struct ibv_rx_hash_conf){
2459                                 .rx_hash_function =
2460                                         IBV_RX_HASH_FUNC_TOEPLITZ,
2461                                 .rx_hash_key_len = MLX5_RSS_HASH_KEY_LEN,
2462                                 .rx_hash_key = rss_hash_default_key,
2463                                 .rx_hash_fields_mask = 0,
2464                                 },
2465                         .rwq_ind_tbl = ind_tbl->ind_table,
2466                         .pd = priv->sh->pd
2467                  });
2468         if (!qp) {
2469                 DEBUG("port %u cannot allocate QP for drop queue",
2470                       dev->data->port_id);
2471                 rte_errno = errno;
2472                 goto error;
2473         }
2474         hrxq->qp = qp;
2475 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2476         hrxq->action = mlx5_glue->dv_create_flow_action_dest_ibv_qp(hrxq->qp);
2477         if (!hrxq->action) {
2478                 rte_errno = errno;
2479                 goto error;
2480         }
2481 #endif
2482         rte_atomic32_set(&hrxq->refcnt, 1);
2483         return hrxq;
2484 error:
2485 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2486         if (hrxq && hrxq->action)
2487                 mlx5_glue->destroy_flow_action(hrxq->action);
2488 #endif
2489         if (qp)
2490                 claim_zero(mlx5_glue->destroy_qp(hrxq->qp));
2491         if (ind_tbl)
2492                 mlx5_ind_table_obj_drop_release(dev);
2493         if (hrxq) {
2494                 priv->drop_queue.hrxq = NULL;
2495                 mlx5_free(hrxq);
2496         }
2497         return NULL;
2498 }
2499
2500 /**
2501  * Release a drop hash Rx queue.
2502  *
2503  * @param dev
2504  *   Pointer to Ethernet device.
2505  */
2506 void
2507 mlx5_hrxq_drop_release(struct rte_eth_dev *dev)
2508 {
2509         struct mlx5_priv *priv = dev->data->dev_private;
2510         struct mlx5_hrxq *hrxq = priv->drop_queue.hrxq;
2511
2512         if (rte_atomic32_dec_and_test(&hrxq->refcnt)) {
2513 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2514                 mlx5_glue->destroy_flow_action(hrxq->action);
2515 #endif
2516                 claim_zero(mlx5_glue->destroy_qp(hrxq->qp));
2517                 mlx5_ind_table_obj_drop_release(dev);
2518                 mlx5_free(hrxq);
2519                 priv->drop_queue.hrxq = NULL;
2520         }
2521 }
2522
2523
2524 /**
2525  * Set the Rx queue timestamp conversion parameters
2526  *
2527  * @param[in] dev
2528  *   Pointer to the Ethernet device structure.
2529  */
2530 void
2531 mlx5_rxq_timestamp_set(struct rte_eth_dev *dev)
2532 {
2533         struct mlx5_priv *priv = dev->data->dev_private;
2534         struct mlx5_dev_ctx_shared *sh = priv->sh;
2535         struct mlx5_rxq_data *data;
2536         unsigned int i;
2537
2538         for (i = 0; i != priv->rxqs_n; ++i) {
2539                 if (!(*priv->rxqs)[i])
2540                         continue;
2541                 data = (*priv->rxqs)[i];
2542                 data->sh = sh;
2543                 data->rt_timestamp = priv->config.rt_timestamp;
2544         }
2545 }