4 * Copyright 2015 6WIND S.A.
5 * Copyright 2015 Mellanox.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of 6WIND S.A. nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
42 #pragma GCC diagnostic ignored "-Wpedantic"
44 #include <infiniband/verbs.h>
45 #include <infiniband/mlx5_hw.h>
46 #include <infiniband/arch.h>
48 #pragma GCC diagnostic error "-Wpedantic"
51 /* DPDK headers don't like -pedantic. */
53 #pragma GCC diagnostic ignored "-Wpedantic"
56 #include <rte_mempool.h>
57 #include <rte_prefetch.h>
58 #include <rte_common.h>
59 #include <rte_branch_prediction.h>
60 #include <rte_ether.h>
62 #pragma GCC diagnostic error "-Wpedantic"
66 #include "mlx5_utils.h"
67 #include "mlx5_rxtx.h"
68 #include "mlx5_autoconf.h"
69 #include "mlx5_defs.h"
73 check_cqe(volatile struct mlx5_cqe *cqe,
74 unsigned int cqes_n, const uint16_t ci)
75 __attribute__((always_inline));
78 txq_complete(struct txq *txq) __attribute__((always_inline));
80 static inline uint32_t
81 txq_mp2mr(struct txq *txq, struct rte_mempool *mp)
82 __attribute__((always_inline));
85 mlx5_tx_dbrec(struct txq *txq, volatile struct mlx5_wqe *wqe)
86 __attribute__((always_inline));
88 static inline uint32_t
89 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe)
90 __attribute__((always_inline));
93 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe *cqe,
94 uint16_t cqe_cnt, uint32_t *rss_hash)
95 __attribute__((always_inline));
97 static inline uint32_t
98 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe *cqe)
99 __attribute__((always_inline));
104 * Verify or set magic value in CQE.
113 check_cqe_seen(volatile struct mlx5_cqe *cqe)
115 static const uint8_t magic[] = "seen";
116 volatile uint8_t (*buf)[sizeof(cqe->rsvd0)] = &cqe->rsvd0;
120 for (i = 0; i < sizeof(magic) && i < sizeof(*buf); ++i)
121 if (!ret || (*buf)[i] != magic[i]) {
123 (*buf)[i] = magic[i];
131 * Check whether CQE is valid.
136 * Size of completion queue.
141 * 0 on success, 1 on failure.
144 check_cqe(volatile struct mlx5_cqe *cqe,
145 unsigned int cqes_n, const uint16_t ci)
147 uint16_t idx = ci & cqes_n;
148 uint8_t op_own = cqe->op_own;
149 uint8_t op_owner = MLX5_CQE_OWNER(op_own);
150 uint8_t op_code = MLX5_CQE_OPCODE(op_own);
152 if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID)))
153 return 1; /* No CQE. */
155 if ((op_code == MLX5_CQE_RESP_ERR) ||
156 (op_code == MLX5_CQE_REQ_ERR)) {
157 volatile struct mlx5_err_cqe *err_cqe = (volatile void *)cqe;
158 uint8_t syndrome = err_cqe->syndrome;
160 if ((syndrome == MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR) ||
161 (syndrome == MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR))
163 if (!check_cqe_seen(cqe))
164 ERROR("unexpected CQE error %u (0x%02x)"
166 op_code, op_code, syndrome);
168 } else if ((op_code != MLX5_CQE_RESP_SEND) &&
169 (op_code != MLX5_CQE_REQ)) {
170 if (!check_cqe_seen(cqe))
171 ERROR("unexpected CQE opcode %u (0x%02x)",
180 * Return the address of the WQE.
183 * Pointer to TX queue structure.
185 * WQE consumer index.
190 static inline uintptr_t *
191 tx_mlx5_wqe(struct txq *txq, uint16_t ci)
193 ci &= ((1 << txq->wqe_n) - 1);
194 return (uintptr_t *)((uintptr_t)txq->wqes + ci * MLX5_WQE_SIZE);
198 * Return the size of tailroom of WQ.
201 * Pointer to TX queue structure.
203 * Pointer to tail of WQ.
209 tx_mlx5_wq_tailroom(struct txq *txq, void *addr)
212 tailroom = (uintptr_t)(txq->wqes) +
213 (1 << txq->wqe_n) * MLX5_WQE_SIZE -
219 * Copy data to tailroom of circular queue.
222 * Pointer to destination.
226 * Number of bytes to copy.
228 * Pointer to head of queue.
230 * Size of tailroom from dst.
233 * Pointer after copied data.
236 mlx5_copy_to_wq(void *dst, const void *src, size_t n,
237 void *base, size_t tailroom)
242 rte_memcpy(dst, src, tailroom);
243 rte_memcpy(base, (void *)((uintptr_t)src + tailroom),
245 ret = (uint8_t *)base + n - tailroom;
247 rte_memcpy(dst, src, n);
248 ret = (n == tailroom) ? base : (uint8_t *)dst + n;
254 * Manage TX completions.
256 * When sending a burst, mlx5_tx_burst() posts several WRs.
259 * Pointer to TX queue structure.
262 txq_complete(struct txq *txq)
264 const unsigned int elts_n = 1 << txq->elts_n;
265 const unsigned int cqe_n = 1 << txq->cqe_n;
266 const unsigned int cqe_cnt = cqe_n - 1;
267 uint16_t elts_free = txq->elts_tail;
269 uint16_t cq_ci = txq->cq_ci;
270 volatile struct mlx5_cqe *cqe = NULL;
271 volatile struct mlx5_wqe_ctrl *ctrl;
274 volatile struct mlx5_cqe *tmp;
276 tmp = &(*txq->cqes)[cq_ci & cqe_cnt];
277 if (check_cqe(tmp, cqe_n, cq_ci))
281 if (MLX5_CQE_FORMAT(cqe->op_own) == MLX5_COMPRESSED) {
282 if (!check_cqe_seen(cqe))
283 ERROR("unexpected compressed CQE, TX stopped");
286 if ((MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_RESP_ERR) ||
287 (MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_REQ_ERR)) {
288 if (!check_cqe_seen(cqe))
289 ERROR("unexpected error CQE, TX stopped");
295 if (unlikely(cqe == NULL))
297 txq->wqe_pi = ntohs(cqe->wqe_counter);
298 ctrl = (volatile struct mlx5_wqe_ctrl *)
299 tx_mlx5_wqe(txq, txq->wqe_pi);
300 elts_tail = ctrl->ctrl3;
301 assert(elts_tail < (1 << txq->wqe_n));
303 while (elts_free != elts_tail) {
304 struct rte_mbuf *elt = (*txq->elts)[elts_free];
305 unsigned int elts_free_next =
306 (elts_free + 1) & (elts_n - 1);
307 struct rte_mbuf *elt_next = (*txq->elts)[elts_free_next];
311 memset(&(*txq->elts)[elts_free],
313 sizeof((*txq->elts)[elts_free]));
315 RTE_MBUF_PREFETCH_TO_FREE(elt_next);
316 /* Only one segment needs to be freed. */
317 rte_pktmbuf_free_seg(elt);
318 elts_free = elts_free_next;
321 txq->elts_tail = elts_tail;
322 /* Update the consumer index. */
324 *txq->cq_db = htonl(cq_ci);
328 * Get Memory Pool (MP) from mbuf. If mbuf is indirect, the pool from which
329 * the cloned mbuf is allocated is returned instead.
335 * Memory pool where data is located for given mbuf.
337 static struct rte_mempool *
338 txq_mb2mp(struct rte_mbuf *buf)
340 if (unlikely(RTE_MBUF_INDIRECT(buf)))
341 return rte_mbuf_from_indirect(buf)->pool;
346 * Get Memory Region (MR) <-> Memory Pool (MP) association from txq->mp2mr[].
347 * Add MP to txq->mp2mr[] if it's not registered yet. If mp2mr[] is full,
348 * remove an entry first.
351 * Pointer to TX queue structure.
353 * Memory Pool for which a Memory Region lkey must be returned.
356 * mr->lkey on success, (uint32_t)-1 on failure.
358 static inline uint32_t
359 txq_mp2mr(struct txq *txq, struct rte_mempool *mp)
362 uint32_t lkey = (uint32_t)-1;
364 for (i = 0; (i != RTE_DIM(txq->mp2mr)); ++i) {
365 if (unlikely(txq->mp2mr[i].mp == NULL)) {
366 /* Unknown MP, add a new MR for it. */
369 if (txq->mp2mr[i].mp == mp) {
370 assert(txq->mp2mr[i].lkey != (uint32_t)-1);
371 assert(htonl(txq->mp2mr[i].mr->lkey) ==
373 lkey = txq->mp2mr[i].lkey;
377 if (unlikely(lkey == (uint32_t)-1))
378 lkey = txq_mp2mr_reg(txq, mp, i);
383 * Ring TX queue doorbell.
386 * Pointer to TX queue structure.
388 * Pointer to the last WQE posted in the NIC.
391 mlx5_tx_dbrec(struct txq *txq, volatile struct mlx5_wqe *wqe)
393 uint64_t *dst = (uint64_t *)((uintptr_t)txq->bf_reg);
394 volatile uint64_t *src = ((volatile uint64_t *)wqe);
397 *txq->qp_db = htonl(txq->wqe_ci);
398 /* Ensure ordering between DB record and BF copy. */
404 * DPDK callback to check the status of a tx descriptor.
409 * The index of the descriptor in the ring.
412 * The status of the tx descriptor.
415 mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset)
417 struct txq *txq = tx_queue;
418 const unsigned int elts_n = 1 << txq->elts_n;
419 const unsigned int elts_cnt = elts_n - 1;
423 used = (txq->elts_head - txq->elts_tail) & elts_cnt;
425 return RTE_ETH_TX_DESC_FULL;
426 return RTE_ETH_TX_DESC_DONE;
430 * DPDK callback to check the status of a rx descriptor.
435 * The index of the descriptor in the ring.
438 * The status of the tx descriptor.
441 mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset)
443 struct rxq *rxq = rx_queue;
444 struct rxq_zip *zip = &rxq->zip;
445 volatile struct mlx5_cqe *cqe;
446 const unsigned int cqe_n = (1 << rxq->cqe_n);
447 const unsigned int cqe_cnt = cqe_n - 1;
451 /* if we are processing a compressed cqe */
453 used = zip->cqe_cnt - zip->ca;
459 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
460 while (check_cqe(cqe, cqe_n, cq_ci) == 0) {
464 op_own = cqe->op_own;
465 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED)
466 n = ntohl(cqe->byte_cnt);
471 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
473 used = RTE_MIN(used, (1U << rxq->elts_n) - 1);
475 return RTE_ETH_RX_DESC_DONE;
476 return RTE_ETH_RX_DESC_AVAIL;
480 * DPDK callback for TX.
483 * Generic pointer to TX queue structure.
485 * Packets to transmit.
487 * Number of packets in array.
490 * Number of packets successfully transmitted (<= pkts_n).
493 mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
495 struct txq *txq = (struct txq *)dpdk_txq;
496 uint16_t elts_head = txq->elts_head;
497 const unsigned int elts_n = 1 << txq->elts_n;
504 volatile struct mlx5_wqe_v *wqe = NULL;
505 unsigned int segs_n = 0;
506 struct rte_mbuf *buf = NULL;
509 if (unlikely(!pkts_n))
511 /* Prefetch first packet cacheline. */
512 rte_prefetch0(*pkts);
513 /* Start processing. */
515 max = (elts_n - (elts_head - txq->elts_tail));
518 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
519 if (unlikely(!max_wqe))
522 volatile rte_v128u32_t *dseg = NULL;
527 uint16_t pkt_inline_sz = MLX5_WQE_DWORD_SIZE + 2;
528 uint16_t tso_header_sz = 0;
530 uint8_t cs_flags = 0;
532 #ifdef MLX5_PMD_SOFT_COUNTERS
533 uint32_t total_length = 0;
538 segs_n = buf->nb_segs;
540 * Make sure there is enough room to store this packet and
541 * that one ring entry remains unused.
544 if (max < segs_n + 1)
550 if (unlikely(--max_wqe == 0))
552 wqe = (volatile struct mlx5_wqe_v *)
553 tx_mlx5_wqe(txq, txq->wqe_ci);
554 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
556 rte_prefetch0(*pkts);
557 addr = rte_pktmbuf_mtod(buf, uintptr_t);
558 length = DATA_LEN(buf);
559 ehdr = (((uint8_t *)addr)[1] << 8) |
560 ((uint8_t *)addr)[0];
561 #ifdef MLX5_PMD_SOFT_COUNTERS
562 total_length = length;
564 assert(length >= MLX5_WQE_DWORD_SIZE);
565 /* Update element. */
566 (*txq->elts)[elts_head] = buf;
567 elts_head = (elts_head + 1) & (elts_n - 1);
568 /* Prefetch next buffer data. */
570 volatile void *pkt_addr;
572 pkt_addr = rte_pktmbuf_mtod(*pkts, volatile void *);
573 rte_prefetch0(pkt_addr);
575 /* Should we enable HW CKSUM offload */
577 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {
578 const uint64_t is_tunneled = buf->ol_flags &
580 PKT_TX_TUNNEL_VXLAN);
582 if (is_tunneled && txq->tunnel_en) {
583 cs_flags = MLX5_ETH_WQE_L3_INNER_CSUM |
584 MLX5_ETH_WQE_L4_INNER_CSUM;
585 if (buf->ol_flags & PKT_TX_OUTER_IP_CKSUM)
586 cs_flags |= MLX5_ETH_WQE_L3_CSUM;
588 cs_flags = MLX5_ETH_WQE_L3_CSUM |
589 MLX5_ETH_WQE_L4_CSUM;
592 raw = ((uint8_t *)(uintptr_t)wqe) + 2 * MLX5_WQE_DWORD_SIZE;
593 /* Replace the Ethernet type by the VLAN if necessary. */
594 if (buf->ol_flags & PKT_TX_VLAN_PKT) {
595 uint32_t vlan = htonl(0x81000000 | buf->vlan_tci);
596 unsigned int len = 2 * ETHER_ADDR_LEN - 2;
600 /* Copy Destination and source mac address. */
601 memcpy((uint8_t *)raw, ((uint8_t *)addr), len);
603 memcpy((uint8_t *)raw + len, &vlan, sizeof(vlan));
604 /* Copy missing two bytes to end the DSeg. */
605 memcpy((uint8_t *)raw + len + sizeof(vlan),
606 ((uint8_t *)addr) + len, 2);
610 memcpy((uint8_t *)raw, ((uint8_t *)addr) + 2,
611 MLX5_WQE_DWORD_SIZE);
612 length -= pkt_inline_sz;
613 addr += pkt_inline_sz;
616 tso = buf->ol_flags & PKT_TX_TCP_SEG;
618 uintptr_t end = (uintptr_t)
619 (((uintptr_t)txq->wqes) +
623 uint8_t vlan_sz = (buf->ol_flags &
624 PKT_TX_VLAN_PKT) ? 4 : 0;
625 const uint64_t is_tunneled =
628 PKT_TX_TUNNEL_VXLAN);
630 tso_header_sz = buf->l2_len + vlan_sz +
631 buf->l3_len + buf->l4_len;
633 if (is_tunneled && txq->tunnel_en) {
634 tso_header_sz += buf->outer_l2_len +
636 cs_flags |= MLX5_ETH_WQE_L4_INNER_CSUM;
638 cs_flags |= MLX5_ETH_WQE_L4_CSUM;
640 if (unlikely(tso_header_sz >
641 MLX5_MAX_TSO_HEADER))
643 copy_b = tso_header_sz - pkt_inline_sz;
644 /* First seg must contain all headers. */
645 assert(copy_b <= length);
646 raw += MLX5_WQE_DWORD_SIZE;
648 ((end - (uintptr_t)raw) > copy_b)) {
649 uint16_t n = (MLX5_WQE_DS(copy_b) -
652 if (unlikely(max_wqe < n))
655 rte_memcpy((void *)raw,
656 (void *)addr, copy_b);
659 pkt_inline_sz += copy_b;
661 * Another DWORD will be added
662 * in the inline part.
664 raw += MLX5_WQE_DS(copy_b) *
665 MLX5_WQE_DWORD_SIZE -
669 wqe->ctrl = (rte_v128u32_t){
670 htonl(txq->wqe_ci << 8),
671 htonl(txq->qp_num_8s | 1),
679 elts_head = (elts_head - 1) &
686 /* Inline if enough room. */
687 if (txq->inline_en || tso) {
688 uintptr_t end = (uintptr_t)
689 (((uintptr_t)txq->wqes) +
690 (1 << txq->wqe_n) * MLX5_WQE_SIZE);
691 unsigned int max_inline = txq->max_inline *
692 RTE_CACHE_LINE_SIZE -
694 uintptr_t addr_end = (addr + max_inline) &
695 ~(RTE_CACHE_LINE_SIZE - 1);
696 unsigned int copy_b = (addr_end > addr) ?
697 RTE_MIN((addr_end - addr), length) :
700 raw += MLX5_WQE_DWORD_SIZE;
701 if (copy_b && ((end - (uintptr_t)raw) > copy_b)) {
703 * One Dseg remains in the current WQE. To
704 * keep the computation positive, it is
705 * removed after the bytes to Dseg conversion.
707 uint16_t n = (MLX5_WQE_DS(copy_b) - 1 + 3) / 4;
709 if (unlikely(max_wqe < n))
714 htonl(copy_b | MLX5_INLINE_SEG);
717 MLX5_WQE_DS(tso_header_sz) *
719 rte_memcpy((void *)raw,
720 (void *)&inl, sizeof(inl));
722 pkt_inline_sz += sizeof(inl);
724 rte_memcpy((void *)raw, (void *)addr, copy_b);
727 pkt_inline_sz += copy_b;
730 * 2 DWORDs consumed by the WQE header + ETH segment +
731 * the size of the inline part of the packet.
733 ds = 2 + MLX5_WQE_DS(pkt_inline_sz - 2);
735 if (ds % (MLX5_WQE_SIZE /
736 MLX5_WQE_DWORD_SIZE) == 0) {
737 if (unlikely(--max_wqe == 0))
739 dseg = (volatile rte_v128u32_t *)
740 tx_mlx5_wqe(txq, txq->wqe_ci +
743 dseg = (volatile rte_v128u32_t *)
745 (ds * MLX5_WQE_DWORD_SIZE));
748 } else if (!segs_n) {
751 /* dseg will be advance as part of next_seg */
752 dseg = (volatile rte_v128u32_t *)
754 ((ds - 1) * MLX5_WQE_DWORD_SIZE));
759 * No inline has been done in the packet, only the
760 * Ethernet Header as been stored.
762 dseg = (volatile rte_v128u32_t *)
763 ((uintptr_t)wqe + (3 * MLX5_WQE_DWORD_SIZE));
766 /* Add the remaining packet as a simple ds. */
767 naddr = htonll(addr);
768 *dseg = (rte_v128u32_t){
770 txq_mp2mr(txq, txq_mb2mp(buf)),
783 * Spill on next WQE when the current one does not have
784 * enough room left. Size of WQE must a be a multiple
785 * of data segment size.
787 assert(!(MLX5_WQE_SIZE % MLX5_WQE_DWORD_SIZE));
788 if (!(ds % (MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE))) {
789 if (unlikely(--max_wqe == 0))
791 dseg = (volatile rte_v128u32_t *)
792 tx_mlx5_wqe(txq, txq->wqe_ci + ds / 4);
793 rte_prefetch0(tx_mlx5_wqe(txq,
794 txq->wqe_ci + ds / 4 + 1));
801 length = DATA_LEN(buf);
802 #ifdef MLX5_PMD_SOFT_COUNTERS
803 total_length += length;
805 /* Store segment information. */
806 naddr = htonll(rte_pktmbuf_mtod(buf, uintptr_t));
807 *dseg = (rte_v128u32_t){
809 txq_mp2mr(txq, txq_mb2mp(buf)),
813 (*txq->elts)[elts_head] = buf;
814 elts_head = (elts_head + 1) & (elts_n - 1);
823 /* Initialize known and common part of the WQE structure. */
825 wqe->ctrl = (rte_v128u32_t){
826 htonl((txq->wqe_ci << 8) | MLX5_OPCODE_TSO),
827 htonl(txq->qp_num_8s | ds),
831 wqe->eseg = (rte_v128u32_t){
833 cs_flags | (htons(buf->tso_segsz) << 16),
835 (ehdr << 16) | htons(tso_header_sz),
838 wqe->ctrl = (rte_v128u32_t){
839 htonl((txq->wqe_ci << 8) | MLX5_OPCODE_SEND),
840 htonl(txq->qp_num_8s | ds),
844 wqe->eseg = (rte_v128u32_t){
848 (ehdr << 16) | htons(pkt_inline_sz),
852 txq->wqe_ci += (ds + 3) / 4;
853 #ifdef MLX5_PMD_SOFT_COUNTERS
854 /* Increment sent bytes counter. */
855 txq->stats.obytes += total_length;
858 /* Take a shortcut if nothing must be sent. */
859 if (unlikely((i + k) == 0))
861 /* Check whether completion threshold has been reached. */
862 comp = txq->elts_comp + i + j + k;
863 if (comp >= MLX5_TX_COMP_THRESH) {
864 volatile struct mlx5_wqe_ctrl *w =
865 (volatile struct mlx5_wqe_ctrl *)wqe;
867 /* Request completion on last WQE. */
869 /* Save elts_head in unused "immediate" field of WQE. */
870 w->ctrl3 = elts_head;
873 txq->elts_comp = comp;
875 #ifdef MLX5_PMD_SOFT_COUNTERS
876 /* Increment sent packets counter. */
877 txq->stats.opackets += i;
879 /* Ring QP doorbell. */
880 mlx5_tx_dbrec(txq, (volatile struct mlx5_wqe *)wqe);
881 txq->elts_head = elts_head;
886 * Open a MPW session.
889 * Pointer to TX queue structure.
891 * Pointer to MPW session structure.
896 mlx5_mpw_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
898 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
899 volatile struct mlx5_wqe_data_seg (*dseg)[MLX5_MPW_DSEG_MAX] =
900 (volatile struct mlx5_wqe_data_seg (*)[])
901 tx_mlx5_wqe(txq, idx + 1);
903 mpw->state = MLX5_MPW_STATE_OPENED;
907 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
908 mpw->wqe->eseg.mss = htons(length);
909 mpw->wqe->eseg.inline_hdr_sz = 0;
910 mpw->wqe->eseg.rsvd0 = 0;
911 mpw->wqe->eseg.rsvd1 = 0;
912 mpw->wqe->eseg.rsvd2 = 0;
913 mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
914 (txq->wqe_ci << 8) | MLX5_OPCODE_TSO);
915 mpw->wqe->ctrl[2] = 0;
916 mpw->wqe->ctrl[3] = 0;
917 mpw->data.dseg[0] = (volatile struct mlx5_wqe_data_seg *)
918 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
919 mpw->data.dseg[1] = (volatile struct mlx5_wqe_data_seg *)
920 (((uintptr_t)mpw->wqe) + (3 * MLX5_WQE_DWORD_SIZE));
921 mpw->data.dseg[2] = &(*dseg)[0];
922 mpw->data.dseg[3] = &(*dseg)[1];
923 mpw->data.dseg[4] = &(*dseg)[2];
927 * Close a MPW session.
930 * Pointer to TX queue structure.
932 * Pointer to MPW session structure.
935 mlx5_mpw_close(struct txq *txq, struct mlx5_mpw *mpw)
937 unsigned int num = mpw->pkts_n;
940 * Store size in multiple of 16 bytes. Control and Ethernet segments
943 mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | (2 + num));
944 mpw->state = MLX5_MPW_STATE_CLOSED;
949 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
950 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
954 * DPDK callback for TX with MPW support.
957 * Generic pointer to TX queue structure.
959 * Packets to transmit.
961 * Number of packets in array.
964 * Number of packets successfully transmitted (<= pkts_n).
967 mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
969 struct txq *txq = (struct txq *)dpdk_txq;
970 uint16_t elts_head = txq->elts_head;
971 const unsigned int elts_n = 1 << txq->elts_n;
977 struct mlx5_mpw mpw = {
978 .state = MLX5_MPW_STATE_CLOSED,
981 if (unlikely(!pkts_n))
983 /* Prefetch first packet cacheline. */
984 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
985 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
986 /* Start processing. */
988 max = (elts_n - (elts_head - txq->elts_tail));
991 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
992 if (unlikely(!max_wqe))
995 struct rte_mbuf *buf = *(pkts++);
996 unsigned int elts_head_next;
998 unsigned int segs_n = buf->nb_segs;
999 uint32_t cs_flags = 0;
1002 * Make sure there is enough room to store this packet and
1003 * that one ring entry remains unused.
1006 if (max < segs_n + 1)
1008 /* Do not bother with large packets MPW cannot handle. */
1009 if (segs_n > MLX5_MPW_DSEG_MAX)
1013 /* Should we enable HW CKSUM offload */
1015 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
1016 cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
1017 /* Retrieve packet information. */
1018 length = PKT_LEN(buf);
1020 /* Start new session if packet differs. */
1021 if ((mpw.state == MLX5_MPW_STATE_OPENED) &&
1022 ((mpw.len != length) ||
1024 (mpw.wqe->eseg.cs_flags != cs_flags)))
1025 mlx5_mpw_close(txq, &mpw);
1026 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1028 * Multi-Packet WQE consumes at most two WQE.
1029 * mlx5_mpw_new() expects to be able to use such
1032 if (unlikely(max_wqe < 2))
1035 mlx5_mpw_new(txq, &mpw, length);
1036 mpw.wqe->eseg.cs_flags = cs_flags;
1038 /* Multi-segment packets must be alone in their MPW. */
1039 assert((segs_n == 1) || (mpw.pkts_n == 0));
1040 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1044 volatile struct mlx5_wqe_data_seg *dseg;
1047 elts_head_next = (elts_head + 1) & (elts_n - 1);
1049 (*txq->elts)[elts_head] = buf;
1050 dseg = mpw.data.dseg[mpw.pkts_n];
1051 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1052 *dseg = (struct mlx5_wqe_data_seg){
1053 .byte_count = htonl(DATA_LEN(buf)),
1054 .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
1055 .addr = htonll(addr),
1057 elts_head = elts_head_next;
1058 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1059 length += DATA_LEN(buf);
1065 assert(length == mpw.len);
1066 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1067 mlx5_mpw_close(txq, &mpw);
1068 elts_head = elts_head_next;
1069 #ifdef MLX5_PMD_SOFT_COUNTERS
1070 /* Increment sent bytes counter. */
1071 txq->stats.obytes += length;
1075 /* Take a shortcut if nothing must be sent. */
1076 if (unlikely(i == 0))
1078 /* Check whether completion threshold has been reached. */
1079 /* "j" includes both packets and segments. */
1080 comp = txq->elts_comp + j;
1081 if (comp >= MLX5_TX_COMP_THRESH) {
1082 volatile struct mlx5_wqe *wqe = mpw.wqe;
1084 /* Request completion on last WQE. */
1085 wqe->ctrl[2] = htonl(8);
1086 /* Save elts_head in unused "immediate" field of WQE. */
1087 wqe->ctrl[3] = elts_head;
1090 txq->elts_comp = comp;
1092 #ifdef MLX5_PMD_SOFT_COUNTERS
1093 /* Increment sent packets counter. */
1094 txq->stats.opackets += i;
1096 /* Ring QP doorbell. */
1097 if (mpw.state == MLX5_MPW_STATE_OPENED)
1098 mlx5_mpw_close(txq, &mpw);
1099 mlx5_tx_dbrec(txq, mpw.wqe);
1100 txq->elts_head = elts_head;
1105 * Open a MPW inline session.
1108 * Pointer to TX queue structure.
1110 * Pointer to MPW session structure.
1115 mlx5_mpw_inline_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
1117 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1118 struct mlx5_wqe_inl_small *inl;
1120 mpw->state = MLX5_MPW_INL_STATE_OPENED;
1124 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1125 mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
1126 (txq->wqe_ci << 8) |
1128 mpw->wqe->ctrl[2] = 0;
1129 mpw->wqe->ctrl[3] = 0;
1130 mpw->wqe->eseg.mss = htons(length);
1131 mpw->wqe->eseg.inline_hdr_sz = 0;
1132 mpw->wqe->eseg.cs_flags = 0;
1133 mpw->wqe->eseg.rsvd0 = 0;
1134 mpw->wqe->eseg.rsvd1 = 0;
1135 mpw->wqe->eseg.rsvd2 = 0;
1136 inl = (struct mlx5_wqe_inl_small *)
1137 (((uintptr_t)mpw->wqe) + 2 * MLX5_WQE_DWORD_SIZE);
1138 mpw->data.raw = (uint8_t *)&inl->raw;
1142 * Close a MPW inline session.
1145 * Pointer to TX queue structure.
1147 * Pointer to MPW session structure.
1150 mlx5_mpw_inline_close(struct txq *txq, struct mlx5_mpw *mpw)
1153 struct mlx5_wqe_inl_small *inl = (struct mlx5_wqe_inl_small *)
1154 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
1156 size = MLX5_WQE_SIZE - MLX5_MWQE64_INL_DATA + mpw->total_len;
1158 * Store size in multiple of 16 bytes. Control and Ethernet segments
1161 mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | MLX5_WQE_DS(size));
1162 mpw->state = MLX5_MPW_STATE_CLOSED;
1163 inl->byte_cnt = htonl(mpw->total_len | MLX5_INLINE_SEG);
1164 txq->wqe_ci += (size + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1168 * DPDK callback for TX with MPW inline support.
1171 * Generic pointer to TX queue structure.
1173 * Packets to transmit.
1175 * Number of packets in array.
1178 * Number of packets successfully transmitted (<= pkts_n).
1181 mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
1184 struct txq *txq = (struct txq *)dpdk_txq;
1185 uint16_t elts_head = txq->elts_head;
1186 const unsigned int elts_n = 1 << txq->elts_n;
1192 unsigned int inline_room = txq->max_inline * RTE_CACHE_LINE_SIZE;
1193 struct mlx5_mpw mpw = {
1194 .state = MLX5_MPW_STATE_CLOSED,
1197 * Compute the maximum number of WQE which can be consumed by inline
1200 * - 1 control segment,
1201 * - 1 Ethernet segment,
1202 * - N Dseg from the inline request.
1204 const unsigned int wqe_inl_n =
1205 ((2 * MLX5_WQE_DWORD_SIZE +
1206 txq->max_inline * RTE_CACHE_LINE_SIZE) +
1207 RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE;
1209 if (unlikely(!pkts_n))
1211 /* Prefetch first packet cacheline. */
1212 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
1213 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
1214 /* Start processing. */
1216 max = (elts_n - (elts_head - txq->elts_tail));
1220 struct rte_mbuf *buf = *(pkts++);
1221 unsigned int elts_head_next;
1224 unsigned int segs_n = buf->nb_segs;
1225 uint32_t cs_flags = 0;
1228 * Make sure there is enough room to store this packet and
1229 * that one ring entry remains unused.
1232 if (max < segs_n + 1)
1234 /* Do not bother with large packets MPW cannot handle. */
1235 if (segs_n > MLX5_MPW_DSEG_MAX)
1240 * Compute max_wqe in case less WQE were consumed in previous
1243 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1244 /* Should we enable HW CKSUM offload */
1246 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
1247 cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
1248 /* Retrieve packet information. */
1249 length = PKT_LEN(buf);
1250 /* Start new session if packet differs. */
1251 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1252 if ((mpw.len != length) ||
1254 (mpw.wqe->eseg.cs_flags != cs_flags))
1255 mlx5_mpw_close(txq, &mpw);
1256 } else if (mpw.state == MLX5_MPW_INL_STATE_OPENED) {
1257 if ((mpw.len != length) ||
1259 (length > inline_room) ||
1260 (mpw.wqe->eseg.cs_flags != cs_flags)) {
1261 mlx5_mpw_inline_close(txq, &mpw);
1263 txq->max_inline * RTE_CACHE_LINE_SIZE;
1266 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1267 if ((segs_n != 1) ||
1268 (length > inline_room)) {
1270 * Multi-Packet WQE consumes at most two WQE.
1271 * mlx5_mpw_new() expects to be able to use
1274 if (unlikely(max_wqe < 2))
1277 mlx5_mpw_new(txq, &mpw, length);
1278 mpw.wqe->eseg.cs_flags = cs_flags;
1280 if (unlikely(max_wqe < wqe_inl_n))
1282 max_wqe -= wqe_inl_n;
1283 mlx5_mpw_inline_new(txq, &mpw, length);
1284 mpw.wqe->eseg.cs_flags = cs_flags;
1287 /* Multi-segment packets must be alone in their MPW. */
1288 assert((segs_n == 1) || (mpw.pkts_n == 0));
1289 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1290 assert(inline_room ==
1291 txq->max_inline * RTE_CACHE_LINE_SIZE);
1292 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1296 volatile struct mlx5_wqe_data_seg *dseg;
1299 (elts_head + 1) & (elts_n - 1);
1301 (*txq->elts)[elts_head] = buf;
1302 dseg = mpw.data.dseg[mpw.pkts_n];
1303 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1304 *dseg = (struct mlx5_wqe_data_seg){
1305 .byte_count = htonl(DATA_LEN(buf)),
1306 .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
1307 .addr = htonll(addr),
1309 elts_head = elts_head_next;
1310 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1311 length += DATA_LEN(buf);
1317 assert(length == mpw.len);
1318 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1319 mlx5_mpw_close(txq, &mpw);
1323 assert(mpw.state == MLX5_MPW_INL_STATE_OPENED);
1324 assert(length <= inline_room);
1325 assert(length == DATA_LEN(buf));
1326 elts_head_next = (elts_head + 1) & (elts_n - 1);
1327 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1328 (*txq->elts)[elts_head] = buf;
1329 /* Maximum number of bytes before wrapping. */
1330 max = ((((uintptr_t)(txq->wqes)) +
1333 (uintptr_t)mpw.data.raw);
1335 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1338 mpw.data.raw = (volatile void *)txq->wqes;
1339 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1340 (void *)(addr + max),
1342 mpw.data.raw += length - max;
1344 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1350 (volatile void *)txq->wqes;
1352 mpw.data.raw += length;
1355 mpw.total_len += length;
1357 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX) {
1358 mlx5_mpw_inline_close(txq, &mpw);
1360 txq->max_inline * RTE_CACHE_LINE_SIZE;
1362 inline_room -= length;
1365 elts_head = elts_head_next;
1366 #ifdef MLX5_PMD_SOFT_COUNTERS
1367 /* Increment sent bytes counter. */
1368 txq->stats.obytes += length;
1372 /* Take a shortcut if nothing must be sent. */
1373 if (unlikely(i == 0))
1375 /* Check whether completion threshold has been reached. */
1376 /* "j" includes both packets and segments. */
1377 comp = txq->elts_comp + j;
1378 if (comp >= MLX5_TX_COMP_THRESH) {
1379 volatile struct mlx5_wqe *wqe = mpw.wqe;
1381 /* Request completion on last WQE. */
1382 wqe->ctrl[2] = htonl(8);
1383 /* Save elts_head in unused "immediate" field of WQE. */
1384 wqe->ctrl[3] = elts_head;
1387 txq->elts_comp = comp;
1389 #ifdef MLX5_PMD_SOFT_COUNTERS
1390 /* Increment sent packets counter. */
1391 txq->stats.opackets += i;
1393 /* Ring QP doorbell. */
1394 if (mpw.state == MLX5_MPW_INL_STATE_OPENED)
1395 mlx5_mpw_inline_close(txq, &mpw);
1396 else if (mpw.state == MLX5_MPW_STATE_OPENED)
1397 mlx5_mpw_close(txq, &mpw);
1398 mlx5_tx_dbrec(txq, mpw.wqe);
1399 txq->elts_head = elts_head;
1404 * Open an Enhanced MPW session.
1407 * Pointer to TX queue structure.
1409 * Pointer to MPW session structure.
1414 mlx5_empw_new(struct txq *txq, struct mlx5_mpw *mpw, int padding)
1416 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1418 mpw->state = MLX5_MPW_ENHANCED_STATE_OPENED;
1420 mpw->total_len = sizeof(struct mlx5_wqe);
1421 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1422 mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_ENHANCED_MPSW << 24) |
1423 (txq->wqe_ci << 8) |
1424 MLX5_OPCODE_ENHANCED_MPSW);
1425 mpw->wqe->ctrl[2] = 0;
1426 mpw->wqe->ctrl[3] = 0;
1427 memset((void *)(uintptr_t)&mpw->wqe->eseg, 0, MLX5_WQE_DWORD_SIZE);
1428 if (unlikely(padding)) {
1429 uintptr_t addr = (uintptr_t)(mpw->wqe + 1);
1431 /* Pad the first 2 DWORDs with zero-length inline header. */
1432 *(volatile uint32_t *)addr = htonl(MLX5_INLINE_SEG);
1433 *(volatile uint32_t *)(addr + MLX5_WQE_DWORD_SIZE) =
1434 htonl(MLX5_INLINE_SEG);
1435 mpw->total_len += 2 * MLX5_WQE_DWORD_SIZE;
1436 /* Start from the next WQEBB. */
1437 mpw->data.raw = (volatile void *)(tx_mlx5_wqe(txq, idx + 1));
1439 mpw->data.raw = (volatile void *)(mpw->wqe + 1);
1444 * Close an Enhanced MPW session.
1447 * Pointer to TX queue structure.
1449 * Pointer to MPW session structure.
1452 * Number of consumed WQEs.
1454 static inline uint16_t
1455 mlx5_empw_close(struct txq *txq, struct mlx5_mpw *mpw)
1459 /* Store size in multiple of 16 bytes. Control and Ethernet segments
1462 mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | MLX5_WQE_DS(mpw->total_len));
1463 mpw->state = MLX5_MPW_STATE_CLOSED;
1464 ret = (mpw->total_len + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1470 * DPDK callback for TX with Enhanced MPW support.
1473 * Generic pointer to TX queue structure.
1475 * Packets to transmit.
1477 * Number of packets in array.
1480 * Number of packets successfully transmitted (<= pkts_n).
1483 mlx5_tx_burst_empw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1485 struct txq *txq = (struct txq *)dpdk_txq;
1486 uint16_t elts_head = txq->elts_head;
1487 const unsigned int elts_n = 1 << txq->elts_n;
1490 unsigned int max_elts;
1492 unsigned int max_inline = txq->max_inline * RTE_CACHE_LINE_SIZE;
1493 unsigned int mpw_room = 0;
1494 unsigned int inl_pad = 0;
1496 struct mlx5_mpw mpw = {
1497 .state = MLX5_MPW_STATE_CLOSED,
1500 if (unlikely(!pkts_n))
1502 /* Start processing. */
1504 max_elts = (elts_n - (elts_head - txq->elts_tail));
1505 if (max_elts > elts_n)
1507 /* A CQE slot must always be available. */
1508 assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));
1509 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1510 if (unlikely(!max_wqe))
1513 struct rte_mbuf *buf = *(pkts++);
1514 unsigned int elts_head_next;
1518 unsigned int do_inline = 0; /* Whether inline is possible. */
1520 unsigned int segs_n = buf->nb_segs;
1521 uint32_t cs_flags = 0;
1524 * Make sure there is enough room to store this packet and
1525 * that one ring entry remains unused.
1528 if (max_elts - j < segs_n + 1)
1530 /* Do not bother with large packets MPW cannot handle. */
1531 if (segs_n > MLX5_MPW_DSEG_MAX)
1533 /* Should we enable HW CKSUM offload. */
1535 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
1536 cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
1537 /* Retrieve packet information. */
1538 length = PKT_LEN(buf);
1539 /* Start new session if:
1540 * - multi-segment packet
1541 * - no space left even for a dseg
1542 * - next packet can be inlined with a new WQE
1544 * It can't be MLX5_MPW_STATE_OPENED as always have a single
1547 if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED) {
1548 if ((segs_n != 1) ||
1549 (inl_pad + sizeof(struct mlx5_wqe_data_seg) >
1551 (length <= txq->inline_max_packet_sz &&
1552 inl_pad + sizeof(inl_hdr) + length >
1554 (mpw.wqe->eseg.cs_flags != cs_flags))
1555 max_wqe -= mlx5_empw_close(txq, &mpw);
1557 if (unlikely(mpw.state == MLX5_MPW_STATE_CLOSED)) {
1558 if (unlikely(segs_n != 1)) {
1559 /* Fall back to legacy MPW.
1560 * A MPW session consumes 2 WQEs at most to
1561 * include MLX5_MPW_DSEG_MAX pointers.
1563 if (unlikely(max_wqe < 2))
1565 mlx5_mpw_new(txq, &mpw, length);
1567 /* In Enhanced MPW, inline as much as the budget
1568 * is allowed. The remaining space is to be
1569 * filled with dsegs. If the title WQEBB isn't
1570 * padded, it will have 2 dsegs there.
1572 mpw_room = RTE_MIN(MLX5_WQE_SIZE_MAX,
1573 (max_inline ? max_inline :
1574 pkts_n * MLX5_WQE_DWORD_SIZE) +
1576 if (unlikely(max_wqe * MLX5_WQE_SIZE <
1579 /* Don't pad the title WQEBB to not waste WQ. */
1580 mlx5_empw_new(txq, &mpw, 0);
1581 mpw_room -= mpw.total_len;
1584 length <= txq->inline_max_packet_sz &&
1585 sizeof(inl_hdr) + length <= mpw_room &&
1588 mpw.wqe->eseg.cs_flags = cs_flags;
1590 /* Evaluate whether the next packet can be inlined.
1591 * Inlininig is possible when:
1592 * - length is less than configured value
1593 * - length fits for remaining space
1594 * - not required to fill the title WQEBB with dsegs
1597 length <= txq->inline_max_packet_sz &&
1598 inl_pad + sizeof(inl_hdr) + length <=
1600 (!txq->mpw_hdr_dseg ||
1601 mpw.total_len >= MLX5_WQE_SIZE);
1603 /* Multi-segment packets must be alone in their MPW. */
1604 assert((segs_n == 1) || (mpw.pkts_n == 0));
1605 if (unlikely(mpw.state == MLX5_MPW_STATE_OPENED)) {
1606 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1610 volatile struct mlx5_wqe_data_seg *dseg;
1613 (elts_head + 1) & (elts_n - 1);
1615 (*txq->elts)[elts_head] = buf;
1616 dseg = mpw.data.dseg[mpw.pkts_n];
1617 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1618 *dseg = (struct mlx5_wqe_data_seg){
1619 .byte_count = htonl(DATA_LEN(buf)),
1620 .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
1621 .addr = htonll(addr),
1623 elts_head = elts_head_next;
1624 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1625 length += DATA_LEN(buf);
1631 /* A multi-segmented packet takes one MPW session.
1632 * TODO: Pack more multi-segmented packets if possible.
1634 mlx5_mpw_close(txq, &mpw);
1639 } else if (do_inline) {
1640 /* Inline packet into WQE. */
1643 assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1644 assert(length == DATA_LEN(buf));
1645 inl_hdr = htonl(length | MLX5_INLINE_SEG);
1646 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1647 mpw.data.raw = (volatile void *)
1648 ((uintptr_t)mpw.data.raw + inl_pad);
1649 max = tx_mlx5_wq_tailroom(txq,
1650 (void *)(uintptr_t)mpw.data.raw);
1651 /* Copy inline header. */
1652 mpw.data.raw = (volatile void *)
1654 (void *)(uintptr_t)mpw.data.raw,
1657 (void *)(uintptr_t)txq->wqes,
1659 max = tx_mlx5_wq_tailroom(txq,
1660 (void *)(uintptr_t)mpw.data.raw);
1661 /* Copy packet data. */
1662 mpw.data.raw = (volatile void *)
1664 (void *)(uintptr_t)mpw.data.raw,
1667 (void *)(uintptr_t)txq->wqes,
1670 mpw.total_len += (inl_pad + sizeof(inl_hdr) + length);
1671 /* No need to get completion as the entire packet is
1672 * copied to WQ. Free the buf right away.
1674 elts_head_next = elts_head;
1675 rte_pktmbuf_free_seg(buf);
1676 mpw_room -= (inl_pad + sizeof(inl_hdr) + length);
1677 /* Add pad in the next packet if any. */
1678 inl_pad = (((uintptr_t)mpw.data.raw +
1679 (MLX5_WQE_DWORD_SIZE - 1)) &
1680 ~(MLX5_WQE_DWORD_SIZE - 1)) -
1681 (uintptr_t)mpw.data.raw;
1683 /* No inline. Load a dseg of packet pointer. */
1684 volatile rte_v128u32_t *dseg;
1686 assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1687 assert((inl_pad + sizeof(*dseg)) <= mpw_room);
1688 assert(length == DATA_LEN(buf));
1689 if (!tx_mlx5_wq_tailroom(txq,
1690 (void *)((uintptr_t)mpw.data.raw
1692 dseg = (volatile void *)txq->wqes;
1694 dseg = (volatile void *)
1695 ((uintptr_t)mpw.data.raw +
1697 elts_head_next = (elts_head + 1) & (elts_n - 1);
1698 (*txq->elts)[elts_head] = buf;
1699 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1700 for (n = 0; n * RTE_CACHE_LINE_SIZE < length; n++)
1701 rte_prefetch2((void *)(addr +
1702 n * RTE_CACHE_LINE_SIZE));
1703 naddr = htonll(addr);
1704 *dseg = (rte_v128u32_t) {
1706 txq_mp2mr(txq, txq_mb2mp(buf)),
1710 mpw.data.raw = (volatile void *)(dseg + 1);
1711 mpw.total_len += (inl_pad + sizeof(*dseg));
1714 mpw_room -= (inl_pad + sizeof(*dseg));
1717 elts_head = elts_head_next;
1718 #ifdef MLX5_PMD_SOFT_COUNTERS
1719 /* Increment sent bytes counter. */
1720 txq->stats.obytes += length;
1723 } while (i < pkts_n);
1724 /* Take a shortcut if nothing must be sent. */
1725 if (unlikely(i == 0))
1727 /* Check whether completion threshold has been reached. */
1728 if (txq->elts_comp + j >= MLX5_TX_COMP_THRESH ||
1729 (uint16_t)(txq->wqe_ci - txq->mpw_comp) >=
1730 (1 << txq->wqe_n) / MLX5_TX_COMP_THRESH_INLINE_DIV) {
1731 volatile struct mlx5_wqe *wqe = mpw.wqe;
1733 /* Request completion on last WQE. */
1734 wqe->ctrl[2] = htonl(8);
1735 /* Save elts_head in unused "immediate" field of WQE. */
1736 wqe->ctrl[3] = elts_head;
1738 txq->mpw_comp = txq->wqe_ci;
1741 txq->elts_comp += j;
1743 #ifdef MLX5_PMD_SOFT_COUNTERS
1744 /* Increment sent packets counter. */
1745 txq->stats.opackets += i;
1747 if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED)
1748 mlx5_empw_close(txq, &mpw);
1749 else if (mpw.state == MLX5_MPW_STATE_OPENED)
1750 mlx5_mpw_close(txq, &mpw);
1751 /* Ring QP doorbell. */
1752 mlx5_tx_dbrec(txq, mpw.wqe);
1753 txq->elts_head = elts_head;
1758 * Translate RX completion flags to packet type.
1763 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
1766 * Packet type for struct rte_mbuf.
1768 static inline uint32_t
1769 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe)
1772 uint16_t flags = ntohs(cqe->hdr_type_etc);
1774 if (cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) {
1777 MLX5_CQE_RX_IPV4_PACKET,
1778 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN) |
1780 MLX5_CQE_RX_IPV6_PACKET,
1781 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN);
1782 pkt_type |= ((cqe->pkt_info & MLX5_CQE_RX_OUTER_PACKET) ?
1783 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN :
1784 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN);
1788 MLX5_CQE_L3_HDR_TYPE_IPV6,
1789 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN) |
1791 MLX5_CQE_L3_HDR_TYPE_IPV4,
1792 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN);
1798 * Get size of the next packet for a given CQE. For compressed CQEs, the
1799 * consumer index is updated only once all packets of the current one have
1803 * Pointer to RX queue.
1806 * @param[out] rss_hash
1807 * Packet RSS Hash result.
1810 * Packet size in bytes (0 if there is none), -1 in case of completion
1814 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe *cqe,
1815 uint16_t cqe_cnt, uint32_t *rss_hash)
1817 struct rxq_zip *zip = &rxq->zip;
1818 uint16_t cqe_n = cqe_cnt + 1;
1822 /* Process compressed data in the CQE and mini arrays. */
1824 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1825 (volatile struct mlx5_mini_cqe8 (*)[8])
1826 (uintptr_t)(&(*rxq->cqes)[zip->ca & cqe_cnt]);
1828 len = ntohl((*mc)[zip->ai & 7].byte_cnt);
1829 *rss_hash = ntohl((*mc)[zip->ai & 7].rx_hash_result);
1830 if ((++zip->ai & 7) == 0) {
1831 /* Invalidate consumed CQEs */
1834 while (idx != end) {
1835 (*rxq->cqes)[idx & cqe_cnt].op_own =
1836 MLX5_CQE_INVALIDATE;
1840 * Increment consumer index to skip the number of
1841 * CQEs consumed. Hardware leaves holes in the CQ
1842 * ring for software use.
1847 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1848 /* Invalidate the rest */
1852 while (idx != end) {
1853 (*rxq->cqes)[idx & cqe_cnt].op_own =
1854 MLX5_CQE_INVALIDATE;
1857 rxq->cq_ci = zip->cq_ci;
1860 /* No compressed data, get next CQE and verify if it is compressed. */
1865 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1866 if (unlikely(ret == 1))
1869 op_own = cqe->op_own;
1870 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1871 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1872 (volatile struct mlx5_mini_cqe8 (*)[8])
1873 (uintptr_t)(&(*rxq->cqes)[rxq->cq_ci &
1876 /* Fix endianness. */
1877 zip->cqe_cnt = ntohl(cqe->byte_cnt);
1879 * Current mini array position is the one returned by
1882 * If completion comprises several mini arrays, as a
1883 * special case the second one is located 7 CQEs after
1884 * the initial CQE instead of 8 for subsequent ones.
1886 zip->ca = rxq->cq_ci;
1887 zip->na = zip->ca + 7;
1888 /* Compute the next non compressed CQE. */
1890 zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1891 /* Get packet size to return. */
1892 len = ntohl((*mc)[0].byte_cnt);
1893 *rss_hash = ntohl((*mc)[0].rx_hash_result);
1895 /* Prefetch all the entries to be invalidated */
1898 while (idx != end) {
1899 rte_prefetch0(&(*rxq->cqes)[(idx) & cqe_cnt]);
1903 len = ntohl(cqe->byte_cnt);
1904 *rss_hash = ntohl(cqe->rx_hash_res);
1906 /* Error while receiving packet. */
1907 if (unlikely(MLX5_CQE_OPCODE(op_own) == MLX5_CQE_RESP_ERR))
1914 * Translate RX completion flags to offload flags.
1917 * Pointer to RX queue structure.
1922 * Offload flags (ol_flags) for struct rte_mbuf.
1924 static inline uint32_t
1925 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe *cqe)
1927 uint32_t ol_flags = 0;
1928 uint16_t flags = ntohs(cqe->hdr_type_etc);
1932 MLX5_CQE_RX_L3_HDR_VALID,
1933 PKT_RX_IP_CKSUM_GOOD) |
1935 MLX5_CQE_RX_L4_HDR_VALID,
1936 PKT_RX_L4_CKSUM_GOOD);
1937 if ((cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) && (rxq->csum_l2tun))
1940 MLX5_CQE_RX_L3_HDR_VALID,
1941 PKT_RX_IP_CKSUM_GOOD) |
1943 MLX5_CQE_RX_L4_HDR_VALID,
1944 PKT_RX_L4_CKSUM_GOOD);
1949 * DPDK callback for RX.
1952 * Generic pointer to RX queue structure.
1954 * Array to store received packets.
1956 * Maximum number of packets in array.
1959 * Number of packets successfully received (<= pkts_n).
1962 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1964 struct rxq *rxq = dpdk_rxq;
1965 const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1966 const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1967 const unsigned int sges_n = rxq->sges_n;
1968 struct rte_mbuf *pkt = NULL;
1969 struct rte_mbuf *seg = NULL;
1970 volatile struct mlx5_cqe *cqe =
1971 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1973 unsigned int rq_ci = rxq->rq_ci << sges_n;
1974 int len; /* keep its value across iterations. */
1977 unsigned int idx = rq_ci & wqe_cnt;
1978 volatile struct mlx5_wqe_data_seg *wqe = &(*rxq->wqes)[idx];
1979 struct rte_mbuf *rep = (*rxq->elts)[idx];
1980 uint32_t rss_hash_res = 0;
1988 rep = rte_mbuf_raw_alloc(rxq->mp);
1989 if (unlikely(rep == NULL)) {
1990 ++rxq->stats.rx_nombuf;
1993 * no buffers before we even started,
1994 * bail out silently.
1998 while (pkt != seg) {
1999 assert(pkt != (*rxq->elts)[idx]);
2001 rte_mbuf_refcnt_set(pkt, 0);
2002 __rte_mbuf_raw_free(pkt);
2008 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
2009 len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt,
2012 rte_mbuf_refcnt_set(rep, 0);
2013 __rte_mbuf_raw_free(rep);
2016 if (unlikely(len == -1)) {
2017 /* RX error, packet is likely too large. */
2018 rte_mbuf_refcnt_set(rep, 0);
2019 __rte_mbuf_raw_free(rep);
2020 ++rxq->stats.idropped;
2024 assert(len >= (rxq->crc_present << 2));
2025 /* Update packet information. */
2026 pkt->packet_type = 0;
2028 if (rss_hash_res && rxq->rss_hash) {
2029 pkt->hash.rss = rss_hash_res;
2030 pkt->ol_flags = PKT_RX_RSS_HASH;
2032 if (rxq->mark && (cqe->sop_drop_qpn !=
2033 htonl(MLX5_FLOW_MARK_INVALID))) {
2034 pkt->ol_flags |= PKT_RX_FDIR;
2035 if (cqe->sop_drop_qpn !=
2036 htonl(MLX5_FLOW_MARK_DEFAULT)) {
2037 uint32_t mark = cqe->sop_drop_qpn;
2039 pkt->ol_flags |= PKT_RX_FDIR_ID;
2041 mlx5_flow_mark_get(mark);
2044 if (rxq->csum | rxq->csum_l2tun | rxq->vlan_strip |
2048 rxq_cq_to_pkt_type(cqe);
2050 rxq_cq_to_ol_flags(rxq, cqe);
2052 if (ntohs(cqe->hdr_type_etc) &
2053 MLX5_CQE_VLAN_STRIPPED) {
2054 pkt->ol_flags |= PKT_RX_VLAN_PKT |
2055 PKT_RX_VLAN_STRIPPED;
2056 pkt->vlan_tci = ntohs(cqe->vlan_info);
2058 if (rxq->crc_present)
2059 len -= ETHER_CRC_LEN;
2063 DATA_LEN(rep) = DATA_LEN(seg);
2064 PKT_LEN(rep) = PKT_LEN(seg);
2065 SET_DATA_OFF(rep, DATA_OFF(seg));
2066 NB_SEGS(rep) = NB_SEGS(seg);
2067 PORT(rep) = PORT(seg);
2069 (*rxq->elts)[idx] = rep;
2071 * Fill NIC descriptor with the new buffer. The lkey and size
2072 * of the buffers are already known, only the buffer address
2075 wqe->addr = htonll(rte_pktmbuf_mtod(rep, uintptr_t));
2076 if (len > DATA_LEN(seg)) {
2077 len -= DATA_LEN(seg);
2082 DATA_LEN(seg) = len;
2083 #ifdef MLX5_PMD_SOFT_COUNTERS
2084 /* Increment bytes counter. */
2085 rxq->stats.ibytes += PKT_LEN(pkt);
2087 /* Return packet. */
2093 /* Align consumer index to the next stride. */
2098 if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
2100 /* Update the consumer index. */
2101 rxq->rq_ci = rq_ci >> sges_n;
2103 *rxq->cq_db = htonl(rxq->cq_ci);
2105 *rxq->rq_db = htonl(rxq->rq_ci);
2106 #ifdef MLX5_PMD_SOFT_COUNTERS
2107 /* Increment packets counter. */
2108 rxq->stats.ipackets += i;
2114 * Dummy DPDK callback for TX.
2116 * This function is used to temporarily replace the real callback during
2117 * unsafe control operations on the queue, or in case of error.
2120 * Generic pointer to TX queue structure.
2122 * Packets to transmit.
2124 * Number of packets in array.
2127 * Number of packets successfully transmitted (<= pkts_n).
2130 removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
2139 * Dummy DPDK callback for RX.
2141 * This function is used to temporarily replace the real callback during
2142 * unsafe control operations on the queue, or in case of error.
2145 * Generic pointer to RX queue structure.
2147 * Array to store received packets.
2149 * Maximum number of packets in array.
2152 * Number of packets successfully received (<= pkts_n).
2155 removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
2164 * DPDK callback for rx queue interrupt enable.
2167 * Pointer to Ethernet device structure.
2168 * @param rx_queue_id
2172 * 0 on success, negative on failure.
2175 mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2177 #ifdef HAVE_UPDATE_CQ_CI
2178 struct priv *priv = mlx5_get_priv(dev);
2179 struct rxq *rxq = (*priv->rxqs)[rx_queue_id];
2180 struct rxq_ctrl *rxq_ctrl = container_of(rxq, struct rxq_ctrl, rxq);
2181 struct ibv_cq *cq = rxq_ctrl->cq;
2182 uint16_t ci = rxq->cq_ci;
2185 ibv_mlx5_exp_update_cq_ci(cq, ci);
2186 ret = ibv_req_notify_cq(cq, 0);
2193 WARN("unable to arm interrupt on rx queue %d", rx_queue_id);
2198 * DPDK callback for rx queue interrupt disable.
2201 * Pointer to Ethernet device structure.
2202 * @param rx_queue_id
2206 * 0 on success, negative on failure.
2209 mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2211 #ifdef HAVE_UPDATE_CQ_CI
2212 struct priv *priv = mlx5_get_priv(dev);
2213 struct rxq *rxq = (*priv->rxqs)[rx_queue_id];
2214 struct rxq_ctrl *rxq_ctrl = container_of(rxq, struct rxq_ctrl, rxq);
2215 struct ibv_cq *cq = rxq_ctrl->cq;
2216 struct ibv_cq *ev_cq;
2220 ret = ibv_get_cq_event(cq->channel, &ev_cq, &ev_ctx);
2221 if (ret || ev_cq != cq)
2224 ibv_ack_cq_events(cq, 1);
2231 WARN("unable to disable interrupt on rx queue %d",