4 * Copyright 2015 6WIND S.A.
5 * Copyright 2015 Mellanox.
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8 * modification, are permitted provided that the following conditions
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40 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
42 #pragma GCC diagnostic ignored "-Wpedantic"
44 #include <infiniband/verbs.h>
45 #include <infiniband/mlx5_hw.h>
46 #include <infiniband/arch.h>
48 #pragma GCC diagnostic error "-Wpedantic"
51 /* DPDK headers don't like -pedantic. */
53 #pragma GCC diagnostic ignored "-Wpedantic"
56 #include <rte_mempool.h>
57 #include <rte_prefetch.h>
58 #include <rte_common.h>
59 #include <rte_branch_prediction.h>
60 #include <rte_ether.h>
62 #pragma GCC diagnostic error "-Wpedantic"
66 #include "mlx5_utils.h"
67 #include "mlx5_rxtx.h"
68 #include "mlx5_autoconf.h"
69 #include "mlx5_defs.h"
75 * Verify or set magic value in CQE.
84 check_cqe64_seen(volatile struct mlx5_cqe64 *cqe)
86 static const uint8_t magic[] = "seen";
87 volatile uint8_t (*buf)[sizeof(cqe->rsvd40)] = &cqe->rsvd40;
91 for (i = 0; i < sizeof(magic) && i < sizeof(*buf); ++i)
92 if (!ret || (*buf)[i] != magic[i]) {
102 check_cqe64(volatile struct mlx5_cqe64 *cqe,
103 unsigned int cqes_n, const uint16_t ci)
104 __attribute__((always_inline));
107 * Check whether CQE is valid.
112 * Size of completion queue.
117 * 0 on success, 1 on failure.
120 check_cqe64(volatile struct mlx5_cqe64 *cqe,
121 unsigned int cqes_n, const uint16_t ci)
123 uint16_t idx = ci & cqes_n;
124 uint8_t op_own = cqe->op_own;
125 uint8_t op_owner = MLX5_CQE_OWNER(op_own);
126 uint8_t op_code = MLX5_CQE_OPCODE(op_own);
128 if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID)))
129 return 1; /* No CQE. */
131 if ((op_code == MLX5_CQE_RESP_ERR) ||
132 (op_code == MLX5_CQE_REQ_ERR)) {
133 volatile struct mlx5_err_cqe *err_cqe = (volatile void *)cqe;
134 uint8_t syndrome = err_cqe->syndrome;
136 if ((syndrome == MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR) ||
137 (syndrome == MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR))
139 if (!check_cqe64_seen(cqe))
140 ERROR("unexpected CQE error %u (0x%02x)"
142 op_code, op_code, syndrome);
144 } else if ((op_code != MLX5_CQE_RESP_SEND) &&
145 (op_code != MLX5_CQE_REQ)) {
146 if (!check_cqe64_seen(cqe))
147 ERROR("unexpected CQE opcode %u (0x%02x)",
156 txq_complete(struct txq *txq) __attribute__((always_inline));
159 * Manage TX completions.
161 * When sending a burst, mlx5_tx_burst() posts several WRs.
164 * Pointer to TX queue structure.
167 txq_complete(struct txq *txq)
169 const unsigned int elts_n = 1 << txq->elts_n;
170 const unsigned int cqe_n = 1 << txq->cqe_n;
171 const unsigned int cqe_cnt = cqe_n - 1;
172 uint16_t elts_free = txq->elts_tail;
174 uint16_t cq_ci = txq->cq_ci;
175 volatile struct mlx5_cqe64 *cqe = NULL;
176 volatile struct mlx5_wqe *wqe;
179 volatile struct mlx5_cqe64 *tmp;
181 tmp = &(*txq->cqes)[cq_ci & cqe_cnt].cqe64;
182 if (check_cqe64(tmp, cqe_n, cq_ci))
186 if (MLX5_CQE_FORMAT(cqe->op_own) == MLX5_COMPRESSED) {
187 if (!check_cqe64_seen(cqe))
188 ERROR("unexpected compressed CQE, TX stopped");
191 if ((MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_RESP_ERR) ||
192 (MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_REQ_ERR)) {
193 if (!check_cqe64_seen(cqe))
194 ERROR("unexpected error CQE, TX stopped");
200 if (unlikely(cqe == NULL))
202 wqe = &(*txq->wqes)[htons(cqe->wqe_counter) &
203 ((1 << txq->wqe_n) - 1)].hdr;
204 elts_tail = wqe->ctrl[3];
205 assert(elts_tail < (1 << txq->wqe_n));
207 while (elts_free != elts_tail) {
208 struct rte_mbuf *elt = (*txq->elts)[elts_free];
209 unsigned int elts_free_next =
210 (elts_free + 1) & (elts_n - 1);
211 struct rte_mbuf *elt_next = (*txq->elts)[elts_free_next];
215 memset(&(*txq->elts)[elts_free],
217 sizeof((*txq->elts)[elts_free]));
219 RTE_MBUF_PREFETCH_TO_FREE(elt_next);
220 /* Only one segment needs to be freed. */
221 rte_pktmbuf_free_seg(elt);
222 elts_free = elts_free_next;
225 txq->elts_tail = elts_tail;
226 /* Update the consumer index. */
228 *txq->cq_db = htonl(cq_ci);
232 * Get Memory Pool (MP) from mbuf. If mbuf is indirect, the pool from which
233 * the cloned mbuf is allocated is returned instead.
239 * Memory pool where data is located for given mbuf.
241 static struct rte_mempool *
242 txq_mb2mp(struct rte_mbuf *buf)
244 if (unlikely(RTE_MBUF_INDIRECT(buf)))
245 return rte_mbuf_from_indirect(buf)->pool;
249 static inline uint32_t
250 txq_mp2mr(struct txq *txq, struct rte_mempool *mp)
251 __attribute__((always_inline));
254 * Get Memory Region (MR) <-> Memory Pool (MP) association from txq->mp2mr[].
255 * Add MP to txq->mp2mr[] if it's not registered yet. If mp2mr[] is full,
256 * remove an entry first.
259 * Pointer to TX queue structure.
261 * Memory Pool for which a Memory Region lkey must be returned.
264 * mr->lkey on success, (uint32_t)-1 on failure.
266 static inline uint32_t
267 txq_mp2mr(struct txq *txq, struct rte_mempool *mp)
270 uint32_t lkey = (uint32_t)-1;
272 for (i = 0; (i != RTE_DIM(txq->mp2mr)); ++i) {
273 if (unlikely(txq->mp2mr[i].mp == NULL)) {
274 /* Unknown MP, add a new MR for it. */
277 if (txq->mp2mr[i].mp == mp) {
278 assert(txq->mp2mr[i].lkey != (uint32_t)-1);
279 assert(htonl(txq->mp2mr[i].mr->lkey) ==
281 lkey = txq->mp2mr[i].lkey;
285 if (unlikely(lkey == (uint32_t)-1))
286 lkey = txq_mp2mr_reg(txq, mp, i);
291 * Write a regular WQE.
294 * Pointer to TX queue structure.
296 * Pointer to the WQE to fill.
303 * Number of DS elements consumed.
305 static inline unsigned int
306 mlx5_wqe_write(struct txq *txq, volatile struct mlx5_wqe *wqe,
307 struct rte_mbuf *buf, uint32_t length)
309 uint8_t *raw = (uint8_t *)(uintptr_t)&wqe->eseg.inline_hdr[0];
311 uint16_t pkt_inline_sz = MLX5_WQE_DWORD_SIZE;
312 uintptr_t addr = rte_pktmbuf_mtod(buf, uintptr_t);
313 struct mlx5_wqe_data_seg *dseg = NULL;
315 assert(length >= MLX5_WQE_DWORD_SIZE);
316 /* Start the know and common part of the WQE structure. */
317 wqe->ctrl[0] = htonl((txq->wqe_ci << 8) | MLX5_OPCODE_SEND);
324 /* Start by copying the Ethernet Header. */
325 rte_mov16((uint8_t *)raw, (uint8_t *)addr);
326 length -= MLX5_WQE_DWORD_SIZE;
327 addr += MLX5_WQE_DWORD_SIZE;
328 /* Replace the Ethernet type by the VLAN if necessary. */
329 if (buf->ol_flags & PKT_TX_VLAN_PKT) {
330 uint32_t vlan = htonl(0x81000000 | buf->vlan_tci);
332 memcpy((uint8_t *)(raw + MLX5_WQE_DWORD_SIZE - sizeof(vlan)),
333 &vlan, sizeof(vlan));
334 addr -= sizeof(vlan);
335 length += sizeof(vlan);
337 /* Inline if enough room. */
338 if (txq->max_inline != 0) {
339 uintptr_t end = (uintptr_t)&(*txq->wqes)[1 << txq->wqe_n];
340 uint16_t max_inline = txq->max_inline * RTE_CACHE_LINE_SIZE;
343 raw += MLX5_WQE_DWORD_SIZE;
344 room = end - (uintptr_t)raw;
345 if (room > max_inline) {
346 uintptr_t addr_end = (addr + max_inline) &
347 ~(RTE_CACHE_LINE_SIZE - 1);
348 uint16_t copy_b = ((addr_end - addr) > length) ?
352 rte_memcpy((void *)raw, (void *)addr, copy_b);
355 pkt_inline_sz += copy_b;
357 assert(addr <= addr_end);
359 /* Store the inlined packet size in the WQE. */
360 wqe->eseg.inline_hdr_sz = htons(pkt_inline_sz);
362 * 2 DWORDs consumed by the WQE header + 1 DSEG +
363 * the size of the inline part of the packet.
365 ds = 2 + MLX5_WQE_DS(pkt_inline_sz - 2);
367 dseg = (struct mlx5_wqe_data_seg *)
368 ((uintptr_t)wqe + (ds * MLX5_WQE_DWORD_SIZE));
369 if ((uintptr_t)dseg >= end)
370 dseg = (struct mlx5_wqe_data_seg *)
371 ((uintptr_t)&(*txq->wqes)[0]);
375 /* Add the remaining packet as a simple ds. */
378 * No inline has been done in the packet, only the Ethernet
379 * Header as been stored.
381 wqe->eseg.inline_hdr_sz = htons(MLX5_WQE_DWORD_SIZE);
382 dseg = (struct mlx5_wqe_data_seg *)
383 ((uintptr_t)wqe + (ds * MLX5_WQE_DWORD_SIZE));
385 *dseg = (struct mlx5_wqe_data_seg) {
386 .addr = htonll(addr),
387 .byte_count = htonl(length),
388 .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
392 wqe->ctrl[1] = htonl(txq->qp_num_8s | ds);
397 * Ring TX queue doorbell.
400 * Pointer to TX queue structure.
403 mlx5_tx_dbrec(struct txq *txq)
405 uint8_t *dst = (uint8_t *)((uintptr_t)txq->bf_reg + txq->bf_offset);
407 htonl((txq->wqe_ci << 8) | MLX5_OPCODE_SEND),
408 htonl(txq->qp_num_8s),
413 *txq->qp_db = htonl(txq->wqe_ci);
414 /* Ensure ordering between DB record and BF copy. */
416 rte_mov16(dst, (uint8_t *)data);
417 txq->bf_offset ^= (1 << txq->bf_buf_size);
424 * Pointer to TX queue structure.
426 * CQE consumer index.
429 tx_prefetch_cqe(struct txq *txq, uint16_t ci)
431 volatile struct mlx5_cqe *cqe;
433 cqe = &(*txq->cqes)[ci & ((1 << txq->cqe_n) - 1)];
441 * Pointer to TX queue structure.
443 * WQE consumer index.
446 tx_prefetch_wqe(struct txq *txq, uint16_t ci)
448 volatile struct mlx5_wqe64 *wqe;
450 wqe = &(*txq->wqes)[ci & ((1 << txq->wqe_n) - 1)];
455 * DPDK callback for TX.
458 * Generic pointer to TX queue structure.
460 * Packets to transmit.
462 * Number of packets in array.
465 * Number of packets successfully transmitted (<= pkts_n).
468 mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
470 struct txq *txq = (struct txq *)dpdk_txq;
471 uint16_t elts_head = txq->elts_head;
472 const unsigned int elts_n = 1 << txq->elts_n;
477 volatile struct mlx5_wqe *wqe = NULL;
479 if (unlikely(!pkts_n))
481 /* Prefetch first packet cacheline. */
482 tx_prefetch_cqe(txq, txq->cq_ci);
483 tx_prefetch_cqe(txq, txq->cq_ci + 1);
484 rte_prefetch0(*pkts);
485 /* Start processing. */
487 max = (elts_n - (elts_head - txq->elts_tail));
491 struct rte_mbuf *buf = *(pkts++);
492 unsigned int elts_head_next;
494 unsigned int segs_n = buf->nb_segs;
495 volatile struct mlx5_wqe_data_seg *dseg;
499 * Make sure there is enough room to store this packet and
500 * that one ring entry remains unused.
503 if (max < segs_n + 1)
507 elts_head_next = (elts_head + 1) & (elts_n - 1);
508 wqe = &(*txq->wqes)[txq->wqe_ci & ((1 << txq->wqe_n) - 1)].hdr;
509 tx_prefetch_wqe(txq, txq->wqe_ci);
510 tx_prefetch_wqe(txq, txq->wqe_ci + 1);
512 rte_prefetch0(*pkts);
513 length = DATA_LEN(buf);
514 /* Update element. */
515 (*txq->elts)[elts_head] = buf;
516 /* Prefetch next buffer data. */
518 rte_prefetch0(rte_pktmbuf_mtod(*pkts,
520 /* Should we enable HW CKSUM offload */
522 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {
524 MLX5_ETH_WQE_L3_CSUM |
525 MLX5_ETH_WQE_L4_CSUM;
527 wqe->eseg.cs_flags = 0;
529 ds = mlx5_wqe_write(txq, wqe, buf, length);
532 dseg = (volatile struct mlx5_wqe_data_seg *)
533 (((uintptr_t)wqe) + ds * MLX5_WQE_DWORD_SIZE);
536 * Spill on next WQE when the current one does not have
537 * enough room left. Size of WQE must a be a multiple
538 * of data segment size.
540 assert(!(MLX5_WQE_SIZE % MLX5_WQE_DWORD_SIZE));
541 if (!(ds % (MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE)))
542 dseg = (volatile void *)
543 &(*txq->wqes)[txq->wqe_ci++ &
544 ((1 << txq->wqe_n) - 1)];
550 /* Store segment information. */
551 dseg->byte_count = htonl(DATA_LEN(buf));
552 dseg->lkey = txq_mp2mr(txq, txq_mb2mp(buf));
553 dseg->addr = htonll(rte_pktmbuf_mtod(buf, uintptr_t));
554 (*txq->elts)[elts_head_next] = buf;
555 elts_head_next = (elts_head_next + 1) & (elts_n - 1);
556 #ifdef MLX5_PMD_SOFT_COUNTERS
557 length += DATA_LEN(buf);
561 /* Update DS field in WQE. */
562 wqe->ctrl[1] &= htonl(0xffffffc0);
563 wqe->ctrl[1] |= htonl(ds & 0x3f);
565 #ifdef MLX5_PMD_SOFT_COUNTERS
566 /* Increment sent bytes counter. */
567 txq->stats.obytes += length;
569 /* Increment consumer index. */
570 txq->wqe_ci += (ds + 3) / 4;
571 elts_head = elts_head_next;
574 /* Take a shortcut if nothing must be sent. */
575 if (unlikely(i == 0))
577 /* Check whether completion threshold has been reached. */
578 comp = txq->elts_comp + i + j;
579 if (comp >= MLX5_TX_COMP_THRESH) {
580 /* Request completion on last WQE. */
581 wqe->ctrl[2] = htonl(8);
582 /* Save elts_head in unused "immediate" field of WQE. */
583 wqe->ctrl[3] = elts_head;
586 txq->elts_comp = comp;
588 #ifdef MLX5_PMD_SOFT_COUNTERS
589 /* Increment sent packets counter. */
590 txq->stats.opackets += i;
592 /* Ring QP doorbell. */
594 txq->elts_head = elts_head;
599 * Open a MPW session.
602 * Pointer to TX queue structure.
604 * Pointer to MPW session structure.
609 mlx5_mpw_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
611 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
612 volatile struct mlx5_wqe_data_seg (*dseg)[MLX5_MPW_DSEG_MAX] =
613 (volatile struct mlx5_wqe_data_seg (*)[])
614 (uintptr_t)&(*txq->wqes)[(idx + 1) & ((1 << txq->wqe_n) - 1)];
616 mpw->state = MLX5_MPW_STATE_OPENED;
620 mpw->wqe = (volatile struct mlx5_wqe *)&(*txq->wqes)[idx].hdr;
621 mpw->wqe->eseg.mss = htons(length);
622 mpw->wqe->eseg.inline_hdr_sz = 0;
623 mpw->wqe->eseg.rsvd0 = 0;
624 mpw->wqe->eseg.rsvd1 = 0;
625 mpw->wqe->eseg.rsvd2 = 0;
626 mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
627 (txq->wqe_ci << 8) | MLX5_OPCODE_LSO_MPW);
628 mpw->wqe->ctrl[2] = 0;
629 mpw->wqe->ctrl[3] = 0;
630 mpw->data.dseg[0] = (volatile struct mlx5_wqe_data_seg *)
631 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
632 mpw->data.dseg[1] = (volatile struct mlx5_wqe_data_seg *)
633 (((uintptr_t)mpw->wqe) + (3 * MLX5_WQE_DWORD_SIZE));
634 mpw->data.dseg[2] = &(*dseg)[0];
635 mpw->data.dseg[3] = &(*dseg)[1];
636 mpw->data.dseg[4] = &(*dseg)[2];
640 * Close a MPW session.
643 * Pointer to TX queue structure.
645 * Pointer to MPW session structure.
648 mlx5_mpw_close(struct txq *txq, struct mlx5_mpw *mpw)
650 unsigned int num = mpw->pkts_n;
653 * Store size in multiple of 16 bytes. Control and Ethernet segments
656 mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | (2 + num));
657 mpw->state = MLX5_MPW_STATE_CLOSED;
662 tx_prefetch_wqe(txq, txq->wqe_ci);
663 tx_prefetch_wqe(txq, txq->wqe_ci + 1);
667 * DPDK callback for TX with MPW support.
670 * Generic pointer to TX queue structure.
672 * Packets to transmit.
674 * Number of packets in array.
677 * Number of packets successfully transmitted (<= pkts_n).
680 mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
682 struct txq *txq = (struct txq *)dpdk_txq;
683 uint16_t elts_head = txq->elts_head;
684 const unsigned int elts_n = 1 << txq->elts_n;
689 struct mlx5_mpw mpw = {
690 .state = MLX5_MPW_STATE_CLOSED,
693 if (unlikely(!pkts_n))
695 /* Prefetch first packet cacheline. */
696 tx_prefetch_cqe(txq, txq->cq_ci);
697 tx_prefetch_wqe(txq, txq->wqe_ci);
698 tx_prefetch_wqe(txq, txq->wqe_ci + 1);
699 /* Start processing. */
701 max = (elts_n - (elts_head - txq->elts_tail));
705 struct rte_mbuf *buf = *(pkts++);
706 unsigned int elts_head_next;
708 unsigned int segs_n = buf->nb_segs;
709 uint32_t cs_flags = 0;
712 * Make sure there is enough room to store this packet and
713 * that one ring entry remains unused.
716 if (max < segs_n + 1)
718 /* Do not bother with large packets MPW cannot handle. */
719 if (segs_n > MLX5_MPW_DSEG_MAX)
723 /* Should we enable HW CKSUM offload */
725 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
726 cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
727 /* Retrieve packet information. */
728 length = PKT_LEN(buf);
730 /* Start new session if packet differs. */
731 if ((mpw.state == MLX5_MPW_STATE_OPENED) &&
732 ((mpw.len != length) ||
734 (mpw.wqe->eseg.cs_flags != cs_flags)))
735 mlx5_mpw_close(txq, &mpw);
736 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
737 mlx5_mpw_new(txq, &mpw, length);
738 mpw.wqe->eseg.cs_flags = cs_flags;
740 /* Multi-segment packets must be alone in their MPW. */
741 assert((segs_n == 1) || (mpw.pkts_n == 0));
742 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
746 volatile struct mlx5_wqe_data_seg *dseg;
749 elts_head_next = (elts_head + 1) & (elts_n - 1);
751 (*txq->elts)[elts_head] = buf;
752 dseg = mpw.data.dseg[mpw.pkts_n];
753 addr = rte_pktmbuf_mtod(buf, uintptr_t);
754 *dseg = (struct mlx5_wqe_data_seg){
755 .byte_count = htonl(DATA_LEN(buf)),
756 .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
757 .addr = htonll(addr),
759 elts_head = elts_head_next;
760 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
761 length += DATA_LEN(buf);
767 assert(length == mpw.len);
768 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
769 mlx5_mpw_close(txq, &mpw);
770 elts_head = elts_head_next;
771 #ifdef MLX5_PMD_SOFT_COUNTERS
772 /* Increment sent bytes counter. */
773 txq->stats.obytes += length;
777 /* Take a shortcut if nothing must be sent. */
778 if (unlikely(i == 0))
780 /* Check whether completion threshold has been reached. */
781 /* "j" includes both packets and segments. */
782 comp = txq->elts_comp + j;
783 if (comp >= MLX5_TX_COMP_THRESH) {
784 volatile struct mlx5_wqe *wqe = mpw.wqe;
786 /* Request completion on last WQE. */
787 wqe->ctrl[2] = htonl(8);
788 /* Save elts_head in unused "immediate" field of WQE. */
789 wqe->ctrl[3] = elts_head;
792 txq->elts_comp = comp;
794 #ifdef MLX5_PMD_SOFT_COUNTERS
795 /* Increment sent packets counter. */
796 txq->stats.opackets += i;
798 /* Ring QP doorbell. */
799 if (mpw.state == MLX5_MPW_STATE_OPENED)
800 mlx5_mpw_close(txq, &mpw);
802 txq->elts_head = elts_head;
807 * Open a MPW inline session.
810 * Pointer to TX queue structure.
812 * Pointer to MPW session structure.
817 mlx5_mpw_inline_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
819 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
820 struct mlx5_wqe_inl_small *inl;
822 mpw->state = MLX5_MPW_INL_STATE_OPENED;
826 mpw->wqe = (volatile struct mlx5_wqe *)&(*txq->wqes)[idx].hdr;
827 mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
829 MLX5_OPCODE_LSO_MPW);
830 mpw->wqe->ctrl[2] = 0;
831 mpw->wqe->ctrl[3] = 0;
832 mpw->wqe->eseg.mss = htons(length);
833 mpw->wqe->eseg.inline_hdr_sz = 0;
834 mpw->wqe->eseg.cs_flags = 0;
835 mpw->wqe->eseg.rsvd0 = 0;
836 mpw->wqe->eseg.rsvd1 = 0;
837 mpw->wqe->eseg.rsvd2 = 0;
838 inl = (struct mlx5_wqe_inl_small *)
839 (((uintptr_t)mpw->wqe) + 2 * MLX5_WQE_DWORD_SIZE);
840 mpw->data.raw = (uint8_t *)&inl->raw;
844 * Close a MPW inline session.
847 * Pointer to TX queue structure.
849 * Pointer to MPW session structure.
852 mlx5_mpw_inline_close(struct txq *txq, struct mlx5_mpw *mpw)
855 struct mlx5_wqe_inl_small *inl = (struct mlx5_wqe_inl_small *)
856 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
858 size = MLX5_WQE_SIZE - MLX5_MWQE64_INL_DATA + mpw->total_len;
860 * Store size in multiple of 16 bytes. Control and Ethernet segments
863 mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | MLX5_WQE_DS(size));
864 mpw->state = MLX5_MPW_STATE_CLOSED;
865 inl->byte_cnt = htonl(mpw->total_len | MLX5_INLINE_SEG);
866 txq->wqe_ci += (size + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
870 * DPDK callback for TX with MPW inline support.
873 * Generic pointer to TX queue structure.
875 * Packets to transmit.
877 * Number of packets in array.
880 * Number of packets successfully transmitted (<= pkts_n).
883 mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
886 struct txq *txq = (struct txq *)dpdk_txq;
887 uint16_t elts_head = txq->elts_head;
888 const unsigned int elts_n = 1 << txq->elts_n;
893 unsigned int inline_room = txq->max_inline * RTE_CACHE_LINE_SIZE;
894 struct mlx5_mpw mpw = {
895 .state = MLX5_MPW_STATE_CLOSED,
898 if (unlikely(!pkts_n))
900 /* Prefetch first packet cacheline. */
901 tx_prefetch_cqe(txq, txq->cq_ci);
902 tx_prefetch_wqe(txq, txq->wqe_ci);
903 tx_prefetch_wqe(txq, txq->wqe_ci + 1);
904 /* Start processing. */
906 max = (elts_n - (elts_head - txq->elts_tail));
910 struct rte_mbuf *buf = *(pkts++);
911 unsigned int elts_head_next;
914 unsigned int segs_n = buf->nb_segs;
915 uint32_t cs_flags = 0;
918 * Make sure there is enough room to store this packet and
919 * that one ring entry remains unused.
922 if (max < segs_n + 1)
924 /* Do not bother with large packets MPW cannot handle. */
925 if (segs_n > MLX5_MPW_DSEG_MAX)
929 /* Should we enable HW CKSUM offload */
931 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
932 cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
933 /* Retrieve packet information. */
934 length = PKT_LEN(buf);
935 /* Start new session if packet differs. */
936 if (mpw.state == MLX5_MPW_STATE_OPENED) {
937 if ((mpw.len != length) ||
939 (mpw.wqe->eseg.cs_flags != cs_flags))
940 mlx5_mpw_close(txq, &mpw);
941 } else if (mpw.state == MLX5_MPW_INL_STATE_OPENED) {
942 if ((mpw.len != length) ||
944 (length > inline_room) ||
945 (mpw.wqe->eseg.cs_flags != cs_flags)) {
946 mlx5_mpw_inline_close(txq, &mpw);
948 txq->max_inline * RTE_CACHE_LINE_SIZE;
951 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
953 (length > inline_room)) {
954 mlx5_mpw_new(txq, &mpw, length);
955 mpw.wqe->eseg.cs_flags = cs_flags;
957 mlx5_mpw_inline_new(txq, &mpw, length);
958 mpw.wqe->eseg.cs_flags = cs_flags;
961 /* Multi-segment packets must be alone in their MPW. */
962 assert((segs_n == 1) || (mpw.pkts_n == 0));
963 if (mpw.state == MLX5_MPW_STATE_OPENED) {
964 assert(inline_room ==
965 txq->max_inline * RTE_CACHE_LINE_SIZE);
966 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
970 volatile struct mlx5_wqe_data_seg *dseg;
973 (elts_head + 1) & (elts_n - 1);
975 (*txq->elts)[elts_head] = buf;
976 dseg = mpw.data.dseg[mpw.pkts_n];
977 addr = rte_pktmbuf_mtod(buf, uintptr_t);
978 *dseg = (struct mlx5_wqe_data_seg){
979 .byte_count = htonl(DATA_LEN(buf)),
980 .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
981 .addr = htonll(addr),
983 elts_head = elts_head_next;
984 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
985 length += DATA_LEN(buf);
991 assert(length == mpw.len);
992 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
993 mlx5_mpw_close(txq, &mpw);
997 assert(mpw.state == MLX5_MPW_INL_STATE_OPENED);
998 assert(length <= inline_room);
999 assert(length == DATA_LEN(buf));
1000 elts_head_next = (elts_head + 1) & (elts_n - 1);
1001 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1002 (*txq->elts)[elts_head] = buf;
1003 /* Maximum number of bytes before wrapping. */
1004 max = ((uintptr_t)&(*txq->wqes)[1 << txq->wqe_n] -
1005 (uintptr_t)mpw.data.raw);
1007 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1011 (volatile void *)&(*txq->wqes)[0];
1012 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1013 (void *)(addr + max),
1015 mpw.data.raw += length - max;
1017 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1020 mpw.data.raw += length;
1022 if ((uintptr_t)mpw.data.raw ==
1023 (uintptr_t)&(*txq->wqes)[1 << txq->wqe_n])
1025 (volatile void *)&(*txq->wqes)[0];
1028 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX) {
1029 mlx5_mpw_inline_close(txq, &mpw);
1031 txq->max_inline * RTE_CACHE_LINE_SIZE;
1033 inline_room -= length;
1036 mpw.total_len += length;
1037 elts_head = elts_head_next;
1038 #ifdef MLX5_PMD_SOFT_COUNTERS
1039 /* Increment sent bytes counter. */
1040 txq->stats.obytes += length;
1044 /* Take a shortcut if nothing must be sent. */
1045 if (unlikely(i == 0))
1047 /* Check whether completion threshold has been reached. */
1048 /* "j" includes both packets and segments. */
1049 comp = txq->elts_comp + j;
1050 if (comp >= MLX5_TX_COMP_THRESH) {
1051 volatile struct mlx5_wqe *wqe = mpw.wqe;
1053 /* Request completion on last WQE. */
1054 wqe->ctrl[2] = htonl(8);
1055 /* Save elts_head in unused "immediate" field of WQE. */
1056 wqe->ctrl[3] = elts_head;
1059 txq->elts_comp = comp;
1061 #ifdef MLX5_PMD_SOFT_COUNTERS
1062 /* Increment sent packets counter. */
1063 txq->stats.opackets += i;
1065 /* Ring QP doorbell. */
1066 if (mpw.state == MLX5_MPW_INL_STATE_OPENED)
1067 mlx5_mpw_inline_close(txq, &mpw);
1068 else if (mpw.state == MLX5_MPW_STATE_OPENED)
1069 mlx5_mpw_close(txq, &mpw);
1071 txq->elts_head = elts_head;
1076 * Translate RX completion flags to packet type.
1081 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
1084 * Packet type for struct rte_mbuf.
1086 static inline uint32_t
1087 rxq_cq_to_pkt_type(volatile struct mlx5_cqe64 *cqe)
1090 uint8_t flags = cqe->l4_hdr_type_etc;
1091 uint8_t info = cqe->rsvd0[0];
1093 if (info & IBV_EXP_CQ_RX_TUNNEL_PACKET)
1096 IBV_EXP_CQ_RX_OUTER_IPV4_PACKET,
1097 RTE_PTYPE_L3_IPV4) |
1099 IBV_EXP_CQ_RX_OUTER_IPV6_PACKET,
1100 RTE_PTYPE_L3_IPV6) |
1102 IBV_EXP_CQ_RX_IPV4_PACKET,
1103 RTE_PTYPE_INNER_L3_IPV4) |
1105 IBV_EXP_CQ_RX_IPV6_PACKET,
1106 RTE_PTYPE_INNER_L3_IPV6);
1110 MLX5_CQE_L3_HDR_TYPE_IPV6,
1111 RTE_PTYPE_L3_IPV6) |
1113 MLX5_CQE_L3_HDR_TYPE_IPV4,
1119 * Get size of the next packet for a given CQE. For compressed CQEs, the
1120 * consumer index is updated only once all packets of the current one have
1124 * Pointer to RX queue.
1129 * Packet size in bytes (0 if there is none), -1 in case of completion
1133 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe64 *cqe,
1136 struct rxq_zip *zip = &rxq->zip;
1137 uint16_t cqe_n = cqe_cnt + 1;
1140 /* Process compressed data in the CQE and mini arrays. */
1142 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1143 (volatile struct mlx5_mini_cqe8 (*)[8])
1144 (uintptr_t)(&(*rxq->cqes)[zip->ca & cqe_cnt].cqe64);
1146 len = ntohl((*mc)[zip->ai & 7].byte_cnt);
1147 if ((++zip->ai & 7) == 0) {
1149 * Increment consumer index to skip the number of
1150 * CQEs consumed. Hardware leaves holes in the CQ
1151 * ring for software use.
1156 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1157 uint16_t idx = rxq->cq_ci;
1158 uint16_t end = zip->cq_ci;
1160 while (idx != end) {
1161 (*rxq->cqes)[idx & cqe_cnt].cqe64.op_own =
1162 MLX5_CQE_INVALIDATE;
1165 rxq->cq_ci = zip->cq_ci;
1168 /* No compressed data, get next CQE and verify if it is compressed. */
1173 ret = check_cqe64(cqe, cqe_n, rxq->cq_ci);
1174 if (unlikely(ret == 1))
1177 op_own = cqe->op_own;
1178 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1179 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1180 (volatile struct mlx5_mini_cqe8 (*)[8])
1181 (uintptr_t)(&(*rxq->cqes)[rxq->cq_ci &
1184 /* Fix endianness. */
1185 zip->cqe_cnt = ntohl(cqe->byte_cnt);
1187 * Current mini array position is the one returned by
1190 * If completion comprises several mini arrays, as a
1191 * special case the second one is located 7 CQEs after
1192 * the initial CQE instead of 8 for subsequent ones.
1194 zip->ca = rxq->cq_ci & cqe_cnt;
1195 zip->na = zip->ca + 7;
1196 /* Compute the next non compressed CQE. */
1198 zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1199 /* Get packet size to return. */
1200 len = ntohl((*mc)[0].byte_cnt);
1203 len = ntohl(cqe->byte_cnt);
1205 /* Error while receiving packet. */
1206 if (unlikely(MLX5_CQE_OPCODE(op_own) == MLX5_CQE_RESP_ERR))
1213 * Translate RX completion flags to offload flags.
1216 * Pointer to RX queue structure.
1221 * Offload flags (ol_flags) for struct rte_mbuf.
1223 static inline uint32_t
1224 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe64 *cqe)
1226 uint32_t ol_flags = 0;
1227 uint8_t l3_hdr = (cqe->l4_hdr_type_etc) & MLX5_CQE_L3_HDR_TYPE_MASK;
1228 uint8_t l4_hdr = (cqe->l4_hdr_type_etc) & MLX5_CQE_L4_HDR_TYPE_MASK;
1229 uint8_t info = cqe->rsvd0[0];
1231 if ((l3_hdr == MLX5_CQE_L3_HDR_TYPE_IPV4) ||
1232 (l3_hdr == MLX5_CQE_L3_HDR_TYPE_IPV6))
1234 (!(cqe->hds_ip_ext & MLX5_CQE_L3_OK) *
1235 PKT_RX_IP_CKSUM_BAD);
1236 if ((l4_hdr == MLX5_CQE_L4_HDR_TYPE_TCP) ||
1237 (l4_hdr == MLX5_CQE_L4_HDR_TYPE_TCP_EMP_ACK) ||
1238 (l4_hdr == MLX5_CQE_L4_HDR_TYPE_TCP_ACK) ||
1239 (l4_hdr == MLX5_CQE_L4_HDR_TYPE_UDP))
1241 (!(cqe->hds_ip_ext & MLX5_CQE_L4_OK) *
1242 PKT_RX_L4_CKSUM_BAD);
1244 * PKT_RX_IP_CKSUM_BAD and PKT_RX_L4_CKSUM_BAD are used in place
1245 * of PKT_RX_EIP_CKSUM_BAD because the latter is not functional
1248 if ((info & IBV_EXP_CQ_RX_TUNNEL_PACKET) && (rxq->csum_l2tun))
1250 TRANSPOSE(~cqe->l4_hdr_type_etc,
1251 IBV_EXP_CQ_RX_OUTER_IP_CSUM_OK,
1252 PKT_RX_IP_CKSUM_BAD) |
1253 TRANSPOSE(~cqe->l4_hdr_type_etc,
1254 IBV_EXP_CQ_RX_OUTER_TCP_UDP_CSUM_OK,
1255 PKT_RX_L4_CKSUM_BAD);
1260 * DPDK callback for RX.
1263 * Generic pointer to RX queue structure.
1265 * Array to store received packets.
1267 * Maximum number of packets in array.
1270 * Number of packets successfully received (<= pkts_n).
1273 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1275 struct rxq *rxq = dpdk_rxq;
1276 const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1277 const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1278 const unsigned int sges_n = rxq->sges_n;
1279 struct rte_mbuf *pkt = NULL;
1280 struct rte_mbuf *seg = NULL;
1281 volatile struct mlx5_cqe64 *cqe =
1282 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt].cqe64;
1284 unsigned int rq_ci = rxq->rq_ci << sges_n;
1288 unsigned int idx = rq_ci & wqe_cnt;
1289 volatile struct mlx5_wqe_data_seg *wqe = &(*rxq->wqes)[idx];
1290 struct rte_mbuf *rep = (*rxq->elts)[idx];
1298 rep = rte_mbuf_raw_alloc(rxq->mp);
1299 if (unlikely(rep == NULL)) {
1300 ++rxq->stats.rx_nombuf;
1303 * no buffers before we even started,
1304 * bail out silently.
1308 while (pkt != seg) {
1309 assert(pkt != (*rxq->elts)[idx]);
1311 rte_mbuf_refcnt_set(pkt, 0);
1312 __rte_mbuf_raw_free(pkt);
1318 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt].cqe64;
1319 len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt);
1321 rte_mbuf_refcnt_set(rep, 0);
1322 __rte_mbuf_raw_free(rep);
1325 if (unlikely(len == -1)) {
1326 /* RX error, packet is likely too large. */
1327 rte_mbuf_refcnt_set(rep, 0);
1328 __rte_mbuf_raw_free(rep);
1329 ++rxq->stats.idropped;
1333 assert(len >= (rxq->crc_present << 2));
1334 /* Update packet information. */
1335 pkt->packet_type = 0;
1337 if (rxq->csum | rxq->csum_l2tun | rxq->vlan_strip |
1341 rxq_cq_to_pkt_type(cqe);
1343 rxq_cq_to_ol_flags(rxq, cqe);
1345 if (cqe->l4_hdr_type_etc &
1346 MLX5_CQE_VLAN_STRIPPED) {
1347 pkt->ol_flags |= PKT_RX_VLAN_PKT |
1348 PKT_RX_VLAN_STRIPPED;
1349 pkt->vlan_tci = ntohs(cqe->vlan_info);
1351 if (rxq->crc_present)
1352 len -= ETHER_CRC_LEN;
1356 DATA_LEN(rep) = DATA_LEN(seg);
1357 PKT_LEN(rep) = PKT_LEN(seg);
1358 SET_DATA_OFF(rep, DATA_OFF(seg));
1359 NB_SEGS(rep) = NB_SEGS(seg);
1360 PORT(rep) = PORT(seg);
1362 (*rxq->elts)[idx] = rep;
1364 * Fill NIC descriptor with the new buffer. The lkey and size
1365 * of the buffers are already known, only the buffer address
1368 wqe->addr = htonll(rte_pktmbuf_mtod(rep, uintptr_t));
1369 if (len > DATA_LEN(seg)) {
1370 len -= DATA_LEN(seg);
1375 DATA_LEN(seg) = len;
1376 #ifdef MLX5_PMD_SOFT_COUNTERS
1377 /* Increment bytes counter. */
1378 rxq->stats.ibytes += PKT_LEN(pkt);
1380 /* Return packet. */
1386 /* Align consumer index to the next stride. */
1391 if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
1393 /* Update the consumer index. */
1394 rxq->rq_ci = rq_ci >> sges_n;
1396 *rxq->cq_db = htonl(rxq->cq_ci);
1398 *rxq->rq_db = htonl(rxq->rq_ci);
1399 #ifdef MLX5_PMD_SOFT_COUNTERS
1400 /* Increment packets counter. */
1401 rxq->stats.ipackets += i;
1407 * Dummy DPDK callback for TX.
1409 * This function is used to temporarily replace the real callback during
1410 * unsafe control operations on the queue, or in case of error.
1413 * Generic pointer to TX queue structure.
1415 * Packets to transmit.
1417 * Number of packets in array.
1420 * Number of packets successfully transmitted (<= pkts_n).
1423 removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1432 * Dummy DPDK callback for RX.
1434 * This function is used to temporarily replace the real callback during
1435 * unsafe control operations on the queue, or in case of error.
1438 * Generic pointer to RX queue structure.
1440 * Array to store received packets.
1442 * Maximum number of packets in array.
1445 * Number of packets successfully received (<= pkts_n).
1448 removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)