drivers/net/mlx5/mlx5_rxtx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <assert.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <stdlib.h>
  10
  11 /* Verbs header. */
  12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  13 #ifdef PEDANTIC
  14 #pragma GCC diagnostic ignored "-Wpedantic"
  15 #endif
  16 #include <infiniband/verbs.h>
  17 #include <infiniband/mlx5dv.h>
  18 #ifdef PEDANTIC
  19 #pragma GCC diagnostic error "-Wpedantic"
  20 #endif
  21
  22 #include <rte_mbuf.h>
  23 #include <rte_mempool.h>
  24 #include <rte_prefetch.h>
  25 #include <rte_common.h>
  26 #include <rte_branch_prediction.h>
  27 #include <rte_ether.h>
  28
  29 #include "mlx5.h"
  30 #include "mlx5_utils.h"
  31 #include "mlx5_rxtx.h"
  32 #include "mlx5_autoconf.h"
  33 #include "mlx5_defs.h"
  34 #include "mlx5_prm.h"
  35
  36 static __rte_always_inline uint32_t
  37 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe);
  38
  39 static __rte_always_inline int
  40 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
  41                  uint16_t cqe_cnt, uint32_t *rss_hash);
  42
  43 static __rte_always_inline uint32_t
  44 rxq_cq_to_ol_flags(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe);
  45
  46 uint32_t mlx5_ptype_table[] __rte_cache_aligned = {
  47         [0xff] = RTE_PTYPE_ALL_MASK, /* Last entry for errored packet. */
  48 };
  49
  50 uint8_t mlx5_cksum_table[1 << 10] __rte_cache_aligned;
  51 uint8_t mlx5_swp_types_table[1 << 10] __rte_cache_aligned;
  52
  53 /**
  54  * Build a table to translate Rx completion flags to packet type.
  55  *
  56  * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
  57  */
  58 void
  59 mlx5_set_ptype_table(void)
  60 {
  61         unsigned int i;
  62         uint32_t (*p)[RTE_DIM(mlx5_ptype_table)] = &mlx5_ptype_table;
  63
  64         /* Last entry must not be overwritten, reserved for errored packet. */
  65         for (i = 0; i < RTE_DIM(mlx5_ptype_table) - 1; ++i)
  66                 (*p)[i] = RTE_PTYPE_UNKNOWN;
  67         /*
  68          * The index to the array should have:
  69          * bit[1:0] = l3_hdr_type
  70          * bit[4:2] = l4_hdr_type
  71          * bit[5] = ip_frag
  72          * bit[6] = tunneled
  73          * bit[7] = outer_l3_type
  74          */
  75         /* L2 */
  76         (*p)[0x00] = RTE_PTYPE_L2_ETHER;
  77         /* L3 */
  78         (*p)[0x01] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
  79                      RTE_PTYPE_L4_NONFRAG;
  80         (*p)[0x02] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
  81                      RTE_PTYPE_L4_NONFRAG;
  82         /* Fragmented */
  83         (*p)[0x21] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
  84                      RTE_PTYPE_L4_FRAG;
  85         (*p)[0x22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
  86                      RTE_PTYPE_L4_FRAG;
  87         /* TCP */
  88         (*p)[0x05] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
  89                      RTE_PTYPE_L4_TCP;
  90         (*p)[0x06] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
  91                      RTE_PTYPE_L4_TCP;
  92         (*p)[0x0d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
  93                      RTE_PTYPE_L4_TCP;
  94         (*p)[0x0e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
  95                      RTE_PTYPE_L4_TCP;
  96         (*p)[0x11] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
  97                      RTE_PTYPE_L4_TCP;
  98         (*p)[0x12] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
  99                      RTE_PTYPE_L4_TCP;
 100         /* UDP */
 101         (*p)[0x09] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 102                      RTE_PTYPE_L4_UDP;
 103         (*p)[0x0a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 104                      RTE_PTYPE_L4_UDP;
 105         /* Repeat with outer_l3_type being set. Just in case. */
 106         (*p)[0x81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 107                      RTE_PTYPE_L4_NONFRAG;
 108         (*p)[0x82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 109                      RTE_PTYPE_L4_NONFRAG;
 110         (*p)[0xa1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 111                      RTE_PTYPE_L4_FRAG;
 112         (*p)[0xa2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 113                      RTE_PTYPE_L4_FRAG;
 114         (*p)[0x85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 115                      RTE_PTYPE_L4_TCP;
 116         (*p)[0x86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 117                      RTE_PTYPE_L4_TCP;
 118         (*p)[0x8d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 119                      RTE_PTYPE_L4_TCP;
 120         (*p)[0x8e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 121                      RTE_PTYPE_L4_TCP;
 122         (*p)[0x91] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 123                      RTE_PTYPE_L4_TCP;
 124         (*p)[0x92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 125                      RTE_PTYPE_L4_TCP;
 126         (*p)[0x89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 127                      RTE_PTYPE_L4_UDP;
 128         (*p)[0x8a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 129                      RTE_PTYPE_L4_UDP;
 130         /* Tunneled - L3 */
 131         (*p)[0x41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 132                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 133                      RTE_PTYPE_INNER_L4_NONFRAG;
 134         (*p)[0x42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 135                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 136                      RTE_PTYPE_INNER_L4_NONFRAG;
 137         (*p)[0xc1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 138                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 139                      RTE_PTYPE_INNER_L4_NONFRAG;
 140         (*p)[0xc2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 141                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 142                      RTE_PTYPE_INNER_L4_NONFRAG;
 143         /* Tunneled - Fragmented */
 144         (*p)[0x61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 145                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 146                      RTE_PTYPE_INNER_L4_FRAG;
 147         (*p)[0x62] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 148                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 149                      RTE_PTYPE_INNER_L4_FRAG;
 150         (*p)[0xe1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 151                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 152                      RTE_PTYPE_INNER_L4_FRAG;
 153         (*p)[0xe2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 154                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 155                      RTE_PTYPE_INNER_L4_FRAG;
 156         /* Tunneled - TCP */
 157         (*p)[0x45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 158                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 159                      RTE_PTYPE_INNER_L4_TCP;
 160         (*p)[0x46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 161                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 162                      RTE_PTYPE_INNER_L4_TCP;
 163         (*p)[0x4d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 164                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 165                      RTE_PTYPE_INNER_L4_TCP;
 166         (*p)[0x4e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 167                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 168                      RTE_PTYPE_INNER_L4_TCP;
 169         (*p)[0x51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 170                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 171                      RTE_PTYPE_INNER_L4_TCP;
 172         (*p)[0x52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 173                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 174                      RTE_PTYPE_INNER_L4_TCP;
 175         (*p)[0xc5] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 176                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 177                      RTE_PTYPE_INNER_L4_TCP;
 178         (*p)[0xc6] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 179                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 180                      RTE_PTYPE_INNER_L4_TCP;
 181         (*p)[0xcd] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 182                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 183                      RTE_PTYPE_INNER_L4_TCP;
 184         (*p)[0xce] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 185                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 186                      RTE_PTYPE_INNER_L4_TCP;
 187         (*p)[0xd1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 188                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 189                      RTE_PTYPE_INNER_L4_TCP;
 190         (*p)[0xd2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 191                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 192                      RTE_PTYPE_INNER_L4_TCP;
 193         /* Tunneled - UDP */
 194         (*p)[0x49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 195                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 196                      RTE_PTYPE_INNER_L4_UDP;
 197         (*p)[0x4a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 198                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 199                      RTE_PTYPE_INNER_L4_UDP;
 200         (*p)[0xc9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 201                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 202                      RTE_PTYPE_INNER_L4_UDP;
 203         (*p)[0xca] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 204                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 205                      RTE_PTYPE_INNER_L4_UDP;
 206 }
 207
 208 /**
 209  * Build a table to translate packet to checksum type of Verbs.
 210  */
 211 void
 212 mlx5_set_cksum_table(void)
 213 {
 214         unsigned int i;
 215         uint8_t v;
 216
 217         /*
 218          * The index should have:
 219          * bit[0] = PKT_TX_TCP_SEG
 220          * bit[2:3] = PKT_TX_UDP_CKSUM, PKT_TX_TCP_CKSUM
 221          * bit[4] = PKT_TX_IP_CKSUM
 222          * bit[8] = PKT_TX_OUTER_IP_CKSUM
 223          * bit[9] = tunnel
 224          */
 225         for (i = 0; i < RTE_DIM(mlx5_cksum_table); ++i) {
 226                 v = 0;
 227                 if (i & (1 << 9)) {
 228                         /* Tunneled packet. */
 229                         if (i & (1 << 8)) /* Outer IP. */
 230                                 v |= MLX5_ETH_WQE_L3_CSUM;
 231                         if (i & (1 << 4)) /* Inner IP. */
 232                                 v |= MLX5_ETH_WQE_L3_INNER_CSUM;
 233                         if (i & (3 << 2 | 1 << 0)) /* L4 or TSO. */
 234                                 v |= MLX5_ETH_WQE_L4_INNER_CSUM;
 235                 } else {
 236                         /* No tunnel. */
 237                         if (i & (1 << 4)) /* IP. */
 238                                 v |= MLX5_ETH_WQE_L3_CSUM;
 239                         if (i & (3 << 2 | 1 << 0)) /* L4 or TSO. */
 240                                 v |= MLX5_ETH_WQE_L4_CSUM;
 241                 }
 242                 mlx5_cksum_table[i] = v;
 243         }
 244 }
 245
 246 /**
 247  * Build a table to translate packet type of mbuf to SWP type of Verbs.
 248  */
 249 void
 250 mlx5_set_swp_types_table(void)
 251 {
 252         unsigned int i;
 253         uint8_t v;
 254
 255         /*
 256          * The index should have:
 257          * bit[0:1] = PKT_TX_L4_MASK
 258          * bit[4] = PKT_TX_IPV6
 259          * bit[8] = PKT_TX_OUTER_IPV6
 260          * bit[9] = PKT_TX_OUTER_UDP
 261          */
 262         for (i = 0; i < RTE_DIM(mlx5_swp_types_table); ++i) {
 263                 v = 0;
 264                 if (i & (1 << 8))
 265                         v |= MLX5_ETH_WQE_L3_OUTER_IPV6;
 266                 if (i & (1 << 9))
 267                         v |= MLX5_ETH_WQE_L4_OUTER_UDP;
 268                 if (i & (1 << 4))
 269                         v |= MLX5_ETH_WQE_L3_INNER_IPV6;
 270                 if ((i & 3) == (PKT_TX_UDP_CKSUM >> 52))
 271                         v |= MLX5_ETH_WQE_L4_INNER_UDP;
 272                 mlx5_swp_types_table[i] = v;
 273         }
 274 }
 275
 276 /**
 277  * Return the size of tailroom of WQ.
 278  *
 279  * @param txq
 280  *   Pointer to TX queue structure.
 281  * @param addr
 282  *   Pointer to tail of WQ.
 283  *
 284  * @return
 285  *   Size of tailroom.
 286  */
 287 static inline size_t
 288 tx_mlx5_wq_tailroom(struct mlx5_txq_data *txq, void *addr)
 289 {
 290         size_t tailroom;
 291         tailroom = (uintptr_t)(txq->wqes) +
 292                    (1 << txq->wqe_n) * MLX5_WQE_SIZE -
 293                    (uintptr_t)addr;
 294         return tailroom;
 295 }
 296
 297 /**
 298  * Copy data to tailroom of circular queue.
 299  *
 300  * @param dst
 301  *   Pointer to destination.
 302  * @param src
 303  *   Pointer to source.
 304  * @param n
 305  *   Number of bytes to copy.
 306  * @param base
 307  *   Pointer to head of queue.
 308  * @param tailroom
 309  *   Size of tailroom from dst.
 310  *
 311  * @return
 312  *   Pointer after copied data.
 313  */
 314 static inline void *
 315 mlx5_copy_to_wq(void *dst, const void *src, size_t n,
 316                 void *base, size_t tailroom)
 317 {
 318         void *ret;
 319
 320         if (n > tailroom) {
 321                 rte_memcpy(dst, src, tailroom);
 322                 rte_memcpy(base, (void *)((uintptr_t)src + tailroom),
 323                            n - tailroom);
 324                 ret = (uint8_t *)base + n - tailroom;
 325         } else {
 326                 rte_memcpy(dst, src, n);
 327                 ret = (n == tailroom) ? base : (uint8_t *)dst + n;
 328         }
 329         return ret;
 330 }
 331
 332 /**
 333  * Inline TSO headers into WQE.
 334  *
 335  * @return
 336  *   0 on success, negative errno value on failure.
 337  */
 338 static int
 339 inline_tso(struct mlx5_txq_data *txq, struct rte_mbuf *buf,
 340            uint32_t *length,
 341            uintptr_t *addr,
 342            uint16_t *pkt_inline_sz,
 343            uint8_t **raw,
 344            uint16_t *max_wqe,
 345            uint16_t *tso_segsz,
 346            uint16_t *tso_header_sz)
 347 {
 348         uintptr_t end = (uintptr_t)(((uintptr_t)txq->wqes) +
 349                                     (1 << txq->wqe_n) * MLX5_WQE_SIZE);
 350         unsigned int copy_b;
 351         uint8_t vlan_sz = (buf->ol_flags & PKT_TX_VLAN_PKT) ? 4 : 0;
 352         const uint8_t tunneled = txq->tunnel_en && (buf->ol_flags &
 353                                  PKT_TX_TUNNEL_MASK);
 354         uint16_t n_wqe;
 355
 356         *tso_segsz = buf->tso_segsz;
 357         *tso_header_sz = buf->l2_len + vlan_sz + buf->l3_len + buf->l4_len;
 358         if (unlikely(*tso_segsz == 0 || *tso_header_sz == 0)) {
 359                 txq->stats.oerrors++;
 360                 return -EINVAL;
 361         }
 362         if (tunneled)
 363                 *tso_header_sz += buf->outer_l2_len + buf->outer_l3_len;
 364         /* First seg must contain all TSO headers. */
 365         if (unlikely(*tso_header_sz > MLX5_MAX_TSO_HEADER) ||
 366                      *tso_header_sz > DATA_LEN(buf)) {
 367                 txq->stats.oerrors++;
 368                 return -EINVAL;
 369         }
 370         copy_b = *tso_header_sz - *pkt_inline_sz;
 371         if (!copy_b || ((end - (uintptr_t)*raw) < copy_b))
 372                 return -EAGAIN;
 373         n_wqe = (MLX5_WQE_DS(copy_b) - 1 + 3) / 4;
 374         if (unlikely(*max_wqe < n_wqe))
 375                 return -EINVAL;
 376         *max_wqe -= n_wqe;
 377         rte_memcpy((void *)*raw, (void *)*addr, copy_b);
 378         *length -= copy_b;
 379         *addr += copy_b;
 380         copy_b = MLX5_WQE_DS(copy_b) * MLX5_WQE_DWORD_SIZE;
 381         *pkt_inline_sz += copy_b;
 382         *raw += copy_b;
 383         return 0;
 384 }
 385
 386 /**
 387  * DPDK callback to check the status of a tx descriptor.
 388  *
 389  * @param tx_queue
 390  *   The tx queue.
 391  * @param[in] offset
 392  *   The index of the descriptor in the ring.
 393  *
 394  * @return
 395  *   The status of the tx descriptor.
 396  */
 397 int
 398 mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset)
 399 {
 400         struct mlx5_txq_data *txq = tx_queue;
 401         uint16_t used;
 402
 403         mlx5_tx_complete(txq);
 404         used = txq->elts_head - txq->elts_tail;
 405         if (offset < used)
 406                 return RTE_ETH_TX_DESC_FULL;
 407         return RTE_ETH_TX_DESC_DONE;
 408 }
 409
 410 /**
 411  * DPDK callback to check the status of a rx descriptor.
 412  *
 413  * @param rx_queue
 414  *   The rx queue.
 415  * @param[in] offset
 416  *   The index of the descriptor in the ring.
 417  *
 418  * @return
 419  *   The status of the tx descriptor.
 420  */
 421 int
 422 mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset)
 423 {
 424         struct mlx5_rxq_data *rxq = rx_queue;
 425         struct rxq_zip *zip = &rxq->zip;
 426         volatile struct mlx5_cqe *cqe;
 427         const unsigned int cqe_n = (1 << rxq->cqe_n);
 428         const unsigned int cqe_cnt = cqe_n - 1;
 429         unsigned int cq_ci;
 430         unsigned int used;
 431
 432         /* if we are processing a compressed cqe */
 433         if (zip->ai) {
 434                 used = zip->cqe_cnt - zip->ca;
 435                 cq_ci = zip->cq_ci;
 436         } else {
 437                 used = 0;
 438                 cq_ci = rxq->cq_ci;
 439         }
 440         cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
 441         while (check_cqe(cqe, cqe_n, cq_ci) == 0) {
 442                 int8_t op_own;
 443                 unsigned int n;
 444
 445                 op_own = cqe->op_own;
 446                 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED)
 447                         n = rte_be_to_cpu_32(cqe->byte_cnt);
 448                 else
 449                         n = 1;
 450                 cq_ci += n;
 451                 used += n;
 452                 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
 453         }
 454         used = RTE_MIN(used, (1U << rxq->elts_n) - 1);
 455         if (offset < used)
 456                 return RTE_ETH_RX_DESC_DONE;
 457         return RTE_ETH_RX_DESC_AVAIL;
 458 }
 459
 460 /**
 461  * DPDK callback for TX.
 462  *
 463  * @param dpdk_txq
 464  *   Generic pointer to TX queue structure.
 465  * @param[in] pkts
 466  *   Packets to transmit.
 467  * @param pkts_n
 468  *   Number of packets in array.
 469  *
 470  * @return
 471  *   Number of packets successfully transmitted (<= pkts_n).
 472  */
 473 uint16_t
 474 mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
 475 {
 476         struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
 477         uint16_t elts_head = txq->elts_head;
 478         const uint16_t elts_n = 1 << txq->elts_n;
 479         const uint16_t elts_m = elts_n - 1;
 480         unsigned int i = 0;
 481         unsigned int j = 0;
 482         unsigned int k = 0;
 483         uint16_t max_elts;
 484         uint16_t max_wqe;
 485         unsigned int comp;
 486         volatile struct mlx5_wqe_ctrl *last_wqe = NULL;
 487         unsigned int segs_n = 0;
 488         const unsigned int max_inline = txq->max_inline;
 489
 490         if (unlikely(!pkts_n))
 491                 return 0;
 492         /* Prefetch first packet cacheline. */
 493         rte_prefetch0(*pkts);
 494         /* Start processing. */
 495         mlx5_tx_complete(txq);
 496         max_elts = (elts_n - (elts_head - txq->elts_tail));
 497         /* A CQE slot must always be available. */
 498         assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));
 499         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
 500         if (unlikely(!max_wqe))
 501                 return 0;
 502         do {
 503                 struct rte_mbuf *buf = *pkts; /* First_seg. */
 504                 uint8_t *raw;
 505                 volatile struct mlx5_wqe_v *wqe = NULL;
 506                 volatile rte_v128u32_t *dseg = NULL;
 507                 uint32_t length;
 508                 unsigned int ds = 0;
 509                 unsigned int sg = 0; /* counter of additional segs attached. */
 510                 uintptr_t addr;
 511                 uint16_t pkt_inline_sz = MLX5_WQE_DWORD_SIZE + 2;
 512                 uint16_t tso_header_sz = 0;
 513                 uint16_t ehdr;
 514                 uint8_t cs_flags;
 515                 uint8_t tso = txq->tso_en && (buf->ol_flags & PKT_TX_TCP_SEG);
 516                 uint8_t is_vlan = !!(buf->ol_flags & PKT_TX_VLAN_PKT);
 517                 uint32_t swp_offsets = 0;
 518                 uint8_t swp_types = 0;
 519                 uint16_t tso_segsz = 0;
 520 #ifdef MLX5_PMD_SOFT_COUNTERS
 521                 uint32_t total_length = 0;
 522 #endif
 523                 int ret;
 524
 525                 segs_n = buf->nb_segs;
 526                 /*
 527                  * Make sure there is enough room to store this packet and
 528                  * that one ring entry remains unused.
 529                  */
 530                 assert(segs_n);
 531                 if (max_elts < segs_n)
 532                         break;
 533                 max_elts -= segs_n;
 534                 sg = --segs_n;
 535                 if (unlikely(--max_wqe == 0))
 536                         break;
 537                 wqe = (volatile struct mlx5_wqe_v *)
 538                         tx_mlx5_wqe(txq, txq->wqe_ci);
 539                 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 540                 if (pkts_n - i > 1)
 541                         rte_prefetch0(*(pkts + 1));
 542                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
 543                 length = DATA_LEN(buf);
 544                 ehdr = (((uint8_t *)addr)[1] << 8) |
 545                        ((uint8_t *)addr)[0];
 546 #ifdef MLX5_PMD_SOFT_COUNTERS
 547                 total_length = length;
 548 #endif
 549                 if (length < (MLX5_WQE_DWORD_SIZE + 2)) {
 550                         txq->stats.oerrors++;
 551                         break;
 552                 }
 553                 /* Update element. */
 554                 (*txq->elts)[elts_head & elts_m] = buf;
 555                 /* Prefetch next buffer data. */
 556                 if (pkts_n - i > 1)
 557                         rte_prefetch0(
 558                             rte_pktmbuf_mtod(*(pkts + 1), volatile void *));
 559                 cs_flags = txq_ol_cksum_to_cs(buf);
 560                 txq_mbuf_to_swp(txq, buf, tso, is_vlan,
 561                                 (uint8_t *)&swp_offsets, &swp_types);
 562                 raw = ((uint8_t *)(uintptr_t)wqe) + 2 * MLX5_WQE_DWORD_SIZE;
 563                 /* Replace the Ethernet type by the VLAN if necessary. */
 564                 if (is_vlan) {
 565                         uint32_t vlan = rte_cpu_to_be_32(0x81000000 |
 566                                                          buf->vlan_tci);
 567                         unsigned int len = 2 * ETHER_ADDR_LEN - 2;
 568
 569                         addr += 2;
 570                         length -= 2;
 571                         /* Copy Destination and source mac address. */
 572                         memcpy((uint8_t *)raw, ((uint8_t *)addr), len);
 573                         /* Copy VLAN. */
 574                         memcpy((uint8_t *)raw + len, &vlan, sizeof(vlan));
 575                         /* Copy missing two bytes to end the DSeg. */
 576                         memcpy((uint8_t *)raw + len + sizeof(vlan),
 577                                ((uint8_t *)addr) + len, 2);
 578                         addr += len + 2;
 579                         length -= (len + 2);
 580                 } else {
 581                         memcpy((uint8_t *)raw, ((uint8_t *)addr) + 2,
 582                                MLX5_WQE_DWORD_SIZE);
 583                         length -= pkt_inline_sz;
 584                         addr += pkt_inline_sz;
 585                 }
 586                 raw += MLX5_WQE_DWORD_SIZE;
 587                 if (tso) {
 588                         ret = inline_tso(txq, buf, &length,
 589                                          &addr, &pkt_inline_sz,
 590                                          &raw, &max_wqe,
 591                                          &tso_segsz, &tso_header_sz);
 592                         if (ret == -EINVAL) {
 593                                 break;
 594                         } else if (ret == -EAGAIN) {
 595                                 /* NOP WQE. */
 596                                 wqe->ctrl = (rte_v128u32_t){
 597                                         rte_cpu_to_be_32(txq->wqe_ci << 8),
 598                                         rte_cpu_to_be_32(txq->qp_num_8s | 1),
 599                                         0,
 600                                         0,
 601                                 };
 602                                 ds = 1;
 603 #ifdef MLX5_PMD_SOFT_COUNTERS
 604                                 total_length = 0;
 605 #endif
 606                                 k++;
 607                                 goto next_wqe;
 608                         }
 609                 }
 610                 /* Inline if enough room. */
 611                 if (max_inline || tso) {
 612                         uint32_t inl = 0;
 613                         uintptr_t end = (uintptr_t)
 614                                 (((uintptr_t)txq->wqes) +
 615                                  (1 << txq->wqe_n) * MLX5_WQE_SIZE);
 616                         unsigned int inline_room = max_inline *
 617                                                    RTE_CACHE_LINE_SIZE -
 618                                                    (pkt_inline_sz - 2) -
 619                                                    !!tso * sizeof(inl);
 620                         uintptr_t addr_end;
 621                         unsigned int copy_b;
 622
 623 pkt_inline:
 624                         addr_end = RTE_ALIGN_FLOOR(addr + inline_room,
 625                                                    RTE_CACHE_LINE_SIZE);
 626                         copy_b = (addr_end > addr) ?
 627                                  RTE_MIN((addr_end - addr), length) : 0;
 628                         if (copy_b && ((end - (uintptr_t)raw) > copy_b)) {
 629                                 /*
 630                                  * One Dseg remains in the current WQE.  To
 631                                  * keep the computation positive, it is
 632                                  * removed after the bytes to Dseg conversion.
 633                                  */
 634                                 uint16_t n = (MLX5_WQE_DS(copy_b) - 1 + 3) / 4;
 635
 636                                 if (unlikely(max_wqe < n))
 637                                         break;
 638                                 max_wqe -= n;
 639                                 if (tso && !inl) {
 640                                         inl = rte_cpu_to_be_32(copy_b |
 641                                                                MLX5_INLINE_SEG);
 642                                         rte_memcpy((void *)raw,
 643                                                    (void *)&inl, sizeof(inl));
 644                                         raw += sizeof(inl);
 645                                         pkt_inline_sz += sizeof(inl);
 646                                 }
 647                                 rte_memcpy((void *)raw, (void *)addr, copy_b);
 648                                 addr += copy_b;
 649                                 length -= copy_b;
 650                                 pkt_inline_sz += copy_b;
 651                         }
 652                         /*
 653                          * 2 DWORDs consumed by the WQE header + ETH segment +
 654                          * the size of the inline part of the packet.
 655                          */
 656                         ds = 2 + MLX5_WQE_DS(pkt_inline_sz - 2);
 657                         if (length > 0) {
 658                                 if (ds % (MLX5_WQE_SIZE /
 659                                           MLX5_WQE_DWORD_SIZE) == 0) {
 660                                         if (unlikely(--max_wqe == 0))
 661                                                 break;
 662                                         dseg = (volatile rte_v128u32_t *)
 663                                                tx_mlx5_wqe(txq, txq->wqe_ci +
 664                                                            ds / 4);
 665                                 } else {
 666                                         dseg = (volatile rte_v128u32_t *)
 667                                                 ((uintptr_t)wqe +
 668                                                  (ds * MLX5_WQE_DWORD_SIZE));
 669                                 }
 670                                 goto use_dseg;
 671                         } else if (!segs_n) {
 672                                 goto next_pkt;
 673                         } else {
 674                                 raw += copy_b;
 675                                 inline_room -= copy_b;
 676                                 --segs_n;
 677                                 buf = buf->next;
 678                                 assert(buf);
 679                                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
 680                                 length = DATA_LEN(buf);
 681 #ifdef MLX5_PMD_SOFT_COUNTERS
 682                                 total_length += length;
 683 #endif
 684                                 (*txq->elts)[++elts_head & elts_m] = buf;
 685                                 goto pkt_inline;
 686                         }
 687                 } else {
 688                         /*
 689                          * No inline has been done in the packet, only the
 690                          * Ethernet Header as been stored.
 691                          */
 692                         dseg = (volatile rte_v128u32_t *)
 693                                 ((uintptr_t)wqe + (3 * MLX5_WQE_DWORD_SIZE));
 694                         ds = 3;
 695 use_dseg:
 696                         /* Add the remaining packet as a simple ds. */
 697                         addr = rte_cpu_to_be_64(addr);
 698                         *dseg = (rte_v128u32_t){
 699                                 rte_cpu_to_be_32(length),
 700                                 mlx5_tx_mb2mr(txq, buf),
 701                                 addr,
 702                                 addr >> 32,
 703                         };
 704                         ++ds;
 705                         if (!segs_n)
 706                                 goto next_pkt;
 707                 }
 708 next_seg:
 709                 assert(buf);
 710                 assert(ds);
 711                 assert(wqe);
 712                 /*
 713                  * Spill on next WQE when the current one does not have
 714                  * enough room left. Size of WQE must a be a multiple
 715                  * of data segment size.
 716                  */
 717                 assert(!(MLX5_WQE_SIZE % MLX5_WQE_DWORD_SIZE));
 718                 if (!(ds % (MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE))) {
 719                         if (unlikely(--max_wqe == 0))
 720                                 break;
 721                         dseg = (volatile rte_v128u32_t *)
 722                                tx_mlx5_wqe(txq, txq->wqe_ci + ds / 4);
 723                         rte_prefetch0(tx_mlx5_wqe(txq,
 724                                                   txq->wqe_ci + ds / 4 + 1));
 725                 } else {
 726                         ++dseg;
 727                 }
 728                 ++ds;
 729                 buf = buf->next;
 730                 assert(buf);
 731                 length = DATA_LEN(buf);
 732 #ifdef MLX5_PMD_SOFT_COUNTERS
 733                 total_length += length;
 734 #endif
 735                 /* Store segment information. */
 736                 addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(buf, uintptr_t));
 737                 *dseg = (rte_v128u32_t){
 738                         rte_cpu_to_be_32(length),
 739                         mlx5_tx_mb2mr(txq, buf),
 740                         addr,
 741                         addr >> 32,
 742                 };
 743                 (*txq->elts)[++elts_head & elts_m] = buf;
 744                 if (--segs_n)
 745                         goto next_seg;
 746 next_pkt:
 747                 if (ds > MLX5_DSEG_MAX) {
 748                         txq->stats.oerrors++;
 749                         break;
 750                 }
 751                 ++elts_head;
 752                 ++pkts;
 753                 ++i;
 754                 j += sg;
 755                 /* Initialize known and common part of the WQE structure. */
 756                 if (tso) {
 757                         wqe->ctrl = (rte_v128u32_t){
 758                                 rte_cpu_to_be_32((txq->wqe_ci << 8) |
 759                                                  MLX5_OPCODE_TSO),
 760                                 rte_cpu_to_be_32(txq->qp_num_8s | ds),
 761                                 0,
 762                                 0,
 763                         };
 764                         wqe->eseg = (rte_v128u32_t){
 765                                 swp_offsets,
 766                                 cs_flags | (swp_types << 8) |
 767                                 (rte_cpu_to_be_16(tso_segsz) << 16),
 768                                 0,
 769                                 (ehdr << 16) | rte_cpu_to_be_16(tso_header_sz),
 770                         };
 771                 } else {
 772                         wqe->ctrl = (rte_v128u32_t){
 773                                 rte_cpu_to_be_32((txq->wqe_ci << 8) |
 774                                                  MLX5_OPCODE_SEND),
 775                                 rte_cpu_to_be_32(txq->qp_num_8s | ds),
 776                                 0,
 777                                 0,
 778                         };
 779                         wqe->eseg = (rte_v128u32_t){
 780                                 swp_offsets,
 781                                 cs_flags | (swp_types << 8),
 782                                 0,
 783                                 (ehdr << 16) | rte_cpu_to_be_16(pkt_inline_sz),
 784                         };
 785                 }
 786 next_wqe:
 787                 txq->wqe_ci += (ds + 3) / 4;
 788                 /* Save the last successful WQE for completion request */
 789                 last_wqe = (volatile struct mlx5_wqe_ctrl *)wqe;
 790 #ifdef MLX5_PMD_SOFT_COUNTERS
 791                 /* Increment sent bytes counter. */
 792                 txq->stats.obytes += total_length;
 793 #endif
 794         } while (i < pkts_n);
 795         /* Take a shortcut if nothing must be sent. */
 796         if (unlikely((i + k) == 0))
 797                 return 0;
 798         txq->elts_head += (i + j);
 799         /* Check whether completion threshold has been reached. */
 800         comp = txq->elts_comp + i + j + k;
 801         if (comp >= MLX5_TX_COMP_THRESH) {
 802                 /* Request completion on last WQE. */
 803                 last_wqe->ctrl2 = rte_cpu_to_be_32(8);
 804                 /* Save elts_head in unused "immediate" field of WQE. */
 805                 last_wqe->ctrl3 = txq->elts_head;
 806                 txq->elts_comp = 0;
 807 #ifndef NDEBUG
 808                 ++txq->cq_pi;
 809 #endif
 810         } else {
 811                 txq->elts_comp = comp;
 812         }
 813 #ifdef MLX5_PMD_SOFT_COUNTERS
 814         /* Increment sent packets counter. */
 815         txq->stats.opackets += i;
 816 #endif
 817         /* Ring QP doorbell. */
 818         mlx5_tx_dbrec(txq, (volatile struct mlx5_wqe *)last_wqe);
 819         return i;
 820 }
 821
 822 /**
 823  * Open a MPW session.
 824  *
 825  * @param txq
 826  *   Pointer to TX queue structure.
 827  * @param mpw
 828  *   Pointer to MPW session structure.
 829  * @param length
 830  *   Packet length.
 831  */
 832 static inline void
 833 mlx5_mpw_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw, uint32_t length)
 834 {
 835         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
 836         volatile struct mlx5_wqe_data_seg (*dseg)[MLX5_MPW_DSEG_MAX] =
 837                 (volatile struct mlx5_wqe_data_seg (*)[])
 838                 tx_mlx5_wqe(txq, idx + 1);
 839
 840         mpw->state = MLX5_MPW_STATE_OPENED;
 841         mpw->pkts_n = 0;
 842         mpw->len = length;
 843         mpw->total_len = 0;
 844         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
 845         mpw->wqe->eseg.mss = rte_cpu_to_be_16(length);
 846         mpw->wqe->eseg.inline_hdr_sz = 0;
 847         mpw->wqe->eseg.rsvd0 = 0;
 848         mpw->wqe->eseg.rsvd1 = 0;
 849         mpw->wqe->eseg.rsvd2 = 0;
 850         mpw->wqe->ctrl[0] = rte_cpu_to_be_32((MLX5_OPC_MOD_MPW << 24) |
 851                                              (txq->wqe_ci << 8) |
 852                                              MLX5_OPCODE_TSO);
 853         mpw->wqe->ctrl[2] = 0;
 854         mpw->wqe->ctrl[3] = 0;
 855         mpw->data.dseg[0] = (volatile struct mlx5_wqe_data_seg *)
 856                 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
 857         mpw->data.dseg[1] = (volatile struct mlx5_wqe_data_seg *)
 858                 (((uintptr_t)mpw->wqe) + (3 * MLX5_WQE_DWORD_SIZE));
 859         mpw->data.dseg[2] = &(*dseg)[0];
 860         mpw->data.dseg[3] = &(*dseg)[1];
 861         mpw->data.dseg[4] = &(*dseg)[2];
 862 }
 863
 864 /**
 865  * Close a MPW session.
 866  *
 867  * @param txq
 868  *   Pointer to TX queue structure.
 869  * @param mpw
 870  *   Pointer to MPW session structure.
 871  */
 872 static inline void
 873 mlx5_mpw_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
 874 {
 875         unsigned int num = mpw->pkts_n;
 876
 877         /*
 878          * Store size in multiple of 16 bytes. Control and Ethernet segments
 879          * count as 2.
 880          */
 881         mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s | (2 + num));
 882         mpw->state = MLX5_MPW_STATE_CLOSED;
 883         if (num < 3)
 884                 ++txq->wqe_ci;
 885         else
 886                 txq->wqe_ci += 2;
 887         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
 888         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 889 }
 890
 891 /**
 892  * DPDK callback for TX with MPW support.
 893  *
 894  * @param dpdk_txq
 895  *   Generic pointer to TX queue structure.
 896  * @param[in] pkts
 897  *   Packets to transmit.
 898  * @param pkts_n
 899  *   Number of packets in array.
 900  *
 901  * @return
 902  *   Number of packets successfully transmitted (<= pkts_n).
 903  */
 904 uint16_t
 905 mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
 906 {
 907         struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
 908         uint16_t elts_head = txq->elts_head;
 909         const uint16_t elts_n = 1 << txq->elts_n;
 910         const uint16_t elts_m = elts_n - 1;
 911         unsigned int i = 0;
 912         unsigned int j = 0;
 913         uint16_t max_elts;
 914         uint16_t max_wqe;
 915         unsigned int comp;
 916         struct mlx5_mpw mpw = {
 917                 .state = MLX5_MPW_STATE_CLOSED,
 918         };
 919
 920         if (unlikely(!pkts_n))
 921                 return 0;
 922         /* Prefetch first packet cacheline. */
 923         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
 924         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 925         /* Start processing. */
 926         mlx5_tx_complete(txq);
 927         max_elts = (elts_n - (elts_head - txq->elts_tail));
 928         /* A CQE slot must always be available. */
 929         assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));
 930         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
 931         if (unlikely(!max_wqe))
 932                 return 0;
 933         do {
 934                 struct rte_mbuf *buf = *(pkts++);
 935                 uint32_t length;
 936                 unsigned int segs_n = buf->nb_segs;
 937                 uint32_t cs_flags;
 938
 939                 /*
 940                  * Make sure there is enough room to store this packet and
 941                  * that one ring entry remains unused.
 942                  */
 943                 assert(segs_n);
 944                 if (max_elts < segs_n)
 945                         break;
 946                 /* Do not bother with large packets MPW cannot handle. */
 947                 if (segs_n > MLX5_MPW_DSEG_MAX) {
 948                         txq->stats.oerrors++;
 949                         break;
 950                 }
 951                 max_elts -= segs_n;
 952                 --pkts_n;
 953                 cs_flags = txq_ol_cksum_to_cs(buf);
 954                 /* Retrieve packet information. */
 955                 length = PKT_LEN(buf);
 956                 assert(length);
 957                 /* Start new session if packet differs. */
 958                 if ((mpw.state == MLX5_MPW_STATE_OPENED) &&
 959                     ((mpw.len != length) ||
 960                      (segs_n != 1) ||
 961                      (mpw.wqe->eseg.cs_flags != cs_flags)))
 962                         mlx5_mpw_close(txq, &mpw);
 963                 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
 964                         /*
 965                          * Multi-Packet WQE consumes at most two WQE.
 966                          * mlx5_mpw_new() expects to be able to use such
 967                          * resources.
 968                          */
 969                         if (unlikely(max_wqe < 2))
 970                                 break;
 971                         max_wqe -= 2;
 972                         mlx5_mpw_new(txq, &mpw, length);
 973                         mpw.wqe->eseg.cs_flags = cs_flags;
 974                 }
 975                 /* Multi-segment packets must be alone in their MPW. */
 976                 assert((segs_n == 1) || (mpw.pkts_n == 0));
 977 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
 978                 length = 0;
 979 #endif
 980                 do {
 981                         volatile struct mlx5_wqe_data_seg *dseg;
 982                         uintptr_t addr;
 983
 984                         assert(buf);
 985                         (*txq->elts)[elts_head++ & elts_m] = buf;
 986                         dseg = mpw.data.dseg[mpw.pkts_n];
 987                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
 988                         *dseg = (struct mlx5_wqe_data_seg){
 989                                 .byte_count = rte_cpu_to_be_32(DATA_LEN(buf)),
 990                                 .lkey = mlx5_tx_mb2mr(txq, buf),
 991                                 .addr = rte_cpu_to_be_64(addr),
 992                         };
 993 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
 994                         length += DATA_LEN(buf);
 995 #endif
 996                         buf = buf->next;
 997                         ++mpw.pkts_n;
 998                         ++j;
 999                 } while (--segs_n);
1000                 assert(length == mpw.len);
1001                 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1002                         mlx5_mpw_close(txq, &mpw);
1003 #ifdef MLX5_PMD_SOFT_COUNTERS
1004                 /* Increment sent bytes counter. */
1005                 txq->stats.obytes += length;
1006 #endif
1007                 ++i;
1008         } while (pkts_n);
1009         /* Take a shortcut if nothing must be sent. */
1010         if (unlikely(i == 0))
1011                 return 0;
1012         /* Check whether completion threshold has been reached. */
1013         /* "j" includes both packets and segments. */
1014         comp = txq->elts_comp + j;
1015         if (comp >= MLX5_TX_COMP_THRESH) {
1016                 volatile struct mlx5_wqe *wqe = mpw.wqe;
1017
1018                 /* Request completion on last WQE. */
1019                 wqe->ctrl[2] = rte_cpu_to_be_32(8);
1020                 /* Save elts_head in unused "immediate" field of WQE. */
1021                 wqe->ctrl[3] = elts_head;
1022                 txq->elts_comp = 0;
1023 #ifndef NDEBUG
1024                 ++txq->cq_pi;
1025 #endif
1026         } else {
1027                 txq->elts_comp = comp;
1028         }
1029 #ifdef MLX5_PMD_SOFT_COUNTERS
1030         /* Increment sent packets counter. */
1031         txq->stats.opackets += i;
1032 #endif
1033         /* Ring QP doorbell. */
1034         if (mpw.state == MLX5_MPW_STATE_OPENED)
1035                 mlx5_mpw_close(txq, &mpw);
1036         mlx5_tx_dbrec(txq, mpw.wqe);
1037         txq->elts_head = elts_head;
1038         return i;
1039 }
1040
1041 /**
1042  * Open a MPW inline session.
1043  *
1044  * @param txq
1045  *   Pointer to TX queue structure.
1046  * @param mpw
1047  *   Pointer to MPW session structure.
1048  * @param length
1049  *   Packet length.
1050  */
1051 static inline void
1052 mlx5_mpw_inline_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw,
1053                     uint32_t length)
1054 {
1055         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1056         struct mlx5_wqe_inl_small *inl;
1057
1058         mpw->state = MLX5_MPW_INL_STATE_OPENED;
1059         mpw->pkts_n = 0;
1060         mpw->len = length;
1061         mpw->total_len = 0;
1062         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1063         mpw->wqe->ctrl[0] = rte_cpu_to_be_32((MLX5_OPC_MOD_MPW << 24) |
1064                                              (txq->wqe_ci << 8) |
1065                                              MLX5_OPCODE_TSO);
1066         mpw->wqe->ctrl[2] = 0;
1067         mpw->wqe->ctrl[3] = 0;
1068         mpw->wqe->eseg.mss = rte_cpu_to_be_16(length);
1069         mpw->wqe->eseg.inline_hdr_sz = 0;
1070         mpw->wqe->eseg.cs_flags = 0;
1071         mpw->wqe->eseg.rsvd0 = 0;
1072         mpw->wqe->eseg.rsvd1 = 0;
1073         mpw->wqe->eseg.rsvd2 = 0;
1074         inl = (struct mlx5_wqe_inl_small *)
1075                 (((uintptr_t)mpw->wqe) + 2 * MLX5_WQE_DWORD_SIZE);
1076         mpw->data.raw = (uint8_t *)&inl->raw;
1077 }
1078
1079 /**
1080  * Close a MPW inline session.
1081  *
1082  * @param txq
1083  *   Pointer to TX queue structure.
1084  * @param mpw
1085  *   Pointer to MPW session structure.
1086  */
1087 static inline void
1088 mlx5_mpw_inline_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
1089 {
1090         unsigned int size;
1091         struct mlx5_wqe_inl_small *inl = (struct mlx5_wqe_inl_small *)
1092                 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
1093
1094         size = MLX5_WQE_SIZE - MLX5_MWQE64_INL_DATA + mpw->total_len;
1095         /*
1096          * Store size in multiple of 16 bytes. Control and Ethernet segments
1097          * count as 2.
1098          */
1099         mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s |
1100                                              MLX5_WQE_DS(size));
1101         mpw->state = MLX5_MPW_STATE_CLOSED;
1102         inl->byte_cnt = rte_cpu_to_be_32(mpw->total_len | MLX5_INLINE_SEG);
1103         txq->wqe_ci += (size + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1104 }
1105
1106 /**
1107  * DPDK callback for TX with MPW inline support.
1108  *
1109  * @param dpdk_txq
1110  *   Generic pointer to TX queue structure.
1111  * @param[in] pkts
1112  *   Packets to transmit.
1113  * @param pkts_n
1114  *   Number of packets in array.
1115  *
1116  * @return
1117  *   Number of packets successfully transmitted (<= pkts_n).
1118  */
1119 uint16_t
1120 mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
1121                          uint16_t pkts_n)
1122 {
1123         struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
1124         uint16_t elts_head = txq->elts_head;
1125         const uint16_t elts_n = 1 << txq->elts_n;
1126         const uint16_t elts_m = elts_n - 1;
1127         unsigned int i = 0;
1128         unsigned int j = 0;
1129         uint16_t max_elts;
1130         uint16_t max_wqe;
1131         unsigned int comp;
1132         unsigned int inline_room = txq->max_inline * RTE_CACHE_LINE_SIZE;
1133         struct mlx5_mpw mpw = {
1134                 .state = MLX5_MPW_STATE_CLOSED,
1135         };
1136         /*
1137          * Compute the maximum number of WQE which can be consumed by inline
1138          * code.
1139          * - 2 DSEG for:
1140          *   - 1 control segment,
1141          *   - 1 Ethernet segment,
1142          * - N Dseg from the inline request.
1143          */
1144         const unsigned int wqe_inl_n =
1145                 ((2 * MLX5_WQE_DWORD_SIZE +
1146                   txq->max_inline * RTE_CACHE_LINE_SIZE) +
1147                  RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE;
1148
1149         if (unlikely(!pkts_n))
1150                 return 0;
1151         /* Prefetch first packet cacheline. */
1152         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
1153         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
1154         /* Start processing. */
1155         mlx5_tx_complete(txq);
1156         max_elts = (elts_n - (elts_head - txq->elts_tail));
1157         /* A CQE slot must always be available. */
1158         assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));
1159         do {
1160                 struct rte_mbuf *buf = *(pkts++);
1161                 uintptr_t addr;
1162                 uint32_t length;
1163                 unsigned int segs_n = buf->nb_segs;
1164                 uint8_t cs_flags;
1165
1166                 /*
1167                  * Make sure there is enough room to store this packet and
1168                  * that one ring entry remains unused.
1169                  */
1170                 assert(segs_n);
1171                 if (max_elts < segs_n)
1172                         break;
1173                 /* Do not bother with large packets MPW cannot handle. */
1174                 if (segs_n > MLX5_MPW_DSEG_MAX) {
1175                         txq->stats.oerrors++;
1176                         break;
1177                 }
1178                 max_elts -= segs_n;
1179                 --pkts_n;
1180                 /*
1181                  * Compute max_wqe in case less WQE were consumed in previous
1182                  * iteration.
1183                  */
1184                 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1185                 cs_flags = txq_ol_cksum_to_cs(buf);
1186                 /* Retrieve packet information. */
1187                 length = PKT_LEN(buf);
1188                 /* Start new session if packet differs. */
1189                 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1190                         if ((mpw.len != length) ||
1191                             (segs_n != 1) ||
1192                             (mpw.wqe->eseg.cs_flags != cs_flags))
1193                                 mlx5_mpw_close(txq, &mpw);
1194                 } else if (mpw.state == MLX5_MPW_INL_STATE_OPENED) {
1195                         if ((mpw.len != length) ||
1196                             (segs_n != 1) ||
1197                             (length > inline_room) ||
1198                             (mpw.wqe->eseg.cs_flags != cs_flags)) {
1199                                 mlx5_mpw_inline_close(txq, &mpw);
1200                                 inline_room =
1201                                         txq->max_inline * RTE_CACHE_LINE_SIZE;
1202                         }
1203                 }
1204                 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1205                         if ((segs_n != 1) ||
1206                             (length > inline_room)) {
1207                                 /*
1208                                  * Multi-Packet WQE consumes at most two WQE.
1209                                  * mlx5_mpw_new() expects to be able to use
1210                                  * such resources.
1211                                  */
1212                                 if (unlikely(max_wqe < 2))
1213                                         break;
1214                                 max_wqe -= 2;
1215                                 mlx5_mpw_new(txq, &mpw, length);
1216                                 mpw.wqe->eseg.cs_flags = cs_flags;
1217                         } else {
1218                                 if (unlikely(max_wqe < wqe_inl_n))
1219                                         break;
1220                                 max_wqe -= wqe_inl_n;
1221                                 mlx5_mpw_inline_new(txq, &mpw, length);
1222                                 mpw.wqe->eseg.cs_flags = cs_flags;
1223                         }
1224                 }
1225                 /* Multi-segment packets must be alone in their MPW. */
1226                 assert((segs_n == 1) || (mpw.pkts_n == 0));
1227                 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1228                         assert(inline_room ==
1229                                txq->max_inline * RTE_CACHE_LINE_SIZE);
1230 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1231                         length = 0;
1232 #endif
1233                         do {
1234                                 volatile struct mlx5_wqe_data_seg *dseg;
1235
1236                                 assert(buf);
1237                                 (*txq->elts)[elts_head++ & elts_m] = buf;
1238                                 dseg = mpw.data.dseg[mpw.pkts_n];
1239                                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1240                                 *dseg = (struct mlx5_wqe_data_seg){
1241                                         .byte_count =
1242                                                rte_cpu_to_be_32(DATA_LEN(buf)),
1243                                         .lkey = mlx5_tx_mb2mr(txq, buf),
1244                                         .addr = rte_cpu_to_be_64(addr),
1245                                 };
1246 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1247                                 length += DATA_LEN(buf);
1248 #endif
1249                                 buf = buf->next;
1250                                 ++mpw.pkts_n;
1251                                 ++j;
1252                         } while (--segs_n);
1253                         assert(length == mpw.len);
1254                         if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1255                                 mlx5_mpw_close(txq, &mpw);
1256                 } else {
1257                         unsigned int max;
1258
1259                         assert(mpw.state == MLX5_MPW_INL_STATE_OPENED);
1260                         assert(length <= inline_room);
1261                         assert(length == DATA_LEN(buf));
1262                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1263                         (*txq->elts)[elts_head++ & elts_m] = buf;
1264                         /* Maximum number of bytes before wrapping. */
1265                         max = ((((uintptr_t)(txq->wqes)) +
1266                                 (1 << txq->wqe_n) *
1267                                 MLX5_WQE_SIZE) -
1268                                (uintptr_t)mpw.data.raw);
1269                         if (length > max) {
1270                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1271                                            (void *)addr,
1272                                            max);
1273                                 mpw.data.raw = (volatile void *)txq->wqes;
1274                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1275                                            (void *)(addr + max),
1276                                            length - max);
1277                                 mpw.data.raw += length - max;
1278                         } else {
1279                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1280                                            (void *)addr,
1281                                            length);
1282
1283                                 if (length == max)
1284                                         mpw.data.raw =
1285                                                 (volatile void *)txq->wqes;
1286                                 else
1287                                         mpw.data.raw += length;
1288                         }
1289                         ++mpw.pkts_n;
1290                         mpw.total_len += length;
1291                         ++j;
1292                         if (mpw.pkts_n == MLX5_MPW_DSEG_MAX) {
1293                                 mlx5_mpw_inline_close(txq, &mpw);
1294                                 inline_room =
1295                                         txq->max_inline * RTE_CACHE_LINE_SIZE;
1296                         } else {
1297                                 inline_room -= length;
1298                         }
1299                 }
1300 #ifdef MLX5_PMD_SOFT_COUNTERS
1301                 /* Increment sent bytes counter. */
1302                 txq->stats.obytes += length;
1303 #endif
1304                 ++i;
1305         } while (pkts_n);
1306         /* Take a shortcut if nothing must be sent. */
1307         if (unlikely(i == 0))
1308                 return 0;
1309         /* Check whether completion threshold has been reached. */
1310         /* "j" includes both packets and segments. */
1311         comp = txq->elts_comp + j;
1312         if (comp >= MLX5_TX_COMP_THRESH) {
1313                 volatile struct mlx5_wqe *wqe = mpw.wqe;
1314
1315                 /* Request completion on last WQE. */
1316                 wqe->ctrl[2] = rte_cpu_to_be_32(8);
1317                 /* Save elts_head in unused "immediate" field of WQE. */
1318                 wqe->ctrl[3] = elts_head;
1319                 txq->elts_comp = 0;
1320 #ifndef NDEBUG
1321                 ++txq->cq_pi;
1322 #endif
1323         } else {
1324                 txq->elts_comp = comp;
1325         }
1326 #ifdef MLX5_PMD_SOFT_COUNTERS
1327         /* Increment sent packets counter. */
1328         txq->stats.opackets += i;
1329 #endif
1330         /* Ring QP doorbell. */
1331         if (mpw.state == MLX5_MPW_INL_STATE_OPENED)
1332                 mlx5_mpw_inline_close(txq, &mpw);
1333         else if (mpw.state == MLX5_MPW_STATE_OPENED)
1334                 mlx5_mpw_close(txq, &mpw);
1335         mlx5_tx_dbrec(txq, mpw.wqe);
1336         txq->elts_head = elts_head;
1337         return i;
1338 }
1339
1340 /**
1341  * Open an Enhanced MPW session.
1342  *
1343  * @param txq
1344  *   Pointer to TX queue structure.
1345  * @param mpw
1346  *   Pointer to MPW session structure.
1347  * @param length
1348  *   Packet length.
1349  */
1350 static inline void
1351 mlx5_empw_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw, int padding)
1352 {
1353         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1354
1355         mpw->state = MLX5_MPW_ENHANCED_STATE_OPENED;
1356         mpw->pkts_n = 0;
1357         mpw->total_len = sizeof(struct mlx5_wqe);
1358         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1359         mpw->wqe->ctrl[0] =
1360                 rte_cpu_to_be_32((MLX5_OPC_MOD_ENHANCED_MPSW << 24) |
1361                                  (txq->wqe_ci << 8) |
1362                                  MLX5_OPCODE_ENHANCED_MPSW);
1363         mpw->wqe->ctrl[2] = 0;
1364         mpw->wqe->ctrl[3] = 0;
1365         memset((void *)(uintptr_t)&mpw->wqe->eseg, 0, MLX5_WQE_DWORD_SIZE);
1366         if (unlikely(padding)) {
1367                 uintptr_t addr = (uintptr_t)(mpw->wqe + 1);
1368
1369                 /* Pad the first 2 DWORDs with zero-length inline header. */
1370                 *(volatile uint32_t *)addr = rte_cpu_to_be_32(MLX5_INLINE_SEG);
1371                 *(volatile uint32_t *)(addr + MLX5_WQE_DWORD_SIZE) =
1372                         rte_cpu_to_be_32(MLX5_INLINE_SEG);
1373                 mpw->total_len += 2 * MLX5_WQE_DWORD_SIZE;
1374                 /* Start from the next WQEBB. */
1375                 mpw->data.raw = (volatile void *)(tx_mlx5_wqe(txq, idx + 1));
1376         } else {
1377                 mpw->data.raw = (volatile void *)(mpw->wqe + 1);
1378         }
1379 }
1380
1381 /**
1382  * Close an Enhanced MPW session.
1383  *
1384  * @param txq
1385  *   Pointer to TX queue structure.
1386  * @param mpw
1387  *   Pointer to MPW session structure.
1388  *
1389  * @return
1390  *   Number of consumed WQEs.
1391  */
1392 static inline uint16_t
1393 mlx5_empw_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
1394 {
1395         uint16_t ret;
1396
1397         /* Store size in multiple of 16 bytes. Control and Ethernet segments
1398          * count as 2.
1399          */
1400         mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s |
1401                                              MLX5_WQE_DS(mpw->total_len));
1402         mpw->state = MLX5_MPW_STATE_CLOSED;
1403         ret = (mpw->total_len + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1404         txq->wqe_ci += ret;
1405         return ret;
1406 }
1407
1408 /**
1409  * TX with Enhanced MPW support.
1410  *
1411  * @param txq
1412  *   Pointer to TX queue structure.
1413  * @param[in] pkts
1414  *   Packets to transmit.
1415  * @param pkts_n
1416  *   Number of packets in array.
1417  *
1418  * @return
1419  *   Number of packets successfully transmitted (<= pkts_n).
1420  */
1421 static inline uint16_t
1422 txq_burst_empw(struct mlx5_txq_data *txq, struct rte_mbuf **pkts,
1423                uint16_t pkts_n)
1424 {
1425         uint16_t elts_head = txq->elts_head;
1426         const uint16_t elts_n = 1 << txq->elts_n;
1427         const uint16_t elts_m = elts_n - 1;
1428         unsigned int i = 0;
1429         unsigned int j = 0;
1430         uint16_t max_elts;
1431         uint16_t max_wqe;
1432         unsigned int max_inline = txq->max_inline * RTE_CACHE_LINE_SIZE;
1433         unsigned int mpw_room = 0;
1434         unsigned int inl_pad = 0;
1435         uint32_t inl_hdr;
1436         struct mlx5_mpw mpw = {
1437                 .state = MLX5_MPW_STATE_CLOSED,
1438         };
1439
1440         if (unlikely(!pkts_n))
1441                 return 0;
1442         /* Start processing. */
1443         mlx5_tx_complete(txq);
1444         max_elts = (elts_n - (elts_head - txq->elts_tail));
1445         /* A CQE slot must always be available. */
1446         assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));
1447         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1448         if (unlikely(!max_wqe))
1449                 return 0;
1450         do {
1451                 struct rte_mbuf *buf = *(pkts++);
1452                 uintptr_t addr;
1453                 unsigned int do_inline = 0; /* Whether inline is possible. */
1454                 uint32_t length;
1455                 uint8_t cs_flags;
1456
1457                 /* Multi-segmented packet is handled in slow-path outside. */
1458                 assert(NB_SEGS(buf) == 1);
1459                 /* Make sure there is enough room to store this packet. */
1460                 if (max_elts - j == 0)
1461                         break;
1462                 cs_flags = txq_ol_cksum_to_cs(buf);
1463                 /* Retrieve packet information. */
1464                 length = PKT_LEN(buf);
1465                 /* Start new session if:
1466                  * - multi-segment packet
1467                  * - no space left even for a dseg
1468                  * - next packet can be inlined with a new WQE
1469                  * - cs_flag differs
1470                  */
1471                 if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED) {
1472                         if ((inl_pad + sizeof(struct mlx5_wqe_data_seg) >
1473                              mpw_room) ||
1474                             (length <= txq->inline_max_packet_sz &&
1475                              inl_pad + sizeof(inl_hdr) + length >
1476                              mpw_room) ||
1477                             (mpw.wqe->eseg.cs_flags != cs_flags))
1478                                 max_wqe -= mlx5_empw_close(txq, &mpw);
1479                 }
1480                 if (unlikely(mpw.state == MLX5_MPW_STATE_CLOSED)) {
1481                         /* In Enhanced MPW, inline as much as the budget is
1482                          * allowed. The remaining space is to be filled with
1483                          * dsegs. If the title WQEBB isn't padded, it will have
1484                          * 2 dsegs there.
1485                          */
1486                         mpw_room = RTE_MIN(MLX5_WQE_SIZE_MAX,
1487                                            (max_inline ? max_inline :
1488                                             pkts_n * MLX5_WQE_DWORD_SIZE) +
1489                                            MLX5_WQE_SIZE);
1490                         if (unlikely(max_wqe * MLX5_WQE_SIZE < mpw_room))
1491                                 break;
1492                         /* Don't pad the title WQEBB to not waste WQ. */
1493                         mlx5_empw_new(txq, &mpw, 0);
1494                         mpw_room -= mpw.total_len;
1495                         inl_pad = 0;
1496                         do_inline = length <= txq->inline_max_packet_sz &&
1497                                     sizeof(inl_hdr) + length <= mpw_room &&
1498                                     !txq->mpw_hdr_dseg;
1499                         mpw.wqe->eseg.cs_flags = cs_flags;
1500                 } else {
1501                         /* Evaluate whether the next packet can be inlined.
1502                          * Inlininig is possible when:
1503                          * - length is less than configured value
1504                          * - length fits for remaining space
1505                          * - not required to fill the title WQEBB with dsegs
1506                          */
1507                         do_inline =
1508                                 length <= txq->inline_max_packet_sz &&
1509                                 inl_pad + sizeof(inl_hdr) + length <=
1510                                  mpw_room &&
1511                                 (!txq->mpw_hdr_dseg ||
1512                                  mpw.total_len >= MLX5_WQE_SIZE);
1513                 }
1514                 if (max_inline && do_inline) {
1515                         /* Inline packet into WQE. */
1516                         unsigned int max;
1517
1518                         assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1519                         assert(length == DATA_LEN(buf));
1520                         inl_hdr = rte_cpu_to_be_32(length | MLX5_INLINE_SEG);
1521                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1522                         mpw.data.raw = (volatile void *)
1523                                 ((uintptr_t)mpw.data.raw + inl_pad);
1524                         max = tx_mlx5_wq_tailroom(txq,
1525                                         (void *)(uintptr_t)mpw.data.raw);
1526                         /* Copy inline header. */
1527                         mpw.data.raw = (volatile void *)
1528                                 mlx5_copy_to_wq(
1529                                           (void *)(uintptr_t)mpw.data.raw,
1530                                           &inl_hdr,
1531                                           sizeof(inl_hdr),
1532                                           (void *)(uintptr_t)txq->wqes,
1533                                           max);
1534                         max = tx_mlx5_wq_tailroom(txq,
1535                                         (void *)(uintptr_t)mpw.data.raw);
1536                         /* Copy packet data. */
1537                         mpw.data.raw = (volatile void *)
1538                                 mlx5_copy_to_wq(
1539                                           (void *)(uintptr_t)mpw.data.raw,
1540                                           (void *)addr,
1541                                           length,
1542                                           (void *)(uintptr_t)txq->wqes,
1543                                           max);
1544                         ++mpw.pkts_n;
1545                         mpw.total_len += (inl_pad + sizeof(inl_hdr) + length);
1546                         /* No need to get completion as the entire packet is
1547                          * copied to WQ. Free the buf right away.
1548                          */
1549                         rte_pktmbuf_free_seg(buf);
1550                         mpw_room -= (inl_pad + sizeof(inl_hdr) + length);
1551                         /* Add pad in the next packet if any. */
1552                         inl_pad = (((uintptr_t)mpw.data.raw +
1553                                         (MLX5_WQE_DWORD_SIZE - 1)) &
1554                                         ~(MLX5_WQE_DWORD_SIZE - 1)) -
1555                                   (uintptr_t)mpw.data.raw;
1556                 } else {
1557                         /* No inline. Load a dseg of packet pointer. */
1558                         volatile rte_v128u32_t *dseg;
1559
1560                         assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1561                         assert((inl_pad + sizeof(*dseg)) <= mpw_room);
1562                         assert(length == DATA_LEN(buf));
1563                         if (!tx_mlx5_wq_tailroom(txq,
1564                                         (void *)((uintptr_t)mpw.data.raw
1565                                                 + inl_pad)))
1566                                 dseg = (volatile void *)txq->wqes;
1567                         else
1568                                 dseg = (volatile void *)
1569                                         ((uintptr_t)mpw.data.raw +
1570                                          inl_pad);
1571                         (*txq->elts)[elts_head++ & elts_m] = buf;
1572                         addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(buf,
1573                                                                  uintptr_t));
1574                         *dseg = (rte_v128u32_t) {
1575                                 rte_cpu_to_be_32(length),
1576                                 mlx5_tx_mb2mr(txq, buf),
1577                                 addr,
1578                                 addr >> 32,
1579                         };
1580                         mpw.data.raw = (volatile void *)(dseg + 1);
1581                         mpw.total_len += (inl_pad + sizeof(*dseg));
1582                         ++j;
1583                         ++mpw.pkts_n;
1584                         mpw_room -= (inl_pad + sizeof(*dseg));
1585                         inl_pad = 0;
1586                 }
1587 #ifdef MLX5_PMD_SOFT_COUNTERS
1588                 /* Increment sent bytes counter. */
1589                 txq->stats.obytes += length;
1590 #endif
1591                 ++i;
1592         } while (i < pkts_n);
1593         /* Take a shortcut if nothing must be sent. */
1594         if (unlikely(i == 0))
1595                 return 0;
1596         /* Check whether completion threshold has been reached. */
1597         if (txq->elts_comp + j >= MLX5_TX_COMP_THRESH ||
1598                         (uint16_t)(txq->wqe_ci - txq->mpw_comp) >=
1599                          (1 << txq->wqe_n) / MLX5_TX_COMP_THRESH_INLINE_DIV) {
1600                 volatile struct mlx5_wqe *wqe = mpw.wqe;
1601
1602                 /* Request completion on last WQE. */
1603                 wqe->ctrl[2] = rte_cpu_to_be_32(8);
1604                 /* Save elts_head in unused "immediate" field of WQE. */
1605                 wqe->ctrl[3] = elts_head;
1606                 txq->elts_comp = 0;
1607                 txq->mpw_comp = txq->wqe_ci;
1608 #ifndef NDEBUG
1609                 ++txq->cq_pi;
1610 #endif
1611         } else {
1612                 txq->elts_comp += j;
1613         }
1614 #ifdef MLX5_PMD_SOFT_COUNTERS
1615         /* Increment sent packets counter. */
1616         txq->stats.opackets += i;
1617 #endif
1618         if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED)
1619                 mlx5_empw_close(txq, &mpw);
1620         /* Ring QP doorbell. */
1621         mlx5_tx_dbrec(txq, mpw.wqe);
1622         txq->elts_head = elts_head;
1623         return i;
1624 }
1625
1626 /**
1627  * DPDK callback for TX with Enhanced MPW support.
1628  *
1629  * @param dpdk_txq
1630  *   Generic pointer to TX queue structure.
1631  * @param[in] pkts
1632  *   Packets to transmit.
1633  * @param pkts_n
1634  *   Number of packets in array.
1635  *
1636  * @return
1637  *   Number of packets successfully transmitted (<= pkts_n).
1638  */
1639 uint16_t
1640 mlx5_tx_burst_empw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1641 {
1642         struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
1643         uint16_t nb_tx = 0;
1644
1645         while (pkts_n > nb_tx) {
1646                 uint16_t n;
1647                 uint16_t ret;
1648
1649                 n = txq_count_contig_multi_seg(&pkts[nb_tx], pkts_n - nb_tx);
1650                 if (n) {
1651                         ret = mlx5_tx_burst(dpdk_txq, &pkts[nb_tx], n);
1652                         if (!ret)
1653                                 break;
1654                         nb_tx += ret;
1655                 }
1656                 n = txq_count_contig_single_seg(&pkts[nb_tx], pkts_n - nb_tx);
1657                 if (n) {
1658                         ret = txq_burst_empw(txq, &pkts[nb_tx], n);
1659                         if (!ret)
1660                                 break;
1661                         nb_tx += ret;
1662                 }
1663         }
1664         return nb_tx;
1665 }
1666
1667 /**
1668  * Translate RX completion flags to packet type.
1669  *
1670  * @param[in] cqe
1671  *   Pointer to CQE.
1672  *
1673  * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
1674  *
1675  * @return
1676  *   Packet type for struct rte_mbuf.
1677  */
1678 static inline uint32_t
1679 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe)
1680 {
1681         uint8_t idx;
1682         uint8_t pinfo = cqe->pkt_info;
1683         uint16_t ptype = cqe->hdr_type_etc;
1684
1685         /*
1686          * The index to the array should have:
1687          * bit[1:0] = l3_hdr_type
1688          * bit[4:2] = l4_hdr_type
1689          * bit[5] = ip_frag
1690          * bit[6] = tunneled
1691          * bit[7] = outer_l3_type
1692          */
1693         idx = ((pinfo & 0x3) << 6) | ((ptype & 0xfc00) >> 10);
1694         return mlx5_ptype_table[idx];
1695 }
1696
1697 /**
1698  * Get size of the next packet for a given CQE. For compressed CQEs, the
1699  * consumer index is updated only once all packets of the current one have
1700  * been processed.
1701  *
1702  * @param rxq
1703  *   Pointer to RX queue.
1704  * @param cqe
1705  *   CQE to process.
1706  * @param[out] rss_hash
1707  *   Packet RSS Hash result.
1708  *
1709  * @return
1710  *   Packet size in bytes (0 if there is none), -1 in case of completion
1711  *   with error.
1712  */
1713 static inline int
1714 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
1715                  uint16_t cqe_cnt, uint32_t *rss_hash)
1716 {
1717         struct rxq_zip *zip = &rxq->zip;
1718         uint16_t cqe_n = cqe_cnt + 1;
1719         int len = 0;
1720         uint16_t idx, end;
1721
1722         /* Process compressed data in the CQE and mini arrays. */
1723         if (zip->ai) {
1724                 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1725                         (volatile struct mlx5_mini_cqe8 (*)[8])
1726                         (uintptr_t)(&(*rxq->cqes)[zip->ca & cqe_cnt].pkt_info);
1727
1728                 len = rte_be_to_cpu_32((*mc)[zip->ai & 7].byte_cnt);
1729                 *rss_hash = rte_be_to_cpu_32((*mc)[zip->ai & 7].rx_hash_result);
1730                 if ((++zip->ai & 7) == 0) {
1731                         /* Invalidate consumed CQEs */
1732                         idx = zip->ca;
1733                         end = zip->na;
1734                         while (idx != end) {
1735                                 (*rxq->cqes)[idx & cqe_cnt].op_own =
1736                                         MLX5_CQE_INVALIDATE;
1737                                 ++idx;
1738                         }
1739                         /*
1740                          * Increment consumer index to skip the number of
1741                          * CQEs consumed. Hardware leaves holes in the CQ
1742                          * ring for software use.
1743                          */
1744                         zip->ca = zip->na;
1745                         zip->na += 8;
1746                 }
1747                 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1748                         /* Invalidate the rest */
1749                         idx = zip->ca;
1750                         end = zip->cq_ci;
1751
1752                         while (idx != end) {
1753                                 (*rxq->cqes)[idx & cqe_cnt].op_own =
1754                                         MLX5_CQE_INVALIDATE;
1755                                 ++idx;
1756                         }
1757                         rxq->cq_ci = zip->cq_ci;
1758                         zip->ai = 0;
1759                 }
1760         /* No compressed data, get next CQE and verify if it is compressed. */
1761         } else {
1762                 int ret;
1763                 int8_t op_own;
1764
1765                 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1766                 if (unlikely(ret == 1))
1767                         return 0;
1768                 ++rxq->cq_ci;
1769                 op_own = cqe->op_own;
1770                 rte_cio_rmb();
1771                 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1772                         volatile struct mlx5_mini_cqe8 (*mc)[8] =
1773                                 (volatile struct mlx5_mini_cqe8 (*)[8])
1774                                 (uintptr_t)(&(*rxq->cqes)[rxq->cq_ci &
1775                                                           cqe_cnt].pkt_info);
1776
1777                         /* Fix endianness. */
1778                         zip->cqe_cnt = rte_be_to_cpu_32(cqe->byte_cnt);
1779                         /*
1780                          * Current mini array position is the one returned by
1781                          * check_cqe64().
1782                          *
1783                          * If completion comprises several mini arrays, as a
1784                          * special case the second one is located 7 CQEs after
1785                          * the initial CQE instead of 8 for subsequent ones.
1786                          */
1787                         zip->ca = rxq->cq_ci;
1788                         zip->na = zip->ca + 7;
1789                         /* Compute the next non compressed CQE. */
1790                         --rxq->cq_ci;
1791                         zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1792                         /* Get packet size to return. */
1793                         len = rte_be_to_cpu_32((*mc)[0].byte_cnt);
1794                         *rss_hash = rte_be_to_cpu_32((*mc)[0].rx_hash_result);
1795                         zip->ai = 1;
1796                         /* Prefetch all the entries to be invalidated */
1797                         idx = zip->ca;
1798                         end = zip->cq_ci;
1799                         while (idx != end) {
1800                                 rte_prefetch0(&(*rxq->cqes)[(idx) & cqe_cnt]);
1801                                 ++idx;
1802                         }
1803                 } else {
1804                         len = rte_be_to_cpu_32(cqe->byte_cnt);
1805                         *rss_hash = rte_be_to_cpu_32(cqe->rx_hash_res);
1806                 }
1807                 /* Error while receiving packet. */
1808                 if (unlikely(MLX5_CQE_OPCODE(op_own) == MLX5_CQE_RESP_ERR))
1809                         return -1;
1810         }
1811         return len;
1812 }
1813
1814 /**
1815  * Translate RX completion flags to offload flags.
1816  *
1817  * @param[in] rxq
1818  *   Pointer to RX queue structure.
1819  * @param[in] cqe
1820  *   Pointer to CQE.
1821  *
1822  * @return
1823  *   Offload flags (ol_flags) for struct rte_mbuf.
1824  */
1825 static inline uint32_t
1826 rxq_cq_to_ol_flags(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe)
1827 {
1828         uint32_t ol_flags = 0;
1829         uint16_t flags = rte_be_to_cpu_16(cqe->hdr_type_etc);
1830
1831         ol_flags =
1832                 TRANSPOSE(flags,
1833                           MLX5_CQE_RX_L3_HDR_VALID,
1834                           PKT_RX_IP_CKSUM_GOOD) |
1835                 TRANSPOSE(flags,
1836                           MLX5_CQE_RX_L4_HDR_VALID,
1837                           PKT_RX_L4_CKSUM_GOOD);
1838         if ((cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) && (rxq->csum_l2tun))
1839                 ol_flags |=
1840                         TRANSPOSE(flags,
1841                                   MLX5_CQE_RX_L3_HDR_VALID,
1842                                   PKT_RX_IP_CKSUM_GOOD) |
1843                         TRANSPOSE(flags,
1844                                   MLX5_CQE_RX_L4_HDR_VALID,
1845                                   PKT_RX_L4_CKSUM_GOOD);
1846         return ol_flags;
1847 }
1848
1849 /**
1850  * DPDK callback for RX.
1851  *
1852  * @param dpdk_rxq
1853  *   Generic pointer to RX queue structure.
1854  * @param[out] pkts
1855  *   Array to store received packets.
1856  * @param pkts_n
1857  *   Maximum number of packets in array.
1858  *
1859  * @return
1860  *   Number of packets successfully received (<= pkts_n).
1861  */
1862 uint16_t
1863 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1864 {
1865         struct mlx5_rxq_data *rxq = dpdk_rxq;
1866         const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1867         const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1868         const unsigned int sges_n = rxq->sges_n;
1869         struct rte_mbuf *pkt = NULL;
1870         struct rte_mbuf *seg = NULL;
1871         volatile struct mlx5_cqe *cqe =
1872                 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1873         unsigned int i = 0;
1874         unsigned int rq_ci = rxq->rq_ci << sges_n;
1875         int len = 0; /* keep its value across iterations. */
1876
1877         while (pkts_n) {
1878                 unsigned int idx = rq_ci & wqe_cnt;
1879                 volatile struct mlx5_wqe_data_seg *wqe = &(*rxq->wqes)[idx];
1880                 struct rte_mbuf *rep = (*rxq->elts)[idx];
1881                 uint32_t rss_hash_res = 0;
1882
1883                 if (pkt)
1884                         NEXT(seg) = rep;
1885                 seg = rep;
1886                 rte_prefetch0(seg);
1887                 rte_prefetch0(cqe);
1888                 rte_prefetch0(wqe);
1889                 rep = rte_mbuf_raw_alloc(rxq->mp);
1890                 if (unlikely(rep == NULL)) {
1891                         ++rxq->stats.rx_nombuf;
1892                         if (!pkt) {
1893                                 /*
1894                                  * no buffers before we even started,
1895                                  * bail out silently.
1896                                  */
1897                                 break;
1898                         }
1899                         while (pkt != seg) {
1900                                 assert(pkt != (*rxq->elts)[idx]);
1901                                 rep = NEXT(pkt);
1902                                 NEXT(pkt) = NULL;
1903                                 NB_SEGS(pkt) = 1;
1904                                 rte_mbuf_raw_free(pkt);
1905                                 pkt = rep;
1906                         }
1907                         break;
1908                 }
1909                 if (!pkt) {
1910                         cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1911                         len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt,
1912                                                &rss_hash_res);
1913                         if (!len) {
1914                                 rte_mbuf_raw_free(rep);
1915                                 break;
1916                         }
1917                         if (unlikely(len == -1)) {
1918                                 /* RX error, packet is likely too large. */
1919                                 rte_mbuf_raw_free(rep);
1920                                 ++rxq->stats.idropped;
1921                                 goto skip;
1922                         }
1923                         pkt = seg;
1924                         assert(len >= (rxq->crc_present << 2));
1925                         /* Update packet information. */
1926                         pkt->packet_type = rxq_cq_to_pkt_type(cqe);
1927                         pkt->ol_flags = 0;
1928                         if (rss_hash_res && rxq->rss_hash) {
1929                                 pkt->hash.rss = rss_hash_res;
1930                                 pkt->ol_flags = PKT_RX_RSS_HASH;
1931                         }
1932                         if (rxq->mark &&
1933                             MLX5_FLOW_MARK_IS_VALID(cqe->sop_drop_qpn)) {
1934                                 pkt->ol_flags |= PKT_RX_FDIR;
1935                                 if (cqe->sop_drop_qpn !=
1936                                     rte_cpu_to_be_32(MLX5_FLOW_MARK_DEFAULT)) {
1937                                         uint32_t mark = cqe->sop_drop_qpn;
1938
1939                                         pkt->ol_flags |= PKT_RX_FDIR_ID;
1940                                         pkt->hash.fdir.hi =
1941                                                 mlx5_flow_mark_get(mark);
1942                                 }
1943                         }
1944                         if (rxq->csum | rxq->csum_l2tun)
1945                                 pkt->ol_flags |= rxq_cq_to_ol_flags(rxq, cqe);
1946                         if (rxq->vlan_strip &&
1947                             (cqe->hdr_type_etc &
1948                              rte_cpu_to_be_16(MLX5_CQE_VLAN_STRIPPED))) {
1949                                 pkt->ol_flags |= PKT_RX_VLAN |
1950                                         PKT_RX_VLAN_STRIPPED;
1951                                 pkt->vlan_tci =
1952                                         rte_be_to_cpu_16(cqe->vlan_info);
1953                         }
1954                         if (rxq->hw_timestamp) {
1955                                 pkt->timestamp =
1956                                         rte_be_to_cpu_64(cqe->timestamp);
1957                                 pkt->ol_flags |= PKT_RX_TIMESTAMP;
1958                         }
1959                         if (rxq->crc_present)
1960                                 len -= ETHER_CRC_LEN;
1961                         PKT_LEN(pkt) = len;
1962                 }
1963                 DATA_LEN(rep) = DATA_LEN(seg);
1964                 PKT_LEN(rep) = PKT_LEN(seg);
1965                 SET_DATA_OFF(rep, DATA_OFF(seg));
1966                 PORT(rep) = PORT(seg);
1967                 (*rxq->elts)[idx] = rep;
1968                 /*
1969                  * Fill NIC descriptor with the new buffer.  The lkey and size
1970                  * of the buffers are already known, only the buffer address
1971                  * changes.
1972                  */
1973                 wqe->addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(rep, uintptr_t));
1974                 if (len > DATA_LEN(seg)) {
1975                         len -= DATA_LEN(seg);
1976                         ++NB_SEGS(pkt);
1977                         ++rq_ci;
1978                         continue;
1979                 }
1980                 DATA_LEN(seg) = len;
1981 #ifdef MLX5_PMD_SOFT_COUNTERS
1982                 /* Increment bytes counter. */
1983                 rxq->stats.ibytes += PKT_LEN(pkt);
1984 #endif
1985                 /* Return packet. */
1986                 *(pkts++) = pkt;
1987                 pkt = NULL;
1988                 --pkts_n;
1989                 ++i;
1990 skip:
1991                 /* Align consumer index to the next stride. */
1992                 rq_ci >>= sges_n;
1993                 ++rq_ci;
1994                 rq_ci <<= sges_n;
1995         }
1996         if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
1997                 return 0;
1998         /* Update the consumer index. */
1999         rxq->rq_ci = rq_ci >> sges_n;
2000         rte_cio_wmb();
2001         *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
2002         rte_cio_wmb();
2003         *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
2004 #ifdef MLX5_PMD_SOFT_COUNTERS
2005         /* Increment packets counter. */
2006         rxq->stats.ipackets += i;
2007 #endif
2008         return i;
2009 }
2010
2011 /**
2012  * Dummy DPDK callback for TX.
2013  *
2014  * This function is used to temporarily replace the real callback during
2015  * unsafe control operations on the queue, or in case of error.
2016  *
2017  * @param dpdk_txq
2018  *   Generic pointer to TX queue structure.
2019  * @param[in] pkts
2020  *   Packets to transmit.
2021  * @param pkts_n
2022  *   Number of packets in array.
2023  *
2024  * @return
2025  *   Number of packets successfully transmitted (<= pkts_n).
2026  */
2027 uint16_t
2028 removed_tx_burst(void *dpdk_txq __rte_unused,
2029                  struct rte_mbuf **pkts __rte_unused,
2030                  uint16_t pkts_n __rte_unused)
2031 {
2032         return 0;
2033 }
2034
2035 /**
2036  * Dummy DPDK callback for RX.
2037  *
2038  * This function is used to temporarily replace the real callback during
2039  * unsafe control operations on the queue, or in case of error.
2040  *
2041  * @param dpdk_rxq
2042  *   Generic pointer to RX queue structure.
2043  * @param[out] pkts
2044  *   Array to store received packets.
2045  * @param pkts_n
2046  *   Maximum number of packets in array.
2047  *
2048  * @return
2049  *   Number of packets successfully received (<= pkts_n).
2050  */
2051 uint16_t
2052 removed_rx_burst(void *dpdk_txq __rte_unused,
2053                  struct rte_mbuf **pkts __rte_unused,
2054                  uint16_t pkts_n __rte_unused)
2055 {
2056         return 0;
2057 }
2058
2059 /*
2060  * Vectorized Rx/Tx routines are not compiled in when required vector
2061  * instructions are not supported on a target architecture. The following null
2062  * stubs are needed for linkage when those are not included outside of this file
2063  * (e.g.  mlx5_rxtx_vec_sse.c for x86).
2064  */
2065
2066 uint16_t __attribute__((weak))
2067 mlx5_tx_burst_raw_vec(void *dpdk_txq __rte_unused,
2068                       struct rte_mbuf **pkts __rte_unused,
2069                       uint16_t pkts_n __rte_unused)
2070 {
2071         return 0;
2072 }
2073
2074 uint16_t __attribute__((weak))
2075 mlx5_tx_burst_vec(void *dpdk_txq __rte_unused,
2076                   struct rte_mbuf **pkts __rte_unused,
2077                   uint16_t pkts_n __rte_unused)
2078 {
2079         return 0;
2080 }
2081
2082 uint16_t __attribute__((weak))
2083 mlx5_rx_burst_vec(void *dpdk_txq __rte_unused,
2084                   struct rte_mbuf **pkts __rte_unused,
2085                   uint16_t pkts_n __rte_unused)
2086 {
2087         return 0;
2088 }
2089
2090 int __attribute__((weak))
2091 mlx5_check_raw_vec_tx_support(struct rte_eth_dev *dev __rte_unused)
2092 {
2093         return -ENOTSUP;
2094 }
2095
2096 int __attribute__((weak))
2097 mlx5_check_vec_tx_support(struct rte_eth_dev *dev __rte_unused)
2098 {
2099         return -ENOTSUP;
2100 }
2101
2102 int __attribute__((weak))
2103 mlx5_rxq_check_vec_support(struct mlx5_rxq_data *rxq __rte_unused)
2104 {
2105         return -ENOTSUP;
2106 }
2107
2108 int __attribute__((weak))
2109 mlx5_check_vec_rx_support(struct rte_eth_dev *dev __rte_unused)
2110 {
2111         return -ENOTSUP;
2112 }