1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015-2019 Mellanox Technologies, Ltd
11 #include <rte_mempool.h>
12 #include <rte_prefetch.h>
13 #include <rte_common.h>
14 #include <rte_branch_prediction.h>
15 #include <rte_ether.h>
16 #include <rte_cycles.h>
20 #include <mlx5_common.h>
22 #include "mlx5_autoconf.h"
23 #include "mlx5_defs.h"
26 #include "mlx5_utils.h"
27 #include "mlx5_rxtx.h"
30 /* TX burst subroutines return codes. */
31 enum mlx5_txcmp_code {
32 MLX5_TXCMP_CODE_EXIT = 0,
33 MLX5_TXCMP_CODE_ERROR,
34 MLX5_TXCMP_CODE_SINGLE,
35 MLX5_TXCMP_CODE_MULTI,
41 * These defines are used to configure Tx burst routine option set
42 * supported at compile time. The not specified options are optimized out
43 * out due to if conditions can be explicitly calculated at compile time.
44 * The offloads with bigger runtime check (require more CPU cycles to
45 * skip) overhead should have the bigger index - this is needed to
46 * select the better matching routine function if no exact match and
47 * some offloads are not actually requested.
49 #define MLX5_TXOFF_CONFIG_MULTI (1u << 0) /* Multi-segment packets.*/
50 #define MLX5_TXOFF_CONFIG_TSO (1u << 1) /* TCP send offload supported.*/
51 #define MLX5_TXOFF_CONFIG_SWP (1u << 2) /* Tunnels/SW Parser offloads.*/
52 #define MLX5_TXOFF_CONFIG_CSUM (1u << 3) /* Check Sums offloaded. */
53 #define MLX5_TXOFF_CONFIG_INLINE (1u << 4) /* Data inlining supported. */
54 #define MLX5_TXOFF_CONFIG_VLAN (1u << 5) /* VLAN insertion supported.*/
55 #define MLX5_TXOFF_CONFIG_METADATA (1u << 6) /* Flow metadata. */
56 #define MLX5_TXOFF_CONFIG_EMPW (1u << 8) /* Enhanced MPW supported.*/
57 #define MLX5_TXOFF_CONFIG_MPW (1u << 9) /* Legacy MPW supported.*/
58 #define MLX5_TXOFF_CONFIG_TXPP (1u << 10) /* Scheduling on timestamp.*/
60 /* The most common offloads groups. */
61 #define MLX5_TXOFF_CONFIG_NONE 0
62 #define MLX5_TXOFF_CONFIG_FULL (MLX5_TXOFF_CONFIG_MULTI | \
63 MLX5_TXOFF_CONFIG_TSO | \
64 MLX5_TXOFF_CONFIG_SWP | \
65 MLX5_TXOFF_CONFIG_CSUM | \
66 MLX5_TXOFF_CONFIG_INLINE | \
67 MLX5_TXOFF_CONFIG_VLAN | \
68 MLX5_TXOFF_CONFIG_METADATA)
70 #define MLX5_TXOFF_CONFIG(mask) (olx & MLX5_TXOFF_CONFIG_##mask)
72 #define MLX5_TXOFF_DECL(func, olx) \
73 static uint16_t mlx5_tx_burst_##func(void *txq, \
74 struct rte_mbuf **pkts, \
77 return mlx5_tx_burst_tmpl((struct mlx5_txq_data *)txq, \
78 pkts, pkts_n, (olx)); \
81 #define MLX5_TXOFF_INFO(func, olx) {mlx5_tx_burst_##func, olx},
84 static_assert(MLX5_CQE_STATUS_HW_OWN < 0, "Must be negative value");
85 static_assert(MLX5_CQE_STATUS_SW_OWN < 0, "Must be negative value");
86 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
88 sizeof(rte_v128u32_t)),
89 "invalid Ethernet Segment data size");
90 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
92 sizeof(struct rte_vlan_hdr) +
93 2 * RTE_ETHER_ADDR_LEN),
94 "invalid Ethernet Segment data size");
95 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
97 sizeof(rte_v128u32_t)),
98 "invalid Ethernet Segment data size");
99 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
101 sizeof(struct rte_vlan_hdr) +
102 2 * RTE_ETHER_ADDR_LEN),
103 "invalid Ethernet Segment data size");
104 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
106 sizeof(rte_v128u32_t)),
107 "invalid Ethernet Segment data size");
108 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
110 sizeof(struct rte_vlan_hdr) +
111 2 * RTE_ETHER_ADDR_LEN),
112 "invalid Ethernet Segment data size");
113 static_assert(MLX5_DSEG_MIN_INLINE_SIZE ==
114 (2 * RTE_ETHER_ADDR_LEN),
115 "invalid Data Segment data size");
116 static_assert(MLX5_EMPW_MIN_PACKETS >= 2, "invalid min size");
117 static_assert(MLX5_EMPW_MIN_PACKETS >= 2, "invalid min size");
118 static_assert((sizeof(struct rte_vlan_hdr) +
119 sizeof(struct rte_ether_hdr)) ==
120 MLX5_ESEG_MIN_INLINE_SIZE,
121 "invalid min inline data size");
122 static_assert(MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE <=
123 MLX5_DSEG_MAX, "invalid WQE max size");
124 static_assert(MLX5_WQE_CSEG_SIZE == MLX5_WSEG_SIZE,
125 "invalid WQE Control Segment size");
126 static_assert(MLX5_WQE_ESEG_SIZE == MLX5_WSEG_SIZE,
127 "invalid WQE Ethernet Segment size");
128 static_assert(MLX5_WQE_DSEG_SIZE == MLX5_WSEG_SIZE,
129 "invalid WQE Data Segment size");
130 static_assert(MLX5_WQE_SIZE == 4 * MLX5_WSEG_SIZE,
133 static __rte_always_inline uint32_t
134 rxq_cq_to_pkt_type(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
135 volatile struct mlx5_mini_cqe8 *mcqe);
137 static __rte_always_inline int
138 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
139 uint16_t cqe_cnt, volatile struct mlx5_mini_cqe8 **mcqe);
141 static __rte_always_inline uint32_t
142 rxq_cq_to_ol_flags(volatile struct mlx5_cqe *cqe);
144 static __rte_always_inline void
145 rxq_cq_to_mbuf(struct mlx5_rxq_data *rxq, struct rte_mbuf *pkt,
146 volatile struct mlx5_cqe *cqe,
147 volatile struct mlx5_mini_cqe8 *mcqe);
150 mlx5_queue_state_modify(struct rte_eth_dev *dev,
151 struct mlx5_mp_arg_queue_state_modify *sm);
154 mlx5_lro_update_tcp_hdr(struct rte_tcp_hdr *__rte_restrict tcp,
155 volatile struct mlx5_cqe *__rte_restrict cqe,
156 uint32_t phcsum, uint8_t l4_type);
159 mlx5_lro_update_hdr(uint8_t *__rte_restrict padd,
160 volatile struct mlx5_cqe *__rte_restrict cqe,
161 volatile struct mlx5_mini_cqe8 *mcqe,
162 struct mlx5_rxq_data *rxq, uint32_t len);
164 uint32_t mlx5_ptype_table[] __rte_cache_aligned = {
165 [0xff] = RTE_PTYPE_ALL_MASK, /* Last entry for errored packet. */
168 uint8_t mlx5_cksum_table[1 << 10] __rte_cache_aligned;
169 uint8_t mlx5_swp_types_table[1 << 10] __rte_cache_aligned;
171 uint64_t rte_net_mlx5_dynf_inline_mask;
172 #define PKT_TX_DYNF_NOINLINE rte_net_mlx5_dynf_inline_mask
175 * Build a table to translate Rx completion flags to packet type.
177 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
180 mlx5_set_ptype_table(void)
183 uint32_t (*p)[RTE_DIM(mlx5_ptype_table)] = &mlx5_ptype_table;
185 /* Last entry must not be overwritten, reserved for errored packet. */
186 for (i = 0; i < RTE_DIM(mlx5_ptype_table) - 1; ++i)
187 (*p)[i] = RTE_PTYPE_UNKNOWN;
189 * The index to the array should have:
190 * bit[1:0] = l3_hdr_type
191 * bit[4:2] = l4_hdr_type
194 * bit[7] = outer_l3_type
197 (*p)[0x00] = RTE_PTYPE_L2_ETHER;
199 (*p)[0x01] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
200 RTE_PTYPE_L4_NONFRAG;
201 (*p)[0x02] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
202 RTE_PTYPE_L4_NONFRAG;
204 (*p)[0x21] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
206 (*p)[0x22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
209 (*p)[0x05] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
211 (*p)[0x06] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
213 (*p)[0x0d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
215 (*p)[0x0e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
217 (*p)[0x11] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
219 (*p)[0x12] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
222 (*p)[0x09] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
224 (*p)[0x0a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
226 /* Repeat with outer_l3_type being set. Just in case. */
227 (*p)[0x81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
228 RTE_PTYPE_L4_NONFRAG;
229 (*p)[0x82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
230 RTE_PTYPE_L4_NONFRAG;
231 (*p)[0xa1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
233 (*p)[0xa2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
235 (*p)[0x85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
237 (*p)[0x86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
239 (*p)[0x8d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
241 (*p)[0x8e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
243 (*p)[0x91] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
245 (*p)[0x92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
247 (*p)[0x89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
249 (*p)[0x8a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
252 (*p)[0x40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
253 (*p)[0x41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
254 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
255 RTE_PTYPE_INNER_L4_NONFRAG;
256 (*p)[0x42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
257 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
258 RTE_PTYPE_INNER_L4_NONFRAG;
259 (*p)[0xc0] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
260 (*p)[0xc1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
261 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
262 RTE_PTYPE_INNER_L4_NONFRAG;
263 (*p)[0xc2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
264 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
265 RTE_PTYPE_INNER_L4_NONFRAG;
266 /* Tunneled - Fragmented */
267 (*p)[0x61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
268 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
269 RTE_PTYPE_INNER_L4_FRAG;
270 (*p)[0x62] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
271 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
272 RTE_PTYPE_INNER_L4_FRAG;
273 (*p)[0xe1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
274 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
275 RTE_PTYPE_INNER_L4_FRAG;
276 (*p)[0xe2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
277 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
278 RTE_PTYPE_INNER_L4_FRAG;
280 (*p)[0x45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
281 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
282 RTE_PTYPE_INNER_L4_TCP;
283 (*p)[0x46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
284 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
285 RTE_PTYPE_INNER_L4_TCP;
286 (*p)[0x4d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
287 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
288 RTE_PTYPE_INNER_L4_TCP;
289 (*p)[0x4e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
290 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
291 RTE_PTYPE_INNER_L4_TCP;
292 (*p)[0x51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
293 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
294 RTE_PTYPE_INNER_L4_TCP;
295 (*p)[0x52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
296 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
297 RTE_PTYPE_INNER_L4_TCP;
298 (*p)[0xc5] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
299 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
300 RTE_PTYPE_INNER_L4_TCP;
301 (*p)[0xc6] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
302 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
303 RTE_PTYPE_INNER_L4_TCP;
304 (*p)[0xcd] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
305 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
306 RTE_PTYPE_INNER_L4_TCP;
307 (*p)[0xce] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
308 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
309 RTE_PTYPE_INNER_L4_TCP;
310 (*p)[0xd1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
311 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
312 RTE_PTYPE_INNER_L4_TCP;
313 (*p)[0xd2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
314 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
315 RTE_PTYPE_INNER_L4_TCP;
317 (*p)[0x49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
318 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
319 RTE_PTYPE_INNER_L4_UDP;
320 (*p)[0x4a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
321 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
322 RTE_PTYPE_INNER_L4_UDP;
323 (*p)[0xc9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
324 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
325 RTE_PTYPE_INNER_L4_UDP;
326 (*p)[0xca] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
327 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
328 RTE_PTYPE_INNER_L4_UDP;
332 * Build a table to translate packet to checksum type of Verbs.
335 mlx5_set_cksum_table(void)
341 * The index should have:
342 * bit[0] = PKT_TX_TCP_SEG
343 * bit[2:3] = PKT_TX_UDP_CKSUM, PKT_TX_TCP_CKSUM
344 * bit[4] = PKT_TX_IP_CKSUM
345 * bit[8] = PKT_TX_OUTER_IP_CKSUM
348 for (i = 0; i < RTE_DIM(mlx5_cksum_table); ++i) {
351 /* Tunneled packet. */
352 if (i & (1 << 8)) /* Outer IP. */
353 v |= MLX5_ETH_WQE_L3_CSUM;
354 if (i & (1 << 4)) /* Inner IP. */
355 v |= MLX5_ETH_WQE_L3_INNER_CSUM;
356 if (i & (3 << 2 | 1 << 0)) /* L4 or TSO. */
357 v |= MLX5_ETH_WQE_L4_INNER_CSUM;
360 if (i & (1 << 4)) /* IP. */
361 v |= MLX5_ETH_WQE_L3_CSUM;
362 if (i & (3 << 2 | 1 << 0)) /* L4 or TSO. */
363 v |= MLX5_ETH_WQE_L4_CSUM;
365 mlx5_cksum_table[i] = v;
370 * Build a table to translate packet type of mbuf to SWP type of Verbs.
373 mlx5_set_swp_types_table(void)
379 * The index should have:
380 * bit[0:1] = PKT_TX_L4_MASK
381 * bit[4] = PKT_TX_IPV6
382 * bit[8] = PKT_TX_OUTER_IPV6
383 * bit[9] = PKT_TX_OUTER_UDP
385 for (i = 0; i < RTE_DIM(mlx5_swp_types_table); ++i) {
388 v |= MLX5_ETH_WQE_L3_OUTER_IPV6;
390 v |= MLX5_ETH_WQE_L4_OUTER_UDP;
392 v |= MLX5_ETH_WQE_L3_INNER_IPV6;
393 if ((i & 3) == (PKT_TX_UDP_CKSUM >> 52))
394 v |= MLX5_ETH_WQE_L4_INNER_UDP;
395 mlx5_swp_types_table[i] = v;
400 * Set Software Parser flags and offsets in Ethernet Segment of WQE.
401 * Flags must be preliminary initialized to zero.
404 * Pointer to burst routine local context.
406 * Pointer to store Software Parser flags
408 * Configured Tx offloads mask. It is fully defined at
409 * compile time and may be used for optimization.
412 * Software Parser offsets packed in dword.
413 * Software Parser flags are set by pointer.
415 static __rte_always_inline uint32_t
416 txq_mbuf_to_swp(struct mlx5_txq_local *__rte_restrict loc,
421 unsigned int idx, off;
424 if (!MLX5_TXOFF_CONFIG(SWP))
426 ol = loc->mbuf->ol_flags;
427 tunnel = ol & PKT_TX_TUNNEL_MASK;
429 * Check whether Software Parser is required.
430 * Only customized tunnels may ask for.
432 if (likely(tunnel != PKT_TX_TUNNEL_UDP && tunnel != PKT_TX_TUNNEL_IP))
435 * The index should have:
436 * bit[0:1] = PKT_TX_L4_MASK
437 * bit[4] = PKT_TX_IPV6
438 * bit[8] = PKT_TX_OUTER_IPV6
439 * bit[9] = PKT_TX_OUTER_UDP
441 idx = (ol & (PKT_TX_L4_MASK | PKT_TX_IPV6 | PKT_TX_OUTER_IPV6)) >> 52;
442 idx |= (tunnel == PKT_TX_TUNNEL_UDP) ? (1 << 9) : 0;
443 *swp_flags = mlx5_swp_types_table[idx];
445 * Set offsets for SW parser. Since ConnectX-5, SW parser just
446 * complements HW parser. SW parser starts to engage only if HW parser
447 * can't reach a header. For the older devices, HW parser will not kick
448 * in if any of SWP offsets is set. Therefore, all of the L3 offsets
449 * should be set regardless of HW offload.
451 off = loc->mbuf->outer_l2_len;
452 if (MLX5_TXOFF_CONFIG(VLAN) && ol & PKT_TX_VLAN_PKT)
453 off += sizeof(struct rte_vlan_hdr);
454 set = (off >> 1) << 8; /* Outer L3 offset. */
455 off += loc->mbuf->outer_l3_len;
456 if (tunnel == PKT_TX_TUNNEL_UDP)
457 set |= off >> 1; /* Outer L4 offset. */
458 if (ol & (PKT_TX_IPV4 | PKT_TX_IPV6)) { /* Inner IP. */
459 const uint64_t csum = ol & PKT_TX_L4_MASK;
460 off += loc->mbuf->l2_len;
461 set |= (off >> 1) << 24; /* Inner L3 offset. */
462 if (csum == PKT_TX_TCP_CKSUM ||
463 csum == PKT_TX_UDP_CKSUM ||
464 (MLX5_TXOFF_CONFIG(TSO) && ol & PKT_TX_TCP_SEG)) {
465 off += loc->mbuf->l3_len;
466 set |= (off >> 1) << 16; /* Inner L4 offset. */
469 set = rte_cpu_to_le_32(set);
474 * Convert the Checksum offloads to Verbs.
477 * Pointer to the mbuf.
480 * Converted checksum flags.
482 static __rte_always_inline uint8_t
483 txq_ol_cksum_to_cs(struct rte_mbuf *buf)
486 uint8_t is_tunnel = !!(buf->ol_flags & PKT_TX_TUNNEL_MASK);
487 const uint64_t ol_flags_mask = PKT_TX_TCP_SEG | PKT_TX_L4_MASK |
488 PKT_TX_IP_CKSUM | PKT_TX_OUTER_IP_CKSUM;
491 * The index should have:
492 * bit[0] = PKT_TX_TCP_SEG
493 * bit[2:3] = PKT_TX_UDP_CKSUM, PKT_TX_TCP_CKSUM
494 * bit[4] = PKT_TX_IP_CKSUM
495 * bit[8] = PKT_TX_OUTER_IP_CKSUM
498 idx = ((buf->ol_flags & ol_flags_mask) >> 50) | (!!is_tunnel << 9);
499 return mlx5_cksum_table[idx];
503 * Internal function to compute the number of used descriptors in an RX queue
509 * The number of used rx descriptor.
512 rx_queue_count(struct mlx5_rxq_data *rxq)
514 struct rxq_zip *zip = &rxq->zip;
515 volatile struct mlx5_cqe *cqe;
516 const unsigned int cqe_n = (1 << rxq->cqe_n);
517 const unsigned int sges_n = (1 << rxq->sges_n);
518 const unsigned int elts_n = (1 << rxq->elts_n);
519 const unsigned int strd_n = (1 << rxq->strd_num_n);
520 const unsigned int cqe_cnt = cqe_n - 1;
521 unsigned int cq_ci, used;
523 /* if we are processing a compressed cqe */
525 used = zip->cqe_cnt - zip->ai;
531 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
532 while (check_cqe(cqe, cqe_n, cq_ci) != MLX5_CQE_STATUS_HW_OWN) {
536 op_own = cqe->op_own;
537 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED)
538 n = rte_be_to_cpu_32(cqe->byte_cnt);
543 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
545 used = RTE_MIN(used * sges_n, elts_n * strd_n);
550 * DPDK callback to check the status of a rx descriptor.
555 * The index of the descriptor in the ring.
558 * The status of the tx descriptor.
561 mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset)
563 struct mlx5_rxq_data *rxq = rx_queue;
564 struct mlx5_rxq_ctrl *rxq_ctrl =
565 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
566 struct rte_eth_dev *dev = ETH_DEV(rxq_ctrl->priv);
568 if (dev->rx_pkt_burst == NULL ||
569 dev->rx_pkt_burst == removed_rx_burst) {
573 if (offset >= (1 << rxq->cqe_n)) {
577 if (offset < rx_queue_count(rxq))
578 return RTE_ETH_RX_DESC_DONE;
579 return RTE_ETH_RX_DESC_AVAIL;
583 * DPDK callback to get the RX queue information
586 * Pointer to the device structure.
589 * Rx queue identificator.
592 * Pointer to the RX queue information structure.
599 mlx5_rxq_info_get(struct rte_eth_dev *dev, uint16_t rx_queue_id,
600 struct rte_eth_rxq_info *qinfo)
602 struct mlx5_priv *priv = dev->data->dev_private;
603 struct mlx5_rxq_data *rxq = (*priv->rxqs)[rx_queue_id];
604 struct mlx5_rxq_ctrl *rxq_ctrl =
605 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
609 qinfo->mp = mlx5_rxq_mprq_enabled(rxq) ?
610 rxq->mprq_mp : rxq->mp;
611 qinfo->conf.rx_thresh.pthresh = 0;
612 qinfo->conf.rx_thresh.hthresh = 0;
613 qinfo->conf.rx_thresh.wthresh = 0;
614 qinfo->conf.rx_free_thresh = rxq->rq_repl_thresh;
615 qinfo->conf.rx_drop_en = 1;
616 qinfo->conf.rx_deferred_start = rxq_ctrl ? 0 : 1;
617 qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads;
618 qinfo->scattered_rx = dev->data->scattered_rx;
619 qinfo->nb_desc = mlx5_rxq_mprq_enabled(rxq) ?
620 (1 << rxq->elts_n) * (1 << rxq->strd_num_n) :
625 * DPDK callback to get the RX packet burst mode information
628 * Pointer to the device structure.
631 * Rx queue identificatior.
634 * Pointer to the burts mode information.
637 * 0 as success, -EINVAL as failure.
641 mlx5_rx_burst_mode_get(struct rte_eth_dev *dev,
642 uint16_t rx_queue_id __rte_unused,
643 struct rte_eth_burst_mode *mode)
645 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
646 struct mlx5_priv *priv = dev->data->dev_private;
647 struct mlx5_rxq_data *rxq;
649 rxq = (*priv->rxqs)[rx_queue_id];
654 if (pkt_burst == mlx5_rx_burst) {
655 snprintf(mode->info, sizeof(mode->info), "%s", "Scalar");
656 } else if (pkt_burst == mlx5_rx_burst_mprq) {
657 snprintf(mode->info, sizeof(mode->info), "%s", "Multi-Packet RQ");
658 } else if (pkt_burst == mlx5_rx_burst_vec) {
659 #if defined RTE_ARCH_X86_64
660 snprintf(mode->info, sizeof(mode->info), "%s", "Vector SSE");
661 #elif defined RTE_ARCH_ARM64
662 snprintf(mode->info, sizeof(mode->info), "%s", "Vector Neon");
663 #elif defined RTE_ARCH_PPC_64
664 snprintf(mode->info, sizeof(mode->info), "%s", "Vector AltiVec");
668 } else if (pkt_burst == mlx5_rx_burst_mprq_vec) {
669 #if defined RTE_ARCH_X86_64
670 snprintf(mode->info, sizeof(mode->info), "%s", "MPRQ Vector SSE");
671 #elif defined RTE_ARCH_ARM64
672 snprintf(mode->info, sizeof(mode->info), "%s", "MPRQ Vector Neon");
673 #elif defined RTE_ARCH_PPC_64
674 snprintf(mode->info, sizeof(mode->info), "%s", "MPRQ Vector AltiVec");
685 * DPDK callback to get the number of used descriptors in a RX queue
688 * Pointer to the device structure.
694 * The number of used rx descriptor.
695 * -EINVAL if the queue is invalid
698 mlx5_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
700 struct mlx5_priv *priv = dev->data->dev_private;
701 struct mlx5_rxq_data *rxq;
703 if (dev->rx_pkt_burst == NULL ||
704 dev->rx_pkt_burst == removed_rx_burst) {
708 rxq = (*priv->rxqs)[rx_queue_id];
713 return rx_queue_count(rxq);
716 #define MLX5_SYSTEM_LOG_DIR "/var/log"
718 * Dump debug information to log file.
723 * If not NULL this string is printed as a header to the output
724 * and the output will be in hexadecimal view.
726 * This is the buffer address to print out.
728 * The number of bytes to dump out.
731 mlx5_dump_debug_information(const char *fname, const char *hex_title,
732 const void *buf, unsigned int hex_len)
736 MKSTR(path, "%s/%s", MLX5_SYSTEM_LOG_DIR, fname);
737 fd = fopen(path, "a+");
739 DRV_LOG(WARNING, "cannot open %s for debug dump", path);
740 MKSTR(path2, "./%s", fname);
741 fd = fopen(path2, "a+");
743 DRV_LOG(ERR, "cannot open %s for debug dump", path2);
746 DRV_LOG(INFO, "New debug dump in file %s", path2);
748 DRV_LOG(INFO, "New debug dump in file %s", path);
751 rte_hexdump(fd, hex_title, buf, hex_len);
753 fprintf(fd, "%s", (const char *)buf);
754 fprintf(fd, "\n\n\n");
759 * Move QP from error state to running state and initialize indexes.
762 * Pointer to TX queue control structure.
765 * 0 on success, else -1.
768 tx_recover_qp(struct mlx5_txq_ctrl *txq_ctrl)
770 struct mlx5_mp_arg_queue_state_modify sm = {
772 .queue_id = txq_ctrl->txq.idx,
775 if (mlx5_queue_state_modify(ETH_DEV(txq_ctrl->priv), &sm))
777 txq_ctrl->txq.wqe_ci = 0;
778 txq_ctrl->txq.wqe_pi = 0;
779 txq_ctrl->txq.elts_comp = 0;
783 /* Return 1 if the error CQE is signed otherwise, sign it and return 0. */
785 check_err_cqe_seen(volatile struct mlx5_err_cqe *err_cqe)
787 static const uint8_t magic[] = "seen";
791 for (i = 0; i < sizeof(magic); ++i)
792 if (!ret || err_cqe->rsvd1[i] != magic[i]) {
794 err_cqe->rsvd1[i] = magic[i];
803 * Pointer to TX queue structure.
805 * Pointer to the error CQE.
808 * Negative value if queue recovery failed, otherwise
809 * the error completion entry is handled successfully.
812 mlx5_tx_error_cqe_handle(struct mlx5_txq_data *__rte_restrict txq,
813 volatile struct mlx5_err_cqe *err_cqe)
815 if (err_cqe->syndrome != MLX5_CQE_SYNDROME_WR_FLUSH_ERR) {
816 const uint16_t wqe_m = ((1 << txq->wqe_n) - 1);
817 struct mlx5_txq_ctrl *txq_ctrl =
818 container_of(txq, struct mlx5_txq_ctrl, txq);
819 uint16_t new_wqe_pi = rte_be_to_cpu_16(err_cqe->wqe_counter);
820 int seen = check_err_cqe_seen(err_cqe);
822 if (!seen && txq_ctrl->dump_file_n <
823 txq_ctrl->priv->config.max_dump_files_num) {
824 MKSTR(err_str, "Unexpected CQE error syndrome "
825 "0x%02x CQN = %u SQN = %u wqe_counter = %u "
826 "wq_ci = %u cq_ci = %u", err_cqe->syndrome,
827 txq->cqe_s, txq->qp_num_8s >> 8,
828 rte_be_to_cpu_16(err_cqe->wqe_counter),
829 txq->wqe_ci, txq->cq_ci);
830 MKSTR(name, "dpdk_mlx5_port_%u_txq_%u_index_%u_%u",
831 PORT_ID(txq_ctrl->priv), txq->idx,
832 txq_ctrl->dump_file_n, (uint32_t)rte_rdtsc());
833 mlx5_dump_debug_information(name, NULL, err_str, 0);
834 mlx5_dump_debug_information(name, "MLX5 Error CQ:",
835 (const void *)((uintptr_t)
839 mlx5_dump_debug_information(name, "MLX5 Error SQ:",
840 (const void *)((uintptr_t)
844 txq_ctrl->dump_file_n++;
848 * Count errors in WQEs units.
849 * Later it can be improved to count error packets,
850 * for example, by SQ parsing to find how much packets
851 * should be counted for each WQE.
853 txq->stats.oerrors += ((txq->wqe_ci & wqe_m) -
855 if (tx_recover_qp(txq_ctrl)) {
856 /* Recovering failed - retry later on the same WQE. */
859 /* Release all the remaining buffers. */
860 txq_free_elts(txq_ctrl);
866 * Translate RX completion flags to packet type.
869 * Pointer to RX queue structure.
873 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
876 * Packet type for struct rte_mbuf.
878 static inline uint32_t
879 rxq_cq_to_pkt_type(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
880 volatile struct mlx5_mini_cqe8 *mcqe)
884 uint8_t pinfo = (cqe->pkt_info & 0x3) << 6;
886 /* Get l3/l4 header from mini-CQE in case L3/L4 format*/
888 rxq->mcqe_format != MLX5_CQE_RESP_FORMAT_L34H_STRIDX)
889 ptype = (cqe->hdr_type_etc & 0xfc00) >> 10;
891 ptype = mcqe->hdr_type >> 2;
893 * The index to the array should have:
894 * bit[1:0] = l3_hdr_type
895 * bit[4:2] = l4_hdr_type
898 * bit[7] = outer_l3_type
901 return mlx5_ptype_table[idx] | rxq->tunnel * !!(idx & (1 << 6));
905 * Initialize Rx WQ and indexes.
908 * Pointer to RX queue structure.
911 mlx5_rxq_initialize(struct mlx5_rxq_data *rxq)
913 const unsigned int wqe_n = 1 << rxq->elts_n;
916 for (i = 0; (i != wqe_n); ++i) {
917 volatile struct mlx5_wqe_data_seg *scat;
921 if (mlx5_rxq_mprq_enabled(rxq)) {
922 struct mlx5_mprq_buf *buf = (*rxq->mprq_bufs)[i];
924 scat = &((volatile struct mlx5_wqe_mprq *)
926 addr = (uintptr_t)mlx5_mprq_buf_addr(buf,
927 1 << rxq->strd_num_n);
928 byte_count = (1 << rxq->strd_sz_n) *
929 (1 << rxq->strd_num_n);
931 struct rte_mbuf *buf = (*rxq->elts)[i];
933 scat = &((volatile struct mlx5_wqe_data_seg *)
935 addr = rte_pktmbuf_mtod(buf, uintptr_t);
936 byte_count = DATA_LEN(buf);
938 /* scat->addr must be able to store a pointer. */
939 MLX5_ASSERT(sizeof(scat->addr) >= sizeof(uintptr_t));
940 *scat = (struct mlx5_wqe_data_seg){
941 .addr = rte_cpu_to_be_64(addr),
942 .byte_count = rte_cpu_to_be_32(byte_count),
943 .lkey = mlx5_rx_addr2mr(rxq, addr),
946 rxq->consumed_strd = 0;
947 rxq->decompressed = 0;
949 rxq->zip = (struct rxq_zip){
952 rxq->elts_ci = mlx5_rxq_mprq_enabled(rxq) ?
953 (wqe_n >> rxq->sges_n) * (1 << rxq->strd_num_n) : 0;
954 /* Update doorbell counter. */
955 rxq->rq_ci = wqe_n >> rxq->sges_n;
957 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
961 * Modify a Verbs/DevX queue state.
962 * This must be called from the primary process.
965 * Pointer to Ethernet device.
967 * State modify request parameters.
970 * 0 in case of success else non-zero value and rte_errno is set.
973 mlx5_queue_state_modify_primary(struct rte_eth_dev *dev,
974 const struct mlx5_mp_arg_queue_state_modify *sm)
977 struct mlx5_priv *priv = dev->data->dev_private;
980 struct mlx5_rxq_data *rxq = (*priv->rxqs)[sm->queue_id];
981 struct mlx5_rxq_ctrl *rxq_ctrl =
982 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
984 ret = priv->obj_ops.rxq_obj_modify(rxq_ctrl->obj, sm->state);
986 DRV_LOG(ERR, "Cannot change Rx WQ state to %u - %s",
987 sm->state, strerror(errno));
992 struct mlx5_txq_data *txq = (*priv->txqs)[sm->queue_id];
993 struct mlx5_txq_ctrl *txq_ctrl =
994 container_of(txq, struct mlx5_txq_ctrl, txq);
996 ret = priv->obj_ops.txq_obj_modify(txq_ctrl->obj,
997 MLX5_TXQ_MOD_ERR2RDY,
998 (uint8_t)priv->dev_port);
1006 * Modify a Verbs queue state.
1009 * Pointer to Ethernet device.
1011 * State modify request parameters.
1014 * 0 in case of success else non-zero value.
1017 mlx5_queue_state_modify(struct rte_eth_dev *dev,
1018 struct mlx5_mp_arg_queue_state_modify *sm)
1020 struct mlx5_priv *priv = dev->data->dev_private;
1023 switch (rte_eal_process_type()) {
1024 case RTE_PROC_PRIMARY:
1025 ret = mlx5_queue_state_modify_primary(dev, sm);
1027 case RTE_PROC_SECONDARY:
1028 ret = mlx5_mp_req_queue_state_modify(&priv->mp_id, sm);
1037 * Handle a Rx error.
1038 * The function inserts the RQ state to reset when the first error CQE is
1039 * shown, then drains the CQ by the caller function loop. When the CQ is empty,
1040 * it moves the RQ state to ready and initializes the RQ.
1041 * Next CQE identification and error counting are in the caller responsibility.
1044 * Pointer to RX queue structure.
1046 * 1 when called from vectorized Rx burst, need to prepare mbufs for the RQ.
1047 * 0 when called from non-vectorized Rx burst.
1050 * -1 in case of recovery error, otherwise the CQE status.
1053 mlx5_rx_err_handle(struct mlx5_rxq_data *rxq, uint8_t vec)
1055 const uint16_t cqe_n = 1 << rxq->cqe_n;
1056 const uint16_t cqe_mask = cqe_n - 1;
1057 const uint16_t wqe_n = 1 << rxq->elts_n;
1058 const uint16_t strd_n = 1 << rxq->strd_num_n;
1059 struct mlx5_rxq_ctrl *rxq_ctrl =
1060 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
1062 volatile struct mlx5_cqe *cqe;
1063 volatile struct mlx5_err_cqe *err_cqe;
1065 .cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_mask],
1067 struct mlx5_mp_arg_queue_state_modify sm;
1070 switch (rxq->err_state) {
1071 case MLX5_RXQ_ERR_STATE_NO_ERROR:
1072 rxq->err_state = MLX5_RXQ_ERR_STATE_NEED_RESET;
1074 case MLX5_RXQ_ERR_STATE_NEED_RESET:
1076 sm.queue_id = rxq->idx;
1077 sm.state = IBV_WQS_RESET;
1078 if (mlx5_queue_state_modify(ETH_DEV(rxq_ctrl->priv), &sm))
1080 if (rxq_ctrl->dump_file_n <
1081 rxq_ctrl->priv->config.max_dump_files_num) {
1082 MKSTR(err_str, "Unexpected CQE error syndrome "
1083 "0x%02x CQN = %u RQN = %u wqe_counter = %u"
1084 " rq_ci = %u cq_ci = %u", u.err_cqe->syndrome,
1085 rxq->cqn, rxq_ctrl->wqn,
1086 rte_be_to_cpu_16(u.err_cqe->wqe_counter),
1087 rxq->rq_ci << rxq->sges_n, rxq->cq_ci);
1088 MKSTR(name, "dpdk_mlx5_port_%u_rxq_%u_%u",
1089 rxq->port_id, rxq->idx, (uint32_t)rte_rdtsc());
1090 mlx5_dump_debug_information(name, NULL, err_str, 0);
1091 mlx5_dump_debug_information(name, "MLX5 Error CQ:",
1092 (const void *)((uintptr_t)
1094 sizeof(*u.cqe) * cqe_n);
1095 mlx5_dump_debug_information(name, "MLX5 Error RQ:",
1096 (const void *)((uintptr_t)
1099 rxq_ctrl->dump_file_n++;
1101 rxq->err_state = MLX5_RXQ_ERR_STATE_NEED_READY;
1103 case MLX5_RXQ_ERR_STATE_NEED_READY:
1104 ret = check_cqe(u.cqe, cqe_n, rxq->cq_ci);
1105 if (ret == MLX5_CQE_STATUS_HW_OWN) {
1107 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
1110 * The RQ consumer index must be zeroed while moving
1111 * from RESET state to RDY state.
1113 *rxq->rq_db = rte_cpu_to_be_32(0);
1116 sm.queue_id = rxq->idx;
1117 sm.state = IBV_WQS_RDY;
1118 if (mlx5_queue_state_modify(ETH_DEV(rxq_ctrl->priv),
1122 const uint32_t elts_n =
1123 mlx5_rxq_mprq_enabled(rxq) ?
1124 wqe_n * strd_n : wqe_n;
1125 const uint32_t e_mask = elts_n - 1;
1127 mlx5_rxq_mprq_enabled(rxq) ?
1128 rxq->elts_ci : rxq->rq_ci;
1130 struct rte_mbuf **elt;
1132 unsigned int n = elts_n - (elts_ci -
1135 for (i = 0; i < (int)n; ++i) {
1136 elt_idx = (elts_ci + i) & e_mask;
1137 elt = &(*rxq->elts)[elt_idx];
1138 *elt = rte_mbuf_raw_alloc(rxq->mp);
1140 for (i--; i >= 0; --i) {
1141 elt_idx = (elts_ci +
1145 rte_pktmbuf_free_seg
1151 for (i = 0; i < (int)elts_n; ++i) {
1152 elt = &(*rxq->elts)[i];
1154 (uint16_t)((*elt)->buf_len -
1155 rte_pktmbuf_headroom(*elt));
1157 /* Padding with a fake mbuf for vec Rx. */
1158 for (i = 0; i < MLX5_VPMD_DESCS_PER_LOOP; ++i)
1159 (*rxq->elts)[elts_n + i] =
1162 mlx5_rxq_initialize(rxq);
1163 rxq->err_state = MLX5_RXQ_ERR_STATE_NO_ERROR;
1172 * Get size of the next packet for a given CQE. For compressed CQEs, the
1173 * consumer index is updated only once all packets of the current one have
1177 * Pointer to RX queue.
1181 * Store pointer to mini-CQE if compressed. Otherwise, the pointer is not
1185 * 0 in case of empty CQE, otherwise the packet size in bytes.
1188 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
1189 uint16_t cqe_cnt, volatile struct mlx5_mini_cqe8 **mcqe)
1191 struct rxq_zip *zip = &rxq->zip;
1192 uint16_t cqe_n = cqe_cnt + 1;
1198 /* Process compressed data in the CQE and mini arrays. */
1200 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1201 (volatile struct mlx5_mini_cqe8 (*)[8])
1202 (uintptr_t)(&(*rxq->cqes)[zip->ca &
1204 len = rte_be_to_cpu_32((*mc)[zip->ai & 7].byte_cnt &
1206 *mcqe = &(*mc)[zip->ai & 7];
1207 if ((++zip->ai & 7) == 0) {
1208 /* Invalidate consumed CQEs */
1211 while (idx != end) {
1212 (*rxq->cqes)[idx & cqe_cnt].op_own =
1213 MLX5_CQE_INVALIDATE;
1217 * Increment consumer index to skip the number
1218 * of CQEs consumed. Hardware leaves holes in
1219 * the CQ ring for software use.
1224 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1225 /* Invalidate the rest */
1229 while (idx != end) {
1230 (*rxq->cqes)[idx & cqe_cnt].op_own =
1231 MLX5_CQE_INVALIDATE;
1234 rxq->cq_ci = zip->cq_ci;
1238 * No compressed data, get next CQE and verify if it is
1246 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1247 if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) {
1248 if (unlikely(ret == MLX5_CQE_STATUS_ERR ||
1250 ret = mlx5_rx_err_handle(rxq, 0);
1251 if (ret == MLX5_CQE_STATUS_HW_OWN ||
1259 * Introduce the local variable to have queue cq_ci
1260 * index in queue structure always consistent with
1261 * actual CQE boundary (not pointing to the middle
1262 * of compressed CQE session).
1264 cq_ci = rxq->cq_ci + 1;
1265 op_own = cqe->op_own;
1266 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1267 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1268 (volatile struct mlx5_mini_cqe8 (*)[8])
1269 (uintptr_t)(&(*rxq->cqes)
1270 [cq_ci & cqe_cnt].pkt_info);
1272 /* Fix endianness. */
1273 zip->cqe_cnt = rte_be_to_cpu_32(cqe->byte_cnt);
1275 * Current mini array position is the one
1276 * returned by check_cqe64().
1278 * If completion comprises several mini arrays,
1279 * as a special case the second one is located
1280 * 7 CQEs after the initial CQE instead of 8
1281 * for subsequent ones.
1284 zip->na = zip->ca + 7;
1285 /* Compute the next non compressed CQE. */
1286 zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1287 /* Get packet size to return. */
1288 len = rte_be_to_cpu_32((*mc)[0].byte_cnt &
1292 /* Prefetch all to be invalidated */
1295 while (idx != end) {
1296 rte_prefetch0(&(*rxq->cqes)[(idx) &
1302 len = rte_be_to_cpu_32(cqe->byte_cnt);
1305 if (unlikely(rxq->err_state)) {
1306 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1307 ++rxq->stats.idropped;
1315 * Translate RX completion flags to offload flags.
1321 * Offload flags (ol_flags) for struct rte_mbuf.
1323 static inline uint32_t
1324 rxq_cq_to_ol_flags(volatile struct mlx5_cqe *cqe)
1326 uint32_t ol_flags = 0;
1327 uint16_t flags = rte_be_to_cpu_16(cqe->hdr_type_etc);
1331 MLX5_CQE_RX_L3_HDR_VALID,
1332 PKT_RX_IP_CKSUM_GOOD) |
1334 MLX5_CQE_RX_L4_HDR_VALID,
1335 PKT_RX_L4_CKSUM_GOOD);
1340 * Fill in mbuf fields from RX completion flags.
1341 * Note that pkt->ol_flags should be initialized outside of this function.
1344 * Pointer to RX queue.
1349 * @param rss_hash_res
1350 * Packet RSS Hash result.
1353 rxq_cq_to_mbuf(struct mlx5_rxq_data *rxq, struct rte_mbuf *pkt,
1354 volatile struct mlx5_cqe *cqe,
1355 volatile struct mlx5_mini_cqe8 *mcqe)
1357 /* Update packet information. */
1358 pkt->packet_type = rxq_cq_to_pkt_type(rxq, cqe, mcqe);
1360 if (rxq->rss_hash) {
1361 uint32_t rss_hash_res = 0;
1363 /* If compressed, take hash result from mini-CQE. */
1365 rxq->mcqe_format != MLX5_CQE_RESP_FORMAT_HASH)
1366 rss_hash_res = rte_be_to_cpu_32(cqe->rx_hash_res);
1368 rss_hash_res = rte_be_to_cpu_32(mcqe->rx_hash_result);
1370 pkt->hash.rss = rss_hash_res;
1371 pkt->ol_flags |= PKT_RX_RSS_HASH;
1377 /* If compressed, take flow tag from mini-CQE. */
1379 rxq->mcqe_format != MLX5_CQE_RESP_FORMAT_FTAG_STRIDX)
1380 mark = cqe->sop_drop_qpn;
1382 mark = ((mcqe->byte_cnt_flow & 0xff) << 8) |
1383 (mcqe->flow_tag_high << 16);
1384 if (MLX5_FLOW_MARK_IS_VALID(mark)) {
1385 pkt->ol_flags |= PKT_RX_FDIR;
1386 if (mark != RTE_BE32(MLX5_FLOW_MARK_DEFAULT)) {
1387 pkt->ol_flags |= PKT_RX_FDIR_ID;
1388 pkt->hash.fdir.hi = mlx5_flow_mark_get(mark);
1392 if (rxq->dynf_meta) {
1393 uint32_t meta = cqe->flow_table_metadata &
1394 rxq->flow_meta_port_mask;
1397 pkt->ol_flags |= rxq->flow_meta_mask;
1398 *RTE_MBUF_DYNFIELD(pkt, rxq->flow_meta_offset,
1403 pkt->ol_flags |= rxq_cq_to_ol_flags(cqe);
1404 if (rxq->vlan_strip) {
1408 rxq->mcqe_format != MLX5_CQE_RESP_FORMAT_L34H_STRIDX)
1409 vlan_strip = cqe->hdr_type_etc &
1410 RTE_BE16(MLX5_CQE_VLAN_STRIPPED);
1412 vlan_strip = mcqe->hdr_type &
1413 RTE_BE16(MLX5_CQE_VLAN_STRIPPED);
1415 pkt->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1416 pkt->vlan_tci = rte_be_to_cpu_16(cqe->vlan_info);
1419 if (rxq->hw_timestamp) {
1420 uint64_t ts = rte_be_to_cpu_64(cqe->timestamp);
1422 if (rxq->rt_timestamp)
1423 ts = mlx5_txpp_convert_rx_ts(rxq->sh, ts);
1424 mlx5_timestamp_set(pkt, rxq->timestamp_offset, ts);
1425 pkt->ol_flags |= rxq->timestamp_rx_flag;
1430 * DPDK callback for RX.
1433 * Generic pointer to RX queue structure.
1435 * Array to store received packets.
1437 * Maximum number of packets in array.
1440 * Number of packets successfully received (<= pkts_n).
1443 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1445 struct mlx5_rxq_data *rxq = dpdk_rxq;
1446 const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1447 const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1448 const unsigned int sges_n = rxq->sges_n;
1449 struct rte_mbuf *pkt = NULL;
1450 struct rte_mbuf *seg = NULL;
1451 volatile struct mlx5_cqe *cqe =
1452 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1454 unsigned int rq_ci = rxq->rq_ci << sges_n;
1455 int len = 0; /* keep its value across iterations. */
1458 unsigned int idx = rq_ci & wqe_cnt;
1459 volatile struct mlx5_wqe_data_seg *wqe =
1460 &((volatile struct mlx5_wqe_data_seg *)rxq->wqes)[idx];
1461 struct rte_mbuf *rep = (*rxq->elts)[idx];
1462 volatile struct mlx5_mini_cqe8 *mcqe = NULL;
1470 /* Allocate the buf from the same pool. */
1471 rep = rte_mbuf_raw_alloc(seg->pool);
1472 if (unlikely(rep == NULL)) {
1473 ++rxq->stats.rx_nombuf;
1476 * no buffers before we even started,
1477 * bail out silently.
1481 while (pkt != seg) {
1482 MLX5_ASSERT(pkt != (*rxq->elts)[idx]);
1486 rte_mbuf_raw_free(pkt);
1495 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1496 len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt, &mcqe);
1498 rte_mbuf_raw_free(rep);
1502 MLX5_ASSERT(len >= (rxq->crc_present << 2));
1503 pkt->ol_flags &= EXT_ATTACHED_MBUF;
1504 rxq_cq_to_mbuf(rxq, pkt, cqe, mcqe);
1505 if (rxq->crc_present)
1506 len -= RTE_ETHER_CRC_LEN;
1508 if (cqe->lro_num_seg > 1) {
1510 (rte_pktmbuf_mtod(pkt, uint8_t *), cqe,
1512 pkt->ol_flags |= PKT_RX_LRO;
1513 pkt->tso_segsz = len / cqe->lro_num_seg;
1516 DATA_LEN(rep) = DATA_LEN(seg);
1517 PKT_LEN(rep) = PKT_LEN(seg);
1518 SET_DATA_OFF(rep, DATA_OFF(seg));
1519 PORT(rep) = PORT(seg);
1520 (*rxq->elts)[idx] = rep;
1522 * Fill NIC descriptor with the new buffer. The lkey and size
1523 * of the buffers are already known, only the buffer address
1526 wqe->addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(rep, uintptr_t));
1527 /* If there's only one MR, no need to replace LKey in WQE. */
1528 if (unlikely(mlx5_mr_btree_len(&rxq->mr_ctrl.cache_bh) > 1))
1529 wqe->lkey = mlx5_rx_mb2mr(rxq, rep);
1530 if (len > DATA_LEN(seg)) {
1531 len -= DATA_LEN(seg);
1536 DATA_LEN(seg) = len;
1537 #ifdef MLX5_PMD_SOFT_COUNTERS
1538 /* Increment bytes counter. */
1539 rxq->stats.ibytes += PKT_LEN(pkt);
1541 /* Return packet. */
1546 /* Align consumer index to the next stride. */
1551 if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
1553 /* Update the consumer index. */
1554 rxq->rq_ci = rq_ci >> sges_n;
1556 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
1558 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
1559 #ifdef MLX5_PMD_SOFT_COUNTERS
1560 /* Increment packets counter. */
1561 rxq->stats.ipackets += i;
1567 * Update LRO packet TCP header.
1568 * The HW LRO feature doesn't update the TCP header after coalescing the
1569 * TCP segments but supplies information in CQE to fill it by SW.
1572 * Pointer to the TCP header.
1574 * Pointer to the completion entry..
1576 * The L3 pseudo-header checksum.
1579 mlx5_lro_update_tcp_hdr(struct rte_tcp_hdr *__rte_restrict tcp,
1580 volatile struct mlx5_cqe *__rte_restrict cqe,
1581 uint32_t phcsum, uint8_t l4_type)
1584 * The HW calculates only the TCP payload checksum, need to complete
1585 * the TCP header checksum and the L3 pseudo-header checksum.
1587 uint32_t csum = phcsum + cqe->csum;
1589 if (l4_type == MLX5_L4_HDR_TYPE_TCP_EMPTY_ACK ||
1590 l4_type == MLX5_L4_HDR_TYPE_TCP_WITH_ACL) {
1591 tcp->tcp_flags |= RTE_TCP_ACK_FLAG;
1592 tcp->recv_ack = cqe->lro_ack_seq_num;
1593 tcp->rx_win = cqe->lro_tcp_win;
1595 if (cqe->lro_tcppsh_abort_dupack & MLX5_CQE_LRO_PUSH_MASK)
1596 tcp->tcp_flags |= RTE_TCP_PSH_FLAG;
1598 csum += rte_raw_cksum(tcp, (tcp->data_off >> 4) * 4);
1599 csum = ((csum & 0xffff0000) >> 16) + (csum & 0xffff);
1600 csum = (~csum) & 0xffff;
1607 * Update LRO packet headers.
1608 * The HW LRO feature doesn't update the L3/TCP headers after coalescing the
1609 * TCP segments but supply information in CQE to fill it by SW.
1612 * The packet address.
1614 * Pointer to the completion entry..
1616 * The packet length.
1619 mlx5_lro_update_hdr(uint8_t *__rte_restrict padd,
1620 volatile struct mlx5_cqe *__rte_restrict cqe,
1621 volatile struct mlx5_mini_cqe8 *mcqe,
1622 struct mlx5_rxq_data *rxq, uint32_t len)
1625 struct rte_ether_hdr *eth;
1626 struct rte_vlan_hdr *vlan;
1627 struct rte_ipv4_hdr *ipv4;
1628 struct rte_ipv6_hdr *ipv6;
1629 struct rte_tcp_hdr *tcp;
1634 uint16_t proto = h.eth->ether_type;
1639 while (proto == RTE_BE16(RTE_ETHER_TYPE_VLAN) ||
1640 proto == RTE_BE16(RTE_ETHER_TYPE_QINQ)) {
1641 proto = h.vlan->eth_proto;
1644 if (proto == RTE_BE16(RTE_ETHER_TYPE_IPV4)) {
1645 h.ipv4->time_to_live = cqe->lro_min_ttl;
1646 h.ipv4->total_length = rte_cpu_to_be_16(len - (h.hdr - padd));
1647 h.ipv4->hdr_checksum = 0;
1648 h.ipv4->hdr_checksum = rte_ipv4_cksum(h.ipv4);
1649 phcsum = rte_ipv4_phdr_cksum(h.ipv4, 0);
1652 h.ipv6->hop_limits = cqe->lro_min_ttl;
1653 h.ipv6->payload_len = rte_cpu_to_be_16(len - (h.hdr - padd) -
1655 phcsum = rte_ipv6_phdr_cksum(h.ipv6, 0);
1659 rxq->mcqe_format != MLX5_CQE_RESP_FORMAT_L34H_STRIDX)
1660 l4_type = (rte_be_to_cpu_16(cqe->hdr_type_etc) &
1661 MLX5_CQE_L4_TYPE_MASK) >> MLX5_CQE_L4_TYPE_SHIFT;
1663 l4_type = (rte_be_to_cpu_16(mcqe->hdr_type) &
1664 MLX5_CQE_L4_TYPE_MASK) >> MLX5_CQE_L4_TYPE_SHIFT;
1665 mlx5_lro_update_tcp_hdr(h.tcp, cqe, phcsum, l4_type);
1669 mlx5_mprq_buf_free_cb(void *addr __rte_unused, void *opaque)
1671 struct mlx5_mprq_buf *buf = opaque;
1673 if (__atomic_load_n(&buf->refcnt, __ATOMIC_RELAXED) == 1) {
1674 rte_mempool_put(buf->mp, buf);
1675 } else if (unlikely(__atomic_sub_fetch(&buf->refcnt, 1,
1676 __ATOMIC_RELAXED) == 0)) {
1677 __atomic_store_n(&buf->refcnt, 1, __ATOMIC_RELAXED);
1678 rte_mempool_put(buf->mp, buf);
1683 mlx5_mprq_buf_free(struct mlx5_mprq_buf *buf)
1685 mlx5_mprq_buf_free_cb(NULL, buf);
1689 * DPDK callback for RX with Multi-Packet RQ support.
1692 * Generic pointer to RX queue structure.
1694 * Array to store received packets.
1696 * Maximum number of packets in array.
1699 * Number of packets successfully received (<= pkts_n).
1702 mlx5_rx_burst_mprq(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1704 struct mlx5_rxq_data *rxq = dpdk_rxq;
1705 const uint32_t strd_n = 1 << rxq->strd_num_n;
1706 const uint32_t strd_sz = 1 << rxq->strd_sz_n;
1707 const uint32_t cq_mask = (1 << rxq->cqe_n) - 1;
1708 const uint32_t wq_mask = (1 << rxq->elts_n) - 1;
1709 volatile struct mlx5_cqe *cqe = &(*rxq->cqes)[rxq->cq_ci & cq_mask];
1711 uint32_t rq_ci = rxq->rq_ci;
1712 uint16_t consumed_strd = rxq->consumed_strd;
1713 struct mlx5_mprq_buf *buf = (*rxq->mprq_bufs)[rq_ci & wq_mask];
1715 while (i < pkts_n) {
1716 struct rte_mbuf *pkt;
1722 volatile struct mlx5_mini_cqe8 *mcqe = NULL;
1723 enum mlx5_rqx_code rxq_code;
1725 if (consumed_strd == strd_n) {
1726 /* Replace WQE if the buffer is still in use. */
1727 mprq_buf_replace(rxq, rq_ci & wq_mask);
1728 /* Advance to the next WQE. */
1731 buf = (*rxq->mprq_bufs)[rq_ci & wq_mask];
1733 cqe = &(*rxq->cqes)[rxq->cq_ci & cq_mask];
1734 ret = mlx5_rx_poll_len(rxq, cqe, cq_mask, &mcqe);
1738 len = (byte_cnt & MLX5_MPRQ_LEN_MASK) >> MLX5_MPRQ_LEN_SHIFT;
1739 MLX5_ASSERT((int)len >= (rxq->crc_present << 2));
1740 if (rxq->crc_present)
1741 len -= RTE_ETHER_CRC_LEN;
1743 rxq->mcqe_format == MLX5_CQE_RESP_FORMAT_FTAG_STRIDX)
1744 strd_cnt = (len / strd_sz) + !!(len % strd_sz);
1746 strd_cnt = (byte_cnt & MLX5_MPRQ_STRIDE_NUM_MASK) >>
1747 MLX5_MPRQ_STRIDE_NUM_SHIFT;
1748 MLX5_ASSERT(strd_cnt);
1749 consumed_strd += strd_cnt;
1750 if (byte_cnt & MLX5_MPRQ_FILLER_MASK)
1752 strd_idx = rte_be_to_cpu_16(mcqe == NULL ?
1755 MLX5_ASSERT(strd_idx < strd_n);
1756 MLX5_ASSERT(!((rte_be_to_cpu_16(cqe->wqe_id) ^ rq_ci) &
1758 pkt = rte_pktmbuf_alloc(rxq->mp);
1759 if (unlikely(pkt == NULL)) {
1760 ++rxq->stats.rx_nombuf;
1763 len = (byte_cnt & MLX5_MPRQ_LEN_MASK) >> MLX5_MPRQ_LEN_SHIFT;
1764 MLX5_ASSERT((int)len >= (rxq->crc_present << 2));
1765 if (rxq->crc_present)
1766 len -= RTE_ETHER_CRC_LEN;
1767 rxq_code = mprq_buf_to_pkt(rxq, pkt, len, buf,
1768 strd_idx, strd_cnt);
1769 if (unlikely(rxq_code != MLX5_RXQ_CODE_EXIT)) {
1770 rte_pktmbuf_free_seg(pkt);
1771 if (rxq_code == MLX5_RXQ_CODE_DROPPED) {
1772 ++rxq->stats.idropped;
1775 if (rxq_code == MLX5_RXQ_CODE_NOMBUF) {
1776 ++rxq->stats.rx_nombuf;
1780 rxq_cq_to_mbuf(rxq, pkt, cqe, mcqe);
1781 if (cqe->lro_num_seg > 1) {
1782 mlx5_lro_update_hdr(rte_pktmbuf_mtod(pkt, uint8_t *),
1783 cqe, mcqe, rxq, len);
1784 pkt->ol_flags |= PKT_RX_LRO;
1785 pkt->tso_segsz = len / cqe->lro_num_seg;
1788 PORT(pkt) = rxq->port_id;
1789 #ifdef MLX5_PMD_SOFT_COUNTERS
1790 /* Increment bytes counter. */
1791 rxq->stats.ibytes += PKT_LEN(pkt);
1793 /* Return packet. */
1797 /* Update the consumer indexes. */
1798 rxq->consumed_strd = consumed_strd;
1800 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
1801 if (rq_ci != rxq->rq_ci) {
1804 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
1806 #ifdef MLX5_PMD_SOFT_COUNTERS
1807 /* Increment packets counter. */
1808 rxq->stats.ipackets += i;
1814 * Dummy DPDK callback for TX.
1816 * This function is used to temporarily replace the real callback during
1817 * unsafe control operations on the queue, or in case of error.
1820 * Generic pointer to TX queue structure.
1822 * Packets to transmit.
1824 * Number of packets in array.
1827 * Number of packets successfully transmitted (<= pkts_n).
1830 removed_tx_burst(void *dpdk_txq __rte_unused,
1831 struct rte_mbuf **pkts __rte_unused,
1832 uint16_t pkts_n __rte_unused)
1839 * Dummy DPDK callback for RX.
1841 * This function is used to temporarily replace the real callback during
1842 * unsafe control operations on the queue, or in case of error.
1845 * Generic pointer to RX queue structure.
1847 * Array to store received packets.
1849 * Maximum number of packets in array.
1852 * Number of packets successfully received (<= pkts_n).
1855 removed_rx_burst(void *dpdk_txq __rte_unused,
1856 struct rte_mbuf **pkts __rte_unused,
1857 uint16_t pkts_n __rte_unused)
1864 * Vectorized Rx/Tx routines are not compiled in when required vector
1865 * instructions are not supported on a target architecture. The following null
1866 * stubs are needed for linkage when those are not included outside of this file
1867 * (e.g. mlx5_rxtx_vec_sse.c for x86).
1871 mlx5_rx_burst_vec(void *dpdk_txq __rte_unused,
1872 struct rte_mbuf **pkts __rte_unused,
1873 uint16_t pkts_n __rte_unused)
1879 mlx5_rx_burst_mprq_vec(void *dpdk_txq __rte_unused,
1880 struct rte_mbuf **pkts __rte_unused,
1881 uint16_t pkts_n __rte_unused)
1887 mlx5_rxq_check_vec_support(struct mlx5_rxq_data *rxq __rte_unused)
1893 mlx5_check_vec_rx_support(struct rte_eth_dev *dev __rte_unused)
1899 * Free the mbufs from the linear array of pointers.
1902 * Pointer to Tx queue structure.
1904 * Pointer to array of packets to be free.
1906 * Number of packets to be freed.
1908 * Configured Tx offloads mask. It is fully defined at
1909 * compile time and may be used for optimization.
1911 static __rte_always_inline void
1912 mlx5_tx_free_mbuf(struct mlx5_txq_data *__rte_restrict txq,
1913 struct rte_mbuf **__rte_restrict pkts,
1914 unsigned int pkts_n,
1915 unsigned int olx __rte_unused)
1917 struct rte_mempool *pool = NULL;
1918 struct rte_mbuf **p_free = NULL;
1919 struct rte_mbuf *mbuf;
1920 unsigned int n_free = 0;
1923 * The implemented algorithm eliminates
1924 * copying pointers to temporary array
1925 * for rte_mempool_put_bulk() calls.
1928 MLX5_ASSERT(pkts_n);
1930 * Free mbufs directly to the pool in bulk
1931 * if fast free offload is engaged
1933 if (!MLX5_TXOFF_CONFIG(MULTI) && txq->fast_free) {
1936 rte_mempool_put_bulk(pool, (void *)pkts, pkts_n);
1942 * Decrement mbuf reference counter, detach
1943 * indirect and external buffers if needed.
1945 mbuf = rte_pktmbuf_prefree_seg(*pkts);
1946 if (likely(mbuf != NULL)) {
1947 MLX5_ASSERT(mbuf == *pkts);
1948 if (likely(n_free != 0)) {
1949 if (unlikely(pool != mbuf->pool))
1950 /* From different pool. */
1953 /* Start new scan array. */
1960 if (unlikely(pkts_n == 0)) {
1966 * This happens if mbuf is still referenced.
1967 * We can't put it back to the pool, skip.
1971 if (unlikely(n_free != 0))
1972 /* There is some array to free.*/
1974 if (unlikely(pkts_n == 0))
1975 /* Last mbuf, nothing to free. */
1981 * This loop is implemented to avoid multiple
1982 * inlining of rte_mempool_put_bulk().
1985 MLX5_ASSERT(p_free);
1986 MLX5_ASSERT(n_free);
1988 * Free the array of pre-freed mbufs
1989 * belonging to the same memory pool.
1991 rte_mempool_put_bulk(pool, (void *)p_free, n_free);
1992 if (unlikely(mbuf != NULL)) {
1993 /* There is the request to start new scan. */
1998 if (likely(pkts_n != 0))
2001 * This is the last mbuf to be freed.
2002 * Do one more loop iteration to complete.
2003 * This is rare case of the last unique mbuf.
2008 if (likely(pkts_n == 0))
2016 * No inline version to free buffers for optimal call
2017 * on the tx_burst completion.
2019 static __rte_noinline void
2020 __mlx5_tx_free_mbuf(struct mlx5_txq_data *__rte_restrict txq,
2021 struct rte_mbuf **__rte_restrict pkts,
2022 unsigned int pkts_n,
2023 unsigned int olx __rte_unused)
2025 mlx5_tx_free_mbuf(txq, pkts, pkts_n, olx);
2029 * Free the mbuf from the elts ring buffer till new tail.
2032 * Pointer to Tx queue structure.
2034 * Index in elts to free up to, becomes new elts tail.
2036 * Configured Tx offloads mask. It is fully defined at
2037 * compile time and may be used for optimization.
2039 static __rte_always_inline void
2040 mlx5_tx_free_elts(struct mlx5_txq_data *__rte_restrict txq,
2042 unsigned int olx __rte_unused)
2044 uint16_t n_elts = tail - txq->elts_tail;
2046 MLX5_ASSERT(n_elts);
2047 MLX5_ASSERT(n_elts <= txq->elts_s);
2049 * Implement a loop to support ring buffer wraparound
2050 * with single inlining of mlx5_tx_free_mbuf().
2055 part = txq->elts_s - (txq->elts_tail & txq->elts_m);
2056 part = RTE_MIN(part, n_elts);
2058 MLX5_ASSERT(part <= txq->elts_s);
2059 mlx5_tx_free_mbuf(txq,
2060 &txq->elts[txq->elts_tail & txq->elts_m],
2062 txq->elts_tail += part;
2068 * Store the mbuf being sent into elts ring buffer.
2069 * On Tx completion these mbufs will be freed.
2072 * Pointer to Tx queue structure.
2074 * Pointer to array of packets to be stored.
2076 * Number of packets to be stored.
2078 * Configured Tx offloads mask. It is fully defined at
2079 * compile time and may be used for optimization.
2081 static __rte_always_inline void
2082 mlx5_tx_copy_elts(struct mlx5_txq_data *__rte_restrict txq,
2083 struct rte_mbuf **__rte_restrict pkts,
2084 unsigned int pkts_n,
2085 unsigned int olx __rte_unused)
2088 struct rte_mbuf **elts = (struct rte_mbuf **)txq->elts;
2091 MLX5_ASSERT(pkts_n);
2092 part = txq->elts_s - (txq->elts_head & txq->elts_m);
2094 MLX5_ASSERT(part <= txq->elts_s);
2095 /* This code is a good candidate for vectorizing with SIMD. */
2096 rte_memcpy((void *)(elts + (txq->elts_head & txq->elts_m)),
2098 RTE_MIN(part, pkts_n) * sizeof(struct rte_mbuf *));
2099 txq->elts_head += pkts_n;
2100 if (unlikely(part < pkts_n))
2101 /* The copy is wrapping around the elts array. */
2102 rte_memcpy((void *)elts, (void *)(pkts + part),
2103 (pkts_n - part) * sizeof(struct rte_mbuf *));
2107 * Update completion queue consuming index via doorbell
2108 * and flush the completed data buffers.
2111 * Pointer to TX queue structure.
2112 * @param valid CQE pointer
2113 * if not NULL update txq->wqe_pi and flush the buffers
2115 * Configured Tx offloads mask. It is fully defined at
2116 * compile time and may be used for optimization.
2118 static __rte_always_inline void
2119 mlx5_tx_comp_flush(struct mlx5_txq_data *__rte_restrict txq,
2120 volatile struct mlx5_cqe *last_cqe,
2121 unsigned int olx __rte_unused)
2123 if (likely(last_cqe != NULL)) {
2126 txq->wqe_pi = rte_be_to_cpu_16(last_cqe->wqe_counter);
2127 tail = txq->fcqs[(txq->cq_ci - 1) & txq->cqe_m];
2128 if (likely(tail != txq->elts_tail)) {
2129 mlx5_tx_free_elts(txq, tail, olx);
2130 MLX5_ASSERT(tail == txq->elts_tail);
2136 * Manage TX completions. This routine checks the CQ for
2137 * arrived CQEs, deduces the last accomplished WQE in SQ,
2138 * updates SQ producing index and frees all completed mbufs.
2141 * Pointer to TX queue structure.
2143 * Configured Tx offloads mask. It is fully defined at
2144 * compile time and may be used for optimization.
2146 * NOTE: not inlined intentionally, it makes tx_burst
2147 * routine smaller, simple and faster - from experiments.
2150 mlx5_tx_handle_completion(struct mlx5_txq_data *__rte_restrict txq,
2151 unsigned int olx __rte_unused)
2153 unsigned int count = MLX5_TX_COMP_MAX_CQE;
2154 volatile struct mlx5_cqe *last_cqe = NULL;
2155 bool ring_doorbell = false;
2159 volatile struct mlx5_cqe *cqe;
2161 cqe = &txq->cqes[txq->cq_ci & txq->cqe_m];
2162 ret = check_cqe(cqe, txq->cqe_s, txq->cq_ci);
2163 if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) {
2164 if (likely(ret != MLX5_CQE_STATUS_ERR)) {
2165 /* No new CQEs in completion queue. */
2166 MLX5_ASSERT(ret == MLX5_CQE_STATUS_HW_OWN);
2170 * Some error occurred, try to restart.
2171 * We have no barrier after WQE related Doorbell
2172 * written, make sure all writes are completed
2173 * here, before we might perform SQ reset.
2176 ret = mlx5_tx_error_cqe_handle
2177 (txq, (volatile struct mlx5_err_cqe *)cqe);
2178 if (unlikely(ret < 0)) {
2180 * Some error occurred on queue error
2181 * handling, we do not advance the index
2182 * here, allowing to retry on next call.
2187 * We are going to fetch all entries with
2188 * MLX5_CQE_SYNDROME_WR_FLUSH_ERR status.
2189 * The send queue is supposed to be empty.
2191 ring_doorbell = true;
2193 txq->cq_pi = txq->cq_ci;
2197 /* Normal transmit completion. */
2198 MLX5_ASSERT(txq->cq_ci != txq->cq_pi);
2199 #ifdef RTE_LIBRTE_MLX5_DEBUG
2200 MLX5_ASSERT((txq->fcqs[txq->cq_ci & txq->cqe_m] >> 16) ==
2203 ring_doorbell = true;
2207 * We have to restrict the amount of processed CQEs
2208 * in one tx_burst routine call. The CQ may be large
2209 * and many CQEs may be updated by the NIC in one
2210 * transaction. Buffers freeing is time consuming,
2211 * multiple iterations may introduce significant
2214 if (likely(--count == 0))
2217 if (likely(ring_doorbell)) {
2218 /* Ring doorbell to notify hardware. */
2219 rte_compiler_barrier();
2220 *txq->cq_db = rte_cpu_to_be_32(txq->cq_ci);
2221 mlx5_tx_comp_flush(txq, last_cqe, olx);
2226 * Check if the completion request flag should be set in the last WQE.
2227 * Both pushed mbufs and WQEs are monitored and the completion request
2228 * flag is set if any of thresholds is reached.
2231 * Pointer to TX queue structure.
2233 * Pointer to burst routine local context.
2235 * Configured Tx offloads mask. It is fully defined at
2236 * compile time and may be used for optimization.
2238 static __rte_always_inline void
2239 mlx5_tx_request_completion(struct mlx5_txq_data *__rte_restrict txq,
2240 struct mlx5_txq_local *__rte_restrict loc,
2243 uint16_t head = txq->elts_head;
2246 part = MLX5_TXOFF_CONFIG(INLINE) ?
2247 0 : loc->pkts_sent - loc->pkts_copy;
2249 if ((uint16_t)(head - txq->elts_comp) >= MLX5_TX_COMP_THRESH ||
2250 (MLX5_TXOFF_CONFIG(INLINE) &&
2251 (uint16_t)(txq->wqe_ci - txq->wqe_comp) >= txq->wqe_thres)) {
2252 volatile struct mlx5_wqe *last = loc->wqe_last;
2255 txq->elts_comp = head;
2256 if (MLX5_TXOFF_CONFIG(INLINE))
2257 txq->wqe_comp = txq->wqe_ci;
2258 /* Request unconditional completion on last WQE. */
2259 last->cseg.flags = RTE_BE32(MLX5_COMP_ALWAYS <<
2260 MLX5_COMP_MODE_OFFSET);
2261 /* Save elts_head in dedicated free on completion queue. */
2262 #ifdef RTE_LIBRTE_MLX5_DEBUG
2263 txq->fcqs[txq->cq_pi++ & txq->cqe_m] = head |
2264 (last->cseg.opcode >> 8) << 16;
2266 txq->fcqs[txq->cq_pi++ & txq->cqe_m] = head;
2268 /* A CQE slot must always be available. */
2269 MLX5_ASSERT((txq->cq_pi - txq->cq_ci) <= txq->cqe_s);
2274 * DPDK callback to check the status of a tx descriptor.
2279 * The index of the descriptor in the ring.
2282 * The status of the tx descriptor.
2285 mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset)
2287 struct mlx5_txq_data *__rte_restrict txq = tx_queue;
2290 mlx5_tx_handle_completion(txq, 0);
2291 used = txq->elts_head - txq->elts_tail;
2293 return RTE_ETH_TX_DESC_FULL;
2294 return RTE_ETH_TX_DESC_DONE;
2298 * Build the Control Segment with specified opcode:
2299 * - MLX5_OPCODE_SEND
2300 * - MLX5_OPCODE_ENHANCED_MPSW
2304 * Pointer to TX queue structure.
2306 * Pointer to burst routine local context.
2308 * Pointer to WQE to fill with built Control Segment.
2310 * Supposed length of WQE in segments.
2312 * SQ WQE opcode to put into Control Segment.
2314 * Configured Tx offloads mask. It is fully defined at
2315 * compile time and may be used for optimization.
2317 static __rte_always_inline void
2318 mlx5_tx_cseg_init(struct mlx5_txq_data *__rte_restrict txq,
2319 struct mlx5_txq_local *__rte_restrict loc __rte_unused,
2320 struct mlx5_wqe *__rte_restrict wqe,
2322 unsigned int opcode,
2323 unsigned int olx __rte_unused)
2325 struct mlx5_wqe_cseg *__rte_restrict cs = &wqe->cseg;
2327 /* For legacy MPW replace the EMPW by TSO with modifier. */
2328 if (MLX5_TXOFF_CONFIG(MPW) && opcode == MLX5_OPCODE_ENHANCED_MPSW)
2329 opcode = MLX5_OPCODE_TSO | MLX5_OPC_MOD_MPW << 24;
2330 cs->opcode = rte_cpu_to_be_32((txq->wqe_ci << 8) | opcode);
2331 cs->sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | ds);
2332 cs->flags = RTE_BE32(MLX5_COMP_ONLY_FIRST_ERR <<
2333 MLX5_COMP_MODE_OFFSET);
2334 cs->misc = RTE_BE32(0);
2338 * Build the Synchronize Queue Segment with specified completion index.
2341 * Pointer to TX queue structure.
2343 * Pointer to burst routine local context.
2345 * Pointer to WQE to fill with built Control Segment.
2347 * Completion index in Clock Queue to wait.
2349 * Configured Tx offloads mask. It is fully defined at
2350 * compile time and may be used for optimization.
2352 static __rte_always_inline void
2353 mlx5_tx_wseg_init(struct mlx5_txq_data *restrict txq,
2354 struct mlx5_txq_local *restrict loc __rte_unused,
2355 struct mlx5_wqe *restrict wqe,
2357 unsigned int olx __rte_unused)
2359 struct mlx5_wqe_qseg *qs;
2361 qs = RTE_PTR_ADD(wqe, MLX5_WSEG_SIZE);
2362 qs->max_index = rte_cpu_to_be_32(wci);
2363 qs->qpn_cqn = rte_cpu_to_be_32(txq->sh->txpp.clock_queue.cq_obj.cq->id);
2364 qs->reserved0 = RTE_BE32(0);
2365 qs->reserved1 = RTE_BE32(0);
2369 * Build the Ethernet Segment without inlined data.
2370 * Supports Software Parser, Checksums and VLAN
2371 * insertion Tx offload features.
2374 * Pointer to TX queue structure.
2376 * Pointer to burst routine local context.
2378 * Pointer to WQE to fill with built Ethernet Segment.
2380 * Configured Tx offloads mask. It is fully defined at
2381 * compile time and may be used for optimization.
2383 static __rte_always_inline void
2384 mlx5_tx_eseg_none(struct mlx5_txq_data *__rte_restrict txq __rte_unused,
2385 struct mlx5_txq_local *__rte_restrict loc,
2386 struct mlx5_wqe *__rte_restrict wqe,
2389 struct mlx5_wqe_eseg *__rte_restrict es = &wqe->eseg;
2393 * Calculate and set check sum flags first, dword field
2394 * in segment may be shared with Software Parser flags.
2396 csum = MLX5_TXOFF_CONFIG(CSUM) ? txq_ol_cksum_to_cs(loc->mbuf) : 0;
2397 es->flags = rte_cpu_to_le_32(csum);
2399 * Calculate and set Software Parser offsets and flags.
2400 * These flags a set for custom UDP and IP tunnel packets.
2402 es->swp_offs = txq_mbuf_to_swp(loc, &es->swp_flags, olx);
2403 /* Fill metadata field if needed. */
2404 es->metadata = MLX5_TXOFF_CONFIG(METADATA) ?
2405 loc->mbuf->ol_flags & PKT_TX_DYNF_METADATA ?
2406 *RTE_FLOW_DYNF_METADATA(loc->mbuf) : 0 : 0;
2407 /* Engage VLAN tag insertion feature if requested. */
2408 if (MLX5_TXOFF_CONFIG(VLAN) &&
2409 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) {
2411 * We should get here only if device support
2412 * this feature correctly.
2414 MLX5_ASSERT(txq->vlan_en);
2415 es->inline_hdr = rte_cpu_to_be_32(MLX5_ETH_WQE_VLAN_INSERT |
2416 loc->mbuf->vlan_tci);
2418 es->inline_hdr = RTE_BE32(0);
2423 * Build the Ethernet Segment with minimal inlined data
2424 * of MLX5_ESEG_MIN_INLINE_SIZE bytes length. This is
2425 * used to fill the gap in single WQEBB WQEs.
2426 * Supports Software Parser, Checksums and VLAN
2427 * insertion Tx offload features.
2430 * Pointer to TX queue structure.
2432 * Pointer to burst routine local context.
2434 * Pointer to WQE to fill with built Ethernet Segment.
2436 * Length of VLAN tag insertion if any.
2438 * Configured Tx offloads mask. It is fully defined at
2439 * compile time and may be used for optimization.
2441 static __rte_always_inline void
2442 mlx5_tx_eseg_dmin(struct mlx5_txq_data *__rte_restrict txq __rte_unused,
2443 struct mlx5_txq_local *__rte_restrict loc,
2444 struct mlx5_wqe *__rte_restrict wqe,
2448 struct mlx5_wqe_eseg *__rte_restrict es = &wqe->eseg;
2450 uint8_t *psrc, *pdst;
2453 * Calculate and set check sum flags first, dword field
2454 * in segment may be shared with Software Parser flags.
2456 csum = MLX5_TXOFF_CONFIG(CSUM) ? txq_ol_cksum_to_cs(loc->mbuf) : 0;
2457 es->flags = rte_cpu_to_le_32(csum);
2459 * Calculate and set Software Parser offsets and flags.
2460 * These flags a set for custom UDP and IP tunnel packets.
2462 es->swp_offs = txq_mbuf_to_swp(loc, &es->swp_flags, olx);
2463 /* Fill metadata field if needed. */
2464 es->metadata = MLX5_TXOFF_CONFIG(METADATA) ?
2465 loc->mbuf->ol_flags & PKT_TX_DYNF_METADATA ?
2466 *RTE_FLOW_DYNF_METADATA(loc->mbuf) : 0 : 0;
2467 psrc = rte_pktmbuf_mtod(loc->mbuf, uint8_t *);
2468 es->inline_hdr_sz = RTE_BE16(MLX5_ESEG_MIN_INLINE_SIZE);
2469 es->inline_data = *(unaligned_uint16_t *)psrc;
2470 psrc += sizeof(uint16_t);
2471 pdst = (uint8_t *)(es + 1);
2472 if (MLX5_TXOFF_CONFIG(VLAN) && vlan) {
2473 /* Implement VLAN tag insertion as part inline data. */
2474 memcpy(pdst, psrc, 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t));
2475 pdst += 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t);
2476 psrc += 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t);
2477 /* Insert VLAN ethertype + VLAN tag. */
2478 *(unaligned_uint32_t *)pdst = rte_cpu_to_be_32
2479 ((RTE_ETHER_TYPE_VLAN << 16) |
2480 loc->mbuf->vlan_tci);
2481 pdst += sizeof(struct rte_vlan_hdr);
2482 /* Copy the rest two bytes from packet data. */
2483 MLX5_ASSERT(pdst == RTE_PTR_ALIGN(pdst, sizeof(uint16_t)));
2484 *(uint16_t *)pdst = *(unaligned_uint16_t *)psrc;
2486 /* Fill the gap in the title WQEBB with inline data. */
2487 rte_mov16(pdst, psrc);
2492 * Build the Ethernet Segment with entire packet
2493 * data inlining. Checks the boundary of WQEBB and
2494 * ring buffer wrapping, supports Software Parser,
2495 * Checksums and VLAN insertion Tx offload features.
2498 * Pointer to TX queue structure.
2500 * Pointer to burst routine local context.
2502 * Pointer to WQE to fill with built Ethernet Segment.
2504 * Length of VLAN tag insertion if any.
2506 * Length of data to inline (VLAN included, if any).
2508 * TSO flag, set mss field from the packet.
2510 * Configured Tx offloads mask. It is fully defined at
2511 * compile time and may be used for optimization.
2514 * Pointer to the next Data Segment (aligned and wrapped around).
2516 static __rte_always_inline struct mlx5_wqe_dseg *
2517 mlx5_tx_eseg_data(struct mlx5_txq_data *__rte_restrict txq,
2518 struct mlx5_txq_local *__rte_restrict loc,
2519 struct mlx5_wqe *__rte_restrict wqe,
2525 struct mlx5_wqe_eseg *__rte_restrict es = &wqe->eseg;
2527 uint8_t *psrc, *pdst;
2531 * Calculate and set check sum flags first, dword field
2532 * in segment may be shared with Software Parser flags.
2534 csum = MLX5_TXOFF_CONFIG(CSUM) ? txq_ol_cksum_to_cs(loc->mbuf) : 0;
2537 csum |= loc->mbuf->tso_segsz;
2538 es->flags = rte_cpu_to_be_32(csum);
2540 es->flags = rte_cpu_to_le_32(csum);
2543 * Calculate and set Software Parser offsets and flags.
2544 * These flags a set for custom UDP and IP tunnel packets.
2546 es->swp_offs = txq_mbuf_to_swp(loc, &es->swp_flags, olx);
2547 /* Fill metadata field if needed. */
2548 es->metadata = MLX5_TXOFF_CONFIG(METADATA) ?
2549 loc->mbuf->ol_flags & PKT_TX_DYNF_METADATA ?
2550 *RTE_FLOW_DYNF_METADATA(loc->mbuf) : 0 : 0;
2551 psrc = rte_pktmbuf_mtod(loc->mbuf, uint8_t *);
2552 es->inline_hdr_sz = rte_cpu_to_be_16(inlen);
2553 es->inline_data = *(unaligned_uint16_t *)psrc;
2554 psrc += sizeof(uint16_t);
2555 pdst = (uint8_t *)(es + 1);
2556 if (MLX5_TXOFF_CONFIG(VLAN) && vlan) {
2557 /* Implement VLAN tag insertion as part inline data. */
2558 memcpy(pdst, psrc, 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t));
2559 pdst += 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t);
2560 psrc += 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t);
2561 /* Insert VLAN ethertype + VLAN tag. */
2562 *(unaligned_uint32_t *)pdst = rte_cpu_to_be_32
2563 ((RTE_ETHER_TYPE_VLAN << 16) |
2564 loc->mbuf->vlan_tci);
2565 pdst += sizeof(struct rte_vlan_hdr);
2566 /* Copy the rest two bytes from packet data. */
2567 MLX5_ASSERT(pdst == RTE_PTR_ALIGN(pdst, sizeof(uint16_t)));
2568 *(uint16_t *)pdst = *(unaligned_uint16_t *)psrc;
2569 psrc += sizeof(uint16_t);
2571 /* Fill the gap in the title WQEBB with inline data. */
2572 rte_mov16(pdst, psrc);
2573 psrc += sizeof(rte_v128u32_t);
2575 pdst = (uint8_t *)(es + 2);
2576 MLX5_ASSERT(inlen >= MLX5_ESEG_MIN_INLINE_SIZE);
2577 MLX5_ASSERT(pdst < (uint8_t *)txq->wqes_end);
2578 inlen -= MLX5_ESEG_MIN_INLINE_SIZE;
2580 MLX5_ASSERT(pdst == RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE));
2581 return (struct mlx5_wqe_dseg *)pdst;
2584 * The WQEBB space availability is checked by caller.
2585 * Here we should be aware of WQE ring buffer wraparound only.
2587 part = (uint8_t *)txq->wqes_end - pdst;
2588 part = RTE_MIN(part, inlen);
2590 rte_memcpy(pdst, psrc, part);
2592 if (likely(!inlen)) {
2594 * If return value is not used by the caller
2595 * the code below will be optimized out.
2598 pdst = RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE);
2599 if (unlikely(pdst >= (uint8_t *)txq->wqes_end))
2600 pdst = (uint8_t *)txq->wqes;
2601 return (struct mlx5_wqe_dseg *)pdst;
2603 pdst = (uint8_t *)txq->wqes;
2610 * Copy data from chain of mbuf to the specified linear buffer.
2611 * Checksums and VLAN insertion Tx offload features. If data
2612 * from some mbuf copied completely this mbuf is freed. Local
2613 * structure is used to keep the byte stream state.
2616 * Pointer to the destination linear buffer.
2618 * Pointer to burst routine local context.
2620 * Length of data to be copied.
2622 * Length of data to be copied ignoring no inline hint.
2624 * Configured Tx offloads mask. It is fully defined at
2625 * compile time and may be used for optimization.
2628 * Number of actual copied data bytes. This is always greater than or
2629 * equal to must parameter and might be lesser than len in no inline
2630 * hint flag is encountered.
2632 static __rte_always_inline unsigned int
2633 mlx5_tx_mseg_memcpy(uint8_t *pdst,
2634 struct mlx5_txq_local *__rte_restrict loc,
2637 unsigned int olx __rte_unused)
2639 struct rte_mbuf *mbuf;
2640 unsigned int part, dlen, copy = 0;
2644 MLX5_ASSERT(must <= len);
2646 /* Allow zero length packets, must check first. */
2647 dlen = rte_pktmbuf_data_len(loc->mbuf);
2648 if (dlen <= loc->mbuf_off) {
2649 /* Exhausted packet, just free. */
2651 loc->mbuf = mbuf->next;
2652 rte_pktmbuf_free_seg(mbuf);
2654 MLX5_ASSERT(loc->mbuf_nseg > 1);
2655 MLX5_ASSERT(loc->mbuf);
2657 if (loc->mbuf->ol_flags & PKT_TX_DYNF_NOINLINE) {
2662 * We already copied the minimal
2663 * requested amount of data.
2668 if (diff <= rte_pktmbuf_data_len(loc->mbuf)) {
2670 * Copy only the minimal required
2671 * part of the data buffer.
2678 dlen -= loc->mbuf_off;
2679 psrc = rte_pktmbuf_mtod_offset(loc->mbuf, uint8_t *,
2681 part = RTE_MIN(len, dlen);
2682 rte_memcpy(pdst, psrc, part);
2684 loc->mbuf_off += part;
2687 if (loc->mbuf_off >= rte_pktmbuf_data_len(loc->mbuf)) {
2689 /* Exhausted packet, just free. */
2691 loc->mbuf = mbuf->next;
2692 rte_pktmbuf_free_seg(mbuf);
2694 MLX5_ASSERT(loc->mbuf_nseg >= 1);
2704 * Build the Ethernet Segment with inlined data from
2705 * multi-segment packet. Checks the boundary of WQEBB
2706 * and ring buffer wrapping, supports Software Parser,
2707 * Checksums and VLAN insertion Tx offload features.
2710 * Pointer to TX queue structure.
2712 * Pointer to burst routine local context.
2714 * Pointer to WQE to fill with built Ethernet Segment.
2716 * Length of VLAN tag insertion if any.
2718 * Length of data to inline (VLAN included, if any).
2720 * TSO flag, set mss field from the packet.
2722 * Configured Tx offloads mask. It is fully defined at
2723 * compile time and may be used for optimization.
2726 * Pointer to the next Data Segment (aligned and
2727 * possible NOT wrapped around - caller should do
2728 * wrapping check on its own).
2730 static __rte_always_inline struct mlx5_wqe_dseg *
2731 mlx5_tx_eseg_mdat(struct mlx5_txq_data *__rte_restrict txq,
2732 struct mlx5_txq_local *__rte_restrict loc,
2733 struct mlx5_wqe *__rte_restrict wqe,
2739 struct mlx5_wqe_eseg *__rte_restrict es = &wqe->eseg;
2742 unsigned int part, tlen = 0;
2745 * Calculate and set check sum flags first, uint32_t field
2746 * in segment may be shared with Software Parser flags.
2748 csum = MLX5_TXOFF_CONFIG(CSUM) ? txq_ol_cksum_to_cs(loc->mbuf) : 0;
2751 csum |= loc->mbuf->tso_segsz;
2752 es->flags = rte_cpu_to_be_32(csum);
2754 es->flags = rte_cpu_to_le_32(csum);
2757 * Calculate and set Software Parser offsets and flags.
2758 * These flags a set for custom UDP and IP tunnel packets.
2760 es->swp_offs = txq_mbuf_to_swp(loc, &es->swp_flags, olx);
2761 /* Fill metadata field if needed. */
2762 es->metadata = MLX5_TXOFF_CONFIG(METADATA) ?
2763 loc->mbuf->ol_flags & PKT_TX_DYNF_METADATA ?
2764 *RTE_FLOW_DYNF_METADATA(loc->mbuf) : 0 : 0;
2765 MLX5_ASSERT(inlen >= MLX5_ESEG_MIN_INLINE_SIZE);
2766 pdst = (uint8_t *)&es->inline_data;
2767 if (MLX5_TXOFF_CONFIG(VLAN) && vlan) {
2768 /* Implement VLAN tag insertion as part inline data. */
2769 mlx5_tx_mseg_memcpy(pdst, loc,
2770 2 * RTE_ETHER_ADDR_LEN,
2771 2 * RTE_ETHER_ADDR_LEN, olx);
2772 pdst += 2 * RTE_ETHER_ADDR_LEN;
2773 *(unaligned_uint32_t *)pdst = rte_cpu_to_be_32
2774 ((RTE_ETHER_TYPE_VLAN << 16) |
2775 loc->mbuf->vlan_tci);
2776 pdst += sizeof(struct rte_vlan_hdr);
2777 tlen += 2 * RTE_ETHER_ADDR_LEN + sizeof(struct rte_vlan_hdr);
2779 MLX5_ASSERT(pdst < (uint8_t *)txq->wqes_end);
2781 * The WQEBB space availability is checked by caller.
2782 * Here we should be aware of WQE ring buffer wraparound only.
2784 part = (uint8_t *)txq->wqes_end - pdst;
2785 part = RTE_MIN(part, inlen - tlen);
2791 * Copying may be interrupted inside the routine
2792 * if run into no inline hint flag.
2794 copy = tlen >= txq->inlen_mode ? 0 : (txq->inlen_mode - tlen);
2795 copy = mlx5_tx_mseg_memcpy(pdst, loc, part, copy, olx);
2797 if (likely(inlen <= tlen) || copy < part) {
2798 es->inline_hdr_sz = rte_cpu_to_be_16(tlen);
2800 pdst = RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE);
2801 return (struct mlx5_wqe_dseg *)pdst;
2803 pdst = (uint8_t *)txq->wqes;
2804 part = inlen - tlen;
2809 * Build the Data Segment of pointer type.
2812 * Pointer to TX queue structure.
2814 * Pointer to burst routine local context.
2816 * Pointer to WQE to fill with built Data Segment.
2818 * Data buffer to point.
2820 * Data buffer length.
2822 * Configured Tx offloads mask. It is fully defined at
2823 * compile time and may be used for optimization.
2825 static __rte_always_inline void
2826 mlx5_tx_dseg_ptr(struct mlx5_txq_data *__rte_restrict txq,
2827 struct mlx5_txq_local *__rte_restrict loc,
2828 struct mlx5_wqe_dseg *__rte_restrict dseg,
2831 unsigned int olx __rte_unused)
2835 dseg->bcount = rte_cpu_to_be_32(len);
2836 dseg->lkey = mlx5_tx_mb2mr(txq, loc->mbuf);
2837 dseg->pbuf = rte_cpu_to_be_64((uintptr_t)buf);
2841 * Build the Data Segment of pointer type or inline
2842 * if data length is less than buffer in minimal
2843 * Data Segment size.
2846 * Pointer to TX queue structure.
2848 * Pointer to burst routine local context.
2850 * Pointer to WQE to fill with built Data Segment.
2852 * Data buffer to point.
2854 * Data buffer length.
2856 * Configured Tx offloads mask. It is fully defined at
2857 * compile time and may be used for optimization.
2859 static __rte_always_inline void
2860 mlx5_tx_dseg_iptr(struct mlx5_txq_data *__rte_restrict txq,
2861 struct mlx5_txq_local *__rte_restrict loc,
2862 struct mlx5_wqe_dseg *__rte_restrict dseg,
2865 unsigned int olx __rte_unused)
2871 if (len > MLX5_DSEG_MIN_INLINE_SIZE) {
2872 dseg->bcount = rte_cpu_to_be_32(len);
2873 dseg->lkey = mlx5_tx_mb2mr(txq, loc->mbuf);
2874 dseg->pbuf = rte_cpu_to_be_64((uintptr_t)buf);
2878 dseg->bcount = rte_cpu_to_be_32(len | MLX5_ETH_WQE_DATA_INLINE);
2879 /* Unrolled implementation of generic rte_memcpy. */
2880 dst = (uintptr_t)&dseg->inline_data[0];
2881 src = (uintptr_t)buf;
2883 #ifdef RTE_ARCH_STRICT_ALIGN
2884 MLX5_ASSERT(dst == RTE_PTR_ALIGN(dst, sizeof(uint32_t)));
2885 *(uint32_t *)dst = *(unaligned_uint32_t *)src;
2886 dst += sizeof(uint32_t);
2887 src += sizeof(uint32_t);
2888 *(uint32_t *)dst = *(unaligned_uint32_t *)src;
2889 dst += sizeof(uint32_t);
2890 src += sizeof(uint32_t);
2892 *(uint64_t *)dst = *(unaligned_uint64_t *)src;
2893 dst += sizeof(uint64_t);
2894 src += sizeof(uint64_t);
2898 *(uint32_t *)dst = *(unaligned_uint32_t *)src;
2899 dst += sizeof(uint32_t);
2900 src += sizeof(uint32_t);
2903 *(uint16_t *)dst = *(unaligned_uint16_t *)src;
2904 dst += sizeof(uint16_t);
2905 src += sizeof(uint16_t);
2908 *(uint8_t *)dst = *(uint8_t *)src;
2912 * Build the Data Segment of inlined data from single
2913 * segment packet, no VLAN insertion.
2916 * Pointer to TX queue structure.
2918 * Pointer to burst routine local context.
2920 * Pointer to WQE to fill with built Data Segment.
2922 * Data buffer to point.
2924 * Data buffer length.
2926 * Configured Tx offloads mask. It is fully defined at
2927 * compile time and may be used for optimization.
2930 * Pointer to the next Data Segment after inlined data.
2931 * Ring buffer wraparound check is needed. We do not
2932 * do it here because it may not be needed for the
2933 * last packet in the eMPW session.
2935 static __rte_always_inline struct mlx5_wqe_dseg *
2936 mlx5_tx_dseg_empw(struct mlx5_txq_data *__rte_restrict txq,
2937 struct mlx5_txq_local *__rte_restrict loc __rte_unused,
2938 struct mlx5_wqe_dseg *__rte_restrict dseg,
2941 unsigned int olx __rte_unused)
2946 if (!MLX5_TXOFF_CONFIG(MPW)) {
2947 /* Store the descriptor byte counter for eMPW sessions. */
2948 dseg->bcount = rte_cpu_to_be_32(len | MLX5_ETH_WQE_DATA_INLINE);
2949 pdst = &dseg->inline_data[0];
2951 /* The entire legacy MPW session counter is stored on close. */
2952 pdst = (uint8_t *)dseg;
2955 * The WQEBB space availability is checked by caller.
2956 * Here we should be aware of WQE ring buffer wraparound only.
2958 part = (uint8_t *)txq->wqes_end - pdst;
2959 part = RTE_MIN(part, len);
2961 rte_memcpy(pdst, buf, part);
2965 if (!MLX5_TXOFF_CONFIG(MPW))
2966 pdst = RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE);
2967 /* Note: no final wraparound check here. */
2968 return (struct mlx5_wqe_dseg *)pdst;
2970 pdst = (uint8_t *)txq->wqes;
2977 * Build the Data Segment of inlined data from single
2978 * segment packet with VLAN insertion.
2981 * Pointer to TX queue structure.
2983 * Pointer to burst routine local context.
2985 * Pointer to the dseg fill with built Data Segment.
2987 * Data buffer to point.
2989 * Data buffer length.
2991 * Configured Tx offloads mask. It is fully defined at
2992 * compile time and may be used for optimization.
2995 * Pointer to the next Data Segment after inlined data.
2996 * Ring buffer wraparound check is needed.
2998 static __rte_always_inline struct mlx5_wqe_dseg *
2999 mlx5_tx_dseg_vlan(struct mlx5_txq_data *__rte_restrict txq,
3000 struct mlx5_txq_local *__rte_restrict loc __rte_unused,
3001 struct mlx5_wqe_dseg *__rte_restrict dseg,
3004 unsigned int olx __rte_unused)
3010 MLX5_ASSERT(len > MLX5_ESEG_MIN_INLINE_SIZE);
3011 if (!MLX5_TXOFF_CONFIG(MPW)) {
3012 /* Store the descriptor byte counter for eMPW sessions. */
3013 dseg->bcount = rte_cpu_to_be_32
3014 ((len + sizeof(struct rte_vlan_hdr)) |
3015 MLX5_ETH_WQE_DATA_INLINE);
3016 pdst = &dseg->inline_data[0];
3018 /* The entire legacy MPW session counter is stored on close. */
3019 pdst = (uint8_t *)dseg;
3021 memcpy(pdst, buf, MLX5_DSEG_MIN_INLINE_SIZE);
3022 buf += MLX5_DSEG_MIN_INLINE_SIZE;
3023 pdst += MLX5_DSEG_MIN_INLINE_SIZE;
3024 len -= MLX5_DSEG_MIN_INLINE_SIZE;
3025 /* Insert VLAN ethertype + VLAN tag. Pointer is aligned. */
3026 MLX5_ASSERT(pdst == RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE));
3027 if (unlikely(pdst >= (uint8_t *)txq->wqes_end))
3028 pdst = (uint8_t *)txq->wqes;
3029 *(uint32_t *)pdst = rte_cpu_to_be_32((RTE_ETHER_TYPE_VLAN << 16) |
3030 loc->mbuf->vlan_tci);
3031 pdst += sizeof(struct rte_vlan_hdr);
3033 * The WQEBB space availability is checked by caller.
3034 * Here we should be aware of WQE ring buffer wraparound only.
3036 part = (uint8_t *)txq->wqes_end - pdst;
3037 part = RTE_MIN(part, len);
3039 rte_memcpy(pdst, buf, part);
3043 if (!MLX5_TXOFF_CONFIG(MPW))
3044 pdst = RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE);
3045 /* Note: no final wraparound check here. */
3046 return (struct mlx5_wqe_dseg *)pdst;
3048 pdst = (uint8_t *)txq->wqes;
3055 * Build the Ethernet Segment with optionally inlined data with
3056 * VLAN insertion and following Data Segments (if any) from
3057 * multi-segment packet. Used by ordinary send and TSO.
3060 * Pointer to TX queue structure.
3062 * Pointer to burst routine local context.
3064 * Pointer to WQE to fill with built Ethernet/Data Segments.
3066 * Length of VLAN header to insert, 0 means no VLAN insertion.
3068 * Data length to inline. For TSO this parameter specifies
3069 * exact value, for ordinary send routine can be aligned by
3070 * caller to provide better WQE space saving and data buffer
3071 * start address alignment. This length includes VLAN header
3074 * Zero means ordinary send, inlined data can be extended,
3075 * otherwise this is TSO, inlined data length is fixed.
3077 * Configured Tx offloads mask. It is fully defined at
3078 * compile time and may be used for optimization.
3081 * Actual size of built WQE in segments.
3083 static __rte_always_inline unsigned int
3084 mlx5_tx_mseg_build(struct mlx5_txq_data *__rte_restrict txq,
3085 struct mlx5_txq_local *__rte_restrict loc,
3086 struct mlx5_wqe *__rte_restrict wqe,
3090 unsigned int olx __rte_unused)
3092 struct mlx5_wqe_dseg *__rte_restrict dseg;
3095 MLX5_ASSERT((rte_pktmbuf_pkt_len(loc->mbuf) + vlan) >= inlen);
3096 loc->mbuf_nseg = NB_SEGS(loc->mbuf);
3099 dseg = mlx5_tx_eseg_mdat(txq, loc, wqe, vlan, inlen, tso, olx);
3100 if (!loc->mbuf_nseg)
3103 * There are still some mbuf remaining, not inlined.
3104 * The first mbuf may be partially inlined and we
3105 * must process the possible non-zero data offset.
3107 if (loc->mbuf_off) {
3112 * Exhausted packets must be dropped before.
3113 * Non-zero offset means there are some data
3114 * remained in the packet.
3116 MLX5_ASSERT(loc->mbuf_off < rte_pktmbuf_data_len(loc->mbuf));
3117 MLX5_ASSERT(rte_pktmbuf_data_len(loc->mbuf));
3118 dptr = rte_pktmbuf_mtod_offset(loc->mbuf, uint8_t *,
3120 dlen = rte_pktmbuf_data_len(loc->mbuf) - loc->mbuf_off;
3122 * Build the pointer/minimal data Data Segment.
3123 * Do ring buffer wrapping check in advance.
3125 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
3126 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
3127 mlx5_tx_dseg_iptr(txq, loc, dseg, dptr, dlen, olx);
3128 /* Store the mbuf to be freed on completion. */
3129 MLX5_ASSERT(loc->elts_free);
3130 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
3133 if (--loc->mbuf_nseg == 0)
3135 loc->mbuf = loc->mbuf->next;
3139 if (unlikely(!rte_pktmbuf_data_len(loc->mbuf))) {
3140 struct rte_mbuf *mbuf;
3142 /* Zero length segment found, just skip. */
3144 loc->mbuf = loc->mbuf->next;
3145 rte_pktmbuf_free_seg(mbuf);
3146 if (--loc->mbuf_nseg == 0)
3149 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
3150 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
3153 rte_pktmbuf_mtod(loc->mbuf, uint8_t *),
3154 rte_pktmbuf_data_len(loc->mbuf), olx);
3155 MLX5_ASSERT(loc->elts_free);
3156 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
3159 if (--loc->mbuf_nseg == 0)
3161 loc->mbuf = loc->mbuf->next;
3166 /* Calculate actual segments used from the dseg pointer. */
3167 if ((uintptr_t)wqe < (uintptr_t)dseg)
3168 ds = ((uintptr_t)dseg - (uintptr_t)wqe) / MLX5_WSEG_SIZE;
3170 ds = (((uintptr_t)dseg - (uintptr_t)wqe) +
3171 txq->wqe_s * MLX5_WQE_SIZE) / MLX5_WSEG_SIZE;
3176 * The routine checks timestamp flag in the current packet,
3177 * and push WAIT WQE into the queue if scheduling is required.
3180 * Pointer to TX queue structure.
3182 * Pointer to burst routine local context.
3184 * Configured Tx offloads mask. It is fully defined at
3185 * compile time and may be used for optimization.
3188 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3189 * MLX5_TXCMP_CODE_SINGLE - continue processing with the packet.
3190 * MLX5_TXCMP_CODE_MULTI - the WAIT inserted, continue processing.
3191 * Local context variables partially updated.
3193 static __rte_always_inline enum mlx5_txcmp_code
3194 mlx5_tx_schedule_send(struct mlx5_txq_data *restrict txq,
3195 struct mlx5_txq_local *restrict loc,
3198 if (MLX5_TXOFF_CONFIG(TXPP) &&
3199 loc->mbuf->ol_flags & txq->ts_mask) {
3200 struct mlx5_wqe *wqe;
3205 * Estimate the required space quickly and roughly.
3206 * We would like to ensure the packet can be pushed
3207 * to the queue and we won't get the orphan WAIT WQE.
3209 if (loc->wqe_free <= MLX5_WQE_SIZE_MAX / MLX5_WQE_SIZE ||
3210 loc->elts_free < NB_SEGS(loc->mbuf))
3211 return MLX5_TXCMP_CODE_EXIT;
3212 /* Convert the timestamp into completion to wait. */
3213 ts = *RTE_MBUF_DYNFIELD(loc->mbuf, txq->ts_offset, uint64_t *);
3214 wci = mlx5_txpp_convert_tx_ts(txq->sh, ts);
3215 if (unlikely(wci < 0))
3216 return MLX5_TXCMP_CODE_SINGLE;
3217 /* Build the WAIT WQE with specified completion. */
3218 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3219 mlx5_tx_cseg_init(txq, loc, wqe, 2, MLX5_OPCODE_WAIT, olx);
3220 mlx5_tx_wseg_init(txq, loc, wqe, wci, olx);
3223 return MLX5_TXCMP_CODE_MULTI;
3225 return MLX5_TXCMP_CODE_SINGLE;
3229 * Tx one packet function for multi-segment TSO. Supports all
3230 * types of Tx offloads, uses MLX5_OPCODE_TSO to build WQEs,
3231 * sends one packet per WQE.
3233 * This routine is responsible for storing processed mbuf
3234 * into elts ring buffer and update elts_head.
3237 * Pointer to TX queue structure.
3239 * Pointer to burst routine local context.
3241 * Configured Tx offloads mask. It is fully defined at
3242 * compile time and may be used for optimization.
3245 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3246 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3247 * Local context variables partially updated.
3249 static __rte_always_inline enum mlx5_txcmp_code
3250 mlx5_tx_packet_multi_tso(struct mlx5_txq_data *__rte_restrict txq,
3251 struct mlx5_txq_local *__rte_restrict loc,
3254 struct mlx5_wqe *__rte_restrict wqe;
3255 unsigned int ds, dlen, inlen, ntcp, vlan = 0;
3257 if (MLX5_TXOFF_CONFIG(TXPP)) {
3258 enum mlx5_txcmp_code wret;
3260 /* Generate WAIT for scheduling if requested. */
3261 wret = mlx5_tx_schedule_send(txq, loc, olx);
3262 if (wret == MLX5_TXCMP_CODE_EXIT)
3263 return MLX5_TXCMP_CODE_EXIT;
3264 if (wret == MLX5_TXCMP_CODE_ERROR)
3265 return MLX5_TXCMP_CODE_ERROR;
3268 * Calculate data length to be inlined to estimate
3269 * the required space in WQE ring buffer.
3271 dlen = rte_pktmbuf_pkt_len(loc->mbuf);
3272 if (MLX5_TXOFF_CONFIG(VLAN) && loc->mbuf->ol_flags & PKT_TX_VLAN_PKT)
3273 vlan = sizeof(struct rte_vlan_hdr);
3274 inlen = loc->mbuf->l2_len + vlan +
3275 loc->mbuf->l3_len + loc->mbuf->l4_len;
3276 if (unlikely((!inlen || !loc->mbuf->tso_segsz)))
3277 return MLX5_TXCMP_CODE_ERROR;
3278 if (loc->mbuf->ol_flags & PKT_TX_TUNNEL_MASK)
3279 inlen += loc->mbuf->outer_l2_len + loc->mbuf->outer_l3_len;
3280 /* Packet must contain all TSO headers. */
3281 if (unlikely(inlen > MLX5_MAX_TSO_HEADER ||
3282 inlen <= MLX5_ESEG_MIN_INLINE_SIZE ||
3283 inlen > (dlen + vlan)))
3284 return MLX5_TXCMP_CODE_ERROR;
3285 MLX5_ASSERT(inlen >= txq->inlen_mode);
3287 * Check whether there are enough free WQEBBs:
3289 * - Ethernet Segment
3290 * - First Segment of inlined Ethernet data
3291 * - ... data continued ...
3292 * - Data Segments of pointer/min inline type
3294 ds = NB_SEGS(loc->mbuf) + 2 + (inlen -
3295 MLX5_ESEG_MIN_INLINE_SIZE +
3297 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
3298 if (unlikely(loc->wqe_free < ((ds + 3) / 4)))
3299 return MLX5_TXCMP_CODE_EXIT;
3300 /* Check for maximal WQE size. */
3301 if (unlikely((MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE) < ((ds + 3) / 4)))
3302 return MLX5_TXCMP_CODE_ERROR;
3303 #ifdef MLX5_PMD_SOFT_COUNTERS
3304 /* Update sent data bytes/packets counters. */
3305 ntcp = (dlen - (inlen - vlan) + loc->mbuf->tso_segsz - 1) /
3306 loc->mbuf->tso_segsz;
3308 * One will be added for mbuf itself
3309 * at the end of the mlx5_tx_burst from
3310 * loc->pkts_sent field.
3313 txq->stats.opackets += ntcp;
3314 txq->stats.obytes += dlen + vlan + ntcp * inlen;
3316 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3317 loc->wqe_last = wqe;
3318 mlx5_tx_cseg_init(txq, loc, wqe, 0, MLX5_OPCODE_TSO, olx);
3319 ds = mlx5_tx_mseg_build(txq, loc, wqe, vlan, inlen, 1, olx);
3320 wqe->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | ds);
3321 txq->wqe_ci += (ds + 3) / 4;
3322 loc->wqe_free -= (ds + 3) / 4;
3323 return MLX5_TXCMP_CODE_MULTI;
3327 * Tx one packet function for multi-segment SEND. Supports all
3328 * types of Tx offloads, uses MLX5_OPCODE_SEND to build WQEs,
3329 * sends one packet per WQE, without any data inlining in
3332 * This routine is responsible for storing processed mbuf
3333 * into elts ring buffer and update elts_head.
3336 * Pointer to TX queue structure.
3338 * Pointer to burst routine local context.
3340 * Configured Tx offloads mask. It is fully defined at
3341 * compile time and may be used for optimization.
3344 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3345 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3346 * Local context variables partially updated.
3348 static __rte_always_inline enum mlx5_txcmp_code
3349 mlx5_tx_packet_multi_send(struct mlx5_txq_data *__rte_restrict txq,
3350 struct mlx5_txq_local *__rte_restrict loc,
3353 struct mlx5_wqe_dseg *__rte_restrict dseg;
3354 struct mlx5_wqe *__rte_restrict wqe;
3355 unsigned int ds, nseg;
3357 MLX5_ASSERT(NB_SEGS(loc->mbuf) > 1);
3358 if (MLX5_TXOFF_CONFIG(TXPP)) {
3359 enum mlx5_txcmp_code wret;
3361 /* Generate WAIT for scheduling if requested. */
3362 wret = mlx5_tx_schedule_send(txq, loc, olx);
3363 if (wret == MLX5_TXCMP_CODE_EXIT)
3364 return MLX5_TXCMP_CODE_EXIT;
3365 if (wret == MLX5_TXCMP_CODE_ERROR)
3366 return MLX5_TXCMP_CODE_ERROR;
3369 * No inline at all, it means the CPU cycles saving
3370 * is prioritized at configuration, we should not
3371 * copy any packet data to WQE.
3373 nseg = NB_SEGS(loc->mbuf);
3375 if (unlikely(loc->wqe_free < ((ds + 3) / 4)))
3376 return MLX5_TXCMP_CODE_EXIT;
3377 /* Check for maximal WQE size. */
3378 if (unlikely((MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE) < ((ds + 3) / 4)))
3379 return MLX5_TXCMP_CODE_ERROR;
3381 * Some Tx offloads may cause an error if
3382 * packet is not long enough, check against
3383 * assumed minimal length.
3385 if (rte_pktmbuf_pkt_len(loc->mbuf) <= MLX5_ESEG_MIN_INLINE_SIZE)
3386 return MLX5_TXCMP_CODE_ERROR;
3387 #ifdef MLX5_PMD_SOFT_COUNTERS
3388 /* Update sent data bytes counter. */
3389 txq->stats.obytes += rte_pktmbuf_pkt_len(loc->mbuf);
3390 if (MLX5_TXOFF_CONFIG(VLAN) &&
3391 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT)
3392 txq->stats.obytes += sizeof(struct rte_vlan_hdr);
3395 * SEND WQE, one WQEBB:
3396 * - Control Segment, SEND opcode
3397 * - Ethernet Segment, optional VLAN, no inline
3398 * - Data Segments, pointer only type
3400 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3401 loc->wqe_last = wqe;
3402 mlx5_tx_cseg_init(txq, loc, wqe, ds, MLX5_OPCODE_SEND, olx);
3403 mlx5_tx_eseg_none(txq, loc, wqe, olx);
3404 dseg = &wqe->dseg[0];
3406 if (unlikely(!rte_pktmbuf_data_len(loc->mbuf))) {
3407 struct rte_mbuf *mbuf;
3410 * Zero length segment found, have to
3411 * correct total size of WQE in segments.
3412 * It is supposed to be rare occasion, so
3413 * in normal case (no zero length segments)
3414 * we avoid extra writing to the Control
3418 wqe->cseg.sq_ds -= RTE_BE32(1);
3420 loc->mbuf = mbuf->next;
3421 rte_pktmbuf_free_seg(mbuf);
3427 rte_pktmbuf_mtod(loc->mbuf, uint8_t *),
3428 rte_pktmbuf_data_len(loc->mbuf), olx);
3429 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
3434 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
3435 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
3436 loc->mbuf = loc->mbuf->next;
3439 txq->wqe_ci += (ds + 3) / 4;
3440 loc->wqe_free -= (ds + 3) / 4;
3441 return MLX5_TXCMP_CODE_MULTI;
3445 * Tx one packet function for multi-segment SEND. Supports all
3446 * types of Tx offloads, uses MLX5_OPCODE_SEND to build WQEs,
3447 * sends one packet per WQE, with data inlining in
3448 * Ethernet Segment and minimal Data Segments.
3450 * This routine is responsible for storing processed mbuf
3451 * into elts ring buffer and update elts_head.
3454 * Pointer to TX queue structure.
3456 * Pointer to burst routine local context.
3458 * Configured Tx offloads mask. It is fully defined at
3459 * compile time and may be used for optimization.
3462 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3463 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3464 * Local context variables partially updated.
3466 static __rte_always_inline enum mlx5_txcmp_code
3467 mlx5_tx_packet_multi_inline(struct mlx5_txq_data *__rte_restrict txq,
3468 struct mlx5_txq_local *__rte_restrict loc,
3471 struct mlx5_wqe *__rte_restrict wqe;
3472 unsigned int ds, inlen, dlen, vlan = 0;
3474 MLX5_ASSERT(MLX5_TXOFF_CONFIG(INLINE));
3475 MLX5_ASSERT(NB_SEGS(loc->mbuf) > 1);
3476 if (MLX5_TXOFF_CONFIG(TXPP)) {
3477 enum mlx5_txcmp_code wret;
3479 /* Generate WAIT for scheduling if requested. */
3480 wret = mlx5_tx_schedule_send(txq, loc, olx);
3481 if (wret == MLX5_TXCMP_CODE_EXIT)
3482 return MLX5_TXCMP_CODE_EXIT;
3483 if (wret == MLX5_TXCMP_CODE_ERROR)
3484 return MLX5_TXCMP_CODE_ERROR;
3487 * First calculate data length to be inlined
3488 * to estimate the required space for WQE.
3490 dlen = rte_pktmbuf_pkt_len(loc->mbuf);
3491 if (MLX5_TXOFF_CONFIG(VLAN) && loc->mbuf->ol_flags & PKT_TX_VLAN_PKT)
3492 vlan = sizeof(struct rte_vlan_hdr);
3493 inlen = dlen + vlan;
3494 /* Check against minimal length. */
3495 if (inlen <= MLX5_ESEG_MIN_INLINE_SIZE)
3496 return MLX5_TXCMP_CODE_ERROR;
3497 MLX5_ASSERT(txq->inlen_send >= MLX5_ESEG_MIN_INLINE_SIZE);
3498 if (inlen > txq->inlen_send ||
3499 loc->mbuf->ol_flags & PKT_TX_DYNF_NOINLINE) {
3500 struct rte_mbuf *mbuf;
3505 * Packet length exceeds the allowed inline
3506 * data length, check whether the minimal
3507 * inlining is required.
3509 if (txq->inlen_mode) {
3510 MLX5_ASSERT(txq->inlen_mode >=
3511 MLX5_ESEG_MIN_INLINE_SIZE);
3512 MLX5_ASSERT(txq->inlen_mode <= txq->inlen_send);
3513 inlen = txq->inlen_mode;
3515 if (loc->mbuf->ol_flags & PKT_TX_DYNF_NOINLINE ||
3516 !vlan || txq->vlan_en) {
3518 * VLAN insertion will be done inside by HW.
3519 * It is not utmost effective - VLAN flag is
3520 * checked twice, but we should proceed the
3521 * inlining length correctly and take into
3522 * account the VLAN header being inserted.
3524 return mlx5_tx_packet_multi_send
3527 inlen = MLX5_ESEG_MIN_INLINE_SIZE;
3530 * Now we know the minimal amount of data is requested
3531 * to inline. Check whether we should inline the buffers
3532 * from the chain beginning to eliminate some mbufs.
3535 nxlen = rte_pktmbuf_data_len(mbuf);
3536 if (unlikely(nxlen <= txq->inlen_send)) {
3537 /* We can inline first mbuf at least. */
3538 if (nxlen < inlen) {
3541 /* Scan mbufs till inlen filled. */
3546 nxlen = rte_pktmbuf_data_len(mbuf);
3548 } while (unlikely(nxlen < inlen));
3549 if (unlikely(nxlen > txq->inlen_send)) {
3550 /* We cannot inline entire mbuf. */
3551 smlen = inlen - smlen;
3552 start = rte_pktmbuf_mtod_offset
3553 (mbuf, uintptr_t, smlen);
3560 /* There should be not end of packet. */
3562 nxlen = inlen + rte_pktmbuf_data_len(mbuf);
3563 } while (unlikely(nxlen < txq->inlen_send));
3565 start = rte_pktmbuf_mtod(mbuf, uintptr_t);
3567 * Check whether we can do inline to align start
3568 * address of data buffer to cacheline.
3571 start = (~start + 1) & (RTE_CACHE_LINE_SIZE - 1);
3572 if (unlikely(start)) {
3574 if (start <= txq->inlen_send)
3579 * Check whether there are enough free WQEBBs:
3581 * - Ethernet Segment
3582 * - First Segment of inlined Ethernet data
3583 * - ... data continued ...
3584 * - Data Segments of pointer/min inline type
3586 * Estimate the number of Data Segments conservatively,
3587 * supposing no any mbufs is being freed during inlining.
3589 MLX5_ASSERT(inlen <= txq->inlen_send);
3590 ds = NB_SEGS(loc->mbuf) + 2 + (inlen -
3591 MLX5_ESEG_MIN_INLINE_SIZE +
3593 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
3594 if (unlikely(loc->wqe_free < ((ds + 3) / 4)))
3595 return MLX5_TXCMP_CODE_EXIT;
3596 /* Check for maximal WQE size. */
3597 if (unlikely((MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE) < ((ds + 3) / 4)))
3598 return MLX5_TXCMP_CODE_ERROR;
3599 #ifdef MLX5_PMD_SOFT_COUNTERS
3600 /* Update sent data bytes/packets counters. */
3601 txq->stats.obytes += dlen + vlan;
3603 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3604 loc->wqe_last = wqe;
3605 mlx5_tx_cseg_init(txq, loc, wqe, 0, MLX5_OPCODE_SEND, olx);
3606 ds = mlx5_tx_mseg_build(txq, loc, wqe, vlan, inlen, 0, olx);
3607 wqe->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | ds);
3608 txq->wqe_ci += (ds + 3) / 4;
3609 loc->wqe_free -= (ds + 3) / 4;
3610 return MLX5_TXCMP_CODE_MULTI;
3614 * Tx burst function for multi-segment packets. Supports all
3615 * types of Tx offloads, uses MLX5_OPCODE_SEND/TSO to build WQEs,
3616 * sends one packet per WQE. Function stops sending if it
3617 * encounters the single-segment packet.
3619 * This routine is responsible for storing processed mbuf
3620 * into elts ring buffer and update elts_head.
3623 * Pointer to TX queue structure.
3625 * Packets to transmit.
3627 * Number of packets in array.
3629 * Pointer to burst routine local context.
3631 * Configured Tx offloads mask. It is fully defined at
3632 * compile time and may be used for optimization.
3635 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3636 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3637 * MLX5_TXCMP_CODE_SINGLE - single-segment packet encountered.
3638 * MLX5_TXCMP_CODE_TSO - TSO single-segment packet encountered.
3639 * Local context variables updated.
3641 static __rte_always_inline enum mlx5_txcmp_code
3642 mlx5_tx_burst_mseg(struct mlx5_txq_data *__rte_restrict txq,
3643 struct rte_mbuf **__rte_restrict pkts,
3644 unsigned int pkts_n,
3645 struct mlx5_txq_local *__rte_restrict loc,
3648 MLX5_ASSERT(loc->elts_free && loc->wqe_free);
3649 MLX5_ASSERT(pkts_n > loc->pkts_sent);
3650 pkts += loc->pkts_sent + 1;
3651 pkts_n -= loc->pkts_sent;
3653 enum mlx5_txcmp_code ret;
3655 MLX5_ASSERT(NB_SEGS(loc->mbuf) > 1);
3657 * Estimate the number of free elts quickly but
3658 * conservatively. Some segment may be fully inlined
3659 * and freed, ignore this here - precise estimation
3662 if (loc->elts_free < NB_SEGS(loc->mbuf))
3663 return MLX5_TXCMP_CODE_EXIT;
3664 if (MLX5_TXOFF_CONFIG(TSO) &&
3665 unlikely(loc->mbuf->ol_flags & PKT_TX_TCP_SEG)) {
3666 /* Proceed with multi-segment TSO. */
3667 ret = mlx5_tx_packet_multi_tso(txq, loc, olx);
3668 } else if (MLX5_TXOFF_CONFIG(INLINE)) {
3669 /* Proceed with multi-segment SEND with inlining. */
3670 ret = mlx5_tx_packet_multi_inline(txq, loc, olx);
3672 /* Proceed with multi-segment SEND w/o inlining. */
3673 ret = mlx5_tx_packet_multi_send(txq, loc, olx);
3675 if (ret == MLX5_TXCMP_CODE_EXIT)
3676 return MLX5_TXCMP_CODE_EXIT;
3677 if (ret == MLX5_TXCMP_CODE_ERROR)
3678 return MLX5_TXCMP_CODE_ERROR;
3679 /* WQE is built, go to the next packet. */
3682 if (unlikely(!pkts_n || !loc->elts_free || !loc->wqe_free))
3683 return MLX5_TXCMP_CODE_EXIT;
3684 loc->mbuf = *pkts++;
3686 rte_prefetch0(*pkts);
3687 if (likely(NB_SEGS(loc->mbuf) > 1))
3689 /* Here ends the series of multi-segment packets. */
3690 if (MLX5_TXOFF_CONFIG(TSO) &&
3691 unlikely(loc->mbuf->ol_flags & PKT_TX_TCP_SEG))
3692 return MLX5_TXCMP_CODE_TSO;
3693 return MLX5_TXCMP_CODE_SINGLE;
3699 * Tx burst function for single-segment packets with TSO.
3700 * Supports all types of Tx offloads, except multi-packets.
3701 * Uses MLX5_OPCODE_TSO to build WQEs, sends one packet per WQE.
3702 * Function stops sending if it encounters the multi-segment
3703 * packet or packet without TSO requested.
3705 * The routine is responsible for storing processed mbuf
3706 * into elts ring buffer and update elts_head if inline
3707 * offloads is requested due to possible early freeing
3708 * of the inlined mbufs (can not store pkts array in elts
3712 * Pointer to TX queue structure.
3714 * Packets to transmit.
3716 * Number of packets in array.
3718 * Pointer to burst routine local context.
3720 * Configured Tx offloads mask. It is fully defined at
3721 * compile time and may be used for optimization.
3724 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3725 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3726 * MLX5_TXCMP_CODE_SINGLE - single-segment packet encountered.
3727 * MLX5_TXCMP_CODE_MULTI - multi-segment packet encountered.
3728 * Local context variables updated.
3730 static __rte_always_inline enum mlx5_txcmp_code
3731 mlx5_tx_burst_tso(struct mlx5_txq_data *__rte_restrict txq,
3732 struct rte_mbuf **__rte_restrict pkts,
3733 unsigned int pkts_n,
3734 struct mlx5_txq_local *__rte_restrict loc,
3737 MLX5_ASSERT(loc->elts_free && loc->wqe_free);
3738 MLX5_ASSERT(pkts_n > loc->pkts_sent);
3739 pkts += loc->pkts_sent + 1;
3740 pkts_n -= loc->pkts_sent;
3742 struct mlx5_wqe_dseg *__rte_restrict dseg;
3743 struct mlx5_wqe *__rte_restrict wqe;
3744 unsigned int ds, dlen, hlen, ntcp, vlan = 0;
3747 MLX5_ASSERT(NB_SEGS(loc->mbuf) == 1);
3748 if (MLX5_TXOFF_CONFIG(TXPP)) {
3749 enum mlx5_txcmp_code wret;
3751 /* Generate WAIT for scheduling if requested. */
3752 wret = mlx5_tx_schedule_send(txq, loc, olx);
3753 if (wret == MLX5_TXCMP_CODE_EXIT)
3754 return MLX5_TXCMP_CODE_EXIT;
3755 if (wret == MLX5_TXCMP_CODE_ERROR)
3756 return MLX5_TXCMP_CODE_ERROR;
3758 dlen = rte_pktmbuf_data_len(loc->mbuf);
3759 if (MLX5_TXOFF_CONFIG(VLAN) &&
3760 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) {
3761 vlan = sizeof(struct rte_vlan_hdr);
3764 * First calculate the WQE size to check
3765 * whether we have enough space in ring buffer.
3767 hlen = loc->mbuf->l2_len + vlan +
3768 loc->mbuf->l3_len + loc->mbuf->l4_len;
3769 if (unlikely((!hlen || !loc->mbuf->tso_segsz)))
3770 return MLX5_TXCMP_CODE_ERROR;
3771 if (loc->mbuf->ol_flags & PKT_TX_TUNNEL_MASK)
3772 hlen += loc->mbuf->outer_l2_len +
3773 loc->mbuf->outer_l3_len;
3774 /* Segment must contain all TSO headers. */
3775 if (unlikely(hlen > MLX5_MAX_TSO_HEADER ||
3776 hlen <= MLX5_ESEG_MIN_INLINE_SIZE ||
3777 hlen > (dlen + vlan)))
3778 return MLX5_TXCMP_CODE_ERROR;
3780 * Check whether there are enough free WQEBBs:
3782 * - Ethernet Segment
3783 * - First Segment of inlined Ethernet data
3784 * - ... data continued ...
3785 * - Finishing Data Segment of pointer type
3787 ds = 4 + (hlen - MLX5_ESEG_MIN_INLINE_SIZE +
3788 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
3789 if (loc->wqe_free < ((ds + 3) / 4))
3790 return MLX5_TXCMP_CODE_EXIT;
3791 #ifdef MLX5_PMD_SOFT_COUNTERS
3792 /* Update sent data bytes/packets counters. */
3793 ntcp = (dlen + vlan - hlen +
3794 loc->mbuf->tso_segsz - 1) /
3795 loc->mbuf->tso_segsz;
3797 * One will be added for mbuf itself at the end
3798 * of the mlx5_tx_burst from loc->pkts_sent field.
3801 txq->stats.opackets += ntcp;
3802 txq->stats.obytes += dlen + vlan + ntcp * hlen;
3805 * Build the TSO WQE:
3807 * - Ethernet Segment with hlen bytes inlined
3808 * - Data Segment of pointer type
3810 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3811 loc->wqe_last = wqe;
3812 mlx5_tx_cseg_init(txq, loc, wqe, ds,
3813 MLX5_OPCODE_TSO, olx);
3814 dseg = mlx5_tx_eseg_data(txq, loc, wqe, vlan, hlen, 1, olx);
3815 dptr = rte_pktmbuf_mtod(loc->mbuf, uint8_t *) + hlen - vlan;
3816 dlen -= hlen - vlan;
3817 mlx5_tx_dseg_ptr(txq, loc, dseg, dptr, dlen, olx);
3819 * WQE is built, update the loop parameters
3820 * and go to the next packet.
3822 txq->wqe_ci += (ds + 3) / 4;
3823 loc->wqe_free -= (ds + 3) / 4;
3824 if (MLX5_TXOFF_CONFIG(INLINE))
3825 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
3829 if (unlikely(!pkts_n || !loc->elts_free || !loc->wqe_free))
3830 return MLX5_TXCMP_CODE_EXIT;
3831 loc->mbuf = *pkts++;
3833 rte_prefetch0(*pkts);
3834 if (MLX5_TXOFF_CONFIG(MULTI) &&
3835 unlikely(NB_SEGS(loc->mbuf) > 1))
3836 return MLX5_TXCMP_CODE_MULTI;
3837 if (likely(!(loc->mbuf->ol_flags & PKT_TX_TCP_SEG)))
3838 return MLX5_TXCMP_CODE_SINGLE;
3839 /* Continue with the next TSO packet. */
3845 * Analyze the packet and select the best method to send.
3848 * Pointer to TX queue structure.
3850 * Pointer to burst routine local context.
3852 * Configured Tx offloads mask. It is fully defined at
3853 * compile time and may be used for optimization.
3855 * The predefined flag whether do complete check for
3856 * multi-segment packets and TSO.
3859 * MLX5_TXCMP_CODE_MULTI - multi-segment packet encountered.
3860 * MLX5_TXCMP_CODE_TSO - TSO required, use TSO/LSO.
3861 * MLX5_TXCMP_CODE_SINGLE - single-segment packet, use SEND.
3862 * MLX5_TXCMP_CODE_EMPW - single-segment packet, use MPW.
3864 static __rte_always_inline enum mlx5_txcmp_code
3865 mlx5_tx_able_to_empw(struct mlx5_txq_data *__rte_restrict txq,
3866 struct mlx5_txq_local *__rte_restrict loc,
3870 /* Check for multi-segment packet. */
3872 MLX5_TXOFF_CONFIG(MULTI) &&
3873 unlikely(NB_SEGS(loc->mbuf) > 1))
3874 return MLX5_TXCMP_CODE_MULTI;
3875 /* Check for TSO packet. */
3877 MLX5_TXOFF_CONFIG(TSO) &&
3878 unlikely(loc->mbuf->ol_flags & PKT_TX_TCP_SEG))
3879 return MLX5_TXCMP_CODE_TSO;
3880 /* Check if eMPW is enabled at all. */
3881 if (!MLX5_TXOFF_CONFIG(EMPW))
3882 return MLX5_TXCMP_CODE_SINGLE;
3883 /* Check if eMPW can be engaged. */
3884 if (MLX5_TXOFF_CONFIG(VLAN) &&
3885 unlikely(loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) &&
3886 (!MLX5_TXOFF_CONFIG(INLINE) ||
3887 unlikely((rte_pktmbuf_data_len(loc->mbuf) +
3888 sizeof(struct rte_vlan_hdr)) > txq->inlen_empw))) {
3890 * eMPW does not support VLAN insertion offload,
3891 * we have to inline the entire packet but
3892 * packet is too long for inlining.
3894 return MLX5_TXCMP_CODE_SINGLE;
3896 return MLX5_TXCMP_CODE_EMPW;
3900 * Check the next packet attributes to match with the eMPW batch ones.
3901 * In addition, for legacy MPW the packet length is checked either.
3904 * Pointer to TX queue structure.
3906 * Pointer to Ethernet Segment of eMPW batch.
3908 * Pointer to burst routine local context.
3910 * Length of previous packet in MPW descriptor.
3912 * Configured Tx offloads mask. It is fully defined at
3913 * compile time and may be used for optimization.
3916 * true - packet match with eMPW batch attributes.
3917 * false - no match, eMPW should be restarted.
3919 static __rte_always_inline bool
3920 mlx5_tx_match_empw(struct mlx5_txq_data *__rte_restrict txq,
3921 struct mlx5_wqe_eseg *__rte_restrict es,
3922 struct mlx5_txq_local *__rte_restrict loc,
3926 uint8_t swp_flags = 0;
3928 /* Compare the checksum flags, if any. */
3929 if (MLX5_TXOFF_CONFIG(CSUM) &&
3930 txq_ol_cksum_to_cs(loc->mbuf) != es->cs_flags)
3932 /* Compare the Software Parser offsets and flags. */
3933 if (MLX5_TXOFF_CONFIG(SWP) &&
3934 (es->swp_offs != txq_mbuf_to_swp(loc, &swp_flags, olx) ||
3935 es->swp_flags != swp_flags))
3937 /* Fill metadata field if needed. */
3938 if (MLX5_TXOFF_CONFIG(METADATA) &&
3939 es->metadata != (loc->mbuf->ol_flags & PKT_TX_DYNF_METADATA ?
3940 *RTE_FLOW_DYNF_METADATA(loc->mbuf) : 0))
3942 /* Legacy MPW can send packets with the same lengt only. */
3943 if (MLX5_TXOFF_CONFIG(MPW) &&
3944 dlen != rte_pktmbuf_data_len(loc->mbuf))
3946 /* There must be no VLAN packets in eMPW loop. */
3947 if (MLX5_TXOFF_CONFIG(VLAN))
3948 MLX5_ASSERT(!(loc->mbuf->ol_flags & PKT_TX_VLAN_PKT));
3949 /* Check if the scheduling is requested. */
3950 if (MLX5_TXOFF_CONFIG(TXPP) &&
3951 loc->mbuf->ol_flags & txq->ts_mask)
3957 * Update send loop variables and WQE for eMPW loop
3958 * without data inlining. Number of Data Segments is
3959 * equal to the number of sent packets.
3962 * Pointer to TX queue structure.
3964 * Pointer to burst routine local context.
3966 * Number of packets/Data Segments/Packets.
3968 * Accumulated statistics, bytes sent
3970 * Configured Tx offloads mask. It is fully defined at
3971 * compile time and may be used for optimization.
3974 * true - packet match with eMPW batch attributes.
3975 * false - no match, eMPW should be restarted.
3977 static __rte_always_inline void
3978 mlx5_tx_sdone_empw(struct mlx5_txq_data *__rte_restrict txq,
3979 struct mlx5_txq_local *__rte_restrict loc,
3982 unsigned int olx __rte_unused)
3984 MLX5_ASSERT(!MLX5_TXOFF_CONFIG(INLINE));
3985 #ifdef MLX5_PMD_SOFT_COUNTERS
3986 /* Update sent data bytes counter. */
3987 txq->stats.obytes += slen;
3991 loc->elts_free -= ds;
3992 loc->pkts_sent += ds;
3994 loc->wqe_last->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | ds);
3995 txq->wqe_ci += (ds + 3) / 4;
3996 loc->wqe_free -= (ds + 3) / 4;
4000 * Update send loop variables and WQE for eMPW loop
4001 * with data inlining. Gets the size of pushed descriptors
4002 * and data to the WQE.
4005 * Pointer to TX queue structure.
4007 * Pointer to burst routine local context.
4009 * Total size of descriptor/data in bytes.
4011 * Accumulated statistics, data bytes sent.
4013 * The base WQE for the eMPW/MPW descriptor.
4015 * Configured Tx offloads mask. It is fully defined at
4016 * compile time and may be used for optimization.
4019 * true - packet match with eMPW batch attributes.
4020 * false - no match, eMPW should be restarted.
4022 static __rte_always_inline void
4023 mlx5_tx_idone_empw(struct mlx5_txq_data *__rte_restrict txq,
4024 struct mlx5_txq_local *__rte_restrict loc,
4027 struct mlx5_wqe *__rte_restrict wqem,
4028 unsigned int olx __rte_unused)
4030 struct mlx5_wqe_dseg *dseg = &wqem->dseg[0];
4032 MLX5_ASSERT(MLX5_TXOFF_CONFIG(INLINE));
4033 #ifdef MLX5_PMD_SOFT_COUNTERS
4034 /* Update sent data bytes counter. */
4035 txq->stats.obytes += slen;
4039 if (MLX5_TXOFF_CONFIG(MPW) && dseg->bcount == RTE_BE32(0)) {
4041 * If the legacy MPW session contains the inline packets
4042 * we should set the only inline data segment length
4043 * and align the total length to the segment size.
4045 MLX5_ASSERT(len > sizeof(dseg->bcount));
4046 dseg->bcount = rte_cpu_to_be_32((len - sizeof(dseg->bcount)) |
4047 MLX5_ETH_WQE_DATA_INLINE);
4048 len = (len + MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE + 2;
4051 * The session is not legacy MPW or contains the
4052 * data buffer pointer segments.
4054 MLX5_ASSERT((len % MLX5_WSEG_SIZE) == 0);
4055 len = len / MLX5_WSEG_SIZE + 2;
4057 wqem->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | len);
4058 txq->wqe_ci += (len + 3) / 4;
4059 loc->wqe_free -= (len + 3) / 4;
4060 loc->wqe_last = wqem;
4064 * The set of Tx burst functions for single-segment packets
4065 * without TSO and with Multi-Packet Writing feature support.
4066 * Supports all types of Tx offloads, except multi-packets
4069 * Uses MLX5_OPCODE_EMPW to build WQEs if possible and sends
4070 * as many packet per WQE as it can. If eMPW is not configured
4071 * or packet can not be sent with eMPW (VLAN insertion) the
4072 * ordinary SEND opcode is used and only one packet placed
4075 * Functions stop sending if it encounters the multi-segment
4076 * packet or packet with TSO requested.
4078 * The routines are responsible for storing processed mbuf
4079 * into elts ring buffer and update elts_head if inlining
4080 * offload is requested. Otherwise the copying mbufs to elts
4081 * can be postponed and completed at the end of burst routine.
4084 * Pointer to TX queue structure.
4086 * Packets to transmit.
4088 * Number of packets in array.
4090 * Pointer to burst routine local context.
4092 * Configured Tx offloads mask. It is fully defined at
4093 * compile time and may be used for optimization.
4096 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
4097 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
4098 * MLX5_TXCMP_CODE_MULTI - multi-segment packet encountered.
4099 * MLX5_TXCMP_CODE_TSO - TSO packet encountered.
4100 * MLX5_TXCMP_CODE_SINGLE - used inside functions set.
4101 * MLX5_TXCMP_CODE_EMPW - used inside functions set.
4103 * Local context variables updated.
4106 * The routine sends packets with MLX5_OPCODE_EMPW
4107 * without inlining, this is dedicated optimized branch.
4108 * No VLAN insertion is supported.
4110 static __rte_always_inline enum mlx5_txcmp_code
4111 mlx5_tx_burst_empw_simple(struct mlx5_txq_data *__rte_restrict txq,
4112 struct rte_mbuf **__rte_restrict pkts,
4113 unsigned int pkts_n,
4114 struct mlx5_txq_local *__rte_restrict loc,
4118 * Subroutine is the part of mlx5_tx_burst_single()
4119 * and sends single-segment packet with eMPW opcode
4120 * without data inlining.
4122 MLX5_ASSERT(!MLX5_TXOFF_CONFIG(INLINE));
4123 MLX5_ASSERT(MLX5_TXOFF_CONFIG(EMPW));
4124 MLX5_ASSERT(loc->elts_free && loc->wqe_free);
4125 MLX5_ASSERT(pkts_n > loc->pkts_sent);
4126 pkts += loc->pkts_sent + 1;
4127 pkts_n -= loc->pkts_sent;
4129 struct mlx5_wqe_dseg *__rte_restrict dseg;
4130 struct mlx5_wqe_eseg *__rte_restrict eseg;
4131 enum mlx5_txcmp_code ret;
4132 unsigned int part, loop;
4133 unsigned int slen = 0;
4136 MLX5_ASSERT(NB_SEGS(loc->mbuf) == 1);
4137 if (MLX5_TXOFF_CONFIG(TXPP)) {
4138 enum mlx5_txcmp_code wret;
4140 /* Generate WAIT for scheduling if requested. */
4141 wret = mlx5_tx_schedule_send(txq, loc, olx);
4142 if (wret == MLX5_TXCMP_CODE_EXIT)
4143 return MLX5_TXCMP_CODE_EXIT;
4144 if (wret == MLX5_TXCMP_CODE_ERROR)
4145 return MLX5_TXCMP_CODE_ERROR;
4147 part = RTE_MIN(pkts_n, MLX5_TXOFF_CONFIG(MPW) ?
4148 MLX5_MPW_MAX_PACKETS :
4149 MLX5_EMPW_MAX_PACKETS);
4150 if (unlikely(loc->elts_free < part)) {
4151 /* We have no enough elts to save all mbufs. */
4152 if (unlikely(loc->elts_free < MLX5_EMPW_MIN_PACKETS))
4153 return MLX5_TXCMP_CODE_EXIT;
4154 /* But we still able to send at least minimal eMPW. */
4155 part = loc->elts_free;
4157 /* Check whether we have enough WQEs */
4158 if (unlikely(loc->wqe_free < ((2 + part + 3) / 4))) {
4159 if (unlikely(loc->wqe_free <
4160 ((2 + MLX5_EMPW_MIN_PACKETS + 3) / 4)))
4161 return MLX5_TXCMP_CODE_EXIT;
4162 part = (loc->wqe_free * 4) - 2;
4164 if (likely(part > 1))
4165 rte_prefetch0(*pkts);
4166 loc->wqe_last = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4168 * Build eMPW title WQEBB:
4169 * - Control Segment, eMPW opcode
4170 * - Ethernet Segment, no inline
4172 mlx5_tx_cseg_init(txq, loc, loc->wqe_last, part + 2,
4173 MLX5_OPCODE_ENHANCED_MPSW, olx);
4174 mlx5_tx_eseg_none(txq, loc, loc->wqe_last,
4175 olx & ~MLX5_TXOFF_CONFIG_VLAN);
4176 eseg = &loc->wqe_last->eseg;
4177 dseg = &loc->wqe_last->dseg[0];
4179 /* Store the packet length for legacy MPW. */
4180 if (MLX5_TXOFF_CONFIG(MPW))
4181 eseg->mss = rte_cpu_to_be_16
4182 (rte_pktmbuf_data_len(loc->mbuf));
4184 uint32_t dlen = rte_pktmbuf_data_len(loc->mbuf);
4185 #ifdef MLX5_PMD_SOFT_COUNTERS
4186 /* Update sent data bytes counter. */
4191 rte_pktmbuf_mtod(loc->mbuf, uint8_t *),
4193 if (unlikely(--loop == 0))
4195 loc->mbuf = *pkts++;
4196 if (likely(loop > 1))
4197 rte_prefetch0(*pkts);
4198 ret = mlx5_tx_able_to_empw(txq, loc, olx, true);
4200 * Unroll the completion code to avoid
4201 * returning variable value - it results in
4202 * unoptimized sequent checking in caller.
4204 if (ret == MLX5_TXCMP_CODE_MULTI) {
4206 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
4207 if (unlikely(!loc->elts_free ||
4209 return MLX5_TXCMP_CODE_EXIT;
4210 return MLX5_TXCMP_CODE_MULTI;
4212 MLX5_ASSERT(NB_SEGS(loc->mbuf) == 1);
4213 if (ret == MLX5_TXCMP_CODE_TSO) {
4215 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
4216 if (unlikely(!loc->elts_free ||
4218 return MLX5_TXCMP_CODE_EXIT;
4219 return MLX5_TXCMP_CODE_TSO;
4221 if (ret == MLX5_TXCMP_CODE_SINGLE) {
4223 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
4224 if (unlikely(!loc->elts_free ||
4226 return MLX5_TXCMP_CODE_EXIT;
4227 return MLX5_TXCMP_CODE_SINGLE;
4229 if (ret != MLX5_TXCMP_CODE_EMPW) {
4232 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
4233 return MLX5_TXCMP_CODE_ERROR;
4236 * Check whether packet parameters coincide
4237 * within assumed eMPW batch:
4238 * - check sum settings
4240 * - software parser settings
4241 * - packets length (legacy MPW only)
4242 * - scheduling is not required
4244 if (!mlx5_tx_match_empw(txq, eseg, loc, dlen, olx)) {
4247 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
4248 if (unlikely(!loc->elts_free ||
4250 return MLX5_TXCMP_CODE_EXIT;
4254 /* Packet attributes match, continue the same eMPW. */
4256 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
4257 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
4259 /* eMPW is built successfully, update loop parameters. */
4261 MLX5_ASSERT(pkts_n >= part);
4262 #ifdef MLX5_PMD_SOFT_COUNTERS
4263 /* Update sent data bytes counter. */
4264 txq->stats.obytes += slen;
4266 loc->elts_free -= part;
4267 loc->pkts_sent += part;
4268 txq->wqe_ci += (2 + part + 3) / 4;
4269 loc->wqe_free -= (2 + part + 3) / 4;
4271 if (unlikely(!pkts_n || !loc->elts_free || !loc->wqe_free))
4272 return MLX5_TXCMP_CODE_EXIT;
4273 loc->mbuf = *pkts++;
4274 ret = mlx5_tx_able_to_empw(txq, loc, olx, true);
4275 if (unlikely(ret != MLX5_TXCMP_CODE_EMPW))
4277 /* Continue sending eMPW batches. */
4283 * The routine sends packets with MLX5_OPCODE_EMPW
4284 * with inlining, optionally supports VLAN insertion.
4286 static __rte_always_inline enum mlx5_txcmp_code
4287 mlx5_tx_burst_empw_inline(struct mlx5_txq_data *__rte_restrict txq,
4288 struct rte_mbuf **__rte_restrict pkts,
4289 unsigned int pkts_n,
4290 struct mlx5_txq_local *__rte_restrict loc,
4294 * Subroutine is the part of mlx5_tx_burst_single()
4295 * and sends single-segment packet with eMPW opcode
4296 * with data inlining.
4298 MLX5_ASSERT(MLX5_TXOFF_CONFIG(INLINE));
4299 MLX5_ASSERT(MLX5_TXOFF_CONFIG(EMPW));
4300 MLX5_ASSERT(loc->elts_free && loc->wqe_free);
4301 MLX5_ASSERT(pkts_n > loc->pkts_sent);
4302 pkts += loc->pkts_sent + 1;
4303 pkts_n -= loc->pkts_sent;
4305 struct mlx5_wqe_dseg *__rte_restrict dseg;
4306 struct mlx5_wqe *__rte_restrict wqem;
4307 enum mlx5_txcmp_code ret;
4308 unsigned int room, part, nlim;
4309 unsigned int slen = 0;
4311 MLX5_ASSERT(NB_SEGS(loc->mbuf) == 1);
4312 if (MLX5_TXOFF_CONFIG(TXPP)) {
4313 enum mlx5_txcmp_code wret;
4315 /* Generate WAIT for scheduling if requested. */
4316 wret = mlx5_tx_schedule_send(txq, loc, olx);
4317 if (wret == MLX5_TXCMP_CODE_EXIT)
4318 return MLX5_TXCMP_CODE_EXIT;
4319 if (wret == MLX5_TXCMP_CODE_ERROR)
4320 return MLX5_TXCMP_CODE_ERROR;
4323 * Limits the amount of packets in one WQE
4324 * to improve CQE latency generation.
4326 nlim = RTE_MIN(pkts_n, MLX5_TXOFF_CONFIG(MPW) ?
4327 MLX5_MPW_INLINE_MAX_PACKETS :
4328 MLX5_EMPW_MAX_PACKETS);
4329 /* Check whether we have minimal amount WQEs */
4330 if (unlikely(loc->wqe_free <
4331 ((2 + MLX5_EMPW_MIN_PACKETS + 3) / 4)))
4332 return MLX5_TXCMP_CODE_EXIT;
4333 if (likely(pkts_n > 1))
4334 rte_prefetch0(*pkts);
4335 wqem = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4337 * Build eMPW title WQEBB:
4338 * - Control Segment, eMPW opcode, zero DS
4339 * - Ethernet Segment, no inline
4341 mlx5_tx_cseg_init(txq, loc, wqem, 0,
4342 MLX5_OPCODE_ENHANCED_MPSW, olx);
4343 mlx5_tx_eseg_none(txq, loc, wqem,
4344 olx & ~MLX5_TXOFF_CONFIG_VLAN);
4345 dseg = &wqem->dseg[0];
4346 /* Store the packet length for legacy MPW. */
4347 if (MLX5_TXOFF_CONFIG(MPW))
4348 wqem->eseg.mss = rte_cpu_to_be_16
4349 (rte_pktmbuf_data_len(loc->mbuf));
4350 room = RTE_MIN(MLX5_WQE_SIZE_MAX / MLX5_WQE_SIZE,
4351 loc->wqe_free) * MLX5_WQE_SIZE -
4352 MLX5_WQE_CSEG_SIZE -
4354 /* Limit the room for legacy MPW sessions for performance. */
4355 if (MLX5_TXOFF_CONFIG(MPW))
4356 room = RTE_MIN(room,
4357 RTE_MAX(txq->inlen_empw +
4358 sizeof(dseg->bcount) +
4359 (MLX5_TXOFF_CONFIG(VLAN) ?
4360 sizeof(struct rte_vlan_hdr) : 0),
4361 MLX5_MPW_INLINE_MAX_PACKETS *
4362 MLX5_WQE_DSEG_SIZE));
4363 /* Build WQE till we have space, packets and resources. */
4366 uint32_t dlen = rte_pktmbuf_data_len(loc->mbuf);
4367 uint8_t *dptr = rte_pktmbuf_mtod(loc->mbuf, uint8_t *);
4370 MLX5_ASSERT(room >= MLX5_WQE_DSEG_SIZE);
4371 MLX5_ASSERT((room % MLX5_WQE_DSEG_SIZE) == 0);
4372 MLX5_ASSERT((uintptr_t)dseg < (uintptr_t)txq->wqes_end);
4374 * Some Tx offloads may cause an error if
4375 * packet is not long enough, check against
4376 * assumed minimal length.
4378 if (unlikely(dlen <= MLX5_ESEG_MIN_INLINE_SIZE)) {
4380 if (unlikely(!part))
4381 return MLX5_TXCMP_CODE_ERROR;
4383 * We have some successfully built
4384 * packet Data Segments to send.
4386 mlx5_tx_idone_empw(txq, loc, part,
4388 return MLX5_TXCMP_CODE_ERROR;
4390 /* Inline or not inline - that's the Question. */
4391 if (dlen > txq->inlen_empw ||
4392 loc->mbuf->ol_flags & PKT_TX_DYNF_NOINLINE)
4394 if (MLX5_TXOFF_CONFIG(MPW)) {
4395 if (dlen > txq->inlen_send)
4399 /* Open new inline MPW session. */
4400 tlen += sizeof(dseg->bcount);
4401 dseg->bcount = RTE_BE32(0);
4403 (dseg, sizeof(dseg->bcount));
4406 * No pointer and inline descriptor
4407 * intermix for legacy MPW sessions.
4409 if (wqem->dseg[0].bcount)
4413 tlen = sizeof(dseg->bcount) + dlen;
4415 /* Inline entire packet, optional VLAN insertion. */
4416 if (MLX5_TXOFF_CONFIG(VLAN) &&
4417 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) {
4419 * The packet length must be checked in
4420 * mlx5_tx_able_to_empw() and packet
4421 * fits into inline length guaranteed.
4424 sizeof(struct rte_vlan_hdr)) <=
4426 tlen += sizeof(struct rte_vlan_hdr);
4429 dseg = mlx5_tx_dseg_vlan(txq, loc, dseg,
4431 #ifdef MLX5_PMD_SOFT_COUNTERS
4432 /* Update sent data bytes counter. */
4433 slen += sizeof(struct rte_vlan_hdr);
4438 dseg = mlx5_tx_dseg_empw(txq, loc, dseg,
4441 if (!MLX5_TXOFF_CONFIG(MPW))
4442 tlen = RTE_ALIGN(tlen, MLX5_WSEG_SIZE);
4443 MLX5_ASSERT(room >= tlen);
4446 * Packet data are completely inline,
4447 * we can try to free the packet.
4449 if (likely(loc->pkts_sent == loc->mbuf_free)) {
4451 * All the packets from the burst beginning
4452 * are inline, we can free mbufs directly
4453 * from the origin array on tx_burst exit().
4459 * In order no to call rte_pktmbuf_free_seg() here,
4460 * in the most inner loop (that might be very
4461 * expensive) we just save the mbuf in elts.
4463 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
4468 * No pointer and inline descriptor
4469 * intermix for legacy MPW sessions.
4471 if (MLX5_TXOFF_CONFIG(MPW) &&
4473 wqem->dseg[0].bcount == RTE_BE32(0))
4476 * Not inlinable VLAN packets are
4477 * proceeded outside of this routine.
4479 MLX5_ASSERT(room >= MLX5_WQE_DSEG_SIZE);
4480 if (MLX5_TXOFF_CONFIG(VLAN))
4481 MLX5_ASSERT(!(loc->mbuf->ol_flags &
4483 mlx5_tx_dseg_ptr(txq, loc, dseg, dptr, dlen, olx);
4484 /* We have to store mbuf in elts.*/
4485 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
4487 room -= MLX5_WQE_DSEG_SIZE;
4488 /* Ring buffer wraparound is checked at the loop end.*/
4491 #ifdef MLX5_PMD_SOFT_COUNTERS
4492 /* Update sent data bytes counter. */
4497 if (unlikely(!pkts_n || !loc->elts_free)) {
4499 * We have no resources/packets to
4500 * continue build descriptors.
4503 mlx5_tx_idone_empw(txq, loc, part,
4505 return MLX5_TXCMP_CODE_EXIT;
4507 loc->mbuf = *pkts++;
4508 if (likely(pkts_n > 1))
4509 rte_prefetch0(*pkts);
4510 ret = mlx5_tx_able_to_empw(txq, loc, olx, true);
4512 * Unroll the completion code to avoid
4513 * returning variable value - it results in
4514 * unoptimized sequent checking in caller.
4516 if (ret == MLX5_TXCMP_CODE_MULTI) {
4518 mlx5_tx_idone_empw(txq, loc, part,
4520 if (unlikely(!loc->elts_free ||
4522 return MLX5_TXCMP_CODE_EXIT;
4523 return MLX5_TXCMP_CODE_MULTI;
4525 MLX5_ASSERT(NB_SEGS(loc->mbuf) == 1);
4526 if (ret == MLX5_TXCMP_CODE_TSO) {
4528 mlx5_tx_idone_empw(txq, loc, part,
4530 if (unlikely(!loc->elts_free ||
4532 return MLX5_TXCMP_CODE_EXIT;
4533 return MLX5_TXCMP_CODE_TSO;
4535 if (ret == MLX5_TXCMP_CODE_SINGLE) {
4537 mlx5_tx_idone_empw(txq, loc, part,
4539 if (unlikely(!loc->elts_free ||
4541 return MLX5_TXCMP_CODE_EXIT;
4542 return MLX5_TXCMP_CODE_SINGLE;
4544 if (ret != MLX5_TXCMP_CODE_EMPW) {
4547 mlx5_tx_idone_empw(txq, loc, part,
4549 return MLX5_TXCMP_CODE_ERROR;
4551 /* Check if we have minimal room left. */
4553 if (unlikely(!nlim || room < MLX5_WQE_DSEG_SIZE))
4556 * Check whether packet parameters coincide
4557 * within assumed eMPW batch:
4558 * - check sum settings
4560 * - software parser settings
4561 * - packets length (legacy MPW only)
4562 * - scheduling is not required
4564 if (!mlx5_tx_match_empw(txq, &wqem->eseg,
4567 /* Packet attributes match, continue the same eMPW. */
4568 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
4569 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
4572 * We get here to close an existing eMPW
4573 * session and start the new one.
4575 MLX5_ASSERT(pkts_n);
4577 if (unlikely(!part))
4578 return MLX5_TXCMP_CODE_EXIT;
4579 mlx5_tx_idone_empw(txq, loc, part, slen, wqem, olx);
4580 if (unlikely(!loc->elts_free ||
4582 return MLX5_TXCMP_CODE_EXIT;
4583 /* Continue the loop with new eMPW session. */
4589 * The routine sends packets with ordinary MLX5_OPCODE_SEND.
4590 * Data inlining and VLAN insertion are supported.
4592 static __rte_always_inline enum mlx5_txcmp_code
4593 mlx5_tx_burst_single_send(struct mlx5_txq_data *__rte_restrict txq,
4594 struct rte_mbuf **__rte_restrict pkts,
4595 unsigned int pkts_n,
4596 struct mlx5_txq_local *__rte_restrict loc,
4600 * Subroutine is the part of mlx5_tx_burst_single()
4601 * and sends single-segment packet with SEND opcode.
4603 MLX5_ASSERT(loc->elts_free && loc->wqe_free);
4604 MLX5_ASSERT(pkts_n > loc->pkts_sent);
4605 pkts += loc->pkts_sent + 1;
4606 pkts_n -= loc->pkts_sent;
4608 struct mlx5_wqe *__rte_restrict wqe;
4609 enum mlx5_txcmp_code ret;
4611 MLX5_ASSERT(NB_SEGS(loc->mbuf) == 1);
4612 if (MLX5_TXOFF_CONFIG(TXPP)) {
4613 enum mlx5_txcmp_code wret;
4615 /* Generate WAIT for scheduling if requested. */
4616 wret = mlx5_tx_schedule_send(txq, loc, olx);
4617 if (wret == MLX5_TXCMP_CODE_EXIT)
4618 return MLX5_TXCMP_CODE_EXIT;
4619 if (wret == MLX5_TXCMP_CODE_ERROR)
4620 return MLX5_TXCMP_CODE_ERROR;
4622 if (MLX5_TXOFF_CONFIG(INLINE)) {
4623 unsigned int inlen, vlan = 0;
4625 inlen = rte_pktmbuf_data_len(loc->mbuf);
4626 if (MLX5_TXOFF_CONFIG(VLAN) &&
4627 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) {
4628 vlan = sizeof(struct rte_vlan_hdr);
4632 * If inlining is enabled at configuration time
4633 * the limit must be not less than minimal size.
4634 * Otherwise we would do extra check for data
4635 * size to avoid crashes due to length overflow.
4637 MLX5_ASSERT(txq->inlen_send >=
4638 MLX5_ESEG_MIN_INLINE_SIZE);
4639 if (inlen <= txq->inlen_send) {
4640 unsigned int seg_n, wqe_n;
4642 rte_prefetch0(rte_pktmbuf_mtod
4643 (loc->mbuf, uint8_t *));
4644 /* Check against minimal length. */
4645 if (inlen <= MLX5_ESEG_MIN_INLINE_SIZE)
4646 return MLX5_TXCMP_CODE_ERROR;
4647 if (loc->mbuf->ol_flags &
4648 PKT_TX_DYNF_NOINLINE) {
4650 * The hint flag not to inline packet
4651 * data is set. Check whether we can
4654 if ((!MLX5_TXOFF_CONFIG(EMPW) &&
4656 (MLX5_TXOFF_CONFIG(MPW) &&
4658 if (inlen <= txq->inlen_send)
4661 * The hardware requires the
4662 * minimal inline data header.
4664 goto single_min_inline;
4666 if (MLX5_TXOFF_CONFIG(VLAN) &&
4667 vlan && !txq->vlan_en) {
4669 * We must insert VLAN tag
4670 * by software means.
4672 goto single_part_inline;
4674 goto single_no_inline;
4678 * Completely inlined packet data WQE:
4679 * - Control Segment, SEND opcode
4680 * - Ethernet Segment, no VLAN insertion
4681 * - Data inlined, VLAN optionally inserted
4682 * - Alignment to MLX5_WSEG_SIZE
4683 * Have to estimate amount of WQEBBs
4685 seg_n = (inlen + 3 * MLX5_WSEG_SIZE -
4686 MLX5_ESEG_MIN_INLINE_SIZE +
4687 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
4688 /* Check if there are enough WQEBBs. */
4689 wqe_n = (seg_n + 3) / 4;
4690 if (wqe_n > loc->wqe_free)
4691 return MLX5_TXCMP_CODE_EXIT;
4692 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4693 loc->wqe_last = wqe;
4694 mlx5_tx_cseg_init(txq, loc, wqe, seg_n,
4695 MLX5_OPCODE_SEND, olx);
4696 mlx5_tx_eseg_data(txq, loc, wqe,
4697 vlan, inlen, 0, olx);
4698 txq->wqe_ci += wqe_n;
4699 loc->wqe_free -= wqe_n;
4701 * Packet data are completely inlined,
4702 * free the packet immediately.
4704 rte_pktmbuf_free_seg(loc->mbuf);
4705 } else if ((!MLX5_TXOFF_CONFIG(EMPW) ||
4706 MLX5_TXOFF_CONFIG(MPW)) &&
4709 * If minimal inlining is requested the eMPW
4710 * feature should be disabled due to data is
4711 * inlined into Ethernet Segment, which can
4712 * not contain inlined data for eMPW due to
4713 * segment shared for all packets.
4715 struct mlx5_wqe_dseg *__rte_restrict dseg;
4720 * The inline-mode settings require
4721 * to inline the specified amount of
4722 * data bytes to the Ethernet Segment.
4723 * We should check the free space in
4724 * WQE ring buffer to inline partially.
4727 MLX5_ASSERT(txq->inlen_send >= txq->inlen_mode);
4728 MLX5_ASSERT(inlen > txq->inlen_mode);
4729 MLX5_ASSERT(txq->inlen_mode >=
4730 MLX5_ESEG_MIN_INLINE_SIZE);
4732 * Check whether there are enough free WQEBBs:
4734 * - Ethernet Segment
4735 * - First Segment of inlined Ethernet data
4736 * - ... data continued ...
4737 * - Finishing Data Segment of pointer type
4739 ds = (MLX5_WQE_CSEG_SIZE +
4740 MLX5_WQE_ESEG_SIZE +
4741 MLX5_WQE_DSEG_SIZE +
4743 MLX5_ESEG_MIN_INLINE_SIZE +
4744 MLX5_WQE_DSEG_SIZE +
4745 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
4746 if (loc->wqe_free < ((ds + 3) / 4))
4747 return MLX5_TXCMP_CODE_EXIT;
4749 * Build the ordinary SEND WQE:
4751 * - Ethernet Segment, inline inlen_mode bytes
4752 * - Data Segment of pointer type
4754 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4755 loc->wqe_last = wqe;
4756 mlx5_tx_cseg_init(txq, loc, wqe, ds,
4757 MLX5_OPCODE_SEND, olx);
4758 dseg = mlx5_tx_eseg_data(txq, loc, wqe, vlan,
4761 dptr = rte_pktmbuf_mtod(loc->mbuf, uint8_t *) +
4762 txq->inlen_mode - vlan;
4763 inlen -= txq->inlen_mode;
4764 mlx5_tx_dseg_ptr(txq, loc, dseg,
4767 * WQE is built, update the loop parameters
4768 * and got to the next packet.
4770 txq->wqe_ci += (ds + 3) / 4;
4771 loc->wqe_free -= (ds + 3) / 4;
4772 /* We have to store mbuf in elts.*/
4773 MLX5_ASSERT(MLX5_TXOFF_CONFIG(INLINE));
4774 txq->elts[txq->elts_head++ & txq->elts_m] =
4782 * Partially inlined packet data WQE, we have
4783 * some space in title WQEBB, we can fill it
4784 * with some packet data. It takes one WQEBB,
4785 * it is available, no extra space check:
4786 * - Control Segment, SEND opcode
4787 * - Ethernet Segment, no VLAN insertion
4788 * - MLX5_ESEG_MIN_INLINE_SIZE bytes of Data
4789 * - Data Segment, pointer type
4791 * We also get here if VLAN insertion is not
4792 * supported by HW, the inline is enabled.
4795 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4796 loc->wqe_last = wqe;
4797 mlx5_tx_cseg_init(txq, loc, wqe, 4,
4798 MLX5_OPCODE_SEND, olx);
4799 mlx5_tx_eseg_dmin(txq, loc, wqe, vlan, olx);
4800 dptr = rte_pktmbuf_mtod(loc->mbuf, uint8_t *) +
4801 MLX5_ESEG_MIN_INLINE_SIZE - vlan;
4803 * The length check is performed above, by
4804 * comparing with txq->inlen_send. We should
4805 * not get overflow here.
4807 MLX5_ASSERT(inlen > MLX5_ESEG_MIN_INLINE_SIZE);
4808 dlen = inlen - MLX5_ESEG_MIN_INLINE_SIZE;
4809 mlx5_tx_dseg_ptr(txq, loc, &wqe->dseg[1],
4813 /* We have to store mbuf in elts.*/
4814 MLX5_ASSERT(MLX5_TXOFF_CONFIG(INLINE));
4815 txq->elts[txq->elts_head++ & txq->elts_m] =
4819 #ifdef MLX5_PMD_SOFT_COUNTERS
4820 /* Update sent data bytes counter. */
4821 txq->stats.obytes += vlan +
4822 rte_pktmbuf_data_len(loc->mbuf);
4826 * No inline at all, it means the CPU cycles saving
4827 * is prioritized at configuration, we should not
4828 * copy any packet data to WQE.
4830 * SEND WQE, one WQEBB:
4831 * - Control Segment, SEND opcode
4832 * - Ethernet Segment, optional VLAN, no inline
4833 * - Data Segment, pointer type
4836 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4837 loc->wqe_last = wqe;
4838 mlx5_tx_cseg_init(txq, loc, wqe, 3,
4839 MLX5_OPCODE_SEND, olx);
4840 mlx5_tx_eseg_none(txq, loc, wqe, olx);
4842 (txq, loc, &wqe->dseg[0],
4843 rte_pktmbuf_mtod(loc->mbuf, uint8_t *),
4844 rte_pktmbuf_data_len(loc->mbuf), olx);
4848 * We should not store mbuf pointer in elts
4849 * if no inlining is configured, this is done
4850 * by calling routine in a batch copy.
4852 MLX5_ASSERT(!MLX5_TXOFF_CONFIG(INLINE));
4854 #ifdef MLX5_PMD_SOFT_COUNTERS
4855 /* Update sent data bytes counter. */
4856 txq->stats.obytes += rte_pktmbuf_data_len(loc->mbuf);
4857 if (MLX5_TXOFF_CONFIG(VLAN) &&
4858 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT)
4859 txq->stats.obytes +=
4860 sizeof(struct rte_vlan_hdr);
4865 if (unlikely(!pkts_n || !loc->elts_free || !loc->wqe_free))
4866 return MLX5_TXCMP_CODE_EXIT;
4867 loc->mbuf = *pkts++;
4869 rte_prefetch0(*pkts);
4870 ret = mlx5_tx_able_to_empw(txq, loc, olx, true);
4871 if (unlikely(ret != MLX5_TXCMP_CODE_SINGLE))
4877 static __rte_always_inline enum mlx5_txcmp_code
4878 mlx5_tx_burst_single(struct mlx5_txq_data *__rte_restrict txq,
4879 struct rte_mbuf **__rte_restrict pkts,
4880 unsigned int pkts_n,
4881 struct mlx5_txq_local *__rte_restrict loc,
4884 enum mlx5_txcmp_code ret;
4886 ret = mlx5_tx_able_to_empw(txq, loc, olx, false);
4887 if (ret == MLX5_TXCMP_CODE_SINGLE)
4889 MLX5_ASSERT(ret == MLX5_TXCMP_CODE_EMPW);
4891 /* Optimize for inline/no inline eMPW send. */
4892 ret = (MLX5_TXOFF_CONFIG(INLINE)) ?
4893 mlx5_tx_burst_empw_inline
4894 (txq, pkts, pkts_n, loc, olx) :
4895 mlx5_tx_burst_empw_simple
4896 (txq, pkts, pkts_n, loc, olx);
4897 if (ret != MLX5_TXCMP_CODE_SINGLE)
4899 /* The resources to send one packet should remain. */
4900 MLX5_ASSERT(loc->elts_free && loc->wqe_free);
4902 ret = mlx5_tx_burst_single_send(txq, pkts, pkts_n, loc, olx);
4903 MLX5_ASSERT(ret != MLX5_TXCMP_CODE_SINGLE);
4904 if (ret != MLX5_TXCMP_CODE_EMPW)
4906 /* The resources to send one packet should remain. */
4907 MLX5_ASSERT(loc->elts_free && loc->wqe_free);
4912 * DPDK Tx callback template. This is configured template
4913 * used to generate routines optimized for specified offload setup.
4914 * One of this generated functions is chosen at SQ configuration
4918 * Generic pointer to TX queue structure.
4920 * Packets to transmit.
4922 * Number of packets in array.
4924 * Configured offloads mask, presents the bits of MLX5_TXOFF_CONFIG_xxx
4925 * values. Should be static to take compile time static configuration
4929 * Number of packets successfully transmitted (<= pkts_n).
4931 static __rte_always_inline uint16_t
4932 mlx5_tx_burst_tmpl(struct mlx5_txq_data *__rte_restrict txq,
4933 struct rte_mbuf **__rte_restrict pkts,
4937 struct mlx5_txq_local loc;
4938 enum mlx5_txcmp_code ret;
4941 MLX5_ASSERT(txq->elts_s >= (uint16_t)(txq->elts_head - txq->elts_tail));
4942 MLX5_ASSERT(txq->wqe_s >= (uint16_t)(txq->wqe_ci - txq->wqe_pi));
4943 if (unlikely(!pkts_n))
4945 if (MLX5_TXOFF_CONFIG(INLINE))
4949 loc.wqe_last = NULL;
4952 loc.pkts_loop = loc.pkts_sent;
4954 * Check if there are some CQEs, if any:
4955 * - process an encountered errors
4956 * - process the completed WQEs
4957 * - free related mbufs
4958 * - doorbell the NIC about processed CQEs
4960 rte_prefetch0(*(pkts + loc.pkts_sent));
4961 mlx5_tx_handle_completion(txq, olx);
4963 * Calculate the number of available resources - elts and WQEs.
4964 * There are two possible different scenarios:
4965 * - no data inlining into WQEs, one WQEBB may contains up to
4966 * four packets, in this case elts become scarce resource
4967 * - data inlining into WQEs, one packet may require multiple
4968 * WQEBBs, the WQEs become the limiting factor.
4970 MLX5_ASSERT(txq->elts_s >= (uint16_t)(txq->elts_head - txq->elts_tail));
4971 loc.elts_free = txq->elts_s -
4972 (uint16_t)(txq->elts_head - txq->elts_tail);
4973 MLX5_ASSERT(txq->wqe_s >= (uint16_t)(txq->wqe_ci - txq->wqe_pi));
4974 loc.wqe_free = txq->wqe_s -
4975 (uint16_t)(txq->wqe_ci - txq->wqe_pi);
4976 if (unlikely(!loc.elts_free || !loc.wqe_free))
4980 * Fetch the packet from array. Usually this is
4981 * the first packet in series of multi/single
4984 loc.mbuf = *(pkts + loc.pkts_sent);
4985 /* Dedicated branch for multi-segment packets. */
4986 if (MLX5_TXOFF_CONFIG(MULTI) &&
4987 unlikely(NB_SEGS(loc.mbuf) > 1)) {
4989 * Multi-segment packet encountered.
4990 * Hardware is able to process it only
4991 * with SEND/TSO opcodes, one packet
4992 * per WQE, do it in dedicated routine.
4995 MLX5_ASSERT(loc.pkts_sent >= loc.pkts_copy);
4996 part = loc.pkts_sent - loc.pkts_copy;
4997 if (!MLX5_TXOFF_CONFIG(INLINE) && part) {
4999 * There are some single-segment mbufs not
5000 * stored in elts. The mbufs must be in the
5001 * same order as WQEs, so we must copy the
5002 * mbufs to elts here, before the coming
5003 * multi-segment packet mbufs is appended.
5005 mlx5_tx_copy_elts(txq, pkts + loc.pkts_copy,
5007 loc.pkts_copy = loc.pkts_sent;
5009 MLX5_ASSERT(pkts_n > loc.pkts_sent);
5010 ret = mlx5_tx_burst_mseg(txq, pkts, pkts_n, &loc, olx);
5011 if (!MLX5_TXOFF_CONFIG(INLINE))
5012 loc.pkts_copy = loc.pkts_sent;
5014 * These returned code checks are supposed
5015 * to be optimized out due to routine inlining.
5017 if (ret == MLX5_TXCMP_CODE_EXIT) {
5019 * The routine returns this code when
5020 * all packets are sent or there is no
5021 * enough resources to complete request.
5025 if (ret == MLX5_TXCMP_CODE_ERROR) {
5027 * The routine returns this code when
5028 * some error in the incoming packets
5031 txq->stats.oerrors++;
5034 if (ret == MLX5_TXCMP_CODE_SINGLE) {
5036 * The single-segment packet was encountered
5037 * in the array, try to send it with the
5038 * best optimized way, possible engaging eMPW.
5040 goto enter_send_single;
5042 if (MLX5_TXOFF_CONFIG(TSO) &&
5043 ret == MLX5_TXCMP_CODE_TSO) {
5045 * The single-segment TSO packet was
5046 * encountered in the array.
5048 goto enter_send_tso;
5050 /* We must not get here. Something is going wrong. */
5052 txq->stats.oerrors++;
5055 /* Dedicated branch for single-segment TSO packets. */
5056 if (MLX5_TXOFF_CONFIG(TSO) &&
5057 unlikely(loc.mbuf->ol_flags & PKT_TX_TCP_SEG)) {
5059 * TSO might require special way for inlining
5060 * (dedicated parameters) and is sent with
5061 * MLX5_OPCODE_TSO opcode only, provide this
5062 * in dedicated branch.
5065 MLX5_ASSERT(NB_SEGS(loc.mbuf) == 1);
5066 MLX5_ASSERT(pkts_n > loc.pkts_sent);
5067 ret = mlx5_tx_burst_tso(txq, pkts, pkts_n, &loc, olx);
5069 * These returned code checks are supposed
5070 * to be optimized out due to routine inlining.
5072 if (ret == MLX5_TXCMP_CODE_EXIT)
5074 if (ret == MLX5_TXCMP_CODE_ERROR) {
5075 txq->stats.oerrors++;
5078 if (ret == MLX5_TXCMP_CODE_SINGLE)
5079 goto enter_send_single;
5080 if (MLX5_TXOFF_CONFIG(MULTI) &&
5081 ret == MLX5_TXCMP_CODE_MULTI) {
5083 * The multi-segment packet was
5084 * encountered in the array.
5086 goto enter_send_multi;
5088 /* We must not get here. Something is going wrong. */
5090 txq->stats.oerrors++;
5094 * The dedicated branch for the single-segment packets
5095 * without TSO. Often these ones can be sent using
5096 * MLX5_OPCODE_EMPW with multiple packets in one WQE.
5097 * The routine builds the WQEs till it encounters
5098 * the TSO or multi-segment packet (in case if these
5099 * offloads are requested at SQ configuration time).
5102 MLX5_ASSERT(pkts_n > loc.pkts_sent);
5103 ret = mlx5_tx_burst_single(txq, pkts, pkts_n, &loc, olx);
5105 * These returned code checks are supposed
5106 * to be optimized out due to routine inlining.
5108 if (ret == MLX5_TXCMP_CODE_EXIT)
5110 if (ret == MLX5_TXCMP_CODE_ERROR) {
5111 txq->stats.oerrors++;
5114 if (MLX5_TXOFF_CONFIG(MULTI) &&
5115 ret == MLX5_TXCMP_CODE_MULTI) {
5117 * The multi-segment packet was
5118 * encountered in the array.
5120 goto enter_send_multi;
5122 if (MLX5_TXOFF_CONFIG(TSO) &&
5123 ret == MLX5_TXCMP_CODE_TSO) {
5125 * The single-segment TSO packet was
5126 * encountered in the array.
5128 goto enter_send_tso;
5130 /* We must not get here. Something is going wrong. */
5132 txq->stats.oerrors++;
5136 * Main Tx loop is completed, do the rest:
5137 * - set completion request if thresholds are reached
5138 * - doorbell the hardware
5139 * - copy the rest of mbufs to elts (if any)
5141 MLX5_ASSERT(MLX5_TXOFF_CONFIG(INLINE) ||
5142 loc.pkts_sent >= loc.pkts_copy);
5143 /* Take a shortcut if nothing is sent. */
5144 if (unlikely(loc.pkts_sent == loc.pkts_loop))
5146 /* Request CQE generation if limits are reached. */
5147 mlx5_tx_request_completion(txq, &loc, olx);
5149 * Ring QP doorbell immediately after WQE building completion
5150 * to improve latencies. The pure software related data treatment
5151 * can be completed after doorbell. Tx CQEs for this SQ are
5152 * processed in this thread only by the polling.
5154 * The rdma core library can map doorbell register in two ways,
5155 * depending on the environment variable "MLX5_SHUT_UP_BF":
5157 * - as regular cached memory, the variable is either missing or
5158 * set to zero. This type of mapping may cause the significant
5159 * doorbell register writing latency and requires explicit
5160 * memory write barrier to mitigate this issue and prevent
5163 * - as non-cached memory, the variable is present and set to
5164 * not "0" value. This type of mapping may cause performance
5165 * impact under heavy loading conditions but the explicit write
5166 * memory barrier is not required and it may improve core
5169 * - the legacy behaviour (prior 19.08 release) was to use some
5170 * heuristics to decide whether write memory barrier should
5171 * be performed. This behavior is supported with specifying
5172 * tx_db_nc=2, write barrier is skipped if application
5173 * provides the full recommended burst of packets, it
5174 * supposes the next packets are coming and the write barrier
5175 * will be issued on the next burst (after descriptor writing,
5178 mlx5_tx_dbrec_cond_wmb(txq, loc.wqe_last, !txq->db_nc &&
5179 (!txq->db_heu || pkts_n % MLX5_TX_DEFAULT_BURST));
5180 /* Not all of the mbufs may be stored into elts yet. */
5181 part = MLX5_TXOFF_CONFIG(INLINE) ? 0 : loc.pkts_sent - loc.pkts_copy;
5182 if (!MLX5_TXOFF_CONFIG(INLINE) && part) {
5184 * There are some single-segment mbufs not stored in elts.
5185 * It can be only if the last packet was single-segment.
5186 * The copying is gathered into one place due to it is
5187 * a good opportunity to optimize that with SIMD.
5188 * Unfortunately if inlining is enabled the gaps in
5189 * pointer array may happen due to early freeing of the
5192 mlx5_tx_copy_elts(txq, pkts + loc.pkts_copy, part, olx);
5193 loc.pkts_copy = loc.pkts_sent;
5195 MLX5_ASSERT(txq->elts_s >= (uint16_t)(txq->elts_head - txq->elts_tail));
5196 MLX5_ASSERT(txq->wqe_s >= (uint16_t)(txq->wqe_ci - txq->wqe_pi));
5197 if (pkts_n > loc.pkts_sent) {
5199 * If burst size is large there might be no enough CQE
5200 * fetched from completion queue and no enough resources
5201 * freed to send all the packets.
5206 #ifdef MLX5_PMD_SOFT_COUNTERS
5207 /* Increment sent packets counter. */
5208 txq->stats.opackets += loc.pkts_sent;
5210 if (MLX5_TXOFF_CONFIG(INLINE) && loc.mbuf_free)
5211 __mlx5_tx_free_mbuf(txq, pkts, loc.mbuf_free, olx);
5212 return loc.pkts_sent;
5215 /* Generate routines with Enhanced Multi-Packet Write support. */
5216 MLX5_TXOFF_DECL(full_empw,
5217 MLX5_TXOFF_CONFIG_FULL | MLX5_TXOFF_CONFIG_EMPW)
5219 MLX5_TXOFF_DECL(none_empw,
5220 MLX5_TXOFF_CONFIG_NONE | MLX5_TXOFF_CONFIG_EMPW)
5222 MLX5_TXOFF_DECL(md_empw,
5223 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5225 MLX5_TXOFF_DECL(mt_empw,
5226 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5227 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5229 MLX5_TXOFF_DECL(mtsc_empw,
5230 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5231 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5232 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5234 MLX5_TXOFF_DECL(mti_empw,
5235 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5236 MLX5_TXOFF_CONFIG_INLINE |
5237 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5239 MLX5_TXOFF_DECL(mtv_empw,
5240 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5241 MLX5_TXOFF_CONFIG_VLAN |
5242 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5244 MLX5_TXOFF_DECL(mtiv_empw,
5245 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5246 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5247 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5249 MLX5_TXOFF_DECL(sc_empw,
5250 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5251 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5253 MLX5_TXOFF_DECL(sci_empw,
5254 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5255 MLX5_TXOFF_CONFIG_INLINE |
5256 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5258 MLX5_TXOFF_DECL(scv_empw,
5259 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5260 MLX5_TXOFF_CONFIG_VLAN |
5261 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5263 MLX5_TXOFF_DECL(sciv_empw,
5264 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5265 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5266 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5268 MLX5_TXOFF_DECL(i_empw,
5269 MLX5_TXOFF_CONFIG_INLINE |
5270 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5272 MLX5_TXOFF_DECL(v_empw,
5273 MLX5_TXOFF_CONFIG_VLAN |
5274 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5276 MLX5_TXOFF_DECL(iv_empw,
5277 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5278 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5280 /* Generate routines without Enhanced Multi-Packet Write support. */
5281 MLX5_TXOFF_DECL(full,
5282 MLX5_TXOFF_CONFIG_FULL)
5284 MLX5_TXOFF_DECL(none,
5285 MLX5_TXOFF_CONFIG_NONE)
5288 MLX5_TXOFF_CONFIG_METADATA)
5291 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5292 MLX5_TXOFF_CONFIG_METADATA)
5294 MLX5_TXOFF_DECL(mtsc,
5295 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5296 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5297 MLX5_TXOFF_CONFIG_METADATA)
5299 MLX5_TXOFF_DECL(mti,
5300 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5301 MLX5_TXOFF_CONFIG_INLINE |
5302 MLX5_TXOFF_CONFIG_METADATA)
5305 MLX5_TXOFF_DECL(mtv,
5306 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5307 MLX5_TXOFF_CONFIG_VLAN |
5308 MLX5_TXOFF_CONFIG_METADATA)
5311 MLX5_TXOFF_DECL(mtiv,
5312 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5313 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5314 MLX5_TXOFF_CONFIG_METADATA)
5317 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5318 MLX5_TXOFF_CONFIG_METADATA)
5320 MLX5_TXOFF_DECL(sci,
5321 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5322 MLX5_TXOFF_CONFIG_INLINE |
5323 MLX5_TXOFF_CONFIG_METADATA)
5326 MLX5_TXOFF_DECL(scv,
5327 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5328 MLX5_TXOFF_CONFIG_VLAN |
5329 MLX5_TXOFF_CONFIG_METADATA)
5332 MLX5_TXOFF_DECL(sciv,
5333 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5334 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5335 MLX5_TXOFF_CONFIG_METADATA)
5338 MLX5_TXOFF_CONFIG_INLINE |
5339 MLX5_TXOFF_CONFIG_METADATA)
5342 MLX5_TXOFF_CONFIG_VLAN |
5343 MLX5_TXOFF_CONFIG_METADATA)
5346 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5347 MLX5_TXOFF_CONFIG_METADATA)
5349 /* Generate routines with timestamp scheduling. */
5350 MLX5_TXOFF_DECL(full_ts_nompw,
5351 MLX5_TXOFF_CONFIG_FULL | MLX5_TXOFF_CONFIG_TXPP)
5353 MLX5_TXOFF_DECL(full_ts_nompwi,
5354 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5355 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5356 MLX5_TXOFF_CONFIG_VLAN | MLX5_TXOFF_CONFIG_METADATA |
5357 MLX5_TXOFF_CONFIG_TXPP)
5359 MLX5_TXOFF_DECL(full_ts,
5360 MLX5_TXOFF_CONFIG_FULL | MLX5_TXOFF_CONFIG_TXPP |
5361 MLX5_TXOFF_CONFIG_EMPW)
5363 MLX5_TXOFF_DECL(full_ts_noi,
5364 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5365 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5366 MLX5_TXOFF_CONFIG_VLAN | MLX5_TXOFF_CONFIG_METADATA |
5367 MLX5_TXOFF_CONFIG_TXPP | MLX5_TXOFF_CONFIG_EMPW)
5369 MLX5_TXOFF_DECL(none_ts,
5370 MLX5_TXOFF_CONFIG_NONE | MLX5_TXOFF_CONFIG_TXPP |
5371 MLX5_TXOFF_CONFIG_EMPW)
5373 MLX5_TXOFF_DECL(mdi_ts,
5374 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_METADATA |
5375 MLX5_TXOFF_CONFIG_TXPP | MLX5_TXOFF_CONFIG_EMPW)
5377 MLX5_TXOFF_DECL(mti_ts,
5378 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5379 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_METADATA |
5380 MLX5_TXOFF_CONFIG_TXPP | MLX5_TXOFF_CONFIG_EMPW)
5382 MLX5_TXOFF_DECL(mtiv_ts,
5383 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5384 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5385 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_TXPP |
5386 MLX5_TXOFF_CONFIG_EMPW)
5389 * Generate routines with Legacy Multi-Packet Write support.
5390 * This mode is supported by ConnectX-4 Lx only and imposes
5391 * offload limitations, not supported:
5392 * - ACL/Flows (metadata are becoming meaningless)
5393 * - WQE Inline headers
5394 * - SRIOV (E-Switch offloads)
5396 * - tunnel encapsulation/decapsulation
5399 MLX5_TXOFF_DECL(none_mpw,
5400 MLX5_TXOFF_CONFIG_NONE | MLX5_TXOFF_CONFIG_EMPW |
5401 MLX5_TXOFF_CONFIG_MPW)
5403 MLX5_TXOFF_DECL(mci_mpw,
5404 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_CSUM |
5405 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_EMPW |
5406 MLX5_TXOFF_CONFIG_MPW)
5408 MLX5_TXOFF_DECL(mc_mpw,
5409 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_CSUM |
5410 MLX5_TXOFF_CONFIG_EMPW | MLX5_TXOFF_CONFIG_MPW)
5412 MLX5_TXOFF_DECL(i_mpw,
5413 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_EMPW |
5414 MLX5_TXOFF_CONFIG_MPW)
5417 * Array of declared and compiled Tx burst function and corresponding
5418 * supported offloads set. The array is used to select the Tx burst
5419 * function for specified offloads set at Tx queue configuration time.
5422 eth_tx_burst_t func;
5425 MLX5_TXOFF_INFO(full_empw,
5426 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5427 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5428 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5429 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5431 MLX5_TXOFF_INFO(none_empw,
5432 MLX5_TXOFF_CONFIG_NONE | MLX5_TXOFF_CONFIG_EMPW)
5434 MLX5_TXOFF_INFO(md_empw,
5435 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5437 MLX5_TXOFF_INFO(mt_empw,
5438 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5439 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5441 MLX5_TXOFF_INFO(mtsc_empw,
5442 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5443 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5444 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5446 MLX5_TXOFF_INFO(mti_empw,
5447 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5448 MLX5_TXOFF_CONFIG_INLINE |
5449 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5451 MLX5_TXOFF_INFO(mtv_empw,
5452 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5453 MLX5_TXOFF_CONFIG_VLAN |
5454 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5456 MLX5_TXOFF_INFO(mtiv_empw,
5457 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5458 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5459 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5461 MLX5_TXOFF_INFO(sc_empw,
5462 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5463 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5465 MLX5_TXOFF_INFO(sci_empw,
5466 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5467 MLX5_TXOFF_CONFIG_INLINE |
5468 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5470 MLX5_TXOFF_INFO(scv_empw,
5471 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5472 MLX5_TXOFF_CONFIG_VLAN |
5473 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5475 MLX5_TXOFF_INFO(sciv_empw,
5476 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5477 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5478 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5480 MLX5_TXOFF_INFO(i_empw,
5481 MLX5_TXOFF_CONFIG_INLINE |
5482 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5484 MLX5_TXOFF_INFO(v_empw,
5485 MLX5_TXOFF_CONFIG_VLAN |
5486 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5488 MLX5_TXOFF_INFO(iv_empw,
5489 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5490 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5492 MLX5_TXOFF_INFO(full_ts_nompw,
5493 MLX5_TXOFF_CONFIG_FULL | MLX5_TXOFF_CONFIG_TXPP)
5495 MLX5_TXOFF_INFO(full_ts_nompwi,
5496 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5497 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5498 MLX5_TXOFF_CONFIG_VLAN | MLX5_TXOFF_CONFIG_METADATA |
5499 MLX5_TXOFF_CONFIG_TXPP)
5501 MLX5_TXOFF_INFO(full_ts,
5502 MLX5_TXOFF_CONFIG_FULL | MLX5_TXOFF_CONFIG_TXPP |
5503 MLX5_TXOFF_CONFIG_EMPW)
5505 MLX5_TXOFF_INFO(full_ts_noi,
5506 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5507 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5508 MLX5_TXOFF_CONFIG_VLAN | MLX5_TXOFF_CONFIG_METADATA |
5509 MLX5_TXOFF_CONFIG_TXPP | MLX5_TXOFF_CONFIG_EMPW)
5511 MLX5_TXOFF_INFO(none_ts,
5512 MLX5_TXOFF_CONFIG_NONE | MLX5_TXOFF_CONFIG_TXPP |
5513 MLX5_TXOFF_CONFIG_EMPW)
5515 MLX5_TXOFF_INFO(mdi_ts,
5516 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_METADATA |
5517 MLX5_TXOFF_CONFIG_TXPP | MLX5_TXOFF_CONFIG_EMPW)
5519 MLX5_TXOFF_INFO(mti_ts,
5520 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5521 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_METADATA |
5522 MLX5_TXOFF_CONFIG_TXPP | MLX5_TXOFF_CONFIG_EMPW)
5524 MLX5_TXOFF_INFO(mtiv_ts,
5525 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5526 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5527 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_TXPP |
5528 MLX5_TXOFF_CONFIG_EMPW)
5530 MLX5_TXOFF_INFO(full,
5531 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5532 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5533 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5534 MLX5_TXOFF_CONFIG_METADATA)
5536 MLX5_TXOFF_INFO(none,
5537 MLX5_TXOFF_CONFIG_NONE)
5540 MLX5_TXOFF_CONFIG_METADATA)
5543 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5544 MLX5_TXOFF_CONFIG_METADATA)
5546 MLX5_TXOFF_INFO(mtsc,
5547 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5548 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5549 MLX5_TXOFF_CONFIG_METADATA)
5551 MLX5_TXOFF_INFO(mti,
5552 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5553 MLX5_TXOFF_CONFIG_INLINE |
5554 MLX5_TXOFF_CONFIG_METADATA)
5556 MLX5_TXOFF_INFO(mtv,
5557 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5558 MLX5_TXOFF_CONFIG_VLAN |
5559 MLX5_TXOFF_CONFIG_METADATA)
5561 MLX5_TXOFF_INFO(mtiv,
5562 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5563 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5564 MLX5_TXOFF_CONFIG_METADATA)
5567 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5568 MLX5_TXOFF_CONFIG_METADATA)
5570 MLX5_TXOFF_INFO(sci,
5571 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5572 MLX5_TXOFF_CONFIG_INLINE |
5573 MLX5_TXOFF_CONFIG_METADATA)
5575 MLX5_TXOFF_INFO(scv,
5576 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5577 MLX5_TXOFF_CONFIG_VLAN |
5578 MLX5_TXOFF_CONFIG_METADATA)
5580 MLX5_TXOFF_INFO(sciv,
5581 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5582 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5583 MLX5_TXOFF_CONFIG_METADATA)
5586 MLX5_TXOFF_CONFIG_INLINE |
5587 MLX5_TXOFF_CONFIG_METADATA)
5590 MLX5_TXOFF_CONFIG_VLAN |
5591 MLX5_TXOFF_CONFIG_METADATA)
5594 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5595 MLX5_TXOFF_CONFIG_METADATA)
5597 MLX5_TXOFF_INFO(none_mpw,
5598 MLX5_TXOFF_CONFIG_NONE | MLX5_TXOFF_CONFIG_EMPW |
5599 MLX5_TXOFF_CONFIG_MPW)
5601 MLX5_TXOFF_INFO(mci_mpw,
5602 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_CSUM |
5603 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_EMPW |
5604 MLX5_TXOFF_CONFIG_MPW)
5606 MLX5_TXOFF_INFO(mc_mpw,
5607 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_CSUM |
5608 MLX5_TXOFF_CONFIG_EMPW | MLX5_TXOFF_CONFIG_MPW)
5610 MLX5_TXOFF_INFO(i_mpw,
5611 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_EMPW |
5612 MLX5_TXOFF_CONFIG_MPW)
5616 * Configure the Tx function to use. The routine checks configured
5617 * Tx offloads for the device and selects appropriate Tx burst
5618 * routine. There are multiple Tx burst routines compiled from
5619 * the same template in the most optimal way for the dedicated
5623 * Pointer to private data structure.
5626 * Pointer to selected Tx burst function.
5629 mlx5_select_tx_function(struct rte_eth_dev *dev)
5631 struct mlx5_priv *priv = dev->data->dev_private;
5632 struct mlx5_dev_config *config = &priv->config;
5633 uint64_t tx_offloads = dev->data->dev_conf.txmode.offloads;
5634 unsigned int diff = 0, olx = 0, i, m;
5637 if (tx_offloads & DEV_TX_OFFLOAD_MULTI_SEGS) {
5638 /* We should support Multi-Segment Packets. */
5639 olx |= MLX5_TXOFF_CONFIG_MULTI;
5641 if (tx_offloads & (DEV_TX_OFFLOAD_TCP_TSO |
5642 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
5643 DEV_TX_OFFLOAD_GRE_TNL_TSO |
5644 DEV_TX_OFFLOAD_IP_TNL_TSO |
5645 DEV_TX_OFFLOAD_UDP_TNL_TSO)) {
5646 /* We should support TCP Send Offload. */
5647 olx |= MLX5_TXOFF_CONFIG_TSO;
5649 if (tx_offloads & (DEV_TX_OFFLOAD_IP_TNL_TSO |
5650 DEV_TX_OFFLOAD_UDP_TNL_TSO |
5651 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM)) {
5652 /* We should support Software Parser for Tunnels. */
5653 olx |= MLX5_TXOFF_CONFIG_SWP;
5655 if (tx_offloads & (DEV_TX_OFFLOAD_IPV4_CKSUM |
5656 DEV_TX_OFFLOAD_UDP_CKSUM |
5657 DEV_TX_OFFLOAD_TCP_CKSUM |
5658 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM)) {
5659 /* We should support IP/TCP/UDP Checksums. */
5660 olx |= MLX5_TXOFF_CONFIG_CSUM;
5662 if (tx_offloads & DEV_TX_OFFLOAD_VLAN_INSERT) {
5663 /* We should support VLAN insertion. */
5664 olx |= MLX5_TXOFF_CONFIG_VLAN;
5666 if (tx_offloads & DEV_TX_OFFLOAD_SEND_ON_TIMESTAMP &&
5667 rte_mbuf_dynflag_lookup
5668 (RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME, NULL) >= 0 &&
5669 rte_mbuf_dynfield_lookup
5670 (RTE_MBUF_DYNFIELD_TIMESTAMP_NAME, NULL) >= 0) {
5671 /* Offload configured, dynamic entities registered. */
5672 olx |= MLX5_TXOFF_CONFIG_TXPP;
5674 if (priv->txqs_n && (*priv->txqs)[0]) {
5675 struct mlx5_txq_data *txd = (*priv->txqs)[0];
5677 if (txd->inlen_send) {
5679 * Check the data inline requirements. Data inline
5680 * is enabled on per device basis, we can check
5681 * the first Tx queue only.
5683 * If device does not support VLAN insertion in WQE
5684 * and some queues are requested to perform VLAN
5685 * insertion offload than inline must be enabled.
5687 olx |= MLX5_TXOFF_CONFIG_INLINE;
5690 if (config->mps == MLX5_MPW_ENHANCED &&
5691 config->txq_inline_min <= 0) {
5693 * The NIC supports Enhanced Multi-Packet Write
5694 * and does not require minimal inline data.
5696 olx |= MLX5_TXOFF_CONFIG_EMPW;
5698 if (rte_flow_dynf_metadata_avail()) {
5699 /* We should support Flow metadata. */
5700 olx |= MLX5_TXOFF_CONFIG_METADATA;
5702 if (config->mps == MLX5_MPW) {
5704 * The NIC supports Legacy Multi-Packet Write.
5705 * The MLX5_TXOFF_CONFIG_MPW controls the
5706 * descriptor building method in combination
5707 * with MLX5_TXOFF_CONFIG_EMPW.
5709 if (!(olx & (MLX5_TXOFF_CONFIG_TSO |
5710 MLX5_TXOFF_CONFIG_SWP |
5711 MLX5_TXOFF_CONFIG_VLAN |
5712 MLX5_TXOFF_CONFIG_METADATA)))
5713 olx |= MLX5_TXOFF_CONFIG_EMPW |
5714 MLX5_TXOFF_CONFIG_MPW;
5717 * Scan the routines table to find the minimal
5718 * satisfying routine with requested offloads.
5720 m = RTE_DIM(txoff_func);
5721 for (i = 0; i < RTE_DIM(txoff_func); i++) {
5724 tmp = txoff_func[i].olx;
5726 /* Meets requested offloads exactly.*/
5730 if ((tmp & olx) != olx) {
5731 /* Does not meet requested offloads at all. */
5734 if ((olx ^ tmp) & MLX5_TXOFF_CONFIG_MPW)
5735 /* Do not enable legacy MPW if not configured. */
5737 if ((olx ^ tmp) & MLX5_TXOFF_CONFIG_EMPW)
5738 /* Do not enable eMPW if not configured. */
5740 if ((olx ^ tmp) & MLX5_TXOFF_CONFIG_INLINE)
5741 /* Do not enable inlining if not configured. */
5743 if ((olx ^ tmp) & MLX5_TXOFF_CONFIG_TXPP)
5744 /* Do not enable scheduling if not configured. */
5747 * Some routine meets the requirements.
5748 * Check whether it has minimal amount
5749 * of not requested offloads.
5751 tmp = __builtin_popcountl(tmp & ~olx);
5752 if (m >= RTE_DIM(txoff_func) || tmp < diff) {
5753 /* First or better match, save and continue. */
5759 tmp = txoff_func[i].olx ^ txoff_func[m].olx;
5760 if (__builtin_ffsl(txoff_func[i].olx & ~tmp) <
5761 __builtin_ffsl(txoff_func[m].olx & ~tmp)) {
5762 /* Lighter not requested offload. */
5767 if (m >= RTE_DIM(txoff_func)) {
5768 DRV_LOG(DEBUG, "port %u has no selected Tx function"
5769 " for requested offloads %04X",
5770 dev->data->port_id, olx);
5773 DRV_LOG(DEBUG, "port %u has selected Tx function"
5774 " supporting offloads %04X/%04X",
5775 dev->data->port_id, olx, txoff_func[m].olx);
5776 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_MULTI)
5777 DRV_LOG(DEBUG, "\tMULTI (multi segment)");
5778 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_TSO)
5779 DRV_LOG(DEBUG, "\tTSO (TCP send offload)");
5780 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_SWP)
5781 DRV_LOG(DEBUG, "\tSWP (software parser)");
5782 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_CSUM)
5783 DRV_LOG(DEBUG, "\tCSUM (checksum offload)");
5784 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_INLINE)
5785 DRV_LOG(DEBUG, "\tINLIN (inline data)");
5786 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_VLAN)
5787 DRV_LOG(DEBUG, "\tVLANI (VLAN insertion)");
5788 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_METADATA)
5789 DRV_LOG(DEBUG, "\tMETAD (tx Flow metadata)");
5790 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_TXPP)
5791 DRV_LOG(DEBUG, "\tMETAD (tx Scheduling)");
5792 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_EMPW) {
5793 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_MPW)
5794 DRV_LOG(DEBUG, "\tMPW (Legacy MPW)");
5796 DRV_LOG(DEBUG, "\tEMPW (Enhanced MPW)");
5798 return txoff_func[m].func;
5802 * DPDK callback to get the TX queue information
5805 * Pointer to the device structure.
5807 * @param tx_queue_id
5808 * Tx queue identificator.
5811 * Pointer to the TX queue information structure.
5818 mlx5_txq_info_get(struct rte_eth_dev *dev, uint16_t tx_queue_id,
5819 struct rte_eth_txq_info *qinfo)
5821 struct mlx5_priv *priv = dev->data->dev_private;
5822 struct mlx5_txq_data *txq = (*priv->txqs)[tx_queue_id];
5823 struct mlx5_txq_ctrl *txq_ctrl =
5824 container_of(txq, struct mlx5_txq_ctrl, txq);
5828 qinfo->nb_desc = txq->elts_s;
5829 qinfo->conf.tx_thresh.pthresh = 0;
5830 qinfo->conf.tx_thresh.hthresh = 0;
5831 qinfo->conf.tx_thresh.wthresh = 0;
5832 qinfo->conf.tx_rs_thresh = 0;
5833 qinfo->conf.tx_free_thresh = 0;
5834 qinfo->conf.tx_deferred_start = txq_ctrl ? 0 : 1;
5835 qinfo->conf.offloads = dev->data->dev_conf.txmode.offloads;
5839 * DPDK callback to get the TX packet burst mode information
5842 * Pointer to the device structure.
5844 * @param tx_queue_id
5845 * Tx queue identificatior.
5848 * Pointer to the burts mode information.
5851 * 0 as success, -EINVAL as failure.
5855 mlx5_tx_burst_mode_get(struct rte_eth_dev *dev,
5856 uint16_t tx_queue_id,
5857 struct rte_eth_burst_mode *mode)
5859 eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
5860 struct mlx5_priv *priv = dev->data->dev_private;
5861 struct mlx5_txq_data *txq = (*priv->txqs)[tx_queue_id];
5862 unsigned int i, olx;
5864 for (i = 0; i < RTE_DIM(txoff_func); i++) {
5865 if (pkt_burst == txoff_func[i].func) {
5866 olx = txoff_func[i].olx;
5867 snprintf(mode->info, sizeof(mode->info),
5868 "%s%s%s%s%s%s%s%s%s%s",
5869 (olx & MLX5_TXOFF_CONFIG_EMPW) ?
5870 ((olx & MLX5_TXOFF_CONFIG_MPW) ?
5871 "Legacy MPW" : "Enhanced MPW") : "No MPW",
5872 (olx & MLX5_TXOFF_CONFIG_MULTI) ?
5874 (olx & MLX5_TXOFF_CONFIG_TSO) ?
5876 (olx & MLX5_TXOFF_CONFIG_SWP) ?
5878 (olx & MLX5_TXOFF_CONFIG_CSUM) ?
5880 (olx & MLX5_TXOFF_CONFIG_INLINE) ?
5882 (olx & MLX5_TXOFF_CONFIG_VLAN) ?
5884 (olx & MLX5_TXOFF_CONFIG_METADATA) ?
5886 (olx & MLX5_TXOFF_CONFIG_TXPP) ?
5888 (txq && txq->fast_free) ?
5889 " + Fast Free" : "");