drivers/net/mlx5/mlx5_rxtx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <assert.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <stdlib.h>
  10
  11 /* Verbs header. */
  12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  13 #ifdef PEDANTIC
  14 #pragma GCC diagnostic ignored "-Wpedantic"
  15 #endif
  16 #include <infiniband/verbs.h>
  17 #include <infiniband/mlx5dv.h>
  18 #ifdef PEDANTIC
  19 #pragma GCC diagnostic error "-Wpedantic"
  20 #endif
  21
  22 #include <rte_mbuf.h>
  23 #include <rte_mempool.h>
  24 #include <rte_prefetch.h>
  25 #include <rte_common.h>
  26 #include <rte_branch_prediction.h>
  27 #include <rte_ether.h>
  28
  29 #include "mlx5.h"
  30 #include "mlx5_utils.h"
  31 #include "mlx5_rxtx.h"
  32 #include "mlx5_autoconf.h"
  33 #include "mlx5_defs.h"
  34 #include "mlx5_prm.h"
  35
  36 static __rte_always_inline uint32_t
  37 rxq_cq_to_pkt_type(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe);
  38
  39 static __rte_always_inline int
  40 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
  41                  uint16_t cqe_cnt, volatile struct mlx5_mini_cqe8 **mcqe);
  42
  43 static __rte_always_inline uint32_t
  44 rxq_cq_to_ol_flags(volatile struct mlx5_cqe *cqe);
  45
  46 static __rte_always_inline void
  47 rxq_cq_to_mbuf(struct mlx5_rxq_data *rxq, struct rte_mbuf *pkt,
  48                volatile struct mlx5_cqe *cqe, uint32_t rss_hash_res);
  49
  50 static __rte_always_inline void
  51 mprq_buf_replace(struct mlx5_rxq_data *rxq, uint16_t rq_idx);
  52
  53 uint32_t mlx5_ptype_table[] __rte_cache_aligned = {
  54         [0xff] = RTE_PTYPE_ALL_MASK, /* Last entry for errored packet. */
  55 };
  56
  57 uint8_t mlx5_cksum_table[1 << 10] __rte_cache_aligned;
  58 uint8_t mlx5_swp_types_table[1 << 10] __rte_cache_aligned;
  59
  60 /**
  61  * Build a table to translate Rx completion flags to packet type.
  62  *
  63  * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
  64  */
  65 void
  66 mlx5_set_ptype_table(void)
  67 {
  68         unsigned int i;
  69         uint32_t (*p)[RTE_DIM(mlx5_ptype_table)] = &mlx5_ptype_table;
  70
  71         /* Last entry must not be overwritten, reserved for errored packet. */
  72         for (i = 0; i < RTE_DIM(mlx5_ptype_table) - 1; ++i)
  73                 (*p)[i] = RTE_PTYPE_UNKNOWN;
  74         /*
  75          * The index to the array should have:
  76          * bit[1:0] = l3_hdr_type
  77          * bit[4:2] = l4_hdr_type
  78          * bit[5] = ip_frag
  79          * bit[6] = tunneled
  80          * bit[7] = outer_l3_type
  81          */
  82         /* L2 */
  83         (*p)[0x00] = RTE_PTYPE_L2_ETHER;
  84         /* L3 */
  85         (*p)[0x01] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
  86                      RTE_PTYPE_L4_NONFRAG;
  87         (*p)[0x02] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
  88                      RTE_PTYPE_L4_NONFRAG;
  89         /* Fragmented */
  90         (*p)[0x21] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
  91                      RTE_PTYPE_L4_FRAG;
  92         (*p)[0x22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
  93                      RTE_PTYPE_L4_FRAG;
  94         /* TCP */
  95         (*p)[0x05] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
  96                      RTE_PTYPE_L4_TCP;
  97         (*p)[0x06] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
  98                      RTE_PTYPE_L4_TCP;
  99         (*p)[0x0d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 100                      RTE_PTYPE_L4_TCP;
 101         (*p)[0x0e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 102                      RTE_PTYPE_L4_TCP;
 103         (*p)[0x11] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 104                      RTE_PTYPE_L4_TCP;
 105         (*p)[0x12] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 106                      RTE_PTYPE_L4_TCP;
 107         /* UDP */
 108         (*p)[0x09] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 109                      RTE_PTYPE_L4_UDP;
 110         (*p)[0x0a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 111                      RTE_PTYPE_L4_UDP;
 112         /* Repeat with outer_l3_type being set. Just in case. */
 113         (*p)[0x81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 114                      RTE_PTYPE_L4_NONFRAG;
 115         (*p)[0x82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 116                      RTE_PTYPE_L4_NONFRAG;
 117         (*p)[0xa1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 118                      RTE_PTYPE_L4_FRAG;
 119         (*p)[0xa2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 120                      RTE_PTYPE_L4_FRAG;
 121         (*p)[0x85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 122                      RTE_PTYPE_L4_TCP;
 123         (*p)[0x86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 124                      RTE_PTYPE_L4_TCP;
 125         (*p)[0x8d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 126                      RTE_PTYPE_L4_TCP;
 127         (*p)[0x8e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 128                      RTE_PTYPE_L4_TCP;
 129         (*p)[0x91] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 130                      RTE_PTYPE_L4_TCP;
 131         (*p)[0x92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 132                      RTE_PTYPE_L4_TCP;
 133         (*p)[0x89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 134                      RTE_PTYPE_L4_UDP;
 135         (*p)[0x8a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 136                      RTE_PTYPE_L4_UDP;
 137         /* Tunneled - L3 */
 138         (*p)[0x40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
 139         (*p)[0x41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 140                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 141                      RTE_PTYPE_INNER_L4_NONFRAG;
 142         (*p)[0x42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 143                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 144                      RTE_PTYPE_INNER_L4_NONFRAG;
 145         (*p)[0xc0] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
 146         (*p)[0xc1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 147                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 148                      RTE_PTYPE_INNER_L4_NONFRAG;
 149         (*p)[0xc2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 150                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 151                      RTE_PTYPE_INNER_L4_NONFRAG;
 152         /* Tunneled - Fragmented */
 153         (*p)[0x61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 154                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 155                      RTE_PTYPE_INNER_L4_FRAG;
 156         (*p)[0x62] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 157                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 158                      RTE_PTYPE_INNER_L4_FRAG;
 159         (*p)[0xe1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 160                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 161                      RTE_PTYPE_INNER_L4_FRAG;
 162         (*p)[0xe2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 163                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 164                      RTE_PTYPE_INNER_L4_FRAG;
 165         /* Tunneled - TCP */
 166         (*p)[0x45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 167                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 168                      RTE_PTYPE_INNER_L4_TCP;
 169         (*p)[0x46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 170                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 171                      RTE_PTYPE_INNER_L4_TCP;
 172         (*p)[0x4d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 173                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 174                      RTE_PTYPE_INNER_L4_TCP;
 175         (*p)[0x4e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 176                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 177                      RTE_PTYPE_INNER_L4_TCP;
 178         (*p)[0x51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 179                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 180                      RTE_PTYPE_INNER_L4_TCP;
 181         (*p)[0x52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 182                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 183                      RTE_PTYPE_INNER_L4_TCP;
 184         (*p)[0xc5] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 185                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 186                      RTE_PTYPE_INNER_L4_TCP;
 187         (*p)[0xc6] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 188                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 189                      RTE_PTYPE_INNER_L4_TCP;
 190         (*p)[0xcd] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 191                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 192                      RTE_PTYPE_INNER_L4_TCP;
 193         (*p)[0xce] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 194                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 195                      RTE_PTYPE_INNER_L4_TCP;
 196         (*p)[0xd1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 197                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 198                      RTE_PTYPE_INNER_L4_TCP;
 199         (*p)[0xd2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 200                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 201                      RTE_PTYPE_INNER_L4_TCP;
 202         /* Tunneled - UDP */
 203         (*p)[0x49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 204                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 205                      RTE_PTYPE_INNER_L4_UDP;
 206         (*p)[0x4a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 207                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 208                      RTE_PTYPE_INNER_L4_UDP;
 209         (*p)[0xc9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 210                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 211                      RTE_PTYPE_INNER_L4_UDP;
 212         (*p)[0xca] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 213                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 214                      RTE_PTYPE_INNER_L4_UDP;
 215 }
 216
 217 /**
 218  * Build a table to translate packet to checksum type of Verbs.
 219  */
 220 void
 221 mlx5_set_cksum_table(void)
 222 {
 223         unsigned int i;
 224         uint8_t v;
 225
 226         /*
 227          * The index should have:
 228          * bit[0] = PKT_TX_TCP_SEG
 229          * bit[2:3] = PKT_TX_UDP_CKSUM, PKT_TX_TCP_CKSUM
 230          * bit[4] = PKT_TX_IP_CKSUM
 231          * bit[8] = PKT_TX_OUTER_IP_CKSUM
 232          * bit[9] = tunnel
 233          */
 234         for (i = 0; i < RTE_DIM(mlx5_cksum_table); ++i) {
 235                 v = 0;
 236                 if (i & (1 << 9)) {
 237                         /* Tunneled packet. */
 238                         if (i & (1 << 8)) /* Outer IP. */
 239                                 v |= MLX5_ETH_WQE_L3_CSUM;
 240                         if (i & (1 << 4)) /* Inner IP. */
 241                                 v |= MLX5_ETH_WQE_L3_INNER_CSUM;
 242                         if (i & (3 << 2 | 1 << 0)) /* L4 or TSO. */
 243                                 v |= MLX5_ETH_WQE_L4_INNER_CSUM;
 244                 } else {
 245                         /* No tunnel. */
 246                         if (i & (1 << 4)) /* IP. */
 247                                 v |= MLX5_ETH_WQE_L3_CSUM;
 248                         if (i & (3 << 2 | 1 << 0)) /* L4 or TSO. */
 249                                 v |= MLX5_ETH_WQE_L4_CSUM;
 250                 }
 251                 mlx5_cksum_table[i] = v;
 252         }
 253 }
 254
 255 /**
 256  * Build a table to translate packet type of mbuf to SWP type of Verbs.
 257  */
 258 void
 259 mlx5_set_swp_types_table(void)
 260 {
 261         unsigned int i;
 262         uint8_t v;
 263
 264         /*
 265          * The index should have:
 266          * bit[0:1] = PKT_TX_L4_MASK
 267          * bit[4] = PKT_TX_IPV6
 268          * bit[8] = PKT_TX_OUTER_IPV6
 269          * bit[9] = PKT_TX_OUTER_UDP
 270          */
 271         for (i = 0; i < RTE_DIM(mlx5_swp_types_table); ++i) {
 272                 v = 0;
 273                 if (i & (1 << 8))
 274                         v |= MLX5_ETH_WQE_L3_OUTER_IPV6;
 275                 if (i & (1 << 9))
 276                         v |= MLX5_ETH_WQE_L4_OUTER_UDP;
 277                 if (i & (1 << 4))
 278                         v |= MLX5_ETH_WQE_L3_INNER_IPV6;
 279                 if ((i & 3) == (PKT_TX_UDP_CKSUM >> 52))
 280                         v |= MLX5_ETH_WQE_L4_INNER_UDP;
 281                 mlx5_swp_types_table[i] = v;
 282         }
 283 }
 284
 285 /**
 286  * Return the size of tailroom of WQ.
 287  *
 288  * @param txq
 289  *   Pointer to TX queue structure.
 290  * @param addr
 291  *   Pointer to tail of WQ.
 292  *
 293  * @return
 294  *   Size of tailroom.
 295  */
 296 static inline size_t
 297 tx_mlx5_wq_tailroom(struct mlx5_txq_data *txq, void *addr)
 298 {
 299         size_t tailroom;
 300         tailroom = (uintptr_t)(txq->wqes) +
 301                    (1 << txq->wqe_n) * MLX5_WQE_SIZE -
 302                    (uintptr_t)addr;
 303         return tailroom;
 304 }
 305
 306 /**
 307  * Copy data to tailroom of circular queue.
 308  *
 309  * @param dst
 310  *   Pointer to destination.
 311  * @param src
 312  *   Pointer to source.
 313  * @param n
 314  *   Number of bytes to copy.
 315  * @param base
 316  *   Pointer to head of queue.
 317  * @param tailroom
 318  *   Size of tailroom from dst.
 319  *
 320  * @return
 321  *   Pointer after copied data.
 322  */
 323 static inline void *
 324 mlx5_copy_to_wq(void *dst, const void *src, size_t n,
 325                 void *base, size_t tailroom)
 326 {
 327         void *ret;
 328
 329         if (n > tailroom) {
 330                 rte_memcpy(dst, src, tailroom);
 331                 rte_memcpy(base, (void *)((uintptr_t)src + tailroom),
 332                            n - tailroom);
 333                 ret = (uint8_t *)base + n - tailroom;
 334         } else {
 335                 rte_memcpy(dst, src, n);
 336                 ret = (n == tailroom) ? base : (uint8_t *)dst + n;
 337         }
 338         return ret;
 339 }
 340
 341 /**
 342  * Inline TSO headers into WQE.
 343  *
 344  * @return
 345  *   0 on success, negative errno value on failure.
 346  */
 347 static int
 348 inline_tso(struct mlx5_txq_data *txq, struct rte_mbuf *buf,
 349            uint32_t *length,
 350            uintptr_t *addr,
 351            uint16_t *pkt_inline_sz,
 352            uint8_t **raw,
 353            uint16_t *max_wqe,
 354            uint16_t *tso_segsz,
 355            uint16_t *tso_header_sz)
 356 {
 357         uintptr_t end = (uintptr_t)(((uintptr_t)txq->wqes) +
 358                                     (1 << txq->wqe_n) * MLX5_WQE_SIZE);
 359         unsigned int copy_b;
 360         uint8_t vlan_sz = (buf->ol_flags & PKT_TX_VLAN_PKT) ? 4 : 0;
 361         const uint8_t tunneled = txq->tunnel_en && (buf->ol_flags &
 362                                  PKT_TX_TUNNEL_MASK);
 363         uint16_t n_wqe;
 364
 365         *tso_segsz = buf->tso_segsz;
 366         *tso_header_sz = buf->l2_len + vlan_sz + buf->l3_len + buf->l4_len;
 367         if (unlikely(*tso_segsz == 0 || *tso_header_sz == 0)) {
 368                 txq->stats.oerrors++;
 369                 return -EINVAL;
 370         }
 371         if (tunneled)
 372                 *tso_header_sz += buf->outer_l2_len + buf->outer_l3_len;
 373         /* First seg must contain all TSO headers. */
 374         if (unlikely(*tso_header_sz > MLX5_MAX_TSO_HEADER) ||
 375                      *tso_header_sz > DATA_LEN(buf)) {
 376                 txq->stats.oerrors++;
 377                 return -EINVAL;
 378         }
 379         copy_b = *tso_header_sz - *pkt_inline_sz;
 380         if (!copy_b || ((end - (uintptr_t)*raw) < copy_b))
 381                 return -EAGAIN;
 382         n_wqe = (MLX5_WQE_DS(copy_b) - 1 + 3) / 4;
 383         if (unlikely(*max_wqe < n_wqe))
 384                 return -EINVAL;
 385         *max_wqe -= n_wqe;
 386         rte_memcpy((void *)*raw, (void *)*addr, copy_b);
 387         *length -= copy_b;
 388         *addr += copy_b;
 389         copy_b = MLX5_WQE_DS(copy_b) * MLX5_WQE_DWORD_SIZE;
 390         *pkt_inline_sz += copy_b;
 391         *raw += copy_b;
 392         return 0;
 393 }
 394
 395 /**
 396  * DPDK callback to check the status of a tx descriptor.
 397  *
 398  * @param tx_queue
 399  *   The tx queue.
 400  * @param[in] offset
 401  *   The index of the descriptor in the ring.
 402  *
 403  * @return
 404  *   The status of the tx descriptor.
 405  */
 406 int
 407 mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset)
 408 {
 409         struct mlx5_txq_data *txq = tx_queue;
 410         uint16_t used;
 411
 412         mlx5_tx_complete(txq);
 413         used = txq->elts_head - txq->elts_tail;
 414         if (offset < used)
 415                 return RTE_ETH_TX_DESC_FULL;
 416         return RTE_ETH_TX_DESC_DONE;
 417 }
 418
 419 /**
 420  * Internal function to compute the number of used descriptors in an RX queue
 421  *
 422  * @param rxq
 423  *   The Rx queue.
 424  *
 425  * @return
 426  *   The number of used rx descriptor.
 427  */
 428 static uint32_t
 429 rx_queue_count(struct mlx5_rxq_data *rxq)
 430 {
 431         struct rxq_zip *zip = &rxq->zip;
 432         volatile struct mlx5_cqe *cqe;
 433         const unsigned int cqe_n = (1 << rxq->cqe_n);
 434         const unsigned int cqe_cnt = cqe_n - 1;
 435         unsigned int cq_ci;
 436         unsigned int used;
 437
 438         /* if we are processing a compressed cqe */
 439         if (zip->ai) {
 440                 used = zip->cqe_cnt - zip->ca;
 441                 cq_ci = zip->cq_ci;
 442         } else {
 443                 used = 0;
 444                 cq_ci = rxq->cq_ci;
 445         }
 446         cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
 447         while (check_cqe(cqe, cqe_n, cq_ci) == 0) {
 448                 int8_t op_own;
 449                 unsigned int n;
 450
 451                 op_own = cqe->op_own;
 452                 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED)
 453                         n = rte_be_to_cpu_32(cqe->byte_cnt);
 454                 else
 455                         n = 1;
 456                 cq_ci += n;
 457                 used += n;
 458                 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
 459         }
 460         used = RTE_MIN(used, (1U << rxq->elts_n) - 1);
 461         return used;
 462 }
 463
 464 /**
 465  * DPDK callback to check the status of a rx descriptor.
 466  *
 467  * @param rx_queue
 468  *   The Rx queue.
 469  * @param[in] offset
 470  *   The index of the descriptor in the ring.
 471  *
 472  * @return
 473  *   The status of the tx descriptor.
 474  */
 475 int
 476 mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset)
 477 {
 478         struct mlx5_rxq_data *rxq = rx_queue;
 479         struct mlx5_rxq_ctrl *rxq_ctrl =
 480                         container_of(rxq, struct mlx5_rxq_ctrl, rxq);
 481         struct rte_eth_dev *dev = ETH_DEV(rxq_ctrl->priv);
 482
 483         if (dev->rx_pkt_burst != mlx5_rx_burst) {
 484                 rte_errno = ENOTSUP;
 485                 return -rte_errno;
 486         }
 487         if (offset >= (1 << rxq->elts_n)) {
 488                 rte_errno = EINVAL;
 489                 return -rte_errno;
 490         }
 491         if (offset < rx_queue_count(rxq))
 492                 return RTE_ETH_RX_DESC_DONE;
 493         return RTE_ETH_RX_DESC_AVAIL;
 494 }
 495
 496 /**
 497  * DPDK callback to get the number of used descriptors in a RX queue
 498  *
 499  * @param dev
 500  *   Pointer to the device structure.
 501  *
 502  * @param rx_queue_id
 503  *   The Rx queue.
 504  *
 505  * @return
 506  *   The number of used rx descriptor.
 507  *   -EINVAL if the queue is invalid
 508  */
 509 uint32_t
 510 mlx5_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 511 {
 512         struct mlx5_priv *priv = dev->data->dev_private;
 513         struct mlx5_rxq_data *rxq;
 514
 515         if (dev->rx_pkt_burst != mlx5_rx_burst) {
 516                 rte_errno = ENOTSUP;
 517                 return -rte_errno;
 518         }
 519         rxq = (*priv->rxqs)[rx_queue_id];
 520         if (!rxq) {
 521                 rte_errno = EINVAL;
 522                 return -rte_errno;
 523         }
 524         return rx_queue_count(rxq);
 525 }
 526
 527 #define MLX5_SYSTEM_LOG_DIR "/var/log"
 528 /**
 529  * Dump debug information to log file.
 530  *
 531  * @param fname
 532  *   The file name.
 533  * @param hex_title
 534  *   If not NULL this string is printed as a header to the output
 535  *   and the output will be in hexadecimal view.
 536  * @param buf
 537  *   This is the buffer address to print out.
 538  * @param len
 539  *   The number of bytes to dump out.
 540  */
 541 void
 542 mlx5_dump_debug_information(const char *fname, const char *hex_title,
 543                             const void *buf, unsigned int hex_len)
 544 {
 545         FILE *fd;
 546
 547         MKSTR(path, "%s/%s", MLX5_SYSTEM_LOG_DIR, fname);
 548         fd = fopen(path, "a+");
 549         if (!fd) {
 550                 DRV_LOG(WARNING, "cannot open %s for debug dump\n",
 551                         path);
 552                 MKSTR(path2, "./%s", fname);
 553                 fd = fopen(path2, "a+");
 554                 if (!fd) {
 555                         DRV_LOG(ERR, "cannot open %s for debug dump\n",
 556                                 path2);
 557                         return;
 558                 }
 559                 DRV_LOG(INFO, "New debug dump in file %s\n", path2);
 560         } else {
 561                 DRV_LOG(INFO, "New debug dump in file %s\n", path);
 562         }
 563         if (hex_title)
 564                 rte_hexdump(fd, hex_title, buf, hex_len);
 565         else
 566                 fprintf(fd, "%s", (const char *)buf);
 567         fprintf(fd, "\n\n\n");
 568         fclose(fd);
 569 }
 570
 571 /**
 572  * DPDK callback for TX.
 573  *
 574  * @param dpdk_txq
 575  *   Generic pointer to TX queue structure.
 576  * @param[in] pkts
 577  *   Packets to transmit.
 578  * @param pkts_n
 579  *   Number of packets in array.
 580  *
 581  * @return
 582  *   Number of packets successfully transmitted (<= pkts_n).
 583  */
 584 uint16_t
 585 mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
 586 {
 587         struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
 588         uint16_t elts_head = txq->elts_head;
 589         const uint16_t elts_n = 1 << txq->elts_n;
 590         const uint16_t elts_m = elts_n - 1;
 591         unsigned int i = 0;
 592         unsigned int j = 0;
 593         unsigned int k = 0;
 594         uint16_t max_elts;
 595         uint16_t max_wqe;
 596         unsigned int comp;
 597         volatile struct mlx5_wqe_ctrl *last_wqe = NULL;
 598         unsigned int segs_n = 0;
 599         const unsigned int max_inline = txq->max_inline;
 600         uint64_t addr_64;
 601
 602         if (unlikely(!pkts_n))
 603                 return 0;
 604         /* Prefetch first packet cacheline. */
 605         rte_prefetch0(*pkts);
 606         /* Start processing. */
 607         mlx5_tx_complete(txq);
 608         max_elts = (elts_n - (elts_head - txq->elts_tail));
 609         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
 610         if (unlikely(!max_wqe))
 611                 return 0;
 612         do {
 613                 struct rte_mbuf *buf = *pkts; /* First_seg. */
 614                 uint8_t *raw;
 615                 volatile struct mlx5_wqe_v *wqe = NULL;
 616                 volatile rte_v128u32_t *dseg = NULL;
 617                 uint32_t length;
 618                 unsigned int ds = 0;
 619                 unsigned int sg = 0; /* counter of additional segs attached. */
 620                 uintptr_t addr;
 621                 uint16_t pkt_inline_sz = MLX5_WQE_DWORD_SIZE + 2;
 622                 uint16_t tso_header_sz = 0;
 623                 uint16_t ehdr;
 624                 uint8_t cs_flags;
 625                 uint8_t tso = txq->tso_en && (buf->ol_flags & PKT_TX_TCP_SEG);
 626                 uint32_t swp_offsets = 0;
 627                 uint8_t swp_types = 0;
 628                 rte_be32_t metadata;
 629                 uint16_t tso_segsz = 0;
 630 #ifdef MLX5_PMD_SOFT_COUNTERS
 631                 uint32_t total_length = 0;
 632 #endif
 633                 int ret;
 634
 635                 segs_n = buf->nb_segs;
 636                 /*
 637                  * Make sure there is enough room to store this packet and
 638                  * that one ring entry remains unused.
 639                  */
 640                 assert(segs_n);
 641                 if (max_elts < segs_n)
 642                         break;
 643                 max_elts -= segs_n;
 644                 sg = --segs_n;
 645                 if (unlikely(--max_wqe == 0))
 646                         break;
 647                 wqe = (volatile struct mlx5_wqe_v *)
 648                         tx_mlx5_wqe(txq, txq->wqe_ci);
 649                 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 650                 if (pkts_n - i > 1)
 651                         rte_prefetch0(*(pkts + 1));
 652                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
 653                 length = DATA_LEN(buf);
 654                 ehdr = (((uint8_t *)addr)[1] << 8) |
 655                        ((uint8_t *)addr)[0];
 656 #ifdef MLX5_PMD_SOFT_COUNTERS
 657                 total_length = length;
 658 #endif
 659                 if (length < (MLX5_WQE_DWORD_SIZE + 2)) {
 660                         txq->stats.oerrors++;
 661                         break;
 662                 }
 663                 /* Update element. */
 664                 (*txq->elts)[elts_head & elts_m] = buf;
 665                 /* Prefetch next buffer data. */
 666                 if (pkts_n - i > 1)
 667                         rte_prefetch0(
 668                             rte_pktmbuf_mtod(*(pkts + 1), volatile void *));
 669                 cs_flags = txq_ol_cksum_to_cs(buf);
 670                 txq_mbuf_to_swp(txq, buf, (uint8_t *)&swp_offsets, &swp_types);
 671                 raw = ((uint8_t *)(uintptr_t)wqe) + 2 * MLX5_WQE_DWORD_SIZE;
 672                 /* Copy metadata from mbuf if valid */
 673                 metadata = buf->ol_flags & PKT_TX_METADATA ? buf->tx_metadata :
 674                                                              0;
 675                 /* Replace the Ethernet type by the VLAN if necessary. */
 676                 if (buf->ol_flags & PKT_TX_VLAN_PKT) {
 677                         uint32_t vlan = rte_cpu_to_be_32(0x81000000 |
 678                                                          buf->vlan_tci);
 679                         unsigned int len = 2 * RTE_ETHER_ADDR_LEN - 2;
 680
 681                         addr += 2;
 682                         length -= 2;
 683                         /* Copy Destination and source mac address. */
 684                         memcpy((uint8_t *)raw, ((uint8_t *)addr), len);
 685                         /* Copy VLAN. */
 686                         memcpy((uint8_t *)raw + len, &vlan, sizeof(vlan));
 687                         /* Copy missing two bytes to end the DSeg. */
 688                         memcpy((uint8_t *)raw + len + sizeof(vlan),
 689                                ((uint8_t *)addr) + len, 2);
 690                         addr += len + 2;
 691                         length -= (len + 2);
 692                 } else {
 693                         memcpy((uint8_t *)raw, ((uint8_t *)addr) + 2,
 694                                MLX5_WQE_DWORD_SIZE);
 695                         length -= pkt_inline_sz;
 696                         addr += pkt_inline_sz;
 697                 }
 698                 raw += MLX5_WQE_DWORD_SIZE;
 699                 if (tso) {
 700                         ret = inline_tso(txq, buf, &length,
 701                                          &addr, &pkt_inline_sz,
 702                                          &raw, &max_wqe,
 703                                          &tso_segsz, &tso_header_sz);
 704                         if (ret == -EINVAL) {
 705                                 break;
 706                         } else if (ret == -EAGAIN) {
 707                                 /* NOP WQE. */
 708                                 wqe->ctrl = (rte_v128u32_t){
 709                                         rte_cpu_to_be_32(txq->wqe_ci << 8),
 710                                         rte_cpu_to_be_32(txq->qp_num_8s | 1),
 711                                         0,
 712                                         0,
 713                                 };
 714                                 ds = 1;
 715 #ifdef MLX5_PMD_SOFT_COUNTERS
 716                                 total_length = 0;
 717 #endif
 718                                 k++;
 719                                 goto next_wqe;
 720                         }
 721                 }
 722                 /* Inline if enough room. */
 723                 if (max_inline || tso) {
 724                         uint32_t inl = 0;
 725                         uintptr_t end = (uintptr_t)
 726                                 (((uintptr_t)txq->wqes) +
 727                                  (1 << txq->wqe_n) * MLX5_WQE_SIZE);
 728                         unsigned int inline_room = max_inline *
 729                                                    RTE_CACHE_LINE_SIZE -
 730                                                    (pkt_inline_sz - 2) -
 731                                                    !!tso * sizeof(inl);
 732                         uintptr_t addr_end;
 733                         unsigned int copy_b;
 734
 735 pkt_inline:
 736                         addr_end = RTE_ALIGN_FLOOR(addr + inline_room,
 737                                                    RTE_CACHE_LINE_SIZE);
 738                         copy_b = (addr_end > addr) ?
 739                                  RTE_MIN((addr_end - addr), length) : 0;
 740                         if (copy_b && ((end - (uintptr_t)raw) >
 741                                        (copy_b + sizeof(inl)))) {
 742                                 /*
 743                                  * One Dseg remains in the current WQE.  To
 744                                  * keep the computation positive, it is
 745                                  * removed after the bytes to Dseg conversion.
 746                                  */
 747                                 uint16_t n = (MLX5_WQE_DS(copy_b) - 1 + 3) / 4;
 748
 749                                 if (unlikely(max_wqe < n))
 750                                         break;
 751                                 max_wqe -= n;
 752                                 if (tso) {
 753                                         assert(inl == 0);
 754                                         inl = rte_cpu_to_be_32(copy_b |
 755                                                                MLX5_INLINE_SEG);
 756                                         rte_memcpy((void *)raw,
 757                                                    (void *)&inl, sizeof(inl));
 758                                         raw += sizeof(inl);
 759                                         pkt_inline_sz += sizeof(inl);
 760                                 }
 761                                 rte_memcpy((void *)raw, (void *)addr, copy_b);
 762                                 addr += copy_b;
 763                                 length -= copy_b;
 764                                 pkt_inline_sz += copy_b;
 765                         }
 766                         /*
 767                          * 2 DWORDs consumed by the WQE header + ETH segment +
 768                          * the size of the inline part of the packet.
 769                          */
 770                         ds = 2 + MLX5_WQE_DS(pkt_inline_sz - 2);
 771                         if (length > 0) {
 772                                 if (ds % (MLX5_WQE_SIZE /
 773                                           MLX5_WQE_DWORD_SIZE) == 0) {
 774                                         if (unlikely(--max_wqe == 0))
 775                                                 break;
 776                                         dseg = (volatile rte_v128u32_t *)
 777                                                tx_mlx5_wqe(txq, txq->wqe_ci +
 778                                                            ds / 4);
 779                                 } else {
 780                                         dseg = (volatile rte_v128u32_t *)
 781                                                 ((uintptr_t)wqe +
 782                                                  (ds * MLX5_WQE_DWORD_SIZE));
 783                                 }
 784                                 goto use_dseg;
 785                         } else if (!segs_n) {
 786                                 goto next_pkt;
 787                         } else {
 788                                 /*
 789                                  * Further inline the next segment only for
 790                                  * non-TSO packets.
 791                                  */
 792                                 if (!tso) {
 793                                         raw += copy_b;
 794                                         inline_room -= copy_b;
 795                                 } else {
 796                                         inline_room = 0;
 797                                 }
 798                                 /* Move to the next segment. */
 799                                 --segs_n;
 800                                 buf = buf->next;
 801                                 assert(buf);
 802                                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
 803                                 length = DATA_LEN(buf);
 804 #ifdef MLX5_PMD_SOFT_COUNTERS
 805                                 total_length += length;
 806 #endif
 807                                 (*txq->elts)[++elts_head & elts_m] = buf;
 808                                 goto pkt_inline;
 809                         }
 810                 } else {
 811                         /*
 812                          * No inline has been done in the packet, only the
 813                          * Ethernet Header as been stored.
 814                          */
 815                         dseg = (volatile rte_v128u32_t *)
 816                                 ((uintptr_t)wqe + (3 * MLX5_WQE_DWORD_SIZE));
 817                         ds = 3;
 818 use_dseg:
 819                         /* Add the remaining packet as a simple ds. */
 820                         addr_64 = rte_cpu_to_be_64(addr);
 821                         *dseg = (rte_v128u32_t){
 822                                 rte_cpu_to_be_32(length),
 823                                 mlx5_tx_mb2mr(txq, buf),
 824                                 addr_64,
 825                                 addr_64 >> 32,
 826                         };
 827                         ++ds;
 828                         if (!segs_n)
 829                                 goto next_pkt;
 830                 }
 831 next_seg:
 832                 assert(buf);
 833                 assert(ds);
 834                 assert(wqe);
 835                 /*
 836                  * Spill on next WQE when the current one does not have
 837                  * enough room left. Size of WQE must a be a multiple
 838                  * of data segment size.
 839                  */
 840                 assert(!(MLX5_WQE_SIZE % MLX5_WQE_DWORD_SIZE));
 841                 if (!(ds % (MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE))) {
 842                         if (unlikely(--max_wqe == 0))
 843                                 break;
 844                         dseg = (volatile rte_v128u32_t *)
 845                                tx_mlx5_wqe(txq, txq->wqe_ci + ds / 4);
 846                         rte_prefetch0(tx_mlx5_wqe(txq,
 847                                                   txq->wqe_ci + ds / 4 + 1));
 848                 } else {
 849                         ++dseg;
 850                 }
 851                 ++ds;
 852                 buf = buf->next;
 853                 assert(buf);
 854                 length = DATA_LEN(buf);
 855 #ifdef MLX5_PMD_SOFT_COUNTERS
 856                 total_length += length;
 857 #endif
 858                 /* Store segment information. */
 859                 addr_64 = rte_cpu_to_be_64(rte_pktmbuf_mtod(buf, uintptr_t));
 860                 *dseg = (rte_v128u32_t){
 861                         rte_cpu_to_be_32(length),
 862                         mlx5_tx_mb2mr(txq, buf),
 863                         addr_64,
 864                         addr_64 >> 32,
 865                 };
 866                 (*txq->elts)[++elts_head & elts_m] = buf;
 867                 if (--segs_n)
 868                         goto next_seg;
 869 next_pkt:
 870                 if (ds > MLX5_DSEG_MAX) {
 871                         txq->stats.oerrors++;
 872                         break;
 873                 }
 874                 ++elts_head;
 875                 ++pkts;
 876                 ++i;
 877                 j += sg;
 878                 /* Initialize known and common part of the WQE structure. */
 879                 if (tso) {
 880                         wqe->ctrl = (rte_v128u32_t){
 881                                 rte_cpu_to_be_32((txq->wqe_ci << 8) |
 882                                                  MLX5_OPCODE_TSO),
 883                                 rte_cpu_to_be_32(txq->qp_num_8s | ds),
 884                                 0,
 885                                 0,
 886                         };
 887                         wqe->eseg = (rte_v128u32_t){
 888                                 swp_offsets,
 889                                 cs_flags | (swp_types << 8) |
 890                                 (rte_cpu_to_be_16(tso_segsz) << 16),
 891                                 metadata,
 892                                 (ehdr << 16) | rte_cpu_to_be_16(tso_header_sz),
 893                         };
 894                 } else {
 895                         wqe->ctrl = (rte_v128u32_t){
 896                                 rte_cpu_to_be_32((txq->wqe_ci << 8) |
 897                                                  MLX5_OPCODE_SEND),
 898                                 rte_cpu_to_be_32(txq->qp_num_8s | ds),
 899                                 0,
 900                                 0,
 901                         };
 902                         wqe->eseg = (rte_v128u32_t){
 903                                 swp_offsets,
 904                                 cs_flags | (swp_types << 8),
 905                                 metadata,
 906                                 (ehdr << 16) | rte_cpu_to_be_16(pkt_inline_sz),
 907                         };
 908                 }
 909 next_wqe:
 910                 txq->wqe_ci += (ds + 3) / 4;
 911                 /* Save the last successful WQE for completion request */
 912                 last_wqe = (volatile struct mlx5_wqe_ctrl *)wqe;
 913 #ifdef MLX5_PMD_SOFT_COUNTERS
 914                 /* Increment sent bytes counter. */
 915                 txq->stats.obytes += total_length;
 916 #endif
 917         } while (i < pkts_n);
 918         /* Take a shortcut if nothing must be sent. */
 919         if (unlikely((i + k) == 0))
 920                 return 0;
 921         txq->elts_head += (i + j);
 922         /* Check whether completion threshold has been reached. */
 923         comp = txq->elts_comp + i + j + k;
 924         if (comp >= MLX5_TX_COMP_THRESH) {
 925                 /* A CQE slot must always be available. */
 926                 assert((1u << txq->cqe_n) - (txq->cq_pi++ - txq->cq_ci));
 927                 /* Request completion on last WQE. */
 928                 last_wqe->ctrl2 = rte_cpu_to_be_32(8);
 929                 /* Save elts_head in unused "immediate" field of WQE. */
 930                 last_wqe->ctrl3 = txq->elts_head;
 931                 txq->elts_comp = 0;
 932         } else {
 933                 txq->elts_comp = comp;
 934         }
 935 #ifdef MLX5_PMD_SOFT_COUNTERS
 936         /* Increment sent packets counter. */
 937         txq->stats.opackets += i;
 938 #endif
 939         /* Ring QP doorbell. */
 940         mlx5_tx_dbrec(txq, (volatile struct mlx5_wqe *)last_wqe);
 941         return i;
 942 }
 943
 944 /**
 945  * Open a MPW session.
 946  *
 947  * @param txq
 948  *   Pointer to TX queue structure.
 949  * @param mpw
 950  *   Pointer to MPW session structure.
 951  * @param length
 952  *   Packet length.
 953  */
 954 static inline void
 955 mlx5_mpw_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw, uint32_t length)
 956 {
 957         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
 958         volatile struct mlx5_wqe_data_seg (*dseg)[MLX5_MPW_DSEG_MAX] =
 959                 (volatile struct mlx5_wqe_data_seg (*)[])
 960                 tx_mlx5_wqe(txq, idx + 1);
 961
 962         mpw->state = MLX5_MPW_STATE_OPENED;
 963         mpw->pkts_n = 0;
 964         mpw->len = length;
 965         mpw->total_len = 0;
 966         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
 967         mpw->wqe->eseg.mss = rte_cpu_to_be_16(length);
 968         mpw->wqe->eseg.inline_hdr_sz = 0;
 969         mpw->wqe->eseg.rsvd0 = 0;
 970         mpw->wqe->eseg.rsvd1 = 0;
 971         mpw->wqe->eseg.flow_table_metadata = 0;
 972         mpw->wqe->ctrl[0] = rte_cpu_to_be_32((MLX5_OPC_MOD_MPW << 24) |
 973                                              (txq->wqe_ci << 8) |
 974                                              MLX5_OPCODE_TSO);
 975         mpw->wqe->ctrl[2] = 0;
 976         mpw->wqe->ctrl[3] = 0;
 977         mpw->data.dseg[0] = (volatile struct mlx5_wqe_data_seg *)
 978                 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
 979         mpw->data.dseg[1] = (volatile struct mlx5_wqe_data_seg *)
 980                 (((uintptr_t)mpw->wqe) + (3 * MLX5_WQE_DWORD_SIZE));
 981         mpw->data.dseg[2] = &(*dseg)[0];
 982         mpw->data.dseg[3] = &(*dseg)[1];
 983         mpw->data.dseg[4] = &(*dseg)[2];
 984 }
 985
 986 /**
 987  * Close a MPW session.
 988  *
 989  * @param txq
 990  *   Pointer to TX queue structure.
 991  * @param mpw
 992  *   Pointer to MPW session structure.
 993  */
 994 static inline void
 995 mlx5_mpw_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
 996 {
 997         unsigned int num = mpw->pkts_n;
 998
 999         /*
1000          * Store size in multiple of 16 bytes. Control and Ethernet segments
1001          * count as 2.
1002          */
1003         mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s | (2 + num));
1004         mpw->state = MLX5_MPW_STATE_CLOSED;
1005         if (num < 3)
1006                 ++txq->wqe_ci;
1007         else
1008                 txq->wqe_ci += 2;
1009         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
1010         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
1011 }
1012
1013 /**
1014  * DPDK callback for TX with MPW support.
1015  *
1016  * @param dpdk_txq
1017  *   Generic pointer to TX queue structure.
1018  * @param[in] pkts
1019  *   Packets to transmit.
1020  * @param pkts_n
1021  *   Number of packets in array.
1022  *
1023  * @return
1024  *   Number of packets successfully transmitted (<= pkts_n).
1025  */
1026 uint16_t
1027 mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1028 {
1029         struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
1030         uint16_t elts_head = txq->elts_head;
1031         const uint16_t elts_n = 1 << txq->elts_n;
1032         const uint16_t elts_m = elts_n - 1;
1033         unsigned int i = 0;
1034         unsigned int j = 0;
1035         uint16_t max_elts;
1036         uint16_t max_wqe;
1037         unsigned int comp;
1038         struct mlx5_mpw mpw = {
1039                 .state = MLX5_MPW_STATE_CLOSED,
1040         };
1041
1042         if (unlikely(!pkts_n))
1043                 return 0;
1044         /* Prefetch first packet cacheline. */
1045         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
1046         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
1047         /* Start processing. */
1048         mlx5_tx_complete(txq);
1049         max_elts = (elts_n - (elts_head - txq->elts_tail));
1050         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1051         if (unlikely(!max_wqe))
1052                 return 0;
1053         do {
1054                 struct rte_mbuf *buf = *(pkts++);
1055                 uint32_t length;
1056                 unsigned int segs_n = buf->nb_segs;
1057                 uint32_t cs_flags;
1058                 rte_be32_t metadata;
1059
1060                 /*
1061                  * Make sure there is enough room to store this packet and
1062                  * that one ring entry remains unused.
1063                  */
1064                 assert(segs_n);
1065                 if (max_elts < segs_n)
1066                         break;
1067                 /* Do not bother with large packets MPW cannot handle. */
1068                 if (segs_n > MLX5_MPW_DSEG_MAX) {
1069                         txq->stats.oerrors++;
1070                         break;
1071                 }
1072                 max_elts -= segs_n;
1073                 --pkts_n;
1074                 cs_flags = txq_ol_cksum_to_cs(buf);
1075                 /* Copy metadata from mbuf if valid */
1076                 metadata = buf->ol_flags & PKT_TX_METADATA ? buf->tx_metadata :
1077                                                              0;
1078                 /* Retrieve packet information. */
1079                 length = PKT_LEN(buf);
1080                 assert(length);
1081                 /* Start new session if packet differs. */
1082                 if ((mpw.state == MLX5_MPW_STATE_OPENED) &&
1083                     ((mpw.len != length) ||
1084                      (segs_n != 1) ||
1085                      (mpw.wqe->eseg.flow_table_metadata != metadata) ||
1086                      (mpw.wqe->eseg.cs_flags != cs_flags)))
1087                         mlx5_mpw_close(txq, &mpw);
1088                 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1089                         /*
1090                          * Multi-Packet WQE consumes at most two WQE.
1091                          * mlx5_mpw_new() expects to be able to use such
1092                          * resources.
1093                          */
1094                         if (unlikely(max_wqe < 2))
1095                                 break;
1096                         max_wqe -= 2;
1097                         mlx5_mpw_new(txq, &mpw, length);
1098                         mpw.wqe->eseg.cs_flags = cs_flags;
1099                         mpw.wqe->eseg.flow_table_metadata = metadata;
1100                 }
1101                 /* Multi-segment packets must be alone in their MPW. */
1102                 assert((segs_n == 1) || (mpw.pkts_n == 0));
1103 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1104                 length = 0;
1105 #endif
1106                 do {
1107                         volatile struct mlx5_wqe_data_seg *dseg;
1108                         uintptr_t addr;
1109
1110                         assert(buf);
1111                         (*txq->elts)[elts_head++ & elts_m] = buf;
1112                         dseg = mpw.data.dseg[mpw.pkts_n];
1113                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1114                         *dseg = (struct mlx5_wqe_data_seg){
1115                                 .byte_count = rte_cpu_to_be_32(DATA_LEN(buf)),
1116                                 .lkey = mlx5_tx_mb2mr(txq, buf),
1117                                 .addr = rte_cpu_to_be_64(addr),
1118                         };
1119 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1120                         length += DATA_LEN(buf);
1121 #endif
1122                         buf = buf->next;
1123                         ++mpw.pkts_n;
1124                         ++j;
1125                 } while (--segs_n);
1126                 assert(length == mpw.len);
1127                 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1128                         mlx5_mpw_close(txq, &mpw);
1129 #ifdef MLX5_PMD_SOFT_COUNTERS
1130                 /* Increment sent bytes counter. */
1131                 txq->stats.obytes += length;
1132 #endif
1133                 ++i;
1134         } while (pkts_n);
1135         /* Take a shortcut if nothing must be sent. */
1136         if (unlikely(i == 0))
1137                 return 0;
1138         /* Check whether completion threshold has been reached. */
1139         /* "j" includes both packets and segments. */
1140         comp = txq->elts_comp + j;
1141         if (comp >= MLX5_TX_COMP_THRESH) {
1142                 volatile struct mlx5_wqe *wqe = mpw.wqe;
1143
1144                 /* A CQE slot must always be available. */
1145                 assert((1u << txq->cqe_n) - (txq->cq_pi++ - txq->cq_ci));
1146                 /* Request completion on last WQE. */
1147                 wqe->ctrl[2] = rte_cpu_to_be_32(8);
1148                 /* Save elts_head in unused "immediate" field of WQE. */
1149                 wqe->ctrl[3] = elts_head;
1150                 txq->elts_comp = 0;
1151         } else {
1152                 txq->elts_comp = comp;
1153         }
1154 #ifdef MLX5_PMD_SOFT_COUNTERS
1155         /* Increment sent packets counter. */
1156         txq->stats.opackets += i;
1157 #endif
1158         /* Ring QP doorbell. */
1159         if (mpw.state == MLX5_MPW_STATE_OPENED)
1160                 mlx5_mpw_close(txq, &mpw);
1161         mlx5_tx_dbrec(txq, mpw.wqe);
1162         txq->elts_head = elts_head;
1163         return i;
1164 }
1165
1166 /**
1167  * Open a MPW inline session.
1168  *
1169  * @param txq
1170  *   Pointer to TX queue structure.
1171  * @param mpw
1172  *   Pointer to MPW session structure.
1173  * @param length
1174  *   Packet length.
1175  */
1176 static inline void
1177 mlx5_mpw_inline_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw,
1178                     uint32_t length)
1179 {
1180         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1181         struct mlx5_wqe_inl_small *inl;
1182
1183         mpw->state = MLX5_MPW_INL_STATE_OPENED;
1184         mpw->pkts_n = 0;
1185         mpw->len = length;
1186         mpw->total_len = 0;
1187         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1188         mpw->wqe->ctrl[0] = rte_cpu_to_be_32((MLX5_OPC_MOD_MPW << 24) |
1189                                              (txq->wqe_ci << 8) |
1190                                              MLX5_OPCODE_TSO);
1191         mpw->wqe->ctrl[2] = 0;
1192         mpw->wqe->ctrl[3] = 0;
1193         mpw->wqe->eseg.mss = rte_cpu_to_be_16(length);
1194         mpw->wqe->eseg.inline_hdr_sz = 0;
1195         mpw->wqe->eseg.cs_flags = 0;
1196         mpw->wqe->eseg.rsvd0 = 0;
1197         mpw->wqe->eseg.rsvd1 = 0;
1198         mpw->wqe->eseg.flow_table_metadata = 0;
1199         inl = (struct mlx5_wqe_inl_small *)
1200                 (((uintptr_t)mpw->wqe) + 2 * MLX5_WQE_DWORD_SIZE);
1201         mpw->data.raw = (uint8_t *)&inl->raw;
1202 }
1203
1204 /**
1205  * Close a MPW inline session.
1206  *
1207  * @param txq
1208  *   Pointer to TX queue structure.
1209  * @param mpw
1210  *   Pointer to MPW session structure.
1211  */
1212 static inline void
1213 mlx5_mpw_inline_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
1214 {
1215         unsigned int size;
1216         struct mlx5_wqe_inl_small *inl = (struct mlx5_wqe_inl_small *)
1217                 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
1218
1219         size = MLX5_WQE_SIZE - MLX5_MWQE64_INL_DATA + mpw->total_len;
1220         /*
1221          * Store size in multiple of 16 bytes. Control and Ethernet segments
1222          * count as 2.
1223          */
1224         mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s |
1225                                              MLX5_WQE_DS(size));
1226         mpw->state = MLX5_MPW_STATE_CLOSED;
1227         inl->byte_cnt = rte_cpu_to_be_32(mpw->total_len | MLX5_INLINE_SEG);
1228         txq->wqe_ci += (size + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1229 }
1230
1231 /**
1232  * DPDK callback for TX with MPW inline support.
1233  *
1234  * @param dpdk_txq
1235  *   Generic pointer to TX queue structure.
1236  * @param[in] pkts
1237  *   Packets to transmit.
1238  * @param pkts_n
1239  *   Number of packets in array.
1240  *
1241  * @return
1242  *   Number of packets successfully transmitted (<= pkts_n).
1243  */
1244 uint16_t
1245 mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
1246                          uint16_t pkts_n)
1247 {
1248         struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
1249         uint16_t elts_head = txq->elts_head;
1250         const uint16_t elts_n = 1 << txq->elts_n;
1251         const uint16_t elts_m = elts_n - 1;
1252         unsigned int i = 0;
1253         unsigned int j = 0;
1254         uint16_t max_elts;
1255         uint16_t max_wqe;
1256         unsigned int comp;
1257         unsigned int inline_room = txq->max_inline * RTE_CACHE_LINE_SIZE;
1258         struct mlx5_mpw mpw = {
1259                 .state = MLX5_MPW_STATE_CLOSED,
1260         };
1261         /*
1262          * Compute the maximum number of WQE which can be consumed by inline
1263          * code.
1264          * - 2 DSEG for:
1265          *   - 1 control segment,
1266          *   - 1 Ethernet segment,
1267          * - N Dseg from the inline request.
1268          */
1269         const unsigned int wqe_inl_n =
1270                 ((2 * MLX5_WQE_DWORD_SIZE +
1271                   txq->max_inline * RTE_CACHE_LINE_SIZE) +
1272                  RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE;
1273
1274         if (unlikely(!pkts_n))
1275                 return 0;
1276         /* Prefetch first packet cacheline. */
1277         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
1278         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
1279         /* Start processing. */
1280         mlx5_tx_complete(txq);
1281         max_elts = (elts_n - (elts_head - txq->elts_tail));
1282         do {
1283                 struct rte_mbuf *buf = *(pkts++);
1284                 uintptr_t addr;
1285                 uint32_t length;
1286                 unsigned int segs_n = buf->nb_segs;
1287                 uint8_t cs_flags;
1288                 rte_be32_t metadata;
1289
1290                 /*
1291                  * Make sure there is enough room to store this packet and
1292                  * that one ring entry remains unused.
1293                  */
1294                 assert(segs_n);
1295                 if (max_elts < segs_n)
1296                         break;
1297                 /* Do not bother with large packets MPW cannot handle. */
1298                 if (segs_n > MLX5_MPW_DSEG_MAX) {
1299                         txq->stats.oerrors++;
1300                         break;
1301                 }
1302                 max_elts -= segs_n;
1303                 --pkts_n;
1304                 /*
1305                  * Compute max_wqe in case less WQE were consumed in previous
1306                  * iteration.
1307                  */
1308                 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1309                 cs_flags = txq_ol_cksum_to_cs(buf);
1310                 /* Copy metadata from mbuf if valid */
1311                 metadata = buf->ol_flags & PKT_TX_METADATA ? buf->tx_metadata :
1312                                                              0;
1313                 /* Retrieve packet information. */
1314                 length = PKT_LEN(buf);
1315                 /* Start new session if packet differs. */
1316                 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1317                         if ((mpw.len != length) ||
1318                             (segs_n != 1) ||
1319                             (mpw.wqe->eseg.flow_table_metadata != metadata) ||
1320                             (mpw.wqe->eseg.cs_flags != cs_flags))
1321                                 mlx5_mpw_close(txq, &mpw);
1322                 } else if (mpw.state == MLX5_MPW_INL_STATE_OPENED) {
1323                         if ((mpw.len != length) ||
1324                             (segs_n != 1) ||
1325                             (length > inline_room) ||
1326                             (mpw.wqe->eseg.flow_table_metadata != metadata) ||
1327                             (mpw.wqe->eseg.cs_flags != cs_flags)) {
1328                                 mlx5_mpw_inline_close(txq, &mpw);
1329                                 inline_room =
1330                                         txq->max_inline * RTE_CACHE_LINE_SIZE;
1331                         }
1332                 }
1333                 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1334                         if ((segs_n != 1) ||
1335                             (length > inline_room)) {
1336                                 /*
1337                                  * Multi-Packet WQE consumes at most two WQE.
1338                                  * mlx5_mpw_new() expects to be able to use
1339                                  * such resources.
1340                                  */
1341                                 if (unlikely(max_wqe < 2))
1342                                         break;
1343                                 max_wqe -= 2;
1344                                 mlx5_mpw_new(txq, &mpw, length);
1345                                 mpw.wqe->eseg.cs_flags = cs_flags;
1346                                 mpw.wqe->eseg.flow_table_metadata = metadata;
1347                         } else {
1348                                 if (unlikely(max_wqe < wqe_inl_n))
1349                                         break;
1350                                 max_wqe -= wqe_inl_n;
1351                                 mlx5_mpw_inline_new(txq, &mpw, length);
1352                                 mpw.wqe->eseg.cs_flags = cs_flags;
1353                                 mpw.wqe->eseg.flow_table_metadata = metadata;
1354                         }
1355                 }
1356                 /* Multi-segment packets must be alone in their MPW. */
1357                 assert((segs_n == 1) || (mpw.pkts_n == 0));
1358                 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1359                         assert(inline_room ==
1360                                txq->max_inline * RTE_CACHE_LINE_SIZE);
1361 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1362                         length = 0;
1363 #endif
1364                         do {
1365                                 volatile struct mlx5_wqe_data_seg *dseg;
1366
1367                                 assert(buf);
1368                                 (*txq->elts)[elts_head++ & elts_m] = buf;
1369                                 dseg = mpw.data.dseg[mpw.pkts_n];
1370                                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1371                                 *dseg = (struct mlx5_wqe_data_seg){
1372                                         .byte_count =
1373                                                rte_cpu_to_be_32(DATA_LEN(buf)),
1374                                         .lkey = mlx5_tx_mb2mr(txq, buf),
1375                                         .addr = rte_cpu_to_be_64(addr),
1376                                 };
1377 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1378                                 length += DATA_LEN(buf);
1379 #endif
1380                                 buf = buf->next;
1381                                 ++mpw.pkts_n;
1382                                 ++j;
1383                         } while (--segs_n);
1384                         assert(length == mpw.len);
1385                         if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1386                                 mlx5_mpw_close(txq, &mpw);
1387                 } else {
1388                         unsigned int max;
1389
1390                         assert(mpw.state == MLX5_MPW_INL_STATE_OPENED);
1391                         assert(length <= inline_room);
1392                         assert(length == DATA_LEN(buf));
1393                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1394                         (*txq->elts)[elts_head++ & elts_m] = buf;
1395                         /* Maximum number of bytes before wrapping. */
1396                         max = ((((uintptr_t)(txq->wqes)) +
1397                                 (1 << txq->wqe_n) *
1398                                 MLX5_WQE_SIZE) -
1399                                (uintptr_t)mpw.data.raw);
1400                         if (length > max) {
1401                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1402                                            (void *)addr,
1403                                            max);
1404                                 mpw.data.raw = (volatile void *)txq->wqes;
1405                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1406                                            (void *)(addr + max),
1407                                            length - max);
1408                                 mpw.data.raw += length - max;
1409                         } else {
1410                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1411                                            (void *)addr,
1412                                            length);
1413
1414                                 if (length == max)
1415                                         mpw.data.raw =
1416                                                 (volatile void *)txq->wqes;
1417                                 else
1418                                         mpw.data.raw += length;
1419                         }
1420                         ++mpw.pkts_n;
1421                         mpw.total_len += length;
1422                         ++j;
1423                         if (mpw.pkts_n == MLX5_MPW_DSEG_MAX) {
1424                                 mlx5_mpw_inline_close(txq, &mpw);
1425                                 inline_room =
1426                                         txq->max_inline * RTE_CACHE_LINE_SIZE;
1427                         } else {
1428                                 inline_room -= length;
1429                         }
1430                 }
1431 #ifdef MLX5_PMD_SOFT_COUNTERS
1432                 /* Increment sent bytes counter. */
1433                 txq->stats.obytes += length;
1434 #endif
1435                 ++i;
1436         } while (pkts_n);
1437         /* Take a shortcut if nothing must be sent. */
1438         if (unlikely(i == 0))
1439                 return 0;
1440         /* Check whether completion threshold has been reached. */
1441         /* "j" includes both packets and segments. */
1442         comp = txq->elts_comp + j;
1443         if (comp >= MLX5_TX_COMP_THRESH) {
1444                 volatile struct mlx5_wqe *wqe = mpw.wqe;
1445
1446                 /* A CQE slot must always be available. */
1447                 assert((1u << txq->cqe_n) - (txq->cq_pi++ - txq->cq_ci));
1448                 /* Request completion on last WQE. */
1449                 wqe->ctrl[2] = rte_cpu_to_be_32(8);
1450                 /* Save elts_head in unused "immediate" field of WQE. */
1451                 wqe->ctrl[3] = elts_head;
1452                 txq->elts_comp = 0;
1453         } else {
1454                 txq->elts_comp = comp;
1455         }
1456 #ifdef MLX5_PMD_SOFT_COUNTERS
1457         /* Increment sent packets counter. */
1458         txq->stats.opackets += i;
1459 #endif
1460         /* Ring QP doorbell. */
1461         if (mpw.state == MLX5_MPW_INL_STATE_OPENED)
1462                 mlx5_mpw_inline_close(txq, &mpw);
1463         else if (mpw.state == MLX5_MPW_STATE_OPENED)
1464                 mlx5_mpw_close(txq, &mpw);
1465         mlx5_tx_dbrec(txq, mpw.wqe);
1466         txq->elts_head = elts_head;
1467         return i;
1468 }
1469
1470 /**
1471  * Open an Enhanced MPW session.
1472  *
1473  * @param txq
1474  *   Pointer to TX queue structure.
1475  * @param mpw
1476  *   Pointer to MPW session structure.
1477  * @param length
1478  *   Packet length.
1479  */
1480 static inline void
1481 mlx5_empw_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw, int padding)
1482 {
1483         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1484
1485         mpw->state = MLX5_MPW_ENHANCED_STATE_OPENED;
1486         mpw->pkts_n = 0;
1487         mpw->total_len = sizeof(struct mlx5_wqe);
1488         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1489         mpw->wqe->ctrl[0] =
1490                 rte_cpu_to_be_32((MLX5_OPC_MOD_ENHANCED_MPSW << 24) |
1491                                  (txq->wqe_ci << 8) |
1492                                  MLX5_OPCODE_ENHANCED_MPSW);
1493         mpw->wqe->ctrl[2] = 0;
1494         mpw->wqe->ctrl[3] = 0;
1495         memset((void *)(uintptr_t)&mpw->wqe->eseg, 0, MLX5_WQE_DWORD_SIZE);
1496         if (unlikely(padding)) {
1497                 uintptr_t addr = (uintptr_t)(mpw->wqe + 1);
1498
1499                 /* Pad the first 2 DWORDs with zero-length inline header. */
1500                 *(volatile uint32_t *)addr = rte_cpu_to_be_32(MLX5_INLINE_SEG);
1501                 *(volatile uint32_t *)(addr + MLX5_WQE_DWORD_SIZE) =
1502                         rte_cpu_to_be_32(MLX5_INLINE_SEG);
1503                 mpw->total_len += 2 * MLX5_WQE_DWORD_SIZE;
1504                 /* Start from the next WQEBB. */
1505                 mpw->data.raw = (volatile void *)(tx_mlx5_wqe(txq, idx + 1));
1506         } else {
1507                 mpw->data.raw = (volatile void *)(mpw->wqe + 1);
1508         }
1509 }
1510
1511 /**
1512  * Close an Enhanced MPW session.
1513  *
1514  * @param txq
1515  *   Pointer to TX queue structure.
1516  * @param mpw
1517  *   Pointer to MPW session structure.
1518  *
1519  * @return
1520  *   Number of consumed WQEs.
1521  */
1522 static inline uint16_t
1523 mlx5_empw_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
1524 {
1525         uint16_t ret;
1526
1527         /* Store size in multiple of 16 bytes. Control and Ethernet segments
1528          * count as 2.
1529          */
1530         mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s |
1531                                              MLX5_WQE_DS(mpw->total_len));
1532         mpw->state = MLX5_MPW_STATE_CLOSED;
1533         ret = (mpw->total_len + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1534         txq->wqe_ci += ret;
1535         return ret;
1536 }
1537
1538 /**
1539  * TX with Enhanced MPW support.
1540  *
1541  * @param txq
1542  *   Pointer to TX queue structure.
1543  * @param[in] pkts
1544  *   Packets to transmit.
1545  * @param pkts_n
1546  *   Number of packets in array.
1547  *
1548  * @return
1549  *   Number of packets successfully transmitted (<= pkts_n).
1550  */
1551 static inline uint16_t
1552 txq_burst_empw(struct mlx5_txq_data *txq, struct rte_mbuf **pkts,
1553                uint16_t pkts_n)
1554 {
1555         uint16_t elts_head = txq->elts_head;
1556         const uint16_t elts_n = 1 << txq->elts_n;
1557         const uint16_t elts_m = elts_n - 1;
1558         unsigned int i = 0;
1559         unsigned int j = 0;
1560         uint16_t max_elts;
1561         uint16_t max_wqe;
1562         unsigned int max_inline = txq->max_inline * RTE_CACHE_LINE_SIZE;
1563         unsigned int mpw_room = 0;
1564         unsigned int inl_pad = 0;
1565         uint32_t inl_hdr;
1566         uint64_t addr_64;
1567         struct mlx5_mpw mpw = {
1568                 .state = MLX5_MPW_STATE_CLOSED,
1569         };
1570
1571         if (unlikely(!pkts_n))
1572                 return 0;
1573         /* Start processing. */
1574         mlx5_tx_complete(txq);
1575         max_elts = (elts_n - (elts_head - txq->elts_tail));
1576         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1577         if (unlikely(!max_wqe))
1578                 return 0;
1579         do {
1580                 struct rte_mbuf *buf = *(pkts++);
1581                 uintptr_t addr;
1582                 unsigned int do_inline = 0; /* Whether inline is possible. */
1583                 uint32_t length;
1584                 uint8_t cs_flags;
1585                 rte_be32_t metadata;
1586
1587                 /* Multi-segmented packet is handled in slow-path outside. */
1588                 assert(NB_SEGS(buf) == 1);
1589                 /* Make sure there is enough room to store this packet. */
1590                 if (max_elts - j == 0)
1591                         break;
1592                 cs_flags = txq_ol_cksum_to_cs(buf);
1593                 /* Copy metadata from mbuf if valid */
1594                 metadata = buf->ol_flags & PKT_TX_METADATA ? buf->tx_metadata :
1595                                                              0;
1596                 /* Retrieve packet information. */
1597                 length = PKT_LEN(buf);
1598                 /* Start new session if:
1599                  * - multi-segment packet
1600                  * - no space left even for a dseg
1601                  * - next packet can be inlined with a new WQE
1602                  * - cs_flag differs
1603                  */
1604                 if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED) {
1605                         if ((inl_pad + sizeof(struct mlx5_wqe_data_seg) >
1606                              mpw_room) ||
1607                             (length <= txq->inline_max_packet_sz &&
1608                              inl_pad + sizeof(inl_hdr) + length >
1609                              mpw_room) ||
1610                              (mpw.wqe->eseg.flow_table_metadata != metadata) ||
1611                             (mpw.wqe->eseg.cs_flags != cs_flags))
1612                                 max_wqe -= mlx5_empw_close(txq, &mpw);
1613                 }
1614                 if (unlikely(mpw.state == MLX5_MPW_STATE_CLOSED)) {
1615                         /* In Enhanced MPW, inline as much as the budget is
1616                          * allowed. The remaining space is to be filled with
1617                          * dsegs. If the title WQEBB isn't padded, it will have
1618                          * 2 dsegs there.
1619                          */
1620                         mpw_room = RTE_MIN(MLX5_WQE_SIZE_MAX,
1621                                            (max_inline ? max_inline :
1622                                             pkts_n * MLX5_WQE_DWORD_SIZE) +
1623                                            MLX5_WQE_SIZE);
1624                         if (unlikely(max_wqe * MLX5_WQE_SIZE < mpw_room))
1625                                 break;
1626                         /* Don't pad the title WQEBB to not waste WQ. */
1627                         mlx5_empw_new(txq, &mpw, 0);
1628                         mpw_room -= mpw.total_len;
1629                         inl_pad = 0;
1630                         do_inline = length <= txq->inline_max_packet_sz &&
1631                                     sizeof(inl_hdr) + length <= mpw_room &&
1632                                     !txq->mpw_hdr_dseg;
1633                         mpw.wqe->eseg.cs_flags = cs_flags;
1634                         mpw.wqe->eseg.flow_table_metadata = metadata;
1635                 } else {
1636                         /* Evaluate whether the next packet can be inlined.
1637                          * Inlininig is possible when:
1638                          * - length is less than configured value
1639                          * - length fits for remaining space
1640                          * - not required to fill the title WQEBB with dsegs
1641                          */
1642                         do_inline =
1643                                 length <= txq->inline_max_packet_sz &&
1644                                 inl_pad + sizeof(inl_hdr) + length <=
1645                                  mpw_room &&
1646                                 (!txq->mpw_hdr_dseg ||
1647                                  mpw.total_len >= MLX5_WQE_SIZE);
1648                 }
1649                 if (max_inline && do_inline) {
1650                         /* Inline packet into WQE. */
1651                         unsigned int max;
1652
1653                         assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1654                         assert(length == DATA_LEN(buf));
1655                         inl_hdr = rte_cpu_to_be_32(length | MLX5_INLINE_SEG);
1656                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1657                         mpw.data.raw = (volatile void *)
1658                                 ((uintptr_t)mpw.data.raw + inl_pad);
1659                         max = tx_mlx5_wq_tailroom(txq,
1660                                         (void *)(uintptr_t)mpw.data.raw);
1661                         /* Copy inline header. */
1662                         mpw.data.raw = (volatile void *)
1663                                 mlx5_copy_to_wq(
1664                                           (void *)(uintptr_t)mpw.data.raw,
1665                                           &inl_hdr,
1666                                           sizeof(inl_hdr),
1667                                           (void *)(uintptr_t)txq->wqes,
1668                                           max);
1669                         max = tx_mlx5_wq_tailroom(txq,
1670                                         (void *)(uintptr_t)mpw.data.raw);
1671                         /* Copy packet data. */
1672                         mpw.data.raw = (volatile void *)
1673                                 mlx5_copy_to_wq(
1674                                           (void *)(uintptr_t)mpw.data.raw,
1675                                           (void *)addr,
1676                                           length,
1677                                           (void *)(uintptr_t)txq->wqes,
1678                                           max);
1679                         ++mpw.pkts_n;
1680                         mpw.total_len += (inl_pad + sizeof(inl_hdr) + length);
1681                         /* No need to get completion as the entire packet is
1682                          * copied to WQ. Free the buf right away.
1683                          */
1684                         rte_pktmbuf_free_seg(buf);
1685                         mpw_room -= (inl_pad + sizeof(inl_hdr) + length);
1686                         /* Add pad in the next packet if any. */
1687                         inl_pad = (((uintptr_t)mpw.data.raw +
1688                                         (MLX5_WQE_DWORD_SIZE - 1)) &
1689                                         ~(MLX5_WQE_DWORD_SIZE - 1)) -
1690                                   (uintptr_t)mpw.data.raw;
1691                 } else {
1692                         /* No inline. Load a dseg of packet pointer. */
1693                         volatile rte_v128u32_t *dseg;
1694
1695                         assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1696                         assert((inl_pad + sizeof(*dseg)) <= mpw_room);
1697                         assert(length == DATA_LEN(buf));
1698                         if (!tx_mlx5_wq_tailroom(txq,
1699                                         (void *)((uintptr_t)mpw.data.raw
1700                                                 + inl_pad)))
1701                                 dseg = (volatile void *)txq->wqes;
1702                         else
1703                                 dseg = (volatile void *)
1704                                         ((uintptr_t)mpw.data.raw +
1705                                          inl_pad);
1706                         (*txq->elts)[elts_head++ & elts_m] = buf;
1707                         addr_64 = rte_cpu_to_be_64(rte_pktmbuf_mtod(buf,
1708                                                                     uintptr_t));
1709                         *dseg = (rte_v128u32_t) {
1710                                 rte_cpu_to_be_32(length),
1711                                 mlx5_tx_mb2mr(txq, buf),
1712                                 addr_64,
1713                                 addr_64 >> 32,
1714                         };
1715                         mpw.data.raw = (volatile void *)(dseg + 1);
1716                         mpw.total_len += (inl_pad + sizeof(*dseg));
1717                         ++j;
1718                         ++mpw.pkts_n;
1719                         mpw_room -= (inl_pad + sizeof(*dseg));
1720                         inl_pad = 0;
1721                 }
1722 #ifdef MLX5_PMD_SOFT_COUNTERS
1723                 /* Increment sent bytes counter. */
1724                 txq->stats.obytes += length;
1725 #endif
1726                 ++i;
1727         } while (i < pkts_n);
1728         /* Take a shortcut if nothing must be sent. */
1729         if (unlikely(i == 0))
1730                 return 0;
1731         /* Check whether completion threshold has been reached. */
1732         if (txq->elts_comp + j >= MLX5_TX_COMP_THRESH ||
1733                         (uint16_t)(txq->wqe_ci - txq->mpw_comp) >=
1734                          (1 << txq->wqe_n) / MLX5_TX_COMP_THRESH_INLINE_DIV) {
1735                 volatile struct mlx5_wqe *wqe = mpw.wqe;
1736
1737                 /* A CQE slot must always be available. */
1738                 assert((1u << txq->cqe_n) - (txq->cq_pi++ - txq->cq_ci));
1739                 /* Request completion on last WQE. */
1740                 wqe->ctrl[2] = rte_cpu_to_be_32(8);
1741                 /* Save elts_head in unused "immediate" field of WQE. */
1742                 wqe->ctrl[3] = elts_head;
1743                 txq->elts_comp = 0;
1744                 txq->mpw_comp = txq->wqe_ci;
1745         } else {
1746                 txq->elts_comp += j;
1747         }
1748 #ifdef MLX5_PMD_SOFT_COUNTERS
1749         /* Increment sent packets counter. */
1750         txq->stats.opackets += i;
1751 #endif
1752         if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED)
1753                 mlx5_empw_close(txq, &mpw);
1754         /* Ring QP doorbell. */
1755         mlx5_tx_dbrec(txq, mpw.wqe);
1756         txq->elts_head = elts_head;
1757         return i;
1758 }
1759
1760 /**
1761  * DPDK callback for TX with Enhanced MPW support.
1762  *
1763  * @param dpdk_txq
1764  *   Generic pointer to TX queue structure.
1765  * @param[in] pkts
1766  *   Packets to transmit.
1767  * @param pkts_n
1768  *   Number of packets in array.
1769  *
1770  * @return
1771  *   Number of packets successfully transmitted (<= pkts_n).
1772  */
1773 uint16_t
1774 mlx5_tx_burst_empw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1775 {
1776         struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
1777         uint16_t nb_tx = 0;
1778
1779         while (pkts_n > nb_tx) {
1780                 uint16_t n;
1781                 uint16_t ret;
1782
1783                 n = txq_count_contig_multi_seg(&pkts[nb_tx], pkts_n - nb_tx);
1784                 if (n) {
1785                         ret = mlx5_tx_burst(dpdk_txq, &pkts[nb_tx], n);
1786                         if (!ret)
1787                                 break;
1788                         nb_tx += ret;
1789                 }
1790                 n = txq_count_contig_single_seg(&pkts[nb_tx], pkts_n - nb_tx);
1791                 if (n) {
1792                         ret = txq_burst_empw(txq, &pkts[nb_tx], n);
1793                         if (!ret)
1794                                 break;
1795                         nb_tx += ret;
1796                 }
1797         }
1798         return nb_tx;
1799 }
1800
1801 /**
1802  * Translate RX completion flags to packet type.
1803  *
1804  * @param[in] rxq
1805  *   Pointer to RX queue structure.
1806  * @param[in] cqe
1807  *   Pointer to CQE.
1808  *
1809  * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
1810  *
1811  * @return
1812  *   Packet type for struct rte_mbuf.
1813  */
1814 static inline uint32_t
1815 rxq_cq_to_pkt_type(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe)
1816 {
1817         uint8_t idx;
1818         uint8_t pinfo = cqe->pkt_info;
1819         uint16_t ptype = cqe->hdr_type_etc;
1820
1821         /*
1822          * The index to the array should have:
1823          * bit[1:0] = l3_hdr_type
1824          * bit[4:2] = l4_hdr_type
1825          * bit[5] = ip_frag
1826          * bit[6] = tunneled
1827          * bit[7] = outer_l3_type
1828          */
1829         idx = ((pinfo & 0x3) << 6) | ((ptype & 0xfc00) >> 10);
1830         return mlx5_ptype_table[idx] | rxq->tunnel * !!(idx & (1 << 6));
1831 }
1832
1833 /**
1834  * Initialize Rx WQ and indexes.
1835  *
1836  * @param[in] rxq
1837  *   Pointer to RX queue structure.
1838  */
1839 void
1840 mlx5_rxq_initialize(struct mlx5_rxq_data *rxq)
1841 {
1842         const unsigned int wqe_n = 1 << rxq->elts_n;
1843         unsigned int i;
1844
1845         for (i = 0; (i != wqe_n); ++i) {
1846                 volatile struct mlx5_wqe_data_seg *scat;
1847                 uintptr_t addr;
1848                 uint32_t byte_count;
1849
1850                 if (mlx5_rxq_mprq_enabled(rxq)) {
1851                         struct mlx5_mprq_buf *buf = (*rxq->mprq_bufs)[i];
1852
1853                         scat = &((volatile struct mlx5_wqe_mprq *)
1854                                 rxq->wqes)[i].dseg;
1855                         addr = (uintptr_t)mlx5_mprq_buf_addr(buf);
1856                         byte_count = (1 << rxq->strd_sz_n) *
1857                                         (1 << rxq->strd_num_n);
1858                 } else {
1859                         struct rte_mbuf *buf = (*rxq->elts)[i];
1860
1861                         scat = &((volatile struct mlx5_wqe_data_seg *)
1862                                         rxq->wqes)[i];
1863                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1864                         byte_count = DATA_LEN(buf);
1865                 }
1866                 /* scat->addr must be able to store a pointer. */
1867                 assert(sizeof(scat->addr) >= sizeof(uintptr_t));
1868                 *scat = (struct mlx5_wqe_data_seg){
1869                         .addr = rte_cpu_to_be_64(addr),
1870                         .byte_count = rte_cpu_to_be_32(byte_count),
1871                         .lkey = mlx5_rx_addr2mr(rxq, addr),
1872                 };
1873         }
1874         rxq->consumed_strd = 0;
1875         rxq->decompressed = 0;
1876         rxq->rq_pi = 0;
1877         rxq->zip = (struct rxq_zip){
1878                 .ai = 0,
1879         };
1880         /* Update doorbell counter. */
1881         rxq->rq_ci = wqe_n >> rxq->sges_n;
1882         rte_cio_wmb();
1883         *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
1884 }
1885
1886 /**
1887  * Get size of the next packet for a given CQE. For compressed CQEs, the
1888  * consumer index is updated only once all packets of the current one have
1889  * been processed.
1890  *
1891  * @param rxq
1892  *   Pointer to RX queue.
1893  * @param cqe
1894  *   CQE to process.
1895  * @param[out] mcqe
1896  *   Store pointer to mini-CQE if compressed. Otherwise, the pointer is not
1897  *   written.
1898  *
1899  * @return
1900  *   Packet size in bytes (0 if there is none), -1 in case of completion
1901  *   with error.
1902  */
1903 static inline int
1904 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
1905                  uint16_t cqe_cnt, volatile struct mlx5_mini_cqe8 **mcqe)
1906 {
1907         struct rxq_zip *zip = &rxq->zip;
1908         uint16_t cqe_n = cqe_cnt + 1;
1909         int len = 0;
1910         uint16_t idx, end;
1911
1912         /* Process compressed data in the CQE and mini arrays. */
1913         if (zip->ai) {
1914                 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1915                         (volatile struct mlx5_mini_cqe8 (*)[8])
1916                         (uintptr_t)(&(*rxq->cqes)[zip->ca & cqe_cnt].pkt_info);
1917
1918                 len = rte_be_to_cpu_32((*mc)[zip->ai & 7].byte_cnt);
1919                 *mcqe = &(*mc)[zip->ai & 7];
1920                 if ((++zip->ai & 7) == 0) {
1921                         /* Invalidate consumed CQEs */
1922                         idx = zip->ca;
1923                         end = zip->na;
1924                         while (idx != end) {
1925                                 (*rxq->cqes)[idx & cqe_cnt].op_own =
1926                                         MLX5_CQE_INVALIDATE;
1927                                 ++idx;
1928                         }
1929                         /*
1930                          * Increment consumer index to skip the number of
1931                          * CQEs consumed. Hardware leaves holes in the CQ
1932                          * ring for software use.
1933                          */
1934                         zip->ca = zip->na;
1935                         zip->na += 8;
1936                 }
1937                 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1938                         /* Invalidate the rest */
1939                         idx = zip->ca;
1940                         end = zip->cq_ci;
1941
1942                         while (idx != end) {
1943                                 (*rxq->cqes)[idx & cqe_cnt].op_own =
1944                                         MLX5_CQE_INVALIDATE;
1945                                 ++idx;
1946                         }
1947                         rxq->cq_ci = zip->cq_ci;
1948                         zip->ai = 0;
1949                 }
1950         /* No compressed data, get next CQE and verify if it is compressed. */
1951         } else {
1952                 int ret;
1953                 int8_t op_own;
1954
1955                 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1956                 if (unlikely(ret == 1))
1957                         return 0;
1958                 ++rxq->cq_ci;
1959                 op_own = cqe->op_own;
1960                 rte_cio_rmb();
1961                 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1962                         volatile struct mlx5_mini_cqe8 (*mc)[8] =
1963                                 (volatile struct mlx5_mini_cqe8 (*)[8])
1964                                 (uintptr_t)(&(*rxq->cqes)[rxq->cq_ci &
1965                                                           cqe_cnt].pkt_info);
1966
1967                         /* Fix endianness. */
1968                         zip->cqe_cnt = rte_be_to_cpu_32(cqe->byte_cnt);
1969                         /*
1970                          * Current mini array position is the one returned by
1971                          * check_cqe64().
1972                          *
1973                          * If completion comprises several mini arrays, as a
1974                          * special case the second one is located 7 CQEs after
1975                          * the initial CQE instead of 8 for subsequent ones.
1976                          */
1977                         zip->ca = rxq->cq_ci;
1978                         zip->na = zip->ca + 7;
1979                         /* Compute the next non compressed CQE. */
1980                         --rxq->cq_ci;
1981                         zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1982                         /* Get packet size to return. */
1983                         len = rte_be_to_cpu_32((*mc)[0].byte_cnt);
1984                         *mcqe = &(*mc)[0];
1985                         zip->ai = 1;
1986                         /* Prefetch all the entries to be invalidated */
1987                         idx = zip->ca;
1988                         end = zip->cq_ci;
1989                         while (idx != end) {
1990                                 rte_prefetch0(&(*rxq->cqes)[(idx) & cqe_cnt]);
1991                                 ++idx;
1992                         }
1993                 } else {
1994                         len = rte_be_to_cpu_32(cqe->byte_cnt);
1995                 }
1996                 /* Error while receiving packet. */
1997                 if (unlikely(MLX5_CQE_OPCODE(op_own) == MLX5_CQE_RESP_ERR))
1998                         return -1;
1999         }
2000         return len;
2001 }
2002
2003 /**
2004  * Translate RX completion flags to offload flags.
2005  *
2006  * @param[in] cqe
2007  *   Pointer to CQE.
2008  *
2009  * @return
2010  *   Offload flags (ol_flags) for struct rte_mbuf.
2011  */
2012 static inline uint32_t
2013 rxq_cq_to_ol_flags(volatile struct mlx5_cqe *cqe)
2014 {
2015         uint32_t ol_flags = 0;
2016         uint16_t flags = rte_be_to_cpu_16(cqe->hdr_type_etc);
2017
2018         ol_flags =
2019                 TRANSPOSE(flags,
2020                           MLX5_CQE_RX_L3_HDR_VALID,
2021                           PKT_RX_IP_CKSUM_GOOD) |
2022                 TRANSPOSE(flags,
2023                           MLX5_CQE_RX_L4_HDR_VALID,
2024                           PKT_RX_L4_CKSUM_GOOD);
2025         return ol_flags;
2026 }
2027
2028 /**
2029  * Fill in mbuf fields from RX completion flags.
2030  * Note that pkt->ol_flags should be initialized outside of this function.
2031  *
2032  * @param rxq
2033  *   Pointer to RX queue.
2034  * @param pkt
2035  *   mbuf to fill.
2036  * @param cqe
2037  *   CQE to process.
2038  * @param rss_hash_res
2039  *   Packet RSS Hash result.
2040  */
2041 static inline void
2042 rxq_cq_to_mbuf(struct mlx5_rxq_data *rxq, struct rte_mbuf *pkt,
2043                volatile struct mlx5_cqe *cqe, uint32_t rss_hash_res)
2044 {
2045         /* Update packet information. */
2046         pkt->packet_type = rxq_cq_to_pkt_type(rxq, cqe);
2047         if (rss_hash_res && rxq->rss_hash) {
2048                 pkt->hash.rss = rss_hash_res;
2049                 pkt->ol_flags |= PKT_RX_RSS_HASH;
2050         }
2051         if (rxq->mark && MLX5_FLOW_MARK_IS_VALID(cqe->sop_drop_qpn)) {
2052                 pkt->ol_flags |= PKT_RX_FDIR;
2053                 if (cqe->sop_drop_qpn !=
2054                     rte_cpu_to_be_32(MLX5_FLOW_MARK_DEFAULT)) {
2055                         uint32_t mark = cqe->sop_drop_qpn;
2056
2057                         pkt->ol_flags |= PKT_RX_FDIR_ID;
2058                         pkt->hash.fdir.hi = mlx5_flow_mark_get(mark);
2059                 }
2060         }
2061         if (rxq->csum)
2062                 pkt->ol_flags |= rxq_cq_to_ol_flags(cqe);
2063         if (rxq->vlan_strip &&
2064             (cqe->hdr_type_etc & rte_cpu_to_be_16(MLX5_CQE_VLAN_STRIPPED))) {
2065                 pkt->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
2066                 pkt->vlan_tci = rte_be_to_cpu_16(cqe->vlan_info);
2067         }
2068         if (rxq->hw_timestamp) {
2069                 pkt->timestamp = rte_be_to_cpu_64(cqe->timestamp);
2070                 pkt->ol_flags |= PKT_RX_TIMESTAMP;
2071         }
2072 }
2073
2074 /**
2075  * DPDK callback for RX.
2076  *
2077  * @param dpdk_rxq
2078  *   Generic pointer to RX queue structure.
2079  * @param[out] pkts
2080  *   Array to store received packets.
2081  * @param pkts_n
2082  *   Maximum number of packets in array.
2083  *
2084  * @return
2085  *   Number of packets successfully received (<= pkts_n).
2086  */
2087 uint16_t
2088 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
2089 {
2090         struct mlx5_rxq_data *rxq = dpdk_rxq;
2091         const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
2092         const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
2093         const unsigned int sges_n = rxq->sges_n;
2094         struct rte_mbuf *pkt = NULL;
2095         struct rte_mbuf *seg = NULL;
2096         volatile struct mlx5_cqe *cqe =
2097                 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
2098         unsigned int i = 0;
2099         unsigned int rq_ci = rxq->rq_ci << sges_n;
2100         int len = 0; /* keep its value across iterations. */
2101
2102         while (pkts_n) {
2103                 unsigned int idx = rq_ci & wqe_cnt;
2104                 volatile struct mlx5_wqe_data_seg *wqe =
2105                         &((volatile struct mlx5_wqe_data_seg *)rxq->wqes)[idx];
2106                 struct rte_mbuf *rep = (*rxq->elts)[idx];
2107                 volatile struct mlx5_mini_cqe8 *mcqe = NULL;
2108                 uint32_t rss_hash_res;
2109
2110                 if (pkt)
2111                         NEXT(seg) = rep;
2112                 seg = rep;
2113                 rte_prefetch0(seg);
2114                 rte_prefetch0(cqe);
2115                 rte_prefetch0(wqe);
2116                 rep = rte_mbuf_raw_alloc(rxq->mp);
2117                 if (unlikely(rep == NULL)) {
2118                         ++rxq->stats.rx_nombuf;
2119                         if (!pkt) {
2120                                 /*
2121                                  * no buffers before we even started,
2122                                  * bail out silently.
2123                                  */
2124                                 break;
2125                         }
2126                         while (pkt != seg) {
2127                                 assert(pkt != (*rxq->elts)[idx]);
2128                                 rep = NEXT(pkt);
2129                                 NEXT(pkt) = NULL;
2130                                 NB_SEGS(pkt) = 1;
2131                                 rte_mbuf_raw_free(pkt);
2132                                 pkt = rep;
2133                         }
2134                         break;
2135                 }
2136                 if (!pkt) {
2137                         cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
2138                         len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt, &mcqe);
2139                         if (!len) {
2140                                 rte_mbuf_raw_free(rep);
2141                                 break;
2142                         }
2143                         if (unlikely(len == -1)) {
2144                                 /* RX error, packet is likely too large. */
2145                                 rte_mbuf_raw_free(rep);
2146                                 ++rxq->stats.idropped;
2147                                 goto skip;
2148                         }
2149                         pkt = seg;
2150                         assert(len >= (rxq->crc_present << 2));
2151                         pkt->ol_flags = 0;
2152                         /* If compressed, take hash result from mini-CQE. */
2153                         rss_hash_res = rte_be_to_cpu_32(mcqe == NULL ?
2154                                                         cqe->rx_hash_res :
2155                                                         mcqe->rx_hash_result);
2156                         rxq_cq_to_mbuf(rxq, pkt, cqe, rss_hash_res);
2157                         if (rxq->crc_present)
2158                                 len -= RTE_ETHER_CRC_LEN;
2159                         PKT_LEN(pkt) = len;
2160                 }
2161                 DATA_LEN(rep) = DATA_LEN(seg);
2162                 PKT_LEN(rep) = PKT_LEN(seg);
2163                 SET_DATA_OFF(rep, DATA_OFF(seg));
2164                 PORT(rep) = PORT(seg);
2165                 (*rxq->elts)[idx] = rep;
2166                 /*
2167                  * Fill NIC descriptor with the new buffer.  The lkey and size
2168                  * of the buffers are already known, only the buffer address
2169                  * changes.
2170                  */
2171                 wqe->addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(rep, uintptr_t));
2172                 /* If there's only one MR, no need to replace LKey in WQE. */
2173                 if (unlikely(mlx5_mr_btree_len(&rxq->mr_ctrl.cache_bh) > 1))
2174                         wqe->lkey = mlx5_rx_mb2mr(rxq, rep);
2175                 if (len > DATA_LEN(seg)) {
2176                         len -= DATA_LEN(seg);
2177                         ++NB_SEGS(pkt);
2178                         ++rq_ci;
2179                         continue;
2180                 }
2181                 DATA_LEN(seg) = len;
2182 #ifdef MLX5_PMD_SOFT_COUNTERS
2183                 /* Increment bytes counter. */
2184                 rxq->stats.ibytes += PKT_LEN(pkt);
2185 #endif
2186                 /* Return packet. */
2187                 *(pkts++) = pkt;
2188                 pkt = NULL;
2189                 --pkts_n;
2190                 ++i;
2191 skip:
2192                 /* Align consumer index to the next stride. */
2193                 rq_ci >>= sges_n;
2194                 ++rq_ci;
2195                 rq_ci <<= sges_n;
2196         }
2197         if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
2198                 return 0;
2199         /* Update the consumer index. */
2200         rxq->rq_ci = rq_ci >> sges_n;
2201         rte_cio_wmb();
2202         *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
2203         rte_cio_wmb();
2204         *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
2205 #ifdef MLX5_PMD_SOFT_COUNTERS
2206         /* Increment packets counter. */
2207         rxq->stats.ipackets += i;
2208 #endif
2209         return i;
2210 }
2211
2212 void
2213 mlx5_mprq_buf_free_cb(void *addr __rte_unused, void *opaque)
2214 {
2215         struct mlx5_mprq_buf *buf = opaque;
2216
2217         if (rte_atomic16_read(&buf->refcnt) == 1) {
2218                 rte_mempool_put(buf->mp, buf);
2219         } else if (rte_atomic16_add_return(&buf->refcnt, -1) == 0) {
2220                 rte_atomic16_set(&buf->refcnt, 1);
2221                 rte_mempool_put(buf->mp, buf);
2222         }
2223 }
2224
2225 void
2226 mlx5_mprq_buf_free(struct mlx5_mprq_buf *buf)
2227 {
2228         mlx5_mprq_buf_free_cb(NULL, buf);
2229 }
2230
2231 static inline void
2232 mprq_buf_replace(struct mlx5_rxq_data *rxq, uint16_t rq_idx)
2233 {
2234         struct mlx5_mprq_buf *rep = rxq->mprq_repl;
2235         volatile struct mlx5_wqe_data_seg *wqe =
2236                 &((volatile struct mlx5_wqe_mprq *)rxq->wqes)[rq_idx].dseg;
2237         void *addr;
2238
2239         assert(rep != NULL);
2240         /* Replace MPRQ buf. */
2241         (*rxq->mprq_bufs)[rq_idx] = rep;
2242         /* Replace WQE. */
2243         addr = mlx5_mprq_buf_addr(rep);
2244         wqe->addr = rte_cpu_to_be_64((uintptr_t)addr);
2245         /* If there's only one MR, no need to replace LKey in WQE. */
2246         if (unlikely(mlx5_mr_btree_len(&rxq->mr_ctrl.cache_bh) > 1))
2247                 wqe->lkey = mlx5_rx_addr2mr(rxq, (uintptr_t)addr);
2248         /* Stash a mbuf for next replacement. */
2249         if (likely(!rte_mempool_get(rxq->mprq_mp, (void **)&rep)))
2250                 rxq->mprq_repl = rep;
2251         else
2252                 rxq->mprq_repl = NULL;
2253 }
2254
2255 /**
2256  * DPDK callback for RX with Multi-Packet RQ support.
2257  *
2258  * @param dpdk_rxq
2259  *   Generic pointer to RX queue structure.
2260  * @param[out] pkts
2261  *   Array to store received packets.
2262  * @param pkts_n
2263  *   Maximum number of packets in array.
2264  *
2265  * @return
2266  *   Number of packets successfully received (<= pkts_n).
2267  */
2268 uint16_t
2269 mlx5_rx_burst_mprq(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
2270 {
2271         struct mlx5_rxq_data *rxq = dpdk_rxq;
2272         const unsigned int strd_n = 1 << rxq->strd_num_n;
2273         const unsigned int strd_sz = 1 << rxq->strd_sz_n;
2274         const unsigned int strd_shift =
2275                 MLX5_MPRQ_STRIDE_SHIFT_BYTE * rxq->strd_shift_en;
2276         const unsigned int cq_mask = (1 << rxq->cqe_n) - 1;
2277         const unsigned int wq_mask = (1 << rxq->elts_n) - 1;
2278         volatile struct mlx5_cqe *cqe = &(*rxq->cqes)[rxq->cq_ci & cq_mask];
2279         unsigned int i = 0;
2280         uint32_t rq_ci = rxq->rq_ci;
2281         uint16_t consumed_strd = rxq->consumed_strd;
2282         struct mlx5_mprq_buf *buf = (*rxq->mprq_bufs)[rq_ci & wq_mask];
2283
2284         while (i < pkts_n) {
2285                 struct rte_mbuf *pkt;
2286                 void *addr;
2287                 int ret;
2288                 unsigned int len;
2289                 uint16_t strd_cnt;
2290                 uint16_t strd_idx;
2291                 uint32_t offset;
2292                 uint32_t byte_cnt;
2293                 volatile struct mlx5_mini_cqe8 *mcqe = NULL;
2294                 uint32_t rss_hash_res = 0;
2295
2296                 if (consumed_strd == strd_n) {
2297                         /* Replace WQE only if the buffer is still in use. */
2298                         if (rte_atomic16_read(&buf->refcnt) > 1) {
2299                                 mprq_buf_replace(rxq, rq_ci & wq_mask);
2300                                 /* Release the old buffer. */
2301                                 mlx5_mprq_buf_free(buf);
2302                         } else if (unlikely(rxq->mprq_repl == NULL)) {
2303                                 struct mlx5_mprq_buf *rep;
2304
2305                                 /*
2306                                  * Currently, the MPRQ mempool is out of buffer
2307                                  * and doing memcpy regardless of the size of Rx
2308                                  * packet. Retry allocation to get back to
2309                                  * normal.
2310                                  */
2311                                 if (!rte_mempool_get(rxq->mprq_mp,
2312                                                      (void **)&rep))
2313                                         rxq->mprq_repl = rep;
2314                         }
2315                         /* Advance to the next WQE. */
2316                         consumed_strd = 0;
2317                         ++rq_ci;
2318                         buf = (*rxq->mprq_bufs)[rq_ci & wq_mask];
2319                 }
2320                 cqe = &(*rxq->cqes)[rxq->cq_ci & cq_mask];
2321                 ret = mlx5_rx_poll_len(rxq, cqe, cq_mask, &mcqe);
2322                 if (!ret)
2323                         break;
2324                 if (unlikely(ret == -1)) {
2325                         /* RX error, packet is likely too large. */
2326                         ++rxq->stats.idropped;
2327                         continue;
2328                 }
2329                 byte_cnt = ret;
2330                 strd_cnt = (byte_cnt & MLX5_MPRQ_STRIDE_NUM_MASK) >>
2331                            MLX5_MPRQ_STRIDE_NUM_SHIFT;
2332                 assert(strd_cnt);
2333                 consumed_strd += strd_cnt;
2334                 if (byte_cnt & MLX5_MPRQ_FILLER_MASK)
2335                         continue;
2336                 if (mcqe == NULL) {
2337                         rss_hash_res = rte_be_to_cpu_32(cqe->rx_hash_res);
2338                         strd_idx = rte_be_to_cpu_16(cqe->wqe_counter);
2339                 } else {
2340                         /* mini-CQE for MPRQ doesn't have hash result. */
2341                         strd_idx = rte_be_to_cpu_16(mcqe->stride_idx);
2342                 }
2343                 assert(strd_idx < strd_n);
2344                 assert(!((rte_be_to_cpu_16(cqe->wqe_id) ^ rq_ci) & wq_mask));
2345                 /*
2346                  * Currently configured to receive a packet per a stride. But if
2347                  * MTU is adjusted through kernel interface, device could
2348                  * consume multiple strides without raising an error. In this
2349                  * case, the packet should be dropped because it is bigger than
2350                  * the max_rx_pkt_len.
2351                  */
2352                 if (unlikely(strd_cnt > 1)) {
2353                         ++rxq->stats.idropped;
2354                         continue;
2355                 }
2356                 pkt = rte_pktmbuf_alloc(rxq->mp);
2357                 if (unlikely(pkt == NULL)) {
2358                         ++rxq->stats.rx_nombuf;
2359                         break;
2360                 }
2361                 len = (byte_cnt & MLX5_MPRQ_LEN_MASK) >> MLX5_MPRQ_LEN_SHIFT;
2362                 assert((int)len >= (rxq->crc_present << 2));
2363                 if (rxq->crc_present)
2364                         len -= RTE_ETHER_CRC_LEN;
2365                 offset = strd_idx * strd_sz + strd_shift;
2366                 addr = RTE_PTR_ADD(mlx5_mprq_buf_addr(buf), offset);
2367                 /* Initialize the offload flag. */
2368                 pkt->ol_flags = 0;
2369                 /*
2370                  * Memcpy packets to the target mbuf if:
2371                  * - The size of packet is smaller than mprq_max_memcpy_len.
2372                  * - Out of buffer in the Mempool for Multi-Packet RQ.
2373                  */
2374                 if (len <= rxq->mprq_max_memcpy_len || rxq->mprq_repl == NULL) {
2375                         /*
2376                          * When memcpy'ing packet due to out-of-buffer, the
2377                          * packet must be smaller than the target mbuf.
2378                          */
2379                         if (unlikely(rte_pktmbuf_tailroom(pkt) < len)) {
2380                                 rte_pktmbuf_free_seg(pkt);
2381                                 ++rxq->stats.idropped;
2382                                 continue;
2383                         }
2384                         rte_memcpy(rte_pktmbuf_mtod(pkt, void *), addr, len);
2385                 } else {
2386                         rte_iova_t buf_iova;
2387                         struct rte_mbuf_ext_shared_info *shinfo;
2388                         uint16_t buf_len = strd_cnt * strd_sz;
2389
2390                         /* Increment the refcnt of the whole chunk. */
2391                         rte_atomic16_add_return(&buf->refcnt, 1);
2392                         assert((uint16_t)rte_atomic16_read(&buf->refcnt) <=
2393                                strd_n + 1);
2394                         addr = RTE_PTR_SUB(addr, RTE_PKTMBUF_HEADROOM);
2395                         /*
2396                          * MLX5 device doesn't use iova but it is necessary in a
2397                          * case where the Rx packet is transmitted via a
2398                          * different PMD.
2399                          */
2400                         buf_iova = rte_mempool_virt2iova(buf) +
2401                                    RTE_PTR_DIFF(addr, buf);
2402                         shinfo = rte_pktmbuf_ext_shinfo_init_helper(addr,
2403                                         &buf_len, mlx5_mprq_buf_free_cb, buf);
2404                         /*
2405                          * EXT_ATTACHED_MBUF will be set to pkt->ol_flags when
2406                          * attaching the stride to mbuf and more offload flags
2407                          * will be added below by calling rxq_cq_to_mbuf().
2408                          * Other fields will be overwritten.
2409                          */
2410                         rte_pktmbuf_attach_extbuf(pkt, addr, buf_iova, buf_len,
2411                                                   shinfo);
2412                         rte_pktmbuf_reset_headroom(pkt);
2413                         assert(pkt->ol_flags == EXT_ATTACHED_MBUF);
2414                         /*
2415                          * Prevent potential overflow due to MTU change through
2416                          * kernel interface.
2417                          */
2418                         if (unlikely(rte_pktmbuf_tailroom(pkt) < len)) {
2419                                 rte_pktmbuf_free_seg(pkt);
2420                                 ++rxq->stats.idropped;
2421                                 continue;
2422                         }
2423                 }
2424                 rxq_cq_to_mbuf(rxq, pkt, cqe, rss_hash_res);
2425                 PKT_LEN(pkt) = len;
2426                 DATA_LEN(pkt) = len;
2427                 PORT(pkt) = rxq->port_id;
2428 #ifdef MLX5_PMD_SOFT_COUNTERS
2429                 /* Increment bytes counter. */
2430                 rxq->stats.ibytes += PKT_LEN(pkt);
2431 #endif
2432                 /* Return packet. */
2433                 *(pkts++) = pkt;
2434                 ++i;
2435         }
2436         /* Update the consumer indexes. */
2437         rxq->consumed_strd = consumed_strd;
2438         rte_cio_wmb();
2439         *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
2440         if (rq_ci != rxq->rq_ci) {
2441                 rxq->rq_ci = rq_ci;
2442                 rte_cio_wmb();
2443                 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
2444         }
2445 #ifdef MLX5_PMD_SOFT_COUNTERS
2446         /* Increment packets counter. */
2447         rxq->stats.ipackets += i;
2448 #endif
2449         return i;
2450 }
2451
2452 /**
2453  * Dummy DPDK callback for TX.
2454  *
2455  * This function is used to temporarily replace the real callback during
2456  * unsafe control operations on the queue, or in case of error.
2457  *
2458  * @param dpdk_txq
2459  *   Generic pointer to TX queue structure.
2460  * @param[in] pkts
2461  *   Packets to transmit.
2462  * @param pkts_n
2463  *   Number of packets in array.
2464  *
2465  * @return
2466  *   Number of packets successfully transmitted (<= pkts_n).
2467  */
2468 uint16_t
2469 removed_tx_burst(void *dpdk_txq __rte_unused,
2470                  struct rte_mbuf **pkts __rte_unused,
2471                  uint16_t pkts_n __rte_unused)
2472 {
2473         rte_mb();
2474         return 0;
2475 }
2476
2477 /**
2478  * Dummy DPDK callback for RX.
2479  *
2480  * This function is used to temporarily replace the real callback during
2481  * unsafe control operations on the queue, or in case of error.
2482  *
2483  * @param dpdk_rxq
2484  *   Generic pointer to RX queue structure.
2485  * @param[out] pkts
2486  *   Array to store received packets.
2487  * @param pkts_n
2488  *   Maximum number of packets in array.
2489  *
2490  * @return
2491  *   Number of packets successfully received (<= pkts_n).
2492  */
2493 uint16_t
2494 removed_rx_burst(void *dpdk_txq __rte_unused,
2495                  struct rte_mbuf **pkts __rte_unused,
2496                  uint16_t pkts_n __rte_unused)
2497 {
2498         rte_mb();
2499         return 0;
2500 }
2501
2502 /*
2503  * Vectorized Rx/Tx routines are not compiled in when required vector
2504  * instructions are not supported on a target architecture. The following null
2505  * stubs are needed for linkage when those are not included outside of this file
2506  * (e.g.  mlx5_rxtx_vec_sse.c for x86).
2507  */
2508
2509 __rte_weak uint16_t
2510 mlx5_tx_burst_raw_vec(void *dpdk_txq __rte_unused,
2511                       struct rte_mbuf **pkts __rte_unused,
2512                       uint16_t pkts_n __rte_unused)
2513 {
2514         return 0;
2515 }
2516
2517 __rte_weak uint16_t
2518 mlx5_tx_burst_vec(void *dpdk_txq __rte_unused,
2519                   struct rte_mbuf **pkts __rte_unused,
2520                   uint16_t pkts_n __rte_unused)
2521 {
2522         return 0;
2523 }
2524
2525 __rte_weak uint16_t
2526 mlx5_rx_burst_vec(void *dpdk_txq __rte_unused,
2527                   struct rte_mbuf **pkts __rte_unused,
2528                   uint16_t pkts_n __rte_unused)
2529 {
2530         return 0;
2531 }
2532
2533 __rte_weak int
2534 mlx5_check_raw_vec_tx_support(struct rte_eth_dev *dev __rte_unused)
2535 {
2536         return -ENOTSUP;
2537 }
2538
2539 __rte_weak int
2540 mlx5_check_vec_tx_support(struct rte_eth_dev *dev __rte_unused)
2541 {
2542         return -ENOTSUP;
2543 }
2544
2545 __rte_weak int
2546 mlx5_rxq_check_vec_support(struct mlx5_rxq_data *rxq __rte_unused)
2547 {
2548         return -ENOTSUP;
2549 }
2550
2551 __rte_weak int
2552 mlx5_check_vec_rx_support(struct rte_eth_dev *dev __rte_unused)
2553 {
2554         return -ENOTSUP;
2555 }