1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_RXTX_H_
7 #define RTE_PMD_MLX5_RXTX_H_
11 #include <sys/queue.h>
14 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
16 #pragma GCC diagnostic ignored "-Wpedantic"
18 #include <infiniband/verbs.h>
19 #include <infiniband/mlx5dv.h>
21 #pragma GCC diagnostic error "-Wpedantic"
25 #include <rte_mempool.h>
26 #include <rte_common.h>
27 #include <rte_hexdump.h>
28 #include <rte_atomic.h>
29 #include <rte_spinlock.h>
31 #include <rte_bus_pci.h>
33 #include "mlx5_utils.h"
36 #include "mlx5_autoconf.h"
37 #include "mlx5_defs.h"
40 /* Support tunnel matching. */
41 #define MLX5_FLOW_TUNNEL 5
43 struct mlx5_rxq_stats {
44 unsigned int idx; /**< Mapping index. */
45 #ifdef MLX5_PMD_SOFT_COUNTERS
46 uint64_t ipackets; /**< Total of successfully received packets. */
47 uint64_t ibytes; /**< Total of successfully received bytes. */
49 uint64_t idropped; /**< Total of packets dropped when RX ring full. */
50 uint64_t rx_nombuf; /**< Total of RX mbuf allocation failures. */
53 struct mlx5_txq_stats {
54 unsigned int idx; /**< Mapping index. */
55 #ifdef MLX5_PMD_SOFT_COUNTERS
56 uint64_t opackets; /**< Total of successfully sent packets. */
57 uint64_t obytes; /**< Total of successfully sent bytes. */
59 uint64_t oerrors; /**< Total number of failed transmitted packets. */
64 /* Compressed CQE context. */
66 uint16_t ai; /* Array index. */
67 uint16_t ca; /* Current array index. */
68 uint16_t na; /* Next array index. */
69 uint16_t cq_ci; /* The next CQE. */
70 uint32_t cqe_cnt; /* Number of CQEs. */
73 /* Multi-Packet RQ buffer header. */
74 struct mlx5_mprq_buf {
75 struct rte_mempool *mp;
76 rte_atomic16_t refcnt; /* Atomically accessed refcnt. */
77 uint8_t pad[RTE_PKTMBUF_HEADROOM]; /* Headroom for the first packet. */
78 } __rte_cache_aligned;
80 /* Get pointer to the first stride. */
81 #define mlx5_mprq_buf_addr(ptr) ((ptr) + 1)
83 /* RX queue descriptor. */
84 struct mlx5_rxq_data {
85 unsigned int csum:1; /* Enable checksum offloading. */
86 unsigned int hw_timestamp:1; /* Enable HW timestamp. */
87 unsigned int vlan_strip:1; /* Enable VLAN stripping. */
88 unsigned int crc_present:1; /* CRC must be subtracted. */
89 unsigned int sges_n:2; /* Log 2 of SGEs (max buffers per packet). */
90 unsigned int cqe_n:4; /* Log 2 of CQ elements. */
91 unsigned int elts_n:4; /* Log 2 of Mbufs. */
92 unsigned int rss_hash:1; /* RSS hash result is enabled. */
93 unsigned int mark:1; /* Marked flow available on the queue. */
94 unsigned int strd_num_n:5; /* Log 2 of the number of stride. */
95 unsigned int strd_sz_n:4; /* Log 2 of stride size. */
96 unsigned int strd_shift_en:1; /* Enable 2bytes shift on a stride. */
97 unsigned int :6; /* Remaining bits. */
98 volatile uint32_t *rq_db;
99 volatile uint32_t *cq_db;
102 uint16_t consumed_strd; /* Number of consumed strides in WQE. */
105 uint16_t rq_repl_thresh; /* Threshold for buffer replenishment. */
106 struct mlx5_mr_ctrl mr_ctrl; /* MR control descriptor. */
107 uint16_t mprq_max_memcpy_len; /* Maximum size of packet to memcpy. */
109 volatile struct mlx5_cqe(*cqes)[];
110 struct rxq_zip zip; /* Compressed context. */
113 struct rte_mbuf *(*elts)[];
114 struct mlx5_mprq_buf *(*mprq_bufs)[];
116 struct rte_mempool *mp;
117 struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */
118 struct mlx5_mprq_buf *mprq_repl; /* Stashed mbuf for replenish. */
119 struct mlx5_rxq_stats stats;
120 uint64_t mbuf_initializer; /* Default rearm_data for vectorized Rx. */
121 struct rte_mbuf fake_mbuf; /* elts padding for vectorized Rx. */
122 void *cq_uar; /* CQ user access region. */
123 uint32_t cqn; /* CQ number. */
124 uint8_t cq_arm_sn; /* CQ arm seq number. */
126 rte_spinlock_t *uar_lock_cq;
127 /* CQ (UAR) access lock required for 32bit implementations */
129 uint32_t tunnel; /* Tunnel information. */
130 } __rte_cache_aligned;
132 /* Verbs Rx queue elements. */
133 struct mlx5_rxq_ibv {
134 LIST_ENTRY(mlx5_rxq_ibv) next; /* Pointer to the next element. */
135 rte_atomic32_t refcnt; /* Reference counter. */
136 struct mlx5_rxq_ctrl *rxq_ctrl; /* Back pointer to parent. */
137 struct ibv_cq *cq; /* Completion Queue. */
138 struct ibv_wq *wq; /* Work Queue. */
139 struct ibv_comp_channel *channel;
142 /* RX queue control descriptor. */
143 struct mlx5_rxq_ctrl {
144 LIST_ENTRY(mlx5_rxq_ctrl) next; /* Pointer to the next element. */
145 rte_atomic32_t refcnt; /* Reference counter. */
146 struct mlx5_rxq_ibv *ibv; /* Verbs elements. */
147 struct mlx5_priv *priv; /* Back pointer to private data. */
148 struct mlx5_rxq_data rxq; /* Data path structure. */
149 unsigned int socket; /* CPU socket ID for allocations. */
150 unsigned int irq:1; /* Whether IRQ is enabled. */
151 uint16_t idx; /* Queue index. */
152 uint32_t flow_mark_n; /* Number of Mark/Flag flows using this Queue. */
153 uint32_t flow_tunnels_n[MLX5_FLOW_TUNNEL]; /* Tunnels counters. */
156 /* Indirection table. */
157 struct mlx5_ind_table_ibv {
158 LIST_ENTRY(mlx5_ind_table_ibv) next; /* Pointer to the next element. */
159 rte_atomic32_t refcnt; /* Reference counter. */
160 struct ibv_rwq_ind_table *ind_table; /**< Indirection table. */
161 uint32_t queues_n; /**< Number of queues in the list. */
162 uint16_t queues[]; /**< Queue list. */
167 LIST_ENTRY(mlx5_hrxq) next; /* Pointer to the next element. */
168 rte_atomic32_t refcnt; /* Reference counter. */
169 struct mlx5_ind_table_ibv *ind_table; /* Indirection table. */
170 struct ibv_qp *qp; /* Verbs queue pair. */
171 uint64_t hash_fields; /* Verbs Hash fields. */
172 uint32_t rss_key_len; /* Hash key length in bytes. */
173 uint8_t rss_key[]; /* Hash key. */
176 /* TX queue descriptor. */
178 struct mlx5_txq_data {
179 uint16_t elts_head; /* Current counter in (*elts)[]. */
180 uint16_t elts_tail; /* Counter of first element awaiting completion. */
181 uint16_t elts_comp; /* Counter since last completion request. */
182 uint16_t mpw_comp; /* WQ index since last completion request. */
183 uint16_t cq_ci; /* Consumer index for completion queue. */
185 uint16_t cq_pi; /* Producer index for completion queue. */
187 uint16_t wqe_ci; /* Consumer index for work queue. */
188 uint16_t wqe_pi; /* Producer index for work queue. */
189 uint16_t elts_n:4; /* (*elts)[] length (in log2). */
190 uint16_t cqe_n:4; /* Number of CQ elements (in log2). */
191 uint16_t wqe_n:4; /* Number of of WQ elements (in log2). */
192 uint16_t tso_en:1; /* When set hardware TSO is enabled. */
193 uint16_t tunnel_en:1;
194 /* When set TX offload for tunneled packets are supported. */
195 uint16_t swp_en:1; /* Whether SW parser is enabled. */
196 uint16_t mpw_hdr_dseg:1; /* Enable DSEGs in the title WQEBB. */
197 uint16_t max_inline; /* Multiple of RTE_CACHE_LINE_SIZE to inline. */
198 uint16_t inline_max_packet_sz; /* Max packet size for inlining. */
199 uint32_t qp_num_8s; /* QP number shifted by 8. */
200 uint64_t offloads; /* Offloads for Tx Queue. */
201 struct mlx5_mr_ctrl mr_ctrl; /* MR control descriptor. */
202 volatile struct mlx5_cqe (*cqes)[]; /* Completion queue. */
203 volatile void *wqes; /* Work queue (use volatile to write into). */
204 volatile uint32_t *qp_db; /* Work queue doorbell. */
205 volatile uint32_t *cq_db; /* Completion queue doorbell. */
206 volatile void *bf_reg; /* Blueflame register remapped. */
207 struct rte_mbuf *(*elts)[]; /* TX elements. */
208 struct mlx5_txq_stats stats; /* TX queue counters. */
210 rte_spinlock_t *uar_lock;
211 /* UAR access lock required for 32bit implementations */
213 } __rte_cache_aligned;
215 /* Verbs Rx queue elements. */
216 struct mlx5_txq_ibv {
217 LIST_ENTRY(mlx5_txq_ibv) next; /* Pointer to the next element. */
218 rte_atomic32_t refcnt; /* Reference counter. */
219 struct mlx5_txq_ctrl *txq_ctrl; /* Pointer to the control queue. */
220 struct ibv_cq *cq; /* Completion Queue. */
221 struct ibv_qp *qp; /* Queue Pair. */
224 /* TX queue control descriptor. */
225 struct mlx5_txq_ctrl {
226 LIST_ENTRY(mlx5_txq_ctrl) next; /* Pointer to the next element. */
227 rte_atomic32_t refcnt; /* Reference counter. */
228 unsigned int socket; /* CPU socket ID for allocations. */
229 unsigned int max_inline_data; /* Max inline data. */
230 unsigned int max_tso_header; /* Max TSO header size. */
231 struct mlx5_txq_ibv *ibv; /* Verbs queue object. */
232 struct mlx5_priv *priv; /* Back pointer to private data. */
233 struct mlx5_txq_data txq; /* Data path structure. */
234 off_t uar_mmap_offset; /* UAR mmap offset for non-primary process. */
235 volatile void *bf_reg_orig; /* Blueflame register from verbs. */
236 uint16_t idx; /* Queue index. */
241 extern uint8_t rss_hash_default_key[];
243 int mlx5_check_mprq_support(struct rte_eth_dev *dev);
244 int mlx5_rxq_mprq_enabled(struct mlx5_rxq_data *rxq);
245 int mlx5_mprq_enabled(struct rte_eth_dev *dev);
246 int mlx5_mprq_free_mp(struct rte_eth_dev *dev);
247 int mlx5_mprq_alloc_mp(struct rte_eth_dev *dev);
248 void mlx5_rxq_cleanup(struct mlx5_rxq_ctrl *rxq_ctrl);
249 int mlx5_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
250 unsigned int socket, const struct rte_eth_rxconf *conf,
251 struct rte_mempool *mp);
252 void mlx5_rx_queue_release(void *dpdk_rxq);
253 int mlx5_rx_intr_vec_enable(struct rte_eth_dev *dev);
254 void mlx5_rx_intr_vec_disable(struct rte_eth_dev *dev);
255 int mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id);
256 int mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id);
257 struct mlx5_rxq_ibv *mlx5_rxq_ibv_new(struct rte_eth_dev *dev, uint16_t idx);
258 struct mlx5_rxq_ibv *mlx5_rxq_ibv_get(struct rte_eth_dev *dev, uint16_t idx);
259 int mlx5_rxq_ibv_release(struct mlx5_rxq_ibv *rxq_ibv);
260 int mlx5_rxq_ibv_releasable(struct mlx5_rxq_ibv *rxq_ibv);
261 struct mlx5_rxq_ibv *mlx5_rxq_ibv_drop_new(struct rte_eth_dev *dev);
262 void mlx5_rxq_ibv_drop_release(struct rte_eth_dev *dev);
263 int mlx5_rxq_ibv_verify(struct rte_eth_dev *dev);
264 struct mlx5_rxq_ctrl *mlx5_rxq_new(struct rte_eth_dev *dev, uint16_t idx,
265 uint16_t desc, unsigned int socket,
266 const struct rte_eth_rxconf *conf,
267 struct rte_mempool *mp);
268 struct mlx5_rxq_ctrl *mlx5_rxq_get(struct rte_eth_dev *dev, uint16_t idx);
269 int mlx5_rxq_release(struct rte_eth_dev *dev, uint16_t idx);
270 int mlx5_rxq_releasable(struct rte_eth_dev *dev, uint16_t idx);
271 int mlx5_rxq_verify(struct rte_eth_dev *dev);
272 int rxq_alloc_elts(struct mlx5_rxq_ctrl *rxq_ctrl);
273 int rxq_alloc_mprq_buf(struct mlx5_rxq_ctrl *rxq_ctrl);
274 struct mlx5_ind_table_ibv *mlx5_ind_table_ibv_new(struct rte_eth_dev *dev,
275 const uint16_t *queues,
277 struct mlx5_ind_table_ibv *mlx5_ind_table_ibv_get(struct rte_eth_dev *dev,
278 const uint16_t *queues,
280 int mlx5_ind_table_ibv_release(struct rte_eth_dev *dev,
281 struct mlx5_ind_table_ibv *ind_tbl);
282 int mlx5_ind_table_ibv_verify(struct rte_eth_dev *dev);
283 struct mlx5_ind_table_ibv *mlx5_ind_table_ibv_drop_new(struct rte_eth_dev *dev);
284 void mlx5_ind_table_ibv_drop_release(struct rte_eth_dev *dev);
285 struct mlx5_hrxq *mlx5_hrxq_new(struct rte_eth_dev *dev,
286 const uint8_t *rss_key, uint32_t rss_key_len,
287 uint64_t hash_fields,
288 const uint16_t *queues, uint32_t queues_n,
289 int tunnel __rte_unused);
290 struct mlx5_hrxq *mlx5_hrxq_get(struct rte_eth_dev *dev,
291 const uint8_t *rss_key, uint32_t rss_key_len,
292 uint64_t hash_fields,
293 const uint16_t *queues, uint32_t queues_n);
294 int mlx5_hrxq_release(struct rte_eth_dev *dev, struct mlx5_hrxq *hxrq);
295 int mlx5_hrxq_ibv_verify(struct rte_eth_dev *dev);
296 struct mlx5_hrxq *mlx5_hrxq_drop_new(struct rte_eth_dev *dev);
297 void mlx5_hrxq_drop_release(struct rte_eth_dev *dev);
298 uint64_t mlx5_get_rx_port_offloads(void);
299 uint64_t mlx5_get_rx_queue_offloads(struct rte_eth_dev *dev);
303 int mlx5_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
304 unsigned int socket, const struct rte_eth_txconf *conf);
305 void mlx5_tx_queue_release(void *dpdk_txq);
306 int mlx5_tx_uar_remap(struct rte_eth_dev *dev, int fd);
307 struct mlx5_txq_ibv *mlx5_txq_ibv_new(struct rte_eth_dev *dev, uint16_t idx);
308 struct mlx5_txq_ibv *mlx5_txq_ibv_get(struct rte_eth_dev *dev, uint16_t idx);
309 int mlx5_txq_ibv_release(struct mlx5_txq_ibv *txq_ibv);
310 int mlx5_txq_ibv_releasable(struct mlx5_txq_ibv *txq_ibv);
311 int mlx5_txq_ibv_verify(struct rte_eth_dev *dev);
312 struct mlx5_txq_ctrl *mlx5_txq_new(struct rte_eth_dev *dev, uint16_t idx,
313 uint16_t desc, unsigned int socket,
314 const struct rte_eth_txconf *conf);
315 struct mlx5_txq_ctrl *mlx5_txq_get(struct rte_eth_dev *dev, uint16_t idx);
316 int mlx5_txq_release(struct rte_eth_dev *dev, uint16_t idx);
317 int mlx5_txq_releasable(struct rte_eth_dev *dev, uint16_t idx);
318 int mlx5_txq_verify(struct rte_eth_dev *dev);
319 void txq_alloc_elts(struct mlx5_txq_ctrl *txq_ctrl);
320 uint64_t mlx5_get_tx_port_offloads(struct rte_eth_dev *dev);
324 extern uint32_t mlx5_ptype_table[];
325 extern uint8_t mlx5_cksum_table[];
326 extern uint8_t mlx5_swp_types_table[];
328 void mlx5_set_ptype_table(void);
329 void mlx5_set_cksum_table(void);
330 void mlx5_set_swp_types_table(void);
331 uint16_t mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts,
333 uint16_t mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts,
335 uint16_t mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
337 uint16_t mlx5_tx_burst_empw(void *dpdk_txq, struct rte_mbuf **pkts,
339 uint16_t mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n);
340 void mlx5_mprq_buf_free_cb(void *addr, void *opaque);
341 void mlx5_mprq_buf_free(struct mlx5_mprq_buf *buf);
342 uint16_t mlx5_rx_burst_mprq(void *dpdk_rxq, struct rte_mbuf **pkts,
344 uint16_t removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts,
346 uint16_t removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts,
348 int mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset);
349 int mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset);
350 uint32_t mlx5_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id);
352 /* Vectorized version of mlx5_rxtx.c */
353 int mlx5_check_raw_vec_tx_support(struct rte_eth_dev *dev);
354 int mlx5_check_vec_tx_support(struct rte_eth_dev *dev);
355 int mlx5_rxq_check_vec_support(struct mlx5_rxq_data *rxq_data);
356 int mlx5_check_vec_rx_support(struct rte_eth_dev *dev);
357 uint16_t mlx5_tx_burst_raw_vec(void *dpdk_txq, struct rte_mbuf **pkts,
359 uint16_t mlx5_tx_burst_vec(void *dpdk_txq, struct rte_mbuf **pkts,
361 uint16_t mlx5_rx_burst_vec(void *dpdk_txq, struct rte_mbuf **pkts,
366 void mlx5_mr_flush_local_cache(struct mlx5_mr_ctrl *mr_ctrl);
367 uint32_t mlx5_rx_addr2mr_bh(struct mlx5_rxq_data *rxq, uintptr_t addr);
368 uint32_t mlx5_tx_mb2mr_bh(struct mlx5_txq_data *txq, struct rte_mbuf *mb);
369 uint32_t mlx5_tx_update_ext_mp(struct mlx5_txq_data *txq, uintptr_t addr,
370 struct rte_mempool *mp);
371 int mlx5_dma_map(struct rte_pci_device *pdev, void *addr, uint64_t iova,
373 int mlx5_dma_unmap(struct rte_pci_device *pdev, void *addr, uint64_t iova,
377 * Provide safe 64bit store operation to mlx5 UAR region for both 32bit and
378 * 64bit architectures.
381 * value to write in CPU endian format.
383 * Address to write to.
385 * Address of the lock to use for that UAR access.
387 static __rte_always_inline void
388 __mlx5_uar_write64_relaxed(uint64_t val, void *addr,
389 rte_spinlock_t *lock __rte_unused)
392 *(uint64_t *)addr = val;
393 #else /* !RTE_ARCH_64 */
394 rte_spinlock_lock(lock);
395 *(uint32_t *)addr = val;
397 *((uint32_t *)addr + 1) = val >> 32;
398 rte_spinlock_unlock(lock);
403 * Provide safe 64bit store operation to mlx5 UAR region for both 32bit and
404 * 64bit architectures while guaranteeing the order of execution with the
405 * code being executed.
408 * value to write in CPU endian format.
410 * Address to write to.
412 * Address of the lock to use for that UAR access.
414 static __rte_always_inline void
415 __mlx5_uar_write64(uint64_t val, void *addr, rte_spinlock_t *lock)
418 __mlx5_uar_write64_relaxed(val, addr, lock);
421 /* Assist macros, used instead of directly calling the functions they wrap. */
423 #define mlx5_uar_write64_relaxed(val, dst, lock) \
424 __mlx5_uar_write64_relaxed(val, dst, NULL)
425 #define mlx5_uar_write64(val, dst, lock) __mlx5_uar_write64(val, dst, NULL)
427 #define mlx5_uar_write64_relaxed(val, dst, lock) \
428 __mlx5_uar_write64_relaxed(val, dst, lock)
429 #define mlx5_uar_write64(val, dst, lock) __mlx5_uar_write64(val, dst, lock)
434 * Verify or set magic value in CQE.
443 check_cqe_seen(volatile struct mlx5_cqe *cqe)
445 static const uint8_t magic[] = "seen";
446 volatile uint8_t (*buf)[sizeof(cqe->rsvd1)] = &cqe->rsvd1;
450 for (i = 0; i < sizeof(magic) && i < sizeof(*buf); ++i)
451 if (!ret || (*buf)[i] != magic[i]) {
453 (*buf)[i] = magic[i];
460 * Check whether CQE is valid.
465 * Size of completion queue.
470 * 0 on success, 1 on failure.
472 static __rte_always_inline int
473 check_cqe(volatile struct mlx5_cqe *cqe,
474 unsigned int cqes_n, const uint16_t ci)
476 uint16_t idx = ci & cqes_n;
477 uint8_t op_own = cqe->op_own;
478 uint8_t op_owner = MLX5_CQE_OWNER(op_own);
479 uint8_t op_code = MLX5_CQE_OPCODE(op_own);
481 if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID)))
482 return 1; /* No CQE. */
484 if ((op_code == MLX5_CQE_RESP_ERR) ||
485 (op_code == MLX5_CQE_REQ_ERR)) {
486 volatile struct mlx5_err_cqe *err_cqe = (volatile void *)cqe;
487 uint8_t syndrome = err_cqe->syndrome;
489 if ((syndrome == MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR) ||
490 (syndrome == MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR))
492 if (!check_cqe_seen(cqe)) {
494 "unexpected CQE error %u (0x%02x) syndrome"
496 op_code, op_code, syndrome);
497 rte_hexdump(stderr, "MLX5 Error CQE:",
498 (const void *)((uintptr_t)err_cqe),
502 } else if ((op_code != MLX5_CQE_RESP_SEND) &&
503 (op_code != MLX5_CQE_REQ)) {
504 if (!check_cqe_seen(cqe)) {
505 DRV_LOG(ERR, "unexpected CQE opcode %u (0x%02x)",
507 rte_hexdump(stderr, "MLX5 CQE:",
508 (const void *)((uintptr_t)cqe),
518 * Return the address of the WQE.
521 * Pointer to TX queue structure.
523 * WQE consumer index.
528 static inline uintptr_t *
529 tx_mlx5_wqe(struct mlx5_txq_data *txq, uint16_t ci)
531 ci &= ((1 << txq->wqe_n) - 1);
532 return (uintptr_t *)((uintptr_t)txq->wqes + ci * MLX5_WQE_SIZE);
536 * Manage TX completions.
538 * When sending a burst, mlx5_tx_burst() posts several WRs.
541 * Pointer to TX queue structure.
543 static __rte_always_inline void
544 mlx5_tx_complete(struct mlx5_txq_data *txq)
546 const uint16_t elts_n = 1 << txq->elts_n;
547 const uint16_t elts_m = elts_n - 1;
548 const unsigned int cqe_n = 1 << txq->cqe_n;
549 const unsigned int cqe_cnt = cqe_n - 1;
550 uint16_t elts_free = txq->elts_tail;
552 uint16_t cq_ci = txq->cq_ci;
553 volatile struct mlx5_cqe *cqe = NULL;
554 volatile struct mlx5_wqe_ctrl *ctrl;
555 struct rte_mbuf *m, *free[elts_n];
556 struct rte_mempool *pool = NULL;
557 unsigned int blk_n = 0;
559 cqe = &(*txq->cqes)[cq_ci & cqe_cnt];
560 if (unlikely(check_cqe(cqe, cqe_n, cq_ci)))
563 if ((MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_RESP_ERR) ||
564 (MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_REQ_ERR)) {
565 if (!check_cqe_seen(cqe)) {
566 DRV_LOG(ERR, "unexpected error CQE, Tx stopped");
567 rte_hexdump(stderr, "MLX5 TXQ:",
568 (const void *)((uintptr_t)txq->wqes),
577 txq->wqe_pi = rte_be_to_cpu_16(cqe->wqe_counter);
578 ctrl = (volatile struct mlx5_wqe_ctrl *)
579 tx_mlx5_wqe(txq, txq->wqe_pi);
580 elts_tail = ctrl->ctrl3;
581 assert((elts_tail & elts_m) < (1 << txq->wqe_n));
583 while (elts_free != elts_tail) {
584 m = rte_pktmbuf_prefree_seg((*txq->elts)[elts_free++ & elts_m]);
585 if (likely(m != NULL)) {
586 if (likely(m->pool == pool)) {
589 if (likely(pool != NULL))
590 rte_mempool_put_bulk(pool,
600 rte_mempool_put_bulk(pool, (void *)free, blk_n);
602 elts_free = txq->elts_tail;
604 while (elts_free != elts_tail) {
605 memset(&(*txq->elts)[elts_free & elts_m],
607 sizeof((*txq->elts)[elts_free & elts_m]));
612 txq->elts_tail = elts_tail;
613 /* Update the consumer index. */
614 rte_compiler_barrier();
615 *txq->cq_db = rte_cpu_to_be_32(cq_ci);
619 * Get Memory Pool (MP) from mbuf. If mbuf is indirect, the pool from which the
620 * cloned mbuf is allocated is returned instead.
626 * Memory pool where data is located for given mbuf.
628 static inline struct rte_mempool *
629 mlx5_mb2mp(struct rte_mbuf *buf)
631 if (unlikely(RTE_MBUF_CLONED(buf)))
632 return rte_mbuf_from_indirect(buf)->pool;
637 * Query LKey from a packet buffer for Rx. No need to flush local caches for Rx
638 * as mempool is pre-configured and static.
641 * Pointer to Rx queue structure.
646 * Searched LKey on success, UINT32_MAX on no match.
648 static __rte_always_inline uint32_t
649 mlx5_rx_addr2mr(struct mlx5_rxq_data *rxq, uintptr_t addr)
651 struct mlx5_mr_ctrl *mr_ctrl = &rxq->mr_ctrl;
654 /* Linear search on MR cache array. */
655 lkey = mlx5_mr_lookup_cache(mr_ctrl->cache, &mr_ctrl->mru,
656 MLX5_MR_CACHE_N, addr);
657 if (likely(lkey != UINT32_MAX))
659 /* Take slower bottom-half (Binary Search) on miss. */
660 return mlx5_rx_addr2mr_bh(rxq, addr);
663 #define mlx5_rx_mb2mr(rxq, mb) mlx5_rx_addr2mr(rxq, (uintptr_t)((mb)->buf_addr))
666 * Query LKey from a packet buffer for Tx. If not found, add the mempool.
669 * Pointer to Tx queue structure.
674 * Searched LKey on success, UINT32_MAX on no match.
676 static __rte_always_inline uint32_t
677 mlx5_tx_mb2mr(struct mlx5_txq_data *txq, struct rte_mbuf *mb)
679 struct mlx5_mr_ctrl *mr_ctrl = &txq->mr_ctrl;
680 uintptr_t addr = (uintptr_t)mb->buf_addr;
683 /* Check generation bit to see if there's any change on existing MRs. */
684 if (unlikely(*mr_ctrl->dev_gen_ptr != mr_ctrl->cur_gen))
685 mlx5_mr_flush_local_cache(mr_ctrl);
686 /* Linear search on MR cache array. */
687 lkey = mlx5_mr_lookup_cache(mr_ctrl->cache, &mr_ctrl->mru,
688 MLX5_MR_CACHE_N, addr);
689 if (likely(lkey != UINT32_MAX))
691 /* Take slower bottom-half on miss. */
692 return mlx5_tx_mb2mr_bh(txq, mb);
696 * Ring TX queue doorbell and flush the update if requested.
699 * Pointer to TX queue structure.
701 * Pointer to the last WQE posted in the NIC.
703 * Request for write memory barrier after BlueFlame update.
705 static __rte_always_inline void
706 mlx5_tx_dbrec_cond_wmb(struct mlx5_txq_data *txq, volatile struct mlx5_wqe *wqe,
709 uint64_t *dst = (uint64_t *)((uintptr_t)txq->bf_reg);
710 volatile uint64_t *src = ((volatile uint64_t *)wqe);
713 *txq->qp_db = rte_cpu_to_be_32(txq->wqe_ci);
714 /* Ensure ordering between DB record and BF copy. */
716 mlx5_uar_write64_relaxed(*src, dst, txq->uar_lock);
722 * Ring TX queue doorbell and flush the update by write memory barrier.
725 * Pointer to TX queue structure.
727 * Pointer to the last WQE posted in the NIC.
729 static __rte_always_inline void
730 mlx5_tx_dbrec(struct mlx5_txq_data *txq, volatile struct mlx5_wqe *wqe)
732 mlx5_tx_dbrec_cond_wmb(txq, wqe, 1);
736 * Convert mbuf to Verb SWP.
739 * Pointer to the Tx queue.
741 * Pointer to the mbuf.
743 * Pointer to the SWP header offsets.
745 * Pointer to the SWP header types.
747 static __rte_always_inline void
748 txq_mbuf_to_swp(struct mlx5_txq_data *txq, struct rte_mbuf *buf,
749 uint8_t *offsets, uint8_t *swp_types)
751 const uint64_t vlan = buf->ol_flags & PKT_TX_VLAN_PKT;
752 const uint64_t tunnel = buf->ol_flags & PKT_TX_TUNNEL_MASK;
753 const uint64_t tso = buf->ol_flags & PKT_TX_TCP_SEG;
754 const uint64_t csum_flags = buf->ol_flags & PKT_TX_L4_MASK;
755 const uint64_t inner_ip =
756 buf->ol_flags & (PKT_TX_IPV4 | PKT_TX_IPV6);
757 const uint64_t ol_flags_mask = PKT_TX_L4_MASK | PKT_TX_IPV6 |
762 if (likely(!txq->swp_en || (tunnel != PKT_TX_TUNNEL_UDP &&
763 tunnel != PKT_TX_TUNNEL_IP)))
766 * The index should have:
767 * bit[0:1] = PKT_TX_L4_MASK
768 * bit[4] = PKT_TX_IPV6
769 * bit[8] = PKT_TX_OUTER_IPV6
770 * bit[9] = PKT_TX_OUTER_UDP
772 idx = (buf->ol_flags & ol_flags_mask) >> 52;
773 if (tunnel == PKT_TX_TUNNEL_UDP)
775 *swp_types = mlx5_swp_types_table[idx];
777 * Set offsets for SW parser. Since ConnectX-5, SW parser just
778 * complements HW parser. SW parser starts to engage only if HW parser
779 * can't reach a header. For the older devices, HW parser will not kick
780 * in if any of SWP offsets is set. Therefore, all of the L3 offsets
781 * should be set regardless of HW offload.
783 off = buf->outer_l2_len + (vlan ? sizeof(struct vlan_hdr) : 0);
784 offsets[1] = off >> 1; /* Outer L3 offset. */
785 off += buf->outer_l3_len;
786 if (tunnel == PKT_TX_TUNNEL_UDP)
787 offsets[0] = off >> 1; /* Outer L4 offset. */
790 offsets[3] = off >> 1; /* Inner L3 offset. */
791 if (csum_flags == PKT_TX_TCP_CKSUM || tso ||
792 csum_flags == PKT_TX_UDP_CKSUM) {
794 offsets[2] = off >> 1; /* Inner L4 offset. */
800 * Convert the Checksum offloads to Verbs.
803 * Pointer to the mbuf.
806 * Converted checksum flags.
808 static __rte_always_inline uint8_t
809 txq_ol_cksum_to_cs(struct rte_mbuf *buf)
812 uint8_t is_tunnel = !!(buf->ol_flags & PKT_TX_TUNNEL_MASK);
813 const uint64_t ol_flags_mask = PKT_TX_TCP_SEG | PKT_TX_L4_MASK |
814 PKT_TX_IP_CKSUM | PKT_TX_OUTER_IP_CKSUM;
817 * The index should have:
818 * bit[0] = PKT_TX_TCP_SEG
819 * bit[2:3] = PKT_TX_UDP_CKSUM, PKT_TX_TCP_CKSUM
820 * bit[4] = PKT_TX_IP_CKSUM
821 * bit[8] = PKT_TX_OUTER_IP_CKSUM
824 idx = ((buf->ol_flags & ol_flags_mask) >> 50) | (!!is_tunnel << 9);
825 return mlx5_cksum_table[idx];
829 * Count the number of contiguous single segment packets.
832 * Pointer to array of packets.
837 * Number of contiguous single segment packets.
839 static __rte_always_inline unsigned int
840 txq_count_contig_single_seg(struct rte_mbuf **pkts, uint16_t pkts_n)
846 /* Count the number of contiguous single segment packets. */
847 for (pos = 0; pos < pkts_n; ++pos)
848 if (NB_SEGS(pkts[pos]) > 1)
854 * Count the number of contiguous multi-segment packets.
857 * Pointer to array of packets.
862 * Number of contiguous multi-segment packets.
864 static __rte_always_inline unsigned int
865 txq_count_contig_multi_seg(struct rte_mbuf **pkts, uint16_t pkts_n)
871 /* Count the number of contiguous multi-segment packets. */
872 for (pos = 0; pos < pkts_n; ++pos)
873 if (NB_SEGS(pkts[pos]) == 1)
878 #endif /* RTE_PMD_MLX5_RXTX_H_ */