1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_RXTX_H_
7 #define RTE_PMD_MLX5_RXTX_H_
11 #include <sys/queue.h>
14 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
16 #pragma GCC diagnostic ignored "-Wpedantic"
18 #include <infiniband/verbs.h>
19 #include <infiniband/mlx5dv.h>
21 #pragma GCC diagnostic error "-Wpedantic"
25 #include <rte_mempool.h>
26 #include <rte_common.h>
27 #include <rte_hexdump.h>
28 #include <rte_atomic.h>
29 #include <rte_spinlock.h>
31 #include <rte_bus_pci.h>
32 #include <rte_malloc.h>
34 #include <mlx5_glue.h>
36 #include <mlx5_common.h>
38 #include "mlx5_defs.h"
39 #include "mlx5_utils.h"
42 #include "mlx5_autoconf.h"
44 /* Support tunnel matching. */
45 #define MLX5_FLOW_TUNNEL 10
47 struct mlx5_rxq_stats {
48 #ifdef MLX5_PMD_SOFT_COUNTERS
49 uint64_t ipackets; /**< Total of successfully received packets. */
50 uint64_t ibytes; /**< Total of successfully received bytes. */
52 uint64_t idropped; /**< Total of packets dropped when RX ring full. */
53 uint64_t rx_nombuf; /**< Total of RX mbuf allocation failures. */
56 struct mlx5_txq_stats {
57 #ifdef MLX5_PMD_SOFT_COUNTERS
58 uint64_t opackets; /**< Total of successfully sent packets. */
59 uint64_t obytes; /**< Total of successfully sent bytes. */
61 uint64_t oerrors; /**< Total number of failed transmitted packets. */
66 /* Compressed CQE context. */
68 uint16_t ai; /* Array index. */
69 uint16_t ca; /* Current array index. */
70 uint16_t na; /* Next array index. */
71 uint16_t cq_ci; /* The next CQE. */
72 uint32_t cqe_cnt; /* Number of CQEs. */
75 /* Multi-Packet RQ buffer header. */
76 struct mlx5_mprq_buf {
77 struct rte_mempool *mp;
78 rte_atomic16_t refcnt; /* Atomically accessed refcnt. */
79 uint8_t pad[RTE_PKTMBUF_HEADROOM]; /* Headroom for the first packet. */
80 struct rte_mbuf_ext_shared_info shinfos[];
82 * Shared information per stride.
83 * More memory will be allocated for the first stride head-room and for
86 } __rte_cache_aligned;
88 /* Get pointer to the first stride. */
89 #define mlx5_mprq_buf_addr(ptr, strd_n) (RTE_PTR_ADD((ptr), \
90 sizeof(struct mlx5_mprq_buf) + \
92 sizeof(struct rte_mbuf_ext_shared_info) + \
93 RTE_PKTMBUF_HEADROOM))
95 #define MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES 6
96 #define MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES 9
98 enum mlx5_rxq_err_state {
99 MLX5_RXQ_ERR_STATE_NO_ERROR = 0,
100 MLX5_RXQ_ERR_STATE_NEED_RESET,
101 MLX5_RXQ_ERR_STATE_NEED_READY,
104 /* RX queue descriptor. */
105 struct mlx5_rxq_data {
106 unsigned int csum:1; /* Enable checksum offloading. */
107 unsigned int hw_timestamp:1; /* Enable HW timestamp. */
108 unsigned int vlan_strip:1; /* Enable VLAN stripping. */
109 unsigned int crc_present:1; /* CRC must be subtracted. */
110 unsigned int sges_n:3; /* Log 2 of SGEs (max buffers per packet). */
111 unsigned int cqe_n:4; /* Log 2 of CQ elements. */
112 unsigned int elts_n:4; /* Log 2 of Mbufs. */
113 unsigned int rss_hash:1; /* RSS hash result is enabled. */
114 unsigned int mark:1; /* Marked flow available on the queue. */
115 unsigned int strd_num_n:5; /* Log 2 of the number of stride. */
116 unsigned int strd_sz_n:4; /* Log 2 of stride size. */
117 unsigned int strd_shift_en:1; /* Enable 2bytes shift on a stride. */
118 unsigned int err_state:2; /* enum mlx5_rxq_err_state. */
119 unsigned int strd_headroom_en:1; /* Enable mbuf headroom in MPRQ. */
120 unsigned int lro:1; /* Enable LRO. */
121 unsigned int :1; /* Remaining bits. */
122 volatile uint32_t *rq_db;
123 volatile uint32_t *cq_db;
126 uint16_t consumed_strd; /* Number of consumed strides in WQE. */
129 uint16_t rq_repl_thresh; /* Threshold for buffer replenishment. */
131 struct rxq_zip zip; /* Compressed context. */
132 uint16_t decompressed;
133 /* Number of ready mbufs decompressed from the CQ. */
135 struct mlx5_mr_ctrl mr_ctrl; /* MR control descriptor. */
136 uint16_t mprq_max_memcpy_len; /* Maximum size of packet to memcpy. */
138 volatile struct mlx5_cqe(*cqes)[];
141 struct rte_mbuf *(*elts)[];
142 struct mlx5_mprq_buf *(*mprq_bufs)[];
144 struct rte_mempool *mp;
145 struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */
146 struct mlx5_mprq_buf *mprq_repl; /* Stashed mbuf for replenish. */
147 uint16_t idx; /* Queue index. */
148 struct mlx5_rxq_stats stats;
149 rte_xmm_t mbuf_initializer; /* Default rearm/flags for vectorized Rx. */
150 struct rte_mbuf fake_mbuf; /* elts padding for vectorized Rx. */
151 void *cq_uar; /* CQ user access region. */
152 uint32_t cqn; /* CQ number. */
153 uint8_t cq_arm_sn; /* CQ arm seq number. */
155 rte_spinlock_t *uar_lock_cq;
156 /* CQ (UAR) access lock required for 32bit implementations */
158 uint32_t tunnel; /* Tunnel information. */
159 } __rte_cache_aligned;
161 enum mlx5_rxq_obj_type {
162 MLX5_RXQ_OBJ_TYPE_IBV, /* mlx5_rxq_obj with ibv_wq. */
163 MLX5_RXQ_OBJ_TYPE_DEVX_RQ, /* mlx5_rxq_obj with mlx5_devx_rq. */
164 MLX5_RXQ_OBJ_TYPE_DEVX_HAIRPIN,
165 /* mlx5_rxq_obj with mlx5_devx_rq and hairpin support. */
169 MLX5_RXQ_TYPE_STANDARD, /* Standard Rx queue. */
170 MLX5_RXQ_TYPE_HAIRPIN, /* Hairpin Rx queue. */
171 MLX5_RXQ_TYPE_UNDEFINED,
174 /* Verbs/DevX Rx queue elements. */
175 struct mlx5_rxq_obj {
176 LIST_ENTRY(mlx5_rxq_obj) next; /* Pointer to the next element. */
177 rte_atomic32_t refcnt; /* Reference counter. */
178 struct mlx5_rxq_ctrl *rxq_ctrl; /* Back pointer to parent. */
179 struct ibv_cq *cq; /* Completion Queue. */
180 enum mlx5_rxq_obj_type type;
183 struct ibv_wq *wq; /* Work Queue. */
184 struct mlx5_devx_obj *rq; /* DevX object for Rx Queue. */
186 struct ibv_comp_channel *channel;
189 /* RX queue control descriptor. */
190 struct mlx5_rxq_ctrl {
191 struct mlx5_rxq_data rxq; /* Data path structure. */
192 LIST_ENTRY(mlx5_rxq_ctrl) next; /* Pointer to the next element. */
193 rte_atomic32_t refcnt; /* Reference counter. */
194 struct mlx5_rxq_obj *obj; /* Verbs/DevX elements. */
195 struct mlx5_priv *priv; /* Back pointer to private data. */
196 enum mlx5_rxq_type type; /* Rxq type. */
197 unsigned int socket; /* CPU socket ID for allocations. */
198 unsigned int irq:1; /* Whether IRQ is enabled. */
199 unsigned int dbr_umem_id_valid:1; /* dbr_umem_id holds a valid value. */
200 uint32_t flow_mark_n; /* Number of Mark/Flag flows using this Queue. */
201 uint32_t flow_tunnels_n[MLX5_FLOW_TUNNEL]; /* Tunnels counters. */
202 uint32_t wqn; /* WQ number. */
203 uint16_t dump_file_n; /* Number of dump files. */
204 uint32_t dbr_umem_id; /* Storing door-bell information, */
205 uint64_t dbr_offset; /* needed when freeing door-bell. */
206 struct mlx5dv_devx_umem *wq_umem; /* WQ buffer registration info. */
207 struct rte_eth_hairpin_conf hairpin_conf; /* Hairpin configuration. */
210 enum mlx5_ind_tbl_type {
211 MLX5_IND_TBL_TYPE_IBV,
212 MLX5_IND_TBL_TYPE_DEVX,
215 /* Indirection table. */
216 struct mlx5_ind_table_obj {
217 LIST_ENTRY(mlx5_ind_table_obj) next; /* Pointer to the next element. */
218 rte_atomic32_t refcnt; /* Reference counter. */
219 enum mlx5_ind_tbl_type type;
222 struct ibv_rwq_ind_table *ind_table; /**< Indirection table. */
223 struct mlx5_devx_obj *rqt; /* DevX RQT object. */
225 uint32_t queues_n; /**< Number of queues in the list. */
226 uint16_t queues[]; /**< Queue list. */
231 LIST_ENTRY(mlx5_hrxq) next; /* Pointer to the next element. */
232 rte_atomic32_t refcnt; /* Reference counter. */
233 struct mlx5_ind_table_obj *ind_table; /* Indirection table. */
236 struct ibv_qp *qp; /* Verbs queue pair. */
237 struct mlx5_devx_obj *tir; /* DevX TIR object. */
239 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
240 void *action; /* DV QP action pointer. */
242 uint64_t hash_fields; /* Verbs Hash fields. */
243 uint32_t rss_key_len; /* Hash key length in bytes. */
244 uint8_t rss_key[]; /* Hash key. */
247 /* TX queue send local data. */
249 struct mlx5_txq_local {
250 struct mlx5_wqe *wqe_last; /* last sent WQE pointer. */
251 struct rte_mbuf *mbuf; /* first mbuf to process. */
252 uint16_t pkts_copy; /* packets copied to elts. */
253 uint16_t pkts_sent; /* packets sent. */
254 uint16_t pkts_loop; /* packets sent on loop entry. */
255 uint16_t elts_free; /* available elts remain. */
256 uint16_t wqe_free; /* available wqe remain. */
257 uint16_t mbuf_off; /* data offset in current mbuf. */
258 uint16_t mbuf_nseg; /* number of remaining mbuf. */
261 /* TX queue descriptor. */
263 struct mlx5_txq_data {
264 uint16_t elts_head; /* Current counter in (*elts)[]. */
265 uint16_t elts_tail; /* Counter of first element awaiting completion. */
266 uint16_t elts_comp; /* elts index since last completion request. */
267 uint16_t elts_s; /* Number of mbuf elements. */
268 uint16_t elts_m; /* Mask for mbuf elements indices. */
269 /* Fields related to elts mbuf storage. */
270 uint16_t wqe_ci; /* Consumer index for work queue. */
271 uint16_t wqe_pi; /* Producer index for work queue. */
272 uint16_t wqe_s; /* Number of WQ elements. */
273 uint16_t wqe_m; /* Mask Number for WQ elements. */
274 uint16_t wqe_comp; /* WQE index since last completion request. */
275 uint16_t wqe_thres; /* WQE threshold to request completion in CQ. */
276 /* WQ related fields. */
277 uint16_t cq_ci; /* Consumer index for completion queue. */
278 uint16_t cq_pi; /* Production index for completion queue. */
279 uint16_t cqe_s; /* Number of CQ elements. */
280 uint16_t cqe_m; /* Mask for CQ indices. */
281 /* CQ related fields. */
282 uint16_t elts_n:4; /* elts[] length (in log2). */
283 uint16_t cqe_n:4; /* Number of CQ elements (in log2). */
284 uint16_t wqe_n:4; /* Number of WQ elements (in log2). */
285 uint16_t tso_en:1; /* When set hardware TSO is enabled. */
286 uint16_t tunnel_en:1;
287 /* When set TX offload for tunneled packets are supported. */
288 uint16_t swp_en:1; /* Whether SW parser is enabled. */
289 uint16_t vlan_en:1; /* VLAN insertion in WQE is supported. */
290 uint16_t db_nc:1; /* Doorbell mapped to non-cached region. */
291 uint16_t db_heu:1; /* Doorbell heuristic write barrier. */
292 uint16_t inlen_send; /* Ordinary send data inline size. */
293 uint16_t inlen_empw; /* eMPW max packet size to inline. */
294 uint16_t inlen_mode; /* Minimal data length to inline. */
295 uint32_t qp_num_8s; /* QP number shifted by 8. */
296 uint64_t offloads; /* Offloads for Tx Queue. */
297 struct mlx5_mr_ctrl mr_ctrl; /* MR control descriptor. */
298 struct mlx5_wqe *wqes; /* Work queue. */
299 struct mlx5_wqe *wqes_end; /* Work queue array limit. */
301 uint16_t *fcqs; /* Free completion queue. */
303 uint32_t *fcqs; /* Free completion queue (debug extended). */
305 volatile struct mlx5_cqe *cqes; /* Completion queue. */
306 volatile uint32_t *qp_db; /* Work queue doorbell. */
307 volatile uint32_t *cq_db; /* Completion queue doorbell. */
308 uint16_t port_id; /* Port ID of device. */
309 uint16_t idx; /* Queue index. */
310 struct mlx5_txq_stats stats; /* TX queue counters. */
312 rte_spinlock_t *uar_lock;
313 /* UAR access lock required for 32bit implementations */
315 struct rte_mbuf *elts[0];
316 /* Storage for queued packets, must be the last field. */
317 } __rte_cache_aligned;
319 enum mlx5_txq_obj_type {
320 MLX5_TXQ_OBJ_TYPE_IBV, /* mlx5_txq_obj with ibv_wq. */
321 MLX5_TXQ_OBJ_TYPE_DEVX_HAIRPIN,
322 /* mlx5_txq_obj with mlx5_devx_tq and hairpin support. */
326 MLX5_TXQ_TYPE_STANDARD, /* Standard Tx queue. */
327 MLX5_TXQ_TYPE_HAIRPIN, /* Hairpin Rx queue. */
330 /* Verbs/DevX Tx queue elements. */
331 struct mlx5_txq_obj {
332 LIST_ENTRY(mlx5_txq_obj) next; /* Pointer to the next element. */
333 rte_atomic32_t refcnt; /* Reference counter. */
334 struct mlx5_txq_ctrl *txq_ctrl; /* Pointer to the control queue. */
335 enum mlx5_txq_obj_type type; /* The txq object type. */
339 struct ibv_cq *cq; /* Completion Queue. */
340 struct ibv_qp *qp; /* Queue Pair. */
343 struct mlx5_devx_obj *sq;
344 /* DevX object for Sx queue. */
345 struct mlx5_devx_obj *tis; /* The TIS object. */
350 /* TX queue control descriptor. */
351 struct mlx5_txq_ctrl {
352 LIST_ENTRY(mlx5_txq_ctrl) next; /* Pointer to the next element. */
353 rte_atomic32_t refcnt; /* Reference counter. */
354 unsigned int socket; /* CPU socket ID for allocations. */
355 enum mlx5_txq_type type; /* The txq ctrl type. */
356 unsigned int max_inline_data; /* Max inline data. */
357 unsigned int max_tso_header; /* Max TSO header size. */
358 struct mlx5_txq_obj *obj; /* Verbs/DevX queue object. */
359 struct mlx5_priv *priv; /* Back pointer to private data. */
360 off_t uar_mmap_offset; /* UAR mmap offset for non-primary process. */
361 void *bf_reg; /* BlueFlame register from Verbs. */
362 uint16_t dump_file_n; /* Number of dump files. */
363 struct rte_eth_hairpin_conf hairpin_conf; /* Hairpin configuration. */
364 struct mlx5_txq_data txq; /* Data path structure. */
365 /* Must be the last field in the structure, contains elts[]. */
368 #define MLX5_TX_BFREG(txq) \
369 (MLX5_PROC_PRIV((txq)->port_id)->uar_table[(txq)->idx])
373 extern uint8_t rss_hash_default_key[];
375 int mlx5_check_mprq_support(struct rte_eth_dev *dev);
376 int mlx5_rxq_mprq_enabled(struct mlx5_rxq_data *rxq);
377 int mlx5_mprq_enabled(struct rte_eth_dev *dev);
378 int mlx5_mprq_free_mp(struct rte_eth_dev *dev);
379 int mlx5_mprq_alloc_mp(struct rte_eth_dev *dev);
380 int mlx5_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
381 unsigned int socket, const struct rte_eth_rxconf *conf,
382 struct rte_mempool *mp);
383 int mlx5_rx_hairpin_queue_setup
384 (struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
385 const struct rte_eth_hairpin_conf *hairpin_conf);
386 void mlx5_rx_queue_release(void *dpdk_rxq);
387 int mlx5_rx_intr_vec_enable(struct rte_eth_dev *dev);
388 void mlx5_rx_intr_vec_disable(struct rte_eth_dev *dev);
389 int mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id);
390 int mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id);
391 struct mlx5_rxq_obj *mlx5_rxq_obj_new(struct rte_eth_dev *dev, uint16_t idx,
392 enum mlx5_rxq_obj_type type);
393 int mlx5_rxq_obj_verify(struct rte_eth_dev *dev);
394 struct mlx5_rxq_ctrl *mlx5_rxq_new(struct rte_eth_dev *dev, uint16_t idx,
395 uint16_t desc, unsigned int socket,
396 const struct rte_eth_rxconf *conf,
397 struct rte_mempool *mp);
398 struct mlx5_rxq_ctrl *mlx5_rxq_hairpin_new
399 (struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
400 const struct rte_eth_hairpin_conf *hairpin_conf);
401 struct mlx5_rxq_ctrl *mlx5_rxq_get(struct rte_eth_dev *dev, uint16_t idx);
402 int mlx5_rxq_release(struct rte_eth_dev *dev, uint16_t idx);
403 int mlx5_rxq_verify(struct rte_eth_dev *dev);
404 int rxq_alloc_elts(struct mlx5_rxq_ctrl *rxq_ctrl);
405 int mlx5_ind_table_obj_verify(struct rte_eth_dev *dev);
406 struct mlx5_hrxq *mlx5_hrxq_new(struct rte_eth_dev *dev,
407 const uint8_t *rss_key, uint32_t rss_key_len,
408 uint64_t hash_fields,
409 const uint16_t *queues, uint32_t queues_n,
410 int tunnel __rte_unused);
411 struct mlx5_hrxq *mlx5_hrxq_get(struct rte_eth_dev *dev,
412 const uint8_t *rss_key, uint32_t rss_key_len,
413 uint64_t hash_fields,
414 const uint16_t *queues, uint32_t queues_n);
415 int mlx5_hrxq_release(struct rte_eth_dev *dev, struct mlx5_hrxq *hxrq);
416 int mlx5_hrxq_verify(struct rte_eth_dev *dev);
417 enum mlx5_rxq_type mlx5_rxq_get_type(struct rte_eth_dev *dev, uint16_t idx);
418 struct mlx5_hrxq *mlx5_hrxq_drop_new(struct rte_eth_dev *dev);
419 void mlx5_hrxq_drop_release(struct rte_eth_dev *dev);
420 uint64_t mlx5_get_rx_port_offloads(void);
421 uint64_t mlx5_get_rx_queue_offloads(struct rte_eth_dev *dev);
425 int mlx5_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
426 unsigned int socket, const struct rte_eth_txconf *conf);
427 int mlx5_tx_hairpin_queue_setup
428 (struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
429 const struct rte_eth_hairpin_conf *hairpin_conf);
430 void mlx5_tx_queue_release(void *dpdk_txq);
431 int mlx5_tx_uar_init_secondary(struct rte_eth_dev *dev, int fd);
432 struct mlx5_txq_obj *mlx5_txq_obj_new(struct rte_eth_dev *dev, uint16_t idx,
433 enum mlx5_txq_obj_type type);
434 struct mlx5_txq_obj *mlx5_txq_obj_get(struct rte_eth_dev *dev, uint16_t idx);
435 int mlx5_txq_obj_release(struct mlx5_txq_obj *txq_ibv);
436 int mlx5_txq_obj_verify(struct rte_eth_dev *dev);
437 struct mlx5_txq_ctrl *mlx5_txq_new(struct rte_eth_dev *dev, uint16_t idx,
438 uint16_t desc, unsigned int socket,
439 const struct rte_eth_txconf *conf);
440 struct mlx5_txq_ctrl *mlx5_txq_hairpin_new
441 (struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
442 const struct rte_eth_hairpin_conf *hairpin_conf);
443 struct mlx5_txq_ctrl *mlx5_txq_get(struct rte_eth_dev *dev, uint16_t idx);
444 int mlx5_txq_release(struct rte_eth_dev *dev, uint16_t idx);
445 int mlx5_txq_releasable(struct rte_eth_dev *dev, uint16_t idx);
446 int mlx5_txq_verify(struct rte_eth_dev *dev);
447 void txq_alloc_elts(struct mlx5_txq_ctrl *txq_ctrl);
448 void txq_free_elts(struct mlx5_txq_ctrl *txq_ctrl);
449 uint64_t mlx5_get_tx_port_offloads(struct rte_eth_dev *dev);
453 extern uint32_t mlx5_ptype_table[];
454 extern uint8_t mlx5_cksum_table[];
455 extern uint8_t mlx5_swp_types_table[];
457 void mlx5_set_ptype_table(void);
458 void mlx5_set_cksum_table(void);
459 void mlx5_set_swp_types_table(void);
460 uint16_t mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n);
461 void mlx5_rxq_initialize(struct mlx5_rxq_data *rxq);
462 __rte_noinline int mlx5_rx_err_handle(struct mlx5_rxq_data *rxq, uint8_t vec);
463 void mlx5_mprq_buf_free_cb(void *addr, void *opaque);
464 void mlx5_mprq_buf_free(struct mlx5_mprq_buf *buf);
465 uint16_t mlx5_rx_burst_mprq(void *dpdk_rxq, struct rte_mbuf **pkts,
467 uint16_t removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts,
469 uint16_t removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts,
471 int mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset);
472 int mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset);
473 uint32_t mlx5_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id);
474 void mlx5_dump_debug_information(const char *path, const char *title,
475 const void *buf, unsigned int len);
476 int mlx5_queue_state_modify_primary(struct rte_eth_dev *dev,
477 const struct mlx5_mp_arg_queue_state_modify *sm);
479 /* Vectorized version of mlx5_rxtx.c */
480 int mlx5_rxq_check_vec_support(struct mlx5_rxq_data *rxq_data);
481 int mlx5_check_vec_rx_support(struct rte_eth_dev *dev);
482 uint16_t mlx5_rx_burst_vec(void *dpdk_txq, struct rte_mbuf **pkts,
487 void mlx5_mr_flush_local_cache(struct mlx5_mr_ctrl *mr_ctrl);
488 uint32_t mlx5_rx_addr2mr_bh(struct mlx5_rxq_data *rxq, uintptr_t addr);
489 uint32_t mlx5_tx_mb2mr_bh(struct mlx5_txq_data *txq, struct rte_mbuf *mb);
490 uint32_t mlx5_tx_update_ext_mp(struct mlx5_txq_data *txq, uintptr_t addr,
491 struct rte_mempool *mp);
492 int mlx5_dma_map(struct rte_pci_device *pdev, void *addr, uint64_t iova,
494 int mlx5_dma_unmap(struct rte_pci_device *pdev, void *addr, uint64_t iova,
498 * Provide safe 64bit store operation to mlx5 UAR region for both 32bit and
499 * 64bit architectures.
502 * value to write in CPU endian format.
504 * Address to write to.
506 * Address of the lock to use for that UAR access.
508 static __rte_always_inline void
509 __mlx5_uar_write64_relaxed(uint64_t val, void *addr,
510 rte_spinlock_t *lock __rte_unused)
513 *(uint64_t *)addr = val;
514 #else /* !RTE_ARCH_64 */
515 rte_spinlock_lock(lock);
516 *(uint32_t *)addr = val;
518 *((uint32_t *)addr + 1) = val >> 32;
519 rte_spinlock_unlock(lock);
524 * Provide safe 64bit store operation to mlx5 UAR region for both 32bit and
525 * 64bit architectures while guaranteeing the order of execution with the
526 * code being executed.
529 * value to write in CPU endian format.
531 * Address to write to.
533 * Address of the lock to use for that UAR access.
535 static __rte_always_inline void
536 __mlx5_uar_write64(uint64_t val, void *addr, rte_spinlock_t *lock)
539 __mlx5_uar_write64_relaxed(val, addr, lock);
542 /* Assist macros, used instead of directly calling the functions they wrap. */
544 #define mlx5_uar_write64_relaxed(val, dst, lock) \
545 __mlx5_uar_write64_relaxed(val, dst, NULL)
546 #define mlx5_uar_write64(val, dst, lock) __mlx5_uar_write64(val, dst, NULL)
548 #define mlx5_uar_write64_relaxed(val, dst, lock) \
549 __mlx5_uar_write64_relaxed(val, dst, lock)
550 #define mlx5_uar_write64(val, dst, lock) __mlx5_uar_write64(val, dst, lock)
554 * Get Memory Pool (MP) from mbuf. If mbuf is indirect, the pool from which the
555 * cloned mbuf is allocated is returned instead.
561 * Memory pool where data is located for given mbuf.
563 static inline struct rte_mempool *
564 mlx5_mb2mp(struct rte_mbuf *buf)
566 if (unlikely(RTE_MBUF_CLONED(buf)))
567 return rte_mbuf_from_indirect(buf)->pool;
572 * Query LKey from a packet buffer for Rx. No need to flush local caches for Rx
573 * as mempool is pre-configured and static.
576 * Pointer to Rx queue structure.
581 * Searched LKey on success, UINT32_MAX on no match.
583 static __rte_always_inline uint32_t
584 mlx5_rx_addr2mr(struct mlx5_rxq_data *rxq, uintptr_t addr)
586 struct mlx5_mr_ctrl *mr_ctrl = &rxq->mr_ctrl;
589 /* Linear search on MR cache array. */
590 lkey = mlx5_mr_lookup_cache(mr_ctrl->cache, &mr_ctrl->mru,
591 MLX5_MR_CACHE_N, addr);
592 if (likely(lkey != UINT32_MAX))
594 /* Take slower bottom-half (Binary Search) on miss. */
595 return mlx5_rx_addr2mr_bh(rxq, addr);
598 #define mlx5_rx_mb2mr(rxq, mb) mlx5_rx_addr2mr(rxq, (uintptr_t)((mb)->buf_addr))
601 * Query LKey from a packet buffer for Tx. If not found, add the mempool.
604 * Pointer to Tx queue structure.
609 * Searched LKey on success, UINT32_MAX on no match.
611 static __rte_always_inline uint32_t
612 mlx5_tx_mb2mr(struct mlx5_txq_data *txq, struct rte_mbuf *mb)
614 struct mlx5_mr_ctrl *mr_ctrl = &txq->mr_ctrl;
615 uintptr_t addr = (uintptr_t)mb->buf_addr;
618 /* Check generation bit to see if there's any change on existing MRs. */
619 if (unlikely(*mr_ctrl->dev_gen_ptr != mr_ctrl->cur_gen))
620 mlx5_mr_flush_local_cache(mr_ctrl);
621 /* Linear search on MR cache array. */
622 lkey = mlx5_mr_lookup_cache(mr_ctrl->cache, &mr_ctrl->mru,
623 MLX5_MR_CACHE_N, addr);
624 if (likely(lkey != UINT32_MAX))
626 /* Take slower bottom-half on miss. */
627 return mlx5_tx_mb2mr_bh(txq, mb);
631 * Ring TX queue doorbell and flush the update if requested.
634 * Pointer to TX queue structure.
636 * Pointer to the last WQE posted in the NIC.
638 * Request for write memory barrier after BlueFlame update.
640 static __rte_always_inline void
641 mlx5_tx_dbrec_cond_wmb(struct mlx5_txq_data *txq, volatile struct mlx5_wqe *wqe,
644 uint64_t *dst = MLX5_TX_BFREG(txq);
645 volatile uint64_t *src = ((volatile uint64_t *)wqe);
648 *txq->qp_db = rte_cpu_to_be_32(txq->wqe_ci);
649 /* Ensure ordering between DB record and BF copy. */
651 mlx5_uar_write64_relaxed(*src, dst, txq->uar_lock);
657 * Ring TX queue doorbell and flush the update by write memory barrier.
660 * Pointer to TX queue structure.
662 * Pointer to the last WQE posted in the NIC.
664 static __rte_always_inline void
665 mlx5_tx_dbrec(struct mlx5_txq_data *txq, volatile struct mlx5_wqe *wqe)
667 mlx5_tx_dbrec_cond_wmb(txq, wqe, 1);
670 #endif /* RTE_PMD_MLX5_RXTX_H_ */