1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2017 6WIND S.A.
3 * Copyright 2017 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_RXTX_VEC_NEON_H_
7 #define RTE_PMD_MLX5_RXTX_VEC_NEON_H_
15 #include <rte_mempool.h>
16 #include <rte_prefetch.h>
20 #include "mlx5_defs.h"
22 #include "mlx5_utils.h"
23 #include "mlx5_rxtx.h"
24 #include "mlx5_rxtx_vec.h"
25 #include "mlx5_autoconf.h"
27 #pragma GCC diagnostic ignored "-Wcast-qual"
30 * Store free buffers to RX SW ring.
33 * Pointer to RX queue structure.
35 * Pointer to array of packets to be stored.
37 * Number of packets to be stored.
40 rxq_copy_mbuf_v(struct mlx5_rxq_data *rxq, struct rte_mbuf **pkts, uint16_t n)
42 const uint16_t q_mask = (1 << rxq->elts_n) - 1;
43 struct rte_mbuf **elts = &(*rxq->elts)[rxq->rq_pi & q_mask];
47 for (pos = 0; pos < p; pos += 2) {
50 mbp = vld1q_u64((void *)&elts[pos]);
51 vst1q_u64((void *)&pkts[pos], mbp);
54 pkts[pos] = elts[pos];
58 * Decompress a compressed completion and fill in mbufs in RX SW ring with data
59 * extracted from the title completion descriptor.
62 * Pointer to RX queue structure.
64 * Pointer to completion array having a compressed completion at first.
66 * Pointer to SW ring to be filled. The first mbuf has to be pre-built from
67 * the title completion descriptor to be copied to the rest of mbufs.
70 * Number of mini-CQEs successfully decompressed.
72 static inline uint16_t
73 rxq_cq_decompress_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq,
74 struct rte_mbuf **elts)
76 volatile struct mlx5_mini_cqe8 *mcq = (void *)&(cq + 1)->pkt_info;
77 struct rte_mbuf *t_pkt = elts[0]; /* Title packet is pre-built. */
81 /* Mask to shuffle from extracted mini CQE to mbuf. */
82 const uint8x16_t mcqe_shuf_m1 = {
83 -1, -1, -1, -1, /* skip packet_type */
84 7, 6, -1, -1, /* pkt_len, bswap16 */
85 7, 6, /* data_len, bswap16 */
86 -1, -1, /* skip vlan_tci */
87 3, 2, 1, 0 /* hash.rss, bswap32 */
89 const uint8x16_t mcqe_shuf_m2 = {
90 -1, -1, -1, -1, /* skip packet_type */
91 15, 14, -1, -1, /* pkt_len, bswap16 */
92 15, 14, /* data_len, bswap16 */
93 -1, -1, /* skip vlan_tci */
94 11, 10, 9, 8 /* hash.rss, bswap32 */
96 /* Restore the compressed count. Must be 16 bits. */
97 const uint16_t mcqe_n = t_pkt->data_len +
98 (rxq->crc_present * RTE_ETHER_CRC_LEN);
99 const uint64x2_t rearm =
100 vld1q_u64((void *)&t_pkt->rearm_data);
101 const uint32x4_t rxdf_mask = {
102 0xffffffff, /* packet_type */
103 0, /* skip pkt_len */
104 0xffff0000, /* vlan_tci, skip data_len */
105 0, /* skip hash.rss */
107 const uint8x16_t rxdf =
108 vandq_u8(vld1q_u8((void *)&t_pkt->rx_descriptor_fields1),
109 vreinterpretq_u8_u32(rxdf_mask));
110 const uint16x8_t crc_adj = {
112 rxq->crc_present * RTE_ETHER_CRC_LEN, 0,
113 rxq->crc_present * RTE_ETHER_CRC_LEN, 0,
116 const uint32_t flow_tag = t_pkt->hash.fdir.hi;
117 #ifdef MLX5_PMD_SOFT_COUNTERS
118 uint32_t rcvd_byte = 0;
120 /* Mask to shuffle byte_cnt to add up stats. Do bswap16 for all. */
121 const uint8x8_t len_shuf_m = {
123 15, 14, /* 2nd mCQE */
124 23, 22, /* 3rd mCQE */
125 31, 30 /* 4th mCQE */
129 * A. load mCQEs into a 128bit register.
130 * B. store rearm data to mbuf.
131 * C. combine data from mCQEs with rx_descriptor_fields1.
132 * D. store rx_descriptor_fields1.
133 * E. store flow tag (rte_flow mark).
135 for (pos = 0; pos < mcqe_n; ) {
136 uint8_t *p = (void *)&mcq[pos % 8];
137 uint8_t *e0 = (void *)&elts[pos]->rearm_data;
138 uint8_t *e1 = (void *)&elts[pos + 1]->rearm_data;
139 uint8_t *e2 = (void *)&elts[pos + 2]->rearm_data;
140 uint8_t *e3 = (void *)&elts[pos + 3]->rearm_data;
142 #ifdef MLX5_PMD_SOFT_COUNTERS
143 uint16x4_t invalid_mask =
144 vcreate_u16(mcqe_n - pos < MLX5_VPMD_DESCS_PER_LOOP ?
145 -1UL << ((mcqe_n - pos) *
146 sizeof(uint16_t) * 8) : 0);
149 if (!(pos & 0x7) && pos + 8 < mcqe_n)
150 rte_prefetch0((void *)(cq + pos + 8));
152 /* A.1 load mCQEs into a 128bit register. */
153 "ld1 {v16.16b - v17.16b}, [%[mcq]] \n\t"
154 /* B.1 store rearm data to mbuf. */
155 "st1 {%[rearm].2d}, [%[e0]] \n\t"
156 "add %[e0], %[e0], #16 \n\t"
157 "st1 {%[rearm].2d}, [%[e1]] \n\t"
158 "add %[e1], %[e1], #16 \n\t"
159 /* C.1 combine data from mCQEs with rx_descriptor_fields1. */
160 "tbl v18.16b, {v16.16b}, %[mcqe_shuf_m1].16b \n\t"
161 "tbl v19.16b, {v16.16b}, %[mcqe_shuf_m2].16b \n\t"
162 "sub v18.8h, v18.8h, %[crc_adj].8h \n\t"
163 "sub v19.8h, v19.8h, %[crc_adj].8h \n\t"
164 "orr v18.16b, v18.16b, %[rxdf].16b \n\t"
165 "orr v19.16b, v19.16b, %[rxdf].16b \n\t"
166 /* D.1 store rx_descriptor_fields1. */
167 "st1 {v18.2d}, [%[e0]] \n\t"
168 "st1 {v19.2d}, [%[e1]] \n\t"
169 /* B.1 store rearm data to mbuf. */
170 "st1 {%[rearm].2d}, [%[e2]] \n\t"
171 "add %[e2], %[e2], #16 \n\t"
172 "st1 {%[rearm].2d}, [%[e3]] \n\t"
173 "add %[e3], %[e3], #16 \n\t"
174 /* C.1 combine data from mCQEs with rx_descriptor_fields1. */
175 "tbl v18.16b, {v17.16b}, %[mcqe_shuf_m1].16b \n\t"
176 "tbl v19.16b, {v17.16b}, %[mcqe_shuf_m2].16b \n\t"
177 "sub v18.8h, v18.8h, %[crc_adj].8h \n\t"
178 "sub v19.8h, v19.8h, %[crc_adj].8h \n\t"
179 "orr v18.16b, v18.16b, %[rxdf].16b \n\t"
180 "orr v19.16b, v19.16b, %[rxdf].16b \n\t"
181 /* D.1 store rx_descriptor_fields1. */
182 "st1 {v18.2d}, [%[e2]] \n\t"
183 "st1 {v19.2d}, [%[e3]] \n\t"
184 #ifdef MLX5_PMD_SOFT_COUNTERS
185 "tbl %[byte_cnt].8b, {v16.16b - v17.16b}, %[len_shuf_m].8b \n\t"
187 :[byte_cnt]"=&w"(byte_cnt)
191 [e3]"r"(e3), [e2]"r"(e2), [e1]"r"(e1), [e0]"r"(e0),
192 [mcqe_shuf_m1]"w"(mcqe_shuf_m1),
193 [mcqe_shuf_m2]"w"(mcqe_shuf_m2),
194 [crc_adj]"w"(crc_adj),
195 [len_shuf_m]"w"(len_shuf_m)
196 :"memory", "v16", "v17", "v18", "v19");
197 #ifdef MLX5_PMD_SOFT_COUNTERS
198 byte_cnt = vbic_u16(byte_cnt, invalid_mask);
199 rcvd_byte += vget_lane_u64(vpaddl_u32(vpaddl_u16(byte_cnt)), 0);
202 /* E.1 store flow tag (rte_flow mark). */
203 elts[pos]->hash.fdir.hi = flow_tag;
204 elts[pos + 1]->hash.fdir.hi = flow_tag;
205 elts[pos + 2]->hash.fdir.hi = flow_tag;
206 elts[pos + 3]->hash.fdir.hi = flow_tag;
208 if (rte_flow_dynf_metadata_avail()) {
209 const uint32_t meta = *RTE_FLOW_DYNF_METADATA(t_pkt);
211 /* Check if title packet has valid metadata. */
213 MLX5_ASSERT(t_pkt->ol_flags &
214 PKT_RX_DYNF_METADATA);
215 *RTE_FLOW_DYNF_METADATA(elts[pos]) = meta;
216 *RTE_FLOW_DYNF_METADATA(elts[pos + 1]) = meta;
217 *RTE_FLOW_DYNF_METADATA(elts[pos + 2]) = meta;
218 *RTE_FLOW_DYNF_METADATA(elts[pos + 3]) = meta;
221 pos += MLX5_VPMD_DESCS_PER_LOOP;
222 /* Move to next CQE and invalidate consumed CQEs. */
223 if (!(pos & 0x7) && pos < mcqe_n) {
224 mcq = (void *)&(cq + pos)->pkt_info;
225 for (i = 0; i < 8; ++i)
226 cq[inv++].op_own = MLX5_CQE_INVALIDATE;
229 /* Invalidate the rest of CQEs. */
230 for (; inv < mcqe_n; ++inv)
231 cq[inv].op_own = MLX5_CQE_INVALIDATE;
232 #ifdef MLX5_PMD_SOFT_COUNTERS
233 rxq->stats.ipackets += mcqe_n;
234 rxq->stats.ibytes += rcvd_byte;
236 rxq->cq_ci += mcqe_n;
241 * Calculate packet type and offload flag for mbuf and store it.
244 * Pointer to RX queue structure.
246 * Array of four 4bytes packet type info extracted from the original
247 * completion descriptor.
249 * Array of four 4bytes flow ID extracted from the original completion
252 * Opcode vector having responder error status. Each field is 4B.
254 * Pointer to array of packets to be filled.
257 rxq_cq_to_ptype_oflags_v(struct mlx5_rxq_data *rxq,
258 uint32x4_t ptype_info, uint32x4_t flow_tag,
259 uint16x4_t op_err, struct rte_mbuf **pkts)
262 uint32x4_t pinfo, cv_flags;
263 uint32x4_t ol_flags =
264 vdupq_n_u32(rxq->rss_hash * PKT_RX_RSS_HASH |
265 rxq->hw_timestamp * PKT_RX_TIMESTAMP);
266 const uint32x4_t ptype_ol_mask = { 0x106, 0x106, 0x106, 0x106 };
267 const uint8x16_t cv_flag_sel = {
269 (uint8_t)(PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED),
270 (uint8_t)(PKT_RX_IP_CKSUM_GOOD >> 1),
272 (uint8_t)(PKT_RX_L4_CKSUM_GOOD >> 1),
274 (uint8_t)((PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD) >> 1),
275 0, 0, 0, 0, 0, 0, 0, 0, 0
277 const uint32x4_t cv_mask =
278 vdupq_n_u32(PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD |
279 PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED);
280 const uint64x2_t mbuf_init = vld1q_u64
281 ((const uint64_t *)&rxq->mbuf_initializer);
282 uint64x2_t rearm0, rearm1, rearm2, rearm3;
283 uint8_t pt_idx0, pt_idx1, pt_idx2, pt_idx3;
286 const uint32x4_t ft_def = vdupq_n_u32(MLX5_FLOW_MARK_DEFAULT);
287 const uint32x4_t fdir_flags = vdupq_n_u32(PKT_RX_FDIR);
288 uint32x4_t fdir_id_flags = vdupq_n_u32(PKT_RX_FDIR_ID);
289 uint32x4_t invalid_mask;
291 /* Check if flow tag is non-zero then set PKT_RX_FDIR. */
292 invalid_mask = vceqzq_u32(flow_tag);
293 ol_flags = vorrq_u32(ol_flags,
294 vbicq_u32(fdir_flags, invalid_mask));
295 /* Mask out invalid entries. */
296 fdir_id_flags = vbicq_u32(fdir_id_flags, invalid_mask);
297 /* Check if flow tag MLX5_FLOW_MARK_DEFAULT. */
298 ol_flags = vorrq_u32(ol_flags,
299 vbicq_u32(fdir_id_flags,
300 vceqq_u32(flow_tag, ft_def)));
303 * ptype_info has the following:
307 * bit[11:10] = l3_hdr_type
308 * bit[14:12] = l4_hdr_type
311 * bit[17] = outer_l3_type
313 ptype = vshrn_n_u32(ptype_info, 10);
314 /* Errored packets will have RTE_PTYPE_ALL_MASK. */
315 ptype = vorr_u16(ptype, op_err);
316 pt_idx0 = vget_lane_u8(vreinterpret_u8_u16(ptype), 6);
317 pt_idx1 = vget_lane_u8(vreinterpret_u8_u16(ptype), 4);
318 pt_idx2 = vget_lane_u8(vreinterpret_u8_u16(ptype), 2);
319 pt_idx3 = vget_lane_u8(vreinterpret_u8_u16(ptype), 0);
320 pkts[0]->packet_type = mlx5_ptype_table[pt_idx0] |
321 !!(pt_idx0 & (1 << 6)) * rxq->tunnel;
322 pkts[1]->packet_type = mlx5_ptype_table[pt_idx1] |
323 !!(pt_idx1 & (1 << 6)) * rxq->tunnel;
324 pkts[2]->packet_type = mlx5_ptype_table[pt_idx2] |
325 !!(pt_idx2 & (1 << 6)) * rxq->tunnel;
326 pkts[3]->packet_type = mlx5_ptype_table[pt_idx3] |
327 !!(pt_idx3 & (1 << 6)) * rxq->tunnel;
328 /* Fill flags for checksum and VLAN. */
329 pinfo = vandq_u32(ptype_info, ptype_ol_mask);
330 pinfo = vreinterpretq_u32_u8(
331 vqtbl1q_u8(cv_flag_sel, vreinterpretq_u8_u32(pinfo)));
332 /* Locate checksum flags at byte[2:1] and merge with VLAN flags. */
333 cv_flags = vshlq_n_u32(pinfo, 9);
334 cv_flags = vorrq_u32(pinfo, cv_flags);
335 /* Move back flags to start from byte[0]. */
336 cv_flags = vshrq_n_u32(cv_flags, 8);
337 /* Mask out garbage bits. */
338 cv_flags = vandq_u32(cv_flags, cv_mask);
339 /* Merge to ol_flags. */
340 ol_flags = vorrq_u32(ol_flags, cv_flags);
341 /* Merge mbuf_init and ol_flags, and store. */
342 rearm0 = vreinterpretq_u64_u32(vsetq_lane_u32
343 (vgetq_lane_u32(ol_flags, 3),
344 vreinterpretq_u32_u64(mbuf_init), 2));
345 rearm1 = vreinterpretq_u64_u32(vsetq_lane_u32
346 (vgetq_lane_u32(ol_flags, 2),
347 vreinterpretq_u32_u64(mbuf_init), 2));
348 rearm2 = vreinterpretq_u64_u32(vsetq_lane_u32
349 (vgetq_lane_u32(ol_flags, 1),
350 vreinterpretq_u32_u64(mbuf_init), 2));
351 rearm3 = vreinterpretq_u64_u32(vsetq_lane_u32
352 (vgetq_lane_u32(ol_flags, 0),
353 vreinterpretq_u32_u64(mbuf_init), 2));
355 vst1q_u64((void *)&pkts[0]->rearm_data, rearm0);
356 vst1q_u64((void *)&pkts[1]->rearm_data, rearm1);
357 vst1q_u64((void *)&pkts[2]->rearm_data, rearm2);
358 vst1q_u64((void *)&pkts[3]->rearm_data, rearm3);
362 * Receive burst of packets. An errored completion also consumes a mbuf, but the
363 * packet_type is set to be RTE_PTYPE_ALL_MASK. Marked mbufs should be freed
364 * before returning to application.
367 * Pointer to RX queue structure.
369 * Array to store received packets.
371 * Maximum number of packets in array.
373 * Pointer to a flag. Set non-zero value if pkts array has at least one error
377 * Number of packets received including errors (<= pkts_n).
379 static inline uint16_t
380 rxq_burst_v(struct mlx5_rxq_data *rxq, struct rte_mbuf **pkts, uint16_t pkts_n,
383 const uint16_t q_n = 1 << rxq->cqe_n;
384 const uint16_t q_mask = q_n - 1;
385 volatile struct mlx5_cqe *cq;
386 struct rte_mbuf **elts;
390 uint64_t comp_idx = MLX5_VPMD_DESCS_PER_LOOP;
391 uint16_t nocmp_n = 0;
392 uint16_t rcvd_pkt = 0;
393 unsigned int cq_idx = rxq->cq_ci & q_mask;
394 unsigned int elts_idx;
395 const uint16x4_t ownership = vdup_n_u16(!(rxq->cq_ci & (q_mask + 1)));
396 const uint16x4_t owner_check = vcreate_u16(0x0001000100010001);
397 const uint16x4_t opcode_check = vcreate_u16(0x00f000f000f000f0);
398 const uint16x4_t format_check = vcreate_u16(0x000c000c000c000c);
399 const uint16x4_t resp_err_check = vcreate_u16(0x00e000e000e000e0);
400 #ifdef MLX5_PMD_SOFT_COUNTERS
401 uint32_t rcvd_byte = 0;
403 /* Mask to generate 16B length vector. */
404 const uint8x8_t len_shuf_m = {
405 52, 53, /* 4th CQE */
406 36, 37, /* 3rd CQE */
407 20, 21, /* 2nd CQE */
410 /* Mask to extract 16B data from a 64B CQE. */
411 const uint8x16_t cqe_shuf_m = {
412 28, 29, /* hdr_type_etc */
415 47, 46, /* byte_cnt, bswap16 */
416 31, 30, /* vlan_info, bswap16 */
417 15, 14, 13, 12, /* rx_hash_res, bswap32 */
418 57, 58, 59, /* flow_tag */
421 /* Mask to generate 16B data for mbuf. */
422 const uint8x16_t mb_shuf_m = {
423 4, 5, -1, -1, /* pkt_len */
426 8, 9, 10, 11, /* hash.rss */
427 12, 13, 14, -1 /* hash.fdir.hi */
429 /* Mask to generate 16B owner vector. */
430 const uint8x8_t owner_shuf_m = {
431 63, -1, /* 4th CQE */
432 47, -1, /* 3rd CQE */
433 31, -1, /* 2nd CQE */
436 /* Mask to generate a vector having packet_type/ol_flags. */
437 const uint8x16_t ptype_shuf_m = {
438 48, 49, 50, -1, /* 4th CQE */
439 32, 33, 34, -1, /* 3rd CQE */
440 16, 17, 18, -1, /* 2nd CQE */
441 0, 1, 2, -1 /* 1st CQE */
443 /* Mask to generate a vector having flow tags. */
444 const uint8x16_t ftag_shuf_m = {
445 60, 61, 62, -1, /* 4th CQE */
446 44, 45, 46, -1, /* 3rd CQE */
447 28, 29, 30, -1, /* 2nd CQE */
448 12, 13, 14, -1 /* 1st CQE */
450 const uint16x8_t crc_adj = {
451 0, 0, rxq->crc_present * RTE_ETHER_CRC_LEN, 0, 0, 0, 0, 0
453 const uint32x4_t flow_mark_adj = { 0, 0, 0, rxq->mark * (-1) };
455 MLX5_ASSERT(rxq->sges_n == 0);
456 MLX5_ASSERT(rxq->cqe_n == rxq->elts_n);
457 cq = &(*rxq->cqes)[cq_idx];
458 rte_prefetch_non_temporal(cq);
459 rte_prefetch_non_temporal(cq + 1);
460 rte_prefetch_non_temporal(cq + 2);
461 rte_prefetch_non_temporal(cq + 3);
462 pkts_n = RTE_MIN(pkts_n, MLX5_VPMD_RX_MAX_BURST);
463 repl_n = q_n - (rxq->rq_ci - rxq->rq_pi);
464 if (repl_n >= rxq->rq_repl_thresh)
465 mlx5_rx_replenish_bulk_mbuf(rxq, repl_n);
466 /* See if there're unreturned mbufs from compressed CQE. */
467 rcvd_pkt = rxq->decompressed;
469 rcvd_pkt = RTE_MIN(rcvd_pkt, pkts_n);
470 rxq_copy_mbuf_v(rxq, pkts, rcvd_pkt);
471 rxq->rq_pi += rcvd_pkt;
473 rxq->decompressed -= rcvd_pkt;
475 elts_idx = rxq->rq_pi & q_mask;
476 elts = &(*rxq->elts)[elts_idx];
477 /* Not to overflow pkts array. */
478 pkts_n = RTE_ALIGN_FLOOR(pkts_n - rcvd_pkt, MLX5_VPMD_DESCS_PER_LOOP);
479 /* Not to cross queue end. */
480 pkts_n = RTE_MIN(pkts_n, q_n - elts_idx);
481 pkts_n = RTE_MIN(pkts_n, q_n - cq_idx);
484 /* At this point, there shouldn't be any remained packets. */
485 MLX5_ASSERT(rxq->decompressed == 0);
487 * Note that vectors have reverse order - {v3, v2, v1, v0}, because
488 * there's no instruction to count trailing zeros. __builtin_clzl() is
491 * A. copy 4 mbuf pointers from elts ring to returing pkts.
492 * B. load 64B CQE and extract necessary fields
493 * Final 16bytes cqes[] extracted from original 64bytes CQE has the
494 * following structure:
496 * uint16_t hdr_type_etc;
500 * uint16_t vlan_info;
501 * uint32_t rx_has_res;
502 * uint8_t flow_tag[3];
507 * E. find compressed CQE.
511 pos += MLX5_VPMD_DESCS_PER_LOOP) {
513 uint16x4_t opcode, owner_mask, invalid_mask;
514 uint16x4_t comp_mask;
517 uint32x4_t ptype_info, flow_tag;
518 register uint64x2_t c0, c1, c2, c3;
519 uint8_t *p0, *p1, *p2, *p3;
520 uint8_t *e0 = (void *)&elts[pos]->pkt_len;
521 uint8_t *e1 = (void *)&elts[pos + 1]->pkt_len;
522 uint8_t *e2 = (void *)&elts[pos + 2]->pkt_len;
523 uint8_t *e3 = (void *)&elts[pos + 3]->pkt_len;
524 void *elts_p = (void *)&elts[pos];
525 void *pkts_p = (void *)&pkts[pos];
527 /* A.0 do not cross the end of CQ. */
528 mask = vcreate_u16(pkts_n - pos < MLX5_VPMD_DESCS_PER_LOOP ?
529 -1UL >> ((pkts_n - pos) *
530 sizeof(uint16_t) * 8) : 0);
531 p0 = (void *)&cq[pos].pkt_info;
532 p1 = p0 + (pkts_n - pos > 1) * sizeof(struct mlx5_cqe);
533 p2 = p1 + (pkts_n - pos > 2) * sizeof(struct mlx5_cqe);
534 p3 = p2 + (pkts_n - pos > 3) * sizeof(struct mlx5_cqe);
535 /* B.0 (CQE 3) load a block having op_own. */
536 c3 = vld1q_u64((uint64_t *)(p3 + 48));
537 /* B.0 (CQE 2) load a block having op_own. */
538 c2 = vld1q_u64((uint64_t *)(p2 + 48));
539 /* B.0 (CQE 1) load a block having op_own. */
540 c1 = vld1q_u64((uint64_t *)(p1 + 48));
541 /* B.0 (CQE 0) load a block having op_own. */
542 c0 = vld1q_u64((uint64_t *)(p0 + 48));
543 /* Synchronize for loading the rest of blocks. */
545 /* Prefetch next 4 CQEs. */
546 if (pkts_n - pos >= 2 * MLX5_VPMD_DESCS_PER_LOOP) {
547 unsigned int next = pos + MLX5_VPMD_DESCS_PER_LOOP;
548 rte_prefetch_non_temporal(&cq[next]);
549 rte_prefetch_non_temporal(&cq[next + 1]);
550 rte_prefetch_non_temporal(&cq[next + 2]);
551 rte_prefetch_non_temporal(&cq[next + 3]);
554 /* B.1 (CQE 3) load the rest of blocks. */
555 "ld1 {v16.16b - v18.16b}, [%[p3]] \n\t"
556 /* B.2 (CQE 3) move the block having op_own. */
557 "mov v19.16b, %[c3].16b \n\t"
558 /* B.3 (CQE 3) extract 16B fields. */
559 "tbl v23.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \n\t"
560 /* B.1 (CQE 2) load the rest of blocks. */
561 "ld1 {v16.16b - v18.16b}, [%[p2]] \n\t"
562 /* B.4 (CQE 3) adjust CRC length. */
563 "sub v23.8h, v23.8h, %[crc_adj].8h \n\t"
564 /* C.1 (CQE 3) generate final structure for mbuf. */
565 "tbl v15.16b, {v23.16b}, %[mb_shuf_m].16b \n\t"
566 /* B.2 (CQE 2) move the block having op_own. */
567 "mov v19.16b, %[c2].16b \n\t"
568 /* B.3 (CQE 2) extract 16B fields. */
569 "tbl v22.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \n\t"
570 /* B.1 (CQE 1) load the rest of blocks. */
571 "ld1 {v16.16b - v18.16b}, [%[p1]] \n\t"
572 /* B.4 (CQE 2) adjust CRC length. */
573 "sub v22.8h, v22.8h, %[crc_adj].8h \n\t"
574 /* C.1 (CQE 2) generate final structure for mbuf. */
575 "tbl v14.16b, {v22.16b}, %[mb_shuf_m].16b \n\t"
576 /* B.2 (CQE 1) move the block having op_own. */
577 "mov v19.16b, %[c1].16b \n\t"
578 /* B.3 (CQE 1) extract 16B fields. */
579 "tbl v21.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \n\t"
580 /* B.1 (CQE 0) load the rest of blocks. */
581 "ld1 {v16.16b - v18.16b}, [%[p0]] \n\t"
582 /* B.4 (CQE 1) adjust CRC length. */
583 "sub v21.8h, v21.8h, %[crc_adj].8h \n\t"
584 /* C.1 (CQE 1) generate final structure for mbuf. */
585 "tbl v13.16b, {v21.16b}, %[mb_shuf_m].16b \n\t"
586 /* B.2 (CQE 0) move the block having op_own. */
587 "mov v19.16b, %[c0].16b \n\t"
588 /* A.1 load mbuf pointers. */
589 "ld1 {v24.2d - v25.2d}, [%[elts_p]] \n\t"
590 /* B.3 (CQE 0) extract 16B fields. */
591 "tbl v20.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \n\t"
592 /* B.4 (CQE 0) adjust CRC length. */
593 "sub v20.8h, v20.8h, %[crc_adj].8h \n\t"
594 /* D.1 extract op_own byte. */
595 "tbl %[op_own].8b, {v20.16b - v23.16b}, %[owner_shuf_m].8b \n\t"
596 /* C.2 (CQE 3) adjust flow mark. */
597 "add v15.4s, v15.4s, %[flow_mark_adj].4s \n\t"
598 /* C.3 (CQE 3) fill in mbuf - rx_descriptor_fields1. */
599 "st1 {v15.2d}, [%[e3]] \n\t"
600 /* C.2 (CQE 2) adjust flow mark. */
601 "add v14.4s, v14.4s, %[flow_mark_adj].4s \n\t"
602 /* C.3 (CQE 2) fill in mbuf - rx_descriptor_fields1. */
603 "st1 {v14.2d}, [%[e2]] \n\t"
604 /* C.1 (CQE 0) generate final structure for mbuf. */
605 "tbl v12.16b, {v20.16b}, %[mb_shuf_m].16b \n\t"
606 /* C.2 (CQE 1) adjust flow mark. */
607 "add v13.4s, v13.4s, %[flow_mark_adj].4s \n\t"
608 /* C.3 (CQE 1) fill in mbuf - rx_descriptor_fields1. */
609 "st1 {v13.2d}, [%[e1]] \n\t"
610 #ifdef MLX5_PMD_SOFT_COUNTERS
611 /* Extract byte_cnt. */
612 "tbl %[byte_cnt].8b, {v20.16b - v23.16b}, %[len_shuf_m].8b \n\t"
614 /* Extract ptype_info. */
615 "tbl %[ptype_info].16b, {v20.16b - v23.16b}, %[ptype_shuf_m].16b \n\t"
616 /* Extract flow_tag. */
617 "tbl %[flow_tag].16b, {v20.16b - v23.16b}, %[ftag_shuf_m].16b \n\t"
618 /* A.2 copy mbuf pointers. */
619 "st1 {v24.2d - v25.2d}, [%[pkts_p]] \n\t"
620 /* C.2 (CQE 0) adjust flow mark. */
621 "add v12.4s, v12.4s, %[flow_mark_adj].4s \n\t"
622 /* C.3 (CQE 1) fill in mbuf - rx_descriptor_fields1. */
623 "st1 {v12.2d}, [%[e0]] \n\t"
624 :[op_own]"=&w"(op_own),
625 [byte_cnt]"=&w"(byte_cnt),
626 [ptype_info]"=&w"(ptype_info),
627 [flow_tag]"=&w"(flow_tag)
628 :[p3]"r"(p3), [p2]"r"(p2), [p1]"r"(p1), [p0]"r"(p0),
629 [e3]"r"(e3), [e2]"r"(e2), [e1]"r"(e1), [e0]"r"(e0),
630 [c3]"w"(c3), [c2]"w"(c2), [c1]"w"(c1), [c0]"w"(c0),
633 [cqe_shuf_m]"w"(cqe_shuf_m),
634 [mb_shuf_m]"w"(mb_shuf_m),
635 [owner_shuf_m]"w"(owner_shuf_m),
636 [len_shuf_m]"w"(len_shuf_m),
637 [ptype_shuf_m]"w"(ptype_shuf_m),
638 [ftag_shuf_m]"w"(ftag_shuf_m),
639 [crc_adj]"w"(crc_adj),
640 [flow_mark_adj]"w"(flow_mark_adj)
642 "v12", "v13", "v14", "v15",
643 "v16", "v17", "v18", "v19",
644 "v20", "v21", "v22", "v23",
646 /* D.2 flip owner bit to mark CQEs from last round. */
647 owner_mask = vand_u16(op_own, owner_check);
648 owner_mask = vceq_u16(owner_mask, ownership);
649 /* D.3 get mask for invalidated CQEs. */
650 opcode = vand_u16(op_own, opcode_check);
651 invalid_mask = vceq_u16(opcode_check, opcode);
652 /* E.1 find compressed CQE format. */
653 comp_mask = vand_u16(op_own, format_check);
654 comp_mask = vceq_u16(comp_mask, format_check);
655 /* D.4 mask out beyond boundary. */
656 invalid_mask = vorr_u16(invalid_mask, mask);
657 /* D.5 merge invalid_mask with invalid owner. */
658 invalid_mask = vorr_u16(invalid_mask, owner_mask);
659 /* E.2 mask out invalid entries. */
660 comp_mask = vbic_u16(comp_mask, invalid_mask);
661 /* E.3 get the first compressed CQE. */
662 comp_idx = __builtin_clzl(vget_lane_u64(vreinterpret_u64_u16(
664 (sizeof(uint16_t) * 8);
665 /* D.6 mask out entries after the compressed CQE. */
666 mask = vcreate_u16(comp_idx < MLX5_VPMD_DESCS_PER_LOOP ?
667 -1UL >> (comp_idx * sizeof(uint16_t) * 8) :
669 invalid_mask = vorr_u16(invalid_mask, mask);
670 /* D.7 count non-compressed valid CQEs. */
671 n = __builtin_clzl(vget_lane_u64(vreinterpret_u64_u16(
672 invalid_mask), 0)) / (sizeof(uint16_t) * 8);
674 /* D.2 get the final invalid mask. */
675 mask = vcreate_u16(n < MLX5_VPMD_DESCS_PER_LOOP ?
676 -1UL >> (n * sizeof(uint16_t) * 8) : 0);
677 invalid_mask = vorr_u16(invalid_mask, mask);
678 /* D.3 check error in opcode. */
679 opcode = vceq_u16(resp_err_check, opcode);
680 opcode = vbic_u16(opcode, invalid_mask);
681 /* D.4 mark if any error is set */
682 *err |= vget_lane_u64(vreinterpret_u64_u16(opcode), 0);
683 /* C.4 fill in mbuf - rearm_data and packet_type. */
684 rxq_cq_to_ptype_oflags_v(rxq, ptype_info, flow_tag,
686 if (rxq->hw_timestamp) {
687 elts[pos]->timestamp =
689 container_of(p0, struct mlx5_cqe,
690 pkt_info)->timestamp);
691 elts[pos + 1]->timestamp =
693 container_of(p1, struct mlx5_cqe,
694 pkt_info)->timestamp);
695 elts[pos + 2]->timestamp =
697 container_of(p2, struct mlx5_cqe,
698 pkt_info)->timestamp);
699 elts[pos + 3]->timestamp =
701 container_of(p3, struct mlx5_cqe,
702 pkt_info)->timestamp);
704 if (rte_flow_dynf_metadata_avail()) {
705 /* This code is subject for futher optimization. */
706 *RTE_FLOW_DYNF_METADATA(elts[pos]) =
707 container_of(p0, struct mlx5_cqe,
708 pkt_info)->flow_table_metadata;
709 *RTE_FLOW_DYNF_METADATA(elts[pos + 1]) =
710 container_of(p1, struct mlx5_cqe,
711 pkt_info)->flow_table_metadata;
712 *RTE_FLOW_DYNF_METADATA(elts[pos + 2]) =
713 container_of(p2, struct mlx5_cqe,
714 pkt_info)->flow_table_metadata;
715 *RTE_FLOW_DYNF_METADATA(elts[pos + 3]) =
716 container_of(p3, struct mlx5_cqe,
717 pkt_info)->flow_table_metadata;
718 if (*RTE_FLOW_DYNF_METADATA(elts[pos]))
719 elts[pos]->ol_flags |= PKT_RX_DYNF_METADATA;
720 if (*RTE_FLOW_DYNF_METADATA(elts[pos + 1]))
721 elts[pos + 1]->ol_flags |= PKT_RX_DYNF_METADATA;
722 if (*RTE_FLOW_DYNF_METADATA(elts[pos + 2]))
723 elts[pos + 2]->ol_flags |= PKT_RX_DYNF_METADATA;
724 if (*RTE_FLOW_DYNF_METADATA(elts[pos + 3]))
725 elts[pos + 3]->ol_flags |= PKT_RX_DYNF_METADATA;
727 #ifdef MLX5_PMD_SOFT_COUNTERS
728 /* Add up received bytes count. */
729 byte_cnt = vbic_u16(byte_cnt, invalid_mask);
730 rcvd_byte += vget_lane_u64(vpaddl_u32(vpaddl_u16(byte_cnt)), 0);
733 * Break the loop unless more valid CQE is expected, or if
734 * there's a compressed CQE.
736 if (n != MLX5_VPMD_DESCS_PER_LOOP)
739 /* If no new CQE seen, return without updating cq_db. */
740 if (unlikely(!nocmp_n && comp_idx == MLX5_VPMD_DESCS_PER_LOOP))
742 /* Update the consumer indexes for non-compressed CQEs. */
743 MLX5_ASSERT(nocmp_n <= pkts_n);
744 rxq->cq_ci += nocmp_n;
745 rxq->rq_pi += nocmp_n;
747 #ifdef MLX5_PMD_SOFT_COUNTERS
748 rxq->stats.ipackets += nocmp_n;
749 rxq->stats.ibytes += rcvd_byte;
751 /* Decompress the last CQE if compressed. */
752 if (comp_idx < MLX5_VPMD_DESCS_PER_LOOP && comp_idx == n) {
753 MLX5_ASSERT(comp_idx == (nocmp_n % MLX5_VPMD_DESCS_PER_LOOP));
754 rxq->decompressed = rxq_cq_decompress_v(rxq, &cq[nocmp_n],
756 /* Return more packets if needed. */
757 if (nocmp_n < pkts_n) {
758 uint16_t n = rxq->decompressed;
760 n = RTE_MIN(n, pkts_n - nocmp_n);
761 rxq_copy_mbuf_v(rxq, &pkts[nocmp_n], n);
764 rxq->decompressed -= n;
768 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
772 #endif /* RTE_PMD_MLX5_RXTX_VEC_NEON_H_ */