1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2017 6WIND S.A.
3 * Copyright 2017 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_RXTX_VEC_NEON_H_
7 #define RTE_PMD_MLX5_RXTX_VEC_NEON_H_
15 #include <rte_mempool.h>
16 #include <rte_prefetch.h>
20 #include "mlx5_defs.h"
22 #include "mlx5_utils.h"
23 #include "mlx5_rxtx.h"
24 #include "mlx5_rxtx_vec.h"
25 #include "mlx5_autoconf.h"
27 #pragma GCC diagnostic ignored "-Wcast-qual"
30 * Store free buffers to RX SW ring.
33 * Pointer to RX queue structure.
35 * Pointer to array of packets to be stored.
37 * Number of packets to be stored.
40 rxq_copy_mbuf_v(struct mlx5_rxq_data *rxq, struct rte_mbuf **pkts, uint16_t n)
42 const uint16_t q_mask = (1 << rxq->elts_n) - 1;
43 struct rte_mbuf **elts = &(*rxq->elts)[rxq->rq_pi & q_mask];
47 for (pos = 0; pos < p; pos += 2) {
50 mbp = vld1q_u64((void *)&elts[pos]);
51 vst1q_u64((void *)&pkts[pos], mbp);
54 pkts[pos] = elts[pos];
58 * Decompress a compressed completion and fill in mbufs in RX SW ring with data
59 * extracted from the title completion descriptor.
62 * Pointer to RX queue structure.
64 * Pointer to completion array having a compressed completion at first.
66 * Pointer to SW ring to be filled. The first mbuf has to be pre-built from
67 * the title completion descriptor to be copied to the rest of mbufs.
70 * Number of mini-CQEs successfully decompressed.
72 static inline uint16_t
73 rxq_cq_decompress_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq,
74 struct rte_mbuf **elts)
76 volatile struct mlx5_mini_cqe8 *mcq = (void *)&(cq + 1)->pkt_info;
77 struct rte_mbuf *t_pkt = elts[0]; /* Title packet is pre-built. */
81 /* Mask to shuffle from extracted mini CQE to mbuf. */
82 const uint8x16_t mcqe_shuf_m1 = {
83 -1, -1, -1, -1, /* skip packet_type */
84 7, 6, -1, -1, /* pkt_len, bswap16 */
85 7, 6, /* data_len, bswap16 */
86 -1, -1, /* skip vlan_tci */
87 3, 2, 1, 0 /* hash.rss, bswap32 */
89 const uint8x16_t mcqe_shuf_m2 = {
90 -1, -1, -1, -1, /* skip packet_type */
91 15, 14, -1, -1, /* pkt_len, bswap16 */
92 15, 14, /* data_len, bswap16 */
93 -1, -1, /* skip vlan_tci */
94 11, 10, 9, 8 /* hash.rss, bswap32 */
96 /* Restore the compressed count. Must be 16 bits. */
97 const uint16_t mcqe_n = t_pkt->data_len +
98 (rxq->crc_present * RTE_ETHER_CRC_LEN);
99 const uint64x2_t rearm =
100 vld1q_u64((void *)&t_pkt->rearm_data);
101 const uint32x4_t rxdf_mask = {
102 0xffffffff, /* packet_type */
103 0, /* skip pkt_len */
104 0xffff0000, /* vlan_tci, skip data_len */
105 0, /* skip hash.rss */
107 const uint8x16_t rxdf =
108 vandq_u8(vld1q_u8((void *)&t_pkt->rx_descriptor_fields1),
109 vreinterpretq_u8_u32(rxdf_mask));
110 const uint16x8_t crc_adj = {
112 rxq->crc_present * RTE_ETHER_CRC_LEN, 0,
113 rxq->crc_present * RTE_ETHER_CRC_LEN, 0,
116 const uint32_t flow_tag = t_pkt->hash.fdir.hi;
117 #ifdef MLX5_PMD_SOFT_COUNTERS
118 uint32_t rcvd_byte = 0;
120 /* Mask to shuffle byte_cnt to add up stats. Do bswap16 for all. */
121 const uint8x8_t len_shuf_m = {
123 15, 14, /* 2nd mCQE */
124 23, 22, /* 3rd mCQE */
125 31, 30 /* 4th mCQE */
129 * A. load mCQEs into a 128bit register.
130 * B. store rearm data to mbuf.
131 * C. combine data from mCQEs with rx_descriptor_fields1.
132 * D. store rx_descriptor_fields1.
133 * E. store flow tag (rte_flow mark).
135 for (pos = 0; pos < mcqe_n; ) {
136 uint8_t *p = (void *)&mcq[pos % 8];
137 uint8_t *e0 = (void *)&elts[pos]->rearm_data;
138 uint8_t *e1 = (void *)&elts[pos + 1]->rearm_data;
139 uint8_t *e2 = (void *)&elts[pos + 2]->rearm_data;
140 uint8_t *e3 = (void *)&elts[pos + 3]->rearm_data;
142 #ifdef MLX5_PMD_SOFT_COUNTERS
143 uint16x4_t invalid_mask =
144 vcreate_u16(mcqe_n - pos < MLX5_VPMD_DESCS_PER_LOOP ?
145 -1UL << ((mcqe_n - pos) *
146 sizeof(uint16_t) * 8) : 0);
148 for (i = 0; i < MLX5_VPMD_DESCS_PER_LOOP; ++i)
149 if (likely(pos + i < mcqe_n))
150 rte_prefetch0((void *)(cq + pos + i));
152 /* A.1 load mCQEs into a 128bit register. */
153 "ld1 {v16.16b - v17.16b}, [%[mcq]] \n\t"
154 /* B.1 store rearm data to mbuf. */
155 "st1 {%[rearm].2d}, [%[e0]] \n\t"
156 "add %[e0], %[e0], #16 \n\t"
157 "st1 {%[rearm].2d}, [%[e1]] \n\t"
158 "add %[e1], %[e1], #16 \n\t"
159 /* C.1 combine data from mCQEs with rx_descriptor_fields1. */
160 "tbl v18.16b, {v16.16b}, %[mcqe_shuf_m1].16b \n\t"
161 "tbl v19.16b, {v16.16b}, %[mcqe_shuf_m2].16b \n\t"
162 "sub v18.8h, v18.8h, %[crc_adj].8h \n\t"
163 "sub v19.8h, v19.8h, %[crc_adj].8h \n\t"
164 "orr v18.16b, v18.16b, %[rxdf].16b \n\t"
165 "orr v19.16b, v19.16b, %[rxdf].16b \n\t"
166 /* D.1 store rx_descriptor_fields1. */
167 "st1 {v18.2d}, [%[e0]] \n\t"
168 "st1 {v19.2d}, [%[e1]] \n\t"
169 /* B.1 store rearm data to mbuf. */
170 "st1 {%[rearm].2d}, [%[e2]] \n\t"
171 "add %[e2], %[e2], #16 \n\t"
172 "st1 {%[rearm].2d}, [%[e3]] \n\t"
173 "add %[e3], %[e3], #16 \n\t"
174 /* C.1 combine data from mCQEs with rx_descriptor_fields1. */
175 "tbl v18.16b, {v17.16b}, %[mcqe_shuf_m1].16b \n\t"
176 "tbl v19.16b, {v17.16b}, %[mcqe_shuf_m2].16b \n\t"
177 "sub v18.8h, v18.8h, %[crc_adj].8h \n\t"
178 "sub v19.8h, v19.8h, %[crc_adj].8h \n\t"
179 "orr v18.16b, v18.16b, %[rxdf].16b \n\t"
180 "orr v19.16b, v19.16b, %[rxdf].16b \n\t"
181 /* D.1 store rx_descriptor_fields1. */
182 "st1 {v18.2d}, [%[e2]] \n\t"
183 "st1 {v19.2d}, [%[e3]] \n\t"
184 #ifdef MLX5_PMD_SOFT_COUNTERS
185 "tbl %[byte_cnt].8b, {v16.16b - v17.16b}, %[len_shuf_m].8b \n\t"
187 :[byte_cnt]"=&w"(byte_cnt)
191 [e3]"r"(e3), [e2]"r"(e2), [e1]"r"(e1), [e0]"r"(e0),
192 [mcqe_shuf_m1]"w"(mcqe_shuf_m1),
193 [mcqe_shuf_m2]"w"(mcqe_shuf_m2),
194 [crc_adj]"w"(crc_adj),
195 [len_shuf_m]"w"(len_shuf_m)
196 :"memory", "v16", "v17", "v18", "v19");
197 #ifdef MLX5_PMD_SOFT_COUNTERS
198 byte_cnt = vbic_u16(byte_cnt, invalid_mask);
199 rcvd_byte += vget_lane_u64(vpaddl_u32(vpaddl_u16(byte_cnt)), 0);
202 /* E.1 store flow tag (rte_flow mark). */
203 elts[pos]->hash.fdir.hi = flow_tag;
204 elts[pos + 1]->hash.fdir.hi = flow_tag;
205 elts[pos + 2]->hash.fdir.hi = flow_tag;
206 elts[pos + 3]->hash.fdir.hi = flow_tag;
208 if (rxq->dynf_meta) {
209 int32_t offs = rxq->flow_meta_offset;
210 const uint32_t meta =
211 *RTE_MBUF_DYNFIELD(t_pkt, offs, uint32_t *);
213 /* Check if title packet has valid metadata. */
215 MLX5_ASSERT(t_pkt->ol_flags &
216 rxq->flow_meta_mask);
217 *RTE_MBUF_DYNFIELD(elts[pos], offs,
219 *RTE_MBUF_DYNFIELD(elts[pos + 1], offs,
221 *RTE_MBUF_DYNFIELD(elts[pos + 2], offs,
223 *RTE_MBUF_DYNFIELD(elts[pos + 3], offs,
227 pos += MLX5_VPMD_DESCS_PER_LOOP;
228 /* Move to next CQE and invalidate consumed CQEs. */
229 if (!(pos & 0x7) && pos < mcqe_n) {
230 mcq = (void *)&(cq + pos)->pkt_info;
231 for (i = 0; i < 8; ++i)
232 cq[inv++].op_own = MLX5_CQE_INVALIDATE;
235 /* Invalidate the rest of CQEs. */
236 for (; inv < mcqe_n; ++inv)
237 cq[inv].op_own = MLX5_CQE_INVALIDATE;
238 #ifdef MLX5_PMD_SOFT_COUNTERS
239 rxq->stats.ipackets += mcqe_n;
240 rxq->stats.ibytes += rcvd_byte;
242 rxq->cq_ci += mcqe_n;
247 * Calculate packet type and offload flag for mbuf and store it.
250 * Pointer to RX queue structure.
252 * Array of four 4bytes packet type info extracted from the original
253 * completion descriptor.
255 * Array of four 4bytes flow ID extracted from the original completion
258 * Opcode vector having responder error status. Each field is 4B.
260 * Pointer to array of packets to be filled.
263 rxq_cq_to_ptype_oflags_v(struct mlx5_rxq_data *rxq,
264 uint32x4_t ptype_info, uint32x4_t flow_tag,
265 uint16x4_t op_err, struct rte_mbuf **pkts)
268 uint32x4_t pinfo, cv_flags;
269 uint32x4_t ol_flags =
270 vdupq_n_u32(rxq->rss_hash * PKT_RX_RSS_HASH |
271 rxq->hw_timestamp * PKT_RX_TIMESTAMP);
272 const uint32x4_t ptype_ol_mask = { 0x106, 0x106, 0x106, 0x106 };
273 const uint8x16_t cv_flag_sel = {
275 (uint8_t)(PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED),
276 (uint8_t)(PKT_RX_IP_CKSUM_GOOD >> 1),
278 (uint8_t)(PKT_RX_L4_CKSUM_GOOD >> 1),
280 (uint8_t)((PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD) >> 1),
281 0, 0, 0, 0, 0, 0, 0, 0, 0
283 const uint32x4_t cv_mask =
284 vdupq_n_u32(PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD |
285 PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED);
286 const uint64x2_t mbuf_init = vld1q_u64
287 ((const uint64_t *)&rxq->mbuf_initializer);
288 uint64x2_t rearm0, rearm1, rearm2, rearm3;
289 uint8_t pt_idx0, pt_idx1, pt_idx2, pt_idx3;
292 const uint32x4_t ft_def = vdupq_n_u32(MLX5_FLOW_MARK_DEFAULT);
293 const uint32x4_t fdir_flags = vdupq_n_u32(PKT_RX_FDIR);
294 uint32x4_t fdir_id_flags = vdupq_n_u32(PKT_RX_FDIR_ID);
295 uint32x4_t invalid_mask;
297 /* Check if flow tag is non-zero then set PKT_RX_FDIR. */
298 invalid_mask = vceqzq_u32(flow_tag);
299 ol_flags = vorrq_u32(ol_flags,
300 vbicq_u32(fdir_flags, invalid_mask));
301 /* Mask out invalid entries. */
302 fdir_id_flags = vbicq_u32(fdir_id_flags, invalid_mask);
303 /* Check if flow tag MLX5_FLOW_MARK_DEFAULT. */
304 ol_flags = vorrq_u32(ol_flags,
305 vbicq_u32(fdir_id_flags,
306 vceqq_u32(flow_tag, ft_def)));
309 * ptype_info has the following:
313 * bit[11:10] = l3_hdr_type
314 * bit[14:12] = l4_hdr_type
317 * bit[17] = outer_l3_type
319 ptype = vshrn_n_u32(ptype_info, 10);
320 /* Errored packets will have RTE_PTYPE_ALL_MASK. */
321 ptype = vorr_u16(ptype, op_err);
322 pt_idx0 = vget_lane_u8(vreinterpret_u8_u16(ptype), 6);
323 pt_idx1 = vget_lane_u8(vreinterpret_u8_u16(ptype), 4);
324 pt_idx2 = vget_lane_u8(vreinterpret_u8_u16(ptype), 2);
325 pt_idx3 = vget_lane_u8(vreinterpret_u8_u16(ptype), 0);
326 pkts[0]->packet_type = mlx5_ptype_table[pt_idx0] |
327 !!(pt_idx0 & (1 << 6)) * rxq->tunnel;
328 pkts[1]->packet_type = mlx5_ptype_table[pt_idx1] |
329 !!(pt_idx1 & (1 << 6)) * rxq->tunnel;
330 pkts[2]->packet_type = mlx5_ptype_table[pt_idx2] |
331 !!(pt_idx2 & (1 << 6)) * rxq->tunnel;
332 pkts[3]->packet_type = mlx5_ptype_table[pt_idx3] |
333 !!(pt_idx3 & (1 << 6)) * rxq->tunnel;
334 /* Fill flags for checksum and VLAN. */
335 pinfo = vandq_u32(ptype_info, ptype_ol_mask);
336 pinfo = vreinterpretq_u32_u8(
337 vqtbl1q_u8(cv_flag_sel, vreinterpretq_u8_u32(pinfo)));
338 /* Locate checksum flags at byte[2:1] and merge with VLAN flags. */
339 cv_flags = vshlq_n_u32(pinfo, 9);
340 cv_flags = vorrq_u32(pinfo, cv_flags);
341 /* Move back flags to start from byte[0]. */
342 cv_flags = vshrq_n_u32(cv_flags, 8);
343 /* Mask out garbage bits. */
344 cv_flags = vandq_u32(cv_flags, cv_mask);
345 /* Merge to ol_flags. */
346 ol_flags = vorrq_u32(ol_flags, cv_flags);
347 /* Merge mbuf_init and ol_flags, and store. */
348 rearm0 = vreinterpretq_u64_u32(vsetq_lane_u32
349 (vgetq_lane_u32(ol_flags, 3),
350 vreinterpretq_u32_u64(mbuf_init), 2));
351 rearm1 = vreinterpretq_u64_u32(vsetq_lane_u32
352 (vgetq_lane_u32(ol_flags, 2),
353 vreinterpretq_u32_u64(mbuf_init), 2));
354 rearm2 = vreinterpretq_u64_u32(vsetq_lane_u32
355 (vgetq_lane_u32(ol_flags, 1),
356 vreinterpretq_u32_u64(mbuf_init), 2));
357 rearm3 = vreinterpretq_u64_u32(vsetq_lane_u32
358 (vgetq_lane_u32(ol_flags, 0),
359 vreinterpretq_u32_u64(mbuf_init), 2));
361 vst1q_u64((void *)&pkts[0]->rearm_data, rearm0);
362 vst1q_u64((void *)&pkts[1]->rearm_data, rearm1);
363 vst1q_u64((void *)&pkts[2]->rearm_data, rearm2);
364 vst1q_u64((void *)&pkts[3]->rearm_data, rearm3);
368 * Receive burst of packets. An errored completion also consumes a mbuf, but the
369 * packet_type is set to be RTE_PTYPE_ALL_MASK. Marked mbufs should be freed
370 * before returning to application.
373 * Pointer to RX queue structure.
375 * Array to store received packets.
377 * Maximum number of packets in array.
379 * Pointer to a flag. Set non-zero value if pkts array has at least one error
382 * Pointer to a boolean. Set true if no new CQE seen.
385 * Number of packets received including errors (<= pkts_n).
387 static inline uint16_t
388 rxq_burst_v(struct mlx5_rxq_data *rxq, struct rte_mbuf **pkts, uint16_t pkts_n,
389 uint64_t *err, bool *no_cq)
391 const uint16_t q_n = 1 << rxq->cqe_n;
392 const uint16_t q_mask = q_n - 1;
393 volatile struct mlx5_cqe *cq;
394 struct rte_mbuf **elts;
398 uint64_t comp_idx = MLX5_VPMD_DESCS_PER_LOOP;
399 uint16_t nocmp_n = 0;
400 uint16_t rcvd_pkt = 0;
401 unsigned int cq_idx = rxq->cq_ci & q_mask;
402 unsigned int elts_idx;
403 const uint16x4_t ownership = vdup_n_u16(!(rxq->cq_ci & (q_mask + 1)));
404 const uint16x4_t owner_check = vcreate_u16(0x0001000100010001);
405 const uint16x4_t opcode_check = vcreate_u16(0x00f000f000f000f0);
406 const uint16x4_t format_check = vcreate_u16(0x000c000c000c000c);
407 const uint16x4_t resp_err_check = vcreate_u16(0x00e000e000e000e0);
408 #ifdef MLX5_PMD_SOFT_COUNTERS
409 uint32_t rcvd_byte = 0;
411 /* Mask to generate 16B length vector. */
412 const uint8x8_t len_shuf_m = {
413 52, 53, /* 4th CQE */
414 36, 37, /* 3rd CQE */
415 20, 21, /* 2nd CQE */
418 /* Mask to extract 16B data from a 64B CQE. */
419 const uint8x16_t cqe_shuf_m = {
420 28, 29, /* hdr_type_etc */
423 47, 46, /* byte_cnt, bswap16 */
424 31, 30, /* vlan_info, bswap16 */
425 15, 14, 13, 12, /* rx_hash_res, bswap32 */
426 57, 58, 59, /* flow_tag */
429 /* Mask to generate 16B data for mbuf. */
430 const uint8x16_t mb_shuf_m = {
431 4, 5, -1, -1, /* pkt_len */
434 8, 9, 10, 11, /* hash.rss */
435 12, 13, 14, -1 /* hash.fdir.hi */
437 /* Mask to generate 16B owner vector. */
438 const uint8x8_t owner_shuf_m = {
439 63, -1, /* 4th CQE */
440 47, -1, /* 3rd CQE */
441 31, -1, /* 2nd CQE */
444 /* Mask to generate a vector having packet_type/ol_flags. */
445 const uint8x16_t ptype_shuf_m = {
446 48, 49, 50, -1, /* 4th CQE */
447 32, 33, 34, -1, /* 3rd CQE */
448 16, 17, 18, -1, /* 2nd CQE */
449 0, 1, 2, -1 /* 1st CQE */
451 /* Mask to generate a vector having flow tags. */
452 const uint8x16_t ftag_shuf_m = {
453 60, 61, 62, -1, /* 4th CQE */
454 44, 45, 46, -1, /* 3rd CQE */
455 28, 29, 30, -1, /* 2nd CQE */
456 12, 13, 14, -1 /* 1st CQE */
458 const uint16x8_t crc_adj = {
459 0, 0, rxq->crc_present * RTE_ETHER_CRC_LEN, 0, 0, 0, 0, 0
461 const uint32x4_t flow_mark_adj = { 0, 0, 0, rxq->mark * (-1) };
463 MLX5_ASSERT(rxq->sges_n == 0);
464 MLX5_ASSERT(rxq->cqe_n == rxq->elts_n);
465 cq = &(*rxq->cqes)[cq_idx];
466 rte_prefetch_non_temporal(cq);
467 rte_prefetch_non_temporal(cq + 1);
468 rte_prefetch_non_temporal(cq + 2);
469 rte_prefetch_non_temporal(cq + 3);
470 pkts_n = RTE_MIN(pkts_n, MLX5_VPMD_RX_MAX_BURST);
471 repl_n = q_n - (rxq->rq_ci - rxq->rq_pi);
472 if (repl_n >= rxq->rq_repl_thresh)
473 mlx5_rx_replenish_bulk_mbuf(rxq, repl_n);
474 /* See if there're unreturned mbufs from compressed CQE. */
475 rcvd_pkt = rxq->decompressed;
477 rcvd_pkt = RTE_MIN(rcvd_pkt, pkts_n);
478 rxq_copy_mbuf_v(rxq, pkts, rcvd_pkt);
479 rxq->rq_pi += rcvd_pkt;
481 rxq->decompressed -= rcvd_pkt;
483 elts_idx = rxq->rq_pi & q_mask;
484 elts = &(*rxq->elts)[elts_idx];
485 /* Not to overflow pkts array. */
486 pkts_n = RTE_ALIGN_FLOOR(pkts_n - rcvd_pkt, MLX5_VPMD_DESCS_PER_LOOP);
487 /* Not to cross queue end. */
488 pkts_n = RTE_MIN(pkts_n, q_n - elts_idx);
489 pkts_n = RTE_MIN(pkts_n, q_n - cq_idx);
494 /* At this point, there shouldn't be any remained packets. */
495 MLX5_ASSERT(rxq->decompressed == 0);
497 * Note that vectors have reverse order - {v3, v2, v1, v0}, because
498 * there's no instruction to count trailing zeros. __builtin_clzl() is
501 * A. copy 4 mbuf pointers from elts ring to returing pkts.
502 * B. load 64B CQE and extract necessary fields
503 * Final 16bytes cqes[] extracted from original 64bytes CQE has the
504 * following structure:
506 * uint16_t hdr_type_etc;
510 * uint16_t vlan_info;
511 * uint32_t rx_has_res;
512 * uint8_t flow_tag[3];
517 * E. find compressed CQE.
521 pos += MLX5_VPMD_DESCS_PER_LOOP) {
523 uint16x4_t opcode, owner_mask, invalid_mask;
524 uint16x4_t comp_mask;
527 uint32x4_t ptype_info, flow_tag;
528 register uint64x2_t c0, c1, c2, c3;
529 uint8_t *p0, *p1, *p2, *p3;
530 uint8_t *e0 = (void *)&elts[pos]->pkt_len;
531 uint8_t *e1 = (void *)&elts[pos + 1]->pkt_len;
532 uint8_t *e2 = (void *)&elts[pos + 2]->pkt_len;
533 uint8_t *e3 = (void *)&elts[pos + 3]->pkt_len;
534 void *elts_p = (void *)&elts[pos];
535 void *pkts_p = (void *)&pkts[pos];
537 /* A.0 do not cross the end of CQ. */
538 mask = vcreate_u16(pkts_n - pos < MLX5_VPMD_DESCS_PER_LOOP ?
539 -1UL >> ((pkts_n - pos) *
540 sizeof(uint16_t) * 8) : 0);
541 p0 = (void *)&cq[pos].pkt_info;
542 p1 = p0 + (pkts_n - pos > 1) * sizeof(struct mlx5_cqe);
543 p2 = p1 + (pkts_n - pos > 2) * sizeof(struct mlx5_cqe);
544 p3 = p2 + (pkts_n - pos > 3) * sizeof(struct mlx5_cqe);
545 /* B.0 (CQE 3) load a block having op_own. */
546 c3 = vld1q_u64((uint64_t *)(p3 + 48));
547 /* B.0 (CQE 2) load a block having op_own. */
548 c2 = vld1q_u64((uint64_t *)(p2 + 48));
549 /* B.0 (CQE 1) load a block having op_own. */
550 c1 = vld1q_u64((uint64_t *)(p1 + 48));
551 /* B.0 (CQE 0) load a block having op_own. */
552 c0 = vld1q_u64((uint64_t *)(p0 + 48));
553 /* Synchronize for loading the rest of blocks. */
555 /* Prefetch next 4 CQEs. */
556 if (pkts_n - pos >= 2 * MLX5_VPMD_DESCS_PER_LOOP) {
557 unsigned int next = pos + MLX5_VPMD_DESCS_PER_LOOP;
558 rte_prefetch_non_temporal(&cq[next]);
559 rte_prefetch_non_temporal(&cq[next + 1]);
560 rte_prefetch_non_temporal(&cq[next + 2]);
561 rte_prefetch_non_temporal(&cq[next + 3]);
564 /* B.1 (CQE 3) load the rest of blocks. */
565 "ld1 {v16.16b - v18.16b}, [%[p3]] \n\t"
566 /* B.2 (CQE 3) move the block having op_own. */
567 "mov v19.16b, %[c3].16b \n\t"
568 /* B.3 (CQE 3) extract 16B fields. */
569 "tbl v23.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \n\t"
570 /* B.1 (CQE 2) load the rest of blocks. */
571 "ld1 {v16.16b - v18.16b}, [%[p2]] \n\t"
572 /* B.4 (CQE 3) adjust CRC length. */
573 "sub v23.8h, v23.8h, %[crc_adj].8h \n\t"
574 /* C.1 (CQE 3) generate final structure for mbuf. */
575 "tbl v15.16b, {v23.16b}, %[mb_shuf_m].16b \n\t"
576 /* B.2 (CQE 2) move the block having op_own. */
577 "mov v19.16b, %[c2].16b \n\t"
578 /* B.3 (CQE 2) extract 16B fields. */
579 "tbl v22.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \n\t"
580 /* B.1 (CQE 1) load the rest of blocks. */
581 "ld1 {v16.16b - v18.16b}, [%[p1]] \n\t"
582 /* B.4 (CQE 2) adjust CRC length. */
583 "sub v22.8h, v22.8h, %[crc_adj].8h \n\t"
584 /* C.1 (CQE 2) generate final structure for mbuf. */
585 "tbl v14.16b, {v22.16b}, %[mb_shuf_m].16b \n\t"
586 /* B.2 (CQE 1) move the block having op_own. */
587 "mov v19.16b, %[c1].16b \n\t"
588 /* B.3 (CQE 1) extract 16B fields. */
589 "tbl v21.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \n\t"
590 /* B.1 (CQE 0) load the rest of blocks. */
591 "ld1 {v16.16b - v18.16b}, [%[p0]] \n\t"
592 /* B.4 (CQE 1) adjust CRC length. */
593 "sub v21.8h, v21.8h, %[crc_adj].8h \n\t"
594 /* C.1 (CQE 1) generate final structure for mbuf. */
595 "tbl v13.16b, {v21.16b}, %[mb_shuf_m].16b \n\t"
596 /* B.2 (CQE 0) move the block having op_own. */
597 "mov v19.16b, %[c0].16b \n\t"
598 /* A.1 load mbuf pointers. */
599 "ld1 {v24.2d - v25.2d}, [%[elts_p]] \n\t"
600 /* B.3 (CQE 0) extract 16B fields. */
601 "tbl v20.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \n\t"
602 /* B.4 (CQE 0) adjust CRC length. */
603 "sub v20.8h, v20.8h, %[crc_adj].8h \n\t"
604 /* D.1 extract op_own byte. */
605 "tbl %[op_own].8b, {v20.16b - v23.16b}, %[owner_shuf_m].8b \n\t"
606 /* C.2 (CQE 3) adjust flow mark. */
607 "add v15.4s, v15.4s, %[flow_mark_adj].4s \n\t"
608 /* C.3 (CQE 3) fill in mbuf - rx_descriptor_fields1. */
609 "st1 {v15.2d}, [%[e3]] \n\t"
610 /* C.2 (CQE 2) adjust flow mark. */
611 "add v14.4s, v14.4s, %[flow_mark_adj].4s \n\t"
612 /* C.3 (CQE 2) fill in mbuf - rx_descriptor_fields1. */
613 "st1 {v14.2d}, [%[e2]] \n\t"
614 /* C.1 (CQE 0) generate final structure for mbuf. */
615 "tbl v12.16b, {v20.16b}, %[mb_shuf_m].16b \n\t"
616 /* C.2 (CQE 1) adjust flow mark. */
617 "add v13.4s, v13.4s, %[flow_mark_adj].4s \n\t"
618 /* C.3 (CQE 1) fill in mbuf - rx_descriptor_fields1. */
619 "st1 {v13.2d}, [%[e1]] \n\t"
620 #ifdef MLX5_PMD_SOFT_COUNTERS
621 /* Extract byte_cnt. */
622 "tbl %[byte_cnt].8b, {v20.16b - v23.16b}, %[len_shuf_m].8b \n\t"
624 /* Extract ptype_info. */
625 "tbl %[ptype_info].16b, {v20.16b - v23.16b}, %[ptype_shuf_m].16b \n\t"
626 /* Extract flow_tag. */
627 "tbl %[flow_tag].16b, {v20.16b - v23.16b}, %[ftag_shuf_m].16b \n\t"
628 /* A.2 copy mbuf pointers. */
629 "st1 {v24.2d - v25.2d}, [%[pkts_p]] \n\t"
630 /* C.2 (CQE 0) adjust flow mark. */
631 "add v12.4s, v12.4s, %[flow_mark_adj].4s \n\t"
632 /* C.3 (CQE 1) fill in mbuf - rx_descriptor_fields1. */
633 "st1 {v12.2d}, [%[e0]] \n\t"
634 :[op_own]"=&w"(op_own),
635 [byte_cnt]"=&w"(byte_cnt),
636 [ptype_info]"=&w"(ptype_info),
637 [flow_tag]"=&w"(flow_tag)
638 :[p3]"r"(p3), [p2]"r"(p2), [p1]"r"(p1), [p0]"r"(p0),
639 [e3]"r"(e3), [e2]"r"(e2), [e1]"r"(e1), [e0]"r"(e0),
640 [c3]"w"(c3), [c2]"w"(c2), [c1]"w"(c1), [c0]"w"(c0),
643 [cqe_shuf_m]"w"(cqe_shuf_m),
644 [mb_shuf_m]"w"(mb_shuf_m),
645 [owner_shuf_m]"w"(owner_shuf_m),
646 [len_shuf_m]"w"(len_shuf_m),
647 [ptype_shuf_m]"w"(ptype_shuf_m),
648 [ftag_shuf_m]"w"(ftag_shuf_m),
649 [crc_adj]"w"(crc_adj),
650 [flow_mark_adj]"w"(flow_mark_adj)
652 "v12", "v13", "v14", "v15",
653 "v16", "v17", "v18", "v19",
654 "v20", "v21", "v22", "v23",
656 /* D.2 flip owner bit to mark CQEs from last round. */
657 owner_mask = vand_u16(op_own, owner_check);
658 owner_mask = vceq_u16(owner_mask, ownership);
659 /* D.3 get mask for invalidated CQEs. */
660 opcode = vand_u16(op_own, opcode_check);
661 invalid_mask = vceq_u16(opcode_check, opcode);
662 /* E.1 find compressed CQE format. */
663 comp_mask = vand_u16(op_own, format_check);
664 comp_mask = vceq_u16(comp_mask, format_check);
665 /* D.4 mask out beyond boundary. */
666 invalid_mask = vorr_u16(invalid_mask, mask);
667 /* D.5 merge invalid_mask with invalid owner. */
668 invalid_mask = vorr_u16(invalid_mask, owner_mask);
669 /* E.2 mask out invalid entries. */
670 comp_mask = vbic_u16(comp_mask, invalid_mask);
671 /* E.3 get the first compressed CQE. */
672 comp_idx = __builtin_clzl(vget_lane_u64(vreinterpret_u64_u16(
674 (sizeof(uint16_t) * 8);
675 /* D.6 mask out entries after the compressed CQE. */
676 mask = vcreate_u16(comp_idx < MLX5_VPMD_DESCS_PER_LOOP ?
677 -1UL >> (comp_idx * sizeof(uint16_t) * 8) :
679 invalid_mask = vorr_u16(invalid_mask, mask);
680 /* D.7 count non-compressed valid CQEs. */
681 n = __builtin_clzl(vget_lane_u64(vreinterpret_u64_u16(
682 invalid_mask), 0)) / (sizeof(uint16_t) * 8);
684 /* D.2 get the final invalid mask. */
685 mask = vcreate_u16(n < MLX5_VPMD_DESCS_PER_LOOP ?
686 -1UL >> (n * sizeof(uint16_t) * 8) : 0);
687 invalid_mask = vorr_u16(invalid_mask, mask);
688 /* D.3 check error in opcode. */
689 opcode = vceq_u16(resp_err_check, opcode);
690 opcode = vbic_u16(opcode, invalid_mask);
691 /* D.4 mark if any error is set */
692 *err |= vget_lane_u64(vreinterpret_u64_u16(opcode), 0);
693 /* C.4 fill in mbuf - rearm_data and packet_type. */
694 rxq_cq_to_ptype_oflags_v(rxq, ptype_info, flow_tag,
696 if (rxq->hw_timestamp) {
697 if (rxq->rt_timestamp) {
698 struct mlx5_dev_ctx_shared *sh = rxq->sh;
701 ts = rte_be_to_cpu_64
702 (container_of(p0, struct mlx5_cqe,
703 pkt_info)->timestamp);
704 elts[pos]->timestamp =
705 mlx5_txpp_convert_rx_ts(sh, ts);
706 ts = rte_be_to_cpu_64
707 (container_of(p1, struct mlx5_cqe,
708 pkt_info)->timestamp);
709 elts[pos + 1]->timestamp =
710 mlx5_txpp_convert_rx_ts(sh, ts);
711 ts = rte_be_to_cpu_64
712 (container_of(p2, struct mlx5_cqe,
713 pkt_info)->timestamp);
714 elts[pos + 2]->timestamp =
715 mlx5_txpp_convert_rx_ts(sh, ts);
716 ts = rte_be_to_cpu_64
717 (container_of(p3, struct mlx5_cqe,
718 pkt_info)->timestamp);
719 elts[pos + 3]->timestamp =
720 mlx5_txpp_convert_rx_ts(sh, ts);
722 elts[pos]->timestamp = rte_be_to_cpu_64
723 (container_of(p0, struct mlx5_cqe,
724 pkt_info)->timestamp);
725 elts[pos + 1]->timestamp = rte_be_to_cpu_64
726 (container_of(p1, struct mlx5_cqe,
727 pkt_info)->timestamp);
728 elts[pos + 2]->timestamp = rte_be_to_cpu_64
729 (container_of(p2, struct mlx5_cqe,
730 pkt_info)->timestamp);
731 elts[pos + 3]->timestamp = rte_be_to_cpu_64
732 (container_of(p3, struct mlx5_cqe,
733 pkt_info)->timestamp);
736 if (!!rxq->flow_meta_mask) {
737 /* This code is subject for futher optimization. */
738 int32_t offs = rxq->flow_meta_offset;
740 *RTE_MBUF_DYNFIELD(pkts[pos], offs, uint32_t *) =
741 container_of(p0, struct mlx5_cqe,
742 pkt_info)->flow_table_metadata;
743 *RTE_MBUF_DYNFIELD(pkts[pos], offs, uint32_t *) =
744 container_of(p1, struct mlx5_cqe,
745 pkt_info)->flow_table_metadata;
746 *RTE_MBUF_DYNFIELD(pkts[pos], offs, uint32_t *) =
747 container_of(p2, struct mlx5_cqe,
748 pkt_info)->flow_table_metadata;
749 *RTE_MBUF_DYNFIELD(pkts[pos], offs, uint32_t *) =
750 container_of(p3, struct mlx5_cqe,
751 pkt_info)->flow_table_metadata;
752 if (*RTE_MBUF_DYNFIELD(pkts[pos], offs, uint32_t *))
753 elts[pos]->ol_flags |= rxq->flow_meta_mask;
754 if (*RTE_MBUF_DYNFIELD(pkts[pos + 1], offs, uint32_t *))
755 elts[pos + 1]->ol_flags |= rxq->flow_meta_mask;
756 if (*RTE_MBUF_DYNFIELD(pkts[pos + 2], offs, uint32_t *))
757 elts[pos + 2]->ol_flags |= rxq->flow_meta_mask;
758 if (*RTE_MBUF_DYNFIELD(pkts[pos + 3], offs, uint32_t *))
759 elts[pos + 3]->ol_flags |= rxq->flow_meta_mask;
761 #ifdef MLX5_PMD_SOFT_COUNTERS
762 /* Add up received bytes count. */
763 byte_cnt = vbic_u16(byte_cnt, invalid_mask);
764 rcvd_byte += vget_lane_u64(vpaddl_u32(vpaddl_u16(byte_cnt)), 0);
767 * Break the loop unless more valid CQE is expected, or if
768 * there's a compressed CQE.
770 if (n != MLX5_VPMD_DESCS_PER_LOOP)
773 /* If no new CQE seen, return without updating cq_db. */
774 if (unlikely(!nocmp_n && comp_idx == MLX5_VPMD_DESCS_PER_LOOP)) {
778 /* Update the consumer indexes for non-compressed CQEs. */
779 MLX5_ASSERT(nocmp_n <= pkts_n);
780 rxq->cq_ci += nocmp_n;
781 rxq->rq_pi += nocmp_n;
783 #ifdef MLX5_PMD_SOFT_COUNTERS
784 rxq->stats.ipackets += nocmp_n;
785 rxq->stats.ibytes += rcvd_byte;
787 /* Decompress the last CQE if compressed. */
788 if (comp_idx < MLX5_VPMD_DESCS_PER_LOOP && comp_idx == n) {
789 MLX5_ASSERT(comp_idx == (nocmp_n % MLX5_VPMD_DESCS_PER_LOOP));
790 rxq->decompressed = rxq_cq_decompress_v(rxq, &cq[nocmp_n],
792 /* Return more packets if needed. */
793 if (nocmp_n < pkts_n) {
794 uint16_t n = rxq->decompressed;
796 n = RTE_MIN(n, pkts_n - nocmp_n);
797 rxq_copy_mbuf_v(rxq, &pkts[nocmp_n], n);
800 rxq->decompressed -= n;
804 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
809 #endif /* RTE_PMD_MLX5_RXTX_VEC_NEON_H_ */