1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2020 Mellanox Technologies, Ltd
8 #include <ethdev_driver.h>
9 #include <rte_interrupts.h>
10 #include <rte_alarm.h>
11 #include <rte_malloc.h>
12 #include <rte_cycles.h>
13 #include <rte_eal_paging.h>
15 #include <mlx5_malloc.h>
16 #include <mlx5_common_devx.h>
21 #include "mlx5_common_os.h"
23 static_assert(sizeof(struct mlx5_cqe_ts) == sizeof(rte_int128_t),
24 "Wrong timestamp CQE part size");
26 static const char * const mlx5_txpp_stat_names[] = {
27 "tx_pp_missed_interrupt_errors", /* Missed service interrupt. */
28 "tx_pp_rearm_queue_errors", /* Rearm Queue errors. */
29 "tx_pp_clock_queue_errors", /* Clock Queue errors. */
30 "tx_pp_timestamp_past_errors", /* Timestamp in the past. */
31 "tx_pp_timestamp_future_errors", /* Timestamp in the distant future. */
32 "tx_pp_jitter", /* Timestamp jitter (one Clock Queue completion). */
33 "tx_pp_wander", /* Timestamp wander (half of Clock Queue CQEs). */
34 "tx_pp_sync_lost", /* Scheduling synchronization lost. */
37 /* Destroy Event Queue Notification Channel. */
39 mlx5_txpp_destroy_event_channel(struct mlx5_dev_ctx_shared *sh)
42 mlx5_os_devx_destroy_event_channel(sh->txpp.echan);
43 sh->txpp.echan = NULL;
47 /* Create Event Queue Notification Channel. */
49 mlx5_txpp_create_event_channel(struct mlx5_dev_ctx_shared *sh)
51 MLX5_ASSERT(!sh->txpp.echan);
52 sh->txpp.echan = mlx5_os_devx_create_event_channel(sh->cdev->ctx,
53 MLX5DV_DEVX_CREATE_EVENT_CHANNEL_FLAGS_OMIT_EV_DATA);
54 if (!sh->txpp.echan) {
56 DRV_LOG(ERR, "Failed to create event channel %d.", rte_errno);
63 mlx5_txpp_free_pp_index(struct mlx5_dev_ctx_shared *sh)
65 #ifdef HAVE_MLX5DV_PP_ALLOC
67 mlx5_glue->dv_free_pp(sh->txpp.pp);
73 DRV_LOG(ERR, "Freeing pacing index is not supported.");
77 /* Allocate Packet Pacing index from kernel via mlx5dv call. */
79 mlx5_txpp_alloc_pp_index(struct mlx5_dev_ctx_shared *sh)
81 #ifdef HAVE_MLX5DV_PP_ALLOC
82 uint32_t pp[MLX5_ST_SZ_DW(set_pp_rate_limit_context)];
85 MLX5_ASSERT(!sh->txpp.pp);
86 memset(&pp, 0, sizeof(pp));
87 rate = NS_PER_S / sh->txpp.tick;
88 if (rate * sh->txpp.tick != NS_PER_S)
89 DRV_LOG(WARNING, "Packet pacing frequency is not precise.");
93 len = RTE_MAX(MLX5_TXPP_TEST_PKT_SIZE,
94 (size_t)RTE_ETHER_MIN_LEN);
95 MLX5_SET(set_pp_rate_limit_context, &pp,
96 burst_upper_bound, len);
97 MLX5_SET(set_pp_rate_limit_context, &pp,
98 typical_packet_size, len);
99 /* Convert packets per second into kilobits. */
100 rate = (rate * len) / (1000ul / CHAR_BIT);
101 DRV_LOG(INFO, "Packet pacing rate set to %" PRIu64, rate);
103 MLX5_SET(set_pp_rate_limit_context, &pp, rate_limit, rate);
104 MLX5_SET(set_pp_rate_limit_context, &pp, rate_mode,
105 sh->txpp.test ? MLX5_DATA_RATE : MLX5_WQE_RATE);
106 sh->txpp.pp = mlx5_glue->dv_alloc_pp
107 (sh->cdev->ctx, sizeof(pp), &pp,
108 MLX5DV_PP_ALLOC_FLAGS_DEDICATED_INDEX);
109 if (sh->txpp.pp == NULL) {
110 DRV_LOG(ERR, "Failed to allocate packet pacing index.");
114 if (!((struct mlx5dv_pp *)sh->txpp.pp)->index) {
115 DRV_LOG(ERR, "Zero packet pacing index allocated.");
116 mlx5_txpp_free_pp_index(sh);
120 sh->txpp.pp_id = ((struct mlx5dv_pp *)(sh->txpp.pp))->index;
124 DRV_LOG(ERR, "Allocating pacing index is not supported.");
131 mlx5_txpp_destroy_send_queue(struct mlx5_txpp_wq *wq)
133 mlx5_devx_sq_destroy(&wq->sq_obj);
134 mlx5_devx_cq_destroy(&wq->cq_obj);
135 memset(wq, 0, sizeof(*wq));
139 mlx5_txpp_destroy_rearm_queue(struct mlx5_dev_ctx_shared *sh)
141 struct mlx5_txpp_wq *wq = &sh->txpp.rearm_queue;
143 mlx5_txpp_destroy_send_queue(wq);
147 mlx5_txpp_destroy_clock_queue(struct mlx5_dev_ctx_shared *sh)
149 struct mlx5_txpp_wq *wq = &sh->txpp.clock_queue;
151 mlx5_txpp_destroy_send_queue(wq);
153 mlx5_free(sh->txpp.tsa);
159 mlx5_txpp_doorbell_rearm_queue(struct mlx5_dev_ctx_shared *sh, uint16_t ci)
161 struct mlx5_txpp_wq *wq = &sh->txpp.rearm_queue;
162 struct mlx5_wqe *wqe = (struct mlx5_wqe *)(uintptr_t)wq->sq_obj.wqes;
170 cs.w32[0] = rte_cpu_to_be_32(rte_be_to_cpu_32
171 (wqe[ci & (wq->sq_size - 1)].ctrl[0]) | (ci - 1) << 8);
172 cs.w32[1] = wqe[ci & (wq->sq_size - 1)].ctrl[1];
173 /* Update SQ doorbell record with new SQ ci. */
174 rte_compiler_barrier();
175 *wq->sq_obj.db_rec = rte_cpu_to_be_32(wq->sq_ci);
176 /* Make sure the doorbell record is updated. */
178 /* Write to doorbel register to start processing. */
179 reg_addr = mlx5_os_get_devx_uar_reg_addr(sh->tx_uar);
180 __mlx5_uar_write64_relaxed(cs.w64, reg_addr, NULL);
185 mlx5_txpp_fill_wqe_rearm_queue(struct mlx5_dev_ctx_shared *sh)
187 struct mlx5_txpp_wq *wq = &sh->txpp.rearm_queue;
188 struct mlx5_wqe *wqe = (struct mlx5_wqe *)(uintptr_t)wq->sq_obj.wqes;
191 for (i = 0; i < wq->sq_size; i += 2) {
192 struct mlx5_wqe_cseg *cs;
193 struct mlx5_wqe_qseg *qs;
196 /* Build SEND_EN request with slave WQE index. */
197 cs = &wqe[i + 0].cseg;
198 cs->opcode = RTE_BE32(MLX5_OPCODE_SEND_EN | 0);
199 cs->sq_ds = rte_cpu_to_be_32((wq->sq_obj.sq->id << 8) | 2);
200 cs->flags = RTE_BE32(MLX5_COMP_ALWAYS <<
201 MLX5_COMP_MODE_OFFSET);
202 cs->misc = RTE_BE32(0);
203 qs = RTE_PTR_ADD(cs, sizeof(struct mlx5_wqe_cseg));
204 index = (i * MLX5_TXPP_REARM / 2 + MLX5_TXPP_REARM) &
205 ((1 << MLX5_WQ_INDEX_WIDTH) - 1);
206 qs->max_index = rte_cpu_to_be_32(index);
208 rte_cpu_to_be_32(sh->txpp.clock_queue.sq_obj.sq->id);
209 /* Build WAIT request with slave CQE index. */
210 cs = &wqe[i + 1].cseg;
211 cs->opcode = RTE_BE32(MLX5_OPCODE_WAIT | 0);
212 cs->sq_ds = rte_cpu_to_be_32((wq->sq_obj.sq->id << 8) | 2);
213 cs->flags = RTE_BE32(MLX5_COMP_ONLY_ERR <<
214 MLX5_COMP_MODE_OFFSET);
215 cs->misc = RTE_BE32(0);
216 qs = RTE_PTR_ADD(cs, sizeof(struct mlx5_wqe_cseg));
217 index = (i * MLX5_TXPP_REARM / 2 + MLX5_TXPP_REARM / 2) &
218 ((1 << MLX5_CQ_INDEX_WIDTH) - 1);
219 qs->max_index = rte_cpu_to_be_32(index);
221 rte_cpu_to_be_32(sh->txpp.clock_queue.cq_obj.cq->id);
225 /* Creates the Rearm Queue to fire the requests to Clock Queue in realtime. */
227 mlx5_txpp_create_rearm_queue(struct mlx5_dev_ctx_shared *sh)
229 struct mlx5_devx_create_sq_attr sq_attr = {
231 .state = MLX5_SQC_STATE_RST,
233 .tis_num = sh->tis->id,
234 .wq_attr = (struct mlx5_devx_wq_attr){
236 .uar_page = mlx5_os_get_devx_uar_page_id(sh->tx_uar),
238 .ts_format = mlx5_ts_format_conv(sh->sq_ts_format),
240 struct mlx5_devx_modify_sq_attr msq_attr = { 0 };
241 struct mlx5_devx_cq_attr cq_attr = {
242 .uar_page_id = mlx5_os_get_devx_uar_page_id(sh->tx_uar),
244 struct mlx5_txpp_wq *wq = &sh->txpp.rearm_queue;
247 /* Create completion queue object for Rearm Queue. */
248 ret = mlx5_devx_cq_create(sh->cdev->ctx, &wq->cq_obj,
249 log2above(MLX5_TXPP_REARM_CQ_SIZE), &cq_attr,
252 DRV_LOG(ERR, "Failed to create CQ for Rearm Queue.");
257 wq->sq_size = MLX5_TXPP_REARM_SQ_SIZE;
258 MLX5_ASSERT(wq->sq_size == (1 << log2above(wq->sq_size)));
259 /* Create send queue object for Rearm Queue. */
260 sq_attr.cqn = wq->cq_obj.cq->id;
261 /* There should be no WQE leftovers in the cyclic queue. */
262 ret = mlx5_devx_sq_create(sh->cdev->ctx, &wq->sq_obj,
263 log2above(MLX5_TXPP_REARM_SQ_SIZE), &sq_attr,
267 DRV_LOG(ERR, "Failed to create SQ for Rearm Queue.");
270 /* Build the WQEs in the Send Queue before goto Ready state. */
271 mlx5_txpp_fill_wqe_rearm_queue(sh);
272 /* Change queue state to ready. */
273 msq_attr.sq_state = MLX5_SQC_STATE_RST;
274 msq_attr.state = MLX5_SQC_STATE_RDY;
275 ret = mlx5_devx_cmd_modify_sq(wq->sq_obj.sq, &msq_attr);
277 DRV_LOG(ERR, "Failed to set SQ ready state Rearm Queue.");
283 mlx5_txpp_destroy_rearm_queue(sh);
289 mlx5_txpp_fill_wqe_clock_queue(struct mlx5_dev_ctx_shared *sh)
291 struct mlx5_txpp_wq *wq = &sh->txpp.clock_queue;
292 struct mlx5_wqe *wqe = (struct mlx5_wqe *)(uintptr_t)wq->sq_obj.wqes;
293 struct mlx5_wqe_cseg *cs = &wqe->cseg;
294 uint32_t wqe_size, opcode, i;
297 /* For test purposes fill the WQ with SEND inline packet. */
299 wqe_size = RTE_ALIGN(MLX5_TXPP_TEST_PKT_SIZE +
301 2 * MLX5_WQE_ESEG_SIZE -
302 MLX5_ESEG_MIN_INLINE_SIZE,
304 opcode = MLX5_OPCODE_SEND;
306 wqe_size = MLX5_WSEG_SIZE;
307 opcode = MLX5_OPCODE_NOP;
309 cs->opcode = rte_cpu_to_be_32(opcode | 0); /* Index is ignored. */
310 cs->sq_ds = rte_cpu_to_be_32((wq->sq_obj.sq->id << 8) |
311 (wqe_size / MLX5_WSEG_SIZE));
312 cs->flags = RTE_BE32(MLX5_COMP_ALWAYS << MLX5_COMP_MODE_OFFSET);
313 cs->misc = RTE_BE32(0);
314 wqe_size = RTE_ALIGN(wqe_size, MLX5_WQE_SIZE);
316 struct mlx5_wqe_eseg *es = &wqe->eseg;
317 struct rte_ether_hdr *eth_hdr;
318 struct rte_ipv4_hdr *ip_hdr;
319 struct rte_udp_hdr *udp_hdr;
321 /* Build the inline test packet pattern. */
322 MLX5_ASSERT(wqe_size <= MLX5_WQE_SIZE_MAX);
323 MLX5_ASSERT(MLX5_TXPP_TEST_PKT_SIZE >=
324 (sizeof(struct rte_ether_hdr) +
325 sizeof(struct rte_ipv4_hdr)));
327 es->cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
332 es->inline_hdr_sz = RTE_BE16(MLX5_TXPP_TEST_PKT_SIZE);
333 /* Build test packet L2 header (Ethernet). */
334 dst = (uint8_t *)&es->inline_data;
335 eth_hdr = (struct rte_ether_hdr *)dst;
336 rte_eth_random_addr(ð_hdr->dst_addr.addr_bytes[0]);
337 rte_eth_random_addr(ð_hdr->src_addr.addr_bytes[0]);
338 eth_hdr->ether_type = rte_cpu_to_be_16(RTE_ETHER_TYPE_IPV4);
339 /* Build test packet L3 header (IP v4). */
340 dst += sizeof(struct rte_ether_hdr);
341 ip_hdr = (struct rte_ipv4_hdr *)dst;
342 ip_hdr->version_ihl = RTE_IPV4_VHL_DEF;
343 ip_hdr->type_of_service = 0;
344 ip_hdr->fragment_offset = 0;
345 ip_hdr->time_to_live = 64;
346 ip_hdr->next_proto_id = IPPROTO_UDP;
347 ip_hdr->packet_id = 0;
348 ip_hdr->total_length = RTE_BE16(MLX5_TXPP_TEST_PKT_SIZE -
349 sizeof(struct rte_ether_hdr));
350 /* use RFC5735 / RFC2544 reserved network test addresses */
351 ip_hdr->src_addr = RTE_BE32((198U << 24) | (18 << 16) |
353 ip_hdr->dst_addr = RTE_BE32((198U << 24) | (18 << 16) |
355 if (MLX5_TXPP_TEST_PKT_SIZE <
356 (sizeof(struct rte_ether_hdr) +
357 sizeof(struct rte_ipv4_hdr) +
358 sizeof(struct rte_udp_hdr)))
360 /* Build test packet L4 header (UDP). */
361 dst += sizeof(struct rte_ipv4_hdr);
362 udp_hdr = (struct rte_udp_hdr *)dst;
363 udp_hdr->src_port = RTE_BE16(9); /* RFC863 Discard. */
364 udp_hdr->dst_port = RTE_BE16(9);
365 udp_hdr->dgram_len = RTE_BE16(MLX5_TXPP_TEST_PKT_SIZE -
366 sizeof(struct rte_ether_hdr) -
367 sizeof(struct rte_ipv4_hdr));
368 udp_hdr->dgram_cksum = 0;
369 /* Fill the test packet data. */
370 dst += sizeof(struct rte_udp_hdr);
371 for (i = sizeof(struct rte_ether_hdr) +
372 sizeof(struct rte_ipv4_hdr) +
373 sizeof(struct rte_udp_hdr);
374 i < MLX5_TXPP_TEST_PKT_SIZE; i++)
375 *dst++ = (uint8_t)(i & 0xFF);
378 /* Duplicate the pattern to the next WQEs. */
379 dst = (uint8_t *)(uintptr_t)wq->sq_obj.umem_buf;
380 for (i = 1; i < MLX5_TXPP_CLKQ_SIZE; i++) {
382 rte_memcpy(dst, (void *)(uintptr_t)wq->sq_obj.umem_buf,
387 /* Creates the Clock Queue for packet pacing, returns zero on success. */
389 mlx5_txpp_create_clock_queue(struct mlx5_dev_ctx_shared *sh)
391 struct mlx5_devx_create_sq_attr sq_attr = { 0 };
392 struct mlx5_devx_modify_sq_attr msq_attr = { 0 };
393 struct mlx5_devx_cq_attr cq_attr = {
396 .uar_page_id = mlx5_os_get_devx_uar_page_id(sh->tx_uar),
398 struct mlx5_txpp_wq *wq = &sh->txpp.clock_queue;
401 sh->txpp.tsa = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO,
402 MLX5_TXPP_REARM_SQ_SIZE *
403 sizeof(struct mlx5_txpp_ts),
406 DRV_LOG(ERR, "Failed to allocate memory for CQ stats.");
411 /* Create completion queue object for Clock Queue. */
412 ret = mlx5_devx_cq_create(sh->cdev->ctx, &wq->cq_obj,
413 log2above(MLX5_TXPP_CLKQ_SIZE), &cq_attr,
416 DRV_LOG(ERR, "Failed to create CQ for Clock Queue.");
420 /* Allocate memory buffer for Send Queue WQEs. */
422 wq->sq_size = RTE_ALIGN(MLX5_TXPP_TEST_PKT_SIZE +
424 2 * MLX5_WQE_ESEG_SIZE -
425 MLX5_ESEG_MIN_INLINE_SIZE,
426 MLX5_WQE_SIZE) / MLX5_WQE_SIZE;
427 wq->sq_size *= MLX5_TXPP_CLKQ_SIZE;
429 wq->sq_size = MLX5_TXPP_CLKQ_SIZE;
431 /* There should not be WQE leftovers in the cyclic queue. */
432 MLX5_ASSERT(wq->sq_size == (1 << log2above(wq->sq_size)));
433 /* Create send queue object for Clock Queue. */
435 sq_attr.tis_lst_sz = 1;
436 sq_attr.tis_num = sh->tis->id;
437 sq_attr.non_wire = 0;
438 sq_attr.static_sq_wq = 1;
440 sq_attr.non_wire = 1;
441 sq_attr.static_sq_wq = 1;
443 sq_attr.cqn = wq->cq_obj.cq->id;
444 sq_attr.packet_pacing_rate_limit_index = sh->txpp.pp_id;
445 sq_attr.wq_attr.cd_slave = 1;
446 sq_attr.wq_attr.uar_page = mlx5_os_get_devx_uar_page_id(sh->tx_uar);
447 sq_attr.wq_attr.pd = sh->pdn;
448 sq_attr.ts_format = mlx5_ts_format_conv(sh->sq_ts_format);
449 ret = mlx5_devx_sq_create(sh->cdev->ctx, &wq->sq_obj,
450 log2above(wq->sq_size),
451 &sq_attr, sh->numa_node);
454 DRV_LOG(ERR, "Failed to create SQ for Clock Queue.");
457 /* Build the WQEs in the Send Queue before goto Ready state. */
458 mlx5_txpp_fill_wqe_clock_queue(sh);
459 /* Change queue state to ready. */
460 msq_attr.sq_state = MLX5_SQC_STATE_RST;
461 msq_attr.state = MLX5_SQC_STATE_RDY;
463 ret = mlx5_devx_cmd_modify_sq(wq->sq_obj.sq, &msq_attr);
465 DRV_LOG(ERR, "Failed to set SQ ready state Clock Queue.");
471 mlx5_txpp_destroy_clock_queue(sh);
476 /* Enable notification from the Rearm Queue CQ. */
478 mlx5_txpp_cq_arm(struct mlx5_dev_ctx_shared *sh)
482 struct mlx5_txpp_wq *aq = &sh->txpp.rearm_queue;
483 uint32_t arm_sn = aq->arm_sn << MLX5_CQ_SQN_OFFSET;
484 uint32_t db_hi = arm_sn | MLX5_CQ_DBR_CMD_ALL | aq->cq_ci;
486 rte_cpu_to_be_64(((uint64_t)db_hi << 32) | aq->cq_obj.cq->id);
487 base_addr = mlx5_os_get_devx_uar_base_addr(sh->tx_uar);
488 uint32_t *addr = RTE_PTR_ADD(base_addr, MLX5_CQ_DOORBELL);
490 rte_compiler_barrier();
491 aq->cq_obj.db_rec[MLX5_CQ_ARM_DB] = rte_cpu_to_be_32(db_hi);
494 *(uint64_t *)addr = db_be;
496 *(uint32_t *)addr = db_be;
498 *((uint32_t *)addr + 1) = db_be >> 32;
503 #if defined(RTE_ARCH_X86_64)
505 mlx5_atomic128_compare_exchange(rte_int128_t *dst,
507 const rte_int128_t *src)
511 asm volatile (MPLOCKED
514 : [dst] "=m" (dst->val[0]),
530 mlx5_atomic_read_cqe(rte_int128_t *from, rte_int128_t *ts)
533 * The only CQE of Clock Queue is being continuously
534 * updated by hardware with specified rate. We must
535 * read timestamp and WQE completion index atomically.
537 #if defined(RTE_ARCH_X86_64)
540 memset(&src, 0, sizeof(src));
542 /* if (*from == *ts) *from = *src else *ts = *from; */
543 mlx5_atomic128_compare_exchange(from, ts, &src);
545 uint64_t *cqe = (uint64_t *)from;
548 * Power architecture does not support 16B compare-and-swap.
549 * ARM implements it in software, code below is more relevant.
555 rte_compiler_barrier();
556 tm = __atomic_load_n(cqe + 0, __ATOMIC_RELAXED);
557 op = __atomic_load_n(cqe + 1, __ATOMIC_RELAXED);
558 rte_compiler_barrier();
559 if (tm != __atomic_load_n(cqe + 0, __ATOMIC_RELAXED))
561 if (op != __atomic_load_n(cqe + 1, __ATOMIC_RELAXED))
571 /* Stores timestamp in the cache structure to share data with datapath. */
573 mlx5_txpp_cache_timestamp(struct mlx5_dev_ctx_shared *sh,
574 uint64_t ts, uint64_t ci)
576 ci = ci << (64 - MLX5_CQ_INDEX_WIDTH);
577 ci |= (ts << MLX5_CQ_INDEX_WIDTH) >> MLX5_CQ_INDEX_WIDTH;
578 rte_compiler_barrier();
579 __atomic_store_n(&sh->txpp.ts.ts, ts, __ATOMIC_RELAXED);
580 __atomic_store_n(&sh->txpp.ts.ci_ts, ci, __ATOMIC_RELAXED);
584 /* Reads timestamp from Clock Queue CQE and stores in the cache. */
586 mlx5_txpp_update_timestamp(struct mlx5_dev_ctx_shared *sh)
588 struct mlx5_txpp_wq *wq = &sh->txpp.clock_queue;
589 struct mlx5_cqe *cqe = (struct mlx5_cqe *)(uintptr_t)wq->cq_obj.cqes;
592 struct mlx5_cqe_ts cts;
598 mlx5_atomic_read_cqe((rte_int128_t *)&cqe->timestamp, &to.u128);
599 opcode = MLX5_CQE_OPCODE(to.cts.op_own);
601 if (opcode != MLX5_CQE_INVALID) {
603 * Commit the error state if and only if
604 * we have got at least one actual completion.
607 "Clock Queue error sync lost (%X).", opcode);
608 __atomic_fetch_add(&sh->txpp.err_clock_queue,
609 1, __ATOMIC_RELAXED);
610 sh->txpp.sync_lost = 1;
614 ci = rte_be_to_cpu_16(to.cts.wqe_counter);
615 ts = rte_be_to_cpu_64(to.cts.timestamp);
616 ts = mlx5_txpp_convert_rx_ts(sh, ts);
617 wq->cq_ci += (ci - wq->sq_ci) & UINT16_MAX;
619 mlx5_txpp_cache_timestamp(sh, ts, wq->cq_ci);
622 /* Waits for the first completion on Clock Queue to init timestamp. */
624 mlx5_txpp_init_timestamp(struct mlx5_dev_ctx_shared *sh)
626 struct mlx5_txpp_wq *wq = &sh->txpp.clock_queue;
631 for (wait = 0; wait < MLX5_TXPP_WAIT_INIT_TS; wait++) {
632 mlx5_txpp_update_timestamp(sh);
635 /* Wait one millisecond and try again. */
636 rte_delay_us_sleep(US_PER_S / MS_PER_S);
638 DRV_LOG(ERR, "Unable to initialize timestamp.");
639 sh->txpp.sync_lost = 1;
642 #ifdef HAVE_IBV_DEVX_EVENT
643 /* Gather statistics for timestamp from Clock Queue CQE. */
645 mlx5_txpp_gather_timestamp(struct mlx5_dev_ctx_shared *sh)
647 /* Check whether we have a valid timestamp. */
648 if (!sh->txpp.clock_queue.sq_ci && !sh->txpp.ts_n)
650 MLX5_ASSERT(sh->txpp.ts_p < MLX5_TXPP_REARM_SQ_SIZE);
651 __atomic_store_n(&sh->txpp.tsa[sh->txpp.ts_p].ts,
652 sh->txpp.ts.ts, __ATOMIC_RELAXED);
653 __atomic_store_n(&sh->txpp.tsa[sh->txpp.ts_p].ci_ts,
654 sh->txpp.ts.ci_ts, __ATOMIC_RELAXED);
655 if (++sh->txpp.ts_p >= MLX5_TXPP_REARM_SQ_SIZE)
657 if (sh->txpp.ts_n < MLX5_TXPP_REARM_SQ_SIZE)
661 /* Handles Rearm Queue completions in periodic service. */
662 static __rte_always_inline void
663 mlx5_txpp_handle_rearm_queue(struct mlx5_dev_ctx_shared *sh)
665 struct mlx5_txpp_wq *wq = &sh->txpp.rearm_queue;
666 uint32_t cq_ci = wq->cq_ci;
671 volatile struct mlx5_cqe *cqe;
673 cqe = &wq->cq_obj.cqes[cq_ci & (MLX5_TXPP_REARM_CQ_SIZE - 1)];
674 ret = check_cqe(cqe, MLX5_TXPP_REARM_CQ_SIZE, cq_ci);
676 case MLX5_CQE_STATUS_ERR:
680 case MLX5_CQE_STATUS_SW_OWN:
684 case MLX5_CQE_STATUS_HW_OWN:
690 } while (ret != MLX5_CQE_STATUS_HW_OWN);
691 if (likely(cq_ci != wq->cq_ci)) {
692 /* Check whether we have missed interrupts. */
693 if (cq_ci - wq->cq_ci != 1) {
694 DRV_LOG(DEBUG, "Rearm Queue missed interrupt.");
695 __atomic_fetch_add(&sh->txpp.err_miss_int,
696 1, __ATOMIC_RELAXED);
697 /* Check sync lost on wqe index. */
698 if (cq_ci - wq->cq_ci >=
699 (((1UL << MLX5_WQ_INDEX_WIDTH) /
700 MLX5_TXPP_REARM) - 1))
703 /* Update doorbell record to notify hardware. */
704 rte_compiler_barrier();
705 *wq->cq_obj.db_rec = rte_cpu_to_be_32(cq_ci);
708 /* Fire new requests to Rearm Queue. */
710 DRV_LOG(DEBUG, "Rearm Queue error sync lost.");
711 __atomic_fetch_add(&sh->txpp.err_rearm_queue,
712 1, __ATOMIC_RELAXED);
713 sh->txpp.sync_lost = 1;
718 /* Handles Clock Queue completions in periodic service. */
719 static __rte_always_inline void
720 mlx5_txpp_handle_clock_queue(struct mlx5_dev_ctx_shared *sh)
722 mlx5_txpp_update_timestamp(sh);
723 mlx5_txpp_gather_timestamp(sh);
727 /* Invoked periodically on Rearm Queue completions. */
729 mlx5_txpp_interrupt_handler(void *cb_arg)
731 #ifndef HAVE_IBV_DEVX_EVENT
732 RTE_SET_USED(cb_arg);
735 struct mlx5_dev_ctx_shared *sh = cb_arg;
737 struct mlx5dv_devx_async_event_hdr event_resp;
738 uint8_t buf[sizeof(struct mlx5dv_devx_async_event_hdr) + 128];
741 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
742 /* Process events in the loop. Only rearm completions are expected. */
743 while (mlx5_glue->devx_get_event
747 (ssize_t)sizeof(out.event_resp.cookie)) {
748 mlx5_txpp_handle_rearm_queue(sh);
749 mlx5_txpp_handle_clock_queue(sh);
750 mlx5_txpp_cq_arm(sh);
751 mlx5_txpp_doorbell_rearm_queue
752 (sh, sh->txpp.rearm_queue.sq_ci - 1);
754 #endif /* HAVE_IBV_DEVX_ASYNC */
758 mlx5_txpp_stop_service(struct mlx5_dev_ctx_shared *sh)
760 if (!sh->txpp.intr_handle.fd)
762 mlx5_intr_callback_unregister(&sh->txpp.intr_handle,
763 mlx5_txpp_interrupt_handler, sh);
764 sh->txpp.intr_handle.fd = 0;
767 /* Attach interrupt handler and fires first request to Rearm Queue. */
769 mlx5_txpp_start_service(struct mlx5_dev_ctx_shared *sh)
771 uint16_t event_nums[1] = {0};
775 sh->txpp.err_miss_int = 0;
776 sh->txpp.err_rearm_queue = 0;
777 sh->txpp.err_clock_queue = 0;
778 sh->txpp.err_ts_past = 0;
779 sh->txpp.err_ts_future = 0;
780 /* Attach interrupt handler to process Rearm Queue completions. */
781 fd = mlx5_os_get_devx_channel_fd(sh->txpp.echan);
782 ret = mlx5_os_set_nonblock_channel_fd(fd);
784 DRV_LOG(ERR, "Failed to change event channel FD.");
788 memset(&sh->txpp.intr_handle, 0, sizeof(sh->txpp.intr_handle));
789 fd = mlx5_os_get_devx_channel_fd(sh->txpp.echan);
790 sh->txpp.intr_handle.fd = fd;
791 sh->txpp.intr_handle.type = RTE_INTR_HANDLE_EXT;
792 if (rte_intr_callback_register(&sh->txpp.intr_handle,
793 mlx5_txpp_interrupt_handler, sh)) {
794 sh->txpp.intr_handle.fd = 0;
795 DRV_LOG(ERR, "Failed to register CQE interrupt %d.", rte_errno);
798 /* Subscribe CQ event to the event channel controlled by the driver. */
799 ret = mlx5_os_devx_subscribe_devx_event(sh->txpp.echan,
800 sh->txpp.rearm_queue.cq_obj.cq->obj,
801 sizeof(event_nums), event_nums, 0);
803 DRV_LOG(ERR, "Failed to subscribe CQE event.");
807 /* Enable interrupts in the CQ. */
808 mlx5_txpp_cq_arm(sh);
809 /* Fire the first request on Rearm Queue. */
810 mlx5_txpp_doorbell_rearm_queue(sh, sh->txpp.rearm_queue.sq_size - 1);
811 mlx5_txpp_init_timestamp(sh);
816 * The routine initializes the packet pacing infrastructure:
817 * - allocates PP context
820 * - attaches rearm interrupt handler
821 * - starts Clock Queue
823 * Returns 0 on success, negative otherwise
826 mlx5_txpp_create(struct mlx5_dev_ctx_shared *sh, struct mlx5_priv *priv)
828 int tx_pp = priv->config.tx_pp;
831 /* Store the requested pacing parameters. */
832 sh->txpp.tick = tx_pp >= 0 ? tx_pp : -tx_pp;
833 sh->txpp.test = !!(tx_pp < 0);
834 sh->txpp.skew = priv->config.tx_skew;
835 sh->txpp.freq = priv->config.hca_attr.dev_freq_khz;
836 ret = mlx5_txpp_create_event_channel(sh);
839 ret = mlx5_txpp_alloc_pp_index(sh);
842 ret = mlx5_txpp_create_clock_queue(sh);
845 ret = mlx5_txpp_create_rearm_queue(sh);
848 ret = mlx5_txpp_start_service(sh);
853 mlx5_txpp_stop_service(sh);
854 mlx5_txpp_destroy_rearm_queue(sh);
855 mlx5_txpp_destroy_clock_queue(sh);
856 mlx5_txpp_free_pp_index(sh);
857 mlx5_txpp_destroy_event_channel(sh);
866 * The routine destroys the packet pacing infrastructure:
867 * - detaches rearm interrupt handler
873 mlx5_txpp_destroy(struct mlx5_dev_ctx_shared *sh)
875 mlx5_txpp_stop_service(sh);
876 mlx5_txpp_destroy_rearm_queue(sh);
877 mlx5_txpp_destroy_clock_queue(sh);
878 mlx5_txpp_free_pp_index(sh);
879 mlx5_txpp_destroy_event_channel(sh);
886 * Creates and starts packet pacing infrastructure on specified device.
889 * Pointer to Ethernet device structure.
892 * 0 on success, a negative errno value otherwise and rte_errno is set.
895 mlx5_txpp_start(struct rte_eth_dev *dev)
897 struct mlx5_priv *priv = dev->data->dev_private;
898 struct mlx5_dev_ctx_shared *sh = priv->sh;
902 if (!priv->config.tx_pp) {
903 /* Packet pacing is not requested for the device. */
904 MLX5_ASSERT(priv->txpp_en == 0);
908 /* Packet pacing is already enabled for the device. */
909 MLX5_ASSERT(sh->txpp.refcnt);
912 if (priv->config.tx_pp > 0) {
913 ret = rte_mbuf_dynflag_lookup
914 (RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME, NULL);
918 ret = pthread_mutex_lock(&sh->txpp.mutex);
921 if (sh->txpp.refcnt) {
925 err = mlx5_txpp_create(sh, priv);
927 MLX5_ASSERT(sh->txpp.tick);
934 ret = pthread_mutex_unlock(&sh->txpp.mutex);
941 * Stops and destroys packet pacing infrastructure on specified device.
944 * Pointer to Ethernet device structure.
947 * 0 on success, a negative errno value otherwise and rte_errno is set.
950 mlx5_txpp_stop(struct rte_eth_dev *dev)
952 struct mlx5_priv *priv = dev->data->dev_private;
953 struct mlx5_dev_ctx_shared *sh = priv->sh;
956 if (!priv->txpp_en) {
957 /* Packet pacing is already disabled for the device. */
961 ret = pthread_mutex_lock(&sh->txpp.mutex);
964 MLX5_ASSERT(sh->txpp.refcnt);
965 if (!sh->txpp.refcnt || --sh->txpp.refcnt)
967 /* No references any more, do actual destroy. */
968 mlx5_txpp_destroy(sh);
969 ret = pthread_mutex_unlock(&sh->txpp.mutex);
975 * Read the current clock counter of an Ethernet device
977 * This returns the current raw clock value of an Ethernet device. It is
978 * a raw amount of ticks, with no given time reference.
979 * The value returned here is from the same clock than the one
980 * filling timestamp field of Rx/Tx packets when using hardware timestamp
981 * offload. Therefore it can be used to compute a precise conversion of
982 * the device clock to the real time.
985 * Pointer to Ethernet device structure.
987 * Pointer to the uint64_t that holds the raw clock value.
991 * - -ENOTSUP: The function is not supported in this mode. Requires
992 * packet pacing module configured and started (tx_pp devarg)
995 mlx5_txpp_read_clock(struct rte_eth_dev *dev, uint64_t *timestamp)
997 struct mlx5_priv *priv = dev->data->dev_private;
998 struct mlx5_dev_ctx_shared *sh = priv->sh;
1001 if (sh->txpp.refcnt) {
1002 struct mlx5_txpp_wq *wq = &sh->txpp.clock_queue;
1003 struct mlx5_cqe *cqe =
1004 (struct mlx5_cqe *)(uintptr_t)wq->cq_obj.cqes;
1007 struct mlx5_cqe_ts cts;
1011 mlx5_atomic_read_cqe((rte_int128_t *)&cqe->timestamp, &to.u128);
1012 if (to.cts.op_own >> 4) {
1013 DRV_LOG(DEBUG, "Clock Queue error sync lost.");
1014 __atomic_fetch_add(&sh->txpp.err_clock_queue,
1015 1, __ATOMIC_RELAXED);
1016 sh->txpp.sync_lost = 1;
1019 ts = rte_be_to_cpu_64(to.cts.timestamp);
1020 ts = mlx5_txpp_convert_rx_ts(sh, ts);
1024 /* Not supported in isolated mode - kernel does not see the CQEs. */
1025 if (priv->isolated || rte_eal_process_type() != RTE_PROC_PRIMARY)
1027 ret = mlx5_read_clock(dev, timestamp);
1032 * DPDK callback to clear device extended statistics.
1035 * Pointer to Ethernet device structure.
1038 * 0 on success and stats is reset, negative errno value otherwise and
1041 int mlx5_txpp_xstats_reset(struct rte_eth_dev *dev)
1043 struct mlx5_priv *priv = dev->data->dev_private;
1044 struct mlx5_dev_ctx_shared *sh = priv->sh;
1046 __atomic_store_n(&sh->txpp.err_miss_int, 0, __ATOMIC_RELAXED);
1047 __atomic_store_n(&sh->txpp.err_rearm_queue, 0, __ATOMIC_RELAXED);
1048 __atomic_store_n(&sh->txpp.err_clock_queue, 0, __ATOMIC_RELAXED);
1049 __atomic_store_n(&sh->txpp.err_ts_past, 0, __ATOMIC_RELAXED);
1050 __atomic_store_n(&sh->txpp.err_ts_future, 0, __ATOMIC_RELAXED);
1055 * Routine to retrieve names of extended device statistics
1056 * for packet send scheduling. It appends the specific stats names
1057 * after the parts filled by preceding modules (eth stats, etc.)
1060 * Pointer to Ethernet device structure.
1061 * @param[out] xstats_names
1062 * Buffer to insert names into.
1066 * Number of names filled by preceding statistics modules.
1069 * Number of xstats names.
1071 int mlx5_txpp_xstats_get_names(struct rte_eth_dev *dev __rte_unused,
1072 struct rte_eth_xstat_name *xstats_names,
1073 unsigned int n, unsigned int n_used)
1075 unsigned int n_txpp = RTE_DIM(mlx5_txpp_stat_names);
1078 if (n >= n_used + n_txpp && xstats_names) {
1079 for (i = 0; i < n_txpp; ++i) {
1080 strncpy(xstats_names[i + n_used].name,
1081 mlx5_txpp_stat_names[i],
1082 RTE_ETH_XSTATS_NAME_SIZE);
1083 xstats_names[i + n_used].name
1084 [RTE_ETH_XSTATS_NAME_SIZE - 1] = 0;
1087 return n_used + n_txpp;
1091 mlx5_txpp_read_tsa(struct mlx5_dev_txpp *txpp,
1092 struct mlx5_txpp_ts *tsa, uint16_t idx)
1097 ts = __atomic_load_n(&txpp->tsa[idx].ts, __ATOMIC_RELAXED);
1098 ci = __atomic_load_n(&txpp->tsa[idx].ci_ts, __ATOMIC_RELAXED);
1099 rte_compiler_barrier();
1100 if ((ci ^ ts) << MLX5_CQ_INDEX_WIDTH != 0)
1102 if (__atomic_load_n(&txpp->tsa[idx].ts,
1103 __ATOMIC_RELAXED) != ts)
1105 if (__atomic_load_n(&txpp->tsa[idx].ci_ts,
1106 __ATOMIC_RELAXED) != ci)
1115 * Jitter reflects the clock change between
1116 * neighbours Clock Queue completions.
1119 mlx5_txpp_xstats_jitter(struct mlx5_dev_txpp *txpp)
1121 struct mlx5_txpp_ts tsa0, tsa1;
1125 if (txpp->ts_n < 2) {
1126 /* No gathered enough reports yet. */
1133 rte_compiler_barrier();
1136 ts_0 += MLX5_TXPP_REARM_SQ_SIZE;
1139 ts_1 += MLX5_TXPP_REARM_SQ_SIZE;
1140 mlx5_txpp_read_tsa(txpp, &tsa0, ts_0);
1141 mlx5_txpp_read_tsa(txpp, &tsa1, ts_1);
1142 rte_compiler_barrier();
1143 } while (ts_p != txpp->ts_p);
1144 /* We have two neighbor reports, calculate the jitter. */
1145 dts = tsa1.ts - tsa0.ts;
1146 dci = (tsa1.ci_ts >> (64 - MLX5_CQ_INDEX_WIDTH)) -
1147 (tsa0.ci_ts >> (64 - MLX5_CQ_INDEX_WIDTH));
1149 dci += 1 << MLX5_CQ_INDEX_WIDTH;
1151 return (dts > dci) ? dts - dci : dci - dts;
1155 * Wander reflects the long-term clock change
1156 * over the entire length of all Clock Queue completions.
1159 mlx5_txpp_xstats_wander(struct mlx5_dev_txpp *txpp)
1161 struct mlx5_txpp_ts tsa0, tsa1;
1165 if (txpp->ts_n < MLX5_TXPP_REARM_SQ_SIZE) {
1166 /* No gathered enough reports yet. */
1173 rte_compiler_barrier();
1174 ts_0 = ts_p - MLX5_TXPP_REARM_SQ_SIZE / 2 - 1;
1176 ts_0 += MLX5_TXPP_REARM_SQ_SIZE;
1179 ts_1 += MLX5_TXPP_REARM_SQ_SIZE;
1180 mlx5_txpp_read_tsa(txpp, &tsa0, ts_0);
1181 mlx5_txpp_read_tsa(txpp, &tsa1, ts_1);
1182 rte_compiler_barrier();
1183 } while (ts_p != txpp->ts_p);
1184 /* We have two neighbor reports, calculate the jitter. */
1185 dts = tsa1.ts - tsa0.ts;
1186 dci = (tsa1.ci_ts >> (64 - MLX5_CQ_INDEX_WIDTH)) -
1187 (tsa0.ci_ts >> (64 - MLX5_CQ_INDEX_WIDTH));
1188 dci += 1 << MLX5_CQ_INDEX_WIDTH;
1190 return (dts > dci) ? dts - dci : dci - dts;
1194 * Routine to retrieve extended device statistics
1195 * for packet send scheduling. It appends the specific statistics
1196 * after the parts filled by preceding modules (eth stats, etc.)
1199 * Pointer to Ethernet device.
1201 * Pointer to rte extended stats table.
1203 * The size of the stats table.
1205 * Number of stats filled by preceding statistics modules.
1208 * Number of extended stats on success and stats is filled,
1209 * negative on error and rte_errno is set.
1212 mlx5_txpp_xstats_get(struct rte_eth_dev *dev,
1213 struct rte_eth_xstat *stats,
1214 unsigned int n, unsigned int n_used)
1216 unsigned int n_txpp = RTE_DIM(mlx5_txpp_stat_names);
1218 if (n >= n_used + n_txpp && stats) {
1219 struct mlx5_priv *priv = dev->data->dev_private;
1220 struct mlx5_dev_ctx_shared *sh = priv->sh;
1223 for (i = 0; i < n_txpp; ++i)
1224 stats[n_used + i].id = n_used + i;
1225 stats[n_used + 0].value =
1226 __atomic_load_n(&sh->txpp.err_miss_int,
1228 stats[n_used + 1].value =
1229 __atomic_load_n(&sh->txpp.err_rearm_queue,
1231 stats[n_used + 2].value =
1232 __atomic_load_n(&sh->txpp.err_clock_queue,
1234 stats[n_used + 3].value =
1235 __atomic_load_n(&sh->txpp.err_ts_past,
1237 stats[n_used + 4].value =
1238 __atomic_load_n(&sh->txpp.err_ts_future,
1240 stats[n_used + 5].value = mlx5_txpp_xstats_jitter(&sh->txpp);
1241 stats[n_used + 6].value = mlx5_txpp_xstats_wander(&sh->txpp);
1242 stats[n_used + 7].value = sh->txpp.sync_lost;
1244 return n_used + n_txpp;