4 * Copyright 2015 6WIND S.A.
5 * Copyright 2015 Mellanox.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of 6WIND S.A. nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
45 #pragma GCC diagnostic ignored "-Wpedantic"
47 #include <infiniband/verbs.h>
49 #pragma GCC diagnostic error "-Wpedantic"
53 #include <rte_malloc.h>
54 #include <rte_ethdev_driver.h>
55 #include <rte_common.h>
57 #include "mlx5_utils.h"
58 #include "mlx5_defs.h"
60 #include "mlx5_rxtx.h"
61 #include "mlx5_autoconf.h"
64 * Allocate TX queue elements.
67 * Pointer to TX queue structure.
70 txq_alloc_elts(struct mlx5_txq_ctrl *txq_ctrl)
72 const unsigned int elts_n = 1 << txq_ctrl->txq.elts_n;
75 for (i = 0; (i != elts_n); ++i)
76 (*txq_ctrl->txq.elts)[i] = NULL;
77 DEBUG("%p: allocated and configured %u WRs", (void *)txq_ctrl, elts_n);
78 txq_ctrl->txq.elts_head = 0;
79 txq_ctrl->txq.elts_tail = 0;
80 txq_ctrl->txq.elts_comp = 0;
84 * Free TX queue elements.
87 * Pointer to TX queue structure.
90 txq_free_elts(struct mlx5_txq_ctrl *txq_ctrl)
92 const uint16_t elts_n = 1 << txq_ctrl->txq.elts_n;
93 const uint16_t elts_m = elts_n - 1;
94 uint16_t elts_head = txq_ctrl->txq.elts_head;
95 uint16_t elts_tail = txq_ctrl->txq.elts_tail;
96 struct rte_mbuf *(*elts)[elts_n] = txq_ctrl->txq.elts;
98 DEBUG("%p: freeing WRs", (void *)txq_ctrl);
99 txq_ctrl->txq.elts_head = 0;
100 txq_ctrl->txq.elts_tail = 0;
101 txq_ctrl->txq.elts_comp = 0;
103 while (elts_tail != elts_head) {
104 struct rte_mbuf *elt = (*elts)[elts_tail & elts_m];
107 rte_pktmbuf_free_seg(elt);
110 memset(&(*elts)[elts_tail & elts_m],
112 sizeof((*elts)[elts_tail & elts_m]));
119 * Returns the per-port supported offloads.
122 * Pointer to private structure.
125 * Supported Tx offloads.
128 mlx5_priv_get_tx_port_offloads(struct priv *priv)
130 uint64_t offloads = (DEV_TX_OFFLOAD_MULTI_SEGS |
131 DEV_TX_OFFLOAD_VLAN_INSERT);
132 struct mlx5_dev_config *config = &priv->config;
135 offloads |= (DEV_TX_OFFLOAD_IPV4_CKSUM |
136 DEV_TX_OFFLOAD_UDP_CKSUM |
137 DEV_TX_OFFLOAD_TCP_CKSUM);
139 offloads |= DEV_TX_OFFLOAD_TCP_TSO;
140 if (config->tunnel_en) {
142 offloads |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
144 offloads |= (DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
145 DEV_TX_OFFLOAD_GRE_TNL_TSO);
151 * Checks if the per-queue offload configuration is valid.
154 * Pointer to private structure.
156 * Per-queue offloads configuration.
159 * 1 if the configuration is valid, 0 otherwise.
162 priv_is_tx_queue_offloads_allowed(struct priv *priv, uint64_t offloads)
164 uint64_t port_offloads = priv->dev->data->dev_conf.txmode.offloads;
165 uint64_t port_supp_offloads = mlx5_priv_get_tx_port_offloads(priv);
167 /* There are no Tx offloads which are per queue. */
168 if ((offloads & port_supp_offloads) != offloads)
170 if ((port_offloads ^ offloads) & port_supp_offloads)
176 * DPDK callback to configure a TX queue.
179 * Pointer to Ethernet device structure.
183 * Number of descriptors to configure in queue.
185 * NUMA socket on which memory must be allocated.
187 * Thresholds parameters.
190 * 0 on success, negative errno value on failure.
193 mlx5_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
194 unsigned int socket, const struct rte_eth_txconf *conf)
196 struct priv *priv = dev->data->dev_private;
197 struct mlx5_txq_data *txq = (*priv->txqs)[idx];
198 struct mlx5_txq_ctrl *txq_ctrl =
199 container_of(txq, struct mlx5_txq_ctrl, txq);
204 * Don't verify port offloads for application which
207 if (!!(conf->txq_flags & ETH_TXQ_FLAGS_IGNORE) &&
208 !priv_is_tx_queue_offloads_allowed(priv, conf->offloads)) {
210 ERROR("%p: Tx queue offloads 0x%" PRIx64 " don't match port "
211 "offloads 0x%" PRIx64 " or supported offloads 0x%" PRIx64,
212 (void *)dev, conf->offloads,
213 dev->data->dev_conf.txmode.offloads,
214 mlx5_priv_get_tx_port_offloads(priv));
217 if (desc <= MLX5_TX_COMP_THRESH) {
218 WARN("%p: number of descriptors requested for TX queue %u"
219 " must be higher than MLX5_TX_COMP_THRESH, using"
221 (void *)dev, idx, MLX5_TX_COMP_THRESH + 1, desc);
222 desc = MLX5_TX_COMP_THRESH + 1;
224 if (!rte_is_power_of_2(desc)) {
225 desc = 1 << log2above(desc);
226 WARN("%p: increased number of descriptors in TX queue %u"
227 " to the next power of two (%d)",
228 (void *)dev, idx, desc);
230 DEBUG("%p: configuring queue %u for %u descriptors",
231 (void *)dev, idx, desc);
232 if (idx >= priv->txqs_n) {
233 ERROR("%p: queue index out of range (%u >= %u)",
234 (void *)dev, idx, priv->txqs_n);
238 if (!mlx5_priv_txq_releasable(priv, idx)) {
240 ERROR("%p: unable to release queue index %u",
244 mlx5_priv_txq_release(priv, idx);
245 txq_ctrl = mlx5_priv_txq_new(priv, idx, desc, socket, conf);
247 ERROR("%p: unable to allocate queue index %u",
252 DEBUG("%p: adding TX queue %p to list",
253 (void *)dev, (void *)txq_ctrl);
254 (*priv->txqs)[idx] = &txq_ctrl->txq;
261 * DPDK callback to release a TX queue.
264 * Generic TX queue pointer.
267 mlx5_tx_queue_release(void *dpdk_txq)
269 struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
270 struct mlx5_txq_ctrl *txq_ctrl;
276 txq_ctrl = container_of(txq, struct mlx5_txq_ctrl, txq);
277 priv = txq_ctrl->priv;
279 for (i = 0; (i != priv->txqs_n); ++i)
280 if ((*priv->txqs)[i] == txq) {
281 DEBUG("%p: removing TX queue %p from list",
282 (void *)priv->dev, (void *)txq_ctrl);
283 mlx5_priv_txq_release(priv, i);
291 * Mmap TX UAR(HW doorbell) pages into reserved UAR address space.
292 * Both primary and secondary process do mmap to make UAR address
296 * Pointer to private structure.
298 * Verbs file descriptor to map UAR pages.
301 * 0 on success, errno value on failure.
304 priv_tx_uar_remap(struct priv *priv, int fd)
307 uintptr_t pages[priv->txqs_n];
308 unsigned int pages_n = 0;
313 struct mlx5_txq_data *txq;
314 struct mlx5_txq_ctrl *txq_ctrl;
316 size_t page_size = sysconf(_SC_PAGESIZE);
319 memset(pages, 0, priv->txqs_n * sizeof(uintptr_t));
321 * As rdma-core, UARs are mapped in size of OS page size.
322 * Use aligned address to avoid duplicate mmap.
323 * Ref to libmlx5 function: mlx5_init_context()
325 for (i = 0; i != priv->txqs_n; ++i) {
326 txq = (*priv->txqs)[i];
327 txq_ctrl = container_of(txq, struct mlx5_txq_ctrl, txq);
328 /* UAR addr form verbs used to find dup and offset in page. */
329 uar_va = (uintptr_t)txq_ctrl->bf_reg_orig;
330 off = uar_va & (page_size - 1); /* offset in page. */
331 uar_va = RTE_ALIGN_FLOOR(uar_va, page_size); /* page addr. */
333 for (j = 0; j != pages_n; ++j) {
334 if (pages[j] == uar_va) {
339 /* new address in reserved UAR address space. */
340 addr = RTE_PTR_ADD(priv->uar_base,
341 uar_va & (MLX5_UAR_SIZE - 1));
342 if (!already_mapped) {
343 pages[pages_n++] = uar_va;
344 /* fixed mmap to specified address in reserved
347 ret = mmap(addr, page_size,
348 PROT_WRITE, MAP_FIXED | MAP_SHARED, fd,
349 txq_ctrl->uar_mmap_offset);
351 /* fixed mmap have to return same address */
352 ERROR("call to mmap failed on UAR for txq %d\n",
358 if (rte_eal_process_type() == RTE_PROC_PRIMARY) /* save once */
359 txq_ctrl->txq.bf_reg = RTE_PTR_ADD((void *)addr, off);
361 assert(txq_ctrl->txq.bf_reg ==
362 RTE_PTR_ADD((void *)addr, off));
368 * Check if the burst function is using eMPW.
370 * @param tx_pkt_burst
371 * Tx burst function pointer.
374 * 1 if the burst function is using eMPW, 0 otherwise.
377 is_empw_burst_func(eth_tx_burst_t tx_pkt_burst)
379 if (tx_pkt_burst == mlx5_tx_burst_raw_vec ||
380 tx_pkt_burst == mlx5_tx_burst_vec ||
381 tx_pkt_burst == mlx5_tx_burst_empw)
387 * Create the Tx queue Verbs object.
390 * Pointer to private structure.
392 * Queue index in DPDK Rx queue array
395 * The Verbs object initialised if it can be created.
398 mlx5_priv_txq_ibv_new(struct priv *priv, uint16_t idx)
400 struct mlx5_txq_data *txq_data = (*priv->txqs)[idx];
401 struct mlx5_txq_ctrl *txq_ctrl =
402 container_of(txq_data, struct mlx5_txq_ctrl, txq);
403 struct mlx5_txq_ibv tmpl;
404 struct mlx5_txq_ibv *txq_ibv;
406 struct ibv_qp_init_attr_ex init;
407 struct ibv_cq_init_attr_ex cq;
408 struct ibv_qp_attr mod;
409 struct ibv_cq_ex cq_attr;
412 struct mlx5dv_qp qp = { .comp_mask = MLX5DV_QP_MASK_UAR_MMAP_OFFSET };
413 struct mlx5dv_cq cq_info;
414 struct mlx5dv_obj obj;
415 const int desc = 1 << txq_data->elts_n;
416 eth_tx_burst_t tx_pkt_burst = priv_select_tx_function(priv, priv->dev);
420 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_TX_QUEUE;
421 priv->verbs_alloc_ctx.obj = txq_ctrl;
422 if (mlx5_getenv_int("MLX5_ENABLE_CQE_COMPRESSION")) {
423 ERROR("MLX5_ENABLE_CQE_COMPRESSION must never be set");
426 memset(&tmpl, 0, sizeof(struct mlx5_txq_ibv));
427 /* MRs will be registered in mp2mr[] later. */
428 attr.cq = (struct ibv_cq_init_attr_ex){
431 cqe_n = ((desc / MLX5_TX_COMP_THRESH) - 1) ?
432 ((desc / MLX5_TX_COMP_THRESH) - 1) : 1;
433 if (is_empw_burst_func(tx_pkt_burst))
434 cqe_n += MLX5_TX_COMP_THRESH_INLINE_DIV;
435 tmpl.cq = ibv_create_cq(priv->ctx, cqe_n, NULL, NULL, 0);
436 if (tmpl.cq == NULL) {
437 ERROR("%p: CQ creation failure", (void *)txq_ctrl);
440 attr.init = (struct ibv_qp_init_attr_ex){
441 /* CQ to be associated with the send queue. */
443 /* CQ to be associated with the receive queue. */
446 /* Max number of outstanding WRs. */
448 ((priv->device_attr.orig_attr.max_qp_wr <
450 priv->device_attr.orig_attr.max_qp_wr :
453 * Max number of scatter/gather elements in a WR,
454 * must be 1 to prevent libmlx5 from trying to affect
455 * too much memory. TX gather is not impacted by the
456 * priv->device_attr.max_sge limit and will still work
461 .qp_type = IBV_QPT_RAW_PACKET,
463 * Do *NOT* enable this, completions events are managed per
468 .comp_mask = IBV_QP_INIT_ATTR_PD,
470 if (txq_data->max_inline)
471 attr.init.cap.max_inline_data = txq_ctrl->max_inline_data;
472 if (txq_data->tso_en) {
473 attr.init.max_tso_header = txq_ctrl->max_tso_header;
474 attr.init.comp_mask |= IBV_QP_INIT_ATTR_MAX_TSO_HEADER;
476 tmpl.qp = ibv_create_qp_ex(priv->ctx, &attr.init);
477 if (tmpl.qp == NULL) {
478 ERROR("%p: QP creation failure", (void *)txq_ctrl);
481 attr.mod = (struct ibv_qp_attr){
482 /* Move the QP to this state. */
483 .qp_state = IBV_QPS_INIT,
484 /* Primary port number. */
485 .port_num = priv->port
487 ret = ibv_modify_qp(tmpl.qp, &attr.mod, (IBV_QP_STATE | IBV_QP_PORT));
489 ERROR("%p: QP state to IBV_QPS_INIT failed", (void *)txq_ctrl);
492 attr.mod = (struct ibv_qp_attr){
493 .qp_state = IBV_QPS_RTR
495 ret = ibv_modify_qp(tmpl.qp, &attr.mod, IBV_QP_STATE);
497 ERROR("%p: QP state to IBV_QPS_RTR failed", (void *)txq_ctrl);
500 attr.mod.qp_state = IBV_QPS_RTS;
501 ret = ibv_modify_qp(tmpl.qp, &attr.mod, IBV_QP_STATE);
503 ERROR("%p: QP state to IBV_QPS_RTS failed", (void *)txq_ctrl);
506 txq_ibv = rte_calloc_socket(__func__, 1, sizeof(struct mlx5_txq_ibv), 0,
509 ERROR("%p: cannot allocate memory", (void *)txq_ctrl);
513 obj.cq.out = &cq_info;
516 ret = mlx5dv_init_obj(&obj, MLX5DV_OBJ_CQ | MLX5DV_OBJ_QP);
519 if (cq_info.cqe_size != RTE_CACHE_LINE_SIZE) {
520 ERROR("Wrong MLX5_CQE_SIZE environment variable value: "
521 "it should be set to %u", RTE_CACHE_LINE_SIZE);
524 txq_data->cqe_n = log2above(cq_info.cqe_cnt);
525 txq_data->qp_num_8s = tmpl.qp->qp_num << 8;
526 txq_data->wqes = qp.sq.buf;
527 txq_data->wqe_n = log2above(qp.sq.wqe_cnt);
528 txq_data->qp_db = &qp.dbrec[MLX5_SND_DBR];
529 txq_ctrl->bf_reg_orig = qp.bf.reg;
530 txq_data->cq_db = cq_info.dbrec;
532 (volatile struct mlx5_cqe (*)[])
533 (uintptr_t)cq_info.buf;
538 txq_data->wqe_ci = 0;
539 txq_data->wqe_pi = 0;
540 txq_ibv->qp = tmpl.qp;
541 txq_ibv->cq = tmpl.cq;
542 rte_atomic32_inc(&txq_ibv->refcnt);
543 if (qp.comp_mask & MLX5DV_QP_MASK_UAR_MMAP_OFFSET) {
544 txq_ctrl->uar_mmap_offset = qp.uar_mmap_offset;
546 ERROR("Failed to retrieve UAR info, invalid libmlx5.so version");
549 DEBUG("%p: Verbs Tx queue %p: refcnt %d", (void *)priv,
550 (void *)txq_ibv, rte_atomic32_read(&txq_ibv->refcnt));
551 LIST_INSERT_HEAD(&priv->txqsibv, txq_ibv, next);
552 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
556 claim_zero(ibv_destroy_cq(tmpl.cq));
558 claim_zero(ibv_destroy_qp(tmpl.qp));
559 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
564 * Get an Tx queue Verbs object.
567 * Pointer to private structure.
569 * Queue index in DPDK Rx queue array
572 * The Verbs object if it exists.
575 mlx5_priv_txq_ibv_get(struct priv *priv, uint16_t idx)
577 struct mlx5_txq_ctrl *txq_ctrl;
579 if (idx >= priv->txqs_n)
581 if (!(*priv->txqs)[idx])
583 txq_ctrl = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl, txq);
585 rte_atomic32_inc(&txq_ctrl->ibv->refcnt);
586 DEBUG("%p: Verbs Tx queue %p: refcnt %d", (void *)priv,
587 (void *)txq_ctrl->ibv,
588 rte_atomic32_read(&txq_ctrl->ibv->refcnt));
590 return txq_ctrl->ibv;
594 * Release an Tx verbs queue object.
597 * Pointer to private structure.
599 * Verbs Tx queue object.
602 * 0 on success, errno on failure.
605 mlx5_priv_txq_ibv_release(struct priv *priv, struct mlx5_txq_ibv *txq_ibv)
609 DEBUG("%p: Verbs Tx queue %p: refcnt %d", (void *)priv,
610 (void *)txq_ibv, rte_atomic32_read(&txq_ibv->refcnt));
611 if (rte_atomic32_dec_and_test(&txq_ibv->refcnt)) {
612 claim_zero(ibv_destroy_qp(txq_ibv->qp));
613 claim_zero(ibv_destroy_cq(txq_ibv->cq));
614 LIST_REMOVE(txq_ibv, next);
622 * Return true if a single reference exists on the object.
625 * Pointer to private structure.
627 * Verbs Tx queue object.
630 mlx5_priv_txq_ibv_releasable(struct priv *priv, struct mlx5_txq_ibv *txq_ibv)
634 return (rte_atomic32_read(&txq_ibv->refcnt) == 1);
638 * Verify the Verbs Tx queue list is empty
641 * Pointer to private structure.
643 * @return the number of object not released.
646 mlx5_priv_txq_ibv_verify(struct priv *priv)
649 struct mlx5_txq_ibv *txq_ibv;
651 LIST_FOREACH(txq_ibv, &priv->txqsibv, next) {
652 DEBUG("%p: Verbs Tx queue %p still referenced", (void *)priv,
660 * Set Tx queue parameters from device configuration.
663 * Pointer to Tx queue control structure.
666 txq_set_params(struct mlx5_txq_ctrl *txq_ctrl)
668 struct priv *priv = txq_ctrl->priv;
669 struct mlx5_dev_config *config = &priv->config;
670 const unsigned int max_tso_inline =
671 ((MLX5_MAX_TSO_HEADER + (RTE_CACHE_LINE_SIZE - 1)) /
672 RTE_CACHE_LINE_SIZE);
673 unsigned int txq_inline;
674 unsigned int txqs_inline;
675 unsigned int inline_max_packet_sz;
676 eth_tx_burst_t tx_pkt_burst = priv_select_tx_function(priv, priv->dev);
677 int is_empw_func = is_empw_burst_func(tx_pkt_burst);
678 int tso = !!(txq_ctrl->txq.offloads & DEV_TX_OFFLOAD_TCP_TSO);
680 txq_inline = (config->txq_inline == MLX5_ARG_UNSET) ?
681 0 : config->txq_inline;
682 txqs_inline = (config->txqs_inline == MLX5_ARG_UNSET) ?
683 0 : config->txqs_inline;
684 inline_max_packet_sz =
685 (config->inline_max_packet_sz == MLX5_ARG_UNSET) ?
686 0 : config->inline_max_packet_sz;
688 if (config->txq_inline == MLX5_ARG_UNSET)
689 txq_inline = MLX5_WQE_SIZE_MAX - MLX5_WQE_SIZE;
690 if (config->txqs_inline == MLX5_ARG_UNSET)
691 txqs_inline = MLX5_EMPW_MIN_TXQS;
692 if (config->inline_max_packet_sz == MLX5_ARG_UNSET)
693 inline_max_packet_sz = MLX5_EMPW_MAX_INLINE_LEN;
694 txq_ctrl->txq.mpw_hdr_dseg = config->mpw_hdr_dseg;
695 txq_ctrl->txq.inline_max_packet_sz = inline_max_packet_sz;
697 if (txq_inline && priv->txqs_n >= txqs_inline) {
700 txq_ctrl->txq.max_inline =
701 ((txq_inline + (RTE_CACHE_LINE_SIZE - 1)) /
702 RTE_CACHE_LINE_SIZE);
704 /* To minimize the size of data set, avoid requesting
707 txq_ctrl->max_inline_data =
708 ((RTE_MIN(txq_inline,
709 inline_max_packet_sz) +
710 (RTE_CACHE_LINE_SIZE - 1)) /
711 RTE_CACHE_LINE_SIZE) * RTE_CACHE_LINE_SIZE;
713 int inline_diff = txq_ctrl->txq.max_inline -
717 * Adjust inline value as Verbs aggregates
718 * tso_inline and txq_inline fields.
720 txq_ctrl->max_inline_data = inline_diff > 0 ?
722 RTE_CACHE_LINE_SIZE :
725 txq_ctrl->max_inline_data =
726 txq_ctrl->txq.max_inline * RTE_CACHE_LINE_SIZE;
729 * Check if the inline size is too large in a way which
730 * can make the WQE DS to overflow.
731 * Considering in calculation:
736 ds_cnt = 2 + (txq_ctrl->txq.max_inline / MLX5_WQE_DWORD_SIZE);
737 if (ds_cnt > MLX5_DSEG_MAX) {
738 unsigned int max_inline = (MLX5_DSEG_MAX - 2) *
741 max_inline = max_inline - (max_inline %
742 RTE_CACHE_LINE_SIZE);
743 WARN("txq inline is too large (%d) setting it to "
744 "the maximum possible: %d\n",
745 txq_inline, max_inline);
746 txq_ctrl->txq.max_inline = max_inline /
751 txq_ctrl->max_tso_header = max_tso_inline * RTE_CACHE_LINE_SIZE;
752 txq_ctrl->txq.max_inline = RTE_MAX(txq_ctrl->txq.max_inline,
754 txq_ctrl->txq.tso_en = 1;
756 txq_ctrl->txq.tunnel_en = config->tunnel_en;
760 * Create a DPDK Tx queue.
763 * Pointer to private structure.
767 * Number of descriptors to configure in queue.
769 * NUMA socket on which memory must be allocated.
771 * Thresholds parameters.
774 * A DPDK queue object on success.
776 struct mlx5_txq_ctrl*
777 mlx5_priv_txq_new(struct priv *priv, uint16_t idx, uint16_t desc,
779 const struct rte_eth_txconf *conf)
781 struct mlx5_txq_ctrl *tmpl;
783 tmpl = rte_calloc_socket("TXQ", 1,
785 desc * sizeof(struct rte_mbuf *),
789 assert(desc > MLX5_TX_COMP_THRESH);
790 tmpl->txq.offloads = conf->offloads;
792 tmpl->socket = socket;
793 tmpl->txq.elts_n = log2above(desc);
794 txq_set_params(tmpl);
795 /* MRs will be registered in mp2mr[] later. */
796 DEBUG("priv->device_attr.max_qp_wr is %d",
797 priv->device_attr.orig_attr.max_qp_wr);
798 DEBUG("priv->device_attr.max_sge is %d",
799 priv->device_attr.orig_attr.max_sge);
801 (struct rte_mbuf *(*)[1 << tmpl->txq.elts_n])(tmpl + 1);
802 tmpl->txq.stats.idx = idx;
803 rte_atomic32_inc(&tmpl->refcnt);
804 DEBUG("%p: Tx queue %p: refcnt %d", (void *)priv,
805 (void *)tmpl, rte_atomic32_read(&tmpl->refcnt));
806 LIST_INSERT_HEAD(&priv->txqsctrl, tmpl, next);
814 * Pointer to private structure.
819 * A pointer to the queue if it exists.
821 struct mlx5_txq_ctrl*
822 mlx5_priv_txq_get(struct priv *priv, uint16_t idx)
824 struct mlx5_txq_ctrl *ctrl = NULL;
826 if ((*priv->txqs)[idx]) {
827 ctrl = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl,
831 mlx5_priv_txq_ibv_get(priv, idx);
832 for (i = 0; i != MLX5_PMD_TX_MP_CACHE; ++i) {
833 struct mlx5_mr *mr = NULL;
836 if (ctrl->txq.mp2mr[i]) {
837 mr = priv_mr_get(priv, ctrl->txq.mp2mr[i]->mp);
841 rte_atomic32_inc(&ctrl->refcnt);
842 DEBUG("%p: Tx queue %p: refcnt %d", (void *)priv,
843 (void *)ctrl, rte_atomic32_read(&ctrl->refcnt));
849 * Release a Tx queue.
852 * Pointer to private structure.
857 * 0 on success, errno on failure.
860 mlx5_priv_txq_release(struct priv *priv, uint16_t idx)
863 struct mlx5_txq_ctrl *txq;
864 size_t page_size = sysconf(_SC_PAGESIZE);
866 if (!(*priv->txqs)[idx])
868 txq = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl, txq);
869 DEBUG("%p: Tx queue %p: refcnt %d", (void *)priv,
870 (void *)txq, rte_atomic32_read(&txq->refcnt));
874 ret = mlx5_priv_txq_ibv_release(priv, txq->ibv);
878 for (i = 0; i != MLX5_PMD_TX_MP_CACHE; ++i) {
879 if (txq->txq.mp2mr[i]) {
880 priv_mr_release(priv, txq->txq.mp2mr[i]);
881 txq->txq.mp2mr[i] = NULL;
885 munmap((void *)RTE_ALIGN_FLOOR((uintptr_t)txq->txq.bf_reg,
886 page_size), page_size);
887 if (rte_atomic32_dec_and_test(&txq->refcnt)) {
889 LIST_REMOVE(txq, next);
891 (*priv->txqs)[idx] = NULL;
898 * Verify if the queue can be released.
901 * Pointer to private structure.
906 * 1 if the queue can be released.
909 mlx5_priv_txq_releasable(struct priv *priv, uint16_t idx)
911 struct mlx5_txq_ctrl *txq;
913 if (!(*priv->txqs)[idx])
915 txq = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl, txq);
916 return (rte_atomic32_read(&txq->refcnt) == 1);
920 * Verify the Tx Queue list is empty
923 * Pointer to private structure.
925 * @return the number of object not released.
928 mlx5_priv_txq_verify(struct priv *priv)
930 struct mlx5_txq_ctrl *txq;
933 LIST_FOREACH(txq, &priv->txqsctrl, next) {
934 DEBUG("%p: Tx Queue %p still referenced", (void *)priv,