1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
15 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
17 #pragma GCC diagnostic ignored "-Wpedantic"
19 #include <infiniband/verbs.h>
20 #include <infiniband/mlx5dv.h>
22 #pragma GCC diagnostic error "-Wpedantic"
26 #include <rte_malloc.h>
27 #include <rte_ethdev_driver.h>
28 #include <rte_common.h>
30 #include <mlx5_glue.h>
31 #include <mlx5_devx_cmds.h>
32 #include <mlx5_common.h>
33 #include <mlx5_common_mr.h>
35 #include "mlx5_defs.h"
36 #include "mlx5_utils.h"
38 #include "mlx5_rxtx.h"
39 #include "mlx5_autoconf.h"
42 * Allocate TX queue elements.
45 * Pointer to TX queue structure.
48 txq_alloc_elts(struct mlx5_txq_ctrl *txq_ctrl)
50 const unsigned int elts_n = 1 << txq_ctrl->txq.elts_n;
53 for (i = 0; (i != elts_n); ++i)
54 txq_ctrl->txq.elts[i] = NULL;
55 DRV_LOG(DEBUG, "port %u Tx queue %u allocated and configured %u WRs",
56 PORT_ID(txq_ctrl->priv), txq_ctrl->txq.idx, elts_n);
57 txq_ctrl->txq.elts_head = 0;
58 txq_ctrl->txq.elts_tail = 0;
59 txq_ctrl->txq.elts_comp = 0;
63 * Free TX queue elements.
66 * Pointer to TX queue structure.
69 txq_free_elts(struct mlx5_txq_ctrl *txq_ctrl)
71 const uint16_t elts_n = 1 << txq_ctrl->txq.elts_n;
72 const uint16_t elts_m = elts_n - 1;
73 uint16_t elts_head = txq_ctrl->txq.elts_head;
74 uint16_t elts_tail = txq_ctrl->txq.elts_tail;
75 struct rte_mbuf *(*elts)[elts_n] = &txq_ctrl->txq.elts;
77 DRV_LOG(DEBUG, "port %u Tx queue %u freeing WRs",
78 PORT_ID(txq_ctrl->priv), txq_ctrl->txq.idx);
79 txq_ctrl->txq.elts_head = 0;
80 txq_ctrl->txq.elts_tail = 0;
81 txq_ctrl->txq.elts_comp = 0;
83 while (elts_tail != elts_head) {
84 struct rte_mbuf *elt = (*elts)[elts_tail & elts_m];
86 MLX5_ASSERT(elt != NULL);
87 rte_pktmbuf_free_seg(elt);
88 #ifdef RTE_LIBRTE_MLX5_DEBUG
90 memset(&(*elts)[elts_tail & elts_m],
92 sizeof((*elts)[elts_tail & elts_m]));
99 * Returns the per-port supported offloads.
102 * Pointer to Ethernet device.
105 * Supported Tx offloads.
108 mlx5_get_tx_port_offloads(struct rte_eth_dev *dev)
110 struct mlx5_priv *priv = dev->data->dev_private;
111 uint64_t offloads = (DEV_TX_OFFLOAD_MULTI_SEGS |
112 DEV_TX_OFFLOAD_VLAN_INSERT);
113 struct mlx5_dev_config *config = &priv->config;
116 offloads |= (DEV_TX_OFFLOAD_IPV4_CKSUM |
117 DEV_TX_OFFLOAD_UDP_CKSUM |
118 DEV_TX_OFFLOAD_TCP_CKSUM);
120 offloads |= DEV_TX_OFFLOAD_TCP_TSO;
123 offloads |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
125 offloads |= (DEV_TX_OFFLOAD_IP_TNL_TSO |
126 DEV_TX_OFFLOAD_UDP_TNL_TSO);
128 if (config->tunnel_en) {
130 offloads |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
132 offloads |= (DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
133 DEV_TX_OFFLOAD_GRE_TNL_TSO |
134 DEV_TX_OFFLOAD_GENEVE_TNL_TSO);
140 * Tx queue presetup checks.
143 * Pointer to Ethernet device structure.
147 * Number of descriptors to configure in queue.
150 * 0 on success, a negative errno value otherwise and rte_errno is set.
153 mlx5_tx_queue_pre_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc)
155 struct mlx5_priv *priv = dev->data->dev_private;
157 if (desc <= MLX5_TX_COMP_THRESH) {
159 "port %u number of descriptors requested for Tx queue"
160 " %u must be higher than MLX5_TX_COMP_THRESH, using %u"
162 dev->data->port_id, idx, MLX5_TX_COMP_THRESH + 1, desc);
163 desc = MLX5_TX_COMP_THRESH + 1;
165 if (!rte_is_power_of_2(desc)) {
166 desc = 1 << log2above(desc);
168 "port %u increased number of descriptors in Tx queue"
169 " %u to the next power of two (%d)",
170 dev->data->port_id, idx, desc);
172 DRV_LOG(DEBUG, "port %u configuring queue %u for %u descriptors",
173 dev->data->port_id, idx, desc);
174 if (idx >= priv->txqs_n) {
175 DRV_LOG(ERR, "port %u Tx queue index out of range (%u >= %u)",
176 dev->data->port_id, idx, priv->txqs_n);
177 rte_errno = EOVERFLOW;
180 if (!mlx5_txq_releasable(dev, idx)) {
182 DRV_LOG(ERR, "port %u unable to release queue index %u",
183 dev->data->port_id, idx);
186 mlx5_txq_release(dev, idx);
190 * DPDK callback to configure a TX queue.
193 * Pointer to Ethernet device structure.
197 * Number of descriptors to configure in queue.
199 * NUMA socket on which memory must be allocated.
201 * Thresholds parameters.
204 * 0 on success, a negative errno value otherwise and rte_errno is set.
207 mlx5_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
208 unsigned int socket, const struct rte_eth_txconf *conf)
210 struct mlx5_priv *priv = dev->data->dev_private;
211 struct mlx5_txq_data *txq = (*priv->txqs)[idx];
212 struct mlx5_txq_ctrl *txq_ctrl =
213 container_of(txq, struct mlx5_txq_ctrl, txq);
216 res = mlx5_tx_queue_pre_setup(dev, idx, desc);
219 txq_ctrl = mlx5_txq_new(dev, idx, desc, socket, conf);
221 DRV_LOG(ERR, "port %u unable to allocate queue index %u",
222 dev->data->port_id, idx);
225 DRV_LOG(DEBUG, "port %u adding Tx queue %u to list",
226 dev->data->port_id, idx);
227 (*priv->txqs)[idx] = &txq_ctrl->txq;
232 * DPDK callback to configure a TX hairpin queue.
235 * Pointer to Ethernet device structure.
239 * Number of descriptors to configure in queue.
240 * @param[in] hairpin_conf
241 * The hairpin binding configuration.
244 * 0 on success, a negative errno value otherwise and rte_errno is set.
247 mlx5_tx_hairpin_queue_setup(struct rte_eth_dev *dev, uint16_t idx,
249 const struct rte_eth_hairpin_conf *hairpin_conf)
251 struct mlx5_priv *priv = dev->data->dev_private;
252 struct mlx5_txq_data *txq = (*priv->txqs)[idx];
253 struct mlx5_txq_ctrl *txq_ctrl =
254 container_of(txq, struct mlx5_txq_ctrl, txq);
257 res = mlx5_tx_queue_pre_setup(dev, idx, desc);
260 if (hairpin_conf->peer_count != 1 ||
261 hairpin_conf->peers[0].port != dev->data->port_id ||
262 hairpin_conf->peers[0].queue >= priv->rxqs_n) {
263 DRV_LOG(ERR, "port %u unable to setup hairpin queue index %u "
264 " invalid hairpind configuration", dev->data->port_id,
269 txq_ctrl = mlx5_txq_hairpin_new(dev, idx, desc, hairpin_conf);
271 DRV_LOG(ERR, "port %u unable to allocate queue index %u",
272 dev->data->port_id, idx);
275 DRV_LOG(DEBUG, "port %u adding Tx queue %u to list",
276 dev->data->port_id, idx);
277 (*priv->txqs)[idx] = &txq_ctrl->txq;
282 * DPDK callback to release a TX queue.
285 * Generic TX queue pointer.
288 mlx5_tx_queue_release(void *dpdk_txq)
290 struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
291 struct mlx5_txq_ctrl *txq_ctrl;
292 struct mlx5_priv *priv;
297 txq_ctrl = container_of(txq, struct mlx5_txq_ctrl, txq);
298 priv = txq_ctrl->priv;
299 for (i = 0; (i != priv->txqs_n); ++i)
300 if ((*priv->txqs)[i] == txq) {
301 DRV_LOG(DEBUG, "port %u removing Tx queue %u from list",
302 PORT_ID(priv), txq->idx);
303 mlx5_txq_release(ETH_DEV(priv), i);
309 * Configure the doorbell register non-cached attribute.
312 * Pointer to Tx queue control structure.
317 txq_uar_ncattr_init(struct mlx5_txq_ctrl *txq_ctrl, size_t page_size)
319 struct mlx5_priv *priv = txq_ctrl->priv;
322 txq_ctrl->txq.db_heu = priv->config.dbnc == MLX5_TXDB_HEURISTIC;
323 txq_ctrl->txq.db_nc = 0;
324 /* Check the doorbell register mapping type. */
325 cmd = txq_ctrl->uar_mmap_offset / page_size;
326 cmd >>= MLX5_UAR_MMAP_CMD_SHIFT;
327 cmd &= MLX5_UAR_MMAP_CMD_MASK;
328 if (cmd == MLX5_MMAP_GET_NC_PAGES_CMD)
329 txq_ctrl->txq.db_nc = 1;
333 * Initialize Tx UAR registers for primary process.
336 * Pointer to Tx queue control structure.
339 txq_uar_init(struct mlx5_txq_ctrl *txq_ctrl)
341 struct mlx5_priv *priv = txq_ctrl->priv;
342 struct mlx5_proc_priv *ppriv = MLX5_PROC_PRIV(PORT_ID(priv));
343 const size_t page_size = sysconf(_SC_PAGESIZE);
345 unsigned int lock_idx;
348 if (txq_ctrl->type != MLX5_TXQ_TYPE_STANDARD)
350 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
352 ppriv->uar_table[txq_ctrl->txq.idx] = txq_ctrl->bf_reg;
353 txq_uar_ncattr_init(txq_ctrl, page_size);
355 /* Assign an UAR lock according to UAR page number */
356 lock_idx = (txq_ctrl->uar_mmap_offset / page_size) &
357 MLX5_UAR_PAGE_NUM_MASK;
358 txq_ctrl->txq.uar_lock = &priv->uar_lock[lock_idx];
363 * Remap UAR register of a Tx queue for secondary process.
365 * Remapped address is stored at the table in the process private structure of
366 * the device, indexed by queue index.
369 * Pointer to Tx queue control structure.
371 * Verbs file descriptor to map UAR pages.
374 * 0 on success, a negative errno value otherwise and rte_errno is set.
377 txq_uar_init_secondary(struct mlx5_txq_ctrl *txq_ctrl, int fd)
379 struct mlx5_priv *priv = txq_ctrl->priv;
380 struct mlx5_proc_priv *ppriv = MLX5_PROC_PRIV(PORT_ID(priv));
381 struct mlx5_txq_data *txq = &txq_ctrl->txq;
385 const size_t page_size = sysconf(_SC_PAGESIZE);
387 if (txq_ctrl->type != MLX5_TXQ_TYPE_STANDARD)
391 * As rdma-core, UARs are mapped in size of OS page
392 * size. Ref to libmlx5 function: mlx5_init_context()
394 uar_va = (uintptr_t)txq_ctrl->bf_reg;
395 offset = uar_va & (page_size - 1); /* Offset in page. */
396 addr = mmap(NULL, page_size, PROT_WRITE, MAP_SHARED, fd,
397 txq_ctrl->uar_mmap_offset);
398 if (addr == MAP_FAILED) {
400 "port %u mmap failed for BF reg of txq %u",
401 txq->port_id, txq->idx);
405 addr = RTE_PTR_ADD(addr, offset);
406 ppriv->uar_table[txq->idx] = addr;
407 txq_uar_ncattr_init(txq_ctrl, page_size);
412 * Unmap UAR register of a Tx queue for secondary process.
415 * Pointer to Tx queue control structure.
418 txq_uar_uninit_secondary(struct mlx5_txq_ctrl *txq_ctrl)
420 struct mlx5_proc_priv *ppriv = MLX5_PROC_PRIV(PORT_ID(txq_ctrl->priv));
421 const size_t page_size = sysconf(_SC_PAGESIZE);
424 if (txq_ctrl->type != MLX5_TXQ_TYPE_STANDARD)
426 addr = ppriv->uar_table[txq_ctrl->txq.idx];
427 munmap(RTE_PTR_ALIGN_FLOOR(addr, page_size), page_size);
431 * Initialize Tx UAR registers for secondary process.
434 * Pointer to Ethernet device.
436 * Verbs file descriptor to map UAR pages.
439 * 0 on success, a negative errno value otherwise and rte_errno is set.
442 mlx5_tx_uar_init_secondary(struct rte_eth_dev *dev, int fd)
444 struct mlx5_priv *priv = dev->data->dev_private;
445 struct mlx5_txq_data *txq;
446 struct mlx5_txq_ctrl *txq_ctrl;
450 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_SECONDARY);
451 for (i = 0; i != priv->txqs_n; ++i) {
452 if (!(*priv->txqs)[i])
454 txq = (*priv->txqs)[i];
455 txq_ctrl = container_of(txq, struct mlx5_txq_ctrl, txq);
456 if (txq_ctrl->type != MLX5_TXQ_TYPE_STANDARD)
458 MLX5_ASSERT(txq->idx == (uint16_t)i);
459 ret = txq_uar_init_secondary(txq_ctrl, fd);
467 if (!(*priv->txqs)[i])
469 txq = (*priv->txqs)[i];
470 txq_ctrl = container_of(txq, struct mlx5_txq_ctrl, txq);
471 txq_uar_uninit_secondary(txq_ctrl);
477 * Create the Tx hairpin queue object.
480 * Pointer to Ethernet device.
482 * Queue index in DPDK Tx queue array
485 * The hairpin DevX object initialised, NULL otherwise and rte_errno is set.
487 static struct mlx5_txq_obj *
488 mlx5_txq_obj_hairpin_new(struct rte_eth_dev *dev, uint16_t idx)
490 struct mlx5_priv *priv = dev->data->dev_private;
491 struct mlx5_txq_data *txq_data = (*priv->txqs)[idx];
492 struct mlx5_txq_ctrl *txq_ctrl =
493 container_of(txq_data, struct mlx5_txq_ctrl, txq);
494 struct mlx5_devx_create_sq_attr attr = { 0 };
495 struct mlx5_txq_obj *tmpl = NULL;
496 uint32_t max_wq_data;
498 MLX5_ASSERT(txq_data);
499 MLX5_ASSERT(!txq_ctrl->obj);
500 tmpl = rte_calloc_socket(__func__, 1, sizeof(*tmpl), 0,
504 "port %u Tx queue %u cannot allocate memory resources",
505 dev->data->port_id, txq_data->idx);
509 tmpl->type = MLX5_TXQ_OBJ_TYPE_DEVX_HAIRPIN;
510 tmpl->txq_ctrl = txq_ctrl;
513 max_wq_data = priv->config.hca_attr.log_max_hairpin_wq_data_sz;
514 /* Jumbo frames > 9KB should be supported, and more packets. */
515 if (priv->config.log_hp_size != (uint32_t)MLX5_ARG_UNSET) {
516 if (priv->config.log_hp_size > max_wq_data) {
517 DRV_LOG(ERR, "total data size %u power of 2 is "
518 "too large for hairpin",
519 priv->config.log_hp_size);
524 attr.wq_attr.log_hairpin_data_sz = priv->config.log_hp_size;
526 attr.wq_attr.log_hairpin_data_sz =
527 (max_wq_data < MLX5_HAIRPIN_JUMBO_LOG_SIZE) ?
528 max_wq_data : MLX5_HAIRPIN_JUMBO_LOG_SIZE;
530 /* Set the packets number to the maximum value for performance. */
531 attr.wq_attr.log_hairpin_num_packets =
532 attr.wq_attr.log_hairpin_data_sz -
533 MLX5_HAIRPIN_QUEUE_STRIDE;
534 attr.tis_num = priv->sh->tis->id;
535 tmpl->sq = mlx5_devx_cmd_create_sq(priv->sh->ctx, &attr);
538 "port %u tx hairpin queue %u can't create sq object",
539 dev->data->port_id, idx);
544 DRV_LOG(DEBUG, "port %u sxq %u updated with %p", dev->data->port_id,
546 rte_atomic32_inc(&tmpl->refcnt);
547 LIST_INSERT_HEAD(&priv->txqsobj, tmpl, next);
552 * Create the Tx queue Verbs object.
555 * Pointer to Ethernet device.
557 * Queue index in DPDK Tx queue array.
559 * Type of the Tx queue object to create.
562 * The Verbs object initialised, NULL otherwise and rte_errno is set.
564 struct mlx5_txq_obj *
565 mlx5_txq_obj_new(struct rte_eth_dev *dev, uint16_t idx,
566 enum mlx5_txq_obj_type type)
568 struct mlx5_priv *priv = dev->data->dev_private;
569 struct mlx5_txq_data *txq_data = (*priv->txqs)[idx];
570 struct mlx5_txq_ctrl *txq_ctrl =
571 container_of(txq_data, struct mlx5_txq_ctrl, txq);
572 struct mlx5_txq_obj tmpl;
573 struct mlx5_txq_obj *txq_obj = NULL;
575 struct ibv_qp_init_attr_ex init;
576 struct ibv_cq_init_attr_ex cq;
577 struct ibv_qp_attr mod;
580 struct mlx5dv_qp qp = { .comp_mask = MLX5DV_QP_MASK_UAR_MMAP_OFFSET };
581 struct mlx5dv_cq cq_info;
582 struct mlx5dv_obj obj;
583 const int desc = 1 << txq_data->elts_n;
586 if (type == MLX5_TXQ_OBJ_TYPE_DEVX_HAIRPIN)
587 return mlx5_txq_obj_hairpin_new(dev, idx);
588 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
589 /* If using DevX, need additional mask to read tisn value. */
590 if (priv->config.devx && !priv->sh->tdn)
591 qp.comp_mask |= MLX5DV_QP_MASK_RAW_QP_HANDLES;
593 MLX5_ASSERT(txq_data);
594 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_TX_QUEUE;
595 priv->verbs_alloc_ctx.obj = txq_ctrl;
596 if (mlx5_getenv_int("MLX5_ENABLE_CQE_COMPRESSION")) {
598 "port %u MLX5_ENABLE_CQE_COMPRESSION must never be set",
603 memset(&tmpl, 0, sizeof(struct mlx5_txq_obj));
604 attr.cq = (struct ibv_cq_init_attr_ex){
607 cqe_n = desc / MLX5_TX_COMP_THRESH +
608 1 + MLX5_TX_COMP_THRESH_INLINE_DIV;
609 tmpl.cq = mlx5_glue->create_cq(priv->sh->ctx, cqe_n, NULL, NULL, 0);
610 if (tmpl.cq == NULL) {
611 DRV_LOG(ERR, "port %u Tx queue %u CQ creation failure",
612 dev->data->port_id, idx);
616 attr.init = (struct ibv_qp_init_attr_ex){
617 /* CQ to be associated with the send queue. */
619 /* CQ to be associated with the receive queue. */
622 /* Max number of outstanding WRs. */
624 ((priv->sh->device_attr.orig_attr.max_qp_wr <
626 priv->sh->device_attr.orig_attr.max_qp_wr :
629 * Max number of scatter/gather elements in a WR,
630 * must be 1 to prevent libmlx5 from trying to affect
631 * too much memory. TX gather is not impacted by the
632 * device_attr.max_sge limit and will still work
637 .qp_type = IBV_QPT_RAW_PACKET,
639 * Do *NOT* enable this, completions events are managed per
644 .comp_mask = IBV_QP_INIT_ATTR_PD,
646 if (txq_data->inlen_send)
647 attr.init.cap.max_inline_data = txq_ctrl->max_inline_data;
648 if (txq_data->tso_en) {
649 attr.init.max_tso_header = txq_ctrl->max_tso_header;
650 attr.init.comp_mask |= IBV_QP_INIT_ATTR_MAX_TSO_HEADER;
652 tmpl.qp = mlx5_glue->create_qp_ex(priv->sh->ctx, &attr.init);
653 if (tmpl.qp == NULL) {
654 DRV_LOG(ERR, "port %u Tx queue %u QP creation failure",
655 dev->data->port_id, idx);
659 attr.mod = (struct ibv_qp_attr){
660 /* Move the QP to this state. */
661 .qp_state = IBV_QPS_INIT,
662 /* IB device port number. */
663 .port_num = (uint8_t)priv->ibv_port,
665 ret = mlx5_glue->modify_qp(tmpl.qp, &attr.mod,
666 (IBV_QP_STATE | IBV_QP_PORT));
669 "port %u Tx queue %u QP state to IBV_QPS_INIT failed",
670 dev->data->port_id, idx);
674 attr.mod = (struct ibv_qp_attr){
675 .qp_state = IBV_QPS_RTR
677 ret = mlx5_glue->modify_qp(tmpl.qp, &attr.mod, IBV_QP_STATE);
680 "port %u Tx queue %u QP state to IBV_QPS_RTR failed",
681 dev->data->port_id, idx);
685 attr.mod.qp_state = IBV_QPS_RTS;
686 ret = mlx5_glue->modify_qp(tmpl.qp, &attr.mod, IBV_QP_STATE);
689 "port %u Tx queue %u QP state to IBV_QPS_RTS failed",
690 dev->data->port_id, idx);
694 txq_obj = rte_calloc_socket(__func__, 1, sizeof(struct mlx5_txq_obj), 0,
697 DRV_LOG(ERR, "port %u Tx queue %u cannot allocate memory",
698 dev->data->port_id, idx);
703 obj.cq.out = &cq_info;
706 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_CQ | MLX5DV_OBJ_QP);
711 if (cq_info.cqe_size != RTE_CACHE_LINE_SIZE) {
713 "port %u wrong MLX5_CQE_SIZE environment variable"
714 " value: it should be set to %u",
715 dev->data->port_id, RTE_CACHE_LINE_SIZE);
719 txq_data->cqe_n = log2above(cq_info.cqe_cnt);
720 txq_data->cqe_s = 1 << txq_data->cqe_n;
721 txq_data->cqe_m = txq_data->cqe_s - 1;
722 txq_data->qp_num_8s = tmpl.qp->qp_num << 8;
723 txq_data->wqes = qp.sq.buf;
724 txq_data->wqe_n = log2above(qp.sq.wqe_cnt);
725 txq_data->wqe_s = 1 << txq_data->wqe_n;
726 txq_data->wqe_m = txq_data->wqe_s - 1;
727 txq_data->wqes_end = txq_data->wqes + txq_data->wqe_s;
728 txq_data->qp_db = &qp.dbrec[MLX5_SND_DBR];
729 txq_data->cq_db = cq_info.dbrec;
730 txq_data->cqes = (volatile struct mlx5_cqe *)cq_info.buf;
733 txq_data->wqe_ci = 0;
734 txq_data->wqe_pi = 0;
735 txq_data->wqe_comp = 0;
736 txq_data->wqe_thres = txq_data->wqe_s / MLX5_TX_COMP_THRESH_INLINE_DIV;
737 txq_data->fcqs = rte_calloc_socket(__func__,
739 sizeof(*txq_data->fcqs),
742 if (!txq_data->fcqs) {
743 DRV_LOG(ERR, "port %u Tx queue %u cannot allocate memory (FCQ)",
744 dev->data->port_id, idx);
748 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
750 * If using DevX need to query and store TIS transport domain value.
751 * This is done once per port.
752 * Will use this value on Rx, when creating matching TIR.
754 if (priv->config.devx && !priv->sh->tdn) {
755 ret = mlx5_devx_cmd_qp_query_tis_td(tmpl.qp, qp.tisn,
758 DRV_LOG(ERR, "Fail to query port %u Tx queue %u QP TIS "
759 "transport domain", dev->data->port_id, idx);
763 DRV_LOG(DEBUG, "port %u Tx queue %u TIS number %d "
764 "transport domain %d", dev->data->port_id,
765 idx, qp.tisn, priv->sh->tdn);
769 txq_obj->qp = tmpl.qp;
770 txq_obj->cq = tmpl.cq;
771 rte_atomic32_inc(&txq_obj->refcnt);
772 txq_ctrl->bf_reg = qp.bf.reg;
773 if (qp.comp_mask & MLX5DV_QP_MASK_UAR_MMAP_OFFSET) {
774 txq_ctrl->uar_mmap_offset = qp.uar_mmap_offset;
775 DRV_LOG(DEBUG, "port %u: uar_mmap_offset 0x%"PRIx64,
776 dev->data->port_id, txq_ctrl->uar_mmap_offset);
779 "port %u failed to retrieve UAR info, invalid"
785 txq_uar_init(txq_ctrl);
786 LIST_INSERT_HEAD(&priv->txqsobj, txq_obj, next);
787 txq_obj->txq_ctrl = txq_ctrl;
788 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
791 ret = rte_errno; /* Save rte_errno before cleanup. */
793 claim_zero(mlx5_glue->destroy_cq(tmpl.cq));
795 claim_zero(mlx5_glue->destroy_qp(tmpl.qp));
797 rte_free(txq_data->fcqs);
800 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
801 rte_errno = ret; /* Restore rte_errno. */
806 * Get an Tx queue Verbs object.
809 * Pointer to Ethernet device.
811 * Queue index in DPDK Tx queue array.
814 * The Verbs object if it exists.
816 struct mlx5_txq_obj *
817 mlx5_txq_obj_get(struct rte_eth_dev *dev, uint16_t idx)
819 struct mlx5_priv *priv = dev->data->dev_private;
820 struct mlx5_txq_ctrl *txq_ctrl;
822 if (idx >= priv->txqs_n)
824 if (!(*priv->txqs)[idx])
826 txq_ctrl = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl, txq);
828 rte_atomic32_inc(&txq_ctrl->obj->refcnt);
829 return txq_ctrl->obj;
833 * Release an Tx verbs queue object.
836 * Verbs Tx queue object.
839 * 1 while a reference on it exists, 0 when freed.
842 mlx5_txq_obj_release(struct mlx5_txq_obj *txq_obj)
844 MLX5_ASSERT(txq_obj);
845 if (rte_atomic32_dec_and_test(&txq_obj->refcnt)) {
846 if (txq_obj->type == MLX5_TXQ_OBJ_TYPE_DEVX_HAIRPIN) {
848 claim_zero(mlx5_devx_cmd_destroy(txq_obj->tis));
850 claim_zero(mlx5_glue->destroy_qp(txq_obj->qp));
851 claim_zero(mlx5_glue->destroy_cq(txq_obj->cq));
852 if (txq_obj->txq_ctrl->txq.fcqs)
853 rte_free(txq_obj->txq_ctrl->txq.fcqs);
855 LIST_REMOVE(txq_obj, next);
863 * Verify the Verbs Tx queue list is empty
866 * Pointer to Ethernet device.
869 * The number of object not released.
872 mlx5_txq_obj_verify(struct rte_eth_dev *dev)
874 struct mlx5_priv *priv = dev->data->dev_private;
876 struct mlx5_txq_obj *txq_obj;
878 LIST_FOREACH(txq_obj, &priv->txqsobj, next) {
879 DRV_LOG(DEBUG, "port %u Verbs Tx queue %u still referenced",
880 dev->data->port_id, txq_obj->txq_ctrl->txq.idx);
887 * Calculate the total number of WQEBB for Tx queue.
889 * Simplified version of calc_sq_size() in rdma-core.
892 * Pointer to Tx queue control structure.
895 * The number of WQEBB.
898 txq_calc_wqebb_cnt(struct mlx5_txq_ctrl *txq_ctrl)
900 unsigned int wqe_size;
901 const unsigned int desc = 1 << txq_ctrl->txq.elts_n;
903 wqe_size = MLX5_WQE_CSEG_SIZE +
906 MLX5_ESEG_MIN_INLINE_SIZE +
907 txq_ctrl->max_inline_data;
908 return rte_align32pow2(wqe_size * desc) / MLX5_WQE_SIZE;
912 * Calculate the maximal inline data size for Tx queue.
915 * Pointer to Tx queue control structure.
918 * The maximal inline data size.
921 txq_calc_inline_max(struct mlx5_txq_ctrl *txq_ctrl)
923 const unsigned int desc = 1 << txq_ctrl->txq.elts_n;
924 struct mlx5_priv *priv = txq_ctrl->priv;
925 unsigned int wqe_size;
927 wqe_size = priv->sh->device_attr.orig_attr.max_qp_wr / desc;
931 * This calculation is derived from tthe source of
932 * mlx5_calc_send_wqe() in rdma_core library.
934 wqe_size = wqe_size * MLX5_WQE_SIZE -
939 MLX5_DSEG_MIN_INLINE_SIZE;
944 * Set Tx queue parameters from device configuration.
947 * Pointer to Tx queue control structure.
950 txq_set_params(struct mlx5_txq_ctrl *txq_ctrl)
952 struct mlx5_priv *priv = txq_ctrl->priv;
953 struct mlx5_dev_config *config = &priv->config;
954 unsigned int inlen_send; /* Inline data for ordinary SEND.*/
955 unsigned int inlen_empw; /* Inline data for enhanced MPW. */
956 unsigned int inlen_mode; /* Minimal required Inline data. */
957 unsigned int txqs_inline; /* Min Tx queues to enable inline. */
958 uint64_t dev_txoff = priv->dev_data->dev_conf.txmode.offloads;
959 bool tso = txq_ctrl->txq.offloads & (DEV_TX_OFFLOAD_TCP_TSO |
960 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
961 DEV_TX_OFFLOAD_GRE_TNL_TSO |
962 DEV_TX_OFFLOAD_IP_TNL_TSO |
963 DEV_TX_OFFLOAD_UDP_TNL_TSO);
967 if (config->txqs_inline == MLX5_ARG_UNSET)
969 #if defined(RTE_ARCH_ARM64)
970 (priv->pci_dev->id.device_id ==
971 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF) ?
972 MLX5_INLINE_MAX_TXQS_BLUEFIELD :
974 MLX5_INLINE_MAX_TXQS;
976 txqs_inline = (unsigned int)config->txqs_inline;
977 inlen_send = (config->txq_inline_max == MLX5_ARG_UNSET) ?
978 MLX5_SEND_DEF_INLINE_LEN :
979 (unsigned int)config->txq_inline_max;
980 inlen_empw = (config->txq_inline_mpw == MLX5_ARG_UNSET) ?
981 MLX5_EMPW_DEF_INLINE_LEN :
982 (unsigned int)config->txq_inline_mpw;
983 inlen_mode = (config->txq_inline_min == MLX5_ARG_UNSET) ?
984 0 : (unsigned int)config->txq_inline_min;
985 if (config->mps != MLX5_MPW_ENHANCED && config->mps != MLX5_MPW)
988 * If there is requested minimal amount of data to inline
989 * we MUST enable inlining. This is a case for ConnectX-4
990 * which usually requires L2 inlined for correct operating
991 * and ConnectX-4 Lx which requires L2-L4 inlined to
992 * support E-Switch Flows.
995 if (inlen_mode <= MLX5_ESEG_MIN_INLINE_SIZE) {
997 * Optimize minimal inlining for single
998 * segment packets to fill one WQEBB
1001 temp = MLX5_ESEG_MIN_INLINE_SIZE;
1003 temp = inlen_mode - MLX5_ESEG_MIN_INLINE_SIZE;
1004 temp = RTE_ALIGN(temp, MLX5_WSEG_SIZE) +
1005 MLX5_ESEG_MIN_INLINE_SIZE;
1006 temp = RTE_MIN(temp, MLX5_SEND_MAX_INLINE_LEN);
1008 if (temp != inlen_mode) {
1010 "port %u minimal required inline setting"
1011 " aligned from %u to %u",
1012 PORT_ID(priv), inlen_mode, temp);
1017 * If port is configured to support VLAN insertion and device
1018 * does not support this feature by HW (for NICs before ConnectX-5
1019 * or in case of wqe_vlan_insert flag is not set) we must enable
1020 * data inline on all queues because it is supported by single
1023 txq_ctrl->txq.vlan_en = config->hw_vlan_insert;
1024 vlan_inline = (dev_txoff & DEV_TX_OFFLOAD_VLAN_INSERT) &&
1025 !config->hw_vlan_insert;
1027 * If there are few Tx queues it is prioritized
1028 * to save CPU cycles and disable data inlining at all.
1030 if (inlen_send && priv->txqs_n >= txqs_inline) {
1032 * The data sent with ordinal MLX5_OPCODE_SEND
1033 * may be inlined in Ethernet Segment, align the
1034 * length accordingly to fit entire WQEBBs.
1036 temp = RTE_MAX(inlen_send,
1037 MLX5_ESEG_MIN_INLINE_SIZE + MLX5_WQE_DSEG_SIZE);
1038 temp -= MLX5_ESEG_MIN_INLINE_SIZE + MLX5_WQE_DSEG_SIZE;
1039 temp = RTE_ALIGN(temp, MLX5_WQE_SIZE);
1040 temp += MLX5_ESEG_MIN_INLINE_SIZE + MLX5_WQE_DSEG_SIZE;
1041 temp = RTE_MIN(temp, MLX5_WQE_SIZE_MAX +
1042 MLX5_ESEG_MIN_INLINE_SIZE -
1043 MLX5_WQE_CSEG_SIZE -
1044 MLX5_WQE_ESEG_SIZE -
1045 MLX5_WQE_DSEG_SIZE * 2);
1046 temp = RTE_MIN(temp, MLX5_SEND_MAX_INLINE_LEN);
1047 temp = RTE_MAX(temp, inlen_mode);
1048 if (temp != inlen_send) {
1050 "port %u ordinary send inline setting"
1051 " aligned from %u to %u",
1052 PORT_ID(priv), inlen_send, temp);
1056 * Not aligned to cache lines, but to WQEs.
1057 * First bytes of data (initial alignment)
1058 * is going to be copied explicitly at the
1059 * beginning of inlining buffer in Ethernet
1062 MLX5_ASSERT(inlen_send >= MLX5_ESEG_MIN_INLINE_SIZE);
1063 MLX5_ASSERT(inlen_send <= MLX5_WQE_SIZE_MAX +
1064 MLX5_ESEG_MIN_INLINE_SIZE -
1065 MLX5_WQE_CSEG_SIZE -
1066 MLX5_WQE_ESEG_SIZE -
1067 MLX5_WQE_DSEG_SIZE * 2);
1068 } else if (inlen_mode) {
1070 * If minimal inlining is requested we must
1071 * enable inlining in general, despite the
1072 * number of configured queues. Ignore the
1073 * txq_inline_max devarg, this is not
1074 * full-featured inline.
1076 inlen_send = inlen_mode;
1078 } else if (vlan_inline) {
1080 * Hardware does not report offload for
1081 * VLAN insertion, we must enable data inline
1082 * to implement feature by software.
1084 inlen_send = MLX5_ESEG_MIN_INLINE_SIZE;
1090 txq_ctrl->txq.inlen_send = inlen_send;
1091 txq_ctrl->txq.inlen_mode = inlen_mode;
1092 txq_ctrl->txq.inlen_empw = 0;
1093 if (inlen_send && inlen_empw && priv->txqs_n >= txqs_inline) {
1095 * The data sent with MLX5_OPCODE_ENHANCED_MPSW
1096 * may be inlined in Data Segment, align the
1097 * length accordingly to fit entire WQEBBs.
1099 temp = RTE_MAX(inlen_empw,
1100 MLX5_WQE_SIZE + MLX5_DSEG_MIN_INLINE_SIZE);
1101 temp -= MLX5_DSEG_MIN_INLINE_SIZE;
1102 temp = RTE_ALIGN(temp, MLX5_WQE_SIZE);
1103 temp += MLX5_DSEG_MIN_INLINE_SIZE;
1104 temp = RTE_MIN(temp, MLX5_WQE_SIZE_MAX +
1105 MLX5_DSEG_MIN_INLINE_SIZE -
1106 MLX5_WQE_CSEG_SIZE -
1107 MLX5_WQE_ESEG_SIZE -
1108 MLX5_WQE_DSEG_SIZE);
1109 temp = RTE_MIN(temp, MLX5_EMPW_MAX_INLINE_LEN);
1110 if (temp != inlen_empw) {
1112 "port %u enhanced empw inline setting"
1113 " aligned from %u to %u",
1114 PORT_ID(priv), inlen_empw, temp);
1117 MLX5_ASSERT(inlen_empw >= MLX5_ESEG_MIN_INLINE_SIZE);
1118 MLX5_ASSERT(inlen_empw <= MLX5_WQE_SIZE_MAX +
1119 MLX5_DSEG_MIN_INLINE_SIZE -
1120 MLX5_WQE_CSEG_SIZE -
1121 MLX5_WQE_ESEG_SIZE -
1122 MLX5_WQE_DSEG_SIZE);
1123 txq_ctrl->txq.inlen_empw = inlen_empw;
1125 txq_ctrl->max_inline_data = RTE_MAX(inlen_send, inlen_empw);
1127 txq_ctrl->max_tso_header = MLX5_MAX_TSO_HEADER;
1128 txq_ctrl->max_inline_data = RTE_MAX(txq_ctrl->max_inline_data,
1129 MLX5_MAX_TSO_HEADER);
1130 txq_ctrl->txq.tso_en = 1;
1132 txq_ctrl->txq.tunnel_en = config->tunnel_en | config->swp;
1133 txq_ctrl->txq.swp_en = ((DEV_TX_OFFLOAD_IP_TNL_TSO |
1134 DEV_TX_OFFLOAD_UDP_TNL_TSO |
1135 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM) &
1136 txq_ctrl->txq.offloads) && config->swp;
1140 * Adjust Tx queue data inline parameters for large queue sizes.
1141 * The data inline feature requires multiple WQEs to fit the packets,
1142 * and if the large amount of Tx descriptors is requested by application
1143 * the total WQE amount may exceed the hardware capabilities. If the
1144 * default inline setting are used we can try to adjust these ones and
1145 * meet the hardware requirements and not exceed the queue size.
1148 * Pointer to Tx queue control structure.
1151 * Zero on success, otherwise the parameters can not be adjusted.
1154 txq_adjust_params(struct mlx5_txq_ctrl *txq_ctrl)
1156 struct mlx5_priv *priv = txq_ctrl->priv;
1157 struct mlx5_dev_config *config = &priv->config;
1158 unsigned int max_inline;
1160 max_inline = txq_calc_inline_max(txq_ctrl);
1161 if (!txq_ctrl->txq.inlen_send) {
1163 * Inline data feature is not engaged at all.
1164 * There is nothing to adjust.
1168 if (txq_ctrl->max_inline_data <= max_inline) {
1170 * The requested inline data length does not
1171 * exceed queue capabilities.
1175 if (txq_ctrl->txq.inlen_mode > max_inline) {
1177 "minimal data inline requirements (%u) are not"
1178 " satisfied (%u) on port %u, try the smaller"
1179 " Tx queue size (%d)",
1180 txq_ctrl->txq.inlen_mode, max_inline,
1181 priv->dev_data->port_id,
1182 priv->sh->device_attr.orig_attr.max_qp_wr);
1185 if (txq_ctrl->txq.inlen_send > max_inline &&
1186 config->txq_inline_max != MLX5_ARG_UNSET &&
1187 config->txq_inline_max > (int)max_inline) {
1189 "txq_inline_max requirements (%u) are not"
1190 " satisfied (%u) on port %u, try the smaller"
1191 " Tx queue size (%d)",
1192 txq_ctrl->txq.inlen_send, max_inline,
1193 priv->dev_data->port_id,
1194 priv->sh->device_attr.orig_attr.max_qp_wr);
1197 if (txq_ctrl->txq.inlen_empw > max_inline &&
1198 config->txq_inline_mpw != MLX5_ARG_UNSET &&
1199 config->txq_inline_mpw > (int)max_inline) {
1201 "txq_inline_mpw requirements (%u) are not"
1202 " satisfied (%u) on port %u, try the smaller"
1203 " Tx queue size (%d)",
1204 txq_ctrl->txq.inlen_empw, max_inline,
1205 priv->dev_data->port_id,
1206 priv->sh->device_attr.orig_attr.max_qp_wr);
1209 if (txq_ctrl->txq.tso_en && max_inline < MLX5_MAX_TSO_HEADER) {
1211 "tso header inline requirements (%u) are not"
1212 " satisfied (%u) on port %u, try the smaller"
1213 " Tx queue size (%d)",
1214 MLX5_MAX_TSO_HEADER, max_inline,
1215 priv->dev_data->port_id,
1216 priv->sh->device_attr.orig_attr.max_qp_wr);
1219 if (txq_ctrl->txq.inlen_send > max_inline) {
1221 "adjust txq_inline_max (%u->%u)"
1222 " due to large Tx queue on port %u",
1223 txq_ctrl->txq.inlen_send, max_inline,
1224 priv->dev_data->port_id);
1225 txq_ctrl->txq.inlen_send = max_inline;
1227 if (txq_ctrl->txq.inlen_empw > max_inline) {
1229 "adjust txq_inline_mpw (%u->%u)"
1230 "due to large Tx queue on port %u",
1231 txq_ctrl->txq.inlen_empw, max_inline,
1232 priv->dev_data->port_id);
1233 txq_ctrl->txq.inlen_empw = max_inline;
1235 txq_ctrl->max_inline_data = RTE_MAX(txq_ctrl->txq.inlen_send,
1236 txq_ctrl->txq.inlen_empw);
1237 MLX5_ASSERT(txq_ctrl->max_inline_data <= max_inline);
1238 MLX5_ASSERT(txq_ctrl->txq.inlen_mode <= max_inline);
1239 MLX5_ASSERT(txq_ctrl->txq.inlen_mode <= txq_ctrl->txq.inlen_send);
1240 MLX5_ASSERT(txq_ctrl->txq.inlen_mode <= txq_ctrl->txq.inlen_empw ||
1241 !txq_ctrl->txq.inlen_empw);
1249 * Create a DPDK Tx queue.
1252 * Pointer to Ethernet device.
1256 * Number of descriptors to configure in queue.
1258 * NUMA socket on which memory must be allocated.
1260 * Thresholds parameters.
1263 * A DPDK queue object on success, NULL otherwise and rte_errno is set.
1265 struct mlx5_txq_ctrl *
1266 mlx5_txq_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1267 unsigned int socket, const struct rte_eth_txconf *conf)
1269 struct mlx5_priv *priv = dev->data->dev_private;
1270 struct mlx5_txq_ctrl *tmpl;
1272 tmpl = rte_calloc_socket("TXQ", 1,
1274 desc * sizeof(struct rte_mbuf *),
1280 if (mlx5_mr_btree_init(&tmpl->txq.mr_ctrl.cache_bh,
1281 MLX5_MR_BTREE_CACHE_N, socket)) {
1282 /* rte_errno is already set. */
1285 /* Save pointer of global generation number to check memory event. */
1286 tmpl->txq.mr_ctrl.dev_gen_ptr = &priv->sh->share_cache.dev_gen;
1287 MLX5_ASSERT(desc > MLX5_TX_COMP_THRESH);
1288 tmpl->txq.offloads = conf->offloads |
1289 dev->data->dev_conf.txmode.offloads;
1291 tmpl->socket = socket;
1292 tmpl->txq.elts_n = log2above(desc);
1293 tmpl->txq.elts_s = desc;
1294 tmpl->txq.elts_m = desc - 1;
1295 tmpl->txq.port_id = dev->data->port_id;
1296 tmpl->txq.idx = idx;
1297 txq_set_params(tmpl);
1298 if (txq_adjust_params(tmpl))
1300 if (txq_calc_wqebb_cnt(tmpl) >
1301 priv->sh->device_attr.orig_attr.max_qp_wr) {
1303 "port %u Tx WQEBB count (%d) exceeds the limit (%d),"
1304 " try smaller queue size",
1305 dev->data->port_id, txq_calc_wqebb_cnt(tmpl),
1306 priv->sh->device_attr.orig_attr.max_qp_wr);
1310 rte_atomic32_inc(&tmpl->refcnt);
1311 tmpl->type = MLX5_TXQ_TYPE_STANDARD;
1312 LIST_INSERT_HEAD(&priv->txqsctrl, tmpl, next);
1320 * Create a DPDK Tx hairpin queue.
1323 * Pointer to Ethernet device.
1327 * Number of descriptors to configure in queue.
1328 * @param hairpin_conf
1329 * The hairpin configuration.
1332 * A DPDK queue object on success, NULL otherwise and rte_errno is set.
1334 struct mlx5_txq_ctrl *
1335 mlx5_txq_hairpin_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1336 const struct rte_eth_hairpin_conf *hairpin_conf)
1338 struct mlx5_priv *priv = dev->data->dev_private;
1339 struct mlx5_txq_ctrl *tmpl;
1341 tmpl = rte_calloc_socket("TXQ", 1,
1342 sizeof(*tmpl), 0, SOCKET_ID_ANY);
1348 tmpl->socket = SOCKET_ID_ANY;
1349 tmpl->txq.elts_n = log2above(desc);
1350 tmpl->txq.port_id = dev->data->port_id;
1351 tmpl->txq.idx = idx;
1352 tmpl->hairpin_conf = *hairpin_conf;
1353 tmpl->type = MLX5_TXQ_TYPE_HAIRPIN;
1354 rte_atomic32_inc(&tmpl->refcnt);
1355 LIST_INSERT_HEAD(&priv->txqsctrl, tmpl, next);
1363 * Pointer to Ethernet device.
1368 * A pointer to the queue if it exists.
1370 struct mlx5_txq_ctrl *
1371 mlx5_txq_get(struct rte_eth_dev *dev, uint16_t idx)
1373 struct mlx5_priv *priv = dev->data->dev_private;
1374 struct mlx5_txq_ctrl *ctrl = NULL;
1376 if ((*priv->txqs)[idx]) {
1377 ctrl = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl,
1379 mlx5_txq_obj_get(dev, idx);
1380 rte_atomic32_inc(&ctrl->refcnt);
1386 * Release a Tx queue.
1389 * Pointer to Ethernet device.
1394 * 1 while a reference on it exists, 0 when freed.
1397 mlx5_txq_release(struct rte_eth_dev *dev, uint16_t idx)
1399 struct mlx5_priv *priv = dev->data->dev_private;
1400 struct mlx5_txq_ctrl *txq;
1402 if (!(*priv->txqs)[idx])
1404 txq = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl, txq);
1405 if (txq->obj && !mlx5_txq_obj_release(txq->obj))
1407 if (rte_atomic32_dec_and_test(&txq->refcnt)) {
1409 mlx5_mr_btree_free(&txq->txq.mr_ctrl.cache_bh);
1410 LIST_REMOVE(txq, next);
1412 (*priv->txqs)[idx] = NULL;
1419 * Verify if the queue can be released.
1422 * Pointer to Ethernet device.
1427 * 1 if the queue can be released.
1430 mlx5_txq_releasable(struct rte_eth_dev *dev, uint16_t idx)
1432 struct mlx5_priv *priv = dev->data->dev_private;
1433 struct mlx5_txq_ctrl *txq;
1435 if (!(*priv->txqs)[idx])
1437 txq = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl, txq);
1438 return (rte_atomic32_read(&txq->refcnt) == 1);
1442 * Verify the Tx Queue list is empty
1445 * Pointer to Ethernet device.
1448 * The number of object not released.
1451 mlx5_txq_verify(struct rte_eth_dev *dev)
1453 struct mlx5_priv *priv = dev->data->dev_private;
1454 struct mlx5_txq_ctrl *txq_ctrl;
1457 LIST_FOREACH(txq_ctrl, &priv->txqsctrl, next) {
1458 DRV_LOG(DEBUG, "port %u Tx queue %u still referenced",
1459 dev->data->port_id, txq_ctrl->txq.idx);