drivers/net/mlx5/windows/mlx5_os.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2020 Mellanox Technologies, Ltd
   3  */
   4
   5 #include <errno.h>
   6 #include <stdalign.h>
   7 #include <stddef.h>
   8 #include <stdint.h>
   9 #include <stdlib.h>
  10
  11 #include <rte_windows.h>
  12 #include <ethdev_pci.h>
  13
  14 #include <mlx5_glue.h>
  15 #include <mlx5_devx_cmds.h>
  16 #include <mlx5_common.h>
  17 #include <mlx5_common_mp.h>
  18 #include <mlx5_common_mr.h>
  19 #include <mlx5_malloc.h>
  20
  21 #include "mlx5_defs.h"
  22 #include "mlx5.h"
  23 #include "mlx5_common_os.h"
  24 #include "mlx5_utils.h"
  25 #include "mlx5_rxtx.h"
  26 #include "mlx5_rx.h"
  27 #include "mlx5_tx.h"
  28 #include "mlx5_autoconf.h"
  29 #include "mlx5_mr.h"
  30 #include "mlx5_flow.h"
  31 #include "mlx5_devx.h"
  32
  33 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data";
  34
  35 /* Spinlock for mlx5_shared_data allocation. */
  36 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER;
  37
  38 /* rte flow indexed pool configuration. */
  39 static struct mlx5_indexed_pool_config icfg[] = {
  40         {
  41                 .size = sizeof(struct rte_flow),
  42                 .trunk_size = 64,
  43                 .need_lock = 1,
  44                 .release_mem_en = 0,
  45                 .malloc = mlx5_malloc,
  46                 .free = mlx5_free,
  47                 .per_core_cache = 0,
  48                 .type = "ctl_flow_ipool",
  49         },
  50         {
  51                 .size = sizeof(struct rte_flow),
  52                 .trunk_size = 64,
  53                 .grow_trunk = 3,
  54                 .grow_shift = 2,
  55                 .need_lock = 1,
  56                 .release_mem_en = 0,
  57                 .malloc = mlx5_malloc,
  58                 .free = mlx5_free,
  59                 .per_core_cache = 1 << 14,
  60                 .type = "rte_flow_ipool",
  61         },
  62         {
  63                 .size = sizeof(struct rte_flow),
  64                 .trunk_size = 64,
  65                 .grow_trunk = 3,
  66                 .grow_shift = 2,
  67                 .need_lock = 1,
  68                 .release_mem_en = 0,
  69                 .malloc = mlx5_malloc,
  70                 .free = mlx5_free,
  71                 .per_core_cache = 0,
  72                 .type = "mcp_flow_ipool",
  73         },
  74 };
  75
  76 /**
  77  * Initialize shared data between primary and secondary process.
  78  *
  79  * A memzone is reserved by primary process and secondary processes attach to
  80  * the memzone.
  81  *
  82  * @return
  83  *   0 on success, a negative errno value otherwise and rte_errno is set.
  84  */
  85 static int
  86 mlx5_init_shared_data(void)
  87 {
  88         const struct rte_memzone *mz;
  89         int ret = 0;
  90
  91         rte_spinlock_lock(&mlx5_shared_data_lock);
  92         if (mlx5_shared_data == NULL) {
  93                 /* Allocate shared memory. */
  94                 mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA,
  95                                          sizeof(*mlx5_shared_data),
  96                                          SOCKET_ID_ANY, 0);
  97                 if (mz == NULL) {
  98                         DRV_LOG(ERR,
  99                                 "Cannot allocate mlx5 shared data");
 100                         ret = -rte_errno;
 101                         goto error;
 102                 }
 103                 mlx5_shared_data = mz->addr;
 104                 memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data));
 105                 rte_spinlock_init(&mlx5_shared_data->lock);
 106         }
 107 error:
 108         rte_spinlock_unlock(&mlx5_shared_data_lock);
 109         return ret;
 110 }
 111
 112 /**
 113  * PMD global initialization.
 114  *
 115  * Independent from individual device, this function initializes global
 116  * per-PMD data structures distinguishing primary and secondary processes.
 117  * Hence, each initialization is called once per a process.
 118  *
 119  * @return
 120  *   0 on success, a negative errno value otherwise and rte_errno is set.
 121  */
 122 static int
 123 mlx5_init_once(void)
 124 {
 125         struct mlx5_shared_data *sd;
 126
 127         if (mlx5_init_shared_data())
 128                 return -rte_errno;
 129         sd = mlx5_shared_data;
 130         rte_spinlock_lock(&sd->lock);
 131         MLX5_ASSERT(sd);
 132         if (!sd->init_done) {
 133                 LIST_INIT(&sd->mem_event_cb_list);
 134                 rte_rwlock_init(&sd->mem_event_rwlock);
 135                 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB",
 136                                                 mlx5_mr_mem_event_cb, NULL);
 137                 sd->init_done = true;
 138         }
 139         rte_spinlock_unlock(&sd->lock);
 140         return 0;
 141 }
 142
 143 /**
 144  * Get mlx5 device attributes.
 145  *
 146  * @param cdev
 147  *   Pointer to mlx5 device.
 148  *
 149  * @param device_attr
 150  *   Pointer to mlx5 device attributes.
 151  *
 152  * @return
 153  *   0 on success, non zero error number otherwise.
 154  */
 155 int
 156 mlx5_os_get_dev_attr(struct mlx5_common_device *cdev,
 157                      struct mlx5_dev_attr *device_attr)
 158 {
 159         struct mlx5_context *mlx5_ctx;
 160         void *pv_iseg = NULL;
 161         u32 cb_iseg = 0;
 162         int err = 0;
 163
 164         if (!cdev || !cdev->ctx)
 165                 return -EINVAL;
 166         mlx5_ctx = (struct mlx5_context *)cdev->ctx;
 167         memset(device_attr, 0, sizeof(*device_attr));
 168         device_attr->max_cq = 1 << cdev->config.hca_attr.log_max_cq;
 169         device_attr->max_qp = 1 << cdev->config.hca_attr.log_max_qp;
 170         device_attr->max_qp_wr = 1 << cdev->config.hca_attr.log_max_qp_sz;
 171         device_attr->max_cqe = 1 << cdev->config.hca_attr.log_max_cq_sz;
 172         device_attr->max_mr = 1 << cdev->config.hca_attr.log_max_mrw_sz;
 173         device_attr->max_pd = 1 << cdev->config.hca_attr.log_max_pd;
 174         device_attr->max_srq = 1 << cdev->config.hca_attr.log_max_srq;
 175         device_attr->max_srq_wr = 1 << cdev->config.hca_attr.log_max_srq_sz;
 176         device_attr->max_tso = 1 << cdev->config.hca_attr.max_lso_cap;
 177         if (cdev->config.hca_attr.rss_ind_tbl_cap) {
 178                 device_attr->max_rwq_indirection_table_size =
 179                         1 << cdev->config.hca_attr.rss_ind_tbl_cap;
 180         }
 181         device_attr->sw_parsing_offloads =
 182                 mlx5_get_supported_sw_parsing_offloads(&cdev->config.hca_attr);
 183         device_attr->tunnel_offloads_caps =
 184                 mlx5_get_supported_tunneling_offloads(&cdev->config.hca_attr);
 185         pv_iseg = mlx5_glue->query_hca_iseg(mlx5_ctx, &cb_iseg);
 186         if (pv_iseg == NULL) {
 187                 DRV_LOG(ERR, "Failed to get device hca_iseg");
 188                 return errno;
 189         }
 190         if (!err) {
 191                 snprintf(device_attr->fw_ver, 64, "%x.%x.%04x",
 192                         MLX5_GET(initial_seg, pv_iseg, fw_rev_major),
 193                         MLX5_GET(initial_seg, pv_iseg, fw_rev_minor),
 194                         MLX5_GET(initial_seg, pv_iseg, fw_rev_subminor));
 195         }
 196         return err;
 197 }
 198
 199 /**
 200  * Initialize DR related data within private structure.
 201  * Routine checks the reference counter and does actual
 202  * resources creation/initialization only if counter is zero.
 203  *
 204  * @param[in] priv
 205  *   Pointer to the private device data structure.
 206  *
 207  * @return
 208  *   Zero on success, positive error code otherwise.
 209  */
 210 static int
 211 mlx5_alloc_shared_dr(struct mlx5_priv *priv)
 212 {
 213         struct mlx5_dev_ctx_shared *sh = priv->sh;
 214         int err = 0;
 215
 216         if (!sh->flow_tbls)
 217                 err = mlx5_alloc_table_hash_list(priv);
 218         else
 219                 DRV_LOG(DEBUG, "sh->flow_tbls[%p] already created, reuse",
 220                         (void *)sh->flow_tbls);
 221         return err;
 222 }
 223 /**
 224  * Destroy DR related data within private structure.
 225  *
 226  * @param[in] priv
 227  *   Pointer to the private device data structure.
 228  */
 229 void
 230 mlx5_os_free_shared_dr(struct mlx5_priv *priv)
 231 {
 232         mlx5_free_table_hash_list(priv);
 233 }
 234
 235 /**
 236  * Set the completion channel file descriptor interrupt as non-blocking.
 237  * Currently it has no support under Windows.
 238  *
 239  * @param[in] rxq_obj
 240  *   Pointer to RQ channel object, which includes the channel fd
 241  *
 242  * @param[out] fd
 243  *   The file descriptor (representing the intetrrupt) used in this channel.
 244  *
 245  * @return
 246  *   0 on successfully setting the fd to non-blocking, non-zero otherwise.
 247  */
 248 int
 249 mlx5_os_set_nonblock_channel_fd(int fd)
 250 {
 251         (void)fd;
 252         DRV_LOG(WARNING, "%s: is not supported", __func__);
 253         return -ENOTSUP;
 254 }
 255
 256 /**
 257  * DV flow counter mode detect and config.
 258  *
 259  * @param dev
 260  *   Pointer to rte_eth_dev structure.
 261  *
 262  */
 263 static void
 264 mlx5_flow_counter_mode_config(struct rte_eth_dev *dev __rte_unused)
 265 {
 266 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
 267         struct mlx5_priv *priv = dev->data->dev_private;
 268         struct mlx5_dev_ctx_shared *sh = priv->sh;
 269         bool fallback;
 270
 271 #ifndef HAVE_IBV_DEVX_ASYNC
 272         fallback = true;
 273 #else
 274         fallback = false;
 275         if (!sh->devx || !priv->config.dv_flow_en ||
 276             !priv->config.hca_attr.flow_counters_dump ||
 277             !(priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4) ||
 278             (mlx5_flow_dv_discover_counter_offset_support(dev) == -ENOTSUP))
 279                 fallback = true;
 280 #endif
 281         if (fallback)
 282                 DRV_LOG(INFO, "Use fall-back DV counter management. Flow "
 283                         "counter dump:%d, bulk_alloc_bitmap:0x%hhx.",
 284                         priv->config.hca_attr.flow_counters_dump,
 285                         priv->config.hca_attr.flow_counter_bulk_alloc_bitmap);
 286         /* Initialize fallback mode only on the port initializes sh. */
 287         if (sh->refcnt == 1)
 288                 sh->cmng.counter_fallback = fallback;
 289         else if (fallback != sh->cmng.counter_fallback)
 290                 DRV_LOG(WARNING, "Port %d in sh has different fallback mode "
 291                         "with others:%d.", PORT_ID(priv), fallback);
 292 #endif
 293 }
 294
 295 /**
 296  * Spawn an Ethernet device from DevX information.
 297  *
 298  * @param dpdk_dev
 299  *   Backing DPDK device.
 300  * @param spawn
 301  *   Verbs device parameters (name, port, switch_info) to spawn.
 302  * @param config
 303  *   Device configuration parameters.
 304  *
 305  * @return
 306  *   A valid Ethernet device object on success, NULL otherwise and rte_errno
 307  *   is set. The following errors are defined:
 308  *
 309  *   EEXIST: device is already spawned
 310  */
 311 static struct rte_eth_dev *
 312 mlx5_dev_spawn(struct rte_device *dpdk_dev,
 313                struct mlx5_dev_spawn_data *spawn,
 314                struct mlx5_dev_config *config)
 315 {
 316         const struct mlx5_switch_info *switch_info = &spawn->info;
 317         struct mlx5_dev_ctx_shared *sh = NULL;
 318         struct mlx5_dev_attr device_attr;
 319         struct rte_eth_dev *eth_dev = NULL;
 320         struct mlx5_priv *priv = NULL;
 321         int err = 0;
 322         unsigned int cqe_comp;
 323         struct rte_ether_addr mac;
 324         char name[RTE_ETH_NAME_MAX_LEN];
 325         int own_domain_id = 0;
 326         uint16_t port_id;
 327         int i;
 328
 329         /* Build device name. */
 330         strlcpy(name, dpdk_dev->name, sizeof(name));
 331         /* check if the device is already spawned */
 332         if (rte_eth_dev_get_port_by_name(name, &port_id) == 0) {
 333                 rte_errno = EEXIST;
 334                 return NULL;
 335         }
 336         DRV_LOG(DEBUG, "naming Ethernet device \"%s\"", name);
 337         /*
 338          * Some parameters are needed in advance to create device context. We
 339          * process the devargs here to get ones, and later process devargs
 340          * again to override some hardware settings.
 341          */
 342         err = mlx5_args(config, dpdk_dev->devargs);
 343         if (err) {
 344                 err = rte_errno;
 345                 DRV_LOG(ERR, "failed to process device arguments: %s",
 346                         strerror(rte_errno));
 347                 goto error;
 348         }
 349         sh = mlx5_alloc_shared_dev_ctx(spawn, config);
 350         if (!sh)
 351                 return NULL;
 352         /* Initialize the shutdown event in mlx5_dev_spawn to
 353          * support mlx5_is_removed for Windows.
 354          */
 355         err = mlx5_glue->devx_init_showdown_event(sh->cdev->ctx);
 356         if (err) {
 357                 DRV_LOG(ERR, "failed to init showdown event: %s",
 358                         strerror(errno));
 359                 goto error;
 360         }
 361         DRV_LOG(DEBUG, "MPW isn't supported");
 362         mlx5_os_get_dev_attr(sh->cdev, &device_attr);
 363         config->swp = device_attr.sw_parsing_offloads &
 364                 (MLX5_SW_PARSING_CAP | MLX5_SW_PARSING_CSUM_CAP |
 365                  MLX5_SW_PARSING_TSO_CAP);
 366         config->ind_table_max_size =
 367                 sh->device_attr.max_rwq_indirection_table_size;
 368         cqe_comp = 0;
 369         config->cqe_comp = cqe_comp;
 370         config->tunnel_en = device_attr.tunnel_offloads_caps &
 371                 (MLX5_TUNNELED_OFFLOADS_VXLAN_CAP |
 372                  MLX5_TUNNELED_OFFLOADS_GRE_CAP |
 373                  MLX5_TUNNELED_OFFLOADS_GENEVE_CAP);
 374         if (config->tunnel_en) {
 375                 DRV_LOG(DEBUG, "tunnel offloading is supported for %s%s%s",
 376                 config->tunnel_en &
 377                 MLX5_TUNNELED_OFFLOADS_VXLAN_CAP ? "[VXLAN]" : "",
 378                 config->tunnel_en &
 379                 MLX5_TUNNELED_OFFLOADS_GRE_CAP ? "[GRE]" : "",
 380                 config->tunnel_en &
 381                 MLX5_TUNNELED_OFFLOADS_GENEVE_CAP ? "[GENEVE]" : ""
 382                 );
 383         } else {
 384                 DRV_LOG(DEBUG, "tunnel offloading is not supported");
 385         }
 386         DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is no supported");
 387         config->mpls_en = 0;
 388         /* Allocate private eth device data. */
 389         priv = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE,
 390                            sizeof(*priv),
 391                            RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 392         if (priv == NULL) {
 393                 DRV_LOG(ERR, "priv allocation failure");
 394                 err = ENOMEM;
 395                 goto error;
 396         }
 397         priv->sh = sh;
 398         priv->dev_port = spawn->phys_port;
 399         priv->pci_dev = spawn->pci_dev;
 400         priv->mtu = RTE_ETHER_MTU;
 401         priv->mp_id.port_id = port_id;
 402         strlcpy(priv->mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN);
 403         priv->representor = !!switch_info->representor;
 404         priv->master = !!switch_info->master;
 405         priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
 406         priv->vport_meta_tag = 0;
 407         priv->vport_meta_mask = 0;
 408         priv->pf_bond = spawn->pf_bond;
 409         priv->vport_id = -1;
 410         /* representor_id field keeps the unmodified VF index. */
 411         priv->representor_id = -1;
 412         /*
 413          * Look for sibling devices in order to reuse their switch domain
 414          * if any, otherwise allocate one.
 415          */
 416         MLX5_ETH_FOREACH_DEV(port_id, dpdk_dev) {
 417                 const struct mlx5_priv *opriv =
 418                         rte_eth_devices[port_id].data->dev_private;
 419
 420                 if (!opriv ||
 421                     opriv->sh != priv->sh ||
 422                         opriv->domain_id ==
 423                         RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID)
 424                         continue;
 425                 priv->domain_id = opriv->domain_id;
 426                 break;
 427         }
 428         if (priv->domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
 429                 err = rte_eth_switch_domain_alloc(&priv->domain_id);
 430                 if (err) {
 431                         err = rte_errno;
 432                         DRV_LOG(ERR, "unable to allocate switch domain: %s",
 433                                 strerror(rte_errno));
 434                         goto error;
 435                 }
 436                 own_domain_id = 1;
 437         }
 438         /* Override some values set by hardware configuration. */
 439         mlx5_args(config, dpdk_dev->devargs);
 440         err = mlx5_dev_check_sibling_config(priv, config, dpdk_dev);
 441         if (err)
 442                 goto error;
 443         DRV_LOG(DEBUG, "counters are not supported");
 444         config->ind_table_max_size =
 445                 sh->device_attr.max_rwq_indirection_table_size;
 446         /*
 447          * Remove this check once DPDK supports larger/variable
 448          * indirection tables.
 449          */
 450         if (config->ind_table_max_size > (unsigned int)ETH_RSS_RETA_SIZE_512)
 451                 config->ind_table_max_size = ETH_RSS_RETA_SIZE_512;
 452         DRV_LOG(DEBUG, "maximum Rx indirection table size is %u",
 453                 config->ind_table_max_size);
 454         if (config->hw_padding) {
 455                 DRV_LOG(DEBUG, "Rx end alignment padding isn't supported");
 456                 config->hw_padding = 0;
 457         }
 458         config->tso = (sh->device_attr.max_tso > 0);
 459         if (config->tso)
 460                 config->tso_max_payload_sz = sh->device_attr.max_tso;
 461         DRV_LOG(DEBUG, "%sMPS is %s.",
 462                 config->mps == MLX5_MPW_ENHANCED ? "enhanced " :
 463                 config->mps == MLX5_MPW ? "legacy " : "",
 464                 config->mps != MLX5_MPW_DISABLED ? "enabled" : "disabled");
 465         if (config->cqe_comp && !cqe_comp) {
 466                 DRV_LOG(WARNING, "Rx CQE compression isn't supported.");
 467                 config->cqe_comp = 0;
 468         }
 469         if (sh->devx) {
 470                 config->hca_attr = sh->cdev->config.hca_attr;
 471                 config->hw_csum = config->hca_attr.csum_cap;
 472                 DRV_LOG(DEBUG, "checksum offloading is %ssupported",
 473                     (config->hw_csum ? "" : "not "));
 474                 config->hw_vlan_strip = config->hca_attr.vlan_cap;
 475                 DRV_LOG(DEBUG, "VLAN stripping is %ssupported",
 476                         (config->hw_vlan_strip ? "" : "not "));
 477                 config->hw_fcs_strip = config->hca_attr.scatter_fcs;
 478         }
 479         if (sh->devx) {
 480                 uint32_t reg[MLX5_ST_SZ_DW(register_mtutc)];
 481
 482                 err = config->hca_attr.access_register_user ?
 483                         mlx5_devx_cmd_register_read
 484                                 (sh->cdev->ctx, MLX5_REGISTER_ID_MTUTC, 0,
 485                                 reg, MLX5_ST_SZ_DW(register_mtutc)) : ENOTSUP;
 486                 if (!err) {
 487                         uint32_t ts_mode;
 488
 489                         /* MTUTC register is read successfully. */
 490                         ts_mode = MLX5_GET(register_mtutc, reg,
 491                                            time_stamp_mode);
 492                         if (ts_mode == MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME)
 493                                 config->rt_timestamp = 1;
 494                 } else {
 495                         /* Kernel does not support register reading. */
 496                         if (config->hca_attr.dev_freq_khz ==
 497                                                  (NS_PER_S / MS_PER_S))
 498                                 config->rt_timestamp = 1;
 499                 }
 500         }
 501         if (config->mprq.enabled) {
 502                 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported");
 503                 config->mprq.enabled = 0;
 504         }
 505         if (config->max_dump_files_num == 0)
 506                 config->max_dump_files_num = 128;
 507         eth_dev = rte_eth_dev_allocate(name);
 508         if (eth_dev == NULL) {
 509                 DRV_LOG(ERR, "can not allocate rte ethdev");
 510                 err = ENOMEM;
 511                 goto error;
 512         }
 513         if (priv->representor) {
 514                 eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR;
 515                 eth_dev->data->representor_id = priv->representor_id;
 516                 MLX5_ETH_FOREACH_DEV(port_id, dpdk_dev) {
 517                         struct mlx5_priv *opriv =
 518                                 rte_eth_devices[port_id].data->dev_private;
 519                         if (opriv &&
 520                             opriv->master &&
 521                             opriv->domain_id == priv->domain_id &&
 522                             opriv->sh == priv->sh) {
 523                                 eth_dev->data->backer_port_id = port_id;
 524                                 break;
 525                         }
 526                 }
 527                 if (port_id >= RTE_MAX_ETHPORTS)
 528                         eth_dev->data->backer_port_id = eth_dev->data->port_id;
 529         }
 530         /*
 531          * Store associated network device interface index. This index
 532          * is permanent throughout the lifetime of device. So, we may store
 533          * the ifindex here and use the cached value further.
 534          */
 535         MLX5_ASSERT(spawn->ifindex);
 536         priv->if_index = spawn->ifindex;
 537         eth_dev->data->dev_private = priv;
 538         priv->dev_data = eth_dev->data;
 539         eth_dev->data->mac_addrs = priv->mac;
 540         eth_dev->device = dpdk_dev;
 541         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
 542         /* Configure the first MAC address by default. */
 543         if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) {
 544                 DRV_LOG(ERR,
 545                         "port %u cannot get MAC address, is mlx5_en"
 546                         " loaded? (errno: %s).",
 547                         eth_dev->data->port_id, strerror(rte_errno));
 548                 err = ENODEV;
 549                 goto error;
 550         }
 551         DRV_LOG(INFO,
 552                 "port %u MAC address is " RTE_ETHER_ADDR_PRT_FMT,
 553                 eth_dev->data->port_id, RTE_ETHER_ADDR_BYTES(&mac));
 554 #ifdef RTE_LIBRTE_MLX5_DEBUG
 555         {
 556                 char ifname[MLX5_NAMESIZE];
 557
 558                 if (mlx5_get_ifname(eth_dev, &ifname) == 0)
 559                         DRV_LOG(DEBUG, "port %u ifname is \"%s\"",
 560                                 eth_dev->data->port_id, ifname);
 561                 else
 562                         DRV_LOG(DEBUG, "port %u ifname is unknown.",
 563                                 eth_dev->data->port_id);
 564         }
 565 #endif
 566         /* Get actual MTU if possible. */
 567         err = mlx5_get_mtu(eth_dev, &priv->mtu);
 568         if (err) {
 569                 err = rte_errno;
 570                 goto error;
 571         }
 572         DRV_LOG(DEBUG, "port %u MTU is %u.", eth_dev->data->port_id,
 573                 priv->mtu);
 574         /* Initialize burst functions to prevent crashes before link-up. */
 575         eth_dev->rx_pkt_burst = removed_rx_burst;
 576         eth_dev->tx_pkt_burst = removed_tx_burst;
 577         eth_dev->dev_ops = &mlx5_dev_ops;
 578         eth_dev->rx_descriptor_status = mlx5_rx_descriptor_status;
 579         eth_dev->tx_descriptor_status = mlx5_tx_descriptor_status;
 580         eth_dev->rx_queue_count = mlx5_rx_queue_count;
 581         /* Register MAC address. */
 582         claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0));
 583         priv->ctrl_flows = 0;
 584         TAILQ_INIT(&priv->flow_meters);
 585         priv->mtr_profile_tbl = mlx5_l3t_create(MLX5_L3T_TYPE_PTR);
 586         if (!priv->mtr_profile_tbl)
 587                 goto error;
 588         /* Bring Ethernet device up. */
 589         DRV_LOG(DEBUG, "port %u forcing Ethernet interface up.",
 590                 eth_dev->data->port_id);
 591         /* nl calls are unsupported - set to -1 not to fail on release */
 592         priv->nl_socket_rdma = -1;
 593         priv->nl_socket_route = -1;
 594         mlx5_set_link_up(eth_dev);
 595         /*
 596          * Even though the interrupt handler is not installed yet,
 597          * interrupts will still trigger on the async_fd from
 598          * Verbs context returned by ibv_open_device().
 599          */
 600         mlx5_link_update(eth_dev, 0);
 601         config->dv_esw_en = 0;
 602         /* Detect minimal data bytes to inline. */
 603         mlx5_set_min_inline(spawn, config);
 604         /* Store device configuration on private structure. */
 605         priv->config = *config;
 606         for (i = 0; i < MLX5_FLOW_TYPE_MAXI; i++) {
 607                 icfg[i].release_mem_en = !!config->reclaim_mode;
 608                 if (config->reclaim_mode)
 609                         icfg[i].per_core_cache = 0;
 610                 priv->flows[i] = mlx5_ipool_create(&icfg[i]);
 611                 if (!priv->flows[i])
 612                         goto error;
 613         }
 614         /* Create context for virtual machine VLAN workaround. */
 615         priv->vmwa_context = NULL;
 616         if (config->dv_flow_en) {
 617                 err = mlx5_alloc_shared_dr(priv);
 618                 if (err)
 619                         goto error;
 620         }
 621         /* No supported flow priority number detection. */
 622         priv->config.flow_prio = -1;
 623         if (!priv->config.dv_esw_en &&
 624             priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
 625                 DRV_LOG(WARNING, "metadata mode %u is not supported "
 626                                  "(no E-Switch)", priv->config.dv_xmeta_en);
 627                 priv->config.dv_xmeta_en = MLX5_XMETA_MODE_LEGACY;
 628         }
 629         mlx5_set_metadata_mask(eth_dev);
 630         if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
 631             !priv->sh->dv_regc0_mask) {
 632                 DRV_LOG(ERR, "metadata mode %u is not supported "
 633                              "(no metadata reg_c[0] is available).",
 634                              priv->config.dv_xmeta_en);
 635                         err = ENOTSUP;
 636                         goto error;
 637         }
 638         priv->hrxqs = mlx5_list_create("hrxq", eth_dev, true,
 639                 mlx5_hrxq_create_cb, mlx5_hrxq_match_cb,
 640                 mlx5_hrxq_remove_cb, mlx5_hrxq_clone_cb,
 641                 mlx5_hrxq_clone_free_cb);
 642         /* Query availability of metadata reg_c's. */
 643         err = mlx5_flow_discover_mreg_c(eth_dev);
 644         if (err < 0) {
 645                 err = -err;
 646                 goto error;
 647         }
 648         if (!mlx5_flow_ext_mreg_supported(eth_dev)) {
 649                 DRV_LOG(DEBUG,
 650                         "port %u extensive metadata register is not supported.",
 651                         eth_dev->data->port_id);
 652                 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
 653                         DRV_LOG(ERR, "metadata mode %u is not supported "
 654                                      "(no metadata registers available).",
 655                                      priv->config.dv_xmeta_en);
 656                         err = ENOTSUP;
 657                         goto error;
 658                 }
 659         }
 660         if (sh->devx && config->dv_flow_en) {
 661                 priv->obj_ops = devx_obj_ops;
 662         } else {
 663                 DRV_LOG(ERR, "Flow mode %u is not supported "
 664                                 "(Windows flow must be DevX with DV flow enabled).",
 665                                 priv->config.dv_flow_en);
 666                 err = ENOTSUP;
 667                 goto error;
 668         }
 669         mlx5_flow_counter_mode_config(eth_dev);
 670         return eth_dev;
 671 error:
 672         if (priv) {
 673                 if (priv->mtr_profile_tbl)
 674                         mlx5_l3t_destroy(priv->mtr_profile_tbl);
 675                 if (own_domain_id)
 676                         claim_zero(rte_eth_switch_domain_free(priv->domain_id));
 677                 mlx5_free(priv);
 678                 if (eth_dev != NULL)
 679                         eth_dev->data->dev_private = NULL;
 680         }
 681         if (eth_dev != NULL) {
 682                 /* mac_addrs must not be freed alone because part of
 683                  * dev_private
 684                  **/
 685                 eth_dev->data->mac_addrs = NULL;
 686                 rte_eth_dev_release_port(eth_dev);
 687         }
 688         if (sh)
 689                 mlx5_free_shared_dev_ctx(sh);
 690         MLX5_ASSERT(err > 0);
 691         rte_errno = err;
 692         return NULL;
 693 }
 694
 695 /**
 696  * This function should share events between multiple ports of single IB
 697  * device.  Currently it has no support under Windows.
 698  *
 699  * @param sh
 700  *   Pointer to mlx5_dev_ctx_shared object.
 701  */
 702 void
 703 mlx5_os_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh)
 704 {
 705         (void)sh;
 706         DRV_LOG(WARNING, "%s: is not supported", __func__);
 707 }
 708
 709 /**
 710  * This function should share events between multiple ports of single IB
 711  * device.  Currently it has no support under Windows.
 712  *
 713  * @param dev
 714  *   Pointer to mlx5_dev_ctx_shared object.
 715  */
 716 void
 717 mlx5_os_dev_shared_handler_uninstall(struct mlx5_dev_ctx_shared *sh)
 718 {
 719         (void)sh;
 720         DRV_LOG(WARNING, "%s: is not supported", __func__);
 721 }
 722
 723 /**
 724  * Read statistics by a named counter.
 725  *
 726  * @param[in] priv
 727  *   Pointer to the private device data structure.
 728  * @param[in] ctr_name
 729  *   Pointer to the name of the statistic counter to read
 730  * @param[out] stat
 731  *   Pointer to read statistic value.
 732  * @return
 733  *   0 on success and stat is valud, 1 if failed to read the value
 734  *   rte_errno is set.
 735  *
 736  */
 737 int
 738 mlx5_os_read_dev_stat(struct mlx5_priv *priv, const char *ctr_name,
 739                       uint64_t *stat)
 740 {
 741         RTE_SET_USED(priv);
 742         RTE_SET_USED(ctr_name);
 743         RTE_SET_USED(stat);
 744         DRV_LOG(WARNING, "%s: is not supported", __func__);
 745         return -ENOTSUP;
 746 }
 747
 748 /**
 749  * Flush device MAC addresses
 750  * Currently it has no support under Windows.
 751  *
 752  * @param dev
 753  *   Pointer to Ethernet device structure.
 754  *
 755  */
 756 void
 757 mlx5_os_mac_addr_flush(struct rte_eth_dev *dev)
 758 {
 759         (void)dev;
 760         DRV_LOG(WARNING, "%s: is not supported", __func__);
 761 }
 762
 763 /**
 764  * Remove a MAC address from device
 765  * Currently it has no support under Windows.
 766  *
 767  * @param dev
 768  *   Pointer to Ethernet device structure.
 769  * @param index
 770  *   MAC address index.
 771  */
 772 void
 773 mlx5_os_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index)
 774 {
 775         (void)dev;
 776         (void)(index);
 777         DRV_LOG(WARNING, "%s: is not supported", __func__);
 778 }
 779
 780 /**
 781  * Adds a MAC address to the device
 782  * Currently it has no support under Windows.
 783  *
 784  * @param dev
 785  *   Pointer to Ethernet device structure.
 786  * @param mac_addr
 787  *   MAC address to register.
 788  * @param index
 789  *   MAC address index.
 790  *
 791  * @return
 792  *   0 on success, a negative errno value otherwise
 793  */
 794 int
 795 mlx5_os_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac,
 796                      uint32_t index)
 797 {
 798         (void)index;
 799         struct rte_ether_addr lmac;
 800
 801         if (mlx5_get_mac(dev, &lmac.addr_bytes)) {
 802                 DRV_LOG(ERR,
 803                         "port %u cannot get MAC address, is mlx5_en"
 804                         " loaded? (errno: %s)",
 805                         dev->data->port_id, strerror(rte_errno));
 806                 return rte_errno;
 807         }
 808         if (!rte_is_same_ether_addr(&lmac, mac)) {
 809                 DRV_LOG(ERR,
 810                         "adding new mac address to device is unsupported");
 811                 return -ENOTSUP;
 812         }
 813         return 0;
 814 }
 815
 816 /**
 817  * Modify a VF MAC address
 818  * Currently it has no support under Windows.
 819  *
 820  * @param priv
 821  *   Pointer to device private data.
 822  * @param mac_addr
 823  *   MAC address to modify into.
 824  * @param iface_idx
 825  *   Net device interface index
 826  * @param vf_index
 827  *   VF index
 828  *
 829  * @return
 830  *   0 on success, a negative errno value otherwise
 831  */
 832 int
 833 mlx5_os_vf_mac_addr_modify(struct mlx5_priv *priv,
 834                            unsigned int iface_idx,
 835                            struct rte_ether_addr *mac_addr,
 836                            int vf_index)
 837 {
 838         (void)priv;
 839         (void)iface_idx;
 840         (void)mac_addr;
 841         (void)vf_index;
 842         DRV_LOG(WARNING, "%s: is not supported", __func__);
 843         return -ENOTSUP;
 844 }
 845
 846 /**
 847  * Set device promiscuous mode
 848  * Currently it has no support under Windows.
 849  *
 850  * @param dev
 851  *   Pointer to Ethernet device structure.
 852  * @param enable
 853  *   0 - promiscuous is disabled, otherwise - enabled
 854  *
 855  * @return
 856  *   0 on success, a negative error value otherwise
 857  */
 858 int
 859 mlx5_os_set_promisc(struct rte_eth_dev *dev, int enable)
 860 {
 861         (void)dev;
 862         (void)enable;
 863         DRV_LOG(WARNING, "%s: is not supported", __func__);
 864         return -ENOTSUP;
 865 }
 866
 867 /**
 868  * Set device allmulti mode
 869  *
 870  * @param dev
 871  *   Pointer to Ethernet device structure.
 872  * @param enable
 873  *   0 - all multicase is disabled, otherwise - enabled
 874  *
 875  * @return
 876  *   0 on success, a negative error value otherwise
 877  */
 878 int
 879 mlx5_os_set_allmulti(struct rte_eth_dev *dev, int enable)
 880 {
 881         (void)dev;
 882         (void)enable;
 883         DRV_LOG(WARNING, "%s: is not supported", __func__);
 884         return -ENOTSUP;
 885 }
 886
 887 /**
 888  * DPDK callback to register a PCI device.
 889  *
 890  * This function spawns Ethernet devices out of a given device.
 891  *
 892  * @param[in] dev
 893  *   Pointer to the common device.
 894  *
 895  * @return
 896  *   0 on success, a negative errno value otherwise and rte_errno is set.
 897  */
 898 int
 899 mlx5_os_net_probe(struct mlx5_common_device *cdev)
 900 {
 901         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(cdev->dev);
 902         struct mlx5_dev_spawn_data spawn = {
 903                 .pf_bond = -1,
 904                 .max_port = 1,
 905                 .phys_port = 1,
 906                 .phys_dev_name = mlx5_os_get_ctx_device_name(cdev->ctx),
 907                 .pci_dev = pci_dev,
 908                 .cdev = cdev,
 909                 .ifindex = -1, /* Spawn will assign */
 910                 .info = (struct mlx5_switch_info){
 911                         .name_type = MLX5_PHYS_PORT_NAME_TYPE_UPLINK,
 912                 },
 913         };
 914         struct mlx5_dev_config dev_config = {
 915                 .rx_vec_en = 1,
 916                 .txq_inline_max = MLX5_ARG_UNSET,
 917                 .txq_inline_min = MLX5_ARG_UNSET,
 918                 .txq_inline_mpw = MLX5_ARG_UNSET,
 919                 .txqs_inline = MLX5_ARG_UNSET,
 920                 .mprq = {
 921                         .max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN,
 922                         .min_rxqs_num = MLX5_MPRQ_MIN_RXQS,
 923                 },
 924                 .dv_flow_en = 1,
 925                 .log_hp_size = MLX5_ARG_UNSET,
 926         };
 927         int ret;
 928         uint32_t restore;
 929
 930         if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
 931                 DRV_LOG(ERR, "Secondary process is not supported on Windows.");
 932                 return -ENOTSUP;
 933         }
 934         ret = mlx5_init_once();
 935         if (ret) {
 936                 DRV_LOG(ERR, "unable to init PMD global data: %s",
 937                         strerror(rte_errno));
 938                 return -rte_errno;
 939         }
 940         /* Device specific configuration. */
 941         switch (pci_dev->id.device_id) {
 942         case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
 943         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
 944         case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
 945         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
 946         case PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF:
 947         case PCI_DEVICE_ID_MELLANOX_CONNECTX6VF:
 948         case PCI_DEVICE_ID_MELLANOX_CONNECTXVF:
 949                 dev_config.vf = 1;
 950                 break;
 951         default:
 952                 dev_config.vf = 0;
 953                 break;
 954         }
 955         spawn.eth_dev = mlx5_dev_spawn(cdev->dev, &spawn, &dev_config);
 956         if (!spawn.eth_dev)
 957                 return -rte_errno;
 958         restore = spawn.eth_dev->data->dev_flags;
 959         rte_eth_copy_pci_info(spawn.eth_dev, pci_dev);
 960         /* Restore non-PCI flags cleared by the above call. */
 961         spawn.eth_dev->data->dev_flags |= restore;
 962         rte_eth_dev_probing_finish(spawn.eth_dev);
 963         return 0;
 964 }
 965
 966 const struct mlx5_flow_driver_ops mlx5_flow_verbs_drv_ops = {0};