1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2020 Mellanox Technologies, Ltd
11 #include <rte_windows.h>
12 #include <ethdev_pci.h>
14 #include <mlx5_glue.h>
15 #include <mlx5_devx_cmds.h>
16 #include <mlx5_common.h>
17 #include <mlx5_common_mp.h>
18 #include <mlx5_common_mr.h>
19 #include <mlx5_malloc.h>
21 #include "mlx5_defs.h"
23 #include "mlx5_common_os.h"
24 #include "mlx5_utils.h"
25 #include "mlx5_rxtx.h"
28 #include "mlx5_autoconf.h"
30 #include "mlx5_flow.h"
31 #include "mlx5_devx.h"
33 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data";
35 /* Spinlock for mlx5_shared_data allocation. */
36 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER;
38 /* rte flow indexed pool configuration. */
39 static struct mlx5_indexed_pool_config icfg[] = {
41 .size = sizeof(struct rte_flow),
45 .malloc = mlx5_malloc,
48 .type = "ctl_flow_ipool",
51 .size = sizeof(struct rte_flow),
57 .malloc = mlx5_malloc,
59 .per_core_cache = 1 << 14,
60 .type = "rte_flow_ipool",
63 .size = sizeof(struct rte_flow),
69 .malloc = mlx5_malloc,
72 .type = "mcp_flow_ipool",
77 * Initialize shared data between primary and secondary process.
79 * A memzone is reserved by primary process and secondary processes attach to
83 * 0 on success, a negative errno value otherwise and rte_errno is set.
86 mlx5_init_shared_data(void)
88 const struct rte_memzone *mz;
91 rte_spinlock_lock(&mlx5_shared_data_lock);
92 if (mlx5_shared_data == NULL) {
93 /* Allocate shared memory. */
94 mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA,
95 sizeof(*mlx5_shared_data),
99 "Cannot allocate mlx5 shared data");
103 mlx5_shared_data = mz->addr;
104 memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data));
105 rte_spinlock_init(&mlx5_shared_data->lock);
108 rte_spinlock_unlock(&mlx5_shared_data_lock);
113 * PMD global initialization.
115 * Independent from individual device, this function initializes global
116 * per-PMD data structures distinguishing primary and secondary processes.
117 * Hence, each initialization is called once per a process.
120 * 0 on success, a negative errno value otherwise and rte_errno is set.
125 if (mlx5_init_shared_data())
131 * Get mlx5 device attributes.
134 * Pointer to device context.
137 * Pointer to mlx5 device attributes.
140 * 0 on success, non zero error number otherwise
143 mlx5_os_get_dev_attr(void *ctx, struct mlx5_dev_attr *device_attr)
145 struct mlx5_context *mlx5_ctx;
146 struct mlx5_hca_attr hca_attr;
147 void *pv_iseg = NULL;
153 mlx5_ctx = (struct mlx5_context *)ctx;
154 memset(device_attr, 0, sizeof(*device_attr));
155 err = mlx5_devx_cmd_query_hca_attr(mlx5_ctx, &hca_attr);
157 DRV_LOG(ERR, "Failed to get device hca_cap");
160 device_attr->max_cq = 1 << hca_attr.log_max_cq;
161 device_attr->max_qp = 1 << hca_attr.log_max_qp;
162 device_attr->max_qp_wr = 1 << hca_attr.log_max_qp_sz;
163 device_attr->max_cqe = 1 << hca_attr.log_max_cq_sz;
164 device_attr->max_mr = 1 << hca_attr.log_max_mrw_sz;
165 device_attr->max_pd = 1 << hca_attr.log_max_pd;
166 device_attr->max_srq = 1 << hca_attr.log_max_srq;
167 device_attr->max_srq_wr = 1 << hca_attr.log_max_srq_sz;
168 device_attr->max_tso = 1 << hca_attr.max_lso_cap;
169 if (hca_attr.rss_ind_tbl_cap) {
170 device_attr->max_rwq_indirection_table_size =
171 1 << hca_attr.rss_ind_tbl_cap;
173 device_attr->sw_parsing_offloads =
174 mlx5_get_supported_sw_parsing_offloads(&hca_attr);
175 device_attr->tunnel_offloads_caps =
176 mlx5_get_supported_tunneling_offloads(&hca_attr);
177 pv_iseg = mlx5_glue->query_hca_iseg(mlx5_ctx, &cb_iseg);
178 if (pv_iseg == NULL) {
179 DRV_LOG(ERR, "Failed to get device hca_iseg");
183 snprintf(device_attr->fw_ver, 64, "%x.%x.%04x",
184 MLX5_GET(initial_seg, pv_iseg, fw_rev_major),
185 MLX5_GET(initial_seg, pv_iseg, fw_rev_minor),
186 MLX5_GET(initial_seg, pv_iseg, fw_rev_subminor));
192 * Initialize DR related data within private structure.
193 * Routine checks the reference counter and does actual
194 * resources creation/initialization only if counter is zero.
197 * Pointer to the private device data structure.
200 * Zero on success, positive error code otherwise.
203 mlx5_alloc_shared_dr(struct mlx5_priv *priv)
205 struct mlx5_dev_ctx_shared *sh = priv->sh;
209 err = mlx5_alloc_table_hash_list(priv);
211 DRV_LOG(DEBUG, "sh->flow_tbls[%p] already created, reuse",
212 (void *)sh->flow_tbls);
216 * Destroy DR related data within private structure.
219 * Pointer to the private device data structure.
222 mlx5_os_free_shared_dr(struct mlx5_priv *priv)
224 mlx5_free_table_hash_list(priv);
228 * Set the completion channel file descriptor interrupt as non-blocking.
229 * Currently it has no support under Windows.
232 * Pointer to RQ channel object, which includes the channel fd
235 * The file descriptor (representing the intetrrupt) used in this channel.
238 * 0 on successfully setting the fd to non-blocking, non-zero otherwise.
241 mlx5_os_set_nonblock_channel_fd(int fd)
244 DRV_LOG(WARNING, "%s: is not supported", __func__);
249 * Function API open device under Windows
251 * This function calls the Windows glue APIs to open a device.
254 * Pointer to the device attributes (name, port, etc).
256 * Pointer to device configuration structure.
258 * Pointer to shared context structure.
261 * 0 on success, a positive error value otherwise.
264 mlx5_os_open_device(const struct mlx5_dev_spawn_data *spawn,
265 const struct mlx5_dev_config *config,
266 struct mlx5_dev_ctx_shared *sh)
268 RTE_SET_USED(config);
270 struct mlx5_context *mlx5_ctx;
272 pthread_mutex_init(&sh->txpp.mutex, NULL);
273 /* Set numa node from pci probe */
274 sh->numa_node = spawn->pci_dev->device.numa_node;
276 /* Try to open device with DevX */
278 sh->ctx = mlx5_glue->open_device(spawn->phys_dev);
280 DRV_LOG(ERR, "open_device failed");
285 mlx5_ctx = (struct mlx5_context *)sh->ctx;
286 err = mlx5_glue->query_device(spawn->phys_dev, &mlx5_ctx->mlx5_dev);
288 DRV_LOG(ERR, "Failed to query device context fields.");
293 * DV flow counter mode detect and config.
296 * Pointer to rte_eth_dev structure.
300 mlx5_flow_counter_mode_config(struct rte_eth_dev *dev __rte_unused)
302 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
303 struct mlx5_priv *priv = dev->data->dev_private;
304 struct mlx5_dev_ctx_shared *sh = priv->sh;
307 #ifndef HAVE_IBV_DEVX_ASYNC
311 if (!priv->config.devx || !priv->config.dv_flow_en ||
312 !priv->config.hca_attr.flow_counters_dump ||
313 !(priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4) ||
314 (mlx5_flow_dv_discover_counter_offset_support(dev) == -ENOTSUP))
318 DRV_LOG(INFO, "Use fall-back DV counter management. Flow "
319 "counter dump:%d, bulk_alloc_bitmap:0x%hhx.",
320 priv->config.hca_attr.flow_counters_dump,
321 priv->config.hca_attr.flow_counter_bulk_alloc_bitmap);
322 /* Initialize fallback mode only on the port initializes sh. */
324 sh->cmng.counter_fallback = fallback;
325 else if (fallback != sh->cmng.counter_fallback)
326 DRV_LOG(WARNING, "Port %d in sh has different fallback mode "
327 "with others:%d.", PORT_ID(priv), fallback);
332 * Spawn an Ethernet device from Verbs information.
335 * Backing DPDK device.
337 * Verbs device parameters (name, port, switch_info) to spawn.
339 * Device configuration parameters.
342 * A valid Ethernet device object on success, NULL otherwise and rte_errno
343 * is set. The following errors are defined:
345 * EEXIST: device is already spawned
347 static struct rte_eth_dev *
348 mlx5_dev_spawn(struct rte_device *dpdk_dev,
349 struct mlx5_dev_spawn_data *spawn,
350 struct mlx5_dev_config *config)
352 const struct mlx5_switch_info *switch_info = &spawn->info;
353 struct mlx5_dev_ctx_shared *sh = NULL;
354 struct mlx5_dev_attr device_attr;
355 struct rte_eth_dev *eth_dev = NULL;
356 struct mlx5_priv *priv = NULL;
358 unsigned int cqe_comp;
359 struct rte_ether_addr mac;
360 char name[RTE_ETH_NAME_MAX_LEN];
361 int own_domain_id = 0;
365 /* Build device name. */
366 strlcpy(name, dpdk_dev->name, sizeof(name));
367 /* check if the device is already spawned */
368 if (rte_eth_dev_get_port_by_name(name, &port_id) == 0) {
372 DRV_LOG(DEBUG, "naming Ethernet device \"%s\"", name);
374 * Some parameters are needed in advance to create device context. We
375 * process the devargs here to get ones, and later process devargs
376 * again to override some hardware settings.
378 err = mlx5_args(config, dpdk_dev->devargs);
381 DRV_LOG(ERR, "failed to process device arguments: %s",
382 strerror(rte_errno));
385 mlx5_malloc_mem_select(config->sys_mem_en);
386 sh = mlx5_alloc_shared_dev_ctx(spawn, config);
389 config->devx = sh->devx;
390 /* Initialize the shutdown event in mlx5_dev_spawn to
391 * support mlx5_is_removed for Windows.
393 err = mlx5_glue->devx_init_showdown_event(sh->ctx);
395 DRV_LOG(ERR, "failed to init showdown event: %s",
399 DRV_LOG(DEBUG, "MPW isn't supported");
400 mlx5_os_get_dev_attr(sh->ctx, &device_attr);
401 config->swp = device_attr.sw_parsing_offloads &
402 (MLX5_SW_PARSING_CAP | MLX5_SW_PARSING_CSUM_CAP |
403 MLX5_SW_PARSING_TSO_CAP);
404 config->ind_table_max_size =
405 sh->device_attr.max_rwq_indirection_table_size;
407 config->cqe_comp = cqe_comp;
408 config->tunnel_en = device_attr.tunnel_offloads_caps &
409 (MLX5_TUNNELED_OFFLOADS_VXLAN_CAP |
410 MLX5_TUNNELED_OFFLOADS_GRE_CAP |
411 MLX5_TUNNELED_OFFLOADS_GENEVE_CAP);
412 if (config->tunnel_en) {
413 DRV_LOG(DEBUG, "tunnel offloading is supported for %s%s%s",
415 MLX5_TUNNELED_OFFLOADS_VXLAN_CAP ? "[VXLAN]" : "",
417 MLX5_TUNNELED_OFFLOADS_GRE_CAP ? "[GRE]" : "",
419 MLX5_TUNNELED_OFFLOADS_GENEVE_CAP ? "[GENEVE]" : ""
422 DRV_LOG(DEBUG, "tunnel offloading is not supported");
424 DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is no supported");
426 /* Allocate private eth device data. */
427 priv = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE,
429 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
431 DRV_LOG(ERR, "priv allocation failure");
436 priv->dev_port = spawn->phys_port;
437 priv->pci_dev = spawn->pci_dev;
438 priv->mtu = RTE_ETHER_MTU;
439 priv->mp_id.port_id = port_id;
440 strlcpy(priv->mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN);
441 priv->representor = !!switch_info->representor;
442 priv->master = !!switch_info->master;
443 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
444 priv->vport_meta_tag = 0;
445 priv->vport_meta_mask = 0;
446 priv->pf_bond = spawn->pf_bond;
448 /* representor_id field keeps the unmodified VF index. */
449 priv->representor_id = -1;
451 * Look for sibling devices in order to reuse their switch domain
452 * if any, otherwise allocate one.
454 MLX5_ETH_FOREACH_DEV(port_id, dpdk_dev) {
455 const struct mlx5_priv *opriv =
456 rte_eth_devices[port_id].data->dev_private;
459 opriv->sh != priv->sh ||
461 RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID)
463 priv->domain_id = opriv->domain_id;
466 if (priv->domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
467 err = rte_eth_switch_domain_alloc(&priv->domain_id);
470 DRV_LOG(ERR, "unable to allocate switch domain: %s",
471 strerror(rte_errno));
476 /* Override some values set by hardware configuration. */
477 mlx5_args(config, dpdk_dev->devargs);
478 err = mlx5_dev_check_sibling_config(priv, config, dpdk_dev);
481 DRV_LOG(DEBUG, "counters are not supported");
482 config->ind_table_max_size =
483 sh->device_attr.max_rwq_indirection_table_size;
485 * Remove this check once DPDK supports larger/variable
486 * indirection tables.
488 if (config->ind_table_max_size > (unsigned int)ETH_RSS_RETA_SIZE_512)
489 config->ind_table_max_size = ETH_RSS_RETA_SIZE_512;
490 DRV_LOG(DEBUG, "maximum Rx indirection table size is %u",
491 config->ind_table_max_size);
492 DRV_LOG(DEBUG, "VLAN stripping is %ssupported",
493 (config->hw_vlan_strip ? "" : "not "));
494 if (config->hw_padding) {
495 DRV_LOG(DEBUG, "Rx end alignment padding isn't supported");
496 config->hw_padding = 0;
498 config->tso = (sh->device_attr.max_tso > 0);
500 config->tso_max_payload_sz = sh->device_attr.max_tso;
501 DRV_LOG(DEBUG, "%sMPS is %s.",
502 config->mps == MLX5_MPW_ENHANCED ? "enhanced " :
503 config->mps == MLX5_MPW ? "legacy " : "",
504 config->mps != MLX5_MPW_DISABLED ? "enabled" : "disabled");
505 if (config->cqe_comp && !cqe_comp) {
506 DRV_LOG(WARNING, "Rx CQE compression isn't supported.");
507 config->cqe_comp = 0;
510 err = mlx5_devx_cmd_query_hca_attr(sh->ctx, &config->hca_attr);
515 /* Check relax ordering support. */
516 sh->cmng.relaxed_ordering_read = 0;
517 sh->cmng.relaxed_ordering_write = 0;
518 if (!haswell_broadwell_cpu) {
519 sh->cmng.relaxed_ordering_write =
520 config->hca_attr.relaxed_ordering_write;
521 sh->cmng.relaxed_ordering_read =
522 config->hca_attr.relaxed_ordering_read;
524 config->hw_csum = config->hca_attr.csum_cap;
525 DRV_LOG(DEBUG, "checksum offloading is %ssupported",
526 (config->hw_csum ? "" : "not "));
529 uint32_t reg[MLX5_ST_SZ_DW(register_mtutc)];
531 err = config->hca_attr.access_register_user ?
532 mlx5_devx_cmd_register_read
533 (sh->ctx, MLX5_REGISTER_ID_MTUTC, 0,
534 reg, MLX5_ST_SZ_DW(register_mtutc)) : ENOTSUP;
538 /* MTUTC register is read successfully. */
539 ts_mode = MLX5_GET(register_mtutc, reg,
541 if (ts_mode == MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME)
542 config->rt_timestamp = 1;
544 /* Kernel does not support register reading. */
545 if (config->hca_attr.dev_freq_khz ==
546 (NS_PER_S / MS_PER_S))
547 config->rt_timestamp = 1;
549 sh->rq_ts_format = config->hca_attr.rq_ts_format;
550 sh->sq_ts_format = config->hca_attr.sq_ts_format;
551 sh->qp_ts_format = config->hca_attr.qp_ts_format;
553 if (config->mprq.enabled) {
554 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported");
555 config->mprq.enabled = 0;
557 if (config->max_dump_files_num == 0)
558 config->max_dump_files_num = 128;
559 eth_dev = rte_eth_dev_allocate(name);
560 if (eth_dev == NULL) {
561 DRV_LOG(ERR, "can not allocate rte ethdev");
565 if (priv->representor) {
566 eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR;
567 eth_dev->data->representor_id = priv->representor_id;
568 MLX5_ETH_FOREACH_DEV(port_id, dpdk_dev) {
569 struct mlx5_priv *opriv =
570 rte_eth_devices[port_id].data->dev_private;
573 opriv->domain_id == priv->domain_id &&
574 opriv->sh == priv->sh) {
575 eth_dev->data->backer_port_id = port_id;
579 if (port_id >= RTE_MAX_ETHPORTS)
580 eth_dev->data->backer_port_id = eth_dev->data->port_id;
583 * Store associated network device interface index. This index
584 * is permanent throughout the lifetime of device. So, we may store
585 * the ifindex here and use the cached value further.
587 MLX5_ASSERT(spawn->ifindex);
588 priv->if_index = spawn->ifindex;
589 eth_dev->data->dev_private = priv;
590 priv->dev_data = eth_dev->data;
591 eth_dev->data->mac_addrs = priv->mac;
592 eth_dev->device = dpdk_dev;
593 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
594 /* Configure the first MAC address by default. */
595 if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) {
597 "port %u cannot get MAC address, is mlx5_en"
598 " loaded? (errno: %s).",
599 eth_dev->data->port_id, strerror(rte_errno));
604 "port %u MAC address is " RTE_ETHER_ADDR_PRT_FMT,
605 eth_dev->data->port_id, RTE_ETHER_ADDR_BYTES(&mac));
606 #ifdef RTE_LIBRTE_MLX5_DEBUG
608 char ifname[MLX5_NAMESIZE];
610 if (mlx5_get_ifname(eth_dev, &ifname) == 0)
611 DRV_LOG(DEBUG, "port %u ifname is \"%s\"",
612 eth_dev->data->port_id, ifname);
614 DRV_LOG(DEBUG, "port %u ifname is unknown.",
615 eth_dev->data->port_id);
618 /* Get actual MTU if possible. */
619 err = mlx5_get_mtu(eth_dev, &priv->mtu);
624 DRV_LOG(DEBUG, "port %u MTU is %u.", eth_dev->data->port_id,
626 /* Initialize burst functions to prevent crashes before link-up. */
627 eth_dev->rx_pkt_burst = removed_rx_burst;
628 eth_dev->tx_pkt_burst = removed_tx_burst;
629 eth_dev->dev_ops = &mlx5_dev_ops;
630 eth_dev->rx_descriptor_status = mlx5_rx_descriptor_status;
631 eth_dev->tx_descriptor_status = mlx5_tx_descriptor_status;
632 eth_dev->rx_queue_count = mlx5_rx_queue_count;
633 /* Register MAC address. */
634 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0));
635 priv->ctrl_flows = 0;
636 TAILQ_INIT(&priv->flow_meters);
637 priv->mtr_profile_tbl = mlx5_l3t_create(MLX5_L3T_TYPE_PTR);
638 if (!priv->mtr_profile_tbl)
640 /* Bring Ethernet device up. */
641 DRV_LOG(DEBUG, "port %u forcing Ethernet interface up.",
642 eth_dev->data->port_id);
643 /* nl calls are unsupported - set to -1 not to fail on release */
644 priv->nl_socket_rdma = -1;
645 priv->nl_socket_route = -1;
646 mlx5_set_link_up(eth_dev);
648 * Even though the interrupt handler is not installed yet,
649 * interrupts will still trigger on the async_fd from
650 * Verbs context returned by ibv_open_device().
652 mlx5_link_update(eth_dev, 0);
653 config->dv_esw_en = 0;
654 /* Detect minimal data bytes to inline. */
655 mlx5_set_min_inline(spawn, config);
656 /* Store device configuration on private structure. */
657 priv->config = *config;
658 for (i = 0; i < MLX5_FLOW_TYPE_MAXI; i++) {
659 icfg[i].release_mem_en = !!config->reclaim_mode;
660 if (config->reclaim_mode)
661 icfg[i].per_core_cache = 0;
662 priv->flows[i] = mlx5_ipool_create(&icfg[i]);
666 /* Create context for virtual machine VLAN workaround. */
667 priv->vmwa_context = NULL;
668 if (config->dv_flow_en) {
669 err = mlx5_alloc_shared_dr(priv);
673 /* No supported flow priority number detection. */
674 priv->config.flow_prio = -1;
675 if (!priv->config.dv_esw_en &&
676 priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
677 DRV_LOG(WARNING, "metadata mode %u is not supported "
678 "(no E-Switch)", priv->config.dv_xmeta_en);
679 priv->config.dv_xmeta_en = MLX5_XMETA_MODE_LEGACY;
681 mlx5_set_metadata_mask(eth_dev);
682 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
683 !priv->sh->dv_regc0_mask) {
684 DRV_LOG(ERR, "metadata mode %u is not supported "
685 "(no metadata reg_c[0] is available).",
686 priv->config.dv_xmeta_en);
690 priv->hrxqs = mlx5_list_create("hrxq", eth_dev, true,
691 mlx5_hrxq_create_cb, mlx5_hrxq_match_cb,
692 mlx5_hrxq_remove_cb, mlx5_hrxq_clone_cb,
693 mlx5_hrxq_clone_free_cb);
694 /* Query availability of metadata reg_c's. */
695 err = mlx5_flow_discover_mreg_c(eth_dev);
700 if (!mlx5_flow_ext_mreg_supported(eth_dev)) {
702 "port %u extensive metadata register is not supported.",
703 eth_dev->data->port_id);
704 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
705 DRV_LOG(ERR, "metadata mode %u is not supported "
706 "(no metadata registers available).",
707 priv->config.dv_xmeta_en);
712 if (config->devx && config->dv_flow_en) {
713 priv->obj_ops = devx_obj_ops;
715 DRV_LOG(ERR, "Flow mode %u is not supported "
716 "(Windows flow must be DevX with DV flow enabled).",
717 priv->config.dv_flow_en);
721 mlx5_flow_counter_mode_config(eth_dev);
725 if (priv->mtr_profile_tbl)
726 mlx5_l3t_destroy(priv->mtr_profile_tbl);
728 claim_zero(rte_eth_switch_domain_free(priv->domain_id));
731 eth_dev->data->dev_private = NULL;
733 if (eth_dev != NULL) {
734 /* mac_addrs must not be freed alone because part of
737 eth_dev->data->mac_addrs = NULL;
738 rte_eth_dev_release_port(eth_dev);
741 mlx5_free_shared_dev_ctx(sh);
742 MLX5_ASSERT(err > 0);
748 * This function should share events between multiple ports of single IB
749 * device. Currently it has no support under Windows.
752 * Pointer to mlx5_dev_ctx_shared object.
755 mlx5_os_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh)
758 DRV_LOG(WARNING, "%s: is not supported", __func__);
762 * This function should share events between multiple ports of single IB
763 * device. Currently it has no support under Windows.
766 * Pointer to mlx5_dev_ctx_shared object.
769 mlx5_os_dev_shared_handler_uninstall(struct mlx5_dev_ctx_shared *sh)
772 DRV_LOG(WARNING, "%s: is not supported", __func__);
776 * Read statistics by a named counter.
779 * Pointer to the private device data structure.
780 * @param[in] ctr_name
781 * Pointer to the name of the statistic counter to read
783 * Pointer to read statistic value.
785 * 0 on success and stat is valud, 1 if failed to read the value
790 mlx5_os_read_dev_stat(struct mlx5_priv *priv, const char *ctr_name,
794 RTE_SET_USED(ctr_name);
796 DRV_LOG(WARNING, "%s: is not supported", __func__);
801 * Flush device MAC addresses
802 * Currently it has no support under Windows.
805 * Pointer to Ethernet device structure.
809 mlx5_os_mac_addr_flush(struct rte_eth_dev *dev)
812 DRV_LOG(WARNING, "%s: is not supported", __func__);
816 * Remove a MAC address from device
817 * Currently it has no support under Windows.
820 * Pointer to Ethernet device structure.
825 mlx5_os_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index)
829 DRV_LOG(WARNING, "%s: is not supported", __func__);
833 * Adds a MAC address to the device
834 * Currently it has no support under Windows.
837 * Pointer to Ethernet device structure.
839 * MAC address to register.
844 * 0 on success, a negative errno value otherwise
847 mlx5_os_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac,
851 struct rte_ether_addr lmac;
853 if (mlx5_get_mac(dev, &lmac.addr_bytes)) {
855 "port %u cannot get MAC address, is mlx5_en"
856 " loaded? (errno: %s)",
857 dev->data->port_id, strerror(rte_errno));
860 if (!rte_is_same_ether_addr(&lmac, mac)) {
862 "adding new mac address to device is unsupported");
869 * Modify a VF MAC address
870 * Currently it has no support under Windows.
873 * Pointer to device private data.
875 * MAC address to modify into.
877 * Net device interface index
882 * 0 on success, a negative errno value otherwise
885 mlx5_os_vf_mac_addr_modify(struct mlx5_priv *priv,
886 unsigned int iface_idx,
887 struct rte_ether_addr *mac_addr,
894 DRV_LOG(WARNING, "%s: is not supported", __func__);
899 * Set device promiscuous mode
900 * Currently it has no support under Windows.
903 * Pointer to Ethernet device structure.
905 * 0 - promiscuous is disabled, otherwise - enabled
908 * 0 on success, a negative error value otherwise
911 mlx5_os_set_promisc(struct rte_eth_dev *dev, int enable)
915 DRV_LOG(WARNING, "%s: is not supported", __func__);
920 * Set device allmulti mode
923 * Pointer to Ethernet device structure.
925 * 0 - all multicase is disabled, otherwise - enabled
928 * 0 on success, a negative error value otherwise
931 mlx5_os_set_allmulti(struct rte_eth_dev *dev, int enable)
935 DRV_LOG(WARNING, "%s: is not supported", __func__);
940 * Detect if a devx_device_bdf object has identical DBDF values to the
941 * rte_pci_addr found in bus/pci probing
943 * @param[in] devx_bdf
944 * Pointer to the devx_device_bdf structure.
946 * Pointer to the rte_pci_addr structure.
949 * 1 on Device match, 0 on mismatch.
952 mlx5_match_devx_bdf_to_addr(struct devx_device_bdf *devx_bdf,
953 struct rte_pci_addr *addr)
955 if (addr->domain != (devx_bdf->bus_id >> 8) ||
956 addr->bus != (devx_bdf->bus_id & 0xff) ||
957 addr->devid != devx_bdf->dev_id ||
958 addr->function != devx_bdf->fnc_id) {
965 * Detect if a devx_device_bdf object matches the rte_pci_addr
966 * found in bus/pci probing
967 * Compare both the Native/PF BDF and the raw_bdf representing a VF BDF.
969 * @param[in] devx_bdf
970 * Pointer to the devx_device_bdf structure.
972 * Pointer to the rte_pci_addr structure.
975 * 1 on Device match, 0 on mismatch, rte_errno code on failure.
978 mlx5_match_devx_devices_to_addr(struct devx_device_bdf *devx_bdf,
979 struct rte_pci_addr *addr)
982 struct devx_device mlx5_dev;
984 if (mlx5_match_devx_bdf_to_addr(devx_bdf, addr))
987 * Didn't match on Native/PF BDF, could still
988 * Match a VF BDF, check it next
990 err = mlx5_glue->query_device(devx_bdf, &mlx5_dev);
992 DRV_LOG(ERR, "query_device failed");
996 if (mlx5_match_devx_bdf_to_addr(&mlx5_dev.raw_bdf, addr))
1002 * DPDK callback to register a PCI device.
1004 * This function spawns Ethernet devices out of a given device.
1007 * Pointer to the generic device.
1010 * 0 on success, a negative errno value otherwise and rte_errno is set.
1013 mlx5_os_net_probe(struct rte_device *dev)
1015 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
1016 struct devx_device_bdf *devx_bdf_devs, *orig_devx_bdf_devs;
1018 * Number of found IB Devices matching with requested PCI BDF.
1019 * nd != 1 means there are multiple IB devices over the same
1020 * PCI device and we have representors and master.
1022 unsigned int nd = 0;
1024 * Number of found IB device Ports. nd = 1 and np = 1..n means
1025 * we have the single multiport IB device, and there may be
1026 * representors attached to some of found ports.
1027 * Currently not supported.
1028 * unsigned int np = 0;
1032 * Number of DPDK ethernet devices to Spawn - either over
1033 * multiple IB devices or multiple ports of single IB device.
1034 * Actually this is the number of iterations to spawn.
1036 unsigned int ns = 0;
1039 * < 0 - no bonding device (single one)
1040 * >= 0 - bonding device (value is slave PF index)
1043 struct mlx5_dev_spawn_data *list = NULL;
1044 struct mlx5_dev_config dev_config;
1045 unsigned int dev_config_vf;
1049 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1050 DRV_LOG(ERR, "Secondary process is not supported on Windows.");
1053 ret = mlx5_init_once();
1055 DRV_LOG(ERR, "unable to init PMD global data: %s",
1056 strerror(rte_errno));
1060 devx_bdf_devs = mlx5_glue->get_device_list(&ret);
1061 orig_devx_bdf_devs = devx_bdf_devs;
1062 if (!devx_bdf_devs) {
1063 rte_errno = errno ? errno : ENOSYS;
1064 DRV_LOG(ERR, "cannot list devices, is ib_uverbs loaded?");
1068 * First scan the list of all Infiniband devices to find
1069 * matching ones, gathering into the list.
1071 struct devx_device_bdf *devx_bdf_match[ret + 1];
1074 err = mlx5_match_devx_devices_to_addr(devx_bdf_devs,
1084 devx_bdf_match[nd++] = devx_bdf_devs;
1086 devx_bdf_match[nd] = NULL;
1088 /* No device matches, just complain and bail out. */
1090 "no DevX device matches PCI device " PCI_PRI_FMT ","
1091 " is DevX Configured?",
1092 pci_dev->addr.domain, pci_dev->addr.bus,
1093 pci_dev->addr.devid, pci_dev->addr.function);
1099 * Now we can determine the maximal
1100 * amount of devices to be spawned.
1102 list = mlx5_malloc(MLX5_MEM_ZERO,
1103 sizeof(struct mlx5_dev_spawn_data),
1104 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
1106 DRV_LOG(ERR, "spawn data array allocation failure");
1111 memset(&list[ns].info, 0, sizeof(list[ns].info));
1112 list[ns].max_port = 1;
1113 list[ns].phys_port = 1;
1114 list[ns].phys_dev = devx_bdf_match[ns];
1115 list[ns].eth_dev = NULL;
1116 list[ns].pci_dev = pci_dev;
1117 list[ns].pf_bond = bd;
1118 list[ns].ifindex = -1; /* Spawn will assign */
1120 (struct mlx5_switch_info){
1123 .name_type = MLX5_PHYS_PORT_NAME_TYPE_UPLINK,
1127 /* Device specific configuration. */
1128 switch (pci_dev->id.device_id) {
1129 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1130 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
1131 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
1132 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
1133 case PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF:
1134 case PCI_DEVICE_ID_MELLANOX_CONNECTX6VF:
1135 case PCI_DEVICE_ID_MELLANOX_CONNECTXVF:
1142 /* Default configuration. */
1143 memset(&dev_config, 0, sizeof(struct mlx5_dev_config));
1144 dev_config.vf = dev_config_vf;
1146 dev_config.dbnc = MLX5_ARG_UNSET;
1147 dev_config.rx_vec_en = 1;
1148 dev_config.txq_inline_max = MLX5_ARG_UNSET;
1149 dev_config.txq_inline_min = MLX5_ARG_UNSET;
1150 dev_config.txq_inline_mpw = MLX5_ARG_UNSET;
1151 dev_config.txqs_inline = MLX5_ARG_UNSET;
1152 dev_config.vf_nl_en = 0;
1153 dev_config.mr_ext_memseg_en = 1;
1154 dev_config.mr_mempool_reg_en = 1;
1155 dev_config.mprq.max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN;
1156 dev_config.mprq.min_rxqs_num = MLX5_MPRQ_MIN_RXQS;
1157 dev_config.dv_esw_en = 0;
1158 dev_config.dv_flow_en = 1;
1159 dev_config.decap_en = 0;
1160 dev_config.log_hp_size = MLX5_ARG_UNSET;
1161 list[ns].numa_node = pci_dev->device.numa_node;
1162 list[ns].eth_dev = mlx5_dev_spawn(&pci_dev->device,
1165 if (!list[ns].eth_dev)
1167 restore = list[ns].eth_dev->data->dev_flags;
1168 rte_eth_copy_pci_info(list[ns].eth_dev, pci_dev);
1169 /* Restore non-PCI flags cleared by the above call. */
1170 list[ns].eth_dev->data->dev_flags |= restore;
1171 rte_eth_dev_probing_finish(list[ns].eth_dev);
1175 * Do the routine cleanup:
1176 * - free allocated spawn data array
1177 * - free the device list
1181 MLX5_ASSERT(orig_devx_bdf_devs);
1182 mlx5_glue->free_device_list(orig_devx_bdf_devs);
1187 * Set the reg_mr and dereg_mr call backs
1189 * @param reg_mr_cb[out]
1190 * Pointer to reg_mr func
1191 * @param dereg_mr_cb[out]
1192 * Pointer to dereg_mr func
1196 mlx5_os_set_reg_mr_cb(mlx5_reg_mr_t *reg_mr_cb,
1197 mlx5_dereg_mr_t *dereg_mr_cb)
1199 *reg_mr_cb = mlx5_os_reg_mr;
1200 *dereg_mr_cb = mlx5_os_dereg_mr;
1204 * Extract pdn of PD object using DevX
1207 * Pointer to the DevX PD object.
1209 * Pointer to the PD object number variable.
1212 * 0 on success, error value otherwise.
1215 mlx5_os_get_pdn(void *pd, uint32_t *pdn)
1220 *pdn = ((struct mlx5_pd *)pd)->pdn;
1224 const struct mlx5_flow_driver_ops mlx5_flow_verbs_drv_ops = {0};