drivers/net/mrvl/mrvl_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2017 Marvell International Ltd.
   3  * Copyright(c) 2017 Semihalf.
   4  * All rights reserved.
   5  */
   6
   7 #include <rte_ethdev_driver.h>
   8 #include <rte_kvargs.h>
   9 #include <rte_log.h>
  10 #include <rte_malloc.h>
  11 #include <rte_bus_vdev.h>
  12
  13 /* Unluckily, container_of is defined by both DPDK and MUSDK,
  14  * we'll declare only one version.
  15  *
  16  * Note that it is not used in this PMD anyway.
  17  */
  18 #ifdef container_of
  19 #undef container_of
  20 #endif
  21
  22 #include <fcntl.h>
  23 #include <linux/ethtool.h>
  24 #include <linux/sockios.h>
  25 #include <net/if.h>
  26 #include <net/if_arp.h>
  27 #include <sys/ioctl.h>
  28 #include <sys/socket.h>
  29 #include <sys/stat.h>
  30 #include <sys/types.h>
  31
  32 #include "mrvl_ethdev.h"
  33 #include "mrvl_qos.h"
  34
  35 /* bitmask with reserved hifs */
  36 #define MRVL_MUSDK_HIFS_RESERVED 0x0F
  37 /* bitmask with reserved bpools */
  38 #define MRVL_MUSDK_BPOOLS_RESERVED 0x07
  39 /* bitmask with reserved kernel RSS tables */
  40 #define MRVL_MUSDK_RSS_RESERVED 0x01
  41 /* maximum number of available hifs */
  42 #define MRVL_MUSDK_HIFS_MAX 9
  43
  44 /* prefetch shift */
  45 #define MRVL_MUSDK_PREFETCH_SHIFT 2
  46
  47 /* TCAM has 25 entries reserved for uc/mc filter entries */
  48 #define MRVL_MAC_ADDRS_MAX 25
  49 #define MRVL_MATCH_LEN 16
  50 #define MRVL_PKT_EFFEC_OFFS (MRVL_PKT_OFFS + MV_MH_SIZE)
  51 /* Maximum allowable packet size */
  52 #define MRVL_PKT_SIZE_MAX (10240 - MV_MH_SIZE)
  53
  54 #define MRVL_IFACE_NAME_ARG "iface"
  55 #define MRVL_CFG_ARG "cfg"
  56
  57 #define MRVL_BURST_SIZE 64
  58
  59 #define MRVL_ARP_LENGTH 28
  60
  61 #define MRVL_COOKIE_ADDR_INVALID ~0ULL
  62
  63 #define MRVL_COOKIE_HIGH_ADDR_SHIFT     (sizeof(pp2_cookie_t) * 8)
  64 #define MRVL_COOKIE_HIGH_ADDR_MASK      (~0ULL << MRVL_COOKIE_HIGH_ADDR_SHIFT)
  65
  66 /* Memory size (in bytes) for MUSDK dma buffers */
  67 #define MRVL_MUSDK_DMA_MEMSIZE 41943040
  68
  69 /** Port Rx offload capabilities */
  70 #define MRVL_RX_OFFLOADS (DEV_RX_OFFLOAD_VLAN_FILTER | \
  71                           DEV_RX_OFFLOAD_JUMBO_FRAME | \
  72                           DEV_RX_OFFLOAD_CRC_STRIP | \
  73                           DEV_RX_OFFLOAD_CHECKSUM)
  74
  75 /** Port Tx offloads capabilities */
  76 #define MRVL_TX_OFFLOADS (DEV_TX_OFFLOAD_IPV4_CKSUM | \
  77                           DEV_TX_OFFLOAD_UDP_CKSUM | \
  78                           DEV_TX_OFFLOAD_TCP_CKSUM)
  79
  80 static const char * const valid_args[] = {
  81         MRVL_IFACE_NAME_ARG,
  82         MRVL_CFG_ARG,
  83         NULL
  84 };
  85
  86 static int used_hifs = MRVL_MUSDK_HIFS_RESERVED;
  87 static struct pp2_hif *hifs[RTE_MAX_LCORE];
  88 static int used_bpools[PP2_NUM_PKT_PROC] = {
  89         MRVL_MUSDK_BPOOLS_RESERVED,
  90         MRVL_MUSDK_BPOOLS_RESERVED
  91 };
  92
  93 struct pp2_bpool *mrvl_port_to_bpool_lookup[RTE_MAX_ETHPORTS];
  94 int mrvl_port_bpool_size[PP2_NUM_PKT_PROC][PP2_BPOOL_NUM_POOLS][RTE_MAX_LCORE];
  95 uint64_t cookie_addr_high = MRVL_COOKIE_ADDR_INVALID;
  96
  97 struct mrvl_ifnames {
  98         const char *names[PP2_NUM_ETH_PPIO * PP2_NUM_PKT_PROC];
  99         int idx;
 100 };
 101
 102 /*
 103  * To use buffer harvesting based on loopback port shadow queue structure
 104  * was introduced for buffers information bookkeeping.
 105  *
 106  * Before sending the packet, related buffer information (pp2_buff_inf) is
 107  * stored in shadow queue. After packet is transmitted no longer used
 108  * packet buffer is released back to it's original hardware pool,
 109  * on condition it originated from interface.
 110  * In case it  was generated by application itself i.e: mbuf->port field is
 111  * 0xff then its released to software mempool.
 112  */
 113 struct mrvl_shadow_txq {
 114         int head;           /* write index - used when sending buffers */
 115         int tail;           /* read index - used when releasing buffers */
 116         u16 size;           /* queue occupied size */
 117         u16 num_to_release; /* number of buffers sent, that can be released */
 118         struct buff_release_entry ent[MRVL_PP2_TX_SHADOWQ_SIZE]; /* q entries */
 119 };
 120
 121 struct mrvl_rxq {
 122         struct mrvl_priv *priv;
 123         struct rte_mempool *mp;
 124         int queue_id;
 125         int port_id;
 126         int cksum_enabled;
 127         uint64_t bytes_recv;
 128         uint64_t drop_mac;
 129 };
 130
 131 struct mrvl_txq {
 132         struct mrvl_priv *priv;
 133         int queue_id;
 134         int port_id;
 135         uint64_t bytes_sent;
 136         struct mrvl_shadow_txq shadow_txqs[RTE_MAX_LCORE];
 137 };
 138
 139 static int mrvl_lcore_first;
 140 static int mrvl_lcore_last;
 141 static int mrvl_dev_num;
 142
 143 static int mrvl_fill_bpool(struct mrvl_rxq *rxq, int num);
 144 static inline void mrvl_free_sent_buffers(struct pp2_ppio *ppio,
 145                         struct pp2_hif *hif, unsigned int core_id,
 146                         struct mrvl_shadow_txq *sq, int qid, int force);
 147
 148 static inline int
 149 mrvl_get_bpool_size(int pp2_id, int pool_id)
 150 {
 151         int i;
 152         int size = 0;
 153
 154         for (i = mrvl_lcore_first; i <= mrvl_lcore_last; i++)
 155                 size += mrvl_port_bpool_size[pp2_id][pool_id][i];
 156
 157         return size;
 158 }
 159
 160 static inline int
 161 mrvl_reserve_bit(int *bitmap, int max)
 162 {
 163         int n = sizeof(*bitmap) * 8 - __builtin_clz(*bitmap);
 164
 165         if (n >= max)
 166                 return -1;
 167
 168         *bitmap |= 1 << n;
 169
 170         return n;
 171 }
 172
 173 static int
 174 mrvl_init_hif(int core_id)
 175 {
 176         struct pp2_hif_params params;
 177         char match[MRVL_MATCH_LEN];
 178         int ret;
 179
 180         ret = mrvl_reserve_bit(&used_hifs, MRVL_MUSDK_HIFS_MAX);
 181         if (ret < 0) {
 182                 RTE_LOG(ERR, PMD, "Failed to allocate hif %d\n", core_id);
 183                 return ret;
 184         }
 185
 186         snprintf(match, sizeof(match), "hif-%d", ret);
 187         memset(&params, 0, sizeof(params));
 188         params.match = match;
 189         params.out_size = MRVL_PP2_AGGR_TXQD_MAX;
 190         ret = pp2_hif_init(&params, &hifs[core_id]);
 191         if (ret) {
 192                 RTE_LOG(ERR, PMD, "Failed to initialize hif %d\n", core_id);
 193                 return ret;
 194         }
 195
 196         return 0;
 197 }
 198
 199 static inline struct pp2_hif*
 200 mrvl_get_hif(struct mrvl_priv *priv, int core_id)
 201 {
 202         int ret;
 203
 204         if (likely(hifs[core_id] != NULL))
 205                 return hifs[core_id];
 206
 207         rte_spinlock_lock(&priv->lock);
 208
 209         ret = mrvl_init_hif(core_id);
 210         if (ret < 0) {
 211                 RTE_LOG(ERR, PMD, "Failed to allocate hif %d\n", core_id);
 212                 goto out;
 213         }
 214
 215         if (core_id < mrvl_lcore_first)
 216                 mrvl_lcore_first = core_id;
 217
 218         if (core_id > mrvl_lcore_last)
 219                 mrvl_lcore_last = core_id;
 220 out:
 221         rte_spinlock_unlock(&priv->lock);
 222
 223         return hifs[core_id];
 224 }
 225
 226 /**
 227  * Configure rss based on dpdk rss configuration.
 228  *
 229  * @param priv
 230  *   Pointer to private structure.
 231  * @param rss_conf
 232  *   Pointer to RSS configuration.
 233  *
 234  * @return
 235  *   0 on success, negative error value otherwise.
 236  */
 237 static int
 238 mrvl_configure_rss(struct mrvl_priv *priv, struct rte_eth_rss_conf *rss_conf)
 239 {
 240         if (rss_conf->rss_key)
 241                 RTE_LOG(WARNING, PMD, "Changing hash key is not supported\n");
 242
 243         if (rss_conf->rss_hf == 0) {
 244                 priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE;
 245         } else if (rss_conf->rss_hf & ETH_RSS_IPV4) {
 246                 priv->ppio_params.inqs_params.hash_type =
 247                         PP2_PPIO_HASH_T_2_TUPLE;
 248         } else if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) {
 249                 priv->ppio_params.inqs_params.hash_type =
 250                         PP2_PPIO_HASH_T_5_TUPLE;
 251                 priv->rss_hf_tcp = 1;
 252         } else if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) {
 253                 priv->ppio_params.inqs_params.hash_type =
 254                         PP2_PPIO_HASH_T_5_TUPLE;
 255                 priv->rss_hf_tcp = 0;
 256         } else {
 257                 return -EINVAL;
 258         }
 259
 260         return 0;
 261 }
 262
 263 /**
 264  * Ethernet device configuration.
 265  *
 266  * Prepare the driver for a given number of TX and RX queues and
 267  * configure RSS.
 268  *
 269  * @param dev
 270  *   Pointer to Ethernet device structure.
 271  *
 272  * @return
 273  *   0 on success, negative error value otherwise.
 274  */
 275 static int
 276 mrvl_dev_configure(struct rte_eth_dev *dev)
 277 {
 278         struct mrvl_priv *priv = dev->data->dev_private;
 279         int ret;
 280
 281         if (dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_NONE &&
 282             dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) {
 283                 RTE_LOG(INFO, PMD, "Unsupported rx multi queue mode %d\n",
 284                         dev->data->dev_conf.rxmode.mq_mode);
 285                 return -EINVAL;
 286         }
 287
 288         if (!(dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_CRC_STRIP)) {
 289                 RTE_LOG(INFO, PMD,
 290                         "L2 CRC stripping is always enabled in hw\n");
 291                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_CRC_STRIP;
 292         }
 293
 294         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
 295                 RTE_LOG(INFO, PMD, "VLAN stripping not supported\n");
 296                 return -EINVAL;
 297         }
 298
 299         if (dev->data->dev_conf.rxmode.split_hdr_size) {
 300                 RTE_LOG(INFO, PMD, "Split headers not supported\n");
 301                 return -EINVAL;
 302         }
 303
 304         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER) {
 305                 RTE_LOG(INFO, PMD, "RX Scatter/Gather not supported\n");
 306                 return -EINVAL;
 307         }
 308
 309         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO) {
 310                 RTE_LOG(INFO, PMD, "LRO not supported\n");
 311                 return -EINVAL;
 312         }
 313
 314         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
 315                 dev->data->mtu = dev->data->dev_conf.rxmode.max_rx_pkt_len -
 316                                  ETHER_HDR_LEN - ETHER_CRC_LEN;
 317
 318         ret = mrvl_configure_rxqs(priv, dev->data->port_id,
 319                                   dev->data->nb_rx_queues);
 320         if (ret < 0)
 321                 return ret;
 322
 323         ret = mrvl_configure_txqs(priv, dev->data->port_id,
 324                                   dev->data->nb_tx_queues);
 325         if (ret < 0)
 326                 return ret;
 327
 328         priv->ppio_params.outqs_params.num_outqs = dev->data->nb_tx_queues;
 329         priv->ppio_params.maintain_stats = 1;
 330         priv->nb_rx_queues = dev->data->nb_rx_queues;
 331
 332         if (dev->data->nb_rx_queues == 1 &&
 333             dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) {
 334                 RTE_LOG(WARNING, PMD, "Disabling hash for 1 rx queue\n");
 335                 priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE;
 336
 337                 return 0;
 338         }
 339
 340         return mrvl_configure_rss(priv,
 341                                   &dev->data->dev_conf.rx_adv_conf.rss_conf);
 342 }
 343
 344 /**
 345  * DPDK callback to change the MTU.
 346  *
 347  * Setting the MTU affects hardware MRU (packets larger than the MRU
 348  * will be dropped).
 349  *
 350  * @param dev
 351  *   Pointer to Ethernet device structure.
 352  * @param mtu
 353  *   New MTU.
 354  *
 355  * @return
 356  *   0 on success, negative error value otherwise.
 357  */
 358 static int
 359 mrvl_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 360 {
 361         struct mrvl_priv *priv = dev->data->dev_private;
 362         /* extra MV_MH_SIZE bytes are required for Marvell tag */
 363         uint16_t mru = mtu + MV_MH_SIZE + ETHER_HDR_LEN + ETHER_CRC_LEN;
 364         int ret;
 365
 366         if (mtu < ETHER_MIN_MTU || mru > MRVL_PKT_SIZE_MAX)
 367                 return -EINVAL;
 368
 369         if (!priv->ppio)
 370                 return 0;
 371
 372         ret = pp2_ppio_set_mru(priv->ppio, mru);
 373         if (ret)
 374                 return ret;
 375
 376         return pp2_ppio_set_mtu(priv->ppio, mtu);
 377 }
 378
 379 /**
 380  * DPDK callback to bring the link up.
 381  *
 382  * @param dev
 383  *   Pointer to Ethernet device structure.
 384  *
 385  * @return
 386  *   0 on success, negative error value otherwise.
 387  */
 388 static int
 389 mrvl_dev_set_link_up(struct rte_eth_dev *dev)
 390 {
 391         struct mrvl_priv *priv = dev->data->dev_private;
 392         int ret;
 393
 394         if (!priv->ppio)
 395                 return -EPERM;
 396
 397         ret = pp2_ppio_enable(priv->ppio);
 398         if (ret)
 399                 return ret;
 400
 401         /*
 402          * mtu/mru can be updated if pp2_ppio_enable() was called at least once
 403          * as pp2_ppio_enable() changes port->t_mode from default 0 to
 404          * PP2_TRAFFIC_INGRESS_EGRESS.
 405          *
 406          * Set mtu to default DPDK value here.
 407          */
 408         ret = mrvl_mtu_set(dev, dev->data->mtu);
 409         if (ret)
 410                 pp2_ppio_disable(priv->ppio);
 411
 412         return ret;
 413 }
 414
 415 /**
 416  * DPDK callback to bring the link down.
 417  *
 418  * @param dev
 419  *   Pointer to Ethernet device structure.
 420  *
 421  * @return
 422  *   0 on success, negative error value otherwise.
 423  */
 424 static int
 425 mrvl_dev_set_link_down(struct rte_eth_dev *dev)
 426 {
 427         struct mrvl_priv *priv = dev->data->dev_private;
 428
 429         if (!priv->ppio)
 430                 return -EPERM;
 431
 432         return pp2_ppio_disable(priv->ppio);
 433 }
 434
 435 /**
 436  * DPDK callback to start the device.
 437  *
 438  * @param dev
 439  *   Pointer to Ethernet device structure.
 440  *
 441  * @return
 442  *   0 on success, negative errno value on failure.
 443  */
 444 static int
 445 mrvl_dev_start(struct rte_eth_dev *dev)
 446 {
 447         struct mrvl_priv *priv = dev->data->dev_private;
 448         char match[MRVL_MATCH_LEN];
 449         int ret = 0, def_init_size;
 450
 451         snprintf(match, sizeof(match), "ppio-%d:%d",
 452                  priv->pp_id, priv->ppio_id);
 453         priv->ppio_params.match = match;
 454
 455         /*
 456          * Calculate the minimum bpool size for refill feature as follows:
 457          * 2 default burst sizes multiply by number of rx queues.
 458          * If the bpool size will be below this value, new buffers will
 459          * be added to the pool.
 460          */
 461         priv->bpool_min_size = priv->nb_rx_queues * MRVL_BURST_SIZE * 2;
 462
 463         /* In case initial bpool size configured in queues setup is
 464          * smaller than minimum size add more buffers
 465          */
 466         def_init_size = priv->bpool_min_size + MRVL_BURST_SIZE * 2;
 467         if (priv->bpool_init_size < def_init_size) {
 468                 int buffs_to_add = def_init_size - priv->bpool_init_size;
 469
 470                 priv->bpool_init_size += buffs_to_add;
 471                 ret = mrvl_fill_bpool(dev->data->rx_queues[0], buffs_to_add);
 472                 if (ret)
 473                         RTE_LOG(ERR, PMD, "Failed to add buffers to bpool\n");
 474         }
 475
 476         /*
 477          * Calculate the maximum bpool size for refill feature as follows:
 478          * maximum number of descriptors in rx queue multiply by number
 479          * of rx queues plus minimum bpool size.
 480          * In case the bpool size will exceed this value, superfluous buffers
 481          * will be removed
 482          */
 483         priv->bpool_max_size = (priv->nb_rx_queues * MRVL_PP2_RXD_MAX) +
 484                                 priv->bpool_min_size;
 485
 486         ret = pp2_ppio_init(&priv->ppio_params, &priv->ppio);
 487         if (ret) {
 488                 RTE_LOG(ERR, PMD, "Failed to init ppio\n");
 489                 return ret;
 490         }
 491
 492         /*
 493          * In case there are some some stale uc/mc mac addresses flush them
 494          * here. It cannot be done during mrvl_dev_close() as port information
 495          * is already gone at that point (due to pp2_ppio_deinit() in
 496          * mrvl_dev_stop()).
 497          */
 498         if (!priv->uc_mc_flushed) {
 499                 ret = pp2_ppio_flush_mac_addrs(priv->ppio, 1, 1);
 500                 if (ret) {
 501                         RTE_LOG(ERR, PMD,
 502                                 "Failed to flush uc/mc filter list\n");
 503                         goto out;
 504                 }
 505                 priv->uc_mc_flushed = 1;
 506         }
 507
 508         if (!priv->vlan_flushed) {
 509                 ret = pp2_ppio_flush_vlan(priv->ppio);
 510                 if (ret) {
 511                         RTE_LOG(ERR, PMD, "Failed to flush vlan list\n");
 512                         /*
 513                          * TODO
 514                          * once pp2_ppio_flush_vlan() is supported jump to out
 515                          * goto out;
 516                          */
 517                 }
 518                 priv->vlan_flushed = 1;
 519         }
 520
 521         /* For default QoS config, don't start classifier. */
 522         if (mrvl_qos_cfg) {
 523                 ret = mrvl_start_qos_mapping(priv);
 524                 if (ret) {
 525                         RTE_LOG(ERR, PMD, "Failed to setup QoS mapping\n");
 526                         goto out;
 527                 }
 528         }
 529
 530         ret = mrvl_dev_set_link_up(dev);
 531         if (ret) {
 532                 RTE_LOG(ERR, PMD, "Failed to set link up\n");
 533                 goto out;
 534         }
 535
 536         return 0;
 537 out:
 538         RTE_LOG(ERR, PMD, "Failed to start device\n");
 539         pp2_ppio_deinit(priv->ppio);
 540         return ret;
 541 }
 542
 543 /**
 544  * Flush receive queues.
 545  *
 546  * @param dev
 547  *   Pointer to Ethernet device structure.
 548  */
 549 static void
 550 mrvl_flush_rx_queues(struct rte_eth_dev *dev)
 551 {
 552         int i;
 553
 554         RTE_LOG(INFO, PMD, "Flushing rx queues\n");
 555         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 556                 int ret, num;
 557
 558                 do {
 559                         struct mrvl_rxq *q = dev->data->rx_queues[i];
 560                         struct pp2_ppio_desc descs[MRVL_PP2_RXD_MAX];
 561
 562                         num = MRVL_PP2_RXD_MAX;
 563                         ret = pp2_ppio_recv(q->priv->ppio,
 564                                             q->priv->rxq_map[q->queue_id].tc,
 565                                             q->priv->rxq_map[q->queue_id].inq,
 566                                             descs, (uint16_t *)&num);
 567                 } while (ret == 0 && num);
 568         }
 569 }
 570
 571 /**
 572  * Flush transmit shadow queues.
 573  *
 574  * @param dev
 575  *   Pointer to Ethernet device structure.
 576  */
 577 static void
 578 mrvl_flush_tx_shadow_queues(struct rte_eth_dev *dev)
 579 {
 580         int i, j;
 581         struct mrvl_txq *txq;
 582
 583         RTE_LOG(INFO, PMD, "Flushing tx shadow queues\n");
 584         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 585                 txq = (struct mrvl_txq *)dev->data->tx_queues[i];
 586
 587                 for (j = 0; j < RTE_MAX_LCORE; j++) {
 588                         struct mrvl_shadow_txq *sq;
 589
 590                         if (!hifs[j])
 591                                 continue;
 592
 593                         sq = &txq->shadow_txqs[j];
 594                         mrvl_free_sent_buffers(txq->priv->ppio,
 595                                 hifs[j], j, sq, txq->queue_id, 1);
 596                         while (sq->tail != sq->head) {
 597                                 uint64_t addr = cookie_addr_high |
 598                                         sq->ent[sq->tail].buff.cookie;
 599                                 rte_pktmbuf_free(
 600                                         (struct rte_mbuf *)addr);
 601                                 sq->tail = (sq->tail + 1) &
 602                                             MRVL_PP2_TX_SHADOWQ_MASK;
 603                         }
 604                         memset(sq, 0, sizeof(*sq));
 605                 }
 606         }
 607 }
 608
 609 /**
 610  * Flush hardware bpool (buffer-pool).
 611  *
 612  * @param dev
 613  *   Pointer to Ethernet device structure.
 614  */
 615 static void
 616 mrvl_flush_bpool(struct rte_eth_dev *dev)
 617 {
 618         struct mrvl_priv *priv = dev->data->dev_private;
 619         struct pp2_hif *hif;
 620         uint32_t num;
 621         int ret;
 622         unsigned int core_id = rte_lcore_id();
 623
 624         if (core_id == LCORE_ID_ANY)
 625                 core_id = 0;
 626
 627         hif = mrvl_get_hif(priv, core_id);
 628
 629         ret = pp2_bpool_get_num_buffs(priv->bpool, &num);
 630         if (ret) {
 631                 RTE_LOG(ERR, PMD, "Failed to get bpool buffers number\n");
 632                 return;
 633         }
 634
 635         while (num--) {
 636                 struct pp2_buff_inf inf;
 637                 uint64_t addr;
 638
 639                 ret = pp2_bpool_get_buff(hif, priv->bpool, &inf);
 640                 if (ret)
 641                         break;
 642
 643                 addr = cookie_addr_high | inf.cookie;
 644                 rte_pktmbuf_free((struct rte_mbuf *)addr);
 645         }
 646 }
 647
 648 /**
 649  * DPDK callback to stop the device.
 650  *
 651  * @param dev
 652  *   Pointer to Ethernet device structure.
 653  */
 654 static void
 655 mrvl_dev_stop(struct rte_eth_dev *dev)
 656 {
 657         struct mrvl_priv *priv = dev->data->dev_private;
 658
 659         mrvl_dev_set_link_down(dev);
 660         mrvl_flush_rx_queues(dev);
 661         mrvl_flush_tx_shadow_queues(dev);
 662         if (priv->cls_tbl) {
 663                 pp2_cls_tbl_deinit(priv->cls_tbl);
 664                 priv->cls_tbl = NULL;
 665         }
 666         if (priv->qos_tbl) {
 667                 pp2_cls_qos_tbl_deinit(priv->qos_tbl);
 668                 priv->qos_tbl = NULL;
 669         }
 670         if (priv->ppio)
 671                 pp2_ppio_deinit(priv->ppio);
 672         priv->ppio = NULL;
 673
 674         /* policer must be released after ppio deinitialization */
 675         if (priv->policer) {
 676                 pp2_cls_plcr_deinit(priv->policer);
 677                 priv->policer = NULL;
 678         }
 679 }
 680
 681 /**
 682  * DPDK callback to close the device.
 683  *
 684  * @param dev
 685  *   Pointer to Ethernet device structure.
 686  */
 687 static void
 688 mrvl_dev_close(struct rte_eth_dev *dev)
 689 {
 690         struct mrvl_priv *priv = dev->data->dev_private;
 691         size_t i;
 692
 693         for (i = 0; i < priv->ppio_params.inqs_params.num_tcs; ++i) {
 694                 struct pp2_ppio_tc_params *tc_params =
 695                         &priv->ppio_params.inqs_params.tcs_params[i];
 696
 697                 if (tc_params->inqs_params) {
 698                         rte_free(tc_params->inqs_params);
 699                         tc_params->inqs_params = NULL;
 700                 }
 701         }
 702
 703         mrvl_flush_bpool(dev);
 704 }
 705
 706 /**
 707  * DPDK callback to retrieve physical link information.
 708  *
 709  * @param dev
 710  *   Pointer to Ethernet device structure.
 711  * @param wait_to_complete
 712  *   Wait for request completion (ignored).
 713  *
 714  * @return
 715  *   0 on success, negative error value otherwise.
 716  */
 717 static int
 718 mrvl_link_update(struct rte_eth_dev *dev, int wait_to_complete __rte_unused)
 719 {
 720         /*
 721          * TODO
 722          * once MUSDK provides necessary API use it here
 723          */
 724         struct mrvl_priv *priv = dev->data->dev_private;
 725         struct ethtool_cmd edata;
 726         struct ifreq req;
 727         int ret, fd, link_up;
 728
 729         if (!priv->ppio)
 730                 return -EPERM;
 731
 732         edata.cmd = ETHTOOL_GSET;
 733
 734         strcpy(req.ifr_name, dev->data->name);
 735         req.ifr_data = (void *)&edata;
 736
 737         fd = socket(AF_INET, SOCK_DGRAM, 0);
 738         if (fd == -1)
 739                 return -EFAULT;
 740
 741         ret = ioctl(fd, SIOCETHTOOL, &req);
 742         if (ret == -1) {
 743                 close(fd);
 744                 return -EFAULT;
 745         }
 746
 747         close(fd);
 748
 749         switch (ethtool_cmd_speed(&edata)) {
 750         case SPEED_10:
 751                 dev->data->dev_link.link_speed = ETH_SPEED_NUM_10M;
 752                 break;
 753         case SPEED_100:
 754                 dev->data->dev_link.link_speed = ETH_SPEED_NUM_100M;
 755                 break;
 756         case SPEED_1000:
 757                 dev->data->dev_link.link_speed = ETH_SPEED_NUM_1G;
 758                 break;
 759         case SPEED_10000:
 760                 dev->data->dev_link.link_speed = ETH_SPEED_NUM_10G;
 761                 break;
 762         default:
 763                 dev->data->dev_link.link_speed = ETH_SPEED_NUM_NONE;
 764         }
 765
 766         dev->data->dev_link.link_duplex = edata.duplex ? ETH_LINK_FULL_DUPLEX :
 767                                                          ETH_LINK_HALF_DUPLEX;
 768         dev->data->dev_link.link_autoneg = edata.autoneg ? ETH_LINK_AUTONEG :
 769                                                            ETH_LINK_FIXED;
 770         pp2_ppio_get_link_state(priv->ppio, &link_up);
 771         dev->data->dev_link.link_status = link_up ? ETH_LINK_UP : ETH_LINK_DOWN;
 772
 773         return 0;
 774 }
 775
 776 /**
 777  * DPDK callback to enable promiscuous mode.
 778  *
 779  * @param dev
 780  *   Pointer to Ethernet device structure.
 781  */
 782 static void
 783 mrvl_promiscuous_enable(struct rte_eth_dev *dev)
 784 {
 785         struct mrvl_priv *priv = dev->data->dev_private;
 786         int ret;
 787
 788         if (!priv->ppio)
 789                 return;
 790
 791         if (priv->isolated)
 792                 return;
 793
 794         ret = pp2_ppio_set_promisc(priv->ppio, 1);
 795         if (ret)
 796                 RTE_LOG(ERR, PMD, "Failed to enable promiscuous mode\n");
 797 }
 798
 799 /**
 800  * DPDK callback to enable allmulti mode.
 801  *
 802  * @param dev
 803  *   Pointer to Ethernet device structure.
 804  */
 805 static void
 806 mrvl_allmulticast_enable(struct rte_eth_dev *dev)
 807 {
 808         struct mrvl_priv *priv = dev->data->dev_private;
 809         int ret;
 810
 811         if (!priv->ppio)
 812                 return;
 813
 814         if (priv->isolated)
 815                 return;
 816
 817         ret = pp2_ppio_set_mc_promisc(priv->ppio, 1);
 818         if (ret)
 819                 RTE_LOG(ERR, PMD, "Failed enable all-multicast mode\n");
 820 }
 821
 822 /**
 823  * DPDK callback to disable promiscuous mode.
 824  *
 825  * @param dev
 826  *   Pointer to Ethernet device structure.
 827  */
 828 static void
 829 mrvl_promiscuous_disable(struct rte_eth_dev *dev)
 830 {
 831         struct mrvl_priv *priv = dev->data->dev_private;
 832         int ret;
 833
 834         if (!priv->ppio)
 835                 return;
 836
 837         ret = pp2_ppio_set_promisc(priv->ppio, 0);
 838         if (ret)
 839                 RTE_LOG(ERR, PMD, "Failed to disable promiscuous mode\n");
 840 }
 841
 842 /**
 843  * DPDK callback to disable allmulticast mode.
 844  *
 845  * @param dev
 846  *   Pointer to Ethernet device structure.
 847  */
 848 static void
 849 mrvl_allmulticast_disable(struct rte_eth_dev *dev)
 850 {
 851         struct mrvl_priv *priv = dev->data->dev_private;
 852         int ret;
 853
 854         if (!priv->ppio)
 855                 return;
 856
 857         ret = pp2_ppio_set_mc_promisc(priv->ppio, 0);
 858         if (ret)
 859                 RTE_LOG(ERR, PMD, "Failed to disable all-multicast mode\n");
 860 }
 861
 862 /**
 863  * DPDK callback to remove a MAC address.
 864  *
 865  * @param dev
 866  *   Pointer to Ethernet device structure.
 867  * @param index
 868  *   MAC address index.
 869  */
 870 static void
 871 mrvl_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index)
 872 {
 873         struct mrvl_priv *priv = dev->data->dev_private;
 874         char buf[ETHER_ADDR_FMT_SIZE];
 875         int ret;
 876
 877         if (!priv->ppio)
 878                 return;
 879
 880         if (priv->isolated)
 881                 return;
 882
 883         ret = pp2_ppio_remove_mac_addr(priv->ppio,
 884                                        dev->data->mac_addrs[index].addr_bytes);
 885         if (ret) {
 886                 ether_format_addr(buf, sizeof(buf),
 887                                   &dev->data->mac_addrs[index]);
 888                 RTE_LOG(ERR, PMD, "Failed to remove mac %s\n", buf);
 889         }
 890 }
 891
 892 /**
 893  * DPDK callback to add a MAC address.
 894  *
 895  * @param dev
 896  *   Pointer to Ethernet device structure.
 897  * @param mac_addr
 898  *   MAC address to register.
 899  * @param index
 900  *   MAC address index.
 901  * @param vmdq
 902  *   VMDq pool index to associate address with (unused).
 903  *
 904  * @return
 905  *   0 on success, negative error value otherwise.
 906  */
 907 static int
 908 mrvl_mac_addr_add(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 909                   uint32_t index, uint32_t vmdq __rte_unused)
 910 {
 911         struct mrvl_priv *priv = dev->data->dev_private;
 912         char buf[ETHER_ADDR_FMT_SIZE];
 913         int ret;
 914
 915         if (priv->isolated)
 916                 return -ENOTSUP;
 917
 918         if (index == 0)
 919                 /* For setting index 0, mrvl_mac_addr_set() should be used.*/
 920                 return -1;
 921
 922         if (!priv->ppio)
 923                 return 0;
 924
 925         /*
 926          * Maximum number of uc addresses can be tuned via kernel module mvpp2x
 927          * parameter uc_filter_max. Maximum number of mc addresses is then
 928          * MRVL_MAC_ADDRS_MAX - uc_filter_max. Currently it defaults to 4 and
 929          * 21 respectively.
 930          *
 931          * If more than uc_filter_max uc addresses were added to filter list
 932          * then NIC will switch to promiscuous mode automatically.
 933          *
 934          * If more than MRVL_MAC_ADDRS_MAX - uc_filter_max number mc addresses
 935          * were added to filter list then NIC will switch to all-multicast mode
 936          * automatically.
 937          */
 938         ret = pp2_ppio_add_mac_addr(priv->ppio, mac_addr->addr_bytes);
 939         if (ret) {
 940                 ether_format_addr(buf, sizeof(buf), mac_addr);
 941                 RTE_LOG(ERR, PMD, "Failed to add mac %s\n", buf);
 942                 return -1;
 943         }
 944
 945         return 0;
 946 }
 947
 948 /**
 949  * DPDK callback to set the primary MAC address.
 950  *
 951  * @param dev
 952  *   Pointer to Ethernet device structure.
 953  * @param mac_addr
 954  *   MAC address to register.
 955  */
 956 static void
 957 mrvl_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr)
 958 {
 959         struct mrvl_priv *priv = dev->data->dev_private;
 960         int ret;
 961
 962         if (!priv->ppio)
 963                 return;
 964
 965         if (priv->isolated)
 966                 return;
 967
 968         ret = pp2_ppio_set_mac_addr(priv->ppio, mac_addr->addr_bytes);
 969         if (ret) {
 970                 char buf[ETHER_ADDR_FMT_SIZE];
 971                 ether_format_addr(buf, sizeof(buf), mac_addr);
 972                 RTE_LOG(ERR, PMD, "Failed to set mac to %s\n", buf);
 973         }
 974 }
 975
 976 /**
 977  * DPDK callback to get device statistics.
 978  *
 979  * @param dev
 980  *   Pointer to Ethernet device structure.
 981  * @param stats
 982  *   Stats structure output buffer.
 983  *
 984  * @return
 985  *   0 on success, negative error value otherwise.
 986  */
 987 static int
 988 mrvl_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
 989 {
 990         struct mrvl_priv *priv = dev->data->dev_private;
 991         struct pp2_ppio_statistics ppio_stats;
 992         uint64_t drop_mac = 0;
 993         unsigned int i, idx, ret;
 994
 995         if (!priv->ppio)
 996                 return -EPERM;
 997
 998         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 999                 struct mrvl_rxq *rxq = dev->data->rx_queues[i];
1000                 struct pp2_ppio_inq_statistics rx_stats;
1001
1002                 if (!rxq)
1003                         continue;
1004
1005                 idx = rxq->queue_id;
1006                 if (unlikely(idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)) {
1007                         RTE_LOG(ERR, PMD,
1008                                 "rx queue %d stats out of range (0 - %d)\n",
1009                                 idx, RTE_ETHDEV_QUEUE_STAT_CNTRS - 1);
1010                         continue;
1011                 }
1012
1013                 ret = pp2_ppio_inq_get_statistics(priv->ppio,
1014                                                   priv->rxq_map[idx].tc,
1015                                                   priv->rxq_map[idx].inq,
1016                                                   &rx_stats, 0);
1017                 if (unlikely(ret)) {
1018                         RTE_LOG(ERR, PMD,
1019                                 "Failed to update rx queue %d stats\n", idx);
1020                         break;
1021                 }
1022
1023                 stats->q_ibytes[idx] = rxq->bytes_recv;
1024                 stats->q_ipackets[idx] = rx_stats.enq_desc - rxq->drop_mac;
1025                 stats->q_errors[idx] = rx_stats.drop_early +
1026                                        rx_stats.drop_fullq +
1027                                        rx_stats.drop_bm +
1028                                        rxq->drop_mac;
1029                 stats->ibytes += rxq->bytes_recv;
1030                 drop_mac += rxq->drop_mac;
1031         }
1032
1033         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1034                 struct mrvl_txq *txq = dev->data->tx_queues[i];
1035                 struct pp2_ppio_outq_statistics tx_stats;
1036
1037                 if (!txq)
1038                         continue;
1039
1040                 idx = txq->queue_id;
1041                 if (unlikely(idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)) {
1042                         RTE_LOG(ERR, PMD,
1043                                 "tx queue %d stats out of range (0 - %d)\n",
1044                                 idx, RTE_ETHDEV_QUEUE_STAT_CNTRS - 1);
1045                 }
1046
1047                 ret = pp2_ppio_outq_get_statistics(priv->ppio, idx,
1048                                                    &tx_stats, 0);
1049                 if (unlikely(ret)) {
1050                         RTE_LOG(ERR, PMD,
1051                                 "Failed to update tx queue %d stats\n", idx);
1052                         break;
1053                 }
1054
1055                 stats->q_opackets[idx] = tx_stats.deq_desc;
1056                 stats->q_obytes[idx] = txq->bytes_sent;
1057                 stats->obytes += txq->bytes_sent;
1058         }
1059
1060         ret = pp2_ppio_get_statistics(priv->ppio, &ppio_stats, 0);
1061         if (unlikely(ret)) {
1062                 RTE_LOG(ERR, PMD, "Failed to update port statistics\n");
1063                 return ret;
1064         }
1065
1066         stats->ipackets += ppio_stats.rx_packets - drop_mac;
1067         stats->opackets += ppio_stats.tx_packets;
1068         stats->imissed += ppio_stats.rx_fullq_dropped +
1069                           ppio_stats.rx_bm_dropped +
1070                           ppio_stats.rx_early_dropped +
1071                           ppio_stats.rx_fifo_dropped +
1072                           ppio_stats.rx_cls_dropped;
1073         stats->ierrors = drop_mac;
1074
1075         return 0;
1076 }
1077
1078 /**
1079  * DPDK callback to clear device statistics.
1080  *
1081  * @param dev
1082  *   Pointer to Ethernet device structure.
1083  */
1084 static void
1085 mrvl_stats_reset(struct rte_eth_dev *dev)
1086 {
1087         struct mrvl_priv *priv = dev->data->dev_private;
1088         int i;
1089
1090         if (!priv->ppio)
1091                 return;
1092
1093         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1094                 struct mrvl_rxq *rxq = dev->data->rx_queues[i];
1095
1096                 pp2_ppio_inq_get_statistics(priv->ppio, priv->rxq_map[i].tc,
1097                                             priv->rxq_map[i].inq, NULL, 1);
1098                 rxq->bytes_recv = 0;
1099                 rxq->drop_mac = 0;
1100         }
1101
1102         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1103                 struct mrvl_txq *txq = dev->data->tx_queues[i];
1104
1105                 pp2_ppio_outq_get_statistics(priv->ppio, i, NULL, 1);
1106                 txq->bytes_sent = 0;
1107         }
1108
1109         pp2_ppio_get_statistics(priv->ppio, NULL, 1);
1110 }
1111
1112 /**
1113  * DPDK callback to get information about the device.
1114  *
1115  * @param dev
1116  *   Pointer to Ethernet device structure (unused).
1117  * @param info
1118  *   Info structure output buffer.
1119  */
1120 static void
1121 mrvl_dev_infos_get(struct rte_eth_dev *dev __rte_unused,
1122                    struct rte_eth_dev_info *info)
1123 {
1124         info->speed_capa = ETH_LINK_SPEED_10M |
1125                            ETH_LINK_SPEED_100M |
1126                            ETH_LINK_SPEED_1G |
1127                            ETH_LINK_SPEED_10G;
1128
1129         info->max_rx_queues = MRVL_PP2_RXQ_MAX;
1130         info->max_tx_queues = MRVL_PP2_TXQ_MAX;
1131         info->max_mac_addrs = MRVL_MAC_ADDRS_MAX;
1132
1133         info->rx_desc_lim.nb_max = MRVL_PP2_RXD_MAX;
1134         info->rx_desc_lim.nb_min = MRVL_PP2_RXD_MIN;
1135         info->rx_desc_lim.nb_align = MRVL_PP2_RXD_ALIGN;
1136
1137         info->tx_desc_lim.nb_max = MRVL_PP2_TXD_MAX;
1138         info->tx_desc_lim.nb_min = MRVL_PP2_TXD_MIN;
1139         info->tx_desc_lim.nb_align = MRVL_PP2_TXD_ALIGN;
1140
1141         info->rx_offload_capa = MRVL_RX_OFFLOADS;
1142         info->rx_queue_offload_capa = MRVL_RX_OFFLOADS;
1143
1144         info->tx_offload_capa = MRVL_TX_OFFLOADS;
1145         info->tx_queue_offload_capa = MRVL_TX_OFFLOADS;
1146
1147         info->flow_type_rss_offloads = ETH_RSS_IPV4 |
1148                                        ETH_RSS_NONFRAG_IPV4_TCP |
1149                                        ETH_RSS_NONFRAG_IPV4_UDP;
1150
1151         /* By default packets are dropped if no descriptors are available */
1152         info->default_rxconf.rx_drop_en = 1;
1153         info->default_rxconf.offloads = DEV_RX_OFFLOAD_CRC_STRIP;
1154
1155         info->max_rx_pktlen = MRVL_PKT_SIZE_MAX;
1156 }
1157
1158 /**
1159  * Return supported packet types.
1160  *
1161  * @param dev
1162  *   Pointer to Ethernet device structure (unused).
1163  *
1164  * @return
1165  *   Const pointer to the table with supported packet types.
1166  */
1167 static const uint32_t *
1168 mrvl_dev_supported_ptypes_get(struct rte_eth_dev *dev __rte_unused)
1169 {
1170         static const uint32_t ptypes[] = {
1171                 RTE_PTYPE_L2_ETHER,
1172                 RTE_PTYPE_L3_IPV4,
1173                 RTE_PTYPE_L3_IPV4_EXT,
1174                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1175                 RTE_PTYPE_L3_IPV6,
1176                 RTE_PTYPE_L3_IPV6_EXT,
1177                 RTE_PTYPE_L2_ETHER_ARP,
1178                 RTE_PTYPE_L4_TCP,
1179                 RTE_PTYPE_L4_UDP
1180         };
1181
1182         return ptypes;
1183 }
1184
1185 /**
1186  * DPDK callback to get information about specific receive queue.
1187  *
1188  * @param dev
1189  *   Pointer to Ethernet device structure.
1190  * @param rx_queue_id
1191  *   Receive queue index.
1192  * @param qinfo
1193  *   Receive queue information structure.
1194  */
1195 static void mrvl_rxq_info_get(struct rte_eth_dev *dev, uint16_t rx_queue_id,
1196                               struct rte_eth_rxq_info *qinfo)
1197 {
1198         struct mrvl_rxq *q = dev->data->rx_queues[rx_queue_id];
1199         struct mrvl_priv *priv = dev->data->dev_private;
1200         int inq = priv->rxq_map[rx_queue_id].inq;
1201         int tc = priv->rxq_map[rx_queue_id].tc;
1202         struct pp2_ppio_tc_params *tc_params =
1203                 &priv->ppio_params.inqs_params.tcs_params[tc];
1204
1205         qinfo->mp = q->mp;
1206         qinfo->nb_desc = tc_params->inqs_params[inq].size;
1207 }
1208
1209 /**
1210  * DPDK callback to get information about specific transmit queue.
1211  *
1212  * @param dev
1213  *   Pointer to Ethernet device structure.
1214  * @param tx_queue_id
1215  *   Transmit queue index.
1216  * @param qinfo
1217  *   Transmit queue information structure.
1218  */
1219 static void mrvl_txq_info_get(struct rte_eth_dev *dev, uint16_t tx_queue_id,
1220                               struct rte_eth_txq_info *qinfo)
1221 {
1222         struct mrvl_priv *priv = dev->data->dev_private;
1223
1224         qinfo->nb_desc =
1225                 priv->ppio_params.outqs_params.outqs_params[tx_queue_id].size;
1226 }
1227
1228 /**
1229  * DPDK callback to Configure a VLAN filter.
1230  *
1231  * @param dev
1232  *   Pointer to Ethernet device structure.
1233  * @param vlan_id
1234  *   VLAN ID to filter.
1235  * @param on
1236  *   Toggle filter.
1237  *
1238  * @return
1239  *   0 on success, negative error value otherwise.
1240  */
1241 static int
1242 mrvl_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1243 {
1244         struct mrvl_priv *priv = dev->data->dev_private;
1245
1246         if (!priv->ppio)
1247                 return -EPERM;
1248
1249         if (priv->isolated)
1250                 return -ENOTSUP;
1251
1252         return on ? pp2_ppio_add_vlan(priv->ppio, vlan_id) :
1253                     pp2_ppio_remove_vlan(priv->ppio, vlan_id);
1254 }
1255
1256 /**
1257  * Release buffers to hardware bpool (buffer-pool)
1258  *
1259  * @param rxq
1260  *   Receive queue pointer.
1261  * @param num
1262  *   Number of buffers to release to bpool.
1263  *
1264  * @return
1265  *   0 on success, negative error value otherwise.
1266  */
1267 static int
1268 mrvl_fill_bpool(struct mrvl_rxq *rxq, int num)
1269 {
1270         struct buff_release_entry entries[MRVL_PP2_TXD_MAX];
1271         struct rte_mbuf *mbufs[MRVL_PP2_TXD_MAX];
1272         int i, ret;
1273         unsigned int core_id;
1274         struct pp2_hif *hif;
1275         struct pp2_bpool *bpool;
1276
1277         core_id = rte_lcore_id();
1278         if (core_id == LCORE_ID_ANY)
1279                 core_id = 0;
1280
1281         hif = mrvl_get_hif(rxq->priv, core_id);
1282         if (!hif)
1283                 return -1;
1284
1285         bpool = rxq->priv->bpool;
1286
1287         ret = rte_pktmbuf_alloc_bulk(rxq->mp, mbufs, num);
1288         if (ret)
1289                 return ret;
1290
1291         if (cookie_addr_high == MRVL_COOKIE_ADDR_INVALID)
1292                 cookie_addr_high =
1293                         (uint64_t)mbufs[0] & MRVL_COOKIE_HIGH_ADDR_MASK;
1294
1295         for (i = 0; i < num; i++) {
1296                 if (((uint64_t)mbufs[i] & MRVL_COOKIE_HIGH_ADDR_MASK)
1297                         != cookie_addr_high) {
1298                         RTE_LOG(ERR, PMD,
1299                                 "mbuf virtual addr high 0x%lx out of range\n",
1300                                 (uint64_t)mbufs[i] >> 32);
1301                         goto out;
1302                 }
1303
1304                 entries[i].buff.addr =
1305                         rte_mbuf_data_iova_default(mbufs[i]);
1306                 entries[i].buff.cookie = (pp2_cookie_t)(uint64_t)mbufs[i];
1307                 entries[i].bpool = bpool;
1308         }
1309
1310         pp2_bpool_put_buffs(hif, entries, (uint16_t *)&i);
1311         mrvl_port_bpool_size[bpool->pp2_id][bpool->id][core_id] += i;
1312
1313         if (i != num)
1314                 goto out;
1315
1316         return 0;
1317 out:
1318         for (; i < num; i++)
1319                 rte_pktmbuf_free(mbufs[i]);
1320
1321         return -1;
1322 }
1323
1324 /**
1325  * Check whether requested rx queue offloads match port offloads.
1326  *
1327  * @param
1328  *   dev Pointer to the device.
1329  * @param
1330  *   requested Bitmap of the requested offloads.
1331  *
1332  * @return
1333  *   1 if requested offloads are okay, 0 otherwise.
1334  */
1335 static int
1336 mrvl_rx_queue_offloads_okay(struct rte_eth_dev *dev, uint64_t requested)
1337 {
1338         uint64_t mandatory = dev->data->dev_conf.rxmode.offloads;
1339         uint64_t supported = MRVL_RX_OFFLOADS;
1340         uint64_t unsupported = requested & ~supported;
1341         uint64_t missing = mandatory & ~requested;
1342
1343         if (unsupported) {
1344                 RTE_LOG(ERR, PMD, "Some Rx offloads are not supported. "
1345                         "Requested 0x%" PRIx64 " supported 0x%" PRIx64 ".\n",
1346                         requested, supported);
1347                 return 0;
1348         }
1349
1350         if (missing) {
1351                 RTE_LOG(ERR, PMD, "Some Rx offloads are missing. "
1352                         "Requested 0x%" PRIx64 " missing 0x%" PRIx64 ".\n",
1353                         requested, missing);
1354                 return 0;
1355         }
1356
1357         return 1;
1358 }
1359
1360 /**
1361  * DPDK callback to configure the receive queue.
1362  *
1363  * @param dev
1364  *   Pointer to Ethernet device structure.
1365  * @param idx
1366  *   RX queue index.
1367  * @param desc
1368  *   Number of descriptors to configure in queue.
1369  * @param socket
1370  *   NUMA socket on which memory must be allocated.
1371  * @param conf
1372  *   Thresholds parameters.
1373  * @param mp
1374  *   Memory pool for buffer allocations.
1375  *
1376  * @return
1377  *   0 on success, negative error value otherwise.
1378  */
1379 static int
1380 mrvl_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1381                     unsigned int socket,
1382                     const struct rte_eth_rxconf *conf,
1383                     struct rte_mempool *mp)
1384 {
1385         struct mrvl_priv *priv = dev->data->dev_private;
1386         struct mrvl_rxq *rxq;
1387         uint32_t min_size,
1388                  max_rx_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
1389         int ret, tc, inq;
1390
1391         if (!mrvl_rx_queue_offloads_okay(dev, conf->offloads))
1392                 return -ENOTSUP;
1393
1394         if (priv->rxq_map[idx].tc == MRVL_UNKNOWN_TC) {
1395                 /*
1396                  * Unknown TC mapping, mapping will not have a correct queue.
1397                  */
1398                 RTE_LOG(ERR, PMD, "Unknown TC mapping for queue %hu eth%hhu\n",
1399                         idx, priv->ppio_id);
1400                 return -EFAULT;
1401         }
1402
1403         min_size = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM -
1404                    MRVL_PKT_EFFEC_OFFS;
1405         if (min_size < max_rx_pkt_len) {
1406                 RTE_LOG(ERR, PMD,
1407                         "Mbuf size must be increased to %u bytes to hold up to %u bytes of data.\n",
1408                         max_rx_pkt_len + RTE_PKTMBUF_HEADROOM +
1409                         MRVL_PKT_EFFEC_OFFS,
1410                         max_rx_pkt_len);
1411                 return -EINVAL;
1412         }
1413
1414         if (dev->data->rx_queues[idx]) {
1415                 rte_free(dev->data->rx_queues[idx]);
1416                 dev->data->rx_queues[idx] = NULL;
1417         }
1418
1419         rxq = rte_zmalloc_socket("rxq", sizeof(*rxq), 0, socket);
1420         if (!rxq)
1421                 return -ENOMEM;
1422
1423         rxq->priv = priv;
1424         rxq->mp = mp;
1425         rxq->cksum_enabled =
1426                 dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_IPV4_CKSUM;
1427         rxq->queue_id = idx;
1428         rxq->port_id = dev->data->port_id;
1429         mrvl_port_to_bpool_lookup[rxq->port_id] = priv->bpool;
1430
1431         tc = priv->rxq_map[rxq->queue_id].tc,
1432         inq = priv->rxq_map[rxq->queue_id].inq;
1433         priv->ppio_params.inqs_params.tcs_params[tc].inqs_params[inq].size =
1434                 desc;
1435
1436         ret = mrvl_fill_bpool(rxq, desc);
1437         if (ret) {
1438                 rte_free(rxq);
1439                 return ret;
1440         }
1441
1442         priv->bpool_init_size += desc;
1443
1444         dev->data->rx_queues[idx] = rxq;
1445
1446         return 0;
1447 }
1448
1449 /**
1450  * DPDK callback to release the receive queue.
1451  *
1452  * @param rxq
1453  *   Generic receive queue pointer.
1454  */
1455 static void
1456 mrvl_rx_queue_release(void *rxq)
1457 {
1458         struct mrvl_rxq *q = rxq;
1459         struct pp2_ppio_tc_params *tc_params;
1460         int i, num, tc, inq;
1461         struct pp2_hif *hif;
1462         unsigned int core_id = rte_lcore_id();
1463
1464         if (core_id == LCORE_ID_ANY)
1465                 core_id = 0;
1466
1467         hif = mrvl_get_hif(q->priv, core_id);
1468
1469         if (!q || !hif)
1470                 return;
1471
1472         tc = q->priv->rxq_map[q->queue_id].tc;
1473         inq = q->priv->rxq_map[q->queue_id].inq;
1474         tc_params = &q->priv->ppio_params.inqs_params.tcs_params[tc];
1475         num = tc_params->inqs_params[inq].size;
1476         for (i = 0; i < num; i++) {
1477                 struct pp2_buff_inf inf;
1478                 uint64_t addr;
1479
1480                 pp2_bpool_get_buff(hif, q->priv->bpool, &inf);
1481                 addr = cookie_addr_high | inf.cookie;
1482                 rte_pktmbuf_free((struct rte_mbuf *)addr);
1483         }
1484
1485         rte_free(q);
1486 }
1487
1488 /**
1489  * Check whether requested tx queue offloads match port offloads.
1490  *
1491  * @param
1492  *   dev Pointer to the device.
1493  * @param
1494  *   requested Bitmap of the requested offloads.
1495  *
1496  * @return
1497  *   1 if requested offloads are okay, 0 otherwise.
1498  */
1499 static int
1500 mrvl_tx_queue_offloads_okay(struct rte_eth_dev *dev, uint64_t requested)
1501 {
1502         uint64_t mandatory = dev->data->dev_conf.txmode.offloads;
1503         uint64_t supported = MRVL_TX_OFFLOADS;
1504         uint64_t unsupported = requested & ~supported;
1505         uint64_t missing = mandatory & ~requested;
1506
1507         if (unsupported) {
1508                 RTE_LOG(ERR, PMD, "Some Rx offloads are not supported. "
1509                         "Requested 0x%" PRIx64 " supported 0x%" PRIx64 ".\n",
1510                         requested, supported);
1511                 return 0;
1512         }
1513
1514         if (missing) {
1515                 RTE_LOG(ERR, PMD, "Some Rx offloads are missing. "
1516                         "Requested 0x%" PRIx64 " missing 0x%" PRIx64 ".\n",
1517                         requested, missing);
1518                 return 0;
1519         }
1520
1521         return 1;
1522 }
1523
1524 /**
1525  * DPDK callback to configure the transmit queue.
1526  *
1527  * @param dev
1528  *   Pointer to Ethernet device structure.
1529  * @param idx
1530  *   Transmit queue index.
1531  * @param desc
1532  *   Number of descriptors to configure in the queue.
1533  * @param socket
1534  *   NUMA socket on which memory must be allocated.
1535  * @param conf
1536  *   Thresholds parameters.
1537  *
1538  * @return
1539  *   0 on success, negative error value otherwise.
1540  */
1541 static int
1542 mrvl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1543                     unsigned int socket,
1544                     const struct rte_eth_txconf *conf)
1545 {
1546         struct mrvl_priv *priv = dev->data->dev_private;
1547         struct mrvl_txq *txq;
1548
1549         if (!mrvl_tx_queue_offloads_okay(dev, conf->offloads))
1550                 return -ENOTSUP;
1551
1552         if (dev->data->tx_queues[idx]) {
1553                 rte_free(dev->data->tx_queues[idx]);
1554                 dev->data->tx_queues[idx] = NULL;
1555         }
1556
1557         txq = rte_zmalloc_socket("txq", sizeof(*txq), 0, socket);
1558         if (!txq)
1559                 return -ENOMEM;
1560
1561         txq->priv = priv;
1562         txq->queue_id = idx;
1563         txq->port_id = dev->data->port_id;
1564         dev->data->tx_queues[idx] = txq;
1565
1566         priv->ppio_params.outqs_params.outqs_params[idx].size = desc;
1567
1568         return 0;
1569 }
1570
1571 /**
1572  * DPDK callback to release the transmit queue.
1573  *
1574  * @param txq
1575  *   Generic transmit queue pointer.
1576  */
1577 static void
1578 mrvl_tx_queue_release(void *txq)
1579 {
1580         struct mrvl_txq *q = txq;
1581
1582         if (!q)
1583                 return;
1584
1585         rte_free(q);
1586 }
1587
1588 /**
1589  * Update RSS hash configuration
1590  *
1591  * @param dev
1592  *   Pointer to Ethernet device structure.
1593  * @param rss_conf
1594  *   Pointer to RSS configuration.
1595  *
1596  * @return
1597  *   0 on success, negative error value otherwise.
1598  */
1599 static int
1600 mrvl_rss_hash_update(struct rte_eth_dev *dev,
1601                      struct rte_eth_rss_conf *rss_conf)
1602 {
1603         struct mrvl_priv *priv = dev->data->dev_private;
1604
1605         if (priv->isolated)
1606                 return -ENOTSUP;
1607
1608         return mrvl_configure_rss(priv, rss_conf);
1609 }
1610
1611 /**
1612  * DPDK callback to get RSS hash configuration.
1613  *
1614  * @param dev
1615  *   Pointer to Ethernet device structure.
1616  * @rss_conf
1617  *   Pointer to RSS configuration.
1618  *
1619  * @return
1620  *   Always 0.
1621  */
1622 static int
1623 mrvl_rss_hash_conf_get(struct rte_eth_dev *dev,
1624                        struct rte_eth_rss_conf *rss_conf)
1625 {
1626         struct mrvl_priv *priv = dev->data->dev_private;
1627         enum pp2_ppio_hash_type hash_type =
1628                 priv->ppio_params.inqs_params.hash_type;
1629
1630         rss_conf->rss_key = NULL;
1631
1632         if (hash_type == PP2_PPIO_HASH_T_NONE)
1633                 rss_conf->rss_hf = 0;
1634         else if (hash_type == PP2_PPIO_HASH_T_2_TUPLE)
1635                 rss_conf->rss_hf = ETH_RSS_IPV4;
1636         else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && priv->rss_hf_tcp)
1637                 rss_conf->rss_hf = ETH_RSS_NONFRAG_IPV4_TCP;
1638         else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && !priv->rss_hf_tcp)
1639                 rss_conf->rss_hf = ETH_RSS_NONFRAG_IPV4_UDP;
1640
1641         return 0;
1642 }
1643
1644 /**
1645  * DPDK callback to get rte_flow callbacks.
1646  *
1647  * @param dev
1648  *   Pointer to the device structure.
1649  * @param filer_type
1650  *   Flow filter type.
1651  * @param filter_op
1652  *   Flow filter operation.
1653  * @param arg
1654  *   Pointer to pass the flow ops.
1655  *
1656  * @return
1657  *   0 on success, negative error value otherwise.
1658  */
1659 static int
1660 mrvl_eth_filter_ctrl(struct rte_eth_dev *dev __rte_unused,
1661                      enum rte_filter_type filter_type,
1662                      enum rte_filter_op filter_op, void *arg)
1663 {
1664         switch (filter_type) {
1665         case RTE_ETH_FILTER_GENERIC:
1666                 if (filter_op != RTE_ETH_FILTER_GET)
1667                         return -EINVAL;
1668                 *(const void **)arg = &mrvl_flow_ops;
1669                 return 0;
1670         default:
1671                 RTE_LOG(WARNING, PMD, "Filter type (%d) not supported",
1672                                 filter_type);
1673                 return -EINVAL;
1674         }
1675 }
1676
1677 static const struct eth_dev_ops mrvl_ops = {
1678         .dev_configure = mrvl_dev_configure,
1679         .dev_start = mrvl_dev_start,
1680         .dev_stop = mrvl_dev_stop,
1681         .dev_set_link_up = mrvl_dev_set_link_up,
1682         .dev_set_link_down = mrvl_dev_set_link_down,
1683         .dev_close = mrvl_dev_close,
1684         .link_update = mrvl_link_update,
1685         .promiscuous_enable = mrvl_promiscuous_enable,
1686         .allmulticast_enable = mrvl_allmulticast_enable,
1687         .promiscuous_disable = mrvl_promiscuous_disable,
1688         .allmulticast_disable = mrvl_allmulticast_disable,
1689         .mac_addr_remove = mrvl_mac_addr_remove,
1690         .mac_addr_add = mrvl_mac_addr_add,
1691         .mac_addr_set = mrvl_mac_addr_set,
1692         .mtu_set = mrvl_mtu_set,
1693         .stats_get = mrvl_stats_get,
1694         .stats_reset = mrvl_stats_reset,
1695         .dev_infos_get = mrvl_dev_infos_get,
1696         .dev_supported_ptypes_get = mrvl_dev_supported_ptypes_get,
1697         .rxq_info_get = mrvl_rxq_info_get,
1698         .txq_info_get = mrvl_txq_info_get,
1699         .vlan_filter_set = mrvl_vlan_filter_set,
1700         .rx_queue_setup = mrvl_rx_queue_setup,
1701         .rx_queue_release = mrvl_rx_queue_release,
1702         .tx_queue_setup = mrvl_tx_queue_setup,
1703         .tx_queue_release = mrvl_tx_queue_release,
1704         .rss_hash_update = mrvl_rss_hash_update,
1705         .rss_hash_conf_get = mrvl_rss_hash_conf_get,
1706         .filter_ctrl = mrvl_eth_filter_ctrl
1707 };
1708
1709 /**
1710  * Return packet type information and l3/l4 offsets.
1711  *
1712  * @param desc
1713  *   Pointer to the received packet descriptor.
1714  * @param l3_offset
1715  *   l3 packet offset.
1716  * @param l4_offset
1717  *   l4 packet offset.
1718  *
1719  * @return
1720  *   Packet type information.
1721  */
1722 static inline uint64_t
1723 mrvl_desc_to_packet_type_and_offset(struct pp2_ppio_desc *desc,
1724                                     uint8_t *l3_offset, uint8_t *l4_offset)
1725 {
1726         enum pp2_inq_l3_type l3_type;
1727         enum pp2_inq_l4_type l4_type;
1728         uint64_t packet_type;
1729
1730         pp2_ppio_inq_desc_get_l3_info(desc, &l3_type, l3_offset);
1731         pp2_ppio_inq_desc_get_l4_info(desc, &l4_type, l4_offset);
1732
1733         packet_type = RTE_PTYPE_L2_ETHER;
1734
1735         switch (l3_type) {
1736         case PP2_INQ_L3_TYPE_IPV4_NO_OPTS:
1737                 packet_type |= RTE_PTYPE_L3_IPV4;
1738                 break;
1739         case PP2_INQ_L3_TYPE_IPV4_OK:
1740                 packet_type |= RTE_PTYPE_L3_IPV4_EXT;
1741                 break;
1742         case PP2_INQ_L3_TYPE_IPV4_TTL_ZERO:
1743                 packet_type |= RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
1744                 break;
1745         case PP2_INQ_L3_TYPE_IPV6_NO_EXT:
1746                 packet_type |= RTE_PTYPE_L3_IPV6;
1747                 break;
1748         case PP2_INQ_L3_TYPE_IPV6_EXT:
1749                 packet_type |= RTE_PTYPE_L3_IPV6_EXT;
1750                 break;
1751         case PP2_INQ_L3_TYPE_ARP:
1752                 packet_type |= RTE_PTYPE_L2_ETHER_ARP;
1753                 /*
1754                  * In case of ARP l4_offset is set to wrong value.
1755                  * Set it to proper one so that later on mbuf->l3_len can be
1756                  * calculated subtracting l4_offset and l3_offset.
1757                  */
1758                 *l4_offset = *l3_offset + MRVL_ARP_LENGTH;
1759                 break;
1760         default:
1761                 RTE_LOG(DEBUG, PMD, "Failed to recognise l3 packet type\n");
1762                 break;
1763         }
1764
1765         switch (l4_type) {
1766         case PP2_INQ_L4_TYPE_TCP:
1767                 packet_type |= RTE_PTYPE_L4_TCP;
1768                 break;
1769         case PP2_INQ_L4_TYPE_UDP:
1770                 packet_type |= RTE_PTYPE_L4_UDP;
1771                 break;
1772         default:
1773                 RTE_LOG(DEBUG, PMD, "Failed to recognise l4 packet type\n");
1774                 break;
1775         }
1776
1777         return packet_type;
1778 }
1779
1780 /**
1781  * Get offload information from the received packet descriptor.
1782  *
1783  * @param desc
1784  *   Pointer to the received packet descriptor.
1785  *
1786  * @return
1787  *   Mbuf offload flags.
1788  */
1789 static inline uint64_t
1790 mrvl_desc_to_ol_flags(struct pp2_ppio_desc *desc)
1791 {
1792         uint64_t flags;
1793         enum pp2_inq_desc_status status;
1794
1795         status = pp2_ppio_inq_desc_get_l3_pkt_error(desc);
1796         if (unlikely(status != PP2_DESC_ERR_OK))
1797                 flags = PKT_RX_IP_CKSUM_BAD;
1798         else
1799                 flags = PKT_RX_IP_CKSUM_GOOD;
1800
1801         status = pp2_ppio_inq_desc_get_l4_pkt_error(desc);
1802         if (unlikely(status != PP2_DESC_ERR_OK))
1803                 flags |= PKT_RX_L4_CKSUM_BAD;
1804         else
1805                 flags |= PKT_RX_L4_CKSUM_GOOD;
1806
1807         return flags;
1808 }
1809
1810 /**
1811  * DPDK callback for receive.
1812  *
1813  * @param rxq
1814  *   Generic pointer to the receive queue.
1815  * @param rx_pkts
1816  *   Array to store received packets.
1817  * @param nb_pkts
1818  *   Maximum number of packets in array.
1819  *
1820  * @return
1821  *   Number of packets successfully received.
1822  */
1823 static uint16_t
1824 mrvl_rx_pkt_burst(void *rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1825 {
1826         struct mrvl_rxq *q = rxq;
1827         struct pp2_ppio_desc descs[nb_pkts];
1828         struct pp2_bpool *bpool;
1829         int i, ret, rx_done = 0;
1830         int num;
1831         struct pp2_hif *hif;
1832         unsigned int core_id = rte_lcore_id();
1833
1834         hif = mrvl_get_hif(q->priv, core_id);
1835
1836         if (unlikely(!q->priv->ppio || !hif))
1837                 return 0;
1838
1839         bpool = q->priv->bpool;
1840
1841         ret = pp2_ppio_recv(q->priv->ppio, q->priv->rxq_map[q->queue_id].tc,
1842                             q->priv->rxq_map[q->queue_id].inq, descs, &nb_pkts);
1843         if (unlikely(ret < 0)) {
1844                 RTE_LOG(ERR, PMD, "Failed to receive packets\n");
1845                 return 0;
1846         }
1847         mrvl_port_bpool_size[bpool->pp2_id][bpool->id][core_id] -= nb_pkts;
1848
1849         for (i = 0; i < nb_pkts; i++) {
1850                 struct rte_mbuf *mbuf;
1851                 uint8_t l3_offset, l4_offset;
1852                 enum pp2_inq_desc_status status;
1853                 uint64_t addr;
1854
1855                 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) {
1856                         struct pp2_ppio_desc *pref_desc;
1857                         u64 pref_addr;
1858
1859                         pref_desc = &descs[i + MRVL_MUSDK_PREFETCH_SHIFT];
1860                         pref_addr = cookie_addr_high |
1861                                     pp2_ppio_inq_desc_get_cookie(pref_desc);
1862                         rte_mbuf_prefetch_part1((struct rte_mbuf *)(pref_addr));
1863                         rte_mbuf_prefetch_part2((struct rte_mbuf *)(pref_addr));
1864                 }
1865
1866                 addr = cookie_addr_high |
1867                        pp2_ppio_inq_desc_get_cookie(&descs[i]);
1868                 mbuf = (struct rte_mbuf *)addr;
1869                 rte_pktmbuf_reset(mbuf);
1870
1871                 /* drop packet in case of mac, overrun or resource error */
1872                 status = pp2_ppio_inq_desc_get_l2_pkt_error(&descs[i]);
1873                 if (unlikely(status != PP2_DESC_ERR_OK)) {
1874                         struct pp2_buff_inf binf = {
1875                                 .addr = rte_mbuf_data_iova_default(mbuf),
1876                                 .cookie = (pp2_cookie_t)(uint64_t)mbuf,
1877                         };
1878
1879                         pp2_bpool_put_buff(hif, bpool, &binf);
1880                         mrvl_port_bpool_size
1881                                 [bpool->pp2_id][bpool->id][core_id]++;
1882                         q->drop_mac++;
1883                         continue;
1884                 }
1885
1886                 mbuf->data_off += MRVL_PKT_EFFEC_OFFS;
1887                 mbuf->pkt_len = pp2_ppio_inq_desc_get_pkt_len(&descs[i]);
1888                 mbuf->data_len = mbuf->pkt_len;
1889                 mbuf->port = q->port_id;
1890                 mbuf->packet_type =
1891                         mrvl_desc_to_packet_type_and_offset(&descs[i],
1892                                                             &l3_offset,
1893                                                             &l4_offset);
1894                 mbuf->l2_len = l3_offset;
1895                 mbuf->l3_len = l4_offset - l3_offset;
1896
1897                 if (likely(q->cksum_enabled))
1898                         mbuf->ol_flags = mrvl_desc_to_ol_flags(&descs[i]);
1899
1900                 rx_pkts[rx_done++] = mbuf;
1901                 q->bytes_recv += mbuf->pkt_len;
1902         }
1903
1904         if (rte_spinlock_trylock(&q->priv->lock) == 1) {
1905                 num = mrvl_get_bpool_size(bpool->pp2_id, bpool->id);
1906
1907                 if (unlikely(num <= q->priv->bpool_min_size ||
1908                              (!rx_done && num < q->priv->bpool_init_size))) {
1909                         ret = mrvl_fill_bpool(q, MRVL_BURST_SIZE);
1910                         if (ret)
1911                                 RTE_LOG(ERR, PMD, "Failed to fill bpool\n");
1912                 } else if (unlikely(num > q->priv->bpool_max_size)) {
1913                         int i;
1914                         int pkt_to_remove = num - q->priv->bpool_init_size;
1915                         struct rte_mbuf *mbuf;
1916                         struct pp2_buff_inf buff;
1917
1918                         RTE_LOG(DEBUG, PMD,
1919                                 "\nport-%d:%d: bpool %d oversize - remove %d buffers (pool size: %d -> %d)\n",
1920                                 bpool->pp2_id, q->priv->ppio->port_id,
1921                                 bpool->id, pkt_to_remove, num,
1922                                 q->priv->bpool_init_size);
1923
1924                         for (i = 0; i < pkt_to_remove; i++) {
1925                                 ret = pp2_bpool_get_buff(hif, bpool, &buff);
1926                                 if (ret)
1927                                         break;
1928                                 mbuf = (struct rte_mbuf *)
1929                                         (cookie_addr_high | buff.cookie);
1930                                 rte_pktmbuf_free(mbuf);
1931                         }
1932                         mrvl_port_bpool_size
1933                                 [bpool->pp2_id][bpool->id][core_id] -= i;
1934                 }
1935                 rte_spinlock_unlock(&q->priv->lock);
1936         }
1937
1938         return rx_done;
1939 }
1940
1941 /**
1942  * Prepare offload information.
1943  *
1944  * @param ol_flags
1945  *   Offload flags.
1946  * @param packet_type
1947  *   Packet type bitfield.
1948  * @param l3_type
1949  *   Pointer to the pp2_ouq_l3_type structure.
1950  * @param l4_type
1951  *   Pointer to the pp2_outq_l4_type structure.
1952  * @param gen_l3_cksum
1953  *   Will be set to 1 in case l3 checksum is computed.
1954  * @param l4_cksum
1955  *   Will be set to 1 in case l4 checksum is computed.
1956  *
1957  * @return
1958  *   0 on success, negative error value otherwise.
1959  */
1960 static inline int
1961 mrvl_prepare_proto_info(uint64_t ol_flags, uint32_t packet_type,
1962                         enum pp2_outq_l3_type *l3_type,
1963                         enum pp2_outq_l4_type *l4_type,
1964                         int *gen_l3_cksum,
1965                         int *gen_l4_cksum)
1966 {
1967         /*
1968          * Based on ol_flags prepare information
1969          * for pp2_ppio_outq_desc_set_proto_info() which setups descriptor
1970          * for offloading.
1971          */
1972         if (ol_flags & PKT_TX_IPV4) {
1973                 *l3_type = PP2_OUTQ_L3_TYPE_IPV4;
1974                 *gen_l3_cksum = ol_flags & PKT_TX_IP_CKSUM ? 1 : 0;
1975         } else if (ol_flags & PKT_TX_IPV6) {
1976                 *l3_type = PP2_OUTQ_L3_TYPE_IPV6;
1977                 /* no checksum for ipv6 header */
1978                 *gen_l3_cksum = 0;
1979         } else {
1980                 /* if something different then stop processing */
1981                 return -1;
1982         }
1983
1984         ol_flags &= PKT_TX_L4_MASK;
1985         if ((packet_type & RTE_PTYPE_L4_TCP) &&
1986             ol_flags == PKT_TX_TCP_CKSUM) {
1987                 *l4_type = PP2_OUTQ_L4_TYPE_TCP;
1988                 *gen_l4_cksum = 1;
1989         } else if ((packet_type & RTE_PTYPE_L4_UDP) &&
1990                    ol_flags == PKT_TX_UDP_CKSUM) {
1991                 *l4_type = PP2_OUTQ_L4_TYPE_UDP;
1992                 *gen_l4_cksum = 1;
1993         } else {
1994                 *l4_type = PP2_OUTQ_L4_TYPE_OTHER;
1995                 /* no checksum for other type */
1996                 *gen_l4_cksum = 0;
1997         }
1998
1999         return 0;
2000 }
2001
2002 /**
2003  * Release already sent buffers to bpool (buffer-pool).
2004  *
2005  * @param ppio
2006  *   Pointer to the port structure.
2007  * @param hif
2008  *   Pointer to the MUSDK hardware interface.
2009  * @param sq
2010  *   Pointer to the shadow queue.
2011  * @param qid
2012  *   Queue id number.
2013  * @param force
2014  *   Force releasing packets.
2015  */
2016 static inline void
2017 mrvl_free_sent_buffers(struct pp2_ppio *ppio, struct pp2_hif *hif,
2018                        unsigned int core_id, struct mrvl_shadow_txq *sq,
2019                        int qid, int force)
2020 {
2021         struct buff_release_entry *entry;
2022         uint16_t nb_done = 0, num = 0, skip_bufs = 0;
2023         int i;
2024
2025         pp2_ppio_get_num_outq_done(ppio, hif, qid, &nb_done);
2026
2027         sq->num_to_release += nb_done;
2028
2029         if (likely(!force &&
2030                    sq->num_to_release < MRVL_PP2_BUF_RELEASE_BURST_SIZE))
2031                 return;
2032
2033         nb_done = sq->num_to_release;
2034         sq->num_to_release = 0;
2035
2036         for (i = 0; i < nb_done; i++) {
2037                 entry = &sq->ent[sq->tail + num];
2038                 if (unlikely(!entry->buff.addr)) {
2039                         RTE_LOG(ERR, PMD,
2040                                 "Shadow memory @%d: cookie(%lx), pa(%lx)!\n",
2041                                 sq->tail, (u64)entry->buff.cookie,
2042                                 (u64)entry->buff.addr);
2043                         skip_bufs = 1;
2044                         goto skip;
2045                 }
2046
2047                 if (unlikely(!entry->bpool)) {
2048                         struct rte_mbuf *mbuf;
2049
2050                         mbuf = (struct rte_mbuf *)
2051                                (cookie_addr_high | entry->buff.cookie);
2052                         rte_pktmbuf_free(mbuf);
2053                         skip_bufs = 1;
2054                         goto skip;
2055                 }
2056
2057                 mrvl_port_bpool_size
2058                         [entry->bpool->pp2_id][entry->bpool->id][core_id]++;
2059                 num++;
2060                 if (unlikely(sq->tail + num == MRVL_PP2_TX_SHADOWQ_SIZE))
2061                         goto skip;
2062                 continue;
2063 skip:
2064                 if (likely(num))
2065                         pp2_bpool_put_buffs(hif, &sq->ent[sq->tail], &num);
2066                 num += skip_bufs;
2067                 sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK;
2068                 sq->size -= num;
2069                 num = 0;
2070                 skip_bufs = 0;
2071         }
2072
2073         if (likely(num)) {
2074                 pp2_bpool_put_buffs(hif, &sq->ent[sq->tail], &num);
2075                 sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK;
2076                 sq->size -= num;
2077         }
2078 }
2079
2080 /**
2081  * DPDK callback for transmit.
2082  *
2083  * @param txq
2084  *   Generic pointer transmit queue.
2085  * @param tx_pkts
2086  *   Packets to transmit.
2087  * @param nb_pkts
2088  *   Number of packets in array.
2089  *
2090  * @return
2091  *   Number of packets successfully transmitted.
2092  */
2093 static uint16_t
2094 mrvl_tx_pkt_burst(void *txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2095 {
2096         struct mrvl_txq *q = txq;
2097         struct mrvl_shadow_txq *sq;
2098         struct pp2_hif *hif;
2099         struct pp2_ppio_desc descs[nb_pkts];
2100         unsigned int core_id = rte_lcore_id();
2101         int i, ret, bytes_sent = 0;
2102         uint16_t num, sq_free_size;
2103         uint64_t addr;
2104
2105         hif = mrvl_get_hif(q->priv, core_id);
2106         sq = &q->shadow_txqs[core_id];
2107
2108         if (unlikely(!q->priv->ppio || !hif))
2109                 return 0;
2110
2111         if (sq->size)
2112                 mrvl_free_sent_buffers(q->priv->ppio, hif, core_id,
2113                                        sq, q->queue_id, 0);
2114
2115         sq_free_size = MRVL_PP2_TX_SHADOWQ_SIZE - sq->size - 1;
2116         if (unlikely(nb_pkts > sq_free_size)) {
2117                 RTE_LOG(DEBUG, PMD,
2118                         "No room in shadow queue for %d packets! %d packets will be sent.\n",
2119                         nb_pkts, sq_free_size);
2120                 nb_pkts = sq_free_size;
2121         }
2122
2123         for (i = 0; i < nb_pkts; i++) {
2124                 struct rte_mbuf *mbuf = tx_pkts[i];
2125                 int gen_l3_cksum, gen_l4_cksum;
2126                 enum pp2_outq_l3_type l3_type;
2127                 enum pp2_outq_l4_type l4_type;
2128
2129                 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) {
2130                         struct rte_mbuf *pref_pkt_hdr;
2131
2132                         pref_pkt_hdr = tx_pkts[i + MRVL_MUSDK_PREFETCH_SHIFT];
2133                         rte_mbuf_prefetch_part1(pref_pkt_hdr);
2134                         rte_mbuf_prefetch_part2(pref_pkt_hdr);
2135                 }
2136
2137                 sq->ent[sq->head].buff.cookie = (pp2_cookie_t)(uint64_t)mbuf;
2138                 sq->ent[sq->head].buff.addr =
2139                         rte_mbuf_data_iova_default(mbuf);
2140                 sq->ent[sq->head].bpool =
2141                         (unlikely(mbuf->port >= RTE_MAX_ETHPORTS ||
2142                          mbuf->refcnt > 1)) ? NULL :
2143                          mrvl_port_to_bpool_lookup[mbuf->port];
2144                 sq->head = (sq->head + 1) & MRVL_PP2_TX_SHADOWQ_MASK;
2145                 sq->size++;
2146
2147                 pp2_ppio_outq_desc_reset(&descs[i]);
2148                 pp2_ppio_outq_desc_set_phys_addr(&descs[i],
2149                                                  rte_pktmbuf_iova(mbuf));
2150                 pp2_ppio_outq_desc_set_pkt_offset(&descs[i], 0);
2151                 pp2_ppio_outq_desc_set_pkt_len(&descs[i],
2152                                                rte_pktmbuf_pkt_len(mbuf));
2153
2154                 bytes_sent += rte_pktmbuf_pkt_len(mbuf);
2155                 /*
2156                  * in case unsupported ol_flags were passed
2157                  * do not update descriptor offload information
2158                  */
2159                 ret = mrvl_prepare_proto_info(mbuf->ol_flags, mbuf->packet_type,
2160                                               &l3_type, &l4_type, &gen_l3_cksum,
2161                                               &gen_l4_cksum);
2162                 if (unlikely(ret))
2163                         continue;
2164
2165                 pp2_ppio_outq_desc_set_proto_info(&descs[i], l3_type, l4_type,
2166                                                   mbuf->l2_len,
2167                                                   mbuf->l2_len + mbuf->l3_len,
2168                                                   gen_l3_cksum, gen_l4_cksum);
2169         }
2170
2171         num = nb_pkts;
2172         pp2_ppio_send(q->priv->ppio, hif, q->queue_id, descs, &nb_pkts);
2173         /* number of packets that were not sent */
2174         if (unlikely(num > nb_pkts)) {
2175                 for (i = nb_pkts; i < num; i++) {
2176                         sq->head = (MRVL_PP2_TX_SHADOWQ_SIZE + sq->head - 1) &
2177                                 MRVL_PP2_TX_SHADOWQ_MASK;
2178                         addr = cookie_addr_high | sq->ent[sq->head].buff.cookie;
2179                         bytes_sent -=
2180                                 rte_pktmbuf_pkt_len((struct rte_mbuf *)addr);
2181                 }
2182                 sq->size -= num - nb_pkts;
2183         }
2184
2185         q->bytes_sent += bytes_sent;
2186
2187         return nb_pkts;
2188 }
2189
2190 /**
2191  * Initialize packet processor.
2192  *
2193  * @return
2194  *   0 on success, negative error value otherwise.
2195  */
2196 static int
2197 mrvl_init_pp2(void)
2198 {
2199         struct pp2_init_params init_params;
2200
2201         memset(&init_params, 0, sizeof(init_params));
2202         init_params.hif_reserved_map = MRVL_MUSDK_HIFS_RESERVED;
2203         init_params.bm_pool_reserved_map = MRVL_MUSDK_BPOOLS_RESERVED;
2204         init_params.rss_tbl_reserved_map = MRVL_MUSDK_RSS_RESERVED;
2205
2206         return pp2_init(&init_params);
2207 }
2208
2209 /**
2210  * Deinitialize packet processor.
2211  *
2212  * @return
2213  *   0 on success, negative error value otherwise.
2214  */
2215 static void
2216 mrvl_deinit_pp2(void)
2217 {
2218         pp2_deinit();
2219 }
2220
2221 /**
2222  * Create private device structure.
2223  *
2224  * @param dev_name
2225  *   Pointer to the port name passed in the initialization parameters.
2226  *
2227  * @return
2228  *   Pointer to the newly allocated private device structure.
2229  */
2230 static struct mrvl_priv *
2231 mrvl_priv_create(const char *dev_name)
2232 {
2233         struct pp2_bpool_params bpool_params;
2234         char match[MRVL_MATCH_LEN];
2235         struct mrvl_priv *priv;
2236         int ret, bpool_bit;
2237
2238         priv = rte_zmalloc_socket(dev_name, sizeof(*priv), 0, rte_socket_id());
2239         if (!priv)
2240                 return NULL;
2241
2242         ret = pp2_netdev_get_ppio_info((char *)(uintptr_t)dev_name,
2243                                        &priv->pp_id, &priv->ppio_id);
2244         if (ret)
2245                 goto out_free_priv;
2246
2247         bpool_bit = mrvl_reserve_bit(&used_bpools[priv->pp_id],
2248                                      PP2_BPOOL_NUM_POOLS);
2249         if (bpool_bit < 0)
2250                 goto out_free_priv;
2251         priv->bpool_bit = bpool_bit;
2252
2253         snprintf(match, sizeof(match), "pool-%d:%d", priv->pp_id,
2254                  priv->bpool_bit);
2255         memset(&bpool_params, 0, sizeof(bpool_params));
2256         bpool_params.match = match;
2257         bpool_params.buff_len = MRVL_PKT_SIZE_MAX + MRVL_PKT_EFFEC_OFFS;
2258         ret = pp2_bpool_init(&bpool_params, &priv->bpool);
2259         if (ret)
2260                 goto out_clear_bpool_bit;
2261
2262         priv->ppio_params.type = PP2_PPIO_T_NIC;
2263         rte_spinlock_init(&priv->lock);
2264
2265         return priv;
2266 out_clear_bpool_bit:
2267         used_bpools[priv->pp_id] &= ~(1 << priv->bpool_bit);
2268 out_free_priv:
2269         rte_free(priv);
2270         return NULL;
2271 }
2272
2273 /**
2274  * Create device representing Ethernet port.
2275  *
2276  * @param name
2277  *   Pointer to the port's name.
2278  *
2279  * @return
2280  *   0 on success, negative error value otherwise.
2281  */
2282 static int
2283 mrvl_eth_dev_create(struct rte_vdev_device *vdev, const char *name)
2284 {
2285         int ret, fd = socket(AF_INET, SOCK_DGRAM, 0);
2286         struct rte_eth_dev *eth_dev;
2287         struct mrvl_priv *priv;
2288         struct ifreq req;
2289
2290         eth_dev = rte_eth_dev_allocate(name);
2291         if (!eth_dev)
2292                 return -ENOMEM;
2293
2294         priv = mrvl_priv_create(name);
2295         if (!priv) {
2296                 ret = -ENOMEM;
2297                 goto out_free_dev;
2298         }
2299
2300         eth_dev->data->mac_addrs =
2301                 rte_zmalloc("mac_addrs",
2302                             ETHER_ADDR_LEN * MRVL_MAC_ADDRS_MAX, 0);
2303         if (!eth_dev->data->mac_addrs) {
2304                 RTE_LOG(ERR, PMD, "Failed to allocate space for eth addrs\n");
2305                 ret = -ENOMEM;
2306                 goto out_free_priv;
2307         }
2308
2309         memset(&req, 0, sizeof(req));
2310         strcpy(req.ifr_name, name);
2311         ret = ioctl(fd, SIOCGIFHWADDR, &req);
2312         if (ret)
2313                 goto out_free_mac;
2314
2315         memcpy(eth_dev->data->mac_addrs[0].addr_bytes,
2316                req.ifr_addr.sa_data, ETHER_ADDR_LEN);
2317
2318         eth_dev->rx_pkt_burst = mrvl_rx_pkt_burst;
2319         eth_dev->tx_pkt_burst = mrvl_tx_pkt_burst;
2320         eth_dev->data->kdrv = RTE_KDRV_NONE;
2321         eth_dev->data->dev_private = priv;
2322         eth_dev->device = &vdev->device;
2323         eth_dev->dev_ops = &mrvl_ops;
2324
2325         return 0;
2326 out_free_mac:
2327         rte_free(eth_dev->data->mac_addrs);
2328 out_free_dev:
2329         rte_eth_dev_release_port(eth_dev);
2330 out_free_priv:
2331         rte_free(priv);
2332
2333         return ret;
2334 }
2335
2336 /**
2337  * Cleanup previously created device representing Ethernet port.
2338  *
2339  * @param name
2340  *   Pointer to the port name.
2341  */
2342 static void
2343 mrvl_eth_dev_destroy(const char *name)
2344 {
2345         struct rte_eth_dev *eth_dev;
2346         struct mrvl_priv *priv;
2347
2348         eth_dev = rte_eth_dev_allocated(name);
2349         if (!eth_dev)
2350                 return;
2351
2352         priv = eth_dev->data->dev_private;
2353         pp2_bpool_deinit(priv->bpool);
2354         used_bpools[priv->pp_id] &= ~(1 << priv->bpool_bit);
2355         rte_free(priv);
2356         rte_free(eth_dev->data->mac_addrs);
2357         rte_eth_dev_release_port(eth_dev);
2358 }
2359
2360 /**
2361  * Callback used by rte_kvargs_process() during argument parsing.
2362  *
2363  * @param key
2364  *   Pointer to the parsed key (unused).
2365  * @param value
2366  *   Pointer to the parsed value.
2367  * @param extra_args
2368  *   Pointer to the extra arguments which contains address of the
2369  *   table of pointers to parsed interface names.
2370  *
2371  * @return
2372  *   Always 0.
2373  */
2374 static int
2375 mrvl_get_ifnames(const char *key __rte_unused, const char *value,
2376                  void *extra_args)
2377 {
2378         struct mrvl_ifnames *ifnames = extra_args;
2379
2380         ifnames->names[ifnames->idx++] = value;
2381
2382         return 0;
2383 }
2384
2385 /**
2386  * Deinitialize per-lcore MUSDK hardware interfaces (hifs).
2387  */
2388 static void
2389 mrvl_deinit_hifs(void)
2390 {
2391         int i;
2392
2393         for (i = mrvl_lcore_first; i <= mrvl_lcore_last; i++) {
2394                 if (hifs[i])
2395                         pp2_hif_deinit(hifs[i]);
2396         }
2397         used_hifs = MRVL_MUSDK_HIFS_RESERVED;
2398         memset(hifs, 0, sizeof(hifs));
2399 }
2400
2401 /**
2402  * DPDK callback to register the virtual device.
2403  *
2404  * @param vdev
2405  *   Pointer to the virtual device.
2406  *
2407  * @return
2408  *   0 on success, negative error value otherwise.
2409  */
2410 static int
2411 rte_pmd_mrvl_probe(struct rte_vdev_device *vdev)
2412 {
2413         struct rte_kvargs *kvlist;
2414         struct mrvl_ifnames ifnames;
2415         int ret = -EINVAL;
2416         uint32_t i, ifnum, cfgnum;
2417         const char *params;
2418
2419         params = rte_vdev_device_args(vdev);
2420         if (!params)
2421                 return -EINVAL;
2422
2423         kvlist = rte_kvargs_parse(params, valid_args);
2424         if (!kvlist)
2425                 return -EINVAL;
2426
2427         ifnum = rte_kvargs_count(kvlist, MRVL_IFACE_NAME_ARG);
2428         if (ifnum > RTE_DIM(ifnames.names))
2429                 goto out_free_kvlist;
2430
2431         ifnames.idx = 0;
2432         rte_kvargs_process(kvlist, MRVL_IFACE_NAME_ARG,
2433                            mrvl_get_ifnames, &ifnames);
2434
2435
2436         /*
2437          * The below system initialization should be done only once,
2438          * on the first provided configuration file
2439          */
2440         if (!mrvl_qos_cfg) {
2441                 cfgnum = rte_kvargs_count(kvlist, MRVL_CFG_ARG);
2442                 RTE_LOG(INFO, PMD, "Parsing config file!\n");
2443                 if (cfgnum > 1) {
2444                         RTE_LOG(ERR, PMD, "Cannot handle more than one config file!\n");
2445                         goto out_free_kvlist;
2446                 } else if (cfgnum == 1) {
2447                         rte_kvargs_process(kvlist, MRVL_CFG_ARG,
2448                                            mrvl_get_qoscfg, &mrvl_qos_cfg);
2449                 }
2450         }
2451
2452         if (mrvl_dev_num)
2453                 goto init_devices;
2454
2455         RTE_LOG(INFO, PMD, "Perform MUSDK initializations\n");
2456         /*
2457          * ret == -EEXIST is correct, it means DMA
2458          * has been already initialized (by another PMD).
2459          */
2460         ret = mv_sys_dma_mem_init(MRVL_MUSDK_DMA_MEMSIZE);
2461         if (ret < 0) {
2462                 if (ret != -EEXIST)
2463                         goto out_free_kvlist;
2464                 else
2465                         RTE_LOG(INFO, PMD,
2466                                 "DMA memory has been already initialized by a different driver.\n");
2467         }
2468
2469         ret = mrvl_init_pp2();
2470         if (ret) {
2471                 RTE_LOG(ERR, PMD, "Failed to init PP!\n");
2472                 goto out_deinit_dma;
2473         }
2474
2475         memset(mrvl_port_bpool_size, 0, sizeof(mrvl_port_bpool_size));
2476         memset(mrvl_port_to_bpool_lookup, 0, sizeof(mrvl_port_to_bpool_lookup));
2477
2478         mrvl_lcore_first = RTE_MAX_LCORE;
2479         mrvl_lcore_last = 0;
2480
2481 init_devices:
2482         for (i = 0; i < ifnum; i++) {
2483                 RTE_LOG(INFO, PMD, "Creating %s\n", ifnames.names[i]);
2484                 ret = mrvl_eth_dev_create(vdev, ifnames.names[i]);
2485                 if (ret)
2486                         goto out_cleanup;
2487         }
2488         mrvl_dev_num += ifnum;
2489
2490         rte_kvargs_free(kvlist);
2491
2492         return 0;
2493 out_cleanup:
2494         for (; i > 0; i--)
2495                 mrvl_eth_dev_destroy(ifnames.names[i]);
2496
2497         if (mrvl_dev_num == 0)
2498                 mrvl_deinit_pp2();
2499 out_deinit_dma:
2500         if (mrvl_dev_num == 0)
2501                 mv_sys_dma_mem_destroy();
2502 out_free_kvlist:
2503         rte_kvargs_free(kvlist);
2504
2505         return ret;
2506 }
2507
2508 /**
2509  * DPDK callback to remove virtual device.
2510  *
2511  * @param vdev
2512  *   Pointer to the removed virtual device.
2513  *
2514  * @return
2515  *   0 on success, negative error value otherwise.
2516  */
2517 static int
2518 rte_pmd_mrvl_remove(struct rte_vdev_device *vdev)
2519 {
2520         int i;
2521         const char *name;
2522
2523         name = rte_vdev_device_name(vdev);
2524         if (!name)
2525                 return -EINVAL;
2526
2527         RTE_LOG(INFO, PMD, "Removing %s\n", name);
2528
2529         for (i = 0; i < rte_eth_dev_count(); i++) {
2530                 char ifname[RTE_ETH_NAME_MAX_LEN];
2531
2532                 rte_eth_dev_get_name_by_port(i, ifname);
2533                 mrvl_eth_dev_destroy(ifname);
2534                 mrvl_dev_num--;
2535         }
2536
2537         if (mrvl_dev_num == 0) {
2538                 RTE_LOG(INFO, PMD, "Perform MUSDK deinit\n");
2539                 mrvl_deinit_hifs();
2540                 mrvl_deinit_pp2();
2541                 mv_sys_dma_mem_destroy();
2542         }
2543
2544         return 0;
2545 }
2546
2547 static struct rte_vdev_driver pmd_mrvl_drv = {
2548         .probe = rte_pmd_mrvl_probe,
2549         .remove = rte_pmd_mrvl_remove,
2550 };
2551
2552 RTE_PMD_REGISTER_VDEV(net_mrvl, pmd_mrvl_drv);
2553 RTE_PMD_REGISTER_ALIAS(net_mrvl, eth_mrvl);