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33 #include <rte_ethdev.h>
34 #include <rte_kvargs.h>
36 #include <rte_malloc.h>
39 /* Unluckily, container_of is defined by both DPDK and MUSDK,
40 * we'll declare only one version.
42 * Note that it is not used in this PMD anyway.
48 #include <drivers/mv_pp2.h>
49 #include <drivers/mv_pp2_bpool.h>
50 #include <drivers/mv_pp2_hif.h>
53 #include <linux/ethtool.h>
54 #include <linux/sockios.h>
56 #include <net/if_arp.h>
57 #include <sys/ioctl.h>
58 #include <sys/socket.h>
60 #include <sys/types.h>
62 #include "mrvl_ethdev.h"
65 /* bitmask with reserved hifs */
66 #define MRVL_MUSDK_HIFS_RESERVED 0x0F
67 /* bitmask with reserved bpools */
68 #define MRVL_MUSDK_BPOOLS_RESERVED 0x07
69 /* bitmask with reserved kernel RSS tables */
70 #define MRVL_MUSDK_RSS_RESERVED 0x01
71 /* maximum number of available hifs */
72 #define MRVL_MUSDK_HIFS_MAX 9
75 #define MRVL_MUSDK_PREFETCH_SHIFT 2
77 /* TCAM has 25 entries reserved for uc/mc filter entries */
78 #define MRVL_MAC_ADDRS_MAX 25
79 #define MRVL_MATCH_LEN 16
80 #define MRVL_PKT_EFFEC_OFFS (MRVL_PKT_OFFS + MV_MH_SIZE)
81 /* Maximum allowable packet size */
82 #define MRVL_PKT_SIZE_MAX (10240 - MV_MH_SIZE)
84 #define MRVL_IFACE_NAME_ARG "iface"
85 #define MRVL_CFG_ARG "cfg"
87 #define MRVL_BURST_SIZE 64
89 #define MRVL_ARP_LENGTH 28
91 #define MRVL_COOKIE_ADDR_INVALID ~0ULL
93 #define MRVL_COOKIE_HIGH_ADDR_SHIFT (sizeof(pp2_cookie_t) * 8)
94 #define MRVL_COOKIE_HIGH_ADDR_MASK (~0ULL << MRVL_COOKIE_HIGH_ADDR_SHIFT)
96 static const char * const valid_args[] = {
102 static int used_hifs = MRVL_MUSDK_HIFS_RESERVED;
103 static struct pp2_hif *hifs[RTE_MAX_LCORE];
104 static int used_bpools[PP2_NUM_PKT_PROC] = {
105 MRVL_MUSDK_BPOOLS_RESERVED,
106 MRVL_MUSDK_BPOOLS_RESERVED
109 struct pp2_bpool *mrvl_port_to_bpool_lookup[RTE_MAX_ETHPORTS];
110 int mrvl_port_bpool_size[PP2_NUM_PKT_PROC][PP2_BPOOL_NUM_POOLS][RTE_MAX_LCORE];
111 uint64_t cookie_addr_high = MRVL_COOKIE_ADDR_INVALID;
114 * To use buffer harvesting based on loopback port shadow queue structure
115 * was introduced for buffers information bookkeeping.
117 * Before sending the packet, related buffer information (pp2_buff_inf) is
118 * stored in shadow queue. After packet is transmitted no longer used
119 * packet buffer is released back to it's original hardware pool,
120 * on condition it originated from interface.
121 * In case it was generated by application itself i.e: mbuf->port field is
122 * 0xff then its released to software mempool.
124 struct mrvl_shadow_txq {
125 int head; /* write index - used when sending buffers */
126 int tail; /* read index - used when releasing buffers */
127 u16 size; /* queue occupied size */
128 u16 num_to_release; /* number of buffers sent, that can be released */
129 struct buff_release_entry ent[MRVL_PP2_TX_SHADOWQ_SIZE]; /* q entries */
133 struct mrvl_priv *priv;
134 struct rte_mempool *mp;
140 struct mrvl_priv *priv;
146 * Every tx queue should have dedicated shadow tx queue.
148 * Ports assigned by DPDK might not start at zero or be continuous so
149 * as a workaround define shadow queues for each possible port so that
150 * we eventually fit somewhere.
152 struct mrvl_shadow_txq shadow_txqs[RTE_MAX_ETHPORTS][RTE_MAX_LCORE];
154 /** Number of ports configured. */
156 static int mrvl_lcore_first;
157 static int mrvl_lcore_last;
160 mrvl_get_bpool_size(int pp2_id, int pool_id)
165 for (i = mrvl_lcore_first; i <= mrvl_lcore_last; i++)
166 size += mrvl_port_bpool_size[pp2_id][pool_id][i];
172 mrvl_reserve_bit(int *bitmap, int max)
174 int n = sizeof(*bitmap) * 8 - __builtin_clz(*bitmap);
185 * Configure rss based on dpdk rss configuration.
188 * Pointer to private structure.
190 * Pointer to RSS configuration.
193 * 0 on success, negative error value otherwise.
196 mrvl_configure_rss(struct mrvl_priv *priv, struct rte_eth_rss_conf *rss_conf)
198 if (rss_conf->rss_key)
199 RTE_LOG(WARNING, PMD, "Changing hash key is not supported\n");
201 if (rss_conf->rss_hf == 0) {
202 priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE;
203 } else if (rss_conf->rss_hf & ETH_RSS_IPV4) {
204 priv->ppio_params.inqs_params.hash_type =
205 PP2_PPIO_HASH_T_2_TUPLE;
206 } else if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) {
207 priv->ppio_params.inqs_params.hash_type =
208 PP2_PPIO_HASH_T_5_TUPLE;
209 priv->rss_hf_tcp = 1;
210 } else if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) {
211 priv->ppio_params.inqs_params.hash_type =
212 PP2_PPIO_HASH_T_5_TUPLE;
213 priv->rss_hf_tcp = 0;
222 * Ethernet device configuration.
224 * Prepare the driver for a given number of TX and RX queues and
228 * Pointer to Ethernet device structure.
231 * 0 on success, negative error value otherwise.
234 mrvl_dev_configure(struct rte_eth_dev *dev)
236 struct mrvl_priv *priv = dev->data->dev_private;
239 if (dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_NONE &&
240 dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) {
241 RTE_LOG(INFO, PMD, "Unsupported rx multi queue mode %d\n",
242 dev->data->dev_conf.rxmode.mq_mode);
246 if (!dev->data->dev_conf.rxmode.hw_strip_crc) {
248 "L2 CRC stripping is always enabled in hw\n");
249 dev->data->dev_conf.rxmode.hw_strip_crc = 1;
252 if (dev->data->dev_conf.rxmode.hw_vlan_strip) {
253 RTE_LOG(INFO, PMD, "VLAN stripping not supported\n");
257 if (dev->data->dev_conf.rxmode.split_hdr_size) {
258 RTE_LOG(INFO, PMD, "Split headers not supported\n");
262 if (dev->data->dev_conf.rxmode.enable_scatter) {
263 RTE_LOG(INFO, PMD, "RX Scatter/Gather not supported\n");
267 if (dev->data->dev_conf.rxmode.enable_lro) {
268 RTE_LOG(INFO, PMD, "LRO not supported\n");
272 if (dev->data->dev_conf.rxmode.jumbo_frame)
273 dev->data->mtu = dev->data->dev_conf.rxmode.max_rx_pkt_len -
274 ETHER_HDR_LEN - ETHER_CRC_LEN;
276 ret = mrvl_configure_rxqs(priv, dev->data->port_id,
277 dev->data->nb_rx_queues);
281 priv->ppio_params.outqs_params.num_outqs = dev->data->nb_tx_queues;
282 priv->nb_rx_queues = dev->data->nb_rx_queues;
284 if (dev->data->nb_rx_queues == 1 &&
285 dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) {
286 RTE_LOG(WARNING, PMD, "Disabling hash for 1 rx queue\n");
287 priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE;
292 return mrvl_configure_rss(priv,
293 &dev->data->dev_conf.rx_adv_conf.rss_conf);
297 * DPDK callback to change the MTU.
299 * Setting the MTU affects hardware MRU (packets larger than the MRU
303 * Pointer to Ethernet device structure.
308 * 0 on success, negative error value otherwise.
311 mrvl_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
313 struct mrvl_priv *priv = dev->data->dev_private;
314 /* extra MV_MH_SIZE bytes are required for Marvell tag */
315 uint16_t mru = mtu + MV_MH_SIZE + ETHER_HDR_LEN + ETHER_CRC_LEN;
318 if (mtu < ETHER_MIN_MTU || mru > MRVL_PKT_SIZE_MAX)
321 ret = pp2_ppio_set_mru(priv->ppio, mru);
325 return pp2_ppio_set_mtu(priv->ppio, mtu);
329 * DPDK callback to bring the link up.
332 * Pointer to Ethernet device structure.
335 * 0 on success, negative error value otherwise.
338 mrvl_dev_set_link_up(struct rte_eth_dev *dev)
340 struct mrvl_priv *priv = dev->data->dev_private;
343 ret = pp2_ppio_enable(priv->ppio);
348 * mtu/mru can be updated if pp2_ppio_enable() was called at least once
349 * as pp2_ppio_enable() changes port->t_mode from default 0 to
350 * PP2_TRAFFIC_INGRESS_EGRESS.
352 * Set mtu to default DPDK value here.
354 ret = mrvl_mtu_set(dev, dev->data->mtu);
356 pp2_ppio_disable(priv->ppio);
358 dev->data->dev_link.link_status = ETH_LINK_UP;
364 * DPDK callback to bring the link down.
367 * Pointer to Ethernet device structure.
370 * 0 on success, negative error value otherwise.
373 mrvl_dev_set_link_down(struct rte_eth_dev *dev)
375 struct mrvl_priv *priv = dev->data->dev_private;
378 ret = pp2_ppio_disable(priv->ppio);
382 dev->data->dev_link.link_status = ETH_LINK_DOWN;
388 * DPDK callback to start the device.
391 * Pointer to Ethernet device structure.
394 * 0 on success, negative errno value on failure.
397 mrvl_dev_start(struct rte_eth_dev *dev)
399 struct mrvl_priv *priv = dev->data->dev_private;
400 char match[MRVL_MATCH_LEN];
403 snprintf(match, sizeof(match), "ppio-%d:%d",
404 priv->pp_id, priv->ppio_id);
405 priv->ppio_params.match = match;
408 * Calculate the maximum bpool size for refill feature to 1.5 of the
409 * configured size. In case the bpool size will exceed this value,
410 * superfluous buffers will be removed
412 priv->bpool_max_size = priv->bpool_init_size +
413 (priv->bpool_init_size >> 1);
415 * Calculate the minimum bpool size for refill feature as follows:
416 * 2 default burst sizes multiply by number of rx queues.
417 * If the bpool size will be below this value, new buffers will
418 * be added to the pool.
420 priv->bpool_min_size = priv->nb_rx_queues * MRVL_BURST_SIZE * 2;
422 ret = pp2_ppio_init(&priv->ppio_params, &priv->ppio);
427 * In case there are some some stale uc/mc mac addresses flush them
428 * here. It cannot be done during mrvl_dev_close() as port information
429 * is already gone at that point (due to pp2_ppio_deinit() in
432 if (!priv->uc_mc_flushed) {
433 ret = pp2_ppio_flush_mac_addrs(priv->ppio, 1, 1);
436 "Failed to flush uc/mc filter list\n");
439 priv->uc_mc_flushed = 1;
442 if (!priv->vlan_flushed) {
443 ret = pp2_ppio_flush_vlan(priv->ppio);
445 RTE_LOG(ERR, PMD, "Failed to flush vlan list\n");
448 * once pp2_ppio_flush_vlan() is supported jump to out
452 priv->vlan_flushed = 1;
455 /* For default QoS config, don't start classifier. */
457 ret = mrvl_start_qos_mapping(priv);
459 pp2_ppio_deinit(priv->ppio);
464 ret = mrvl_dev_set_link_up(dev);
470 pp2_ppio_deinit(priv->ppio);
475 * Flush receive queues.
478 * Pointer to Ethernet device structure.
481 mrvl_flush_rx_queues(struct rte_eth_dev *dev)
485 RTE_LOG(INFO, PMD, "Flushing rx queues\n");
486 for (i = 0; i < dev->data->nb_rx_queues; i++) {
490 struct mrvl_rxq *q = dev->data->rx_queues[i];
491 struct pp2_ppio_desc descs[MRVL_PP2_RXD_MAX];
493 num = MRVL_PP2_RXD_MAX;
494 ret = pp2_ppio_recv(q->priv->ppio,
495 q->priv->rxq_map[q->queue_id].tc,
496 q->priv->rxq_map[q->queue_id].inq,
497 descs, (uint16_t *)&num);
498 } while (ret == 0 && num);
503 * Flush transmit shadow queues.
506 * Pointer to Ethernet device structure.
509 mrvl_flush_tx_shadow_queues(struct rte_eth_dev *dev)
513 RTE_LOG(INFO, PMD, "Flushing tx shadow queues\n");
514 for (i = 0; i < RTE_MAX_LCORE; i++) {
515 struct mrvl_shadow_txq *sq =
516 &shadow_txqs[dev->data->port_id][i];
518 while (sq->tail != sq->head) {
519 uint64_t addr = cookie_addr_high |
520 sq->ent[sq->tail].buff.cookie;
521 rte_pktmbuf_free((struct rte_mbuf *)addr);
522 sq->tail = (sq->tail + 1) & MRVL_PP2_TX_SHADOWQ_MASK;
525 memset(sq, 0, sizeof(*sq));
530 * Flush hardware bpool (buffer-pool).
533 * Pointer to Ethernet device structure.
536 mrvl_flush_bpool(struct rte_eth_dev *dev)
538 struct mrvl_priv *priv = dev->data->dev_private;
542 ret = pp2_bpool_get_num_buffs(priv->bpool, &num);
544 RTE_LOG(ERR, PMD, "Failed to get bpool buffers number\n");
549 struct pp2_buff_inf inf;
552 ret = pp2_bpool_get_buff(hifs[rte_lcore_id()], priv->bpool,
557 addr = cookie_addr_high | inf.cookie;
558 rte_pktmbuf_free((struct rte_mbuf *)addr);
563 * DPDK callback to stop the device.
566 * Pointer to Ethernet device structure.
569 mrvl_dev_stop(struct rte_eth_dev *dev)
571 struct mrvl_priv *priv = dev->data->dev_private;
573 mrvl_dev_set_link_down(dev);
574 mrvl_flush_rx_queues(dev);
575 mrvl_flush_tx_shadow_queues(dev);
577 pp2_cls_qos_tbl_deinit(priv->qos_tbl);
578 pp2_ppio_deinit(priv->ppio);
583 * DPDK callback to close the device.
586 * Pointer to Ethernet device structure.
589 mrvl_dev_close(struct rte_eth_dev *dev)
591 struct mrvl_priv *priv = dev->data->dev_private;
594 for (i = 0; i < priv->ppio_params.inqs_params.num_tcs; ++i) {
595 struct pp2_ppio_tc_params *tc_params =
596 &priv->ppio_params.inqs_params.tcs_params[i];
598 if (tc_params->inqs_params) {
599 rte_free(tc_params->inqs_params);
600 tc_params->inqs_params = NULL;
604 mrvl_flush_bpool(dev);
608 * DPDK callback to retrieve physical link information.
611 * Pointer to Ethernet device structure.
612 * @param wait_to_complete
613 * Wait for request completion (ignored).
616 * 0 on success, negative error value otherwise.
619 mrvl_link_update(struct rte_eth_dev *dev, int wait_to_complete __rte_unused)
623 * once MUSDK provides necessary API use it here
625 struct ethtool_cmd edata;
629 edata.cmd = ETHTOOL_GSET;
631 strcpy(req.ifr_name, dev->data->name);
632 req.ifr_data = (void *)&edata;
634 fd = socket(AF_INET, SOCK_DGRAM, 0);
638 ret = ioctl(fd, SIOCETHTOOL, &req);
646 switch (ethtool_cmd_speed(&edata)) {
648 dev->data->dev_link.link_speed = ETH_SPEED_NUM_10M;
651 dev->data->dev_link.link_speed = ETH_SPEED_NUM_100M;
654 dev->data->dev_link.link_speed = ETH_SPEED_NUM_1G;
657 dev->data->dev_link.link_speed = ETH_SPEED_NUM_10G;
660 dev->data->dev_link.link_speed = ETH_SPEED_NUM_NONE;
663 dev->data->dev_link.link_duplex = edata.duplex ? ETH_LINK_FULL_DUPLEX :
664 ETH_LINK_HALF_DUPLEX;
665 dev->data->dev_link.link_autoneg = edata.autoneg ? ETH_LINK_AUTONEG :
672 * DPDK callback to enable promiscuous mode.
675 * Pointer to Ethernet device structure.
678 mrvl_promiscuous_enable(struct rte_eth_dev *dev)
680 struct mrvl_priv *priv = dev->data->dev_private;
683 ret = pp2_ppio_set_uc_promisc(priv->ppio, 1);
685 RTE_LOG(ERR, PMD, "Failed to enable promiscuous mode\n");
689 * DPDK callback to enable allmulti mode.
692 * Pointer to Ethernet device structure.
695 mrvl_allmulticast_enable(struct rte_eth_dev *dev)
697 struct mrvl_priv *priv = dev->data->dev_private;
700 ret = pp2_ppio_set_mc_promisc(priv->ppio, 1);
702 RTE_LOG(ERR, PMD, "Failed enable all-multicast mode\n");
706 * DPDK callback to disable promiscuous mode.
709 * Pointer to Ethernet device structure.
712 mrvl_promiscuous_disable(struct rte_eth_dev *dev)
714 struct mrvl_priv *priv = dev->data->dev_private;
717 ret = pp2_ppio_set_uc_promisc(priv->ppio, 0);
719 RTE_LOG(ERR, PMD, "Failed to disable promiscuous mode\n");
723 * DPDK callback to disable allmulticast mode.
726 * Pointer to Ethernet device structure.
729 mrvl_allmulticast_disable(struct rte_eth_dev *dev)
731 struct mrvl_priv *priv = dev->data->dev_private;
734 ret = pp2_ppio_set_mc_promisc(priv->ppio, 0);
736 RTE_LOG(ERR, PMD, "Failed to disable all-multicast mode\n");
740 * DPDK callback to remove a MAC address.
743 * Pointer to Ethernet device structure.
748 mrvl_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index)
750 struct mrvl_priv *priv = dev->data->dev_private;
751 char buf[ETHER_ADDR_FMT_SIZE];
754 ret = pp2_ppio_remove_mac_addr(priv->ppio,
755 dev->data->mac_addrs[index].addr_bytes);
757 ether_format_addr(buf, sizeof(buf),
758 &dev->data->mac_addrs[index]);
759 RTE_LOG(ERR, PMD, "Failed to remove mac %s\n", buf);
764 * DPDK callback to add a MAC address.
767 * Pointer to Ethernet device structure.
769 * MAC address to register.
773 * VMDq pool index to associate address with (unused).
776 * 0 on success, negative error value otherwise.
779 mrvl_mac_addr_add(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
780 uint32_t index, uint32_t vmdq __rte_unused)
782 struct mrvl_priv *priv = dev->data->dev_private;
783 char buf[ETHER_ADDR_FMT_SIZE];
787 /* For setting index 0, mrvl_mac_addr_set() should be used.*/
791 * Maximum number of uc addresses can be tuned via kernel module mvpp2x
792 * parameter uc_filter_max. Maximum number of mc addresses is then
793 * MRVL_MAC_ADDRS_MAX - uc_filter_max. Currently it defaults to 4 and
796 * If more than uc_filter_max uc addresses were added to filter list
797 * then NIC will switch to promiscuous mode automatically.
799 * If more than MRVL_MAC_ADDRS_MAX - uc_filter_max number mc addresses
800 * were added to filter list then NIC will switch to all-multicast mode
803 ret = pp2_ppio_add_mac_addr(priv->ppio, mac_addr->addr_bytes);
805 ether_format_addr(buf, sizeof(buf), mac_addr);
806 RTE_LOG(ERR, PMD, "Failed to add mac %s\n", buf);
814 * DPDK callback to set the primary MAC address.
817 * Pointer to Ethernet device structure.
819 * MAC address to register.
822 mrvl_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr)
824 struct mrvl_priv *priv = dev->data->dev_private;
826 pp2_ppio_set_mac_addr(priv->ppio, mac_addr->addr_bytes);
829 * Port stops sending packets if pp2_ppio_set_mac_addr()
830 * was called after pp2_ppio_enable(). As a quick fix issue
831 * enable port once again.
833 pp2_ppio_enable(priv->ppio);
837 * DPDK callback to get information about the device.
840 * Pointer to Ethernet device structure (unused).
842 * Info structure output buffer.
845 mrvl_dev_infos_get(struct rte_eth_dev *dev __rte_unused,
846 struct rte_eth_dev_info *info)
848 info->speed_capa = ETH_LINK_SPEED_10M |
849 ETH_LINK_SPEED_100M |
853 info->max_rx_queues = MRVL_PP2_RXQ_MAX;
854 info->max_tx_queues = MRVL_PP2_TXQ_MAX;
855 info->max_mac_addrs = MRVL_MAC_ADDRS_MAX;
857 info->rx_desc_lim.nb_max = MRVL_PP2_RXD_MAX;
858 info->rx_desc_lim.nb_min = MRVL_PP2_RXD_MIN;
859 info->rx_desc_lim.nb_align = MRVL_PP2_RXD_ALIGN;
861 info->tx_desc_lim.nb_max = MRVL_PP2_TXD_MAX;
862 info->tx_desc_lim.nb_min = MRVL_PP2_TXD_MIN;
863 info->tx_desc_lim.nb_align = MRVL_PP2_TXD_ALIGN;
865 info->rx_offload_capa = DEV_RX_OFFLOAD_JUMBO_FRAME |
866 DEV_RX_OFFLOAD_VLAN_FILTER;
867 info->flow_type_rss_offloads = ETH_RSS_IPV4 |
868 ETH_RSS_NONFRAG_IPV4_TCP |
869 ETH_RSS_NONFRAG_IPV4_UDP;
871 /* By default packets are dropped if no descriptors are available */
872 info->default_rxconf.rx_drop_en = 1;
874 info->max_rx_pktlen = MRVL_PKT_SIZE_MAX;
878 * DPDK callback to get information about specific receive queue.
881 * Pointer to Ethernet device structure.
883 * Receive queue index.
885 * Receive queue information structure.
887 static void mrvl_rxq_info_get(struct rte_eth_dev *dev, uint16_t rx_queue_id,
888 struct rte_eth_rxq_info *qinfo)
890 struct mrvl_rxq *q = dev->data->rx_queues[rx_queue_id];
891 struct mrvl_priv *priv = dev->data->dev_private;
892 int inq = priv->rxq_map[rx_queue_id].inq;
893 int tc = priv->rxq_map[rx_queue_id].tc;
894 struct pp2_ppio_tc_params *tc_params =
895 &priv->ppio_params.inqs_params.tcs_params[tc];
898 qinfo->nb_desc = tc_params->inqs_params[inq].size;
902 * DPDK callback to get information about specific transmit queue.
905 * Pointer to Ethernet device structure.
907 * Transmit queue index.
909 * Transmit queue information structure.
911 static void mrvl_txq_info_get(struct rte_eth_dev *dev, uint16_t tx_queue_id,
912 struct rte_eth_txq_info *qinfo)
914 struct mrvl_priv *priv = dev->data->dev_private;
917 priv->ppio_params.outqs_params.outqs_params[tx_queue_id].size;
921 * DPDK callback to Configure a VLAN filter.
924 * Pointer to Ethernet device structure.
931 * 0 on success, negative error value otherwise.
934 mrvl_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
936 struct mrvl_priv *priv = dev->data->dev_private;
938 return on ? pp2_ppio_add_vlan(priv->ppio, vlan_id) :
939 pp2_ppio_remove_vlan(priv->ppio, vlan_id);
943 * Release buffers to hardware bpool (buffer-pool)
946 * Receive queue pointer.
948 * Number of buffers to release to bpool.
951 * 0 on success, negative error value otherwise.
954 mrvl_fill_bpool(struct mrvl_rxq *rxq, int num)
956 struct buff_release_entry entries[MRVL_PP2_TXD_MAX];
957 struct rte_mbuf *mbufs[MRVL_PP2_TXD_MAX];
959 unsigned int core_id = rte_lcore_id();
960 struct pp2_hif *hif = hifs[core_id];
961 struct pp2_bpool *bpool = rxq->priv->bpool;
963 ret = rte_pktmbuf_alloc_bulk(rxq->mp, mbufs, num);
967 if (cookie_addr_high == MRVL_COOKIE_ADDR_INVALID)
969 (uint64_t)mbufs[0] & MRVL_COOKIE_HIGH_ADDR_MASK;
971 for (i = 0; i < num; i++) {
972 if (((uint64_t)mbufs[i] & MRVL_COOKIE_HIGH_ADDR_MASK)
973 != cookie_addr_high) {
975 "mbuf virtual addr high 0x%lx out of range\n",
976 (uint64_t)mbufs[i] >> 32);
980 entries[i].buff.addr =
981 rte_mbuf_data_dma_addr_default(mbufs[i]);
982 entries[i].buff.cookie = (pp2_cookie_t)(uint64_t)mbufs[i];
983 entries[i].bpool = bpool;
986 pp2_bpool_put_buffs(hif, entries, (uint16_t *)&i);
987 mrvl_port_bpool_size[bpool->pp2_id][bpool->id][core_id] += i;
995 rte_pktmbuf_free(mbufs[i]);
1001 * DPDK callback to configure the receive queue.
1004 * Pointer to Ethernet device structure.
1008 * Number of descriptors to configure in queue.
1010 * NUMA socket on which memory must be allocated.
1012 * Thresholds parameters (unused_).
1014 * Memory pool for buffer allocations.
1017 * 0 on success, negative error value otherwise.
1020 mrvl_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1021 unsigned int socket,
1022 const struct rte_eth_rxconf *conf __rte_unused,
1023 struct rte_mempool *mp)
1025 struct mrvl_priv *priv = dev->data->dev_private;
1026 struct mrvl_rxq *rxq;
1028 max_rx_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
1031 if (priv->rxq_map[idx].tc == MRVL_UNKNOWN_TC) {
1033 * Unknown TC mapping, mapping will not have a correct queue.
1035 RTE_LOG(ERR, PMD, "Unknown TC mapping for queue %hu eth%hhu\n",
1036 idx, priv->ppio_id);
1040 min_size = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM -
1041 MRVL_PKT_EFFEC_OFFS;
1042 if (min_size < max_rx_pkt_len) {
1044 "Mbuf size must be increased to %u bytes to hold up to %u bytes of data.\n",
1045 max_rx_pkt_len + RTE_PKTMBUF_HEADROOM +
1046 MRVL_PKT_EFFEC_OFFS,
1051 if (dev->data->rx_queues[idx]) {
1052 rte_free(dev->data->rx_queues[idx]);
1053 dev->data->rx_queues[idx] = NULL;
1056 rxq = rte_zmalloc_socket("rxq", sizeof(*rxq), 0, socket);
1062 rxq->queue_id = idx;
1063 rxq->port_id = dev->data->port_id;
1064 mrvl_port_to_bpool_lookup[rxq->port_id] = priv->bpool;
1066 tc = priv->rxq_map[rxq->queue_id].tc,
1067 inq = priv->rxq_map[rxq->queue_id].inq;
1068 priv->ppio_params.inqs_params.tcs_params[tc].inqs_params[inq].size =
1071 ret = mrvl_fill_bpool(rxq, desc);
1077 priv->bpool_init_size += desc;
1079 dev->data->rx_queues[idx] = rxq;
1085 * DPDK callback to release the receive queue.
1088 * Generic receive queue pointer.
1091 mrvl_rx_queue_release(void *rxq)
1093 struct mrvl_rxq *q = rxq;
1094 struct pp2_ppio_tc_params *tc_params;
1095 int i, num, tc, inq;
1100 tc = q->priv->rxq_map[q->queue_id].tc;
1101 inq = q->priv->rxq_map[q->queue_id].inq;
1102 tc_params = &q->priv->ppio_params.inqs_params.tcs_params[tc];
1103 num = tc_params->inqs_params[inq].size;
1104 for (i = 0; i < num; i++) {
1105 struct pp2_buff_inf inf;
1108 pp2_bpool_get_buff(hifs[rte_lcore_id()], q->priv->bpool, &inf);
1109 addr = cookie_addr_high | inf.cookie;
1110 rte_pktmbuf_free((struct rte_mbuf *)addr);
1117 * DPDK callback to configure the transmit queue.
1120 * Pointer to Ethernet device structure.
1122 * Transmit queue index.
1124 * Number of descriptors to configure in the queue.
1126 * NUMA socket on which memory must be allocated.
1128 * Thresholds parameters (unused).
1131 * 0 on success, negative error value otherwise.
1134 mrvl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1135 unsigned int socket,
1136 const struct rte_eth_txconf *conf __rte_unused)
1138 struct mrvl_priv *priv = dev->data->dev_private;
1139 struct mrvl_txq *txq;
1141 if (dev->data->tx_queues[idx]) {
1142 rte_free(dev->data->tx_queues[idx]);
1143 dev->data->tx_queues[idx] = NULL;
1146 txq = rte_zmalloc_socket("txq", sizeof(*txq), 0, socket);
1151 txq->queue_id = idx;
1152 txq->port_id = dev->data->port_id;
1153 dev->data->tx_queues[idx] = txq;
1155 priv->ppio_params.outqs_params.outqs_params[idx].size = desc;
1156 priv->ppio_params.outqs_params.outqs_params[idx].weight = 1;
1162 * DPDK callback to release the transmit queue.
1165 * Generic transmit queue pointer.
1168 mrvl_tx_queue_release(void *txq)
1170 struct mrvl_txq *q = txq;
1179 * Update RSS hash configuration
1182 * Pointer to Ethernet device structure.
1184 * Pointer to RSS configuration.
1187 * 0 on success, negative error value otherwise.
1190 mrvl_rss_hash_update(struct rte_eth_dev *dev,
1191 struct rte_eth_rss_conf *rss_conf)
1193 struct mrvl_priv *priv = dev->data->dev_private;
1195 return mrvl_configure_rss(priv, rss_conf);
1199 * DPDK callback to get RSS hash configuration.
1202 * Pointer to Ethernet device structure.
1204 * Pointer to RSS configuration.
1210 mrvl_rss_hash_conf_get(struct rte_eth_dev *dev,
1211 struct rte_eth_rss_conf *rss_conf)
1213 struct mrvl_priv *priv = dev->data->dev_private;
1214 enum pp2_ppio_hash_type hash_type =
1215 priv->ppio_params.inqs_params.hash_type;
1217 rss_conf->rss_key = NULL;
1219 if (hash_type == PP2_PPIO_HASH_T_NONE)
1220 rss_conf->rss_hf = 0;
1221 else if (hash_type == PP2_PPIO_HASH_T_2_TUPLE)
1222 rss_conf->rss_hf = ETH_RSS_IPV4;
1223 else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && priv->rss_hf_tcp)
1224 rss_conf->rss_hf = ETH_RSS_NONFRAG_IPV4_TCP;
1225 else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && !priv->rss_hf_tcp)
1226 rss_conf->rss_hf = ETH_RSS_NONFRAG_IPV4_UDP;
1231 static const struct eth_dev_ops mrvl_ops = {
1232 .dev_configure = mrvl_dev_configure,
1233 .dev_start = mrvl_dev_start,
1234 .dev_stop = mrvl_dev_stop,
1235 .dev_set_link_up = mrvl_dev_set_link_up,
1236 .dev_set_link_down = mrvl_dev_set_link_down,
1237 .dev_close = mrvl_dev_close,
1238 .link_update = mrvl_link_update,
1239 .promiscuous_enable = mrvl_promiscuous_enable,
1240 .allmulticast_enable = mrvl_allmulticast_enable,
1241 .promiscuous_disable = mrvl_promiscuous_disable,
1242 .allmulticast_disable = mrvl_allmulticast_disable,
1243 .mac_addr_remove = mrvl_mac_addr_remove,
1244 .mac_addr_add = mrvl_mac_addr_add,
1245 .mac_addr_set = mrvl_mac_addr_set,
1246 .mtu_set = mrvl_mtu_set,
1247 .dev_infos_get = mrvl_dev_infos_get,
1248 .rxq_info_get = mrvl_rxq_info_get,
1249 .txq_info_get = mrvl_txq_info_get,
1250 .vlan_filter_set = mrvl_vlan_filter_set,
1251 .rx_queue_setup = mrvl_rx_queue_setup,
1252 .rx_queue_release = mrvl_rx_queue_release,
1253 .tx_queue_setup = mrvl_tx_queue_setup,
1254 .tx_queue_release = mrvl_tx_queue_release,
1255 .rss_hash_update = mrvl_rss_hash_update,
1256 .rss_hash_conf_get = mrvl_rss_hash_conf_get,
1260 * DPDK callback for receive.
1263 * Generic pointer to the receive queue.
1265 * Array to store received packets.
1267 * Maximum number of packets in array.
1270 * Number of packets successfully received.
1273 mrvl_rx_pkt_burst(void *rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1275 struct mrvl_rxq *q = rxq;
1276 struct pp2_ppio_desc descs[nb_pkts];
1277 struct pp2_bpool *bpool;
1278 int i, ret, rx_done = 0;
1280 unsigned int core_id = rte_lcore_id();
1282 if (unlikely(!q->priv->ppio))
1285 bpool = q->priv->bpool;
1287 ret = pp2_ppio_recv(q->priv->ppio, q->priv->rxq_map[q->queue_id].tc,
1288 q->priv->rxq_map[q->queue_id].inq, descs, &nb_pkts);
1289 if (unlikely(ret < 0)) {
1290 RTE_LOG(ERR, PMD, "Failed to receive packets\n");
1293 mrvl_port_bpool_size[bpool->pp2_id][bpool->id][core_id] -= nb_pkts;
1295 for (i = 0; i < nb_pkts; i++) {
1296 struct rte_mbuf *mbuf;
1297 enum pp2_inq_desc_status status;
1300 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) {
1301 struct pp2_ppio_desc *pref_desc;
1304 pref_desc = &descs[i + MRVL_MUSDK_PREFETCH_SHIFT];
1305 pref_addr = cookie_addr_high |
1306 pp2_ppio_inq_desc_get_cookie(pref_desc);
1307 rte_mbuf_prefetch_part1((struct rte_mbuf *)(pref_addr));
1308 rte_mbuf_prefetch_part2((struct rte_mbuf *)(pref_addr));
1311 addr = cookie_addr_high |
1312 pp2_ppio_inq_desc_get_cookie(&descs[i]);
1313 mbuf = (struct rte_mbuf *)addr;
1314 rte_pktmbuf_reset(mbuf);
1316 /* drop packet in case of mac, overrun or resource error */
1317 status = pp2_ppio_inq_desc_get_l2_pkt_error(&descs[i]);
1318 if (unlikely(status != PP2_DESC_ERR_OK)) {
1319 struct pp2_buff_inf binf = {
1320 .addr = rte_mbuf_data_dma_addr_default(mbuf),
1321 .cookie = (pp2_cookie_t)(uint64_t)mbuf,
1324 pp2_bpool_put_buff(hifs[core_id], bpool, &binf);
1325 mrvl_port_bpool_size
1326 [bpool->pp2_id][bpool->id][core_id]++;
1330 mbuf->data_off += MRVL_PKT_EFFEC_OFFS;
1331 mbuf->pkt_len = pp2_ppio_inq_desc_get_pkt_len(&descs[i]);
1332 mbuf->data_len = mbuf->pkt_len;
1333 mbuf->port = q->port_id;
1335 rx_pkts[rx_done++] = mbuf;
1338 if (rte_spinlock_trylock(&q->priv->lock) == 1) {
1339 num = mrvl_get_bpool_size(bpool->pp2_id, bpool->id);
1341 if (unlikely(num <= q->priv->bpool_min_size ||
1342 (!rx_done && num < q->priv->bpool_init_size))) {
1343 ret = mrvl_fill_bpool(q, MRVL_BURST_SIZE);
1345 RTE_LOG(ERR, PMD, "Failed to fill bpool\n");
1346 } else if (unlikely(num > q->priv->bpool_max_size)) {
1348 int pkt_to_remove = num - q->priv->bpool_init_size;
1349 struct rte_mbuf *mbuf;
1350 struct pp2_buff_inf buff;
1353 "\nport-%d:%d: bpool %d oversize - remove %d buffers (pool size: %d -> %d)\n",
1354 bpool->pp2_id, q->priv->ppio->port_id,
1355 bpool->id, pkt_to_remove, num,
1356 q->priv->bpool_init_size);
1358 for (i = 0; i < pkt_to_remove; i++) {
1359 pp2_bpool_get_buff(hifs[core_id], bpool, &buff);
1360 mbuf = (struct rte_mbuf *)
1361 (cookie_addr_high | buff.cookie);
1362 rte_pktmbuf_free(mbuf);
1364 mrvl_port_bpool_size
1365 [bpool->pp2_id][bpool->id][core_id] -=
1368 rte_spinlock_unlock(&q->priv->lock);
1375 * Release already sent buffers to bpool (buffer-pool).
1378 * Pointer to the port structure.
1380 * Pointer to the MUSDK hardware interface.
1382 * Pointer to the shadow queue.
1386 * Force releasing packets.
1389 mrvl_free_sent_buffers(struct pp2_ppio *ppio, struct pp2_hif *hif,
1390 struct mrvl_shadow_txq *sq, int qid, int force)
1392 struct buff_release_entry *entry;
1393 uint16_t nb_done = 0, num = 0, skip_bufs = 0;
1394 int i, core_id = rte_lcore_id();
1396 pp2_ppio_get_num_outq_done(ppio, hif, qid, &nb_done);
1398 sq->num_to_release += nb_done;
1400 if (likely(!force &&
1401 sq->num_to_release < MRVL_PP2_BUF_RELEASE_BURST_SIZE))
1404 nb_done = sq->num_to_release;
1405 sq->num_to_release = 0;
1407 for (i = 0; i < nb_done; i++) {
1408 entry = &sq->ent[sq->tail + num];
1409 if (unlikely(!entry->buff.addr)) {
1411 "Shadow memory @%d: cookie(%lx), pa(%lx)!\n",
1412 sq->tail, (u64)entry->buff.cookie,
1413 (u64)entry->buff.addr);
1418 if (unlikely(!entry->bpool)) {
1419 struct rte_mbuf *mbuf;
1421 mbuf = (struct rte_mbuf *)
1422 (cookie_addr_high | entry->buff.cookie);
1423 rte_pktmbuf_free(mbuf);
1428 mrvl_port_bpool_size
1429 [entry->bpool->pp2_id][entry->bpool->id][core_id]++;
1431 if (unlikely(sq->tail + num == MRVL_PP2_TX_SHADOWQ_SIZE))
1436 pp2_bpool_put_buffs(hif, &sq->ent[sq->tail], &num);
1438 sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK;
1444 pp2_bpool_put_buffs(hif, &sq->ent[sq->tail], &num);
1445 sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK;
1451 * DPDK callback for transmit.
1454 * Generic pointer transmit queue.
1456 * Packets to transmit.
1458 * Number of packets in array.
1461 * Number of packets successfully transmitted.
1464 mrvl_tx_pkt_burst(void *txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1466 struct mrvl_txq *q = txq;
1467 struct mrvl_shadow_txq *sq = &shadow_txqs[q->port_id][rte_lcore_id()];
1468 struct pp2_hif *hif = hifs[rte_lcore_id()];
1469 struct pp2_ppio_desc descs[nb_pkts];
1471 uint16_t num, sq_free_size;
1473 if (unlikely(!q->priv->ppio))
1477 mrvl_free_sent_buffers(q->priv->ppio, hif, sq, q->queue_id, 0);
1479 sq_free_size = MRVL_PP2_TX_SHADOWQ_SIZE - sq->size - 1;
1480 if (unlikely(nb_pkts > sq_free_size)) {
1482 "No room in shadow queue for %d packets! %d packets will be sent.\n",
1483 nb_pkts, sq_free_size);
1484 nb_pkts = sq_free_size;
1487 for (i = 0; i < nb_pkts; i++) {
1488 struct rte_mbuf *mbuf = tx_pkts[i];
1490 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) {
1491 struct rte_mbuf *pref_pkt_hdr;
1493 pref_pkt_hdr = tx_pkts[i + MRVL_MUSDK_PREFETCH_SHIFT];
1494 rte_mbuf_prefetch_part1(pref_pkt_hdr);
1495 rte_mbuf_prefetch_part2(pref_pkt_hdr);
1498 sq->ent[sq->head].buff.cookie = (pp2_cookie_t)(uint64_t)mbuf;
1499 sq->ent[sq->head].buff.addr =
1500 rte_mbuf_data_dma_addr_default(mbuf);
1501 sq->ent[sq->head].bpool =
1502 (unlikely(mbuf->port == 0xff || mbuf->refcnt > 1)) ?
1503 NULL : mrvl_port_to_bpool_lookup[mbuf->port];
1504 sq->head = (sq->head + 1) & MRVL_PP2_TX_SHADOWQ_MASK;
1507 pp2_ppio_outq_desc_reset(&descs[i]);
1508 pp2_ppio_outq_desc_set_phys_addr(&descs[i],
1509 rte_pktmbuf_mtophys(mbuf));
1510 pp2_ppio_outq_desc_set_pkt_offset(&descs[i], 0);
1511 pp2_ppio_outq_desc_set_pkt_len(&descs[i],
1512 rte_pktmbuf_pkt_len(mbuf));
1516 pp2_ppio_send(q->priv->ppio, hif, q->queue_id, descs, &nb_pkts);
1517 /* number of packets that were not sent */
1518 if (unlikely(num > nb_pkts)) {
1519 for (i = nb_pkts; i < num; i++) {
1520 sq->head = (MRVL_PP2_TX_SHADOWQ_SIZE + sq->head - 1) &
1521 MRVL_PP2_TX_SHADOWQ_MASK;
1523 sq->size -= num - nb_pkts;
1530 * Initialize packet processor.
1533 * 0 on success, negative error value otherwise.
1538 struct pp2_init_params init_params;
1540 memset(&init_params, 0, sizeof(init_params));
1541 init_params.hif_reserved_map = MRVL_MUSDK_HIFS_RESERVED;
1542 init_params.bm_pool_reserved_map = MRVL_MUSDK_BPOOLS_RESERVED;
1543 init_params.rss_tbl_reserved_map = MRVL_MUSDK_RSS_RESERVED;
1545 return pp2_init(&init_params);
1549 * Deinitialize packet processor.
1552 * 0 on success, negative error value otherwise.
1555 mrvl_deinit_pp2(void)
1561 * Create private device structure.
1564 * Pointer to the port name passed in the initialization parameters.
1567 * Pointer to the newly allocated private device structure.
1569 static struct mrvl_priv *
1570 mrvl_priv_create(const char *dev_name)
1572 struct pp2_bpool_params bpool_params;
1573 char match[MRVL_MATCH_LEN];
1574 struct mrvl_priv *priv;
1577 priv = rte_zmalloc_socket(dev_name, sizeof(*priv), 0, rte_socket_id());
1581 ret = pp2_netdev_get_ppio_info((char *)(uintptr_t)dev_name,
1582 &priv->pp_id, &priv->ppio_id);
1586 bpool_bit = mrvl_reserve_bit(&used_bpools[priv->pp_id],
1587 PP2_BPOOL_NUM_POOLS);
1590 priv->bpool_bit = bpool_bit;
1592 snprintf(match, sizeof(match), "pool-%d:%d", priv->pp_id,
1594 memset(&bpool_params, 0, sizeof(bpool_params));
1595 bpool_params.match = match;
1596 bpool_params.buff_len = MRVL_PKT_SIZE_MAX + MRVL_PKT_EFFEC_OFFS;
1597 ret = pp2_bpool_init(&bpool_params, &priv->bpool);
1599 goto out_clear_bpool_bit;
1601 priv->ppio_params.type = PP2_PPIO_T_NIC;
1602 rte_spinlock_init(&priv->lock);
1605 out_clear_bpool_bit:
1606 used_bpools[priv->pp_id] &= ~(1 << priv->bpool_bit);
1613 * Create device representing Ethernet port.
1616 * Pointer to the port's name.
1619 * 0 on success, negative error value otherwise.
1622 mrvl_eth_dev_create(struct rte_vdev_device *vdev, const char *name)
1624 int ret, fd = socket(AF_INET, SOCK_DGRAM, 0);
1625 struct rte_eth_dev *eth_dev;
1626 struct mrvl_priv *priv;
1629 eth_dev = rte_eth_dev_allocate(name);
1633 priv = mrvl_priv_create(name);
1639 eth_dev->data->mac_addrs =
1640 rte_zmalloc("mac_addrs",
1641 ETHER_ADDR_LEN * MRVL_MAC_ADDRS_MAX, 0);
1642 if (!eth_dev->data->mac_addrs) {
1643 RTE_LOG(ERR, PMD, "Failed to allocate space for eth addrs\n");
1648 memset(&req, 0, sizeof(req));
1649 strcpy(req.ifr_name, name);
1650 ret = ioctl(fd, SIOCGIFHWADDR, &req);
1654 memcpy(eth_dev->data->mac_addrs[0].addr_bytes,
1655 req.ifr_addr.sa_data, ETHER_ADDR_LEN);
1657 eth_dev->rx_pkt_burst = mrvl_rx_pkt_burst;
1658 eth_dev->tx_pkt_burst = mrvl_tx_pkt_burst;
1659 eth_dev->data->dev_private = priv;
1660 eth_dev->device = &vdev->device;
1661 eth_dev->dev_ops = &mrvl_ops;
1665 rte_free(eth_dev->data->mac_addrs);
1667 rte_eth_dev_release_port(eth_dev);
1675 * Cleanup previously created device representing Ethernet port.
1678 * Pointer to the port name.
1681 mrvl_eth_dev_destroy(const char *name)
1683 struct rte_eth_dev *eth_dev;
1684 struct mrvl_priv *priv;
1686 eth_dev = rte_eth_dev_allocated(name);
1690 priv = eth_dev->data->dev_private;
1691 pp2_bpool_deinit(priv->bpool);
1693 rte_free(eth_dev->data->mac_addrs);
1694 rte_eth_dev_release_port(eth_dev);
1698 * Callback used by rte_kvargs_process() during argument parsing.
1701 * Pointer to the parsed key (unused).
1703 * Pointer to the parsed value.
1705 * Pointer to the extra arguments which contains address of the
1706 * table of pointers to parsed interface names.
1712 mrvl_get_ifnames(const char *key __rte_unused, const char *value,
1715 const char **ifnames = extra_args;
1717 ifnames[mrvl_ports_nb++] = value;
1723 * Initialize per-lcore MUSDK hardware interfaces (hifs).
1726 * 0 on success, negative error value otherwise.
1729 mrvl_init_hifs(void)
1731 struct pp2_hif_params params;
1732 char match[MRVL_MATCH_LEN];
1735 RTE_LCORE_FOREACH(i) {
1736 ret = mrvl_reserve_bit(&used_hifs, MRVL_MUSDK_HIFS_MAX);
1740 snprintf(match, sizeof(match), "hif-%d", ret);
1741 memset(¶ms, 0, sizeof(params));
1742 params.match = match;
1743 params.out_size = MRVL_PP2_AGGR_TXQD_MAX;
1744 ret = pp2_hif_init(¶ms, &hifs[i]);
1746 RTE_LOG(ERR, PMD, "Failed to initialize hif %d\n", i);
1755 * Deinitialize per-lcore MUSDK hardware interfaces (hifs).
1758 mrvl_deinit_hifs(void)
1762 RTE_LCORE_FOREACH(i) {
1764 pp2_hif_deinit(hifs[i]);
1768 static void mrvl_set_first_last_cores(int core_id)
1770 if (core_id < mrvl_lcore_first)
1771 mrvl_lcore_first = core_id;
1773 if (core_id > mrvl_lcore_last)
1774 mrvl_lcore_last = core_id;
1778 * DPDK callback to register the virtual device.
1781 * Pointer to the virtual device.
1784 * 0 on success, negative error value otherwise.
1787 rte_pmd_mrvl_probe(struct rte_vdev_device *vdev)
1789 struct rte_kvargs *kvlist;
1790 const char *ifnames[PP2_NUM_ETH_PPIO * PP2_NUM_PKT_PROC];
1792 uint32_t i, ifnum, cfgnum, core_id;
1795 params = rte_vdev_device_args(vdev);
1799 kvlist = rte_kvargs_parse(params, valid_args);
1803 ifnum = rte_kvargs_count(kvlist, MRVL_IFACE_NAME_ARG);
1804 if (ifnum > RTE_DIM(ifnames))
1805 goto out_free_kvlist;
1807 rte_kvargs_process(kvlist, MRVL_IFACE_NAME_ARG,
1808 mrvl_get_ifnames, &ifnames);
1810 cfgnum = rte_kvargs_count(kvlist, MRVL_CFG_ARG);
1812 RTE_LOG(ERR, PMD, "Cannot handle more than one config file!\n");
1813 goto out_free_kvlist;
1814 } else if (cfgnum == 1) {
1815 rte_kvargs_process(kvlist, MRVL_CFG_ARG,
1816 mrvl_get_qoscfg, &mrvl_qos_cfg);
1820 * ret == -EEXIST is correct, it means DMA
1821 * has been already initialized (by another PMD).
1823 ret = mv_sys_dma_mem_init(RTE_MRVL_MUSDK_DMA_MEMSIZE);
1824 if (ret < 0 && ret != -EEXIST)
1825 goto out_free_kvlist;
1827 ret = mrvl_init_pp2();
1829 RTE_LOG(ERR, PMD, "Failed to init PP!\n");
1830 goto out_deinit_dma;
1833 ret = mrvl_init_hifs();
1835 goto out_deinit_hifs;
1837 for (i = 0; i < ifnum; i++) {
1838 RTE_LOG(INFO, PMD, "Creating %s\n", ifnames[i]);
1839 ret = mrvl_eth_dev_create(vdev, ifnames[i]);
1844 rte_kvargs_free(kvlist);
1846 memset(mrvl_port_bpool_size, 0, sizeof(mrvl_port_bpool_size));
1848 mrvl_lcore_first = RTE_MAX_LCORE;
1849 mrvl_lcore_last = 0;
1851 RTE_LCORE_FOREACH(core_id) {
1852 mrvl_set_first_last_cores(core_id);
1858 mrvl_eth_dev_destroy(ifnames[i]);
1863 mv_sys_dma_mem_destroy();
1865 rte_kvargs_free(kvlist);
1871 * DPDK callback to remove virtual device.
1874 * Pointer to the removed virtual device.
1877 * 0 on success, negative error value otherwise.
1880 rte_pmd_mrvl_remove(struct rte_vdev_device *vdev)
1885 name = rte_vdev_device_name(vdev);
1889 RTE_LOG(INFO, PMD, "Removing %s\n", name);
1891 for (i = 0; i < rte_eth_dev_count(); i++) {
1892 char ifname[RTE_ETH_NAME_MAX_LEN];
1894 rte_eth_dev_get_name_by_port(i, ifname);
1895 mrvl_eth_dev_destroy(ifname);
1900 mv_sys_dma_mem_destroy();
1905 static struct rte_vdev_driver pmd_mrvl_drv = {
1906 .probe = rte_pmd_mrvl_probe,
1907 .remove = rte_pmd_mrvl_remove,
1910 RTE_PMD_REGISTER_VDEV(net_mrvl, pmd_mrvl_drv);
1911 RTE_PMD_REGISTER_ALIAS(net_mrvl, eth_mrvl);