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33 #include <rte_ethdev.h>
34 #include <rte_kvargs.h>
36 #include <rte_malloc.h>
39 /* Unluckily, container_of is defined by both DPDK and MUSDK,
40 * we'll declare only one version.
42 * Note that it is not used in this PMD anyway.
48 #include <drivers/mv_pp2.h>
49 #include <drivers/mv_pp2_bpool.h>
50 #include <drivers/mv_pp2_hif.h>
53 #include <linux/ethtool.h>
54 #include <linux/sockios.h>
56 #include <net/if_arp.h>
57 #include <sys/ioctl.h>
58 #include <sys/socket.h>
60 #include <sys/types.h>
62 #include "mrvl_ethdev.h"
65 /* bitmask with reserved hifs */
66 #define MRVL_MUSDK_HIFS_RESERVED 0x0F
67 /* bitmask with reserved bpools */
68 #define MRVL_MUSDK_BPOOLS_RESERVED 0x07
69 /* bitmask with reserved kernel RSS tables */
70 #define MRVL_MUSDK_RSS_RESERVED 0x01
71 /* maximum number of available hifs */
72 #define MRVL_MUSDK_HIFS_MAX 9
75 #define MRVL_MUSDK_PREFETCH_SHIFT 2
77 /* TCAM has 25 entries reserved for uc/mc filter entries */
78 #define MRVL_MAC_ADDRS_MAX 25
79 #define MRVL_MATCH_LEN 16
80 #define MRVL_PKT_EFFEC_OFFS (MRVL_PKT_OFFS + MV_MH_SIZE)
81 /* Maximum allowable packet size */
82 #define MRVL_PKT_SIZE_MAX (10240 - MV_MH_SIZE)
84 #define MRVL_IFACE_NAME_ARG "iface"
85 #define MRVL_CFG_ARG "cfg"
87 #define MRVL_BURST_SIZE 64
89 #define MRVL_ARP_LENGTH 28
91 #define MRVL_COOKIE_ADDR_INVALID ~0ULL
93 #define MRVL_COOKIE_HIGH_ADDR_SHIFT (sizeof(pp2_cookie_t) * 8)
94 #define MRVL_COOKIE_HIGH_ADDR_MASK (~0ULL << MRVL_COOKIE_HIGH_ADDR_SHIFT)
96 static const char * const valid_args[] = {
102 static int used_hifs = MRVL_MUSDK_HIFS_RESERVED;
103 static struct pp2_hif *hifs[RTE_MAX_LCORE];
104 static int used_bpools[PP2_NUM_PKT_PROC] = {
105 MRVL_MUSDK_BPOOLS_RESERVED,
106 MRVL_MUSDK_BPOOLS_RESERVED
109 struct pp2_bpool *mrvl_port_to_bpool_lookup[RTE_MAX_ETHPORTS];
110 int mrvl_port_bpool_size[PP2_NUM_PKT_PROC][PP2_BPOOL_NUM_POOLS][RTE_MAX_LCORE];
111 uint64_t cookie_addr_high = MRVL_COOKIE_ADDR_INVALID;
114 * To use buffer harvesting based on loopback port shadow queue structure
115 * was introduced for buffers information bookkeeping.
117 * Before sending the packet, related buffer information (pp2_buff_inf) is
118 * stored in shadow queue. After packet is transmitted no longer used
119 * packet buffer is released back to it's original hardware pool,
120 * on condition it originated from interface.
121 * In case it was generated by application itself i.e: mbuf->port field is
122 * 0xff then its released to software mempool.
124 struct mrvl_shadow_txq {
125 int head; /* write index - used when sending buffers */
126 int tail; /* read index - used when releasing buffers */
127 u16 size; /* queue occupied size */
128 u16 num_to_release; /* number of buffers sent, that can be released */
129 struct buff_release_entry ent[MRVL_PP2_TX_SHADOWQ_SIZE]; /* q entries */
133 struct mrvl_priv *priv;
134 struct rte_mempool *mp;
140 struct mrvl_priv *priv;
146 * Every tx queue should have dedicated shadow tx queue.
148 * Ports assigned by DPDK might not start at zero or be continuous so
149 * as a workaround define shadow queues for each possible port so that
150 * we eventually fit somewhere.
152 struct mrvl_shadow_txq shadow_txqs[RTE_MAX_ETHPORTS][RTE_MAX_LCORE];
154 /** Number of ports configured. */
156 static int mrvl_lcore_first;
157 static int mrvl_lcore_last;
160 mrvl_get_bpool_size(int pp2_id, int pool_id)
165 for (i = mrvl_lcore_first; i <= mrvl_lcore_last; i++)
166 size += mrvl_port_bpool_size[pp2_id][pool_id][i];
172 mrvl_reserve_bit(int *bitmap, int max)
174 int n = sizeof(*bitmap) * 8 - __builtin_clz(*bitmap);
185 * Configure rss based on dpdk rss configuration.
188 * Pointer to private structure.
190 * Pointer to RSS configuration.
193 * 0 on success, negative error value otherwise.
196 mrvl_configure_rss(struct mrvl_priv *priv, struct rte_eth_rss_conf *rss_conf)
198 if (rss_conf->rss_key)
199 RTE_LOG(WARNING, PMD, "Changing hash key is not supported\n");
201 if (rss_conf->rss_hf == 0) {
202 priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE;
203 } else if (rss_conf->rss_hf & ETH_RSS_IPV4) {
204 priv->ppio_params.inqs_params.hash_type =
205 PP2_PPIO_HASH_T_2_TUPLE;
206 } else if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) {
207 priv->ppio_params.inqs_params.hash_type =
208 PP2_PPIO_HASH_T_5_TUPLE;
209 priv->rss_hf_tcp = 1;
210 } else if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) {
211 priv->ppio_params.inqs_params.hash_type =
212 PP2_PPIO_HASH_T_5_TUPLE;
213 priv->rss_hf_tcp = 0;
222 * Ethernet device configuration.
224 * Prepare the driver for a given number of TX and RX queues and
228 * Pointer to Ethernet device structure.
231 * 0 on success, negative error value otherwise.
234 mrvl_dev_configure(struct rte_eth_dev *dev)
236 struct mrvl_priv *priv = dev->data->dev_private;
239 if (dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_NONE &&
240 dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) {
241 RTE_LOG(INFO, PMD, "Unsupported rx multi queue mode %d\n",
242 dev->data->dev_conf.rxmode.mq_mode);
246 if (!dev->data->dev_conf.rxmode.hw_strip_crc) {
248 "L2 CRC stripping is always enabled in hw\n");
249 dev->data->dev_conf.rxmode.hw_strip_crc = 1;
252 if (dev->data->dev_conf.rxmode.hw_vlan_strip) {
253 RTE_LOG(INFO, PMD, "VLAN stripping not supported\n");
257 if (dev->data->dev_conf.rxmode.split_hdr_size) {
258 RTE_LOG(INFO, PMD, "Split headers not supported\n");
262 if (dev->data->dev_conf.rxmode.enable_scatter) {
263 RTE_LOG(INFO, PMD, "RX Scatter/Gather not supported\n");
267 if (dev->data->dev_conf.rxmode.enable_lro) {
268 RTE_LOG(INFO, PMD, "LRO not supported\n");
272 if (dev->data->dev_conf.rxmode.jumbo_frame)
273 dev->data->mtu = dev->data->dev_conf.rxmode.max_rx_pkt_len -
274 ETHER_HDR_LEN - ETHER_CRC_LEN;
276 ret = mrvl_configure_rxqs(priv, dev->data->port_id,
277 dev->data->nb_rx_queues);
281 priv->ppio_params.outqs_params.num_outqs = dev->data->nb_tx_queues;
282 priv->nb_rx_queues = dev->data->nb_rx_queues;
284 if (dev->data->nb_rx_queues == 1 &&
285 dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) {
286 RTE_LOG(WARNING, PMD, "Disabling hash for 1 rx queue\n");
287 priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE;
292 return mrvl_configure_rss(priv,
293 &dev->data->dev_conf.rx_adv_conf.rss_conf);
297 * DPDK callback to change the MTU.
299 * Setting the MTU affects hardware MRU (packets larger than the MRU
303 * Pointer to Ethernet device structure.
308 * 0 on success, negative error value otherwise.
311 mrvl_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
313 struct mrvl_priv *priv = dev->data->dev_private;
314 /* extra MV_MH_SIZE bytes are required for Marvell tag */
315 uint16_t mru = mtu + MV_MH_SIZE + ETHER_HDR_LEN + ETHER_CRC_LEN;
318 if (mtu < ETHER_MIN_MTU || mru > MRVL_PKT_SIZE_MAX)
321 ret = pp2_ppio_set_mru(priv->ppio, mru);
325 return pp2_ppio_set_mtu(priv->ppio, mtu);
329 * DPDK callback to bring the link up.
332 * Pointer to Ethernet device structure.
335 * 0 on success, negative error value otherwise.
338 mrvl_dev_set_link_up(struct rte_eth_dev *dev)
340 struct mrvl_priv *priv = dev->data->dev_private;
343 ret = pp2_ppio_enable(priv->ppio);
348 * mtu/mru can be updated if pp2_ppio_enable() was called at least once
349 * as pp2_ppio_enable() changes port->t_mode from default 0 to
350 * PP2_TRAFFIC_INGRESS_EGRESS.
352 * Set mtu to default DPDK value here.
354 ret = mrvl_mtu_set(dev, dev->data->mtu);
356 pp2_ppio_disable(priv->ppio);
358 dev->data->dev_link.link_status = ETH_LINK_UP;
364 * DPDK callback to bring the link down.
367 * Pointer to Ethernet device structure.
370 * 0 on success, negative error value otherwise.
373 mrvl_dev_set_link_down(struct rte_eth_dev *dev)
375 struct mrvl_priv *priv = dev->data->dev_private;
378 ret = pp2_ppio_disable(priv->ppio);
382 dev->data->dev_link.link_status = ETH_LINK_DOWN;
388 * DPDK callback to start the device.
391 * Pointer to Ethernet device structure.
394 * 0 on success, negative errno value on failure.
397 mrvl_dev_start(struct rte_eth_dev *dev)
399 struct mrvl_priv *priv = dev->data->dev_private;
400 char match[MRVL_MATCH_LEN];
403 snprintf(match, sizeof(match), "ppio-%d:%d",
404 priv->pp_id, priv->ppio_id);
405 priv->ppio_params.match = match;
408 * Calculate the maximum bpool size for refill feature to 1.5 of the
409 * configured size. In case the bpool size will exceed this value,
410 * superfluous buffers will be removed
412 priv->bpool_max_size = priv->bpool_init_size +
413 (priv->bpool_init_size >> 1);
415 * Calculate the minimum bpool size for refill feature as follows:
416 * 2 default burst sizes multiply by number of rx queues.
417 * If the bpool size will be below this value, new buffers will
418 * be added to the pool.
420 priv->bpool_min_size = priv->nb_rx_queues * MRVL_BURST_SIZE * 2;
422 ret = pp2_ppio_init(&priv->ppio_params, &priv->ppio);
427 * In case there are some some stale uc/mc mac addresses flush them
428 * here. It cannot be done during mrvl_dev_close() as port information
429 * is already gone at that point (due to pp2_ppio_deinit() in
432 if (!priv->uc_mc_flushed) {
433 ret = pp2_ppio_flush_mac_addrs(priv->ppio, 1, 1);
436 "Failed to flush uc/mc filter list\n");
439 priv->uc_mc_flushed = 1;
442 /* For default QoS config, don't start classifier. */
444 ret = mrvl_start_qos_mapping(priv);
446 pp2_ppio_deinit(priv->ppio);
451 ret = mrvl_dev_set_link_up(dev);
457 pp2_ppio_deinit(priv->ppio);
462 * Flush receive queues.
465 * Pointer to Ethernet device structure.
468 mrvl_flush_rx_queues(struct rte_eth_dev *dev)
472 RTE_LOG(INFO, PMD, "Flushing rx queues\n");
473 for (i = 0; i < dev->data->nb_rx_queues; i++) {
477 struct mrvl_rxq *q = dev->data->rx_queues[i];
478 struct pp2_ppio_desc descs[MRVL_PP2_RXD_MAX];
480 num = MRVL_PP2_RXD_MAX;
481 ret = pp2_ppio_recv(q->priv->ppio,
482 q->priv->rxq_map[q->queue_id].tc,
483 q->priv->rxq_map[q->queue_id].inq,
484 descs, (uint16_t *)&num);
485 } while (ret == 0 && num);
490 * Flush transmit shadow queues.
493 * Pointer to Ethernet device structure.
496 mrvl_flush_tx_shadow_queues(struct rte_eth_dev *dev)
500 RTE_LOG(INFO, PMD, "Flushing tx shadow queues\n");
501 for (i = 0; i < RTE_MAX_LCORE; i++) {
502 struct mrvl_shadow_txq *sq =
503 &shadow_txqs[dev->data->port_id][i];
505 while (sq->tail != sq->head) {
506 uint64_t addr = cookie_addr_high |
507 sq->ent[sq->tail].buff.cookie;
508 rte_pktmbuf_free((struct rte_mbuf *)addr);
509 sq->tail = (sq->tail + 1) & MRVL_PP2_TX_SHADOWQ_MASK;
512 memset(sq, 0, sizeof(*sq));
517 * Flush hardware bpool (buffer-pool).
520 * Pointer to Ethernet device structure.
523 mrvl_flush_bpool(struct rte_eth_dev *dev)
525 struct mrvl_priv *priv = dev->data->dev_private;
529 ret = pp2_bpool_get_num_buffs(priv->bpool, &num);
531 RTE_LOG(ERR, PMD, "Failed to get bpool buffers number\n");
536 struct pp2_buff_inf inf;
539 ret = pp2_bpool_get_buff(hifs[rte_lcore_id()], priv->bpool,
544 addr = cookie_addr_high | inf.cookie;
545 rte_pktmbuf_free((struct rte_mbuf *)addr);
550 * DPDK callback to stop the device.
553 * Pointer to Ethernet device structure.
556 mrvl_dev_stop(struct rte_eth_dev *dev)
558 struct mrvl_priv *priv = dev->data->dev_private;
560 mrvl_dev_set_link_down(dev);
561 mrvl_flush_rx_queues(dev);
562 mrvl_flush_tx_shadow_queues(dev);
564 pp2_cls_qos_tbl_deinit(priv->qos_tbl);
565 pp2_ppio_deinit(priv->ppio);
570 * DPDK callback to close the device.
573 * Pointer to Ethernet device structure.
576 mrvl_dev_close(struct rte_eth_dev *dev)
578 struct mrvl_priv *priv = dev->data->dev_private;
581 for (i = 0; i < priv->ppio_params.inqs_params.num_tcs; ++i) {
582 struct pp2_ppio_tc_params *tc_params =
583 &priv->ppio_params.inqs_params.tcs_params[i];
585 if (tc_params->inqs_params) {
586 rte_free(tc_params->inqs_params);
587 tc_params->inqs_params = NULL;
591 mrvl_flush_bpool(dev);
595 * DPDK callback to retrieve physical link information.
598 * Pointer to Ethernet device structure.
599 * @param wait_to_complete
600 * Wait for request completion (ignored).
603 * 0 on success, negative error value otherwise.
606 mrvl_link_update(struct rte_eth_dev *dev, int wait_to_complete __rte_unused)
610 * once MUSDK provides necessary API use it here
612 struct ethtool_cmd edata;
616 edata.cmd = ETHTOOL_GSET;
618 strcpy(req.ifr_name, dev->data->name);
619 req.ifr_data = (void *)&edata;
621 fd = socket(AF_INET, SOCK_DGRAM, 0);
625 ret = ioctl(fd, SIOCETHTOOL, &req);
633 switch (ethtool_cmd_speed(&edata)) {
635 dev->data->dev_link.link_speed = ETH_SPEED_NUM_10M;
638 dev->data->dev_link.link_speed = ETH_SPEED_NUM_100M;
641 dev->data->dev_link.link_speed = ETH_SPEED_NUM_1G;
644 dev->data->dev_link.link_speed = ETH_SPEED_NUM_10G;
647 dev->data->dev_link.link_speed = ETH_SPEED_NUM_NONE;
650 dev->data->dev_link.link_duplex = edata.duplex ? ETH_LINK_FULL_DUPLEX :
651 ETH_LINK_HALF_DUPLEX;
652 dev->data->dev_link.link_autoneg = edata.autoneg ? ETH_LINK_AUTONEG :
659 * DPDK callback to enable promiscuous mode.
662 * Pointer to Ethernet device structure.
665 mrvl_promiscuous_enable(struct rte_eth_dev *dev)
667 struct mrvl_priv *priv = dev->data->dev_private;
670 ret = pp2_ppio_set_uc_promisc(priv->ppio, 1);
672 RTE_LOG(ERR, PMD, "Failed to enable promiscuous mode\n");
676 * DPDK callback to enable allmulti mode.
679 * Pointer to Ethernet device structure.
682 mrvl_allmulticast_enable(struct rte_eth_dev *dev)
684 struct mrvl_priv *priv = dev->data->dev_private;
687 ret = pp2_ppio_set_mc_promisc(priv->ppio, 1);
689 RTE_LOG(ERR, PMD, "Failed enable all-multicast mode\n");
693 * DPDK callback to disable promiscuous mode.
696 * Pointer to Ethernet device structure.
699 mrvl_promiscuous_disable(struct rte_eth_dev *dev)
701 struct mrvl_priv *priv = dev->data->dev_private;
704 ret = pp2_ppio_set_uc_promisc(priv->ppio, 0);
706 RTE_LOG(ERR, PMD, "Failed to disable promiscuous mode\n");
710 * DPDK callback to disable allmulticast mode.
713 * Pointer to Ethernet device structure.
716 mrvl_allmulticast_disable(struct rte_eth_dev *dev)
718 struct mrvl_priv *priv = dev->data->dev_private;
721 ret = pp2_ppio_set_mc_promisc(priv->ppio, 0);
723 RTE_LOG(ERR, PMD, "Failed to disable all-multicast mode\n");
727 * DPDK callback to remove a MAC address.
730 * Pointer to Ethernet device structure.
735 mrvl_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index)
737 struct mrvl_priv *priv = dev->data->dev_private;
738 char buf[ETHER_ADDR_FMT_SIZE];
741 ret = pp2_ppio_remove_mac_addr(priv->ppio,
742 dev->data->mac_addrs[index].addr_bytes);
744 ether_format_addr(buf, sizeof(buf),
745 &dev->data->mac_addrs[index]);
746 RTE_LOG(ERR, PMD, "Failed to remove mac %s\n", buf);
751 * DPDK callback to add a MAC address.
754 * Pointer to Ethernet device structure.
756 * MAC address to register.
760 * VMDq pool index to associate address with (unused).
763 * 0 on success, negative error value otherwise.
766 mrvl_mac_addr_add(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
767 uint32_t index, uint32_t vmdq __rte_unused)
769 struct mrvl_priv *priv = dev->data->dev_private;
770 char buf[ETHER_ADDR_FMT_SIZE];
774 /* For setting index 0, mrvl_mac_addr_set() should be used.*/
778 * Maximum number of uc addresses can be tuned via kernel module mvpp2x
779 * parameter uc_filter_max. Maximum number of mc addresses is then
780 * MRVL_MAC_ADDRS_MAX - uc_filter_max. Currently it defaults to 4 and
783 * If more than uc_filter_max uc addresses were added to filter list
784 * then NIC will switch to promiscuous mode automatically.
786 * If more than MRVL_MAC_ADDRS_MAX - uc_filter_max number mc addresses
787 * were added to filter list then NIC will switch to all-multicast mode
790 ret = pp2_ppio_add_mac_addr(priv->ppio, mac_addr->addr_bytes);
792 ether_format_addr(buf, sizeof(buf), mac_addr);
793 RTE_LOG(ERR, PMD, "Failed to add mac %s\n", buf);
801 * DPDK callback to set the primary MAC address.
804 * Pointer to Ethernet device structure.
806 * MAC address to register.
809 mrvl_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr)
811 struct mrvl_priv *priv = dev->data->dev_private;
813 pp2_ppio_set_mac_addr(priv->ppio, mac_addr->addr_bytes);
816 * Port stops sending packets if pp2_ppio_set_mac_addr()
817 * was called after pp2_ppio_enable(). As a quick fix issue
818 * enable port once again.
820 pp2_ppio_enable(priv->ppio);
824 * DPDK callback to get information about the device.
827 * Pointer to Ethernet device structure (unused).
829 * Info structure output buffer.
832 mrvl_dev_infos_get(struct rte_eth_dev *dev __rte_unused,
833 struct rte_eth_dev_info *info)
835 info->speed_capa = ETH_LINK_SPEED_10M |
836 ETH_LINK_SPEED_100M |
840 info->max_rx_queues = MRVL_PP2_RXQ_MAX;
841 info->max_tx_queues = MRVL_PP2_TXQ_MAX;
842 info->max_mac_addrs = MRVL_MAC_ADDRS_MAX;
844 info->rx_desc_lim.nb_max = MRVL_PP2_RXD_MAX;
845 info->rx_desc_lim.nb_min = MRVL_PP2_RXD_MIN;
846 info->rx_desc_lim.nb_align = MRVL_PP2_RXD_ALIGN;
848 info->tx_desc_lim.nb_max = MRVL_PP2_TXD_MAX;
849 info->tx_desc_lim.nb_min = MRVL_PP2_TXD_MIN;
850 info->tx_desc_lim.nb_align = MRVL_PP2_TXD_ALIGN;
852 info->rx_offload_capa = DEV_RX_OFFLOAD_JUMBO_FRAME;
853 info->flow_type_rss_offloads = ETH_RSS_IPV4 |
854 ETH_RSS_NONFRAG_IPV4_TCP |
855 ETH_RSS_NONFRAG_IPV4_UDP;
857 /* By default packets are dropped if no descriptors are available */
858 info->default_rxconf.rx_drop_en = 1;
860 info->max_rx_pktlen = MRVL_PKT_SIZE_MAX;
864 * DPDK callback to get information about specific receive queue.
867 * Pointer to Ethernet device structure.
869 * Receive queue index.
871 * Receive queue information structure.
873 static void mrvl_rxq_info_get(struct rte_eth_dev *dev, uint16_t rx_queue_id,
874 struct rte_eth_rxq_info *qinfo)
876 struct mrvl_rxq *q = dev->data->rx_queues[rx_queue_id];
877 struct mrvl_priv *priv = dev->data->dev_private;
878 int inq = priv->rxq_map[rx_queue_id].inq;
879 int tc = priv->rxq_map[rx_queue_id].tc;
880 struct pp2_ppio_tc_params *tc_params =
881 &priv->ppio_params.inqs_params.tcs_params[tc];
884 qinfo->nb_desc = tc_params->inqs_params[inq].size;
888 * DPDK callback to get information about specific transmit queue.
891 * Pointer to Ethernet device structure.
893 * Transmit queue index.
895 * Transmit queue information structure.
897 static void mrvl_txq_info_get(struct rte_eth_dev *dev, uint16_t tx_queue_id,
898 struct rte_eth_txq_info *qinfo)
900 struct mrvl_priv *priv = dev->data->dev_private;
903 priv->ppio_params.outqs_params.outqs_params[tx_queue_id].size;
907 * Release buffers to hardware bpool (buffer-pool)
910 * Receive queue pointer.
912 * Number of buffers to release to bpool.
915 * 0 on success, negative error value otherwise.
918 mrvl_fill_bpool(struct mrvl_rxq *rxq, int num)
920 struct buff_release_entry entries[MRVL_PP2_TXD_MAX];
921 struct rte_mbuf *mbufs[MRVL_PP2_TXD_MAX];
923 unsigned int core_id = rte_lcore_id();
924 struct pp2_hif *hif = hifs[core_id];
925 struct pp2_bpool *bpool = rxq->priv->bpool;
927 ret = rte_pktmbuf_alloc_bulk(rxq->mp, mbufs, num);
931 if (cookie_addr_high == MRVL_COOKIE_ADDR_INVALID)
933 (uint64_t)mbufs[0] & MRVL_COOKIE_HIGH_ADDR_MASK;
935 for (i = 0; i < num; i++) {
936 if (((uint64_t)mbufs[i] & MRVL_COOKIE_HIGH_ADDR_MASK)
937 != cookie_addr_high) {
939 "mbuf virtual addr high 0x%lx out of range\n",
940 (uint64_t)mbufs[i] >> 32);
944 entries[i].buff.addr =
945 rte_mbuf_data_dma_addr_default(mbufs[i]);
946 entries[i].buff.cookie = (pp2_cookie_t)(uint64_t)mbufs[i];
947 entries[i].bpool = bpool;
950 pp2_bpool_put_buffs(hif, entries, (uint16_t *)&i);
951 mrvl_port_bpool_size[bpool->pp2_id][bpool->id][core_id] += i;
959 rte_pktmbuf_free(mbufs[i]);
965 * DPDK callback to configure the receive queue.
968 * Pointer to Ethernet device structure.
972 * Number of descriptors to configure in queue.
974 * NUMA socket on which memory must be allocated.
976 * Thresholds parameters (unused_).
978 * Memory pool for buffer allocations.
981 * 0 on success, negative error value otherwise.
984 mrvl_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
986 const struct rte_eth_rxconf *conf __rte_unused,
987 struct rte_mempool *mp)
989 struct mrvl_priv *priv = dev->data->dev_private;
990 struct mrvl_rxq *rxq;
992 max_rx_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
995 if (priv->rxq_map[idx].tc == MRVL_UNKNOWN_TC) {
997 * Unknown TC mapping, mapping will not have a correct queue.
999 RTE_LOG(ERR, PMD, "Unknown TC mapping for queue %hu eth%hhu\n",
1000 idx, priv->ppio_id);
1004 min_size = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM -
1005 MRVL_PKT_EFFEC_OFFS;
1006 if (min_size < max_rx_pkt_len) {
1008 "Mbuf size must be increased to %u bytes to hold up to %u bytes of data.\n",
1009 max_rx_pkt_len + RTE_PKTMBUF_HEADROOM +
1010 MRVL_PKT_EFFEC_OFFS,
1015 if (dev->data->rx_queues[idx]) {
1016 rte_free(dev->data->rx_queues[idx]);
1017 dev->data->rx_queues[idx] = NULL;
1020 rxq = rte_zmalloc_socket("rxq", sizeof(*rxq), 0, socket);
1026 rxq->queue_id = idx;
1027 rxq->port_id = dev->data->port_id;
1028 mrvl_port_to_bpool_lookup[rxq->port_id] = priv->bpool;
1030 tc = priv->rxq_map[rxq->queue_id].tc,
1031 inq = priv->rxq_map[rxq->queue_id].inq;
1032 priv->ppio_params.inqs_params.tcs_params[tc].inqs_params[inq].size =
1035 ret = mrvl_fill_bpool(rxq, desc);
1041 priv->bpool_init_size += desc;
1043 dev->data->rx_queues[idx] = rxq;
1049 * DPDK callback to release the receive queue.
1052 * Generic receive queue pointer.
1055 mrvl_rx_queue_release(void *rxq)
1057 struct mrvl_rxq *q = rxq;
1058 struct pp2_ppio_tc_params *tc_params;
1059 int i, num, tc, inq;
1064 tc = q->priv->rxq_map[q->queue_id].tc;
1065 inq = q->priv->rxq_map[q->queue_id].inq;
1066 tc_params = &q->priv->ppio_params.inqs_params.tcs_params[tc];
1067 num = tc_params->inqs_params[inq].size;
1068 for (i = 0; i < num; i++) {
1069 struct pp2_buff_inf inf;
1072 pp2_bpool_get_buff(hifs[rte_lcore_id()], q->priv->bpool, &inf);
1073 addr = cookie_addr_high | inf.cookie;
1074 rte_pktmbuf_free((struct rte_mbuf *)addr);
1081 * DPDK callback to configure the transmit queue.
1084 * Pointer to Ethernet device structure.
1086 * Transmit queue index.
1088 * Number of descriptors to configure in the queue.
1090 * NUMA socket on which memory must be allocated.
1092 * Thresholds parameters (unused).
1095 * 0 on success, negative error value otherwise.
1098 mrvl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1099 unsigned int socket,
1100 const struct rte_eth_txconf *conf __rte_unused)
1102 struct mrvl_priv *priv = dev->data->dev_private;
1103 struct mrvl_txq *txq;
1105 if (dev->data->tx_queues[idx]) {
1106 rte_free(dev->data->tx_queues[idx]);
1107 dev->data->tx_queues[idx] = NULL;
1110 txq = rte_zmalloc_socket("txq", sizeof(*txq), 0, socket);
1115 txq->queue_id = idx;
1116 txq->port_id = dev->data->port_id;
1117 dev->data->tx_queues[idx] = txq;
1119 priv->ppio_params.outqs_params.outqs_params[idx].size = desc;
1120 priv->ppio_params.outqs_params.outqs_params[idx].weight = 1;
1126 * DPDK callback to release the transmit queue.
1129 * Generic transmit queue pointer.
1132 mrvl_tx_queue_release(void *txq)
1134 struct mrvl_txq *q = txq;
1143 * Update RSS hash configuration
1146 * Pointer to Ethernet device structure.
1148 * Pointer to RSS configuration.
1151 * 0 on success, negative error value otherwise.
1154 mrvl_rss_hash_update(struct rte_eth_dev *dev,
1155 struct rte_eth_rss_conf *rss_conf)
1157 struct mrvl_priv *priv = dev->data->dev_private;
1159 return mrvl_configure_rss(priv, rss_conf);
1163 * DPDK callback to get RSS hash configuration.
1166 * Pointer to Ethernet device structure.
1168 * Pointer to RSS configuration.
1174 mrvl_rss_hash_conf_get(struct rte_eth_dev *dev,
1175 struct rte_eth_rss_conf *rss_conf)
1177 struct mrvl_priv *priv = dev->data->dev_private;
1178 enum pp2_ppio_hash_type hash_type =
1179 priv->ppio_params.inqs_params.hash_type;
1181 rss_conf->rss_key = NULL;
1183 if (hash_type == PP2_PPIO_HASH_T_NONE)
1184 rss_conf->rss_hf = 0;
1185 else if (hash_type == PP2_PPIO_HASH_T_2_TUPLE)
1186 rss_conf->rss_hf = ETH_RSS_IPV4;
1187 else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && priv->rss_hf_tcp)
1188 rss_conf->rss_hf = ETH_RSS_NONFRAG_IPV4_TCP;
1189 else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && !priv->rss_hf_tcp)
1190 rss_conf->rss_hf = ETH_RSS_NONFRAG_IPV4_UDP;
1195 static const struct eth_dev_ops mrvl_ops = {
1196 .dev_configure = mrvl_dev_configure,
1197 .dev_start = mrvl_dev_start,
1198 .dev_stop = mrvl_dev_stop,
1199 .dev_set_link_up = mrvl_dev_set_link_up,
1200 .dev_set_link_down = mrvl_dev_set_link_down,
1201 .dev_close = mrvl_dev_close,
1202 .link_update = mrvl_link_update,
1203 .promiscuous_enable = mrvl_promiscuous_enable,
1204 .allmulticast_enable = mrvl_allmulticast_enable,
1205 .promiscuous_disable = mrvl_promiscuous_disable,
1206 .allmulticast_disable = mrvl_allmulticast_disable,
1207 .mac_addr_remove = mrvl_mac_addr_remove,
1208 .mac_addr_add = mrvl_mac_addr_add,
1209 .mac_addr_set = mrvl_mac_addr_set,
1210 .mtu_set = mrvl_mtu_set,
1211 .dev_infos_get = mrvl_dev_infos_get,
1212 .rxq_info_get = mrvl_rxq_info_get,
1213 .txq_info_get = mrvl_txq_info_get,
1214 .rx_queue_setup = mrvl_rx_queue_setup,
1215 .rx_queue_release = mrvl_rx_queue_release,
1216 .tx_queue_setup = mrvl_tx_queue_setup,
1217 .tx_queue_release = mrvl_tx_queue_release,
1218 .rss_hash_update = mrvl_rss_hash_update,
1219 .rss_hash_conf_get = mrvl_rss_hash_conf_get,
1223 * DPDK callback for receive.
1226 * Generic pointer to the receive queue.
1228 * Array to store received packets.
1230 * Maximum number of packets in array.
1233 * Number of packets successfully received.
1236 mrvl_rx_pkt_burst(void *rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1238 struct mrvl_rxq *q = rxq;
1239 struct pp2_ppio_desc descs[nb_pkts];
1240 struct pp2_bpool *bpool;
1241 int i, ret, rx_done = 0;
1243 unsigned int core_id = rte_lcore_id();
1245 if (unlikely(!q->priv->ppio))
1248 bpool = q->priv->bpool;
1250 ret = pp2_ppio_recv(q->priv->ppio, q->priv->rxq_map[q->queue_id].tc,
1251 q->priv->rxq_map[q->queue_id].inq, descs, &nb_pkts);
1252 if (unlikely(ret < 0)) {
1253 RTE_LOG(ERR, PMD, "Failed to receive packets\n");
1256 mrvl_port_bpool_size[bpool->pp2_id][bpool->id][core_id] -= nb_pkts;
1258 for (i = 0; i < nb_pkts; i++) {
1259 struct rte_mbuf *mbuf;
1260 enum pp2_inq_desc_status status;
1263 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) {
1264 struct pp2_ppio_desc *pref_desc;
1267 pref_desc = &descs[i + MRVL_MUSDK_PREFETCH_SHIFT];
1268 pref_addr = cookie_addr_high |
1269 pp2_ppio_inq_desc_get_cookie(pref_desc);
1270 rte_mbuf_prefetch_part1((struct rte_mbuf *)(pref_addr));
1271 rte_mbuf_prefetch_part2((struct rte_mbuf *)(pref_addr));
1274 addr = cookie_addr_high |
1275 pp2_ppio_inq_desc_get_cookie(&descs[i]);
1276 mbuf = (struct rte_mbuf *)addr;
1277 rte_pktmbuf_reset(mbuf);
1279 /* drop packet in case of mac, overrun or resource error */
1280 status = pp2_ppio_inq_desc_get_l2_pkt_error(&descs[i]);
1281 if (unlikely(status != PP2_DESC_ERR_OK)) {
1282 struct pp2_buff_inf binf = {
1283 .addr = rte_mbuf_data_dma_addr_default(mbuf),
1284 .cookie = (pp2_cookie_t)(uint64_t)mbuf,
1287 pp2_bpool_put_buff(hifs[core_id], bpool, &binf);
1288 mrvl_port_bpool_size
1289 [bpool->pp2_id][bpool->id][core_id]++;
1293 mbuf->data_off += MRVL_PKT_EFFEC_OFFS;
1294 mbuf->pkt_len = pp2_ppio_inq_desc_get_pkt_len(&descs[i]);
1295 mbuf->data_len = mbuf->pkt_len;
1296 mbuf->port = q->port_id;
1298 rx_pkts[rx_done++] = mbuf;
1301 if (rte_spinlock_trylock(&q->priv->lock) == 1) {
1302 num = mrvl_get_bpool_size(bpool->pp2_id, bpool->id);
1304 if (unlikely(num <= q->priv->bpool_min_size ||
1305 (!rx_done && num < q->priv->bpool_init_size))) {
1306 ret = mrvl_fill_bpool(q, MRVL_BURST_SIZE);
1308 RTE_LOG(ERR, PMD, "Failed to fill bpool\n");
1309 } else if (unlikely(num > q->priv->bpool_max_size)) {
1311 int pkt_to_remove = num - q->priv->bpool_init_size;
1312 struct rte_mbuf *mbuf;
1313 struct pp2_buff_inf buff;
1316 "\nport-%d:%d: bpool %d oversize - remove %d buffers (pool size: %d -> %d)\n",
1317 bpool->pp2_id, q->priv->ppio->port_id,
1318 bpool->id, pkt_to_remove, num,
1319 q->priv->bpool_init_size);
1321 for (i = 0; i < pkt_to_remove; i++) {
1322 pp2_bpool_get_buff(hifs[core_id], bpool, &buff);
1323 mbuf = (struct rte_mbuf *)
1324 (cookie_addr_high | buff.cookie);
1325 rte_pktmbuf_free(mbuf);
1327 mrvl_port_bpool_size
1328 [bpool->pp2_id][bpool->id][core_id] -=
1331 rte_spinlock_unlock(&q->priv->lock);
1338 * Release already sent buffers to bpool (buffer-pool).
1341 * Pointer to the port structure.
1343 * Pointer to the MUSDK hardware interface.
1345 * Pointer to the shadow queue.
1349 * Force releasing packets.
1352 mrvl_free_sent_buffers(struct pp2_ppio *ppio, struct pp2_hif *hif,
1353 struct mrvl_shadow_txq *sq, int qid, int force)
1355 struct buff_release_entry *entry;
1356 uint16_t nb_done = 0, num = 0, skip_bufs = 0;
1357 int i, core_id = rte_lcore_id();
1359 pp2_ppio_get_num_outq_done(ppio, hif, qid, &nb_done);
1361 sq->num_to_release += nb_done;
1363 if (likely(!force &&
1364 sq->num_to_release < MRVL_PP2_BUF_RELEASE_BURST_SIZE))
1367 nb_done = sq->num_to_release;
1368 sq->num_to_release = 0;
1370 for (i = 0; i < nb_done; i++) {
1371 entry = &sq->ent[sq->tail + num];
1372 if (unlikely(!entry->buff.addr)) {
1374 "Shadow memory @%d: cookie(%lx), pa(%lx)!\n",
1375 sq->tail, (u64)entry->buff.cookie,
1376 (u64)entry->buff.addr);
1381 if (unlikely(!entry->bpool)) {
1382 struct rte_mbuf *mbuf;
1384 mbuf = (struct rte_mbuf *)
1385 (cookie_addr_high | entry->buff.cookie);
1386 rte_pktmbuf_free(mbuf);
1391 mrvl_port_bpool_size
1392 [entry->bpool->pp2_id][entry->bpool->id][core_id]++;
1394 if (unlikely(sq->tail + num == MRVL_PP2_TX_SHADOWQ_SIZE))
1399 pp2_bpool_put_buffs(hif, &sq->ent[sq->tail], &num);
1401 sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK;
1407 pp2_bpool_put_buffs(hif, &sq->ent[sq->tail], &num);
1408 sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK;
1414 * DPDK callback for transmit.
1417 * Generic pointer transmit queue.
1419 * Packets to transmit.
1421 * Number of packets in array.
1424 * Number of packets successfully transmitted.
1427 mrvl_tx_pkt_burst(void *txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1429 struct mrvl_txq *q = txq;
1430 struct mrvl_shadow_txq *sq = &shadow_txqs[q->port_id][rte_lcore_id()];
1431 struct pp2_hif *hif = hifs[rte_lcore_id()];
1432 struct pp2_ppio_desc descs[nb_pkts];
1434 uint16_t num, sq_free_size;
1436 if (unlikely(!q->priv->ppio))
1440 mrvl_free_sent_buffers(q->priv->ppio, hif, sq, q->queue_id, 0);
1442 sq_free_size = MRVL_PP2_TX_SHADOWQ_SIZE - sq->size - 1;
1443 if (unlikely(nb_pkts > sq_free_size)) {
1445 "No room in shadow queue for %d packets! %d packets will be sent.\n",
1446 nb_pkts, sq_free_size);
1447 nb_pkts = sq_free_size;
1450 for (i = 0; i < nb_pkts; i++) {
1451 struct rte_mbuf *mbuf = tx_pkts[i];
1453 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) {
1454 struct rte_mbuf *pref_pkt_hdr;
1456 pref_pkt_hdr = tx_pkts[i + MRVL_MUSDK_PREFETCH_SHIFT];
1457 rte_mbuf_prefetch_part1(pref_pkt_hdr);
1458 rte_mbuf_prefetch_part2(pref_pkt_hdr);
1461 sq->ent[sq->head].buff.cookie = (pp2_cookie_t)(uint64_t)mbuf;
1462 sq->ent[sq->head].buff.addr =
1463 rte_mbuf_data_dma_addr_default(mbuf);
1464 sq->ent[sq->head].bpool =
1465 (unlikely(mbuf->port == 0xff || mbuf->refcnt > 1)) ?
1466 NULL : mrvl_port_to_bpool_lookup[mbuf->port];
1467 sq->head = (sq->head + 1) & MRVL_PP2_TX_SHADOWQ_MASK;
1470 pp2_ppio_outq_desc_reset(&descs[i]);
1471 pp2_ppio_outq_desc_set_phys_addr(&descs[i],
1472 rte_pktmbuf_mtophys(mbuf));
1473 pp2_ppio_outq_desc_set_pkt_offset(&descs[i], 0);
1474 pp2_ppio_outq_desc_set_pkt_len(&descs[i],
1475 rte_pktmbuf_pkt_len(mbuf));
1479 pp2_ppio_send(q->priv->ppio, hif, q->queue_id, descs, &nb_pkts);
1480 /* number of packets that were not sent */
1481 if (unlikely(num > nb_pkts)) {
1482 for (i = nb_pkts; i < num; i++) {
1483 sq->head = (MRVL_PP2_TX_SHADOWQ_SIZE + sq->head - 1) &
1484 MRVL_PP2_TX_SHADOWQ_MASK;
1486 sq->size -= num - nb_pkts;
1493 * Initialize packet processor.
1496 * 0 on success, negative error value otherwise.
1501 struct pp2_init_params init_params;
1503 memset(&init_params, 0, sizeof(init_params));
1504 init_params.hif_reserved_map = MRVL_MUSDK_HIFS_RESERVED;
1505 init_params.bm_pool_reserved_map = MRVL_MUSDK_BPOOLS_RESERVED;
1506 init_params.rss_tbl_reserved_map = MRVL_MUSDK_RSS_RESERVED;
1508 return pp2_init(&init_params);
1512 * Deinitialize packet processor.
1515 * 0 on success, negative error value otherwise.
1518 mrvl_deinit_pp2(void)
1524 * Create private device structure.
1527 * Pointer to the port name passed in the initialization parameters.
1530 * Pointer to the newly allocated private device structure.
1532 static struct mrvl_priv *
1533 mrvl_priv_create(const char *dev_name)
1535 struct pp2_bpool_params bpool_params;
1536 char match[MRVL_MATCH_LEN];
1537 struct mrvl_priv *priv;
1540 priv = rte_zmalloc_socket(dev_name, sizeof(*priv), 0, rte_socket_id());
1544 ret = pp2_netdev_get_ppio_info((char *)(uintptr_t)dev_name,
1545 &priv->pp_id, &priv->ppio_id);
1549 bpool_bit = mrvl_reserve_bit(&used_bpools[priv->pp_id],
1550 PP2_BPOOL_NUM_POOLS);
1553 priv->bpool_bit = bpool_bit;
1555 snprintf(match, sizeof(match), "pool-%d:%d", priv->pp_id,
1557 memset(&bpool_params, 0, sizeof(bpool_params));
1558 bpool_params.match = match;
1559 bpool_params.buff_len = MRVL_PKT_SIZE_MAX + MRVL_PKT_EFFEC_OFFS;
1560 ret = pp2_bpool_init(&bpool_params, &priv->bpool);
1562 goto out_clear_bpool_bit;
1564 priv->ppio_params.type = PP2_PPIO_T_NIC;
1565 rte_spinlock_init(&priv->lock);
1568 out_clear_bpool_bit:
1569 used_bpools[priv->pp_id] &= ~(1 << priv->bpool_bit);
1576 * Create device representing Ethernet port.
1579 * Pointer to the port's name.
1582 * 0 on success, negative error value otherwise.
1585 mrvl_eth_dev_create(struct rte_vdev_device *vdev, const char *name)
1587 int ret, fd = socket(AF_INET, SOCK_DGRAM, 0);
1588 struct rte_eth_dev *eth_dev;
1589 struct mrvl_priv *priv;
1592 eth_dev = rte_eth_dev_allocate(name);
1596 priv = mrvl_priv_create(name);
1602 eth_dev->data->mac_addrs =
1603 rte_zmalloc("mac_addrs",
1604 ETHER_ADDR_LEN * MRVL_MAC_ADDRS_MAX, 0);
1605 if (!eth_dev->data->mac_addrs) {
1606 RTE_LOG(ERR, PMD, "Failed to allocate space for eth addrs\n");
1611 memset(&req, 0, sizeof(req));
1612 strcpy(req.ifr_name, name);
1613 ret = ioctl(fd, SIOCGIFHWADDR, &req);
1617 memcpy(eth_dev->data->mac_addrs[0].addr_bytes,
1618 req.ifr_addr.sa_data, ETHER_ADDR_LEN);
1620 eth_dev->rx_pkt_burst = mrvl_rx_pkt_burst;
1621 eth_dev->tx_pkt_burst = mrvl_tx_pkt_burst;
1622 eth_dev->data->dev_private = priv;
1623 eth_dev->device = &vdev->device;
1624 eth_dev->dev_ops = &mrvl_ops;
1628 rte_free(eth_dev->data->mac_addrs);
1630 rte_eth_dev_release_port(eth_dev);
1638 * Cleanup previously created device representing Ethernet port.
1641 * Pointer to the port name.
1644 mrvl_eth_dev_destroy(const char *name)
1646 struct rte_eth_dev *eth_dev;
1647 struct mrvl_priv *priv;
1649 eth_dev = rte_eth_dev_allocated(name);
1653 priv = eth_dev->data->dev_private;
1654 pp2_bpool_deinit(priv->bpool);
1656 rte_free(eth_dev->data->mac_addrs);
1657 rte_eth_dev_release_port(eth_dev);
1661 * Callback used by rte_kvargs_process() during argument parsing.
1664 * Pointer to the parsed key (unused).
1666 * Pointer to the parsed value.
1668 * Pointer to the extra arguments which contains address of the
1669 * table of pointers to parsed interface names.
1675 mrvl_get_ifnames(const char *key __rte_unused, const char *value,
1678 const char **ifnames = extra_args;
1680 ifnames[mrvl_ports_nb++] = value;
1686 * Initialize per-lcore MUSDK hardware interfaces (hifs).
1689 * 0 on success, negative error value otherwise.
1692 mrvl_init_hifs(void)
1694 struct pp2_hif_params params;
1695 char match[MRVL_MATCH_LEN];
1698 RTE_LCORE_FOREACH(i) {
1699 ret = mrvl_reserve_bit(&used_hifs, MRVL_MUSDK_HIFS_MAX);
1703 snprintf(match, sizeof(match), "hif-%d", ret);
1704 memset(¶ms, 0, sizeof(params));
1705 params.match = match;
1706 params.out_size = MRVL_PP2_AGGR_TXQD_MAX;
1707 ret = pp2_hif_init(¶ms, &hifs[i]);
1709 RTE_LOG(ERR, PMD, "Failed to initialize hif %d\n", i);
1718 * Deinitialize per-lcore MUSDK hardware interfaces (hifs).
1721 mrvl_deinit_hifs(void)
1725 RTE_LCORE_FOREACH(i) {
1727 pp2_hif_deinit(hifs[i]);
1731 static void mrvl_set_first_last_cores(int core_id)
1733 if (core_id < mrvl_lcore_first)
1734 mrvl_lcore_first = core_id;
1736 if (core_id > mrvl_lcore_last)
1737 mrvl_lcore_last = core_id;
1741 * DPDK callback to register the virtual device.
1744 * Pointer to the virtual device.
1747 * 0 on success, negative error value otherwise.
1750 rte_pmd_mrvl_probe(struct rte_vdev_device *vdev)
1752 struct rte_kvargs *kvlist;
1753 const char *ifnames[PP2_NUM_ETH_PPIO * PP2_NUM_PKT_PROC];
1755 uint32_t i, ifnum, cfgnum, core_id;
1758 params = rte_vdev_device_args(vdev);
1762 kvlist = rte_kvargs_parse(params, valid_args);
1766 ifnum = rte_kvargs_count(kvlist, MRVL_IFACE_NAME_ARG);
1767 if (ifnum > RTE_DIM(ifnames))
1768 goto out_free_kvlist;
1770 rte_kvargs_process(kvlist, MRVL_IFACE_NAME_ARG,
1771 mrvl_get_ifnames, &ifnames);
1773 cfgnum = rte_kvargs_count(kvlist, MRVL_CFG_ARG);
1775 RTE_LOG(ERR, PMD, "Cannot handle more than one config file!\n");
1776 goto out_free_kvlist;
1777 } else if (cfgnum == 1) {
1778 rte_kvargs_process(kvlist, MRVL_CFG_ARG,
1779 mrvl_get_qoscfg, &mrvl_qos_cfg);
1783 * ret == -EEXIST is correct, it means DMA
1784 * has been already initialized (by another PMD).
1786 ret = mv_sys_dma_mem_init(RTE_MRVL_MUSDK_DMA_MEMSIZE);
1787 if (ret < 0 && ret != -EEXIST)
1788 goto out_free_kvlist;
1790 ret = mrvl_init_pp2();
1792 RTE_LOG(ERR, PMD, "Failed to init PP!\n");
1793 goto out_deinit_dma;
1796 ret = mrvl_init_hifs();
1798 goto out_deinit_hifs;
1800 for (i = 0; i < ifnum; i++) {
1801 RTE_LOG(INFO, PMD, "Creating %s\n", ifnames[i]);
1802 ret = mrvl_eth_dev_create(vdev, ifnames[i]);
1807 rte_kvargs_free(kvlist);
1809 memset(mrvl_port_bpool_size, 0, sizeof(mrvl_port_bpool_size));
1811 mrvl_lcore_first = RTE_MAX_LCORE;
1812 mrvl_lcore_last = 0;
1814 RTE_LCORE_FOREACH(core_id) {
1815 mrvl_set_first_last_cores(core_id);
1821 mrvl_eth_dev_destroy(ifnames[i]);
1826 mv_sys_dma_mem_destroy();
1828 rte_kvargs_free(kvlist);
1834 * DPDK callback to remove virtual device.
1837 * Pointer to the removed virtual device.
1840 * 0 on success, negative error value otherwise.
1843 rte_pmd_mrvl_remove(struct rte_vdev_device *vdev)
1848 name = rte_vdev_device_name(vdev);
1852 RTE_LOG(INFO, PMD, "Removing %s\n", name);
1854 for (i = 0; i < rte_eth_dev_count(); i++) {
1855 char ifname[RTE_ETH_NAME_MAX_LEN];
1857 rte_eth_dev_get_name_by_port(i, ifname);
1858 mrvl_eth_dev_destroy(ifname);
1863 mv_sys_dma_mem_destroy();
1868 static struct rte_vdev_driver pmd_mrvl_drv = {
1869 .probe = rte_pmd_mrvl_probe,
1870 .remove = rte_pmd_mrvl_remove,
1873 RTE_PMD_REGISTER_VDEV(net_mrvl, pmd_mrvl_drv);
1874 RTE_PMD_REGISTER_ALIAS(net_mrvl, eth_mrvl);