drivers/net/mrvl/mrvl_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2017 Marvell International Ltd.
   5  *   Copyright(c) 2017 Semihalf.
   6  *   All rights reserved.
   7  *
   8  *   Redistribution and use in source and binary forms, with or without
   9  *   modification, are permitted provided that the following conditions
  10  *   are met:
  11  *
  12  *     * Redistributions of source code must retain the above copyright
  13  *       notice, this list of conditions and the following disclaimer.
  14  *     * Redistributions in binary form must reproduce the above copyright
  15  *       notice, this list of conditions and the following disclaimer in
  16  *       the documentation and/or other materials provided with the
  17  *       distribution.
  18  *     * Neither the name of Semihalf nor the names of its
  19  *       contributors may be used to endorse or promote products derived
  20  *       from this software without specific prior written permission.
  21  *
  22  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  23  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  24  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  25  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  26  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  27  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  28  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  29  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  30  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  32  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33  */
  34
  35 #include <rte_ethdev.h>
  36 #include <rte_kvargs.h>
  37 #include <rte_log.h>
  38 #include <rte_malloc.h>
  39 #include <rte_bus_vdev.h>
  40
  41 /* Unluckily, container_of is defined by both DPDK and MUSDK,
  42  * we'll declare only one version.
  43  *
  44  * Note that it is not used in this PMD anyway.
  45  */
  46 #ifdef container_of
  47 #undef container_of
  48 #endif
  49
  50 #include <fcntl.h>
  51 #include <linux/ethtool.h>
  52 #include <linux/sockios.h>
  53 #include <net/if.h>
  54 #include <net/if_arp.h>
  55 #include <sys/ioctl.h>
  56 #include <sys/socket.h>
  57 #include <sys/stat.h>
  58 #include <sys/types.h>
  59
  60 #include "mrvl_ethdev.h"
  61 #include "mrvl_qos.h"
  62
  63 /* bitmask with reserved hifs */
  64 #define MRVL_MUSDK_HIFS_RESERVED 0x0F
  65 /* bitmask with reserved bpools */
  66 #define MRVL_MUSDK_BPOOLS_RESERVED 0x07
  67 /* bitmask with reserved kernel RSS tables */
  68 #define MRVL_MUSDK_RSS_RESERVED 0x01
  69 /* maximum number of available hifs */
  70 #define MRVL_MUSDK_HIFS_MAX 9
  71
  72 /* prefetch shift */
  73 #define MRVL_MUSDK_PREFETCH_SHIFT 2
  74
  75 /* TCAM has 25 entries reserved for uc/mc filter entries */
  76 #define MRVL_MAC_ADDRS_MAX 25
  77 #define MRVL_MATCH_LEN 16
  78 #define MRVL_PKT_EFFEC_OFFS (MRVL_PKT_OFFS + MV_MH_SIZE)
  79 /* Maximum allowable packet size */
  80 #define MRVL_PKT_SIZE_MAX (10240 - MV_MH_SIZE)
  81
  82 #define MRVL_IFACE_NAME_ARG "iface"
  83 #define MRVL_CFG_ARG "cfg"
  84
  85 #define MRVL_BURST_SIZE 64
  86
  87 #define MRVL_ARP_LENGTH 28
  88
  89 #define MRVL_COOKIE_ADDR_INVALID ~0ULL
  90
  91 #define MRVL_COOKIE_HIGH_ADDR_SHIFT     (sizeof(pp2_cookie_t) * 8)
  92 #define MRVL_COOKIE_HIGH_ADDR_MASK      (~0ULL << MRVL_COOKIE_HIGH_ADDR_SHIFT)
  93
  94 /* Memory size (in bytes) for MUSDK dma buffers */
  95 #define MRVL_MUSDK_DMA_MEMSIZE 41943040
  96
  97 static const char * const valid_args[] = {
  98         MRVL_IFACE_NAME_ARG,
  99         MRVL_CFG_ARG,
 100         NULL
 101 };
 102
 103 static int used_hifs = MRVL_MUSDK_HIFS_RESERVED;
 104 static struct pp2_hif *hifs[RTE_MAX_LCORE];
 105 static int used_bpools[PP2_NUM_PKT_PROC] = {
 106         MRVL_MUSDK_BPOOLS_RESERVED,
 107         MRVL_MUSDK_BPOOLS_RESERVED
 108 };
 109
 110 struct pp2_bpool *mrvl_port_to_bpool_lookup[RTE_MAX_ETHPORTS];
 111 int mrvl_port_bpool_size[PP2_NUM_PKT_PROC][PP2_BPOOL_NUM_POOLS][RTE_MAX_LCORE];
 112 uint64_t cookie_addr_high = MRVL_COOKIE_ADDR_INVALID;
 113
 114 /*
 115  * To use buffer harvesting based on loopback port shadow queue structure
 116  * was introduced for buffers information bookkeeping.
 117  *
 118  * Before sending the packet, related buffer information (pp2_buff_inf) is
 119  * stored in shadow queue. After packet is transmitted no longer used
 120  * packet buffer is released back to it's original hardware pool,
 121  * on condition it originated from interface.
 122  * In case it  was generated by application itself i.e: mbuf->port field is
 123  * 0xff then its released to software mempool.
 124  */
 125 struct mrvl_shadow_txq {
 126         int head;           /* write index - used when sending buffers */
 127         int tail;           /* read index - used when releasing buffers */
 128         u16 size;           /* queue occupied size */
 129         u16 num_to_release; /* number of buffers sent, that can be released */
 130         struct buff_release_entry ent[MRVL_PP2_TX_SHADOWQ_SIZE]; /* q entries */
 131 };
 132
 133 struct mrvl_rxq {
 134         struct mrvl_priv *priv;
 135         struct rte_mempool *mp;
 136         int queue_id;
 137         int port_id;
 138         int cksum_enabled;
 139         uint64_t bytes_recv;
 140         uint64_t drop_mac;
 141 };
 142
 143 struct mrvl_txq {
 144         struct mrvl_priv *priv;
 145         int queue_id;
 146         int port_id;
 147         uint64_t bytes_sent;
 148 };
 149
 150 /*
 151  * Every tx queue should have dedicated shadow tx queue.
 152  *
 153  * Ports assigned by DPDK might not start at zero or be continuous so
 154  * as a workaround define shadow queues for each possible port so that
 155  * we eventually fit somewhere.
 156  */
 157 struct mrvl_shadow_txq shadow_txqs[RTE_MAX_ETHPORTS][RTE_MAX_LCORE];
 158
 159 /** Number of ports configured. */
 160 int mrvl_ports_nb;
 161 static int mrvl_lcore_first;
 162 static int mrvl_lcore_last;
 163
 164 static inline int
 165 mrvl_get_bpool_size(int pp2_id, int pool_id)
 166 {
 167         int i;
 168         int size = 0;
 169
 170         for (i = mrvl_lcore_first; i <= mrvl_lcore_last; i++)
 171                 size += mrvl_port_bpool_size[pp2_id][pool_id][i];
 172
 173         return size;
 174 }
 175
 176 static inline int
 177 mrvl_reserve_bit(int *bitmap, int max)
 178 {
 179         int n = sizeof(*bitmap) * 8 - __builtin_clz(*bitmap);
 180
 181         if (n >= max)
 182                 return -1;
 183
 184         *bitmap |= 1 << n;
 185
 186         return n;
 187 }
 188
 189 /**
 190  * Configure rss based on dpdk rss configuration.
 191  *
 192  * @param priv
 193  *   Pointer to private structure.
 194  * @param rss_conf
 195  *   Pointer to RSS configuration.
 196  *
 197  * @return
 198  *   0 on success, negative error value otherwise.
 199  */
 200 static int
 201 mrvl_configure_rss(struct mrvl_priv *priv, struct rte_eth_rss_conf *rss_conf)
 202 {
 203         if (rss_conf->rss_key)
 204                 RTE_LOG(WARNING, PMD, "Changing hash key is not supported\n");
 205
 206         if (rss_conf->rss_hf == 0) {
 207                 priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE;
 208         } else if (rss_conf->rss_hf & ETH_RSS_IPV4) {
 209                 priv->ppio_params.inqs_params.hash_type =
 210                         PP2_PPIO_HASH_T_2_TUPLE;
 211         } else if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) {
 212                 priv->ppio_params.inqs_params.hash_type =
 213                         PP2_PPIO_HASH_T_5_TUPLE;
 214                 priv->rss_hf_tcp = 1;
 215         } else if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) {
 216                 priv->ppio_params.inqs_params.hash_type =
 217                         PP2_PPIO_HASH_T_5_TUPLE;
 218                 priv->rss_hf_tcp = 0;
 219         } else {
 220                 return -EINVAL;
 221         }
 222
 223         return 0;
 224 }
 225
 226 /**
 227  * Ethernet device configuration.
 228  *
 229  * Prepare the driver for a given number of TX and RX queues and
 230  * configure RSS.
 231  *
 232  * @param dev
 233  *   Pointer to Ethernet device structure.
 234  *
 235  * @return
 236  *   0 on success, negative error value otherwise.
 237  */
 238 static int
 239 mrvl_dev_configure(struct rte_eth_dev *dev)
 240 {
 241         struct mrvl_priv *priv = dev->data->dev_private;
 242         int ret;
 243
 244         if (dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_NONE &&
 245             dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) {
 246                 RTE_LOG(INFO, PMD, "Unsupported rx multi queue mode %d\n",
 247                         dev->data->dev_conf.rxmode.mq_mode);
 248                 return -EINVAL;
 249         }
 250
 251         if (!dev->data->dev_conf.rxmode.hw_strip_crc) {
 252                 RTE_LOG(INFO, PMD,
 253                         "L2 CRC stripping is always enabled in hw\n");
 254                 dev->data->dev_conf.rxmode.hw_strip_crc = 1;
 255         }
 256
 257         if (dev->data->dev_conf.rxmode.hw_vlan_strip) {
 258                 RTE_LOG(INFO, PMD, "VLAN stripping not supported\n");
 259                 return -EINVAL;
 260         }
 261
 262         if (dev->data->dev_conf.rxmode.split_hdr_size) {
 263                 RTE_LOG(INFO, PMD, "Split headers not supported\n");
 264                 return -EINVAL;
 265         }
 266
 267         if (dev->data->dev_conf.rxmode.enable_scatter) {
 268                 RTE_LOG(INFO, PMD, "RX Scatter/Gather not supported\n");
 269                 return -EINVAL;
 270         }
 271
 272         if (dev->data->dev_conf.rxmode.enable_lro) {
 273                 RTE_LOG(INFO, PMD, "LRO not supported\n");
 274                 return -EINVAL;
 275         }
 276
 277         if (dev->data->dev_conf.rxmode.jumbo_frame)
 278                 dev->data->mtu = dev->data->dev_conf.rxmode.max_rx_pkt_len -
 279                                  ETHER_HDR_LEN - ETHER_CRC_LEN;
 280
 281         ret = mrvl_configure_rxqs(priv, dev->data->port_id,
 282                                   dev->data->nb_rx_queues);
 283         if (ret < 0)
 284                 return ret;
 285
 286         priv->ppio_params.outqs_params.num_outqs = dev->data->nb_tx_queues;
 287         priv->ppio_params.maintain_stats = 1;
 288         priv->nb_rx_queues = dev->data->nb_rx_queues;
 289
 290         if (dev->data->nb_rx_queues == 1 &&
 291             dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) {
 292                 RTE_LOG(WARNING, PMD, "Disabling hash for 1 rx queue\n");
 293                 priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE;
 294
 295                 return 0;
 296         }
 297
 298         return mrvl_configure_rss(priv,
 299                                   &dev->data->dev_conf.rx_adv_conf.rss_conf);
 300 }
 301
 302 /**
 303  * DPDK callback to change the MTU.
 304  *
 305  * Setting the MTU affects hardware MRU (packets larger than the MRU
 306  * will be dropped).
 307  *
 308  * @param dev
 309  *   Pointer to Ethernet device structure.
 310  * @param mtu
 311  *   New MTU.
 312  *
 313  * @return
 314  *   0 on success, negative error value otherwise.
 315  */
 316 static int
 317 mrvl_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 318 {
 319         struct mrvl_priv *priv = dev->data->dev_private;
 320         /* extra MV_MH_SIZE bytes are required for Marvell tag */
 321         uint16_t mru = mtu + MV_MH_SIZE + ETHER_HDR_LEN + ETHER_CRC_LEN;
 322         int ret;
 323
 324         if (mtu < ETHER_MIN_MTU || mru > MRVL_PKT_SIZE_MAX)
 325                 return -EINVAL;
 326
 327         ret = pp2_ppio_set_mru(priv->ppio, mru);
 328         if (ret)
 329                 return ret;
 330
 331         return pp2_ppio_set_mtu(priv->ppio, mtu);
 332 }
 333
 334 /**
 335  * DPDK callback to bring the link up.
 336  *
 337  * @param dev
 338  *   Pointer to Ethernet device structure.
 339  *
 340  * @return
 341  *   0 on success, negative error value otherwise.
 342  */
 343 static int
 344 mrvl_dev_set_link_up(struct rte_eth_dev *dev)
 345 {
 346         struct mrvl_priv *priv = dev->data->dev_private;
 347         int ret;
 348
 349         ret = pp2_ppio_enable(priv->ppio);
 350         if (ret)
 351                 return ret;
 352
 353         /*
 354          * mtu/mru can be updated if pp2_ppio_enable() was called at least once
 355          * as pp2_ppio_enable() changes port->t_mode from default 0 to
 356          * PP2_TRAFFIC_INGRESS_EGRESS.
 357          *
 358          * Set mtu to default DPDK value here.
 359          */
 360         ret = mrvl_mtu_set(dev, dev->data->mtu);
 361         if (ret)
 362                 pp2_ppio_disable(priv->ppio);
 363
 364         return ret;
 365 }
 366
 367 /**
 368  * DPDK callback to bring the link down.
 369  *
 370  * @param dev
 371  *   Pointer to Ethernet device structure.
 372  *
 373  * @return
 374  *   0 on success, negative error value otherwise.
 375  */
 376 static int
 377 mrvl_dev_set_link_down(struct rte_eth_dev *dev)
 378 {
 379         struct mrvl_priv *priv = dev->data->dev_private;
 380
 381         return pp2_ppio_disable(priv->ppio);
 382 }
 383
 384 /**
 385  * DPDK callback to start the device.
 386  *
 387  * @param dev
 388  *   Pointer to Ethernet device structure.
 389  *
 390  * @return
 391  *   0 on success, negative errno value on failure.
 392  */
 393 static int
 394 mrvl_dev_start(struct rte_eth_dev *dev)
 395 {
 396         struct mrvl_priv *priv = dev->data->dev_private;
 397         char match[MRVL_MATCH_LEN];
 398         int ret;
 399
 400         snprintf(match, sizeof(match), "ppio-%d:%d",
 401                  priv->pp_id, priv->ppio_id);
 402         priv->ppio_params.match = match;
 403
 404         /*
 405          * Calculate the maximum bpool size for refill feature to 1.5 of the
 406          * configured size. In case the bpool size will exceed this value,
 407          * superfluous buffers will be removed
 408          */
 409         priv->bpool_max_size = priv->bpool_init_size +
 410                               (priv->bpool_init_size >> 1);
 411         /*
 412          * Calculate the minimum bpool size for refill feature as follows:
 413          * 2 default burst sizes multiply by number of rx queues.
 414          * If the bpool size will be below this value, new buffers will
 415          * be added to the pool.
 416          */
 417         priv->bpool_min_size = priv->nb_rx_queues * MRVL_BURST_SIZE * 2;
 418
 419         ret = pp2_ppio_init(&priv->ppio_params, &priv->ppio);
 420         if (ret)
 421                 return ret;
 422
 423         /*
 424          * In case there are some some stale uc/mc mac addresses flush them
 425          * here. It cannot be done during mrvl_dev_close() as port information
 426          * is already gone at that point (due to pp2_ppio_deinit() in
 427          * mrvl_dev_stop()).
 428          */
 429         if (!priv->uc_mc_flushed) {
 430                 ret = pp2_ppio_flush_mac_addrs(priv->ppio, 1, 1);
 431                 if (ret) {
 432                         RTE_LOG(ERR, PMD,
 433                                 "Failed to flush uc/mc filter list\n");
 434                         goto out;
 435                 }
 436                 priv->uc_mc_flushed = 1;
 437         }
 438
 439         if (!priv->vlan_flushed) {
 440                 ret = pp2_ppio_flush_vlan(priv->ppio);
 441                 if (ret) {
 442                         RTE_LOG(ERR, PMD, "Failed to flush vlan list\n");
 443                         /*
 444                          * TODO
 445                          * once pp2_ppio_flush_vlan() is supported jump to out
 446                          * goto out;
 447                          */
 448                 }
 449                 priv->vlan_flushed = 1;
 450         }
 451
 452         /* For default QoS config, don't start classifier. */
 453         if (mrvl_qos_cfg) {
 454                 ret = mrvl_start_qos_mapping(priv);
 455                 if (ret) {
 456                         pp2_ppio_deinit(priv->ppio);
 457                         return ret;
 458                 }
 459         }
 460
 461         ret = mrvl_dev_set_link_up(dev);
 462         if (ret)
 463                 goto out;
 464
 465         return 0;
 466 out:
 467         pp2_ppio_deinit(priv->ppio);
 468         return ret;
 469 }
 470
 471 /**
 472  * Flush receive queues.
 473  *
 474  * @param dev
 475  *   Pointer to Ethernet device structure.
 476  */
 477 static void
 478 mrvl_flush_rx_queues(struct rte_eth_dev *dev)
 479 {
 480         int i;
 481
 482         RTE_LOG(INFO, PMD, "Flushing rx queues\n");
 483         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 484                 int ret, num;
 485
 486                 do {
 487                         struct mrvl_rxq *q = dev->data->rx_queues[i];
 488                         struct pp2_ppio_desc descs[MRVL_PP2_RXD_MAX];
 489
 490                         num = MRVL_PP2_RXD_MAX;
 491                         ret = pp2_ppio_recv(q->priv->ppio,
 492                                             q->priv->rxq_map[q->queue_id].tc,
 493                                             q->priv->rxq_map[q->queue_id].inq,
 494                                             descs, (uint16_t *)&num);
 495                 } while (ret == 0 && num);
 496         }
 497 }
 498
 499 /**
 500  * Flush transmit shadow queues.
 501  *
 502  * @param dev
 503  *   Pointer to Ethernet device structure.
 504  */
 505 static void
 506 mrvl_flush_tx_shadow_queues(struct rte_eth_dev *dev)
 507 {
 508         int i;
 509
 510         RTE_LOG(INFO, PMD, "Flushing tx shadow queues\n");
 511         for (i = 0; i < RTE_MAX_LCORE; i++) {
 512                 struct mrvl_shadow_txq *sq =
 513                         &shadow_txqs[dev->data->port_id][i];
 514
 515                 while (sq->tail != sq->head) {
 516                         uint64_t addr = cookie_addr_high |
 517                                         sq->ent[sq->tail].buff.cookie;
 518                         rte_pktmbuf_free((struct rte_mbuf *)addr);
 519                         sq->tail = (sq->tail + 1) & MRVL_PP2_TX_SHADOWQ_MASK;
 520                 }
 521
 522                 memset(sq, 0, sizeof(*sq));
 523         }
 524 }
 525
 526 /**
 527  * Flush hardware bpool (buffer-pool).
 528  *
 529  * @param dev
 530  *   Pointer to Ethernet device structure.
 531  */
 532 static void
 533 mrvl_flush_bpool(struct rte_eth_dev *dev)
 534 {
 535         struct mrvl_priv *priv = dev->data->dev_private;
 536         uint32_t num;
 537         int ret;
 538
 539         ret = pp2_bpool_get_num_buffs(priv->bpool, &num);
 540         if (ret) {
 541                 RTE_LOG(ERR, PMD, "Failed to get bpool buffers number\n");
 542                 return;
 543         }
 544
 545         while (num--) {
 546                 struct pp2_buff_inf inf;
 547                 uint64_t addr;
 548
 549                 ret = pp2_bpool_get_buff(hifs[rte_lcore_id()], priv->bpool,
 550                                          &inf);
 551                 if (ret)
 552                         break;
 553
 554                 addr = cookie_addr_high | inf.cookie;
 555                 rte_pktmbuf_free((struct rte_mbuf *)addr);
 556         }
 557 }
 558
 559 /**
 560  * DPDK callback to stop the device.
 561  *
 562  * @param dev
 563  *   Pointer to Ethernet device structure.
 564  */
 565 static void
 566 mrvl_dev_stop(struct rte_eth_dev *dev)
 567 {
 568         struct mrvl_priv *priv = dev->data->dev_private;
 569
 570         mrvl_dev_set_link_down(dev);
 571         mrvl_flush_rx_queues(dev);
 572         mrvl_flush_tx_shadow_queues(dev);
 573         if (priv->qos_tbl)
 574                 pp2_cls_qos_tbl_deinit(priv->qos_tbl);
 575         pp2_ppio_deinit(priv->ppio);
 576         priv->ppio = NULL;
 577 }
 578
 579 /**
 580  * DPDK callback to close the device.
 581  *
 582  * @param dev
 583  *   Pointer to Ethernet device structure.
 584  */
 585 static void
 586 mrvl_dev_close(struct rte_eth_dev *dev)
 587 {
 588         struct mrvl_priv *priv = dev->data->dev_private;
 589         size_t i;
 590
 591         for (i = 0; i < priv->ppio_params.inqs_params.num_tcs; ++i) {
 592                 struct pp2_ppio_tc_params *tc_params =
 593                         &priv->ppio_params.inqs_params.tcs_params[i];
 594
 595                 if (tc_params->inqs_params) {
 596                         rte_free(tc_params->inqs_params);
 597                         tc_params->inqs_params = NULL;
 598                 }
 599         }
 600
 601         mrvl_flush_bpool(dev);
 602 }
 603
 604 /**
 605  * DPDK callback to retrieve physical link information.
 606  *
 607  * @param dev
 608  *   Pointer to Ethernet device structure.
 609  * @param wait_to_complete
 610  *   Wait for request completion (ignored).
 611  *
 612  * @return
 613  *   0 on success, negative error value otherwise.
 614  */
 615 static int
 616 mrvl_link_update(struct rte_eth_dev *dev, int wait_to_complete __rte_unused)
 617 {
 618         /*
 619          * TODO
 620          * once MUSDK provides necessary API use it here
 621          */
 622         struct mrvl_priv *priv = dev->data->dev_private;
 623         struct ethtool_cmd edata;
 624         struct ifreq req;
 625         int ret, fd, link_up;
 626
 627         edata.cmd = ETHTOOL_GSET;
 628
 629         strcpy(req.ifr_name, dev->data->name);
 630         req.ifr_data = (void *)&edata;
 631
 632         fd = socket(AF_INET, SOCK_DGRAM, 0);
 633         if (fd == -1)
 634                 return -EFAULT;
 635
 636         ret = ioctl(fd, SIOCETHTOOL, &req);
 637         if (ret == -1) {
 638                 close(fd);
 639                 return -EFAULT;
 640         }
 641
 642         close(fd);
 643
 644         switch (ethtool_cmd_speed(&edata)) {
 645         case SPEED_10:
 646                 dev->data->dev_link.link_speed = ETH_SPEED_NUM_10M;
 647                 break;
 648         case SPEED_100:
 649                 dev->data->dev_link.link_speed = ETH_SPEED_NUM_100M;
 650                 break;
 651         case SPEED_1000:
 652                 dev->data->dev_link.link_speed = ETH_SPEED_NUM_1G;
 653                 break;
 654         case SPEED_10000:
 655                 dev->data->dev_link.link_speed = ETH_SPEED_NUM_10G;
 656                 break;
 657         default:
 658                 dev->data->dev_link.link_speed = ETH_SPEED_NUM_NONE;
 659         }
 660
 661         dev->data->dev_link.link_duplex = edata.duplex ? ETH_LINK_FULL_DUPLEX :
 662                                                          ETH_LINK_HALF_DUPLEX;
 663         dev->data->dev_link.link_autoneg = edata.autoneg ? ETH_LINK_AUTONEG :
 664                                                            ETH_LINK_FIXED;
 665         pp2_ppio_get_link_state(priv->ppio, &link_up);
 666         dev->data->dev_link.link_status = link_up ? ETH_LINK_UP : ETH_LINK_DOWN;
 667
 668         return 0;
 669 }
 670
 671 /**
 672  * DPDK callback to enable promiscuous mode.
 673  *
 674  * @param dev
 675  *   Pointer to Ethernet device structure.
 676  */
 677 static void
 678 mrvl_promiscuous_enable(struct rte_eth_dev *dev)
 679 {
 680         struct mrvl_priv *priv = dev->data->dev_private;
 681         int ret;
 682
 683         ret = pp2_ppio_set_promisc(priv->ppio, 1);
 684         if (ret)
 685                 RTE_LOG(ERR, PMD, "Failed to enable promiscuous mode\n");
 686 }
 687
 688 /**
 689  * DPDK callback to enable allmulti mode.
 690  *
 691  * @param dev
 692  *   Pointer to Ethernet device structure.
 693  */
 694 static void
 695 mrvl_allmulticast_enable(struct rte_eth_dev *dev)
 696 {
 697         struct mrvl_priv *priv = dev->data->dev_private;
 698         int ret;
 699
 700         ret = pp2_ppio_set_mc_promisc(priv->ppio, 1);
 701         if (ret)
 702                 RTE_LOG(ERR, PMD, "Failed enable all-multicast mode\n");
 703 }
 704
 705 /**
 706  * DPDK callback to disable promiscuous mode.
 707  *
 708  * @param dev
 709  *   Pointer to Ethernet device structure.
 710  */
 711 static void
 712 mrvl_promiscuous_disable(struct rte_eth_dev *dev)
 713 {
 714         struct mrvl_priv *priv = dev->data->dev_private;
 715         int ret;
 716
 717         ret = pp2_ppio_set_promisc(priv->ppio, 0);
 718         if (ret)
 719                 RTE_LOG(ERR, PMD, "Failed to disable promiscuous mode\n");
 720 }
 721
 722 /**
 723  * DPDK callback to disable allmulticast mode.
 724  *
 725  * @param dev
 726  *   Pointer to Ethernet device structure.
 727  */
 728 static void
 729 mrvl_allmulticast_disable(struct rte_eth_dev *dev)
 730 {
 731         struct mrvl_priv *priv = dev->data->dev_private;
 732         int ret;
 733
 734         ret = pp2_ppio_set_mc_promisc(priv->ppio, 0);
 735         if (ret)
 736                 RTE_LOG(ERR, PMD, "Failed to disable all-multicast mode\n");
 737 }
 738
 739 /**
 740  * DPDK callback to remove a MAC address.
 741  *
 742  * @param dev
 743  *   Pointer to Ethernet device structure.
 744  * @param index
 745  *   MAC address index.
 746  */
 747 static void
 748 mrvl_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index)
 749 {
 750         struct mrvl_priv *priv = dev->data->dev_private;
 751         char buf[ETHER_ADDR_FMT_SIZE];
 752         int ret;
 753
 754         ret = pp2_ppio_remove_mac_addr(priv->ppio,
 755                                        dev->data->mac_addrs[index].addr_bytes);
 756         if (ret) {
 757                 ether_format_addr(buf, sizeof(buf),
 758                                   &dev->data->mac_addrs[index]);
 759                 RTE_LOG(ERR, PMD, "Failed to remove mac %s\n", buf);
 760         }
 761 }
 762
 763 /**
 764  * DPDK callback to add a MAC address.
 765  *
 766  * @param dev
 767  *   Pointer to Ethernet device structure.
 768  * @param mac_addr
 769  *   MAC address to register.
 770  * @param index
 771  *   MAC address index.
 772  * @param vmdq
 773  *   VMDq pool index to associate address with (unused).
 774  *
 775  * @return
 776  *   0 on success, negative error value otherwise.
 777  */
 778 static int
 779 mrvl_mac_addr_add(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 780                   uint32_t index, uint32_t vmdq __rte_unused)
 781 {
 782         struct mrvl_priv *priv = dev->data->dev_private;
 783         char buf[ETHER_ADDR_FMT_SIZE];
 784         int ret;
 785
 786         if (index == 0)
 787                 /* For setting index 0, mrvl_mac_addr_set() should be used.*/
 788                 return -1;
 789
 790         /*
 791          * Maximum number of uc addresses can be tuned via kernel module mvpp2x
 792          * parameter uc_filter_max. Maximum number of mc addresses is then
 793          * MRVL_MAC_ADDRS_MAX - uc_filter_max. Currently it defaults to 4 and
 794          * 21 respectively.
 795          *
 796          * If more than uc_filter_max uc addresses were added to filter list
 797          * then NIC will switch to promiscuous mode automatically.
 798          *
 799          * If more than MRVL_MAC_ADDRS_MAX - uc_filter_max number mc addresses
 800          * were added to filter list then NIC will switch to all-multicast mode
 801          * automatically.
 802          */
 803         ret = pp2_ppio_add_mac_addr(priv->ppio, mac_addr->addr_bytes);
 804         if (ret) {
 805                 ether_format_addr(buf, sizeof(buf), mac_addr);
 806                 RTE_LOG(ERR, PMD, "Failed to add mac %s\n", buf);
 807                 return -1;
 808         }
 809
 810         return 0;
 811 }
 812
 813 /**
 814  * DPDK callback to set the primary MAC address.
 815  *
 816  * @param dev
 817  *   Pointer to Ethernet device structure.
 818  * @param mac_addr
 819  *   MAC address to register.
 820  */
 821 static void
 822 mrvl_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr)
 823 {
 824         struct mrvl_priv *priv = dev->data->dev_private;
 825
 826         pp2_ppio_set_mac_addr(priv->ppio, mac_addr->addr_bytes);
 827         /*
 828          * TODO
 829          * Port stops sending packets if pp2_ppio_set_mac_addr()
 830          * was called after pp2_ppio_enable(). As a quick fix issue
 831          * enable port once again.
 832          */
 833         pp2_ppio_enable(priv->ppio);
 834 }
 835
 836 /**
 837  * DPDK callback to get device statistics.
 838  *
 839  * @param dev
 840  *   Pointer to Ethernet device structure.
 841  * @param stats
 842  *   Stats structure output buffer.
 843  *
 844  * @return
 845  *   0 on success, negative error value otherwise.
 846  */
 847 static int
 848 mrvl_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
 849 {
 850         struct mrvl_priv *priv = dev->data->dev_private;
 851         struct pp2_ppio_statistics ppio_stats;
 852         uint64_t drop_mac = 0;
 853         unsigned int i, idx, ret;
 854
 855         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 856                 struct mrvl_rxq *rxq = dev->data->rx_queues[i];
 857                 struct pp2_ppio_inq_statistics rx_stats;
 858
 859                 if (!rxq)
 860                         continue;
 861
 862                 idx = rxq->queue_id;
 863                 if (unlikely(idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)) {
 864                         RTE_LOG(ERR, PMD,
 865                                 "rx queue %d stats out of range (0 - %d)\n",
 866                                 idx, RTE_ETHDEV_QUEUE_STAT_CNTRS - 1);
 867                         continue;
 868                 }
 869
 870                 ret = pp2_ppio_inq_get_statistics(priv->ppio,
 871                                                   priv->rxq_map[idx].tc,
 872                                                   priv->rxq_map[idx].inq,
 873                                                   &rx_stats, 0);
 874                 if (unlikely(ret)) {
 875                         RTE_LOG(ERR, PMD,
 876                                 "Failed to update rx queue %d stats\n", idx);
 877                         break;
 878                 }
 879
 880                 stats->q_ibytes[idx] = rxq->bytes_recv;
 881                 stats->q_ipackets[idx] = rx_stats.enq_desc - rxq->drop_mac;
 882                 stats->q_errors[idx] = rx_stats.drop_early +
 883                                        rx_stats.drop_fullq +
 884                                        rx_stats.drop_bm +
 885                                        rxq->drop_mac;
 886                 stats->ibytes += rxq->bytes_recv;
 887                 drop_mac += rxq->drop_mac;
 888         }
 889
 890         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 891                 struct mrvl_txq *txq = dev->data->tx_queues[i];
 892                 struct pp2_ppio_outq_statistics tx_stats;
 893
 894                 if (!txq)
 895                         continue;
 896
 897                 idx = txq->queue_id;
 898                 if (unlikely(idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)) {
 899                         RTE_LOG(ERR, PMD,
 900                                 "tx queue %d stats out of range (0 - %d)\n",
 901                                 idx, RTE_ETHDEV_QUEUE_STAT_CNTRS - 1);
 902                 }
 903
 904                 ret = pp2_ppio_outq_get_statistics(priv->ppio, idx,
 905                                                    &tx_stats, 0);
 906                 if (unlikely(ret)) {
 907                         RTE_LOG(ERR, PMD,
 908                                 "Failed to update tx queue %d stats\n", idx);
 909                         break;
 910                 }
 911
 912                 stats->q_opackets[idx] = tx_stats.deq_desc;
 913                 stats->q_obytes[idx] = txq->bytes_sent;
 914                 stats->obytes += txq->bytes_sent;
 915         }
 916
 917         ret = pp2_ppio_get_statistics(priv->ppio, &ppio_stats, 0);
 918         if (unlikely(ret)) {
 919                 RTE_LOG(ERR, PMD, "Failed to update port statistics\n");
 920                 return ret;
 921         }
 922
 923         stats->ipackets += ppio_stats.rx_packets - drop_mac;
 924         stats->opackets += ppio_stats.tx_packets;
 925         stats->imissed += ppio_stats.rx_fullq_dropped +
 926                           ppio_stats.rx_bm_dropped +
 927                           ppio_stats.rx_early_dropped +
 928                           ppio_stats.rx_fifo_dropped +
 929                           ppio_stats.rx_cls_dropped;
 930         stats->ierrors = drop_mac;
 931
 932         return 0;
 933 }
 934
 935 /**
 936  * DPDK callback to clear device statistics.
 937  *
 938  * @param dev
 939  *   Pointer to Ethernet device structure.
 940  */
 941 static void
 942 mrvl_stats_reset(struct rte_eth_dev *dev)
 943 {
 944         struct mrvl_priv *priv = dev->data->dev_private;
 945         int i;
 946
 947         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 948                 struct mrvl_rxq *rxq = dev->data->rx_queues[i];
 949
 950                 pp2_ppio_inq_get_statistics(priv->ppio, priv->rxq_map[i].tc,
 951                                             priv->rxq_map[i].inq, NULL, 1);
 952                 rxq->bytes_recv = 0;
 953                 rxq->drop_mac = 0;
 954         }
 955
 956         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 957                 struct mrvl_txq *txq = dev->data->tx_queues[i];
 958
 959                 pp2_ppio_outq_get_statistics(priv->ppio, i, NULL, 1);
 960                 txq->bytes_sent = 0;
 961         }
 962
 963         pp2_ppio_get_statistics(priv->ppio, NULL, 1);
 964 }
 965
 966 /**
 967  * DPDK callback to get information about the device.
 968  *
 969  * @param dev
 970  *   Pointer to Ethernet device structure (unused).
 971  * @param info
 972  *   Info structure output buffer.
 973  */
 974 static void
 975 mrvl_dev_infos_get(struct rte_eth_dev *dev __rte_unused,
 976                    struct rte_eth_dev_info *info)
 977 {
 978         info->speed_capa = ETH_LINK_SPEED_10M |
 979                            ETH_LINK_SPEED_100M |
 980                            ETH_LINK_SPEED_1G |
 981                            ETH_LINK_SPEED_10G;
 982
 983         info->max_rx_queues = MRVL_PP2_RXQ_MAX;
 984         info->max_tx_queues = MRVL_PP2_TXQ_MAX;
 985         info->max_mac_addrs = MRVL_MAC_ADDRS_MAX;
 986
 987         info->rx_desc_lim.nb_max = MRVL_PP2_RXD_MAX;
 988         info->rx_desc_lim.nb_min = MRVL_PP2_RXD_MIN;
 989         info->rx_desc_lim.nb_align = MRVL_PP2_RXD_ALIGN;
 990
 991         info->tx_desc_lim.nb_max = MRVL_PP2_TXD_MAX;
 992         info->tx_desc_lim.nb_min = MRVL_PP2_TXD_MIN;
 993         info->tx_desc_lim.nb_align = MRVL_PP2_TXD_ALIGN;
 994
 995         info->rx_offload_capa = DEV_RX_OFFLOAD_JUMBO_FRAME |
 996                                 DEV_RX_OFFLOAD_VLAN_FILTER |
 997                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
 998                                 DEV_RX_OFFLOAD_UDP_CKSUM |
 999                                 DEV_RX_OFFLOAD_TCP_CKSUM;
1000
1001         info->tx_offload_capa = DEV_TX_OFFLOAD_IPV4_CKSUM |
1002                                 DEV_TX_OFFLOAD_UDP_CKSUM |
1003                                 DEV_TX_OFFLOAD_TCP_CKSUM;
1004
1005         info->flow_type_rss_offloads = ETH_RSS_IPV4 |
1006                                        ETH_RSS_NONFRAG_IPV4_TCP |
1007                                        ETH_RSS_NONFRAG_IPV4_UDP;
1008
1009         /* By default packets are dropped if no descriptors are available */
1010         info->default_rxconf.rx_drop_en = 1;
1011
1012         info->max_rx_pktlen = MRVL_PKT_SIZE_MAX;
1013 }
1014
1015 /**
1016  * Return supported packet types.
1017  *
1018  * @param dev
1019  *   Pointer to Ethernet device structure (unused).
1020  *
1021  * @return
1022  *   Const pointer to the table with supported packet types.
1023  */
1024 static const uint32_t *
1025 mrvl_dev_supported_ptypes_get(struct rte_eth_dev *dev __rte_unused)
1026 {
1027         static const uint32_t ptypes[] = {
1028                 RTE_PTYPE_L2_ETHER,
1029                 RTE_PTYPE_L3_IPV4,
1030                 RTE_PTYPE_L3_IPV4_EXT,
1031                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1032                 RTE_PTYPE_L3_IPV6,
1033                 RTE_PTYPE_L3_IPV6_EXT,
1034                 RTE_PTYPE_L2_ETHER_ARP,
1035                 RTE_PTYPE_L4_TCP,
1036                 RTE_PTYPE_L4_UDP
1037         };
1038
1039         return ptypes;
1040 }
1041
1042 /**
1043  * DPDK callback to get information about specific receive queue.
1044  *
1045  * @param dev
1046  *   Pointer to Ethernet device structure.
1047  * @param rx_queue_id
1048  *   Receive queue index.
1049  * @param qinfo
1050  *   Receive queue information structure.
1051  */
1052 static void mrvl_rxq_info_get(struct rte_eth_dev *dev, uint16_t rx_queue_id,
1053                               struct rte_eth_rxq_info *qinfo)
1054 {
1055         struct mrvl_rxq *q = dev->data->rx_queues[rx_queue_id];
1056         struct mrvl_priv *priv = dev->data->dev_private;
1057         int inq = priv->rxq_map[rx_queue_id].inq;
1058         int tc = priv->rxq_map[rx_queue_id].tc;
1059         struct pp2_ppio_tc_params *tc_params =
1060                 &priv->ppio_params.inqs_params.tcs_params[tc];
1061
1062         qinfo->mp = q->mp;
1063         qinfo->nb_desc = tc_params->inqs_params[inq].size;
1064 }
1065
1066 /**
1067  * DPDK callback to get information about specific transmit queue.
1068  *
1069  * @param dev
1070  *   Pointer to Ethernet device structure.
1071  * @param tx_queue_id
1072  *   Transmit queue index.
1073  * @param qinfo
1074  *   Transmit queue information structure.
1075  */
1076 static void mrvl_txq_info_get(struct rte_eth_dev *dev, uint16_t tx_queue_id,
1077                               struct rte_eth_txq_info *qinfo)
1078 {
1079         struct mrvl_priv *priv = dev->data->dev_private;
1080
1081         qinfo->nb_desc =
1082                 priv->ppio_params.outqs_params.outqs_params[tx_queue_id].size;
1083 }
1084
1085 /**
1086  * DPDK callback to Configure a VLAN filter.
1087  *
1088  * @param dev
1089  *   Pointer to Ethernet device structure.
1090  * @param vlan_id
1091  *   VLAN ID to filter.
1092  * @param on
1093  *   Toggle filter.
1094  *
1095  * @return
1096  *   0 on success, negative error value otherwise.
1097  */
1098 static int
1099 mrvl_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1100 {
1101         struct mrvl_priv *priv = dev->data->dev_private;
1102
1103         return on ? pp2_ppio_add_vlan(priv->ppio, vlan_id) :
1104                     pp2_ppio_remove_vlan(priv->ppio, vlan_id);
1105 }
1106
1107 /**
1108  * Release buffers to hardware bpool (buffer-pool)
1109  *
1110  * @param rxq
1111  *   Receive queue pointer.
1112  * @param num
1113  *   Number of buffers to release to bpool.
1114  *
1115  * @return
1116  *   0 on success, negative error value otherwise.
1117  */
1118 static int
1119 mrvl_fill_bpool(struct mrvl_rxq *rxq, int num)
1120 {
1121         struct buff_release_entry entries[MRVL_PP2_TXD_MAX];
1122         struct rte_mbuf *mbufs[MRVL_PP2_TXD_MAX];
1123         int i, ret;
1124         unsigned int core_id = rte_lcore_id();
1125         struct pp2_hif *hif = hifs[core_id];
1126         struct pp2_bpool *bpool = rxq->priv->bpool;
1127
1128         ret = rte_pktmbuf_alloc_bulk(rxq->mp, mbufs, num);
1129         if (ret)
1130                 return ret;
1131
1132         if (cookie_addr_high == MRVL_COOKIE_ADDR_INVALID)
1133                 cookie_addr_high =
1134                         (uint64_t)mbufs[0] & MRVL_COOKIE_HIGH_ADDR_MASK;
1135
1136         for (i = 0; i < num; i++) {
1137                 if (((uint64_t)mbufs[i] & MRVL_COOKIE_HIGH_ADDR_MASK)
1138                         != cookie_addr_high) {
1139                         RTE_LOG(ERR, PMD,
1140                                 "mbuf virtual addr high 0x%lx out of range\n",
1141                                 (uint64_t)mbufs[i] >> 32);
1142                         goto out;
1143                 }
1144
1145                 entries[i].buff.addr =
1146                         rte_mbuf_data_iova_default(mbufs[i]);
1147                 entries[i].buff.cookie = (pp2_cookie_t)(uint64_t)mbufs[i];
1148                 entries[i].bpool = bpool;
1149         }
1150
1151         pp2_bpool_put_buffs(hif, entries, (uint16_t *)&i);
1152         mrvl_port_bpool_size[bpool->pp2_id][bpool->id][core_id] += i;
1153
1154         if (i != num)
1155                 goto out;
1156
1157         return 0;
1158 out:
1159         for (; i < num; i++)
1160                 rte_pktmbuf_free(mbufs[i]);
1161
1162         return -1;
1163 }
1164
1165 /**
1166  * DPDK callback to configure the receive queue.
1167  *
1168  * @param dev
1169  *   Pointer to Ethernet device structure.
1170  * @param idx
1171  *   RX queue index.
1172  * @param desc
1173  *   Number of descriptors to configure in queue.
1174  * @param socket
1175  *   NUMA socket on which memory must be allocated.
1176  * @param conf
1177  *   Thresholds parameters (unused_).
1178  * @param mp
1179  *   Memory pool for buffer allocations.
1180  *
1181  * @return
1182  *   0 on success, negative error value otherwise.
1183  */
1184 static int
1185 mrvl_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1186                     unsigned int socket,
1187                     const struct rte_eth_rxconf *conf __rte_unused,
1188                     struct rte_mempool *mp)
1189 {
1190         struct mrvl_priv *priv = dev->data->dev_private;
1191         struct mrvl_rxq *rxq;
1192         uint32_t min_size,
1193                  max_rx_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
1194         int ret, tc, inq;
1195
1196         if (priv->rxq_map[idx].tc == MRVL_UNKNOWN_TC) {
1197                 /*
1198                  * Unknown TC mapping, mapping will not have a correct queue.
1199                  */
1200                 RTE_LOG(ERR, PMD, "Unknown TC mapping for queue %hu eth%hhu\n",
1201                         idx, priv->ppio_id);
1202                 return -EFAULT;
1203         }
1204
1205         min_size = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM -
1206                    MRVL_PKT_EFFEC_OFFS;
1207         if (min_size < max_rx_pkt_len) {
1208                 RTE_LOG(ERR, PMD,
1209                         "Mbuf size must be increased to %u bytes to hold up to %u bytes of data.\n",
1210                         max_rx_pkt_len + RTE_PKTMBUF_HEADROOM +
1211                         MRVL_PKT_EFFEC_OFFS,
1212                         max_rx_pkt_len);
1213                 return -EINVAL;
1214         }
1215
1216         if (dev->data->rx_queues[idx]) {
1217                 rte_free(dev->data->rx_queues[idx]);
1218                 dev->data->rx_queues[idx] = NULL;
1219         }
1220
1221         rxq = rte_zmalloc_socket("rxq", sizeof(*rxq), 0, socket);
1222         if (!rxq)
1223                 return -ENOMEM;
1224
1225         rxq->priv = priv;
1226         rxq->mp = mp;
1227         rxq->cksum_enabled = dev->data->dev_conf.rxmode.hw_ip_checksum;
1228         rxq->queue_id = idx;
1229         rxq->port_id = dev->data->port_id;
1230         mrvl_port_to_bpool_lookup[rxq->port_id] = priv->bpool;
1231
1232         tc = priv->rxq_map[rxq->queue_id].tc,
1233         inq = priv->rxq_map[rxq->queue_id].inq;
1234         priv->ppio_params.inqs_params.tcs_params[tc].inqs_params[inq].size =
1235                 desc;
1236
1237         ret = mrvl_fill_bpool(rxq, desc);
1238         if (ret) {
1239                 rte_free(rxq);
1240                 return ret;
1241         }
1242
1243         priv->bpool_init_size += desc;
1244
1245         dev->data->rx_queues[idx] = rxq;
1246
1247         return 0;
1248 }
1249
1250 /**
1251  * DPDK callback to release the receive queue.
1252  *
1253  * @param rxq
1254  *   Generic receive queue pointer.
1255  */
1256 static void
1257 mrvl_rx_queue_release(void *rxq)
1258 {
1259         struct mrvl_rxq *q = rxq;
1260         struct pp2_ppio_tc_params *tc_params;
1261         int i, num, tc, inq;
1262
1263         if (!q)
1264                 return;
1265
1266         tc = q->priv->rxq_map[q->queue_id].tc;
1267         inq = q->priv->rxq_map[q->queue_id].inq;
1268         tc_params = &q->priv->ppio_params.inqs_params.tcs_params[tc];
1269         num = tc_params->inqs_params[inq].size;
1270         for (i = 0; i < num; i++) {
1271                 struct pp2_buff_inf inf;
1272                 uint64_t addr;
1273
1274                 pp2_bpool_get_buff(hifs[rte_lcore_id()], q->priv->bpool, &inf);
1275                 addr = cookie_addr_high | inf.cookie;
1276                 rte_pktmbuf_free((struct rte_mbuf *)addr);
1277         }
1278
1279         rte_free(q);
1280 }
1281
1282 /**
1283  * DPDK callback to configure the transmit queue.
1284  *
1285  * @param dev
1286  *   Pointer to Ethernet device structure.
1287  * @param idx
1288  *   Transmit queue index.
1289  * @param desc
1290  *   Number of descriptors to configure in the queue.
1291  * @param socket
1292  *   NUMA socket on which memory must be allocated.
1293  * @param conf
1294  *   Thresholds parameters (unused).
1295  *
1296  * @return
1297  *   0 on success, negative error value otherwise.
1298  */
1299 static int
1300 mrvl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1301                     unsigned int socket,
1302                     const struct rte_eth_txconf *conf __rte_unused)
1303 {
1304         struct mrvl_priv *priv = dev->data->dev_private;
1305         struct mrvl_txq *txq;
1306
1307         if (dev->data->tx_queues[idx]) {
1308                 rte_free(dev->data->tx_queues[idx]);
1309                 dev->data->tx_queues[idx] = NULL;
1310         }
1311
1312         txq = rte_zmalloc_socket("txq", sizeof(*txq), 0, socket);
1313         if (!txq)
1314                 return -ENOMEM;
1315
1316         txq->priv = priv;
1317         txq->queue_id = idx;
1318         txq->port_id = dev->data->port_id;
1319         dev->data->tx_queues[idx] = txq;
1320
1321         priv->ppio_params.outqs_params.outqs_params[idx].size = desc;
1322         priv->ppio_params.outqs_params.outqs_params[idx].weight = 1;
1323
1324         return 0;
1325 }
1326
1327 /**
1328  * DPDK callback to release the transmit queue.
1329  *
1330  * @param txq
1331  *   Generic transmit queue pointer.
1332  */
1333 static void
1334 mrvl_tx_queue_release(void *txq)
1335 {
1336         struct mrvl_txq *q = txq;
1337
1338         if (!q)
1339                 return;
1340
1341         rte_free(q);
1342 }
1343
1344 /**
1345  * Update RSS hash configuration
1346  *
1347  * @param dev
1348  *   Pointer to Ethernet device structure.
1349  * @param rss_conf
1350  *   Pointer to RSS configuration.
1351  *
1352  * @return
1353  *   0 on success, negative error value otherwise.
1354  */
1355 static int
1356 mrvl_rss_hash_update(struct rte_eth_dev *dev,
1357                      struct rte_eth_rss_conf *rss_conf)
1358 {
1359         struct mrvl_priv *priv = dev->data->dev_private;
1360
1361         return mrvl_configure_rss(priv, rss_conf);
1362 }
1363
1364 /**
1365  * DPDK callback to get RSS hash configuration.
1366  *
1367  * @param dev
1368  *   Pointer to Ethernet device structure.
1369  * @rss_conf
1370  *   Pointer to RSS configuration.
1371  *
1372  * @return
1373  *   Always 0.
1374  */
1375 static int
1376 mrvl_rss_hash_conf_get(struct rte_eth_dev *dev,
1377                        struct rte_eth_rss_conf *rss_conf)
1378 {
1379         struct mrvl_priv *priv = dev->data->dev_private;
1380         enum pp2_ppio_hash_type hash_type =
1381                 priv->ppio_params.inqs_params.hash_type;
1382
1383         rss_conf->rss_key = NULL;
1384
1385         if (hash_type == PP2_PPIO_HASH_T_NONE)
1386                 rss_conf->rss_hf = 0;
1387         else if (hash_type == PP2_PPIO_HASH_T_2_TUPLE)
1388                 rss_conf->rss_hf = ETH_RSS_IPV4;
1389         else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && priv->rss_hf_tcp)
1390                 rss_conf->rss_hf = ETH_RSS_NONFRAG_IPV4_TCP;
1391         else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && !priv->rss_hf_tcp)
1392                 rss_conf->rss_hf = ETH_RSS_NONFRAG_IPV4_UDP;
1393
1394         return 0;
1395 }
1396
1397 static const struct eth_dev_ops mrvl_ops = {
1398         .dev_configure = mrvl_dev_configure,
1399         .dev_start = mrvl_dev_start,
1400         .dev_stop = mrvl_dev_stop,
1401         .dev_set_link_up = mrvl_dev_set_link_up,
1402         .dev_set_link_down = mrvl_dev_set_link_down,
1403         .dev_close = mrvl_dev_close,
1404         .link_update = mrvl_link_update,
1405         .promiscuous_enable = mrvl_promiscuous_enable,
1406         .allmulticast_enable = mrvl_allmulticast_enable,
1407         .promiscuous_disable = mrvl_promiscuous_disable,
1408         .allmulticast_disable = mrvl_allmulticast_disable,
1409         .mac_addr_remove = mrvl_mac_addr_remove,
1410         .mac_addr_add = mrvl_mac_addr_add,
1411         .mac_addr_set = mrvl_mac_addr_set,
1412         .mtu_set = mrvl_mtu_set,
1413         .stats_get = mrvl_stats_get,
1414         .stats_reset = mrvl_stats_reset,
1415         .dev_infos_get = mrvl_dev_infos_get,
1416         .dev_supported_ptypes_get = mrvl_dev_supported_ptypes_get,
1417         .rxq_info_get = mrvl_rxq_info_get,
1418         .txq_info_get = mrvl_txq_info_get,
1419         .vlan_filter_set = mrvl_vlan_filter_set,
1420         .rx_queue_setup = mrvl_rx_queue_setup,
1421         .rx_queue_release = mrvl_rx_queue_release,
1422         .tx_queue_setup = mrvl_tx_queue_setup,
1423         .tx_queue_release = mrvl_tx_queue_release,
1424         .rss_hash_update = mrvl_rss_hash_update,
1425         .rss_hash_conf_get = mrvl_rss_hash_conf_get,
1426 };
1427
1428 /**
1429  * Return packet type information and l3/l4 offsets.
1430  *
1431  * @param desc
1432  *   Pointer to the received packet descriptor.
1433  * @param l3_offset
1434  *   l3 packet offset.
1435  * @param l4_offset
1436  *   l4 packet offset.
1437  *
1438  * @return
1439  *   Packet type information.
1440  */
1441 static inline uint64_t
1442 mrvl_desc_to_packet_type_and_offset(struct pp2_ppio_desc *desc,
1443                                     uint8_t *l3_offset, uint8_t *l4_offset)
1444 {
1445         enum pp2_inq_l3_type l3_type;
1446         enum pp2_inq_l4_type l4_type;
1447         uint64_t packet_type;
1448
1449         pp2_ppio_inq_desc_get_l3_info(desc, &l3_type, l3_offset);
1450         pp2_ppio_inq_desc_get_l4_info(desc, &l4_type, l4_offset);
1451
1452         packet_type = RTE_PTYPE_L2_ETHER;
1453
1454         switch (l3_type) {
1455         case PP2_INQ_L3_TYPE_IPV4_NO_OPTS:
1456                 packet_type |= RTE_PTYPE_L3_IPV4;
1457                 break;
1458         case PP2_INQ_L3_TYPE_IPV4_OK:
1459                 packet_type |= RTE_PTYPE_L3_IPV4_EXT;
1460                 break;
1461         case PP2_INQ_L3_TYPE_IPV4_TTL_ZERO:
1462                 packet_type |= RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
1463                 break;
1464         case PP2_INQ_L3_TYPE_IPV6_NO_EXT:
1465                 packet_type |= RTE_PTYPE_L3_IPV6;
1466                 break;
1467         case PP2_INQ_L3_TYPE_IPV6_EXT:
1468                 packet_type |= RTE_PTYPE_L3_IPV6_EXT;
1469                 break;
1470         case PP2_INQ_L3_TYPE_ARP:
1471                 packet_type |= RTE_PTYPE_L2_ETHER_ARP;
1472                 /*
1473                  * In case of ARP l4_offset is set to wrong value.
1474                  * Set it to proper one so that later on mbuf->l3_len can be
1475                  * calculated subtracting l4_offset and l3_offset.
1476                  */
1477                 *l4_offset = *l3_offset + MRVL_ARP_LENGTH;
1478                 break;
1479         default:
1480                 RTE_LOG(DEBUG, PMD, "Failed to recognise l3 packet type\n");
1481                 break;
1482         }
1483
1484         switch (l4_type) {
1485         case PP2_INQ_L4_TYPE_TCP:
1486                 packet_type |= RTE_PTYPE_L4_TCP;
1487                 break;
1488         case PP2_INQ_L4_TYPE_UDP:
1489                 packet_type |= RTE_PTYPE_L4_UDP;
1490                 break;
1491         default:
1492                 RTE_LOG(DEBUG, PMD, "Failed to recognise l4 packet type\n");
1493                 break;
1494         }
1495
1496         return packet_type;
1497 }
1498
1499 /**
1500  * Get offload information from the received packet descriptor.
1501  *
1502  * @param desc
1503  *   Pointer to the received packet descriptor.
1504  *
1505  * @return
1506  *   Mbuf offload flags.
1507  */
1508 static inline uint64_t
1509 mrvl_desc_to_ol_flags(struct pp2_ppio_desc *desc)
1510 {
1511         uint64_t flags;
1512         enum pp2_inq_desc_status status;
1513
1514         status = pp2_ppio_inq_desc_get_l3_pkt_error(desc);
1515         if (unlikely(status != PP2_DESC_ERR_OK))
1516                 flags = PKT_RX_IP_CKSUM_BAD;
1517         else
1518                 flags = PKT_RX_IP_CKSUM_GOOD;
1519
1520         status = pp2_ppio_inq_desc_get_l4_pkt_error(desc);
1521         if (unlikely(status != PP2_DESC_ERR_OK))
1522                 flags |= PKT_RX_L4_CKSUM_BAD;
1523         else
1524                 flags |= PKT_RX_L4_CKSUM_GOOD;
1525
1526         return flags;
1527 }
1528
1529 /**
1530  * DPDK callback for receive.
1531  *
1532  * @param rxq
1533  *   Generic pointer to the receive queue.
1534  * @param rx_pkts
1535  *   Array to store received packets.
1536  * @param nb_pkts
1537  *   Maximum number of packets in array.
1538  *
1539  * @return
1540  *   Number of packets successfully received.
1541  */
1542 static uint16_t
1543 mrvl_rx_pkt_burst(void *rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1544 {
1545         struct mrvl_rxq *q = rxq;
1546         struct pp2_ppio_desc descs[nb_pkts];
1547         struct pp2_bpool *bpool;
1548         int i, ret, rx_done = 0;
1549         int num;
1550         unsigned int core_id = rte_lcore_id();
1551
1552         if (unlikely(!q->priv->ppio))
1553                 return 0;
1554
1555         bpool = q->priv->bpool;
1556
1557         ret = pp2_ppio_recv(q->priv->ppio, q->priv->rxq_map[q->queue_id].tc,
1558                             q->priv->rxq_map[q->queue_id].inq, descs, &nb_pkts);
1559         if (unlikely(ret < 0)) {
1560                 RTE_LOG(ERR, PMD, "Failed to receive packets\n");
1561                 return 0;
1562         }
1563         mrvl_port_bpool_size[bpool->pp2_id][bpool->id][core_id] -= nb_pkts;
1564
1565         for (i = 0; i < nb_pkts; i++) {
1566                 struct rte_mbuf *mbuf;
1567                 uint8_t l3_offset, l4_offset;
1568                 enum pp2_inq_desc_status status;
1569                 uint64_t addr;
1570
1571                 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) {
1572                         struct pp2_ppio_desc *pref_desc;
1573                         u64 pref_addr;
1574
1575                         pref_desc = &descs[i + MRVL_MUSDK_PREFETCH_SHIFT];
1576                         pref_addr = cookie_addr_high |
1577                                     pp2_ppio_inq_desc_get_cookie(pref_desc);
1578                         rte_mbuf_prefetch_part1((struct rte_mbuf *)(pref_addr));
1579                         rte_mbuf_prefetch_part2((struct rte_mbuf *)(pref_addr));
1580                 }
1581
1582                 addr = cookie_addr_high |
1583                        pp2_ppio_inq_desc_get_cookie(&descs[i]);
1584                 mbuf = (struct rte_mbuf *)addr;
1585                 rte_pktmbuf_reset(mbuf);
1586
1587                 /* drop packet in case of mac, overrun or resource error */
1588                 status = pp2_ppio_inq_desc_get_l2_pkt_error(&descs[i]);
1589                 if (unlikely(status != PP2_DESC_ERR_OK)) {
1590                         struct pp2_buff_inf binf = {
1591                                 .addr = rte_mbuf_data_iova_default(mbuf),
1592                                 .cookie = (pp2_cookie_t)(uint64_t)mbuf,
1593                         };
1594
1595                         pp2_bpool_put_buff(hifs[core_id], bpool, &binf);
1596                         mrvl_port_bpool_size
1597                                 [bpool->pp2_id][bpool->id][core_id]++;
1598                         q->drop_mac++;
1599                         continue;
1600                 }
1601
1602                 mbuf->data_off += MRVL_PKT_EFFEC_OFFS;
1603                 mbuf->pkt_len = pp2_ppio_inq_desc_get_pkt_len(&descs[i]);
1604                 mbuf->data_len = mbuf->pkt_len;
1605                 mbuf->port = q->port_id;
1606                 mbuf->packet_type =
1607                         mrvl_desc_to_packet_type_and_offset(&descs[i],
1608                                                             &l3_offset,
1609                                                             &l4_offset);
1610                 mbuf->l2_len = l3_offset;
1611                 mbuf->l3_len = l4_offset - l3_offset;
1612
1613                 if (likely(q->cksum_enabled))
1614                         mbuf->ol_flags = mrvl_desc_to_ol_flags(&descs[i]);
1615
1616                 rx_pkts[rx_done++] = mbuf;
1617                 q->bytes_recv += mbuf->pkt_len;
1618         }
1619
1620         if (rte_spinlock_trylock(&q->priv->lock) == 1) {
1621                 num = mrvl_get_bpool_size(bpool->pp2_id, bpool->id);
1622
1623                 if (unlikely(num <= q->priv->bpool_min_size ||
1624                              (!rx_done && num < q->priv->bpool_init_size))) {
1625                         ret = mrvl_fill_bpool(q, MRVL_BURST_SIZE);
1626                         if (ret)
1627                                 RTE_LOG(ERR, PMD, "Failed to fill bpool\n");
1628                 } else if (unlikely(num > q->priv->bpool_max_size)) {
1629                         int i;
1630                         int pkt_to_remove = num - q->priv->bpool_init_size;
1631                         struct rte_mbuf *mbuf;
1632                         struct pp2_buff_inf buff;
1633
1634                         RTE_LOG(DEBUG, PMD,
1635                                 "\nport-%d:%d: bpool %d oversize - remove %d buffers (pool size: %d -> %d)\n",
1636                                 bpool->pp2_id, q->priv->ppio->port_id,
1637                                 bpool->id, pkt_to_remove, num,
1638                                 q->priv->bpool_init_size);
1639
1640                         for (i = 0; i < pkt_to_remove; i++) {
1641                                 pp2_bpool_get_buff(hifs[core_id], bpool, &buff);
1642                                 mbuf = (struct rte_mbuf *)
1643                                         (cookie_addr_high | buff.cookie);
1644                                 rte_pktmbuf_free(mbuf);
1645                         }
1646                         mrvl_port_bpool_size
1647                                 [bpool->pp2_id][bpool->id][core_id] -=
1648                                                                 pkt_to_remove;
1649                 }
1650                 rte_spinlock_unlock(&q->priv->lock);
1651         }
1652
1653         return rx_done;
1654 }
1655
1656 /**
1657  * Prepare offload information.
1658  *
1659  * @param ol_flags
1660  *   Offload flags.
1661  * @param packet_type
1662  *   Packet type bitfield.
1663  * @param l3_type
1664  *   Pointer to the pp2_ouq_l3_type structure.
1665  * @param l4_type
1666  *   Pointer to the pp2_outq_l4_type structure.
1667  * @param gen_l3_cksum
1668  *   Will be set to 1 in case l3 checksum is computed.
1669  * @param l4_cksum
1670  *   Will be set to 1 in case l4 checksum is computed.
1671  *
1672  * @return
1673  *   0 on success, negative error value otherwise.
1674  */
1675 static inline int
1676 mrvl_prepare_proto_info(uint64_t ol_flags, uint32_t packet_type,
1677                         enum pp2_outq_l3_type *l3_type,
1678                         enum pp2_outq_l4_type *l4_type,
1679                         int *gen_l3_cksum,
1680                         int *gen_l4_cksum)
1681 {
1682         /*
1683          * Based on ol_flags prepare information
1684          * for pp2_ppio_outq_desc_set_proto_info() which setups descriptor
1685          * for offloading.
1686          */
1687         if (ol_flags & PKT_TX_IPV4) {
1688                 *l3_type = PP2_OUTQ_L3_TYPE_IPV4;
1689                 *gen_l3_cksum = ol_flags & PKT_TX_IP_CKSUM ? 1 : 0;
1690         } else if (ol_flags & PKT_TX_IPV6) {
1691                 *l3_type = PP2_OUTQ_L3_TYPE_IPV6;
1692                 /* no checksum for ipv6 header */
1693                 *gen_l3_cksum = 0;
1694         } else {
1695                 /* if something different then stop processing */
1696                 return -1;
1697         }
1698
1699         ol_flags &= PKT_TX_L4_MASK;
1700         if ((packet_type & RTE_PTYPE_L4_TCP) &&
1701             ol_flags == PKT_TX_TCP_CKSUM) {
1702                 *l4_type = PP2_OUTQ_L4_TYPE_TCP;
1703                 *gen_l4_cksum = 1;
1704         } else if ((packet_type & RTE_PTYPE_L4_UDP) &&
1705                    ol_flags == PKT_TX_UDP_CKSUM) {
1706                 *l4_type = PP2_OUTQ_L4_TYPE_UDP;
1707                 *gen_l4_cksum = 1;
1708         } else {
1709                 *l4_type = PP2_OUTQ_L4_TYPE_OTHER;
1710                 /* no checksum for other type */
1711                 *gen_l4_cksum = 0;
1712         }
1713
1714         return 0;
1715 }
1716
1717 /**
1718  * Release already sent buffers to bpool (buffer-pool).
1719  *
1720  * @param ppio
1721  *   Pointer to the port structure.
1722  * @param hif
1723  *   Pointer to the MUSDK hardware interface.
1724  * @param sq
1725  *   Pointer to the shadow queue.
1726  * @param qid
1727  *   Queue id number.
1728  * @param force
1729  *   Force releasing packets.
1730  */
1731 static inline void
1732 mrvl_free_sent_buffers(struct pp2_ppio *ppio, struct pp2_hif *hif,
1733                        struct mrvl_shadow_txq *sq, int qid, int force)
1734 {
1735         struct buff_release_entry *entry;
1736         uint16_t nb_done = 0, num = 0, skip_bufs = 0;
1737         int i, core_id = rte_lcore_id();
1738
1739         pp2_ppio_get_num_outq_done(ppio, hif, qid, &nb_done);
1740
1741         sq->num_to_release += nb_done;
1742
1743         if (likely(!force &&
1744                    sq->num_to_release < MRVL_PP2_BUF_RELEASE_BURST_SIZE))
1745                 return;
1746
1747         nb_done = sq->num_to_release;
1748         sq->num_to_release = 0;
1749
1750         for (i = 0; i < nb_done; i++) {
1751                 entry = &sq->ent[sq->tail + num];
1752                 if (unlikely(!entry->buff.addr)) {
1753                         RTE_LOG(ERR, PMD,
1754                                 "Shadow memory @%d: cookie(%lx), pa(%lx)!\n",
1755                                 sq->tail, (u64)entry->buff.cookie,
1756                                 (u64)entry->buff.addr);
1757                         skip_bufs = 1;
1758                         goto skip;
1759                 }
1760
1761                 if (unlikely(!entry->bpool)) {
1762                         struct rte_mbuf *mbuf;
1763
1764                         mbuf = (struct rte_mbuf *)
1765                                (cookie_addr_high | entry->buff.cookie);
1766                         rte_pktmbuf_free(mbuf);
1767                         skip_bufs = 1;
1768                         goto skip;
1769                 }
1770
1771                 mrvl_port_bpool_size
1772                         [entry->bpool->pp2_id][entry->bpool->id][core_id]++;
1773                 num++;
1774                 if (unlikely(sq->tail + num == MRVL_PP2_TX_SHADOWQ_SIZE))
1775                         goto skip;
1776                 continue;
1777 skip:
1778                 if (likely(num))
1779                         pp2_bpool_put_buffs(hif, &sq->ent[sq->tail], &num);
1780                 num += skip_bufs;
1781                 sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK;
1782                 sq->size -= num;
1783                 num = 0;
1784         }
1785
1786         if (likely(num)) {
1787                 pp2_bpool_put_buffs(hif, &sq->ent[sq->tail], &num);
1788                 sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK;
1789                 sq->size -= num;
1790         }
1791 }
1792
1793 /**
1794  * DPDK callback for transmit.
1795  *
1796  * @param txq
1797  *   Generic pointer transmit queue.
1798  * @param tx_pkts
1799  *   Packets to transmit.
1800  * @param nb_pkts
1801  *   Number of packets in array.
1802  *
1803  * @return
1804  *   Number of packets successfully transmitted.
1805  */
1806 static uint16_t
1807 mrvl_tx_pkt_burst(void *txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1808 {
1809         struct mrvl_txq *q = txq;
1810         struct mrvl_shadow_txq *sq = &shadow_txqs[q->port_id][rte_lcore_id()];
1811         struct pp2_hif *hif = hifs[rte_lcore_id()];
1812         struct pp2_ppio_desc descs[nb_pkts];
1813         int i, ret, bytes_sent = 0;
1814         uint16_t num, sq_free_size;
1815         uint64_t addr;
1816
1817         if (unlikely(!q->priv->ppio))
1818                 return 0;
1819
1820         if (sq->size)
1821                 mrvl_free_sent_buffers(q->priv->ppio, hif, sq, q->queue_id, 0);
1822
1823         sq_free_size = MRVL_PP2_TX_SHADOWQ_SIZE - sq->size - 1;
1824         if (unlikely(nb_pkts > sq_free_size)) {
1825                 RTE_LOG(DEBUG, PMD,
1826                         "No room in shadow queue for %d packets! %d packets will be sent.\n",
1827                         nb_pkts, sq_free_size);
1828                 nb_pkts = sq_free_size;
1829         }
1830
1831         for (i = 0; i < nb_pkts; i++) {
1832                 struct rte_mbuf *mbuf = tx_pkts[i];
1833                 int gen_l3_cksum, gen_l4_cksum;
1834                 enum pp2_outq_l3_type l3_type;
1835                 enum pp2_outq_l4_type l4_type;
1836
1837                 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) {
1838                         struct rte_mbuf *pref_pkt_hdr;
1839
1840                         pref_pkt_hdr = tx_pkts[i + MRVL_MUSDK_PREFETCH_SHIFT];
1841                         rte_mbuf_prefetch_part1(pref_pkt_hdr);
1842                         rte_mbuf_prefetch_part2(pref_pkt_hdr);
1843                 }
1844
1845                 sq->ent[sq->head].buff.cookie = (pp2_cookie_t)(uint64_t)mbuf;
1846                 sq->ent[sq->head].buff.addr =
1847                         rte_mbuf_data_iova_default(mbuf);
1848                 sq->ent[sq->head].bpool =
1849                         (unlikely(mbuf->port == 0xff || mbuf->refcnt > 1)) ?
1850                          NULL : mrvl_port_to_bpool_lookup[mbuf->port];
1851                 sq->head = (sq->head + 1) & MRVL_PP2_TX_SHADOWQ_MASK;
1852                 sq->size++;
1853
1854                 pp2_ppio_outq_desc_reset(&descs[i]);
1855                 pp2_ppio_outq_desc_set_phys_addr(&descs[i],
1856                                                  rte_pktmbuf_iova(mbuf));
1857                 pp2_ppio_outq_desc_set_pkt_offset(&descs[i], 0);
1858                 pp2_ppio_outq_desc_set_pkt_len(&descs[i],
1859                                                rte_pktmbuf_pkt_len(mbuf));
1860
1861                 bytes_sent += rte_pktmbuf_pkt_len(mbuf);
1862                 /*
1863                  * in case unsupported ol_flags were passed
1864                  * do not update descriptor offload information
1865                  */
1866                 ret = mrvl_prepare_proto_info(mbuf->ol_flags, mbuf->packet_type,
1867                                               &l3_type, &l4_type, &gen_l3_cksum,
1868                                               &gen_l4_cksum);
1869                 if (unlikely(ret))
1870                         continue;
1871
1872                 pp2_ppio_outq_desc_set_proto_info(&descs[i], l3_type, l4_type,
1873                                                   mbuf->l2_len,
1874                                                   mbuf->l2_len + mbuf->l3_len,
1875                                                   gen_l3_cksum, gen_l4_cksum);
1876         }
1877
1878         num = nb_pkts;
1879         pp2_ppio_send(q->priv->ppio, hif, q->queue_id, descs, &nb_pkts);
1880         /* number of packets that were not sent */
1881         if (unlikely(num > nb_pkts)) {
1882                 for (i = nb_pkts; i < num; i++) {
1883                         sq->head = (MRVL_PP2_TX_SHADOWQ_SIZE + sq->head - 1) &
1884                                 MRVL_PP2_TX_SHADOWQ_MASK;
1885                         addr = cookie_addr_high | sq->ent[sq->head].buff.cookie;
1886                         bytes_sent -=
1887                                 rte_pktmbuf_pkt_len((struct rte_mbuf *)addr);
1888                 }
1889                 sq->size -= num - nb_pkts;
1890         }
1891
1892         q->bytes_sent += bytes_sent;
1893
1894         return nb_pkts;
1895 }
1896
1897 /**
1898  * Initialize packet processor.
1899  *
1900  * @return
1901  *   0 on success, negative error value otherwise.
1902  */
1903 static int
1904 mrvl_init_pp2(void)
1905 {
1906         struct pp2_init_params init_params;
1907
1908         memset(&init_params, 0, sizeof(init_params));
1909         init_params.hif_reserved_map = MRVL_MUSDK_HIFS_RESERVED;
1910         init_params.bm_pool_reserved_map = MRVL_MUSDK_BPOOLS_RESERVED;
1911         init_params.rss_tbl_reserved_map = MRVL_MUSDK_RSS_RESERVED;
1912
1913         return pp2_init(&init_params);
1914 }
1915
1916 /**
1917  * Deinitialize packet processor.
1918  *
1919  * @return
1920  *   0 on success, negative error value otherwise.
1921  */
1922 static void
1923 mrvl_deinit_pp2(void)
1924 {
1925         pp2_deinit();
1926 }
1927
1928 /**
1929  * Create private device structure.
1930  *
1931  * @param dev_name
1932  *   Pointer to the port name passed in the initialization parameters.
1933  *
1934  * @return
1935  *   Pointer to the newly allocated private device structure.
1936  */
1937 static struct mrvl_priv *
1938 mrvl_priv_create(const char *dev_name)
1939 {
1940         struct pp2_bpool_params bpool_params;
1941         char match[MRVL_MATCH_LEN];
1942         struct mrvl_priv *priv;
1943         int ret, bpool_bit;
1944
1945         priv = rte_zmalloc_socket(dev_name, sizeof(*priv), 0, rte_socket_id());
1946         if (!priv)
1947                 return NULL;
1948
1949         ret = pp2_netdev_get_ppio_info((char *)(uintptr_t)dev_name,
1950                                        &priv->pp_id, &priv->ppio_id);
1951         if (ret)
1952                 goto out_free_priv;
1953
1954         bpool_bit = mrvl_reserve_bit(&used_bpools[priv->pp_id],
1955                                      PP2_BPOOL_NUM_POOLS);
1956         if (bpool_bit < 0)
1957                 goto out_free_priv;
1958         priv->bpool_bit = bpool_bit;
1959
1960         snprintf(match, sizeof(match), "pool-%d:%d", priv->pp_id,
1961                  priv->bpool_bit);
1962         memset(&bpool_params, 0, sizeof(bpool_params));
1963         bpool_params.match = match;
1964         bpool_params.buff_len = MRVL_PKT_SIZE_MAX + MRVL_PKT_EFFEC_OFFS;
1965         ret = pp2_bpool_init(&bpool_params, &priv->bpool);
1966         if (ret)
1967                 goto out_clear_bpool_bit;
1968
1969         priv->ppio_params.type = PP2_PPIO_T_NIC;
1970         rte_spinlock_init(&priv->lock);
1971
1972         return priv;
1973 out_clear_bpool_bit:
1974         used_bpools[priv->pp_id] &= ~(1 << priv->bpool_bit);
1975 out_free_priv:
1976         rte_free(priv);
1977         return NULL;
1978 }
1979
1980 /**
1981  * Create device representing Ethernet port.
1982  *
1983  * @param name
1984  *   Pointer to the port's name.
1985  *
1986  * @return
1987  *   0 on success, negative error value otherwise.
1988  */
1989 static int
1990 mrvl_eth_dev_create(struct rte_vdev_device *vdev, const char *name)
1991 {
1992         int ret, fd = socket(AF_INET, SOCK_DGRAM, 0);
1993         struct rte_eth_dev *eth_dev;
1994         struct mrvl_priv *priv;
1995         struct ifreq req;
1996
1997         eth_dev = rte_eth_dev_allocate(name);
1998         if (!eth_dev)
1999                 return -ENOMEM;
2000
2001         priv = mrvl_priv_create(name);
2002         if (!priv) {
2003                 ret = -ENOMEM;
2004                 goto out_free_dev;
2005         }
2006
2007         eth_dev->data->mac_addrs =
2008                 rte_zmalloc("mac_addrs",
2009                             ETHER_ADDR_LEN * MRVL_MAC_ADDRS_MAX, 0);
2010         if (!eth_dev->data->mac_addrs) {
2011                 RTE_LOG(ERR, PMD, "Failed to allocate space for eth addrs\n");
2012                 ret = -ENOMEM;
2013                 goto out_free_priv;
2014         }
2015
2016         memset(&req, 0, sizeof(req));
2017         strcpy(req.ifr_name, name);
2018         ret = ioctl(fd, SIOCGIFHWADDR, &req);
2019         if (ret)
2020                 goto out_free_mac;
2021
2022         memcpy(eth_dev->data->mac_addrs[0].addr_bytes,
2023                req.ifr_addr.sa_data, ETHER_ADDR_LEN);
2024
2025         eth_dev->rx_pkt_burst = mrvl_rx_pkt_burst;
2026         eth_dev->tx_pkt_burst = mrvl_tx_pkt_burst;
2027         eth_dev->data->dev_private = priv;
2028         eth_dev->device = &vdev->device;
2029         eth_dev->dev_ops = &mrvl_ops;
2030
2031         return 0;
2032 out_free_mac:
2033         rte_free(eth_dev->data->mac_addrs);
2034 out_free_dev:
2035         rte_eth_dev_release_port(eth_dev);
2036 out_free_priv:
2037         rte_free(priv);
2038
2039         return ret;
2040 }
2041
2042 /**
2043  * Cleanup previously created device representing Ethernet port.
2044  *
2045  * @param name
2046  *   Pointer to the port name.
2047  */
2048 static void
2049 mrvl_eth_dev_destroy(const char *name)
2050 {
2051         struct rte_eth_dev *eth_dev;
2052         struct mrvl_priv *priv;
2053
2054         eth_dev = rte_eth_dev_allocated(name);
2055         if (!eth_dev)
2056                 return;
2057
2058         priv = eth_dev->data->dev_private;
2059         pp2_bpool_deinit(priv->bpool);
2060         rte_free(priv);
2061         rte_free(eth_dev->data->mac_addrs);
2062         rte_eth_dev_release_port(eth_dev);
2063 }
2064
2065 /**
2066  * Callback used by rte_kvargs_process() during argument parsing.
2067  *
2068  * @param key
2069  *   Pointer to the parsed key (unused).
2070  * @param value
2071  *   Pointer to the parsed value.
2072  * @param extra_args
2073  *   Pointer to the extra arguments which contains address of the
2074  *   table of pointers to parsed interface names.
2075  *
2076  * @return
2077  *   Always 0.
2078  */
2079 static int
2080 mrvl_get_ifnames(const char *key __rte_unused, const char *value,
2081                  void *extra_args)
2082 {
2083         const char **ifnames = extra_args;
2084
2085         ifnames[mrvl_ports_nb++] = value;
2086
2087         return 0;
2088 }
2089
2090 /**
2091  * Initialize per-lcore MUSDK hardware interfaces (hifs).
2092  *
2093  * @return
2094  *   0 on success, negative error value otherwise.
2095  */
2096 static int
2097 mrvl_init_hifs(void)
2098 {
2099         struct pp2_hif_params params;
2100         char match[MRVL_MATCH_LEN];
2101         int i, ret;
2102
2103         RTE_LCORE_FOREACH(i) {
2104                 ret = mrvl_reserve_bit(&used_hifs, MRVL_MUSDK_HIFS_MAX);
2105                 if (ret < 0)
2106                         return ret;
2107
2108                 snprintf(match, sizeof(match), "hif-%d", ret);
2109                 memset(&params, 0, sizeof(params));
2110                 params.match = match;
2111                 params.out_size = MRVL_PP2_AGGR_TXQD_MAX;
2112                 ret = pp2_hif_init(&params, &hifs[i]);
2113                 if (ret) {
2114                         RTE_LOG(ERR, PMD, "Failed to initialize hif %d\n", i);
2115                         return ret;
2116                 }
2117         }
2118
2119         return 0;
2120 }
2121
2122 /**
2123  * Deinitialize per-lcore MUSDK hardware interfaces (hifs).
2124  */
2125 static void
2126 mrvl_deinit_hifs(void)
2127 {
2128         int i;
2129
2130         RTE_LCORE_FOREACH(i) {
2131                 if (hifs[i])
2132                         pp2_hif_deinit(hifs[i]);
2133         }
2134 }
2135
2136 static void mrvl_set_first_last_cores(int core_id)
2137 {
2138         if (core_id < mrvl_lcore_first)
2139                 mrvl_lcore_first = core_id;
2140
2141         if (core_id > mrvl_lcore_last)
2142                 mrvl_lcore_last = core_id;
2143 }
2144
2145 /**
2146  * DPDK callback to register the virtual device.
2147  *
2148  * @param vdev
2149  *   Pointer to the virtual device.
2150  *
2151  * @return
2152  *   0 on success, negative error value otherwise.
2153  */
2154 static int
2155 rte_pmd_mrvl_probe(struct rte_vdev_device *vdev)
2156 {
2157         struct rte_kvargs *kvlist;
2158         const char *ifnames[PP2_NUM_ETH_PPIO * PP2_NUM_PKT_PROC];
2159         int ret = -EINVAL;
2160         uint32_t i, ifnum, cfgnum, core_id;
2161         const char *params;
2162
2163         params = rte_vdev_device_args(vdev);
2164         if (!params)
2165                 return -EINVAL;
2166
2167         kvlist = rte_kvargs_parse(params, valid_args);
2168         if (!kvlist)
2169                 return -EINVAL;
2170
2171         ifnum = rte_kvargs_count(kvlist, MRVL_IFACE_NAME_ARG);
2172         if (ifnum > RTE_DIM(ifnames))
2173                 goto out_free_kvlist;
2174
2175         rte_kvargs_process(kvlist, MRVL_IFACE_NAME_ARG,
2176                            mrvl_get_ifnames, &ifnames);
2177
2178         cfgnum = rte_kvargs_count(kvlist, MRVL_CFG_ARG);
2179         if (cfgnum > 1) {
2180                 RTE_LOG(ERR, PMD, "Cannot handle more than one config file!\n");
2181                 goto out_free_kvlist;
2182         } else if (cfgnum == 1) {
2183                 rte_kvargs_process(kvlist, MRVL_CFG_ARG,
2184                                    mrvl_get_qoscfg, &mrvl_qos_cfg);
2185         }
2186
2187         /*
2188          * ret == -EEXIST is correct, it means DMA
2189          * has been already initialized (by another PMD).
2190          */
2191         ret = mv_sys_dma_mem_init(MRVL_MUSDK_DMA_MEMSIZE);
2192         if (ret < 0) {
2193                 if (ret != -EEXIST)
2194                         goto out_free_kvlist;
2195                 else
2196                         RTE_LOG(INFO, PMD,
2197                                 "DMA memory has been already initialized by a different driver.\n");
2198         }
2199
2200         ret = mrvl_init_pp2();
2201         if (ret) {
2202                 RTE_LOG(ERR, PMD, "Failed to init PP!\n");
2203                 goto out_deinit_dma;
2204         }
2205
2206         ret = mrvl_init_hifs();
2207         if (ret)
2208                 goto out_deinit_hifs;
2209
2210         for (i = 0; i < ifnum; i++) {
2211                 RTE_LOG(INFO, PMD, "Creating %s\n", ifnames[i]);
2212                 ret = mrvl_eth_dev_create(vdev, ifnames[i]);
2213                 if (ret)
2214                         goto out_cleanup;
2215         }
2216
2217         rte_kvargs_free(kvlist);
2218
2219         memset(mrvl_port_bpool_size, 0, sizeof(mrvl_port_bpool_size));
2220
2221         mrvl_lcore_first = RTE_MAX_LCORE;
2222         mrvl_lcore_last = 0;
2223
2224         RTE_LCORE_FOREACH(core_id) {
2225                 mrvl_set_first_last_cores(core_id);
2226         }
2227
2228         return 0;
2229 out_cleanup:
2230         for (; i > 0; i--)
2231                 mrvl_eth_dev_destroy(ifnames[i]);
2232 out_deinit_hifs:
2233         mrvl_deinit_hifs();
2234         mrvl_deinit_pp2();
2235 out_deinit_dma:
2236         mv_sys_dma_mem_destroy();
2237 out_free_kvlist:
2238         rte_kvargs_free(kvlist);
2239
2240         return ret;
2241 }
2242
2243 /**
2244  * DPDK callback to remove virtual device.
2245  *
2246  * @param vdev
2247  *   Pointer to the removed virtual device.
2248  *
2249  * @return
2250  *   0 on success, negative error value otherwise.
2251  */
2252 static int
2253 rte_pmd_mrvl_remove(struct rte_vdev_device *vdev)
2254 {
2255         int i;
2256         const char *name;
2257
2258         name = rte_vdev_device_name(vdev);
2259         if (!name)
2260                 return -EINVAL;
2261
2262         RTE_LOG(INFO, PMD, "Removing %s\n", name);
2263
2264         for (i = 0; i < rte_eth_dev_count(); i++) {
2265                 char ifname[RTE_ETH_NAME_MAX_LEN];
2266
2267                 rte_eth_dev_get_name_by_port(i, ifname);
2268                 mrvl_eth_dev_destroy(ifname);
2269         }
2270
2271         mrvl_deinit_hifs();
2272         mrvl_deinit_pp2();
2273         mv_sys_dma_mem_destroy();
2274
2275         return 0;
2276 }
2277
2278 static struct rte_vdev_driver pmd_mrvl_drv = {
2279         .probe = rte_pmd_mrvl_probe,
2280         .remove = rte_pmd_mrvl_remove,
2281 };
2282
2283 RTE_PMD_REGISTER_VDEV(net_mrvl, pmd_mrvl_drv);
2284 RTE_PMD_REGISTER_ALIAS(net_mrvl, eth_mrvl);