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33 #ifndef _MRVL_ETHDEV_H_
34 #define _MRVL_ETHDEV_H_
36 #include <drivers/mv_pp2_cls.h>
37 #include <drivers/mv_pp2_ppio.h>
39 /** Maximum number of rx queues per port */
40 #define MRVL_PP2_RXQ_MAX 32
42 /** Maximum number of tx queues per port */
43 #define MRVL_PP2_TXQ_MAX 8
45 /** Minimum number of descriptors in tx queue */
46 #define MRVL_PP2_TXD_MIN 16
48 /** Maximum number of descriptors in tx queue */
49 #define MRVL_PP2_TXD_MAX 2048
51 /** Tx queue descriptors alignment */
52 #define MRVL_PP2_TXD_ALIGN 16
54 /** Minimum number of descriptors in rx queue */
55 #define MRVL_PP2_RXD_MIN 16
57 /** Maximum number of descriptors in rx queue */
58 #define MRVL_PP2_RXD_MAX 2048
60 /** Rx queue descriptors alignment */
61 #define MRVL_PP2_RXD_ALIGN 16
63 /** Maximum number of descriptors in tx aggregated queue */
64 #define MRVL_PP2_AGGR_TXQD_MAX 2048
66 /** Maximum number of Traffic Classes. */
67 #define MRVL_PP2_TC_MAX 8
69 /** Packet offset inside RX buffer. */
70 #define MRVL_PKT_OFFS 64
73 /* Hot fields, used in fast path. */
74 struct pp2_bpool *bpool; /**< BPool pointer */
75 struct pp2_ppio *ppio; /**< Port handler pointer */
76 uint16_t bpool_max_size; /**< BPool maximum size */
77 uint16_t bpool_min_size; /**< BPool minimum size */
78 uint16_t bpool_init_size; /**< Configured BPool size */
80 /** Mapping for DPDK rx queue->(TC, MRVL relative inq) */
82 uint8_t tc; /**< Traffic Class */
83 uint8_t inq; /**< Relative in-queue number */
84 } rxq_map[MRVL_PP2_RXQ_MAX] __rte_cache_aligned;
86 /* Configuration data, used sporadically. */
91 struct pp2_ppio_params ppio_params;
92 struct pp2_cls_qos_tbl_params qos_tbl_params;
93 struct pp2_cls_tbl *qos_tbl;
94 uint16_t nb_rx_queues;
97 /** Number of ports configured. */
98 extern int mrvl_ports_nb;
100 #endif /* _MRVL_ETHDEV_H_ */