1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2017 Marvell International Ltd.
3 * Copyright(c) 2017 Semihalf.
7 #include <rte_ethdev_driver.h>
8 #include <rte_kvargs.h>
10 #include <rte_malloc.h>
11 #include <rte_bus_vdev.h>
14 #include <linux/ethtool.h>
15 #include <linux/sockios.h>
17 #include <net/if_arp.h>
18 #include <sys/ioctl.h>
19 #include <sys/socket.h>
21 #include <sys/types.h>
23 #include <rte_mvep_common.h>
24 #include "mrvl_ethdev.h"
26 #include "mrvl_flow.h"
30 /* bitmask with reserved hifs */
31 #define MRVL_MUSDK_HIFS_RESERVED 0x0F
32 /* bitmask with reserved bpools */
33 #define MRVL_MUSDK_BPOOLS_RESERVED 0x07
34 /* bitmask with reserved kernel RSS tables */
35 #define MRVL_MUSDK_RSS_RESERVED 0x01
36 /* maximum number of available hifs */
37 #define MRVL_MUSDK_HIFS_MAX 9
40 #define MRVL_MUSDK_PREFETCH_SHIFT 2
42 /* TCAM has 25 entries reserved for uc/mc filter entries */
43 #define MRVL_MAC_ADDRS_MAX 25
44 #define MRVL_MATCH_LEN 16
45 #define MRVL_PKT_EFFEC_OFFS (MRVL_PKT_OFFS + MV_MH_SIZE)
46 /* Maximum allowable packet size */
47 #define MRVL_PKT_SIZE_MAX (10240 - MV_MH_SIZE)
49 #define MRVL_IFACE_NAME_ARG "iface"
50 #define MRVL_CFG_ARG "cfg"
52 #define MRVL_BURST_SIZE 64
54 #define MRVL_ARP_LENGTH 28
56 #define MRVL_COOKIE_ADDR_INVALID ~0ULL
57 #define MRVL_COOKIE_HIGH_ADDR_MASK 0xffffff0000000000
59 /** Port Rx offload capabilities */
60 #define MRVL_RX_OFFLOADS (DEV_RX_OFFLOAD_VLAN_FILTER | \
61 DEV_RX_OFFLOAD_JUMBO_FRAME | \
62 DEV_RX_OFFLOAD_CHECKSUM)
64 /** Port Tx offloads capabilities */
65 #define MRVL_TX_OFFLOADS (DEV_TX_OFFLOAD_IPV4_CKSUM | \
66 DEV_TX_OFFLOAD_UDP_CKSUM | \
67 DEV_TX_OFFLOAD_TCP_CKSUM)
69 static const char * const valid_args[] = {
75 static int used_hifs = MRVL_MUSDK_HIFS_RESERVED;
76 static struct pp2_hif *hifs[RTE_MAX_LCORE];
77 static int used_bpools[PP2_NUM_PKT_PROC] = {
78 [0 ... PP2_NUM_PKT_PROC - 1] = MRVL_MUSDK_BPOOLS_RESERVED
81 static struct pp2_bpool *mrvl_port_to_bpool_lookup[RTE_MAX_ETHPORTS];
82 static int mrvl_port_bpool_size[PP2_NUM_PKT_PROC][PP2_BPOOL_NUM_POOLS][RTE_MAX_LCORE];
83 static uint64_t cookie_addr_high = MRVL_COOKIE_ADDR_INVALID;
88 const char *names[PP2_NUM_ETH_PPIO * PP2_NUM_PKT_PROC];
93 * To use buffer harvesting based on loopback port shadow queue structure
94 * was introduced for buffers information bookkeeping.
96 * Before sending the packet, related buffer information (pp2_buff_inf) is
97 * stored in shadow queue. After packet is transmitted no longer used
98 * packet buffer is released back to it's original hardware pool,
99 * on condition it originated from interface.
100 * In case it was generated by application itself i.e: mbuf->port field is
101 * 0xff then its released to software mempool.
103 struct mrvl_shadow_txq {
104 int head; /* write index - used when sending buffers */
105 int tail; /* read index - used when releasing buffers */
106 u16 size; /* queue occupied size */
107 u16 num_to_release; /* number of buffers sent, that can be released */
108 struct buff_release_entry ent[MRVL_PP2_TX_SHADOWQ_SIZE]; /* q entries */
112 struct mrvl_priv *priv;
113 struct rte_mempool *mp;
122 struct mrvl_priv *priv;
126 struct mrvl_shadow_txq shadow_txqs[RTE_MAX_LCORE];
127 int tx_deferred_start;
130 static int mrvl_lcore_first;
131 static int mrvl_lcore_last;
132 static int mrvl_dev_num;
134 static int mrvl_fill_bpool(struct mrvl_rxq *rxq, int num);
135 static inline void mrvl_free_sent_buffers(struct pp2_ppio *ppio,
136 struct pp2_hif *hif, unsigned int core_id,
137 struct mrvl_shadow_txq *sq, int qid, int force);
139 #define MRVL_XSTATS_TBL_ENTRY(name) { \
140 #name, offsetof(struct pp2_ppio_statistics, name), \
141 sizeof(((struct pp2_ppio_statistics *)0)->name) \
144 /* Table with xstats data */
149 } mrvl_xstats_tbl[] = {
150 MRVL_XSTATS_TBL_ENTRY(rx_bytes),
151 MRVL_XSTATS_TBL_ENTRY(rx_packets),
152 MRVL_XSTATS_TBL_ENTRY(rx_unicast_packets),
153 MRVL_XSTATS_TBL_ENTRY(rx_errors),
154 MRVL_XSTATS_TBL_ENTRY(rx_fullq_dropped),
155 MRVL_XSTATS_TBL_ENTRY(rx_bm_dropped),
156 MRVL_XSTATS_TBL_ENTRY(rx_early_dropped),
157 MRVL_XSTATS_TBL_ENTRY(rx_fifo_dropped),
158 MRVL_XSTATS_TBL_ENTRY(rx_cls_dropped),
159 MRVL_XSTATS_TBL_ENTRY(tx_bytes),
160 MRVL_XSTATS_TBL_ENTRY(tx_packets),
161 MRVL_XSTATS_TBL_ENTRY(tx_unicast_packets),
162 MRVL_XSTATS_TBL_ENTRY(tx_errors)
166 mrvl_get_bpool_size(int pp2_id, int pool_id)
171 for (i = mrvl_lcore_first; i <= mrvl_lcore_last; i++)
172 size += mrvl_port_bpool_size[pp2_id][pool_id][i];
178 mrvl_reserve_bit(int *bitmap, int max)
180 int n = sizeof(*bitmap) * 8 - __builtin_clz(*bitmap);
191 mrvl_init_hif(int core_id)
193 struct pp2_hif_params params;
194 char match[MRVL_MATCH_LEN];
197 ret = mrvl_reserve_bit(&used_hifs, MRVL_MUSDK_HIFS_MAX);
199 MRVL_LOG(ERR, "Failed to allocate hif %d", core_id);
203 snprintf(match, sizeof(match), "hif-%d", ret);
204 memset(¶ms, 0, sizeof(params));
205 params.match = match;
206 params.out_size = MRVL_PP2_AGGR_TXQD_MAX;
207 ret = pp2_hif_init(¶ms, &hifs[core_id]);
209 MRVL_LOG(ERR, "Failed to initialize hif %d", core_id);
216 static inline struct pp2_hif*
217 mrvl_get_hif(struct mrvl_priv *priv, int core_id)
221 if (likely(hifs[core_id] != NULL))
222 return hifs[core_id];
224 rte_spinlock_lock(&priv->lock);
226 ret = mrvl_init_hif(core_id);
228 MRVL_LOG(ERR, "Failed to allocate hif %d", core_id);
232 if (core_id < mrvl_lcore_first)
233 mrvl_lcore_first = core_id;
235 if (core_id > mrvl_lcore_last)
236 mrvl_lcore_last = core_id;
238 rte_spinlock_unlock(&priv->lock);
240 return hifs[core_id];
244 * Configure rss based on dpdk rss configuration.
247 * Pointer to private structure.
249 * Pointer to RSS configuration.
252 * 0 on success, negative error value otherwise.
255 mrvl_configure_rss(struct mrvl_priv *priv, struct rte_eth_rss_conf *rss_conf)
257 if (rss_conf->rss_key)
258 MRVL_LOG(WARNING, "Changing hash key is not supported");
260 if (rss_conf->rss_hf == 0) {
261 priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE;
262 } else if (rss_conf->rss_hf & ETH_RSS_IPV4) {
263 priv->ppio_params.inqs_params.hash_type =
264 PP2_PPIO_HASH_T_2_TUPLE;
265 } else if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) {
266 priv->ppio_params.inqs_params.hash_type =
267 PP2_PPIO_HASH_T_5_TUPLE;
268 priv->rss_hf_tcp = 1;
269 } else if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) {
270 priv->ppio_params.inqs_params.hash_type =
271 PP2_PPIO_HASH_T_5_TUPLE;
272 priv->rss_hf_tcp = 0;
281 * Ethernet device configuration.
283 * Prepare the driver for a given number of TX and RX queues and
287 * Pointer to Ethernet device structure.
290 * 0 on success, negative error value otherwise.
293 mrvl_dev_configure(struct rte_eth_dev *dev)
295 struct mrvl_priv *priv = dev->data->dev_private;
299 MRVL_LOG(INFO, "Device reconfiguration is not supported");
303 if (dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_NONE &&
304 dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) {
305 MRVL_LOG(INFO, "Unsupported rx multi queue mode %d",
306 dev->data->dev_conf.rxmode.mq_mode);
310 if (dev->data->dev_conf.rxmode.split_hdr_size) {
311 MRVL_LOG(INFO, "Split headers not supported");
315 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
316 dev->data->mtu = dev->data->dev_conf.rxmode.max_rx_pkt_len -
317 MRVL_PP2_ETH_HDRS_LEN;
319 ret = mrvl_configure_rxqs(priv, dev->data->port_id,
320 dev->data->nb_rx_queues);
324 ret = mrvl_configure_txqs(priv, dev->data->port_id,
325 dev->data->nb_tx_queues);
329 priv->ppio_params.outqs_params.num_outqs = dev->data->nb_tx_queues;
330 priv->ppio_params.maintain_stats = 1;
331 priv->nb_rx_queues = dev->data->nb_rx_queues;
333 ret = mrvl_tm_init(dev);
337 if (dev->data->nb_rx_queues == 1 &&
338 dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) {
339 MRVL_LOG(WARNING, "Disabling hash for 1 rx queue");
340 priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE;
345 return mrvl_configure_rss(priv,
346 &dev->data->dev_conf.rx_adv_conf.rss_conf);
350 * DPDK callback to change the MTU.
352 * Setting the MTU affects hardware MRU (packets larger than the MRU
356 * Pointer to Ethernet device structure.
361 * 0 on success, negative error value otherwise.
364 mrvl_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
366 struct mrvl_priv *priv = dev->data->dev_private;
368 uint16_t mbuf_data_size = 0; /* SW buffer size */
371 mru = MRVL_PP2_MTU_TO_MRU(mtu);
373 * min_rx_buf_size is equal to mbuf data size
374 * if pmd didn't set it differently
376 mbuf_data_size = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM;
378 * - setting mru greater than the mbuf size resulting in
379 * hw and sw buffer size mismatch
380 * - setting mtu that requires the support of scattered packets
381 * when this feature has not been enabled/supported so far
382 * (TODO check scattered_rx flag here once scattered RX is supported).
384 if (mru + MRVL_PKT_OFFS > mbuf_data_size) {
385 mru = mbuf_data_size - MRVL_PKT_OFFS;
386 mtu = MRVL_PP2_MRU_TO_MTU(mru);
387 MRVL_LOG(WARNING, "MTU too big, max MTU possible limitted "
388 "by current mbuf size: %u. Set MTU to %u, MRU to %u",
389 mbuf_data_size, mtu, mru);
392 if (mtu < ETHER_MIN_MTU || mru > MRVL_PKT_SIZE_MAX) {
393 MRVL_LOG(ERR, "Invalid MTU [%u] or MRU [%u]", mtu, mru);
397 dev->data->mtu = mtu;
398 dev->data->dev_conf.rxmode.max_rx_pkt_len = mru - MV_MH_SIZE;
403 ret = pp2_ppio_set_mru(priv->ppio, mru);
405 MRVL_LOG(ERR, "Failed to change MRU");
409 ret = pp2_ppio_set_mtu(priv->ppio, mtu);
411 MRVL_LOG(ERR, "Failed to change MTU");
419 * DPDK callback to bring the link up.
422 * Pointer to Ethernet device structure.
425 * 0 on success, negative error value otherwise.
428 mrvl_dev_set_link_up(struct rte_eth_dev *dev)
430 struct mrvl_priv *priv = dev->data->dev_private;
436 ret = pp2_ppio_enable(priv->ppio);
441 * mtu/mru can be updated if pp2_ppio_enable() was called at least once
442 * as pp2_ppio_enable() changes port->t_mode from default 0 to
443 * PP2_TRAFFIC_INGRESS_EGRESS.
445 * Set mtu to default DPDK value here.
447 ret = mrvl_mtu_set(dev, dev->data->mtu);
449 pp2_ppio_disable(priv->ppio);
455 * DPDK callback to bring the link down.
458 * Pointer to Ethernet device structure.
461 * 0 on success, negative error value otherwise.
464 mrvl_dev_set_link_down(struct rte_eth_dev *dev)
466 struct mrvl_priv *priv = dev->data->dev_private;
471 return pp2_ppio_disable(priv->ppio);
475 * DPDK callback to start tx queue.
478 * Pointer to Ethernet device structure.
480 * Transmit queue index.
483 * 0 on success, negative error value otherwise.
486 mrvl_tx_queue_start(struct rte_eth_dev *dev, uint16_t queue_id)
488 struct mrvl_priv *priv = dev->data->dev_private;
494 /* passing 1 enables given tx queue */
495 ret = pp2_ppio_set_outq_state(priv->ppio, queue_id, 1);
497 MRVL_LOG(ERR, "Failed to start txq %d", queue_id);
501 dev->data->tx_queue_state[queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
507 * DPDK callback to stop tx queue.
510 * Pointer to Ethernet device structure.
512 * Transmit queue index.
515 * 0 on success, negative error value otherwise.
518 mrvl_tx_queue_stop(struct rte_eth_dev *dev, uint16_t queue_id)
520 struct mrvl_priv *priv = dev->data->dev_private;
526 /* passing 0 disables given tx queue */
527 ret = pp2_ppio_set_outq_state(priv->ppio, queue_id, 0);
529 MRVL_LOG(ERR, "Failed to stop txq %d", queue_id);
533 dev->data->tx_queue_state[queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
539 * DPDK callback to start the device.
542 * Pointer to Ethernet device structure.
545 * 0 on success, negative errno value on failure.
548 mrvl_dev_start(struct rte_eth_dev *dev)
550 struct mrvl_priv *priv = dev->data->dev_private;
551 char match[MRVL_MATCH_LEN];
552 int ret = 0, i, def_init_size;
555 return mrvl_dev_set_link_up(dev);
557 snprintf(match, sizeof(match), "ppio-%d:%d",
558 priv->pp_id, priv->ppio_id);
559 priv->ppio_params.match = match;
562 * Calculate the minimum bpool size for refill feature as follows:
563 * 2 default burst sizes multiply by number of rx queues.
564 * If the bpool size will be below this value, new buffers will
565 * be added to the pool.
567 priv->bpool_min_size = priv->nb_rx_queues * MRVL_BURST_SIZE * 2;
569 /* In case initial bpool size configured in queues setup is
570 * smaller than minimum size add more buffers
572 def_init_size = priv->bpool_min_size + MRVL_BURST_SIZE * 2;
573 if (priv->bpool_init_size < def_init_size) {
574 int buffs_to_add = def_init_size - priv->bpool_init_size;
576 priv->bpool_init_size += buffs_to_add;
577 ret = mrvl_fill_bpool(dev->data->rx_queues[0], buffs_to_add);
579 MRVL_LOG(ERR, "Failed to add buffers to bpool");
583 * Calculate the maximum bpool size for refill feature as follows:
584 * maximum number of descriptors in rx queue multiply by number
585 * of rx queues plus minimum bpool size.
586 * In case the bpool size will exceed this value, superfluous buffers
589 priv->bpool_max_size = (priv->nb_rx_queues * MRVL_PP2_RXD_MAX) +
590 priv->bpool_min_size;
592 ret = pp2_ppio_init(&priv->ppio_params, &priv->ppio);
594 MRVL_LOG(ERR, "Failed to init ppio");
599 * In case there are some some stale uc/mc mac addresses flush them
600 * here. It cannot be done during mrvl_dev_close() as port information
601 * is already gone at that point (due to pp2_ppio_deinit() in
604 if (!priv->uc_mc_flushed) {
605 ret = pp2_ppio_flush_mac_addrs(priv->ppio, 1, 1);
608 "Failed to flush uc/mc filter list");
611 priv->uc_mc_flushed = 1;
614 if (!priv->vlan_flushed) {
615 ret = pp2_ppio_flush_vlan(priv->ppio);
617 MRVL_LOG(ERR, "Failed to flush vlan list");
620 * once pp2_ppio_flush_vlan() is supported jump to out
624 priv->vlan_flushed = 1;
626 ret = mrvl_mtu_set(dev, dev->data->mtu);
628 MRVL_LOG(ERR, "Failed to set MTU to %d", dev->data->mtu);
630 /* For default QoS config, don't start classifier. */
632 mrvl_qos_cfg->port[dev->data->port_id].use_global_defaults == 0) {
633 ret = mrvl_start_qos_mapping(priv);
635 MRVL_LOG(ERR, "Failed to setup QoS mapping");
640 ret = mrvl_dev_set_link_up(dev);
642 MRVL_LOG(ERR, "Failed to set link up");
646 /* start tx queues */
647 for (i = 0; i < dev->data->nb_tx_queues; i++) {
648 struct mrvl_txq *txq = dev->data->tx_queues[i];
650 dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STARTED;
652 if (!txq->tx_deferred_start)
656 * All txqs are started by default. Stop them
657 * so that tx_deferred_start works as expected.
659 ret = mrvl_tx_queue_stop(dev, i);
669 MRVL_LOG(ERR, "Failed to start device");
670 pp2_ppio_deinit(priv->ppio);
675 * Flush receive queues.
678 * Pointer to Ethernet device structure.
681 mrvl_flush_rx_queues(struct rte_eth_dev *dev)
685 MRVL_LOG(INFO, "Flushing rx queues");
686 for (i = 0; i < dev->data->nb_rx_queues; i++) {
690 struct mrvl_rxq *q = dev->data->rx_queues[i];
691 struct pp2_ppio_desc descs[MRVL_PP2_RXD_MAX];
693 num = MRVL_PP2_RXD_MAX;
694 ret = pp2_ppio_recv(q->priv->ppio,
695 q->priv->rxq_map[q->queue_id].tc,
696 q->priv->rxq_map[q->queue_id].inq,
697 descs, (uint16_t *)&num);
698 } while (ret == 0 && num);
703 * Flush transmit shadow queues.
706 * Pointer to Ethernet device structure.
709 mrvl_flush_tx_shadow_queues(struct rte_eth_dev *dev)
712 struct mrvl_txq *txq;
714 MRVL_LOG(INFO, "Flushing tx shadow queues");
715 for (i = 0; i < dev->data->nb_tx_queues; i++) {
716 txq = (struct mrvl_txq *)dev->data->tx_queues[i];
718 for (j = 0; j < RTE_MAX_LCORE; j++) {
719 struct mrvl_shadow_txq *sq;
724 sq = &txq->shadow_txqs[j];
725 mrvl_free_sent_buffers(txq->priv->ppio,
726 hifs[j], j, sq, txq->queue_id, 1);
727 while (sq->tail != sq->head) {
728 uint64_t addr = cookie_addr_high |
729 sq->ent[sq->tail].buff.cookie;
731 (struct rte_mbuf *)addr);
732 sq->tail = (sq->tail + 1) &
733 MRVL_PP2_TX_SHADOWQ_MASK;
735 memset(sq, 0, sizeof(*sq));
741 * Flush hardware bpool (buffer-pool).
744 * Pointer to Ethernet device structure.
747 mrvl_flush_bpool(struct rte_eth_dev *dev)
749 struct mrvl_priv *priv = dev->data->dev_private;
753 unsigned int core_id = rte_lcore_id();
755 if (core_id == LCORE_ID_ANY)
758 hif = mrvl_get_hif(priv, core_id);
760 ret = pp2_bpool_get_num_buffs(priv->bpool, &num);
762 MRVL_LOG(ERR, "Failed to get bpool buffers number");
767 struct pp2_buff_inf inf;
770 ret = pp2_bpool_get_buff(hif, priv->bpool, &inf);
774 addr = cookie_addr_high | inf.cookie;
775 rte_pktmbuf_free((struct rte_mbuf *)addr);
780 * DPDK callback to stop the device.
783 * Pointer to Ethernet device structure.
786 mrvl_dev_stop(struct rte_eth_dev *dev)
788 mrvl_dev_set_link_down(dev);
792 * DPDK callback to close the device.
795 * Pointer to Ethernet device structure.
798 mrvl_dev_close(struct rte_eth_dev *dev)
800 struct mrvl_priv *priv = dev->data->dev_private;
803 mrvl_flush_rx_queues(dev);
804 mrvl_flush_tx_shadow_queues(dev);
805 mrvl_flow_deinit(dev);
806 mrvl_mtr_deinit(dev);
808 for (i = 0; i < priv->ppio_params.inqs_params.num_tcs; ++i) {
809 struct pp2_ppio_tc_params *tc_params =
810 &priv->ppio_params.inqs_params.tcs_params[i];
812 if (tc_params->inqs_params) {
813 rte_free(tc_params->inqs_params);
814 tc_params->inqs_params = NULL;
819 pp2_cls_tbl_deinit(priv->cls_tbl);
820 priv->cls_tbl = NULL;
824 pp2_cls_qos_tbl_deinit(priv->qos_tbl);
825 priv->qos_tbl = NULL;
828 mrvl_flush_bpool(dev);
832 pp2_ppio_deinit(priv->ppio);
836 /* policer must be released after ppio deinitialization */
837 if (priv->default_policer) {
838 pp2_cls_plcr_deinit(priv->default_policer);
839 priv->default_policer = NULL;
844 * DPDK callback to retrieve physical link information.
847 * Pointer to Ethernet device structure.
848 * @param wait_to_complete
849 * Wait for request completion (ignored).
852 * 0 on success, negative error value otherwise.
855 mrvl_link_update(struct rte_eth_dev *dev, int wait_to_complete __rte_unused)
859 * once MUSDK provides necessary API use it here
861 struct mrvl_priv *priv = dev->data->dev_private;
862 struct ethtool_cmd edata;
864 int ret, fd, link_up;
869 edata.cmd = ETHTOOL_GSET;
871 strcpy(req.ifr_name, dev->data->name);
872 req.ifr_data = (void *)&edata;
874 fd = socket(AF_INET, SOCK_DGRAM, 0);
878 ret = ioctl(fd, SIOCETHTOOL, &req);
886 switch (ethtool_cmd_speed(&edata)) {
888 dev->data->dev_link.link_speed = ETH_SPEED_NUM_10M;
891 dev->data->dev_link.link_speed = ETH_SPEED_NUM_100M;
894 dev->data->dev_link.link_speed = ETH_SPEED_NUM_1G;
897 dev->data->dev_link.link_speed = ETH_SPEED_NUM_10G;
900 dev->data->dev_link.link_speed = ETH_SPEED_NUM_NONE;
903 dev->data->dev_link.link_duplex = edata.duplex ? ETH_LINK_FULL_DUPLEX :
904 ETH_LINK_HALF_DUPLEX;
905 dev->data->dev_link.link_autoneg = edata.autoneg ? ETH_LINK_AUTONEG :
907 pp2_ppio_get_link_state(priv->ppio, &link_up);
908 dev->data->dev_link.link_status = link_up ? ETH_LINK_UP : ETH_LINK_DOWN;
914 * DPDK callback to enable promiscuous mode.
917 * Pointer to Ethernet device structure.
920 mrvl_promiscuous_enable(struct rte_eth_dev *dev)
922 struct mrvl_priv *priv = dev->data->dev_private;
931 ret = pp2_ppio_set_promisc(priv->ppio, 1);
933 MRVL_LOG(ERR, "Failed to enable promiscuous mode");
937 * DPDK callback to enable allmulti mode.
940 * Pointer to Ethernet device structure.
943 mrvl_allmulticast_enable(struct rte_eth_dev *dev)
945 struct mrvl_priv *priv = dev->data->dev_private;
954 ret = pp2_ppio_set_mc_promisc(priv->ppio, 1);
956 MRVL_LOG(ERR, "Failed enable all-multicast mode");
960 * DPDK callback to disable promiscuous mode.
963 * Pointer to Ethernet device structure.
966 mrvl_promiscuous_disable(struct rte_eth_dev *dev)
968 struct mrvl_priv *priv = dev->data->dev_private;
974 ret = pp2_ppio_set_promisc(priv->ppio, 0);
976 MRVL_LOG(ERR, "Failed to disable promiscuous mode");
980 * DPDK callback to disable allmulticast mode.
983 * Pointer to Ethernet device structure.
986 mrvl_allmulticast_disable(struct rte_eth_dev *dev)
988 struct mrvl_priv *priv = dev->data->dev_private;
994 ret = pp2_ppio_set_mc_promisc(priv->ppio, 0);
996 MRVL_LOG(ERR, "Failed to disable all-multicast mode");
1000 * DPDK callback to remove a MAC address.
1003 * Pointer to Ethernet device structure.
1005 * MAC address index.
1008 mrvl_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index)
1010 struct mrvl_priv *priv = dev->data->dev_private;
1011 char buf[ETHER_ADDR_FMT_SIZE];
1020 ret = pp2_ppio_remove_mac_addr(priv->ppio,
1021 dev->data->mac_addrs[index].addr_bytes);
1023 ether_format_addr(buf, sizeof(buf),
1024 &dev->data->mac_addrs[index]);
1025 MRVL_LOG(ERR, "Failed to remove mac %s", buf);
1030 * DPDK callback to add a MAC address.
1033 * Pointer to Ethernet device structure.
1035 * MAC address to register.
1037 * MAC address index.
1039 * VMDq pool index to associate address with (unused).
1042 * 0 on success, negative error value otherwise.
1045 mrvl_mac_addr_add(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1046 uint32_t index, uint32_t vmdq __rte_unused)
1048 struct mrvl_priv *priv = dev->data->dev_private;
1049 char buf[ETHER_ADDR_FMT_SIZE];
1056 /* For setting index 0, mrvl_mac_addr_set() should be used.*/
1063 * Maximum number of uc addresses can be tuned via kernel module mvpp2x
1064 * parameter uc_filter_max. Maximum number of mc addresses is then
1065 * MRVL_MAC_ADDRS_MAX - uc_filter_max. Currently it defaults to 4 and
1068 * If more than uc_filter_max uc addresses were added to filter list
1069 * then NIC will switch to promiscuous mode automatically.
1071 * If more than MRVL_MAC_ADDRS_MAX - uc_filter_max number mc addresses
1072 * were added to filter list then NIC will switch to all-multicast mode
1075 ret = pp2_ppio_add_mac_addr(priv->ppio, mac_addr->addr_bytes);
1077 ether_format_addr(buf, sizeof(buf), mac_addr);
1078 MRVL_LOG(ERR, "Failed to add mac %s", buf);
1086 * DPDK callback to set the primary MAC address.
1089 * Pointer to Ethernet device structure.
1091 * MAC address to register.
1094 * 0 on success, negative error value otherwise.
1097 mrvl_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr)
1099 struct mrvl_priv *priv = dev->data->dev_private;
1108 ret = pp2_ppio_set_mac_addr(priv->ppio, mac_addr->addr_bytes);
1110 char buf[ETHER_ADDR_FMT_SIZE];
1111 ether_format_addr(buf, sizeof(buf), mac_addr);
1112 MRVL_LOG(ERR, "Failed to set mac to %s", buf);
1119 * DPDK callback to get device statistics.
1122 * Pointer to Ethernet device structure.
1124 * Stats structure output buffer.
1127 * 0 on success, negative error value otherwise.
1130 mrvl_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1132 struct mrvl_priv *priv = dev->data->dev_private;
1133 struct pp2_ppio_statistics ppio_stats;
1134 uint64_t drop_mac = 0;
1135 unsigned int i, idx, ret;
1140 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1141 struct mrvl_rxq *rxq = dev->data->rx_queues[i];
1142 struct pp2_ppio_inq_statistics rx_stats;
1147 idx = rxq->queue_id;
1148 if (unlikely(idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)) {
1150 "rx queue %d stats out of range (0 - %d)",
1151 idx, RTE_ETHDEV_QUEUE_STAT_CNTRS - 1);
1155 ret = pp2_ppio_inq_get_statistics(priv->ppio,
1156 priv->rxq_map[idx].tc,
1157 priv->rxq_map[idx].inq,
1159 if (unlikely(ret)) {
1161 "Failed to update rx queue %d stats", idx);
1165 stats->q_ibytes[idx] = rxq->bytes_recv;
1166 stats->q_ipackets[idx] = rx_stats.enq_desc - rxq->drop_mac;
1167 stats->q_errors[idx] = rx_stats.drop_early +
1168 rx_stats.drop_fullq +
1171 stats->ibytes += rxq->bytes_recv;
1172 drop_mac += rxq->drop_mac;
1175 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1176 struct mrvl_txq *txq = dev->data->tx_queues[i];
1177 struct pp2_ppio_outq_statistics tx_stats;
1182 idx = txq->queue_id;
1183 if (unlikely(idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)) {
1185 "tx queue %d stats out of range (0 - %d)",
1186 idx, RTE_ETHDEV_QUEUE_STAT_CNTRS - 1);
1189 ret = pp2_ppio_outq_get_statistics(priv->ppio, idx,
1191 if (unlikely(ret)) {
1193 "Failed to update tx queue %d stats", idx);
1197 stats->q_opackets[idx] = tx_stats.deq_desc;
1198 stats->q_obytes[idx] = txq->bytes_sent;
1199 stats->obytes += txq->bytes_sent;
1202 ret = pp2_ppio_get_statistics(priv->ppio, &ppio_stats, 0);
1203 if (unlikely(ret)) {
1204 MRVL_LOG(ERR, "Failed to update port statistics");
1208 stats->ipackets += ppio_stats.rx_packets - drop_mac;
1209 stats->opackets += ppio_stats.tx_packets;
1210 stats->imissed += ppio_stats.rx_fullq_dropped +
1211 ppio_stats.rx_bm_dropped +
1212 ppio_stats.rx_early_dropped +
1213 ppio_stats.rx_fifo_dropped +
1214 ppio_stats.rx_cls_dropped;
1215 stats->ierrors = drop_mac;
1221 * DPDK callback to clear device statistics.
1224 * Pointer to Ethernet device structure.
1227 mrvl_stats_reset(struct rte_eth_dev *dev)
1229 struct mrvl_priv *priv = dev->data->dev_private;
1235 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1236 struct mrvl_rxq *rxq = dev->data->rx_queues[i];
1238 pp2_ppio_inq_get_statistics(priv->ppio, priv->rxq_map[i].tc,
1239 priv->rxq_map[i].inq, NULL, 1);
1240 rxq->bytes_recv = 0;
1244 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1245 struct mrvl_txq *txq = dev->data->tx_queues[i];
1247 pp2_ppio_outq_get_statistics(priv->ppio, i, NULL, 1);
1248 txq->bytes_sent = 0;
1251 pp2_ppio_get_statistics(priv->ppio, NULL, 1);
1255 * DPDK callback to get extended statistics.
1258 * Pointer to Ethernet device structure.
1260 * Pointer to xstats table.
1262 * Number of entries in xstats table.
1264 * Negative value on error, number of read xstats otherwise.
1267 mrvl_xstats_get(struct rte_eth_dev *dev,
1268 struct rte_eth_xstat *stats, unsigned int n)
1270 struct mrvl_priv *priv = dev->data->dev_private;
1271 struct pp2_ppio_statistics ppio_stats;
1277 pp2_ppio_get_statistics(priv->ppio, &ppio_stats, 0);
1278 for (i = 0; i < n && i < RTE_DIM(mrvl_xstats_tbl); i++) {
1281 if (mrvl_xstats_tbl[i].size == sizeof(uint32_t))
1282 val = *(uint32_t *)((uint8_t *)&ppio_stats +
1283 mrvl_xstats_tbl[i].offset);
1284 else if (mrvl_xstats_tbl[i].size == sizeof(uint64_t))
1285 val = *(uint64_t *)((uint8_t *)&ppio_stats +
1286 mrvl_xstats_tbl[i].offset);
1291 stats[i].value = val;
1298 * DPDK callback to reset extended statistics.
1301 * Pointer to Ethernet device structure.
1304 mrvl_xstats_reset(struct rte_eth_dev *dev)
1306 mrvl_stats_reset(dev);
1310 * DPDK callback to get extended statistics names.
1312 * @param dev (unused)
1313 * Pointer to Ethernet device structure.
1314 * @param xstats_names
1315 * Pointer to xstats names table.
1317 * Size of the xstats names table.
1319 * Number of read names.
1322 mrvl_xstats_get_names(struct rte_eth_dev *dev __rte_unused,
1323 struct rte_eth_xstat_name *xstats_names,
1329 return RTE_DIM(mrvl_xstats_tbl);
1331 for (i = 0; i < size && i < RTE_DIM(mrvl_xstats_tbl); i++)
1332 snprintf(xstats_names[i].name, RTE_ETH_XSTATS_NAME_SIZE, "%s",
1333 mrvl_xstats_tbl[i].name);
1339 * DPDK callback to get information about the device.
1342 * Pointer to Ethernet device structure (unused).
1344 * Info structure output buffer.
1347 mrvl_dev_infos_get(struct rte_eth_dev *dev __rte_unused,
1348 struct rte_eth_dev_info *info)
1350 info->speed_capa = ETH_LINK_SPEED_10M |
1351 ETH_LINK_SPEED_100M |
1355 info->max_rx_queues = MRVL_PP2_RXQ_MAX;
1356 info->max_tx_queues = MRVL_PP2_TXQ_MAX;
1357 info->max_mac_addrs = MRVL_MAC_ADDRS_MAX;
1359 info->rx_desc_lim.nb_max = MRVL_PP2_RXD_MAX;
1360 info->rx_desc_lim.nb_min = MRVL_PP2_RXD_MIN;
1361 info->rx_desc_lim.nb_align = MRVL_PP2_RXD_ALIGN;
1363 info->tx_desc_lim.nb_max = MRVL_PP2_TXD_MAX;
1364 info->tx_desc_lim.nb_min = MRVL_PP2_TXD_MIN;
1365 info->tx_desc_lim.nb_align = MRVL_PP2_TXD_ALIGN;
1367 info->rx_offload_capa = MRVL_RX_OFFLOADS;
1368 info->rx_queue_offload_capa = MRVL_RX_OFFLOADS;
1370 info->tx_offload_capa = MRVL_TX_OFFLOADS;
1371 info->tx_queue_offload_capa = MRVL_TX_OFFLOADS;
1373 info->flow_type_rss_offloads = ETH_RSS_IPV4 |
1374 ETH_RSS_NONFRAG_IPV4_TCP |
1375 ETH_RSS_NONFRAG_IPV4_UDP;
1377 /* By default packets are dropped if no descriptors are available */
1378 info->default_rxconf.rx_drop_en = 1;
1380 info->max_rx_pktlen = MRVL_PKT_SIZE_MAX;
1384 * Return supported packet types.
1387 * Pointer to Ethernet device structure (unused).
1390 * Const pointer to the table with supported packet types.
1392 static const uint32_t *
1393 mrvl_dev_supported_ptypes_get(struct rte_eth_dev *dev __rte_unused)
1395 static const uint32_t ptypes[] = {
1397 RTE_PTYPE_L2_ETHER_VLAN,
1398 RTE_PTYPE_L2_ETHER_QINQ,
1400 RTE_PTYPE_L3_IPV4_EXT,
1401 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1403 RTE_PTYPE_L3_IPV6_EXT,
1404 RTE_PTYPE_L2_ETHER_ARP,
1413 * DPDK callback to get information about specific receive queue.
1416 * Pointer to Ethernet device structure.
1417 * @param rx_queue_id
1418 * Receive queue index.
1420 * Receive queue information structure.
1422 static void mrvl_rxq_info_get(struct rte_eth_dev *dev, uint16_t rx_queue_id,
1423 struct rte_eth_rxq_info *qinfo)
1425 struct mrvl_rxq *q = dev->data->rx_queues[rx_queue_id];
1426 struct mrvl_priv *priv = dev->data->dev_private;
1427 int inq = priv->rxq_map[rx_queue_id].inq;
1428 int tc = priv->rxq_map[rx_queue_id].tc;
1429 struct pp2_ppio_tc_params *tc_params =
1430 &priv->ppio_params.inqs_params.tcs_params[tc];
1433 qinfo->nb_desc = tc_params->inqs_params[inq].size;
1437 * DPDK callback to get information about specific transmit queue.
1440 * Pointer to Ethernet device structure.
1441 * @param tx_queue_id
1442 * Transmit queue index.
1444 * Transmit queue information structure.
1446 static void mrvl_txq_info_get(struct rte_eth_dev *dev, uint16_t tx_queue_id,
1447 struct rte_eth_txq_info *qinfo)
1449 struct mrvl_priv *priv = dev->data->dev_private;
1450 struct mrvl_txq *txq = dev->data->tx_queues[tx_queue_id];
1453 priv->ppio_params.outqs_params.outqs_params[tx_queue_id].size;
1454 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1458 * DPDK callback to Configure a VLAN filter.
1461 * Pointer to Ethernet device structure.
1463 * VLAN ID to filter.
1468 * 0 on success, negative error value otherwise.
1471 mrvl_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1473 struct mrvl_priv *priv = dev->data->dev_private;
1481 return on ? pp2_ppio_add_vlan(priv->ppio, vlan_id) :
1482 pp2_ppio_remove_vlan(priv->ppio, vlan_id);
1486 * Release buffers to hardware bpool (buffer-pool)
1489 * Receive queue pointer.
1491 * Number of buffers to release to bpool.
1494 * 0 on success, negative error value otherwise.
1497 mrvl_fill_bpool(struct mrvl_rxq *rxq, int num)
1499 struct buff_release_entry entries[MRVL_PP2_RXD_MAX];
1500 struct rte_mbuf *mbufs[MRVL_PP2_RXD_MAX];
1502 unsigned int core_id;
1503 struct pp2_hif *hif;
1504 struct pp2_bpool *bpool;
1506 core_id = rte_lcore_id();
1507 if (core_id == LCORE_ID_ANY)
1510 hif = mrvl_get_hif(rxq->priv, core_id);
1514 bpool = rxq->priv->bpool;
1516 ret = rte_pktmbuf_alloc_bulk(rxq->mp, mbufs, num);
1520 if (cookie_addr_high == MRVL_COOKIE_ADDR_INVALID)
1522 (uint64_t)mbufs[0] & MRVL_COOKIE_HIGH_ADDR_MASK;
1524 for (i = 0; i < num; i++) {
1525 if (((uint64_t)mbufs[i] & MRVL_COOKIE_HIGH_ADDR_MASK)
1526 != cookie_addr_high) {
1528 "mbuf virtual addr high 0x%lx out of range",
1529 (uint64_t)mbufs[i] >> 32);
1533 entries[i].buff.addr =
1534 rte_mbuf_data_iova_default(mbufs[i]);
1535 entries[i].buff.cookie = (uint64_t)mbufs[i];
1536 entries[i].bpool = bpool;
1539 pp2_bpool_put_buffs(hif, entries, (uint16_t *)&i);
1540 mrvl_port_bpool_size[bpool->pp2_id][bpool->id][core_id] += i;
1547 for (; i < num; i++)
1548 rte_pktmbuf_free(mbufs[i]);
1554 * DPDK callback to configure the receive queue.
1557 * Pointer to Ethernet device structure.
1561 * Number of descriptors to configure in queue.
1563 * NUMA socket on which memory must be allocated.
1565 * Thresholds parameters.
1567 * Memory pool for buffer allocations.
1570 * 0 on success, negative error value otherwise.
1573 mrvl_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1574 unsigned int socket,
1575 const struct rte_eth_rxconf *conf,
1576 struct rte_mempool *mp)
1578 struct mrvl_priv *priv = dev->data->dev_private;
1579 struct mrvl_rxq *rxq;
1580 uint32_t frame_size, buf_size = rte_pktmbuf_data_room_size(mp);
1581 uint32_t max_rx_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
1585 offloads = conf->offloads | dev->data->dev_conf.rxmode.offloads;
1587 if (priv->rxq_map[idx].tc == MRVL_UNKNOWN_TC) {
1589 * Unknown TC mapping, mapping will not have a correct queue.
1591 MRVL_LOG(ERR, "Unknown TC mapping for queue %hu eth%hhu",
1592 idx, priv->ppio_id);
1596 frame_size = buf_size - RTE_PKTMBUF_HEADROOM - MRVL_PKT_EFFEC_OFFS;
1597 if (frame_size < max_rx_pkt_len) {
1599 "Mbuf size must be increased to %u bytes to hold up "
1600 "to %u bytes of data.",
1601 buf_size + max_rx_pkt_len - frame_size,
1603 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1604 MRVL_LOG(INFO, "Setting max rx pkt len to %u",
1605 dev->data->dev_conf.rxmode.max_rx_pkt_len);
1608 if (dev->data->rx_queues[idx]) {
1609 rte_free(dev->data->rx_queues[idx]);
1610 dev->data->rx_queues[idx] = NULL;
1613 rxq = rte_zmalloc_socket("rxq", sizeof(*rxq), 0, socket);
1619 rxq->cksum_enabled = offloads & DEV_RX_OFFLOAD_IPV4_CKSUM;
1620 rxq->queue_id = idx;
1621 rxq->port_id = dev->data->port_id;
1622 mrvl_port_to_bpool_lookup[rxq->port_id] = priv->bpool;
1624 tc = priv->rxq_map[rxq->queue_id].tc,
1625 inq = priv->rxq_map[rxq->queue_id].inq;
1626 priv->ppio_params.inqs_params.tcs_params[tc].inqs_params[inq].size =
1629 ret = mrvl_fill_bpool(rxq, desc);
1635 priv->bpool_init_size += desc;
1637 dev->data->rx_queues[idx] = rxq;
1643 * DPDK callback to release the receive queue.
1646 * Generic receive queue pointer.
1649 mrvl_rx_queue_release(void *rxq)
1651 struct mrvl_rxq *q = rxq;
1652 struct pp2_ppio_tc_params *tc_params;
1653 int i, num, tc, inq;
1654 struct pp2_hif *hif;
1655 unsigned int core_id = rte_lcore_id();
1657 if (core_id == LCORE_ID_ANY)
1663 hif = mrvl_get_hif(q->priv, core_id);
1668 tc = q->priv->rxq_map[q->queue_id].tc;
1669 inq = q->priv->rxq_map[q->queue_id].inq;
1670 tc_params = &q->priv->ppio_params.inqs_params.tcs_params[tc];
1671 num = tc_params->inqs_params[inq].size;
1672 for (i = 0; i < num; i++) {
1673 struct pp2_buff_inf inf;
1676 pp2_bpool_get_buff(hif, q->priv->bpool, &inf);
1677 addr = cookie_addr_high | inf.cookie;
1678 rte_pktmbuf_free((struct rte_mbuf *)addr);
1685 * DPDK callback to configure the transmit queue.
1688 * Pointer to Ethernet device structure.
1690 * Transmit queue index.
1692 * Number of descriptors to configure in the queue.
1694 * NUMA socket on which memory must be allocated.
1696 * Tx queue configuration parameters.
1699 * 0 on success, negative error value otherwise.
1702 mrvl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1703 unsigned int socket,
1704 const struct rte_eth_txconf *conf)
1706 struct mrvl_priv *priv = dev->data->dev_private;
1707 struct mrvl_txq *txq;
1709 if (dev->data->tx_queues[idx]) {
1710 rte_free(dev->data->tx_queues[idx]);
1711 dev->data->tx_queues[idx] = NULL;
1714 txq = rte_zmalloc_socket("txq", sizeof(*txq), 0, socket);
1719 txq->queue_id = idx;
1720 txq->port_id = dev->data->port_id;
1721 txq->tx_deferred_start = conf->tx_deferred_start;
1722 dev->data->tx_queues[idx] = txq;
1724 priv->ppio_params.outqs_params.outqs_params[idx].size = desc;
1730 * DPDK callback to release the transmit queue.
1733 * Generic transmit queue pointer.
1736 mrvl_tx_queue_release(void *txq)
1738 struct mrvl_txq *q = txq;
1747 * DPDK callback to get flow control configuration.
1750 * Pointer to Ethernet device structure.
1752 * Pointer to the flow control configuration.
1755 * 0 on success, negative error value otherwise.
1758 mrvl_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1760 struct mrvl_priv *priv = dev->data->dev_private;
1766 ret = pp2_ppio_get_rx_pause(priv->ppio, &en);
1768 MRVL_LOG(ERR, "Failed to read rx pause state");
1772 fc_conf->mode = en ? RTE_FC_RX_PAUSE : RTE_FC_NONE;
1778 * DPDK callback to set flow control configuration.
1781 * Pointer to Ethernet device structure.
1783 * Pointer to the flow control configuration.
1786 * 0 on success, negative error value otherwise.
1789 mrvl_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1791 struct mrvl_priv *priv = dev->data->dev_private;
1796 if (fc_conf->high_water ||
1797 fc_conf->low_water ||
1798 fc_conf->pause_time ||
1799 fc_conf->mac_ctrl_frame_fwd ||
1801 MRVL_LOG(ERR, "Flowctrl parameter is not supported");
1806 if (fc_conf->mode == RTE_FC_NONE ||
1807 fc_conf->mode == RTE_FC_RX_PAUSE) {
1810 en = fc_conf->mode == RTE_FC_NONE ? 0 : 1;
1811 ret = pp2_ppio_set_rx_pause(priv->ppio, en);
1814 "Failed to change flowctrl on RX side");
1823 * Update RSS hash configuration
1826 * Pointer to Ethernet device structure.
1828 * Pointer to RSS configuration.
1831 * 0 on success, negative error value otherwise.
1834 mrvl_rss_hash_update(struct rte_eth_dev *dev,
1835 struct rte_eth_rss_conf *rss_conf)
1837 struct mrvl_priv *priv = dev->data->dev_private;
1842 return mrvl_configure_rss(priv, rss_conf);
1846 * DPDK callback to get RSS hash configuration.
1849 * Pointer to Ethernet device structure.
1851 * Pointer to RSS configuration.
1857 mrvl_rss_hash_conf_get(struct rte_eth_dev *dev,
1858 struct rte_eth_rss_conf *rss_conf)
1860 struct mrvl_priv *priv = dev->data->dev_private;
1861 enum pp2_ppio_hash_type hash_type =
1862 priv->ppio_params.inqs_params.hash_type;
1864 rss_conf->rss_key = NULL;
1866 if (hash_type == PP2_PPIO_HASH_T_NONE)
1867 rss_conf->rss_hf = 0;
1868 else if (hash_type == PP2_PPIO_HASH_T_2_TUPLE)
1869 rss_conf->rss_hf = ETH_RSS_IPV4;
1870 else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && priv->rss_hf_tcp)
1871 rss_conf->rss_hf = ETH_RSS_NONFRAG_IPV4_TCP;
1872 else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && !priv->rss_hf_tcp)
1873 rss_conf->rss_hf = ETH_RSS_NONFRAG_IPV4_UDP;
1879 * DPDK callback to get rte_flow callbacks.
1882 * Pointer to the device structure.
1886 * Flow filter operation.
1888 * Pointer to pass the flow ops.
1891 * 0 on success, negative error value otherwise.
1894 mrvl_eth_filter_ctrl(struct rte_eth_dev *dev __rte_unused,
1895 enum rte_filter_type filter_type,
1896 enum rte_filter_op filter_op, void *arg)
1898 switch (filter_type) {
1899 case RTE_ETH_FILTER_GENERIC:
1900 if (filter_op != RTE_ETH_FILTER_GET)
1902 *(const void **)arg = &mrvl_flow_ops;
1905 MRVL_LOG(WARNING, "Filter type (%d) not supported",
1912 * DPDK callback to get rte_mtr callbacks.
1915 * Pointer to the device structure.
1917 * Pointer to pass the mtr ops.
1923 mrvl_mtr_ops_get(struct rte_eth_dev *dev __rte_unused, void *ops)
1925 *(const void **)ops = &mrvl_mtr_ops;
1931 * DPDK callback to get rte_tm callbacks.
1934 * Pointer to the device structure.
1936 * Pointer to pass the tm ops.
1942 mrvl_tm_ops_get(struct rte_eth_dev *dev __rte_unused, void *ops)
1944 *(const void **)ops = &mrvl_tm_ops;
1949 static const struct eth_dev_ops mrvl_ops = {
1950 .dev_configure = mrvl_dev_configure,
1951 .dev_start = mrvl_dev_start,
1952 .dev_stop = mrvl_dev_stop,
1953 .dev_set_link_up = mrvl_dev_set_link_up,
1954 .dev_set_link_down = mrvl_dev_set_link_down,
1955 .dev_close = mrvl_dev_close,
1956 .link_update = mrvl_link_update,
1957 .promiscuous_enable = mrvl_promiscuous_enable,
1958 .allmulticast_enable = mrvl_allmulticast_enable,
1959 .promiscuous_disable = mrvl_promiscuous_disable,
1960 .allmulticast_disable = mrvl_allmulticast_disable,
1961 .mac_addr_remove = mrvl_mac_addr_remove,
1962 .mac_addr_add = mrvl_mac_addr_add,
1963 .mac_addr_set = mrvl_mac_addr_set,
1964 .mtu_set = mrvl_mtu_set,
1965 .stats_get = mrvl_stats_get,
1966 .stats_reset = mrvl_stats_reset,
1967 .xstats_get = mrvl_xstats_get,
1968 .xstats_reset = mrvl_xstats_reset,
1969 .xstats_get_names = mrvl_xstats_get_names,
1970 .dev_infos_get = mrvl_dev_infos_get,
1971 .dev_supported_ptypes_get = mrvl_dev_supported_ptypes_get,
1972 .rxq_info_get = mrvl_rxq_info_get,
1973 .txq_info_get = mrvl_txq_info_get,
1974 .vlan_filter_set = mrvl_vlan_filter_set,
1975 .tx_queue_start = mrvl_tx_queue_start,
1976 .tx_queue_stop = mrvl_tx_queue_stop,
1977 .rx_queue_setup = mrvl_rx_queue_setup,
1978 .rx_queue_release = mrvl_rx_queue_release,
1979 .tx_queue_setup = mrvl_tx_queue_setup,
1980 .tx_queue_release = mrvl_tx_queue_release,
1981 .flow_ctrl_get = mrvl_flow_ctrl_get,
1982 .flow_ctrl_set = mrvl_flow_ctrl_set,
1983 .rss_hash_update = mrvl_rss_hash_update,
1984 .rss_hash_conf_get = mrvl_rss_hash_conf_get,
1985 .filter_ctrl = mrvl_eth_filter_ctrl,
1986 .mtr_ops_get = mrvl_mtr_ops_get,
1987 .tm_ops_get = mrvl_tm_ops_get,
1991 * Return packet type information and l3/l4 offsets.
1994 * Pointer to the received packet descriptor.
2001 * Packet type information.
2003 static inline uint64_t
2004 mrvl_desc_to_packet_type_and_offset(struct pp2_ppio_desc *desc,
2005 uint8_t *l3_offset, uint8_t *l4_offset)
2007 enum pp2_inq_l3_type l3_type;
2008 enum pp2_inq_l4_type l4_type;
2009 enum pp2_inq_vlan_tag vlan_tag;
2010 uint64_t packet_type;
2012 pp2_ppio_inq_desc_get_l3_info(desc, &l3_type, l3_offset);
2013 pp2_ppio_inq_desc_get_l4_info(desc, &l4_type, l4_offset);
2014 pp2_ppio_inq_desc_get_vlan_tag(desc, &vlan_tag);
2016 packet_type = RTE_PTYPE_L2_ETHER;
2019 case PP2_INQ_VLAN_TAG_SINGLE:
2020 packet_type |= RTE_PTYPE_L2_ETHER_VLAN;
2022 case PP2_INQ_VLAN_TAG_DOUBLE:
2023 case PP2_INQ_VLAN_TAG_TRIPLE:
2024 packet_type |= RTE_PTYPE_L2_ETHER_QINQ;
2031 case PP2_INQ_L3_TYPE_IPV4_NO_OPTS:
2032 packet_type |= RTE_PTYPE_L3_IPV4;
2034 case PP2_INQ_L3_TYPE_IPV4_OK:
2035 packet_type |= RTE_PTYPE_L3_IPV4_EXT;
2037 case PP2_INQ_L3_TYPE_IPV4_TTL_ZERO:
2038 packet_type |= RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
2040 case PP2_INQ_L3_TYPE_IPV6_NO_EXT:
2041 packet_type |= RTE_PTYPE_L3_IPV6;
2043 case PP2_INQ_L3_TYPE_IPV6_EXT:
2044 packet_type |= RTE_PTYPE_L3_IPV6_EXT;
2046 case PP2_INQ_L3_TYPE_ARP:
2047 packet_type |= RTE_PTYPE_L2_ETHER_ARP;
2049 * In case of ARP l4_offset is set to wrong value.
2050 * Set it to proper one so that later on mbuf->l3_len can be
2051 * calculated subtracting l4_offset and l3_offset.
2053 *l4_offset = *l3_offset + MRVL_ARP_LENGTH;
2056 MRVL_LOG(DEBUG, "Failed to recognise l3 packet type");
2061 case PP2_INQ_L4_TYPE_TCP:
2062 packet_type |= RTE_PTYPE_L4_TCP;
2064 case PP2_INQ_L4_TYPE_UDP:
2065 packet_type |= RTE_PTYPE_L4_UDP;
2068 MRVL_LOG(DEBUG, "Failed to recognise l4 packet type");
2076 * Get offload information from the received packet descriptor.
2079 * Pointer to the received packet descriptor.
2082 * Mbuf offload flags.
2084 static inline uint64_t
2085 mrvl_desc_to_ol_flags(struct pp2_ppio_desc *desc)
2088 enum pp2_inq_desc_status status;
2090 status = pp2_ppio_inq_desc_get_l3_pkt_error(desc);
2091 if (unlikely(status != PP2_DESC_ERR_OK))
2092 flags = PKT_RX_IP_CKSUM_BAD;
2094 flags = PKT_RX_IP_CKSUM_GOOD;
2096 status = pp2_ppio_inq_desc_get_l4_pkt_error(desc);
2097 if (unlikely(status != PP2_DESC_ERR_OK))
2098 flags |= PKT_RX_L4_CKSUM_BAD;
2100 flags |= PKT_RX_L4_CKSUM_GOOD;
2106 * DPDK callback for receive.
2109 * Generic pointer to the receive queue.
2111 * Array to store received packets.
2113 * Maximum number of packets in array.
2116 * Number of packets successfully received.
2119 mrvl_rx_pkt_burst(void *rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
2121 struct mrvl_rxq *q = rxq;
2122 struct pp2_ppio_desc descs[nb_pkts];
2123 struct pp2_bpool *bpool;
2124 int i, ret, rx_done = 0;
2126 struct pp2_hif *hif;
2127 unsigned int core_id = rte_lcore_id();
2129 hif = mrvl_get_hif(q->priv, core_id);
2131 if (unlikely(!q->priv->ppio || !hif))
2134 bpool = q->priv->bpool;
2136 ret = pp2_ppio_recv(q->priv->ppio, q->priv->rxq_map[q->queue_id].tc,
2137 q->priv->rxq_map[q->queue_id].inq, descs, &nb_pkts);
2138 if (unlikely(ret < 0)) {
2139 MRVL_LOG(ERR, "Failed to receive packets");
2142 mrvl_port_bpool_size[bpool->pp2_id][bpool->id][core_id] -= nb_pkts;
2144 for (i = 0; i < nb_pkts; i++) {
2145 struct rte_mbuf *mbuf;
2146 uint8_t l3_offset, l4_offset;
2147 enum pp2_inq_desc_status status;
2150 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) {
2151 struct pp2_ppio_desc *pref_desc;
2154 pref_desc = &descs[i + MRVL_MUSDK_PREFETCH_SHIFT];
2155 pref_addr = cookie_addr_high |
2156 pp2_ppio_inq_desc_get_cookie(pref_desc);
2157 rte_mbuf_prefetch_part1((struct rte_mbuf *)(pref_addr));
2158 rte_mbuf_prefetch_part2((struct rte_mbuf *)(pref_addr));
2161 addr = cookie_addr_high |
2162 pp2_ppio_inq_desc_get_cookie(&descs[i]);
2163 mbuf = (struct rte_mbuf *)addr;
2164 rte_pktmbuf_reset(mbuf);
2166 /* drop packet in case of mac, overrun or resource error */
2167 status = pp2_ppio_inq_desc_get_l2_pkt_error(&descs[i]);
2168 if (unlikely(status != PP2_DESC_ERR_OK)) {
2169 struct pp2_buff_inf binf = {
2170 .addr = rte_mbuf_data_iova_default(mbuf),
2171 .cookie = (uint64_t)mbuf,
2174 pp2_bpool_put_buff(hif, bpool, &binf);
2175 mrvl_port_bpool_size
2176 [bpool->pp2_id][bpool->id][core_id]++;
2181 mbuf->data_off += MRVL_PKT_EFFEC_OFFS;
2182 mbuf->pkt_len = pp2_ppio_inq_desc_get_pkt_len(&descs[i]);
2183 mbuf->data_len = mbuf->pkt_len;
2184 mbuf->port = q->port_id;
2186 mrvl_desc_to_packet_type_and_offset(&descs[i],
2189 mbuf->l2_len = l3_offset;
2190 mbuf->l3_len = l4_offset - l3_offset;
2192 if (likely(q->cksum_enabled))
2193 mbuf->ol_flags = mrvl_desc_to_ol_flags(&descs[i]);
2195 rx_pkts[rx_done++] = mbuf;
2196 q->bytes_recv += mbuf->pkt_len;
2199 if (rte_spinlock_trylock(&q->priv->lock) == 1) {
2200 num = mrvl_get_bpool_size(bpool->pp2_id, bpool->id);
2202 if (unlikely(num <= q->priv->bpool_min_size ||
2203 (!rx_done && num < q->priv->bpool_init_size))) {
2204 ret = mrvl_fill_bpool(q, MRVL_BURST_SIZE);
2206 MRVL_LOG(ERR, "Failed to fill bpool");
2207 } else if (unlikely(num > q->priv->bpool_max_size)) {
2209 int pkt_to_remove = num - q->priv->bpool_init_size;
2210 struct rte_mbuf *mbuf;
2211 struct pp2_buff_inf buff;
2214 "port-%d:%d: bpool %d oversize - remove %d buffers (pool size: %d -> %d)",
2215 bpool->pp2_id, q->priv->ppio->port_id,
2216 bpool->id, pkt_to_remove, num,
2217 q->priv->bpool_init_size);
2219 for (i = 0; i < pkt_to_remove; i++) {
2220 ret = pp2_bpool_get_buff(hif, bpool, &buff);
2223 mbuf = (struct rte_mbuf *)
2224 (cookie_addr_high | buff.cookie);
2225 rte_pktmbuf_free(mbuf);
2227 mrvl_port_bpool_size
2228 [bpool->pp2_id][bpool->id][core_id] -= i;
2230 rte_spinlock_unlock(&q->priv->lock);
2237 * Prepare offload information.
2241 * @param packet_type
2242 * Packet type bitfield.
2244 * Pointer to the pp2_ouq_l3_type structure.
2246 * Pointer to the pp2_outq_l4_type structure.
2247 * @param gen_l3_cksum
2248 * Will be set to 1 in case l3 checksum is computed.
2250 * Will be set to 1 in case l4 checksum is computed.
2253 * 0 on success, negative error value otherwise.
2256 mrvl_prepare_proto_info(uint64_t ol_flags, uint32_t packet_type,
2257 enum pp2_outq_l3_type *l3_type,
2258 enum pp2_outq_l4_type *l4_type,
2263 * Based on ol_flags prepare information
2264 * for pp2_ppio_outq_desc_set_proto_info() which setups descriptor
2267 if (ol_flags & PKT_TX_IPV4) {
2268 *l3_type = PP2_OUTQ_L3_TYPE_IPV4;
2269 *gen_l3_cksum = ol_flags & PKT_TX_IP_CKSUM ? 1 : 0;
2270 } else if (ol_flags & PKT_TX_IPV6) {
2271 *l3_type = PP2_OUTQ_L3_TYPE_IPV6;
2272 /* no checksum for ipv6 header */
2275 /* if something different then stop processing */
2279 ol_flags &= PKT_TX_L4_MASK;
2280 if ((packet_type & RTE_PTYPE_L4_TCP) &&
2281 ol_flags == PKT_TX_TCP_CKSUM) {
2282 *l4_type = PP2_OUTQ_L4_TYPE_TCP;
2284 } else if ((packet_type & RTE_PTYPE_L4_UDP) &&
2285 ol_flags == PKT_TX_UDP_CKSUM) {
2286 *l4_type = PP2_OUTQ_L4_TYPE_UDP;
2289 *l4_type = PP2_OUTQ_L4_TYPE_OTHER;
2290 /* no checksum for other type */
2298 * Release already sent buffers to bpool (buffer-pool).
2301 * Pointer to the port structure.
2303 * Pointer to the MUSDK hardware interface.
2305 * Pointer to the shadow queue.
2309 * Force releasing packets.
2312 mrvl_free_sent_buffers(struct pp2_ppio *ppio, struct pp2_hif *hif,
2313 unsigned int core_id, struct mrvl_shadow_txq *sq,
2316 struct buff_release_entry *entry;
2317 uint16_t nb_done = 0, num = 0, skip_bufs = 0;
2320 pp2_ppio_get_num_outq_done(ppio, hif, qid, &nb_done);
2322 sq->num_to_release += nb_done;
2324 if (likely(!force &&
2325 sq->num_to_release < MRVL_PP2_BUF_RELEASE_BURST_SIZE))
2328 nb_done = sq->num_to_release;
2329 sq->num_to_release = 0;
2331 for (i = 0; i < nb_done; i++) {
2332 entry = &sq->ent[sq->tail + num];
2333 if (unlikely(!entry->buff.addr)) {
2335 "Shadow memory @%d: cookie(%lx), pa(%lx)!",
2336 sq->tail, (u64)entry->buff.cookie,
2337 (u64)entry->buff.addr);
2342 if (unlikely(!entry->bpool)) {
2343 struct rte_mbuf *mbuf;
2345 mbuf = (struct rte_mbuf *)
2346 (cookie_addr_high | entry->buff.cookie);
2347 rte_pktmbuf_free(mbuf);
2352 mrvl_port_bpool_size
2353 [entry->bpool->pp2_id][entry->bpool->id][core_id]++;
2355 if (unlikely(sq->tail + num == MRVL_PP2_TX_SHADOWQ_SIZE))
2360 pp2_bpool_put_buffs(hif, &sq->ent[sq->tail], &num);
2362 sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK;
2369 pp2_bpool_put_buffs(hif, &sq->ent[sq->tail], &num);
2370 sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK;
2376 * DPDK callback for transmit.
2379 * Generic pointer transmit queue.
2381 * Packets to transmit.
2383 * Number of packets in array.
2386 * Number of packets successfully transmitted.
2389 mrvl_tx_pkt_burst(void *txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2391 struct mrvl_txq *q = txq;
2392 struct mrvl_shadow_txq *sq;
2393 struct pp2_hif *hif;
2394 struct pp2_ppio_desc descs[nb_pkts];
2395 unsigned int core_id = rte_lcore_id();
2396 int i, ret, bytes_sent = 0;
2397 uint16_t num, sq_free_size;
2400 hif = mrvl_get_hif(q->priv, core_id);
2401 sq = &q->shadow_txqs[core_id];
2403 if (unlikely(!q->priv->ppio || !hif))
2407 mrvl_free_sent_buffers(q->priv->ppio, hif, core_id,
2408 sq, q->queue_id, 0);
2410 sq_free_size = MRVL_PP2_TX_SHADOWQ_SIZE - sq->size - 1;
2411 if (unlikely(nb_pkts > sq_free_size)) {
2413 "No room in shadow queue for %d packets! %d packets will be sent.",
2414 nb_pkts, sq_free_size);
2415 nb_pkts = sq_free_size;
2418 for (i = 0; i < nb_pkts; i++) {
2419 struct rte_mbuf *mbuf = tx_pkts[i];
2420 int gen_l3_cksum, gen_l4_cksum;
2421 enum pp2_outq_l3_type l3_type;
2422 enum pp2_outq_l4_type l4_type;
2424 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) {
2425 struct rte_mbuf *pref_pkt_hdr;
2427 pref_pkt_hdr = tx_pkts[i + MRVL_MUSDK_PREFETCH_SHIFT];
2428 rte_mbuf_prefetch_part1(pref_pkt_hdr);
2429 rte_mbuf_prefetch_part2(pref_pkt_hdr);
2432 sq->ent[sq->head].buff.cookie = (uint64_t)mbuf;
2433 sq->ent[sq->head].buff.addr =
2434 rte_mbuf_data_iova_default(mbuf);
2435 sq->ent[sq->head].bpool =
2436 (unlikely(mbuf->port >= RTE_MAX_ETHPORTS ||
2437 mbuf->refcnt > 1)) ? NULL :
2438 mrvl_port_to_bpool_lookup[mbuf->port];
2439 sq->head = (sq->head + 1) & MRVL_PP2_TX_SHADOWQ_MASK;
2442 pp2_ppio_outq_desc_reset(&descs[i]);
2443 pp2_ppio_outq_desc_set_phys_addr(&descs[i],
2444 rte_pktmbuf_iova(mbuf));
2445 pp2_ppio_outq_desc_set_pkt_offset(&descs[i], 0);
2446 pp2_ppio_outq_desc_set_pkt_len(&descs[i],
2447 rte_pktmbuf_pkt_len(mbuf));
2449 bytes_sent += rte_pktmbuf_pkt_len(mbuf);
2451 * in case unsupported ol_flags were passed
2452 * do not update descriptor offload information
2454 ret = mrvl_prepare_proto_info(mbuf->ol_flags, mbuf->packet_type,
2455 &l3_type, &l4_type, &gen_l3_cksum,
2460 pp2_ppio_outq_desc_set_proto_info(&descs[i], l3_type, l4_type,
2462 mbuf->l2_len + mbuf->l3_len,
2463 gen_l3_cksum, gen_l4_cksum);
2467 pp2_ppio_send(q->priv->ppio, hif, q->queue_id, descs, &nb_pkts);
2468 /* number of packets that were not sent */
2469 if (unlikely(num > nb_pkts)) {
2470 for (i = nb_pkts; i < num; i++) {
2471 sq->head = (MRVL_PP2_TX_SHADOWQ_SIZE + sq->head - 1) &
2472 MRVL_PP2_TX_SHADOWQ_MASK;
2473 addr = cookie_addr_high | sq->ent[sq->head].buff.cookie;
2475 rte_pktmbuf_pkt_len((struct rte_mbuf *)addr);
2477 sq->size -= num - nb_pkts;
2480 q->bytes_sent += bytes_sent;
2486 * Initialize packet processor.
2489 * 0 on success, negative error value otherwise.
2494 struct pp2_init_params init_params;
2496 memset(&init_params, 0, sizeof(init_params));
2497 init_params.hif_reserved_map = MRVL_MUSDK_HIFS_RESERVED;
2498 init_params.bm_pool_reserved_map = MRVL_MUSDK_BPOOLS_RESERVED;
2499 init_params.rss_tbl_reserved_map = MRVL_MUSDK_RSS_RESERVED;
2501 return pp2_init(&init_params);
2505 * Deinitialize packet processor.
2508 * 0 on success, negative error value otherwise.
2511 mrvl_deinit_pp2(void)
2517 * Create private device structure.
2520 * Pointer to the port name passed in the initialization parameters.
2523 * Pointer to the newly allocated private device structure.
2525 static struct mrvl_priv *
2526 mrvl_priv_create(const char *dev_name)
2528 struct pp2_bpool_params bpool_params;
2529 char match[MRVL_MATCH_LEN];
2530 struct mrvl_priv *priv;
2533 priv = rte_zmalloc_socket(dev_name, sizeof(*priv), 0, rte_socket_id());
2537 ret = pp2_netdev_get_ppio_info((char *)(uintptr_t)dev_name,
2538 &priv->pp_id, &priv->ppio_id);
2542 bpool_bit = mrvl_reserve_bit(&used_bpools[priv->pp_id],
2543 PP2_BPOOL_NUM_POOLS);
2546 priv->bpool_bit = bpool_bit;
2548 snprintf(match, sizeof(match), "pool-%d:%d", priv->pp_id,
2550 memset(&bpool_params, 0, sizeof(bpool_params));
2551 bpool_params.match = match;
2552 bpool_params.buff_len = MRVL_PKT_SIZE_MAX + MRVL_PKT_EFFEC_OFFS;
2553 ret = pp2_bpool_init(&bpool_params, &priv->bpool);
2555 goto out_clear_bpool_bit;
2557 priv->ppio_params.type = PP2_PPIO_T_NIC;
2558 rte_spinlock_init(&priv->lock);
2561 out_clear_bpool_bit:
2562 used_bpools[priv->pp_id] &= ~(1 << priv->bpool_bit);
2569 * Create device representing Ethernet port.
2572 * Pointer to the port's name.
2575 * 0 on success, negative error value otherwise.
2578 mrvl_eth_dev_create(struct rte_vdev_device *vdev, const char *name)
2580 int ret, fd = socket(AF_INET, SOCK_DGRAM, 0);
2581 struct rte_eth_dev *eth_dev;
2582 struct mrvl_priv *priv;
2585 eth_dev = rte_eth_dev_allocate(name);
2589 priv = mrvl_priv_create(name);
2595 eth_dev->data->mac_addrs =
2596 rte_zmalloc("mac_addrs",
2597 ETHER_ADDR_LEN * MRVL_MAC_ADDRS_MAX, 0);
2598 if (!eth_dev->data->mac_addrs) {
2599 MRVL_LOG(ERR, "Failed to allocate space for eth addrs");
2604 memset(&req, 0, sizeof(req));
2605 strcpy(req.ifr_name, name);
2606 ret = ioctl(fd, SIOCGIFHWADDR, &req);
2610 memcpy(eth_dev->data->mac_addrs[0].addr_bytes,
2611 req.ifr_addr.sa_data, ETHER_ADDR_LEN);
2613 eth_dev->rx_pkt_burst = mrvl_rx_pkt_burst;
2614 eth_dev->tx_pkt_burst = mrvl_tx_pkt_burst;
2615 eth_dev->data->kdrv = RTE_KDRV_NONE;
2616 eth_dev->data->dev_private = priv;
2617 eth_dev->device = &vdev->device;
2618 eth_dev->dev_ops = &mrvl_ops;
2620 rte_eth_dev_probing_finish(eth_dev);
2623 rte_free(eth_dev->data->mac_addrs);
2625 rte_eth_dev_release_port(eth_dev);
2633 * Cleanup previously created device representing Ethernet port.
2636 * Pointer to the port name.
2639 mrvl_eth_dev_destroy(const char *name)
2641 struct rte_eth_dev *eth_dev;
2642 struct mrvl_priv *priv;
2644 eth_dev = rte_eth_dev_allocated(name);
2648 priv = eth_dev->data->dev_private;
2649 pp2_bpool_deinit(priv->bpool);
2650 used_bpools[priv->pp_id] &= ~(1 << priv->bpool_bit);
2652 rte_free(eth_dev->data->mac_addrs);
2653 rte_eth_dev_release_port(eth_dev);
2657 * Callback used by rte_kvargs_process() during argument parsing.
2660 * Pointer to the parsed key (unused).
2662 * Pointer to the parsed value.
2664 * Pointer to the extra arguments which contains address of the
2665 * table of pointers to parsed interface names.
2671 mrvl_get_ifnames(const char *key __rte_unused, const char *value,
2674 struct mrvl_ifnames *ifnames = extra_args;
2676 ifnames->names[ifnames->idx++] = value;
2682 * Deinitialize per-lcore MUSDK hardware interfaces (hifs).
2685 mrvl_deinit_hifs(void)
2689 for (i = mrvl_lcore_first; i <= mrvl_lcore_last; i++) {
2691 pp2_hif_deinit(hifs[i]);
2693 used_hifs = MRVL_MUSDK_HIFS_RESERVED;
2694 memset(hifs, 0, sizeof(hifs));
2698 * DPDK callback to register the virtual device.
2701 * Pointer to the virtual device.
2704 * 0 on success, negative error value otherwise.
2707 rte_pmd_mrvl_probe(struct rte_vdev_device *vdev)
2709 struct rte_kvargs *kvlist;
2710 struct mrvl_ifnames ifnames;
2712 uint32_t i, ifnum, cfgnum;
2715 params = rte_vdev_device_args(vdev);
2719 kvlist = rte_kvargs_parse(params, valid_args);
2723 ifnum = rte_kvargs_count(kvlist, MRVL_IFACE_NAME_ARG);
2724 if (ifnum > RTE_DIM(ifnames.names))
2725 goto out_free_kvlist;
2728 rte_kvargs_process(kvlist, MRVL_IFACE_NAME_ARG,
2729 mrvl_get_ifnames, &ifnames);
2733 * The below system initialization should be done only once,
2734 * on the first provided configuration file
2736 if (!mrvl_qos_cfg) {
2737 cfgnum = rte_kvargs_count(kvlist, MRVL_CFG_ARG);
2738 MRVL_LOG(INFO, "Parsing config file!");
2740 MRVL_LOG(ERR, "Cannot handle more than one config file!");
2741 goto out_free_kvlist;
2742 } else if (cfgnum == 1) {
2743 rte_kvargs_process(kvlist, MRVL_CFG_ARG,
2744 mrvl_get_qoscfg, &mrvl_qos_cfg);
2751 MRVL_LOG(INFO, "Perform MUSDK initializations");
2753 ret = rte_mvep_init(MVEP_MOD_T_PP2, kvlist);
2755 goto out_free_kvlist;
2757 ret = mrvl_init_pp2();
2759 MRVL_LOG(ERR, "Failed to init PP!");
2760 rte_mvep_deinit(MVEP_MOD_T_PP2);
2761 goto out_free_kvlist;
2764 memset(mrvl_port_bpool_size, 0, sizeof(mrvl_port_bpool_size));
2765 memset(mrvl_port_to_bpool_lookup, 0, sizeof(mrvl_port_to_bpool_lookup));
2767 mrvl_lcore_first = RTE_MAX_LCORE;
2768 mrvl_lcore_last = 0;
2771 for (i = 0; i < ifnum; i++) {
2772 MRVL_LOG(INFO, "Creating %s", ifnames.names[i]);
2773 ret = mrvl_eth_dev_create(vdev, ifnames.names[i]);
2777 mrvl_dev_num += ifnum;
2779 rte_kvargs_free(kvlist);
2784 mrvl_eth_dev_destroy(ifnames.names[i]);
2786 if (mrvl_dev_num == 0) {
2788 rte_mvep_deinit(MVEP_MOD_T_PP2);
2791 rte_kvargs_free(kvlist);
2797 * DPDK callback to remove virtual device.
2800 * Pointer to the removed virtual device.
2803 * 0 on success, negative error value otherwise.
2806 rte_pmd_mrvl_remove(struct rte_vdev_device *vdev)
2811 name = rte_vdev_device_name(vdev);
2815 MRVL_LOG(INFO, "Removing %s", name);
2817 RTE_ETH_FOREACH_DEV(i) { /* FIXME: removing all devices! */
2818 char ifname[RTE_ETH_NAME_MAX_LEN];
2820 rte_eth_dev_get_name_by_port(i, ifname);
2821 mrvl_eth_dev_destroy(ifname);
2825 if (mrvl_dev_num == 0) {
2826 MRVL_LOG(INFO, "Perform MUSDK deinit");
2829 rte_mvep_deinit(MVEP_MOD_T_PP2);
2835 static struct rte_vdev_driver pmd_mrvl_drv = {
2836 .probe = rte_pmd_mrvl_probe,
2837 .remove = rte_pmd_mrvl_remove,
2840 RTE_PMD_REGISTER_VDEV(net_mvpp2, pmd_mrvl_drv);
2841 RTE_PMD_REGISTER_ALIAS(net_mvpp2, eth_mvpp2);
2843 RTE_INIT(mrvl_init_log)
2845 mrvl_logtype = rte_log_register("pmd.net.mvpp2");
2846 if (mrvl_logtype >= 0)
2847 rte_log_set_level(mrvl_logtype, RTE_LOG_NOTICE);