1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2017 Marvell International Ltd.
3 * Copyright(c) 2017 Semihalf.
7 #include <rte_ethdev_driver.h>
8 #include <rte_kvargs.h>
10 #include <rte_malloc.h>
11 #include <rte_bus_vdev.h>
13 /* Unluckily, container_of is defined by both DPDK and MUSDK,
14 * we'll declare only one version.
16 * Note that it is not used in this PMD anyway.
23 #include <linux/ethtool.h>
24 #include <linux/sockios.h>
26 #include <net/if_arp.h>
27 #include <sys/ioctl.h>
28 #include <sys/socket.h>
30 #include <sys/types.h>
32 #include <rte_mvep_common.h>
33 #include "mrvl_ethdev.h"
36 /* bitmask with reserved hifs */
37 #define MRVL_MUSDK_HIFS_RESERVED 0x0F
38 /* bitmask with reserved bpools */
39 #define MRVL_MUSDK_BPOOLS_RESERVED 0x07
40 /* bitmask with reserved kernel RSS tables */
41 #define MRVL_MUSDK_RSS_RESERVED 0x01
42 /* maximum number of available hifs */
43 #define MRVL_MUSDK_HIFS_MAX 9
46 #define MRVL_MUSDK_PREFETCH_SHIFT 2
48 /* TCAM has 25 entries reserved for uc/mc filter entries */
49 #define MRVL_MAC_ADDRS_MAX 25
50 #define MRVL_MATCH_LEN 16
51 #define MRVL_PKT_EFFEC_OFFS (MRVL_PKT_OFFS + MV_MH_SIZE)
52 /* Maximum allowable packet size */
53 #define MRVL_PKT_SIZE_MAX (10240 - MV_MH_SIZE)
55 #define MRVL_IFACE_NAME_ARG "iface"
56 #define MRVL_CFG_ARG "cfg"
58 #define MRVL_BURST_SIZE 64
60 #define MRVL_ARP_LENGTH 28
62 #define MRVL_COOKIE_ADDR_INVALID ~0ULL
64 #define MRVL_COOKIE_HIGH_ADDR_SHIFT (sizeof(pp2_cookie_t) * 8)
65 #define MRVL_COOKIE_HIGH_ADDR_MASK (~0ULL << MRVL_COOKIE_HIGH_ADDR_SHIFT)
67 /** Port Rx offload capabilities */
68 #define MRVL_RX_OFFLOADS (DEV_RX_OFFLOAD_VLAN_FILTER | \
69 DEV_RX_OFFLOAD_JUMBO_FRAME | \
70 DEV_RX_OFFLOAD_CRC_STRIP | \
71 DEV_RX_OFFLOAD_CHECKSUM)
73 /** Port Tx offloads capabilities */
74 #define MRVL_TX_OFFLOADS (DEV_TX_OFFLOAD_IPV4_CKSUM | \
75 DEV_TX_OFFLOAD_UDP_CKSUM | \
76 DEV_TX_OFFLOAD_TCP_CKSUM)
78 static const char * const valid_args[] = {
84 static int used_hifs = MRVL_MUSDK_HIFS_RESERVED;
85 static struct pp2_hif *hifs[RTE_MAX_LCORE];
86 static int used_bpools[PP2_NUM_PKT_PROC] = {
87 [0 ... PP2_NUM_PKT_PROC - 1] = MRVL_MUSDK_BPOOLS_RESERVED
90 static struct pp2_bpool *mrvl_port_to_bpool_lookup[RTE_MAX_ETHPORTS];
91 static int mrvl_port_bpool_size[PP2_NUM_PKT_PROC][PP2_BPOOL_NUM_POOLS][RTE_MAX_LCORE];
92 static uint64_t cookie_addr_high = MRVL_COOKIE_ADDR_INVALID;
97 const char *names[PP2_NUM_ETH_PPIO * PP2_NUM_PKT_PROC];
102 * To use buffer harvesting based on loopback port shadow queue structure
103 * was introduced for buffers information bookkeeping.
105 * Before sending the packet, related buffer information (pp2_buff_inf) is
106 * stored in shadow queue. After packet is transmitted no longer used
107 * packet buffer is released back to it's original hardware pool,
108 * on condition it originated from interface.
109 * In case it was generated by application itself i.e: mbuf->port field is
110 * 0xff then its released to software mempool.
112 struct mrvl_shadow_txq {
113 int head; /* write index - used when sending buffers */
114 int tail; /* read index - used when releasing buffers */
115 u16 size; /* queue occupied size */
116 u16 num_to_release; /* number of buffers sent, that can be released */
117 struct buff_release_entry ent[MRVL_PP2_TX_SHADOWQ_SIZE]; /* q entries */
121 struct mrvl_priv *priv;
122 struct rte_mempool *mp;
131 struct mrvl_priv *priv;
135 struct mrvl_shadow_txq shadow_txqs[RTE_MAX_LCORE];
136 int tx_deferred_start;
139 static int mrvl_lcore_first;
140 static int mrvl_lcore_last;
141 static int mrvl_dev_num;
143 static int mrvl_fill_bpool(struct mrvl_rxq *rxq, int num);
144 static inline void mrvl_free_sent_buffers(struct pp2_ppio *ppio,
145 struct pp2_hif *hif, unsigned int core_id,
146 struct mrvl_shadow_txq *sq, int qid, int force);
148 #define MRVL_XSTATS_TBL_ENTRY(name) { \
149 #name, offsetof(struct pp2_ppio_statistics, name), \
150 sizeof(((struct pp2_ppio_statistics *)0)->name) \
153 /* Table with xstats data */
158 } mrvl_xstats_tbl[] = {
159 MRVL_XSTATS_TBL_ENTRY(rx_bytes),
160 MRVL_XSTATS_TBL_ENTRY(rx_packets),
161 MRVL_XSTATS_TBL_ENTRY(rx_unicast_packets),
162 MRVL_XSTATS_TBL_ENTRY(rx_errors),
163 MRVL_XSTATS_TBL_ENTRY(rx_fullq_dropped),
164 MRVL_XSTATS_TBL_ENTRY(rx_bm_dropped),
165 MRVL_XSTATS_TBL_ENTRY(rx_early_dropped),
166 MRVL_XSTATS_TBL_ENTRY(rx_fifo_dropped),
167 MRVL_XSTATS_TBL_ENTRY(rx_cls_dropped),
168 MRVL_XSTATS_TBL_ENTRY(tx_bytes),
169 MRVL_XSTATS_TBL_ENTRY(tx_packets),
170 MRVL_XSTATS_TBL_ENTRY(tx_unicast_packets),
171 MRVL_XSTATS_TBL_ENTRY(tx_errors)
175 mrvl_get_bpool_size(int pp2_id, int pool_id)
180 for (i = mrvl_lcore_first; i <= mrvl_lcore_last; i++)
181 size += mrvl_port_bpool_size[pp2_id][pool_id][i];
187 mrvl_reserve_bit(int *bitmap, int max)
189 int n = sizeof(*bitmap) * 8 - __builtin_clz(*bitmap);
200 mrvl_init_hif(int core_id)
202 struct pp2_hif_params params;
203 char match[MRVL_MATCH_LEN];
206 ret = mrvl_reserve_bit(&used_hifs, MRVL_MUSDK_HIFS_MAX);
208 MRVL_LOG(ERR, "Failed to allocate hif %d", core_id);
212 snprintf(match, sizeof(match), "hif-%d", ret);
213 memset(¶ms, 0, sizeof(params));
214 params.match = match;
215 params.out_size = MRVL_PP2_AGGR_TXQD_MAX;
216 ret = pp2_hif_init(¶ms, &hifs[core_id]);
218 MRVL_LOG(ERR, "Failed to initialize hif %d", core_id);
225 static inline struct pp2_hif*
226 mrvl_get_hif(struct mrvl_priv *priv, int core_id)
230 if (likely(hifs[core_id] != NULL))
231 return hifs[core_id];
233 rte_spinlock_lock(&priv->lock);
235 ret = mrvl_init_hif(core_id);
237 MRVL_LOG(ERR, "Failed to allocate hif %d", core_id);
241 if (core_id < mrvl_lcore_first)
242 mrvl_lcore_first = core_id;
244 if (core_id > mrvl_lcore_last)
245 mrvl_lcore_last = core_id;
247 rte_spinlock_unlock(&priv->lock);
249 return hifs[core_id];
253 * Configure rss based on dpdk rss configuration.
256 * Pointer to private structure.
258 * Pointer to RSS configuration.
261 * 0 on success, negative error value otherwise.
264 mrvl_configure_rss(struct mrvl_priv *priv, struct rte_eth_rss_conf *rss_conf)
266 if (rss_conf->rss_key)
267 MRVL_LOG(WARNING, "Changing hash key is not supported");
269 if (rss_conf->rss_hf == 0) {
270 priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE;
271 } else if (rss_conf->rss_hf & ETH_RSS_IPV4) {
272 priv->ppio_params.inqs_params.hash_type =
273 PP2_PPIO_HASH_T_2_TUPLE;
274 } else if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) {
275 priv->ppio_params.inqs_params.hash_type =
276 PP2_PPIO_HASH_T_5_TUPLE;
277 priv->rss_hf_tcp = 1;
278 } else if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) {
279 priv->ppio_params.inqs_params.hash_type =
280 PP2_PPIO_HASH_T_5_TUPLE;
281 priv->rss_hf_tcp = 0;
290 * Ethernet device configuration.
292 * Prepare the driver for a given number of TX and RX queues and
296 * Pointer to Ethernet device structure.
299 * 0 on success, negative error value otherwise.
302 mrvl_dev_configure(struct rte_eth_dev *dev)
304 struct mrvl_priv *priv = dev->data->dev_private;
307 if (dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_NONE &&
308 dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) {
309 MRVL_LOG(INFO, "Unsupported rx multi queue mode %d",
310 dev->data->dev_conf.rxmode.mq_mode);
314 /* KEEP_CRC offload flag is not supported by PMD
315 * can remove the below block when DEV_RX_OFFLOAD_CRC_STRIP removed
317 if (rte_eth_dev_must_keep_crc(dev->data->dev_conf.rxmode.offloads)) {
318 MRVL_LOG(INFO, "L2 CRC stripping is always enabled in hw");
319 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_CRC_STRIP;
322 if (dev->data->dev_conf.rxmode.split_hdr_size) {
323 MRVL_LOG(INFO, "Split headers not supported");
327 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
328 dev->data->mtu = dev->data->dev_conf.rxmode.max_rx_pkt_len -
329 ETHER_HDR_LEN - ETHER_CRC_LEN;
331 ret = mrvl_configure_rxqs(priv, dev->data->port_id,
332 dev->data->nb_rx_queues);
336 ret = mrvl_configure_txqs(priv, dev->data->port_id,
337 dev->data->nb_tx_queues);
341 priv->ppio_params.outqs_params.num_outqs = dev->data->nb_tx_queues;
342 priv->ppio_params.maintain_stats = 1;
343 priv->nb_rx_queues = dev->data->nb_rx_queues;
345 if (dev->data->nb_rx_queues == 1 &&
346 dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) {
347 MRVL_LOG(WARNING, "Disabling hash for 1 rx queue");
348 priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE;
353 return mrvl_configure_rss(priv,
354 &dev->data->dev_conf.rx_adv_conf.rss_conf);
358 * DPDK callback to change the MTU.
360 * Setting the MTU affects hardware MRU (packets larger than the MRU
364 * Pointer to Ethernet device structure.
369 * 0 on success, negative error value otherwise.
372 mrvl_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
374 struct mrvl_priv *priv = dev->data->dev_private;
375 /* extra MV_MH_SIZE bytes are required for Marvell tag */
376 uint16_t mru = mtu + MV_MH_SIZE + ETHER_HDR_LEN + ETHER_CRC_LEN;
379 if (mtu < ETHER_MIN_MTU || mru > MRVL_PKT_SIZE_MAX)
385 ret = pp2_ppio_set_mru(priv->ppio, mru);
389 return pp2_ppio_set_mtu(priv->ppio, mtu);
393 * DPDK callback to bring the link up.
396 * Pointer to Ethernet device structure.
399 * 0 on success, negative error value otherwise.
402 mrvl_dev_set_link_up(struct rte_eth_dev *dev)
404 struct mrvl_priv *priv = dev->data->dev_private;
410 ret = pp2_ppio_enable(priv->ppio);
415 * mtu/mru can be updated if pp2_ppio_enable() was called at least once
416 * as pp2_ppio_enable() changes port->t_mode from default 0 to
417 * PP2_TRAFFIC_INGRESS_EGRESS.
419 * Set mtu to default DPDK value here.
421 ret = mrvl_mtu_set(dev, dev->data->mtu);
423 pp2_ppio_disable(priv->ppio);
429 * DPDK callback to bring the link down.
432 * Pointer to Ethernet device structure.
435 * 0 on success, negative error value otherwise.
438 mrvl_dev_set_link_down(struct rte_eth_dev *dev)
440 struct mrvl_priv *priv = dev->data->dev_private;
445 return pp2_ppio_disable(priv->ppio);
449 * DPDK callback to start tx queue.
452 * Pointer to Ethernet device structure.
454 * Transmit queue index.
457 * 0 on success, negative error value otherwise.
460 mrvl_tx_queue_start(struct rte_eth_dev *dev, uint16_t queue_id)
462 struct mrvl_priv *priv = dev->data->dev_private;
468 /* passing 1 enables given tx queue */
469 ret = pp2_ppio_set_outq_state(priv->ppio, queue_id, 1);
471 MRVL_LOG(ERR, "Failed to start txq %d", queue_id);
475 dev->data->tx_queue_state[queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
481 * DPDK callback to stop tx queue.
484 * Pointer to Ethernet device structure.
486 * Transmit queue index.
489 * 0 on success, negative error value otherwise.
492 mrvl_tx_queue_stop(struct rte_eth_dev *dev, uint16_t queue_id)
494 struct mrvl_priv *priv = dev->data->dev_private;
500 /* passing 0 disables given tx queue */
501 ret = pp2_ppio_set_outq_state(priv->ppio, queue_id, 0);
503 MRVL_LOG(ERR, "Failed to stop txq %d", queue_id);
507 dev->data->tx_queue_state[queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
513 * DPDK callback to start the device.
516 * Pointer to Ethernet device structure.
519 * 0 on success, negative errno value on failure.
522 mrvl_dev_start(struct rte_eth_dev *dev)
524 struct mrvl_priv *priv = dev->data->dev_private;
525 char match[MRVL_MATCH_LEN];
526 int ret = 0, i, def_init_size;
528 snprintf(match, sizeof(match), "ppio-%d:%d",
529 priv->pp_id, priv->ppio_id);
530 priv->ppio_params.match = match;
533 * Calculate the minimum bpool size for refill feature as follows:
534 * 2 default burst sizes multiply by number of rx queues.
535 * If the bpool size will be below this value, new buffers will
536 * be added to the pool.
538 priv->bpool_min_size = priv->nb_rx_queues * MRVL_BURST_SIZE * 2;
540 /* In case initial bpool size configured in queues setup is
541 * smaller than minimum size add more buffers
543 def_init_size = priv->bpool_min_size + MRVL_BURST_SIZE * 2;
544 if (priv->bpool_init_size < def_init_size) {
545 int buffs_to_add = def_init_size - priv->bpool_init_size;
547 priv->bpool_init_size += buffs_to_add;
548 ret = mrvl_fill_bpool(dev->data->rx_queues[0], buffs_to_add);
550 MRVL_LOG(ERR, "Failed to add buffers to bpool");
554 * Calculate the maximum bpool size for refill feature as follows:
555 * maximum number of descriptors in rx queue multiply by number
556 * of rx queues plus minimum bpool size.
557 * In case the bpool size will exceed this value, superfluous buffers
560 priv->bpool_max_size = (priv->nb_rx_queues * MRVL_PP2_RXD_MAX) +
561 priv->bpool_min_size;
563 ret = pp2_ppio_init(&priv->ppio_params, &priv->ppio);
565 MRVL_LOG(ERR, "Failed to init ppio");
570 * In case there are some some stale uc/mc mac addresses flush them
571 * here. It cannot be done during mrvl_dev_close() as port information
572 * is already gone at that point (due to pp2_ppio_deinit() in
575 if (!priv->uc_mc_flushed) {
576 ret = pp2_ppio_flush_mac_addrs(priv->ppio, 1, 1);
579 "Failed to flush uc/mc filter list");
582 priv->uc_mc_flushed = 1;
585 if (!priv->vlan_flushed) {
586 ret = pp2_ppio_flush_vlan(priv->ppio);
588 MRVL_LOG(ERR, "Failed to flush vlan list");
591 * once pp2_ppio_flush_vlan() is supported jump to out
595 priv->vlan_flushed = 1;
598 /* For default QoS config, don't start classifier. */
600 ret = mrvl_start_qos_mapping(priv);
602 MRVL_LOG(ERR, "Failed to setup QoS mapping");
607 ret = mrvl_dev_set_link_up(dev);
609 MRVL_LOG(ERR, "Failed to set link up");
613 /* start tx queues */
614 for (i = 0; i < dev->data->nb_tx_queues; i++) {
615 struct mrvl_txq *txq = dev->data->tx_queues[i];
617 dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STARTED;
619 if (!txq->tx_deferred_start)
623 * All txqs are started by default. Stop them
624 * so that tx_deferred_start works as expected.
626 ret = mrvl_tx_queue_stop(dev, i);
633 MRVL_LOG(ERR, "Failed to start device");
634 pp2_ppio_deinit(priv->ppio);
639 * Flush receive queues.
642 * Pointer to Ethernet device structure.
645 mrvl_flush_rx_queues(struct rte_eth_dev *dev)
649 MRVL_LOG(INFO, "Flushing rx queues");
650 for (i = 0; i < dev->data->nb_rx_queues; i++) {
654 struct mrvl_rxq *q = dev->data->rx_queues[i];
655 struct pp2_ppio_desc descs[MRVL_PP2_RXD_MAX];
657 num = MRVL_PP2_RXD_MAX;
658 ret = pp2_ppio_recv(q->priv->ppio,
659 q->priv->rxq_map[q->queue_id].tc,
660 q->priv->rxq_map[q->queue_id].inq,
661 descs, (uint16_t *)&num);
662 } while (ret == 0 && num);
667 * Flush transmit shadow queues.
670 * Pointer to Ethernet device structure.
673 mrvl_flush_tx_shadow_queues(struct rte_eth_dev *dev)
676 struct mrvl_txq *txq;
678 MRVL_LOG(INFO, "Flushing tx shadow queues");
679 for (i = 0; i < dev->data->nb_tx_queues; i++) {
680 txq = (struct mrvl_txq *)dev->data->tx_queues[i];
682 for (j = 0; j < RTE_MAX_LCORE; j++) {
683 struct mrvl_shadow_txq *sq;
688 sq = &txq->shadow_txqs[j];
689 mrvl_free_sent_buffers(txq->priv->ppio,
690 hifs[j], j, sq, txq->queue_id, 1);
691 while (sq->tail != sq->head) {
692 uint64_t addr = cookie_addr_high |
693 sq->ent[sq->tail].buff.cookie;
695 (struct rte_mbuf *)addr);
696 sq->tail = (sq->tail + 1) &
697 MRVL_PP2_TX_SHADOWQ_MASK;
699 memset(sq, 0, sizeof(*sq));
705 * Flush hardware bpool (buffer-pool).
708 * Pointer to Ethernet device structure.
711 mrvl_flush_bpool(struct rte_eth_dev *dev)
713 struct mrvl_priv *priv = dev->data->dev_private;
717 unsigned int core_id = rte_lcore_id();
719 if (core_id == LCORE_ID_ANY)
722 hif = mrvl_get_hif(priv, core_id);
724 ret = pp2_bpool_get_num_buffs(priv->bpool, &num);
726 MRVL_LOG(ERR, "Failed to get bpool buffers number");
731 struct pp2_buff_inf inf;
734 ret = pp2_bpool_get_buff(hif, priv->bpool, &inf);
738 addr = cookie_addr_high | inf.cookie;
739 rte_pktmbuf_free((struct rte_mbuf *)addr);
744 * DPDK callback to stop the device.
747 * Pointer to Ethernet device structure.
750 mrvl_dev_stop(struct rte_eth_dev *dev)
752 struct mrvl_priv *priv = dev->data->dev_private;
754 mrvl_dev_set_link_down(dev);
755 mrvl_flush_rx_queues(dev);
756 mrvl_flush_tx_shadow_queues(dev);
758 pp2_cls_tbl_deinit(priv->cls_tbl);
759 priv->cls_tbl = NULL;
762 pp2_cls_qos_tbl_deinit(priv->qos_tbl);
763 priv->qos_tbl = NULL;
766 pp2_ppio_deinit(priv->ppio);
769 /* policer must be released after ppio deinitialization */
771 pp2_cls_plcr_deinit(priv->policer);
772 priv->policer = NULL;
777 * DPDK callback to close the device.
780 * Pointer to Ethernet device structure.
783 mrvl_dev_close(struct rte_eth_dev *dev)
785 struct mrvl_priv *priv = dev->data->dev_private;
788 for (i = 0; i < priv->ppio_params.inqs_params.num_tcs; ++i) {
789 struct pp2_ppio_tc_params *tc_params =
790 &priv->ppio_params.inqs_params.tcs_params[i];
792 if (tc_params->inqs_params) {
793 rte_free(tc_params->inqs_params);
794 tc_params->inqs_params = NULL;
798 mrvl_flush_bpool(dev);
802 * DPDK callback to retrieve physical link information.
805 * Pointer to Ethernet device structure.
806 * @param wait_to_complete
807 * Wait for request completion (ignored).
810 * 0 on success, negative error value otherwise.
813 mrvl_link_update(struct rte_eth_dev *dev, int wait_to_complete __rte_unused)
817 * once MUSDK provides necessary API use it here
819 struct mrvl_priv *priv = dev->data->dev_private;
820 struct ethtool_cmd edata;
822 int ret, fd, link_up;
827 edata.cmd = ETHTOOL_GSET;
829 strcpy(req.ifr_name, dev->data->name);
830 req.ifr_data = (void *)&edata;
832 fd = socket(AF_INET, SOCK_DGRAM, 0);
836 ret = ioctl(fd, SIOCETHTOOL, &req);
844 switch (ethtool_cmd_speed(&edata)) {
846 dev->data->dev_link.link_speed = ETH_SPEED_NUM_10M;
849 dev->data->dev_link.link_speed = ETH_SPEED_NUM_100M;
852 dev->data->dev_link.link_speed = ETH_SPEED_NUM_1G;
855 dev->data->dev_link.link_speed = ETH_SPEED_NUM_10G;
858 dev->data->dev_link.link_speed = ETH_SPEED_NUM_NONE;
861 dev->data->dev_link.link_duplex = edata.duplex ? ETH_LINK_FULL_DUPLEX :
862 ETH_LINK_HALF_DUPLEX;
863 dev->data->dev_link.link_autoneg = edata.autoneg ? ETH_LINK_AUTONEG :
865 pp2_ppio_get_link_state(priv->ppio, &link_up);
866 dev->data->dev_link.link_status = link_up ? ETH_LINK_UP : ETH_LINK_DOWN;
872 * DPDK callback to enable promiscuous mode.
875 * Pointer to Ethernet device structure.
878 mrvl_promiscuous_enable(struct rte_eth_dev *dev)
880 struct mrvl_priv *priv = dev->data->dev_private;
889 ret = pp2_ppio_set_promisc(priv->ppio, 1);
891 MRVL_LOG(ERR, "Failed to enable promiscuous mode");
895 * DPDK callback to enable allmulti mode.
898 * Pointer to Ethernet device structure.
901 mrvl_allmulticast_enable(struct rte_eth_dev *dev)
903 struct mrvl_priv *priv = dev->data->dev_private;
912 ret = pp2_ppio_set_mc_promisc(priv->ppio, 1);
914 MRVL_LOG(ERR, "Failed enable all-multicast mode");
918 * DPDK callback to disable promiscuous mode.
921 * Pointer to Ethernet device structure.
924 mrvl_promiscuous_disable(struct rte_eth_dev *dev)
926 struct mrvl_priv *priv = dev->data->dev_private;
932 ret = pp2_ppio_set_promisc(priv->ppio, 0);
934 MRVL_LOG(ERR, "Failed to disable promiscuous mode");
938 * DPDK callback to disable allmulticast mode.
941 * Pointer to Ethernet device structure.
944 mrvl_allmulticast_disable(struct rte_eth_dev *dev)
946 struct mrvl_priv *priv = dev->data->dev_private;
952 ret = pp2_ppio_set_mc_promisc(priv->ppio, 0);
954 MRVL_LOG(ERR, "Failed to disable all-multicast mode");
958 * DPDK callback to remove a MAC address.
961 * Pointer to Ethernet device structure.
966 mrvl_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index)
968 struct mrvl_priv *priv = dev->data->dev_private;
969 char buf[ETHER_ADDR_FMT_SIZE];
978 ret = pp2_ppio_remove_mac_addr(priv->ppio,
979 dev->data->mac_addrs[index].addr_bytes);
981 ether_format_addr(buf, sizeof(buf),
982 &dev->data->mac_addrs[index]);
983 MRVL_LOG(ERR, "Failed to remove mac %s", buf);
988 * DPDK callback to add a MAC address.
991 * Pointer to Ethernet device structure.
993 * MAC address to register.
997 * VMDq pool index to associate address with (unused).
1000 * 0 on success, negative error value otherwise.
1003 mrvl_mac_addr_add(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1004 uint32_t index, uint32_t vmdq __rte_unused)
1006 struct mrvl_priv *priv = dev->data->dev_private;
1007 char buf[ETHER_ADDR_FMT_SIZE];
1014 /* For setting index 0, mrvl_mac_addr_set() should be used.*/
1021 * Maximum number of uc addresses can be tuned via kernel module mvpp2x
1022 * parameter uc_filter_max. Maximum number of mc addresses is then
1023 * MRVL_MAC_ADDRS_MAX - uc_filter_max. Currently it defaults to 4 and
1026 * If more than uc_filter_max uc addresses were added to filter list
1027 * then NIC will switch to promiscuous mode automatically.
1029 * If more than MRVL_MAC_ADDRS_MAX - uc_filter_max number mc addresses
1030 * were added to filter list then NIC will switch to all-multicast mode
1033 ret = pp2_ppio_add_mac_addr(priv->ppio, mac_addr->addr_bytes);
1035 ether_format_addr(buf, sizeof(buf), mac_addr);
1036 MRVL_LOG(ERR, "Failed to add mac %s", buf);
1044 * DPDK callback to set the primary MAC address.
1047 * Pointer to Ethernet device structure.
1049 * MAC address to register.
1052 * 0 on success, negative error value otherwise.
1055 mrvl_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr)
1057 struct mrvl_priv *priv = dev->data->dev_private;
1066 ret = pp2_ppio_set_mac_addr(priv->ppio, mac_addr->addr_bytes);
1068 char buf[ETHER_ADDR_FMT_SIZE];
1069 ether_format_addr(buf, sizeof(buf), mac_addr);
1070 MRVL_LOG(ERR, "Failed to set mac to %s", buf);
1077 * DPDK callback to get device statistics.
1080 * Pointer to Ethernet device structure.
1082 * Stats structure output buffer.
1085 * 0 on success, negative error value otherwise.
1088 mrvl_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1090 struct mrvl_priv *priv = dev->data->dev_private;
1091 struct pp2_ppio_statistics ppio_stats;
1092 uint64_t drop_mac = 0;
1093 unsigned int i, idx, ret;
1098 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1099 struct mrvl_rxq *rxq = dev->data->rx_queues[i];
1100 struct pp2_ppio_inq_statistics rx_stats;
1105 idx = rxq->queue_id;
1106 if (unlikely(idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)) {
1108 "rx queue %d stats out of range (0 - %d)",
1109 idx, RTE_ETHDEV_QUEUE_STAT_CNTRS - 1);
1113 ret = pp2_ppio_inq_get_statistics(priv->ppio,
1114 priv->rxq_map[idx].tc,
1115 priv->rxq_map[idx].inq,
1117 if (unlikely(ret)) {
1119 "Failed to update rx queue %d stats", idx);
1123 stats->q_ibytes[idx] = rxq->bytes_recv;
1124 stats->q_ipackets[idx] = rx_stats.enq_desc - rxq->drop_mac;
1125 stats->q_errors[idx] = rx_stats.drop_early +
1126 rx_stats.drop_fullq +
1129 stats->ibytes += rxq->bytes_recv;
1130 drop_mac += rxq->drop_mac;
1133 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1134 struct mrvl_txq *txq = dev->data->tx_queues[i];
1135 struct pp2_ppio_outq_statistics tx_stats;
1140 idx = txq->queue_id;
1141 if (unlikely(idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)) {
1143 "tx queue %d stats out of range (0 - %d)",
1144 idx, RTE_ETHDEV_QUEUE_STAT_CNTRS - 1);
1147 ret = pp2_ppio_outq_get_statistics(priv->ppio, idx,
1149 if (unlikely(ret)) {
1151 "Failed to update tx queue %d stats", idx);
1155 stats->q_opackets[idx] = tx_stats.deq_desc;
1156 stats->q_obytes[idx] = txq->bytes_sent;
1157 stats->obytes += txq->bytes_sent;
1160 ret = pp2_ppio_get_statistics(priv->ppio, &ppio_stats, 0);
1161 if (unlikely(ret)) {
1162 MRVL_LOG(ERR, "Failed to update port statistics");
1166 stats->ipackets += ppio_stats.rx_packets - drop_mac;
1167 stats->opackets += ppio_stats.tx_packets;
1168 stats->imissed += ppio_stats.rx_fullq_dropped +
1169 ppio_stats.rx_bm_dropped +
1170 ppio_stats.rx_early_dropped +
1171 ppio_stats.rx_fifo_dropped +
1172 ppio_stats.rx_cls_dropped;
1173 stats->ierrors = drop_mac;
1179 * DPDK callback to clear device statistics.
1182 * Pointer to Ethernet device structure.
1185 mrvl_stats_reset(struct rte_eth_dev *dev)
1187 struct mrvl_priv *priv = dev->data->dev_private;
1193 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1194 struct mrvl_rxq *rxq = dev->data->rx_queues[i];
1196 pp2_ppio_inq_get_statistics(priv->ppio, priv->rxq_map[i].tc,
1197 priv->rxq_map[i].inq, NULL, 1);
1198 rxq->bytes_recv = 0;
1202 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1203 struct mrvl_txq *txq = dev->data->tx_queues[i];
1205 pp2_ppio_outq_get_statistics(priv->ppio, i, NULL, 1);
1206 txq->bytes_sent = 0;
1209 pp2_ppio_get_statistics(priv->ppio, NULL, 1);
1213 * DPDK callback to get extended statistics.
1216 * Pointer to Ethernet device structure.
1218 * Pointer to xstats table.
1220 * Number of entries in xstats table.
1222 * Negative value on error, number of read xstats otherwise.
1225 mrvl_xstats_get(struct rte_eth_dev *dev,
1226 struct rte_eth_xstat *stats, unsigned int n)
1228 struct mrvl_priv *priv = dev->data->dev_private;
1229 struct pp2_ppio_statistics ppio_stats;
1235 pp2_ppio_get_statistics(priv->ppio, &ppio_stats, 0);
1236 for (i = 0; i < n && i < RTE_DIM(mrvl_xstats_tbl); i++) {
1239 if (mrvl_xstats_tbl[i].size == sizeof(uint32_t))
1240 val = *(uint32_t *)((uint8_t *)&ppio_stats +
1241 mrvl_xstats_tbl[i].offset);
1242 else if (mrvl_xstats_tbl[i].size == sizeof(uint64_t))
1243 val = *(uint64_t *)((uint8_t *)&ppio_stats +
1244 mrvl_xstats_tbl[i].offset);
1249 stats[i].value = val;
1256 * DPDK callback to reset extended statistics.
1259 * Pointer to Ethernet device structure.
1262 mrvl_xstats_reset(struct rte_eth_dev *dev)
1264 mrvl_stats_reset(dev);
1268 * DPDK callback to get extended statistics names.
1270 * @param dev (unused)
1271 * Pointer to Ethernet device structure.
1272 * @param xstats_names
1273 * Pointer to xstats names table.
1275 * Size of the xstats names table.
1277 * Number of read names.
1280 mrvl_xstats_get_names(struct rte_eth_dev *dev __rte_unused,
1281 struct rte_eth_xstat_name *xstats_names,
1287 return RTE_DIM(mrvl_xstats_tbl);
1289 for (i = 0; i < size && i < RTE_DIM(mrvl_xstats_tbl); i++)
1290 snprintf(xstats_names[i].name, RTE_ETH_XSTATS_NAME_SIZE, "%s",
1291 mrvl_xstats_tbl[i].name);
1297 * DPDK callback to get information about the device.
1300 * Pointer to Ethernet device structure (unused).
1302 * Info structure output buffer.
1305 mrvl_dev_infos_get(struct rte_eth_dev *dev __rte_unused,
1306 struct rte_eth_dev_info *info)
1308 info->speed_capa = ETH_LINK_SPEED_10M |
1309 ETH_LINK_SPEED_100M |
1313 info->max_rx_queues = MRVL_PP2_RXQ_MAX;
1314 info->max_tx_queues = MRVL_PP2_TXQ_MAX;
1315 info->max_mac_addrs = MRVL_MAC_ADDRS_MAX;
1317 info->rx_desc_lim.nb_max = MRVL_PP2_RXD_MAX;
1318 info->rx_desc_lim.nb_min = MRVL_PP2_RXD_MIN;
1319 info->rx_desc_lim.nb_align = MRVL_PP2_RXD_ALIGN;
1321 info->tx_desc_lim.nb_max = MRVL_PP2_TXD_MAX;
1322 info->tx_desc_lim.nb_min = MRVL_PP2_TXD_MIN;
1323 info->tx_desc_lim.nb_align = MRVL_PP2_TXD_ALIGN;
1325 info->rx_offload_capa = MRVL_RX_OFFLOADS;
1326 info->rx_queue_offload_capa = MRVL_RX_OFFLOADS;
1328 info->tx_offload_capa = MRVL_TX_OFFLOADS;
1329 info->tx_queue_offload_capa = MRVL_TX_OFFLOADS;
1331 info->flow_type_rss_offloads = ETH_RSS_IPV4 |
1332 ETH_RSS_NONFRAG_IPV4_TCP |
1333 ETH_RSS_NONFRAG_IPV4_UDP;
1335 /* By default packets are dropped if no descriptors are available */
1336 info->default_rxconf.rx_drop_en = 1;
1337 info->default_rxconf.offloads = DEV_RX_OFFLOAD_CRC_STRIP;
1339 info->max_rx_pktlen = MRVL_PKT_SIZE_MAX;
1343 * Return supported packet types.
1346 * Pointer to Ethernet device structure (unused).
1349 * Const pointer to the table with supported packet types.
1351 static const uint32_t *
1352 mrvl_dev_supported_ptypes_get(struct rte_eth_dev *dev __rte_unused)
1354 static const uint32_t ptypes[] = {
1357 RTE_PTYPE_L3_IPV4_EXT,
1358 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1360 RTE_PTYPE_L3_IPV6_EXT,
1361 RTE_PTYPE_L2_ETHER_ARP,
1370 * DPDK callback to get information about specific receive queue.
1373 * Pointer to Ethernet device structure.
1374 * @param rx_queue_id
1375 * Receive queue index.
1377 * Receive queue information structure.
1379 static void mrvl_rxq_info_get(struct rte_eth_dev *dev, uint16_t rx_queue_id,
1380 struct rte_eth_rxq_info *qinfo)
1382 struct mrvl_rxq *q = dev->data->rx_queues[rx_queue_id];
1383 struct mrvl_priv *priv = dev->data->dev_private;
1384 int inq = priv->rxq_map[rx_queue_id].inq;
1385 int tc = priv->rxq_map[rx_queue_id].tc;
1386 struct pp2_ppio_tc_params *tc_params =
1387 &priv->ppio_params.inqs_params.tcs_params[tc];
1390 qinfo->nb_desc = tc_params->inqs_params[inq].size;
1394 * DPDK callback to get information about specific transmit queue.
1397 * Pointer to Ethernet device structure.
1398 * @param tx_queue_id
1399 * Transmit queue index.
1401 * Transmit queue information structure.
1403 static void mrvl_txq_info_get(struct rte_eth_dev *dev, uint16_t tx_queue_id,
1404 struct rte_eth_txq_info *qinfo)
1406 struct mrvl_priv *priv = dev->data->dev_private;
1407 struct mrvl_txq *txq = dev->data->tx_queues[tx_queue_id];
1410 priv->ppio_params.outqs_params.outqs_params[tx_queue_id].size;
1411 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1415 * DPDK callback to Configure a VLAN filter.
1418 * Pointer to Ethernet device structure.
1420 * VLAN ID to filter.
1425 * 0 on success, negative error value otherwise.
1428 mrvl_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1430 struct mrvl_priv *priv = dev->data->dev_private;
1438 return on ? pp2_ppio_add_vlan(priv->ppio, vlan_id) :
1439 pp2_ppio_remove_vlan(priv->ppio, vlan_id);
1443 * Release buffers to hardware bpool (buffer-pool)
1446 * Receive queue pointer.
1448 * Number of buffers to release to bpool.
1451 * 0 on success, negative error value otherwise.
1454 mrvl_fill_bpool(struct mrvl_rxq *rxq, int num)
1456 struct buff_release_entry entries[MRVL_PP2_RXD_MAX];
1457 struct rte_mbuf *mbufs[MRVL_PP2_RXD_MAX];
1459 unsigned int core_id;
1460 struct pp2_hif *hif;
1461 struct pp2_bpool *bpool;
1463 core_id = rte_lcore_id();
1464 if (core_id == LCORE_ID_ANY)
1467 hif = mrvl_get_hif(rxq->priv, core_id);
1471 bpool = rxq->priv->bpool;
1473 ret = rte_pktmbuf_alloc_bulk(rxq->mp, mbufs, num);
1477 if (cookie_addr_high == MRVL_COOKIE_ADDR_INVALID)
1479 (uint64_t)mbufs[0] & MRVL_COOKIE_HIGH_ADDR_MASK;
1481 for (i = 0; i < num; i++) {
1482 if (((uint64_t)mbufs[i] & MRVL_COOKIE_HIGH_ADDR_MASK)
1483 != cookie_addr_high) {
1485 "mbuf virtual addr high 0x%lx out of range",
1486 (uint64_t)mbufs[i] >> 32);
1490 entries[i].buff.addr =
1491 rte_mbuf_data_iova_default(mbufs[i]);
1492 entries[i].buff.cookie = (pp2_cookie_t)(uint64_t)mbufs[i];
1493 entries[i].bpool = bpool;
1496 pp2_bpool_put_buffs(hif, entries, (uint16_t *)&i);
1497 mrvl_port_bpool_size[bpool->pp2_id][bpool->id][core_id] += i;
1504 for (; i < num; i++)
1505 rte_pktmbuf_free(mbufs[i]);
1511 * DPDK callback to configure the receive queue.
1514 * Pointer to Ethernet device structure.
1518 * Number of descriptors to configure in queue.
1520 * NUMA socket on which memory must be allocated.
1522 * Thresholds parameters.
1524 * Memory pool for buffer allocations.
1527 * 0 on success, negative error value otherwise.
1530 mrvl_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1531 unsigned int socket,
1532 const struct rte_eth_rxconf *conf,
1533 struct rte_mempool *mp)
1535 struct mrvl_priv *priv = dev->data->dev_private;
1536 struct mrvl_rxq *rxq;
1538 max_rx_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
1542 offloads = conf->offloads | dev->data->dev_conf.rxmode.offloads;
1544 if (priv->rxq_map[idx].tc == MRVL_UNKNOWN_TC) {
1546 * Unknown TC mapping, mapping will not have a correct queue.
1548 MRVL_LOG(ERR, "Unknown TC mapping for queue %hu eth%hhu",
1549 idx, priv->ppio_id);
1553 min_size = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM -
1554 MRVL_PKT_EFFEC_OFFS;
1555 if (min_size < max_rx_pkt_len) {
1557 "Mbuf size must be increased to %u bytes to hold up to %u bytes of data.",
1558 max_rx_pkt_len + RTE_PKTMBUF_HEADROOM +
1559 MRVL_PKT_EFFEC_OFFS,
1564 if (dev->data->rx_queues[idx]) {
1565 rte_free(dev->data->rx_queues[idx]);
1566 dev->data->rx_queues[idx] = NULL;
1569 rxq = rte_zmalloc_socket("rxq", sizeof(*rxq), 0, socket);
1575 rxq->cksum_enabled = offloads & DEV_RX_OFFLOAD_IPV4_CKSUM;
1576 rxq->queue_id = idx;
1577 rxq->port_id = dev->data->port_id;
1578 mrvl_port_to_bpool_lookup[rxq->port_id] = priv->bpool;
1580 tc = priv->rxq_map[rxq->queue_id].tc,
1581 inq = priv->rxq_map[rxq->queue_id].inq;
1582 priv->ppio_params.inqs_params.tcs_params[tc].inqs_params[inq].size =
1585 ret = mrvl_fill_bpool(rxq, desc);
1591 priv->bpool_init_size += desc;
1593 dev->data->rx_queues[idx] = rxq;
1599 * DPDK callback to release the receive queue.
1602 * Generic receive queue pointer.
1605 mrvl_rx_queue_release(void *rxq)
1607 struct mrvl_rxq *q = rxq;
1608 struct pp2_ppio_tc_params *tc_params;
1609 int i, num, tc, inq;
1610 struct pp2_hif *hif;
1611 unsigned int core_id = rte_lcore_id();
1613 if (core_id == LCORE_ID_ANY)
1619 hif = mrvl_get_hif(q->priv, core_id);
1624 tc = q->priv->rxq_map[q->queue_id].tc;
1625 inq = q->priv->rxq_map[q->queue_id].inq;
1626 tc_params = &q->priv->ppio_params.inqs_params.tcs_params[tc];
1627 num = tc_params->inqs_params[inq].size;
1628 for (i = 0; i < num; i++) {
1629 struct pp2_buff_inf inf;
1632 pp2_bpool_get_buff(hif, q->priv->bpool, &inf);
1633 addr = cookie_addr_high | inf.cookie;
1634 rte_pktmbuf_free((struct rte_mbuf *)addr);
1641 * DPDK callback to configure the transmit queue.
1644 * Pointer to Ethernet device structure.
1646 * Transmit queue index.
1648 * Number of descriptors to configure in the queue.
1650 * NUMA socket on which memory must be allocated.
1652 * Tx queue configuration parameters.
1655 * 0 on success, negative error value otherwise.
1658 mrvl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1659 unsigned int socket,
1660 const struct rte_eth_txconf *conf)
1662 struct mrvl_priv *priv = dev->data->dev_private;
1663 struct mrvl_txq *txq;
1665 if (dev->data->tx_queues[idx]) {
1666 rte_free(dev->data->tx_queues[idx]);
1667 dev->data->tx_queues[idx] = NULL;
1670 txq = rte_zmalloc_socket("txq", sizeof(*txq), 0, socket);
1675 txq->queue_id = idx;
1676 txq->port_id = dev->data->port_id;
1677 txq->tx_deferred_start = conf->tx_deferred_start;
1678 dev->data->tx_queues[idx] = txq;
1680 priv->ppio_params.outqs_params.outqs_params[idx].size = desc;
1686 * DPDK callback to release the transmit queue.
1689 * Generic transmit queue pointer.
1692 mrvl_tx_queue_release(void *txq)
1694 struct mrvl_txq *q = txq;
1703 * DPDK callback to get flow control configuration.
1706 * Pointer to Ethernet device structure.
1708 * Pointer to the flow control configuration.
1711 * 0 on success, negative error value otherwise.
1714 mrvl_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1716 struct mrvl_priv *priv = dev->data->dev_private;
1722 ret = pp2_ppio_get_rx_pause(priv->ppio, &en);
1724 MRVL_LOG(ERR, "Failed to read rx pause state");
1728 fc_conf->mode = en ? RTE_FC_RX_PAUSE : RTE_FC_NONE;
1734 * DPDK callback to set flow control configuration.
1737 * Pointer to Ethernet device structure.
1739 * Pointer to the flow control configuration.
1742 * 0 on success, negative error value otherwise.
1745 mrvl_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1747 struct mrvl_priv *priv = dev->data->dev_private;
1752 if (fc_conf->high_water ||
1753 fc_conf->low_water ||
1754 fc_conf->pause_time ||
1755 fc_conf->mac_ctrl_frame_fwd ||
1757 MRVL_LOG(ERR, "Flowctrl parameter is not supported");
1762 if (fc_conf->mode == RTE_FC_NONE ||
1763 fc_conf->mode == RTE_FC_RX_PAUSE) {
1766 en = fc_conf->mode == RTE_FC_NONE ? 0 : 1;
1767 ret = pp2_ppio_set_rx_pause(priv->ppio, en);
1770 "Failed to change flowctrl on RX side");
1779 * Update RSS hash configuration
1782 * Pointer to Ethernet device structure.
1784 * Pointer to RSS configuration.
1787 * 0 on success, negative error value otherwise.
1790 mrvl_rss_hash_update(struct rte_eth_dev *dev,
1791 struct rte_eth_rss_conf *rss_conf)
1793 struct mrvl_priv *priv = dev->data->dev_private;
1798 return mrvl_configure_rss(priv, rss_conf);
1802 * DPDK callback to get RSS hash configuration.
1805 * Pointer to Ethernet device structure.
1807 * Pointer to RSS configuration.
1813 mrvl_rss_hash_conf_get(struct rte_eth_dev *dev,
1814 struct rte_eth_rss_conf *rss_conf)
1816 struct mrvl_priv *priv = dev->data->dev_private;
1817 enum pp2_ppio_hash_type hash_type =
1818 priv->ppio_params.inqs_params.hash_type;
1820 rss_conf->rss_key = NULL;
1822 if (hash_type == PP2_PPIO_HASH_T_NONE)
1823 rss_conf->rss_hf = 0;
1824 else if (hash_type == PP2_PPIO_HASH_T_2_TUPLE)
1825 rss_conf->rss_hf = ETH_RSS_IPV4;
1826 else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && priv->rss_hf_tcp)
1827 rss_conf->rss_hf = ETH_RSS_NONFRAG_IPV4_TCP;
1828 else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && !priv->rss_hf_tcp)
1829 rss_conf->rss_hf = ETH_RSS_NONFRAG_IPV4_UDP;
1835 * DPDK callback to get rte_flow callbacks.
1838 * Pointer to the device structure.
1842 * Flow filter operation.
1844 * Pointer to pass the flow ops.
1847 * 0 on success, negative error value otherwise.
1850 mrvl_eth_filter_ctrl(struct rte_eth_dev *dev __rte_unused,
1851 enum rte_filter_type filter_type,
1852 enum rte_filter_op filter_op, void *arg)
1854 switch (filter_type) {
1855 case RTE_ETH_FILTER_GENERIC:
1856 if (filter_op != RTE_ETH_FILTER_GET)
1858 *(const void **)arg = &mrvl_flow_ops;
1861 MRVL_LOG(WARNING, "Filter type (%d) not supported",
1867 static const struct eth_dev_ops mrvl_ops = {
1868 .dev_configure = mrvl_dev_configure,
1869 .dev_start = mrvl_dev_start,
1870 .dev_stop = mrvl_dev_stop,
1871 .dev_set_link_up = mrvl_dev_set_link_up,
1872 .dev_set_link_down = mrvl_dev_set_link_down,
1873 .dev_close = mrvl_dev_close,
1874 .link_update = mrvl_link_update,
1875 .promiscuous_enable = mrvl_promiscuous_enable,
1876 .allmulticast_enable = mrvl_allmulticast_enable,
1877 .promiscuous_disable = mrvl_promiscuous_disable,
1878 .allmulticast_disable = mrvl_allmulticast_disable,
1879 .mac_addr_remove = mrvl_mac_addr_remove,
1880 .mac_addr_add = mrvl_mac_addr_add,
1881 .mac_addr_set = mrvl_mac_addr_set,
1882 .mtu_set = mrvl_mtu_set,
1883 .stats_get = mrvl_stats_get,
1884 .stats_reset = mrvl_stats_reset,
1885 .xstats_get = mrvl_xstats_get,
1886 .xstats_reset = mrvl_xstats_reset,
1887 .xstats_get_names = mrvl_xstats_get_names,
1888 .dev_infos_get = mrvl_dev_infos_get,
1889 .dev_supported_ptypes_get = mrvl_dev_supported_ptypes_get,
1890 .rxq_info_get = mrvl_rxq_info_get,
1891 .txq_info_get = mrvl_txq_info_get,
1892 .vlan_filter_set = mrvl_vlan_filter_set,
1893 .tx_queue_start = mrvl_tx_queue_start,
1894 .tx_queue_stop = mrvl_tx_queue_stop,
1895 .rx_queue_setup = mrvl_rx_queue_setup,
1896 .rx_queue_release = mrvl_rx_queue_release,
1897 .tx_queue_setup = mrvl_tx_queue_setup,
1898 .tx_queue_release = mrvl_tx_queue_release,
1899 .flow_ctrl_get = mrvl_flow_ctrl_get,
1900 .flow_ctrl_set = mrvl_flow_ctrl_set,
1901 .rss_hash_update = mrvl_rss_hash_update,
1902 .rss_hash_conf_get = mrvl_rss_hash_conf_get,
1903 .filter_ctrl = mrvl_eth_filter_ctrl,
1907 * Return packet type information and l3/l4 offsets.
1910 * Pointer to the received packet descriptor.
1917 * Packet type information.
1919 static inline uint64_t
1920 mrvl_desc_to_packet_type_and_offset(struct pp2_ppio_desc *desc,
1921 uint8_t *l3_offset, uint8_t *l4_offset)
1923 enum pp2_inq_l3_type l3_type;
1924 enum pp2_inq_l4_type l4_type;
1925 uint64_t packet_type;
1927 pp2_ppio_inq_desc_get_l3_info(desc, &l3_type, l3_offset);
1928 pp2_ppio_inq_desc_get_l4_info(desc, &l4_type, l4_offset);
1930 packet_type = RTE_PTYPE_L2_ETHER;
1933 case PP2_INQ_L3_TYPE_IPV4_NO_OPTS:
1934 packet_type |= RTE_PTYPE_L3_IPV4;
1936 case PP2_INQ_L3_TYPE_IPV4_OK:
1937 packet_type |= RTE_PTYPE_L3_IPV4_EXT;
1939 case PP2_INQ_L3_TYPE_IPV4_TTL_ZERO:
1940 packet_type |= RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
1942 case PP2_INQ_L3_TYPE_IPV6_NO_EXT:
1943 packet_type |= RTE_PTYPE_L3_IPV6;
1945 case PP2_INQ_L3_TYPE_IPV6_EXT:
1946 packet_type |= RTE_PTYPE_L3_IPV6_EXT;
1948 case PP2_INQ_L3_TYPE_ARP:
1949 packet_type |= RTE_PTYPE_L2_ETHER_ARP;
1951 * In case of ARP l4_offset is set to wrong value.
1952 * Set it to proper one so that later on mbuf->l3_len can be
1953 * calculated subtracting l4_offset and l3_offset.
1955 *l4_offset = *l3_offset + MRVL_ARP_LENGTH;
1958 MRVL_LOG(DEBUG, "Failed to recognise l3 packet type");
1963 case PP2_INQ_L4_TYPE_TCP:
1964 packet_type |= RTE_PTYPE_L4_TCP;
1966 case PP2_INQ_L4_TYPE_UDP:
1967 packet_type |= RTE_PTYPE_L4_UDP;
1970 MRVL_LOG(DEBUG, "Failed to recognise l4 packet type");
1978 * Get offload information from the received packet descriptor.
1981 * Pointer to the received packet descriptor.
1984 * Mbuf offload flags.
1986 static inline uint64_t
1987 mrvl_desc_to_ol_flags(struct pp2_ppio_desc *desc)
1990 enum pp2_inq_desc_status status;
1992 status = pp2_ppio_inq_desc_get_l3_pkt_error(desc);
1993 if (unlikely(status != PP2_DESC_ERR_OK))
1994 flags = PKT_RX_IP_CKSUM_BAD;
1996 flags = PKT_RX_IP_CKSUM_GOOD;
1998 status = pp2_ppio_inq_desc_get_l4_pkt_error(desc);
1999 if (unlikely(status != PP2_DESC_ERR_OK))
2000 flags |= PKT_RX_L4_CKSUM_BAD;
2002 flags |= PKT_RX_L4_CKSUM_GOOD;
2008 * DPDK callback for receive.
2011 * Generic pointer to the receive queue.
2013 * Array to store received packets.
2015 * Maximum number of packets in array.
2018 * Number of packets successfully received.
2021 mrvl_rx_pkt_burst(void *rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
2023 struct mrvl_rxq *q = rxq;
2024 struct pp2_ppio_desc descs[nb_pkts];
2025 struct pp2_bpool *bpool;
2026 int i, ret, rx_done = 0;
2028 struct pp2_hif *hif;
2029 unsigned int core_id = rte_lcore_id();
2031 hif = mrvl_get_hif(q->priv, core_id);
2033 if (unlikely(!q->priv->ppio || !hif))
2036 bpool = q->priv->bpool;
2038 ret = pp2_ppio_recv(q->priv->ppio, q->priv->rxq_map[q->queue_id].tc,
2039 q->priv->rxq_map[q->queue_id].inq, descs, &nb_pkts);
2040 if (unlikely(ret < 0)) {
2041 MRVL_LOG(ERR, "Failed to receive packets");
2044 mrvl_port_bpool_size[bpool->pp2_id][bpool->id][core_id] -= nb_pkts;
2046 for (i = 0; i < nb_pkts; i++) {
2047 struct rte_mbuf *mbuf;
2048 uint8_t l3_offset, l4_offset;
2049 enum pp2_inq_desc_status status;
2052 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) {
2053 struct pp2_ppio_desc *pref_desc;
2056 pref_desc = &descs[i + MRVL_MUSDK_PREFETCH_SHIFT];
2057 pref_addr = cookie_addr_high |
2058 pp2_ppio_inq_desc_get_cookie(pref_desc);
2059 rte_mbuf_prefetch_part1((struct rte_mbuf *)(pref_addr));
2060 rte_mbuf_prefetch_part2((struct rte_mbuf *)(pref_addr));
2063 addr = cookie_addr_high |
2064 pp2_ppio_inq_desc_get_cookie(&descs[i]);
2065 mbuf = (struct rte_mbuf *)addr;
2066 rte_pktmbuf_reset(mbuf);
2068 /* drop packet in case of mac, overrun or resource error */
2069 status = pp2_ppio_inq_desc_get_l2_pkt_error(&descs[i]);
2070 if (unlikely(status != PP2_DESC_ERR_OK)) {
2071 struct pp2_buff_inf binf = {
2072 .addr = rte_mbuf_data_iova_default(mbuf),
2073 .cookie = (pp2_cookie_t)(uint64_t)mbuf,
2076 pp2_bpool_put_buff(hif, bpool, &binf);
2077 mrvl_port_bpool_size
2078 [bpool->pp2_id][bpool->id][core_id]++;
2083 mbuf->data_off += MRVL_PKT_EFFEC_OFFS;
2084 mbuf->pkt_len = pp2_ppio_inq_desc_get_pkt_len(&descs[i]);
2085 mbuf->data_len = mbuf->pkt_len;
2086 mbuf->port = q->port_id;
2088 mrvl_desc_to_packet_type_and_offset(&descs[i],
2091 mbuf->l2_len = l3_offset;
2092 mbuf->l3_len = l4_offset - l3_offset;
2094 if (likely(q->cksum_enabled))
2095 mbuf->ol_flags = mrvl_desc_to_ol_flags(&descs[i]);
2097 rx_pkts[rx_done++] = mbuf;
2098 q->bytes_recv += mbuf->pkt_len;
2101 if (rte_spinlock_trylock(&q->priv->lock) == 1) {
2102 num = mrvl_get_bpool_size(bpool->pp2_id, bpool->id);
2104 if (unlikely(num <= q->priv->bpool_min_size ||
2105 (!rx_done && num < q->priv->bpool_init_size))) {
2106 ret = mrvl_fill_bpool(q, MRVL_BURST_SIZE);
2108 MRVL_LOG(ERR, "Failed to fill bpool");
2109 } else if (unlikely(num > q->priv->bpool_max_size)) {
2111 int pkt_to_remove = num - q->priv->bpool_init_size;
2112 struct rte_mbuf *mbuf;
2113 struct pp2_buff_inf buff;
2116 "port-%d:%d: bpool %d oversize - remove %d buffers (pool size: %d -> %d)",
2117 bpool->pp2_id, q->priv->ppio->port_id,
2118 bpool->id, pkt_to_remove, num,
2119 q->priv->bpool_init_size);
2121 for (i = 0; i < pkt_to_remove; i++) {
2122 ret = pp2_bpool_get_buff(hif, bpool, &buff);
2125 mbuf = (struct rte_mbuf *)
2126 (cookie_addr_high | buff.cookie);
2127 rte_pktmbuf_free(mbuf);
2129 mrvl_port_bpool_size
2130 [bpool->pp2_id][bpool->id][core_id] -= i;
2132 rte_spinlock_unlock(&q->priv->lock);
2139 * Prepare offload information.
2143 * @param packet_type
2144 * Packet type bitfield.
2146 * Pointer to the pp2_ouq_l3_type structure.
2148 * Pointer to the pp2_outq_l4_type structure.
2149 * @param gen_l3_cksum
2150 * Will be set to 1 in case l3 checksum is computed.
2152 * Will be set to 1 in case l4 checksum is computed.
2155 * 0 on success, negative error value otherwise.
2158 mrvl_prepare_proto_info(uint64_t ol_flags, uint32_t packet_type,
2159 enum pp2_outq_l3_type *l3_type,
2160 enum pp2_outq_l4_type *l4_type,
2165 * Based on ol_flags prepare information
2166 * for pp2_ppio_outq_desc_set_proto_info() which setups descriptor
2169 if (ol_flags & PKT_TX_IPV4) {
2170 *l3_type = PP2_OUTQ_L3_TYPE_IPV4;
2171 *gen_l3_cksum = ol_flags & PKT_TX_IP_CKSUM ? 1 : 0;
2172 } else if (ol_flags & PKT_TX_IPV6) {
2173 *l3_type = PP2_OUTQ_L3_TYPE_IPV6;
2174 /* no checksum for ipv6 header */
2177 /* if something different then stop processing */
2181 ol_flags &= PKT_TX_L4_MASK;
2182 if ((packet_type & RTE_PTYPE_L4_TCP) &&
2183 ol_flags == PKT_TX_TCP_CKSUM) {
2184 *l4_type = PP2_OUTQ_L4_TYPE_TCP;
2186 } else if ((packet_type & RTE_PTYPE_L4_UDP) &&
2187 ol_flags == PKT_TX_UDP_CKSUM) {
2188 *l4_type = PP2_OUTQ_L4_TYPE_UDP;
2191 *l4_type = PP2_OUTQ_L4_TYPE_OTHER;
2192 /* no checksum for other type */
2200 * Release already sent buffers to bpool (buffer-pool).
2203 * Pointer to the port structure.
2205 * Pointer to the MUSDK hardware interface.
2207 * Pointer to the shadow queue.
2211 * Force releasing packets.
2214 mrvl_free_sent_buffers(struct pp2_ppio *ppio, struct pp2_hif *hif,
2215 unsigned int core_id, struct mrvl_shadow_txq *sq,
2218 struct buff_release_entry *entry;
2219 uint16_t nb_done = 0, num = 0, skip_bufs = 0;
2222 pp2_ppio_get_num_outq_done(ppio, hif, qid, &nb_done);
2224 sq->num_to_release += nb_done;
2226 if (likely(!force &&
2227 sq->num_to_release < MRVL_PP2_BUF_RELEASE_BURST_SIZE))
2230 nb_done = sq->num_to_release;
2231 sq->num_to_release = 0;
2233 for (i = 0; i < nb_done; i++) {
2234 entry = &sq->ent[sq->tail + num];
2235 if (unlikely(!entry->buff.addr)) {
2237 "Shadow memory @%d: cookie(%lx), pa(%lx)!",
2238 sq->tail, (u64)entry->buff.cookie,
2239 (u64)entry->buff.addr);
2244 if (unlikely(!entry->bpool)) {
2245 struct rte_mbuf *mbuf;
2247 mbuf = (struct rte_mbuf *)
2248 (cookie_addr_high | entry->buff.cookie);
2249 rte_pktmbuf_free(mbuf);
2254 mrvl_port_bpool_size
2255 [entry->bpool->pp2_id][entry->bpool->id][core_id]++;
2257 if (unlikely(sq->tail + num == MRVL_PP2_TX_SHADOWQ_SIZE))
2262 pp2_bpool_put_buffs(hif, &sq->ent[sq->tail], &num);
2264 sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK;
2271 pp2_bpool_put_buffs(hif, &sq->ent[sq->tail], &num);
2272 sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK;
2278 * DPDK callback for transmit.
2281 * Generic pointer transmit queue.
2283 * Packets to transmit.
2285 * Number of packets in array.
2288 * Number of packets successfully transmitted.
2291 mrvl_tx_pkt_burst(void *txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2293 struct mrvl_txq *q = txq;
2294 struct mrvl_shadow_txq *sq;
2295 struct pp2_hif *hif;
2296 struct pp2_ppio_desc descs[nb_pkts];
2297 unsigned int core_id = rte_lcore_id();
2298 int i, ret, bytes_sent = 0;
2299 uint16_t num, sq_free_size;
2302 hif = mrvl_get_hif(q->priv, core_id);
2303 sq = &q->shadow_txqs[core_id];
2305 if (unlikely(!q->priv->ppio || !hif))
2309 mrvl_free_sent_buffers(q->priv->ppio, hif, core_id,
2310 sq, q->queue_id, 0);
2312 sq_free_size = MRVL_PP2_TX_SHADOWQ_SIZE - sq->size - 1;
2313 if (unlikely(nb_pkts > sq_free_size)) {
2315 "No room in shadow queue for %d packets! %d packets will be sent.",
2316 nb_pkts, sq_free_size);
2317 nb_pkts = sq_free_size;
2320 for (i = 0; i < nb_pkts; i++) {
2321 struct rte_mbuf *mbuf = tx_pkts[i];
2322 int gen_l3_cksum, gen_l4_cksum;
2323 enum pp2_outq_l3_type l3_type;
2324 enum pp2_outq_l4_type l4_type;
2326 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) {
2327 struct rte_mbuf *pref_pkt_hdr;
2329 pref_pkt_hdr = tx_pkts[i + MRVL_MUSDK_PREFETCH_SHIFT];
2330 rte_mbuf_prefetch_part1(pref_pkt_hdr);
2331 rte_mbuf_prefetch_part2(pref_pkt_hdr);
2334 sq->ent[sq->head].buff.cookie = (pp2_cookie_t)(uint64_t)mbuf;
2335 sq->ent[sq->head].buff.addr =
2336 rte_mbuf_data_iova_default(mbuf);
2337 sq->ent[sq->head].bpool =
2338 (unlikely(mbuf->port >= RTE_MAX_ETHPORTS ||
2339 mbuf->refcnt > 1)) ? NULL :
2340 mrvl_port_to_bpool_lookup[mbuf->port];
2341 sq->head = (sq->head + 1) & MRVL_PP2_TX_SHADOWQ_MASK;
2344 pp2_ppio_outq_desc_reset(&descs[i]);
2345 pp2_ppio_outq_desc_set_phys_addr(&descs[i],
2346 rte_pktmbuf_iova(mbuf));
2347 pp2_ppio_outq_desc_set_pkt_offset(&descs[i], 0);
2348 pp2_ppio_outq_desc_set_pkt_len(&descs[i],
2349 rte_pktmbuf_pkt_len(mbuf));
2351 bytes_sent += rte_pktmbuf_pkt_len(mbuf);
2353 * in case unsupported ol_flags were passed
2354 * do not update descriptor offload information
2356 ret = mrvl_prepare_proto_info(mbuf->ol_flags, mbuf->packet_type,
2357 &l3_type, &l4_type, &gen_l3_cksum,
2362 pp2_ppio_outq_desc_set_proto_info(&descs[i], l3_type, l4_type,
2364 mbuf->l2_len + mbuf->l3_len,
2365 gen_l3_cksum, gen_l4_cksum);
2369 pp2_ppio_send(q->priv->ppio, hif, q->queue_id, descs, &nb_pkts);
2370 /* number of packets that were not sent */
2371 if (unlikely(num > nb_pkts)) {
2372 for (i = nb_pkts; i < num; i++) {
2373 sq->head = (MRVL_PP2_TX_SHADOWQ_SIZE + sq->head - 1) &
2374 MRVL_PP2_TX_SHADOWQ_MASK;
2375 addr = cookie_addr_high | sq->ent[sq->head].buff.cookie;
2377 rte_pktmbuf_pkt_len((struct rte_mbuf *)addr);
2379 sq->size -= num - nb_pkts;
2382 q->bytes_sent += bytes_sent;
2388 * Initialize packet processor.
2391 * 0 on success, negative error value otherwise.
2396 struct pp2_init_params init_params;
2398 memset(&init_params, 0, sizeof(init_params));
2399 init_params.hif_reserved_map = MRVL_MUSDK_HIFS_RESERVED;
2400 init_params.bm_pool_reserved_map = MRVL_MUSDK_BPOOLS_RESERVED;
2401 init_params.rss_tbl_reserved_map = MRVL_MUSDK_RSS_RESERVED;
2403 return pp2_init(&init_params);
2407 * Deinitialize packet processor.
2410 * 0 on success, negative error value otherwise.
2413 mrvl_deinit_pp2(void)
2419 * Create private device structure.
2422 * Pointer to the port name passed in the initialization parameters.
2425 * Pointer to the newly allocated private device structure.
2427 static struct mrvl_priv *
2428 mrvl_priv_create(const char *dev_name)
2430 struct pp2_bpool_params bpool_params;
2431 char match[MRVL_MATCH_LEN];
2432 struct mrvl_priv *priv;
2435 priv = rte_zmalloc_socket(dev_name, sizeof(*priv), 0, rte_socket_id());
2439 ret = pp2_netdev_get_ppio_info((char *)(uintptr_t)dev_name,
2440 &priv->pp_id, &priv->ppio_id);
2444 bpool_bit = mrvl_reserve_bit(&used_bpools[priv->pp_id],
2445 PP2_BPOOL_NUM_POOLS);
2448 priv->bpool_bit = bpool_bit;
2450 snprintf(match, sizeof(match), "pool-%d:%d", priv->pp_id,
2452 memset(&bpool_params, 0, sizeof(bpool_params));
2453 bpool_params.match = match;
2454 bpool_params.buff_len = MRVL_PKT_SIZE_MAX + MRVL_PKT_EFFEC_OFFS;
2455 ret = pp2_bpool_init(&bpool_params, &priv->bpool);
2457 goto out_clear_bpool_bit;
2459 priv->ppio_params.type = PP2_PPIO_T_NIC;
2460 rte_spinlock_init(&priv->lock);
2463 out_clear_bpool_bit:
2464 used_bpools[priv->pp_id] &= ~(1 << priv->bpool_bit);
2471 * Create device representing Ethernet port.
2474 * Pointer to the port's name.
2477 * 0 on success, negative error value otherwise.
2480 mrvl_eth_dev_create(struct rte_vdev_device *vdev, const char *name)
2482 int ret, fd = socket(AF_INET, SOCK_DGRAM, 0);
2483 struct rte_eth_dev *eth_dev;
2484 struct mrvl_priv *priv;
2487 eth_dev = rte_eth_dev_allocate(name);
2491 priv = mrvl_priv_create(name);
2497 eth_dev->data->mac_addrs =
2498 rte_zmalloc("mac_addrs",
2499 ETHER_ADDR_LEN * MRVL_MAC_ADDRS_MAX, 0);
2500 if (!eth_dev->data->mac_addrs) {
2501 MRVL_LOG(ERR, "Failed to allocate space for eth addrs");
2506 memset(&req, 0, sizeof(req));
2507 strcpy(req.ifr_name, name);
2508 ret = ioctl(fd, SIOCGIFHWADDR, &req);
2512 memcpy(eth_dev->data->mac_addrs[0].addr_bytes,
2513 req.ifr_addr.sa_data, ETHER_ADDR_LEN);
2515 eth_dev->rx_pkt_burst = mrvl_rx_pkt_burst;
2516 eth_dev->tx_pkt_burst = mrvl_tx_pkt_burst;
2517 eth_dev->data->kdrv = RTE_KDRV_NONE;
2518 eth_dev->data->dev_private = priv;
2519 eth_dev->device = &vdev->device;
2520 eth_dev->dev_ops = &mrvl_ops;
2522 rte_eth_dev_probing_finish(eth_dev);
2525 rte_free(eth_dev->data->mac_addrs);
2527 rte_eth_dev_release_port(eth_dev);
2535 * Cleanup previously created device representing Ethernet port.
2538 * Pointer to the port name.
2541 mrvl_eth_dev_destroy(const char *name)
2543 struct rte_eth_dev *eth_dev;
2544 struct mrvl_priv *priv;
2546 eth_dev = rte_eth_dev_allocated(name);
2550 priv = eth_dev->data->dev_private;
2551 pp2_bpool_deinit(priv->bpool);
2552 used_bpools[priv->pp_id] &= ~(1 << priv->bpool_bit);
2554 rte_free(eth_dev->data->mac_addrs);
2555 rte_eth_dev_release_port(eth_dev);
2559 * Callback used by rte_kvargs_process() during argument parsing.
2562 * Pointer to the parsed key (unused).
2564 * Pointer to the parsed value.
2566 * Pointer to the extra arguments which contains address of the
2567 * table of pointers to parsed interface names.
2573 mrvl_get_ifnames(const char *key __rte_unused, const char *value,
2576 struct mrvl_ifnames *ifnames = extra_args;
2578 ifnames->names[ifnames->idx++] = value;
2584 * Deinitialize per-lcore MUSDK hardware interfaces (hifs).
2587 mrvl_deinit_hifs(void)
2591 for (i = mrvl_lcore_first; i <= mrvl_lcore_last; i++) {
2593 pp2_hif_deinit(hifs[i]);
2595 used_hifs = MRVL_MUSDK_HIFS_RESERVED;
2596 memset(hifs, 0, sizeof(hifs));
2600 * DPDK callback to register the virtual device.
2603 * Pointer to the virtual device.
2606 * 0 on success, negative error value otherwise.
2609 rte_pmd_mrvl_probe(struct rte_vdev_device *vdev)
2611 struct rte_kvargs *kvlist;
2612 struct mrvl_ifnames ifnames;
2614 uint32_t i, ifnum, cfgnum;
2617 params = rte_vdev_device_args(vdev);
2621 kvlist = rte_kvargs_parse(params, valid_args);
2625 ifnum = rte_kvargs_count(kvlist, MRVL_IFACE_NAME_ARG);
2626 if (ifnum > RTE_DIM(ifnames.names))
2627 goto out_free_kvlist;
2630 rte_kvargs_process(kvlist, MRVL_IFACE_NAME_ARG,
2631 mrvl_get_ifnames, &ifnames);
2635 * The below system initialization should be done only once,
2636 * on the first provided configuration file
2638 if (!mrvl_qos_cfg) {
2639 cfgnum = rte_kvargs_count(kvlist, MRVL_CFG_ARG);
2640 MRVL_LOG(INFO, "Parsing config file!");
2642 MRVL_LOG(ERR, "Cannot handle more than one config file!");
2643 goto out_free_kvlist;
2644 } else if (cfgnum == 1) {
2645 rte_kvargs_process(kvlist, MRVL_CFG_ARG,
2646 mrvl_get_qoscfg, &mrvl_qos_cfg);
2653 MRVL_LOG(INFO, "Perform MUSDK initializations");
2655 ret = rte_mvep_init(MVEP_MOD_T_PP2, kvlist);
2657 goto out_free_kvlist;
2659 ret = mrvl_init_pp2();
2661 MRVL_LOG(ERR, "Failed to init PP!");
2662 rte_mvep_deinit(MVEP_MOD_T_PP2);
2663 goto out_free_kvlist;
2666 memset(mrvl_port_bpool_size, 0, sizeof(mrvl_port_bpool_size));
2667 memset(mrvl_port_to_bpool_lookup, 0, sizeof(mrvl_port_to_bpool_lookup));
2669 mrvl_lcore_first = RTE_MAX_LCORE;
2670 mrvl_lcore_last = 0;
2673 for (i = 0; i < ifnum; i++) {
2674 MRVL_LOG(INFO, "Creating %s", ifnames.names[i]);
2675 ret = mrvl_eth_dev_create(vdev, ifnames.names[i]);
2679 mrvl_dev_num += ifnum;
2681 rte_kvargs_free(kvlist);
2686 mrvl_eth_dev_destroy(ifnames.names[i]);
2688 if (mrvl_dev_num == 0) {
2690 rte_mvep_deinit(MVEP_MOD_T_PP2);
2693 rte_kvargs_free(kvlist);
2699 * DPDK callback to remove virtual device.
2702 * Pointer to the removed virtual device.
2705 * 0 on success, negative error value otherwise.
2708 rte_pmd_mrvl_remove(struct rte_vdev_device *vdev)
2713 name = rte_vdev_device_name(vdev);
2717 MRVL_LOG(INFO, "Removing %s", name);
2719 RTE_ETH_FOREACH_DEV(i) { /* FIXME: removing all devices! */
2720 char ifname[RTE_ETH_NAME_MAX_LEN];
2722 rte_eth_dev_get_name_by_port(i, ifname);
2723 mrvl_eth_dev_destroy(ifname);
2727 if (mrvl_dev_num == 0) {
2728 MRVL_LOG(INFO, "Perform MUSDK deinit");
2731 rte_mvep_deinit(MVEP_MOD_T_PP2);
2737 static struct rte_vdev_driver pmd_mrvl_drv = {
2738 .probe = rte_pmd_mrvl_probe,
2739 .remove = rte_pmd_mrvl_remove,
2742 RTE_PMD_REGISTER_VDEV(net_mvpp2, pmd_mrvl_drv);
2743 RTE_PMD_REGISTER_ALIAS(net_mvpp2, eth_mvpp2);
2745 RTE_INIT(mrvl_init_log)
2747 mrvl_logtype = rte_log_register("pmd.net.mvpp2");
2748 if (mrvl_logtype >= 0)
2749 rte_log_set_level(mrvl_logtype, RTE_LOG_NOTICE);